Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 33
- Kernel Warnings: 22
- Boot result: PASS
- Errors: 0
1 11:54:10.955449 lava-dispatcher, installed at version: 2023.10
2 11:54:10.955657 start: 0 validate
3 11:54:10.955793 Start time: 2023-11-23 11:54:10.955786+00:00 (UTC)
4 11:54:10.955904 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:54:10.956033 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:54:11.226540 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:54:11.227278 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:54:11.497821 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:54:11.498647 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:54:11.770049 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:54:11.770808 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:54:12.048634 validate duration: 1.09
14 11:54:12.049989 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:54:12.050516 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:54:12.051009 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:54:12.051626 Not decompressing ramdisk as can be used compressed.
18 11:54:12.052120 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
19 11:54:12.052489 saving as /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/ramdisk/rootfs.cpio.gz
20 11:54:12.052908 total size: 43284872 (41 MB)
21 11:54:12.058188 progress 0 % (0 MB)
22 11:54:12.095997 progress 5 % (2 MB)
23 11:54:12.111398 progress 10 % (4 MB)
24 11:54:12.123202 progress 15 % (6 MB)
25 11:54:12.134456 progress 20 % (8 MB)
26 11:54:12.145630 progress 25 % (10 MB)
27 11:54:12.156725 progress 30 % (12 MB)
28 11:54:12.167885 progress 35 % (14 MB)
29 11:54:12.178937 progress 40 % (16 MB)
30 11:54:12.190064 progress 45 % (18 MB)
31 11:54:12.201138 progress 50 % (20 MB)
32 11:54:12.212184 progress 55 % (22 MB)
33 11:54:12.223419 progress 60 % (24 MB)
34 11:54:12.234587 progress 65 % (26 MB)
35 11:54:12.245934 progress 70 % (28 MB)
36 11:54:12.257708 progress 75 % (30 MB)
37 11:54:12.269106 progress 80 % (33 MB)
38 11:54:12.280116 progress 85 % (35 MB)
39 11:54:12.291222 progress 90 % (37 MB)
40 11:54:12.302087 progress 95 % (39 MB)
41 11:54:12.312889 progress 100 % (41 MB)
42 11:54:12.313132 41 MB downloaded in 0.26 s (158.62 MB/s)
43 11:54:12.313290 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:54:12.313532 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:54:12.313617 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:54:12.313701 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:54:12.313839 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:54:12.313908 saving as /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/kernel/Image
50 11:54:12.313971 total size: 49107456 (46 MB)
51 11:54:12.314032 No compression specified
52 11:54:12.315223 progress 0 % (0 MB)
53 11:54:12.327654 progress 5 % (2 MB)
54 11:54:12.340153 progress 10 % (4 MB)
55 11:54:12.352876 progress 15 % (7 MB)
56 11:54:12.365540 progress 20 % (9 MB)
57 11:54:12.378058 progress 25 % (11 MB)
58 11:54:12.390707 progress 30 % (14 MB)
59 11:54:12.403035 progress 35 % (16 MB)
60 11:54:12.415455 progress 40 % (18 MB)
61 11:54:12.427845 progress 45 % (21 MB)
62 11:54:12.440177 progress 50 % (23 MB)
63 11:54:12.452839 progress 55 % (25 MB)
64 11:54:12.465541 progress 60 % (28 MB)
65 11:54:12.478063 progress 65 % (30 MB)
66 11:54:12.490654 progress 70 % (32 MB)
67 11:54:12.503137 progress 75 % (35 MB)
68 11:54:12.515670 progress 80 % (37 MB)
69 11:54:12.528046 progress 85 % (39 MB)
70 11:54:12.540362 progress 90 % (42 MB)
71 11:54:12.552787 progress 95 % (44 MB)
72 11:54:12.565129 progress 100 % (46 MB)
73 11:54:12.565331 46 MB downloaded in 0.25 s (186.32 MB/s)
74 11:54:12.565478 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:54:12.565703 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:54:12.565788 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:54:12.565878 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:54:12.566015 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:54:12.566083 saving as /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/dtb/mt8192-asurada-spherion-r0.dtb
81 11:54:12.566143 total size: 47278 (0 MB)
82 11:54:12.566204 No compression specified
83 11:54:12.567312 progress 69 % (0 MB)
84 11:54:12.567580 progress 100 % (0 MB)
85 11:54:12.567731 0 MB downloaded in 0.00 s (28.43 MB/s)
86 11:54:12.567849 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:54:12.568063 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:54:12.568145 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:54:12.568224 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:54:12.568334 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:54:12.568400 saving as /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/modules/modules.tar
93 11:54:12.568459 total size: 8621364 (8 MB)
94 11:54:12.568554 Using unxz to decompress xz
95 11:54:12.572793 progress 0 % (0 MB)
96 11:54:12.593674 progress 5 % (0 MB)
97 11:54:12.616958 progress 10 % (0 MB)
98 11:54:12.639811 progress 15 % (1 MB)
99 11:54:12.663012 progress 20 % (1 MB)
100 11:54:12.686748 progress 25 % (2 MB)
101 11:54:12.712018 progress 30 % (2 MB)
102 11:54:12.737752 progress 35 % (2 MB)
103 11:54:12.760932 progress 40 % (3 MB)
104 11:54:12.784845 progress 45 % (3 MB)
105 11:54:12.809726 progress 50 % (4 MB)
106 11:54:12.833620 progress 55 % (4 MB)
107 11:54:12.858186 progress 60 % (4 MB)
108 11:54:12.885271 progress 65 % (5 MB)
109 11:54:12.909688 progress 70 % (5 MB)
110 11:54:12.932704 progress 75 % (6 MB)
111 11:54:12.959208 progress 80 % (6 MB)
112 11:54:12.984794 progress 85 % (7 MB)
113 11:54:13.009325 progress 90 % (7 MB)
114 11:54:13.039017 progress 95 % (7 MB)
115 11:54:13.068967 progress 100 % (8 MB)
116 11:54:13.073629 8 MB downloaded in 0.51 s (16.28 MB/s)
117 11:54:13.073880 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:54:13.074137 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:54:13.074229 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:54:13.074323 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:54:13.074402 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:54:13.074486 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:54:13.074705 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3
125 11:54:13.074839 makedir: /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin
126 11:54:13.074946 makedir: /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/tests
127 11:54:13.075044 makedir: /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/results
128 11:54:13.075162 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-add-keys
129 11:54:13.075314 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-add-sources
130 11:54:13.075444 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-background-process-start
131 11:54:13.075574 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-background-process-stop
132 11:54:13.075698 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-common-functions
133 11:54:13.075822 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-echo-ipv4
134 11:54:13.075945 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-install-packages
135 11:54:13.076067 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-installed-packages
136 11:54:13.076190 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-os-build
137 11:54:13.076312 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-probe-channel
138 11:54:13.076436 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-probe-ip
139 11:54:13.076569 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-target-ip
140 11:54:13.076693 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-target-mac
141 11:54:13.076816 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-target-storage
142 11:54:13.076945 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-case
143 11:54:13.077069 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-event
144 11:54:13.077190 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-feedback
145 11:54:13.077313 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-raise
146 11:54:13.077436 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-reference
147 11:54:13.077558 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-runner
148 11:54:13.077680 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-set
149 11:54:13.077805 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-test-shell
150 11:54:13.077931 Updating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-install-packages (oe)
151 11:54:13.078076 Updating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/bin/lava-installed-packages (oe)
152 11:54:13.078203 Creating /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/environment
153 11:54:13.078304 LAVA metadata
154 11:54:13.078378 - LAVA_JOB_ID=12066548
155 11:54:13.078443 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:54:13.078545 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:54:13.078611 skipped lava-vland-overlay
158 11:54:13.078684 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:54:13.078762 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:54:13.078829 skipped lava-multinode-overlay
161 11:54:13.078905 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:54:13.078991 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:54:13.079065 Loading test definitions
164 11:54:13.079156 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:54:13.079229 Using /lava-12066548 at stage 0
166 11:54:13.079533 uuid=12066548_1.5.2.3.1 testdef=None
167 11:54:13.079620 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:54:13.079704 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:54:13.080230 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:54:13.080452 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:54:13.081078 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:54:13.081306 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:54:13.081904 runner path: /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/0/tests/0_igt-kms-mediatek test_uuid 12066548_1.5.2.3.1
176 11:54:13.082062 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:54:13.082268 Creating lava-test-runner.conf files
179 11:54:13.082330 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066548/lava-overlay-fguwxqr3/lava-12066548/0 for stage 0
180 11:54:13.082418 - 0_igt-kms-mediatek
181 11:54:13.082512 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:54:13.082596 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:54:13.089292 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:54:13.089399 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:54:13.089485 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:54:13.089568 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:54:13.089658 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:54:14.461828 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:54:14.462211 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:54:14.462328 extracting modules file /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066548/extract-overlay-ramdisk-25gqfzkt/ramdisk
191 11:54:14.688455 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:54:14.688660 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:54:14.688759 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066548/compress-overlay-mmqlic9i/overlay-1.5.2.4.tar.gz to ramdisk
194 11:54:14.688831 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066548/compress-overlay-mmqlic9i/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066548/extract-overlay-ramdisk-25gqfzkt/ramdisk
195 11:54:14.695511 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:54:14.695629 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:54:14.695722 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:54:14.695809 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:54:14.695885 Building ramdisk /var/lib/lava/dispatcher/tmp/12066548/extract-overlay-ramdisk-25gqfzkt/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066548/extract-overlay-ramdisk-25gqfzkt/ramdisk
200 11:54:15.721365 >> 369977 blocks
201 11:54:21.471096 rename /var/lib/lava/dispatcher/tmp/12066548/extract-overlay-ramdisk-25gqfzkt/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/ramdisk/ramdisk.cpio.gz
202 11:54:21.471544 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:54:21.471667 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 11:54:21.471769 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 11:54:21.471875 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/kernel/Image'
206 11:54:33.368674 Returned 0 in 11 seconds
207 11:54:33.469389 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/kernel/image.itb
208 11:54:34.297307 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:54:34.297699 output: Created: Thu Nov 23 11:54:34 2023
210 11:54:34.297785 output: Image 0 (kernel-1)
211 11:54:34.297855 output: Description:
212 11:54:34.297919 output: Created: Thu Nov 23 11:54:34 2023
213 11:54:34.297981 output: Type: Kernel Image
214 11:54:34.298041 output: Compression: lzma compressed
215 11:54:34.298100 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
216 11:54:34.298159 output: Architecture: AArch64
217 11:54:34.298219 output: OS: Linux
218 11:54:34.298275 output: Load Address: 0x00000000
219 11:54:34.298329 output: Entry Point: 0x00000000
220 11:54:34.298382 output: Hash algo: crc32
221 11:54:34.298438 output: Hash value: e6d7c86f
222 11:54:34.298493 output: Image 1 (fdt-1)
223 11:54:34.298548 output: Description: mt8192-asurada-spherion-r0
224 11:54:34.298601 output: Created: Thu Nov 23 11:54:34 2023
225 11:54:34.298653 output: Type: Flat Device Tree
226 11:54:34.298706 output: Compression: uncompressed
227 11:54:34.298758 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:54:34.298810 output: Architecture: AArch64
229 11:54:34.298862 output: Hash algo: crc32
230 11:54:34.298914 output: Hash value: cc4352de
231 11:54:34.298965 output: Image 2 (ramdisk-1)
232 11:54:34.299017 output: Description: unavailable
233 11:54:34.299068 output: Created: Thu Nov 23 11:54:34 2023
234 11:54:34.299121 output: Type: RAMDisk Image
235 11:54:34.299173 output: Compression: Unknown Compression
236 11:54:34.299225 output: Data Size: 56432282 Bytes = 55109.65 KiB = 53.82 MiB
237 11:54:34.299278 output: Architecture: AArch64
238 11:54:34.299330 output: OS: Linux
239 11:54:34.299382 output: Load Address: unavailable
240 11:54:34.299435 output: Entry Point: unavailable
241 11:54:34.299487 output: Hash algo: crc32
242 11:54:34.299539 output: Hash value: 384973ed
243 11:54:34.299591 output: Default Configuration: 'conf-1'
244 11:54:34.299643 output: Configuration 0 (conf-1)
245 11:54:34.299695 output: Description: mt8192-asurada-spherion-r0
246 11:54:34.299747 output: Kernel: kernel-1
247 11:54:34.299799 output: Init Ramdisk: ramdisk-1
248 11:54:34.299851 output: FDT: fdt-1
249 11:54:34.299903 output: Loadables: kernel-1
250 11:54:34.299955 output:
251 11:54:34.300156 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:54:34.300256 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:54:34.300363 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 11:54:34.300456 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 11:54:34.300563 No LXC device requested
256 11:54:34.300661 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:54:34.300746 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 11:54:34.300824 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:54:34.300896 Checking files for TFTP limit of 4294967296 bytes.
260 11:54:34.301389 end: 1 tftp-deploy (duration 00:00:22) [common]
261 11:54:34.301494 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:54:34.301582 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:54:34.301705 substitutions:
264 11:54:34.301771 - {DTB}: 12066548/tftp-deploy-a36_81vh/dtb/mt8192-asurada-spherion-r0.dtb
265 11:54:34.301836 - {INITRD}: 12066548/tftp-deploy-a36_81vh/ramdisk/ramdisk.cpio.gz
266 11:54:34.301895 - {KERNEL}: 12066548/tftp-deploy-a36_81vh/kernel/Image
267 11:54:34.301952 - {LAVA_MAC}: None
268 11:54:34.302007 - {PRESEED_CONFIG}: None
269 11:54:34.302062 - {PRESEED_LOCAL}: None
270 11:54:34.302116 - {RAMDISK}: 12066548/tftp-deploy-a36_81vh/ramdisk/ramdisk.cpio.gz
271 11:54:34.302171 - {ROOT_PART}: None
272 11:54:34.302224 - {ROOT}: None
273 11:54:34.302280 - {SERVER_IP}: 192.168.201.1
274 11:54:34.302333 - {TEE}: None
275 11:54:34.302389 Parsed boot commands:
276 11:54:34.302442 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:54:34.302617 Parsed boot commands: tftpboot 192.168.201.1 12066548/tftp-deploy-a36_81vh/kernel/image.itb 12066548/tftp-deploy-a36_81vh/kernel/cmdline
278 11:54:34.302707 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:54:34.302798 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:54:34.302896 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:54:34.302986 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:54:34.303057 Not connected, no need to disconnect.
283 11:54:34.303130 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:54:34.303209 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:54:34.303277 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-4'
286 11:54:34.307317 Setting prompt string to ['lava-test: # ']
287 11:54:34.307686 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:54:34.307796 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:54:34.307896 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:54:34.307987 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:54:34.308227 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=reboot'
292 11:54:39.441678 >> Command sent successfully.
293 11:54:39.443953 Returned 0 in 5 seconds
294 11:54:39.544352 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:54:39.544837 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:54:39.544972 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:54:39.545100 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:54:39.545200 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:54:39.545302 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:54:39.545666 [Enter `^Ec?' for help]
302 11:54:39.724673
303 11:54:39.724860
304 11:54:39.724959 F0: 102B 0000
305 11:54:39.725054
306 11:54:39.725141 F3: 1001 0000 [0200]
307 11:54:39.725227
308 11:54:39.728746 F3: 1001 0000
309 11:54:39.728854
310 11:54:39.728945 F7: 102D 0000
311 11:54:39.729035
312 11:54:39.729124 F1: 0000 0000
313 11:54:39.729215
314 11:54:39.732201 V0: 0000 0000 [0001]
315 11:54:39.732307
316 11:54:39.732398 00: 0007 8000
317 11:54:39.732489
318 11:54:39.735949 01: 0000 0000
319 11:54:39.736058
320 11:54:39.736148 BP: 0C00 0209 [0000]
321 11:54:39.736238
322 11:54:39.736325 G0: 1182 0000
323 11:54:39.736411
324 11:54:39.739529 EC: 0000 0021 [4000]
325 11:54:39.739635
326 11:54:39.739728 S7: 0000 0000 [0000]
327 11:54:39.743385
328 11:54:39.743491 CC: 0000 0000 [0001]
329 11:54:39.743585
330 11:54:39.746313 T0: 0000 0040 [010F]
331 11:54:39.746425
332 11:54:39.746516 Jump to BL
333 11:54:39.746612
334 11:54:39.771139
335 11:54:39.771252
336 11:54:39.771346
337 11:54:39.777886 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:54:39.781413 ARM64: Exception handlers installed.
339 11:54:39.785293 ARM64: Testing exception
340 11:54:39.788812 ARM64: Done test exception
341 11:54:39.795939 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:54:39.806593 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:54:39.813920 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:54:39.823713 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:54:39.830259 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:54:39.837114 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:54:39.847413 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:54:39.853980 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:54:39.873896 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:54:39.877406 WDT: Last reset was cold boot
351 11:54:39.880445 SPI1(PAD0) initialized at 2873684 Hz
352 11:54:39.883997 SPI5(PAD0) initialized at 992727 Hz
353 11:54:39.887269 VBOOT: Loading verstage.
354 11:54:39.893758 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:54:39.897584 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:54:39.900386 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:54:39.903835 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:54:39.911279 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:54:39.917855 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:54:39.928877 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
361 11:54:39.928986
362 11:54:39.929080
363 11:54:39.938780 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:54:39.942252 ARM64: Exception handlers installed.
365 11:54:39.945447 ARM64: Testing exception
366 11:54:39.945558 ARM64: Done test exception
367 11:54:39.952032 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:54:39.955282 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:54:39.969833 Probing TPM: . done!
370 11:54:39.969942 TPM ready after 0 ms
371 11:54:39.976866 Connected to device vid:did:rid of 1ae0:0028:00
372 11:54:39.983891 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
373 11:54:39.987041 Initialized TPM device CR50 revision 0
374 11:54:40.046946 tlcl_send_startup: Startup return code is 0
375 11:54:40.047079 TPM: setup succeeded
376 11:54:40.057451 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:54:40.066913 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:54:40.076091 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:54:40.085253 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:54:40.088418 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:54:40.091754 in-header: 03 07 00 00 08 00 00 00
382 11:54:40.095274 in-data: aa e4 47 04 13 02 00 00
383 11:54:40.098445 Chrome EC: UHEPI supported
384 11:54:40.105251 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:54:40.108955 in-header: 03 95 00 00 08 00 00 00
386 11:54:40.112694 in-data: 18 20 20 08 00 00 00 00
387 11:54:40.112823 Phase 1
388 11:54:40.116454 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:54:40.123998 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:54:40.127831 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:54:40.131369 Recovery requested (1009000e)
392 11:54:40.139817 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:54:40.145752 tlcl_extend: response is 0
394 11:54:40.154966 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:54:40.160650 tlcl_extend: response is 0
396 11:54:40.167464 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:54:40.187759 read SPI 0x210d4 0x2173b: 15145 us, 9047 KB/s, 72.376 Mbps
398 11:54:40.195230 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:54:40.195322
400 11:54:40.195409
401 11:54:40.205839 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:54:40.205928 ARM64: Exception handlers installed.
403 11:54:40.209543 ARM64: Testing exception
404 11:54:40.212816 ARM64: Done test exception
405 11:54:40.233108 pmic_efuse_setting: Set efuses in 11 msecs
406 11:54:40.236411 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:54:40.242798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:54:40.246515 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:54:40.252900 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:54:40.256334 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:54:40.263309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:54:40.266587 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:54:40.269941 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:54:40.276456 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:54:40.279870 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:54:40.286434 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:54:40.289661 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:54:40.293127 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:54:40.299777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:54:40.306418 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:54:40.310422 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:54:40.317395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:54:40.321542 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:54:40.328454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:54:40.332282 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:54:40.339538 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:54:40.343432 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:54:40.350725 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:54:40.357826 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:54:40.361408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:54:40.365404 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:54:40.372379 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:54:40.376166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:54:40.383283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:54:40.386794 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:54:40.390612 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:54:40.397551 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:54:40.401537 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:54:40.408463 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:54:40.412153 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:54:40.415485 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:54:40.422911 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:54:40.426578 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:54:40.430328 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:54:40.438054 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:54:40.441469 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:54:40.444740 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:54:40.448130 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:54:40.455697 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:54:40.459132 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:54:40.462649 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:54:40.466645 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:54:40.469927 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:54:40.477315 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:54:40.481052 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:54:40.484455 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:54:40.488316 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:54:40.495535 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:54:40.502767 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:54:40.510123 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:54:40.517324 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:54:40.524484 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:54:40.532315 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:54:40.535690 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:54:40.539148 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:54:40.546308 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
467 11:54:40.553435 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:54:40.557193 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:54:40.560297 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:54:40.570323 [RTC]rtc_get_frequency_meter,154: input=15, output=764
471 11:54:40.580112 [RTC]rtc_get_frequency_meter,154: input=23, output=948
472 11:54:40.589360 [RTC]rtc_get_frequency_meter,154: input=19, output=857
473 11:54:40.598866 [RTC]rtc_get_frequency_meter,154: input=17, output=810
474 11:54:40.608752 [RTC]rtc_get_frequency_meter,154: input=16, output=788
475 11:54:40.617813 [RTC]rtc_get_frequency_meter,154: input=16, output=787
476 11:54:40.627999 [RTC]rtc_get_frequency_meter,154: input=17, output=811
477 11:54:40.631548 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:54:40.635164 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:54:40.642403 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:54:40.646166 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:54:40.649835 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:54:40.653380 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:54:40.657059 ADC[4]: Raw value=670063 ID=5
484 11:54:40.661136 ADC[3]: Raw value=212549 ID=1
485 11:54:40.661221 RAM Code: 0x51
486 11:54:40.664231 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:54:40.671314 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:54:40.678506 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-4GB' @0x75180 size 0x8 in mcache @0x00107f9c
489 11:54:40.685569 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
490 11:54:40.689074 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:54:40.692864 in-header: 03 07 00 00 08 00 00 00
492 11:54:40.692950 in-data: aa e4 47 04 13 02 00 00
493 11:54:40.696716 Chrome EC: UHEPI supported
494 11:54:40.703885 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:54:40.707633 in-header: 03 95 00 00 08 00 00 00
496 11:54:40.711495 in-data: 18 20 20 08 00 00 00 00
497 11:54:40.714813 MRC: failed to locate region type 0.
498 11:54:40.718629 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:54:40.721990 DRAM-K: Running full calibration
500 11:54:40.729940 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_4GB_2_2
501 11:54:40.730025 header.status = 0x0
502 11:54:40.733198 header.version = 0x6 (expected: 0x6)
503 11:54:40.736443 header.size = 0xd00 (expected: 0xd00)
504 11:54:40.740219 header.flags = 0x0
505 11:54:40.743802 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:54:40.763631 read SPI 0x72590 0x1c583: 12503 us, 9285 KB/s, 74.280 Mbps
507 11:54:40.771054 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:54:40.771138 dram_init: ddr_geometry: 0
509 11:54:40.774598 [EMI] MDL number = 0
510 11:54:40.778703 [EMI] Get MDL freq = 0
511 11:54:40.778785 dram_init: ddr_type: 0
512 11:54:40.782129 is_discrete_lpddr4: 1
513 11:54:40.785838 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:54:40.785920
515 11:54:40.785984
516 11:54:40.786044 [Bian_co] ETT version 0.0.0.1
517 11:54:40.793058 dram_type 6, R0 cbt_mode 0, R1 cbt_mode 0 VENDOR=6
518 11:54:40.793145
519 11:54:40.797362 dramc_set_vcore_voltage set vcore to 650000
520 11:54:40.797445 Read voltage for 800, 4
521 11:54:40.797511 Vio18 = 0
522 11:54:40.800586 Vcore = 650000
523 11:54:40.800695 Vdram = 0
524 11:54:40.800788 Vddq = 0
525 11:54:40.804213 Vmddr = 0
526 11:54:40.804321 dram_init: config_dvfs: 1
527 11:54:40.811920 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:54:40.815538 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:54:40.819064 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:54:40.822667 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:54:40.826384 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:54:40.830284 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:54:40.834109 MEM_TYPE=3, freq_sel=18
534 11:54:40.837745 sv_algorithm_assistance_LP4_1600
535 11:54:40.841328 ============ PULL DRAM RESETB DOWN ============
536 11:54:40.845030 ========== PULL DRAM RESETB DOWN end =========
537 11:54:40.848643 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:54:40.852260 ===================================
539 11:54:40.855812 LPDDR4 DRAM CONFIGURATION
540 11:54:40.859724 ===================================
541 11:54:40.859806 EX_ROW_EN[0] = 0x0
542 11:54:40.863387 EX_ROW_EN[1] = 0x0
543 11:54:40.863469 LP4Y_EN = 0x0
544 11:54:40.867108 WORK_FSP = 0x0
545 11:54:40.867190 WL = 0x2
546 11:54:40.867255 RL = 0x2
547 11:54:40.870673 BL = 0x2
548 11:54:40.870755 RPST = 0x0
549 11:54:40.874433 RD_PRE = 0x0
550 11:54:40.874515 WR_PRE = 0x1
551 11:54:40.878056 WR_PST = 0x0
552 11:54:40.878138 DBI_WR = 0x0
553 11:54:40.881399 DBI_RD = 0x0
554 11:54:40.881481 OTF = 0x1
555 11:54:40.885555 ===================================
556 11:54:40.888983 ===================================
557 11:54:40.889065 ANA top config
558 11:54:40.892834 ===================================
559 11:54:40.897039 DLL_ASYNC_EN = 0
560 11:54:40.900382 ALL_SLAVE_EN = 1
561 11:54:40.900490 NEW_RANK_MODE = 1
562 11:54:40.903547 DLL_IDLE_MODE = 1
563 11:54:40.906977 LP45_APHY_COMB_EN = 1
564 11:54:40.910384 TX_ODT_DIS = 1
565 11:54:40.910467 NEW_8X_MODE = 1
566 11:54:40.913719 ===================================
567 11:54:40.916890 ===================================
568 11:54:40.920319 data_rate = 1600
569 11:54:40.923978 CKR = 1
570 11:54:40.927796 DQ_P2S_RATIO = 8
571 11:54:40.931305 ===================================
572 11:54:40.931388 CA_P2S_RATIO = 8
573 11:54:40.935010 DQ_CA_OPEN = 0
574 11:54:40.938471 DQ_SEMI_OPEN = 0
575 11:54:40.942445 CA_SEMI_OPEN = 0
576 11:54:40.942527 CA_FULL_RATE = 0
577 11:54:40.945486 DQ_CKDIV4_EN = 1
578 11:54:40.948654 CA_CKDIV4_EN = 1
579 11:54:40.952011 CA_PREDIV_EN = 0
580 11:54:40.955451 PH8_DLY = 0
581 11:54:40.958825 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:54:40.962370 DQ_AAMCK_DIV = 4
583 11:54:40.962452 CA_AAMCK_DIV = 4
584 11:54:40.965608 CA_ADMCK_DIV = 4
585 11:54:40.969195 DQ_TRACK_CA_EN = 0
586 11:54:40.973250 CA_PICK = 800
587 11:54:40.973332 CA_MCKIO = 800
588 11:54:40.976824 MCKIO_SEMI = 0
589 11:54:40.980400 PLL_FREQ = 3068
590 11:54:40.983494 DQ_UI_PI_RATIO = 32
591 11:54:40.986934 CA_UI_PI_RATIO = 0
592 11:54:40.990448 ===================================
593 11:54:40.993688 ===================================
594 11:54:40.993770 memory_type:LPDDR4
595 11:54:40.997681 GP_NUM : 10
596 11:54:40.997763 SRAM_EN : 1
597 11:54:41.000970 MD32_EN : 0
598 11:54:41.004698 ===================================
599 11:54:41.008644 [ANA_INIT] >>>>>>>>>>>>>>
600 11:54:41.008727 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:54:41.012278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:54:41.015641 ===================================
603 11:54:41.019434 data_rate = 1600,PCW = 0X7600
604 11:54:41.023193 ===================================
605 11:54:41.026754 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:54:41.030431 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:54:41.037262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:54:41.040351 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:54:41.044183 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:54:41.047441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:54:41.050595 [ANA_INIT] flow start
612 11:54:41.053872 [ANA_INIT] PLL >>>>>>>>
613 11:54:41.053954 [ANA_INIT] PLL <<<<<<<<
614 11:54:41.057283 [ANA_INIT] MIDPI >>>>>>>>
615 11:54:41.060896 [ANA_INIT] MIDPI <<<<<<<<
616 11:54:41.060979 [ANA_INIT] DLL >>>>>>>>
617 11:54:41.063971 [ANA_INIT] flow end
618 11:54:41.067447 ============ LP4 DIFF to SE enter ============
619 11:54:41.070868 ============ LP4 DIFF to SE exit ============
620 11:54:41.074022 [ANA_INIT] <<<<<<<<<<<<<
621 11:54:41.077420 [Flow] Enable top DCM control >>>>>
622 11:54:41.080492 [Flow] Enable top DCM control <<<<<
623 11:54:41.083920 Enable DLL master slave shuffle
624 11:54:41.090601 ==============================================================
625 11:54:41.090686 Gating Mode config
626 11:54:41.097258 ==============================================================
627 11:54:41.097342 Config description:
628 11:54:41.107231 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:54:41.113963 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:54:41.120644 SELPH_MODE 0: By rank 1: By Phase
631 11:54:41.123945 ==============================================================
632 11:54:41.127218 GAT_TRACK_EN = 1
633 11:54:41.130564 RX_GATING_MODE = 2
634 11:54:41.134064 RX_GATING_TRACK_MODE = 2
635 11:54:41.137316 SELPH_MODE = 1
636 11:54:41.140631 PICG_EARLY_EN = 1
637 11:54:41.143938 VALID_LAT_VALUE = 1
638 11:54:41.147316 ==============================================================
639 11:54:41.150600 Enter into Gating configuration >>>>
640 11:54:41.154094 Exit from Gating configuration <<<<
641 11:54:41.157178 Enter into DVFS_PRE_config >>>>>
642 11:54:41.170913 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:54:41.173802 Exit from DVFS_PRE_config <<<<<
644 11:54:41.177111 Enter into PICG configuration >>>>
645 11:54:41.180560 Exit from PICG configuration <<<<
646 11:54:41.180643 [RX_INPUT] configuration >>>>>
647 11:54:41.183804 [RX_INPUT] configuration <<<<<
648 11:54:41.190552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:54:41.193835 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:54:41.200655 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:54:41.207377 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:54:41.214021 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:54:41.220898 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:54:41.224142 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:54:41.227414 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:54:41.230812 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:54:41.237436 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:54:41.240698 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:54:41.244416 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:54:41.247577 ===================================
661 11:54:41.250976 LPDDR4 DRAM CONFIGURATION
662 11:54:41.254372 ===================================
663 11:54:41.254456 EX_ROW_EN[0] = 0x0
664 11:54:41.257664 EX_ROW_EN[1] = 0x0
665 11:54:41.261050 LP4Y_EN = 0x0
666 11:54:41.261133 WORK_FSP = 0x0
667 11:54:41.264345 WL = 0x2
668 11:54:41.264428 RL = 0x2
669 11:54:41.267543 BL = 0x2
670 11:54:41.267627 RPST = 0x0
671 11:54:41.270862 RD_PRE = 0x0
672 11:54:41.270945 WR_PRE = 0x1
673 11:54:41.274317 WR_PST = 0x0
674 11:54:41.274400 DBI_WR = 0x0
675 11:54:41.277509 DBI_RD = 0x0
676 11:54:41.277592 OTF = 0x1
677 11:54:41.280986 ===================================
678 11:54:41.284239 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:54:41.290911 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:54:41.294278 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:54:41.297879 ===================================
682 11:54:41.300965 LPDDR4 DRAM CONFIGURATION
683 11:54:41.304358 ===================================
684 11:54:41.304442 EX_ROW_EN[0] = 0x10
685 11:54:41.307527 EX_ROW_EN[1] = 0x0
686 11:54:41.307611 LP4Y_EN = 0x0
687 11:54:41.311163 WORK_FSP = 0x0
688 11:54:41.311247 WL = 0x2
689 11:54:41.314302 RL = 0x2
690 11:54:41.314387 BL = 0x2
691 11:54:41.317842 RPST = 0x0
692 11:54:41.317929 RD_PRE = 0x0
693 11:54:41.321222 WR_PRE = 0x1
694 11:54:41.321318 WR_PST = 0x0
695 11:54:41.324283 DBI_WR = 0x0
696 11:54:41.327624 DBI_RD = 0x0
697 11:54:41.327716 OTF = 0x1
698 11:54:41.331136 ===================================
699 11:54:41.337765 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:54:41.341142 nWR fixed to 40
701 11:54:41.344460 [ModeRegInit_LP4] CH0 RK0
702 11:54:41.344558 [ModeRegInit_LP4] CH0 RK1
703 11:54:41.347735 [ModeRegInit_LP4] CH1 RK0
704 11:54:41.351036 [ModeRegInit_LP4] CH1 RK1
705 11:54:41.351121 match AC timing 12
706 11:54:41.357971 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 0
707 11:54:41.360932 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:54:41.364301 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:54:41.371077 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:54:41.374335 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:54:41.377512 [EMI DOE] emi_dcm 0
712 11:54:41.380947 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:54:41.381034 ==
714 11:54:41.384247 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:54:41.387890 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
716 11:54:41.387976 ==
717 11:54:41.394221 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:54:41.400691 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:54:41.408304 [CA 0] Center 37 (7~68) winsize 62
720 11:54:41.411938 [CA 1] Center 37 (7~68) winsize 62
721 11:54:41.415024 [CA 2] Center 35 (5~66) winsize 62
722 11:54:41.418515 [CA 3] Center 35 (4~66) winsize 63
723 11:54:41.421619 [CA 4] Center 34 (4~65) winsize 62
724 11:54:41.424965 [CA 5] Center 34 (4~64) winsize 61
725 11:54:41.425051
726 11:54:41.428379 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:54:41.428464
728 11:54:41.431630 [CATrainingPosCal] consider 1 rank data
729 11:54:41.435034 u2DelayCellTimex100 = 270/100 ps
730 11:54:41.438447 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
731 11:54:41.441610 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
732 11:54:41.448486 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
733 11:54:41.451832 CA3 delay=35 (4~66),Diff = 1 PI (7 cell)
734 11:54:41.454895 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
735 11:54:41.458342 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
736 11:54:41.458428
737 11:54:41.461859 CA PerBit enable=1, Macro0, CA PI delay=34
738 11:54:41.461944
739 11:54:41.465367 [CBTSetCACLKResult] CA Dly = 34
740 11:54:41.465452 CS Dly: 6 (0~37)
741 11:54:41.465519 ==
742 11:54:41.468471 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:54:41.475961 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
744 11:54:41.476048 ==
745 11:54:41.478553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:54:41.485041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:54:41.494200 [CA 0] Center 37 (6~68) winsize 63
748 11:54:41.497463 [CA 1] Center 37 (6~68) winsize 63
749 11:54:41.500901 [CA 2] Center 35 (4~66) winsize 63
750 11:54:41.504549 [CA 3] Center 34 (4~65) winsize 62
751 11:54:41.507694 [CA 4] Center 33 (3~64) winsize 62
752 11:54:41.511284 [CA 5] Center 33 (3~64) winsize 62
753 11:54:41.511371
754 11:54:41.514532 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:54:41.514617
756 11:54:41.517774 [CATrainingPosCal] consider 2 rank data
757 11:54:41.521333 u2DelayCellTimex100 = 270/100 ps
758 11:54:41.524511 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
759 11:54:41.528119 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
760 11:54:41.531160 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
761 11:54:41.537830 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
762 11:54:41.541401 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
763 11:54:41.544416 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
764 11:54:41.544503
765 11:54:41.547922 CA PerBit enable=1, Macro0, CA PI delay=34
766 11:54:41.548007
767 11:54:41.551253 [CBTSetCACLKResult] CA Dly = 34
768 11:54:41.551337 CS Dly: 6 (0~37)
769 11:54:41.551404
770 11:54:41.554637 ----->DramcWriteLeveling(PI) begin...
771 11:54:41.554750 ==
772 11:54:41.557856 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:54:41.564706 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
774 11:54:41.564842 ==
775 11:54:41.567891 Write leveling (Byte 0): 28 => 28
776 11:54:41.571329 Write leveling (Byte 1): 27 => 27
777 11:54:41.571441 DramcWriteLeveling(PI) end<-----
778 11:54:41.571538
779 11:54:41.574780 ==
780 11:54:41.574889 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:54:41.582030 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
782 11:54:41.582153 ==
783 11:54:41.582252 [Gating] SW mode calibration
784 11:54:41.589665 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:54:41.596466 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:54:41.599775 0 6 0 | B1->B0 | 3333 3232 | 1 0 | (1 0) (1 0)
787 11:54:41.603007 0 6 4 | B1->B0 | 2c2c 2323 | 0 0 | (1 1) (0 0)
788 11:54:41.610263 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:54:41.613951 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:54:41.617079 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:54:41.620266 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:54:41.626889 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:54:41.630535 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:54:41.633646 0 7 0 | B1->B0 | 2424 2b2b | 0 1 | (0 0) (0 0)
795 11:54:41.640235 0 7 4 | B1->B0 | 3b3b 4141 | 0 1 | (0 0) (0 0)
796 11:54:41.643498 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
797 11:54:41.646870 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
798 11:54:41.653544 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
799 11:54:41.656794 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
800 11:54:41.660158 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
801 11:54:41.666878 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
802 11:54:41.670107 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
803 11:54:41.673477 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
804 11:54:41.680441 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
805 11:54:41.683441 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
806 11:54:41.686783 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
807 11:54:41.693353 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
808 11:54:41.696931 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
809 11:54:41.700320 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
810 11:54:41.706788 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
811 11:54:41.710412 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
812 11:54:41.713507 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
813 11:54:41.720268 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
814 11:54:41.723847 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
815 11:54:41.726919 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
816 11:54:41.730365 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
817 11:54:41.736886 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
818 11:54:41.740498 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
819 11:54:41.743616 Total UI for P1: 0, mck2ui 16
820 11:54:41.746801 best dqsien dly found for B1: ( 0, 9, 30)
821 11:54:41.750272 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
822 11:54:41.757089 0 10 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
823 11:54:41.757185 Total UI for P1: 0, mck2ui 16
824 11:54:41.763622 best dqsien dly found for B0: ( 0, 10, 0)
825 11:54:41.766892 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
826 11:54:41.770299 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
827 11:54:41.770383
828 11:54:41.773678 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
829 11:54:41.776879 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
830 11:54:41.780468 [Gating] SW calibration Done
831 11:54:41.780591 ==
832 11:54:41.783550 Dram Type= 6, Freq= 0, CH_0, rank 0
833 11:54:41.786930 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
834 11:54:41.787015 ==
835 11:54:41.790287 RX Vref Scan: 0
836 11:54:41.790370
837 11:54:41.790435 RX Vref 0 -> 0, step: 1
838 11:54:41.790496
839 11:54:41.793796 RX Delay -130 -> 252, step: 16
840 11:54:41.796909 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
841 11:54:41.803588 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
842 11:54:41.807027 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
843 11:54:41.810287 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
844 11:54:41.813728 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
845 11:54:41.816896 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
846 11:54:41.823617 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
847 11:54:41.827077 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
848 11:54:41.830406 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
849 11:54:41.833638 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
850 11:54:41.836939 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
851 11:54:41.843564 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
852 11:54:41.847103 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
853 11:54:41.850521 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
854 11:54:41.853960 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
855 11:54:41.857177 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
856 11:54:41.860293 ==
857 11:54:41.863911 Dram Type= 6, Freq= 0, CH_0, rank 0
858 11:54:41.866970 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
859 11:54:41.867061 ==
860 11:54:41.867128 DQS Delay:
861 11:54:41.870312 DQS0 = 0, DQS1 = 0
862 11:54:41.870397 DQM Delay:
863 11:54:41.873526 DQM0 = 86, DQM1 = 75
864 11:54:41.873611 DQ Delay:
865 11:54:41.876936 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
866 11:54:41.880420 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
867 11:54:41.883674 DQ8 =61, DQ9 =53, DQ10 =77, DQ11 =69
868 11:54:41.886911 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
869 11:54:41.887000
870 11:54:41.887067
871 11:54:41.887128 ==
872 11:54:41.890249 Dram Type= 6, Freq= 0, CH_0, rank 0
873 11:54:41.893570 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
874 11:54:41.893665 ==
875 11:54:41.893733
876 11:54:41.893794
877 11:54:41.897021 TX Vref Scan disable
878 11:54:41.900388 == TX Byte 0 ==
879 11:54:41.903615 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
880 11:54:41.907103 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
881 11:54:41.910400 == TX Byte 1 ==
882 11:54:41.913641 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
883 11:54:41.917013 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
884 11:54:41.917102 ==
885 11:54:41.920362 Dram Type= 6, Freq= 0, CH_0, rank 0
886 11:54:41.923806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
887 11:54:41.923895 ==
888 11:54:41.938033 TX Vref=22, minBit 0, minWin=27, winSum=440
889 11:54:41.941281 TX Vref=24, minBit 2, minWin=27, winSum=444
890 11:54:41.944809 TX Vref=26, minBit 2, minWin=27, winSum=446
891 11:54:41.947950 TX Vref=28, minBit 0, minWin=28, winSum=448
892 11:54:41.951834 TX Vref=30, minBit 0, minWin=28, winSum=452
893 11:54:41.954961 TX Vref=32, minBit 0, minWin=28, winSum=450
894 11:54:41.961462 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 30
895 11:54:41.961569
896 11:54:41.964960 Final TX Range 1 Vref 30
897 11:54:41.965050
898 11:54:41.965116 ==
899 11:54:41.968432 Dram Type= 6, Freq= 0, CH_0, rank 0
900 11:54:41.971908 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
901 11:54:41.971997 ==
902 11:54:41.972064
903 11:54:41.972125
904 11:54:41.975144 TX Vref Scan disable
905 11:54:41.978635 == TX Byte 0 ==
906 11:54:41.982634 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
907 11:54:41.985282 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
908 11:54:41.988462 == TX Byte 1 ==
909 11:54:41.991997 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
910 11:54:41.995340 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
911 11:54:41.995437
912 11:54:41.998612 [DATLAT]
913 11:54:41.998697 Freq=800, CH0 RK0
914 11:54:41.998764
915 11:54:42.001890 DATLAT Default: 0xa
916 11:54:42.001976 0, 0xFFFF, sum = 0
917 11:54:42.005369 1, 0xFFFF, sum = 0
918 11:54:42.005462 2, 0xFFFF, sum = 0
919 11:54:42.008646 3, 0xFFFF, sum = 0
920 11:54:42.008733 4, 0xFFFF, sum = 0
921 11:54:42.012028 5, 0xFFFF, sum = 0
922 11:54:42.012121 6, 0xFFFF, sum = 0
923 11:54:42.015347 7, 0xFFFF, sum = 0
924 11:54:42.015435 8, 0x0, sum = 1
925 11:54:42.018745 9, 0x0, sum = 2
926 11:54:42.018832 10, 0x0, sum = 3
927 11:54:42.021924 11, 0x0, sum = 4
928 11:54:42.022010 best_step = 9
929 11:54:42.022076
930 11:54:42.022137 ==
931 11:54:42.025361 Dram Type= 6, Freq= 0, CH_0, rank 0
932 11:54:42.028437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
933 11:54:42.028530 ==
934 11:54:42.031823 RX Vref Scan: 1
935 11:54:42.031909
936 11:54:42.035357 Set Vref Range= 32 -> 127
937 11:54:42.035443
938 11:54:42.035509 RX Vref 32 -> 127, step: 1
939 11:54:42.035572
940 11:54:42.038965 RX Delay -111 -> 252, step: 8
941 11:54:42.039049
942 11:54:42.041765 Set Vref, RX VrefLevel [Byte0]: 32
943 11:54:42.045043 [Byte1]: 32
944 11:54:42.048854
945 11:54:42.048940 Set Vref, RX VrefLevel [Byte0]: 33
946 11:54:42.052022 [Byte1]: 33
947 11:54:42.056398
948 11:54:42.056489 Set Vref, RX VrefLevel [Byte0]: 34
949 11:54:42.059675 [Byte1]: 34
950 11:54:42.064042
951 11:54:42.064131 Set Vref, RX VrefLevel [Byte0]: 35
952 11:54:42.067267 [Byte1]: 35
953 11:54:42.071735
954 11:54:42.071822 Set Vref, RX VrefLevel [Byte0]: 36
955 11:54:42.075484 [Byte1]: 36
956 11:54:42.079409
957 11:54:42.079498 Set Vref, RX VrefLevel [Byte0]: 37
958 11:54:42.082953 [Byte1]: 37
959 11:54:42.086918
960 11:54:42.087005 Set Vref, RX VrefLevel [Byte0]: 38
961 11:54:42.090496 [Byte1]: 38
962 11:54:42.094856
963 11:54:42.094972 Set Vref, RX VrefLevel [Byte0]: 39
964 11:54:42.097981 [Byte1]: 39
965 11:54:42.102434
966 11:54:42.102533 Set Vref, RX VrefLevel [Byte0]: 40
967 11:54:42.105566 [Byte1]: 40
968 11:54:42.109931
969 11:54:42.110021 Set Vref, RX VrefLevel [Byte0]: 41
970 11:54:42.113144 [Byte1]: 41
971 11:54:42.117632
972 11:54:42.117723 Set Vref, RX VrefLevel [Byte0]: 42
973 11:54:42.120862 [Byte1]: 42
974 11:54:42.125424
975 11:54:42.125513 Set Vref, RX VrefLevel [Byte0]: 43
976 11:54:42.128441 [Byte1]: 43
977 11:54:42.132995
978 11:54:42.133085 Set Vref, RX VrefLevel [Byte0]: 44
979 11:54:42.136201 [Byte1]: 44
980 11:54:42.140616
981 11:54:42.140707 Set Vref, RX VrefLevel [Byte0]: 45
982 11:54:42.143806 [Byte1]: 45
983 11:54:42.148229
984 11:54:42.148320 Set Vref, RX VrefLevel [Byte0]: 46
985 11:54:42.151544 [Byte1]: 46
986 11:54:42.155883
987 11:54:42.155975 Set Vref, RX VrefLevel [Byte0]: 47
988 11:54:42.159098 [Byte1]: 47
989 11:54:42.163760
990 11:54:42.163851 Set Vref, RX VrefLevel [Byte0]: 48
991 11:54:42.166880 [Byte1]: 48
992 11:54:42.171080
993 11:54:42.171170 Set Vref, RX VrefLevel [Byte0]: 49
994 11:54:42.174379 [Byte1]: 49
995 11:54:42.178874
996 11:54:42.178965 Set Vref, RX VrefLevel [Byte0]: 50
997 11:54:42.182090 [Byte1]: 50
998 11:54:42.186364
999 11:54:42.186456 Set Vref, RX VrefLevel [Byte0]: 51
1000 11:54:42.189913 [Byte1]: 51
1001 11:54:42.193986
1002 11:54:42.194080 Set Vref, RX VrefLevel [Byte0]: 52
1003 11:54:42.197302 [Byte1]: 52
1004 11:54:42.201691
1005 11:54:42.201785 Set Vref, RX VrefLevel [Byte0]: 53
1006 11:54:42.205000 [Byte1]: 53
1007 11:54:42.209250
1008 11:54:42.209342 Set Vref, RX VrefLevel [Byte0]: 54
1009 11:54:42.212841 [Byte1]: 54
1010 11:54:42.217092
1011 11:54:42.217185 Set Vref, RX VrefLevel [Byte0]: 55
1012 11:54:42.223421 [Byte1]: 55
1013 11:54:42.223517
1014 11:54:42.226905 Set Vref, RX VrefLevel [Byte0]: 56
1015 11:54:42.230325 [Byte1]: 56
1016 11:54:42.230414
1017 11:54:42.233458 Set Vref, RX VrefLevel [Byte0]: 57
1018 11:54:42.236852 [Byte1]: 57
1019 11:54:42.236937
1020 11:54:42.240766 Set Vref, RX VrefLevel [Byte0]: 58
1021 11:54:42.243948 [Byte1]: 58
1022 11:54:42.248251
1023 11:54:42.248348 Set Vref, RX VrefLevel [Byte0]: 59
1024 11:54:42.251306 [Byte1]: 59
1025 11:54:42.255538
1026 11:54:42.255631 Set Vref, RX VrefLevel [Byte0]: 60
1027 11:54:42.258641 [Byte1]: 60
1028 11:54:42.263253
1029 11:54:42.263347 Set Vref, RX VrefLevel [Byte0]: 61
1030 11:54:42.266787 [Byte1]: 61
1031 11:54:42.270272
1032 11:54:42.273806 Set Vref, RX VrefLevel [Byte0]: 62
1033 11:54:42.273901 [Byte1]: 62
1034 11:54:42.278018
1035 11:54:42.278105 Set Vref, RX VrefLevel [Byte0]: 63
1036 11:54:42.281544 [Byte1]: 63
1037 11:54:42.285752
1038 11:54:42.285837 Set Vref, RX VrefLevel [Byte0]: 64
1039 11:54:42.289094 [Byte1]: 64
1040 11:54:42.293677
1041 11:54:42.293768 Set Vref, RX VrefLevel [Byte0]: 65
1042 11:54:42.296783 [Byte1]: 65
1043 11:54:42.301183
1044 11:54:42.301272 Set Vref, RX VrefLevel [Byte0]: 66
1045 11:54:42.304336 [Byte1]: 66
1046 11:54:42.308723
1047 11:54:42.308822 Set Vref, RX VrefLevel [Byte0]: 67
1048 11:54:42.311999 [Byte1]: 67
1049 11:54:42.316405
1050 11:54:42.316493 Set Vref, RX VrefLevel [Byte0]: 68
1051 11:54:42.319838 [Byte1]: 68
1052 11:54:42.323908
1053 11:54:42.323995 Set Vref, RX VrefLevel [Byte0]: 69
1054 11:54:42.327202 [Byte1]: 69
1055 11:54:42.331626
1056 11:54:42.331717 Set Vref, RX VrefLevel [Byte0]: 70
1057 11:54:42.335093 [Byte1]: 70
1058 11:54:42.339300
1059 11:54:42.339417 Set Vref, RX VrefLevel [Byte0]: 71
1060 11:54:42.342469 [Byte1]: 71
1061 11:54:42.346907
1062 11:54:42.347022 Set Vref, RX VrefLevel [Byte0]: 72
1063 11:54:42.350365 [Byte1]: 72
1064 11:54:42.354499
1065 11:54:42.354620 Set Vref, RX VrefLevel [Byte0]: 73
1066 11:54:42.357928 [Byte1]: 73
1067 11:54:42.362104
1068 11:54:42.362216 Set Vref, RX VrefLevel [Byte0]: 74
1069 11:54:42.365509 [Byte1]: 74
1070 11:54:42.369981
1071 11:54:42.370094 Set Vref, RX VrefLevel [Byte0]: 75
1072 11:54:42.373321 [Byte1]: 75
1073 11:54:42.377398
1074 11:54:42.377508 Final RX Vref Byte 0 = 53 to rank0
1075 11:54:42.380896 Final RX Vref Byte 1 = 51 to rank0
1076 11:54:42.384006 Final RX Vref Byte 0 = 53 to rank1
1077 11:54:42.387327 Final RX Vref Byte 1 = 51 to rank1==
1078 11:54:42.390749 Dram Type= 6, Freq= 0, CH_0, rank 0
1079 11:54:42.397627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1080 11:54:42.397768 ==
1081 11:54:42.397866 DQS Delay:
1082 11:54:42.397958 DQS0 = 0, DQS1 = 0
1083 11:54:42.400721 DQM Delay:
1084 11:54:42.400828 DQM0 = 83, DQM1 = 73
1085 11:54:42.404059 DQ Delay:
1086 11:54:42.407592 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1087 11:54:42.407706 DQ4 =88, DQ5 =72, DQ6 =92, DQ7 =92
1088 11:54:42.410758 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1089 11:54:42.414156 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =84
1090 11:54:42.417557
1091 11:54:42.417644
1092 11:54:42.424257 [DQSOSCAuto] RK0, (LSB)MR18= 0x3c3c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
1093 11:54:42.427694 CH0 RK0: MR19=606, MR18=3C3C
1094 11:54:42.434395 CH0_RK0: MR19=0x606, MR18=0x3C3C, DQSOSC=394, MR23=63, INC=95, DEC=63
1095 11:54:42.434500
1096 11:54:42.437655 ----->DramcWriteLeveling(PI) begin...
1097 11:54:42.437743 ==
1098 11:54:42.441108 Dram Type= 6, Freq= 0, CH_0, rank 1
1099 11:54:42.444260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1100 11:54:42.444351 ==
1101 11:54:42.447629 Write leveling (Byte 0): 27 => 27
1102 11:54:42.450844 Write leveling (Byte 1): 27 => 27
1103 11:54:42.454371 DramcWriteLeveling(PI) end<-----
1104 11:54:42.454461
1105 11:54:42.454525 ==
1106 11:54:42.457671 Dram Type= 6, Freq= 0, CH_0, rank 1
1107 11:54:42.460806 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1108 11:54:42.460892 ==
1109 11:54:42.464247 [Gating] SW mode calibration
1110 11:54:42.471005 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1111 11:54:42.477554 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1112 11:54:42.480846 0 6 0 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
1113 11:54:42.484275 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1114 11:54:42.490904 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1115 11:54:42.494181 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1116 11:54:42.497484 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1117 11:54:42.504221 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1118 11:54:42.507869 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1119 11:54:42.510952 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1120 11:54:42.517419 0 7 0 | B1->B0 | 2b2b 2e2e | 1 0 | (0 0) (0 0)
1121 11:54:42.520801 0 7 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1122 11:54:42.524299 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1123 11:54:42.530833 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1124 11:54:42.534139 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1125 11:54:42.537452 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1126 11:54:42.540759 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1127 11:54:42.547611 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1128 11:54:42.550760 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1129 11:54:42.553993 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1130 11:54:42.561001 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1131 11:54:42.563947 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1132 11:54:42.567498 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1133 11:54:42.573938 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1134 11:54:42.577352 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1135 11:54:42.580855 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1136 11:54:42.587288 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1137 11:54:42.590594 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1138 11:54:42.593985 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1139 11:54:42.600495 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1140 11:54:42.603976 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1141 11:54:42.607316 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1142 11:54:42.613954 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1143 11:54:42.617154 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1144 11:54:42.620573 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1145 11:54:42.627401 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1146 11:54:42.627508 Total UI for P1: 0, mck2ui 16
1147 11:54:42.633865 best dqsien dly found for B0: ( 0, 10, 0)
1148 11:54:42.633965 Total UI for P1: 0, mck2ui 16
1149 11:54:42.637172 best dqsien dly found for B1: ( 0, 10, 0)
1150 11:54:42.643840 best DQS0 dly(MCK, UI, PI) = (0, 10, 0)
1151 11:54:42.647088 best DQS1 dly(MCK, UI, PI) = (0, 10, 0)
1152 11:54:42.647179
1153 11:54:42.691357 best DQS0 P1 dly(MCK, UI, PI) = (0, 14, 0)
1154 11:54:42.691598 best DQS1 P1 dly(MCK, UI, PI) = (0, 14, 0)
1155 11:54:42.691697 [Gating] SW calibration Done
1156 11:54:42.691788 ==
1157 11:54:42.691848 Dram Type= 6, Freq= 0, CH_0, rank 1
1158 11:54:42.692127 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1159 11:54:42.692209 ==
1160 11:54:42.692266 RX Vref Scan: 0
1161 11:54:42.692323
1162 11:54:42.692378 RX Vref 0 -> 0, step: 1
1163 11:54:42.692433
1164 11:54:42.692499 RX Delay -130 -> 252, step: 16
1165 11:54:42.692610 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1166 11:54:42.692665 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1167 11:54:42.692933 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1168 11:54:42.692992 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1169 11:54:42.693243 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1170 11:54:42.729452 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1171 11:54:42.729855 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1172 11:54:42.729932 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1173 11:54:42.729995 iDelay=222, Bit 8, Center 61 (-50 ~ 173) 224
1174 11:54:42.730054 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1175 11:54:42.730125 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1176 11:54:42.730220 iDelay=222, Bit 11, Center 61 (-50 ~ 173) 224
1177 11:54:42.730506 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1178 11:54:42.730617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1179 11:54:42.730674 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1180 11:54:42.733691 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1181 11:54:42.736901 ==
1182 11:54:42.740185 Dram Type= 6, Freq= 0, CH_0, rank 1
1183 11:54:42.743669 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1184 11:54:42.743756 ==
1185 11:54:42.743820 DQS Delay:
1186 11:54:42.747015 DQS0 = 0, DQS1 = 0
1187 11:54:42.747099 DQM Delay:
1188 11:54:42.750163 DQM0 = 84, DQM1 = 72
1189 11:54:42.750246 DQ Delay:
1190 11:54:42.753842 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
1191 11:54:42.756887 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
1192 11:54:42.760494 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1193 11:54:42.763692 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1194 11:54:42.763777
1195 11:54:42.763841
1196 11:54:42.763900 ==
1197 11:54:42.766806 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 11:54:42.770212 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1199 11:54:42.770298 ==
1200 11:54:42.770363
1201 11:54:42.770423
1202 11:54:42.773581 TX Vref Scan disable
1203 11:54:42.777112 == TX Byte 0 ==
1204 11:54:42.780245 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1205 11:54:42.783943 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1206 11:54:42.786977 == TX Byte 1 ==
1207 11:54:42.790294 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1208 11:54:42.793826 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1209 11:54:42.793916 ==
1210 11:54:42.797104 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:54:42.800345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1212 11:54:42.803571 ==
1213 11:54:42.814510 TX Vref=22, minBit 0, minWin=27, winSum=441
1214 11:54:42.818077 TX Vref=24, minBit 0, minWin=27, winSum=446
1215 11:54:42.821717 TX Vref=26, minBit 14, minWin=27, winSum=449
1216 11:54:42.825310 TX Vref=28, minBit 4, minWin=28, winSum=457
1217 11:54:42.829672 TX Vref=30, minBit 4, minWin=28, winSum=455
1218 11:54:42.833319 TX Vref=32, minBit 2, minWin=28, winSum=456
1219 11:54:42.840494 [TxChooseVref] Worse bit 4, Min win 28, Win sum 457, Final Vref 28
1220 11:54:42.840690
1221 11:54:42.840788 Final TX Range 1 Vref 28
1222 11:54:42.840878
1223 11:54:42.840966 ==
1224 11:54:42.843573 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 11:54:42.850301 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1226 11:54:42.850433 ==
1227 11:54:42.850528
1228 11:54:42.850616
1229 11:54:42.850704 TX Vref Scan disable
1230 11:54:42.854833 == TX Byte 0 ==
1231 11:54:42.857915 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1232 11:54:42.861278 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1233 11:54:42.864654 == TX Byte 1 ==
1234 11:54:42.867720 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1235 11:54:42.874475 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1236 11:54:42.874606
1237 11:54:42.874704 [DATLAT]
1238 11:54:42.874796 Freq=800, CH0 RK1
1239 11:54:42.874885
1240 11:54:42.877894 DATLAT Default: 0x9
1241 11:54:42.878007 0, 0xFFFF, sum = 0
1242 11:54:42.881538 1, 0xFFFF, sum = 0
1243 11:54:42.881648 2, 0xFFFF, sum = 0
1244 11:54:42.884491 3, 0xFFFF, sum = 0
1245 11:54:42.884606 4, 0xFFFF, sum = 0
1246 11:54:42.887898 5, 0xFFFF, sum = 0
1247 11:54:42.891102 6, 0xFFFF, sum = 0
1248 11:54:42.891211 7, 0xFFFF, sum = 0
1249 11:54:42.891305 8, 0x0, sum = 1
1250 11:54:42.894472 9, 0x0, sum = 2
1251 11:54:42.894582 10, 0x0, sum = 3
1252 11:54:42.897827 11, 0x0, sum = 4
1253 11:54:42.897935 best_step = 9
1254 11:54:42.898028
1255 11:54:42.898119 ==
1256 11:54:42.901301 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 11:54:42.907790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1258 11:54:42.907932 ==
1259 11:54:42.908030 RX Vref Scan: 0
1260 11:54:42.908122
1261 11:54:42.911199 RX Vref 0 -> 0, step: 1
1262 11:54:42.911309
1263 11:54:42.914482 RX Delay -111 -> 252, step: 8
1264 11:54:42.917759 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1265 11:54:42.921065 iDelay=217, Bit 1, Center 88 (-31 ~ 208) 240
1266 11:54:42.927873 iDelay=217, Bit 2, Center 84 (-31 ~ 200) 232
1267 11:54:42.931132 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1268 11:54:42.934285 iDelay=217, Bit 4, Center 88 (-31 ~ 208) 240
1269 11:54:42.937617 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1270 11:54:42.941021 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1271 11:54:42.947793 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1272 11:54:42.951025 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
1273 11:54:42.954431 iDelay=217, Bit 9, Center 64 (-47 ~ 176) 224
1274 11:54:42.957681 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1275 11:54:42.961109 iDelay=217, Bit 11, Center 64 (-47 ~ 176) 224
1276 11:54:42.967827 iDelay=217, Bit 12, Center 80 (-31 ~ 192) 224
1277 11:54:42.971067 iDelay=217, Bit 13, Center 80 (-31 ~ 192) 224
1278 11:54:42.974368 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
1279 11:54:42.977704 iDelay=217, Bit 15, Center 80 (-31 ~ 192) 224
1280 11:54:42.977795 ==
1281 11:54:42.981323 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 11:54:42.984437 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1283 11:54:42.987713 ==
1284 11:54:42.987800 DQS Delay:
1285 11:54:42.987865 DQS0 = 0, DQS1 = 0
1286 11:54:42.991349 DQM Delay:
1287 11:54:42.991432 DQM0 = 86, DQM1 = 74
1288 11:54:42.994663 DQ Delay:
1289 11:54:42.994751 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1290 11:54:42.997972 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1291 11:54:43.001241 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =64
1292 11:54:43.004372 DQ12 =80, DQ13 =80, DQ14 =84, DQ15 =80
1293 11:54:43.004465
1294 11:54:43.008001
1295 11:54:43.014695 [DQSOSCAuto] RK1, (LSB)MR18= 0x4141, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
1296 11:54:43.018121 CH0 RK1: MR19=606, MR18=4141
1297 11:54:43.024703 CH0_RK1: MR19=0x606, MR18=0x4141, DQSOSC=393, MR23=63, INC=95, DEC=63
1298 11:54:43.024804 [RxdqsGatingPostProcess] freq 800
1299 11:54:43.031077 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1300 11:54:43.034417 Pre-setting of DQS Precalculation
1301 11:54:43.037873 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1302 11:54:43.041079 ==
1303 11:54:43.041191 Dram Type= 6, Freq= 0, CH_1, rank 0
1304 11:54:43.047873 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1305 11:54:43.047967 ==
1306 11:54:43.051203 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1307 11:54:43.057761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1308 11:54:43.067400 [CA 0] Center 36 (6~67) winsize 62
1309 11:54:43.070942 [CA 1] Center 36 (6~67) winsize 62
1310 11:54:43.073889 [CA 2] Center 34 (4~65) winsize 62
1311 11:54:43.077249 [CA 3] Center 34 (4~64) winsize 61
1312 11:54:43.080641 [CA 4] Center 33 (3~64) winsize 62
1313 11:54:43.084006 [CA 5] Center 33 (3~64) winsize 62
1314 11:54:43.084093
1315 11:54:43.087416 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1316 11:54:43.087500
1317 11:54:43.090671 [CATrainingPosCal] consider 1 rank data
1318 11:54:43.093876 u2DelayCellTimex100 = 270/100 ps
1319 11:54:43.097336 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1320 11:54:43.100676 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1321 11:54:43.107242 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1322 11:54:43.110504 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1323 11:54:43.113923 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1324 11:54:43.117499 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1325 11:54:43.117587
1326 11:54:43.120628 CA PerBit enable=1, Macro0, CA PI delay=33
1327 11:54:43.120712
1328 11:54:43.123979 [CBTSetCACLKResult] CA Dly = 33
1329 11:54:43.124062 CS Dly: 4 (0~35)
1330 11:54:43.124127 ==
1331 11:54:43.127345 Dram Type= 6, Freq= 0, CH_1, rank 1
1332 11:54:43.134075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1333 11:54:43.134172 ==
1334 11:54:43.137426 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1335 11:54:43.143736 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1336 11:54:43.153107 [CA 0] Center 36 (6~67) winsize 62
1337 11:54:43.156520 [CA 1] Center 36 (5~67) winsize 63
1338 11:54:43.159670 [CA 2] Center 34 (3~65) winsize 63
1339 11:54:43.163054 [CA 3] Center 34 (3~65) winsize 63
1340 11:54:43.166437 [CA 4] Center 33 (2~64) winsize 63
1341 11:54:43.169652 [CA 5] Center 33 (3~64) winsize 62
1342 11:54:43.169738
1343 11:54:43.172918 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1344 11:54:43.173002
1345 11:54:43.176314 [CATrainingPosCal] consider 2 rank data
1346 11:54:43.179653 u2DelayCellTimex100 = 270/100 ps
1347 11:54:43.183061 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1348 11:54:43.186344 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1349 11:54:43.192930 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1350 11:54:43.196368 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1351 11:54:43.199895 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
1352 11:54:43.202894 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1353 11:54:43.202997
1354 11:54:43.206298 CA PerBit enable=1, Macro0, CA PI delay=33
1355 11:54:43.206382
1356 11:54:43.209540 [CBTSetCACLKResult] CA Dly = 33
1357 11:54:43.209624 CS Dly: 4 (0~36)
1358 11:54:43.209688
1359 11:54:43.213018 ----->DramcWriteLeveling(PI) begin...
1360 11:54:43.216154 ==
1361 11:54:43.219723 Dram Type= 6, Freq= 0, CH_1, rank 0
1362 11:54:43.222837 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1363 11:54:43.222925 ==
1364 11:54:43.226363 Write leveling (Byte 0): 23 => 23
1365 11:54:43.229717 Write leveling (Byte 1): 25 => 25
1366 11:54:43.232877 DramcWriteLeveling(PI) end<-----
1367 11:54:43.232962
1368 11:54:43.233026 ==
1369 11:54:43.236126 Dram Type= 6, Freq= 0, CH_1, rank 0
1370 11:54:43.239533 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1371 11:54:43.239618 ==
1372 11:54:43.242864 [Gating] SW mode calibration
1373 11:54:43.249585 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1374 11:54:43.252987 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1375 11:54:43.259553 0 6 0 | B1->B0 | 2e2e 2525 | 0 0 | (1 0) (0 0)
1376 11:54:43.262834 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1377 11:54:43.266304 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1378 11:54:43.272819 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1379 11:54:43.276146 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1380 11:54:43.279515 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1381 11:54:43.286063 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1382 11:54:43.289503 0 6 28 | B1->B0 | 2525 2f2f | 0 0 | (0 0) (0 0)
1383 11:54:43.292849 0 7 0 | B1->B0 | 2f2f 3d3d | 1 0 | (0 0) (0 0)
1384 11:54:43.299521 0 7 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
1385 11:54:43.302633 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1386 11:54:43.306158 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1387 11:54:43.312653 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1388 11:54:43.316012 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1389 11:54:43.319366 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1390 11:54:43.325980 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1391 11:54:43.329535 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1392 11:54:43.332540 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1393 11:54:43.339437 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1394 11:54:43.342718 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1395 11:54:43.345998 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1396 11:54:43.349531 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1397 11:54:43.356003 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1398 11:54:43.359355 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1399 11:54:43.362751 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1400 11:54:43.369246 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1401 11:54:43.372615 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1402 11:54:43.376319 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1403 11:54:43.382574 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1404 11:54:43.385950 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1405 11:54:43.389379 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1406 11:54:43.395988 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1407 11:54:43.399233 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1408 11:54:43.402575 Total UI for P1: 0, mck2ui 16
1409 11:54:43.405932 best dqsien dly found for B0: ( 0, 9, 30)
1410 11:54:43.409243 Total UI for P1: 0, mck2ui 16
1411 11:54:43.412632 best dqsien dly found for B1: ( 0, 9, 30)
1412 11:54:43.415888 best DQS0 dly(MCK, UI, PI) = (0, 9, 30)
1413 11:54:43.419111 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1414 11:54:43.419202
1415 11:54:43.422415 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 30)
1416 11:54:43.425663 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1417 11:54:43.429100 [Gating] SW calibration Done
1418 11:54:43.429187 ==
1419 11:54:43.432844 Dram Type= 6, Freq= 0, CH_1, rank 0
1420 11:54:43.438918 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1421 11:54:43.439018 ==
1422 11:54:43.439087 RX Vref Scan: 0
1423 11:54:43.439148
1424 11:54:43.442512 RX Vref 0 -> 0, step: 1
1425 11:54:43.442596
1426 11:54:43.445814 RX Delay -130 -> 252, step: 16
1427 11:54:43.449079 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1428 11:54:43.452242 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1429 11:54:43.455537 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1430 11:54:43.459005 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1431 11:54:43.465745 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1432 11:54:43.468939 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1433 11:54:43.472233 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1434 11:54:43.475560 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1435 11:54:43.478914 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1436 11:54:43.486381 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1437 11:54:43.490067 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1438 11:54:43.493639 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1439 11:54:43.497080 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1440 11:54:43.500945 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1441 11:54:43.504473 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1442 11:54:43.508385 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1443 11:54:43.508481 ==
1444 11:54:43.512266 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:54:43.515391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1446 11:54:43.515484 ==
1447 11:54:43.519374 DQS Delay:
1448 11:54:43.519465 DQS0 = 0, DQS1 = 0
1449 11:54:43.519533 DQM Delay:
1450 11:54:43.522477 DQM0 = 80, DQM1 = 70
1451 11:54:43.522562 DQ Delay:
1452 11:54:43.526012 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1453 11:54:43.529042 DQ4 =77, DQ5 =93, DQ6 =85, DQ7 =77
1454 11:54:43.532890 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1455 11:54:43.535765 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1456 11:54:43.535882
1457 11:54:43.535975
1458 11:54:43.536064 ==
1459 11:54:43.539150 Dram Type= 6, Freq= 0, CH_1, rank 0
1460 11:54:43.545671 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1461 11:54:43.545791 ==
1462 11:54:43.545886
1463 11:54:43.545976
1464 11:54:43.546065 TX Vref Scan disable
1465 11:54:43.549036 == TX Byte 0 ==
1466 11:54:43.552439 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1467 11:54:43.555739 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1468 11:54:43.559319 == TX Byte 1 ==
1469 11:54:43.562695 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1470 11:54:43.566111 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1471 11:54:43.569108 ==
1472 11:54:43.572620 Dram Type= 6, Freq= 0, CH_1, rank 0
1473 11:54:43.575817 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1474 11:54:43.575930 ==
1475 11:54:43.588281 TX Vref=22, minBit 0, minWin=27, winSum=445
1476 11:54:43.591541 TX Vref=24, minBit 0, minWin=28, winSum=454
1477 11:54:43.594845 TX Vref=26, minBit 3, minWin=28, winSum=457
1478 11:54:43.598011 TX Vref=28, minBit 3, minWin=28, winSum=457
1479 11:54:43.601348 TX Vref=30, minBit 8, minWin=28, winSum=459
1480 11:54:43.604649 TX Vref=32, minBit 8, minWin=28, winSum=460
1481 11:54:43.611369 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 32
1482 11:54:43.611483
1483 11:54:43.614737 Final TX Range 1 Vref 32
1484 11:54:43.614846
1485 11:54:43.614939 ==
1486 11:54:43.617985 Dram Type= 6, Freq= 0, CH_1, rank 0
1487 11:54:43.621342 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1488 11:54:43.621452 ==
1489 11:54:43.624790
1490 11:54:43.624897
1491 11:54:43.624989 TX Vref Scan disable
1492 11:54:43.628191 == TX Byte 0 ==
1493 11:54:43.631395 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
1494 11:54:43.634692 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
1495 11:54:43.638126 == TX Byte 1 ==
1496 11:54:43.641417 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1497 11:54:43.644937 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1498 11:54:43.648110
1499 11:54:43.648216 [DATLAT]
1500 11:54:43.648310 Freq=800, CH1 RK0
1501 11:54:43.648400
1502 11:54:43.651485 DATLAT Default: 0xa
1503 11:54:43.651575 0, 0xFFFF, sum = 0
1504 11:54:43.655040 1, 0xFFFF, sum = 0
1505 11:54:43.655127 2, 0xFFFF, sum = 0
1506 11:54:43.658369 3, 0xFFFF, sum = 0
1507 11:54:43.658453 4, 0xFFFF, sum = 0
1508 11:54:43.661718 5, 0xFFFF, sum = 0
1509 11:54:43.661803 6, 0xFFFF, sum = 0
1510 11:54:43.665042 7, 0xFFFF, sum = 0
1511 11:54:43.665126 8, 0x0, sum = 1
1512 11:54:43.668281 9, 0x0, sum = 2
1513 11:54:43.668365 10, 0x0, sum = 3
1514 11:54:43.671888 11, 0x0, sum = 4
1515 11:54:43.671972 best_step = 9
1516 11:54:43.672038
1517 11:54:43.672098 ==
1518 11:54:43.675017 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 11:54:43.678483 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1520 11:54:43.681961 ==
1521 11:54:43.682048 RX Vref Scan: 1
1522 11:54:43.682113
1523 11:54:43.685126 Set Vref Range= 32 -> 127
1524 11:54:43.685212
1525 11:54:43.688680 RX Vref 32 -> 127, step: 1
1526 11:54:43.688763
1527 11:54:43.688830 RX Delay -111 -> 252, step: 8
1528 11:54:43.688891
1529 11:54:43.691886 Set Vref, RX VrefLevel [Byte0]: 32
1530 11:54:43.695236 [Byte1]: 32
1531 11:54:43.699126
1532 11:54:43.699220 Set Vref, RX VrefLevel [Byte0]: 33
1533 11:54:43.702391 [Byte1]: 33
1534 11:54:43.706896
1535 11:54:43.706985 Set Vref, RX VrefLevel [Byte0]: 34
1536 11:54:43.709904 [Byte1]: 34
1537 11:54:43.714280
1538 11:54:43.714370 Set Vref, RX VrefLevel [Byte0]: 35
1539 11:54:43.717651 [Byte1]: 35
1540 11:54:43.722007
1541 11:54:43.722099 Set Vref, RX VrefLevel [Byte0]: 36
1542 11:54:43.725252 [Byte1]: 36
1543 11:54:43.729643
1544 11:54:43.729733 Set Vref, RX VrefLevel [Byte0]: 37
1545 11:54:43.732794 [Byte1]: 37
1546 11:54:43.737429
1547 11:54:43.737520 Set Vref, RX VrefLevel [Byte0]: 38
1548 11:54:43.740633 [Byte1]: 38
1549 11:54:43.745095
1550 11:54:43.745184 Set Vref, RX VrefLevel [Byte0]: 39
1551 11:54:43.748253 [Byte1]: 39
1552 11:54:43.752760
1553 11:54:43.752848 Set Vref, RX VrefLevel [Byte0]: 40
1554 11:54:43.755917 [Byte1]: 40
1555 11:54:43.760144
1556 11:54:43.760228 Set Vref, RX VrefLevel [Byte0]: 41
1557 11:54:43.763636 [Byte1]: 41
1558 11:54:43.767783
1559 11:54:43.767868 Set Vref, RX VrefLevel [Byte0]: 42
1560 11:54:43.771139 [Byte1]: 42
1561 11:54:43.775454
1562 11:54:43.775545 Set Vref, RX VrefLevel [Byte0]: 43
1563 11:54:43.778804 [Byte1]: 43
1564 11:54:43.783043
1565 11:54:43.783129 Set Vref, RX VrefLevel [Byte0]: 44
1566 11:54:43.789582 [Byte1]: 44
1567 11:54:43.789685
1568 11:54:43.793022 Set Vref, RX VrefLevel [Byte0]: 45
1569 11:54:43.796290 [Byte1]: 45
1570 11:54:43.796377
1571 11:54:43.799774 Set Vref, RX VrefLevel [Byte0]: 46
1572 11:54:43.802933 [Byte1]: 46
1573 11:54:43.803018
1574 11:54:43.806243 Set Vref, RX VrefLevel [Byte0]: 47
1575 11:54:43.809814 [Byte1]: 47
1576 11:54:43.813850
1577 11:54:43.813939 Set Vref, RX VrefLevel [Byte0]: 48
1578 11:54:43.817041 [Byte1]: 48
1579 11:54:43.821671
1580 11:54:43.821785 Set Vref, RX VrefLevel [Byte0]: 49
1581 11:54:43.824876 [Byte1]: 49
1582 11:54:43.829092
1583 11:54:43.829178 Set Vref, RX VrefLevel [Byte0]: 50
1584 11:54:43.832254 [Byte1]: 50
1585 11:54:43.836718
1586 11:54:43.836806 Set Vref, RX VrefLevel [Byte0]: 51
1587 11:54:43.839973 [Byte1]: 51
1588 11:54:43.844260
1589 11:54:43.844348 Set Vref, RX VrefLevel [Byte0]: 52
1590 11:54:43.847652 [Byte1]: 52
1591 11:54:43.852081
1592 11:54:43.852169 Set Vref, RX VrefLevel [Byte0]: 53
1593 11:54:43.855267 [Byte1]: 53
1594 11:54:43.859691
1595 11:54:43.859776 Set Vref, RX VrefLevel [Byte0]: 54
1596 11:54:43.862808 [Byte1]: 54
1597 11:54:43.867326
1598 11:54:43.867411 Set Vref, RX VrefLevel [Byte0]: 55
1599 11:54:43.870646 [Byte1]: 55
1600 11:54:43.875187
1601 11:54:43.875273 Set Vref, RX VrefLevel [Byte0]: 56
1602 11:54:43.878150 [Byte1]: 56
1603 11:54:43.882519
1604 11:54:43.882608 Set Vref, RX VrefLevel [Byte0]: 57
1605 11:54:43.885952 [Byte1]: 57
1606 11:54:43.890287
1607 11:54:43.890376 Set Vref, RX VrefLevel [Byte0]: 58
1608 11:54:43.893493 [Byte1]: 58
1609 11:54:43.897944
1610 11:54:43.898041 Set Vref, RX VrefLevel [Byte0]: 59
1611 11:54:43.901378 [Byte1]: 59
1612 11:54:43.905591
1613 11:54:43.905713 Set Vref, RX VrefLevel [Byte0]: 60
1614 11:54:43.908817 [Byte1]: 60
1615 11:54:43.913029
1616 11:54:43.913138 Set Vref, RX VrefLevel [Byte0]: 61
1617 11:54:43.916409 [Byte1]: 61
1618 11:54:43.920884
1619 11:54:43.920996 Set Vref, RX VrefLevel [Byte0]: 62
1620 11:54:43.924018 [Byte1]: 62
1621 11:54:43.928345
1622 11:54:43.928454 Set Vref, RX VrefLevel [Byte0]: 63
1623 11:54:43.931838 [Byte1]: 63
1624 11:54:43.936197
1625 11:54:43.936309 Set Vref, RX VrefLevel [Byte0]: 64
1626 11:54:43.939580 [Byte1]: 64
1627 11:54:43.943773
1628 11:54:43.943885 Set Vref, RX VrefLevel [Byte0]: 65
1629 11:54:43.946995 [Byte1]: 65
1630 11:54:43.951190
1631 11:54:43.951302 Set Vref, RX VrefLevel [Byte0]: 66
1632 11:54:43.954561 [Byte1]: 66
1633 11:54:43.959209
1634 11:54:43.959296 Set Vref, RX VrefLevel [Byte0]: 67
1635 11:54:43.962313 [Byte1]: 67
1636 11:54:43.966874
1637 11:54:43.966960 Set Vref, RX VrefLevel [Byte0]: 68
1638 11:54:43.970099 [Byte1]: 68
1639 11:54:43.974304
1640 11:54:43.974392 Set Vref, RX VrefLevel [Byte0]: 69
1641 11:54:43.977538 [Byte1]: 69
1642 11:54:43.981907
1643 11:54:43.981995 Set Vref, RX VrefLevel [Byte0]: 70
1644 11:54:43.985361 [Byte1]: 70
1645 11:54:43.989570
1646 11:54:43.989655 Set Vref, RX VrefLevel [Byte0]: 71
1647 11:54:43.992835 [Byte1]: 71
1648 11:54:43.997264
1649 11:54:43.997357 Set Vref, RX VrefLevel [Byte0]: 72
1650 11:54:44.000670 [Byte1]: 72
1651 11:54:44.004894
1652 11:54:44.005014 Set Vref, RX VrefLevel [Byte0]: 73
1653 11:54:44.008088 [Byte1]: 73
1654 11:54:44.012529
1655 11:54:44.012644 Set Vref, RX VrefLevel [Byte0]: 74
1656 11:54:44.016014 [Byte1]: 74
1657 11:54:44.020215
1658 11:54:44.020329 Set Vref, RX VrefLevel [Byte0]: 75
1659 11:54:44.023565 [Byte1]: 75
1660 11:54:44.027750
1661 11:54:44.027863 Final RX Vref Byte 0 = 60 to rank0
1662 11:54:44.031220 Final RX Vref Byte 1 = 57 to rank0
1663 11:54:44.034627 Final RX Vref Byte 0 = 60 to rank1
1664 11:54:44.037688 Final RX Vref Byte 1 = 57 to rank1==
1665 11:54:44.041120 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 11:54:44.047804 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1667 11:54:44.047944 ==
1668 11:54:44.048051 DQS Delay:
1669 11:54:44.048141 DQS0 = 0, DQS1 = 0
1670 11:54:44.051340 DQM Delay:
1671 11:54:44.051447 DQM0 = 79, DQM1 = 71
1672 11:54:44.054787 DQ Delay:
1673 11:54:44.057824 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1674 11:54:44.057935 DQ4 =76, DQ5 =92, DQ6 =88, DQ7 =76
1675 11:54:44.061190 DQ8 =56, DQ9 =60, DQ10 =72, DQ11 =64
1676 11:54:44.064719 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
1677 11:54:44.064830
1678 11:54:44.064924
1679 11:54:44.075440 [DQSOSCAuto] RK0, (LSB)MR18= 0x5151, (MSB)MR19= 0x606, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
1680 11:54:44.078683 CH1 RK0: MR19=606, MR18=5151
1681 11:54:44.082160 CH1_RK0: MR19=0x606, MR18=0x5151, DQSOSC=389, MR23=63, INC=97, DEC=65
1682 11:54:44.082277
1683 11:54:44.085348 ----->DramcWriteLeveling(PI) begin...
1684 11:54:44.088679 ==
1685 11:54:44.088788 Dram Type= 6, Freq= 0, CH_1, rank 1
1686 11:54:44.095415 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1687 11:54:44.095534 ==
1688 11:54:44.098690 Write leveling (Byte 0): 25 => 25
1689 11:54:44.101967 Write leveling (Byte 1): 25 => 25
1690 11:54:44.105316 DramcWriteLeveling(PI) end<-----
1691 11:54:44.105428
1692 11:54:44.105521 ==
1693 11:54:44.108758 Dram Type= 6, Freq= 0, CH_1, rank 1
1694 11:54:44.112146 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1695 11:54:44.112259 ==
1696 11:54:44.115407 [Gating] SW mode calibration
1697 11:54:44.121942 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1698 11:54:44.125535 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1699 11:54:44.132096 0 6 0 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1700 11:54:44.135445 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1701 11:54:44.138742 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1702 11:54:44.145328 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1703 11:54:44.148944 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1704 11:54:44.152018 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1705 11:54:44.158629 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1706 11:54:44.162248 0 6 28 | B1->B0 | 2424 3131 | 0 0 | (0 0) (0 0)
1707 11:54:44.165911 0 7 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1708 11:54:44.172253 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1709 11:54:44.175343 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1710 11:54:44.178707 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1711 11:54:44.182317 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1712 11:54:44.188808 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1713 11:54:44.192398 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1714 11:54:44.195592 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1715 11:54:44.202281 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1716 11:54:44.205568 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1717 11:54:44.209034 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1718 11:54:44.215646 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1719 11:54:44.219012 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1720 11:54:44.222310 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1721 11:54:44.228830 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1722 11:54:44.232210 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1723 11:54:44.235571 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1724 11:54:44.242292 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1725 11:54:44.245539 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1726 11:54:44.248792 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1727 11:54:44.255304 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1728 11:54:44.258668 0 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1729 11:54:44.261951 0 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1730 11:54:44.268870 0 9 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1731 11:54:44.272006 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1732 11:54:44.275586 Total UI for P1: 0, mck2ui 16
1733 11:54:44.278514 best dqsien dly found for B0: ( 0, 9, 28)
1734 11:54:44.282010 0 10 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1735 11:54:44.285316 Total UI for P1: 0, mck2ui 16
1736 11:54:44.288716 best dqsien dly found for B1: ( 0, 9, 30)
1737 11:54:44.292066 best DQS0 dly(MCK, UI, PI) = (0, 9, 28)
1738 11:54:44.295366 best DQS1 dly(MCK, UI, PI) = (0, 9, 30)
1739 11:54:44.295451
1740 11:54:44.298763 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 28)
1741 11:54:44.305283 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 30)
1742 11:54:44.305421 [Gating] SW calibration Done
1743 11:54:44.308766 ==
1744 11:54:44.308855 Dram Type= 6, Freq= 0, CH_1, rank 1
1745 11:54:44.315497 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1746 11:54:44.315595 ==
1747 11:54:44.315661 RX Vref Scan: 0
1748 11:54:44.315721
1749 11:54:44.318810 RX Vref 0 -> 0, step: 1
1750 11:54:44.318893
1751 11:54:44.321972 RX Delay -130 -> 252, step: 16
1752 11:54:44.325304 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1753 11:54:44.328868 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1754 11:54:44.332251 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1755 11:54:44.338584 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1756 11:54:44.341978 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1757 11:54:44.345418 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1758 11:54:44.348793 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1759 11:54:44.351977 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1760 11:54:44.358590 iDelay=222, Bit 8, Center 53 (-66 ~ 173) 240
1761 11:54:44.361974 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1762 11:54:44.365213 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1763 11:54:44.368579 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1764 11:54:44.372064 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1765 11:54:44.378674 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1766 11:54:44.381915 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1767 11:54:44.385298 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1768 11:54:44.385411 ==
1769 11:54:44.388431 Dram Type= 6, Freq= 0, CH_1, rank 1
1770 11:54:44.391830 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1771 11:54:44.391941 ==
1772 11:54:44.395190 DQS Delay:
1773 11:54:44.395299 DQS0 = 0, DQS1 = 0
1774 11:54:44.398437 DQM Delay:
1775 11:54:44.398545 DQM0 = 84, DQM1 = 74
1776 11:54:44.398640 DQ Delay:
1777 11:54:44.401943 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1778 11:54:44.405218 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1779 11:54:44.408428 DQ8 =53, DQ9 =61, DQ10 =77, DQ11 =61
1780 11:54:44.411823 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1781 11:54:44.411937
1782 11:54:44.412030
1783 11:54:44.415150 ==
1784 11:54:44.415257 Dram Type= 6, Freq= 0, CH_1, rank 1
1785 11:54:44.421834 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1786 11:54:44.421952 ==
1787 11:54:44.422046
1788 11:54:44.422136
1789 11:54:44.425385 TX Vref Scan disable
1790 11:54:44.425491 == TX Byte 0 ==
1791 11:54:44.428696 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1792 11:54:44.435341 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1793 11:54:44.435465 == TX Byte 1 ==
1794 11:54:44.438583 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1795 11:54:44.445165 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1796 11:54:44.445292 ==
1797 11:54:44.448692 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 11:54:44.451803 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1799 11:54:44.451912 ==
1800 11:54:44.464682 TX Vref=22, minBit 12, minWin=27, winSum=447
1801 11:54:44.468220 TX Vref=24, minBit 0, minWin=28, winSum=453
1802 11:54:44.471429 TX Vref=26, minBit 0, minWin=28, winSum=455
1803 11:54:44.474684 TX Vref=28, minBit 0, minWin=28, winSum=455
1804 11:54:44.478053 TX Vref=30, minBit 0, minWin=28, winSum=459
1805 11:54:44.481286 TX Vref=32, minBit 9, minWin=27, winSum=456
1806 11:54:44.488228 [TxChooseVref] Worse bit 0, Min win 28, Win sum 459, Final Vref 30
1807 11:54:44.488357
1808 11:54:44.491509 Final TX Range 1 Vref 30
1809 11:54:44.491616
1810 11:54:44.491707 ==
1811 11:54:44.494871 Dram Type= 6, Freq= 0, CH_1, rank 1
1812 11:54:44.498372 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1813 11:54:44.498482 ==
1814 11:54:44.498573
1815 11:54:44.498661
1816 11:54:44.501367 TX Vref Scan disable
1817 11:54:44.505035 == TX Byte 0 ==
1818 11:54:44.508210 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1819 11:54:44.511574 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1820 11:54:44.515055 == TX Byte 1 ==
1821 11:54:44.518422 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
1822 11:54:44.521544 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
1823 11:54:44.521655
1824 11:54:44.525032 [DATLAT]
1825 11:54:44.525138 Freq=800, CH1 RK1
1826 11:54:44.525229
1827 11:54:44.528243 DATLAT Default: 0x9
1828 11:54:44.528349 0, 0xFFFF, sum = 0
1829 11:54:44.531605 1, 0xFFFF, sum = 0
1830 11:54:44.531712 2, 0xFFFF, sum = 0
1831 11:54:44.535325 3, 0xFFFF, sum = 0
1832 11:54:44.535432 4, 0xFFFF, sum = 0
1833 11:54:44.538512 5, 0xFFFF, sum = 0
1834 11:54:44.538619 6, 0xFFFF, sum = 0
1835 11:54:44.541603 7, 0xFFFF, sum = 0
1836 11:54:44.541709 8, 0x0, sum = 1
1837 11:54:44.544913 9, 0x0, sum = 2
1838 11:54:44.545019 10, 0x0, sum = 3
1839 11:54:44.548361 11, 0x0, sum = 4
1840 11:54:44.548468 best_step = 9
1841 11:54:44.548594
1842 11:54:44.548680 ==
1843 11:54:44.551579 Dram Type= 6, Freq= 0, CH_1, rank 1
1844 11:54:44.555012 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1845 11:54:44.558289 ==
1846 11:54:44.558378 RX Vref Scan: 0
1847 11:54:44.558441
1848 11:54:44.561700 RX Vref 0 -> 0, step: 1
1849 11:54:44.561781
1850 11:54:44.565019 RX Delay -111 -> 252, step: 8
1851 11:54:44.568338 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1852 11:54:44.571637 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
1853 11:54:44.574963 iDelay=209, Bit 2, Center 72 (-47 ~ 192) 240
1854 11:54:44.581857 iDelay=209, Bit 3, Center 80 (-39 ~ 200) 240
1855 11:54:44.584892 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1856 11:54:44.588281 iDelay=209, Bit 5, Center 92 (-23 ~ 208) 232
1857 11:54:44.591669 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1858 11:54:44.595013 iDelay=209, Bit 7, Center 80 (-39 ~ 200) 240
1859 11:54:44.601487 iDelay=209, Bit 8, Center 56 (-63 ~ 176) 240
1860 11:54:44.604872 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1861 11:54:44.608271 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1862 11:54:44.611690 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1863 11:54:44.615026 iDelay=209, Bit 12, Center 84 (-39 ~ 208) 248
1864 11:54:44.621525 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
1865 11:54:44.624884 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1866 11:54:44.628153 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1867 11:54:44.628240 ==
1868 11:54:44.631711 Dram Type= 6, Freq= 0, CH_1, rank 1
1869 11:54:44.634843 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
1870 11:54:44.634937 ==
1871 11:54:44.638381 DQS Delay:
1872 11:54:44.638466 DQS0 = 0, DQS1 = 0
1873 11:54:44.641544 DQM Delay:
1874 11:54:44.641629 DQM0 = 81, DQM1 = 72
1875 11:54:44.641692 DQ Delay:
1876 11:54:44.644691 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =80
1877 11:54:44.648068 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =80
1878 11:54:44.651386 DQ8 =56, DQ9 =56, DQ10 =72, DQ11 =64
1879 11:54:44.654794 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =84
1880 11:54:44.654880
1881 11:54:44.654943
1882 11:54:44.664597 [DQSOSCAuto] RK1, (LSB)MR18= 0x3838, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
1883 11:54:44.668127 CH1 RK1: MR19=606, MR18=3838
1884 11:54:44.674691 CH1_RK1: MR19=0x606, MR18=0x3838, DQSOSC=395, MR23=63, INC=94, DEC=63
1885 11:54:44.674794 [RxdqsGatingPostProcess] freq 800
1886 11:54:44.681262 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1887 11:54:44.684690 Pre-setting of DQS Precalculation
1888 11:54:44.687870 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
1889 11:54:44.698049 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
1890 11:54:44.704935 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
1891 11:54:44.705079
1892 11:54:44.705164
1893 11:54:44.708255 [Calibration Summary] 1600 Mbps
1894 11:54:44.708341 CH 0, Rank 0
1895 11:54:44.711461 SW Impedance : PASS
1896 11:54:44.711545 DUTY Scan : NO K
1897 11:54:44.714815 ZQ Calibration : PASS
1898 11:54:44.718235 Jitter Meter : NO K
1899 11:54:44.718320 CBT Training : PASS
1900 11:54:44.721401 Write leveling : PASS
1901 11:54:44.724804 RX DQS gating : PASS
1902 11:54:44.724887 RX DQ/DQS(RDDQC) : PASS
1903 11:54:44.728078 TX DQ/DQS : PASS
1904 11:54:44.731506 RX DATLAT : PASS
1905 11:54:44.731590 RX DQ/DQS(Engine): PASS
1906 11:54:44.734713 TX OE : NO K
1907 11:54:44.734796 All Pass.
1908 11:54:44.734860
1909 11:54:44.738065 CH 0, Rank 1
1910 11:54:44.738148 SW Impedance : PASS
1911 11:54:44.741559 DUTY Scan : NO K
1912 11:54:44.741643 ZQ Calibration : PASS
1913 11:54:44.744803 Jitter Meter : NO K
1914 11:54:44.748204 CBT Training : PASS
1915 11:54:44.748288 Write leveling : PASS
1916 11:54:44.751254 RX DQS gating : PASS
1917 11:54:44.754931 RX DQ/DQS(RDDQC) : PASS
1918 11:54:44.755021 TX DQ/DQS : PASS
1919 11:54:44.758059 RX DATLAT : PASS
1920 11:54:44.761248 RX DQ/DQS(Engine): PASS
1921 11:54:44.761336 TX OE : NO K
1922 11:54:44.765196 All Pass.
1923 11:54:44.765283
1924 11:54:44.765349 CH 1, Rank 0
1925 11:54:44.768026 SW Impedance : PASS
1926 11:54:44.768108 DUTY Scan : NO K
1927 11:54:44.771262 ZQ Calibration : PASS
1928 11:54:44.774616 Jitter Meter : NO K
1929 11:54:44.774701 CBT Training : PASS
1930 11:54:44.778165 Write leveling : PASS
1931 11:54:44.781523 RX DQS gating : PASS
1932 11:54:44.781609 RX DQ/DQS(RDDQC) : PASS
1933 11:54:44.784706 TX DQ/DQS : PASS
1934 11:54:44.784790 RX DATLAT : PASS
1935 11:54:44.787850 RX DQ/DQS(Engine): PASS
1936 11:54:44.791413 TX OE : NO K
1937 11:54:44.791501 All Pass.
1938 11:54:44.791568
1939 11:54:44.791628 CH 1, Rank 1
1940 11:54:44.794748 SW Impedance : PASS
1941 11:54:44.798317 DUTY Scan : NO K
1942 11:54:44.798404 ZQ Calibration : PASS
1943 11:54:44.801424 Jitter Meter : NO K
1944 11:54:44.804674 CBT Training : PASS
1945 11:54:44.804762 Write leveling : PASS
1946 11:54:44.807982 RX DQS gating : PASS
1947 11:54:44.811329 RX DQ/DQS(RDDQC) : PASS
1948 11:54:44.811416 TX DQ/DQS : PASS
1949 11:54:44.814589 RX DATLAT : PASS
1950 11:54:44.817952 RX DQ/DQS(Engine): PASS
1951 11:54:44.818039 TX OE : NO K
1952 11:54:44.818105 All Pass.
1953 11:54:44.821339
1954 11:54:44.821424 DramC Write-DBI off
1955 11:54:44.824712 PER_BANK_REFRESH: Hybrid Mode
1956 11:54:44.824796 TX_TRACKING: ON
1957 11:54:44.827884 [GetDramInforAfterCalByMRR] Vendor 6.
1958 11:54:44.831215 [GetDramInforAfterCalByMRR] Revision 606.
1959 11:54:44.837804 [GetDramInforAfterCalByMRR] Revision 2 0.
1960 11:54:44.837906 MR0 0x3939
1961 11:54:44.837973 MR8 0x1111
1962 11:54:44.841155 RK0, DieNum 1, Density 16Gb, RKsize 16Gb.
1963 11:54:44.841240
1964 11:54:44.844640 MR0 0x3939
1965 11:54:44.844726 MR8 0x1111
1966 11:54:44.847823 RK1, DieNum 1, Density 16Gb, RKsize 16Gb.
1967 11:54:44.847909
1968 11:54:44.857772 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
1969 11:54:44.861141 [FAST_K] Save calibration result to emmc
1970 11:54:44.864423 [FAST_K] Save calibration result to emmc
1971 11:54:44.867852 dram_init: config_dvfs: 1
1972 11:54:44.871055 dramc_set_vcore_voltage set vcore to 662500
1973 11:54:44.874513 Read voltage for 1200, 2
1974 11:54:44.874604 Vio18 = 0
1975 11:54:44.874669 Vcore = 662500
1976 11:54:44.877833 Vdram = 0
1977 11:54:44.877918 Vddq = 0
1978 11:54:44.877984 Vmddr = 0
1979 11:54:44.884336 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
1980 11:54:44.887947 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
1981 11:54:44.891247 MEM_TYPE=3, freq_sel=15
1982 11:54:44.894460 sv_algorithm_assistance_LP4_1600
1983 11:54:44.897710 ============ PULL DRAM RESETB DOWN ============
1984 11:54:44.901092 ========== PULL DRAM RESETB DOWN end =========
1985 11:54:44.907606 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
1986 11:54:44.911023 ===================================
1987 11:54:44.911116 LPDDR4 DRAM CONFIGURATION
1988 11:54:44.914465 ===================================
1989 11:54:44.917980 EX_ROW_EN[0] = 0x0
1990 11:54:44.921175 EX_ROW_EN[1] = 0x0
1991 11:54:44.921264 LP4Y_EN = 0x0
1992 11:54:44.924554 WORK_FSP = 0x0
1993 11:54:44.924641 WL = 0x4
1994 11:54:44.927754 RL = 0x4
1995 11:54:44.927839 BL = 0x2
1996 11:54:44.931123 RPST = 0x0
1997 11:54:44.931207 RD_PRE = 0x0
1998 11:54:44.934572 WR_PRE = 0x1
1999 11:54:44.934656 WR_PST = 0x0
2000 11:54:44.937709 DBI_WR = 0x0
2001 11:54:44.937792 DBI_RD = 0x0
2002 11:54:44.941168 OTF = 0x1
2003 11:54:44.944713 ===================================
2004 11:54:44.947685 ===================================
2005 11:54:44.947772 ANA top config
2006 11:54:44.951186 ===================================
2007 11:54:44.954703 DLL_ASYNC_EN = 0
2008 11:54:44.957879 ALL_SLAVE_EN = 0
2009 11:54:44.957969 NEW_RANK_MODE = 1
2010 11:54:44.961411 DLL_IDLE_MODE = 1
2011 11:54:44.964447 LP45_APHY_COMB_EN = 1
2012 11:54:44.967894 TX_ODT_DIS = 1
2013 11:54:44.967981 NEW_8X_MODE = 1
2014 11:54:44.971073 ===================================
2015 11:54:44.974587 ===================================
2016 11:54:44.977878 data_rate = 2400
2017 11:54:44.981308 CKR = 1
2018 11:54:44.984634 DQ_P2S_RATIO = 8
2019 11:54:44.988305 ===================================
2020 11:54:44.991313 CA_P2S_RATIO = 8
2021 11:54:44.994669 DQ_CA_OPEN = 0
2022 11:54:44.994758 DQ_SEMI_OPEN = 0
2023 11:54:44.997929 CA_SEMI_OPEN = 0
2024 11:54:45.001441 CA_FULL_RATE = 0
2025 11:54:45.004610 DQ_CKDIV4_EN = 0
2026 11:54:45.008261 CA_CKDIV4_EN = 0
2027 11:54:45.011603 CA_PREDIV_EN = 0
2028 11:54:45.011694 PH8_DLY = 17
2029 11:54:45.014770 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2030 11:54:45.017990 DQ_AAMCK_DIV = 4
2031 11:54:45.021559 CA_AAMCK_DIV = 4
2032 11:54:45.025016 CA_ADMCK_DIV = 4
2033 11:54:45.025105 DQ_TRACK_CA_EN = 0
2034 11:54:45.028145 CA_PICK = 1200
2035 11:54:45.031587 CA_MCKIO = 1200
2036 11:54:45.034799 MCKIO_SEMI = 0
2037 11:54:45.038267 PLL_FREQ = 2366
2038 11:54:45.041701 DQ_UI_PI_RATIO = 32
2039 11:54:45.044767 CA_UI_PI_RATIO = 0
2040 11:54:45.048112 ===================================
2041 11:54:45.051445 ===================================
2042 11:54:45.051534 memory_type:LPDDR4
2043 11:54:45.054648 GP_NUM : 10
2044 11:54:45.058354 SRAM_EN : 1
2045 11:54:45.058443 MD32_EN : 0
2046 11:54:45.061616 ===================================
2047 11:54:45.064979 [ANA_INIT] >>>>>>>>>>>>>>
2048 11:54:45.067970 <<<<<< [CONFIGURE PHASE]: ANA_TX
2049 11:54:45.071434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2050 11:54:45.074670 ===================================
2051 11:54:45.077922 data_rate = 2400,PCW = 0X5b00
2052 11:54:45.081242 ===================================
2053 11:54:45.084614 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2054 11:54:45.088084 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2055 11:54:45.094679 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2056 11:54:45.097910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2057 11:54:45.101342 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2058 11:54:45.104667 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2059 11:54:45.108424 [ANA_INIT] flow start
2060 11:54:45.111333 [ANA_INIT] PLL >>>>>>>>
2061 11:54:45.111423 [ANA_INIT] PLL <<<<<<<<
2062 11:54:45.114715 [ANA_INIT] MIDPI >>>>>>>>
2063 11:54:45.118207 [ANA_INIT] MIDPI <<<<<<<<
2064 11:54:45.121490 [ANA_INIT] DLL >>>>>>>>
2065 11:54:45.121577 [ANA_INIT] DLL <<<<<<<<
2066 11:54:45.125009 [ANA_INIT] flow end
2067 11:54:45.127937 ============ LP4 DIFF to SE enter ============
2068 11:54:45.131336 ============ LP4 DIFF to SE exit ============
2069 11:54:45.134807 [ANA_INIT] <<<<<<<<<<<<<
2070 11:54:45.138300 [Flow] Enable top DCM control >>>>>
2071 11:54:45.141362 [Flow] Enable top DCM control <<<<<
2072 11:54:45.144744 Enable DLL master slave shuffle
2073 11:54:45.148042 ==============================================================
2074 11:54:45.151328 Gating Mode config
2075 11:54:45.157990 ==============================================================
2076 11:54:45.158108 Config description:
2077 11:54:45.168050 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2078 11:54:45.174679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2079 11:54:45.181391 SELPH_MODE 0: By rank 1: By Phase
2080 11:54:45.184621 ==============================================================
2081 11:54:45.187875 GAT_TRACK_EN = 1
2082 11:54:45.191419 RX_GATING_MODE = 2
2083 11:54:45.194547 RX_GATING_TRACK_MODE = 2
2084 11:54:45.197996 SELPH_MODE = 1
2085 11:54:45.201299 PICG_EARLY_EN = 1
2086 11:54:45.204634 VALID_LAT_VALUE = 1
2087 11:54:45.207870 ==============================================================
2088 11:54:45.211198 Enter into Gating configuration >>>>
2089 11:54:45.215001 Exit from Gating configuration <<<<
2090 11:54:45.217933 Enter into DVFS_PRE_config >>>>>
2091 11:54:45.231167 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2092 11:54:45.231314 Exit from DVFS_PRE_config <<<<<
2093 11:54:45.234615 Enter into PICG configuration >>>>
2094 11:54:45.237982 Exit from PICG configuration <<<<
2095 11:54:45.241258 [RX_INPUT] configuration >>>>>
2096 11:54:45.244811 [RX_INPUT] configuration <<<<<
2097 11:54:45.251270 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2098 11:54:45.254547 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2099 11:54:45.261201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2100 11:54:45.267793 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2101 11:54:45.274619 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2102 11:54:45.281043 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2103 11:54:45.284435 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2104 11:54:45.287957 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2105 11:54:45.291079 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2106 11:54:45.298125 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2107 11:54:45.301374 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2108 11:54:45.304296 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2109 11:54:45.307718 ===================================
2110 11:54:45.311015 LPDDR4 DRAM CONFIGURATION
2111 11:54:45.314427 ===================================
2112 11:54:45.314527 EX_ROW_EN[0] = 0x0
2113 11:54:45.317674 EX_ROW_EN[1] = 0x0
2114 11:54:45.321138 LP4Y_EN = 0x0
2115 11:54:45.321223 WORK_FSP = 0x0
2116 11:54:45.324467 WL = 0x4
2117 11:54:45.324591 RL = 0x4
2118 11:54:45.327771 BL = 0x2
2119 11:54:45.327854 RPST = 0x0
2120 11:54:45.330956 RD_PRE = 0x0
2121 11:54:45.331039 WR_PRE = 0x1
2122 11:54:45.334620 WR_PST = 0x0
2123 11:54:45.334703 DBI_WR = 0x0
2124 11:54:45.337720 DBI_RD = 0x0
2125 11:54:45.337802 OTF = 0x1
2126 11:54:45.341082 ===================================
2127 11:54:45.344348 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2128 11:54:45.351139 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2129 11:54:45.354479 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2130 11:54:45.357640 ===================================
2131 11:54:45.361101 LPDDR4 DRAM CONFIGURATION
2132 11:54:45.364334 ===================================
2133 11:54:45.364422 EX_ROW_EN[0] = 0x10
2134 11:54:45.367688 EX_ROW_EN[1] = 0x0
2135 11:54:45.367771 LP4Y_EN = 0x0
2136 11:54:45.371478 WORK_FSP = 0x0
2137 11:54:45.371562 WL = 0x4
2138 11:54:45.374590 RL = 0x4
2139 11:54:45.374672 BL = 0x2
2140 11:54:45.377811 RPST = 0x0
2141 11:54:45.380947 RD_PRE = 0x0
2142 11:54:45.381032 WR_PRE = 0x1
2143 11:54:45.384252 WR_PST = 0x0
2144 11:54:45.384335 DBI_WR = 0x0
2145 11:54:45.387713 DBI_RD = 0x0
2146 11:54:45.387796 OTF = 0x1
2147 11:54:45.390893 ===================================
2148 11:54:45.397731 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2149 11:54:45.397831 ==
2150 11:54:45.401095 Dram Type= 6, Freq= 0, CH_0, rank 0
2151 11:54:45.404416 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2152 11:54:45.404511 ==
2153 11:54:45.407967 [Duty_Offset_Calibration]
2154 11:54:45.408052 B0:0 B1:2 CA:1
2155 11:54:45.408117
2156 11:54:45.411132 [DutyScan_Calibration_Flow] k_type=0
2157 11:54:45.422044
2158 11:54:45.422176 ==CLK 0==
2159 11:54:45.425310 Final CLK duty delay cell = 0
2160 11:54:45.428957 [0] MAX Duty = 5093%(X100), DQS PI = 12
2161 11:54:45.432121 [0] MIN Duty = 4938%(X100), DQS PI = 52
2162 11:54:45.432207 [0] AVG Duty = 5015%(X100)
2163 11:54:45.435394
2164 11:54:45.435478 CH0 CLK Duty spec in!! Max-Min= 155%
2165 11:54:45.442328 [DutyScan_Calibration_Flow] ====Done====
2166 11:54:45.442433
2167 11:54:45.445298 [DutyScan_Calibration_Flow] k_type=1
2168 11:54:45.461407
2169 11:54:45.461551 ==DQS 0 ==
2170 11:54:45.464815 Final DQS duty delay cell = 0
2171 11:54:45.467988 [0] MAX Duty = 5125%(X100), DQS PI = 30
2172 11:54:45.471293 [0] MIN Duty = 5031%(X100), DQS PI = 4
2173 11:54:45.471378 [0] AVG Duty = 5078%(X100)
2174 11:54:45.474681
2175 11:54:45.474762 ==DQS 1 ==
2176 11:54:45.478017 Final DQS duty delay cell = 0
2177 11:54:45.481391 [0] MAX Duty = 5062%(X100), DQS PI = 58
2178 11:54:45.484823 [0] MIN Duty = 4906%(X100), DQS PI = 16
2179 11:54:45.484972 [0] AVG Duty = 4984%(X100)
2180 11:54:45.488063
2181 11:54:45.491516 CH0 DQS 0 Duty spec in!! Max-Min= 94%
2182 11:54:45.491599
2183 11:54:45.494678 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2184 11:54:45.498080 [DutyScan_Calibration_Flow] ====Done====
2185 11:54:45.498164
2186 11:54:45.501266 [DutyScan_Calibration_Flow] k_type=3
2187 11:54:45.518387
2188 11:54:45.518534 ==DQM 0 ==
2189 11:54:45.521701 Final DQM duty delay cell = 0
2190 11:54:45.525090 [0] MAX Duty = 5124%(X100), DQS PI = 20
2191 11:54:45.528266 [0] MIN Duty = 4969%(X100), DQS PI = 40
2192 11:54:45.531892 [0] AVG Duty = 5046%(X100)
2193 11:54:45.531981
2194 11:54:45.532045 ==DQM 1 ==
2195 11:54:45.535154 Final DQM duty delay cell = 4
2196 11:54:45.538400 [4] MAX Duty = 5187%(X100), DQS PI = 52
2197 11:54:45.541739 [4] MIN Duty = 5000%(X100), DQS PI = 18
2198 11:54:45.545222 [4] AVG Duty = 5093%(X100)
2199 11:54:45.545308
2200 11:54:45.548435 CH0 DQM 0 Duty spec in!! Max-Min= 155%
2201 11:54:45.548528
2202 11:54:45.551759 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2203 11:54:45.554907 [DutyScan_Calibration_Flow] ====Done====
2204 11:54:45.554994
2205 11:54:45.558336 [DutyScan_Calibration_Flow] k_type=2
2206 11:54:45.573534
2207 11:54:45.573677 ==DQ 0 ==
2208 11:54:45.576742 Final DQ duty delay cell = -4
2209 11:54:45.580061 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2210 11:54:45.583332 [-4] MIN Duty = 4813%(X100), DQS PI = 8
2211 11:54:45.586987 [-4] AVG Duty = 4937%(X100)
2212 11:54:45.587074
2213 11:54:45.587138 ==DQ 1 ==
2214 11:54:45.590105 Final DQ duty delay cell = -4
2215 11:54:45.593373 [-4] MAX Duty = 5062%(X100), DQS PI = 6
2216 11:54:45.596673 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2217 11:54:45.600327 [-4] AVG Duty = 4969%(X100)
2218 11:54:45.600423
2219 11:54:45.603428 CH0 DQ 0 Duty spec in!! Max-Min= 249%
2220 11:54:45.603512
2221 11:54:45.606529 CH0 DQ 1 Duty spec in!! Max-Min= 186%
2222 11:54:45.610009 [DutyScan_Calibration_Flow] ====Done====
2223 11:54:45.610097 ==
2224 11:54:45.613291 Dram Type= 6, Freq= 0, CH_1, rank 0
2225 11:54:45.616713 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2226 11:54:45.616800 ==
2227 11:54:45.619872 [Duty_Offset_Calibration]
2228 11:54:45.619955 B0:0 B1:5 CA:-5
2229 11:54:45.620019
2230 11:54:45.623103 [DutyScan_Calibration_Flow] k_type=0
2231 11:54:45.634113
2232 11:54:45.634235 ==CLK 0==
2233 11:54:45.637295 Final CLK duty delay cell = 0
2234 11:54:45.640493 [0] MAX Duty = 5125%(X100), DQS PI = 10
2235 11:54:45.643877 [0] MIN Duty = 4875%(X100), DQS PI = 46
2236 11:54:45.643964 [0] AVG Duty = 5000%(X100)
2237 11:54:45.647112
2238 11:54:45.650491 CH1 CLK Duty spec in!! Max-Min= 250%
2239 11:54:45.653864 [DutyScan_Calibration_Flow] ====Done====
2240 11:54:45.653961
2241 11:54:45.657256 [DutyScan_Calibration_Flow] k_type=1
2242 11:54:45.672400
2243 11:54:45.672571 ==DQS 0 ==
2244 11:54:45.675637 Final DQS duty delay cell = 0
2245 11:54:45.678990 [0] MAX Duty = 5125%(X100), DQS PI = 16
2246 11:54:45.682295 [0] MIN Duty = 4875%(X100), DQS PI = 40
2247 11:54:45.685745 [0] AVG Duty = 5000%(X100)
2248 11:54:45.685831
2249 11:54:45.685893 ==DQS 1 ==
2250 11:54:45.689017 Final DQS duty delay cell = -4
2251 11:54:45.692428 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2252 11:54:45.696054 [-4] MIN Duty = 4907%(X100), DQS PI = 56
2253 11:54:45.698914 [-4] AVG Duty = 4953%(X100)
2254 11:54:45.699016
2255 11:54:45.702433 CH1 DQS 0 Duty spec in!! Max-Min= 250%
2256 11:54:45.702523
2257 11:54:45.705630 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2258 11:54:45.708915 [DutyScan_Calibration_Flow] ====Done====
2259 11:54:45.709000
2260 11:54:45.712153 [DutyScan_Calibration_Flow] k_type=3
2261 11:54:45.727611
2262 11:54:45.727766 ==DQM 0 ==
2263 11:54:45.731004 Final DQM duty delay cell = -4
2264 11:54:45.734398 [-4] MAX Duty = 5094%(X100), DQS PI = 32
2265 11:54:45.737709 [-4] MIN Duty = 4844%(X100), DQS PI = 40
2266 11:54:45.741125 [-4] AVG Duty = 4969%(X100)
2267 11:54:45.741270
2268 11:54:45.741363 ==DQM 1 ==
2269 11:54:45.744627 Final DQM duty delay cell = -4
2270 11:54:45.747768 [-4] MAX Duty = 5062%(X100), DQS PI = 4
2271 11:54:45.751001 [-4] MIN Duty = 4906%(X100), DQS PI = 44
2272 11:54:45.754486 [-4] AVG Duty = 4984%(X100)
2273 11:54:45.754577
2274 11:54:45.757819 CH1 DQM 0 Duty spec in!! Max-Min= 250%
2275 11:54:45.757905
2276 11:54:45.760977 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2277 11:54:45.764448 [DutyScan_Calibration_Flow] ====Done====
2278 11:54:45.764540
2279 11:54:45.767600 [DutyScan_Calibration_Flow] k_type=2
2280 11:54:45.784907
2281 11:54:45.785053 ==DQ 0 ==
2282 11:54:45.788143 Final DQ duty delay cell = 0
2283 11:54:45.791325 [0] MAX Duty = 5062%(X100), DQS PI = 0
2284 11:54:45.794652 [0] MIN Duty = 4938%(X100), DQS PI = 44
2285 11:54:45.794741 [0] AVG Duty = 5000%(X100)
2286 11:54:45.794805
2287 11:54:45.797998 ==DQ 1 ==
2288 11:54:45.801339 Final DQ duty delay cell = 0
2289 11:54:45.804736 [0] MAX Duty = 5000%(X100), DQS PI = 6
2290 11:54:45.807972 [0] MIN Duty = 4875%(X100), DQS PI = 44
2291 11:54:45.808064 [0] AVG Duty = 4937%(X100)
2292 11:54:45.808129
2293 11:54:45.811224 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2294 11:54:45.811310
2295 11:54:45.817949 CH1 DQ 1 Duty spec in!! Max-Min= 125%
2296 11:54:45.821240 [DutyScan_Calibration_Flow] ====Done====
2297 11:54:45.824470 nWR fixed to 30
2298 11:54:45.824593 [ModeRegInit_LP4] CH0 RK0
2299 11:54:45.828015 [ModeRegInit_LP4] CH0 RK1
2300 11:54:45.831295 [ModeRegInit_LP4] CH1 RK0
2301 11:54:45.831378 [ModeRegInit_LP4] CH1 RK1
2302 11:54:45.834602 match AC timing 6
2303 11:54:45.838092 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 0
2304 11:54:45.841254 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2305 11:54:45.847703 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2306 11:54:45.851236 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2307 11:54:45.857893 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2308 11:54:45.858007 ==
2309 11:54:45.861112 Dram Type= 6, Freq= 0, CH_0, rank 0
2310 11:54:45.864479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2311 11:54:45.864574 ==
2312 11:54:45.871200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2313 11:54:45.874447 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2314 11:54:45.884474 [CA 0] Center 39 (9~70) winsize 62
2315 11:54:45.887837 [CA 1] Center 39 (8~70) winsize 63
2316 11:54:45.891258 [CA 2] Center 36 (5~67) winsize 63
2317 11:54:45.894620 [CA 3] Center 35 (4~66) winsize 63
2318 11:54:45.897705 [CA 4] Center 34 (3~65) winsize 63
2319 11:54:45.901157 [CA 5] Center 33 (3~64) winsize 62
2320 11:54:45.901251
2321 11:54:45.904397 [CmdBusTrainingLP45] Vref(ca) range 1: 39
2322 11:54:45.904483
2323 11:54:45.907723 [CATrainingPosCal] consider 1 rank data
2324 11:54:45.911259 u2DelayCellTimex100 = 270/100 ps
2325 11:54:45.914482 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2326 11:54:45.917626 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2327 11:54:45.924352 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2328 11:54:45.927676 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2329 11:54:45.931075 CA4 delay=34 (3~65),Diff = 1 PI (4 cell)
2330 11:54:45.934312 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2331 11:54:45.934398
2332 11:54:45.937706 CA PerBit enable=1, Macro0, CA PI delay=33
2333 11:54:45.937804
2334 11:54:45.941157 [CBTSetCACLKResult] CA Dly = 33
2335 11:54:45.941241 CS Dly: 7 (0~38)
2336 11:54:45.944344 ==
2337 11:54:45.944429 Dram Type= 6, Freq= 0, CH_0, rank 1
2338 11:54:45.951031 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2339 11:54:45.951132 ==
2340 11:54:45.954450 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2341 11:54:45.960908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2342 11:54:45.969909 [CA 0] Center 39 (8~70) winsize 63
2343 11:54:45.973291 [CA 1] Center 39 (8~70) winsize 63
2344 11:54:45.976433 [CA 2] Center 36 (5~67) winsize 63
2345 11:54:45.979796 [CA 3] Center 35 (4~66) winsize 63
2346 11:54:45.983235 [CA 4] Center 33 (3~64) winsize 62
2347 11:54:45.986524 [CA 5] Center 34 (3~65) winsize 63
2348 11:54:45.986611
2349 11:54:45.989876 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2350 11:54:45.989959
2351 11:54:45.993306 [CATrainingPosCal] consider 2 rank data
2352 11:54:45.996545 u2DelayCellTimex100 = 270/100 ps
2353 11:54:46.000025 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2354 11:54:46.003254 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2355 11:54:46.010017 CA2 delay=36 (5~67),Diff = 3 PI (14 cell)
2356 11:54:46.013165 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2357 11:54:46.016745 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2358 11:54:46.019977 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2359 11:54:46.020068
2360 11:54:46.023431 CA PerBit enable=1, Macro0, CA PI delay=33
2361 11:54:46.023516
2362 11:54:46.026693 [CBTSetCACLKResult] CA Dly = 33
2363 11:54:46.026778 CS Dly: 7 (0~39)
2364 11:54:46.026843
2365 11:54:46.030287 ----->DramcWriteLeveling(PI) begin...
2366 11:54:46.033348 ==
2367 11:54:46.033432 Dram Type= 6, Freq= 0, CH_0, rank 0
2368 11:54:46.040412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2369 11:54:46.040526 ==
2370 11:54:46.043502 Write leveling (Byte 0): 28 => 28
2371 11:54:46.046714 Write leveling (Byte 1): 26 => 26
2372 11:54:46.046801 DramcWriteLeveling(PI) end<-----
2373 11:54:46.050203
2374 11:54:46.050288 ==
2375 11:54:46.053320 Dram Type= 6, Freq= 0, CH_0, rank 0
2376 11:54:46.056668 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2377 11:54:46.056755 ==
2378 11:54:46.059970 [Gating] SW mode calibration
2379 11:54:46.066783 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2380 11:54:46.070332 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2381 11:54:46.076950 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2382 11:54:46.079962 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2383 11:54:46.083241 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2384 11:54:46.090121 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2385 11:54:46.093360 0 11 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2386 11:54:46.096721 0 11 20 | B1->B0 | 2d2d 2c2c | 1 1 | (1 0) (1 0)
2387 11:54:46.103347 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2388 11:54:46.106612 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2389 11:54:46.110015 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2390 11:54:46.116755 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2391 11:54:46.120057 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2392 11:54:46.123298 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2393 11:54:46.130087 0 12 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2394 11:54:46.133541 0 12 20 | B1->B0 | 3b3b 4444 | 1 0 | (0 0) (0 0)
2395 11:54:46.136892 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2396 11:54:46.143380 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2397 11:54:46.146675 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2398 11:54:46.150073 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2399 11:54:46.153386 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2400 11:54:46.159920 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2401 11:54:46.163158 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2402 11:54:46.166558 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2403 11:54:46.173612 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2404 11:54:46.176626 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2405 11:54:46.180126 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2406 11:54:46.186725 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2407 11:54:46.189766 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2408 11:54:46.193102 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2409 11:54:46.199942 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2410 11:54:46.203331 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2411 11:54:46.206714 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2412 11:54:46.213570 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2413 11:54:46.216640 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2414 11:54:46.220151 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2415 11:54:46.226734 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2416 11:54:46.230048 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2417 11:54:46.233210 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2418 11:54:46.239866 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2419 11:54:46.243386 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2420 11:54:46.246656 Total UI for P1: 0, mck2ui 16
2421 11:54:46.249733 best dqsien dly found for B0: ( 0, 15, 18)
2422 11:54:46.253350 Total UI for P1: 0, mck2ui 16
2423 11:54:46.256436 best dqsien dly found for B1: ( 0, 15, 20)
2424 11:54:46.259957 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2425 11:54:46.262979 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2426 11:54:46.263068
2427 11:54:46.266380 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2428 11:54:46.269675 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2429 11:54:46.272922 [Gating] SW calibration Done
2430 11:54:46.273009 ==
2431 11:54:46.276317 Dram Type= 6, Freq= 0, CH_0, rank 0
2432 11:54:46.279903 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2433 11:54:46.283100 ==
2434 11:54:46.283186 RX Vref Scan: 0
2435 11:54:46.283251
2436 11:54:46.286482 RX Vref 0 -> 0, step: 1
2437 11:54:46.286566
2438 11:54:46.286630 RX Delay -40 -> 252, step: 8
2439 11:54:46.293095 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2440 11:54:46.296411 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2441 11:54:46.300005 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2442 11:54:46.303182 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2443 11:54:46.306518 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2444 11:54:46.313039 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2445 11:54:46.316384 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2446 11:54:46.319624 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2447 11:54:46.322915 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2448 11:54:46.326405 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2449 11:54:46.332871 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2450 11:54:46.336060 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2451 11:54:46.339348 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2452 11:54:46.342651 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2453 11:54:46.346147 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2454 11:54:46.353036 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2455 11:54:46.353135 ==
2456 11:54:46.356126 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 11:54:46.359389 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2458 11:54:46.359480 ==
2459 11:54:46.359546 DQS Delay:
2460 11:54:46.362651 DQS0 = 0, DQS1 = 0
2461 11:54:46.362733 DQM Delay:
2462 11:54:46.366055 DQM0 = 115, DQM1 = 105
2463 11:54:46.366140 DQ Delay:
2464 11:54:46.369433 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2465 11:54:46.372777 DQ4 =123, DQ5 =103, DQ6 =123, DQ7 =123
2466 11:54:46.376110 DQ8 =95, DQ9 =91, DQ10 =103, DQ11 =99
2467 11:54:46.379408 DQ12 =111, DQ13 =115, DQ14 =115, DQ15 =115
2468 11:54:46.379495
2469 11:54:46.379560
2470 11:54:46.382707 ==
2471 11:54:46.386182 Dram Type= 6, Freq= 0, CH_0, rank 0
2472 11:54:46.389627 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2473 11:54:46.389714 ==
2474 11:54:46.389779
2475 11:54:46.389838
2476 11:54:46.392625 TX Vref Scan disable
2477 11:54:46.392707 == TX Byte 0 ==
2478 11:54:46.396267 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2479 11:54:46.402698 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2480 11:54:46.402805 == TX Byte 1 ==
2481 11:54:46.406024 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2482 11:54:46.412628 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2483 11:54:46.412733 ==
2484 11:54:46.416070 Dram Type= 6, Freq= 0, CH_0, rank 0
2485 11:54:46.419326 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2486 11:54:46.419416 ==
2487 11:54:46.431570 TX Vref=22, minBit 9, minWin=25, winSum=415
2488 11:54:46.434632 TX Vref=24, minBit 10, minWin=25, winSum=425
2489 11:54:46.438125 TX Vref=26, minBit 8, minWin=25, winSum=428
2490 11:54:46.441519 TX Vref=28, minBit 9, minWin=25, winSum=431
2491 11:54:46.444493 TX Vref=30, minBit 8, minWin=25, winSum=432
2492 11:54:46.447906 TX Vref=32, minBit 8, minWin=26, winSum=433
2493 11:54:46.454717 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2494 11:54:46.454827
2495 11:54:46.458426 Final TX Range 1 Vref 32
2496 11:54:46.458515
2497 11:54:46.458581 ==
2498 11:54:46.461335 Dram Type= 6, Freq= 0, CH_0, rank 0
2499 11:54:46.464736 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2500 11:54:46.464823 ==
2501 11:54:46.464887
2502 11:54:46.468129
2503 11:54:46.468212 TX Vref Scan disable
2504 11:54:46.471273 == TX Byte 0 ==
2505 11:54:46.474734 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2506 11:54:46.477905 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2507 11:54:46.481531 == TX Byte 1 ==
2508 11:54:46.484791 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
2509 11:54:46.488244 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
2510 11:54:46.488329
2511 11:54:46.491455 [DATLAT]
2512 11:54:46.491537 Freq=1200, CH0 RK0
2513 11:54:46.491602
2514 11:54:46.494558 DATLAT Default: 0xd
2515 11:54:46.494640 0, 0xFFFF, sum = 0
2516 11:54:46.497939 1, 0xFFFF, sum = 0
2517 11:54:46.498022 2, 0xFFFF, sum = 0
2518 11:54:46.501084 3, 0xFFFF, sum = 0
2519 11:54:46.501177 4, 0xFFFF, sum = 0
2520 11:54:46.504439 5, 0xFFFF, sum = 0
2521 11:54:46.507721 6, 0xFFFF, sum = 0
2522 11:54:46.507808 7, 0xFFFF, sum = 0
2523 11:54:46.511060 8, 0xFFFF, sum = 0
2524 11:54:46.511147 9, 0xFFFF, sum = 0
2525 11:54:46.514518 10, 0xFFFF, sum = 0
2526 11:54:46.514604 11, 0x0, sum = 1
2527 11:54:46.517764 12, 0x0, sum = 2
2528 11:54:46.517851 13, 0x0, sum = 3
2529 11:54:46.517916 14, 0x0, sum = 4
2530 11:54:46.521082 best_step = 12
2531 11:54:46.521165
2532 11:54:46.521229 ==
2533 11:54:46.524380 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 11:54:46.527585 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2535 11:54:46.527670 ==
2536 11:54:46.531043 RX Vref Scan: 1
2537 11:54:46.531128
2538 11:54:46.534513 Set Vref Range= 32 -> 127
2539 11:54:46.534627
2540 11:54:46.534710 RX Vref 32 -> 127, step: 1
2541 11:54:46.534771
2542 11:54:46.537533 RX Delay -21 -> 252, step: 4
2543 11:54:46.537615
2544 11:54:46.541066 Set Vref, RX VrefLevel [Byte0]: 32
2545 11:54:46.544234 [Byte1]: 32
2546 11:54:46.548051
2547 11:54:46.548140 Set Vref, RX VrefLevel [Byte0]: 33
2548 11:54:46.551334 [Byte1]: 33
2549 11:54:46.555833
2550 11:54:46.555923 Set Vref, RX VrefLevel [Byte0]: 34
2551 11:54:46.559117 [Byte1]: 34
2552 11:54:46.563852
2553 11:54:46.563941 Set Vref, RX VrefLevel [Byte0]: 35
2554 11:54:46.566902 [Byte1]: 35
2555 11:54:46.572357
2556 11:54:46.572477 Set Vref, RX VrefLevel [Byte0]: 36
2557 11:54:46.574808 [Byte1]: 36
2558 11:54:46.579734
2559 11:54:46.579824 Set Vref, RX VrefLevel [Byte0]: 37
2560 11:54:46.582948 [Byte1]: 37
2561 11:54:46.587450
2562 11:54:46.587537 Set Vref, RX VrefLevel [Byte0]: 38
2563 11:54:46.590821 [Byte1]: 38
2564 11:54:46.595413
2565 11:54:46.595501 Set Vref, RX VrefLevel [Byte0]: 39
2566 11:54:46.598628 [Byte1]: 39
2567 11:54:46.603253
2568 11:54:46.603348 Set Vref, RX VrefLevel [Byte0]: 40
2569 11:54:46.606500 [Byte1]: 40
2570 11:54:46.611546
2571 11:54:46.611641 Set Vref, RX VrefLevel [Byte0]: 41
2572 11:54:46.614435 [Byte1]: 41
2573 11:54:46.619239
2574 11:54:46.619331 Set Vref, RX VrefLevel [Byte0]: 42
2575 11:54:46.622753 [Byte1]: 42
2576 11:54:46.627009
2577 11:54:46.627097 Set Vref, RX VrefLevel [Byte0]: 43
2578 11:54:46.630362 [Byte1]: 43
2579 11:54:46.634871
2580 11:54:46.634961 Set Vref, RX VrefLevel [Byte0]: 44
2581 11:54:46.638135 [Byte1]: 44
2582 11:54:46.642862
2583 11:54:46.642952 Set Vref, RX VrefLevel [Byte0]: 45
2584 11:54:46.646326 [Byte1]: 45
2585 11:54:46.650718
2586 11:54:46.650805 Set Vref, RX VrefLevel [Byte0]: 46
2587 11:54:46.654203 [Byte1]: 46
2588 11:54:46.658933
2589 11:54:46.659080 Set Vref, RX VrefLevel [Byte0]: 47
2590 11:54:46.662330 [Byte1]: 47
2591 11:54:46.666780
2592 11:54:46.666875 Set Vref, RX VrefLevel [Byte0]: 48
2593 11:54:46.669919 [Byte1]: 48
2594 11:54:46.674762
2595 11:54:46.674852 Set Vref, RX VrefLevel [Byte0]: 49
2596 11:54:46.677874 [Byte1]: 49
2597 11:54:46.682428
2598 11:54:46.682518 Set Vref, RX VrefLevel [Byte0]: 50
2599 11:54:46.685933 [Byte1]: 50
2600 11:54:46.690466
2601 11:54:46.690553 Set Vref, RX VrefLevel [Byte0]: 51
2602 11:54:46.693856 [Byte1]: 51
2603 11:54:46.698359
2604 11:54:46.698442 Set Vref, RX VrefLevel [Byte0]: 52
2605 11:54:46.701717 [Byte1]: 52
2606 11:54:46.706250
2607 11:54:46.706333 Set Vref, RX VrefLevel [Byte0]: 53
2608 11:54:46.709816 [Byte1]: 53
2609 11:54:46.714176
2610 11:54:46.714264 Set Vref, RX VrefLevel [Byte0]: 54
2611 11:54:46.717453 [Byte1]: 54
2612 11:54:46.722005
2613 11:54:46.722094 Set Vref, RX VrefLevel [Byte0]: 55
2614 11:54:46.725473 [Byte1]: 55
2615 11:54:46.730080
2616 11:54:46.730167 Set Vref, RX VrefLevel [Byte0]: 56
2617 11:54:46.733324 [Byte1]: 56
2618 11:54:46.738008
2619 11:54:46.738097 Set Vref, RX VrefLevel [Byte0]: 57
2620 11:54:46.741235 [Byte1]: 57
2621 11:54:46.745978
2622 11:54:46.746064 Set Vref, RX VrefLevel [Byte0]: 58
2623 11:54:46.749118 [Byte1]: 58
2624 11:54:46.753850
2625 11:54:46.753937 Set Vref, RX VrefLevel [Byte0]: 59
2626 11:54:46.757183 [Byte1]: 59
2627 11:54:46.761636
2628 11:54:46.761724 Set Vref, RX VrefLevel [Byte0]: 60
2629 11:54:46.765157 [Byte1]: 60
2630 11:54:46.769542
2631 11:54:46.769629 Set Vref, RX VrefLevel [Byte0]: 61
2632 11:54:46.773186 [Byte1]: 61
2633 11:54:46.777712
2634 11:54:46.777801 Set Vref, RX VrefLevel [Byte0]: 62
2635 11:54:46.780878 [Byte1]: 62
2636 11:54:46.785547
2637 11:54:46.785633 Set Vref, RX VrefLevel [Byte0]: 63
2638 11:54:46.788814 [Byte1]: 63
2639 11:54:46.793525
2640 11:54:46.793614 Set Vref, RX VrefLevel [Byte0]: 64
2641 11:54:46.796663 [Byte1]: 64
2642 11:54:46.801277
2643 11:54:46.801363 Set Vref, RX VrefLevel [Byte0]: 65
2644 11:54:46.804837 [Byte1]: 65
2645 11:54:46.809349
2646 11:54:46.809445 Set Vref, RX VrefLevel [Byte0]: 66
2647 11:54:46.812518 [Byte1]: 66
2648 11:54:46.817086
2649 11:54:46.817173 Set Vref, RX VrefLevel [Byte0]: 67
2650 11:54:46.820412 [Byte1]: 67
2651 11:54:46.825179
2652 11:54:46.828381 Final RX Vref Byte 0 = 47 to rank0
2653 11:54:46.828493 Final RX Vref Byte 1 = 47 to rank0
2654 11:54:46.831438 Final RX Vref Byte 0 = 47 to rank1
2655 11:54:46.835093 Final RX Vref Byte 1 = 47 to rank1==
2656 11:54:46.838256 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 11:54:46.844914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2658 11:54:46.845031 ==
2659 11:54:46.845110 DQS Delay:
2660 11:54:46.848148 DQS0 = 0, DQS1 = 0
2661 11:54:46.848230 DQM Delay:
2662 11:54:46.848293 DQM0 = 114, DQM1 = 105
2663 11:54:46.851653 DQ Delay:
2664 11:54:46.855177 DQ0 =110, DQ1 =114, DQ2 =112, DQ3 =108
2665 11:54:46.858431 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =120
2666 11:54:46.861553 DQ8 =94, DQ9 =86, DQ10 =106, DQ11 =96
2667 11:54:46.864935 DQ12 =114, DQ13 =112, DQ14 =118, DQ15 =114
2668 11:54:46.865022
2669 11:54:46.865086
2670 11:54:46.871539 [DQSOSCAuto] RK0, (LSB)MR18= 0x606, (MSB)MR19= 0x404, tDQSOscB0 = 407 ps tDQSOscB1 = 407 ps
2671 11:54:46.875033 CH0 RK0: MR19=404, MR18=606
2672 11:54:46.881393 CH0_RK0: MR19=0x404, MR18=0x606, DQSOSC=407, MR23=63, INC=39, DEC=26
2673 11:54:46.881500
2674 11:54:46.884764 ----->DramcWriteLeveling(PI) begin...
2675 11:54:46.884849 ==
2676 11:54:46.888314 Dram Type= 6, Freq= 0, CH_0, rank 1
2677 11:54:46.891776 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2678 11:54:46.894735 ==
2679 11:54:46.894820 Write leveling (Byte 0): 27 => 27
2680 11:54:46.898181 Write leveling (Byte 1): 23 => 23
2681 11:54:46.901390 DramcWriteLeveling(PI) end<-----
2682 11:54:46.901475
2683 11:54:46.901540 ==
2684 11:54:46.904772 Dram Type= 6, Freq= 0, CH_0, rank 1
2685 11:54:46.911357 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2686 11:54:46.911468 ==
2687 11:54:46.911536 [Gating] SW mode calibration
2688 11:54:46.921440 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2689 11:54:46.924972 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2690 11:54:46.928274 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2691 11:54:46.934722 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2692 11:54:46.938211 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2693 11:54:46.941303 0 11 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2694 11:54:46.948256 0 11 16 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
2695 11:54:46.951415 0 11 20 | B1->B0 | 2e2e 2626 | 0 0 | (1 0) (0 0)
2696 11:54:46.954917 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2697 11:54:46.961487 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2698 11:54:46.964635 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2699 11:54:46.967990 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2700 11:54:46.974883 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2701 11:54:46.978421 0 12 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2702 11:54:46.981543 0 12 16 | B1->B0 | 2424 2e2e | 0 1 | (0 0) (0 0)
2703 11:54:46.988246 0 12 20 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
2704 11:54:46.991371 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2705 11:54:46.994680 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2706 11:54:47.001595 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2707 11:54:47.004824 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2708 11:54:47.008325 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2709 11:54:47.011506 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2710 11:54:47.018617 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2711 11:54:47.021507 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2712 11:54:47.025147 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2713 11:54:47.031760 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2714 11:54:47.034959 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2715 11:54:47.038323 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2716 11:54:47.045045 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2717 11:54:47.048387 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2718 11:54:47.051744 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2719 11:54:47.058209 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2720 11:54:47.061728 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2721 11:54:47.064876 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2722 11:54:47.071424 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2723 11:54:47.074837 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2724 11:54:47.078240 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2725 11:54:47.085124 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2726 11:54:47.087985 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2727 11:54:47.091439 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2728 11:54:47.098300 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2729 11:54:47.098409 Total UI for P1: 0, mck2ui 16
2730 11:54:47.101479 best dqsien dly found for B0: ( 0, 15, 18)
2731 11:54:47.104778 Total UI for P1: 0, mck2ui 16
2732 11:54:47.108173 best dqsien dly found for B1: ( 0, 15, 20)
2733 11:54:47.111414 best DQS0 dly(MCK, UI, PI) = (0, 15, 18)
2734 11:54:47.118083 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
2735 11:54:47.118190
2736 11:54:47.121354 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 18)
2737 11:54:47.124722 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
2738 11:54:47.128000 [Gating] SW calibration Done
2739 11:54:47.128088 ==
2740 11:54:47.131488 Dram Type= 6, Freq= 0, CH_0, rank 1
2741 11:54:47.134710 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2742 11:54:47.134796 ==
2743 11:54:47.137939 RX Vref Scan: 0
2744 11:54:47.138023
2745 11:54:47.138087 RX Vref 0 -> 0, step: 1
2746 11:54:47.138147
2747 11:54:47.141450 RX Delay -40 -> 252, step: 8
2748 11:54:47.144543 iDelay=200, Bit 0, Center 107 (32 ~ 183) 152
2749 11:54:47.151251 iDelay=200, Bit 1, Center 119 (40 ~ 199) 160
2750 11:54:47.154589 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2751 11:54:47.157914 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2752 11:54:47.161342 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2753 11:54:47.164635 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2754 11:54:47.167998 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2755 11:54:47.174672 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2756 11:54:47.178075 iDelay=200, Bit 8, Center 91 (24 ~ 159) 136
2757 11:54:47.181475 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2758 11:54:47.184489 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2759 11:54:47.188416 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2760 11:54:47.194706 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2761 11:54:47.198072 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2762 11:54:47.201314 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2763 11:54:47.204677 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2764 11:54:47.204769 ==
2765 11:54:47.207942 Dram Type= 6, Freq= 0, CH_0, rank 1
2766 11:54:47.214807 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2767 11:54:47.214906 ==
2768 11:54:47.214973 DQS Delay:
2769 11:54:47.215032 DQS0 = 0, DQS1 = 0
2770 11:54:47.218040 DQM Delay:
2771 11:54:47.218123 DQM0 = 115, DQM1 = 107
2772 11:54:47.221178 DQ Delay:
2773 11:54:47.224749 DQ0 =107, DQ1 =119, DQ2 =115, DQ3 =111
2774 11:54:47.227957 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2775 11:54:47.231196 DQ8 =91, DQ9 =91, DQ10 =111, DQ11 =99
2776 11:54:47.234732 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2777 11:54:47.234819
2778 11:54:47.234884
2779 11:54:47.234942 ==
2780 11:54:47.237868 Dram Type= 6, Freq= 0, CH_0, rank 1
2781 11:54:47.241200 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2782 11:54:47.241283 ==
2783 11:54:47.241347
2784 11:54:47.244906
2785 11:54:47.244990 TX Vref Scan disable
2786 11:54:47.247970 == TX Byte 0 ==
2787 11:54:47.251291 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2788 11:54:47.254791 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2789 11:54:47.258051 == TX Byte 1 ==
2790 11:54:47.261352 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2791 11:54:47.264652 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2792 11:54:47.264743 ==
2793 11:54:47.268256 Dram Type= 6, Freq= 0, CH_0, rank 1
2794 11:54:47.271569 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2795 11:54:47.274786 ==
2796 11:54:47.285273 TX Vref=22, minBit 8, minWin=24, winSum=416
2797 11:54:47.288620 TX Vref=24, minBit 8, minWin=25, winSum=421
2798 11:54:47.291848 TX Vref=26, minBit 8, minWin=25, winSum=426
2799 11:54:47.295358 TX Vref=28, minBit 8, minWin=25, winSum=429
2800 11:54:47.298493 TX Vref=30, minBit 8, minWin=25, winSum=432
2801 11:54:47.301758 TX Vref=32, minBit 8, minWin=25, winSum=429
2802 11:54:47.308564 [TxChooseVref] Worse bit 8, Min win 25, Win sum 432, Final Vref 30
2803 11:54:47.308685
2804 11:54:47.311985 Final TX Range 1 Vref 30
2805 11:54:47.312076
2806 11:54:47.312140 ==
2807 11:54:47.315119 Dram Type= 6, Freq= 0, CH_0, rank 1
2808 11:54:47.318724 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2809 11:54:47.318814 ==
2810 11:54:47.318881
2811 11:54:47.321790
2812 11:54:47.321872 TX Vref Scan disable
2813 11:54:47.325125 == TX Byte 0 ==
2814 11:54:47.328583 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2815 11:54:47.331765 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2816 11:54:47.335087 == TX Byte 1 ==
2817 11:54:47.338437 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
2818 11:54:47.341825 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
2819 11:54:47.341913
2820 11:54:47.345182 [DATLAT]
2821 11:54:47.345267 Freq=1200, CH0 RK1
2822 11:54:47.345333
2823 11:54:47.348624 DATLAT Default: 0xc
2824 11:54:47.348708 0, 0xFFFF, sum = 0
2825 11:54:47.351872 1, 0xFFFF, sum = 0
2826 11:54:47.351957 2, 0xFFFF, sum = 0
2827 11:54:47.355306 3, 0xFFFF, sum = 0
2828 11:54:47.355394 4, 0xFFFF, sum = 0
2829 11:54:47.358394 5, 0xFFFF, sum = 0
2830 11:54:47.358481 6, 0xFFFF, sum = 0
2831 11:54:47.361855 7, 0xFFFF, sum = 0
2832 11:54:47.361941 8, 0xFFFF, sum = 0
2833 11:54:47.365050 9, 0xFFFF, sum = 0
2834 11:54:47.368464 10, 0xFFFF, sum = 0
2835 11:54:47.368562 11, 0x0, sum = 1
2836 11:54:47.368630 12, 0x0, sum = 2
2837 11:54:47.372153 13, 0x0, sum = 3
2838 11:54:47.372237 14, 0x0, sum = 4
2839 11:54:47.375095 best_step = 12
2840 11:54:47.375177
2841 11:54:47.375242 ==
2842 11:54:47.378672 Dram Type= 6, Freq= 0, CH_0, rank 1
2843 11:54:47.382034 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2844 11:54:47.382121 ==
2845 11:54:47.385259 RX Vref Scan: 0
2846 11:54:47.385343
2847 11:54:47.385407 RX Vref 0 -> 0, step: 1
2848 11:54:47.385467
2849 11:54:47.388484 RX Delay -21 -> 252, step: 4
2850 11:54:47.395427 iDelay=199, Bit 0, Center 110 (39 ~ 182) 144
2851 11:54:47.398760 iDelay=199, Bit 1, Center 116 (43 ~ 190) 148
2852 11:54:47.402091 iDelay=199, Bit 2, Center 114 (43 ~ 186) 144
2853 11:54:47.405311 iDelay=199, Bit 3, Center 108 (39 ~ 178) 140
2854 11:54:47.408750 iDelay=199, Bit 4, Center 118 (47 ~ 190) 144
2855 11:54:47.415513 iDelay=199, Bit 5, Center 108 (39 ~ 178) 140
2856 11:54:47.418748 iDelay=199, Bit 6, Center 124 (55 ~ 194) 140
2857 11:54:47.422112 iDelay=199, Bit 7, Center 124 (51 ~ 198) 148
2858 11:54:47.425377 iDelay=199, Bit 8, Center 94 (31 ~ 158) 128
2859 11:54:47.428676 iDelay=199, Bit 9, Center 90 (27 ~ 154) 128
2860 11:54:47.435264 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
2861 11:54:47.438573 iDelay=199, Bit 11, Center 96 (35 ~ 158) 124
2862 11:54:47.442166 iDelay=199, Bit 12, Center 114 (51 ~ 178) 128
2863 11:54:47.445257 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
2864 11:54:47.448743 iDelay=199, Bit 14, Center 116 (51 ~ 182) 132
2865 11:54:47.455167 iDelay=199, Bit 15, Center 114 (51 ~ 178) 128
2866 11:54:47.455271 ==
2867 11:54:47.458562 Dram Type= 6, Freq= 0, CH_0, rank 1
2868 11:54:47.461721 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2869 11:54:47.461813 ==
2870 11:54:47.461878 DQS Delay:
2871 11:54:47.465221 DQS0 = 0, DQS1 = 0
2872 11:54:47.465306 DQM Delay:
2873 11:54:47.468720 DQM0 = 115, DQM1 = 105
2874 11:54:47.468804 DQ Delay:
2875 11:54:47.471856 DQ0 =110, DQ1 =116, DQ2 =114, DQ3 =108
2876 11:54:47.475265 DQ4 =118, DQ5 =108, DQ6 =124, DQ7 =124
2877 11:54:47.478491 DQ8 =94, DQ9 =90, DQ10 =110, DQ11 =96
2878 11:54:47.481649 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =114
2879 11:54:47.481738
2880 11:54:47.481804
2881 11:54:47.491777 [DQSOSCAuto] RK1, (LSB)MR18= 0xf0f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 404 ps
2882 11:54:47.495273 CH0 RK1: MR19=404, MR18=F0F
2883 11:54:47.498583 CH0_RK1: MR19=0x404, MR18=0xF0F, DQSOSC=404, MR23=63, INC=40, DEC=26
2884 11:54:47.501890 [RxdqsGatingPostProcess] freq 1200
2885 11:54:47.508502 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2886 11:54:47.511814 Pre-setting of DQS Precalculation
2887 11:54:47.515380 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
2888 11:54:47.515478 ==
2889 11:54:47.518377 Dram Type= 6, Freq= 0, CH_1, rank 0
2890 11:54:47.525106 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2891 11:54:47.525213 ==
2892 11:54:47.528427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2893 11:54:47.534989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2894 11:54:47.543957 [CA 0] Center 37 (7~68) winsize 62
2895 11:54:47.547083 [CA 1] Center 37 (7~68) winsize 62
2896 11:54:47.550317 [CA 2] Center 34 (4~65) winsize 62
2897 11:54:47.553958 [CA 3] Center 33 (3~64) winsize 62
2898 11:54:47.557169 [CA 4] Center 32 (2~63) winsize 62
2899 11:54:47.560410 [CA 5] Center 32 (2~63) winsize 62
2900 11:54:47.560500
2901 11:54:47.563613 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2902 11:54:47.563699
2903 11:54:47.567300 [CATrainingPosCal] consider 1 rank data
2904 11:54:47.570464 u2DelayCellTimex100 = 270/100 ps
2905 11:54:47.573739 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2906 11:54:47.577105 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2907 11:54:47.583681 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2908 11:54:47.587091 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2909 11:54:47.590524 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2910 11:54:47.593832 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2911 11:54:47.593917
2912 11:54:47.597306 CA PerBit enable=1, Macro0, CA PI delay=32
2913 11:54:47.597390
2914 11:54:47.600671 [CBTSetCACLKResult] CA Dly = 32
2915 11:54:47.600755 CS Dly: 6 (0~37)
2916 11:54:47.600824 ==
2917 11:54:47.603921 Dram Type= 6, Freq= 0, CH_1, rank 1
2918 11:54:47.610382 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2919 11:54:47.610487 ==
2920 11:54:47.613749 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2921 11:54:47.620428 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2922 11:54:47.628949 [CA 0] Center 37 (7~68) winsize 62
2923 11:54:47.632370 [CA 1] Center 37 (6~68) winsize 63
2924 11:54:47.635681 [CA 2] Center 34 (3~65) winsize 63
2925 11:54:47.639021 [CA 3] Center 33 (3~64) winsize 62
2926 11:54:47.642312 [CA 4] Center 32 (2~63) winsize 62
2927 11:54:47.645650 [CA 5] Center 32 (2~62) winsize 61
2928 11:54:47.645738
2929 11:54:47.649162 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2930 11:54:47.649247
2931 11:54:47.652429 [CATrainingPosCal] consider 2 rank data
2932 11:54:47.655791 u2DelayCellTimex100 = 270/100 ps
2933 11:54:47.658892 CA0 delay=37 (7~68),Diff = 5 PI (24 cell)
2934 11:54:47.662366 CA1 delay=37 (7~68),Diff = 5 PI (24 cell)
2935 11:54:47.669057 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2936 11:54:47.672491 CA3 delay=33 (3~64),Diff = 1 PI (4 cell)
2937 11:54:47.675754 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
2938 11:54:47.679300 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
2939 11:54:47.679415
2940 11:54:47.682553 CA PerBit enable=1, Macro0, CA PI delay=32
2941 11:54:47.682648
2942 11:54:47.685870 [CBTSetCACLKResult] CA Dly = 32
2943 11:54:47.685955 CS Dly: 6 (0~38)
2944 11:54:47.686019
2945 11:54:47.689125 ----->DramcWriteLeveling(PI) begin...
2946 11:54:47.689254 ==
2947 11:54:47.692432 Dram Type= 6, Freq= 0, CH_1, rank 0
2948 11:54:47.699349 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2949 11:54:47.699446 ==
2950 11:54:47.702474 Write leveling (Byte 0): 21 => 21
2951 11:54:47.706075 Write leveling (Byte 1): 23 => 23
2952 11:54:47.706168 DramcWriteLeveling(PI) end<-----
2953 11:54:47.709235
2954 11:54:47.709318 ==
2955 11:54:47.712696 Dram Type= 6, Freq= 0, CH_1, rank 0
2956 11:54:47.715893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
2957 11:54:47.716020 ==
2958 11:54:47.719248 [Gating] SW mode calibration
2959 11:54:47.725865 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2960 11:54:47.729238 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
2961 11:54:47.735814 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2962 11:54:47.739260 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2963 11:54:47.742472 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2964 11:54:47.749366 0 11 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2965 11:54:47.752785 0 11 16 | B1->B0 | 3232 2929 | 0 1 | (0 0) (1 0)
2966 11:54:47.755833 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2967 11:54:47.762546 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2968 11:54:47.765939 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2969 11:54:47.769304 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2970 11:54:47.775919 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2971 11:54:47.779415 0 12 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2972 11:54:47.782671 0 12 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2973 11:54:47.789240 0 12 16 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
2974 11:54:47.792552 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 11:54:47.795923 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2976 11:54:47.799427 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2977 11:54:47.806244 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2978 11:54:47.809320 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2979 11:54:47.812489 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2980 11:54:47.819322 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2981 11:54:47.822536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2982 11:54:47.825895 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2983 11:54:47.832442 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:54:47.836416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:54:47.839269 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:54:47.845797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:54:47.849167 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:54:47.852449 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 11:54:47.859312 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 11:54:47.862468 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2991 11:54:47.865758 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2992 11:54:47.872442 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2993 11:54:47.875715 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2994 11:54:47.879055 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2995 11:54:47.885696 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2996 11:54:47.889118 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2997 11:54:47.892358 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2998 11:54:47.899210 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2999 11:54:47.899320 Total UI for P1: 0, mck2ui 16
3000 11:54:47.902464 best dqsien dly found for B0: ( 0, 15, 16)
3001 11:54:47.909155 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3002 11:54:47.912468 Total UI for P1: 0, mck2ui 16
3003 11:54:47.915859 best dqsien dly found for B1: ( 0, 15, 20)
3004 11:54:47.919088 best DQS0 dly(MCK, UI, PI) = (0, 15, 16)
3005 11:54:47.922626 best DQS1 dly(MCK, UI, PI) = (0, 15, 20)
3006 11:54:47.922715
3007 11:54:47.925708 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 16)
3008 11:54:47.929248 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 20)
3009 11:54:47.932440 [Gating] SW calibration Done
3010 11:54:47.932582 ==
3011 11:54:47.935843 Dram Type= 6, Freq= 0, CH_1, rank 0
3012 11:54:47.939102 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3013 11:54:47.939188 ==
3014 11:54:47.942381 RX Vref Scan: 0
3015 11:54:47.942463
3016 11:54:47.945695 RX Vref 0 -> 0, step: 1
3017 11:54:47.945776
3018 11:54:47.945841 RX Delay -40 -> 252, step: 8
3019 11:54:47.952474 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3020 11:54:47.955685 iDelay=208, Bit 1, Center 107 (32 ~ 183) 152
3021 11:54:47.959013 iDelay=208, Bit 2, Center 107 (32 ~ 183) 152
3022 11:54:47.962364 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3023 11:54:47.965759 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3024 11:54:47.972418 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3025 11:54:47.975582 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3026 11:54:47.979297 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3027 11:54:47.982140 iDelay=208, Bit 8, Center 87 (16 ~ 159) 144
3028 11:54:47.985495 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3029 11:54:47.992482 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3030 11:54:47.995528 iDelay=208, Bit 11, Center 99 (32 ~ 167) 136
3031 11:54:47.999149 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3032 11:54:48.002237 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3033 11:54:48.005585 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3034 11:54:48.012252 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3035 11:54:48.012368 ==
3036 11:54:48.015503 Dram Type= 6, Freq= 0, CH_1, rank 0
3037 11:54:48.019124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3038 11:54:48.019215 ==
3039 11:54:48.019281 DQS Delay:
3040 11:54:48.022383 DQS0 = 0, DQS1 = 0
3041 11:54:48.022467 DQM Delay:
3042 11:54:48.025556 DQM0 = 116, DQM1 = 108
3043 11:54:48.025640 DQ Delay:
3044 11:54:48.028879 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3045 11:54:48.032127 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3046 11:54:48.035553 DQ8 =87, DQ9 =95, DQ10 =111, DQ11 =99
3047 11:54:48.038745 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3048 11:54:48.038833
3049 11:54:48.038898
3050 11:54:48.038958 ==
3051 11:54:48.042225 Dram Type= 6, Freq= 0, CH_1, rank 0
3052 11:54:48.048691 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3053 11:54:48.048787 ==
3054 11:54:48.048853
3055 11:54:48.048913
3056 11:54:48.048972 TX Vref Scan disable
3057 11:54:48.052407 == TX Byte 0 ==
3058 11:54:48.055981 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3059 11:54:48.062499 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3060 11:54:48.062583 == TX Byte 1 ==
3061 11:54:48.065976 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3062 11:54:48.069251 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3063 11:54:48.072412 ==
3064 11:54:48.076038 Dram Type= 6, Freq= 0, CH_1, rank 0
3065 11:54:48.079057 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3066 11:54:48.079138 ==
3067 11:54:48.090283 TX Vref=22, minBit 3, minWin=25, winSum=409
3068 11:54:48.093615 TX Vref=24, minBit 11, minWin=25, winSum=416
3069 11:54:48.096864 TX Vref=26, minBit 0, minWin=26, winSum=425
3070 11:54:48.100270 TX Vref=28, minBit 0, minWin=26, winSum=429
3071 11:54:48.103850 TX Vref=30, minBit 15, minWin=25, winSum=426
3072 11:54:48.110359 TX Vref=32, minBit 9, minWin=25, winSum=427
3073 11:54:48.113637 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
3074 11:54:48.113728
3075 11:54:48.116949 Final TX Range 1 Vref 28
3076 11:54:48.117048
3077 11:54:48.117113 ==
3078 11:54:48.119987 Dram Type= 6, Freq= 0, CH_1, rank 0
3079 11:54:48.123365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3080 11:54:48.126561 ==
3081 11:54:48.126642
3082 11:54:48.126706
3083 11:54:48.126765 TX Vref Scan disable
3084 11:54:48.130617 == TX Byte 0 ==
3085 11:54:48.133546 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3086 11:54:48.136709 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3087 11:54:48.140097 == TX Byte 1 ==
3088 11:54:48.143516 Update DQ dly =839 (3 ,1, 39) DQ OEN =(2 ,6)
3089 11:54:48.150288 Update DQM dly =839 (3 ,1, 39) DQM OEN =(2 ,6)
3090 11:54:48.150369
3091 11:54:48.150432 [DATLAT]
3092 11:54:48.150492 Freq=1200, CH1 RK0
3093 11:54:48.150550
3094 11:54:48.153607 DATLAT Default: 0xd
3095 11:54:48.153686 0, 0xFFFF, sum = 0
3096 11:54:48.156741 1, 0xFFFF, sum = 0
3097 11:54:48.156823 2, 0xFFFF, sum = 0
3098 11:54:48.160249 3, 0xFFFF, sum = 0
3099 11:54:48.163562 4, 0xFFFF, sum = 0
3100 11:54:48.163644 5, 0xFFFF, sum = 0
3101 11:54:48.166675 6, 0xFFFF, sum = 0
3102 11:54:48.166757 7, 0xFFFF, sum = 0
3103 11:54:48.170102 8, 0xFFFF, sum = 0
3104 11:54:48.170185 9, 0xFFFF, sum = 0
3105 11:54:48.173264 10, 0xFFFF, sum = 0
3106 11:54:48.173346 11, 0x0, sum = 1
3107 11:54:48.176587 12, 0x0, sum = 2
3108 11:54:48.176669 13, 0x0, sum = 3
3109 11:54:48.180068 14, 0x0, sum = 4
3110 11:54:48.180149 best_step = 12
3111 11:54:48.180212
3112 11:54:48.180272 ==
3113 11:54:48.183404 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:54:48.186660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3115 11:54:48.186741 ==
3116 11:54:48.190154 RX Vref Scan: 1
3117 11:54:48.190234
3118 11:54:48.193338 Set Vref Range= 32 -> 127
3119 11:54:48.193419
3120 11:54:48.193482 RX Vref 32 -> 127, step: 1
3121 11:54:48.193541
3122 11:54:48.196823 RX Delay -29 -> 252, step: 4
3123 11:54:48.196904
3124 11:54:48.200158 Set Vref, RX VrefLevel [Byte0]: 32
3125 11:54:48.203219 [Byte1]: 32
3126 11:54:48.206962
3127 11:54:48.207043 Set Vref, RX VrefLevel [Byte0]: 33
3128 11:54:48.210034 [Byte1]: 33
3129 11:54:48.215061
3130 11:54:48.215142 Set Vref, RX VrefLevel [Byte0]: 34
3131 11:54:48.218214 [Byte1]: 34
3132 11:54:48.222802
3133 11:54:48.222882 Set Vref, RX VrefLevel [Byte0]: 35
3134 11:54:48.226088 [Byte1]: 35
3135 11:54:48.230716
3136 11:54:48.230800 Set Vref, RX VrefLevel [Byte0]: 36
3137 11:54:48.234006 [Byte1]: 36
3138 11:54:48.238646
3139 11:54:48.238725 Set Vref, RX VrefLevel [Byte0]: 37
3140 11:54:48.241983 [Byte1]: 37
3141 11:54:48.246588
3142 11:54:48.246667 Set Vref, RX VrefLevel [Byte0]: 38
3143 11:54:48.249981 [Byte1]: 38
3144 11:54:48.254767
3145 11:54:48.254847 Set Vref, RX VrefLevel [Byte0]: 39
3146 11:54:48.257853 [Byte1]: 39
3147 11:54:48.262793
3148 11:54:48.262874 Set Vref, RX VrefLevel [Byte0]: 40
3149 11:54:48.266141 [Byte1]: 40
3150 11:54:48.270673
3151 11:54:48.270753 Set Vref, RX VrefLevel [Byte0]: 41
3152 11:54:48.273696 [Byte1]: 41
3153 11:54:48.278412
3154 11:54:48.278493 Set Vref, RX VrefLevel [Byte0]: 42
3155 11:54:48.281750 [Byte1]: 42
3156 11:54:48.286498
3157 11:54:48.286579 Set Vref, RX VrefLevel [Byte0]: 43
3158 11:54:48.289839 [Byte1]: 43
3159 11:54:48.294365
3160 11:54:48.294446 Set Vref, RX VrefLevel [Byte0]: 44
3161 11:54:48.297792 [Byte1]: 44
3162 11:54:48.302589
3163 11:54:48.302670 Set Vref, RX VrefLevel [Byte0]: 45
3164 11:54:48.305916 [Byte1]: 45
3165 11:54:48.310221
3166 11:54:48.310304 Set Vref, RX VrefLevel [Byte0]: 46
3167 11:54:48.313656 [Byte1]: 46
3168 11:54:48.318238
3169 11:54:48.318327 Set Vref, RX VrefLevel [Byte0]: 47
3170 11:54:48.321783 [Byte1]: 47
3171 11:54:48.326411
3172 11:54:48.326493 Set Vref, RX VrefLevel [Byte0]: 48
3173 11:54:48.329422 [Byte1]: 48
3174 11:54:48.334233
3175 11:54:48.334313 Set Vref, RX VrefLevel [Byte0]: 49
3176 11:54:48.337459 [Byte1]: 49
3177 11:54:48.342117
3178 11:54:48.342199 Set Vref, RX VrefLevel [Byte0]: 50
3179 11:54:48.345226 [Byte1]: 50
3180 11:54:48.350122
3181 11:54:48.350202 Set Vref, RX VrefLevel [Byte0]: 51
3182 11:54:48.353363 [Byte1]: 51
3183 11:54:48.357913
3184 11:54:48.357994 Set Vref, RX VrefLevel [Byte0]: 52
3185 11:54:48.361447 [Byte1]: 52
3186 11:54:48.366122
3187 11:54:48.366240 Set Vref, RX VrefLevel [Byte0]: 53
3188 11:54:48.369242 [Byte1]: 53
3189 11:54:48.373873
3190 11:54:48.373955 Set Vref, RX VrefLevel [Byte0]: 54
3191 11:54:48.377223 [Byte1]: 54
3192 11:54:48.381848
3193 11:54:48.381929 Set Vref, RX VrefLevel [Byte0]: 55
3194 11:54:48.385226 [Byte1]: 55
3195 11:54:48.390000
3196 11:54:48.390081 Set Vref, RX VrefLevel [Byte0]: 56
3197 11:54:48.393073 [Byte1]: 56
3198 11:54:48.397858
3199 11:54:48.397942 Set Vref, RX VrefLevel [Byte0]: 57
3200 11:54:48.401055 [Byte1]: 57
3201 11:54:48.405665
3202 11:54:48.405745 Set Vref, RX VrefLevel [Byte0]: 58
3203 11:54:48.409262 [Byte1]: 58
3204 11:54:48.413726
3205 11:54:48.413806 Set Vref, RX VrefLevel [Byte0]: 59
3206 11:54:48.416921 [Byte1]: 59
3207 11:54:48.421555
3208 11:54:48.421636 Set Vref, RX VrefLevel [Byte0]: 60
3209 11:54:48.424935 [Byte1]: 60
3210 11:54:48.429739
3211 11:54:48.429819 Set Vref, RX VrefLevel [Byte0]: 61
3212 11:54:48.433260 [Byte1]: 61
3213 11:54:48.437606
3214 11:54:48.437686 Set Vref, RX VrefLevel [Byte0]: 62
3215 11:54:48.440981 [Byte1]: 62
3216 11:54:48.445422
3217 11:54:48.445502 Set Vref, RX VrefLevel [Byte0]: 63
3218 11:54:48.448993 [Byte1]: 63
3219 11:54:48.453458
3220 11:54:48.453538 Set Vref, RX VrefLevel [Byte0]: 64
3221 11:54:48.456711 [Byte1]: 64
3222 11:54:48.461508
3223 11:54:48.461588 Set Vref, RX VrefLevel [Byte0]: 65
3224 11:54:48.464947 [Byte1]: 65
3225 11:54:48.469396
3226 11:54:48.469476 Final RX Vref Byte 0 = 58 to rank0
3227 11:54:48.472697 Final RX Vref Byte 1 = 51 to rank0
3228 11:54:48.476176 Final RX Vref Byte 0 = 58 to rank1
3229 11:54:48.479792 Final RX Vref Byte 1 = 51 to rank1==
3230 11:54:48.483355 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 11:54:48.489446 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3232 11:54:48.489528 ==
3233 11:54:48.489593 DQS Delay:
3234 11:54:48.489653 DQS0 = 0, DQS1 = 0
3235 11:54:48.492984 DQM Delay:
3236 11:54:48.493065 DQM0 = 115, DQM1 = 105
3237 11:54:48.496070 DQ Delay:
3238 11:54:48.499439 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3239 11:54:48.502864 DQ4 =114, DQ5 =124, DQ6 =120, DQ7 =114
3240 11:54:48.506233 DQ8 =86, DQ9 =94, DQ10 =108, DQ11 =98
3241 11:54:48.509276 DQ12 =112, DQ13 =116, DQ14 =116, DQ15 =114
3242 11:54:48.509357
3243 11:54:48.509421
3244 11:54:48.516233 [DQSOSCAuto] RK0, (LSB)MR18= 0x1818, (MSB)MR19= 0x404, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
3245 11:54:48.519440 CH1 RK0: MR19=404, MR18=1818
3246 11:54:48.526059 CH1_RK0: MR19=0x404, MR18=0x1818, DQSOSC=400, MR23=63, INC=40, DEC=27
3247 11:54:48.526141
3248 11:54:48.529163 ----->DramcWriteLeveling(PI) begin...
3249 11:54:48.529244 ==
3250 11:54:48.532480 Dram Type= 6, Freq= 0, CH_1, rank 1
3251 11:54:48.535893 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3252 11:54:48.539332 ==
3253 11:54:48.539414 Write leveling (Byte 0): 23 => 23
3254 11:54:48.542534 Write leveling (Byte 1): 21 => 21
3255 11:54:48.545897 DramcWriteLeveling(PI) end<-----
3256 11:54:48.545978
3257 11:54:48.546042 ==
3258 11:54:48.549179 Dram Type= 6, Freq= 0, CH_1, rank 1
3259 11:54:48.555582 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3260 11:54:48.555663 ==
3261 11:54:48.558866 [Gating] SW mode calibration
3262 11:54:48.565670 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 24 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3263 11:54:48.568904 RX_Path_delay_UI(43) -3 - DQSINCTL_UI(32) = u1StartUI(11)
3264 11:54:48.575434 0 11 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3265 11:54:48.578798 0 11 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3266 11:54:48.582160 0 11 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3267 11:54:48.588851 0 11 12 | B1->B0 | 3434 2b2b | 1 1 | (1 1) (1 0)
3268 11:54:48.592251 0 11 16 | B1->B0 | 3030 2424 | 0 0 | (0 1) (1 0)
3269 11:54:48.595515 0 11 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 11:54:48.598812 0 11 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3271 11:54:48.605585 0 11 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3272 11:54:48.608895 0 12 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3273 11:54:48.612229 0 12 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3274 11:54:48.619115 0 12 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3275 11:54:48.622173 0 12 12 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
3276 11:54:48.625740 0 12 16 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
3277 11:54:48.632466 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 11:54:48.635651 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3279 11:54:48.639052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3280 11:54:48.645641 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3281 11:54:48.649015 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3282 11:54:48.652444 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3283 11:54:48.658971 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3284 11:54:48.662401 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3285 11:54:48.666204 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:54:48.672339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:54:48.675769 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 11:54:48.678938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 11:54:48.685881 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 11:54:48.689247 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 11:54:48.692406 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 11:54:48.695601 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 11:54:48.702455 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 11:54:48.705572 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3295 11:54:48.708893 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3296 11:54:48.715555 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3297 11:54:48.718825 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3298 11:54:48.722438 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3299 11:54:48.728944 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3300 11:54:48.732432 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3301 11:54:48.735610 Total UI for P1: 0, mck2ui 16
3302 11:54:48.738779 best dqsien dly found for B0: ( 0, 15, 12)
3303 11:54:48.742175 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3304 11:54:48.745761 Total UI for P1: 0, mck2ui 16
3305 11:54:48.748754 best dqsien dly found for B1: ( 0, 15, 14)
3306 11:54:48.752199 best DQS0 dly(MCK, UI, PI) = (0, 15, 12)
3307 11:54:48.755543 best DQS1 dly(MCK, UI, PI) = (0, 15, 14)
3308 11:54:48.755625
3309 11:54:48.762315 best DQS0 P1 dly(MCK, UI, PI) = (1, 3, 12)
3310 11:54:48.765621 best DQS1 P1 dly(MCK, UI, PI) = (1, 3, 14)
3311 11:54:48.765704 [Gating] SW calibration Done
3312 11:54:48.768731 ==
3313 11:54:48.772324 Dram Type= 6, Freq= 0, CH_1, rank 1
3314 11:54:48.775688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3315 11:54:48.775771 ==
3316 11:54:48.775834 RX Vref Scan: 0
3317 11:54:48.775895
3318 11:54:48.778812 RX Vref 0 -> 0, step: 1
3319 11:54:48.778893
3320 11:54:48.782326 RX Delay -40 -> 252, step: 8
3321 11:54:48.785531 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3322 11:54:48.788797 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3323 11:54:48.792335 iDelay=200, Bit 2, Center 107 (32 ~ 183) 152
3324 11:54:48.798805 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3325 11:54:48.802419 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3326 11:54:48.805451 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3327 11:54:48.808811 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3328 11:54:48.812381 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3329 11:54:48.818826 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
3330 11:54:48.822196 iDelay=200, Bit 9, Center 91 (16 ~ 167) 152
3331 11:54:48.825691 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3332 11:54:48.829014 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3333 11:54:48.832239 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3334 11:54:48.838899 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3335 11:54:48.842266 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3336 11:54:48.845763 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3337 11:54:48.845872 ==
3338 11:54:48.848909 Dram Type= 6, Freq= 0, CH_1, rank 1
3339 11:54:48.852387 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3340 11:54:48.852546 ==
3341 11:54:48.855497 DQS Delay:
3342 11:54:48.855599 DQS0 = 0, DQS1 = 0
3343 11:54:48.858839 DQM Delay:
3344 11:54:48.858940 DQM0 = 116, DQM1 = 105
3345 11:54:48.859031 DQ Delay:
3346 11:54:48.865427 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3347 11:54:48.868917 DQ4 =115, DQ5 =127, DQ6 =123, DQ7 =115
3348 11:54:48.872641 DQ8 =91, DQ9 =91, DQ10 =103, DQ11 =103
3349 11:54:48.875587 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =111
3350 11:54:48.875706
3351 11:54:48.875803
3352 11:54:48.875894 ==
3353 11:54:48.878944 Dram Type= 6, Freq= 0, CH_1, rank 1
3354 11:54:48.882175 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3355 11:54:48.882283 ==
3356 11:54:48.882379
3357 11:54:48.882476
3358 11:54:48.885567 TX Vref Scan disable
3359 11:54:48.888915 == TX Byte 0 ==
3360 11:54:48.892199 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3361 11:54:48.895753 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3362 11:54:48.898900 == TX Byte 1 ==
3363 11:54:48.902175 Update DQ dly =838 (3 ,1, 38) DQ OEN =(2 ,6)
3364 11:54:48.905511 Update DQM dly =838 (3 ,1, 38) DQM OEN =(2 ,6)
3365 11:54:48.905623 ==
3366 11:54:48.909276 Dram Type= 6, Freq= 0, CH_1, rank 1
3367 11:54:48.912406 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3368 11:54:48.912580 ==
3369 11:54:48.925491 TX Vref=22, minBit 7, minWin=25, winSum=418
3370 11:54:48.928968 TX Vref=24, minBit 9, minWin=25, winSum=423
3371 11:54:48.931960 TX Vref=26, minBit 9, minWin=25, winSum=427
3372 11:54:48.935202 TX Vref=28, minBit 9, minWin=26, winSum=432
3373 11:54:48.938591 TX Vref=30, minBit 8, minWin=26, winSum=433
3374 11:54:48.942269 TX Vref=32, minBit 0, minWin=26, winSum=430
3375 11:54:48.949102 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 30
3376 11:54:48.949232
3377 11:54:48.952036 Final TX Range 1 Vref 30
3378 11:54:48.952131
3379 11:54:48.952197 ==
3380 11:54:48.955521 Dram Type= 6, Freq= 0, CH_1, rank 1
3381 11:54:48.958790 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3382 11:54:48.958893 ==
3383 11:54:48.958959
3384 11:54:48.959021
3385 11:54:48.962035 TX Vref Scan disable
3386 11:54:48.965420 == TX Byte 0 ==
3387 11:54:48.968654 Update DQ dly =840 (3 ,1, 40) DQ OEN =(2 ,6)
3388 11:54:48.971838 Update DQM dly =840 (3 ,1, 40) DQM OEN =(2 ,6)
3389 11:54:48.975423 == TX Byte 1 ==
3390 11:54:48.978487 Update DQ dly =837 (3 ,1, 37) DQ OEN =(2 ,6)
3391 11:54:48.982053 Update DQM dly =837 (3 ,1, 37) DQM OEN =(2 ,6)
3392 11:54:48.982159
3393 11:54:48.985272 [DATLAT]
3394 11:54:48.985413 Freq=1200, CH1 RK1
3395 11:54:48.985532
3396 11:54:48.988668 DATLAT Default: 0xc
3397 11:54:48.988756 0, 0xFFFF, sum = 0
3398 11:54:48.991965 1, 0xFFFF, sum = 0
3399 11:54:48.992061 2, 0xFFFF, sum = 0
3400 11:54:48.995270 3, 0xFFFF, sum = 0
3401 11:54:48.995359 4, 0xFFFF, sum = 0
3402 11:54:48.998613 5, 0xFFFF, sum = 0
3403 11:54:48.998701 6, 0xFFFF, sum = 0
3404 11:54:49.002373 7, 0xFFFF, sum = 0
3405 11:54:49.002463 8, 0xFFFF, sum = 0
3406 11:54:49.005445 9, 0xFFFF, sum = 0
3407 11:54:49.008633 10, 0xFFFF, sum = 0
3408 11:54:49.008739 11, 0x0, sum = 1
3409 11:54:49.008807 12, 0x0, sum = 2
3410 11:54:49.012159 13, 0x0, sum = 3
3411 11:54:49.012269 14, 0x0, sum = 4
3412 11:54:49.015561 best_step = 12
3413 11:54:49.015644
3414 11:54:49.015710 ==
3415 11:54:49.018572 Dram Type= 6, Freq= 0, CH_1, rank 1
3416 11:54:49.021998 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3417 11:54:49.022081 ==
3418 11:54:49.025446 RX Vref Scan: 0
3419 11:54:49.025527
3420 11:54:49.025591 RX Vref 0 -> 0, step: 1
3421 11:54:49.025650
3422 11:54:49.028546 RX Delay -29 -> 252, step: 4
3423 11:54:49.036050 iDelay=199, Bit 0, Center 116 (47 ~ 186) 140
3424 11:54:49.038865 iDelay=199, Bit 1, Center 108 (39 ~ 178) 140
3425 11:54:49.042257 iDelay=199, Bit 2, Center 108 (39 ~ 178) 140
3426 11:54:49.045501 iDelay=199, Bit 3, Center 112 (43 ~ 182) 140
3427 11:54:49.048959 iDelay=199, Bit 4, Center 114 (43 ~ 186) 144
3428 11:54:49.055706 iDelay=199, Bit 5, Center 124 (51 ~ 198) 148
3429 11:54:49.058915 iDelay=199, Bit 6, Center 122 (51 ~ 194) 144
3430 11:54:49.062471 iDelay=199, Bit 7, Center 112 (43 ~ 182) 140
3431 11:54:49.065602 iDelay=199, Bit 8, Center 86 (19 ~ 154) 136
3432 11:54:49.068929 iDelay=199, Bit 9, Center 92 (27 ~ 158) 132
3433 11:54:49.075766 iDelay=199, Bit 10, Center 106 (39 ~ 174) 136
3434 11:54:49.078931 iDelay=199, Bit 11, Center 98 (31 ~ 166) 136
3435 11:54:49.082445 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3436 11:54:49.085552 iDelay=199, Bit 13, Center 112 (47 ~ 178) 132
3437 11:54:49.088955 iDelay=199, Bit 14, Center 114 (47 ~ 182) 136
3438 11:54:49.095565 iDelay=199, Bit 15, Center 112 (47 ~ 178) 132
3439 11:54:49.095649 ==
3440 11:54:49.098922 Dram Type= 6, Freq= 0, CH_1, rank 1
3441 11:54:49.102124 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3442 11:54:49.102207 ==
3443 11:54:49.102271 DQS Delay:
3444 11:54:49.105729 DQS0 = 0, DQS1 = 0
3445 11:54:49.105810 DQM Delay:
3446 11:54:49.108953 DQM0 = 114, DQM1 = 104
3447 11:54:49.109036 DQ Delay:
3448 11:54:49.112157 DQ0 =116, DQ1 =108, DQ2 =108, DQ3 =112
3449 11:54:49.115734 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3450 11:54:49.119093 DQ8 =86, DQ9 =92, DQ10 =106, DQ11 =98
3451 11:54:49.122303 DQ12 =114, DQ13 =112, DQ14 =114, DQ15 =112
3452 11:54:49.122386
3453 11:54:49.122451
3454 11:54:49.132047 [DQSOSCAuto] RK1, (LSB)MR18= 0xc0c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 405 ps
3455 11:54:49.135808 CH1 RK1: MR19=404, MR18=C0C
3456 11:54:49.138820 CH1_RK1: MR19=0x404, MR18=0xC0C, DQSOSC=405, MR23=63, INC=39, DEC=26
3457 11:54:49.142310 [RxdqsGatingPostProcess] freq 1200
3458 11:54:49.148903 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
3459 11:54:49.152055 Pre-setting of DQS Precalculation
3460 11:54:49.155514 [DualRankRxdatlatCal] RK0: 12, RK1: 12, Final_Datlat 12
3461 11:54:49.165439 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3462 11:54:49.172211 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3463 11:54:49.172299
3464 11:54:49.172364
3465 11:54:49.175740 [Calibration Summary] 2400 Mbps
3466 11:54:49.175821 CH 0, Rank 0
3467 11:54:49.178986 SW Impedance : PASS
3468 11:54:49.179069 DUTY Scan : NO K
3469 11:54:49.182296 ZQ Calibration : PASS
3470 11:54:49.185490 Jitter Meter : NO K
3471 11:54:49.185572 CBT Training : PASS
3472 11:54:49.188863 Write leveling : PASS
3473 11:54:49.192324 RX DQS gating : PASS
3474 11:54:49.192405 RX DQ/DQS(RDDQC) : PASS
3475 11:54:49.195555 TX DQ/DQS : PASS
3476 11:54:49.195637 RX DATLAT : PASS
3477 11:54:49.198863 RX DQ/DQS(Engine): PASS
3478 11:54:49.202257 TX OE : NO K
3479 11:54:49.202339 All Pass.
3480 11:54:49.202404
3481 11:54:49.202464 CH 0, Rank 1
3482 11:54:49.205610 SW Impedance : PASS
3483 11:54:49.209081 DUTY Scan : NO K
3484 11:54:49.209165 ZQ Calibration : PASS
3485 11:54:49.212068 Jitter Meter : NO K
3486 11:54:49.215542 CBT Training : PASS
3487 11:54:49.215624 Write leveling : PASS
3488 11:54:49.218790 RX DQS gating : PASS
3489 11:54:49.222037 RX DQ/DQS(RDDQC) : PASS
3490 11:54:49.222120 TX DQ/DQS : PASS
3491 11:54:49.225446 RX DATLAT : PASS
3492 11:54:49.228818 RX DQ/DQS(Engine): PASS
3493 11:54:49.228899 TX OE : NO K
3494 11:54:49.228964 All Pass.
3495 11:54:49.232107
3496 11:54:49.232190 CH 1, Rank 0
3497 11:54:49.235606 SW Impedance : PASS
3498 11:54:49.235687 DUTY Scan : NO K
3499 11:54:49.238816 ZQ Calibration : PASS
3500 11:54:49.238897 Jitter Meter : NO K
3501 11:54:49.242320 CBT Training : PASS
3502 11:54:49.245613 Write leveling : PASS
3503 11:54:49.245695 RX DQS gating : PASS
3504 11:54:49.248957 RX DQ/DQS(RDDQC) : PASS
3505 11:54:49.252175 TX DQ/DQS : PASS
3506 11:54:49.252256 RX DATLAT : PASS
3507 11:54:49.255739 RX DQ/DQS(Engine): PASS
3508 11:54:49.258892 TX OE : NO K
3509 11:54:49.258973 All Pass.
3510 11:54:49.259039
3511 11:54:49.259098 CH 1, Rank 1
3512 11:54:49.262228 SW Impedance : PASS
3513 11:54:49.265534 DUTY Scan : NO K
3514 11:54:49.265615 ZQ Calibration : PASS
3515 11:54:49.268883 Jitter Meter : NO K
3516 11:54:49.272146 CBT Training : PASS
3517 11:54:49.272226 Write leveling : PASS
3518 11:54:49.275460 RX DQS gating : PASS
3519 11:54:49.278737 RX DQ/DQS(RDDQC) : PASS
3520 11:54:49.278818 TX DQ/DQS : PASS
3521 11:54:49.282224 RX DATLAT : PASS
3522 11:54:49.282304 RX DQ/DQS(Engine): PASS
3523 11:54:49.285572 TX OE : NO K
3524 11:54:49.285653 All Pass.
3525 11:54:49.285717
3526 11:54:49.288926 DramC Write-DBI off
3527 11:54:49.292234 PER_BANK_REFRESH: Hybrid Mode
3528 11:54:49.292316 TX_TRACKING: ON
3529 11:54:49.302418 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3530 11:54:49.305781 [FAST_K] Save calibration result to emmc
3531 11:54:49.309109 dramc_set_vcore_voltage set vcore to 650000
3532 11:54:49.312709 Read voltage for 600, 5
3533 11:54:49.312790 Vio18 = 0
3534 11:54:49.312855 Vcore = 650000
3535 11:54:49.315986 Vdram = 0
3536 11:54:49.316066 Vddq = 0
3537 11:54:49.316129 Vmddr = 0
3538 11:54:49.322342 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3539 11:54:49.325873 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3540 11:54:49.329364 MEM_TYPE=3, freq_sel=19
3541 11:54:49.332313 sv_algorithm_assistance_LP4_1600
3542 11:54:49.335528 ============ PULL DRAM RESETB DOWN ============
3543 11:54:49.338995 ========== PULL DRAM RESETB DOWN end =========
3544 11:54:49.345486 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3545 11:54:49.348966 ===================================
3546 11:54:49.352264 LPDDR4 DRAM CONFIGURATION
3547 11:54:49.355744 ===================================
3548 11:54:49.355825 EX_ROW_EN[0] = 0x0
3549 11:54:49.359062 EX_ROW_EN[1] = 0x0
3550 11:54:49.359143 LP4Y_EN = 0x0
3551 11:54:49.362311 WORK_FSP = 0x0
3552 11:54:49.362393 WL = 0x2
3553 11:54:49.365607 RL = 0x2
3554 11:54:49.365689 BL = 0x2
3555 11:54:49.368833 RPST = 0x0
3556 11:54:49.368914 RD_PRE = 0x0
3557 11:54:49.372136 WR_PRE = 0x1
3558 11:54:49.372216 WR_PST = 0x0
3559 11:54:49.375236 DBI_WR = 0x0
3560 11:54:49.375316 DBI_RD = 0x0
3561 11:54:49.378741 OTF = 0x1
3562 11:54:49.381980 ===================================
3563 11:54:49.385526 ===================================
3564 11:54:49.385607 ANA top config
3565 11:54:49.388787 ===================================
3566 11:54:49.391926 DLL_ASYNC_EN = 0
3567 11:54:49.395314 ALL_SLAVE_EN = 1
3568 11:54:49.398487 NEW_RANK_MODE = 1
3569 11:54:49.398568 DLL_IDLE_MODE = 1
3570 11:54:49.401966 LP45_APHY_COMB_EN = 1
3571 11:54:49.405232 TX_ODT_DIS = 1
3572 11:54:49.408376 NEW_8X_MODE = 1
3573 11:54:49.411879 ===================================
3574 11:54:49.415104 ===================================
3575 11:54:49.418309 data_rate = 1200
3576 11:54:49.421746 CKR = 1
3577 11:54:49.421828 DQ_P2S_RATIO = 8
3578 11:54:49.425144 ===================================
3579 11:54:49.428465 CA_P2S_RATIO = 8
3580 11:54:49.432080 DQ_CA_OPEN = 0
3581 11:54:49.435067 DQ_SEMI_OPEN = 0
3582 11:54:49.438286 CA_SEMI_OPEN = 0
3583 11:54:49.441639 CA_FULL_RATE = 0
3584 11:54:49.441723 DQ_CKDIV4_EN = 1
3585 11:54:49.445009 CA_CKDIV4_EN = 1
3586 11:54:49.448244 CA_PREDIV_EN = 0
3587 11:54:49.451695 PH8_DLY = 0
3588 11:54:49.455071 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3589 11:54:49.455153 DQ_AAMCK_DIV = 4
3590 11:54:49.458388 CA_AAMCK_DIV = 4
3591 11:54:49.461536 CA_ADMCK_DIV = 4
3592 11:54:49.464850 DQ_TRACK_CA_EN = 0
3593 11:54:49.468002 CA_PICK = 600
3594 11:54:49.471558 CA_MCKIO = 600
3595 11:54:49.474993 MCKIO_SEMI = 0
3596 11:54:49.478087 PLL_FREQ = 2288
3597 11:54:49.478171 DQ_UI_PI_RATIO = 32
3598 11:54:49.481380 CA_UI_PI_RATIO = 0
3599 11:54:49.484821 ===================================
3600 11:54:49.487833 ===================================
3601 11:54:49.491348 memory_type:LPDDR4
3602 11:54:49.494659 GP_NUM : 10
3603 11:54:49.494741 SRAM_EN : 1
3604 11:54:49.497900 MD32_EN : 0
3605 11:54:49.501038 ===================================
3606 11:54:49.504756 [ANA_INIT] >>>>>>>>>>>>>>
3607 11:54:49.504838 <<<<<< [CONFIGURE PHASE]: ANA_TX
3608 11:54:49.507739 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3609 11:54:49.511005 ===================================
3610 11:54:49.514383 data_rate = 1200,PCW = 0X5800
3611 11:54:49.517684 ===================================
3612 11:54:49.520949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3613 11:54:49.527610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3614 11:54:49.534044 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3615 11:54:49.537485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3616 11:54:49.541312 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3617 11:54:49.543992 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3618 11:54:49.547469 [ANA_INIT] flow start
3619 11:54:49.547552 [ANA_INIT] PLL >>>>>>>>
3620 11:54:49.550624 [ANA_INIT] PLL <<<<<<<<
3621 11:54:49.553904 [ANA_INIT] MIDPI >>>>>>>>
3622 11:54:49.557152 [ANA_INIT] MIDPI <<<<<<<<
3623 11:54:49.557234 [ANA_INIT] DLL >>>>>>>>
3624 11:54:49.560608 [ANA_INIT] flow end
3625 11:54:49.563783 ============ LP4 DIFF to SE enter ============
3626 11:54:49.567084 ============ LP4 DIFF to SE exit ============
3627 11:54:49.570418 [ANA_INIT] <<<<<<<<<<<<<
3628 11:54:49.573636 [Flow] Enable top DCM control >>>>>
3629 11:54:49.576826 [Flow] Enable top DCM control <<<<<
3630 11:54:49.580268 Enable DLL master slave shuffle
3631 11:54:49.587053 ==============================================================
3632 11:54:49.587138 Gating Mode config
3633 11:54:49.593877 ==============================================================
3634 11:54:49.593960 Config description:
3635 11:54:49.603254 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3636 11:54:49.609914 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3637 11:54:49.616693 SELPH_MODE 0: By rank 1: By Phase
3638 11:54:49.619855 ==============================================================
3639 11:54:49.623391 GAT_TRACK_EN = 1
3640 11:54:49.626520 RX_GATING_MODE = 2
3641 11:54:49.629886 RX_GATING_TRACK_MODE = 2
3642 11:54:49.632996 SELPH_MODE = 1
3643 11:54:49.636425 PICG_EARLY_EN = 1
3644 11:54:49.639952 VALID_LAT_VALUE = 1
3645 11:54:49.646485 ==============================================================
3646 11:54:49.649589 Enter into Gating configuration >>>>
3647 11:54:49.653032 Exit from Gating configuration <<<<
3648 11:54:49.653116 Enter into DVFS_PRE_config >>>>>
3649 11:54:49.666094 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3650 11:54:49.669352 Exit from DVFS_PRE_config <<<<<
3651 11:54:49.672647 Enter into PICG configuration >>>>
3652 11:54:49.675967 Exit from PICG configuration <<<<
3653 11:54:49.679345 [RX_INPUT] configuration >>>>>
3654 11:54:49.679429 [RX_INPUT] configuration <<<<<
3655 11:54:49.686212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3656 11:54:49.692701 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3657 11:54:49.695851 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3658 11:54:49.702587 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3659 11:54:49.709108 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3660 11:54:49.715642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3661 11:54:49.718980 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3662 11:54:49.722354 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3663 11:54:49.728938 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3664 11:54:49.732213 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3665 11:54:49.735473 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3666 11:54:49.742311 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3667 11:54:49.745394 ===================================
3668 11:54:49.745477 LPDDR4 DRAM CONFIGURATION
3669 11:54:49.749006 ===================================
3670 11:54:49.752329 EX_ROW_EN[0] = 0x0
3671 11:54:49.752411 EX_ROW_EN[1] = 0x0
3672 11:54:49.755413 LP4Y_EN = 0x0
3673 11:54:49.758756 WORK_FSP = 0x0
3674 11:54:49.758838 WL = 0x2
3675 11:54:49.761974 RL = 0x2
3676 11:54:49.762057 BL = 0x2
3677 11:54:49.765197 RPST = 0x0
3678 11:54:49.765280 RD_PRE = 0x0
3679 11:54:49.768383 WR_PRE = 0x1
3680 11:54:49.768465 WR_PST = 0x0
3681 11:54:49.771895 DBI_WR = 0x0
3682 11:54:49.771977 DBI_RD = 0x0
3683 11:54:49.775185 OTF = 0x1
3684 11:54:49.778634 ===================================
3685 11:54:49.781569 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3686 11:54:49.785209 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3687 11:54:49.791665 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3688 11:54:49.795153 ===================================
3689 11:54:49.795239 LPDDR4 DRAM CONFIGURATION
3690 11:54:49.798223 ===================================
3691 11:54:49.801642 EX_ROW_EN[0] = 0x10
3692 11:54:49.805020 EX_ROW_EN[1] = 0x0
3693 11:54:49.805102 LP4Y_EN = 0x0
3694 11:54:49.808355 WORK_FSP = 0x0
3695 11:54:49.808466 WL = 0x2
3696 11:54:49.811445 RL = 0x2
3697 11:54:49.811526 BL = 0x2
3698 11:54:49.814827 RPST = 0x0
3699 11:54:49.814910 RD_PRE = 0x0
3700 11:54:49.818084 WR_PRE = 0x1
3701 11:54:49.818167 WR_PST = 0x0
3702 11:54:49.821500 DBI_WR = 0x0
3703 11:54:49.821582 DBI_RD = 0x0
3704 11:54:49.824989 OTF = 0x1
3705 11:54:49.828133 ===================================
3706 11:54:49.834663 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3707 11:54:49.838197 nWR fixed to 30
3708 11:54:49.838285 [ModeRegInit_LP4] CH0 RK0
3709 11:54:49.841226 [ModeRegInit_LP4] CH0 RK1
3710 11:54:49.844663 [ModeRegInit_LP4] CH1 RK0
3711 11:54:49.848054 [ModeRegInit_LP4] CH1 RK1
3712 11:54:49.848138 match AC timing 16
3713 11:54:49.851432 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 0
3714 11:54:49.857835 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3715 11:54:49.861241 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3716 11:54:49.868065 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3717 11:54:49.871164 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3718 11:54:49.871251 ==
3719 11:54:49.874252 Dram Type= 6, Freq= 0, CH_0, rank 0
3720 11:54:49.877730 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3721 11:54:49.877815 ==
3722 11:54:49.884437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3723 11:54:49.890827 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
3724 11:54:49.894142 [CA 0] Center 35 (5~66) winsize 62
3725 11:54:49.897460 [CA 1] Center 35 (5~66) winsize 62
3726 11:54:49.900737 [CA 2] Center 34 (4~65) winsize 62
3727 11:54:49.903876 [CA 3] Center 34 (4~65) winsize 62
3728 11:54:49.907270 [CA 4] Center 33 (3~64) winsize 62
3729 11:54:49.910697 [CA 5] Center 33 (3~64) winsize 62
3730 11:54:49.910782
3731 11:54:49.913861 [CmdBusTrainingLP45] Vref(ca) range 1: 39
3732 11:54:49.913944
3733 11:54:49.917290 [CATrainingPosCal] consider 1 rank data
3734 11:54:49.920544 u2DelayCellTimex100 = 270/100 ps
3735 11:54:49.923970 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3736 11:54:49.927101 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3737 11:54:49.930404 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3738 11:54:49.933658 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3739 11:54:49.936980 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3740 11:54:49.940334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3741 11:54:49.940443
3742 11:54:49.947109 CA PerBit enable=1, Macro0, CA PI delay=33
3743 11:54:49.947196
3744 11:54:49.950300 [CBTSetCACLKResult] CA Dly = 33
3745 11:54:49.950383 CS Dly: 5 (0~36)
3746 11:54:49.950449 ==
3747 11:54:49.953665 Dram Type= 6, Freq= 0, CH_0, rank 1
3748 11:54:49.957321 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3749 11:54:49.957403 ==
3750 11:54:49.963393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3751 11:54:49.970089 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3752 11:54:49.973694 [CA 0] Center 36 (6~66) winsize 61
3753 11:54:49.976684 [CA 1] Center 36 (6~66) winsize 61
3754 11:54:49.980241 [CA 2] Center 34 (4~65) winsize 62
3755 11:54:49.983578 [CA 3] Center 34 (4~65) winsize 62
3756 11:54:49.987321 [CA 4] Center 33 (3~64) winsize 62
3757 11:54:49.990228 [CA 5] Center 33 (3~64) winsize 62
3758 11:54:49.990315
3759 11:54:49.993577 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3760 11:54:49.993660
3761 11:54:49.996827 [CATrainingPosCal] consider 2 rank data
3762 11:54:50.000128 u2DelayCellTimex100 = 270/100 ps
3763 11:54:50.003328 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3764 11:54:50.006736 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3765 11:54:50.010042 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3766 11:54:50.013298 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3767 11:54:50.016667 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3768 11:54:50.023475 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3769 11:54:50.023561
3770 11:54:50.026667 CA PerBit enable=1, Macro0, CA PI delay=33
3771 11:54:50.026749
3772 11:54:50.029920 [CBTSetCACLKResult] CA Dly = 33
3773 11:54:50.030002 CS Dly: 5 (0~36)
3774 11:54:50.030067
3775 11:54:50.033396 ----->DramcWriteLeveling(PI) begin...
3776 11:54:50.033479 ==
3777 11:54:50.036842 Dram Type= 6, Freq= 0, CH_0, rank 0
3778 11:54:50.043535 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3779 11:54:50.043618 ==
3780 11:54:50.046489 Write leveling (Byte 0): 29 => 29
3781 11:54:50.046571 Write leveling (Byte 1): 31 => 31
3782 11:54:50.049961 DramcWriteLeveling(PI) end<-----
3783 11:54:50.050042
3784 11:54:50.050106 ==
3785 11:54:50.053135 Dram Type= 6, Freq= 0, CH_0, rank 0
3786 11:54:50.059787 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3787 11:54:50.059870 ==
3788 11:54:50.062990 [Gating] SW mode calibration
3789 11:54:50.069713 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3790 11:54:50.072990 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3791 11:54:50.079646 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3792 11:54:50.082962 0 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3793 11:54:50.086322 0 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
3794 11:54:50.093058 0 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
3795 11:54:50.096198 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3796 11:54:50.099574 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3797 11:54:50.106293 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3798 11:54:50.109715 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3799 11:54:50.112856 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3800 11:54:50.119747 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3801 11:54:50.122869 0 6 8 | B1->B0 | 2d2d 3232 | 1 0 | (0 0) (0 0)
3802 11:54:50.126608 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3803 11:54:50.129775 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3804 11:54:50.136093 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3805 11:54:50.139477 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3806 11:54:50.142851 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3807 11:54:50.149413 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3808 11:54:50.152678 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3809 11:54:50.156052 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3810 11:54:50.162629 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3811 11:54:50.165913 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3812 11:54:50.169403 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3813 11:54:50.176020 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3814 11:54:50.179341 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3815 11:54:50.182594 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3816 11:54:50.189108 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3817 11:54:50.192439 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3818 11:54:50.195684 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3819 11:54:50.202476 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3820 11:54:50.205521 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3821 11:54:50.208918 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3822 11:54:50.215484 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3823 11:54:50.218860 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3824 11:54:50.222286 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3825 11:54:50.228943 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3826 11:54:50.232211 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3827 11:54:50.235536 Total UI for P1: 0, mck2ui 16
3828 11:54:50.238919 best dqsien dly found for B0: ( 0, 9, 8)
3829 11:54:50.242480 Total UI for P1: 0, mck2ui 16
3830 11:54:50.245501 best dqsien dly found for B1: ( 0, 9, 10)
3831 11:54:50.248895 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
3832 11:54:50.251978 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
3833 11:54:50.252081
3834 11:54:50.255372 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
3835 11:54:50.258697 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
3836 11:54:50.262149 [Gating] SW calibration Done
3837 11:54:50.262232 ==
3838 11:54:50.265320 Dram Type= 6, Freq= 0, CH_0, rank 0
3839 11:54:50.268758 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3840 11:54:50.271801 ==
3841 11:54:50.271883 RX Vref Scan: 0
3842 11:54:50.271947
3843 11:54:50.275087 RX Vref 0 -> 0, step: 1
3844 11:54:50.275170
3845 11:54:50.278652 RX Delay -230 -> 252, step: 16
3846 11:54:50.281668 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
3847 11:54:50.285367 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
3848 11:54:50.288361 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
3849 11:54:50.295125 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
3850 11:54:50.298339 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
3851 11:54:50.301870 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
3852 11:54:50.305279 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
3853 11:54:50.308398 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
3854 11:54:50.314984 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
3855 11:54:50.318590 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
3856 11:54:50.321452 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
3857 11:54:50.324853 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
3858 11:54:50.331333 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
3859 11:54:50.335015 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
3860 11:54:50.338166 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
3861 11:54:50.341350 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
3862 11:54:50.341438 ==
3863 11:54:50.344766 Dram Type= 6, Freq= 0, CH_0, rank 0
3864 11:54:50.351374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3865 11:54:50.351467 ==
3866 11:54:50.351533 DQS Delay:
3867 11:54:50.354689 DQS0 = 0, DQS1 = 0
3868 11:54:50.354772 DQM Delay:
3869 11:54:50.354837 DQM0 = 38, DQM1 = 33
3870 11:54:50.357930 DQ Delay:
3871 11:54:50.361286 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
3872 11:54:50.364726 DQ4 =49, DQ5 =25, DQ6 =49, DQ7 =49
3873 11:54:50.367908 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
3874 11:54:50.371326 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
3875 11:54:50.371410
3876 11:54:50.371475
3877 11:54:50.371534 ==
3878 11:54:50.374540 Dram Type= 6, Freq= 0, CH_0, rank 0
3879 11:54:50.377826 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3880 11:54:50.377910 ==
3881 11:54:50.377975
3882 11:54:50.378034
3883 11:54:50.381203 TX Vref Scan disable
3884 11:54:50.384461 == TX Byte 0 ==
3885 11:54:50.387681 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3886 11:54:50.391102 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3887 11:54:50.394297 == TX Byte 1 ==
3888 11:54:50.397694 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3889 11:54:50.401047 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3890 11:54:50.401131 ==
3891 11:54:50.404249 Dram Type= 6, Freq= 0, CH_0, rank 0
3892 11:54:50.407612 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3893 11:54:50.411074 ==
3894 11:54:50.411162
3895 11:54:50.411228
3896 11:54:50.411286 TX Vref Scan disable
3897 11:54:50.414832 == TX Byte 0 ==
3898 11:54:50.418140 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
3899 11:54:50.424643 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
3900 11:54:50.424736 == TX Byte 1 ==
3901 11:54:50.427963 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
3902 11:54:50.434624 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
3903 11:54:50.434717
3904 11:54:50.434783 [DATLAT]
3905 11:54:50.434843 Freq=600, CH0 RK0
3906 11:54:50.434900
3907 11:54:50.438678 DATLAT Default: 0x9
3908 11:54:50.438761 0, 0xFFFF, sum = 0
3909 11:54:50.441291 1, 0xFFFF, sum = 0
3910 11:54:50.444450 2, 0xFFFF, sum = 0
3911 11:54:50.444558 3, 0xFFFF, sum = 0
3912 11:54:50.448210 4, 0xFFFF, sum = 0
3913 11:54:50.448323 5, 0xFFFF, sum = 0
3914 11:54:50.451425 6, 0xFFFF, sum = 0
3915 11:54:50.451553 7, 0x0, sum = 1
3916 11:54:50.451620 8, 0x0, sum = 2
3917 11:54:50.454492 9, 0x0, sum = 3
3918 11:54:50.454576 10, 0x0, sum = 4
3919 11:54:50.457912 best_step = 8
3920 11:54:50.457994
3921 11:54:50.458058 ==
3922 11:54:50.461160 Dram Type= 6, Freq= 0, CH_0, rank 0
3923 11:54:50.464422 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3924 11:54:50.464544 ==
3925 11:54:50.467785 RX Vref Scan: 1
3926 11:54:50.467869
3927 11:54:50.467935 RX Vref 0 -> 0, step: 1
3928 11:54:50.467996
3929 11:54:50.471080 RX Delay -195 -> 252, step: 8
3930 11:54:50.471162
3931 11:54:50.474410 Set Vref, RX VrefLevel [Byte0]: 47
3932 11:54:50.477608 [Byte1]: 47
3933 11:54:50.481766
3934 11:54:50.481853 Final RX Vref Byte 0 = 47 to rank0
3935 11:54:50.485064 Final RX Vref Byte 1 = 47 to rank0
3936 11:54:50.488473 Final RX Vref Byte 0 = 47 to rank1
3937 11:54:50.491869 Final RX Vref Byte 1 = 47 to rank1==
3938 11:54:50.495281 Dram Type= 6, Freq= 0, CH_0, rank 0
3939 11:54:50.501825 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3940 11:54:50.501921 ==
3941 11:54:50.501989 DQS Delay:
3942 11:54:50.502049 DQS0 = 0, DQS1 = 0
3943 11:54:50.505188 DQM Delay:
3944 11:54:50.505270 DQM0 = 39, DQM1 = 29
3945 11:54:50.508399 DQ Delay:
3946 11:54:50.511791 DQ0 =36, DQ1 =40, DQ2 =36, DQ3 =36
3947 11:54:50.515357 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =44
3948 11:54:50.515447 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
3949 11:54:50.521663 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =40
3950 11:54:50.521753
3951 11:54:50.521819
3952 11:54:50.528433 [DQSOSCAuto] RK0, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
3953 11:54:50.531785 CH0 RK0: MR19=808, MR18=5858
3954 11:54:50.538422 CH0_RK0: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
3955 11:54:50.538530
3956 11:54:50.541926 ----->DramcWriteLeveling(PI) begin...
3957 11:54:50.542012 ==
3958 11:54:50.545142 Dram Type= 6, Freq= 0, CH_0, rank 1
3959 11:54:50.548353 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3960 11:54:50.548466 ==
3961 11:54:50.551764 Write leveling (Byte 0): 31 => 31
3962 11:54:50.555079 Write leveling (Byte 1): 31 => 31
3963 11:54:50.558432 DramcWriteLeveling(PI) end<-----
3964 11:54:50.558514
3965 11:54:50.558578 ==
3966 11:54:50.561628 Dram Type= 6, Freq= 0, CH_0, rank 1
3967 11:54:50.565075 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
3968 11:54:50.565161 ==
3969 11:54:50.568423 [Gating] SW mode calibration
3970 11:54:50.574961 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 11:54:50.581747 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
3972 11:54:50.584914 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 11:54:50.588308 0 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 11:54:50.594963 0 5 8 | B1->B0 | 3131 3030 | 1 1 | (1 0) (1 0)
3975 11:54:50.598464 0 5 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3976 11:54:50.601737 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 11:54:50.608132 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 11:54:50.611574 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:54:50.614717 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:54:50.621313 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:54:50.624774 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:54:50.628204 0 6 8 | B1->B0 | 2b2b 3737 | 0 1 | (1 1) (1 1)
3983 11:54:50.634553 0 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3984 11:54:50.637812 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 11:54:50.641194 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:54:50.647861 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:54:50.651161 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:54:50.654548 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:54:50.660937 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:54:50.664496 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3991 11:54:50.667723 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:54:50.674582 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:54:50.677768 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:54:50.681087 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:54:50.687798 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:54:50.691003 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:54:50.694453 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:54:50.701151 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:54:50.704231 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:54:50.707600 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:54:50.714262 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:54:50.717484 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:54:50.720807 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:54:50.727789 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:54:50.730629 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:54:50.733957 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4007 11:54:50.740710 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4008 11:54:50.740796 Total UI for P1: 0, mck2ui 16
4009 11:54:50.747278 best dqsien dly found for B0: ( 0, 9, 8)
4010 11:54:50.747363 Total UI for P1: 0, mck2ui 16
4011 11:54:50.750456 best dqsien dly found for B1: ( 0, 9, 8)
4012 11:54:50.757266 best DQS0 dly(MCK, UI, PI) = (0, 9, 8)
4013 11:54:50.760625 best DQS1 dly(MCK, UI, PI) = (0, 9, 8)
4014 11:54:50.760708
4015 11:54:50.763780 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 8)
4016 11:54:50.767007 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 8)
4017 11:54:50.770345 [Gating] SW calibration Done
4018 11:54:50.770428 ==
4019 11:54:50.773833 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 11:54:50.776947 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4021 11:54:50.777031 ==
4022 11:54:50.780340 RX Vref Scan: 0
4023 11:54:50.780422
4024 11:54:50.780487 RX Vref 0 -> 0, step: 1
4025 11:54:50.780556
4026 11:54:50.783862 RX Delay -230 -> 252, step: 16
4027 11:54:50.786926 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4028 11:54:50.793636 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4029 11:54:50.797092 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4030 11:54:50.800666 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4031 11:54:50.803636 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4032 11:54:50.810594 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4033 11:54:50.813847 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4034 11:54:50.816815 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4035 11:54:50.820058 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4036 11:54:50.823522 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4037 11:54:50.829942 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4038 11:54:50.833265 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4039 11:54:50.836467 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4040 11:54:50.840055 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4041 11:54:50.846571 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4042 11:54:50.850048 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4043 11:54:50.850131 ==
4044 11:54:50.853480 Dram Type= 6, Freq= 0, CH_0, rank 1
4045 11:54:50.856810 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4046 11:54:50.856893 ==
4047 11:54:50.859657 DQS Delay:
4048 11:54:50.859739 DQS0 = 0, DQS1 = 0
4049 11:54:50.859803 DQM Delay:
4050 11:54:50.863162 DQM0 = 42, DQM1 = 33
4051 11:54:50.863299 DQ Delay:
4052 11:54:50.866278 DQ0 =33, DQ1 =49, DQ2 =41, DQ3 =33
4053 11:54:50.869786 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4054 11:54:50.873152 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4055 11:54:50.876388 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4056 11:54:50.876497
4057 11:54:50.876591
4058 11:54:50.876672 ==
4059 11:54:50.879593 Dram Type= 6, Freq= 0, CH_0, rank 1
4060 11:54:50.886412 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4061 11:54:50.886498 ==
4062 11:54:50.886583
4063 11:54:50.886663
4064 11:54:50.886741 TX Vref Scan disable
4065 11:54:50.890000 == TX Byte 0 ==
4066 11:54:50.893520 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4067 11:54:50.900038 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4068 11:54:50.900123 == TX Byte 1 ==
4069 11:54:50.903466 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4070 11:54:50.909895 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4071 11:54:50.909978 ==
4072 11:54:50.913338 Dram Type= 6, Freq= 0, CH_0, rank 1
4073 11:54:50.916874 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4074 11:54:50.916959 ==
4075 11:54:50.917043
4076 11:54:50.917122
4077 11:54:50.920229 TX Vref Scan disable
4078 11:54:50.920337 == TX Byte 0 ==
4079 11:54:50.926523 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4080 11:54:50.930113 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4081 11:54:50.933306 == TX Byte 1 ==
4082 11:54:50.936349 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4083 11:54:50.939658 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4084 11:54:50.939742
4085 11:54:50.939827 [DATLAT]
4086 11:54:50.942874 Freq=600, CH0 RK1
4087 11:54:50.942958
4088 11:54:50.946312 DATLAT Default: 0x8
4089 11:54:50.946395 0, 0xFFFF, sum = 0
4090 11:54:50.949580 1, 0xFFFF, sum = 0
4091 11:54:50.949665 2, 0xFFFF, sum = 0
4092 11:54:50.952885 3, 0xFFFF, sum = 0
4093 11:54:50.952968 4, 0xFFFF, sum = 0
4094 11:54:50.956224 5, 0xFFFF, sum = 0
4095 11:54:50.956308 6, 0xFFFF, sum = 0
4096 11:54:50.959641 7, 0x0, sum = 1
4097 11:54:50.959717 8, 0x0, sum = 2
4098 11:54:50.959814 9, 0x0, sum = 3
4099 11:54:50.962940 10, 0x0, sum = 4
4100 11:54:50.963023 best_step = 8
4101 11:54:50.963122
4102 11:54:50.963218 ==
4103 11:54:50.966275 Dram Type= 6, Freq= 0, CH_0, rank 1
4104 11:54:50.972769 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4105 11:54:50.972851 ==
4106 11:54:50.972935 RX Vref Scan: 0
4107 11:54:50.973013
4108 11:54:50.976052 RX Vref 0 -> 0, step: 1
4109 11:54:50.976133
4110 11:54:50.979460 RX Delay -195 -> 252, step: 8
4111 11:54:50.986218 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4112 11:54:50.989228 iDelay=205, Bit 1, Center 48 (-107 ~ 204) 312
4113 11:54:50.992828 iDelay=205, Bit 2, Center 40 (-115 ~ 196) 312
4114 11:54:50.995994 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4115 11:54:50.999441 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4116 11:54:51.005823 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4117 11:54:51.009264 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4118 11:54:51.012385 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4119 11:54:51.016012 iDelay=205, Bit 8, Center 20 (-131 ~ 172) 304
4120 11:54:51.022505 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4121 11:54:51.025905 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4122 11:54:51.029073 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4123 11:54:51.032394 iDelay=205, Bit 12, Center 36 (-115 ~ 188) 304
4124 11:54:51.038952 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4125 11:54:51.042461 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4126 11:54:51.045568 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4127 11:54:51.045651 ==
4128 11:54:51.048954 Dram Type= 6, Freq= 0, CH_0, rank 1
4129 11:54:51.052474 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4130 11:54:51.052574 ==
4131 11:54:51.055487 DQS Delay:
4132 11:54:51.055570 DQS0 = 0, DQS1 = 0
4133 11:54:51.058791 DQM Delay:
4134 11:54:51.058875 DQM0 = 40, DQM1 = 32
4135 11:54:51.058960 DQ Delay:
4136 11:54:51.062085 DQ0 =36, DQ1 =48, DQ2 =40, DQ3 =36
4137 11:54:51.065497 DQ4 =40, DQ5 =32, DQ6 =44, DQ7 =48
4138 11:54:51.068855 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4139 11:54:51.072191 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =44
4140 11:54:51.072275
4141 11:54:51.072375
4142 11:54:51.081952 [DQSOSCAuto] RK1, (LSB)MR18= 0x6464, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 391 ps
4143 11:54:51.085306 CH0 RK1: MR19=808, MR18=6464
4144 11:54:51.092079 CH0_RK1: MR19=0x808, MR18=0x6464, DQSOSC=391, MR23=63, INC=171, DEC=114
4145 11:54:51.092164 [RxdqsGatingPostProcess] freq 600
4146 11:54:51.098533 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4147 11:54:51.101874 Pre-setting of DQS Precalculation
4148 11:54:51.105330 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4149 11:54:51.108441 ==
4150 11:54:51.112125 Dram Type= 6, Freq= 0, CH_1, rank 0
4151 11:54:51.115206 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4152 11:54:51.115289 ==
4153 11:54:51.118357 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4154 11:54:51.125510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4155 11:54:51.129060 [CA 0] Center 35 (5~66) winsize 62
4156 11:54:51.132338 [CA 1] Center 35 (5~66) winsize 62
4157 11:54:51.135743 [CA 2] Center 33 (3~64) winsize 62
4158 11:54:51.138958 [CA 3] Center 33 (3~64) winsize 62
4159 11:54:51.142274 [CA 4] Center 32 (1~64) winsize 64
4160 11:54:51.145637 [CA 5] Center 32 (2~63) winsize 62
4161 11:54:51.145718
4162 11:54:51.148890 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4163 11:54:51.148971
4164 11:54:51.152274 [CATrainingPosCal] consider 1 rank data
4165 11:54:51.155715 u2DelayCellTimex100 = 270/100 ps
4166 11:54:51.158631 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4167 11:54:51.165377 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4168 11:54:51.168665 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4169 11:54:51.172017 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4170 11:54:51.175340 CA4 delay=32 (1~64),Diff = 0 PI (0 cell)
4171 11:54:51.178974 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4172 11:54:51.179055
4173 11:54:51.181970 CA PerBit enable=1, Macro0, CA PI delay=32
4174 11:54:51.182051
4175 11:54:51.185507 [CBTSetCACLKResult] CA Dly = 32
4176 11:54:51.185588 CS Dly: 3 (0~34)
4177 11:54:51.188543 ==
4178 11:54:51.188638 Dram Type= 6, Freq= 0, CH_1, rank 1
4179 11:54:51.195399 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4180 11:54:51.195481 ==
4181 11:54:51.198463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4182 11:54:51.205069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4183 11:54:51.208872 [CA 0] Center 35 (5~66) winsize 62
4184 11:54:51.212293 [CA 1] Center 34 (4~65) winsize 62
4185 11:54:51.215433 [CA 2] Center 33 (3~64) winsize 62
4186 11:54:51.218979 [CA 3] Center 33 (3~64) winsize 62
4187 11:54:51.222230 [CA 4] Center 32 (2~63) winsize 62
4188 11:54:51.225488 [CA 5] Center 33 (2~64) winsize 63
4189 11:54:51.225569
4190 11:54:51.228726 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4191 11:54:51.228808
4192 11:54:51.232283 [CATrainingPosCal] consider 2 rank data
4193 11:54:51.235735 u2DelayCellTimex100 = 270/100 ps
4194 11:54:51.238700 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4195 11:54:51.245350 CA1 delay=35 (5~65),Diff = 3 PI (28 cell)
4196 11:54:51.248639 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4197 11:54:51.251915 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4198 11:54:51.255247 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
4199 11:54:51.258565 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4200 11:54:51.258646
4201 11:54:51.261726 CA PerBit enable=1, Macro0, CA PI delay=32
4202 11:54:51.261807
4203 11:54:51.265202 [CBTSetCACLKResult] CA Dly = 32
4204 11:54:51.265283 CS Dly: 3 (0~35)
4205 11:54:51.268481
4206 11:54:51.271777 ----->DramcWriteLeveling(PI) begin...
4207 11:54:51.271859 ==
4208 11:54:51.275093 Dram Type= 6, Freq= 0, CH_1, rank 0
4209 11:54:51.278477 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4210 11:54:51.278559 ==
4211 11:54:51.281751 Write leveling (Byte 0): 28 => 28
4212 11:54:51.285030 Write leveling (Byte 1): 27 => 27
4213 11:54:51.288381 DramcWriteLeveling(PI) end<-----
4214 11:54:51.288461
4215 11:54:51.288531 ==
4216 11:54:51.291510 Dram Type= 6, Freq= 0, CH_1, rank 0
4217 11:54:51.294955 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4218 11:54:51.295037 ==
4219 11:54:51.298124 [Gating] SW mode calibration
4220 11:54:51.305091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4221 11:54:51.311468 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4222 11:54:51.314767 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4223 11:54:51.317994 0 5 4 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4224 11:54:51.324632 0 5 8 | B1->B0 | 2f2f 2b2b | 1 0 | (1 0) (0 0)
4225 11:54:51.327960 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:54:51.331440 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 11:54:51.337994 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 11:54:51.341219 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 11:54:51.344757 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4230 11:54:51.351146 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4231 11:54:51.354535 0 6 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4232 11:54:51.358020 0 6 8 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
4233 11:54:51.364448 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:54:51.367653 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:54:51.371213 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:54:51.377825 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:54:51.380938 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4238 11:54:51.384137 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4239 11:54:51.390875 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4240 11:54:51.394138 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4241 11:54:51.397338 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:54:51.404064 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:54:51.407472 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:54:51.410696 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:54:51.417633 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:54:51.420706 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:54:51.423739 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:54:51.430484 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:54:51.433735 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:54:51.437265 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:54:51.443690 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:54:51.447171 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:54:51.450172 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:54:51.456817 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:54:51.460182 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4256 11:54:51.463393 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4257 11:54:51.469944 0 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:54:51.470026 Total UI for P1: 0, mck2ui 16
4259 11:54:51.473331 best dqsien dly found for B0: ( 0, 9, 6)
4260 11:54:51.476737 Total UI for P1: 0, mck2ui 16
4261 11:54:51.479973 best dqsien dly found for B1: ( 0, 9, 10)
4262 11:54:51.486416 best DQS0 dly(MCK, UI, PI) = (0, 9, 6)
4263 11:54:51.489869 best DQS1 dly(MCK, UI, PI) = (0, 9, 10)
4264 11:54:51.489949
4265 11:54:51.493062 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 6)
4266 11:54:51.496486 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 10)
4267 11:54:51.499710 [Gating] SW calibration Done
4268 11:54:51.499794 ==
4269 11:54:51.502973 Dram Type= 6, Freq= 0, CH_1, rank 0
4270 11:54:51.506336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4271 11:54:51.506417 ==
4272 11:54:51.509553 RX Vref Scan: 0
4273 11:54:51.509633
4274 11:54:51.509696 RX Vref 0 -> 0, step: 1
4275 11:54:51.509755
4276 11:54:51.513187 RX Delay -230 -> 252, step: 16
4277 11:54:51.516206 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4278 11:54:51.522868 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4279 11:54:51.526119 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4280 11:54:51.529595 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4281 11:54:51.532802 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4282 11:54:51.539361 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4283 11:54:51.543026 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4284 11:54:51.545979 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4285 11:54:51.549372 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4286 11:54:51.555876 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4287 11:54:51.559235 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4288 11:54:51.562492 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4289 11:54:51.565991 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4290 11:54:51.569184 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4291 11:54:51.575927 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4292 11:54:51.579049 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4293 11:54:51.579131 ==
4294 11:54:51.582756 Dram Type= 6, Freq= 0, CH_1, rank 0
4295 11:54:51.585677 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4296 11:54:51.585758 ==
4297 11:54:51.588948 DQS Delay:
4298 11:54:51.589028 DQS0 = 0, DQS1 = 0
4299 11:54:51.592386 DQM Delay:
4300 11:54:51.592492 DQM0 = 38, DQM1 = 32
4301 11:54:51.592573 DQ Delay:
4302 11:54:51.595745 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4303 11:54:51.599168 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4304 11:54:51.602366 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4305 11:54:51.605841 DQ12 =41, DQ13 =49, DQ14 =33, DQ15 =49
4306 11:54:51.605927
4307 11:54:51.605990
4308 11:54:51.606050 ==
4309 11:54:51.608842 Dram Type= 6, Freq= 0, CH_1, rank 0
4310 11:54:51.615452 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4311 11:54:51.615563 ==
4312 11:54:51.615656
4313 11:54:51.615744
4314 11:54:51.619054 TX Vref Scan disable
4315 11:54:51.619138 == TX Byte 0 ==
4316 11:54:51.622222 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4317 11:54:51.628707 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4318 11:54:51.628789 == TX Byte 1 ==
4319 11:54:51.632019 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4320 11:54:51.638775 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4321 11:54:51.638856 ==
4322 11:54:51.642183 Dram Type= 6, Freq= 0, CH_1, rank 0
4323 11:54:51.645538 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4324 11:54:51.645620 ==
4325 11:54:51.645684
4326 11:54:51.645743
4327 11:54:51.648781 TX Vref Scan disable
4328 11:54:51.652199 == TX Byte 0 ==
4329 11:54:51.655349 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4330 11:54:51.658740 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4331 11:54:51.662220 == TX Byte 1 ==
4332 11:54:51.665372 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4333 11:54:51.668544 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4334 11:54:51.668642
4335 11:54:51.672063 [DATLAT]
4336 11:54:51.672144 Freq=600, CH1 RK0
4337 11:54:51.672208
4338 11:54:51.675361 DATLAT Default: 0x9
4339 11:54:51.675441 0, 0xFFFF, sum = 0
4340 11:54:51.678706 1, 0xFFFF, sum = 0
4341 11:54:51.678788 2, 0xFFFF, sum = 0
4342 11:54:51.681798 3, 0xFFFF, sum = 0
4343 11:54:51.681880 4, 0xFFFF, sum = 0
4344 11:54:51.685301 5, 0xFFFF, sum = 0
4345 11:54:51.685382 6, 0xFFFF, sum = 0
4346 11:54:51.688444 7, 0x0, sum = 1
4347 11:54:51.688587 8, 0x0, sum = 2
4348 11:54:51.691734 9, 0x0, sum = 3
4349 11:54:51.691814 10, 0x0, sum = 4
4350 11:54:51.691879 best_step = 8
4351 11:54:51.695284
4352 11:54:51.695364 ==
4353 11:54:51.698518 Dram Type= 6, Freq= 0, CH_1, rank 0
4354 11:54:51.701761 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4355 11:54:51.701842 ==
4356 11:54:51.701905 RX Vref Scan: 1
4357 11:54:51.701965
4358 11:54:51.705330 RX Vref 0 -> 0, step: 1
4359 11:54:51.705410
4360 11:54:51.708327 RX Delay -195 -> 252, step: 8
4361 11:54:51.708406
4362 11:54:51.711720 Set Vref, RX VrefLevel [Byte0]: 58
4363 11:54:51.714895 [Byte1]: 51
4364 11:54:51.718193
4365 11:54:51.718273 Final RX Vref Byte 0 = 58 to rank0
4366 11:54:51.721703 Final RX Vref Byte 1 = 51 to rank0
4367 11:54:51.724958 Final RX Vref Byte 0 = 58 to rank1
4368 11:54:51.728075 Final RX Vref Byte 1 = 51 to rank1==
4369 11:54:51.731444 Dram Type= 6, Freq= 0, CH_1, rank 0
4370 11:54:51.738288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4371 11:54:51.738370 ==
4372 11:54:51.738434 DQS Delay:
4373 11:54:51.738493 DQS0 = 0, DQS1 = 0
4374 11:54:51.741307 DQM Delay:
4375 11:54:51.741387 DQM0 = 37, DQM1 = 31
4376 11:54:51.744832 DQ Delay:
4377 11:54:51.747919 DQ0 =44, DQ1 =28, DQ2 =28, DQ3 =36
4378 11:54:51.751401 DQ4 =36, DQ5 =44, DQ6 =44, DQ7 =36
4379 11:54:51.754781 DQ8 =12, DQ9 =20, DQ10 =36, DQ11 =24
4380 11:54:51.758003 DQ12 =40, DQ13 =40, DQ14 =36, DQ15 =40
4381 11:54:51.758085
4382 11:54:51.758148
4383 11:54:51.764621 [DQSOSCAuto] RK0, (LSB)MR18= 0x7676, (MSB)MR19= 0x808, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
4384 11:54:51.768107 CH1 RK0: MR19=808, MR18=7676
4385 11:54:51.774647 CH1_RK0: MR19=0x808, MR18=0x7676, DQSOSC=387, MR23=63, INC=175, DEC=116
4386 11:54:51.774729
4387 11:54:51.777958 ----->DramcWriteLeveling(PI) begin...
4388 11:54:51.778040 ==
4389 11:54:51.781122 Dram Type= 6, Freq= 0, CH_1, rank 1
4390 11:54:51.784391 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4391 11:54:51.784498 ==
4392 11:54:51.787919 Write leveling (Byte 0): 29 => 29
4393 11:54:51.791231 Write leveling (Byte 1): 28 => 28
4394 11:54:51.794681 DramcWriteLeveling(PI) end<-----
4395 11:54:51.794761
4396 11:54:51.794825 ==
4397 11:54:51.797831 Dram Type= 6, Freq= 0, CH_1, rank 1
4398 11:54:51.801222 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4399 11:54:51.801304 ==
4400 11:54:51.804615 [Gating] SW mode calibration
4401 11:54:51.810979 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4402 11:54:51.817722 RX_Path_delay_UI(21) -3 - DQSINCTL_UI(16) = u1StartUI(5)
4403 11:54:51.821088 0 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4404 11:54:51.827575 0 5 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
4405 11:54:51.831006 0 5 8 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4406 11:54:51.834321 0 5 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4407 11:54:51.840877 0 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4408 11:54:51.844108 0 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4409 11:54:51.847408 0 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4410 11:54:51.854200 0 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4411 11:54:51.857431 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 11:54:51.860702 0 6 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
4413 11:54:51.864029 0 6 8 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
4414 11:54:51.870730 0 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4415 11:54:51.874016 0 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4416 11:54:51.877237 0 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4417 11:54:51.884103 0 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4418 11:54:51.887441 0 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 11:54:51.890691 0 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4420 11:54:51.897332 0 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 11:54:51.900525 0 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4422 11:54:51.903935 0 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4423 11:54:51.910402 0 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4424 11:54:51.914001 0 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4425 11:54:51.916928 0 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4426 11:54:51.923585 0 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:54:51.926947 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 11:54:51.930188 0 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:54:51.936927 0 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:54:51.940296 0 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:54:51.943459 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:54:51.950337 0 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:54:51.953509 0 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:54:51.956790 0 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:54:51.963445 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:54:51.966783 0 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4437 11:54:51.970072 0 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:54:51.973385 Total UI for P1: 0, mck2ui 16
4439 11:54:51.976723 best dqsien dly found for B0: ( 0, 9, 4)
4440 11:54:51.980045 Total UI for P1: 0, mck2ui 16
4441 11:54:51.983247 best dqsien dly found for B1: ( 0, 9, 6)
4442 11:54:51.986574 best DQS0 dly(MCK, UI, PI) = (0, 9, 4)
4443 11:54:51.989959 best DQS1 dly(MCK, UI, PI) = (0, 9, 6)
4444 11:54:51.990044
4445 11:54:51.996631 best DQS0 P1 dly(MCK, UI, PI) = (0, 13, 4)
4446 11:54:51.999758 best DQS1 P1 dly(MCK, UI, PI) = (0, 13, 6)
4447 11:54:51.999842 [Gating] SW calibration Done
4448 11:54:52.003423 ==
4449 11:54:52.006783 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 11:54:52.009526 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4451 11:54:52.009611 ==
4452 11:54:52.009697 RX Vref Scan: 0
4453 11:54:52.009777
4454 11:54:52.012870 RX Vref 0 -> 0, step: 1
4455 11:54:52.012955
4456 11:54:52.016068 RX Delay -230 -> 252, step: 16
4457 11:54:52.019526 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4458 11:54:52.022732 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4459 11:54:52.029526 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4460 11:54:52.032924 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4461 11:54:52.036219 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4462 11:54:52.039347 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4463 11:54:52.045979 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4464 11:54:52.049298 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4465 11:54:52.052526 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4466 11:54:52.056234 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4467 11:54:52.059302 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4468 11:54:52.065873 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4469 11:54:52.069206 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4470 11:54:52.072387 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4471 11:54:52.075775 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4472 11:54:52.082409 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4473 11:54:52.082492 ==
4474 11:54:52.085767 Dram Type= 6, Freq= 0, CH_1, rank 1
4475 11:54:52.088986 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4476 11:54:52.089074 ==
4477 11:54:52.089139 DQS Delay:
4478 11:54:52.092229 DQS0 = 0, DQS1 = 0
4479 11:54:52.092311 DQM Delay:
4480 11:54:52.095724 DQM0 = 41, DQM1 = 34
4481 11:54:52.095805 DQ Delay:
4482 11:54:52.098989 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =41
4483 11:54:52.102541 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4484 11:54:52.105752 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4485 11:54:52.109042 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4486 11:54:52.109124
4487 11:54:52.109187
4488 11:54:52.109247 ==
4489 11:54:52.112151 Dram Type= 6, Freq= 0, CH_1, rank 1
4490 11:54:52.115312 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4491 11:54:52.118708 ==
4492 11:54:52.118791
4493 11:54:52.118856
4494 11:54:52.118916 TX Vref Scan disable
4495 11:54:52.121989 == TX Byte 0 ==
4496 11:54:52.125510 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4497 11:54:52.132177 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4498 11:54:52.132264 == TX Byte 1 ==
4499 11:54:52.135319 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4500 11:54:52.141977 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4501 11:54:52.142062 ==
4502 11:54:52.145088 Dram Type= 6, Freq= 0, CH_1, rank 1
4503 11:54:52.148550 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4504 11:54:52.148646 ==
4505 11:54:52.148712
4506 11:54:52.148773
4507 11:54:52.151940 TX Vref Scan disable
4508 11:54:52.155210 == TX Byte 0 ==
4509 11:54:52.158566 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4510 11:54:52.161931 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4511 11:54:52.165039 == TX Byte 1 ==
4512 11:54:52.168439 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4513 11:54:52.171682 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4514 11:54:52.171763
4515 11:54:52.171828 [DATLAT]
4516 11:54:52.174964 Freq=600, CH1 RK1
4517 11:54:52.175045
4518 11:54:52.178211 DATLAT Default: 0x8
4519 11:54:52.178291 0, 0xFFFF, sum = 0
4520 11:54:52.181613 1, 0xFFFF, sum = 0
4521 11:54:52.181696 2, 0xFFFF, sum = 0
4522 11:54:52.185117 3, 0xFFFF, sum = 0
4523 11:54:52.185199 4, 0xFFFF, sum = 0
4524 11:54:52.188346 5, 0xFFFF, sum = 0
4525 11:54:52.188429 6, 0xFFFF, sum = 0
4526 11:54:52.191547 7, 0x0, sum = 1
4527 11:54:52.191629 8, 0x0, sum = 2
4528 11:54:52.191696 9, 0x0, sum = 3
4529 11:54:52.194943 10, 0x0, sum = 4
4530 11:54:52.195025 best_step = 8
4531 11:54:52.195088
4532 11:54:52.195147 ==
4533 11:54:52.198376 Dram Type= 6, Freq= 0, CH_1, rank 1
4534 11:54:52.204762 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4535 11:54:52.204846 ==
4536 11:54:52.204911 RX Vref Scan: 0
4537 11:54:52.204971
4538 11:54:52.208136 RX Vref 0 -> 0, step: 1
4539 11:54:52.208217
4540 11:54:52.211323 RX Delay -195 -> 252, step: 8
4541 11:54:52.214733 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4542 11:54:52.221352 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4543 11:54:52.224664 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4544 11:54:52.227939 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4545 11:54:52.231401 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4546 11:54:52.237785 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4547 11:54:52.241338 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4548 11:54:52.244418 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4549 11:54:52.247753 iDelay=205, Bit 8, Center 12 (-147 ~ 172) 320
4550 11:54:52.254426 iDelay=205, Bit 9, Center 16 (-147 ~ 180) 328
4551 11:54:52.257782 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4552 11:54:52.261104 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4553 11:54:52.264364 iDelay=205, Bit 12, Center 44 (-115 ~ 204) 320
4554 11:54:52.267660 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4555 11:54:52.274321 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4556 11:54:52.277606 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4557 11:54:52.277688 ==
4558 11:54:52.280908 Dram Type= 6, Freq= 0, CH_1, rank 1
4559 11:54:52.284365 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4560 11:54:52.284446 ==
4561 11:54:52.287803 DQS Delay:
4562 11:54:52.287883 DQS0 = 0, DQS1 = 0
4563 11:54:52.291104 DQM Delay:
4564 11:54:52.291185 DQM0 = 37, DQM1 = 29
4565 11:54:52.291249 DQ Delay:
4566 11:54:52.294299 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4567 11:54:52.297421 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =36
4568 11:54:52.301238 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4569 11:54:52.304216 DQ12 =44, DQ13 =40, DQ14 =36, DQ15 =40
4570 11:54:52.304297
4571 11:54:52.304360
4572 11:54:52.313968 [DQSOSCAuto] RK1, (LSB)MR18= 0x5858, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
4573 11:54:52.317315 CH1 RK1: MR19=808, MR18=5858
4574 11:54:52.324007 CH1_RK1: MR19=0x808, MR18=0x5858, DQSOSC=393, MR23=63, INC=169, DEC=113
4575 11:54:52.324100 [RxdqsGatingPostProcess] freq 600
4576 11:54:52.330627 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4577 11:54:52.333940 Pre-setting of DQS Precalculation
4578 11:54:52.337103 [DualRankRxdatlatCal] RK0: 8, RK1: 8, Final_Datlat 8
4579 11:54:52.347254 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4580 11:54:52.353667 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4581 11:54:52.353756
4582 11:54:52.353840
4583 11:54:52.357010 [Calibration Summary] 1200 Mbps
4584 11:54:52.357093 CH 0, Rank 0
4585 11:54:52.360428 SW Impedance : PASS
4586 11:54:52.360573 DUTY Scan : NO K
4587 11:54:52.363634 ZQ Calibration : PASS
4588 11:54:52.367024 Jitter Meter : NO K
4589 11:54:52.367105 CBT Training : PASS
4590 11:54:52.370347 Write leveling : PASS
4591 11:54:52.373658 RX DQS gating : PASS
4592 11:54:52.373739 RX DQ/DQS(RDDQC) : PASS
4593 11:54:52.377116 TX DQ/DQS : PASS
4594 11:54:52.380377 RX DATLAT : PASS
4595 11:54:52.380484 RX DQ/DQS(Engine): PASS
4596 11:54:52.383645 TX OE : NO K
4597 11:54:52.383726 All Pass.
4598 11:54:52.383790
4599 11:54:52.387040 CH 0, Rank 1
4600 11:54:52.387120 SW Impedance : PASS
4601 11:54:52.390259 DUTY Scan : NO K
4602 11:54:52.393987 ZQ Calibration : PASS
4603 11:54:52.394102 Jitter Meter : NO K
4604 11:54:52.397250 CBT Training : PASS
4605 11:54:52.400226 Write leveling : PASS
4606 11:54:52.400331 RX DQS gating : PASS
4607 11:54:52.403696 RX DQ/DQS(RDDQC) : PASS
4608 11:54:52.403777 TX DQ/DQS : PASS
4609 11:54:52.407211 RX DATLAT : PASS
4610 11:54:52.410353 RX DQ/DQS(Engine): PASS
4611 11:54:52.410434 TX OE : NO K
4612 11:54:52.413487 All Pass.
4613 11:54:52.413568
4614 11:54:52.413632 CH 1, Rank 0
4615 11:54:52.416999 SW Impedance : PASS
4616 11:54:52.417080 DUTY Scan : NO K
4617 11:54:52.420323 ZQ Calibration : PASS
4618 11:54:52.423815 Jitter Meter : NO K
4619 11:54:52.423922 CBT Training : PASS
4620 11:54:52.426804 Write leveling : PASS
4621 11:54:52.430314 RX DQS gating : PASS
4622 11:54:52.430394 RX DQ/DQS(RDDQC) : PASS
4623 11:54:52.433381 TX DQ/DQS : PASS
4624 11:54:52.437085 RX DATLAT : PASS
4625 11:54:52.437165 RX DQ/DQS(Engine): PASS
4626 11:54:52.440102 TX OE : NO K
4627 11:54:52.440183 All Pass.
4628 11:54:52.440247
4629 11:54:52.443423 CH 1, Rank 1
4630 11:54:52.443504 SW Impedance : PASS
4631 11:54:52.446627 DUTY Scan : NO K
4632 11:54:52.449963 ZQ Calibration : PASS
4633 11:54:52.450044 Jitter Meter : NO K
4634 11:54:52.453336 CBT Training : PASS
4635 11:54:52.453416 Write leveling : PASS
4636 11:54:52.456919 RX DQS gating : PASS
4637 11:54:52.459913 RX DQ/DQS(RDDQC) : PASS
4638 11:54:52.459994 TX DQ/DQS : PASS
4639 11:54:52.463314 RX DATLAT : PASS
4640 11:54:52.466682 RX DQ/DQS(Engine): PASS
4641 11:54:52.466764 TX OE : NO K
4642 11:54:52.470141 All Pass.
4643 11:54:52.470232
4644 11:54:52.470303 DramC Write-DBI off
4645 11:54:52.473263 PER_BANK_REFRESH: Hybrid Mode
4646 11:54:52.476375 TX_TRACKING: ON
4647 11:54:52.482964 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4648 11:54:52.486346 [FAST_K] Save calibration result to emmc
4649 11:54:52.489749 dramc_set_vcore_voltage set vcore to 662500
4650 11:54:52.493019 Read voltage for 933, 3
4651 11:54:52.493100 Vio18 = 0
4652 11:54:52.496457 Vcore = 662500
4653 11:54:52.496560 Vdram = 0
4654 11:54:52.496625 Vddq = 0
4655 11:54:52.499499 Vmddr = 0
4656 11:54:52.503023 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4657 11:54:52.509902 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4658 11:54:52.509986 MEM_TYPE=3, freq_sel=17
4659 11:54:52.512885 sv_algorithm_assistance_LP4_1600
4660 11:54:52.519469 ============ PULL DRAM RESETB DOWN ============
4661 11:54:52.522797 ========== PULL DRAM RESETB DOWN end =========
4662 11:54:52.526346 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4663 11:54:52.529647 ===================================
4664 11:54:52.532892 LPDDR4 DRAM CONFIGURATION
4665 11:54:52.536064 ===================================
4666 11:54:52.539629 EX_ROW_EN[0] = 0x0
4667 11:54:52.539713 EX_ROW_EN[1] = 0x0
4668 11:54:52.542927 LP4Y_EN = 0x0
4669 11:54:52.543010 WORK_FSP = 0x0
4670 11:54:52.546008 WL = 0x3
4671 11:54:52.546091 RL = 0x3
4672 11:54:52.549278 BL = 0x2
4673 11:54:52.549362 RPST = 0x0
4674 11:54:52.552918 RD_PRE = 0x0
4675 11:54:52.553002 WR_PRE = 0x1
4676 11:54:52.556015 WR_PST = 0x0
4677 11:54:52.556098 DBI_WR = 0x0
4678 11:54:52.559209 DBI_RD = 0x0
4679 11:54:52.559292 OTF = 0x1
4680 11:54:52.562885 ===================================
4681 11:54:52.566123 ===================================
4682 11:54:52.569257 ANA top config
4683 11:54:52.572537 ===================================
4684 11:54:52.575944 DLL_ASYNC_EN = 0
4685 11:54:52.576028 ALL_SLAVE_EN = 1
4686 11:54:52.579448 NEW_RANK_MODE = 1
4687 11:54:52.582500 DLL_IDLE_MODE = 1
4688 11:54:52.585773 LP45_APHY_COMB_EN = 1
4689 11:54:52.585857 TX_ODT_DIS = 1
4690 11:54:52.589138 NEW_8X_MODE = 1
4691 11:54:52.592440 ===================================
4692 11:54:52.595922 ===================================
4693 11:54:52.599065 data_rate = 1866
4694 11:54:52.602421 CKR = 1
4695 11:54:52.605840 DQ_P2S_RATIO = 8
4696 11:54:52.609135 ===================================
4697 11:54:52.612256 CA_P2S_RATIO = 8
4698 11:54:52.612339 DQ_CA_OPEN = 0
4699 11:54:52.615668 DQ_SEMI_OPEN = 0
4700 11:54:52.618919 CA_SEMI_OPEN = 0
4701 11:54:52.622302 CA_FULL_RATE = 0
4702 11:54:52.625488 DQ_CKDIV4_EN = 1
4703 11:54:52.628783 CA_CKDIV4_EN = 1
4704 11:54:52.628868 CA_PREDIV_EN = 0
4705 11:54:52.632188 PH8_DLY = 0
4706 11:54:52.635354 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4707 11:54:52.638854 DQ_AAMCK_DIV = 4
4708 11:54:52.642664 CA_AAMCK_DIV = 4
4709 11:54:52.645506 CA_ADMCK_DIV = 4
4710 11:54:52.645587 DQ_TRACK_CA_EN = 0
4711 11:54:52.648558 CA_PICK = 933
4712 11:54:52.651845 CA_MCKIO = 933
4713 11:54:52.655275 MCKIO_SEMI = 0
4714 11:54:52.658588 PLL_FREQ = 3732
4715 11:54:52.661840 DQ_UI_PI_RATIO = 32
4716 11:54:52.665139 CA_UI_PI_RATIO = 0
4717 11:54:52.668473 ===================================
4718 11:54:52.671991 ===================================
4719 11:54:52.672073 memory_type:LPDDR4
4720 11:54:52.675309 GP_NUM : 10
4721 11:54:52.678472 SRAM_EN : 1
4722 11:54:52.678554 MD32_EN : 0
4723 11:54:52.681829 ===================================
4724 11:54:52.685426 [ANA_INIT] >>>>>>>>>>>>>>
4725 11:54:52.688479 <<<<<< [CONFIGURE PHASE]: ANA_TX
4726 11:54:52.692051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4727 11:54:52.695236 ===================================
4728 11:54:52.698626 data_rate = 1866,PCW = 0X8f00
4729 11:54:52.701820 ===================================
4730 11:54:52.705235 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4731 11:54:52.708857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4732 11:54:52.715326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4733 11:54:52.718554 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4734 11:54:52.722319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4735 11:54:52.725350 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4736 11:54:52.728539 [ANA_INIT] flow start
4737 11:54:52.732007 [ANA_INIT] PLL >>>>>>>>
4738 11:54:52.732089 [ANA_INIT] PLL <<<<<<<<
4739 11:54:52.735187 [ANA_INIT] MIDPI >>>>>>>>
4740 11:54:52.738352 [ANA_INIT] MIDPI <<<<<<<<
4741 11:54:52.738432 [ANA_INIT] DLL >>>>>>>>
4742 11:54:52.741666 [ANA_INIT] flow end
4743 11:54:52.745004 ============ LP4 DIFF to SE enter ============
4744 11:54:52.751748 ============ LP4 DIFF to SE exit ============
4745 11:54:52.751831 [ANA_INIT] <<<<<<<<<<<<<
4746 11:54:52.755068 [Flow] Enable top DCM control >>>>>
4747 11:54:52.758310 [Flow] Enable top DCM control <<<<<
4748 11:54:52.761634 Enable DLL master slave shuffle
4749 11:54:52.768298 ==============================================================
4750 11:54:52.768381 Gating Mode config
4751 11:54:52.775032 ==============================================================
4752 11:54:52.778232 Config description:
4753 11:54:52.785129 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4754 11:54:52.791555 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4755 11:54:52.798234 SELPH_MODE 0: By rank 1: By Phase
4756 11:54:52.804582 ==============================================================
4757 11:54:52.808049 GAT_TRACK_EN = 1
4758 11:54:52.808131 RX_GATING_MODE = 2
4759 11:54:52.811393 RX_GATING_TRACK_MODE = 2
4760 11:54:52.814676 SELPH_MODE = 1
4761 11:54:52.817971 PICG_EARLY_EN = 1
4762 11:54:52.821443 VALID_LAT_VALUE = 1
4763 11:54:52.828248 ==============================================================
4764 11:54:52.831398 Enter into Gating configuration >>>>
4765 11:54:52.834545 Exit from Gating configuration <<<<
4766 11:54:52.837947 Enter into DVFS_PRE_config >>>>>
4767 11:54:52.847667 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4768 11:54:52.851036 Exit from DVFS_PRE_config <<<<<
4769 11:54:52.854525 Enter into PICG configuration >>>>
4770 11:54:52.857887 Exit from PICG configuration <<<<
4771 11:54:52.860861 [RX_INPUT] configuration >>>>>
4772 11:54:52.864224 [RX_INPUT] configuration <<<<<
4773 11:54:52.867581 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4774 11:54:52.874298 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4775 11:54:52.880797 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4776 11:54:52.884169 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4777 11:54:52.890617 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4778 11:54:52.897232 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4779 11:54:52.900763 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4780 11:54:52.907488 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4781 11:54:52.910762 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4782 11:54:52.913796 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4783 11:54:52.917327 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4784 11:54:52.923770 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4785 11:54:52.927428 ===================================
4786 11:54:52.927510 LPDDR4 DRAM CONFIGURATION
4787 11:54:52.930563 ===================================
4788 11:54:52.934012 EX_ROW_EN[0] = 0x0
4789 11:54:52.937337 EX_ROW_EN[1] = 0x0
4790 11:54:52.937417 LP4Y_EN = 0x0
4791 11:54:52.940500 WORK_FSP = 0x0
4792 11:54:52.940633 WL = 0x3
4793 11:54:52.943918 RL = 0x3
4794 11:54:52.943998 BL = 0x2
4795 11:54:52.947143 RPST = 0x0
4796 11:54:52.947222 RD_PRE = 0x0
4797 11:54:52.950717 WR_PRE = 0x1
4798 11:54:52.950797 WR_PST = 0x0
4799 11:54:52.953755 DBI_WR = 0x0
4800 11:54:52.953836 DBI_RD = 0x0
4801 11:54:52.957026 OTF = 0x1
4802 11:54:52.960468 ===================================
4803 11:54:52.963721 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4804 11:54:52.967044 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4805 11:54:52.973756 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4806 11:54:52.976934 ===================================
4807 11:54:52.977017 LPDDR4 DRAM CONFIGURATION
4808 11:54:52.980266 ===================================
4809 11:54:52.983729 EX_ROW_EN[0] = 0x10
4810 11:54:52.986864 EX_ROW_EN[1] = 0x0
4811 11:54:52.986945 LP4Y_EN = 0x0
4812 11:54:52.990301 WORK_FSP = 0x0
4813 11:54:52.990382 WL = 0x3
4814 11:54:52.993647 RL = 0x3
4815 11:54:52.993729 BL = 0x2
4816 11:54:52.996904 RPST = 0x0
4817 11:54:52.996985 RD_PRE = 0x0
4818 11:54:53.000433 WR_PRE = 0x1
4819 11:54:53.000574 WR_PST = 0x0
4820 11:54:53.003595 DBI_WR = 0x0
4821 11:54:53.003676 DBI_RD = 0x0
4822 11:54:53.007036 OTF = 0x1
4823 11:54:53.010222 ===================================
4824 11:54:53.016791 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4825 11:54:53.020136 nWR fixed to 30
4826 11:54:53.020219 [ModeRegInit_LP4] CH0 RK0
4827 11:54:53.023401 [ModeRegInit_LP4] CH0 RK1
4828 11:54:53.026873 [ModeRegInit_LP4] CH1 RK0
4829 11:54:53.026955 [ModeRegInit_LP4] CH1 RK1
4830 11:54:53.030078 match AC timing 8
4831 11:54:53.033436 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 0
4832 11:54:53.036638 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4833 11:54:53.043261 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
4834 11:54:53.046540 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
4835 11:54:53.053313 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
4836 11:54:53.053397 ==
4837 11:54:53.056667 Dram Type= 6, Freq= 0, CH_0, rank 0
4838 11:54:53.059801 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4839 11:54:53.059884 ==
4840 11:54:53.066385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4841 11:54:53.073064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
4842 11:54:53.076292 [CA 0] Center 38 (8~69) winsize 62
4843 11:54:53.079573 [CA 1] Center 38 (8~69) winsize 62
4844 11:54:53.082981 [CA 2] Center 36 (6~67) winsize 62
4845 11:54:53.086391 [CA 3] Center 36 (6~67) winsize 62
4846 11:54:53.089730 [CA 4] Center 34 (4~65) winsize 62
4847 11:54:53.092998 [CA 5] Center 34 (4~65) winsize 62
4848 11:54:53.093080
4849 11:54:53.096217 [CmdBusTrainingLP45] Vref(ca) range 1: 39
4850 11:54:53.096298
4851 11:54:53.099454 [CATrainingPosCal] consider 1 rank data
4852 11:54:53.102873 u2DelayCellTimex100 = 270/100 ps
4853 11:54:53.106343 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4854 11:54:53.109526 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4855 11:54:53.112852 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4856 11:54:53.116025 CA3 delay=36 (6~67),Diff = 2 PI (12 cell)
4857 11:54:53.119386 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4858 11:54:53.122818 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4859 11:54:53.122899
4860 11:54:53.129398 CA PerBit enable=1, Macro0, CA PI delay=34
4861 11:54:53.129479
4862 11:54:53.129543 [CBTSetCACLKResult] CA Dly = 34
4863 11:54:53.132433 CS Dly: 7 (0~38)
4864 11:54:53.132574 ==
4865 11:54:53.135717 Dram Type= 6, Freq= 0, CH_0, rank 1
4866 11:54:53.139242 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4867 11:54:53.139324 ==
4868 11:54:53.145812 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4869 11:54:53.152747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4870 11:54:53.155936 [CA 0] Center 38 (8~69) winsize 62
4871 11:54:53.159047 [CA 1] Center 38 (8~69) winsize 62
4872 11:54:53.162485 [CA 2] Center 36 (6~67) winsize 62
4873 11:54:53.165716 [CA 3] Center 35 (5~66) winsize 62
4874 11:54:53.169263 [CA 4] Center 34 (4~65) winsize 62
4875 11:54:53.172292 [CA 5] Center 34 (4~65) winsize 62
4876 11:54:53.172398
4877 11:54:53.175678 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4878 11:54:53.175760
4879 11:54:53.179018 [CATrainingPosCal] consider 2 rank data
4880 11:54:53.182370 u2DelayCellTimex100 = 270/100 ps
4881 11:54:53.185647 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
4882 11:54:53.189077 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
4883 11:54:53.192266 CA2 delay=36 (6~67),Diff = 2 PI (12 cell)
4884 11:54:53.195553 CA3 delay=36 (6~66),Diff = 2 PI (12 cell)
4885 11:54:53.198738 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4886 11:54:53.205595 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
4887 11:54:53.205676
4888 11:54:53.208651 CA PerBit enable=1, Macro0, CA PI delay=34
4889 11:54:53.208732
4890 11:54:53.211966 [CBTSetCACLKResult] CA Dly = 34
4891 11:54:53.212046 CS Dly: 7 (0~39)
4892 11:54:53.212109
4893 11:54:53.215572 ----->DramcWriteLeveling(PI) begin...
4894 11:54:53.215655 ==
4895 11:54:53.218684 Dram Type= 6, Freq= 0, CH_0, rank 0
4896 11:54:53.225187 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4897 11:54:53.225300 ==
4898 11:54:53.228422 Write leveling (Byte 0): 30 => 30
4899 11:54:53.228560 Write leveling (Byte 1): 26 => 26
4900 11:54:53.231887 DramcWriteLeveling(PI) end<-----
4901 11:54:53.231967
4902 11:54:53.235086 ==
4903 11:54:53.238574 Dram Type= 6, Freq= 0, CH_0, rank 0
4904 11:54:53.241622 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4905 11:54:53.241703 ==
4906 11:54:53.244934 [Gating] SW mode calibration
4907 11:54:53.251572 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
4908 11:54:53.254800 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
4909 11:54:53.261497 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4910 11:54:53.264967 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4911 11:54:53.268121 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4912 11:54:53.275008 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4913 11:54:53.278073 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4914 11:54:53.281452 0 10 20 | B1->B0 | 3333 3030 | 1 0 | (1 0) (1 0)
4915 11:54:53.288263 0 10 24 | B1->B0 | 2e2e 2424 | 0 0 | (0 0) (0 0)
4916 11:54:53.291591 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4917 11:54:53.294878 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4918 11:54:53.301452 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4919 11:54:53.304494 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4920 11:54:53.307795 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4921 11:54:53.314527 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4922 11:54:53.317871 0 11 20 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (0 0)
4923 11:54:53.321098 0 11 24 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4924 11:54:53.327828 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4925 11:54:53.331464 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4926 11:54:53.334677 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4927 11:54:53.337882 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4928 11:54:53.344839 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4929 11:54:53.347913 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4930 11:54:53.351380 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4931 11:54:53.358043 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4932 11:54:53.361410 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4933 11:54:53.364466 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4934 11:54:53.370952 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4935 11:54:53.374354 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4936 11:54:53.377690 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4937 11:54:53.384361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4938 11:54:53.387415 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4939 11:54:53.390650 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4940 11:54:53.397351 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4941 11:54:53.400619 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4942 11:54:53.403992 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4943 11:54:53.410841 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4944 11:54:53.413946 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4945 11:54:53.417246 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4946 11:54:53.424001 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4947 11:54:53.427463 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4948 11:54:53.430657 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4949 11:54:53.433925 Total UI for P1: 0, mck2ui 16
4950 11:54:53.437267 best dqsien dly found for B0: ( 0, 14, 22)
4951 11:54:53.440484 Total UI for P1: 0, mck2ui 16
4952 11:54:53.443918 best dqsien dly found for B1: ( 0, 14, 20)
4953 11:54:53.447267 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
4954 11:54:53.450553 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
4955 11:54:53.453814
4956 11:54:53.457353 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
4957 11:54:53.460386 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
4958 11:54:53.463824 [Gating] SW calibration Done
4959 11:54:53.463904 ==
4960 11:54:53.467110 Dram Type= 6, Freq= 0, CH_0, rank 0
4961 11:54:53.470374 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4962 11:54:53.470454 ==
4963 11:54:53.470519 RX Vref Scan: 0
4964 11:54:53.470579
4965 11:54:53.473733 RX Vref 0 -> 0, step: 1
4966 11:54:53.473813
4967 11:54:53.476950 RX Delay -80 -> 252, step: 8
4968 11:54:53.480570 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
4969 11:54:53.483664 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
4970 11:54:53.490378 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
4971 11:54:53.493689 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
4972 11:54:53.496928 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
4973 11:54:53.500423 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
4974 11:54:53.503851 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
4975 11:54:53.507120 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
4976 11:54:53.513652 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
4977 11:54:53.516970 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
4978 11:54:53.520326 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
4979 11:54:53.523314 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
4980 11:54:53.526968 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
4981 11:54:53.533578 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
4982 11:54:53.536666 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
4983 11:54:53.540232 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
4984 11:54:53.540405 ==
4985 11:54:53.543560 Dram Type= 6, Freq= 0, CH_0, rank 0
4986 11:54:53.546853 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
4987 11:54:53.547036 ==
4988 11:54:53.550403 DQS Delay:
4989 11:54:53.550591 DQS0 = 0, DQS1 = 0
4990 11:54:53.550724 DQM Delay:
4991 11:54:53.553571 DQM0 = 96, DQM1 = 88
4992 11:54:53.553760 DQ Delay:
4993 11:54:53.556775 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
4994 11:54:53.560009 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
4995 11:54:53.563259 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
4996 11:54:53.566646 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
4997 11:54:53.566856
4998 11:54:53.566987
4999 11:54:53.569875 ==
5000 11:54:53.570067 Dram Type= 6, Freq= 0, CH_0, rank 0
5001 11:54:53.576851 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5002 11:54:53.577136 ==
5003 11:54:53.577312
5004 11:54:53.577466
5005 11:54:53.580215 TX Vref Scan disable
5006 11:54:53.580571 == TX Byte 0 ==
5007 11:54:53.583553 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5008 11:54:53.590159 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5009 11:54:53.590613 == TX Byte 1 ==
5010 11:54:53.593942 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5011 11:54:53.599859 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5012 11:54:53.600326 ==
5013 11:54:53.603244 Dram Type= 6, Freq= 0, CH_0, rank 0
5014 11:54:53.606158 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5015 11:54:53.606278 ==
5016 11:54:53.606374
5017 11:54:53.606454
5018 11:54:53.609542 TX Vref Scan disable
5019 11:54:53.613040 == TX Byte 0 ==
5020 11:54:53.616072 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5021 11:54:53.619520 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5022 11:54:53.622759 == TX Byte 1 ==
5023 11:54:53.625971 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5024 11:54:53.629444 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5025 11:54:53.629559
5026 11:54:53.632636 [DATLAT]
5027 11:54:53.632730 Freq=933, CH0 RK0
5028 11:54:53.632821
5029 11:54:53.635978 DATLAT Default: 0xd
5030 11:54:53.636064 0, 0xFFFF, sum = 0
5031 11:54:53.639284 1, 0xFFFF, sum = 0
5032 11:54:53.639374 2, 0xFFFF, sum = 0
5033 11:54:53.642541 3, 0xFFFF, sum = 0
5034 11:54:53.642633 4, 0xFFFF, sum = 0
5035 11:54:53.645917 5, 0xFFFF, sum = 0
5036 11:54:53.646007 6, 0xFFFF, sum = 0
5037 11:54:53.649301 7, 0xFFFF, sum = 0
5038 11:54:53.649393 8, 0xFFFF, sum = 0
5039 11:54:53.652634 9, 0xFFFF, sum = 0
5040 11:54:53.652725 10, 0x0, sum = 1
5041 11:54:53.656044 11, 0x0, sum = 2
5042 11:54:53.656134 12, 0x0, sum = 3
5043 11:54:53.659150 13, 0x0, sum = 4
5044 11:54:53.659244 best_step = 11
5045 11:54:53.659331
5046 11:54:53.659411 ==
5047 11:54:53.662554 Dram Type= 6, Freq= 0, CH_0, rank 0
5048 11:54:53.666022 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5049 11:54:53.669163 ==
5050 11:54:53.669250 RX Vref Scan: 1
5051 11:54:53.669336
5052 11:54:53.672582 RX Vref 0 -> 0, step: 1
5053 11:54:53.672666
5054 11:54:53.675862 RX Delay -69 -> 252, step: 4
5055 11:54:53.675950
5056 11:54:53.679092 Set Vref, RX VrefLevel [Byte0]: 47
5057 11:54:53.682485 [Byte1]: 47
5058 11:54:53.682569
5059 11:54:53.685674 Final RX Vref Byte 0 = 47 to rank0
5060 11:54:53.689081 Final RX Vref Byte 1 = 47 to rank0
5061 11:54:53.692261 Final RX Vref Byte 0 = 47 to rank1
5062 11:54:53.695568 Final RX Vref Byte 1 = 47 to rank1==
5063 11:54:53.698968 Dram Type= 6, Freq= 0, CH_0, rank 0
5064 11:54:53.702345 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5065 11:54:53.702447 ==
5066 11:54:53.705456 DQS Delay:
5067 11:54:53.705545 DQS0 = 0, DQS1 = 0
5068 11:54:53.705632 DQM Delay:
5069 11:54:53.708844 DQM0 = 97, DQM1 = 86
5070 11:54:53.708932 DQ Delay:
5071 11:54:53.712277 DQ0 =94, DQ1 =100, DQ2 =94, DQ3 =94
5072 11:54:53.715549 DQ4 =102, DQ5 =88, DQ6 =102, DQ7 =102
5073 11:54:53.719118 DQ8 =78, DQ9 =70, DQ10 =86, DQ11 =78
5074 11:54:53.722280 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =98
5075 11:54:53.722411
5076 11:54:53.722500
5077 11:54:53.732048 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5078 11:54:53.735514 CH0 RK0: MR19=505, MR18=2626
5079 11:54:53.738689 CH0_RK0: MR19=0x505, MR18=0x2626, DQSOSC=409, MR23=63, INC=64, DEC=43
5080 11:54:53.738774
5081 11:54:53.742239 ----->DramcWriteLeveling(PI) begin...
5082 11:54:53.745413 ==
5083 11:54:53.748704 Dram Type= 6, Freq= 0, CH_0, rank 1
5084 11:54:53.752288 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5085 11:54:53.752707 ==
5086 11:54:53.755586 Write leveling (Byte 0): 27 => 27
5087 11:54:53.758861 Write leveling (Byte 1): 25 => 25
5088 11:54:53.762153 DramcWriteLeveling(PI) end<-----
5089 11:54:53.762515
5090 11:54:53.762888 ==
5091 11:54:53.765457 Dram Type= 6, Freq= 0, CH_0, rank 1
5092 11:54:53.769086 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5093 11:54:53.769455 ==
5094 11:54:53.772133 [Gating] SW mode calibration
5095 11:54:53.778772 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5096 11:54:53.785164 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5097 11:54:53.788525 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5098 11:54:53.791994 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5099 11:54:53.798577 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5100 11:54:53.801958 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 11:54:53.805154 0 10 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 11:54:53.811682 0 10 20 | B1->B0 | 3232 2d2d | 1 1 | (1 0) (1 0)
5103 11:54:53.815120 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5104 11:54:53.818410 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5105 11:54:53.821805 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5106 11:54:53.828191 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5107 11:54:53.831655 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5108 11:54:53.834873 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 11:54:53.841800 0 11 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5110 11:54:53.844935 0 11 20 | B1->B0 | 2929 3535 | 0 0 | (0 0) (0 0)
5111 11:54:53.848079 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5112 11:54:53.854705 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5113 11:54:53.858179 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5114 11:54:53.861467 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5115 11:54:53.868204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5116 11:54:53.871477 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 11:54:53.874689 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 11:54:53.881420 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5119 11:54:53.884808 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5120 11:54:53.887825 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5121 11:54:53.894613 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5122 11:54:53.897998 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5123 11:54:53.901174 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5124 11:54:53.907787 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 11:54:53.911281 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:54:53.914272 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:54:53.921421 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:54:53.924339 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:54:53.927731 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:54:53.934193 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:54:53.937820 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:54:53.940978 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:54:53.947657 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:54:53.950664 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5135 11:54:53.954117 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 11:54:53.957441 Total UI for P1: 0, mck2ui 16
5137 11:54:53.960796 best dqsien dly found for B0: ( 0, 14, 22)
5138 11:54:53.964063 Total UI for P1: 0, mck2ui 16
5139 11:54:53.967356 best dqsien dly found for B1: ( 0, 14, 20)
5140 11:54:53.970620 best DQS0 dly(MCK, UI, PI) = (0, 14, 22)
5141 11:54:53.973961 best DQS1 dly(MCK, UI, PI) = (0, 14, 20)
5142 11:54:53.974041
5143 11:54:53.980453 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 22)
5144 11:54:53.983852 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 20)
5145 11:54:53.987270 [Gating] SW calibration Done
5146 11:54:53.987349 ==
5147 11:54:53.990511 Dram Type= 6, Freq= 0, CH_0, rank 1
5148 11:54:53.993839 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5149 11:54:53.993919 ==
5150 11:54:53.993983 RX Vref Scan: 0
5151 11:54:53.994041
5152 11:54:53.997210 RX Vref 0 -> 0, step: 1
5153 11:54:53.997290
5154 11:54:54.000387 RX Delay -80 -> 252, step: 8
5155 11:54:54.003923 iDelay=200, Bit 0, Center 91 (-8 ~ 191) 200
5156 11:54:54.007024 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5157 11:54:54.010515 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5158 11:54:54.016910 iDelay=200, Bit 3, Center 91 (0 ~ 183) 184
5159 11:54:54.020327 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5160 11:54:54.023442 iDelay=200, Bit 5, Center 91 (-8 ~ 191) 200
5161 11:54:54.026847 iDelay=200, Bit 6, Center 99 (0 ~ 199) 200
5162 11:54:54.030018 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5163 11:54:54.033384 iDelay=200, Bit 8, Center 75 (-16 ~ 167) 184
5164 11:54:54.039957 iDelay=200, Bit 9, Center 71 (-24 ~ 167) 192
5165 11:54:54.043437 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5166 11:54:54.046667 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5167 11:54:54.050021 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5168 11:54:54.053278 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5169 11:54:54.059950 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5170 11:54:54.063215 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5171 11:54:54.063296 ==
5172 11:54:54.066666 Dram Type= 6, Freq= 0, CH_0, rank 1
5173 11:54:54.069734 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5174 11:54:54.069816 ==
5175 11:54:54.073127 DQS Delay:
5176 11:54:54.073207 DQS0 = 0, DQS1 = 0
5177 11:54:54.073270 DQM Delay:
5178 11:54:54.076266 DQM0 = 95, DQM1 = 87
5179 11:54:54.076345 DQ Delay:
5180 11:54:54.079663 DQ0 =91, DQ1 =99, DQ2 =91, DQ3 =91
5181 11:54:54.083071 DQ4 =99, DQ5 =91, DQ6 =99, DQ7 =103
5182 11:54:54.086262 DQ8 =75, DQ9 =71, DQ10 =95, DQ11 =79
5183 11:54:54.089612 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5184 11:54:54.089693
5185 11:54:54.089756
5186 11:54:54.089815 ==
5187 11:54:54.092827 Dram Type= 6, Freq= 0, CH_0, rank 1
5188 11:54:54.099431 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5189 11:54:54.099516 ==
5190 11:54:54.099579
5191 11:54:54.099637
5192 11:54:54.099693 TX Vref Scan disable
5193 11:54:54.102919 == TX Byte 0 ==
5194 11:54:54.106314 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5195 11:54:54.112908 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5196 11:54:54.112988 == TX Byte 1 ==
5197 11:54:54.116262 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5198 11:54:54.122854 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5199 11:54:54.122935 ==
5200 11:54:54.125966 Dram Type= 6, Freq= 0, CH_0, rank 1
5201 11:54:54.129263 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5202 11:54:54.129344 ==
5203 11:54:54.129408
5204 11:54:54.129467
5205 11:54:54.132862 TX Vref Scan disable
5206 11:54:54.132942 == TX Byte 0 ==
5207 11:54:54.139469 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5208 11:54:54.142502 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5209 11:54:54.145988 == TX Byte 1 ==
5210 11:54:54.149250 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5211 11:54:54.152477 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5212 11:54:54.152566
5213 11:54:54.152630 [DATLAT]
5214 11:54:54.155745 Freq=933, CH0 RK1
5215 11:54:54.155826
5216 11:54:54.155890 DATLAT Default: 0xb
5217 11:54:54.159046 0, 0xFFFF, sum = 0
5218 11:54:54.162445 1, 0xFFFF, sum = 0
5219 11:54:54.162527 2, 0xFFFF, sum = 0
5220 11:54:54.165757 3, 0xFFFF, sum = 0
5221 11:54:54.165839 4, 0xFFFF, sum = 0
5222 11:54:54.169063 5, 0xFFFF, sum = 0
5223 11:54:54.169144 6, 0xFFFF, sum = 0
5224 11:54:54.172410 7, 0xFFFF, sum = 0
5225 11:54:54.172491 8, 0xFFFF, sum = 0
5226 11:54:54.175626 9, 0xFFFF, sum = 0
5227 11:54:54.175706 10, 0x0, sum = 1
5228 11:54:54.179042 11, 0x0, sum = 2
5229 11:54:54.179123 12, 0x0, sum = 3
5230 11:54:54.182222 13, 0x0, sum = 4
5231 11:54:54.182304 best_step = 11
5232 11:54:54.182367
5233 11:54:54.182426 ==
5234 11:54:54.185457 Dram Type= 6, Freq= 0, CH_0, rank 1
5235 11:54:54.188597 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5236 11:54:54.188678 ==
5237 11:54:54.192244 RX Vref Scan: 0
5238 11:54:54.192323
5239 11:54:54.195291 RX Vref 0 -> 0, step: 1
5240 11:54:54.195371
5241 11:54:54.195433 RX Delay -69 -> 252, step: 4
5242 11:54:54.203238 iDelay=199, Bit 0, Center 94 (3 ~ 186) 184
5243 11:54:54.206653 iDelay=199, Bit 1, Center 98 (3 ~ 194) 192
5244 11:54:54.210089 iDelay=199, Bit 2, Center 94 (3 ~ 186) 184
5245 11:54:54.213313 iDelay=199, Bit 3, Center 94 (7 ~ 182) 176
5246 11:54:54.216754 iDelay=199, Bit 4, Center 102 (11 ~ 194) 184
5247 11:54:54.220021 iDelay=199, Bit 5, Center 88 (-5 ~ 182) 188
5248 11:54:54.226762 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5249 11:54:54.230103 iDelay=199, Bit 7, Center 106 (15 ~ 198) 184
5250 11:54:54.233358 iDelay=199, Bit 8, Center 76 (-9 ~ 162) 172
5251 11:54:54.236666 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5252 11:54:54.239911 iDelay=199, Bit 10, Center 88 (-5 ~ 182) 188
5253 11:54:54.246510 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5254 11:54:54.250014 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5255 11:54:54.253336 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5256 11:54:54.256459 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5257 11:54:54.259820 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5258 11:54:54.259901 ==
5259 11:54:54.263044 Dram Type= 6, Freq= 0, CH_0, rank 1
5260 11:54:54.269747 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5261 11:54:54.269828 ==
5262 11:54:54.269893 DQS Delay:
5263 11:54:54.269952 DQS0 = 0, DQS1 = 0
5264 11:54:54.273040 DQM Delay:
5265 11:54:54.273120 DQM0 = 97, DQM1 = 86
5266 11:54:54.276324 DQ Delay:
5267 11:54:54.279558 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =94
5268 11:54:54.282941 DQ4 =102, DQ5 =88, DQ6 =104, DQ7 =106
5269 11:54:54.286347 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =78
5270 11:54:54.289981 DQ12 =94, DQ13 =92, DQ14 =98, DQ15 =96
5271 11:54:54.290062
5272 11:54:54.290126
5273 11:54:54.296230 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b2b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 408 ps
5274 11:54:54.299682 CH0 RK1: MR19=505, MR18=2B2B
5275 11:54:54.306318 CH0_RK1: MR19=0x505, MR18=0x2B2B, DQSOSC=408, MR23=63, INC=65, DEC=43
5276 11:54:54.309610 [RxdqsGatingPostProcess] freq 933
5277 11:54:54.312787 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5278 11:54:54.316118 Pre-setting of DQS Precalculation
5279 11:54:54.322737 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5280 11:54:54.322819 ==
5281 11:54:54.326010 Dram Type= 6, Freq= 0, CH_1, rank 0
5282 11:54:54.329390 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5283 11:54:54.329481 ==
5284 11:54:54.336249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5285 11:54:54.342778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5286 11:54:54.346143 [CA 0] Center 37 (7~68) winsize 62
5287 11:54:54.349378 [CA 1] Center 37 (6~68) winsize 63
5288 11:54:54.352814 [CA 2] Center 35 (5~65) winsize 61
5289 11:54:54.355893 [CA 3] Center 34 (4~65) winsize 62
5290 11:54:54.359108 [CA 4] Center 33 (2~64) winsize 63
5291 11:54:54.362497 [CA 5] Center 33 (3~64) winsize 62
5292 11:54:54.362576
5293 11:54:54.365908 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5294 11:54:54.365987
5295 11:54:54.369125 [CATrainingPosCal] consider 1 rank data
5296 11:54:54.372415 u2DelayCellTimex100 = 270/100 ps
5297 11:54:54.375832 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5298 11:54:54.379004 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5299 11:54:54.382517 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5300 11:54:54.385770 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5301 11:54:54.389064 CA4 delay=33 (2~64),Diff = 0 PI (0 cell)
5302 11:54:54.392434 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5303 11:54:54.392531
5304 11:54:54.398901 CA PerBit enable=1, Macro0, CA PI delay=33
5305 11:54:54.399011
5306 11:54:54.399098 [CBTSetCACLKResult] CA Dly = 33
5307 11:54:54.402337 CS Dly: 5 (0~36)
5308 11:54:54.402440 ==
5309 11:54:54.405388 Dram Type= 6, Freq= 0, CH_1, rank 1
5310 11:54:54.408865 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5311 11:54:54.408943 ==
5312 11:54:54.415857 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5313 11:54:54.422206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5314 11:54:54.425495 [CA 0] Center 37 (6~68) winsize 63
5315 11:54:54.428904 [CA 1] Center 37 (6~68) winsize 63
5316 11:54:54.432248 [CA 2] Center 34 (4~65) winsize 62
5317 11:54:54.435361 [CA 3] Center 34 (4~65) winsize 62
5318 11:54:54.438970 [CA 4] Center 33 (3~63) winsize 61
5319 11:54:54.442251 [CA 5] Center 32 (2~63) winsize 62
5320 11:54:54.442330
5321 11:54:54.445511 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5322 11:54:54.445590
5323 11:54:54.448623 [CATrainingPosCal] consider 2 rank data
5324 11:54:54.451910 u2DelayCellTimex100 = 270/100 ps
5325 11:54:54.455181 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5326 11:54:54.458718 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5327 11:54:54.461870 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5328 11:54:54.465264 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5329 11:54:54.468549 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
5330 11:54:54.471816 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5331 11:54:54.475075
5332 11:54:54.478702 CA PerBit enable=1, Macro0, CA PI delay=33
5333 11:54:54.478787
5334 11:54:54.481742 [CBTSetCACLKResult] CA Dly = 33
5335 11:54:54.481906 CS Dly: 5 (0~37)
5336 11:54:54.481980
5337 11:54:54.485517 ----->DramcWriteLeveling(PI) begin...
5338 11:54:54.485675 ==
5339 11:54:54.488449 Dram Type= 6, Freq= 0, CH_1, rank 0
5340 11:54:54.492228 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5341 11:54:54.495266 ==
5342 11:54:54.495435 Write leveling (Byte 0): 25 => 25
5343 11:54:54.498376 Write leveling (Byte 1): 23 => 23
5344 11:54:54.501779 DramcWriteLeveling(PI) end<-----
5345 11:54:54.501888
5346 11:54:54.501967 ==
5347 11:54:54.505088 Dram Type= 6, Freq= 0, CH_1, rank 0
5348 11:54:54.512042 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5349 11:54:54.512238 ==
5350 11:54:54.515228 [Gating] SW mode calibration
5351 11:54:54.521617 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5352 11:54:54.525004 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5353 11:54:54.531742 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 11:54:54.534964 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:54:54.538195 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:54:54.544945 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 11:54:54.548768 0 10 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
5358 11:54:54.551795 0 10 20 | B1->B0 | 3333 2424 | 1 0 | (1 0) (1 0)
5359 11:54:54.558806 0 10 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
5360 11:54:54.561947 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 11:54:54.565764 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:54:54.568436 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:54:54.575468 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:54:54.578663 0 11 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 11:54:54.582022 0 11 16 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
5366 11:54:54.588631 0 11 20 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
5367 11:54:54.591305 0 11 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5368 11:54:54.595159 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:54:54.601404 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:54:54.604963 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:54:54.608226 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:54:54.614454 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:54:54.617829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5374 11:54:54.621160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5375 11:54:54.627868 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:54:54.631187 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:54:54.634401 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:54:54.641222 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:54:54.644627 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:54:54.648205 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:54:54.654489 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:54:54.657880 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:54:54.661008 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:54:54.668055 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:54:54.671454 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:54:54.674549 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:54:54.681068 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:54:54.684530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:54:54.688000 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5390 11:54:54.694309 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5391 11:54:54.697439 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 11:54:54.700970 Total UI for P1: 0, mck2ui 16
5393 11:54:54.704226 best dqsien dly found for B0: ( 0, 14, 18)
5394 11:54:54.707474 Total UI for P1: 0, mck2ui 16
5395 11:54:54.710803 best dqsien dly found for B1: ( 0, 14, 18)
5396 11:54:54.714083 best DQS0 dly(MCK, UI, PI) = (0, 14, 18)
5397 11:54:54.717502 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5398 11:54:54.718012
5399 11:54:54.720400 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 18)
5400 11:54:54.724071 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5401 11:54:54.727147 [Gating] SW calibration Done
5402 11:54:54.727725 ==
5403 11:54:54.730636 Dram Type= 6, Freq= 0, CH_1, rank 0
5404 11:54:54.737019 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5405 11:54:54.737435 ==
5406 11:54:54.737761 RX Vref Scan: 0
5407 11:54:54.738063
5408 11:54:54.740371 RX Vref 0 -> 0, step: 1
5409 11:54:54.740830
5410 11:54:54.743999 RX Delay -80 -> 252, step: 8
5411 11:54:54.747168 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5412 11:54:54.750528 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5413 11:54:54.753465 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5414 11:54:54.757039 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5415 11:54:54.763861 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5416 11:54:54.766942 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5417 11:54:54.770278 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5418 11:54:54.773723 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5419 11:54:54.776617 iDelay=208, Bit 8, Center 71 (-24 ~ 167) 192
5420 11:54:54.779802 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5421 11:54:54.786723 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5422 11:54:54.790295 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5423 11:54:54.793624 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5424 11:54:54.796895 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5425 11:54:54.800396 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5426 11:54:54.806934 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5427 11:54:54.807452 ==
5428 11:54:54.810196 Dram Type= 6, Freq= 0, CH_1, rank 0
5429 11:54:54.813207 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5430 11:54:54.813626 ==
5431 11:54:54.813956 DQS Delay:
5432 11:54:54.816802 DQS0 = 0, DQS1 = 0
5433 11:54:54.817314 DQM Delay:
5434 11:54:54.819906 DQM0 = 94, DQM1 = 87
5435 11:54:54.820420 DQ Delay:
5436 11:54:54.823147 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5437 11:54:54.826335 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5438 11:54:54.829996 DQ8 =71, DQ9 =75, DQ10 =87, DQ11 =79
5439 11:54:54.833513 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =99
5440 11:54:54.834026
5441 11:54:54.834352
5442 11:54:54.834655 ==
5443 11:54:54.836361 Dram Type= 6, Freq= 0, CH_1, rank 0
5444 11:54:54.839660 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5445 11:54:54.843349 ==
5446 11:54:54.843867
5447 11:54:54.844196
5448 11:54:54.844501 TX Vref Scan disable
5449 11:54:54.846078 == TX Byte 0 ==
5450 11:54:54.849575 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5451 11:54:54.853094 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5452 11:54:54.856289 == TX Byte 1 ==
5453 11:54:54.859613 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5454 11:54:54.862915 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5455 11:54:54.863328 ==
5456 11:54:54.866711 Dram Type= 6, Freq= 0, CH_1, rank 0
5457 11:54:54.872897 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5458 11:54:54.873409 ==
5459 11:54:54.873734
5460 11:54:54.874038
5461 11:54:54.874327 TX Vref Scan disable
5462 11:54:54.877182 == TX Byte 0 ==
5463 11:54:54.880779 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5464 11:54:54.887569 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5465 11:54:54.888082 == TX Byte 1 ==
5466 11:54:54.890513 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5467 11:54:54.897263 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5468 11:54:54.897780
5469 11:54:54.898106 [DATLAT]
5470 11:54:54.898409 Freq=933, CH1 RK0
5471 11:54:54.898701
5472 11:54:54.900733 DATLAT Default: 0xd
5473 11:54:54.901242 0, 0xFFFF, sum = 0
5474 11:54:54.903693 1, 0xFFFF, sum = 0
5475 11:54:54.904107 2, 0xFFFF, sum = 0
5476 11:54:54.907542 3, 0xFFFF, sum = 0
5477 11:54:54.910647 4, 0xFFFF, sum = 0
5478 11:54:54.911168 5, 0xFFFF, sum = 0
5479 11:54:54.914087 6, 0xFFFF, sum = 0
5480 11:54:54.914601 7, 0xFFFF, sum = 0
5481 11:54:54.917468 8, 0xFFFF, sum = 0
5482 11:54:54.917985 9, 0xFFFF, sum = 0
5483 11:54:54.920504 10, 0x0, sum = 1
5484 11:54:54.921178 11, 0x0, sum = 2
5485 11:54:54.923732 12, 0x0, sum = 3
5486 11:54:54.924248 13, 0x0, sum = 4
5487 11:54:54.924627 best_step = 11
5488 11:54:54.924938
5489 11:54:54.927323 ==
5490 11:54:54.930219 Dram Type= 6, Freq= 0, CH_1, rank 0
5491 11:54:54.933928 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5492 11:54:54.934445 ==
5493 11:54:54.934780 RX Vref Scan: 1
5494 11:54:54.935088
5495 11:54:54.936820 RX Vref 0 -> 0, step: 1
5496 11:54:54.937228
5497 11:54:54.940132 RX Delay -69 -> 252, step: 4
5498 11:54:54.940580
5499 11:54:54.943491 Set Vref, RX VrefLevel [Byte0]: 58
5500 11:54:54.947068 [Byte1]: 51
5501 11:54:54.947580
5502 11:54:54.950415 Final RX Vref Byte 0 = 58 to rank0
5503 11:54:54.953595 Final RX Vref Byte 1 = 51 to rank0
5504 11:54:54.956981 Final RX Vref Byte 0 = 58 to rank1
5505 11:54:54.960255 Final RX Vref Byte 1 = 51 to rank1==
5506 11:54:54.963541 Dram Type= 6, Freq= 0, CH_1, rank 0
5507 11:54:54.966949 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5508 11:54:54.970371 ==
5509 11:54:54.970942 DQS Delay:
5510 11:54:54.971276 DQS0 = 0, DQS1 = 0
5511 11:54:54.973567 DQM Delay:
5512 11:54:54.974008 DQM0 = 94, DQM1 = 88
5513 11:54:54.977159 DQ Delay:
5514 11:54:54.977668 DQ0 =96, DQ1 =88, DQ2 =86, DQ3 =92
5515 11:54:54.980240 DQ4 =94, DQ5 =104, DQ6 =102, DQ7 =92
5516 11:54:54.983497 DQ8 =72, DQ9 =80, DQ10 =88, DQ11 =80
5517 11:54:54.987016 DQ12 =94, DQ13 =98, DQ14 =96, DQ15 =96
5518 11:54:54.990365
5519 11:54:54.990879
5520 11:54:54.996759 [DQSOSCAuto] RK0, (LSB)MR18= 0x3232, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 406 ps
5521 11:54:54.999912 CH1 RK0: MR19=505, MR18=3232
5522 11:54:55.006989 CH1_RK0: MR19=0x505, MR18=0x3232, DQSOSC=406, MR23=63, INC=65, DEC=43
5523 11:54:55.007504
5524 11:54:55.010046 ----->DramcWriteLeveling(PI) begin...
5525 11:54:55.010464 ==
5526 11:54:55.013456 Dram Type= 6, Freq= 0, CH_1, rank 1
5527 11:54:55.016712 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5528 11:54:55.017230 ==
5529 11:54:55.020218 Write leveling (Byte 0): 21 => 21
5530 11:54:55.023437 Write leveling (Byte 1): 21 => 21
5531 11:54:55.026461 DramcWriteLeveling(PI) end<-----
5532 11:54:55.026871
5533 11:54:55.027197 ==
5534 11:54:55.029749 Dram Type= 6, Freq= 0, CH_1, rank 1
5535 11:54:55.033513 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5536 11:54:55.034026 ==
5537 11:54:55.036670 [Gating] SW mode calibration
5538 11:54:55.043395 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 20 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5539 11:54:55.049956 RX_Path_delay_UI(34) -3 - DQSINCTL_UI(24) = u1StartUI(10)
5540 11:54:55.053253 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5541 11:54:55.056650 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5542 11:54:55.063277 0 10 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5543 11:54:55.066419 0 10 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5544 11:54:55.069479 0 10 16 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
5545 11:54:55.075980 0 10 20 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
5546 11:54:55.079803 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5547 11:54:55.082846 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5548 11:54:55.089202 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5549 11:54:55.092797 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5550 11:54:55.096062 0 11 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5551 11:54:55.103025 0 11 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5552 11:54:55.105939 0 11 16 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
5553 11:54:55.109061 0 11 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5554 11:54:55.116187 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5555 11:54:55.119414 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5556 11:54:55.122818 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5557 11:54:55.129236 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5558 11:54:55.132852 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5559 11:54:55.135864 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5560 11:54:55.142718 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5561 11:54:55.146196 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5562 11:54:55.148884 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 11:54:55.156144 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5564 11:54:55.159346 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5565 11:54:55.162481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5566 11:54:55.169092 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5567 11:54:55.172434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5568 11:54:55.175536 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5569 11:54:55.182021 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5570 11:54:55.185236 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5571 11:54:55.189073 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5572 11:54:55.195634 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5573 11:54:55.198845 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5574 11:54:55.201833 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5575 11:54:55.209050 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5576 11:54:55.212388 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5577 11:54:55.215166 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:54:55.218937 Total UI for P1: 0, mck2ui 16
5579 11:54:55.221707 best dqsien dly found for B0: ( 0, 14, 16)
5580 11:54:55.225067 Total UI for P1: 0, mck2ui 16
5581 11:54:55.228856 best dqsien dly found for B1: ( 0, 14, 18)
5582 11:54:55.231614 best DQS0 dly(MCK, UI, PI) = (0, 14, 16)
5583 11:54:55.235273 best DQS1 dly(MCK, UI, PI) = (0, 14, 18)
5584 11:54:55.235790
5585 11:54:55.241703 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 16)
5586 11:54:55.245039 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 18)
5587 11:54:55.245550 [Gating] SW calibration Done
5588 11:54:55.248052 ==
5589 11:54:55.251683 Dram Type= 6, Freq= 0, CH_1, rank 1
5590 11:54:55.254994 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5591 11:54:55.255512 ==
5592 11:54:55.255845 RX Vref Scan: 0
5593 11:54:55.256153
5594 11:54:55.258133 RX Vref 0 -> 0, step: 1
5595 11:54:55.258652
5596 11:54:55.261738 RX Delay -80 -> 252, step: 8
5597 11:54:55.265098 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5598 11:54:55.268317 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5599 11:54:55.271821 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5600 11:54:55.278452 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5601 11:54:55.281315 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5602 11:54:55.284862 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5603 11:54:55.288001 iDelay=208, Bit 6, Center 99 (0 ~ 199) 200
5604 11:54:55.291352 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5605 11:54:55.294476 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5606 11:54:55.301229 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5607 11:54:55.304471 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5608 11:54:55.307897 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5609 11:54:55.311196 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5610 11:54:55.314702 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5611 11:54:55.320967 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5612 11:54:55.324086 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5613 11:54:55.324549 ==
5614 11:54:55.327437 Dram Type= 6, Freq= 0, CH_1, rank 1
5615 11:54:55.330985 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5616 11:54:55.331526 ==
5617 11:54:55.334479 DQS Delay:
5618 11:54:55.334992 DQS0 = 0, DQS1 = 0
5619 11:54:55.335322 DQM Delay:
5620 11:54:55.337669 DQM0 = 95, DQM1 = 88
5621 11:54:55.338078 DQ Delay:
5622 11:54:55.340612 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =95
5623 11:54:55.344158 DQ4 =95, DQ5 =107, DQ6 =99, DQ7 =91
5624 11:54:55.347255 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5625 11:54:55.350804 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =95
5626 11:54:55.351317
5627 11:54:55.351642
5628 11:54:55.351945 ==
5629 11:54:55.354293 Dram Type= 6, Freq= 0, CH_1, rank 1
5630 11:54:55.360672 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5631 11:54:55.361233 ==
5632 11:54:55.361575
5633 11:54:55.361884
5634 11:54:55.362176 TX Vref Scan disable
5635 11:54:55.363838 == TX Byte 0 ==
5636 11:54:55.367718 Update DQ dly =705 (2 ,5, 33) DQ OEN =(2 ,2)
5637 11:54:55.371097 Update DQM dly =705 (2 ,5, 33) DQM OEN =(2 ,2)
5638 11:54:55.374190 == TX Byte 1 ==
5639 11:54:55.377408 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5640 11:54:55.381059 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5641 11:54:55.384161 ==
5642 11:54:55.387673 Dram Type= 6, Freq= 0, CH_1, rank 1
5643 11:54:55.390880 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5644 11:54:55.391400 ==
5645 11:54:55.391733
5646 11:54:55.392038
5647 11:54:55.394092 TX Vref Scan disable
5648 11:54:55.394607 == TX Byte 0 ==
5649 11:54:55.400924 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5650 11:54:55.403953 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5651 11:54:55.404475 == TX Byte 1 ==
5652 11:54:55.410474 Update DQ dly =704 (2 ,5, 32) DQ OEN =(2 ,2)
5653 11:54:55.414190 Update DQM dly =704 (2 ,5, 32) DQM OEN =(2 ,2)
5654 11:54:55.414711
5655 11:54:55.415044 [DATLAT]
5656 11:54:55.417461 Freq=933, CH1 RK1
5657 11:54:55.417973
5658 11:54:55.418306 DATLAT Default: 0xb
5659 11:54:55.420663 0, 0xFFFF, sum = 0
5660 11:54:55.421223 1, 0xFFFF, sum = 0
5661 11:54:55.423779 2, 0xFFFF, sum = 0
5662 11:54:55.424201 3, 0xFFFF, sum = 0
5663 11:54:55.427304 4, 0xFFFF, sum = 0
5664 11:54:55.430240 5, 0xFFFF, sum = 0
5665 11:54:55.430666 6, 0xFFFF, sum = 0
5666 11:54:55.433551 7, 0xFFFF, sum = 0
5667 11:54:55.433971 8, 0xFFFF, sum = 0
5668 11:54:55.437044 9, 0xFFFF, sum = 0
5669 11:54:55.437462 10, 0x0, sum = 1
5670 11:54:55.440301 11, 0x0, sum = 2
5671 11:54:55.440979 12, 0x0, sum = 3
5672 11:54:55.441451 13, 0x0, sum = 4
5673 11:54:55.443571 best_step = 11
5674 11:54:55.444139
5675 11:54:55.444473 ==
5676 11:54:55.447219 Dram Type= 6, Freq= 0, CH_1, rank 1
5677 11:54:55.450460 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5678 11:54:55.450986 ==
5679 11:54:55.453409 RX Vref Scan: 0
5680 11:54:55.453824
5681 11:54:55.456943 RX Vref 0 -> 0, step: 1
5682 11:54:55.457459
5683 11:54:55.457800 RX Delay -69 -> 252, step: 4
5684 11:54:55.464549 iDelay=203, Bit 0, Center 98 (7 ~ 190) 184
5685 11:54:55.468076 iDelay=203, Bit 1, Center 92 (-1 ~ 186) 188
5686 11:54:55.471372 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5687 11:54:55.474540 iDelay=203, Bit 3, Center 92 (-1 ~ 186) 188
5688 11:54:55.477871 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5689 11:54:55.481052 iDelay=203, Bit 5, Center 106 (11 ~ 202) 192
5690 11:54:55.487944 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5691 11:54:55.491035 iDelay=203, Bit 7, Center 94 (-1 ~ 190) 192
5692 11:54:55.494307 iDelay=203, Bit 8, Center 74 (-17 ~ 166) 184
5693 11:54:55.497380 iDelay=203, Bit 9, Center 76 (-17 ~ 170) 188
5694 11:54:55.501151 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5695 11:54:55.507672 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5696 11:54:55.511125 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5697 11:54:55.514340 iDelay=203, Bit 13, Center 96 (7 ~ 186) 180
5698 11:54:55.517459 iDelay=203, Bit 14, Center 96 (-1 ~ 194) 196
5699 11:54:55.520786 iDelay=203, Bit 15, Center 96 (7 ~ 186) 180
5700 11:54:55.523961 ==
5701 11:54:55.524371 Dram Type= 6, Freq= 0, CH_1, rank 1
5702 11:54:55.530609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 1
5703 11:54:55.531126 ==
5704 11:54:55.531459 DQS Delay:
5705 11:54:55.533988 DQS0 = 0, DQS1 = 0
5706 11:54:55.534500 DQM Delay:
5707 11:54:55.537075 DQM0 = 96, DQM1 = 87
5708 11:54:55.537490 DQ Delay:
5709 11:54:55.540283 DQ0 =98, DQ1 =92, DQ2 =88, DQ3 =92
5710 11:54:55.543818 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5711 11:54:55.547024 DQ8 =74, DQ9 =76, DQ10 =88, DQ11 =80
5712 11:54:55.550666 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
5713 11:54:55.551187
5714 11:54:55.551520
5715 11:54:55.557125 [DQSOSCAuto] RK1, (LSB)MR18= 0x2727, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 409 ps
5716 11:54:55.560403 CH1 RK1: MR19=505, MR18=2727
5717 11:54:55.566782 CH1_RK1: MR19=0x505, MR18=0x2727, DQSOSC=409, MR23=63, INC=64, DEC=43
5718 11:54:55.570441 [RxdqsGatingPostProcess] freq 933
5719 11:54:55.576893 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
5720 11:54:55.577417 Pre-setting of DQS Precalculation
5721 11:54:55.583554 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5722 11:54:55.590316 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5723 11:54:55.596915 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5724 11:54:55.597431
5725 11:54:55.597757
5726 11:54:55.600210 [Calibration Summary] 1866 Mbps
5727 11:54:55.603242 CH 0, Rank 0
5728 11:54:55.603754 SW Impedance : PASS
5729 11:54:55.607075 DUTY Scan : NO K
5730 11:54:55.610209 ZQ Calibration : PASS
5731 11:54:55.610720 Jitter Meter : NO K
5732 11:54:55.613482 CBT Training : PASS
5733 11:54:55.616548 Write leveling : PASS
5734 11:54:55.617066 RX DQS gating : PASS
5735 11:54:55.620028 RX DQ/DQS(RDDQC) : PASS
5736 11:54:55.623132 TX DQ/DQS : PASS
5737 11:54:55.623548 RX DATLAT : PASS
5738 11:54:55.626261 RX DQ/DQS(Engine): PASS
5739 11:54:55.629454 TX OE : NO K
5740 11:54:55.629872 All Pass.
5741 11:54:55.630199
5742 11:54:55.630502 CH 0, Rank 1
5743 11:54:55.632900 SW Impedance : PASS
5744 11:54:55.636632 DUTY Scan : NO K
5745 11:54:55.637146 ZQ Calibration : PASS
5746 11:54:55.639433 Jitter Meter : NO K
5747 11:54:55.639843 CBT Training : PASS
5748 11:54:55.643088 Write leveling : PASS
5749 11:54:55.646664 RX DQS gating : PASS
5750 11:54:55.647175 RX DQ/DQS(RDDQC) : PASS
5751 11:54:55.649852 TX DQ/DQS : PASS
5752 11:54:55.653243 RX DATLAT : PASS
5753 11:54:55.653755 RX DQ/DQS(Engine): PASS
5754 11:54:55.656288 TX OE : NO K
5755 11:54:55.656839 All Pass.
5756 11:54:55.657166
5757 11:54:55.660093 CH 1, Rank 0
5758 11:54:55.660645 SW Impedance : PASS
5759 11:54:55.663001 DUTY Scan : NO K
5760 11:54:55.665954 ZQ Calibration : PASS
5761 11:54:55.666367 Jitter Meter : NO K
5762 11:54:55.669522 CBT Training : PASS
5763 11:54:55.672359 Write leveling : PASS
5764 11:54:55.672811 RX DQS gating : PASS
5765 11:54:55.676131 RX DQ/DQS(RDDQC) : PASS
5766 11:54:55.679290 TX DQ/DQS : PASS
5767 11:54:55.679800 RX DATLAT : PASS
5768 11:54:55.682613 RX DQ/DQS(Engine): PASS
5769 11:54:55.686033 TX OE : NO K
5770 11:54:55.686553 All Pass.
5771 11:54:55.686884
5772 11:54:55.687187 CH 1, Rank 1
5773 11:54:55.689353 SW Impedance : PASS
5774 11:54:55.692956 DUTY Scan : NO K
5775 11:54:55.693476 ZQ Calibration : PASS
5776 11:54:55.696059 Jitter Meter : NO K
5777 11:54:55.699147 CBT Training : PASS
5778 11:54:55.699658 Write leveling : PASS
5779 11:54:55.702670 RX DQS gating : PASS
5780 11:54:55.703183 RX DQ/DQS(RDDQC) : PASS
5781 11:54:55.706036 TX DQ/DQS : PASS
5782 11:54:55.708868 RX DATLAT : PASS
5783 11:54:55.709282 RX DQ/DQS(Engine): PASS
5784 11:54:55.712739 TX OE : NO K
5785 11:54:55.713276 All Pass.
5786 11:54:55.713733
5787 11:54:55.715427 DramC Write-DBI off
5788 11:54:55.719066 PER_BANK_REFRESH: Hybrid Mode
5789 11:54:55.719602 TX_TRACKING: ON
5790 11:54:55.729157 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
5791 11:54:55.732344 [FAST_K] Save calibration result to emmc
5792 11:54:55.735456 dramc_set_vcore_voltage set vcore to 650000
5793 11:54:55.738973 Read voltage for 400, 6
5794 11:54:55.739384 Vio18 = 0
5795 11:54:55.739707 Vcore = 650000
5796 11:54:55.742565 Vdram = 0
5797 11:54:55.743081 Vddq = 0
5798 11:54:55.743413 Vmddr = 0
5799 11:54:55.748772 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
5800 11:54:55.755448 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5801 11:54:55.755985 MEM_TYPE=3, freq_sel=20
5802 11:54:55.758845 sv_algorithm_assistance_LP4_800
5803 11:54:55.761886 ============ PULL DRAM RESETB DOWN ============
5804 11:54:55.768966 ========== PULL DRAM RESETB DOWN end =========
5805 11:54:55.772176 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5806 11:54:55.775448 ===================================
5807 11:54:55.778637 LPDDR4 DRAM CONFIGURATION
5808 11:54:55.781839 ===================================
5809 11:54:55.782372 EX_ROW_EN[0] = 0x0
5810 11:54:55.784938 EX_ROW_EN[1] = 0x0
5811 11:54:55.785381 LP4Y_EN = 0x0
5812 11:54:55.788757 WORK_FSP = 0x0
5813 11:54:55.789287 WL = 0x2
5814 11:54:55.791820 RL = 0x2
5815 11:54:55.792350 BL = 0x2
5816 11:54:55.795162 RPST = 0x0
5817 11:54:55.795696 RD_PRE = 0x0
5818 11:54:55.798528 WR_PRE = 0x1
5819 11:54:55.801652 WR_PST = 0x0
5820 11:54:55.802088 DBI_WR = 0x0
5821 11:54:55.805096 DBI_RD = 0x0
5822 11:54:55.805633 OTF = 0x1
5823 11:54:55.808719 ===================================
5824 11:54:55.811483 ===================================
5825 11:54:55.815091 ANA top config
5826 11:54:55.818060 ===================================
5827 11:54:55.818580 DLL_ASYNC_EN = 0
5828 11:54:55.821604 ALL_SLAVE_EN = 1
5829 11:54:55.824446 NEW_RANK_MODE = 1
5830 11:54:55.827947 DLL_IDLE_MODE = 1
5831 11:54:55.828368 LP45_APHY_COMB_EN = 1
5832 11:54:55.831312 TX_ODT_DIS = 1
5833 11:54:55.835114 NEW_8X_MODE = 1
5834 11:54:55.838037 ===================================
5835 11:54:55.841234 ===================================
5836 11:54:55.844732 data_rate = 800
5837 11:54:55.847962 CKR = 1
5838 11:54:55.851325 DQ_P2S_RATIO = 4
5839 11:54:55.854934 ===================================
5840 11:54:55.855459 CA_P2S_RATIO = 4
5841 11:54:55.857599 DQ_CA_OPEN = 0
5842 11:54:55.861428 DQ_SEMI_OPEN = 1
5843 11:54:55.864574 CA_SEMI_OPEN = 1
5844 11:54:55.867718 CA_FULL_RATE = 0
5845 11:54:55.871250 DQ_CKDIV4_EN = 0
5846 11:54:55.871662 CA_CKDIV4_EN = 1
5847 11:54:55.874760 CA_PREDIV_EN = 0
5848 11:54:55.877786 PH8_DLY = 0
5849 11:54:55.880920 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
5850 11:54:55.884185 DQ_AAMCK_DIV = 0
5851 11:54:55.887399 CA_AAMCK_DIV = 0
5852 11:54:55.887908 CA_ADMCK_DIV = 4
5853 11:54:55.890958 DQ_TRACK_CA_EN = 0
5854 11:54:55.894198 CA_PICK = 800
5855 11:54:55.897526 CA_MCKIO = 400
5856 11:54:55.900725 MCKIO_SEMI = 400
5857 11:54:55.904178 PLL_FREQ = 3016
5858 11:54:55.907531 DQ_UI_PI_RATIO = 32
5859 11:54:55.910457 CA_UI_PI_RATIO = 32
5860 11:54:55.913901 ===================================
5861 11:54:55.917374 ===================================
5862 11:54:55.917881 memory_type:LPDDR4
5863 11:54:55.920451 GP_NUM : 10
5864 11:54:55.921002 SRAM_EN : 1
5865 11:54:55.923674 MD32_EN : 0
5866 11:54:55.927008 ===================================
5867 11:54:55.930180 [ANA_INIT] >>>>>>>>>>>>>>
5868 11:54:55.933948 <<<<<< [CONFIGURE PHASE]: ANA_TX
5869 11:54:55.937059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5870 11:54:55.940256 ===================================
5871 11:54:55.940715 data_rate = 800,PCW = 0X7400
5872 11:54:55.946903 ===================================
5873 11:54:55.950102 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5874 11:54:55.953731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5875 11:54:55.966999 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5876 11:54:55.970424 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5877 11:54:55.973883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5878 11:54:55.977011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5879 11:54:55.980464 [ANA_INIT] flow start
5880 11:54:55.981029 [ANA_INIT] PLL >>>>>>>>
5881 11:54:55.983257 [ANA_INIT] PLL <<<<<<<<
5882 11:54:55.986996 [ANA_INIT] MIDPI >>>>>>>>
5883 11:54:55.990323 [ANA_INIT] MIDPI <<<<<<<<
5884 11:54:55.990843 [ANA_INIT] DLL >>>>>>>>
5885 11:54:55.993218 [ANA_INIT] flow end
5886 11:54:55.996736 ============ LP4 DIFF to SE enter ============
5887 11:54:56.000056 ============ LP4 DIFF to SE exit ============
5888 11:54:56.003261 [ANA_INIT] <<<<<<<<<<<<<
5889 11:54:56.006682 [Flow] Enable top DCM control >>>>>
5890 11:54:56.010012 [Flow] Enable top DCM control <<<<<
5891 11:54:56.013171 Enable DLL master slave shuffle
5892 11:54:56.019768 ==============================================================
5893 11:54:56.020282 Gating Mode config
5894 11:54:56.026325 ==============================================================
5895 11:54:56.026831 Config description:
5896 11:54:56.036045 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5897 11:54:56.042733 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5898 11:54:56.049181 SELPH_MODE 0: By rank 1: By Phase
5899 11:54:56.052464 ==============================================================
5900 11:54:56.055995 GAT_TRACK_EN = 0
5901 11:54:56.059185 RX_GATING_MODE = 2
5902 11:54:56.062758 RX_GATING_TRACK_MODE = 2
5903 11:54:56.066196 SELPH_MODE = 1
5904 11:54:56.069359 PICG_EARLY_EN = 1
5905 11:54:56.073019 VALID_LAT_VALUE = 1
5906 11:54:56.079450 ==============================================================
5907 11:54:56.082470 Enter into Gating configuration >>>>
5908 11:54:56.086256 Exit from Gating configuration <<<<
5909 11:54:56.089179 Enter into DVFS_PRE_config >>>>>
5910 11:54:56.099404 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5911 11:54:56.102515 Exit from DVFS_PRE_config <<<<<
5912 11:54:56.105723 Enter into PICG configuration >>>>
5913 11:54:56.108621 Exit from PICG configuration <<<<
5914 11:54:56.112370 [RX_INPUT] configuration >>>>>
5915 11:54:56.112928 [RX_INPUT] configuration <<<<<
5916 11:54:56.118858 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5917 11:54:56.125421 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5918 11:54:56.128566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5919 11:54:56.135722 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5920 11:54:56.141946 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5921 11:54:56.148646 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5922 11:54:56.151944 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5923 11:54:56.155040 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5924 11:54:56.161523 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5925 11:54:56.165470 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5926 11:54:56.168723 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5927 11:54:56.175203 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5928 11:54:56.178327 ===================================
5929 11:54:56.178851 LPDDR4 DRAM CONFIGURATION
5930 11:54:56.181562 ===================================
5931 11:54:56.184771 EX_ROW_EN[0] = 0x0
5932 11:54:56.188023 EX_ROW_EN[1] = 0x0
5933 11:54:56.188462 LP4Y_EN = 0x0
5934 11:54:56.191620 WORK_FSP = 0x0
5935 11:54:56.192030 WL = 0x2
5936 11:54:56.194654 RL = 0x2
5937 11:54:56.195063 BL = 0x2
5938 11:54:56.198157 RPST = 0x0
5939 11:54:56.198670 RD_PRE = 0x0
5940 11:54:56.201194 WR_PRE = 0x1
5941 11:54:56.201700 WR_PST = 0x0
5942 11:54:56.205093 DBI_WR = 0x0
5943 11:54:56.205606 DBI_RD = 0x0
5944 11:54:56.208446 OTF = 0x1
5945 11:54:56.211419 ===================================
5946 11:54:56.214886 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5947 11:54:56.217904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5948 11:54:56.224636 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
5949 11:54:56.227676 ===================================
5950 11:54:56.228091 LPDDR4 DRAM CONFIGURATION
5951 11:54:56.230811 ===================================
5952 11:54:56.234091 EX_ROW_EN[0] = 0x10
5953 11:54:56.237836 EX_ROW_EN[1] = 0x0
5954 11:54:56.238348 LP4Y_EN = 0x0
5955 11:54:56.241184 WORK_FSP = 0x0
5956 11:54:56.241595 WL = 0x2
5957 11:54:56.244208 RL = 0x2
5958 11:54:56.244785 BL = 0x2
5959 11:54:56.247854 RPST = 0x0
5960 11:54:56.248362 RD_PRE = 0x0
5961 11:54:56.251288 WR_PRE = 0x1
5962 11:54:56.251796 WR_PST = 0x0
5963 11:54:56.254222 DBI_WR = 0x0
5964 11:54:56.254737 DBI_RD = 0x0
5965 11:54:56.257829 OTF = 0x1
5966 11:54:56.260997 ===================================
5967 11:54:56.267428 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5968 11:54:56.270986 nWR fixed to 30
5969 11:54:56.271503 [ModeRegInit_LP4] CH0 RK0
5970 11:54:56.274325 [ModeRegInit_LP4] CH0 RK1
5971 11:54:56.277471 [ModeRegInit_LP4] CH1 RK0
5972 11:54:56.280941 [ModeRegInit_LP4] CH1 RK1
5973 11:54:56.281458 match AC timing 18
5974 11:54:56.287293 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 0
5975 11:54:56.291026 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5976 11:54:56.293991 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
5977 11:54:56.300347 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
5978 11:54:56.304182 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
5979 11:54:56.304731 ==
5980 11:54:56.307277 Dram Type= 6, Freq= 0, CH_0, rank 0
5981 11:54:56.310689 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
5982 11:54:56.311217 ==
5983 11:54:56.317430 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
5984 11:54:56.323629 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=39, u1VrefScanEnd=39
5985 11:54:56.326827 [CA 0] Center 36 (8~64) winsize 57
5986 11:54:56.327250 [CA 1] Center 36 (8~64) winsize 57
5987 11:54:56.330353 [CA 2] Center 36 (8~64) winsize 57
5988 11:54:56.333608 [CA 3] Center 36 (8~64) winsize 57
5989 11:54:56.337186 [CA 4] Center 36 (8~64) winsize 57
5990 11:54:56.340402 [CA 5] Center 36 (8~64) winsize 57
5991 11:54:56.341005
5992 11:54:56.343595 [CmdBusTrainingLP45] Vref(ca) range 1: 39
5993 11:54:56.344106
5994 11:54:56.350561 [CATrainingPosCal] consider 1 rank data
5995 11:54:56.351131 u2DelayCellTimex100 = 270/100 ps
5996 11:54:56.356718 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
5997 11:54:56.360059 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
5998 11:54:56.363371 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
5999 11:54:56.366922 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6000 11:54:56.370092 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6001 11:54:56.373027 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6002 11:54:56.373491
6003 11:54:56.376976 CA PerBit enable=1, Macro0, CA PI delay=36
6004 11:54:56.377534
6005 11:54:56.380068 [CBTSetCACLKResult] CA Dly = 36
6006 11:54:56.383135 CS Dly: 1 (0~32)
6007 11:54:56.383547 ==
6008 11:54:56.387036 Dram Type= 6, Freq= 0, CH_0, rank 1
6009 11:54:56.389877 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6010 11:54:56.390298 ==
6011 11:54:56.396875 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6012 11:54:56.400018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6013 11:54:56.403148 [CA 0] Center 36 (8~64) winsize 57
6014 11:54:56.406782 [CA 1] Center 36 (8~64) winsize 57
6015 11:54:56.409959 [CA 2] Center 36 (8~64) winsize 57
6016 11:54:56.413002 [CA 3] Center 36 (8~64) winsize 57
6017 11:54:56.416300 [CA 4] Center 36 (8~64) winsize 57
6018 11:54:56.419858 [CA 5] Center 36 (8~64) winsize 57
6019 11:54:56.420410
6020 11:54:56.423195 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6021 11:54:56.423723
6022 11:54:56.426111 [CATrainingPosCal] consider 2 rank data
6023 11:54:56.429680 u2DelayCellTimex100 = 270/100 ps
6024 11:54:56.432938 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6025 11:54:56.436576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6026 11:54:56.439594 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6027 11:54:56.446218 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6028 11:54:56.449512 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6029 11:54:56.453103 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6030 11:54:56.453646
6031 11:54:56.455995 CA PerBit enable=1, Macro0, CA PI delay=36
6032 11:54:56.456549
6033 11:54:56.463202 [CBTSetCACLKResult] CA Dly = 36
6034 11:54:56.463616 CS Dly: 1 (0~32)
6035 11:54:56.463943
6036 11:54:56.464245 ----->DramcWriteLeveling(PI) begin...
6037 11:54:56.465724 ==
6038 11:54:56.466136 Dram Type= 6, Freq= 0, CH_0, rank 0
6039 11:54:56.472614 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6040 11:54:56.473033 ==
6041 11:54:56.475814 Write leveling (Byte 0): 32 => 0
6042 11:54:56.478972 Write leveling (Byte 1): 32 => 0
6043 11:54:56.479381 DramcWriteLeveling(PI) end<-----
6044 11:54:56.482149
6045 11:54:56.482558 ==
6046 11:54:56.486073 Dram Type= 6, Freq= 0, CH_0, rank 0
6047 11:54:56.489465 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6048 11:54:56.489879 ==
6049 11:54:56.492267 [Gating] SW mode calibration
6050 11:54:56.499468 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6051 11:54:56.502597 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6052 11:54:56.509423 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6053 11:54:56.512590 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6054 11:54:56.515827 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6055 11:54:56.522382 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6056 11:54:56.525920 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6057 11:54:56.529005 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6058 11:54:56.535875 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6059 11:54:56.539076 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6060 11:54:56.542344 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6061 11:54:56.545851 Total UI for P1: 0, mck2ui 16
6062 11:54:56.549124 best dqsien dly found for B0: ( 0, 10, 16)
6063 11:54:56.552424 Total UI for P1: 0, mck2ui 16
6064 11:54:56.555783 best dqsien dly found for B1: ( 0, 10, 16)
6065 11:54:56.559111 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6066 11:54:56.562108 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6067 11:54:56.562620
6068 11:54:56.569056 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6069 11:54:56.572495 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6070 11:54:56.575709 [Gating] SW calibration Done
6071 11:54:56.576217 ==
6072 11:54:56.578828 Dram Type= 6, Freq= 0, CH_0, rank 0
6073 11:54:56.582037 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6074 11:54:56.582551 ==
6075 11:54:56.582883 RX Vref Scan: 0
6076 11:54:56.585480
6077 11:54:56.586007 RX Vref 0 -> 0, step: 1
6078 11:54:56.586342
6079 11:54:56.588962 RX Delay -410 -> 252, step: 16
6080 11:54:56.591868 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6081 11:54:56.598888 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6082 11:54:56.602018 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6083 11:54:56.605417 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6084 11:54:56.608651 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6085 11:54:56.615526 iDelay=230, Bit 5, Center -51 (-314 ~ 213) 528
6086 11:54:56.618634 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6087 11:54:56.621602 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6088 11:54:56.625764 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6089 11:54:56.631726 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6090 11:54:56.635056 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6091 11:54:56.638672 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6092 11:54:56.641706 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6093 11:54:56.648341 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6094 11:54:56.651976 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6095 11:54:56.655005 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6096 11:54:56.655517 ==
6097 11:54:56.658752 Dram Type= 6, Freq= 0, CH_0, rank 0
6098 11:54:56.664779 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6099 11:54:56.665300 ==
6100 11:54:56.665635 DQS Delay:
6101 11:54:56.668229 DQS0 = 51, DQS1 = 59
6102 11:54:56.668780 DQM Delay:
6103 11:54:56.669112 DQM0 = 13, DQM1 = 15
6104 11:54:56.671401 DQ Delay:
6105 11:54:56.674823 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6106 11:54:56.677959 DQ4 =24, DQ5 =0, DQ6 =24, DQ7 =24
6107 11:54:56.678469 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6108 11:54:56.681475 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6109 11:54:56.684857
6110 11:54:56.685369
6111 11:54:56.685697 ==
6112 11:54:56.687742 Dram Type= 6, Freq= 0, CH_0, rank 0
6113 11:54:56.691425 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6114 11:54:56.691942 ==
6115 11:54:56.692269
6116 11:54:56.692621
6117 11:54:56.694789 TX Vref Scan disable
6118 11:54:56.695302 == TX Byte 0 ==
6119 11:54:56.697989 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6120 11:54:56.704351 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6121 11:54:56.704908 == TX Byte 1 ==
6122 11:54:56.707818 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6123 11:54:56.714883 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6124 11:54:56.715397 ==
6125 11:54:56.718250 Dram Type= 6, Freq= 0, CH_0, rank 0
6126 11:54:56.721180 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6127 11:54:56.721697 ==
6128 11:54:56.722030
6129 11:54:56.722333
6130 11:54:56.724730 TX Vref Scan disable
6131 11:54:56.725142 == TX Byte 0 ==
6132 11:54:56.731029 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6133 11:54:56.734029 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6134 11:54:56.734443 == TX Byte 1 ==
6135 11:54:56.741229 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6136 11:54:56.744340 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6137 11:54:56.744900
6138 11:54:56.745239 [DATLAT]
6139 11:54:56.747785 Freq=400, CH0 RK0
6140 11:54:56.748298
6141 11:54:56.748686 DATLAT Default: 0xf
6142 11:54:56.751057 0, 0xFFFF, sum = 0
6143 11:54:56.751580 1, 0xFFFF, sum = 0
6144 11:54:56.754333 2, 0xFFFF, sum = 0
6145 11:54:56.754846 3, 0xFFFF, sum = 0
6146 11:54:56.757851 4, 0xFFFF, sum = 0
6147 11:54:56.758368 5, 0xFFFF, sum = 0
6148 11:54:56.760592 6, 0xFFFF, sum = 0
6149 11:54:56.761010 7, 0xFFFF, sum = 0
6150 11:54:56.764269 8, 0xFFFF, sum = 0
6151 11:54:56.764846 9, 0xFFFF, sum = 0
6152 11:54:56.767909 10, 0xFFFF, sum = 0
6153 11:54:56.770586 11, 0xFFFF, sum = 0
6154 11:54:56.770963 12, 0x0, sum = 1
6155 11:54:56.774264 13, 0x0, sum = 2
6156 11:54:56.774681 14, 0x0, sum = 3
6157 11:54:56.775009 15, 0x0, sum = 4
6158 11:54:56.777469 best_step = 13
6159 11:54:56.777980
6160 11:54:56.778312 ==
6161 11:54:56.781009 Dram Type= 6, Freq= 0, CH_0, rank 0
6162 11:54:56.784381 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6163 11:54:56.784940 ==
6164 11:54:56.787760 RX Vref Scan: 1
6165 11:54:56.788268
6166 11:54:56.788633 RX Vref 0 -> 0, step: 1
6167 11:54:56.791063
6168 11:54:56.791572 RX Delay -359 -> 252, step: 8
6169 11:54:56.791902
6170 11:54:56.794556 Set Vref, RX VrefLevel [Byte0]: 47
6171 11:54:56.797708 [Byte1]: 47
6172 11:54:56.802878
6173 11:54:56.803391 Final RX Vref Byte 0 = 47 to rank0
6174 11:54:56.806443 Final RX Vref Byte 1 = 47 to rank0
6175 11:54:56.809407 Final RX Vref Byte 0 = 47 to rank1
6176 11:54:56.812545 Final RX Vref Byte 1 = 47 to rank1==
6177 11:54:56.816105 Dram Type= 6, Freq= 0, CH_0, rank 0
6178 11:54:56.822260 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6179 11:54:56.822778 ==
6180 11:54:56.823117 DQS Delay:
6181 11:54:56.825419 DQS0 = 52, DQS1 = 68
6182 11:54:56.825829 DQM Delay:
6183 11:54:56.826160 DQM0 = 8, DQM1 = 17
6184 11:54:56.828796 DQ Delay:
6185 11:54:56.832004 DQ0 =4, DQ1 =8, DQ2 =8, DQ3 =4
6186 11:54:56.832414 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6187 11:54:56.835227 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6188 11:54:56.838999 DQ12 =24, DQ13 =28, DQ14 =28, DQ15 =28
6189 11:54:56.839409
6190 11:54:56.841851
6191 11:54:56.848650 [DQSOSCAuto] RK0, (LSB)MR18= 0xa4a4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 389 ps
6192 11:54:56.852265 CH0 RK0: MR19=C0C, MR18=A4A4
6193 11:54:56.858716 CH0_RK0: MR19=0xC0C, MR18=0xA4A4, DQSOSC=389, MR23=63, INC=390, DEC=260
6194 11:54:56.859231 ==
6195 11:54:56.861844 Dram Type= 6, Freq= 0, CH_0, rank 1
6196 11:54:56.865609 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6197 11:54:56.866120 ==
6198 11:54:56.868575 [Gating] SW mode calibration
6199 11:54:56.874833 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6200 11:54:56.881992 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6201 11:54:56.884951 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6202 11:54:56.888411 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6203 11:54:56.895353 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6204 11:54:56.898596 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6205 11:54:56.901577 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6206 11:54:56.908427 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6207 11:54:56.911577 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6208 11:54:56.914986 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
6209 11:54:56.921368 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6210 11:54:56.921883 Total UI for P1: 0, mck2ui 16
6211 11:54:56.928226 best dqsien dly found for B0: ( 0, 10, 16)
6212 11:54:56.928894 Total UI for P1: 0, mck2ui 16
6213 11:54:56.931498 best dqsien dly found for B1: ( 0, 10, 24)
6214 11:54:56.938135 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6215 11:54:56.941146 best DQS1 dly(MCK, UI, PI) = (0, 10, 24)
6216 11:54:56.941565
6217 11:54:56.944432 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6218 11:54:56.948110 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 24)
6219 11:54:56.951542 [Gating] SW calibration Done
6220 11:54:56.952051 ==
6221 11:54:56.954988 Dram Type= 6, Freq= 0, CH_0, rank 1
6222 11:54:56.957774 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6223 11:54:56.958190 ==
6224 11:54:56.961044 RX Vref Scan: 0
6225 11:54:56.961454
6226 11:54:56.961778 RX Vref 0 -> 0, step: 1
6227 11:54:56.962080
6228 11:54:56.964341 RX Delay -410 -> 252, step: 16
6229 11:54:56.970991 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6230 11:54:56.974325 iDelay=230, Bit 1, Center -35 (-298 ~ 229) 528
6231 11:54:56.977708 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6232 11:54:56.981170 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6233 11:54:56.987733 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6234 11:54:56.990905 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6235 11:54:56.994300 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6236 11:54:56.997880 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6237 11:54:57.004786 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6238 11:54:57.007670 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6239 11:54:57.010962 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6240 11:54:57.014422 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6241 11:54:57.020854 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6242 11:54:57.024259 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6243 11:54:57.027169 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6244 11:54:57.030750 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6245 11:54:57.033875 ==
6246 11:54:57.037042 Dram Type= 6, Freq= 0, CH_0, rank 1
6247 11:54:57.040479 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6248 11:54:57.040947 ==
6249 11:54:57.041278 DQS Delay:
6250 11:54:57.043898 DQS0 = 43, DQS1 = 59
6251 11:54:57.044310 DQM Delay:
6252 11:54:57.046954 DQM0 = 7, DQM1 = 15
6253 11:54:57.047367 DQ Delay:
6254 11:54:57.050335 DQ0 =0, DQ1 =8, DQ2 =0, DQ3 =0
6255 11:54:57.053627 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6256 11:54:57.057004 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6257 11:54:57.060641 DQ12 =24, DQ13 =16, DQ14 =24, DQ15 =24
6258 11:54:57.061367
6259 11:54:57.061835
6260 11:54:57.062154 ==
6261 11:54:57.063877 Dram Type= 6, Freq= 0, CH_0, rank 1
6262 11:54:57.066715 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6263 11:54:57.067133 ==
6264 11:54:57.067461
6265 11:54:57.067764
6266 11:54:57.070540 TX Vref Scan disable
6267 11:54:57.070952 == TX Byte 0 ==
6268 11:54:57.076722 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6269 11:54:57.080238 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6270 11:54:57.080701 == TX Byte 1 ==
6271 11:54:57.087207 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6272 11:54:57.090169 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6273 11:54:57.090714 ==
6274 11:54:57.093327 Dram Type= 6, Freq= 0, CH_0, rank 1
6275 11:54:57.096863 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6276 11:54:57.097277 ==
6277 11:54:57.097603
6278 11:54:57.097914
6279 11:54:57.100269 TX Vref Scan disable
6280 11:54:57.100839 == TX Byte 0 ==
6281 11:54:57.107315 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6282 11:54:57.110267 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6283 11:54:57.110782 == TX Byte 1 ==
6284 11:54:57.117151 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6285 11:54:57.120136 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6286 11:54:57.120697
6287 11:54:57.121033 [DATLAT]
6288 11:54:57.123458 Freq=400, CH0 RK1
6289 11:54:57.123971
6290 11:54:57.124299 DATLAT Default: 0xd
6291 11:54:57.126579 0, 0xFFFF, sum = 0
6292 11:54:57.126995 1, 0xFFFF, sum = 0
6293 11:54:57.129764 2, 0xFFFF, sum = 0
6294 11:54:57.130177 3, 0xFFFF, sum = 0
6295 11:54:57.133012 4, 0xFFFF, sum = 0
6296 11:54:57.133426 5, 0xFFFF, sum = 0
6297 11:54:57.136217 6, 0xFFFF, sum = 0
6298 11:54:57.136673 7, 0xFFFF, sum = 0
6299 11:54:57.139447 8, 0xFFFF, sum = 0
6300 11:54:57.143084 9, 0xFFFF, sum = 0
6301 11:54:57.143498 10, 0xFFFF, sum = 0
6302 11:54:57.146345 11, 0xFFFF, sum = 0
6303 11:54:57.146763 12, 0x0, sum = 1
6304 11:54:57.149598 13, 0x0, sum = 2
6305 11:54:57.150013 14, 0x0, sum = 3
6306 11:54:57.150341 15, 0x0, sum = 4
6307 11:54:57.152948 best_step = 13
6308 11:54:57.153357
6309 11:54:57.153673 ==
6310 11:54:57.156206 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 11:54:57.159902 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6312 11:54:57.160412 ==
6313 11:54:57.163055 RX Vref Scan: 0
6314 11:54:57.163565
6315 11:54:57.165893 RX Vref 0 -> 0, step: 1
6316 11:54:57.166303
6317 11:54:57.166621 RX Delay -359 -> 252, step: 8
6318 11:54:57.174752 iDelay=217, Bit 0, Center -48 (-295 ~ 200) 496
6319 11:54:57.178129 iDelay=217, Bit 1, Center -36 (-287 ~ 216) 504
6320 11:54:57.181473 iDelay=217, Bit 2, Center -44 (-295 ~ 208) 504
6321 11:54:57.188282 iDelay=217, Bit 3, Center -48 (-295 ~ 200) 496
6322 11:54:57.191331 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6323 11:54:57.195082 iDelay=217, Bit 5, Center -52 (-303 ~ 200) 504
6324 11:54:57.197904 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6325 11:54:57.205400 iDelay=217, Bit 7, Center -32 (-279 ~ 216) 496
6326 11:54:57.208051 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6327 11:54:57.211211 iDelay=217, Bit 9, Center -64 (-303 ~ 176) 480
6328 11:54:57.215174 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
6329 11:54:57.221455 iDelay=217, Bit 11, Center -60 (-303 ~ 184) 488
6330 11:54:57.224395 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6331 11:54:57.227671 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6332 11:54:57.231315 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6333 11:54:57.237470 iDelay=217, Bit 15, Center -44 (-287 ~ 200) 488
6334 11:54:57.237901 ==
6335 11:54:57.241248 Dram Type= 6, Freq= 0, CH_0, rank 1
6336 11:54:57.244140 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6337 11:54:57.244582 ==
6338 11:54:57.244919 DQS Delay:
6339 11:54:57.247771 DQS0 = 52, DQS1 = 64
6340 11:54:57.248279 DQM Delay:
6341 11:54:57.250887 DQM0 = 10, DQM1 = 13
6342 11:54:57.251292 DQ Delay:
6343 11:54:57.254130 DQ0 =4, DQ1 =16, DQ2 =8, DQ3 =4
6344 11:54:57.257877 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6345 11:54:57.261115 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6346 11:54:57.264392 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6347 11:54:57.264947
6348 11:54:57.265310
6349 11:54:57.270762 [DQSOSCAuto] RK1, (LSB)MR18= 0xc5c5, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 385 ps
6350 11:54:57.273944 CH0 RK1: MR19=C0C, MR18=C5C5
6351 11:54:57.281048 CH0_RK1: MR19=0xC0C, MR18=0xC5C5, DQSOSC=385, MR23=63, INC=398, DEC=265
6352 11:54:57.284090 [RxdqsGatingPostProcess] freq 400
6353 11:54:57.290875 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6354 11:54:57.294253 Pre-setting of DQS Precalculation
6355 11:54:57.297270 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6356 11:54:57.297789 ==
6357 11:54:57.300485 Dram Type= 6, Freq= 0, CH_1, rank 0
6358 11:54:57.304336 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6359 11:54:57.304917 ==
6360 11:54:57.310773 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6361 11:54:57.317295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6362 11:54:57.320675 [CA 0] Center 36 (8~64) winsize 57
6363 11:54:57.324064 [CA 1] Center 36 (8~64) winsize 57
6364 11:54:57.326967 [CA 2] Center 36 (8~64) winsize 57
6365 11:54:57.330867 [CA 3] Center 36 (8~64) winsize 57
6366 11:54:57.333620 [CA 4] Center 36 (8~64) winsize 57
6367 11:54:57.337287 [CA 5] Center 36 (8~64) winsize 57
6368 11:54:57.337698
6369 11:54:57.340809 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6370 11:54:57.341318
6371 11:54:57.343799 [CATrainingPosCal] consider 1 rank data
6372 11:54:57.347162 u2DelayCellTimex100 = 270/100 ps
6373 11:54:57.350707 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 11:54:57.353666 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 11:54:57.357077 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 11:54:57.360591 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 11:54:57.363536 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 11:54:57.367028 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 11:54:57.367544
6380 11:54:57.370459 CA PerBit enable=1, Macro0, CA PI delay=36
6381 11:54:57.371160
6382 11:54:57.373476 [CBTSetCACLKResult] CA Dly = 36
6383 11:54:57.376992 CS Dly: 1 (0~32)
6384 11:54:57.377505 ==
6385 11:54:57.380220 Dram Type= 6, Freq= 0, CH_1, rank 1
6386 11:54:57.383199 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6387 11:54:57.383613 ==
6388 11:54:57.390556 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6389 11:54:57.396662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6390 11:54:57.400225 [CA 0] Center 36 (8~64) winsize 57
6391 11:54:57.400788 [CA 1] Center 36 (8~64) winsize 57
6392 11:54:57.403541 [CA 2] Center 36 (8~64) winsize 57
6393 11:54:57.406919 [CA 3] Center 36 (8~64) winsize 57
6394 11:54:57.410407 [CA 4] Center 36 (8~64) winsize 57
6395 11:54:57.413672 [CA 5] Center 36 (8~64) winsize 57
6396 11:54:57.414184
6397 11:54:57.416895 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6398 11:54:57.417417
6399 11:54:57.423423 [CATrainingPosCal] consider 2 rank data
6400 11:54:57.423939 u2DelayCellTimex100 = 270/100 ps
6401 11:54:57.426347 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6402 11:54:57.433205 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6403 11:54:57.436436 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6404 11:54:57.439678 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6405 11:54:57.443035 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6406 11:54:57.446996 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6407 11:54:57.447557
6408 11:54:57.450075 CA PerBit enable=1, Macro0, CA PI delay=36
6409 11:54:57.450632
6410 11:54:57.453240 [CBTSetCACLKResult] CA Dly = 36
6411 11:54:57.456322 CS Dly: 1 (0~32)
6412 11:54:57.456826
6413 11:54:57.460032 ----->DramcWriteLeveling(PI) begin...
6414 11:54:57.460664 ==
6415 11:54:57.463223 Dram Type= 6, Freq= 0, CH_1, rank 0
6416 11:54:57.466120 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6417 11:54:57.466581 ==
6418 11:54:57.469815 Write leveling (Byte 0): 32 => 0
6419 11:54:57.473234 Write leveling (Byte 1): 32 => 0
6420 11:54:57.476485 DramcWriteLeveling(PI) end<-----
6421 11:54:57.477088
6422 11:54:57.477447 ==
6423 11:54:57.479626 Dram Type= 6, Freq= 0, CH_1, rank 0
6424 11:54:57.483202 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6425 11:54:57.483757 ==
6426 11:54:57.486436 [Gating] SW mode calibration
6427 11:54:57.493008 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6428 11:54:57.499524 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6429 11:54:57.502762 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6430 11:54:57.506566 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 11:54:57.512759 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 11:54:57.516342 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6433 11:54:57.519571 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 11:54:57.526041 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 11:54:57.529267 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 11:54:57.532473 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
6437 11:54:57.539135 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6438 11:54:57.539598 Total UI for P1: 0, mck2ui 16
6439 11:54:57.542418 best dqsien dly found for B0: ( 0, 10, 16)
6440 11:54:57.546007 Total UI for P1: 0, mck2ui 16
6441 11:54:57.549331 best dqsien dly found for B1: ( 0, 10, 16)
6442 11:54:57.555926 best DQS0 dly(MCK, UI, PI) = (0, 10, 16)
6443 11:54:57.559365 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6444 11:54:57.559920
6445 11:54:57.562237 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 16)
6446 11:54:57.565472 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6447 11:54:57.568818 [Gating] SW calibration Done
6448 11:54:57.569372 ==
6449 11:54:57.572287 Dram Type= 6, Freq= 0, CH_1, rank 0
6450 11:54:57.575852 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6451 11:54:57.576431 ==
6452 11:54:57.578815 RX Vref Scan: 0
6453 11:54:57.579273
6454 11:54:57.579646 RX Vref 0 -> 0, step: 1
6455 11:54:57.580055
6456 11:54:57.582519 RX Delay -410 -> 252, step: 16
6457 11:54:57.588631 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6458 11:54:57.592413 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6459 11:54:57.595245 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6460 11:54:57.598378 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6461 11:54:57.605491 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6462 11:54:57.608501 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6463 11:54:57.611773 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6464 11:54:57.615364 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6465 11:54:57.621569 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6466 11:54:57.625047 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6467 11:54:57.628080 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6468 11:54:57.634615 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6469 11:54:57.638053 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6470 11:54:57.641462 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6471 11:54:57.644948 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6472 11:54:57.651407 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6473 11:54:57.651931 ==
6474 11:54:57.654698 Dram Type= 6, Freq= 0, CH_1, rank 0
6475 11:54:57.658294 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6476 11:54:57.659037 ==
6477 11:54:57.659593 DQS Delay:
6478 11:54:57.661297 DQS0 = 43, DQS1 = 59
6479 11:54:57.661742 DQM Delay:
6480 11:54:57.664624 DQM0 = 6, DQM1 = 15
6481 11:54:57.665047 DQ Delay:
6482 11:54:57.668069 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6483 11:54:57.671477 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6484 11:54:57.674396 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6485 11:54:57.678281 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =32
6486 11:54:57.678794
6487 11:54:57.679129
6488 11:54:57.679440 ==
6489 11:54:57.681169 Dram Type= 6, Freq= 0, CH_1, rank 0
6490 11:54:57.685003 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6491 11:54:57.685516 ==
6492 11:54:57.685848
6493 11:54:57.686159
6494 11:54:57.687707 TX Vref Scan disable
6495 11:54:57.688124 == TX Byte 0 ==
6496 11:54:57.694315 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6497 11:54:57.697497 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6498 11:54:57.700855 == TX Byte 1 ==
6499 11:54:57.704274 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6500 11:54:57.707626 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6501 11:54:57.708136 ==
6502 11:54:57.710894 Dram Type= 6, Freq= 0, CH_1, rank 0
6503 11:54:57.714281 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6504 11:54:57.717438 ==
6505 11:54:57.717899
6506 11:54:57.718258
6507 11:54:57.718595 TX Vref Scan disable
6508 11:54:57.720794 == TX Byte 0 ==
6509 11:54:57.724198 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6510 11:54:57.727623 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6511 11:54:57.730728 == TX Byte 1 ==
6512 11:54:57.733876 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6513 11:54:57.737360 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6514 11:54:57.737837
6515 11:54:57.740553 [DATLAT]
6516 11:54:57.741014 Freq=400, CH1 RK0
6517 11:54:57.741380
6518 11:54:57.743821 DATLAT Default: 0xf
6519 11:54:57.744293 0, 0xFFFF, sum = 0
6520 11:54:57.747112 1, 0xFFFF, sum = 0
6521 11:54:57.747628 2, 0xFFFF, sum = 0
6522 11:54:57.750606 3, 0xFFFF, sum = 0
6523 11:54:57.751384 4, 0xFFFF, sum = 0
6524 11:54:57.753711 5, 0xFFFF, sum = 0
6525 11:54:57.754175 6, 0xFFFF, sum = 0
6526 11:54:57.757071 7, 0xFFFF, sum = 0
6527 11:54:57.757536 8, 0xFFFF, sum = 0
6528 11:54:57.760048 9, 0xFFFF, sum = 0
6529 11:54:57.760425 10, 0xFFFF, sum = 0
6530 11:54:57.763791 11, 0xFFFF, sum = 0
6531 11:54:57.764323 12, 0x0, sum = 1
6532 11:54:57.766937 13, 0x0, sum = 2
6533 11:54:57.767402 14, 0x0, sum = 3
6534 11:54:57.770520 15, 0x0, sum = 4
6535 11:54:57.771072 best_step = 13
6536 11:54:57.771407
6537 11:54:57.771714 ==
6538 11:54:57.773723 Dram Type= 6, Freq= 0, CH_1, rank 0
6539 11:54:57.780576 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6540 11:54:57.781091 ==
6541 11:54:57.781423 RX Vref Scan: 1
6542 11:54:57.781730
6543 11:54:57.783674 RX Vref 0 -> 0, step: 1
6544 11:54:57.784189
6545 11:54:57.786600 RX Delay -359 -> 252, step: 8
6546 11:54:57.787017
6547 11:54:57.790390 Set Vref, RX VrefLevel [Byte0]: 58
6548 11:54:57.793082 [Byte1]: 51
6549 11:54:57.797093
6550 11:54:57.797607 Final RX Vref Byte 0 = 58 to rank0
6551 11:54:57.800422 Final RX Vref Byte 1 = 51 to rank0
6552 11:54:57.803374 Final RX Vref Byte 0 = 58 to rank1
6553 11:54:57.806857 Final RX Vref Byte 1 = 51 to rank1==
6554 11:54:57.810507 Dram Type= 6, Freq= 0, CH_1, rank 0
6555 11:54:57.816914 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6556 11:54:57.817468 ==
6557 11:54:57.817838 DQS Delay:
6558 11:54:57.820152 DQS0 = 48, DQS1 = 64
6559 11:54:57.820767 DQM Delay:
6560 11:54:57.821151 DQM0 = 7, DQM1 = 15
6561 11:54:57.823507 DQ Delay:
6562 11:54:57.826536 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =4
6563 11:54:57.827093 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =4
6564 11:54:57.829716 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6565 11:54:57.833386 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6566 11:54:57.833944
6567 11:54:57.836366
6568 11:54:57.843344 [DQSOSCAuto] RK0, (LSB)MR18= 0xdddd, (MSB)MR19= 0xc0c, tDQSOscB0 = 382 ps tDQSOscB1 = 382 ps
6569 11:54:57.846573 CH1 RK0: MR19=C0C, MR18=DDDD
6570 11:54:57.852909 CH1_RK0: MR19=0xC0C, MR18=0xDDDD, DQSOSC=382, MR23=63, INC=404, DEC=269
6571 11:54:57.853446 ==
6572 11:54:57.856211 Dram Type= 6, Freq= 0, CH_1, rank 1
6573 11:54:57.859688 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6574 11:54:57.860244 ==
6575 11:54:57.862831 [Gating] SW mode calibration
6576 11:54:57.869694 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6577 11:54:57.875853 RX_Path_delay_UI(27) -3 - DQSINCTL_UI(20) = u1StartUI(7)
6578 11:54:57.879399 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6579 11:54:57.882654 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6580 11:54:57.889305 0 8 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6581 11:54:57.892592 0 8 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6582 11:54:57.895862 0 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6583 11:54:57.902544 0 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6584 11:54:57.906078 0 10 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6585 11:54:57.909129 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
6586 11:54:57.912457 Total UI for P1: 0, mck2ui 16
6587 11:54:57.915710 best dqsien dly found for B0: ( 0, 10, 8)
6588 11:54:57.919265 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6589 11:54:57.922527 Total UI for P1: 0, mck2ui 16
6590 11:54:57.925835 best dqsien dly found for B1: ( 0, 10, 16)
6591 11:54:57.928841 best DQS0 dly(MCK, UI, PI) = (0, 10, 8)
6592 11:54:57.935639 best DQS1 dly(MCK, UI, PI) = (0, 10, 16)
6593 11:54:57.936202
6594 11:54:57.939006 best DQS0 P1 dly(MCK, UI, PI) = (0, 12, 8)
6595 11:54:57.942366 best DQS1 P1 dly(MCK, UI, PI) = (0, 12, 16)
6596 11:54:57.945419 [Gating] SW calibration Done
6597 11:54:57.945884 ==
6598 11:54:57.948909 Dram Type= 6, Freq= 0, CH_1, rank 1
6599 11:54:57.952424 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6600 11:54:57.953068 ==
6601 11:54:57.955441 RX Vref Scan: 0
6602 11:54:57.955991
6603 11:54:57.956359 RX Vref 0 -> 0, step: 1
6604 11:54:57.956783
6605 11:54:57.958646 RX Delay -410 -> 252, step: 16
6606 11:54:57.965444 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6607 11:54:57.968727 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6608 11:54:57.972262 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6609 11:54:57.975332 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6610 11:54:57.982025 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6611 11:54:57.985424 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6612 11:54:57.988439 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6613 11:54:57.991957 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6614 11:54:57.998602 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6615 11:54:58.001636 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6616 11:54:58.005147 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6617 11:54:58.008609 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6618 11:54:58.015088 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6619 11:54:58.018632 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6620 11:54:58.021504 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6621 11:54:58.025077 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6622 11:54:58.025633 ==
6623 11:54:58.028351 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 11:54:58.035074 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6625 11:54:58.035620 ==
6626 11:54:58.035992 DQS Delay:
6627 11:54:58.038229 DQS0 = 43, DQS1 = 59
6628 11:54:58.038717 DQM Delay:
6629 11:54:58.041538 DQM0 = 10, DQM1 = 17
6630 11:54:58.042006 DQ Delay:
6631 11:54:58.044844 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6632 11:54:58.048262 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6633 11:54:58.048862 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6634 11:54:58.055265 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =24
6635 11:54:58.055820
6636 11:54:58.056186
6637 11:54:58.056561 ==
6638 11:54:58.057953 Dram Type= 6, Freq= 0, CH_1, rank 1
6639 11:54:58.061613 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6640 11:54:58.062171 ==
6641 11:54:58.062539
6642 11:54:58.062877
6643 11:54:58.064867 TX Vref Scan disable
6644 11:54:58.065331 == TX Byte 0 ==
6645 11:54:58.071448 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6646 11:54:58.074463 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6647 11:54:58.074926 == TX Byte 1 ==
6648 11:54:58.078293 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6649 11:54:58.085092 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6650 11:54:58.085647 ==
6651 11:54:58.088187 Dram Type= 6, Freq= 0, CH_1, rank 1
6652 11:54:58.090913 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6653 11:54:58.091378 ==
6654 11:54:58.091745
6655 11:54:58.092081
6656 11:54:58.094434 TX Vref Scan disable
6657 11:54:58.094989 == TX Byte 0 ==
6658 11:54:58.100894 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6659 11:54:58.104545 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6660 11:54:58.105100 == TX Byte 1 ==
6661 11:54:58.111206 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6662 11:54:58.114405 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6663 11:54:58.114972
6664 11:54:58.115344 [DATLAT]
6665 11:54:58.117627 Freq=400, CH1 RK1
6666 11:54:58.118181
6667 11:54:58.118549 DATLAT Default: 0xd
6668 11:54:58.121070 0, 0xFFFF, sum = 0
6669 11:54:58.121541 1, 0xFFFF, sum = 0
6670 11:54:58.124263 2, 0xFFFF, sum = 0
6671 11:54:58.124902 3, 0xFFFF, sum = 0
6672 11:54:58.127679 4, 0xFFFF, sum = 0
6673 11:54:58.128238 5, 0xFFFF, sum = 0
6674 11:54:58.130711 6, 0xFFFF, sum = 0
6675 11:54:58.131181 7, 0xFFFF, sum = 0
6676 11:54:58.134092 8, 0xFFFF, sum = 0
6677 11:54:58.134564 9, 0xFFFF, sum = 0
6678 11:54:58.137299 10, 0xFFFF, sum = 0
6679 11:54:58.140708 11, 0xFFFF, sum = 0
6680 11:54:58.141370 12, 0x0, sum = 1
6681 11:54:58.141763 13, 0x0, sum = 2
6682 11:54:58.144175 14, 0x0, sum = 3
6683 11:54:58.144692 15, 0x0, sum = 4
6684 11:54:58.147707 best_step = 13
6685 11:54:58.148259
6686 11:54:58.148698 ==
6687 11:54:58.150703 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 11:54:58.154560 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6689 11:54:58.155118 ==
6690 11:54:58.157195 RX Vref Scan: 0
6691 11:54:58.157655
6692 11:54:58.158007 RX Vref 0 -> 0, step: 1
6693 11:54:58.158319
6694 11:54:58.160433 RX Delay -359 -> 252, step: 8
6695 11:54:58.169123 iDelay=225, Bit 0, Center -36 (-279 ~ 208) 488
6696 11:54:58.172325 iDelay=225, Bit 1, Center -44 (-287 ~ 200) 488
6697 11:54:58.176059 iDelay=225, Bit 2, Center -48 (-295 ~ 200) 496
6698 11:54:58.179517 iDelay=225, Bit 3, Center -40 (-287 ~ 208) 496
6699 11:54:58.185377 iDelay=225, Bit 4, Center -40 (-287 ~ 208) 496
6700 11:54:58.189068 iDelay=225, Bit 5, Center -28 (-279 ~ 224) 504
6701 11:54:58.192243 iDelay=225, Bit 6, Center -32 (-279 ~ 216) 496
6702 11:54:58.195636 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
6703 11:54:58.202107 iDelay=225, Bit 8, Center -64 (-311 ~ 184) 496
6704 11:54:58.205445 iDelay=225, Bit 9, Center -60 (-311 ~ 192) 504
6705 11:54:58.208770 iDelay=225, Bit 10, Center -48 (-295 ~ 200) 496
6706 11:54:58.215938 iDelay=225, Bit 11, Center -56 (-303 ~ 192) 496
6707 11:54:58.218742 iDelay=225, Bit 12, Center -40 (-287 ~ 208) 496
6708 11:54:58.222262 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
6709 11:54:58.225146 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
6710 11:54:58.232384 iDelay=225, Bit 15, Center -40 (-287 ~ 208) 496
6711 11:54:58.232988 ==
6712 11:54:58.235333 Dram Type= 6, Freq= 0, CH_1, rank 1
6713 11:54:58.238659 fsp= 0, odt_onoff= 0, Byte mode= 0, DivMode= 2
6714 11:54:58.239131 ==
6715 11:54:58.239501 DQS Delay:
6716 11:54:58.241835 DQS0 = 48, DQS1 = 64
6717 11:54:58.242294 DQM Delay:
6718 11:54:58.245720 DQM0 = 9, DQM1 = 15
6719 11:54:58.246183 DQ Delay:
6720 11:54:58.248334 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6721 11:54:58.252067 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6722 11:54:58.255323 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6723 11:54:58.258595 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6724 11:54:58.259154
6725 11:54:58.259518
6726 11:54:58.265458 [DQSOSCAuto] RK1, (LSB)MR18= 0xb3b3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 387 ps
6727 11:54:58.268670 CH1 RK1: MR19=C0C, MR18=B3B3
6728 11:54:58.275139 CH1_RK1: MR19=0xC0C, MR18=0xB3B3, DQSOSC=387, MR23=63, INC=394, DEC=262
6729 11:54:58.278593 [RxdqsGatingPostProcess] freq 400
6730 11:54:58.285438 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
6731 11:54:58.285997 Pre-setting of DQS Precalculation
6732 11:54:58.291897 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
6733 11:54:58.298418 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6734 11:54:58.305011 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6735 11:54:58.305817
6736 11:54:58.306205
6737 11:54:58.308626 [Calibration Summary] 800 Mbps
6738 11:54:58.311861 CH 0, Rank 0
6739 11:54:58.312416 SW Impedance : PASS
6740 11:54:58.314967 DUTY Scan : NO K
6741 11:54:58.318143 ZQ Calibration : PASS
6742 11:54:58.318694 Jitter Meter : NO K
6743 11:54:58.321788 CBT Training : PASS
6744 11:54:58.324863 Write leveling : PASS
6745 11:54:58.325415 RX DQS gating : PASS
6746 11:54:58.328030 RX DQ/DQS(RDDQC) : PASS
6747 11:54:58.328624 TX DQ/DQS : PASS
6748 11:54:58.331178 RX DATLAT : PASS
6749 11:54:58.334786 RX DQ/DQS(Engine): PASS
6750 11:54:58.335253 TX OE : NO K
6751 11:54:58.337727 All Pass.
6752 11:54:58.338195
6753 11:54:58.338569 CH 0, Rank 1
6754 11:54:58.341310 SW Impedance : PASS
6755 11:54:58.341976 DUTY Scan : NO K
6756 11:54:58.344457 ZQ Calibration : PASS
6757 11:54:58.347787 Jitter Meter : NO K
6758 11:54:58.348255 CBT Training : PASS
6759 11:54:58.351129 Write leveling : NO K
6760 11:54:58.354539 RX DQS gating : PASS
6761 11:54:58.355092 RX DQ/DQS(RDDQC) : PASS
6762 11:54:58.357947 TX DQ/DQS : PASS
6763 11:54:58.360898 RX DATLAT : PASS
6764 11:54:58.361361 RX DQ/DQS(Engine): PASS
6765 11:54:58.364173 TX OE : NO K
6766 11:54:58.364638 All Pass.
6767 11:54:58.365025
6768 11:54:58.367672 CH 1, Rank 0
6769 11:54:58.368263 SW Impedance : PASS
6770 11:54:58.371095 DUTY Scan : NO K
6771 11:54:58.374430 ZQ Calibration : PASS
6772 11:54:58.374847 Jitter Meter : NO K
6773 11:54:58.377438 CBT Training : PASS
6774 11:54:58.381189 Write leveling : PASS
6775 11:54:58.381699 RX DQS gating : PASS
6776 11:54:58.384314 RX DQ/DQS(RDDQC) : PASS
6777 11:54:58.384768 TX DQ/DQS : PASS
6778 11:54:58.387797 RX DATLAT : PASS
6779 11:54:58.391387 RX DQ/DQS(Engine): PASS
6780 11:54:58.391897 TX OE : NO K
6781 11:54:58.394525 All Pass.
6782 11:54:58.394981
6783 11:54:58.395343 CH 1, Rank 1
6784 11:54:58.397659 SW Impedance : PASS
6785 11:54:58.398118 DUTY Scan : NO K
6786 11:54:58.400983 ZQ Calibration : PASS
6787 11:54:58.404309 Jitter Meter : NO K
6788 11:54:58.404904 CBT Training : PASS
6789 11:54:58.408051 Write leveling : NO K
6790 11:54:58.411167 RX DQS gating : PASS
6791 11:54:58.411714 RX DQ/DQS(RDDQC) : PASS
6792 11:54:58.414542 TX DQ/DQS : PASS
6793 11:54:58.417948 RX DATLAT : PASS
6794 11:54:58.418503 RX DQ/DQS(Engine): PASS
6795 11:54:58.421071 TX OE : NO K
6796 11:54:58.421627 All Pass.
6797 11:54:58.421991
6798 11:54:58.424672 DramC Write-DBI off
6799 11:54:58.427993 PER_BANK_REFRESH: Hybrid Mode
6800 11:54:58.428591 TX_TRACKING: ON
6801 11:54:58.437438 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
6802 11:54:58.440753 [FAST_K] Save calibration result to emmc
6803 11:54:58.444247 dramc_set_vcore_voltage set vcore to 725000
6804 11:54:58.447511 Read voltage for 1600, 0
6805 11:54:58.447971 Vio18 = 0
6806 11:54:58.448405 Vcore = 725000
6807 11:54:58.450728 Vdram = 0
6808 11:54:58.451186 Vddq = 0
6809 11:54:58.451549 Vmddr = 0
6810 11:54:58.457665 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
6811 11:54:58.461069 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6812 11:54:58.464039 MEM_TYPE=3, freq_sel=13
6813 11:54:58.467353 sv_algorithm_assistance_LP4_3733
6814 11:54:58.470901 ============ PULL DRAM RESETB DOWN ============
6815 11:54:58.473902 ========== PULL DRAM RESETB DOWN end =========
6816 11:54:58.480880 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6817 11:54:58.483934 ===================================
6818 11:54:58.486973 LPDDR4 DRAM CONFIGURATION
6819 11:54:58.490578 ===================================
6820 11:54:58.491042 EX_ROW_EN[0] = 0x0
6821 11:54:58.493591 EX_ROW_EN[1] = 0x0
6822 11:54:58.494051 LP4Y_EN = 0x0
6823 11:54:58.497153 WORK_FSP = 0x1
6824 11:54:58.497619 WL = 0x5
6825 11:54:58.500939 RL = 0x5
6826 11:54:58.501401 BL = 0x2
6827 11:54:58.504099 RPST = 0x0
6828 11:54:58.504699 RD_PRE = 0x0
6829 11:54:58.506931 WR_PRE = 0x1
6830 11:54:58.507637 WR_PST = 0x1
6831 11:54:58.510350 DBI_WR = 0x0
6832 11:54:58.510811 DBI_RD = 0x0
6833 11:54:58.513831 OTF = 0x1
6834 11:54:58.517247 ===================================
6835 11:54:58.520394 ===================================
6836 11:54:58.520992 ANA top config
6837 11:54:58.524230 ===================================
6838 11:54:58.527182 DLL_ASYNC_EN = 0
6839 11:54:58.529981 ALL_SLAVE_EN = 0
6840 11:54:58.533444 NEW_RANK_MODE = 1
6841 11:54:58.533994 DLL_IDLE_MODE = 1
6842 11:54:58.536753 LP45_APHY_COMB_EN = 1
6843 11:54:58.540027 TX_ODT_DIS = 0
6844 11:54:58.543310 NEW_8X_MODE = 1
6845 11:54:58.546716 ===================================
6846 11:54:58.550207 ===================================
6847 11:54:58.553108 data_rate = 3200
6848 11:54:58.556585 CKR = 1
6849 11:54:58.557139 DQ_P2S_RATIO = 8
6850 11:54:58.559995 ===================================
6851 11:54:58.563329 CA_P2S_RATIO = 8
6852 11:54:58.566474 DQ_CA_OPEN = 0
6853 11:54:58.570082 DQ_SEMI_OPEN = 0
6854 11:54:58.573565 CA_SEMI_OPEN = 0
6855 11:54:58.576306 CA_FULL_RATE = 0
6856 11:54:58.576881 DQ_CKDIV4_EN = 0
6857 11:54:58.579861 CA_CKDIV4_EN = 0
6858 11:54:58.583309 CA_PREDIV_EN = 0
6859 11:54:58.586435 PH8_DLY = 12
6860 11:54:58.589515 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
6861 11:54:58.592867 DQ_AAMCK_DIV = 4
6862 11:54:58.593332 CA_AAMCK_DIV = 4
6863 11:54:58.596051 CA_ADMCK_DIV = 4
6864 11:54:58.599376 DQ_TRACK_CA_EN = 0
6865 11:54:58.602862 CA_PICK = 1600
6866 11:54:58.606153 CA_MCKIO = 1600
6867 11:54:58.609315 MCKIO_SEMI = 0
6868 11:54:58.612782 PLL_FREQ = 3068
6869 11:54:58.615949 DQ_UI_PI_RATIO = 32
6870 11:54:58.616499 CA_UI_PI_RATIO = 0
6871 11:54:58.619319 ===================================
6872 11:54:58.622617 ===================================
6873 11:54:58.625870 memory_type:LPDDR4
6874 11:54:58.629210 GP_NUM : 10
6875 11:54:58.629758 SRAM_EN : 1
6876 11:54:58.632877 MD32_EN : 0
6877 11:54:58.635722 ===================================
6878 11:54:58.638887 [ANA_INIT] >>>>>>>>>>>>>>
6879 11:54:58.642193 <<<<<< [CONFIGURE PHASE]: ANA_TX
6880 11:54:58.645847 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6881 11:54:58.648900 ===================================
6882 11:54:58.649359 data_rate = 3200,PCW = 0X7600
6883 11:54:58.651813 ===================================
6884 11:54:58.655520 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6885 11:54:58.662386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6886 11:54:58.669126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6887 11:54:58.672003 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6888 11:54:58.675274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6889 11:54:58.678606 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6890 11:54:58.682054 [ANA_INIT] flow start
6891 11:54:58.685314 [ANA_INIT] PLL >>>>>>>>
6892 11:54:58.685775 [ANA_INIT] PLL <<<<<<<<
6893 11:54:58.688712 [ANA_INIT] MIDPI >>>>>>>>
6894 11:54:58.692585 [ANA_INIT] MIDPI <<<<<<<<
6895 11:54:58.693141 [ANA_INIT] DLL >>>>>>>>
6896 11:54:58.695251 [ANA_INIT] DLL <<<<<<<<
6897 11:54:58.698486 [ANA_INIT] flow end
6898 11:54:58.701972 ============ LP4 DIFF to SE enter ============
6899 11:54:58.705111 ============ LP4 DIFF to SE exit ============
6900 11:54:58.708599 [ANA_INIT] <<<<<<<<<<<<<
6901 11:54:58.711993 [Flow] Enable top DCM control >>>>>
6902 11:54:58.715404 [Flow] Enable top DCM control <<<<<
6903 11:54:58.718465 Enable DLL master slave shuffle
6904 11:54:58.721550 ==============================================================
6905 11:54:58.724762 Gating Mode config
6906 11:54:58.731796 ==============================================================
6907 11:54:58.732353 Config description:
6908 11:54:58.741261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6909 11:54:58.748294 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6910 11:54:58.751495 SELPH_MODE 0: By rank 1: By Phase
6911 11:54:58.757967 ==============================================================
6912 11:54:58.761423 GAT_TRACK_EN = 1
6913 11:54:58.764427 RX_GATING_MODE = 2
6914 11:54:58.767970 RX_GATING_TRACK_MODE = 2
6915 11:54:58.771043 SELPH_MODE = 1
6916 11:54:58.774949 PICG_EARLY_EN = 1
6917 11:54:58.778227 VALID_LAT_VALUE = 1
6918 11:54:58.781219 ==============================================================
6919 11:54:58.784560 Enter into Gating configuration >>>>
6920 11:54:58.787736 Exit from Gating configuration <<<<
6921 11:54:58.791221 Enter into DVFS_PRE_config >>>>>
6922 11:54:58.804305 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6923 11:54:58.807868 Exit from DVFS_PRE_config <<<<<
6924 11:54:58.808422 Enter into PICG configuration >>>>
6925 11:54:58.811111 Exit from PICG configuration <<<<
6926 11:54:58.814386 [RX_INPUT] configuration >>>>>
6927 11:54:58.817812 [RX_INPUT] configuration <<<<<
6928 11:54:58.824255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6929 11:54:58.827685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6930 11:54:58.834204 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6931 11:54:58.840764 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6932 11:54:58.847405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6933 11:54:58.853966 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6934 11:54:58.857447 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6935 11:54:58.860884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6936 11:54:58.864179 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6937 11:54:58.870601 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6938 11:54:58.874188 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6939 11:54:58.877240 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6940 11:54:58.880390 ===================================
6941 11:54:58.884158 LPDDR4 DRAM CONFIGURATION
6942 11:54:58.887106 ===================================
6943 11:54:58.890583 EX_ROW_EN[0] = 0x0
6944 11:54:58.891137 EX_ROW_EN[1] = 0x0
6945 11:54:58.893792 LP4Y_EN = 0x0
6946 11:54:58.894341 WORK_FSP = 0x1
6947 11:54:58.897406 WL = 0x5
6948 11:54:58.897961 RL = 0x5
6949 11:54:58.900752 BL = 0x2
6950 11:54:58.901301 RPST = 0x0
6951 11:54:58.903698 RD_PRE = 0x0
6952 11:54:58.904250 WR_PRE = 0x1
6953 11:54:58.907009 WR_PST = 0x1
6954 11:54:58.907564 DBI_WR = 0x0
6955 11:54:58.910190 DBI_RD = 0x0
6956 11:54:58.910702 OTF = 0x1
6957 11:54:58.913392 ===================================
6958 11:54:58.920275 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6959 11:54:58.923747 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6960 11:54:58.927069 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
6961 11:54:58.930293 ===================================
6962 11:54:58.933362 LPDDR4 DRAM CONFIGURATION
6963 11:54:58.936486 ===================================
6964 11:54:58.939900 EX_ROW_EN[0] = 0x10
6965 11:54:58.940369 EX_ROW_EN[1] = 0x0
6966 11:54:58.943149 LP4Y_EN = 0x0
6967 11:54:58.943612 WORK_FSP = 0x1
6968 11:54:58.946790 WL = 0x5
6969 11:54:58.947338 RL = 0x5
6970 11:54:58.950123 BL = 0x2
6971 11:54:58.950575 RPST = 0x0
6972 11:54:58.952985 RD_PRE = 0x0
6973 11:54:58.953442 WR_PRE = 0x1
6974 11:54:58.956568 WR_PST = 0x1
6975 11:54:58.957021 DBI_WR = 0x0
6976 11:54:58.960014 DBI_RD = 0x0
6977 11:54:58.960426 OTF = 0x1
6978 11:54:58.963372 ===================================
6979 11:54:58.969643 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6980 11:54:58.970161 ==
6981 11:54:58.973372 Dram Type= 6, Freq= 0, CH_0, rank 0
6982 11:54:58.979460 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
6983 11:54:58.979881 ==
6984 11:54:58.980213 [Duty_Offset_Calibration]
6985 11:54:58.982922 B0:0 B1:2 CA:1
6986 11:54:58.983432
6987 11:54:58.986563 [DutyScan_Calibration_Flow] k_type=0
6988 11:54:58.996023
6989 11:54:58.996553 ==CLK 0==
6990 11:54:58.999151 Final CLK duty delay cell = 0
6991 11:54:59.002566 [0] MAX Duty = 5187%(X100), DQS PI = 24
6992 11:54:59.006009 [0] MIN Duty = 4938%(X100), DQS PI = 54
6993 11:54:59.006525 [0] AVG Duty = 5062%(X100)
6994 11:54:59.008828
6995 11:54:59.012317 CH0 CLK Duty spec in!! Max-Min= 249%
6996 11:54:59.015913 [DutyScan_Calibration_Flow] ====Done====
6997 11:54:59.016421
6998 11:54:59.018599 [DutyScan_Calibration_Flow] k_type=1
6999 11:54:59.034907
7000 11:54:59.035459 ==DQS 0 ==
7001 11:54:59.038511 Final DQS duty delay cell = -4
7002 11:54:59.041458 [-4] MAX Duty = 4969%(X100), DQS PI = 2
7003 11:54:59.044982 [-4] MIN Duty = 4875%(X100), DQS PI = 8
7004 11:54:59.048083 [-4] AVG Duty = 4922%(X100)
7005 11:54:59.048563
7006 11:54:59.048930 ==DQS 1 ==
7007 11:54:59.051463 Final DQS duty delay cell = 0
7008 11:54:59.054666 [0] MAX Duty = 5031%(X100), DQS PI = 0
7009 11:54:59.058282 [0] MIN Duty = 4876%(X100), DQS PI = 16
7010 11:54:59.061648 [0] AVG Duty = 4953%(X100)
7011 11:54:59.062204
7012 11:54:59.065315 CH0 DQS 0 Duty spec in!! Max-Min= 94%
7013 11:54:59.065872
7014 11:54:59.068175 CH0 DQS 1 Duty spec in!! Max-Min= 155%
7015 11:54:59.071363 [DutyScan_Calibration_Flow] ====Done====
7016 11:54:59.071913
7017 11:54:59.074661 [DutyScan_Calibration_Flow] k_type=3
7018 11:54:59.092268
7019 11:54:59.092863 ==DQM 0 ==
7020 11:54:59.095592 Final DQM duty delay cell = 0
7021 11:54:59.098840 [0] MAX Duty = 5187%(X100), DQS PI = 22
7022 11:54:59.102253 [0] MIN Duty = 4907%(X100), DQS PI = 42
7023 11:54:59.105399 [0] AVG Duty = 5047%(X100)
7024 11:54:59.105949
7025 11:54:59.106317 ==DQM 1 ==
7026 11:54:59.108615 Final DQM duty delay cell = 0
7027 11:54:59.111926 [0] MAX Duty = 5031%(X100), DQS PI = 50
7028 11:54:59.115399 [0] MIN Duty = 4782%(X100), DQS PI = 12
7029 11:54:59.118227 [0] AVG Duty = 4906%(X100)
7030 11:54:59.118656
7031 11:54:59.121823 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7032 11:54:59.122378
7033 11:54:59.125190 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7034 11:54:59.128414 [DutyScan_Calibration_Flow] ====Done====
7035 11:54:59.129028
7036 11:54:59.131710 [DutyScan_Calibration_Flow] k_type=2
7037 11:54:59.148573
7038 11:54:59.149127 ==DQ 0 ==
7039 11:54:59.151645 Final DQ duty delay cell = 0
7040 11:54:59.154958 [0] MAX Duty = 5218%(X100), DQS PI = 18
7041 11:54:59.158620 [0] MIN Duty = 4938%(X100), DQS PI = 56
7042 11:54:59.159171 [0] AVG Duty = 5078%(X100)
7043 11:54:59.161914
7044 11:54:59.162467 ==DQ 1 ==
7045 11:54:59.164989 Final DQ duty delay cell = -4
7046 11:54:59.168274 [-4] MAX Duty = 5062%(X100), DQS PI = 4
7047 11:54:59.171992 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7048 11:54:59.174991 [-4] AVG Duty = 4953%(X100)
7049 11:54:59.175536
7050 11:54:59.178308 CH0 DQ 0 Duty spec in!! Max-Min= 280%
7051 11:54:59.178766
7052 11:54:59.181821 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7053 11:54:59.185538 [DutyScan_Calibration_Flow] ====Done====
7054 11:54:59.186094 ==
7055 11:54:59.188346 Dram Type= 6, Freq= 0, CH_1, rank 0
7056 11:54:59.191840 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7057 11:54:59.192398 ==
7058 11:54:59.195206 [Duty_Offset_Calibration]
7059 11:54:59.195751 B0:0 B1:5 CA:-5
7060 11:54:59.196117
7061 11:54:59.198378 [DutyScan_Calibration_Flow] k_type=0
7062 11:54:59.209510
7063 11:54:59.210062 ==CLK 0==
7064 11:54:59.212247 Final CLK duty delay cell = 0
7065 11:54:59.215956 [0] MAX Duty = 5156%(X100), DQS PI = 20
7066 11:54:59.219252 [0] MIN Duty = 4906%(X100), DQS PI = 52
7067 11:54:59.219713 [0] AVG Duty = 5031%(X100)
7068 11:54:59.222608
7069 11:54:59.225744 CH1 CLK Duty spec in!! Max-Min= 250%
7070 11:54:59.228988 [DutyScan_Calibration_Flow] ====Done====
7071 11:54:59.229452
7072 11:54:59.232302 [DutyScan_Calibration_Flow] k_type=1
7073 11:54:59.248089
7074 11:54:59.248701 ==DQS 0 ==
7075 11:54:59.251474 Final DQS duty delay cell = 0
7076 11:54:59.255075 [0] MAX Duty = 5156%(X100), DQS PI = 18
7077 11:54:59.257706 [0] MIN Duty = 4844%(X100), DQS PI = 44
7078 11:54:59.260998 [0] AVG Duty = 5000%(X100)
7079 11:54:59.261454
7080 11:54:59.261820 ==DQS 1 ==
7081 11:54:59.264802 Final DQS duty delay cell = -4
7082 11:54:59.268116 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7083 11:54:59.271065 [-4] MIN Duty = 4844%(X100), DQS PI = 38
7084 11:54:59.274613 [-4] AVG Duty = 4922%(X100)
7085 11:54:59.275164
7086 11:54:59.277671 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7087 11:54:59.278264
7088 11:54:59.281128 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7089 11:54:59.284414 [DutyScan_Calibration_Flow] ====Done====
7090 11:54:59.285028
7091 11:54:59.287739 [DutyScan_Calibration_Flow] k_type=3
7092 11:54:59.303797
7093 11:54:59.304348 ==DQM 0 ==
7094 11:54:59.307166 Final DQM duty delay cell = -4
7095 11:54:59.310291 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7096 11:54:59.313767 [-4] MIN Duty = 4813%(X100), DQS PI = 42
7097 11:54:59.317192 [-4] AVG Duty = 4937%(X100)
7098 11:54:59.317744
7099 11:54:59.318108 ==DQM 1 ==
7100 11:54:59.320271 Final DQM duty delay cell = -4
7101 11:54:59.323784 [-4] MAX Duty = 5062%(X100), DQS PI = 0
7102 11:54:59.326932 [-4] MIN Duty = 4907%(X100), DQS PI = 38
7103 11:54:59.330139 [-4] AVG Duty = 4984%(X100)
7104 11:54:59.330619
7105 11:54:59.333500 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7106 11:54:59.333958
7107 11:54:59.336999 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7108 11:54:59.340164 [DutyScan_Calibration_Flow] ====Done====
7109 11:54:59.340749
7110 11:54:59.343732 [DutyScan_Calibration_Flow] k_type=2
7111 11:54:59.361479
7112 11:54:59.362026 ==DQ 0 ==
7113 11:54:59.364326 Final DQ duty delay cell = 0
7114 11:54:59.368246 [0] MAX Duty = 5093%(X100), DQS PI = 20
7115 11:54:59.371075 [0] MIN Duty = 4969%(X100), DQS PI = 46
7116 11:54:59.371621 [0] AVG Duty = 5031%(X100)
7117 11:54:59.374487
7118 11:54:59.375039 ==DQ 1 ==
7119 11:54:59.377529 Final DQ duty delay cell = 0
7120 11:54:59.381210 [0] MAX Duty = 5062%(X100), DQS PI = 6
7121 11:54:59.384413 [0] MIN Duty = 4876%(X100), DQS PI = 24
7122 11:54:59.385010 [0] AVG Duty = 4969%(X100)
7123 11:54:59.385382
7124 11:54:59.390956 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7125 11:54:59.391414
7126 11:54:59.394614 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7127 11:54:59.397486 [DutyScan_Calibration_Flow] ====Done====
7128 11:54:59.400905 nWR fixed to 30
7129 11:54:59.401471 [ModeRegInit_LP4] CH0 RK0
7130 11:54:59.404172 [ModeRegInit_LP4] CH0 RK1
7131 11:54:59.407701 [ModeRegInit_LP4] CH1 RK0
7132 11:54:59.410865 [ModeRegInit_LP4] CH1 RK1
7133 11:54:59.411429 match AC timing 4
7134 11:54:59.413965 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 0
7135 11:54:59.420974 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7136 11:54:59.424145 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7137 11:54:59.430779 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7138 11:54:59.433796 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7139 11:54:59.434259 [MiockJmeterHQA]
7140 11:54:59.434625
7141 11:54:59.437434 [DramcMiockJmeter] u1RxGatingPI = 0
7142 11:54:59.440504 0 : 4363, 4137
7143 11:54:59.441117 4 : 4253, 4027
7144 11:54:59.444054 8 : 4368, 4140
7145 11:54:59.444802 12 : 4257, 4029
7146 11:54:59.445303 16 : 4368, 4140
7147 11:54:59.447118 20 : 4363, 4137
7148 11:54:59.447582 24 : 4250, 4024
7149 11:54:59.450734 28 : 4250, 4027
7150 11:54:59.451200 32 : 4363, 4138
7151 11:54:59.453673 36 : 4252, 4027
7152 11:54:59.454231 40 : 4360, 4138
7153 11:54:59.457098 44 : 4249, 4027
7154 11:54:59.457566 48 : 4250, 4027
7155 11:54:59.457937 52 : 4250, 4027
7156 11:54:59.460158 56 : 4250, 4026
7157 11:54:59.460657 60 : 4250, 4027
7158 11:54:59.463553 64 : 4361, 4137
7159 11:54:59.464109 68 : 4250, 4026
7160 11:54:59.467410 72 : 4250, 4027
7161 11:54:59.468038 76 : 4250, 4026
7162 11:54:59.470222 80 : 4250, 4027
7163 11:54:59.470786 84 : 4363, 4138
7164 11:54:59.471166 88 : 4250, 4027
7165 11:54:59.473731 92 : 4363, 4140
7166 11:54:59.474286 96 : 4252, 4029
7167 11:54:59.476909 100 : 4363, 2333
7168 11:54:59.477379 104 : 4360, 0
7169 11:54:59.480107 108 : 4250, 0
7170 11:54:59.480621 112 : 4363, 0
7171 11:54:59.481004 116 : 4363, 0
7172 11:54:59.483685 120 : 4363, 0
7173 11:54:59.484243 124 : 4250, 0
7174 11:54:59.486966 128 : 4250, 0
7175 11:54:59.487526 132 : 4250, 0
7176 11:54:59.487901 136 : 4253, 0
7177 11:54:59.490152 140 : 4249, 0
7178 11:54:59.490731 144 : 4250, 0
7179 11:54:59.491111 148 : 4255, 0
7180 11:54:59.493198 152 : 4360, 0
7181 11:54:59.493665 156 : 4361, 0
7182 11:54:59.496577 160 : 4250, 0
7183 11:54:59.497147 164 : 4250, 0
7184 11:54:59.497526 168 : 4361, 0
7185 11:54:59.500185 172 : 4361, 0
7186 11:54:59.500797 176 : 4250, 0
7187 11:54:59.503280 180 : 4250, 0
7188 11:54:59.503845 184 : 4250, 0
7189 11:54:59.504223 188 : 4253, 0
7190 11:54:59.506654 192 : 4249, 0
7191 11:54:59.507158 196 : 4250, 0
7192 11:54:59.510321 200 : 4255, 0
7193 11:54:59.510887 204 : 4361, 0
7194 11:54:59.511267 208 : 4361, 0
7195 11:54:59.513230 212 : 4250, 0
7196 11:54:59.513698 216 : 4250, 0
7197 11:54:59.516577 220 : 4360, 445
7198 11:54:59.517053 224 : 4250, 3986
7199 11:54:59.517425 228 : 4360, 4137
7200 11:54:59.520275 232 : 4250, 4027
7201 11:54:59.520899 236 : 4252, 4027
7202 11:54:59.523465 240 : 4250, 4026
7203 11:54:59.524023 244 : 4252, 4029
7204 11:54:59.526600 248 : 4250, 4026
7205 11:54:59.527178 252 : 4360, 4138
7206 11:54:59.530071 256 : 4250, 4027
7207 11:54:59.530633 260 : 4250, 4026
7208 11:54:59.532998 264 : 4361, 4137
7209 11:54:59.533486 268 : 4360, 4138
7210 11:54:59.536566 272 : 4249, 4027
7211 11:54:59.537041 276 : 4250, 4027
7212 11:54:59.539830 280 : 4250, 4027
7213 11:54:59.540298 284 : 4253, 4029
7214 11:54:59.543216 288 : 4250, 4027
7215 11:54:59.543775 292 : 4254, 4030
7216 11:54:59.544150 296 : 4253, 4029
7217 11:54:59.546784 300 : 4250, 4027
7218 11:54:59.547249 304 : 4250, 4026
7219 11:54:59.549813 308 : 4250, 4027
7220 11:54:59.550379 312 : 4250, 4026
7221 11:54:59.552951 316 : 4361, 4137
7222 11:54:59.553420 320 : 4366, 4140
7223 11:54:59.556301 324 : 4250, 4027
7224 11:54:59.556832 328 : 4250, 4027
7225 11:54:59.559605 332 : 4252, 4030
7226 11:54:59.560073 336 : 4252, 3973
7227 11:54:59.563119 340 : 4250, 1939
7228 11:54:59.563715
7229 11:54:59.564093 MIOCK jitter meter ch=0
7230 11:54:59.564440
7231 11:54:59.566231 1T = (340-104) = 236 dly cells
7232 11:54:59.572741 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7233 11:54:59.573199 ==
7234 11:54:59.576082 Dram Type= 6, Freq= 0, CH_0, rank 0
7235 11:54:59.579579 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7236 11:54:59.580035 ==
7237 11:54:59.586053 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7238 11:54:59.589256 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7239 11:54:59.592583 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7240 11:54:59.599615 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7241 11:54:59.608806 [CA 0] Center 42 (12~73) winsize 62
7242 11:54:59.611608 [CA 1] Center 42 (12~73) winsize 62
7243 11:54:59.615174 [CA 2] Center 39 (9~69) winsize 61
7244 11:54:59.618550 [CA 3] Center 38 (9~68) winsize 60
7245 11:54:59.621907 [CA 4] Center 37 (7~67) winsize 61
7246 11:54:59.625058 [CA 5] Center 36 (6~66) winsize 61
7247 11:54:59.625471
7248 11:54:59.628584 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7249 11:54:59.629119
7250 11:54:59.631916 [CATrainingPosCal] consider 1 rank data
7251 11:54:59.635169 u2DelayCellTimex100 = 275/100 ps
7252 11:54:59.638153 CA0 delay=42 (12~73),Diff = 6 PI (21 cell)
7253 11:54:59.645024 CA1 delay=42 (12~73),Diff = 6 PI (21 cell)
7254 11:54:59.648570 CA2 delay=39 (9~69),Diff = 3 PI (10 cell)
7255 11:54:59.651561 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7256 11:54:59.654776 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7257 11:54:59.658497 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7258 11:54:59.659115
7259 11:54:59.661810 CA PerBit enable=1, Macro0, CA PI delay=36
7260 11:54:59.662267
7261 11:54:59.664877 [CBTSetCACLKResult] CA Dly = 36
7262 11:54:59.667996 CS Dly: 10 (0~41)
7263 11:54:59.671623 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7264 11:54:59.675406 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7265 11:54:59.675917 ==
7266 11:54:59.678223 Dram Type= 6, Freq= 0, CH_0, rank 1
7267 11:54:59.681608 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7268 11:54:59.684728 ==
7269 11:54:59.688610 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7270 11:54:59.691509 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7271 11:54:59.698140 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7272 11:54:59.701510 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7273 11:54:59.711257 [CA 0] Center 42 (12~73) winsize 62
7274 11:54:59.714438 [CA 1] Center 41 (11~72) winsize 62
7275 11:54:59.717761 [CA 2] Center 38 (9~68) winsize 60
7276 11:54:59.721079 [CA 3] Center 37 (8~67) winsize 60
7277 11:54:59.724198 [CA 4] Center 35 (5~65) winsize 61
7278 11:54:59.728057 [CA 5] Center 35 (5~65) winsize 61
7279 11:54:59.728652
7280 11:54:59.731006 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7281 11:54:59.731561
7282 11:54:59.734333 [CATrainingPosCal] consider 2 rank data
7283 11:54:59.737447 u2DelayCellTimex100 = 275/100 ps
7284 11:54:59.740909 CA0 delay=42 (12~73),Diff = 7 PI (24 cell)
7285 11:54:59.747399 CA1 delay=42 (12~72),Diff = 7 PI (24 cell)
7286 11:54:59.751138 CA2 delay=38 (9~68),Diff = 3 PI (10 cell)
7287 11:54:59.754188 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7288 11:54:59.757175 CA4 delay=36 (7~65),Diff = 1 PI (3 cell)
7289 11:54:59.761307 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7290 11:54:59.761871
7291 11:54:59.764028 CA PerBit enable=1, Macro0, CA PI delay=35
7292 11:54:59.764490
7293 11:54:59.767232 [CBTSetCACLKResult] CA Dly = 35
7294 11:54:59.770345 CS Dly: 11 (0~43)
7295 11:54:59.773743 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7296 11:54:59.777032 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7297 11:54:59.777512
7298 11:54:59.780652 ----->DramcWriteLeveling(PI) begin...
7299 11:54:59.781264 ==
7300 11:54:59.783857 Dram Type= 6, Freq= 0, CH_0, rank 0
7301 11:54:59.790369 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7302 11:54:59.790788 ==
7303 11:54:59.794169 Write leveling (Byte 0): 30 => 30
7304 11:54:59.797162 Write leveling (Byte 1): 25 => 25
7305 11:54:59.797581 DramcWriteLeveling(PI) end<-----
7306 11:54:59.797907
7307 11:54:59.800499 ==
7308 11:54:59.804032 Dram Type= 6, Freq= 0, CH_0, rank 0
7309 11:54:59.806988 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7310 11:54:59.807489 ==
7311 11:54:59.810766 [Gating] SW mode calibration
7312 11:54:59.817033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7313 11:54:59.820392 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7314 11:54:59.827067 0 12 0 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
7315 11:54:59.830276 0 12 4 | B1->B0 | 2423 3333 | 1 0 | (0 0) (0 0)
7316 11:54:59.833921 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7317 11:54:59.840557 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7318 11:54:59.843483 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7319 11:54:59.846883 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7320 11:54:59.853557 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7321 11:54:59.857001 0 12 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7322 11:54:59.860308 0 13 0 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
7323 11:54:59.866940 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
7324 11:54:59.870362 0 13 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7325 11:54:59.873585 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7326 11:54:59.880065 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7327 11:54:59.883398 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7328 11:54:59.886717 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7329 11:54:59.893139 0 13 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7330 11:54:59.897043 0 14 0 | B1->B0 | 2424 3b3b | 0 0 | (0 0) (0 0)
7331 11:54:59.900252 0 14 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
7332 11:54:59.907059 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7333 11:54:59.910063 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7334 11:54:59.913444 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7335 11:54:59.920035 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7336 11:54:59.923491 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7337 11:54:59.926843 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7338 11:54:59.933313 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7339 11:54:59.936605 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7340 11:54:59.939713 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7341 11:54:59.943044 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7342 11:54:59.949868 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7343 11:54:59.953061 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7344 11:54:59.956205 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7345 11:54:59.962859 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7346 11:54:59.966468 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7347 11:54:59.969634 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7348 11:54:59.976658 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7349 11:54:59.979634 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7350 11:54:59.982873 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7351 11:54:59.989376 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7352 11:54:59.992864 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7353 11:54:59.996051 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7354 11:55:00.002949 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7355 11:55:00.006093 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7356 11:55:00.009141 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7357 11:55:00.012783 Total UI for P1: 0, mck2ui 16
7358 11:55:00.016047 best dqsien dly found for B0: ( 1, 1, 0)
7359 11:55:00.019584 Total UI for P1: 0, mck2ui 16
7360 11:55:00.022846 best dqsien dly found for B1: ( 1, 1, 0)
7361 11:55:00.026081 best DQS0 dly(MCK, UI, PI) = (1, 1, 0)
7362 11:55:00.029158 best DQS1 dly(MCK, UI, PI) = (1, 1, 0)
7363 11:55:00.029625
7364 11:55:00.035528 best DQS0 P1 dly(MCK, UI, PI) = (1, 5, 0)
7365 11:55:00.039270 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 0)
7366 11:55:00.039853 [Gating] SW calibration Done
7367 11:55:00.042383 ==
7368 11:55:00.042845 Dram Type= 6, Freq= 0, CH_0, rank 0
7369 11:55:00.048858 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7370 11:55:00.049486 ==
7371 11:55:00.050118 RX Vref Scan: 0
7372 11:55:00.050518
7373 11:55:00.052301 RX Vref 0 -> 0, step: 1
7374 11:55:00.052818
7375 11:55:00.055717 RX Delay 0 -> 252, step: 8
7376 11:55:00.058937 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7377 11:55:00.062563 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7378 11:55:00.066280 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
7379 11:55:00.072420 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7380 11:55:00.075736 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7381 11:55:00.079207 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7382 11:55:00.082506 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7383 11:55:00.085858 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
7384 11:55:00.092068 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
7385 11:55:00.095692 iDelay=200, Bit 9, Center 107 (56 ~ 159) 104
7386 11:55:00.098829 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7387 11:55:00.102114 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7388 11:55:00.105544 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7389 11:55:00.112086 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7390 11:55:00.115492 iDelay=200, Bit 14, Center 139 (80 ~ 199) 120
7391 11:55:00.118568 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7392 11:55:00.119036 ==
7393 11:55:00.122346 Dram Type= 6, Freq= 0, CH_0, rank 0
7394 11:55:00.125278 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7395 11:55:00.128953 ==
7396 11:55:00.129504 DQS Delay:
7397 11:55:00.129920 DQS0 = 0, DQS1 = 0
7398 11:55:00.131908 DQM Delay:
7399 11:55:00.132370 DQM0 = 129, DQM1 = 124
7400 11:55:00.135278 DQ Delay:
7401 11:55:00.138945 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =127
7402 11:55:00.141997 DQ4 =135, DQ5 =119, DQ6 =135, DQ7 =139
7403 11:55:00.145504 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
7404 11:55:00.148592 DQ12 =131, DQ13 =131, DQ14 =139, DQ15 =135
7405 11:55:00.149128
7406 11:55:00.149500
7407 11:55:00.149839 ==
7408 11:55:00.151926 Dram Type= 6, Freq= 0, CH_0, rank 0
7409 11:55:00.155271 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7410 11:55:00.155838 ==
7411 11:55:00.156209
7412 11:55:00.156602
7413 11:55:00.158504 TX Vref Scan disable
7414 11:55:00.162039 == TX Byte 0 ==
7415 11:55:00.165113 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
7416 11:55:00.168473 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
7417 11:55:00.172362 == TX Byte 1 ==
7418 11:55:00.175391 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7419 11:55:00.178577 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7420 11:55:00.179139 ==
7421 11:55:00.181813 Dram Type= 6, Freq= 0, CH_0, rank 0
7422 11:55:00.188214 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7423 11:55:00.188858 ==
7424 11:55:00.199971
7425 11:55:00.203734 TX Vref early break, caculate TX vref
7426 11:55:00.206848 TX Vref=16, minBit 6, minWin=22, winSum=368
7427 11:55:00.209912 TX Vref=18, minBit 6, minWin=22, winSum=375
7428 11:55:00.213340 TX Vref=20, minBit 2, minWin=23, winSum=381
7429 11:55:00.216738 TX Vref=22, minBit 10, minWin=23, winSum=392
7430 11:55:00.220183 TX Vref=24, minBit 0, minWin=24, winSum=399
7431 11:55:00.226427 TX Vref=26, minBit 1, minWin=25, winSum=409
7432 11:55:00.229811 TX Vref=28, minBit 8, minWin=24, winSum=409
7433 11:55:00.233396 TX Vref=30, minBit 0, minWin=24, winSum=402
7434 11:55:00.236848 TX Vref=32, minBit 0, minWin=24, winSum=396
7435 11:55:00.239851 TX Vref=34, minBit 6, minWin=22, winSum=382
7436 11:55:00.246699 [TxChooseVref] Worse bit 1, Min win 25, Win sum 409, Final Vref 26
7437 11:55:00.247303
7438 11:55:00.249745 Final TX Range 0 Vref 26
7439 11:55:00.250210
7440 11:55:00.250577 ==
7441 11:55:00.253306 Dram Type= 6, Freq= 0, CH_0, rank 0
7442 11:55:00.256295 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7443 11:55:00.256793 ==
7444 11:55:00.257165
7445 11:55:00.257509
7446 11:55:00.259919 TX Vref Scan disable
7447 11:55:00.266830 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7448 11:55:00.267389 == TX Byte 0 ==
7449 11:55:00.269778 u2DelayCellOfst[0]=10 cells (3 PI)
7450 11:55:00.272806 u2DelayCellOfst[1]=17 cells (5 PI)
7451 11:55:00.276479 u2DelayCellOfst[2]=10 cells (3 PI)
7452 11:55:00.279691 u2DelayCellOfst[3]=10 cells (3 PI)
7453 11:55:00.283024 u2DelayCellOfst[4]=7 cells (2 PI)
7454 11:55:00.286405 u2DelayCellOfst[5]=0 cells (0 PI)
7455 11:55:00.289635 u2DelayCellOfst[6]=17 cells (5 PI)
7456 11:55:00.292571 u2DelayCellOfst[7]=14 cells (4 PI)
7457 11:55:00.296096 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7458 11:55:00.299420 Update DQM dly =986 (3 ,6, 26) DQM OEN =(3 ,3)
7459 11:55:00.302925 == TX Byte 1 ==
7460 11:55:00.306322 u2DelayCellOfst[8]=0 cells (0 PI)
7461 11:55:00.306876 u2DelayCellOfst[9]=0 cells (0 PI)
7462 11:55:00.309507 u2DelayCellOfst[10]=7 cells (2 PI)
7463 11:55:00.312900 u2DelayCellOfst[11]=3 cells (1 PI)
7464 11:55:00.316082 u2DelayCellOfst[12]=14 cells (4 PI)
7465 11:55:00.319138 u2DelayCellOfst[13]=14 cells (4 PI)
7466 11:55:00.322656 u2DelayCellOfst[14]=14 cells (4 PI)
7467 11:55:00.325880 u2DelayCellOfst[15]=14 cells (4 PI)
7468 11:55:00.329169 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
7469 11:55:00.335832 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
7470 11:55:00.336676 DramC Write-DBI on
7471 11:55:00.337217 ==
7472 11:55:00.339149 Dram Type= 6, Freq= 0, CH_0, rank 0
7473 11:55:00.345751 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7474 11:55:00.346213 ==
7475 11:55:00.346574
7476 11:55:00.346915
7477 11:55:00.347434 TX Vref Scan disable
7478 11:55:00.349473 == TX Byte 0 ==
7479 11:55:00.353227 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7480 11:55:00.356150 == TX Byte 1 ==
7481 11:55:00.359877 Update DQM dly =719 (2 ,6, 15) DQM OEN =(3 ,3)
7482 11:55:00.362883 DramC Write-DBI off
7483 11:55:00.363461
7484 11:55:00.363840 [DATLAT]
7485 11:55:00.364181 Freq=1600, CH0 RK0
7486 11:55:00.364556
7487 11:55:00.366021 DATLAT Default: 0xf
7488 11:55:00.366479 0, 0xFFFF, sum = 0
7489 11:55:00.369785 1, 0xFFFF, sum = 0
7490 11:55:00.372808 2, 0xFFFF, sum = 0
7491 11:55:00.373272 3, 0xFFFF, sum = 0
7492 11:55:00.376316 4, 0xFFFF, sum = 0
7493 11:55:00.376839 5, 0xFFFF, sum = 0
7494 11:55:00.379447 6, 0xFFFF, sum = 0
7495 11:55:00.379908 7, 0xFFFF, sum = 0
7496 11:55:00.382542 8, 0xFFFF, sum = 0
7497 11:55:00.383015 9, 0xFFFF, sum = 0
7498 11:55:00.386176 10, 0xFFFF, sum = 0
7499 11:55:00.386736 11, 0xFFFF, sum = 0
7500 11:55:00.389082 12, 0xFFF, sum = 0
7501 11:55:00.389547 13, 0x0, sum = 1
7502 11:55:00.392615 14, 0x0, sum = 2
7503 11:55:00.393085 15, 0x0, sum = 3
7504 11:55:00.396252 16, 0x0, sum = 4
7505 11:55:00.396871 best_step = 14
7506 11:55:00.397242
7507 11:55:00.397580 ==
7508 11:55:00.399395 Dram Type= 6, Freq= 0, CH_0, rank 0
7509 11:55:00.402950 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7510 11:55:00.406344 ==
7511 11:55:00.406897 RX Vref Scan: 1
7512 11:55:00.407263
7513 11:55:00.409214 Set Vref Range= 24 -> 127
7514 11:55:00.409673
7515 11:55:00.412750 RX Vref 24 -> 127, step: 1
7516 11:55:00.413307
7517 11:55:00.413671 RX Delay 11 -> 252, step: 4
7518 11:55:00.414010
7519 11:55:00.415591 Set Vref, RX VrefLevel [Byte0]: 24
7520 11:55:00.419132 [Byte1]: 24
7521 11:55:00.423198
7522 11:55:00.423754 Set Vref, RX VrefLevel [Byte0]: 25
7523 11:55:00.426464 [Byte1]: 25
7524 11:55:00.430737
7525 11:55:00.431292 Set Vref, RX VrefLevel [Byte0]: 26
7526 11:55:00.434418 [Byte1]: 26
7527 11:55:00.438352
7528 11:55:00.438905 Set Vref, RX VrefLevel [Byte0]: 27
7529 11:55:00.441395 [Byte1]: 27
7530 11:55:00.445927
7531 11:55:00.446454 Set Vref, RX VrefLevel [Byte0]: 28
7532 11:55:00.448868 [Byte1]: 28
7533 11:55:00.453398
7534 11:55:00.453858 Set Vref, RX VrefLevel [Byte0]: 29
7535 11:55:00.456723 [Byte1]: 29
7536 11:55:00.461178
7537 11:55:00.461645 Set Vref, RX VrefLevel [Byte0]: 30
7538 11:55:00.464220 [Byte1]: 30
7539 11:55:00.468472
7540 11:55:00.468975 Set Vref, RX VrefLevel [Byte0]: 31
7541 11:55:00.471759 [Byte1]: 31
7542 11:55:00.476378
7543 11:55:00.477004 Set Vref, RX VrefLevel [Byte0]: 32
7544 11:55:00.479519 [Byte1]: 32
7545 11:55:00.483930
7546 11:55:00.484484 Set Vref, RX VrefLevel [Byte0]: 33
7547 11:55:00.487395 [Byte1]: 33
7548 11:55:00.491760
7549 11:55:00.492294 Set Vref, RX VrefLevel [Byte0]: 34
7550 11:55:00.494871 [Byte1]: 34
7551 11:55:00.499173
7552 11:55:00.499727 Set Vref, RX VrefLevel [Byte0]: 35
7553 11:55:00.502486 [Byte1]: 35
7554 11:55:00.506755
7555 11:55:00.507301 Set Vref, RX VrefLevel [Byte0]: 36
7556 11:55:00.509912 [Byte1]: 36
7557 11:55:00.514323
7558 11:55:00.514880 Set Vref, RX VrefLevel [Byte0]: 37
7559 11:55:00.517488 [Byte1]: 37
7560 11:55:00.522203
7561 11:55:00.522755 Set Vref, RX VrefLevel [Byte0]: 38
7562 11:55:00.525126 [Byte1]: 38
7563 11:55:00.529459
7564 11:55:00.529995 Set Vref, RX VrefLevel [Byte0]: 39
7565 11:55:00.532923 [Byte1]: 39
7566 11:55:00.537229
7567 11:55:00.537748 Set Vref, RX VrefLevel [Byte0]: 40
7568 11:55:00.540310 [Byte1]: 40
7569 11:55:00.545044
7570 11:55:00.545611 Set Vref, RX VrefLevel [Byte0]: 41
7571 11:55:00.548047 [Byte1]: 41
7572 11:55:00.552230
7573 11:55:00.552737 Set Vref, RX VrefLevel [Byte0]: 42
7574 11:55:00.555825 [Byte1]: 42
7575 11:55:00.559966
7576 11:55:00.560544 Set Vref, RX VrefLevel [Byte0]: 43
7577 11:55:00.563408 [Byte1]: 43
7578 11:55:00.567479
7579 11:55:00.568036 Set Vref, RX VrefLevel [Byte0]: 44
7580 11:55:00.570893 [Byte1]: 44
7581 11:55:00.575032
7582 11:55:00.575486 Set Vref, RX VrefLevel [Byte0]: 45
7583 11:55:00.578533 [Byte1]: 45
7584 11:55:00.583049
7585 11:55:00.583607 Set Vref, RX VrefLevel [Byte0]: 46
7586 11:55:00.586002 [Byte1]: 46
7587 11:55:00.590512
7588 11:55:00.590968 Set Vref, RX VrefLevel [Byte0]: 47
7589 11:55:00.593736 [Byte1]: 47
7590 11:55:00.598022
7591 11:55:00.598478 Set Vref, RX VrefLevel [Byte0]: 48
7592 11:55:00.601325 [Byte1]: 48
7593 11:55:00.605765
7594 11:55:00.606314 Set Vref, RX VrefLevel [Byte0]: 49
7595 11:55:00.609325 [Byte1]: 49
7596 11:55:00.613271
7597 11:55:00.613744 Set Vref, RX VrefLevel [Byte0]: 50
7598 11:55:00.616651 [Byte1]: 50
7599 11:55:00.621013
7600 11:55:00.621470 Set Vref, RX VrefLevel [Byte0]: 51
7601 11:55:00.624185 [Byte1]: 51
7602 11:55:00.628740
7603 11:55:00.629292 Set Vref, RX VrefLevel [Byte0]: 52
7604 11:55:00.632237 [Byte1]: 52
7605 11:55:00.636248
7606 11:55:00.636874 Set Vref, RX VrefLevel [Byte0]: 53
7607 11:55:00.639598 [Byte1]: 53
7608 11:55:00.643836
7609 11:55:00.644432 Set Vref, RX VrefLevel [Byte0]: 54
7610 11:55:00.647025 [Byte1]: 54
7611 11:55:00.651054
7612 11:55:00.651530 Set Vref, RX VrefLevel [Byte0]: 55
7613 11:55:00.654329 [Byte1]: 55
7614 11:55:00.659346
7615 11:55:00.659905 Set Vref, RX VrefLevel [Byte0]: 56
7616 11:55:00.662067 [Byte1]: 56
7617 11:55:00.666589
7618 11:55:00.667045 Set Vref, RX VrefLevel [Byte0]: 57
7619 11:55:00.669888 [Byte1]: 57
7620 11:55:00.674066
7621 11:55:00.674521 Set Vref, RX VrefLevel [Byte0]: 58
7622 11:55:00.677229 [Byte1]: 58
7623 11:55:00.681735
7624 11:55:00.682288 Set Vref, RX VrefLevel [Byte0]: 59
7625 11:55:00.685149 [Byte1]: 59
7626 11:55:00.689311
7627 11:55:00.689878 Set Vref, RX VrefLevel [Byte0]: 60
7628 11:55:00.692918 [Byte1]: 60
7629 11:55:00.697399
7630 11:55:00.697957 Set Vref, RX VrefLevel [Byte0]: 61
7631 11:55:00.700638 [Byte1]: 61
7632 11:55:00.704600
7633 11:55:00.705178 Set Vref, RX VrefLevel [Byte0]: 62
7634 11:55:00.707995 [Byte1]: 62
7635 11:55:00.712310
7636 11:55:00.712913 Set Vref, RX VrefLevel [Byte0]: 63
7637 11:55:00.715438 [Byte1]: 63
7638 11:55:00.719803
7639 11:55:00.720362 Set Vref, RX VrefLevel [Byte0]: 64
7640 11:55:00.723137 [Byte1]: 64
7641 11:55:00.727452
7642 11:55:00.728020 Set Vref, RX VrefLevel [Byte0]: 65
7643 11:55:00.731125 [Byte1]: 65
7644 11:55:00.735340
7645 11:55:00.735893 Set Vref, RX VrefLevel [Byte0]: 66
7646 11:55:00.738743 [Byte1]: 66
7647 11:55:00.742426
7648 11:55:00.742883 Set Vref, RX VrefLevel [Byte0]: 67
7649 11:55:00.745901 [Byte1]: 67
7650 11:55:00.750187
7651 11:55:00.750754 Set Vref, RX VrefLevel [Byte0]: 68
7652 11:55:00.753542 [Byte1]: 68
7653 11:55:00.758107
7654 11:55:00.758663 Set Vref, RX VrefLevel [Byte0]: 69
7655 11:55:00.761240 [Byte1]: 69
7656 11:55:00.765492
7657 11:55:00.766046 Set Vref, RX VrefLevel [Byte0]: 70
7658 11:55:00.769042 [Byte1]: 70
7659 11:55:00.773200
7660 11:55:00.773776 Set Vref, RX VrefLevel [Byte0]: 71
7661 11:55:00.776371 [Byte1]: 71
7662 11:55:00.780839
7663 11:55:00.781643 Final RX Vref Byte 0 = 53 to rank0
7664 11:55:00.784020 Final RX Vref Byte 1 = 57 to rank0
7665 11:55:00.787849 Final RX Vref Byte 0 = 53 to rank1
7666 11:55:00.791004 Final RX Vref Byte 1 = 57 to rank1==
7667 11:55:00.794060 Dram Type= 6, Freq= 0, CH_0, rank 0
7668 11:55:00.800736 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7669 11:55:00.801293 ==
7670 11:55:00.801658 DQS Delay:
7671 11:55:00.804227 DQS0 = 0, DQS1 = 0
7672 11:55:00.804827 DQM Delay:
7673 11:55:00.805200 DQM0 = 127, DQM1 = 121
7674 11:55:00.807294 DQ Delay:
7675 11:55:00.810403 DQ0 =124, DQ1 =128, DQ2 =124, DQ3 =122
7676 11:55:00.814104 DQ4 =130, DQ5 =116, DQ6 =138, DQ7 =134
7677 11:55:00.817290 DQ8 =110, DQ9 =106, DQ10 =120, DQ11 =112
7678 11:55:00.820593 DQ12 =126, DQ13 =126, DQ14 =136, DQ15 =134
7679 11:55:00.821150
7680 11:55:00.821515
7681 11:55:00.821853
7682 11:55:00.824233 [DramC_TX_OE_Calibration] TA2
7683 11:55:00.827238 Original DQ_B0 (3 6) =30, OEN = 27
7684 11:55:00.830324 Original DQ_B1 (3 6) =30, OEN = 27
7685 11:55:00.834088 24, 0x0, End_B0=24 End_B1=24
7686 11:55:00.834659 25, 0x0, End_B0=25 End_B1=25
7687 11:55:00.836898 26, 0x0, End_B0=26 End_B1=26
7688 11:55:00.840755 27, 0x0, End_B0=27 End_B1=27
7689 11:55:00.843572 28, 0x0, End_B0=28 End_B1=28
7690 11:55:00.846633 29, 0x0, End_B0=29 End_B1=29
7691 11:55:00.847098 30, 0x0, End_B0=30 End_B1=30
7692 11:55:00.850077 31, 0x4141, End_B0=30 End_B1=30
7693 11:55:00.853687 Byte0 end_step=30 best_step=27
7694 11:55:00.856919 Byte1 end_step=30 best_step=27
7695 11:55:00.860014 Byte0 TX OE(2T, 0.5T) = (3, 3)
7696 11:55:00.863291 Byte1 TX OE(2T, 0.5T) = (3, 3)
7697 11:55:00.863751
7698 11:55:00.864116
7699 11:55:00.870128 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f1f, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 394 ps
7700 11:55:00.873210 CH0 RK0: MR19=303, MR18=1F1F
7701 11:55:00.880187 CH0_RK0: MR19=0x303, MR18=0x1F1F, DQSOSC=394, MR23=63, INC=23, DEC=15
7702 11:55:00.880760
7703 11:55:00.883236 ----->DramcWriteLeveling(PI) begin...
7704 11:55:00.883706 ==
7705 11:55:00.886716 Dram Type= 6, Freq= 0, CH_0, rank 1
7706 11:55:00.890224 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7707 11:55:00.890854 ==
7708 11:55:00.893149 Write leveling (Byte 0): 29 => 29
7709 11:55:00.897171 Write leveling (Byte 1): 26 => 26
7710 11:55:00.900197 DramcWriteLeveling(PI) end<-----
7711 11:55:00.900885
7712 11:55:00.901288 ==
7713 11:55:00.903291 Dram Type= 6, Freq= 0, CH_0, rank 1
7714 11:55:00.906448 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7715 11:55:00.906911 ==
7716 11:55:00.910005 [Gating] SW mode calibration
7717 11:55:00.916413 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7718 11:55:00.923340 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
7719 11:55:00.926221 0 12 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
7720 11:55:00.933496 0 12 4 | B1->B0 | 2929 3434 | 1 1 | (1 1) (1 1)
7721 11:55:00.936295 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7722 11:55:00.939898 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7723 11:55:00.946569 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7724 11:55:00.949765 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7725 11:55:00.953017 0 12 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7726 11:55:00.959641 0 12 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7727 11:55:00.962913 0 13 0 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (1 0)
7728 11:55:00.966084 0 13 4 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7729 11:55:00.969672 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7730 11:55:00.976262 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7731 11:55:00.979378 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7732 11:55:00.982951 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7733 11:55:00.989780 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7734 11:55:00.992702 0 13 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7735 11:55:00.996348 0 14 0 | B1->B0 | 2323 3d3d | 0 0 | (0 0) (0 0)
7736 11:55:01.003138 0 14 4 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
7737 11:55:01.006053 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7738 11:55:01.009533 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7739 11:55:01.016392 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 11:55:01.019759 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7741 11:55:01.022661 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7742 11:55:01.029451 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7743 11:55:01.032788 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7744 11:55:01.035818 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7745 11:55:01.042732 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7746 11:55:01.045951 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7747 11:55:01.049275 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7748 11:55:01.055614 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7749 11:55:01.059183 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7750 11:55:01.062788 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7751 11:55:01.069077 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7752 11:55:01.072070 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7753 11:55:01.075523 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7754 11:55:01.082177 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7755 11:55:01.085409 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7756 11:55:01.088927 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7757 11:55:01.095396 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7758 11:55:01.098976 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7759 11:55:01.102315 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7760 11:55:01.105463 Total UI for P1: 0, mck2ui 16
7761 11:55:01.109061 best dqsien dly found for B0: ( 1, 0, 28)
7762 11:55:01.115661 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7763 11:55:01.118980 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7764 11:55:01.122243 Total UI for P1: 0, mck2ui 16
7765 11:55:01.125649 best dqsien dly found for B1: ( 1, 1, 2)
7766 11:55:01.128991 best DQS0 dly(MCK, UI, PI) = (1, 0, 28)
7767 11:55:01.132314 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
7768 11:55:01.132915
7769 11:55:01.135204 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 28)
7770 11:55:01.139170 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
7771 11:55:01.141902 [Gating] SW calibration Done
7772 11:55:01.142549 ==
7773 11:55:01.145652 Dram Type= 6, Freq= 0, CH_0, rank 1
7774 11:55:01.148709 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7775 11:55:01.149276 ==
7776 11:55:01.151793 RX Vref Scan: 0
7777 11:55:01.152283
7778 11:55:01.155462 RX Vref 0 -> 0, step: 1
7779 11:55:01.155921
7780 11:55:01.156289 RX Delay 0 -> 252, step: 8
7781 11:55:01.162194 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7782 11:55:01.165197 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
7783 11:55:01.168964 iDelay=200, Bit 2, Center 131 (72 ~ 191) 120
7784 11:55:01.172197 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7785 11:55:01.175790 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
7786 11:55:01.178717 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7787 11:55:01.185245 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7788 11:55:01.188438 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7789 11:55:01.192000 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7790 11:55:01.194993 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7791 11:55:01.198319 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7792 11:55:01.205481 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7793 11:55:01.208454 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7794 11:55:01.211818 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7795 11:55:01.215059 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7796 11:55:01.221732 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7797 11:55:01.222274 ==
7798 11:55:01.225035 Dram Type= 6, Freq= 0, CH_0, rank 1
7799 11:55:01.228725 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7800 11:55:01.229284 ==
7801 11:55:01.229655 DQS Delay:
7802 11:55:01.231700 DQS0 = 0, DQS1 = 0
7803 11:55:01.232266 DQM Delay:
7804 11:55:01.235107 DQM0 = 131, DQM1 = 124
7805 11:55:01.235661 DQ Delay:
7806 11:55:01.238267 DQ0 =127, DQ1 =131, DQ2 =131, DQ3 =127
7807 11:55:01.241247 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =143
7808 11:55:01.244848 DQ8 =111, DQ9 =111, DQ10 =123, DQ11 =119
7809 11:55:01.248188 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7810 11:55:01.248833
7811 11:55:01.251374
7812 11:55:01.251833 ==
7813 11:55:01.254856 Dram Type= 6, Freq= 0, CH_0, rank 1
7814 11:55:01.258087 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7815 11:55:01.258552 ==
7816 11:55:01.258918
7817 11:55:01.259257
7818 11:55:01.261155 TX Vref Scan disable
7819 11:55:01.261614 == TX Byte 0 ==
7820 11:55:01.268196 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7821 11:55:01.271203 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7822 11:55:01.271663 == TX Byte 1 ==
7823 11:55:01.278094 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7824 11:55:01.281528 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7825 11:55:01.281990 ==
7826 11:55:01.284650 Dram Type= 6, Freq= 0, CH_0, rank 1
7827 11:55:01.287979 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7828 11:55:01.288577 ==
7829 11:55:01.302421
7830 11:55:01.305953 TX Vref early break, caculate TX vref
7831 11:55:01.309121 TX Vref=16, minBit 9, minWin=21, winSum=363
7832 11:55:01.312398 TX Vref=18, minBit 1, minWin=22, winSum=368
7833 11:55:01.315643 TX Vref=20, minBit 1, minWin=23, winSum=385
7834 11:55:01.319224 TX Vref=22, minBit 1, minWin=23, winSum=388
7835 11:55:01.322741 TX Vref=24, minBit 0, minWin=24, winSum=396
7836 11:55:01.329162 TX Vref=26, minBit 1, minWin=23, winSum=396
7837 11:55:01.332573 TX Vref=28, minBit 0, minWin=25, winSum=408
7838 11:55:01.335973 TX Vref=30, minBit 2, minWin=24, winSum=399
7839 11:55:01.339048 TX Vref=32, minBit 0, minWin=24, winSum=398
7840 11:55:01.342065 TX Vref=34, minBit 0, minWin=23, winSum=389
7841 11:55:01.345742 TX Vref=36, minBit 1, minWin=23, winSum=383
7842 11:55:01.352140 [TxChooseVref] Worse bit 0, Min win 25, Win sum 408, Final Vref 28
7843 11:55:01.352646
7844 11:55:01.355411 Final TX Range 0 Vref 28
7845 11:55:01.355876
7846 11:55:01.356244 ==
7847 11:55:01.359065 Dram Type= 6, Freq= 0, CH_0, rank 1
7848 11:55:01.362106 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7849 11:55:01.362571 ==
7850 11:55:01.362939
7851 11:55:01.363281
7852 11:55:01.365489 TX Vref Scan disable
7853 11:55:01.372035 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7854 11:55:01.372650 == TX Byte 0 ==
7855 11:55:01.375407 u2DelayCellOfst[0]=10 cells (3 PI)
7856 11:55:01.378817 u2DelayCellOfst[1]=14 cells (4 PI)
7857 11:55:01.381982 u2DelayCellOfst[2]=10 cells (3 PI)
7858 11:55:01.385485 u2DelayCellOfst[3]=10 cells (3 PI)
7859 11:55:01.388647 u2DelayCellOfst[4]=7 cells (2 PI)
7860 11:55:01.391782 u2DelayCellOfst[5]=0 cells (0 PI)
7861 11:55:01.395246 u2DelayCellOfst[6]=17 cells (5 PI)
7862 11:55:01.398829 u2DelayCellOfst[7]=14 cells (4 PI)
7863 11:55:01.401968 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7864 11:55:01.405077 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7865 11:55:01.408481 == TX Byte 1 ==
7866 11:55:01.411793 u2DelayCellOfst[8]=0 cells (0 PI)
7867 11:55:01.415035 u2DelayCellOfst[9]=0 cells (0 PI)
7868 11:55:01.415499 u2DelayCellOfst[10]=7 cells (2 PI)
7869 11:55:01.418481 u2DelayCellOfst[11]=3 cells (1 PI)
7870 11:55:01.422096 u2DelayCellOfst[12]=14 cells (4 PI)
7871 11:55:01.425109 u2DelayCellOfst[13]=14 cells (4 PI)
7872 11:55:01.428851 u2DelayCellOfst[14]=17 cells (5 PI)
7873 11:55:01.431723 u2DelayCellOfst[15]=14 cells (4 PI)
7874 11:55:01.438355 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7875 11:55:01.441514 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7876 11:55:01.441969 DramC Write-DBI on
7877 11:55:01.442333 ==
7878 11:55:01.445054 Dram Type= 6, Freq= 0, CH_0, rank 1
7879 11:55:01.451337 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7880 11:55:01.451794 ==
7881 11:55:01.452252
7882 11:55:01.452661
7883 11:55:01.453109 TX Vref Scan disable
7884 11:55:01.455735 == TX Byte 0 ==
7885 11:55:01.458878 Update DQM dly =729 (2 ,6, 25) DQM OEN =(3 ,3)
7886 11:55:01.462417 == TX Byte 1 ==
7887 11:55:01.465417 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
7888 11:55:01.468727 DramC Write-DBI off
7889 11:55:01.469183
7890 11:55:01.469548 [DATLAT]
7891 11:55:01.469885 Freq=1600, CH0 RK1
7892 11:55:01.470217
7893 11:55:01.472320 DATLAT Default: 0xe
7894 11:55:01.472880 0, 0xFFFF, sum = 0
7895 11:55:01.475398 1, 0xFFFF, sum = 0
7896 11:55:01.478805 2, 0xFFFF, sum = 0
7897 11:55:01.479270 3, 0xFFFF, sum = 0
7898 11:55:01.482348 4, 0xFFFF, sum = 0
7899 11:55:01.482945 5, 0xFFFF, sum = 0
7900 11:55:01.485608 6, 0xFFFF, sum = 0
7901 11:55:01.486124 7, 0xFFFF, sum = 0
7902 11:55:01.488841 8, 0xFFFF, sum = 0
7903 11:55:01.489264 9, 0xFFFF, sum = 0
7904 11:55:01.492352 10, 0xFFFF, sum = 0
7905 11:55:01.492917 11, 0xFFFF, sum = 0
7906 11:55:01.495302 12, 0x8FFF, sum = 0
7907 11:55:01.495717 13, 0x0, sum = 1
7908 11:55:01.498809 14, 0x0, sum = 2
7909 11:55:01.499394 15, 0x0, sum = 3
7910 11:55:01.501864 16, 0x0, sum = 4
7911 11:55:01.502285 best_step = 14
7912 11:55:01.502614
7913 11:55:01.502922 ==
7914 11:55:01.505280 Dram Type= 6, Freq= 0, CH_0, rank 1
7915 11:55:01.508478 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7916 11:55:01.512085 ==
7917 11:55:01.512625 RX Vref Scan: 0
7918 11:55:01.512963
7919 11:55:01.515408 RX Vref 0 -> 0, step: 1
7920 11:55:01.515818
7921 11:55:01.516146 RX Delay 11 -> 252, step: 4
7922 11:55:01.523164 iDelay=195, Bit 0, Center 124 (71 ~ 178) 108
7923 11:55:01.525896 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
7924 11:55:01.529134 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
7925 11:55:01.532577 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
7926 11:55:01.536075 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
7927 11:55:01.542518 iDelay=195, Bit 5, Center 118 (63 ~ 174) 112
7928 11:55:01.545726 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
7929 11:55:01.548972 iDelay=195, Bit 7, Center 138 (83 ~ 194) 112
7930 11:55:01.552409 iDelay=195, Bit 8, Center 108 (55 ~ 162) 108
7931 11:55:01.555784 iDelay=195, Bit 9, Center 106 (51 ~ 162) 112
7932 11:55:01.562755 iDelay=195, Bit 10, Center 120 (67 ~ 174) 108
7933 11:55:01.565544 iDelay=195, Bit 11, Center 112 (59 ~ 166) 108
7934 11:55:01.568820 iDelay=195, Bit 12, Center 126 (71 ~ 182) 112
7935 11:55:01.572350 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
7936 11:55:01.579028 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
7937 11:55:01.582232 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
7938 11:55:01.582783 ==
7939 11:55:01.585638 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 11:55:01.589108 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7941 11:55:01.589572 ==
7942 11:55:01.592059 DQS Delay:
7943 11:55:01.592565 DQS0 = 0, DQS1 = 0
7944 11:55:01.592949 DQM Delay:
7945 11:55:01.595306 DQM0 = 128, DQM1 = 120
7946 11:55:01.595763 DQ Delay:
7947 11:55:01.598729 DQ0 =124, DQ1 =132, DQ2 =126, DQ3 =124
7948 11:55:01.602218 DQ4 =130, DQ5 =118, DQ6 =138, DQ7 =138
7949 11:55:01.605418 DQ8 =108, DQ9 =106, DQ10 =120, DQ11 =112
7950 11:55:01.612020 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =130
7951 11:55:01.612585
7952 11:55:01.612962
7953 11:55:01.613303
7954 11:55:01.615434 [DramC_TX_OE_Calibration] TA2
7955 11:55:01.618814 Original DQ_B0 (3 6) =30, OEN = 27
7956 11:55:01.619342 Original DQ_B1 (3 6) =30, OEN = 27
7957 11:55:01.622230 24, 0x0, End_B0=24 End_B1=24
7958 11:55:01.625476 25, 0x0, End_B0=25 End_B1=25
7959 11:55:01.628957 26, 0x0, End_B0=26 End_B1=26
7960 11:55:01.632326 27, 0x0, End_B0=27 End_B1=27
7961 11:55:01.632943 28, 0x0, End_B0=28 End_B1=28
7962 11:55:01.635529 29, 0x0, End_B0=29 End_B1=29
7963 11:55:01.638511 30, 0x0, End_B0=30 End_B1=30
7964 11:55:01.642297 31, 0x4141, End_B0=30 End_B1=30
7965 11:55:01.645237 Byte0 end_step=30 best_step=27
7966 11:55:01.645770 Byte1 end_step=30 best_step=27
7967 11:55:01.648474 Byte0 TX OE(2T, 0.5T) = (3, 3)
7968 11:55:01.651886 Byte1 TX OE(2T, 0.5T) = (3, 3)
7969 11:55:01.652465
7970 11:55:01.652909
7971 11:55:01.661812 [DQSOSCAuto] RK1, (LSB)MR18= 0x2121, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
7972 11:55:01.662350 CH0 RK1: MR19=303, MR18=2121
7973 11:55:01.668839 CH0_RK1: MR19=0x303, MR18=0x2121, DQSOSC=393, MR23=63, INC=23, DEC=15
7974 11:55:01.671681 [RxdqsGatingPostProcess] freq 1600
7975 11:55:01.678329 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
7976 11:55:01.681820 Pre-setting of DQS Precalculation
7977 11:55:01.684957 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7978 11:55:01.685438 ==
7979 11:55:01.688445 Dram Type= 6, Freq= 0, CH_1, rank 0
7980 11:55:01.694932 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
7981 11:55:01.695480 ==
7982 11:55:01.698082 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7983 11:55:01.705137 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
7984 11:55:01.707919 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
7985 11:55:01.714956 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7986 11:55:01.721784 [CA 0] Center 41 (11~72) winsize 62
7987 11:55:01.725223 [CA 1] Center 41 (11~72) winsize 62
7988 11:55:01.728572 [CA 2] Center 37 (8~67) winsize 60
7989 11:55:01.731913 [CA 3] Center 36 (7~66) winsize 60
7990 11:55:01.735021 [CA 4] Center 34 (4~64) winsize 61
7991 11:55:01.738127 [CA 5] Center 34 (5~64) winsize 60
7992 11:55:01.738614
7993 11:55:01.741435 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7994 11:55:01.741910
7995 11:55:01.745118 [CATrainingPosCal] consider 1 rank data
7996 11:55:01.748247 u2DelayCellTimex100 = 275/100 ps
7997 11:55:01.751468 CA0 delay=41 (11~72),Diff = 7 PI (24 cell)
7998 11:55:01.758050 CA1 delay=41 (11~72),Diff = 7 PI (24 cell)
7999 11:55:01.761266 CA2 delay=37 (8~67),Diff = 3 PI (10 cell)
8000 11:55:01.764612 CA3 delay=36 (7~66),Diff = 2 PI (7 cell)
8001 11:55:01.768319 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
8002 11:55:01.771349 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8003 11:55:01.772056
8004 11:55:01.774763 CA PerBit enable=1, Macro0, CA PI delay=34
8005 11:55:01.775441
8006 11:55:01.778336 [CBTSetCACLKResult] CA Dly = 34
8007 11:55:01.781228 CS Dly: 8 (0~39)
8008 11:55:01.784444 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8009 11:55:01.788165 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8010 11:55:01.788750 ==
8011 11:55:01.791253 Dram Type= 6, Freq= 0, CH_1, rank 1
8012 11:55:01.794502 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8013 11:55:01.797758 ==
8014 11:55:01.801233 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8015 11:55:01.804744 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8016 11:55:01.811399 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8017 11:55:01.814387 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8018 11:55:01.824147 [CA 0] Center 41 (11~71) winsize 61
8019 11:55:01.827748 [CA 1] Center 41 (11~71) winsize 61
8020 11:55:01.831129 [CA 2] Center 36 (6~66) winsize 61
8021 11:55:01.834342 [CA 3] Center 36 (7~65) winsize 59
8022 11:55:01.837702 [CA 4] Center 34 (5~64) winsize 60
8023 11:55:01.840726 [CA 5] Center 34 (4~64) winsize 61
8024 11:55:01.841193
8025 11:55:01.843811 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8026 11:55:01.844275
8027 11:55:01.847141 [CATrainingPosCal] consider 2 rank data
8028 11:55:01.850796 u2DelayCellTimex100 = 275/100 ps
8029 11:55:01.853992 CA0 delay=41 (11~71),Diff = 7 PI (24 cell)
8030 11:55:01.860632 CA1 delay=41 (11~71),Diff = 7 PI (24 cell)
8031 11:55:01.863719 CA2 delay=37 (8~66),Diff = 3 PI (10 cell)
8032 11:55:01.867118 CA3 delay=36 (7~65),Diff = 2 PI (7 cell)
8033 11:55:01.870577 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
8034 11:55:01.873643 CA5 delay=34 (5~64),Diff = 0 PI (0 cell)
8035 11:55:01.874099
8036 11:55:01.877142 CA PerBit enable=1, Macro0, CA PI delay=34
8037 11:55:01.877599
8038 11:55:01.880310 [CBTSetCACLKResult] CA Dly = 34
8039 11:55:01.883851 CS Dly: 9 (0~41)
8040 11:55:01.887123 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8041 11:55:01.890347 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8042 11:55:01.890805
8043 11:55:01.893723 ----->DramcWriteLeveling(PI) begin...
8044 11:55:01.894288 ==
8045 11:55:01.896913 Dram Type= 6, Freq= 0, CH_1, rank 0
8046 11:55:01.903553 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8047 11:55:01.904016 ==
8048 11:55:01.907239 Write leveling (Byte 0): 24 => 24
8049 11:55:01.907695 Write leveling (Byte 1): 24 => 24
8050 11:55:01.910189 DramcWriteLeveling(PI) end<-----
8051 11:55:01.910643
8052 11:55:01.911004 ==
8053 11:55:01.913648 Dram Type= 6, Freq= 0, CH_1, rank 0
8054 11:55:01.920207 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8055 11:55:01.920763 ==
8056 11:55:01.923344 [Gating] SW mode calibration
8057 11:55:01.929974 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8058 11:55:01.933564 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8059 11:55:01.940073 0 12 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8060 11:55:01.943539 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:55:01.946981 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8062 11:55:01.953196 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8063 11:55:01.956812 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8064 11:55:01.960129 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8065 11:55:01.966573 0 12 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (1 0)
8066 11:55:01.970138 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8067 11:55:01.973014 0 13 0 | B1->B0 | 3333 2323 | 1 0 | (1 0) (1 0)
8068 11:55:01.980276 0 13 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
8069 11:55:01.983181 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8070 11:55:01.987136 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8071 11:55:01.993274 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8072 11:55:01.996448 0 13 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8073 11:55:01.999767 0 13 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8074 11:55:02.003315 0 13 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
8075 11:55:02.009865 0 14 0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)
8076 11:55:02.013281 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:55:02.016308 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:55:02.023178 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:55:02.026348 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 11:55:02.030228 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 11:55:02.036591 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8082 11:55:02.039418 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8083 11:55:02.042615 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8084 11:55:02.049587 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8085 11:55:02.052614 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:55:02.056074 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:55:02.062845 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:55:02.065987 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:55:02.069163 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:55:02.076173 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:55:02.079295 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:55:02.082984 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:55:02.089239 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 11:55:02.092610 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 11:55:02.096071 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:55:02.102872 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:55:02.106005 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8098 11:55:02.109399 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8099 11:55:02.115986 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8100 11:55:02.116449 Total UI for P1: 0, mck2ui 16
8101 11:55:02.122320 best dqsien dly found for B0: ( 1, 0, 26)
8102 11:55:02.125511 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8103 11:55:02.129081 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 11:55:02.132366 Total UI for P1: 0, mck2ui 16
8105 11:55:02.135582 best dqsien dly found for B1: ( 1, 1, 2)
8106 11:55:02.138776 best DQS0 dly(MCK, UI, PI) = (1, 0, 26)
8107 11:55:02.142386 best DQS1 dly(MCK, UI, PI) = (1, 1, 2)
8108 11:55:02.142945
8109 11:55:02.148798 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 26)
8110 11:55:02.152584 best DQS1 P1 dly(MCK, UI, PI) = (1, 5, 2)
8111 11:55:02.153136 [Gating] SW calibration Done
8112 11:55:02.155570 ==
8113 11:55:02.156136 Dram Type= 6, Freq= 0, CH_1, rank 0
8114 11:55:02.162458 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8115 11:55:02.163034 ==
8116 11:55:02.163405 RX Vref Scan: 0
8117 11:55:02.163746
8118 11:55:02.165690 RX Vref 0 -> 0, step: 1
8119 11:55:02.166144
8120 11:55:02.168595 RX Delay 0 -> 252, step: 8
8121 11:55:02.172004 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8122 11:55:02.175596 iDelay=200, Bit 1, Center 123 (72 ~ 175) 104
8123 11:55:02.178657 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8124 11:55:02.185176 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8125 11:55:02.188970 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8126 11:55:02.192006 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8127 11:55:02.195291 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8128 11:55:02.198395 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8129 11:55:02.205115 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8130 11:55:02.208452 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8131 11:55:02.211676 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8132 11:55:02.215205 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8133 11:55:02.218654 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8134 11:55:02.225276 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8135 11:55:02.228482 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8136 11:55:02.231931 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8137 11:55:02.232487 ==
8138 11:55:02.235326 Dram Type= 6, Freq= 0, CH_1, rank 0
8139 11:55:02.238379 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8140 11:55:02.238896 ==
8141 11:55:02.241600 DQS Delay:
8142 11:55:02.242054 DQS0 = 0, DQS1 = 0
8143 11:55:02.245347 DQM Delay:
8144 11:55:02.245818 DQM0 = 130, DQM1 = 125
8145 11:55:02.248065 DQ Delay:
8146 11:55:02.252124 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =127
8147 11:55:02.255007 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8148 11:55:02.258162 DQ8 =107, DQ9 =115, DQ10 =127, DQ11 =115
8149 11:55:02.261381 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =135
8150 11:55:02.261839
8151 11:55:02.262203
8152 11:55:02.262542 ==
8153 11:55:02.264989 Dram Type= 6, Freq= 0, CH_1, rank 0
8154 11:55:02.268241 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8155 11:55:02.268765 ==
8156 11:55:02.269138
8157 11:55:02.269476
8158 11:55:02.271353 TX Vref Scan disable
8159 11:55:02.274866 == TX Byte 0 ==
8160 11:55:02.278539 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8161 11:55:02.281545 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8162 11:55:02.284739 == TX Byte 1 ==
8163 11:55:02.288026 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8164 11:55:02.291897 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8165 11:55:02.292474 ==
8166 11:55:02.295057 Dram Type= 6, Freq= 0, CH_1, rank 0
8167 11:55:02.301515 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8168 11:55:02.302130 ==
8169 11:55:02.312775
8170 11:55:02.315828 TX Vref early break, caculate TX vref
8171 11:55:02.319112 TX Vref=16, minBit 0, minWin=22, winSum=370
8172 11:55:02.322531 TX Vref=18, minBit 0, minWin=22, winSum=375
8173 11:55:02.325831 TX Vref=20, minBit 0, minWin=23, winSum=386
8174 11:55:02.329212 TX Vref=22, minBit 0, minWin=24, winSum=396
8175 11:55:02.332326 TX Vref=24, minBit 0, minWin=24, winSum=404
8176 11:55:02.338675 TX Vref=26, minBit 0, minWin=25, winSum=412
8177 11:55:02.342102 TX Vref=28, minBit 9, minWin=24, winSum=415
8178 11:55:02.345268 TX Vref=30, minBit 9, minWin=24, winSum=411
8179 11:55:02.348496 TX Vref=32, minBit 0, minWin=24, winSum=402
8180 11:55:02.351645 TX Vref=34, minBit 1, minWin=23, winSum=390
8181 11:55:02.358587 [TxChooseVref] Worse bit 0, Min win 25, Win sum 412, Final Vref 26
8182 11:55:02.359095
8183 11:55:02.361872 Final TX Range 0 Vref 26
8184 11:55:02.362335
8185 11:55:02.362812 ==
8186 11:55:02.364996 Dram Type= 6, Freq= 0, CH_1, rank 0
8187 11:55:02.368416 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8188 11:55:02.368989 ==
8189 11:55:02.369462
8190 11:55:02.369823
8191 11:55:02.371611 TX Vref Scan disable
8192 11:55:02.378395 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8193 11:55:02.378962 == TX Byte 0 ==
8194 11:55:02.381669 u2DelayCellOfst[0]=17 cells (5 PI)
8195 11:55:02.384806 u2DelayCellOfst[1]=10 cells (3 PI)
8196 11:55:02.387895 u2DelayCellOfst[2]=0 cells (0 PI)
8197 11:55:02.391293 u2DelayCellOfst[3]=7 cells (2 PI)
8198 11:55:02.394712 u2DelayCellOfst[4]=7 cells (2 PI)
8199 11:55:02.398076 u2DelayCellOfst[5]=14 cells (4 PI)
8200 11:55:02.401073 u2DelayCellOfst[6]=14 cells (4 PI)
8201 11:55:02.404793 u2DelayCellOfst[7]=7 cells (2 PI)
8202 11:55:02.408281 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8203 11:55:02.411412 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8204 11:55:02.414674 == TX Byte 1 ==
8205 11:55:02.417974 u2DelayCellOfst[8]=0 cells (0 PI)
8206 11:55:02.418534 u2DelayCellOfst[9]=7 cells (2 PI)
8207 11:55:02.421085 u2DelayCellOfst[10]=10 cells (3 PI)
8208 11:55:02.424582 u2DelayCellOfst[11]=3 cells (1 PI)
8209 11:55:02.427845 u2DelayCellOfst[12]=17 cells (5 PI)
8210 11:55:02.431374 u2DelayCellOfst[13]=21 cells (6 PI)
8211 11:55:02.434606 u2DelayCellOfst[14]=21 cells (6 PI)
8212 11:55:02.438007 u2DelayCellOfst[15]=17 cells (5 PI)
8213 11:55:02.441167 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8214 11:55:02.447999 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8215 11:55:02.448500 DramC Write-DBI on
8216 11:55:02.449022 ==
8217 11:55:02.451039 Dram Type= 6, Freq= 0, CH_1, rank 0
8218 11:55:02.457745 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8219 11:55:02.458207 ==
8220 11:55:02.458571
8221 11:55:02.458906
8222 11:55:02.459229 TX Vref Scan disable
8223 11:55:02.461310 == TX Byte 0 ==
8224 11:55:02.464628 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8225 11:55:02.468001 == TX Byte 1 ==
8226 11:55:02.471154 Update DQM dly =718 (2 ,6, 14) DQM OEN =(3 ,3)
8227 11:55:02.474429 DramC Write-DBI off
8228 11:55:02.474882
8229 11:55:02.475242 [DATLAT]
8230 11:55:02.475579 Freq=1600, CH1 RK0
8231 11:55:02.475908
8232 11:55:02.477865 DATLAT Default: 0xf
8233 11:55:02.478278 0, 0xFFFF, sum = 0
8234 11:55:02.481025 1, 0xFFFF, sum = 0
8235 11:55:02.484739 2, 0xFFFF, sum = 0
8236 11:55:02.485178 3, 0xFFFF, sum = 0
8237 11:55:02.487768 4, 0xFFFF, sum = 0
8238 11:55:02.488189 5, 0xFFFF, sum = 0
8239 11:55:02.491044 6, 0xFFFF, sum = 0
8240 11:55:02.491462 7, 0xFFFF, sum = 0
8241 11:55:02.495014 8, 0xFFFF, sum = 0
8242 11:55:02.495526 9, 0xFFFF, sum = 0
8243 11:55:02.497722 10, 0xFFFF, sum = 0
8244 11:55:02.498143 11, 0xFFFF, sum = 0
8245 11:55:02.501141 12, 0x8F7F, sum = 0
8246 11:55:02.501558 13, 0x0, sum = 1
8247 11:55:02.504333 14, 0x0, sum = 2
8248 11:55:02.504793 15, 0x0, sum = 3
8249 11:55:02.507521 16, 0x0, sum = 4
8250 11:55:02.507955 best_step = 14
8251 11:55:02.508280
8252 11:55:02.508623 ==
8253 11:55:02.511005 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 11:55:02.517744 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8255 11:55:02.518261 ==
8256 11:55:02.518597 RX Vref Scan: 1
8257 11:55:02.518903
8258 11:55:02.520897 Set Vref Range= 24 -> 127
8259 11:55:02.521414
8260 11:55:02.524273 RX Vref 24 -> 127, step: 1
8261 11:55:02.524834
8262 11:55:02.525173 RX Delay 3 -> 252, step: 4
8263 11:55:02.525483
8264 11:55:02.527660 Set Vref, RX VrefLevel [Byte0]: 24
8265 11:55:02.530599 [Byte1]: 24
8266 11:55:02.534976
8267 11:55:02.535482 Set Vref, RX VrefLevel [Byte0]: 25
8268 11:55:02.538229 [Byte1]: 25
8269 11:55:02.542169
8270 11:55:02.542586 Set Vref, RX VrefLevel [Byte0]: 26
8271 11:55:02.545758 [Byte1]: 26
8272 11:55:02.549923
8273 11:55:02.553322 Set Vref, RX VrefLevel [Byte0]: 27
8274 11:55:02.553843 [Byte1]: 27
8275 11:55:02.557607
8276 11:55:02.558020 Set Vref, RX VrefLevel [Byte0]: 28
8277 11:55:02.561215 [Byte1]: 28
8278 11:55:02.565154
8279 11:55:02.565565 Set Vref, RX VrefLevel [Byte0]: 29
8280 11:55:02.568476 [Byte1]: 29
8281 11:55:02.572884
8282 11:55:02.573297 Set Vref, RX VrefLevel [Byte0]: 30
8283 11:55:02.576126 [Byte1]: 30
8284 11:55:02.581047
8285 11:55:02.581558 Set Vref, RX VrefLevel [Byte0]: 31
8286 11:55:02.584368 [Byte1]: 31
8287 11:55:02.588298
8288 11:55:02.588864 Set Vref, RX VrefLevel [Byte0]: 32
8289 11:55:02.591588 [Byte1]: 32
8290 11:55:02.596179
8291 11:55:02.596773 Set Vref, RX VrefLevel [Byte0]: 33
8292 11:55:02.599180 [Byte1]: 33
8293 11:55:02.603613
8294 11:55:02.604040 Set Vref, RX VrefLevel [Byte0]: 34
8295 11:55:02.606725 [Byte1]: 34
8296 11:55:02.611048
8297 11:55:02.611453 Set Vref, RX VrefLevel [Byte0]: 35
8298 11:55:02.614339 [Byte1]: 35
8299 11:55:02.619321
8300 11:55:02.619730 Set Vref, RX VrefLevel [Byte0]: 36
8301 11:55:02.622531 [Byte1]: 36
8302 11:55:02.627009
8303 11:55:02.627514 Set Vref, RX VrefLevel [Byte0]: 37
8304 11:55:02.630078 [Byte1]: 37
8305 11:55:02.634235
8306 11:55:02.634739 Set Vref, RX VrefLevel [Byte0]: 38
8307 11:55:02.637479 [Byte1]: 38
8308 11:55:02.641674
8309 11:55:02.642124 Set Vref, RX VrefLevel [Byte0]: 39
8310 11:55:02.645113 [Byte1]: 39
8311 11:55:02.649620
8312 11:55:02.650112 Set Vref, RX VrefLevel [Byte0]: 40
8313 11:55:02.652629 [Byte1]: 40
8314 11:55:02.657214
8315 11:55:02.657815 Set Vref, RX VrefLevel [Byte0]: 41
8316 11:55:02.660460 [Byte1]: 41
8317 11:55:02.664865
8318 11:55:02.665317 Set Vref, RX VrefLevel [Byte0]: 42
8319 11:55:02.668078 [Byte1]: 42
8320 11:55:02.672970
8321 11:55:02.673517 Set Vref, RX VrefLevel [Byte0]: 43
8322 11:55:02.675840 [Byte1]: 43
8323 11:55:02.680454
8324 11:55:02.681052 Set Vref, RX VrefLevel [Byte0]: 44
8325 11:55:02.683346 [Byte1]: 44
8326 11:55:02.688018
8327 11:55:02.688619 Set Vref, RX VrefLevel [Byte0]: 45
8328 11:55:02.691176 [Byte1]: 45
8329 11:55:02.695417
8330 11:55:02.695971 Set Vref, RX VrefLevel [Byte0]: 46
8331 11:55:02.698665 [Byte1]: 46
8332 11:55:02.702909
8333 11:55:02.703363 Set Vref, RX VrefLevel [Byte0]: 47
8334 11:55:02.706378 [Byte1]: 47
8335 11:55:02.710791
8336 11:55:02.711399 Set Vref, RX VrefLevel [Byte0]: 48
8337 11:55:02.713991 [Byte1]: 48
8338 11:55:02.718691
8339 11:55:02.719233 Set Vref, RX VrefLevel [Byte0]: 49
8340 11:55:02.721768 [Byte1]: 49
8341 11:55:02.726255
8342 11:55:02.726801 Set Vref, RX VrefLevel [Byte0]: 50
8343 11:55:02.729407 [Byte1]: 50
8344 11:55:02.733844
8345 11:55:02.734392 Set Vref, RX VrefLevel [Byte0]: 51
8346 11:55:02.736966 [Byte1]: 51
8347 11:55:02.741587
8348 11:55:02.742137 Set Vref, RX VrefLevel [Byte0]: 52
8349 11:55:02.744627 [Byte1]: 52
8350 11:55:02.748987
8351 11:55:02.749530 Set Vref, RX VrefLevel [Byte0]: 53
8352 11:55:02.752779 [Byte1]: 53
8353 11:55:02.756636
8354 11:55:02.757183 Set Vref, RX VrefLevel [Byte0]: 54
8355 11:55:02.760078 [Byte1]: 54
8356 11:55:02.764484
8357 11:55:02.765113 Set Vref, RX VrefLevel [Byte0]: 55
8358 11:55:02.767645 [Byte1]: 55
8359 11:55:02.772083
8360 11:55:02.772684 Set Vref, RX VrefLevel [Byte0]: 56
8361 11:55:02.775291 [Byte1]: 56
8362 11:55:02.780145
8363 11:55:02.780756 Set Vref, RX VrefLevel [Byte0]: 57
8364 11:55:02.783124 [Byte1]: 57
8365 11:55:02.787469
8366 11:55:02.788022 Set Vref, RX VrefLevel [Byte0]: 58
8367 11:55:02.790613 [Byte1]: 58
8368 11:55:02.794603
8369 11:55:02.795054 Set Vref, RX VrefLevel [Byte0]: 59
8370 11:55:02.798224 [Byte1]: 59
8371 11:55:02.802494
8372 11:55:02.802946 Set Vref, RX VrefLevel [Byte0]: 60
8373 11:55:02.805837 [Byte1]: 60
8374 11:55:02.810338
8375 11:55:02.810937 Set Vref, RX VrefLevel [Byte0]: 61
8376 11:55:02.813428 [Byte1]: 61
8377 11:55:02.818115
8378 11:55:02.818681 Set Vref, RX VrefLevel [Byte0]: 62
8379 11:55:02.821203 [Byte1]: 62
8380 11:55:02.825431
8381 11:55:02.825988 Set Vref, RX VrefLevel [Byte0]: 63
8382 11:55:02.829220 [Byte1]: 63
8383 11:55:02.833442
8384 11:55:02.833992 Set Vref, RX VrefLevel [Byte0]: 64
8385 11:55:02.836626 [Byte1]: 64
8386 11:55:02.840618
8387 11:55:02.841085 Set Vref, RX VrefLevel [Byte0]: 65
8388 11:55:02.844406 [Byte1]: 65
8389 11:55:02.848541
8390 11:55:02.849008 Set Vref, RX VrefLevel [Byte0]: 66
8391 11:55:02.851915 [Byte1]: 66
8392 11:55:02.856020
8393 11:55:02.856471 Set Vref, RX VrefLevel [Byte0]: 67
8394 11:55:02.859615 [Byte1]: 67
8395 11:55:02.863882
8396 11:55:02.864668 Set Vref, RX VrefLevel [Byte0]: 68
8397 11:55:02.867237 [Byte1]: 68
8398 11:55:02.871517
8399 11:55:02.872071 Set Vref, RX VrefLevel [Byte0]: 69
8400 11:55:02.874780 [Byte1]: 69
8401 11:55:02.879223
8402 11:55:02.879677 Final RX Vref Byte 0 = 59 to rank0
8403 11:55:02.882162 Final RX Vref Byte 1 = 53 to rank0
8404 11:55:02.885845 Final RX Vref Byte 0 = 59 to rank1
8405 11:55:02.888769 Final RX Vref Byte 1 = 53 to rank1==
8406 11:55:02.892668 Dram Type= 6, Freq= 0, CH_1, rank 0
8407 11:55:02.899032 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8408 11:55:02.899599 ==
8409 11:55:02.899964 DQS Delay:
8410 11:55:02.900302 DQS0 = 0, DQS1 = 0
8411 11:55:02.902437 DQM Delay:
8412 11:55:02.902987 DQM0 = 128, DQM1 = 123
8413 11:55:02.905294 DQ Delay:
8414 11:55:02.908971 DQ0 =132, DQ1 =122, DQ2 =116, DQ3 =126
8415 11:55:02.912095 DQ4 =130, DQ5 =142, DQ6 =136, DQ7 =126
8416 11:55:02.915557 DQ8 =104, DQ9 =114, DQ10 =126, DQ11 =114
8417 11:55:02.918776 DQ12 =130, DQ13 =134, DQ14 =132, DQ15 =134
8418 11:55:02.919232
8419 11:55:02.919591
8420 11:55:02.919922
8421 11:55:02.922539 [DramC_TX_OE_Calibration] TA2
8422 11:55:02.925433 Original DQ_B0 (3 6) =30, OEN = 27
8423 11:55:02.929037 Original DQ_B1 (3 6) =30, OEN = 27
8424 11:55:02.932311 24, 0x0, End_B0=24 End_B1=24
8425 11:55:02.932927 25, 0x0, End_B0=25 End_B1=25
8426 11:55:02.935639 26, 0x0, End_B0=26 End_B1=26
8427 11:55:02.938935 27, 0x0, End_B0=27 End_B1=27
8428 11:55:02.942147 28, 0x0, End_B0=28 End_B1=28
8429 11:55:02.945716 29, 0x0, End_B0=29 End_B1=29
8430 11:55:02.946245 30, 0x0, End_B0=30 End_B1=30
8431 11:55:02.948932 31, 0x4141, End_B0=30 End_B1=30
8432 11:55:02.952643 Byte0 end_step=30 best_step=27
8433 11:55:02.955398 Byte1 end_step=30 best_step=27
8434 11:55:02.958929 Byte0 TX OE(2T, 0.5T) = (3, 3)
8435 11:55:02.962144 Byte1 TX OE(2T, 0.5T) = (3, 3)
8436 11:55:02.962601
8437 11:55:02.962960
8438 11:55:02.968792 [DQSOSCAuto] RK0, (LSB)MR18= 0x2626, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 390 ps
8439 11:55:02.972421 CH1 RK0: MR19=303, MR18=2626
8440 11:55:02.978710 CH1_RK0: MR19=0x303, MR18=0x2626, DQSOSC=390, MR23=63, INC=24, DEC=16
8441 11:55:02.979290
8442 11:55:02.982191 ----->DramcWriteLeveling(PI) begin...
8443 11:55:02.982777 ==
8444 11:55:02.985646 Dram Type= 6, Freq= 0, CH_1, rank 1
8445 11:55:02.988744 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8446 11:55:02.989305 ==
8447 11:55:02.992227 Write leveling (Byte 0): 21 => 21
8448 11:55:02.995460 Write leveling (Byte 1): 20 => 20
8449 11:55:02.998609 DramcWriteLeveling(PI) end<-----
8450 11:55:02.999069
8451 11:55:02.999428 ==
8452 11:55:03.002081 Dram Type= 6, Freq= 0, CH_1, rank 1
8453 11:55:03.005001 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8454 11:55:03.005464 ==
8455 11:55:03.008400 [Gating] SW mode calibration
8456 11:55:03.015350 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 28 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8457 11:55:03.021738 RX_Path_delay_UI(52) -3 - DQSINCTL_UI(40) = u1StartUI(12)
8458 11:55:03.025288 0 12 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 11:55:03.028572 0 12 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 11:55:03.035238 0 12 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8461 11:55:03.038390 0 12 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 11:55:03.041369 0 12 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 11:55:03.048318 0 12 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8464 11:55:03.051819 0 12 24 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
8465 11:55:03.054714 0 12 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8466 11:55:03.061784 0 13 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8467 11:55:03.064644 0 13 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 11:55:03.068007 0 13 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 11:55:03.074722 0 13 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 11:55:03.077735 0 13 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 11:55:03.080971 0 13 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8472 11:55:03.087963 0 13 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
8473 11:55:03.091277 0 13 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8474 11:55:03.094613 0 14 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8475 11:55:03.101380 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 11:55:03.104820 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 11:55:03.107995 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 11:55:03.114426 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8479 11:55:03.117669 0 14 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 11:55:03.121059 0 14 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8481 11:55:03.127903 0 14 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8482 11:55:03.131159 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8483 11:55:03.134136 0 15 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 11:55:03.141089 0 15 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 11:55:03.144411 0 15 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 11:55:03.147414 0 15 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 11:55:03.154459 0 15 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:55:03.157115 0 15 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 11:55:03.160408 0 15 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 11:55:03.167375 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 11:55:03.170652 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 11:55:03.174268 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 11:55:03.180531 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 11:55:03.183927 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8495 11:55:03.187205 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8496 11:55:03.193799 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8497 11:55:03.197260 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8498 11:55:03.200487 Total UI for P1: 0, mck2ui 16
8499 11:55:03.203587 best dqsien dly found for B0: ( 1, 0, 24)
8500 11:55:03.206736 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8501 11:55:03.210741 Total UI for P1: 0, mck2ui 16
8502 11:55:03.213489 best dqsien dly found for B1: ( 1, 0, 28)
8503 11:55:03.216628 best DQS0 dly(MCK, UI, PI) = (1, 0, 24)
8504 11:55:03.220222 best DQS1 dly(MCK, UI, PI) = (1, 0, 28)
8505 11:55:03.220849
8506 11:55:03.227276 best DQS0 P1 dly(MCK, UI, PI) = (1, 4, 24)
8507 11:55:03.230384 best DQS1 P1 dly(MCK, UI, PI) = (1, 4, 28)
8508 11:55:03.230949 [Gating] SW calibration Done
8509 11:55:03.233240 ==
8510 11:55:03.237039 Dram Type= 6, Freq= 0, CH_1, rank 1
8511 11:55:03.240112 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8512 11:55:03.240707 ==
8513 11:55:03.241083 RX Vref Scan: 0
8514 11:55:03.241432
8515 11:55:03.242909 RX Vref 0 -> 0, step: 1
8516 11:55:03.243402
8517 11:55:03.246399 RX Delay 0 -> 252, step: 8
8518 11:55:03.249900 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8519 11:55:03.253439 iDelay=200, Bit 1, Center 123 (64 ~ 183) 120
8520 11:55:03.256483 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8521 11:55:03.263545 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8522 11:55:03.266518 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8523 11:55:03.269658 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8524 11:55:03.273183 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8525 11:55:03.276099 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8526 11:55:03.282727 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
8527 11:55:03.286432 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8528 11:55:03.289741 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8529 11:55:03.293054 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8530 11:55:03.299345 iDelay=200, Bit 12, Center 135 (72 ~ 199) 128
8531 11:55:03.302711 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8532 11:55:03.305833 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8533 11:55:03.309095 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8534 11:55:03.309566 ==
8535 11:55:03.312294 Dram Type= 6, Freq= 0, CH_1, rank 1
8536 11:55:03.319688 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8537 11:55:03.320278 ==
8538 11:55:03.320714 DQS Delay:
8539 11:55:03.322675 DQS0 = 0, DQS1 = 0
8540 11:55:03.323262 DQM Delay:
8541 11:55:03.323634 DQM0 = 131, DQM1 = 125
8542 11:55:03.325779 DQ Delay:
8543 11:55:03.329354 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8544 11:55:03.332593 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =127
8545 11:55:03.335846 DQ8 =107, DQ9 =115, DQ10 =123, DQ11 =115
8546 11:55:03.339283 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =131
8547 11:55:03.339845
8548 11:55:03.340215
8549 11:55:03.340618 ==
8550 11:55:03.342563 Dram Type= 6, Freq= 0, CH_1, rank 1
8551 11:55:03.345703 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8552 11:55:03.349121 ==
8553 11:55:03.349701
8554 11:55:03.350074
8555 11:55:03.350414 TX Vref Scan disable
8556 11:55:03.352329 == TX Byte 0 ==
8557 11:55:03.356046 Update DQ dly =975 (3 ,6, 15) DQ OEN =(3 ,3)
8558 11:55:03.359169 Update DQM dly =975 (3 ,6, 15) DQM OEN =(3 ,3)
8559 11:55:03.362314 == TX Byte 1 ==
8560 11:55:03.365528 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8561 11:55:03.369188 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8562 11:55:03.372258 ==
8563 11:55:03.372823 Dram Type= 6, Freq= 0, CH_1, rank 1
8564 11:55:03.378873 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8565 11:55:03.379436 ==
8566 11:55:03.391516
8567 11:55:03.394997 TX Vref early break, caculate TX vref
8568 11:55:03.398375 TX Vref=16, minBit 0, minWin=22, winSum=383
8569 11:55:03.401273 TX Vref=18, minBit 1, minWin=23, winSum=388
8570 11:55:03.404562 TX Vref=20, minBit 1, minWin=23, winSum=394
8571 11:55:03.408439 TX Vref=22, minBit 0, minWin=24, winSum=406
8572 11:55:03.411513 TX Vref=24, minBit 2, minWin=24, winSum=411
8573 11:55:03.418258 TX Vref=26, minBit 1, minWin=25, winSum=420
8574 11:55:03.421311 TX Vref=28, minBit 0, minWin=25, winSum=421
8575 11:55:03.424855 TX Vref=30, minBit 0, minWin=25, winSum=422
8576 11:55:03.428395 TX Vref=32, minBit 0, minWin=24, winSum=410
8577 11:55:03.431483 TX Vref=34, minBit 0, minWin=23, winSum=400
8578 11:55:03.434689 TX Vref=36, minBit 0, minWin=23, winSum=393
8579 11:55:03.441456 [TxChooseVref] Worse bit 0, Min win 25, Win sum 422, Final Vref 30
8580 11:55:03.442015
8581 11:55:03.444997 Final TX Range 0 Vref 30
8582 11:55:03.445553
8583 11:55:03.445922 ==
8584 11:55:03.448155 Dram Type= 6, Freq= 0, CH_1, rank 1
8585 11:55:03.451188 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8586 11:55:03.451758 ==
8587 11:55:03.452125
8588 11:55:03.452468
8589 11:55:03.454605 TX Vref Scan disable
8590 11:55:03.461252 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8591 11:55:03.461804 == TX Byte 0 ==
8592 11:55:03.464555 u2DelayCellOfst[0]=14 cells (4 PI)
8593 11:55:03.468105 u2DelayCellOfst[1]=10 cells (3 PI)
8594 11:55:03.471035 u2DelayCellOfst[2]=0 cells (0 PI)
8595 11:55:03.474496 u2DelayCellOfst[3]=7 cells (2 PI)
8596 11:55:03.478097 u2DelayCellOfst[4]=7 cells (2 PI)
8597 11:55:03.481007 u2DelayCellOfst[5]=10 cells (3 PI)
8598 11:55:03.484413 u2DelayCellOfst[6]=10 cells (3 PI)
8599 11:55:03.487454 u2DelayCellOfst[7]=3 cells (1 PI)
8600 11:55:03.491093 Update DQ dly =974 (3 ,6, 14) DQ OEN =(3 ,3)
8601 11:55:03.494420 Update DQM dly =976 (3 ,6, 16) DQM OEN =(3 ,3)
8602 11:55:03.497666 == TX Byte 1 ==
8603 11:55:03.501141 u2DelayCellOfst[8]=0 cells (0 PI)
8604 11:55:03.501704 u2DelayCellOfst[9]=3 cells (1 PI)
8605 11:55:03.504318 u2DelayCellOfst[10]=10 cells (3 PI)
8606 11:55:03.507870 u2DelayCellOfst[11]=3 cells (1 PI)
8607 11:55:03.511108 u2DelayCellOfst[12]=14 cells (4 PI)
8608 11:55:03.513880 u2DelayCellOfst[13]=17 cells (5 PI)
8609 11:55:03.517232 u2DelayCellOfst[14]=17 cells (5 PI)
8610 11:55:03.520905 u2DelayCellOfst[15]=14 cells (4 PI)
8611 11:55:03.524150 Update DQ dly =972 (3 ,6, 12) DQ OEN =(3 ,3)
8612 11:55:03.530697 Update DQM dly =974 (3 ,6, 14) DQM OEN =(3 ,3)
8613 11:55:03.531297 DramC Write-DBI on
8614 11:55:03.531671 ==
8615 11:55:03.534486 Dram Type= 6, Freq= 0, CH_1, rank 1
8616 11:55:03.540943 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8617 11:55:03.541409 ==
8618 11:55:03.541778
8619 11:55:03.542115
8620 11:55:03.542439 TX Vref Scan disable
8621 11:55:03.544479 == TX Byte 0 ==
8622 11:55:03.548081 Update DQM dly =717 (2 ,6, 13) DQM OEN =(3 ,3)
8623 11:55:03.550993 == TX Byte 1 ==
8624 11:55:03.554450 Update DQM dly =715 (2 ,6, 11) DQM OEN =(3 ,3)
8625 11:55:03.557712 DramC Write-DBI off
8626 11:55:03.558173
8627 11:55:03.558537 [DATLAT]
8628 11:55:03.558882 Freq=1600, CH1 RK1
8629 11:55:03.559212
8630 11:55:03.561118 DATLAT Default: 0xe
8631 11:55:03.561577 0, 0xFFFF, sum = 0
8632 11:55:03.564539 1, 0xFFFF, sum = 0
8633 11:55:03.567558 2, 0xFFFF, sum = 0
8634 11:55:03.568026 3, 0xFFFF, sum = 0
8635 11:55:03.571245 4, 0xFFFF, sum = 0
8636 11:55:03.572042 5, 0xFFFF, sum = 0
8637 11:55:03.574723 6, 0xFFFF, sum = 0
8638 11:55:03.575285 7, 0xFFFF, sum = 0
8639 11:55:03.577675 8, 0xFFFF, sum = 0
8640 11:55:03.578151 9, 0xFFFF, sum = 0
8641 11:55:03.581187 10, 0xFFFF, sum = 0
8642 11:55:03.581751 11, 0xFFFF, sum = 0
8643 11:55:03.584275 12, 0x8FFF, sum = 0
8644 11:55:03.584785 13, 0x0, sum = 1
8645 11:55:03.587585 14, 0x0, sum = 2
8646 11:55:03.588052 15, 0x0, sum = 3
8647 11:55:03.591281 16, 0x0, sum = 4
8648 11:55:03.591846 best_step = 14
8649 11:55:03.592214
8650 11:55:03.592622 ==
8651 11:55:03.594871 Dram Type= 6, Freq= 0, CH_1, rank 1
8652 11:55:03.598084 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8653 11:55:03.600707 ==
8654 11:55:03.601174 RX Vref Scan: 0
8655 11:55:03.601538
8656 11:55:03.604653 RX Vref 0 -> 0, step: 1
8657 11:55:03.605207
8658 11:55:03.605582 RX Delay 3 -> 252, step: 4
8659 11:55:03.611899 iDelay=195, Bit 0, Center 128 (75 ~ 182) 108
8660 11:55:03.615275 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8661 11:55:03.618172 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8662 11:55:03.621602 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
8663 11:55:03.624876 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
8664 11:55:03.631279 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
8665 11:55:03.635216 iDelay=195, Bit 6, Center 136 (83 ~ 190) 108
8666 11:55:03.638720 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8667 11:55:03.641530 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
8668 11:55:03.644780 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8669 11:55:03.651369 iDelay=195, Bit 10, Center 124 (67 ~ 182) 116
8670 11:55:03.654694 iDelay=195, Bit 11, Center 114 (59 ~ 170) 112
8671 11:55:03.658209 iDelay=195, Bit 12, Center 132 (75 ~ 190) 116
8672 11:55:03.661362 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8673 11:55:03.667875 iDelay=195, Bit 14, Center 132 (75 ~ 190) 116
8674 11:55:03.671349 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8675 11:55:03.671911 ==
8676 11:55:03.674689 Dram Type= 6, Freq= 0, CH_1, rank 1
8677 11:55:03.677870 fsp= 1, odt_onoff= 1, Byte mode= 0, DivMode= 1
8678 11:55:03.678436 ==
8679 11:55:03.681153 DQS Delay:
8680 11:55:03.681616 DQS0 = 0, DQS1 = 0
8681 11:55:03.681980 DQM Delay:
8682 11:55:03.684562 DQM0 = 127, DQM1 = 122
8683 11:55:03.685125 DQ Delay:
8684 11:55:03.687770 DQ0 =128, DQ1 =124, DQ2 =116, DQ3 =124
8685 11:55:03.691312 DQ4 =126, DQ5 =138, DQ6 =136, DQ7 =126
8686 11:55:03.694805 DQ8 =106, DQ9 =110, DQ10 =124, DQ11 =114
8687 11:55:03.701495 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8688 11:55:03.702040
8689 11:55:03.702404
8690 11:55:03.702742
8691 11:55:03.704342 [DramC_TX_OE_Calibration] TA2
8692 11:55:03.704934 Original DQ_B0 (3 6) =30, OEN = 27
8693 11:55:03.707830 Original DQ_B1 (3 6) =30, OEN = 27
8694 11:55:03.711145 24, 0x0, End_B0=24 End_B1=24
8695 11:55:03.714443 25, 0x0, End_B0=25 End_B1=25
8696 11:55:03.717694 26, 0x0, End_B0=26 End_B1=26
8697 11:55:03.721179 27, 0x0, End_B0=27 End_B1=27
8698 11:55:03.721742 28, 0x0, End_B0=28 End_B1=28
8699 11:55:03.724461 29, 0x0, End_B0=29 End_B1=29
8700 11:55:03.727692 30, 0x0, End_B0=30 End_B1=30
8701 11:55:03.730947 31, 0x4545, End_B0=30 End_B1=30
8702 11:55:03.734446 Byte0 end_step=30 best_step=27
8703 11:55:03.735001 Byte1 end_step=30 best_step=27
8704 11:55:03.737701 Byte0 TX OE(2T, 0.5T) = (3, 3)
8705 11:55:03.741092 Byte1 TX OE(2T, 0.5T) = (3, 3)
8706 11:55:03.741651
8707 11:55:03.742013
8708 11:55:03.750776 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d1d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 395 ps
8709 11:55:03.751332 CH1 RK1: MR19=303, MR18=1D1D
8710 11:55:03.757220 CH1_RK1: MR19=0x303, MR18=0x1D1D, DQSOSC=395, MR23=63, INC=23, DEC=15
8711 11:55:03.760718 [RxdqsGatingPostProcess] freq 1600
8712 11:55:03.767327 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 2
8713 11:55:03.770661 Pre-setting of DQS Precalculation
8714 11:55:03.773691 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
8715 11:55:03.783849 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8716 11:55:03.790679 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8717 11:55:03.791141
8718 11:55:03.791505
8719 11:55:03.793850 [Calibration Summary] 3200 Mbps
8720 11:55:03.794404 CH 0, Rank 0
8721 11:55:03.797563 SW Impedance : PASS
8722 11:55:03.798114 DUTY Scan : NO K
8723 11:55:03.800411 ZQ Calibration : PASS
8724 11:55:03.803849 Jitter Meter : NO K
8725 11:55:03.804403 CBT Training : PASS
8726 11:55:03.807107 Write leveling : PASS
8727 11:55:03.810635 RX DQS gating : PASS
8728 11:55:03.811191 RX DQ/DQS(RDDQC) : PASS
8729 11:55:03.813508 TX DQ/DQS : PASS
8730 11:55:03.817343 RX DATLAT : PASS
8731 11:55:03.817900 RX DQ/DQS(Engine): PASS
8732 11:55:03.820384 TX OE : PASS
8733 11:55:03.820903 All Pass.
8734 11:55:03.821270
8735 11:55:03.823708 CH 0, Rank 1
8736 11:55:03.824261 SW Impedance : PASS
8737 11:55:03.826984 DUTY Scan : NO K
8738 11:55:03.827541 ZQ Calibration : PASS
8739 11:55:03.830934 Jitter Meter : NO K
8740 11:55:03.833550 CBT Training : PASS
8741 11:55:03.834107 Write leveling : PASS
8742 11:55:03.837149 RX DQS gating : PASS
8743 11:55:03.840384 RX DQ/DQS(RDDQC) : PASS
8744 11:55:03.840990 TX DQ/DQS : PASS
8745 11:55:03.843496 RX DATLAT : PASS
8746 11:55:03.846830 RX DQ/DQS(Engine): PASS
8747 11:55:03.847296 TX OE : PASS
8748 11:55:03.850401 All Pass.
8749 11:55:03.850873
8750 11:55:03.851239 CH 1, Rank 0
8751 11:55:03.853468 SW Impedance : PASS
8752 11:55:03.853928 DUTY Scan : NO K
8753 11:55:03.856917 ZQ Calibration : PASS
8754 11:55:03.860347 Jitter Meter : NO K
8755 11:55:03.860969 CBT Training : PASS
8756 11:55:03.863745 Write leveling : PASS
8757 11:55:03.867125 RX DQS gating : PASS
8758 11:55:03.867706 RX DQ/DQS(RDDQC) : PASS
8759 11:55:03.870396 TX DQ/DQS : PASS
8760 11:55:03.871117 RX DATLAT : PASS
8761 11:55:03.873190 RX DQ/DQS(Engine): PASS
8762 11:55:03.876466 TX OE : PASS
8763 11:55:03.877028 All Pass.
8764 11:55:03.877400
8765 11:55:03.880183 CH 1, Rank 1
8766 11:55:03.880713 SW Impedance : PASS
8767 11:55:03.883262 DUTY Scan : NO K
8768 11:55:03.883724 ZQ Calibration : PASS
8769 11:55:03.886589 Jitter Meter : NO K
8770 11:55:03.890324 CBT Training : PASS
8771 11:55:03.890876 Write leveling : PASS
8772 11:55:03.893183 RX DQS gating : PASS
8773 11:55:03.896558 RX DQ/DQS(RDDQC) : PASS
8774 11:55:03.897123 TX DQ/DQS : PASS
8775 11:55:03.899591 RX DATLAT : PASS
8776 11:55:03.903266 RX DQ/DQS(Engine): PASS
8777 11:55:03.903819 TX OE : PASS
8778 11:55:03.906668 All Pass.
8779 11:55:03.907220
8780 11:55:03.907591 DramC Write-DBI on
8781 11:55:03.910143 PER_BANK_REFRESH: Hybrid Mode
8782 11:55:03.910714 TX_TRACKING: ON
8783 11:55:03.920007 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
8784 11:55:03.930107 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
8785 11:55:03.936496 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8786 11:55:03.939854 [FAST_K] Save calibration result to emmc
8787 11:55:03.943040 sync common calibartion params.
8788 11:55:03.943665 sync cbt_mode0:0, 1:0
8789 11:55:03.946260 dram_init: ddr_geometry: 0
8790 11:55:03.949321 dram_init: ddr_geometry: 0
8791 11:55:03.949802 dram_init: ddr_geometry: 0
8792 11:55:03.952755 0:dram_rank_size:80000000
8793 11:55:03.956309 1:dram_rank_size:80000000
8794 11:55:03.959756 sync rank num:2, rank0_size:0x80000000, rank1_size:0x80000000
8795 11:55:03.962763 DFS_SHUFFLE_HW_MODE: ON
8796 11:55:03.966206 dramc_set_vcore_voltage set vcore to 725000
8797 11:55:03.969489 Read voltage for 1600, 0
8798 11:55:03.970073 Vio18 = 0
8799 11:55:03.972642 Vcore = 725000
8800 11:55:03.973137 Vdram = 0
8801 11:55:03.973500 Vddq = 0
8802 11:55:03.976028 Vmddr = 0
8803 11:55:03.976485 switch to 3200 Mbps bootup
8804 11:55:03.979748 [DramcRunTimeConfig]
8805 11:55:03.980300 PHYPLL
8806 11:55:03.982750 DPM_CONTROL_AFTERK: ON
8807 11:55:03.983297 PER_BANK_REFRESH: ON
8808 11:55:03.985842 REFRESH_OVERHEAD_REDUCTION: ON
8809 11:55:03.989286 CMD_PICG_NEW_MODE: OFF
8810 11:55:03.989746 XRTWTW_NEW_MODE: ON
8811 11:55:03.992619 XRTRTR_NEW_MODE: ON
8812 11:55:03.993079 TX_TRACKING: ON
8813 11:55:03.996094 RDSEL_TRACKING: OFF
8814 11:55:03.999203 DQS Precalculation for DVFS: ON
8815 11:55:03.999667 RX_TRACKING: OFF
8816 11:55:04.003094 HW_GATING DBG: ON
8817 11:55:04.003650 ZQCS_ENABLE_LP4: ON
8818 11:55:04.006327 RX_PICG_NEW_MODE: ON
8819 11:55:04.006884 TX_PICG_NEW_MODE: ON
8820 11:55:04.009556 ENABLE_RX_DCM_DPHY: ON
8821 11:55:04.012642 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
8822 11:55:04.016225 DUMMY_READ_FOR_TRACKING: OFF
8823 11:55:04.016828 !!! SPM_CONTROL_AFTERK: OFF
8824 11:55:04.019531 !!! SPM could not control APHY
8825 11:55:04.022673 IMPEDANCE_TRACKING: ON
8826 11:55:04.023229 TEMP_SENSOR: ON
8827 11:55:04.026293 HW_SAVE_FOR_SR: OFF
8828 11:55:04.029237 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
8829 11:55:04.032694 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
8830 11:55:04.033250 Read ODT Tracking: ON
8831 11:55:04.035972 Refresh Rate DeBounce: ON
8832 11:55:04.039176 DFS_NO_QUEUE_FLUSH: ON
8833 11:55:04.042808 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
8834 11:55:04.043391 ENABLE_DFS_RUNTIME_MRW: OFF
8835 11:55:04.045745 DDR_RESERVE_NEW_MODE: ON
8836 11:55:04.049196 MR_CBT_SWITCH_FREQ: ON
8837 11:55:04.049771 =========================
8838 11:55:04.069380 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
8839 11:55:04.072345 dram_init: ddr_geometry: 0
8840 11:55:04.090763 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
8841 11:55:04.094006 dram_init: dram init end (result: 0)
8842 11:55:04.100699 DRAM-K: Full calibration passed in 23365 msecs
8843 11:55:04.103917 MRC: failed to locate region type 0.
8844 11:55:04.104474 DRAM rank0 size:0x80000000,
8845 11:55:04.107410 DRAM rank1 size=0x80000000
8846 11:55:04.117220 Mapping address range [0x40000000:0x140000000) as cacheable | read-write | non-secure | normal
8847 11:55:04.123984 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
8848 11:55:04.130489 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
8849 11:55:04.137152 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
8850 11:55:04.140580 DRAM rank0 size:0x80000000,
8851 11:55:04.143692 DRAM rank1 size=0x80000000
8852 11:55:04.144249 CBMEM:
8853 11:55:04.147085 IMD: root @ 0xfffff000 254 entries.
8854 11:55:04.149832 IMD: root @ 0xffffec00 62 entries.
8855 11:55:04.153414 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
8856 11:55:04.156809 WARNING: RO_VPD is uninitialized or empty.
8857 11:55:04.163323 FMAP: area RW_VPD found @ 577000 (16384 bytes)
8858 11:55:04.170410 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
8859 11:55:04.183413 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
8860 11:55:04.194391 BS: romstage times (exec / console): total (unknown) / 22911 ms
8861 11:55:04.194949
8862 11:55:04.195314
8863 11:55:04.204392 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
8864 11:55:04.207991 ARM64: Exception handlers installed.
8865 11:55:04.210774 ARM64: Testing exception
8866 11:55:04.214433 ARM64: Done test exception
8867 11:55:04.214990 Enumerating buses...
8868 11:55:04.217390 Show all devs... Before device enumeration.
8869 11:55:04.220798 Root Device: enabled 1
8870 11:55:04.224486 CPU_CLUSTER: 0: enabled 1
8871 11:55:04.225094 CPU: 00: enabled 1
8872 11:55:04.227517 Compare with tree...
8873 11:55:04.228071 Root Device: enabled 1
8874 11:55:04.231383 CPU_CLUSTER: 0: enabled 1
8875 11:55:04.234041 CPU: 00: enabled 1
8876 11:55:04.234595 Root Device scanning...
8877 11:55:04.237270 scan_static_bus for Root Device
8878 11:55:04.240859 CPU_CLUSTER: 0 enabled
8879 11:55:04.244044 scan_static_bus for Root Device done
8880 11:55:04.247417 scan_bus: bus Root Device finished in 8 msecs
8881 11:55:04.247877 done
8882 11:55:04.254015 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
8883 11:55:04.257472 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
8884 11:55:04.263824 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
8885 11:55:04.267571 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
8886 11:55:04.270569 Allocating resources...
8887 11:55:04.273709 Reading resources...
8888 11:55:04.277179 Root Device read_resources bus 0 link: 0
8889 11:55:04.277640 DRAM rank0 size:0x80000000,
8890 11:55:04.280292 DRAM rank1 size=0x80000000
8891 11:55:04.283817 CPU_CLUSTER: 0 read_resources bus 0 link: 0
8892 11:55:04.287248 CPU: 00 missing read_resources
8893 11:55:04.290486 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
8894 11:55:04.297191 Root Device read_resources bus 0 link: 0 done
8895 11:55:04.297750 Done reading resources.
8896 11:55:04.304023 Show resources in subtree (Root Device)...After reading.
8897 11:55:04.307055 Root Device child on link 0 CPU_CLUSTER: 0
8898 11:55:04.310526 CPU_CLUSTER: 0 child on link 0 CPU: 00
8899 11:55:04.320550 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8900 11:55:04.321169 CPU: 00
8901 11:55:04.323596 Root Device assign_resources, bus 0 link: 0
8902 11:55:04.326928 CPU_CLUSTER: 0 missing set_resources
8903 11:55:04.333467 Root Device assign_resources, bus 0 link: 0 done
8904 11:55:04.334038 Done setting resources.
8905 11:55:04.339943 Show resources in subtree (Root Device)...After assigning values.
8906 11:55:04.343396 Root Device child on link 0 CPU_CLUSTER: 0
8907 11:55:04.346281 CPU_CLUSTER: 0 child on link 0 CPU: 00
8908 11:55:04.356399 CPU_CLUSTER: 0 resource base 40000000 size 100000000 align 0 gran 0 limit 0 flags e0004200 index 0
8909 11:55:04.356923 CPU: 00
8910 11:55:04.359853 Done allocating resources.
8911 11:55:04.366262 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
8912 11:55:04.366726 Enabling resources...
8913 11:55:04.367092 done.
8914 11:55:04.373037 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
8915 11:55:04.373642 Initializing devices...
8916 11:55:04.376210 Root Device init
8917 11:55:04.376753 init hardware done!
8918 11:55:04.379413 0x00000018: ctrlr->caps
8919 11:55:04.382843 52.000 MHz: ctrlr->f_max
8920 11:55:04.383322 0.400 MHz: ctrlr->f_min
8921 11:55:04.386142 0x40ff8080: ctrlr->voltages
8922 11:55:04.389360 sclk: 390625
8923 11:55:04.390078 Bus Width = 1
8924 11:55:04.390721 sclk: 390625
8925 11:55:04.392647 Bus Width = 1
8926 11:55:04.393363 Early init status = 3
8927 11:55:04.399224 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
8928 11:55:04.402623 in-header: 03 fc 00 00 01 00 00 00
8929 11:55:04.403245 in-data: 00
8930 11:55:04.409126 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
8931 11:55:04.413338 in-header: 03 fd 00 00 00 00 00 00
8932 11:55:04.416842 in-data:
8933 11:55:04.420002 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
8934 11:55:04.424189 in-header: 03 fc 00 00 01 00 00 00
8935 11:55:04.427135 in-data: 00
8936 11:55:04.430206 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
8937 11:55:04.435118 in-header: 03 fd 00 00 00 00 00 00
8938 11:55:04.438378 in-data:
8939 11:55:04.441595 [SSUSB] Setting up USB HOST controller...
8940 11:55:04.445174 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
8941 11:55:04.448570 [SSUSB] phy power-on done.
8942 11:55:04.451365 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
8943 11:55:04.458063 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
8944 11:55:04.461418 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
8945 11:55:04.468354 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
8946 11:55:04.474671 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
8947 11:55:04.481439 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
8948 11:55:04.487952 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
8949 11:55:04.494470 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
8950 11:55:04.498305 SPM: binary array size = 0x9dc
8951 11:55:04.501149 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
8952 11:55:04.507563 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
8953 11:55:04.514281 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
8954 11:55:04.517552 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
8955 11:55:04.524242 configure_display: Starting display init
8956 11:55:04.557901 anx7625_power_on_init: Init interface.
8957 11:55:04.561705 anx7625_disable_pd_protocol: Disabled PD feature.
8958 11:55:04.564820 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
8959 11:55:04.592265 anx7625_start_dp_work: Secure OCM version=00
8960 11:55:04.595626 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
8961 11:55:04.610319 sp_tx_get_edid_block: EDID Block = 1
8962 11:55:04.713556 Extracted contents:
8963 11:55:04.716386 header: 00 ff ff ff ff ff ff 00
8964 11:55:04.719722 serial number: 26 cf 7d 05 00 00 00 00 00 1e
8965 11:55:04.722883 version: 01 04
8966 11:55:04.726254 basic params: 95 1f 11 78 0a
8967 11:55:04.729521 chroma info: 76 90 94 55 54 90 27 21 50 54
8968 11:55:04.732930 established: 00 00 00
8969 11:55:04.739410 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
8970 11:55:04.742739 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
8971 11:55:04.749190 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
8972 11:55:04.755959 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
8973 11:55:04.762437 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
8974 11:55:04.766098 extensions: 00
8975 11:55:04.766178 checksum: fb
8976 11:55:04.766241
8977 11:55:04.769149 Manufacturer: IVO Model 57d Serial Number 0
8978 11:55:04.772370 Made week 0 of 2020
8979 11:55:04.775620 EDID version: 1.4
8980 11:55:04.775701 Digital display
8981 11:55:04.779159 6 bits per primary color channel
8982 11:55:04.779241 DisplayPort interface
8983 11:55:04.782718 Maximum image size: 31 cm x 17 cm
8984 11:55:04.785827 Gamma: 220%
8985 11:55:04.785906 Check DPMS levels
8986 11:55:04.789162 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
8987 11:55:04.795625 First detailed timing is preferred timing
8988 11:55:04.795733 Established timings supported:
8989 11:55:04.799059 Standard timings supported:
8990 11:55:04.802623 Detailed timings
8991 11:55:04.805461 Hex of detail: 383680a07038204018303c0035ae10000019
8992 11:55:04.811961 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
8993 11:55:04.815498 0780 0798 07c8 0820 hborder 0
8994 11:55:04.818696 0438 043b 0447 0458 vborder 0
8995 11:55:04.821840 -hsync -vsync
8996 11:55:04.821920 Did detailed timing
8997 11:55:04.828586 Hex of detail: 000000000000000000000000000000000000
8998 11:55:04.832228 Manufacturer-specified data, tag 0
8999 11:55:04.834929 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9000 11:55:04.838306 ASCII string: InfoVision
9001 11:55:04.841664 Hex of detail: 000000fe00523134304e574635205248200a
9002 11:55:04.844939 ASCII string: R140NWF5 RH
9003 11:55:04.845021 Checksum
9004 11:55:04.848301 Checksum: 0xfb (valid)
9005 11:55:04.851460 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9006 11:55:04.854931 DSI data_rate: 832800000 bps
9007 11:55:04.861768 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9008 11:55:04.864850 anx7625_parse_edid: pixelclock(138800).
9009 11:55:04.868261 hactive(1920), hsync(48), hfp(24), hbp(88)
9010 11:55:04.871535 vactive(1080), vsync(12), vfp(3), vbp(17)
9011 11:55:04.874823 anx7625_dsi_config: config dsi.
9012 11:55:04.881525 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9013 11:55:04.895225 anx7625_dsi_config: success to config DSI
9014 11:55:04.898287 anx7625_dp_start: MIPI phy setup OK.
9015 11:55:04.901841 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9016 11:55:04.905179 mtk_ddp_mode_set invalid vrefresh 60
9017 11:55:04.908433 main_disp_path_setup
9018 11:55:04.908572 ovl_layer_smi_id_en
9019 11:55:04.911652 ovl_layer_smi_id_en
9020 11:55:04.911733 ccorr_config
9021 11:55:04.911796 aal_config
9022 11:55:04.915041 gamma_config
9023 11:55:04.915121 postmask_config
9024 11:55:04.918151 dither_config
9025 11:55:04.921616 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9026 11:55:04.928363 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9027 11:55:04.931539 Root Device init finished in 552 msecs
9028 11:55:04.934831 CPU_CLUSTER: 0 init
9029 11:55:04.941786 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9030 11:55:04.944558 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9031 11:55:04.948025 APU_MBOX 0x190000b0 = 0x10001
9032 11:55:04.951181 APU_MBOX 0x190001b0 = 0x10001
9033 11:55:04.954755 APU_MBOX 0x190005b0 = 0x10001
9034 11:55:04.957854 APU_MBOX 0x190006b0 = 0x10001
9035 11:55:04.964441 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9036 11:55:04.974069 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9037 11:55:04.986459 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9038 11:55:04.993077 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9039 11:55:05.004987 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9040 11:55:05.013942 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9041 11:55:05.017027 CPU_CLUSTER: 0 init finished in 81 msecs
9042 11:55:05.020412 Devices initialized
9043 11:55:05.023812 Show all devs... After init.
9044 11:55:05.023892 Root Device: enabled 1
9045 11:55:05.026891 CPU_CLUSTER: 0: enabled 1
9046 11:55:05.030407 CPU: 00: enabled 1
9047 11:55:05.033677 BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms
9048 11:55:05.036728 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9049 11:55:05.040050 ELOG: NV offset 0x57f000 size 0x1000
9050 11:55:05.047003 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9051 11:55:05.053760 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9052 11:55:05.057247 ELOG: Event(17) added with size 13 at 2023-11-23 11:55:06 UTC
9053 11:55:05.060438 out: cmd=0x121: 03 db 21 01 00 00 00 00
9054 11:55:05.064624 in-header: 03 2d 00 00 2c 00 00 00
9055 11:55:05.077904 in-data: 36 64 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9056 11:55:05.084490 ELOG: Event(A1) added with size 10 at 2023-11-23 11:55:06 UTC
9057 11:55:05.091208 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9058 11:55:05.097738 ELOG: Event(A0) added with size 9 at 2023-11-23 11:55:06 UTC
9059 11:55:05.101016 elog_add_boot_reason: Logged dev mode boot
9060 11:55:05.104366 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9061 11:55:05.107557 Finalize devices...
9062 11:55:05.107637 Devices finalized
9063 11:55:05.114204 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9064 11:55:05.117517 Writing coreboot table at 0xffe64000
9065 11:55:05.121410 0. 000000000010a000-0000000000113fff: RAMSTAGE
9066 11:55:05.124104 1. 0000000040000000-00000000400fffff: RAM
9067 11:55:05.130609 2. 0000000040100000-000000004032afff: RAMSTAGE
9068 11:55:05.134554 3. 000000004032b000-00000000545fffff: RAM
9069 11:55:05.137330 4. 0000000054600000-000000005465ffff: BL31
9070 11:55:05.140635 5. 0000000054660000-00000000ffe63fff: RAM
9071 11:55:05.147540 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9072 11:55:05.150684 7. 0000000100000000-000000013fffffff: RAM
9073 11:55:05.150764 Passing 5 GPIOs to payload:
9074 11:55:05.157453 NAME | PORT | POLARITY | VALUE
9075 11:55:05.160910 EC in RW | 0x000000aa | low | undefined
9076 11:55:05.167353 EC interrupt | 0x00000005 | low | undefined
9077 11:55:05.170601 TPM interrupt | 0x000000ab | high | undefined
9078 11:55:05.177068 SD card detect | 0x00000011 | high | undefined
9079 11:55:05.180353 speaker enable | 0x00000093 | high | undefined
9080 11:55:05.183780 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9081 11:55:05.187077 in-header: 03 f8 00 00 02 00 00 00
9082 11:55:05.187166 in-data: 03 00
9083 11:55:05.190490 ADC[4]: Raw value=670063 ID=5
9084 11:55:05.193680 ADC[3]: Raw value=212180 ID=1
9085 11:55:05.197350 RAM Code: 0x51
9086 11:55:05.197430 ADC[6]: Raw value=74778 ID=0
9087 11:55:05.200490 ADC[5]: Raw value=211444 ID=1
9088 11:55:05.203485 SKU Code: 0x1
9089 11:55:05.207133 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 9ab
9090 11:55:05.210326 coreboot table: 964 bytes.
9091 11:55:05.213435 IMD ROOT 0. 0xfffff000 0x00001000
9092 11:55:05.216959 IMD SMALL 1. 0xffffe000 0x00001000
9093 11:55:05.220243 RO MCACHE 2. 0xffffc000 0x00001104
9094 11:55:05.223431 CONSOLE 3. 0xfff7c000 0x00080000
9095 11:55:05.226783 FMAP 4. 0xfff7b000 0x00000452
9096 11:55:05.230190 TIME STAMP 5. 0xfff7a000 0x00000910
9097 11:55:05.233562 VBOOT WORK 6. 0xfff66000 0x00014000
9098 11:55:05.236761 RAMOOPS 7. 0xffe66000 0x00100000
9099 11:55:05.240053 COREBOOT 8. 0xffe64000 0x00002000
9100 11:55:05.240134 IMD small region:
9101 11:55:05.243265 IMD ROOT 0. 0xffffec00 0x00000400
9102 11:55:05.246531 VPD 1. 0xffffeb80 0x0000006c
9103 11:55:05.250289 MMC STATUS 2. 0xffffeb60 0x00000004
9104 11:55:05.256770 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9105 11:55:05.259981 Probing TPM: done!
9106 11:55:05.263746 Connected to device vid:did:rid of 1ae0:0028:00
9107 11:55:05.273541 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2fcb6
9108 11:55:05.276735 Initialized TPM device CR50 revision 0
9109 11:55:05.280936 Checking cr50 for pending updates
9110 11:55:05.284104 Reading cr50 TPM mode
9111 11:55:05.292399 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9112 11:55:05.298907 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9113 11:55:05.338924 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9114 11:55:05.342368 Checking segment from ROM address 0x40100000
9115 11:55:05.345606 Checking segment from ROM address 0x4010001c
9116 11:55:05.352475 Loading segment from ROM address 0x40100000
9117 11:55:05.352565 code (compression=0)
9118 11:55:05.362320 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9119 11:55:05.368942 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9120 11:55:05.369023 it's not compressed!
9121 11:55:05.375544 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9122 11:55:05.379181 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9123 11:55:05.399747 Loading segment from ROM address 0x4010001c
9124 11:55:05.399829 Entry Point 0x80000000
9125 11:55:05.402840 Loaded segments
9126 11:55:05.406170 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9127 11:55:05.412708 Jumping to boot code at 0x80000000(0xffe64000)
9128 11:55:05.419412 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9129 11:55:05.426146 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9130 11:55:05.434030 read SPI 0x8eb68 0x74a8: 3222 us, 9268 KB/s, 74.144 Mbps
9131 11:55:05.437056 Checking segment from ROM address 0x40100000
9132 11:55:05.440789 Checking segment from ROM address 0x4010001c
9133 11:55:05.447243 Loading segment from ROM address 0x40100000
9134 11:55:05.447351 code (compression=1)
9135 11:55:05.453857 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9136 11:55:05.463840 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9137 11:55:05.463921 using LZMA
9138 11:55:05.472156 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9139 11:55:05.478953 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9140 11:55:05.482385 Loading segment from ROM address 0x4010001c
9141 11:55:05.482467 Entry Point 0x54601000
9142 11:55:05.485527 Loaded segments
9143 11:55:05.488843 NOTICE: MT8192 bl31_setup
9144 11:55:05.495705 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9145 11:55:05.499281 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9146 11:55:05.502561 WARNING: region 0:
9147 11:55:05.505667 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9148 11:55:05.505749 WARNING: region 1:
9149 11:55:05.512471 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9150 11:55:05.515972 WARNING: region 2:
9151 11:55:05.519243 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9152 11:55:05.522789 WARNING: region 3:
9153 11:55:05.525661 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9154 11:55:05.529001 WARNING: region 4:
9155 11:55:05.535846 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9156 11:55:05.535927 WARNING: region 5:
9157 11:55:05.539279 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9158 11:55:05.542650 WARNING: region 6:
9159 11:55:05.545828 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9160 11:55:05.545909 WARNING: region 7:
9161 11:55:05.552469 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9162 11:55:05.559547 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9163 11:55:05.562709 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9164 11:55:05.566175 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9165 11:55:05.572933 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9166 11:55:05.575881 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9167 11:55:05.579301 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9168 11:55:05.585758 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9169 11:55:05.589098 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9170 11:55:05.595800 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9171 11:55:05.599206 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9172 11:55:05.602725 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9173 11:55:05.609327 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9174 11:55:05.612474 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9175 11:55:05.616198 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9176 11:55:05.622476 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9177 11:55:05.626081 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9178 11:55:05.629411 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9179 11:55:05.635830 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9180 11:55:05.639101 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9181 11:55:05.645965 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9182 11:55:05.648991 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9183 11:55:05.652691 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9184 11:55:05.659234 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9185 11:55:05.662480 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9186 11:55:05.669105 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9187 11:55:05.672595 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9188 11:55:05.675987 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9189 11:55:05.682665 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9190 11:55:05.685995 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9191 11:55:05.692408 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9192 11:55:05.695805 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9193 11:55:05.698965 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9194 11:55:05.705796 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9195 11:55:05.708983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9196 11:55:05.712433 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9197 11:55:05.715981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9198 11:55:05.722305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9199 11:55:05.725577 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9200 11:55:05.729220 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9201 11:55:05.732235 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9202 11:55:05.738912 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9203 11:55:05.742342 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9204 11:55:05.745687 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9205 11:55:05.749177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9206 11:55:05.755737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9207 11:55:05.758979 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9208 11:55:05.762295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9209 11:55:05.766097 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9210 11:55:05.772093 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9211 11:55:05.775438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9212 11:55:05.782199 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9213 11:55:05.785677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9214 11:55:05.792068 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9215 11:55:05.795406 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9216 11:55:05.798752 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9217 11:55:05.805558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9218 11:55:05.808710 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9219 11:55:05.815442 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9220 11:55:05.818954 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9221 11:55:05.825341 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9222 11:55:05.828930 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9223 11:55:05.832137 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9224 11:55:05.839064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9225 11:55:05.841985 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9226 11:55:05.848643 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9227 11:55:05.851869 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9228 11:55:05.858797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9229 11:55:05.862115 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9230 11:55:05.865448 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9231 11:55:05.872068 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9232 11:55:05.875468 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9233 11:55:05.881859 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9234 11:55:05.885513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9235 11:55:05.891989 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9236 11:55:05.895340 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9237 11:55:05.898838 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9238 11:55:05.905554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9239 11:55:05.908703 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9240 11:55:05.915184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9241 11:55:05.918618 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9242 11:55:05.925293 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9243 11:55:05.928511 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9244 11:55:05.935269 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9245 11:55:05.938351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9246 11:55:05.941898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9247 11:55:05.948292 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9248 11:55:05.951743 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9249 11:55:05.958341 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9250 11:55:05.961844 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9251 11:55:05.968463 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9252 11:55:05.971902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9253 11:55:05.975145 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9254 11:55:05.982031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9255 11:55:05.985348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9256 11:55:05.991823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9257 11:55:05.995034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9258 11:55:05.998240 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9259 11:55:06.005058 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9260 11:55:06.008314 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9261 11:55:06.011690 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9262 11:55:06.015039 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9263 11:55:06.021503 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9264 11:55:06.025209 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9265 11:55:06.031682 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9266 11:55:06.035287 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9267 11:55:06.038328 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9268 11:55:06.044970 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9269 11:55:06.048373 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9270 11:55:06.054915 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9271 11:55:06.058275 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9272 11:55:06.061704 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9273 11:55:06.068483 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9274 11:55:06.071431 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9275 11:55:06.078045 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9276 11:55:06.081567 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9277 11:55:06.084672 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9278 11:55:06.091534 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9279 11:55:06.094555 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9280 11:55:06.098274 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9281 11:55:06.104925 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9282 11:55:06.108061 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9283 11:55:06.111418 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9284 11:55:06.114853 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9285 11:55:06.121151 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9286 11:55:06.124585 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9287 11:55:06.128139 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9288 11:55:06.134653 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9289 11:55:06.138007 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9290 11:55:06.145180 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9291 11:55:06.148335 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9292 11:55:06.151507 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9293 11:55:06.158216 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9294 11:55:06.161360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9295 11:55:06.164859 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9296 11:55:06.171630 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9297 11:55:06.174829 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9298 11:55:06.181387 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9299 11:55:06.184547 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9300 11:55:06.188080 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9301 11:55:06.194619 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9302 11:55:06.198123 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9303 11:55:06.204690 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9304 11:55:06.208068 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9305 11:55:06.211504 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9306 11:55:06.217977 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9307 11:55:06.221316 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9308 11:55:06.224606 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9309 11:55:06.231312 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9310 11:55:06.234915 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9311 11:55:06.241214 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9312 11:55:06.244672 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9313 11:55:06.247870 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9314 11:55:06.254635 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9315 11:55:06.257943 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9316 11:55:06.264478 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9317 11:55:06.267823 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9318 11:55:06.271184 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9319 11:55:06.278140 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9320 11:55:06.281289 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9321 11:55:06.287886 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9322 11:55:06.290973 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9323 11:55:06.294429 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9324 11:55:06.301062 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9325 11:55:06.304218 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9326 11:55:06.310925 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9327 11:55:06.314135 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9328 11:55:06.317451 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9329 11:55:06.324342 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9330 11:55:06.327473 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9331 11:55:06.331008 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9332 11:55:06.337514 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9333 11:55:06.340661 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9334 11:55:06.347547 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9335 11:55:06.350717 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9336 11:55:06.353867 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9337 11:55:06.360755 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9338 11:55:06.363772 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9339 11:55:06.370448 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9340 11:55:06.373837 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9341 11:55:06.376925 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9342 11:55:06.383468 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9343 11:55:06.386861 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9344 11:55:06.393499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9345 11:55:06.396731 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9346 11:55:06.400305 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9347 11:55:06.406793 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9348 11:55:06.410280 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9349 11:55:06.416822 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9350 11:55:06.420073 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9351 11:55:06.423466 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9352 11:55:06.429957 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9353 11:55:06.433815 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9354 11:55:06.440137 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9355 11:55:06.443620 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9356 11:55:06.450017 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9357 11:55:06.453244 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9358 11:55:06.456639 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9359 11:55:06.463290 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9360 11:55:06.466506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9361 11:55:06.473293 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9362 11:55:06.476462 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9363 11:55:06.479653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9364 11:55:06.486284 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9365 11:55:06.489608 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9366 11:55:06.496269 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9367 11:55:06.499797 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9368 11:55:06.506303 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9369 11:55:06.509478 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9370 11:55:06.512949 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9371 11:55:06.519708 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9372 11:55:06.522852 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9373 11:55:06.529276 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9374 11:55:06.532562 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9375 11:55:06.539176 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9376 11:55:06.542961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9377 11:55:06.546012 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9378 11:55:06.552817 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9379 11:55:06.555930 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9380 11:55:06.562741 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9381 11:55:06.565740 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9382 11:55:06.569164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9383 11:55:06.575910 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9384 11:55:06.579216 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9385 11:55:06.585640 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9386 11:55:06.588999 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9387 11:55:06.595545 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9388 11:55:06.598893 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9389 11:55:06.602390 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9390 11:55:06.608749 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9391 11:55:06.612378 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9392 11:55:06.615683 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9393 11:55:06.618868 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9394 11:55:06.625416 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9395 11:55:06.628698 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9396 11:55:06.632154 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9397 11:55:06.638913 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9398 11:55:06.642149 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9399 11:55:06.648673 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9400 11:55:06.652051 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9401 11:55:06.655440 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9402 11:55:06.661890 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9403 11:55:06.665273 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9404 11:55:06.668555 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9405 11:55:06.675162 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9406 11:55:06.678514 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9407 11:55:06.681925 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9408 11:55:06.688815 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9409 11:55:06.691872 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9410 11:55:06.695110 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9411 11:55:06.701640 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9412 11:55:06.705044 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9413 11:55:06.711863 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9414 11:55:06.714835 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9415 11:55:06.718364 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9416 11:55:06.724858 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9417 11:55:06.728254 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9418 11:55:06.734781 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9419 11:55:06.738341 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9420 11:55:06.741486 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9421 11:55:06.748043 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9422 11:55:06.751229 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9423 11:55:06.754774 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9424 11:55:06.761161 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9425 11:55:06.764673 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9426 11:55:06.767915 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9427 11:55:06.774330 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9428 11:55:06.777870 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9429 11:55:06.784458 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9430 11:55:06.787561 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9431 11:55:06.791042 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9432 11:55:06.794541 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9433 11:55:06.797542 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9434 11:55:06.804207 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9435 11:55:06.807505 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9436 11:55:06.811262 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9437 11:55:06.814369 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9438 11:55:06.820896 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9439 11:55:06.824130 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9440 11:55:06.827929 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9441 11:55:06.831110 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9442 11:55:06.837355 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9443 11:55:06.840728 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9444 11:55:06.844066 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9445 11:55:06.850680 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9446 11:55:06.854313 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9447 11:55:06.861005 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9448 11:55:06.863939 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9449 11:55:06.870764 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9450 11:55:06.874239 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9451 11:55:06.877338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9452 11:55:06.883988 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9453 11:55:06.887250 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9454 11:55:06.893951 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9455 11:55:06.897096 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9456 11:55:06.900820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9457 11:55:06.907333 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9458 11:55:06.910454 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9459 11:55:06.917132 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9460 11:55:06.920382 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9461 11:55:06.923776 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9462 11:55:06.930526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9463 11:55:06.933978 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9464 11:55:06.940183 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9465 11:55:06.943653 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9466 11:55:06.950225 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9467 11:55:06.953569 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9468 11:55:06.956758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9469 11:55:06.963619 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9470 11:55:06.966545 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9471 11:55:06.973366 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9472 11:55:06.976470 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9473 11:55:06.983255 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9474 11:55:06.986495 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9475 11:55:06.989617 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9476 11:55:06.996392 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9477 11:55:06.999616 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9478 11:55:07.006124 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9479 11:55:07.009505 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9480 11:55:07.012806 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9481 11:55:07.019515 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9482 11:55:07.022849 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9483 11:55:07.029620 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9484 11:55:07.032818 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9485 11:55:07.036015 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9486 11:55:07.042720 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9487 11:55:07.045849 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9488 11:55:07.052675 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9489 11:55:07.055921 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9490 11:55:07.062678 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9491 11:55:07.066252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9492 11:55:07.069175 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9493 11:55:07.075441 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9494 11:55:07.078900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9495 11:55:07.085570 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9496 11:55:07.088548 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9497 11:55:07.095239 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9498 11:55:07.098611 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9499 11:55:07.101961 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9500 11:55:07.108443 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9501 11:55:07.112004 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9502 11:55:07.118322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9503 11:55:07.121810 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9504 11:55:07.125189 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9505 11:55:07.131743 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9506 11:55:07.135250 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9507 11:55:07.141904 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9508 11:55:07.144990 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9509 11:55:07.148281 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9510 11:55:07.154869 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9511 11:55:07.157994 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9512 11:55:07.164651 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9513 11:55:07.167878 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9514 11:55:07.174670 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9515 11:55:07.178045 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9516 11:55:07.181414 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9517 11:55:07.187790 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9518 11:55:07.191096 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9519 11:55:07.197846 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9520 11:55:07.200877 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9521 11:55:07.207416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9522 11:55:07.211336 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9523 11:55:07.214208 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9524 11:55:07.220673 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9525 11:55:07.224132 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9526 11:55:07.230698 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9527 11:55:07.234161 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9528 11:55:07.240518 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9529 11:55:07.243829 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9530 11:55:07.250826 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9531 11:55:07.253853 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9532 11:55:07.257415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9533 11:55:07.264083 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9534 11:55:07.267404 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9535 11:55:07.273878 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9536 11:55:07.277057 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9537 11:55:07.283732 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9538 11:55:07.286942 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9539 11:55:07.290284 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9540 11:55:07.296883 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9541 11:55:07.300180 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9542 11:55:07.306846 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9543 11:55:07.310257 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9544 11:55:07.316856 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9545 11:55:07.320192 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9546 11:55:07.326930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9547 11:55:07.330320 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9548 11:55:07.333597 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9549 11:55:07.340519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9550 11:55:07.343313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9551 11:55:07.349854 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9552 11:55:07.353324 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9553 11:55:07.359928 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9554 11:55:07.363246 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9555 11:55:07.366669 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9556 11:55:07.373250 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9557 11:55:07.376309 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9558 11:55:07.382850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9559 11:55:07.386535 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9560 11:55:07.392923 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9561 11:55:07.396237 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9562 11:55:07.403217 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9563 11:55:07.406685 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9564 11:55:07.409765 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9565 11:55:07.416007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9566 11:55:07.419364 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9567 11:55:07.426199 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9568 11:55:07.429544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9569 11:55:07.435953 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9570 11:55:07.439176 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9571 11:55:07.445814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9572 11:55:07.449346 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9573 11:55:07.456083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9574 11:55:07.459250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9575 11:55:07.465991 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9576 11:55:07.469398 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9577 11:55:07.472469 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9578 11:55:07.479098 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9579 11:55:07.482377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9580 11:55:07.489022 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9581 11:55:07.492448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9582 11:55:07.499144 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9583 11:55:07.502283 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9584 11:55:07.508922 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9585 11:55:07.512202 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9586 11:55:07.518820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9587 11:55:07.522245 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9588 11:55:07.528820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9589 11:55:07.532135 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9590 11:55:07.538884 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9591 11:55:07.542118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9592 11:55:07.548759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9593 11:55:07.552338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9594 11:55:07.558654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9595 11:55:07.561846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9596 11:55:07.568320 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9597 11:55:07.568401 INFO: [APUAPC] vio 0
9598 11:55:07.575889 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9599 11:55:07.579000 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9600 11:55:07.582379 INFO: [APUAPC] D0_APC_0: 0x400510
9601 11:55:07.585714 INFO: [APUAPC] D0_APC_1: 0x0
9602 11:55:07.588999 INFO: [APUAPC] D0_APC_2: 0x1540
9603 11:55:07.592178 INFO: [APUAPC] D0_APC_3: 0x0
9604 11:55:07.595632 INFO: [APUAPC] D1_APC_0: 0xffffffff
9605 11:55:07.598995 INFO: [APUAPC] D1_APC_1: 0xffffffff
9606 11:55:07.602241 INFO: [APUAPC] D1_APC_2: 0x3fffff
9607 11:55:07.605526 INFO: [APUAPC] D1_APC_3: 0x0
9608 11:55:07.608950 INFO: [APUAPC] D2_APC_0: 0xffffffff
9609 11:55:07.612024 INFO: [APUAPC] D2_APC_1: 0xffffffff
9610 11:55:07.615471 INFO: [APUAPC] D2_APC_2: 0x3fffff
9611 11:55:07.618494 INFO: [APUAPC] D2_APC_3: 0x0
9612 11:55:07.621925 INFO: [APUAPC] D3_APC_0: 0xffffffff
9613 11:55:07.625406 INFO: [APUAPC] D3_APC_1: 0xffffffff
9614 11:55:07.628633 INFO: [APUAPC] D3_APC_2: 0x3fffff
9615 11:55:07.632004 INFO: [APUAPC] D3_APC_3: 0x0
9616 11:55:07.635108 INFO: [APUAPC] D4_APC_0: 0xffffffff
9617 11:55:07.638630 INFO: [APUAPC] D4_APC_1: 0xffffffff
9618 11:55:07.642008 INFO: [APUAPC] D4_APC_2: 0x3fffff
9619 11:55:07.645059 INFO: [APUAPC] D4_APC_3: 0x0
9620 11:55:07.648463 INFO: [APUAPC] D5_APC_0: 0xffffffff
9621 11:55:07.651664 INFO: [APUAPC] D5_APC_1: 0xffffffff
9622 11:55:07.654809 INFO: [APUAPC] D5_APC_2: 0x3fffff
9623 11:55:07.654889 INFO: [APUAPC] D5_APC_3: 0x0
9624 11:55:07.661772 INFO: [APUAPC] D6_APC_0: 0xffffffff
9625 11:55:07.665082 INFO: [APUAPC] D6_APC_1: 0xffffffff
9626 11:55:07.668390 INFO: [APUAPC] D6_APC_2: 0x3fffff
9627 11:55:07.668516 INFO: [APUAPC] D6_APC_3: 0x0
9628 11:55:07.671687 INFO: [APUAPC] D7_APC_0: 0xffffffff
9629 11:55:07.674748 INFO: [APUAPC] D7_APC_1: 0xffffffff
9630 11:55:07.678065 INFO: [APUAPC] D7_APC_2: 0x3fffff
9631 11:55:07.681517 INFO: [APUAPC] D7_APC_3: 0x0
9632 11:55:07.684674 INFO: [APUAPC] D8_APC_0: 0xffffffff
9633 11:55:07.688102 INFO: [APUAPC] D8_APC_1: 0xffffffff
9634 11:55:07.691095 INFO: [APUAPC] D8_APC_2: 0x3fffff
9635 11:55:07.694380 INFO: [APUAPC] D8_APC_3: 0x0
9636 11:55:07.697853 INFO: [APUAPC] D9_APC_0: 0xffffffff
9637 11:55:07.701186 INFO: [APUAPC] D9_APC_1: 0xffffffff
9638 11:55:07.704342 INFO: [APUAPC] D9_APC_2: 0x3fffff
9639 11:55:07.707961 INFO: [APUAPC] D9_APC_3: 0x0
9640 11:55:07.711069 INFO: [APUAPC] D10_APC_0: 0xffffffff
9641 11:55:07.714566 INFO: [APUAPC] D10_APC_1: 0xffffffff
9642 11:55:07.717627 INFO: [APUAPC] D10_APC_2: 0x3fffff
9643 11:55:07.721055 INFO: [APUAPC] D10_APC_3: 0x0
9644 11:55:07.724388 INFO: [APUAPC] D11_APC_0: 0xffffffff
9645 11:55:07.727755 INFO: [APUAPC] D11_APC_1: 0xffffffff
9646 11:55:07.731024 INFO: [APUAPC] D11_APC_2: 0x3fffff
9647 11:55:07.734446 INFO: [APUAPC] D11_APC_3: 0x0
9648 11:55:07.737664 INFO: [APUAPC] D12_APC_0: 0xffffffff
9649 11:55:07.741061 INFO: [APUAPC] D12_APC_1: 0xffffffff
9650 11:55:07.744338 INFO: [APUAPC] D12_APC_2: 0x3fffff
9651 11:55:07.747825 INFO: [APUAPC] D12_APC_3: 0x0
9652 11:55:07.750788 INFO: [APUAPC] D13_APC_0: 0xffffffff
9653 11:55:07.754124 INFO: [APUAPC] D13_APC_1: 0xffffffff
9654 11:55:07.757590 INFO: [APUAPC] D13_APC_2: 0x3fffff
9655 11:55:07.760618 INFO: [APUAPC] D13_APC_3: 0x0
9656 11:55:07.764292 INFO: [APUAPC] D14_APC_0: 0xffffffff
9657 11:55:07.767938 INFO: [APUAPC] D14_APC_1: 0xffffffff
9658 11:55:07.770967 INFO: [APUAPC] D14_APC_2: 0x3fffff
9659 11:55:07.774143 INFO: [APUAPC] D14_APC_3: 0x0
9660 11:55:07.777859 INFO: [APUAPC] D15_APC_0: 0xffffffff
9661 11:55:07.784328 INFO: [APUAPC] D15_APC_1: 0xffffffff
9662 11:55:07.787315 INFO: [APUAPC] D15_APC_2: 0x3fffff
9663 11:55:07.787396 INFO: [APUAPC] D15_APC_3: 0x0
9664 11:55:07.790908 INFO: [APUAPC] APC_CON: 0x4
9665 11:55:07.794050 INFO: [NOCDAPC] D0_APC_0: 0x0
9666 11:55:07.797319 INFO: [NOCDAPC] D0_APC_1: 0x0
9667 11:55:07.800786 INFO: [NOCDAPC] D1_APC_0: 0x0
9668 11:55:07.804001 INFO: [NOCDAPC] D1_APC_1: 0xfff
9669 11:55:07.807184 INFO: [NOCDAPC] D2_APC_0: 0x0
9670 11:55:07.810966 INFO: [NOCDAPC] D2_APC_1: 0xfff
9671 11:55:07.814028 INFO: [NOCDAPC] D3_APC_0: 0x0
9672 11:55:07.814115 INFO: [NOCDAPC] D3_APC_1: 0xfff
9673 11:55:07.817240 INFO: [NOCDAPC] D4_APC_0: 0x0
9674 11:55:07.820639 INFO: [NOCDAPC] D4_APC_1: 0xfff
9675 11:55:07.823909 INFO: [NOCDAPC] D5_APC_0: 0x0
9676 11:55:07.827436 INFO: [NOCDAPC] D5_APC_1: 0xfff
9677 11:55:07.830502 INFO: [NOCDAPC] D6_APC_0: 0x0
9678 11:55:07.833709 INFO: [NOCDAPC] D6_APC_1: 0xfff
9679 11:55:07.837172 INFO: [NOCDAPC] D7_APC_0: 0x0
9680 11:55:07.840233 INFO: [NOCDAPC] D7_APC_1: 0xfff
9681 11:55:07.843535 INFO: [NOCDAPC] D8_APC_0: 0x0
9682 11:55:07.847232 INFO: [NOCDAPC] D8_APC_1: 0xfff
9683 11:55:07.847360 INFO: [NOCDAPC] D9_APC_0: 0x0
9684 11:55:07.850383 INFO: [NOCDAPC] D9_APC_1: 0xfff
9685 11:55:07.853410 INFO: [NOCDAPC] D10_APC_0: 0x0
9686 11:55:07.856704 INFO: [NOCDAPC] D10_APC_1: 0xfff
9687 11:55:07.860038 INFO: [NOCDAPC] D11_APC_0: 0x0
9688 11:55:07.863603 INFO: [NOCDAPC] D11_APC_1: 0xfff
9689 11:55:07.866904 INFO: [NOCDAPC] D12_APC_0: 0x0
9690 11:55:07.870154 INFO: [NOCDAPC] D12_APC_1: 0xfff
9691 11:55:07.873150 INFO: [NOCDAPC] D13_APC_0: 0x0
9692 11:55:07.876623 INFO: [NOCDAPC] D13_APC_1: 0xfff
9693 11:55:07.880013 INFO: [NOCDAPC] D14_APC_0: 0x0
9694 11:55:07.883212 INFO: [NOCDAPC] D14_APC_1: 0xfff
9695 11:55:07.886714 INFO: [NOCDAPC] D15_APC_0: 0x0
9696 11:55:07.889781 INFO: [NOCDAPC] D15_APC_1: 0xfff
9697 11:55:07.892946 INFO: [NOCDAPC] APC_CON: 0x4
9698 11:55:07.896362 INFO: [APUAPC] set_apusys_apc done
9699 11:55:07.899871 INFO: [DEVAPC] devapc_init done
9700 11:55:07.903287 INFO: GICv3 without legacy support detected.
9701 11:55:07.906548 INFO: ARM GICv3 driver initialized in EL3
9702 11:55:07.909747 INFO: Maximum SPI INTID supported: 639
9703 11:55:07.913103 INFO: BL31: Initializing runtime services
9704 11:55:07.919623 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9705 11:55:07.922709 INFO: SPM: enable CPC mode
9706 11:55:07.926278 INFO: mcdi ready for mcusys-off-idle and system suspend
9707 11:55:07.932950 INFO: BL31: Preparing for EL3 exit to normal world
9708 11:55:07.936407 INFO: Entry point address = 0x80000000
9709 11:55:07.939349 INFO: SPSR = 0x8
9710 11:55:07.943664
9711 11:55:07.943744
9712 11:55:07.943808
9713 11:55:07.947288 Starting depthcharge on Spherion...
9714 11:55:07.947368
9715 11:55:07.947431 Wipe memory regions:
9716 11:55:07.947491
9717 11:55:07.948149 end: 2.2.3 depthcharge-start (duration 00:00:28) [common]
9718 11:55:07.948252 start: 2.2.4 bootloader-commands (timeout 00:04:26) [common]
9719 11:55:07.948351 Setting prompt string to ['asurada:']
9720 11:55:07.948427 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:26)
9721 11:55:07.950335 [0x00000040000000, 0x00000054600000)
9722 11:55:08.072497
9723 11:55:08.072638 [0x00000054660000, 0x00000080000000)
9724 11:55:08.333528
9725 11:55:08.333693 [0x000000821a7280, 0x000000ffe64000)
9726 11:55:09.078422
9727 11:55:09.078573 [0x00000100000000, 0x00000140000000)
9728 11:55:09.459378
9729 11:55:09.462810 Initializing XHCI USB controller at 0x11200000.
9730 11:55:10.501256
9731 11:55:10.504059 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
9732 11:55:10.504143
9733 11:55:10.504206
9734 11:55:10.504265
9735 11:55:10.504594 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9737 11:55:10.604941 asurada: tftpboot 192.168.201.1 12066548/tftp-deploy-a36_81vh/kernel/image.itb 12066548/tftp-deploy-a36_81vh/kernel/cmdline
9738 11:55:10.605066 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
9739 11:55:10.605150 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:24)
9740 11:55:10.609283 tftpboot 192.168.201.1 12066548/tftp-deploy-a36_81vh/kernel/image.itp-deploy-a36_81vh/kernel/cmdline
9741 11:55:10.609378
9742 11:55:10.609446 Waiting for link
9743 11:55:10.769727
9744 11:55:10.769854 R8152: Initializing
9745 11:55:10.769920
9746 11:55:10.772986 Version 9 (ocp_data = 6010)
9747 11:55:10.773067
9748 11:55:10.776240 R8152: Done initializing
9749 11:55:10.776320
9750 11:55:10.776384 Adding net device
9751 11:55:12.662595
9752 11:55:12.662742 done.
9753 11:55:12.662809
9754 11:55:12.662870 MAC: 00:e0:4c:68:03:bd
9755 11:55:12.662927
9756 11:55:12.665614 Sending DHCP discover... done.
9757 11:55:12.665697
9758 11:55:12.668889 Waiting for reply... done.
9759 11:55:12.668969
9760 11:55:12.672349 Sending DHCP request... done.
9761 11:55:12.672428
9762 11:55:12.677415 Waiting for reply... done.
9763 11:55:12.677495
9764 11:55:12.677558 My ip is 192.168.201.16
9765 11:55:12.677617
9766 11:55:12.680411 The DHCP server ip is 192.168.201.1
9767 11:55:12.680491
9768 11:55:12.687147 TFTP server IP predefined by user: 192.168.201.1
9769 11:55:12.687227
9770 11:55:12.694008 Bootfile predefined by user: 12066548/tftp-deploy-a36_81vh/kernel/image.itb
9771 11:55:12.694088
9772 11:55:12.697335 Sending tftp read request... done.
9773 11:55:12.697415
9774 11:55:12.700628 Waiting for the transfer...
9775 11:55:12.700707
9776 11:55:12.980325 00000000 ################################################################
9777 11:55:12.980494
9778 11:55:13.274750 00080000 ################################################################
9779 11:55:13.274914
9780 11:55:13.562868 00100000 ################################################################
9781 11:55:13.563010
9782 11:55:13.855937 00180000 ################################################################
9783 11:55:13.856087
9784 11:55:14.141388 00200000 ################################################################
9785 11:55:14.141531
9786 11:55:14.401706 00280000 ################################################################
9787 11:55:14.401842
9788 11:55:14.681139 00300000 ################################################################
9789 11:55:14.681277
9790 11:55:14.957895 00380000 ################################################################
9791 11:55:14.958040
9792 11:55:15.226866 00400000 ################################################################
9793 11:55:15.227038
9794 11:55:15.493675 00480000 ################################################################
9795 11:55:15.493807
9796 11:55:15.753453 00500000 ################################################################
9797 11:55:15.753588
9798 11:55:16.027082 00580000 ################################################################
9799 11:55:16.027214
9800 11:55:16.281057 00600000 ################################################################
9801 11:55:16.281191
9802 11:55:16.568251 00680000 ################################################################
9803 11:55:16.568416
9804 11:55:16.859452 00700000 ################################################################
9805 11:55:16.859597
9806 11:55:17.154927 00780000 ################################################################
9807 11:55:17.155059
9808 11:55:17.448663 00800000 ################################################################
9809 11:55:17.448796
9810 11:55:17.744115 00880000 ################################################################
9811 11:55:17.744269
9812 11:55:18.034084 00900000 ################################################################
9813 11:55:18.034244
9814 11:55:18.305775 00980000 ################################################################
9815 11:55:18.305902
9816 11:55:18.590791 00a00000 ################################################################
9817 11:55:18.590918
9818 11:55:18.874267 00a80000 ################################################################
9819 11:55:18.874402
9820 11:55:19.144253 00b00000 ################################################################
9821 11:55:19.144386
9822 11:55:19.425234 00b80000 ################################################################
9823 11:55:19.425364
9824 11:55:19.703066 00c00000 ################################################################
9825 11:55:19.703198
9826 11:55:19.973238 00c80000 ################################################################
9827 11:55:19.973369
9828 11:55:20.241163 00d00000 ################################################################
9829 11:55:20.241298
9830 11:55:20.516713 00d80000 ################################################################
9831 11:55:20.516849
9832 11:55:20.787896 00e00000 ################################################################
9833 11:55:20.788028
9834 11:55:21.047952 00e80000 ################################################################
9835 11:55:21.048084
9836 11:55:21.333865 00f00000 ################################################################
9837 11:55:21.334001
9838 11:55:21.612381 00f80000 ################################################################
9839 11:55:21.612574
9840 11:55:21.906708 01000000 ################################################################
9841 11:55:21.906840
9842 11:55:22.202476 01080000 ################################################################
9843 11:55:22.202650
9844 11:55:22.494999 01100000 ################################################################
9845 11:55:22.495137
9846 11:55:22.764997 01180000 ################################################################
9847 11:55:22.765128
9848 11:55:23.053894 01200000 ################################################################
9849 11:55:23.054030
9850 11:55:23.314696 01280000 ################################################################
9851 11:55:23.314829
9852 11:55:23.566569 01300000 ################################################################
9853 11:55:23.566703
9854 11:55:23.818526 01380000 ################################################################
9855 11:55:23.818656
9856 11:55:24.067862 01400000 ################################################################
9857 11:55:24.067988
9858 11:55:24.319212 01480000 ################################################################
9859 11:55:24.319345
9860 11:55:24.568970 01500000 ################################################################
9861 11:55:24.569102
9862 11:55:24.816683 01580000 ################################################################
9863 11:55:24.816821
9864 11:55:25.070420 01600000 ################################################################
9865 11:55:25.070551
9866 11:55:25.323292 01680000 ################################################################
9867 11:55:25.323423
9868 11:55:25.580491 01700000 ################################################################
9869 11:55:25.580623
9870 11:55:25.834173 01780000 ################################################################
9871 11:55:25.834302
9872 11:55:26.084489 01800000 ################################################################
9873 11:55:26.084626
9874 11:55:26.348210 01880000 ################################################################
9875 11:55:26.348346
9876 11:55:26.614131 01900000 ################################################################
9877 11:55:26.614276
9878 11:55:26.862376 01980000 ################################################################
9879 11:55:26.862525
9880 11:55:27.145315 01a00000 ################################################################
9881 11:55:27.145460
9882 11:55:27.430060 01a80000 ################################################################
9883 11:55:27.430197
9884 11:55:27.695907 01b00000 ################################################################
9885 11:55:27.696049
9886 11:55:27.972065 01b80000 ################################################################
9887 11:55:27.972212
9888 11:55:28.254995 01c00000 ################################################################
9889 11:55:28.255138
9890 11:55:28.541890 01c80000 ################################################################
9891 11:55:28.542032
9892 11:55:28.822595 01d00000 ################################################################
9893 11:55:28.822743
9894 11:55:29.107951 01d80000 ################################################################
9895 11:55:29.108093
9896 11:55:29.388417 01e00000 ################################################################
9897 11:55:29.388561
9898 11:55:29.668812 01e80000 ################################################################
9899 11:55:29.668953
9900 11:55:29.936785 01f00000 ################################################################
9901 11:55:29.936930
9902 11:55:30.210674 01f80000 ################################################################
9903 11:55:30.210847
9904 11:55:30.500382 02000000 ################################################################
9905 11:55:30.500538
9906 11:55:30.762344 02080000 ################################################################
9907 11:55:30.762486
9908 11:55:31.022937 02100000 ################################################################
9909 11:55:31.023089
9910 11:55:31.276363 02180000 ################################################################
9911 11:55:31.276549
9912 11:55:31.535414 02200000 ################################################################
9913 11:55:31.535552
9914 11:55:31.809676 02280000 ################################################################
9915 11:55:31.809842
9916 11:55:32.104844 02300000 ################################################################
9917 11:55:32.105011
9918 11:55:32.377884 02380000 ################################################################
9919 11:55:32.378051
9920 11:55:32.672984 02400000 ################################################################
9921 11:55:32.673157
9922 11:55:32.959661 02480000 ################################################################
9923 11:55:32.959801
9924 11:55:33.253082 02500000 ################################################################
9925 11:55:33.253227
9926 11:55:33.542418 02580000 ################################################################
9927 11:55:33.542564
9928 11:55:33.831641 02600000 ################################################################
9929 11:55:33.831772
9930 11:55:34.107168 02680000 ################################################################
9931 11:55:34.107319
9932 11:55:34.384453 02700000 ################################################################
9933 11:55:34.384629
9934 11:55:34.665869 02780000 ################################################################
9935 11:55:34.666020
9936 11:55:34.940145 02800000 ################################################################
9937 11:55:34.940296
9938 11:55:35.221354 02880000 ################################################################
9939 11:55:35.221511
9940 11:55:35.518410 02900000 ################################################################
9941 11:55:35.518547
9942 11:55:35.804931 02980000 ################################################################
9943 11:55:35.805060
9944 11:55:36.083053 02a00000 ################################################################
9945 11:55:36.083181
9946 11:55:36.343406 02a80000 ################################################################
9947 11:55:36.343563
9948 11:55:36.619217 02b00000 ################################################################
9949 11:55:36.619407
9950 11:55:36.914691 02b80000 ################################################################
9951 11:55:36.914821
9952 11:55:37.197702 02c00000 ################################################################
9953 11:55:37.197830
9954 11:55:37.452325 02c80000 ################################################################
9955 11:55:37.452487
9956 11:55:37.732969 02d00000 ################################################################
9957 11:55:37.733142
9958 11:55:38.004521 02d80000 ################################################################
9959 11:55:38.004700
9960 11:55:38.277168 02e00000 ################################################################
9961 11:55:38.277305
9962 11:55:38.558364 02e80000 ################################################################
9963 11:55:38.558516
9964 11:55:38.848257 02f00000 ################################################################
9965 11:55:38.848448
9966 11:55:39.135799 02f80000 ################################################################
9967 11:55:39.135963
9968 11:55:39.417921 03000000 ################################################################
9969 11:55:39.418083
9970 11:55:39.701417 03080000 ################################################################
9971 11:55:39.701554
9972 11:55:39.991198 03100000 ################################################################
9973 11:55:39.991331
9974 11:55:40.287096 03180000 ################################################################
9975 11:55:40.287233
9976 11:55:40.579974 03200000 ################################################################
9977 11:55:40.580110
9978 11:55:40.881682 03280000 ################################################################
9979 11:55:40.881820
9980 11:55:41.180983 03300000 ################################################################
9981 11:55:41.181116
9982 11:55:41.565951 03380000 ################################################################
9983 11:55:41.566461
9984 11:55:41.952972 03400000 ################################################################
9985 11:55:41.953109
9986 11:55:42.254714 03480000 ################################################################
9987 11:55:42.254843
9988 11:55:42.555752 03500000 ################################################################
9989 11:55:42.555912
9990 11:55:42.852030 03580000 ################################################################
9991 11:55:42.852184
9992 11:55:43.146370 03600000 ################################################################
9993 11:55:43.146503
9994 11:55:43.498472 03680000 ################################################################
9995 11:55:43.499137
9996 11:55:43.903121 03700000 ################################################################
9997 11:55:43.903713
9998 11:55:44.303498 03780000 ################################################################
9999 11:55:44.303998
10000 11:55:44.630559 03800000 ################################################################
10001 11:55:44.630695
10002 11:55:44.932511 03880000 ################################################################
10003 11:55:44.932658
10004 11:55:45.235911 03900000 ################################################################
10005 11:55:45.236075
10006 11:55:45.519609 03980000 ################################################################
10007 11:55:45.519743
10008 11:55:45.814030 03a00000 ################################################################
10009 11:55:45.814158
10010 11:55:46.116665 03a80000 ################################################################
10011 11:55:46.116801
10012 11:55:46.419956 03b00000 ################################################################
10013 11:55:46.420092
10014 11:55:46.714398 03b80000 ################################################################
10015 11:55:46.714543
10016 11:55:47.018241 03c00000 ################################################################
10017 11:55:47.018366
10018 11:55:47.322021 03c80000 ################################################################
10019 11:55:47.322154
10020 11:55:47.624896 03d00000 ################################################################
10021 11:55:47.625030
10022 11:55:47.928291 03d80000 ################################################################
10023 11:55:47.928432
10024 11:55:48.329175 03e00000 ################################################################
10025 11:55:48.329735
10026 11:55:48.762444 03e80000 ################################################################
10027 11:55:48.762957
10028 11:55:49.171144 03f00000 ################################################################
10029 11:55:49.171702
10030 11:55:49.616494 03f80000 ################################################################
10031 11:55:49.617040
10032 11:55:49.922019 04000000 #################################################### done.
10033 11:55:49.922522
10034 11:55:49.925153 The bootfile was 67528778 bytes long.
10035 11:55:49.925573
10036 11:55:49.928315 Sending tftp read request... done.
10037 11:55:49.928779
10038 11:55:49.931540 Waiting for the transfer...
10039 11:55:49.931955
10040 11:55:49.935178 00000000 # done.
10041 11:55:49.935603
10042 11:55:49.941538 Command line loaded dynamically from TFTP file: 12066548/tftp-deploy-a36_81vh/kernel/cmdline
10043 11:55:49.942036
10044 11:55:49.954862 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10045 11:55:49.955375
10046 11:55:49.955708 Loading FIT.
10047 11:55:49.956021
10048 11:55:49.958202 Image ramdisk-1 has 56432282 bytes.
10049 11:55:49.958619
10050 11:55:49.961477 Image fdt-1 has 47278 bytes.
10051 11:55:49.962035
10052 11:55:49.964855 Image kernel-1 has 11047184 bytes.
10053 11:55:49.965376
10054 11:55:49.974947 Compat preference: google,spherion-rev3-sku1 google,spherion-rev3 google,spherion-sku1 google,spherion
10055 11:55:49.975582
10056 11:55:49.991688 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 (match) google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10057 11:55:49.992237
10058 11:55:49.997930 Choosing best match conf-1 for compat google,spherion-rev3.
10059 11:55:49.998456
10060 11:55:50.005515 Connected to device vid:did:rid of 1ae0:0028:00
10061 11:55:50.012640
10062 11:55:50.015883 tpm_get_response: command 0x17b, return code 0x0
10063 11:55:50.016304
10064 11:55:50.019448 ec_init: CrosEC protocol v3 supported (256, 248)
10065 11:55:50.023856
10066 11:55:50.027006 tpm_cleanup: add release locality here.
10067 11:55:50.027527
10068 11:55:50.027860 Shutting down all USB controllers.
10069 11:55:50.030026
10070 11:55:50.030440 Removing current net device
10071 11:55:50.030770
10072 11:55:50.037000 Exiting depthcharge with code 4 at timestamp: 70261856
10073 11:55:50.037504
10074 11:55:50.040374 LZMA decompressing kernel-1 to 0x821a6718
10075 11:55:50.040934
10076 11:55:50.043215 LZMA decompressing kernel-1 to 0x40000000
10077 11:55:51.431382
10078 11:55:51.431973 jumping to kernel
10079 11:55:51.434340 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10080 11:55:51.434902 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10081 11:55:51.435316 Setting prompt string to ['Linux version [0-9]']
10082 11:55:51.435693 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 11:55:51.436073 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10084 11:55:51.481253
10085 11:55:51.484719 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10086 11:55:51.488446 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10087 11:55:51.489088 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10088 11:55:51.489490 Setting prompt string to []
10089 11:55:51.489931 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10090 11:55:51.490383 Using line separator: #'\n'#
10091 11:55:51.490789 No login prompt set.
10092 11:55:51.491186 Parsing kernel messages
10093 11:55:51.491531 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10094 11:55:51.492119 [login-action] Waiting for messages, (timeout 00:03:43)
10095 11:55:51.507782 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10096 11:55:51.510880 [ 0.000000] random: crng init done
10097 11:55:51.517398 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10098 11:55:51.521048 [ 0.000000] efi: UEFI not found.
10099 11:55:51.527651 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10100 11:55:51.534374 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10101 11:55:51.544342 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10102 11:55:51.554401 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10103 11:55:51.560683 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10104 11:55:51.567132 [ 0.000000] printk: bootconsole [mtk8250] enabled
10105 11:55:51.573862 [ 0.000000] NUMA: No NUMA configuration found
10106 11:55:51.580699 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000013fffffff]
10107 11:55:51.584206 [ 0.000000] NUMA: NODE_DATA [mem 0x13f7d4a00-0x13f7d6fff]
10108 11:55:51.587738 [ 0.000000] Zone ranges:
10109 11:55:51.593753 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10110 11:55:51.597130 [ 0.000000] DMA32 empty
10111 11:55:51.604080 [ 0.000000] Normal [mem 0x0000000100000000-0x000000013fffffff]
10112 11:55:51.607276 [ 0.000000] Movable zone start for each node
10113 11:55:51.610181 [ 0.000000] Early memory node ranges
10114 11:55:51.616717 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10115 11:55:51.623779 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10116 11:55:51.630081 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10117 11:55:51.636752 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10118 11:55:51.643394 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000013fffffff]
10119 11:55:51.649640 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000013fffffff]
10120 11:55:51.679864 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10121 11:55:51.686752 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10122 11:55:51.692987 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10123 11:55:51.696296 [ 0.000000] psci: probing for conduit method from DT.
10124 11:55:51.702975 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10125 11:55:51.706167 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10126 11:55:51.712412 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10127 11:55:51.715693 [ 0.000000] psci: SMC Calling Convention v1.2
10128 11:55:51.722482 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10129 11:55:51.725477 [ 0.000000] Detected VIPT I-cache on CPU0
10130 11:55:51.732842 [ 0.000000] CPU features: detected: GIC system register CPU interface
10131 11:55:51.739058 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10132 11:55:51.745700 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10133 11:55:51.752330 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10134 11:55:51.762252 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10135 11:55:51.768489 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10136 11:55:51.771783 [ 0.000000] alternatives: applying boot alternatives
10137 11:55:51.778569 [ 0.000000] Fallback order for Node 0: 0
10138 11:55:51.785199 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1031424
10139 11:55:51.788790 [ 0.000000] Policy zone: Normal
10140 11:55:51.801522 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10141 11:55:51.811353 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10142 11:55:51.822547 <6>[ 0.000000] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10143 11:55:51.832395 <6>[ 0.000000] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear)
10144 11:55:51.838858 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10145 11:55:51.841981 <6>[ 0.000000] software IO TLB: area num 8.
10146 11:55:51.897844 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10147 11:55:51.978548 <6>[ 0.000000] Memory: 3800096K/4191232K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 358368K reserved, 32768K cma-reserved)
10148 11:55:51.985024 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10149 11:55:51.992292 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10150 11:55:51.995020 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10151 11:55:52.001549 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10152 11:55:52.008282 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10153 11:55:52.011322 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10154 11:55:52.021279 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10155 11:55:52.028255 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10156 11:55:52.034686 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10157 11:55:52.041350 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10158 11:55:52.044357 <6>[ 0.000000] GICv3: 608 SPIs implemented
10159 11:55:52.047518 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10160 11:55:52.054494 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10161 11:55:52.057578 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10162 11:55:52.064531 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10163 11:55:52.077452 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10164 11:55:52.090668 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10165 11:55:52.097406 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10166 11:55:52.105161 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10167 11:55:52.117945 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10168 11:55:52.124769 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10169 11:55:52.131580 <6>[ 0.009228] Console: colour dummy device 80x25
10170 11:55:52.141417 <6>[ 0.013954] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10171 11:55:52.147748 <6>[ 0.024395] pid_max: default: 32768 minimum: 301
10172 11:55:52.151460 <6>[ 0.029267] LSM: Security Framework initializing
10173 11:55:52.158013 <6>[ 0.034181] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10174 11:55:52.167823 <6>[ 0.041836] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear)
10175 11:55:52.174435 <6>[ 0.051103] cblist_init_generic: Setting adjustable number of callback queues.
10176 11:55:52.180731 <6>[ 0.058590] cblist_init_generic: Setting shift to 3 and lim to 1.
10177 11:55:52.191037 <6>[ 0.064927] cblist_init_generic: Setting adjustable number of callback queues.
10178 11:55:52.197501 <6>[ 0.072353] cblist_init_generic: Setting shift to 3 and lim to 1.
10179 11:55:52.201191 <6>[ 0.078790] rcu: Hierarchical SRCU implementation.
10180 11:55:52.207534 <6>[ 0.083805] rcu: Max phase no-delay instances is 1000.
10181 11:55:52.213853 <6>[ 0.090860] EFI services will not be available.
10182 11:55:52.217544 <6>[ 0.095812] smp: Bringing up secondary CPUs ...
10183 11:55:52.225536 <6>[ 0.100883] Detected VIPT I-cache on CPU1
10184 11:55:52.232370 <6>[ 0.100951] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10185 11:55:52.238696 <6>[ 0.100982] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10186 11:55:52.242104 <6>[ 0.101316] Detected VIPT I-cache on CPU2
10187 11:55:52.251977 <6>[ 0.101366] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10188 11:55:52.259072 <6>[ 0.101382] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10189 11:55:52.261526 <6>[ 0.101641] Detected VIPT I-cache on CPU3
10190 11:55:52.268288 <6>[ 0.101686] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10191 11:55:52.274796 <6>[ 0.101702] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10192 11:55:52.281254 <6>[ 0.102005] CPU features: detected: Spectre-v4
10193 11:55:52.284612 <6>[ 0.102011] CPU features: detected: Spectre-BHB
10194 11:55:52.288102 <6>[ 0.102016] Detected PIPT I-cache on CPU4
10195 11:55:52.294726 <6>[ 0.102072] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10196 11:55:52.301342 <6>[ 0.102089] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10197 11:55:52.307673 <6>[ 0.102379] Detected PIPT I-cache on CPU5
10198 11:55:52.314511 <6>[ 0.102441] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10199 11:55:52.321200 <6>[ 0.102457] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10200 11:55:52.324450 <6>[ 0.102734] Detected PIPT I-cache on CPU6
10201 11:55:52.334629 <6>[ 0.102796] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10202 11:55:52.340788 <6>[ 0.102812] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10203 11:55:52.344174 <6>[ 0.103110] Detected PIPT I-cache on CPU7
10204 11:55:52.350661 <6>[ 0.103175] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10205 11:55:52.357377 <6>[ 0.103191] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10206 11:55:52.361022 <6>[ 0.103237] smp: Brought up 1 node, 8 CPUs
10207 11:55:52.366912 <6>[ 0.244519] SMP: Total of 8 processors activated.
10208 11:55:52.373332 <6>[ 0.249439] CPU features: detected: 32-bit EL0 Support
10209 11:55:52.380320 <6>[ 0.254802] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10210 11:55:52.386762 <6>[ 0.263657] CPU features: detected: Common not Private translations
10211 11:55:52.393899 <6>[ 0.270133] CPU features: detected: CRC32 instructions
10212 11:55:52.400125 <6>[ 0.275517] CPU features: detected: RCpc load-acquire (LDAPR)
10213 11:55:52.403269 <6>[ 0.281477] CPU features: detected: LSE atomic instructions
10214 11:55:52.410160 <6>[ 0.287294] CPU features: detected: Privileged Access Never
10215 11:55:52.416567 <6>[ 0.293089] CPU features: detected: RAS Extension Support
10216 11:55:52.423182 <6>[ 0.298698] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10217 11:55:52.426163 <6>[ 0.305919] CPU: All CPU(s) started at EL2
10218 11:55:52.433019 <6>[ 0.310252] alternatives: applying system-wide alternatives
10219 11:55:52.442447 <6>[ 0.320147] devtmpfs: initialized
10220 11:55:52.457201 <6>[ 0.328276] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10221 11:55:52.463511 <6>[ 0.338233] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10222 11:55:52.470202 <6>[ 0.346392] pinctrl core: initialized pinctrl subsystem
10223 11:55:52.473716 <6>[ 0.353055] DMI not present or invalid.
10224 11:55:52.480443 <6>[ 0.357460] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10225 11:55:52.490204 <6>[ 0.364319] DMA: preallocated 512 KiB GFP_KERNEL pool for atomic allocations
10226 11:55:52.496706 <6>[ 0.371763] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10227 11:55:52.506818 <6>[ 0.379853] DMA: preallocated 512 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10228 11:55:52.509602 <6>[ 0.388010] audit: initializing netlink subsys (disabled)
10229 11:55:52.519821 <5>[ 0.393704] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10230 11:55:52.526147 <6>[ 0.394394] thermal_sys: Registered thermal governor 'step_wise'
10231 11:55:52.533008 <6>[ 0.401673] thermal_sys: Registered thermal governor 'power_allocator'
10232 11:55:52.536112 <6>[ 0.407928] cpuidle: using governor menu
10233 11:55:52.543123 <6>[ 0.418886] NET: Registered PF_QIPCRTR protocol family
10234 11:55:52.549117 <6>[ 0.424368] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10235 11:55:52.555856 <6>[ 0.431471] ASID allocator initialised with 32768 entries
10236 11:55:52.559018 <6>[ 0.438012] Serial: AMBA PL011 UART driver
10237 11:55:52.569001 <4>[ 0.446772] Trying to register duplicate clock ID: 134
10238 11:55:52.623237 <6>[ 0.504368] KASLR enabled
10239 11:55:52.637571 <6>[ 0.512029] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10240 11:55:52.644161 <6>[ 0.519043] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10241 11:55:52.650877 <6>[ 0.525532] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10242 11:55:52.657771 <6>[ 0.532537] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10243 11:55:52.663925 <6>[ 0.539024] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10244 11:55:52.670834 <6>[ 0.546030] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10245 11:55:52.677177 <6>[ 0.552516] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10246 11:55:52.684012 <6>[ 0.559523] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10247 11:55:52.687173 <6>[ 0.567025] ACPI: Interpreter disabled.
10248 11:55:52.695931 <6>[ 0.573425] iommu: Default domain type: Translated
10249 11:55:52.702123 <6>[ 0.578537] iommu: DMA domain TLB invalidation policy: strict mode
10250 11:55:52.705455 <5>[ 0.585189] SCSI subsystem initialized
10251 11:55:52.712010 <6>[ 0.589349] usbcore: registered new interface driver usbfs
10252 11:55:52.718969 <6>[ 0.595081] usbcore: registered new interface driver hub
10253 11:55:52.722455 <6>[ 0.600633] usbcore: registered new device driver usb
10254 11:55:52.729206 <6>[ 0.606733] pps_core: LinuxPPS API ver. 1 registered
10255 11:55:52.738653 <6>[ 0.611928] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10256 11:55:52.742129 <6>[ 0.621274] PTP clock support registered
10257 11:55:52.745676 <6>[ 0.625516] EDAC MC: Ver: 3.0.0
10258 11:55:52.752746 <6>[ 0.630627] FPGA manager framework
10259 11:55:52.756409 <6>[ 0.634306] Advanced Linux Sound Architecture Driver Initialized.
10260 11:55:52.759981 <6>[ 0.641068] vgaarb: loaded
10261 11:55:52.766718 <6>[ 0.644227] clocksource: Switched to clocksource arch_sys_counter
10262 11:55:52.772906 <5>[ 0.650658] VFS: Disk quotas dquot_6.6.0
10263 11:55:52.779504 <6>[ 0.654843] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10264 11:55:52.782888 <6>[ 0.662029] pnp: PnP ACPI: disabled
10265 11:55:52.791046 <6>[ 0.668622] NET: Registered PF_INET protocol family
10266 11:55:52.797197 <6>[ 0.673991] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear)
10267 11:55:52.809743 <6>[ 0.683994] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear)
10268 11:55:52.819541 <6>[ 0.692781] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10269 11:55:52.826247 <6>[ 0.700748] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear)
10270 11:55:52.832765 <6>[ 0.709151] TCP bind hash table entries: 32768 (order: 8, 1048576 bytes, linear)
10271 11:55:52.843524 <6>[ 0.717810] TCP: Hash tables configured (established 32768 bind 32768)
10272 11:55:52.850062 <6>[ 0.724655] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear)
10273 11:55:52.856645 <6>[ 0.731672] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear)
10274 11:55:52.863254 <6>[ 0.739183] NET: Registered PF_UNIX/PF_LOCAL protocol family
10275 11:55:52.869818 <6>[ 0.745334] RPC: Registered named UNIX socket transport module.
10276 11:55:52.873146 <6>[ 0.751484] RPC: Registered udp transport module.
10277 11:55:52.879984 <6>[ 0.756418] RPC: Registered tcp transport module.
10278 11:55:52.886443 <6>[ 0.761351] RPC: Registered tcp NFSv4.1 backchannel transport module.
10279 11:55:52.889958 <6>[ 0.768016] PCI: CLS 0 bytes, default 64
10280 11:55:52.893328 <6>[ 0.772412] Unpacking initramfs...
10281 11:55:52.902932 <6>[ 0.776136] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10282 11:55:52.909351 <6>[ 0.784775] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10283 11:55:52.915984 <6>[ 0.793602] kvm [1]: IPA Size Limit: 40 bits
10284 11:55:52.919280 <6>[ 0.798129] kvm [1]: GICv3: no GICV resource entry
10285 11:55:52.925935 <6>[ 0.803150] kvm [1]: disabling GICv2 emulation
10286 11:55:52.932380 <6>[ 0.807833] kvm [1]: GIC system register CPU interface enabled
10287 11:55:52.935768 <6>[ 0.813997] kvm [1]: vgic interrupt IRQ18
10288 11:55:52.939295 <6>[ 0.818358] kvm [1]: VHE mode initialized successfully
10289 11:55:52.947017 <5>[ 0.824694] Initialise system trusted keyrings
10290 11:55:52.953163 <6>[ 0.829519] workingset: timestamp_bits=42 max_order=20 bucket_order=0
10291 11:55:52.961375 <6>[ 0.839504] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10292 11:55:52.967935 <5>[ 0.845899] NFS: Registering the id_resolver key type
10293 11:55:52.971164 <5>[ 0.851203] Key type id_resolver registered
10294 11:55:52.978378 <5>[ 0.855617] Key type id_legacy registered
10295 11:55:52.984429 <6>[ 0.859896] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10296 11:55:52.991732 <6>[ 0.866819] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10297 11:55:52.998224 <6>[ 0.874548] 9p: Installing v9fs 9p2000 file system support
10298 11:55:53.034556 <5>[ 0.912274] Key type asymmetric registered
10299 11:55:53.037927 <5>[ 0.916605] Asymmetric key parser 'x509' registered
10300 11:55:53.047724 <6>[ 0.921743] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10301 11:55:53.050903 <6>[ 0.929358] io scheduler mq-deadline registered
10302 11:55:53.054088 <6>[ 0.934119] io scheduler kyber registered
10303 11:55:53.073250 <6>[ 0.951159] EINJ: ACPI disabled.
10304 11:55:53.105694 <4>[ 0.976822] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10305 11:55:53.115373 <4>[ 0.987446] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10306 11:55:53.130372 <6>[ 1.008129] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10307 11:55:53.138508 <6>[ 1.016106] printk: console [ttyS0] disabled
10308 11:55:53.166220 <6>[ 1.040758] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10309 11:55:53.172695 <6>[ 1.050255] printk: console [ttyS0] enabled
10310 11:55:53.176201 <6>[ 1.050255] printk: console [ttyS0] enabled
10311 11:55:53.183003 <6>[ 1.059150] printk: bootconsole [mtk8250] disabled
10312 11:55:53.186022 <6>[ 1.059150] printk: bootconsole [mtk8250] disabled
10313 11:55:53.192846 <6>[ 1.070418] SuperH (H)SCI(F) driver initialized
10314 11:55:53.196302 <6>[ 1.075698] msm_serial: driver initialized
10315 11:55:53.210180 <6>[ 1.084650] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10316 11:55:53.219798 <6>[ 1.093195] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10317 11:55:53.226893 <6>[ 1.101737] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10318 11:55:53.237199 <6>[ 1.110365] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10319 11:55:53.246665 <6>[ 1.119072] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10320 11:55:53.252835 <6>[ 1.127787] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10321 11:55:53.263505 <6>[ 1.136328] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10322 11:55:53.269396 <6>[ 1.145134] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10323 11:55:53.279314 <6>[ 1.153678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10324 11:55:53.291456 <6>[ 1.169118] loop: module loaded
10325 11:55:53.298256 <6>[ 1.175050] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10326 11:55:53.320209 <4>[ 1.198148] mtk-pmic-keys: Failed to locate of_node [id: -1]
10327 11:55:53.327319 <6>[ 1.205040] megasas: 07.719.03.00-rc1
10328 11:55:53.336859 <6>[ 1.214595] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10329 11:55:53.346120 <6>[ 1.223598] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10330 11:55:53.362567 <6>[ 1.240178] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10331 11:55:53.418507 <6>[ 1.290055] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.5.120/cr50_v2.94_mp.81-9de2b2
10332 11:55:55.296781 <6>[ 3.174874] Freeing initrd memory: 55108K
10333 11:55:55.306751 <6>[ 3.185316] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10334 11:55:55.317488 <6>[ 3.196074] tun: Universal TUN/TAP device driver, 1.6
10335 11:55:55.321192 <6>[ 3.202138] thunder_xcv, ver 1.0
10336 11:55:55.324544 <6>[ 3.205643] thunder_bgx, ver 1.0
10337 11:55:55.327746 <6>[ 3.209151] nicpf, ver 1.0
10338 11:55:55.338421 <6>[ 3.213166] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10339 11:55:55.341643 <6>[ 3.220642] hns3: Copyright (c) 2017 Huawei Corporation.
10340 11:55:55.348491 <6>[ 3.226232] hclge is initializing
10341 11:55:55.352042 <6>[ 3.229806] e1000: Intel(R) PRO/1000 Network Driver
10342 11:55:55.358082 <6>[ 3.234935] e1000: Copyright (c) 1999-2006 Intel Corporation.
10343 11:55:55.361573 <6>[ 3.240947] e1000e: Intel(R) PRO/1000 Network Driver
10344 11:55:55.368352 <6>[ 3.246162] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10345 11:55:55.374834 <6>[ 3.252346] igb: Intel(R) Gigabit Ethernet Network Driver
10346 11:55:55.381359 <6>[ 3.257995] igb: Copyright (c) 2007-2014 Intel Corporation.
10347 11:55:55.388079 <6>[ 3.263830] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10348 11:55:55.394526 <6>[ 3.270347] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10349 11:55:55.398051 <6>[ 3.276812] sky2: driver version 1.30
10350 11:55:55.404743 <6>[ 3.281814] VFIO - User Level meta-driver version: 0.3
10351 11:55:55.412071 <6>[ 3.290093] usbcore: registered new interface driver usb-storage
10352 11:55:55.418810 <6>[ 3.296534] usbcore: registered new device driver onboard-usb-hub
10353 11:55:55.427305 <6>[ 3.305687] mt6397-rtc mt6359-rtc: registered as rtc0
10354 11:55:55.437724 <6>[ 3.311153] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:55:56 UTC (1700740556)
10355 11:55:55.440727 <6>[ 3.320723] i2c_dev: i2c /dev entries driver
10356 11:55:55.457663 <6>[ 3.332416] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10357 11:55:55.477291 <6>[ 3.355385] cpu cpu0: EM: created perf domain
10358 11:55:55.480636 <6>[ 3.360287] cpu cpu4: EM: created perf domain
10359 11:55:55.487660 <6>[ 3.365799] sdhci: Secure Digital Host Controller Interface driver
10360 11:55:55.494254 <6>[ 3.372234] sdhci: Copyright(c) Pierre Ossman
10361 11:55:55.501307 <6>[ 3.377162] Synopsys Designware Multimedia Card Interface Driver
10362 11:55:55.507735 <6>[ 3.383760] sdhci-pltfm: SDHCI platform and OF driver helper
10363 11:55:55.510802 <6>[ 3.383916] mmc0: CQHCI version 5.10
10364 11:55:55.517700 <6>[ 3.393711] ledtrig-cpu: registered to indicate activity on CPUs
10365 11:55:55.524145 <6>[ 3.400602] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10366 11:55:55.530772 <6>[ 3.407623] usbcore: registered new interface driver usbhid
10367 11:55:55.534131 <6>[ 3.413447] usbhid: USB HID core driver
10368 11:55:55.540727 <6>[ 3.417636] spi_master spi0: will run message pump with realtime priority
10369 11:55:55.586856 <6>[ 3.458459] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10370 11:55:55.606166 <6>[ 3.473883] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10371 11:55:55.609332 <6>[ 3.487419] mmc0: Command Queue Engine enabled
10372 11:55:55.616195 <6>[ 3.489467] cros-ec-spi spi0.0: Chrome EC device registered
10373 11:55:55.623035 <6>[ 3.492166] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10374 11:55:55.626081 <6>[ 3.505319] mmcblk0: mmc0:0001 DA4064 58.2 GiB
10375 11:55:55.636944 <6>[ 3.511456] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10376 11:55:55.643326 <6>[ 3.515634] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10377 11:55:55.649661 <6>[ 3.521727] NET: Registered PF_PACKET protocol family
10378 11:55:55.652912 <6>[ 3.527969] mmcblk0boot0: mmc0:0001 DA4064 4.00 MiB
10379 11:55:55.659808 <6>[ 3.532076] 9pnet: Installing 9P2000 support
10380 11:55:55.663060 <6>[ 3.537921] mmcblk0boot1: mmc0:0001 DA4064 4.00 MiB
10381 11:55:55.669715 <5>[ 3.541773] Key type dns_resolver registered
10382 11:55:55.676332 <6>[ 3.547626] mmcblk0rpmb: mmc0:0001 DA4064 16.0 MiB, chardev (507:0)
10383 11:55:55.679676 <6>[ 3.551963] registered taskstats version 1
10384 11:55:55.682949 <5>[ 3.562375] Loading compiled-in X.509 certificates
10385 11:55:55.712122 <4>[ 3.583697] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10386 11:55:55.721849 <4>[ 3.594431] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10387 11:55:55.728554 <3>[ 3.604956] debugfs: File 'uA_load' in directory '/' already present!
10388 11:55:55.735428 <3>[ 3.611655] debugfs: File 'min_uV' in directory '/' already present!
10389 11:55:55.741856 <3>[ 3.618262] debugfs: File 'max_uV' in directory '/' already present!
10390 11:55:55.748411 <3>[ 3.624928] debugfs: File 'constraint_flags' in directory '/' already present!
10391 11:55:55.759507 <3>[ 3.634462] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10392 11:55:55.769836 <6>[ 3.647617] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10393 11:55:55.776374 <6>[ 3.654443] xhci-mtk 11200000.usb: xHCI Host Controller
10394 11:55:55.782683 <6>[ 3.659942] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10395 11:55:55.792854 <6>[ 3.667802] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10396 11:55:55.799874 <6>[ 3.677248] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10397 11:55:55.806307 <6>[ 3.683323] xhci-mtk 11200000.usb: xHCI Host Controller
10398 11:55:55.812917 <6>[ 3.688803] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10399 11:55:55.819925 <6>[ 3.696452] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10400 11:55:55.826322 <6>[ 3.704152] hub 1-0:1.0: USB hub found
10401 11:55:55.829626 <6>[ 3.708170] hub 1-0:1.0: 1 port detected
10402 11:55:55.836382 <6>[ 3.712453] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10403 11:55:55.843051 <6>[ 3.721024] hub 2-0:1.0: USB hub found
10404 11:55:55.846619 <6>[ 3.725032] hub 2-0:1.0: 1 port detected
10405 11:55:55.854429 <6>[ 3.732900] mtk-msdc 11f70000.mmc: Got CD GPIO
10406 11:55:55.865782 <6>[ 3.740660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10407 11:55:55.872577 <6>[ 3.748686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10408 11:55:55.882360 <4>[ 3.756609] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10409 11:55:55.892403 <6>[ 3.766132] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10410 11:55:55.898836 <6>[ 3.774207] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10411 11:55:55.905407 <6>[ 3.782236] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10412 11:55:55.916090 <6>[ 3.790175] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10413 11:55:55.922116 <6>[ 3.797993] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10414 11:55:55.932198 <6>[ 3.805810] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10415 11:55:55.941817 <6>[ 3.816079] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10416 11:55:55.948832 <6>[ 3.824443] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10417 11:55:55.958210 <6>[ 3.832790] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10418 11:55:55.965143 <6>[ 3.841129] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10419 11:55:55.974964 <6>[ 3.849467] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10420 11:55:55.981769 <6>[ 3.857805] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10421 11:55:55.991429 <6>[ 3.866142] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10422 11:55:56.001201 <6>[ 3.874480] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10423 11:55:56.008031 <6>[ 3.882818] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10424 11:55:56.017734 <6>[ 3.891181] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10425 11:55:56.024694 <6>[ 3.899520] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10426 11:55:56.034404 <6>[ 3.907858] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10427 11:55:56.040777 <6>[ 3.916195] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10428 11:55:56.051133 <6>[ 3.924534] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10429 11:55:56.057134 <6>[ 3.932871] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10430 11:55:56.064101 <6>[ 3.941623] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10431 11:55:56.070798 <6>[ 3.948575] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10432 11:55:56.077475 <6>[ 3.955436] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10433 11:55:56.087607 <6>[ 3.962285] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10434 11:55:56.093793 <6>[ 3.969282] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10435 11:55:56.100798 <6>[ 3.976142] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10436 11:55:56.110527 <6>[ 3.985276] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10437 11:55:56.120335 <6>[ 3.994395] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10438 11:55:56.130211 <6>[ 4.003688] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10439 11:55:56.140407 <6>[ 4.013159] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10440 11:55:56.150321 <6>[ 4.022626] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10441 11:55:56.156617 <6>[ 4.031745] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10442 11:55:56.166575 <6>[ 4.041211] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10443 11:55:56.176663 <6>[ 4.050330] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10444 11:55:56.186564 <6>[ 4.059623] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10445 11:55:56.196500 <6>[ 4.069783] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10446 11:55:56.206632 <6>[ 4.081341] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10447 11:55:56.261388 <6>[ 4.136493] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10448 11:55:56.416160 <6>[ 4.294285] hub 1-1:1.0: USB hub found
10449 11:55:56.419522 <6>[ 4.298815] hub 1-1:1.0: 4 ports detected
10450 11:55:56.429283 <6>[ 4.307627] hub 1-1:1.0: USB hub found
10451 11:55:56.433150 <6>[ 4.312001] hub 1-1:1.0: 4 ports detected
10452 11:55:56.541777 <6>[ 4.416831] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10453 11:55:56.568214 <6>[ 4.446296] hub 2-1:1.0: USB hub found
10454 11:55:56.571303 <6>[ 4.450799] hub 2-1:1.0: 3 ports detected
10455 11:55:56.580871 <6>[ 4.458933] hub 2-1:1.0: USB hub found
10456 11:55:56.584074 <6>[ 4.463417] hub 2-1:1.0: 3 ports detected
10457 11:55:56.757334 <6>[ 4.632536] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10458 11:55:56.889872 <6>[ 4.768173] hub 1-1.4:1.0: USB hub found
10459 11:55:56.893289 <6>[ 4.772840] hub 1-1.4:1.0: 2 ports detected
10460 11:55:56.902135 <6>[ 4.779928] hub 1-1.4:1.0: USB hub found
10461 11:55:56.904734 <6>[ 4.784487] hub 1-1.4:1.0: 2 ports detected
10462 11:55:56.973640 <6>[ 4.848671] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10463 11:55:57.201616 <6>[ 5.076540] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10464 11:55:57.393001 <6>[ 5.268513] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10465 11:56:08.482617 <6>[ 16.365531] ALSA device list:
10466 11:56:08.489090 <6>[ 16.368818] No soundcards found.
10467 11:56:08.497032 <6>[ 16.376618] Freeing unused kernel memory: 8384K
10468 11:56:08.500391 <6>[ 16.381600] Run /init as init process
10469 11:56:08.546814 <6>[ 16.426301] NET: Registered PF_INET6 protocol family
10470 11:56:08.550306 <6>[ 16.432290] Segment Routing with IPv6
10471 11:56:08.556502 <6>[ 16.436227] In-situ OAM (IOAM) with IPv6
10472 11:56:08.590320 <30>[ 16.450101] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10473 11:56:08.593493 <30>[ 16.473850] systemd[1]: Detected architecture arm64.
10474 11:56:08.593962
10475 11:56:08.600663 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10476 11:56:08.601224
10477 11:56:08.612941 <30>[ 16.492597] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10478 11:56:08.738085 <30>[ 16.614483] systemd[1]: Queued start job for default target Graphical Interface.
10479 11:56:08.798113 <30>[ 16.677484] systemd[1]: Created slice system-getty.slice.
10480 11:56:08.804467 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10481 11:56:08.821250 <30>[ 16.701139] systemd[1]: Created slice system-modprobe.slice.
10482 11:56:08.828049 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10483 11:56:08.845662 <30>[ 16.725275] systemd[1]: Created slice system-serial\x2dgetty.slice.
10484 11:56:08.855471 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10485 11:56:08.869326 <30>[ 16.749081] systemd[1]: Created slice User and Session Slice.
10486 11:56:08.875954 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10487 11:56:08.897130 <30>[ 16.773321] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10488 11:56:08.906909 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10489 11:56:08.924957 <30>[ 16.801256] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10490 11:56:08.931558 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10491 11:56:08.956195 <30>[ 16.829025] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10492 11:56:08.962495 <30>[ 16.841265] systemd[1]: Reached target Local Encrypted Volumes.
10493 11:56:08.968967 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10494 11:56:08.985471 <30>[ 16.864995] systemd[1]: Reached target Paths.
10495 11:56:08.988732 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10496 11:56:09.004861 <30>[ 16.884506] systemd[1]: Reached target Remote File Systems.
10497 11:56:09.011638 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10498 11:56:09.025138 <30>[ 16.904479] systemd[1]: Reached target Slices.
10499 11:56:09.028491 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10500 11:56:09.044796 <30>[ 16.924527] systemd[1]: Reached target Swap.
10501 11:56:09.048371 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10502 11:56:09.068304 <30>[ 16.945013] systemd[1]: Listening on initctl Compatibility Named Pipe.
10503 11:56:09.075082 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10504 11:56:09.081999 <30>[ 16.960181] systemd[1]: Listening on Journal Audit Socket.
10505 11:56:09.088626 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10506 11:56:09.101502 <30>[ 16.980989] systemd[1]: Listening on Journal Socket (/dev/log).
10507 11:56:09.108023 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10508 11:56:09.125967 <30>[ 17.005708] systemd[1]: Listening on Journal Socket.
10509 11:56:09.133153 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10510 11:56:09.145633 <30>[ 17.025071] systemd[1]: Listening on udev Control Socket.
10511 11:56:09.152257 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10512 11:56:09.169806 <30>[ 17.049513] systemd[1]: Listening on udev Kernel Socket.
10513 11:56:09.176165 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10514 11:56:09.217008 <30>[ 17.096615] systemd[1]: Mounting Huge Pages File System...
10515 11:56:09.223700 Mounting [0;1;39mHuge Pages File System[0m...
10516 11:56:09.241022 <30>[ 17.120503] systemd[1]: Mounting POSIX Message Queue File System...
10517 11:56:09.247587 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10518 11:56:09.268552 <30>[ 17.148453] systemd[1]: Mounting Kernel Debug File System...
10519 11:56:09.275877 Mounting [0;1;39mKernel Debug File System[0m...
10520 11:56:09.292392 <30>[ 17.168851] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10521 11:56:09.332921 <30>[ 17.208953] systemd[1]: Starting Create list of static device nodes for the current kernel...
10522 11:56:09.339743 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10523 11:56:09.362183 <30>[ 17.240972] systemd[1]: Starting Load Kernel Module configfs...
10524 11:56:09.367751 Starting [0;1;39mLoad Kernel Module configfs[0m...
10525 11:56:09.385048 <30>[ 17.264667] systemd[1]: Starting Load Kernel Module drm...
10526 11:56:09.391611 Starting [0;1;39mLoad Kernel Module drm[0m...
10527 11:56:09.408316 <30>[ 17.284735] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10528 11:56:09.422748 <30>[ 17.302346] systemd[1]: Starting Journal Service...
10529 11:56:09.426231 Starting [0;1;39mJournal Service[0m...
10530 11:56:09.443583 <30>[ 17.323117] systemd[1]: Starting Load Kernel Modules...
10531 11:56:09.449935 Starting [0;1;39mLoad Kernel Modules[0m...
10532 11:56:09.472832 <30>[ 17.348924] systemd[1]: Starting Remount Root and Kernel File Systems...
10533 11:56:09.478908 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10534 11:56:09.495533 <30>[ 17.375281] systemd[1]: Starting Coldplug All udev Devices...
10535 11:56:09.502277 Starting [0;1;39mColdplug All udev Devices[0m...
10536 11:56:09.520241 <30>[ 17.400016] systemd[1]: Started Journal Service.
10537 11:56:09.526685 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10538 11:56:09.543879 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10539 11:56:09.562208 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10540 11:56:09.577408 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10541 11:56:09.597351 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10542 11:56:09.615690 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10543 11:56:09.635485 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10544 11:56:09.654907 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10545 11:56:09.674597 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10546 11:56:09.688998 See 'systemctl status systemd-remount-fs.service' for details.
10547 11:56:09.730411 Mounting [0;1;39mKernel Configuration File System[0m...
10548 11:56:09.748107 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10549 11:56:09.760654 <46>[ 17.636910] systemd-journald[178]: Received client request to flush runtime journal.
10550 11:56:09.769112 Starting [0;1;39mLoad/Save Random Seed[0m...
10551 11:56:09.789476 Starting [0;1;39mApply Kernel Variables[0m...
10552 11:56:09.809430 Starting [0;1;39mCreate System Users[0m...
10553 11:56:09.827590 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10554 11:56:09.847420 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10555 11:56:09.870084 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10556 11:56:09.886741 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10557 11:56:09.902729 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10558 11:56:09.918567 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10559 11:56:09.961528 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10560 11:56:09.980993 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10561 11:56:09.993397 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10562 11:56:10.012749 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10563 11:56:10.065584 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10564 11:56:10.092197 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10565 11:56:10.114928 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10566 11:56:10.139280 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10567 11:56:10.199996 Starting [0;1;39mNetwork Time Synchronization[0m...
10568 11:56:10.223578 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10569 11:56:10.250242 <6>[ 18.126813] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10570 11:56:10.261489 <6>[ 18.141116] remoteproc remoteproc0: scp is available
10571 11:56:10.271171 [[0;32m OK [0m] Finished [0;1;39mUpdate UTM<6>[ 18.150846] remoteproc remoteproc0: powering up scp
10572 11:56:10.281066 P about System B<6>[ 18.156420] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10573 11:56:10.287881 <6>[ 18.166257] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10574 11:56:10.288444 oot/Shutdown[0m.
10575 11:56:10.306150 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10576 11:56:10.333067 <6>[ 18.209460] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10577 11:56:10.343204 <6>[ 18.217649] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10578 11:56:10.349745 <3>[ 18.220863] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10579 11:56:10.359790 <6>[ 18.226392] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10580 11:56:10.369398 [[0;32m OK [<3>[ 18.244175] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10581 11:56:10.379709 0m] Found device<3>[ 18.253493] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10582 11:56:10.385903 [0;1;39m/dev/t<4>[ 18.263604] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10583 11:56:10.386468 tyS0[0m.
10584 11:56:10.396024 <3>[ 18.264521] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10585 11:56:10.402643 <3>[ 18.280746] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10586 11:56:10.409230 <6>[ 18.281866] usbcore: registered new interface driver r8152
10587 11:56:10.419237 <3>[ 18.288839] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10588 11:56:10.425795 <3>[ 18.288848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10589 11:56:10.435635 <3>[ 18.288851] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10590 11:56:10.442381 <4>[ 18.290328] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10591 11:56:10.448917 <6>[ 18.296462] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10592 11:56:10.455620 <6>[ 18.302816] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10593 11:56:10.465304 <6>[ 18.310847] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10594 11:56:10.472074 <6>[ 18.310860] remoteproc remoteproc0: remote processor scp is now up
10595 11:56:10.478796 <3>[ 18.313142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10596 11:56:10.485396 <6>[ 18.317142] mc: Linux media interface: v0.10
10597 11:56:10.489109 <6>[ 18.317230] Bluetooth: Core ver 2.22
10598 11:56:10.492282 <6>[ 18.317675] NET: Registered PF_BLUETOOTH protocol family
10599 11:56:10.498892 <6>[ 18.317680] Bluetooth: HCI device and connection manager initialized
10600 11:56:10.505486 <6>[ 18.317706] Bluetooth: HCI socket layer initialized
10601 11:56:10.508826 <6>[ 18.317714] Bluetooth: L2CAP socket layer initialized
10602 11:56:10.515565 <6>[ 18.317730] Bluetooth: SCO socket layer initialized
10603 11:56:10.525439 <4>[ 18.328599] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10604 11:56:10.529311 <4>[ 18.328599] Fallback method does not support PEC.
10605 11:56:10.536054 <6>[ 18.336345] videodev: Linux video capture interface: v2.00
10606 11:56:10.542878 <3>[ 18.340707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10607 11:56:10.549672 <3>[ 18.340756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10608 11:56:10.559646 <3>[ 18.340761] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10609 11:56:10.565666 <3>[ 18.340829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10610 11:56:10.576091 <3>[ 18.340832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10611 11:56:10.582921 <3>[ 18.340835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10612 11:56:10.592231 <3>[ 18.340841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10613 11:56:10.598965 <3>[ 18.340843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10614 11:56:10.609127 <3>[ 18.340862] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10615 11:56:10.615651 <6>[ 18.349950] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10616 11:56:10.623135 <3>[ 18.374830] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10617 11:56:10.629733 <6>[ 18.378127] pci_bus 0000:00: root bus resource [bus 00-ff]
10618 11:56:10.636813 <3>[ 18.419209] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10619 11:56:10.646615 <6>[ 18.419777] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10620 11:56:10.652880 <3>[ 18.419983] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10621 11:56:10.659274 <6>[ 18.420611] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10622 11:56:10.666422 <6>[ 18.420909] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10623 11:56:10.677202 <6>[ 18.422727] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10624 11:56:10.684314 <6>[ 18.427215] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10625 11:56:10.695091 <6>[ 18.432901] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10626 11:56:10.704743 <6>[ 18.435864] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10627 11:56:10.715168 <6>[ 18.444895] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10628 11:56:10.721743 <6>[ 18.452156] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10629 11:56:10.731325 <4>[ 18.465504] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10630 11:56:10.738885 <6>[ 18.469490] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10631 11:56:10.745825 <4>[ 18.476551] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10632 11:56:10.748874 <6>[ 18.484633] pci 0000:00:00.0: supports D1 D2
10633 11:56:10.755266 <6>[ 18.485328] usbcore: registered new interface driver cdc_ether
10634 11:56:10.761898 <6>[ 18.499921] usbcore: registered new interface driver r8153_ecm
10635 11:56:10.768557 <6>[ 18.508262] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10636 11:56:10.778694 <6>[ 18.510191] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10637 11:56:10.785228 <3>[ 18.512957] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10638 11:56:10.792029 <6>[ 18.523942] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10639 11:56:10.798287 <6>[ 18.524820] usbcore: registered new interface driver btusb
10640 11:56:10.805285 <6>[ 18.530066] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10641 11:56:10.815787 <4>[ 18.538407] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10642 11:56:10.829214 <6>[ 18.538855] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10643 11:56:10.835869 <6>[ 18.538975] usbcore: registered new interface driver uvcvideo
10644 11:56:10.842218 <6>[ 18.544742] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10645 11:56:10.849207 <6>[ 18.544766] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10646 11:56:10.855734 <3>[ 18.553049] Bluetooth: hci0: Failed to load firmware file (-2)
10647 11:56:10.862360 <6>[ 18.553739] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10648 11:56:10.865995 <6>[ 18.556355] r8152 2-1.3:1.0 eth0: v1.12.13
10649 11:56:10.872854 <6>[ 18.561278] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10650 11:56:10.879490 <6>[ 18.563992] r8152 2-1.3:1.0 enx00e04c6803bd: renamed from eth0
10651 11:56:10.889267 <3>[ 18.564608] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10652 11:56:10.897320 <3>[ 18.565317] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10653 11:56:10.904089 <3>[ 18.570570] Bluetooth: hci0: Failed to set up firmware (-2)
10654 11:56:10.909983 <3>[ 18.578033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10655 11:56:10.917493 <6>[ 18.580740] pci 0000:01:00.0: supports D1 D2
10656 11:56:10.927783 <4>[ 18.590557] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10657 11:56:10.934159 <6>[ 18.599569] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10658 11:56:10.940847 <6>[ 18.612403] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10659 11:56:10.947503 <3>[ 18.624744] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10660 11:56:10.957448 <6>[ 18.630434] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10661 11:56:10.967328 <3>[ 18.663706] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10662 11:56:10.973913 <6>[ 18.670990] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10663 11:56:10.980783 <6>[ 18.670999] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10664 11:56:10.990007 <6>[ 18.671011] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10665 11:56:10.997279 <3>[ 18.701178] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10666 11:56:11.006918 <6>[ 18.712960] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10667 11:56:11.010316 <6>[ 18.712971] pci 0000:00:00.0: PCI bridge to [bus 01]
10668 11:56:11.020451 <6>[ 18.896736] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10669 11:56:11.026898 <6>[ 18.896884] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10670 11:56:11.033274 [[0;32m OK [<6>[ 18.911739] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10671 11:56:11.039957 0m] Created slic<6>[ 18.919482] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10672 11:56:11.046596 e [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10673 11:56:11.060391 <5>[ 18.937023] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10674 11:56:11.069243 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10675 11:56:11.082063 <5>[ 18.958691] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10676 11:56:11.088758 <4>[ 18.965601] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10677 11:56:11.095657 <6>[ 18.974505] cfg80211: failed to load regulatory.db
10678 11:56:11.101667 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10679 11:56:11.144595 <6>[ 19.020919] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10680 11:56:11.150565 <6>[ 19.028557] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10681 11:56:11.161447 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10682 11:56:11.175336 <6>[ 19.055299] mt7921e 0000:01:00.0: ASIC revision: 79610010
10683 11:56:11.187081 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10684 11:56:11.282658 <4>[ 19.155916] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10685 11:56:11.328190 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10686 11:56:11.344844 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10687 11:56:11.364421 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10688 11:56:11.380157 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10689 11:56:11.383331 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10690 11:56:11.404213 <4>[ 19.277582] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10691 11:56:11.410959 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10692 11:56:11.425152 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10693 11:56:11.445159 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10694 11:56:11.464432 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10695 11:56:11.506204 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10696 11:56:11.531317 <4>[ 19.404610] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10697 11:56:11.547184 Starting [0;1;39mUser Login Management[0m...
10698 11:56:11.565812 Starting [0;1;39mPermit User Sessions[0m...
10699 11:56:11.583567 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10700 11:56:11.608891 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10701 11:56:11.629765 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10702 11:56:11.649781 <4>[ 19.523270] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10703 11:56:11.656959 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10704 11:56:11.673843 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10705 11:56:11.690366 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10706 11:56:11.706520 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10707 11:56:11.722566 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10708 11:56:11.741245 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10709 11:56:11.772736 <4>[ 19.645792] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10710 11:56:11.814721 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10711 11:56:11.850508 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10712 11:56:11.890018 <4>[ 19.763336] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10713 11:56:11.907035
10714 11:56:11.907593
10715 11:56:11.910573 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10716 11:56:11.911133
10717 11:56:11.913463 debian-bullseye-arm64 login: root (automatic login)
10718 11:56:11.913971
10719 11:56:11.914335
10720 11:56:11.940698 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
10721 11:56:11.941271
10722 11:56:11.947698 The programs included with the Debian GNU/Linux system are free software;
10723 11:56:11.954065 the exact distribution terms for each program are described in the
10724 11:56:11.957241 individual files in /usr/share/doc/*/copyright.
10725 11:56:11.957702
10726 11:56:11.963844 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10727 11:56:11.966879 permitted by applicable law.
10728 11:56:11.968273 Matched prompt #10: / #
10730 11:56:11.969402 Setting prompt string to ['/ #']
10731 11:56:11.969862 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10733 11:56:11.971078 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
10734 11:56:11.971543 start: 2.2.6 expect-shell-connection (timeout 00:03:22) [common]
10735 11:56:11.971920 Setting prompt string to ['/ #']
10736 11:56:11.972261 Forcing a shell prompt, looking for ['/ #']
10738 11:56:12.023264 / #
10739 11:56:12.023909 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10740 11:56:12.024376 Waiting using forced prompt support (timeout 00:02:30)
10741 11:56:12.024967 <4>[ 19.889315] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10742 11:56:12.029769
10743 11:56:12.030706 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10744 11:56:12.031215 start: 2.2.7 export-device-env (timeout 00:03:22) [common]
10745 11:56:12.031781 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10746 11:56:12.032254 end: 2.2 depthcharge-retry (duration 00:01:38) [common]
10747 11:56:12.032752 end: 2 depthcharge-action (duration 00:01:38) [common]
10748 11:56:12.033247 start: 3 lava-test-retry (timeout 00:08:00) [common]
10749 11:56:12.033708 start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10750 11:56:12.034099 Using namespace: common
10752 11:56:12.135297 / # #
10753 11:56:12.135962 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10754 11:56:12.139381 #<4>[ 20.012886] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10755 11:56:12.139968
10756 11:56:12.181569 Using /lava-12066548
10758 11:56:12.283149 / # export SHELL=/bin/sh
10759 11:56:12.284094 export SHELL=/bin/sh<4>[ 20.132664] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 11:56:12.289332
10762 11:56:12.391393 / # . /lava-12066548/environment
10763 11:56:12.391689 . /lava-12066548/environment<4>[ 20.252588] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10764 11:56:12.396729
10766 11:56:12.497703 / # /lava-12066548/bin/lava-test-runner /lava-12066548/0
10767 11:56:12.498336 Test shell timeout: 10s (minimum of the action and connection timeout)
10768 11:56:12.499980 /lava-12066548/bin/lava-test-runner /lava-12066548/0<3>[ 20.370556] mt7921e 0000:01:00.0: hardware init failed
10769 11:56:12.503970
10770 11:56:12.548969 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.407969] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12066548_1.5.2.3.1>
10771 11:56:12.549594 diatek
10772 11:56:12.549962 + cd /lava-12066548/0/tests/0_igt-kms-mediatek
10773 11:56:12.550309 + cat uuid
10774 11:56:12.550931 Received signal: <STARTRUN> 0_igt-kms-mediatek 12066548_1.5.2.3.1
10775 11:56:12.551315 Starting test lava.0_igt-kms-mediatek (12066548_1.5.2.3.1)
10776 11:56:12.551740 Skipping test definition patterns.
10777 11:56:12.552261 + UUID=12066548_1.5.2.3.1
10778 11:56:12.552658 + set +x
10779 11:56:12.562398 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_<8>[ 20.443409] <LAVA_SIGNAL_TESTSET START core_auth>
10780 11:56:12.563259 Received signal: <TESTSET> START core_auth
10781 11:56:12.563660 Starting test_set core_auth
10782 11:56:12.565620 vblank
10783 11:56:12.592864 <14>[ 20.472629] [IGT] core_auth: executing
10784 11:56:12.599338 IGT-Version: 1.2<14>[ 20.477052] [IGT] core_auth: starting subtest getclient-simple
10785 11:56:12.609430 7.1-g621c2d3 (aa<14>[ 20.484822] [IGT] core_auth: finished subtest getclient-simple, SUCCESS
10786 11:56:12.612706 rch64) (Linux: 6<14>[ 20.492998] [IGT] core_auth: exiting, ret=0
10787 11:56:12.615854 .1.62-cip9 aarch64)
10788 11:56:12.619033 Starting subtest: getclient-simple
10789 11:56:12.622456 Opened device: /dev/dri/card0
10790 11:56:12.629411 [1mSubt<8>[ 20.505811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
10791 11:56:12.630266 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
10793 11:56:12.632115 est getclient-simple: SUCCESS (0.000s)[0m
10794 11:56:12.645690 <14>[ 20.525740] [IGT] core_auth: executing
10795 11:56:12.652431 IGT-Version: 1.2<14>[ 20.530039] [IGT] core_auth: starting subtest getclient-master-drop
10796 11:56:12.662277 7.1-g621c2d3 (aa<14>[ 20.538106] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS
10797 11:56:12.665624 <14>[ 20.546857] [IGT] core_auth: exiting, ret=0
10798 11:56:12.668629 rch64) (Linux: 6.1.62-cip9 aarch64)
10799 11:56:12.672308 Starting subtest: getclient-master-drop
10800 11:56:12.682434 Op<8>[ 20.557452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
10801 11:56:12.682992 ened device: /dev/dri/card0
10802 11:56:12.683643 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
10804 11:56:12.688546 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
10805 11:56:12.697947 <14>[ 20.578236] [IGT] core_auth: executing
10806 11:56:12.704633 IGT-Version: 1.2<14>[ 20.582642] [IGT] core_auth: starting subtest basic-auth
10807 11:56:12.711328 7.1-g621c2d3 (aa<14>[ 20.589628] [IGT] core_auth: finished subtest basic-auth, SUCCESS
10808 11:56:12.717617 rch64) (Linux: 6<14>[ 20.597547] [IGT] core_auth: exiting, ret=0
10809 11:56:12.721126 .1.62-cip9 aarch64)
10810 11:56:12.724480 Opened device: /dev/dri/card0
10811 11:56:12.731281 Starting subtest: basic-auth<8>[ 20.609913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
10812 11:56:12.731837
10813 11:56:12.732482 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
10815 11:56:12.737482 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
10816 11:56:12.749005 <14>[ 20.629272] [IGT] core_auth: executing
10817 11:56:12.755970 IGT-Version: 1.2<14>[ 20.633773] [IGT] core_auth: starting subtest many-magics
10818 11:56:12.759289 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10819 11:56:12.768891 Opened devi<14>[ 20.646339] [IGT] core_auth: finished subtest many-magics, SUCCESS
10820 11:56:12.772030 <14>[ 20.652925] [IGT] core_auth: exiting, ret=0
10821 11:56:12.775566 ce: /dev/dri/card0
10822 11:56:12.776135 Starting subtest: many-magics
10823 11:56:12.785287 Reopening device failed after<8>[ 20.664249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
10824 11:56:12.786153 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
10826 11:56:12.788708 1020 opens
10827 11:56:12.791838 [1mSubtest many-ma<8>[ 20.673142] <LAVA_SIGNAL_TESTSET STOP>
10828 11:56:12.792603 Received signal: <TESTSET> STOP
10829 11:56:12.793034 Closing test_set core_auth
10830 11:56:12.795489 gics: SUCCESS (0.006s)[0m
10831 11:56:12.839714 <14>[ 20.719654] [IGT] core_getclient: executing
10832 11:56:12.846309 IGT-Version: 1.2<14>[ 20.724876] [IGT] core_getclient: exiting, ret=0
10833 11:56:12.849584 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10834 11:56:12.859404 Opened device: /dev/dri/car<8>[ 20.737247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
10835 11:56:12.859986 d0
10836 11:56:12.860765 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
10838 11:56:12.862575 SUCCESS (0.006s)
10839 11:56:12.899699 <14>[ 20.779794] [IGT] core_getstats: executing
10840 11:56:12.906553 IGT-Version: 1.2<14>[ 20.784600] [IGT] core_getstats: exiting, ret=0
10841 11:56:12.909466 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10842 11:56:12.919887 Opened device: /dev/dri/car<8>[ 20.797036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
10843 11:56:12.920465 d0
10844 11:56:12.921290 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
10846 11:56:12.922976 SUCCESS (0.006s)
10847 11:56:12.959585 <14>[ 20.839334] [IGT] core_getversion: executing
10848 11:56:12.966075 IGT-Version: 1.2<14>[ 20.844294] [IGT] core_getversion: exiting, ret=0
10849 11:56:12.969182 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10850 11:56:12.979018 Opened devi<8>[ 20.855709] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
10851 11:56:12.979602 ce: /dev/dri/card0
10852 11:56:12.980372 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
10854 11:56:12.982166 SUCCESS (0.006s)
10855 11:56:13.018339 <14>[ 20.898276] [IGT] core_setmaster_vs_auth: executing
10856 11:56:13.025133 IGT-Version: 1.2<14>[ 20.903893] [IGT] core_setmaster_vs_auth: exiting, ret=0
10857 11:56:13.031473 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10858 11:56:13.032083 Opened device: /dev/dri/card0
10859 11:56:13.034421 SUCCESS (0.007s)
10860 11:56:13.042070 <8>[ 20.919320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
10861 11:56:13.042951 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
10863 11:56:13.073562 <8>[ 20.953650] <LAVA_SIGNAL_TESTSET START drm_read>
10864 11:56:13.074405 Received signal: <TESTSET> START drm_read
10865 11:56:13.074795 Starting test_set drm_read
10866 11:56:13.089713 <14>[ 20.969784] [IGT] drm_read: executing
10867 11:56:13.096319 IGT-Version: 1.2<14>[ 20.974224] [IGT] drm_read: exiting, ret=77
10868 11:56:13.099832 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10869 11:56:13.106466 Opened devi<8>[ 20.985084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
10870 11:56:13.107316 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
10872 11:56:13.109377 ce: /dev/dri/card0
10873 11:56:13.113003 No KMS driver or no outputs, pipes: 8, outputs: 0
10874 11:56:13.115936 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
10875 11:56:13.123230 <14>[ 21.003080] [IGT] drm_read: executing
10876 11:56:13.129489 IGT-Version: 1.2<14>[ 21.007503] [IGT] drm_read: exiting, ret=77
10877 11:56:13.132935 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10878 11:56:13.139547 Opened devi<8>[ 21.018164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
10879 11:56:13.140383 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
10881 11:56:13.142854 ce: /dev/dri/card0
10882 11:56:13.146498 No KMS driver or no outputs, pipes: 8, outputs: 0
10883 11:56:13.149508 [1mSubtest fault-buffer: SKIP (0.000s)[0m
10884 11:56:13.156711 <14>[ 21.036907] [IGT] drm_read: executing
10885 11:56:13.163623 IGT-Version: 1.2<14>[ 21.041295] [IGT] drm_read: exiting, ret=77
10886 11:56:13.166955 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10887 11:56:13.176877 Opened device: /dev/dri/car<8>[ 21.052789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
10888 11:56:13.177455 d0
10889 11:56:13.178113 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
10891 11:56:13.179931 No KMS driver or no outputs, pipes: 8, outputs: 0
10892 11:56:13.183585 [1mSubtest empty-block: SKIP (0.000s)[0m
10893 11:56:13.192870 <14>[ 21.072942] [IGT] drm_read: executing
10894 11:56:13.199264 IGT-Version: 1.2<14>[ 21.077358] [IGT] drm_read: exiting, ret=77
10895 11:56:13.202659 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10896 11:56:13.209327 Opened devi<8>[ 21.087745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
10897 11:56:13.210177 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
10899 11:56:13.212820 ce: /dev/dri/card0
10900 11:56:13.215996 No KMS driver or no outputs, pipes: 8, outputs: 0
10901 11:56:13.219339 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
10902 11:56:13.237482 <14>[ 21.117530] [IGT] drm_read: executing
10903 11:56:13.243921 IGT-Version: 1.2<14>[ 21.122217] [IGT] drm_read: exiting, ret=77
10904 11:56:13.247165 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10905 11:56:13.257333 Opened device: /dev/dri/car<8>[ 21.133307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
10906 11:56:13.257900 d0
10907 11:56:13.258557 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
10909 11:56:13.260355 No KMS driver or no outputs, pipes: 8, outputs: 0
10910 11:56:13.267077 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
10911 11:56:13.277509 <14>[ 21.157724] [IGT] drm_read: executing
10912 11:56:13.284397 IGT-Version: 1.2<14>[ 21.162125] [IGT] drm_read: exiting, ret=77
10913 11:56:13.287781 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10914 11:56:13.294911 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
10916 11:56:13.297501 Opened devi<8>[ 21.173084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
10917 11:56:13.297976 ce: /dev/dri/card0
10918 11:56:13.300461 No KMS driver or no outputs, pipes: 8, outputs: 0
10919 11:56:13.307418 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
10920 11:56:13.311374 <14>[ 21.191505] [IGT] drm_read: executing
10921 11:56:13.317459 IGT-Version: 1.2<14>[ 21.196490] [IGT] drm_read: exiting, ret=77
10922 11:56:13.320809 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10923 11:56:13.330999 Opened devi<8>[ 21.207240] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
10924 11:56:13.331568 ce: /dev/dri/card0
10925 11:56:13.332227 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
10927 11:56:13.337615 No KMS drive<8>[ 21.216648] <LAVA_SIGNAL_TESTSET STOP>
10928 11:56:13.338490 Received signal: <TESTSET> STOP
10929 11:56:13.338902 Closing test_set drm_read
10930 11:56:13.340483 r or no outputs, pipes: 8, outputs: 0
10931 11:56:13.343855 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
10932 11:56:13.367067 <8>[ 21.247249] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
10933 11:56:13.367903 Received signal: <TESTSET> START kms_addfb_basic
10934 11:56:13.368296 Starting test_set kms_addfb_basic
10935 11:56:13.393469 <14>[ 21.273436] [IGT] kms_addfb_basic: executing
10936 11:56:13.406573 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<14>[ 21.282637] [IGT] kms_addfb_basic: starting subtest unused-handle
10937 11:56:13.407143 64)
10938 11:56:13.413086 Opened devi<14>[ 21.290425] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS
10939 11:56:13.416332 ce: /dev/dri/card0
10940 11:56:13.419741 Starting subtest: unused-handle
10941 11:56:13.422871 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
10942 11:56:13.429969 Test requirement<14>[ 21.307923] [IGT] kms_addfb_basic: exiting, ret=0
10943 11:56:13.436160 not met in function igt_require_i915, file ../lib/drmtest.c:720:
10944 11:56:13.443105 Test requirement: is_i915_dev<8>[ 21.321233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
10945 11:56:13.443953 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
10947 11:56:13.446375 ice(fd)
10948 11:56:13.453034 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
10949 11:56:13.455994 Test requirement: is_i915_device(fd)
10950 11:56:13.459617 No KMS driver or no outputs, pipes: 8, outputs: 0
10951 11:56:13.470944 <14>[ 21.351284] [IGT] kms_addfb_basic: executing
10952 11:56:13.484713 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<14>[ 21.360780] [IGT] kms_addfb_basic: starting subtest unused-pitches
10953 11:56:13.485279 64)
10954 11:56:13.490839 Opened devi<14>[ 21.368474] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS
10955 11:56:13.494075 ce: /dev/dri/card0
10956 11:56:13.497665 Starting subtest: unused-pitches
10957 11:56:13.501098 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
10958 11:56:13.507428 Test requirement<14>[ 21.386128] [IGT] kms_addfb_basic: exiting, ret=0
10959 11:56:13.514377 not met in function igt_require_i915, file ../lib/drmtest.c:720:
10960 11:56:13.520815 Test requirem<8>[ 21.399223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
10961 11:56:13.521659 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
10963 11:56:13.524042 ent: is_i915_device(fd)
10964 11:56:13.530575 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
10965 11:56:13.533897 Test requirement: is_i915_device(fd)
10966 11:56:13.537780 No KMS driver or no outputs, pipes: 8, outputs: 0
10967 11:56:13.548543 <14>[ 21.428474] [IGT] kms_addfb_basic: executing
10968 11:56:13.561377 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<14>[ 21.437862] [IGT] kms_addfb_basic: starting subtest unused-offsets
10969 11:56:13.561925 64)
10970 11:56:13.568204 Opened devi<14>[ 21.445588] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS
10971 11:56:13.571254 ce: /dev/dri/card0
10972 11:56:13.574766 Starting subtest: unused-offsets
10973 11:56:13.577978 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
10974 11:56:13.584772 <14>[ 21.463042] [IGT] kms_addfb_basic: exiting, ret=0
10975 11:56:13.597902 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720<8>[ 21.475078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
10976 11:56:13.598452 :
10977 11:56:13.599105 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
10979 11:56:13.601048 Test requirement: is_i915_device(fd)
10980 11:56:13.607688 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
10981 11:56:13.614754 Test requirement: is<14>[ 21.493632] [IGT] kms_addfb_basic: executing
10982 11:56:13.615314 _i915_device(fd)
10983 11:56:13.627835 No KMS driver or no outputs, pipes: 8, outputs<14>[ 21.503872] [IGT] kms_addfb_basic: starting subtest unused-modifier
10984 11:56:13.628416 : 0
10985 11:56:13.634694 IGT-Version<14>[ 21.512030] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS
10986 11:56:13.641357 : 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
10987 11:56:13.644296 Opened device: /dev/dri/card0
10988 11:56:13.647570 Startin<14>[ 21.528596] [IGT] kms_addfb_basic: exiting, ret=0
10989 11:56:13.650949 g subtest: unused-modifier
10990 11:56:13.657194 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
10991 11:56:13.664231 T<8>[ 21.540565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
10992 11:56:13.665161 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
10994 11:56:13.670711 est requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
10995 11:56:13.673711 Test requirement: is_i915_device(fd)
10996 11:56:13.680676 Test requirement not met<14>[ 21.560566] [IGT] kms_addfb_basic: executing
10997 11:56:13.683906 in function igt_require_i915, file ../lib/drmtest.c:720:
10998 11:56:13.693993 Test <14>[ 21.569693] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
10999 11:56:13.700597 requirement: is_<14>[ 21.578137] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP
11000 11:56:13.703563 i915_device(fd)
11001 11:56:13.706920 No KMS driver or no outputs, pipes: 8, outputs: 0
11002 11:56:13.713510 IGT-Version: 1.27.1-g621c2d3<14>[ 21.594933] [IGT] kms_addfb_basic: exiting, ret=77
11003 11:56:13.720180 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11004 11:56:13.720788 Opened device: /dev/dri/card0
11005 11:56:13.730307 Starting<8>[ 21.606965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11006 11:56:13.731150 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11008 11:56:13.733670 subtest: clobberred-modifier
11009 11:56:13.740216 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11010 11:56:13.743525 Test requirement: is_i915_device(fd)
11011 11:56:13.746977 [1mSubt<14>[ 21.627786] [IGT] kms_addfb_basic: executing
11012 11:56:13.753881 est clobberred-modifier: SKIP (0.000s)[0m
11013 11:56:13.760203 Test requirement not<14>[ 21.637854] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11014 11:56:13.769874 met in function<14>[ 21.646967] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP
11015 11:56:13.776602 igt_require_i915, file ../lib/drmtest.c:720:
11016 11:56:13.780064 Test requirement: is_i915_device(fd)
11017 11:56:13.783348 Test requir<14>[ 21.664411] [IGT] kms_addfb_basic: exiting, ret=77
11018 11:56:13.790270 ement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11019 11:56:13.799765 Test req<8>[ 21.676397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11020 11:56:13.800731 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11022 11:56:13.803029 uirement: is_i915_device(fd)
11023 11:56:13.806552 No KMS driver or no outputs, pipes: 8, outputs: 0
11024 11:56:13.813278 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11025 11:56:13.816311 Opened device: /dev/dri/card0
11026 11:56:13.819885 Starting subtest: invalid-smem-bo-on-discrete
11027 11:56:13.826318 Test requirement not met in <14>[ 21.706871] [IGT] kms_addfb_basic: executing
11028 11:56:13.832840 function igt_require_intel, file ../lib/drmtest.c:715:
11029 11:56:13.839617 Test req<14>[ 21.717116] [IGT] kms_addfb_basic: starting subtest legacy-format
11030 11:56:13.843319 uirement: is_intel_device(fd)
11031 11:56:13.846082 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11032 11:56:13.855992 Test requirement not met in function <14>[ 21.734784] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS
11033 11:56:13.862729 igt_require_i915, file ../lib/drmtest.c:720:
11034 11:56:13.865906 Test requirement: is_i915_device(fd)
11035 11:56:13.869434 Test require<14>[ 21.750837] [IGT] kms_addfb_basic: exiting, ret=0
11036 11:56:13.875819 ment not met in function igt_require_i915, file ../lib/drmtest.c:720:
11037 11:56:13.885778 Test requ<8>[ 21.762495] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11038 11:56:13.886344 irement: is_i915_device(fd)
11039 11:56:13.887003 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11041 11:56:13.892588 No KMS driver or no outputs, pipes: 8, outputs: 0
11042 11:56:13.899168 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11043 11:56:13.899717 Opened device: /dev/dri/card0
11044 11:56:13.902397 Starting subtest: legacy-format
11045 11:56:13.912738 Successfully fuzzed 10000 {bpp, depth} vari<14>[ 21.791546] [IGT] kms_addfb_basic: executing
11046 11:56:13.913300 ations
11047 11:56:13.915684 [1mSubtest legacy-format: SUCCESS (0.011s)[0m
11048 11:56:13.925668 Test requirement not met in function ig<14>[ 21.804074] [IGT] kms_addfb_basic: starting subtest no-handle
11049 11:56:13.935589 t_require_i915, <14>[ 21.811378] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS
11050 11:56:13.936152 file ../lib/drmtest.c:720:
11051 11:56:13.938856 Test requirement: is_i915_device(fd)
11052 11:56:13.945628 Test requireme<14>[ 21.826102] [IGT] kms_addfb_basic: exiting, ret=0
11053 11:56:13.952130 nt not met in function igt_require_i915, file ../lib/drmtest.c:720:
11054 11:56:13.958658 Test requir<8>[ 21.838365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11055 11:56:13.959487 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11057 11:56:13.962344 ement: is_i915_device(fd)
11058 11:56:13.965147 No KMS driver or no outputs, pipes: 8, outputs: 0
11059 11:56:13.972442 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11060 11:56:13.975635 Opened device: /dev/dri/card0
11061 11:56:13.978370 Starting subtest: no-handle
11062 11:56:13.981773 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11063 11:56:13.988390 Test<14>[ 21.866931] [IGT] kms_addfb_basic: executing
11064 11:56:13.995303 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11065 11:56:14.001523 Test requirement:<14>[ 21.879456] [IGT] kms_addfb_basic: starting subtest basic
11066 11:56:14.007995 is_i915_device(<14>[ 21.886413] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS
11067 11:56:14.008605 fd)
11068 11:56:14.021447 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 21.900797] [IGT] kms_addfb_basic: exiting, ret=0
11069 11:56:14.022014 c:720:
11070 11:56:14.024636 Test requirement: is_i915_device(fd)
11071 11:56:14.034403 No KMS driver or no outputs, pipes<8>[ 21.913030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11072 11:56:14.034974 : 8, outputs: 0
11073 11:56:14.035631 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11075 11:56:14.041066 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11076 11:56:14.044656 Opened device: /dev/dri/card0
11077 11:56:14.047680 Starting subtest: basic
11078 11:56:14.054207 [1mSubtest basic: SUCCESS (0.000s<14>[ 21.933621] [IGT] kms_addfb_basic: executing
11079 11:56:14.054681 )[0m
11080 11:56:14.067323 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 21.945924] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11081 11:56:14.067881 t.c:720:
11082 11:56:14.077725 Test r<14>[ 21.953032] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS
11083 11:56:14.078277 equirement: is_i915_device(fd)
11084 11:56:14.087599 Test requirement not met in function igt_require<14>[ 21.967060] [IGT] kms_addfb_basic: exiting, ret=0
11085 11:56:14.090757 _i915, file ../lib/drmtest.c:720:
11086 11:56:14.093902 Test requirement: is_i915_device(fd)
11087 11:56:14.100941 No KMS <8>[ 21.980335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11088 11:56:14.101792 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11090 11:56:14.107671 driver or no outputs, pipes: 8, outputs: 0
11091 11:56:14.110708 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11092 11:56:14.114230 Opened device: /dev/dri/card0
11093 11:56:14.121354 <14>[ 21.999726] [IGT] kms_addfb_basic: executing
11094 11:56:14.121915 Starting subtest: bad-pitch-0
11095 11:56:14.127544 [1mSubtest bad-pitch-0: SUCCESS (0.000s)[0m
11096 11:56:14.134070 Te<14>[ 22.010807] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11097 11:56:14.140728 st requirement n<14>[ 22.017953] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS
11098 11:56:14.147489 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11099 11:56:14.153443 Test requiremen<14>[ 22.032194] [IGT] kms_addfb_basic: exiting, ret=0
11100 11:56:14.156991 t: is_i915_device(fd)
11101 11:56:14.166684 Test requirement not met in function igt_require_i915, fi<8>[ 22.044717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11102 11:56:14.167568 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11104 11:56:14.169913 le ../lib/drmtest.c:720:
11105 11:56:14.173137 Test requirement: is_i915_device(fd)
11106 11:56:14.176500 No KMS driver or no outputs, pipes: 8, outputs: 0
11107 11:56:14.183701 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11108 11:56:14.186271 Opened device: /dev/dri/card0
11109 11:56:14.189833 Starting subtest: bad-pitch-32
11110 11:56:14.193167 [1mSubte<14>[ 22.074050] [IGT] kms_addfb_basic: executing
11111 11:56:14.196359 st bad-pitch-32: SUCCESS (0.000s)[0m
11112 11:56:14.209588 Test requirement not met in function igt_require_i915, fi<14>[ 22.086589] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11113 11:56:14.216342 le ../lib/drmtes<14>[ 22.094068] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS
11114 11:56:14.219652 t.c:720:
11115 11:56:14.222789 Test requirement: is_i915_device(fd)
11116 11:56:14.229808 Test requirement not met in func<14>[ 22.108974] [IGT] kms_addfb_basic: exiting, ret=0
11117 11:56:14.232788 tion igt_require_i915, file ../lib/drmtest.c:720:
11118 11:56:14.242769 Test requirement: is_i915_dev<8>[ 22.121369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11119 11:56:14.243322 ice(fd)
11120 11:56:14.243974 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11122 11:56:14.249381 No KMS driver or no outputs, pipes: 8, outputs: 0
11123 11:56:14.255893 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11124 11:56:14.256450 Opened device: /dev/dri/card0
11125 11:56:14.258991 Starting subtest: bad-pitch-63
11126 11:56:14.265768 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11127 11:56:14.269077 Test requirement<14>[ 22.150271] [IGT] kms_addfb_basic: executing
11128 11:56:14.275792 not met in function igt_require_i915, file ../lib/drmtest.c:720:
11129 11:56:14.285445 Test requirement: is_i915_dev<14>[ 22.162823] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11130 11:56:14.286027 ice(fd)
11131 11:56:14.292061 Test re<14>[ 22.170324] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS
11132 11:56:14.298436 quirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11133 11:56:14.305467 Test<14>[ 22.185341] [IGT] kms_addfb_basic: exiting, ret=0
11134 11:56:14.308450 requirement: is_i915_device(fd)
11135 11:56:14.318820 No KMS driver or no outputs, pipes: 8, outputs<8>[ 22.197771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11136 11:56:14.319400 : 0
11137 11:56:14.320184 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11139 11:56:14.325253 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11140 11:56:14.328724 Opened device: /dev/dri/card0
11141 11:56:14.331894 Starting subtest: bad-pitch-128
11142 11:56:14.334776 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11143 11:56:14.345159 Test requirement not met in function igt_require_i915, file ../lib/dr<14>[ 22.226693] [IGT] kms_addfb_basic: executing
11144 11:56:14.348381 mtest.c:720:
11145 11:56:14.351860 Test requirement: is_i915_device(fd)
11146 11:56:14.361510 Test requirement not met in function igt_req<14>[ 22.239278] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11147 11:56:14.371371 uire_i915, file <14>[ 22.246823] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS
11148 11:56:14.371951 ../lib/drmtest.c:720:
11149 11:56:14.375297 Test requirement: is_i915_device(fd)
11150 11:56:14.381064 No KMS driver or no<14>[ 22.261868] [IGT] kms_addfb_basic: exiting, ret=0
11151 11:56:14.384934 outputs, pipes: 8, outputs: 0
11152 11:56:14.398105 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 22.274596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11153 11:56:14.398660 64)
11154 11:56:14.399616 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11156 11:56:14.401311 Opened device: /dev/dri/card0
11157 11:56:14.404874 Starting subtest: bad-pitch-256
11158 11:56:14.407725 [1mSubtest bad-pitch-256: SUCCESS (0.000s)[0m
11159 11:56:14.414521 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11160 11:56:14.417902 Test requirement: is_i915_device(fd)
11161 11:56:14.424914 Test requirement <14>[ 22.304586] [IGT] kms_addfb_basic: executing
11162 11:56:14.431103 not met in function igt_require_i915, file ../lib/drmtest.c:720:
11163 11:56:14.440843 Test requirement: is_i915_devi<14>[ 22.317070] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11164 11:56:14.441413 ce(fd)
11165 11:56:14.447396 No KMS d<14>[ 22.324692] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS
11166 11:56:14.450675 river or no outputs, pipes: 8, outputs: 0
11167 11:56:14.460955 IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[ 22.339752] [IGT] kms_addfb_basic: exiting, ret=0
11168 11:56:14.464218 ) (Linux: 6.1.62-cip9 aarch64)
11169 11:56:14.464819 Opened device: /dev/dri/card0
11170 11:56:14.467070 Starting subtest: bad-pitch-1024
11171 11:56:14.477418 <8>[ 22.352584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11172 11:56:14.477979
11173 11:56:14.478632 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11175 11:56:14.480151 [1mSubtest bad-pitch-1024: SUCCESS (0.000s)[0m
11176 11:56:14.487325 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11177 11:56:14.493724 Test requi<14>[ 22.372078] [IGT] kms_addfb_basic: executing
11178 11:56:14.496702 rement: is_i915_device(fd)
11179 11:56:14.506857 Test requirement not met in function igt_require_i91<14>[ 22.384506] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11180 11:56:14.513409 5, file ../lib/d<14>[ 22.391575] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS
11181 11:56:14.516779 rmtest.c:720:
11182 11:56:14.520104 Test requirement: is_i915_device(fd)
11183 11:56:14.526681 No KMS driver or no outputs<14>[ 22.405993] [IGT] kms_addfb_basic: exiting, ret=0
11184 11:56:14.530096 , pipes: 8, outputs: 0
11185 11:56:14.539717 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-ci<8>[ 22.418826] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11186 11:56:14.540622 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11188 11:56:14.543019 p9 aarch64)
11189 11:56:14.546656 Opened device: /dev/dri/card0
11190 11:56:14.547231 Starting subtest: bad-pitch-999
11191 11:56:14.553189 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11192 11:56:14.559644 Test requirement n<14>[ 22.437825] [IGT] kms_addfb_basic: executing
11193 11:56:14.562714 ot met in function igt_require_i915, file ../lib/drmtest.c:720:
11194 11:56:14.572458 Test requiremen<14>[ 22.449818] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11195 11:56:14.579280 t: is_i915_devic<14>[ 22.457235] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS
11196 11:56:14.582890 e(fd)
11197 11:56:14.592669 Test requirement not met in function igt_require_i915, file ../lib/drmtes<14>[ 22.471612] [IGT] kms_addfb_basic: exiting, ret=0
11198 11:56:14.593231 t.c:720:
11199 11:56:14.595559 Test requirement: is_i915_device(fd)
11200 11:56:14.605446 No KMS driver or no outputs, pip<8>[ 22.484890] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11201 11:56:14.606294 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11203 11:56:14.608636 es: 8, outputs: 0
11204 11:56:14.615594 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11205 11:56:14.618760 Opened device: /dev/dri/card0
11206 11:56:14.619319 Starting subtest: bad-pitch-65536
11207 11:56:14.625496 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11208 11:56:14.635480 Test requirement not met in function igt_require_i9<14>[ 22.514140] [IGT] kms_addfb_basic: executing
11209 11:56:14.636042 15, file ../lib/drmtest.c:720:
11210 11:56:14.638526 Test requirement: is_i915_device(fd)
11211 11:56:14.651765 Test requirement not met in function igt_r<14>[ 22.528684] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11212 11:56:14.658127 equire_i915, fil<14>[ 22.535977] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS
11213 11:56:14.661766 e ../lib/drmtest.c:720:
11214 11:56:14.664720 Test requirement: is_i915_device(fd)
11215 11:56:14.671611 N<14>[ 22.549523] [IGT] kms_addfb_basic: exiting, ret=0
11216 11:56:14.674586 o KMS driver or no outputs, pipes: 8, outputs: 0
11217 11:56:14.685086 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11219 11:56:14.688045 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<8>[ 22.562864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11220 11:56:14.688675 6.1.62-cip9 aarch64)
11221 11:56:14.691661 Opened device: /dev/dri/card0
11222 11:56:14.694949 Starting subtest: invalid-get-prop-any
11223 11:56:14.704762 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)<14>[ 22.584172] [IGT] kms_addfb_basic: executing
11224 11:56:14.705347 [0m
11225 11:56:14.711156 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11226 11:56:14.717667 Test re<14>[ 22.597218] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11227 11:56:14.727885 quirement: is_i9<14>[ 22.604159] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS
11228 11:56:14.728464 15_device(fd)
11229 11:56:14.737536 Test requirement not met in funct<14>[ 22.616971] [IGT] kms_addfb_basic: exiting, ret=0
11230 11:56:14.740984 ion igt_require_i915, file ../lib/drmtest.c:720:
11231 11:56:14.750686 Test requirement: is_i915_devi<8>[ 22.628953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11232 11:56:14.751270 ce(fd)
11233 11:56:14.752050 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11235 11:56:14.757418 No KMS driver or no outputs, pipes: 8, outputs: 0
11236 11:56:14.763886 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11237 11:56:14.764429 Opened device: /dev/dri/card0
11238 11:56:14.767433 Starting subtest: invalid-get-prop
11239 11:56:14.773964 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11240 11:56:14.777340 Test requ<14>[ 22.658365] [IGT] kms_addfb_basic: executing
11241 11:56:14.783871 irement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11242 11:56:14.787204 Test requirement: is_i915_device(fd)
11243 11:56:14.793604 <14>[ 22.672956] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11244 11:56:14.803407 Test requirement<14>[ 22.680387] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS
11245 11:56:14.813371 not met in function igt_require_i915, file ../lib/drmtest.c:720<14>[ 22.693846] [IGT] kms_addfb_basic: exiting, ret=0
11246 11:56:14.816813 :
11247 11:56:14.820320 Test requirement: is_i915_device(fd)
11248 11:56:14.830064 No KMS driver or no outputs, pipes: 8, <8>[ 22.706910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11249 11:56:14.830628 outputs: 0
11250 11:56:14.831282 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11252 11:56:14.836608 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11253 11:56:14.839876 Opened device: /dev/dri/card0
11254 11:56:14.843140 Starting subtest: invalid-set-prop-any
11255 11:56:14.846736 [1mSubt<14>[ 22.727506] [IGT] kms_addfb_basic: executing
11256 11:56:14.853238 est invalid-set-prop-any: SUCCESS (0.000s)[0m
11257 11:56:14.863717 Test requirement not met in function igt_require<14>[ 22.741552] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11258 11:56:14.872990 _i915, file ../l<14>[ 22.748636] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS
11259 11:56:14.873555 ib/drmtest.c:720:
11260 11:56:14.882782 Test requirement: is_i915_dev<14>[ 22.761351] [IGT] kms_addfb_basic: exiting, ret=0
11261 11:56:14.883339 ice(fd)
11262 11:56:14.895825 Test requirement not met in function igt_require_i915, file ../lib/drmt<8>[ 22.773062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11263 11:56:14.896377 est.c:720:
11264 11:56:14.897190 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11266 11:56:14.899338 Test requirement: is_i915_device(fd)
11267 11:56:14.905869 No KMS driver or no outputs, pipes: 8, outputs: 0
11268 11:56:14.909097 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11269 11:56:14.912631 Opened device: /dev/dri/card0
11270 11:56:14.916655 Starting subtest: invalid-set-prop
11271 11:56:14.922583 [1mSubtest invalid<14>[ 22.802647] [IGT] kms_addfb_basic: executing
11272 11:56:14.925573 -set-prop: SUCCESS (0.000s)[0m
11273 11:56:14.932402 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11274 11:56:14.941755 Test requirement: is_i915_de<14>[ 22.819389] [IGT] kms_addfb_basic: starting subtest master-rmfb
11275 11:56:14.942316 vice(fd)
11276 11:56:14.948764 Test r<14>[ 22.826799] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS
11277 11:56:14.958789 equirement not met in function i<14>[ 22.837450] [IGT] kms_addfb_basic: exiting, ret=0
11278 11:56:14.962253 gt_require_i915, file ../lib/drmtest.c:720:
11279 11:56:14.972450 Test requirement: is_i915_device(fd<8>[ 22.849812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11280 11:56:14.973048 )
11281 11:56:14.973704 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11283 11:56:14.975088 No KMS driver or no outputs, pipes: 8, outputs: 0
11284 11:56:14.981850 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11285 11:56:14.985192 Opened device: /dev/dri/card0
11286 11:56:14.988501 Starting subtest: master-rmfb
11287 11:56:14.992397 [1mSubtest master-rmfb: SUCCESS (0.000s)[0m
11288 11:56:14.998205 Test requirement not met<14>[ 22.878527] [IGT] kms_addfb_basic: executing
11289 11:56:15.005217 in function igt_require_i915, file ../lib/drmtest.c:720:
11290 11:56:15.007920 Test requirement: is_i915_device(fd)
11291 11:56:15.021330 Test requirement not met in function igt_require_i915, file ../<14>[ 22.897406] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11292 11:56:15.028253 lib/drmtest.c:72<14>[ 22.905149] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS
11293 11:56:15.031293 0:
11294 11:56:15.034861 Test require<14>[ 22.914975] [IGT] kms_addfb_basic: exiting, ret=0
11295 11:56:15.037787 ment: is_i915_device(fd)
11296 11:56:15.041257 No KMS driver or no outputs, pipes: 8, outputs: 0
11297 11:56:15.050849 IGT<8>[ 22.927923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11298 11:56:15.051768 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11300 11:56:15.057663 -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11301 11:56:15.061007 Opened device: /dev/dri/card0
11302 11:56:15.064267 Starting subtest: addfb25-modifier-no-flag
11303 11:56:15.067433 [1<14>[ 22.947425] [IGT] kms_addfb_basic: executing
11304 11:56:15.074104 mSubtest addfb25-modifier-no-flag: SUCCESS (0.000s)[0m
11305 11:56:15.080889 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11306 11:56:15.087509 Test<14>[ 22.965103] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11307 11:56:15.090611 requirement: is_i915_device(fd)
11308 11:56:15.100760 Test requirement not met in fu<14>[ 22.977407] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL
11309 11:56:15.107285 nction igt_requi<14>[ 22.986568] [IGT] kms_addfb_basic: exiting, ret=98
11310 11:56:15.110496 re_i915, file ../lib/drmtest.c:720:
11311 11:56:15.114454 Test requirement: is_i915_device(fd)
11312 11:56:15.120699 No KM<8>[ 22.999533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11313 11:56:15.121543 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11315 11:56:15.126943 S driver or no outputs, pipes: 8, outputs: 0
11316 11:56:15.133684 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11317 11:56:15.140427 Opened device: /dev/dri/card0<14>[ 23.019320] [IGT] kms_addfb_basic: executing
11318 11:56:15.141166
11319 11:56:15.143410 Starting subtest: addfb25-bad-modifier
11320 11:56:15.156947 (kms_addfb_basic:425) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb<14>[ 23.036563] [IGT] kms_addfb_basic: exiting, ret=77
11321 11:56:15.157511 _basic.c:662:
11322 11:56:15.173468 (kms_addfb_basic:425) CRITICAL: Failed assertion: igt_ioctl((fd),<8>[ 23.049006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11323 11:56:15.174320 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11325 11:56:15.183321 ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11326 11:56:15.189707 (kms_addfb_basic:425) CRITICAL: error: 0 != -1
11327 11:56:15.190260 Stack trace:
11328 11:56:15.192964 #0 ../lib/igt_core.c:1971 __igt_fail_assert()
11329 11:56:15.199425 #1<14>[ 23.079417] [IGT] kms_addfb_basic: executing
11330 11:56:15.202981 [<unknown>+0xc89047e0]
11331 11:56:15.203402 #2 [<unknown>+0xc8906278]
11332 11:56:15.206173 #3 [<unknown>+0xc890167c]
11333 11:56:15.209471 #4 [__libc_start_main+0xe8]
11334 11:56:15.212963 #5 [<unknown>+0xc89016b4]
11335 11:56:15.219743 #6 [<unknown>+0<14>[ 23.098447] [IGT] kms_addfb_basic: exiting, ret=77
11336 11:56:15.220302 xc89016b4]
11337 11:56:15.222891 Subtest addfb25-bad-modifier failed.
11338 11:56:15.223446 **** DEBUG ****
11339 11:56:15.235849 (kms_addfb_basic:425) ioctl_w<8>[ 23.111806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11340 11:56:15.236712 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11342 11:56:15.239048 rappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11343 11:56:15.249304 (kms_addfb_basic:425) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:
11344 11:56:15.262163 (kms_addfb_basic:425) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|<14>[ 23.141979] [IGT] kms_addfb_basic: executing
11345 11:56:15.272262 1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11346 11:56:15.282486 (kms_addfb_basic:425) CRITICAL: error: 0 !=<14>[ 23.160779] [IGT] kms_addfb_basic: exiting, ret=77
11347 11:56:15.283047 -1
11348 11:56:15.285100 (kms_addfb_basic:425) igt_core-INFO: Stack trace:
11349 11:56:15.298798 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11351 11:56:15.301587 (kms_addfb_basic:425) igt_core-INFO: #0 ../lib/igt_cor<8>[ 23.176910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11352 11:56:15.302027 e.c:1971 __igt_fail_assert()
11353 11:56:15.308584 (kms_addfb_basic:425) igt_core-INFO: #1 [<unknown>+0xc89047e0]
11354 11:56:15.315067 (kms_addfb_basic:425) igt_core-INFO: #2 [<unknown>+0xc8906278]
11355 11:56:15.321751 (kms_addfb_basic:425) igt_core-INFO: #3 [<unknown>+0xc890167c]
11356 11:56:15.328113 (kms_addfb_basic:425) igt_co<14>[ 23.207664] [IGT] kms_addfb_basic: executing
11357 11:56:15.331892 re-INFO: #4 [__libc_start_main+0xe8]
11358 11:56:15.334980 (kms_addfb_basic:425) igt_core-INFO: #5 [<unknown>+0xc89016b4]
11359 11:56:15.341449 (kms_addfb_basic:425) igt_core-INFO: #6 [<unknown>+0xc89016b4]
11360 11:56:15.348163 ****<14>[ 23.226598] [IGT] kms_addfb_basic: exiting, ret=77
11361 11:56:15.348768 END ****
11362 11:56:15.354747 [1mSubtest addfb25-bad-modifier: FAIL (0.004s)[0m
11363 11:56:15.365006 Test requirement not met in function igt_requi<8>[ 23.242036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11364 11:56:15.365862 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11366 11:56:15.368052 re_i915, file ../lib/drmtest.c:720:
11367 11:56:15.371649 Test requirement: is_i915_device(fd)
11368 11:56:15.377966 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11369 11:56:15.381064 Test requirement: is_i915_device(fd)
11370 11:56:15.387637 No KMS driver or no outputs, pipes: 8, outputs: 0
11371 11:56:15.390728 IGT-Versi<14>[ 23.272211] [IGT] kms_addfb_basic: executing
11372 11:56:15.397463 on: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11373 11:56:15.400625 Opened device: /dev/dri/card0
11374 11:56:15.410831 Test requirement not met in function igt_require_i915, file ../lib/dr<14>[ 23.291145] [IGT] kms_addfb_basic: exiting, ret=77
11375 11:56:15.411400 mtest.c:720:
11376 11:56:15.413935 Test requirement: is_i915_device(fd)
11377 11:56:15.427272 [1mSubtest addfb25-x-tiled-mismatch-legacy:<8>[ 23.304161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11378 11:56:15.428124 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11380 11:56:15.430381 SKIP (0.000s)[0m
11381 11:56:15.436907 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11382 11:56:15.440336 Test requirement: is_i915_device(fd)
11383 11:56:15.443440 No <14>[ 23.324331] [IGT] kms_addfb_basic: executing
11384 11:56:15.450273 KMS driver or no outputs, pipes: 8, outputs: 0
11385 11:56:15.453614 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11386 11:56:15.463294 Opened device: /dev/dri/car<14>[ 23.342079] [IGT] kms_addfb_basic: exiting, ret=77
11387 11:56:15.463874 d0
11388 11:56:15.476589 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c<8>[ 23.354593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11389 11:56:15.477138 :720:
11390 11:56:15.477778 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11392 11:56:15.479983 Test requirement: is_i915_device(fd)
11393 11:56:15.486674 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000s)[0m
11394 11:56:15.493041 Test requirement not met in function igt_req<14>[ 23.373954] [IGT] kms_addfb_basic: executing
11395 11:56:15.496248 uire_i915, file ../lib/drmtest.c:720:
11396 11:56:15.499788 Test requirement: is_i915_device(fd)
11397 11:56:15.506757 No KMS driver or no outputs, pipes: 8, outputs: 0
11398 11:56:15.513031 IGT-Version: 1.2<14>[ 23.391620] [IGT] kms_addfb_basic: exiting, ret=77
11399 11:56:15.516447 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11400 11:56:15.526316 Opened device: /dev/dri/car<8>[ 23.403723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11401 11:56:15.526878 d0
11402 11:56:15.527526 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11404 11:56:15.533495 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11405 11:56:15.536218 Test requirement: is_i915_device(fd)
11406 11:56:15.543010 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11407 11:56:15.552677 Test requirement not met in function igt_require_i915, file ../li<14>[ 23.433776] [IGT] kms_addfb_basic: executing
11408 11:56:15.555999 b/drmtest.c:720:
11409 11:56:15.559436 Test requirement: is_i915_device(fd)
11410 11:56:15.562470 No KMS driver or no outputs, pipes: 8, outputs: 0
11411 11:56:15.569160 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11412 11:56:15.572673 <14>[ 23.452639] [IGT] kms_addfb_basic: exiting, ret=77
11413 11:56:15.575666 Opened device: /dev/dri/card0
11414 11:56:15.589209 Test requirement not met in function igt_require_i915, file ../li<8>[ 23.466444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11415 11:56:15.589771 b/drmtest.c:720:
11416 11:56:15.590422 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11418 11:56:15.592945 Test requirement: is_i915_device(fd)
11419 11:56:15.602239 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11420 11:56:15.605208 Test <14>[ 23.485645] [IGT] kms_addfb_basic: executing
11421 11:56:15.608614 requirement: is_i915_device(fd)
11422 11:56:15.611995 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11423 11:56:15.618806 No KMS driver or no outputs, pipes: 8, outputs: 0
11424 11:56:15.622039 IGT-Ver<14>[ 23.503357] [IGT] kms_addfb_basic: exiting, ret=77
11425 11:56:15.628664 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11426 11:56:15.638548 Opened device: /de<8>[ 23.515667] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11427 11:56:15.639110 v/dri/card0
11428 11:56:15.639756 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11430 11:56:15.645197 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11431 11:56:15.648956 Test requirement: is_i915_device(fd)
11432 11:56:15.655279 Test requirement not met i<14>[ 23.535342] [IGT] kms_addfb_basic: executing
11433 11:56:15.661662 n function igt_require_i915, file ../lib/drmtest.c:720:
11434 11:56:15.665383 Test requirement: is_i915_device(fd)
11435 11:56:15.675322 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.00<14>[ 23.553258] [IGT] kms_addfb_basic: exiting, ret=77
11436 11:56:15.675883 0s)[0m
11437 11:56:15.678158 No KMS driver or no outputs, pipes: 8, outputs: 0
11438 11:56:15.688083 IGT-Version: 1.27.1-<8>[ 23.565611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11439 11:56:15.688984 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11441 11:56:15.691487 g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11442 11:56:15.694692 Opened device: /dev/dri/card0
11443 11:56:15.701183 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11444 11:56:15.704367 Test requirement: is_i915_device(fd)
11445 11:56:15.714693 Test requirement not met in function igt_require_i915, <14>[ 23.594217] [IGT] kms_addfb_basic: executing
11446 11:56:15.717503 file ../lib/drmtest.c:720:
11447 11:56:15.720771 Test requirement: is_i915_device(fd)
11448 11:56:15.724477 [1mSubtest tile-pitch-mismatch: SKIP (0.000s)[0m
11449 11:56:15.727560 No KMS driver or no outputs, pipes: 8, outputs: 0
11450 11:56:15.733937 IGT-Ver<14>[ 23.613485] [IGT] kms_addfb_basic: exiting, ret=77
11451 11:56:15.740909 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11452 11:56:15.744137 Opened device: /dev/dri/card0
11453 11:56:15.751178 Tes<8>[ 23.627036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11454 11:56:15.752029 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11456 11:56:15.757629 t requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11457 11:56:15.760893 Test requirement: is_i915_device(fd)
11458 11:56:15.767391 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11459 11:56:15.770631 Test requirement: is_i915_device(fd)
11460 11:56:15.777760 [1mSubtest basic-y-tiled-legacy:<14>[ 23.657686] [IGT] kms_addfb_basic: executing
11461 11:56:15.780466 SKIP (0.000s)[0m
11462 11:56:15.784125 No KMS driver or no outputs, pipes: 8, outputs: 0
11463 11:56:15.790694 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11464 11:56:15.793548 Opened device: /dev/dri/card0
11465 11:56:15.797198 Test <14>[ 23.677486] [IGT] kms_addfb_basic: exiting, ret=77
11466 11:56:15.803535 requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11467 11:56:15.813596 Test requirement: is_i915_device(f<8>[ 23.693269] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11468 11:56:15.814425 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11470 11:56:15.816870 d)
11471 11:56:15.823330 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11472 11:56:15.827175 Test requirement: is_i915_device(fd)
11473 11:56:15.830153 No KMS driver or no outputs, pipes: 8, outputs: 0
11474 11:56:15.833621 [1mSubtest size-max: SKIP (0.000s)[0m
11475 11:56:15.843220 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-c<14>[ 23.722889] [IGT] kms_addfb_basic: executing
11476 11:56:15.843768 ip9 aarch64)
11477 11:56:15.846537 Opened device: /dev/dri/card0
11478 11:56:15.853553 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11479 11:56:15.856981 Test requirement: is_i915_device(fd)
11480 11:56:15.863351 Test requi<14>[ 23.742615] [IGT] kms_addfb_basic: exiting, ret=77
11481 11:56:15.869844 rement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11482 11:56:15.879907 Test requirement: is_i9<8>[ 23.756156] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11483 11:56:15.880932 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11485 11:56:15.883476 15_device(fd)
11486 11:56:15.886226 No KMS driver or no outputs, pipes: 8, outputs: 0
11487 11:56:15.889731 [1mSubtest too-wide: SKIP (0.000s)[0m
11488 11:56:15.896213 IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[ 23.777327] [IGT] kms_addfb_basic: executing
11489 11:56:15.899435 ) (Linux: 6.1.62-cip9 aarch64)
11490 11:56:15.902777 Opened device: /dev/dri/card0
11491 11:56:15.915983 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:<14>[ 23.794859] [IGT] kms_addfb_basic: exiting, ret=77
11492 11:56:15.916605
11493 11:56:15.919122 Test requirement: is_i915_device(fd)
11494 11:56:15.932441 Test requirement not met in function igt_require_i915, f<8>[ 23.807509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11495 11:56:15.933084 ile ../lib/drmtest.c:720:
11496 11:56:15.933864 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11498 11:56:15.935518 Test requirement: is_i915_device(fd)
11499 11:56:15.941949 No KMS driver or no outputs, pipes: 8, outputs: 0
11500 11:56:15.945223 [1mSubtest too-high: SKIP (0.000s)[0m
11501 11:56:15.952235 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11502 11:56:15.952836 Opened device: /dev/dri/card0
11503 11:56:15.958795 <14>[ 23.838392] [IGT] kms_addfb_basic: executing
11504 11:56:15.959367
11505 11:56:15.965486 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11506 11:56:15.968897 Test requirement: is_i915_device(fd)
11507 11:56:15.978581 Test requirement not met in function igt_require_i915,<14>[ 23.857617] [IGT] kms_addfb_basic: exiting, ret=77
11508 11:56:15.981873 file ../lib/drmtest.c:720:
11509 11:56:15.985330 Test requirement: is_i915_device(fd)
11510 11:56:15.995019 No KMS driver or no outputs, <8>[ 23.871331] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11511 11:56:15.995883 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11513 11:56:15.998250 pipes: 8, outputs: 0
11514 11:56:16.001368 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11515 11:56:16.008397 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11516 11:56:16.009008 Opened device: /dev/dri/card0
11517 11:56:16.018305 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11518 11:56:16.024404 Test requirement: is_i<14>[ 23.903091] [IGT] kms_addfb_basic: executing
11519 11:56:16.024924 915_device(fd)
11520 11:56:16.031478 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11521 11:56:16.034652 Test requirement: is_i915_device(fd)
11522 11:56:16.040964 No KMS driver or no out<14>[ 23.922039] [IGT] kms_addfb_basic: exiting, ret=77
11523 11:56:16.044628 puts, pipes: 8, outputs: 0
11524 11:56:16.047971 [1mSubtest small-bo: SKIP (0.000s)[0m
11525 11:56:16.057440 IGT-Version: 1.27.1-g621c2d<8>[ 23.935628] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11526 11:56:16.058265 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11528 11:56:16.064061 3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11529 11:56:16.064563 Opened device: /dev/dri/card0
11530 11:56:16.074036 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11531 11:56:16.077235 Test requirement: is_i915_device(fd)
11532 11:56:16.087533 Test requirement not met in function igt_require_i915, file ..<14>[ 23.966452] [IGT] kms_addfb_basic: executing
11533 11:56:16.088096 /lib/drmtest.c:720:
11534 11:56:16.090642 Test requirement: is_i915_device(fd)
11535 11:56:16.093954 No KMS driver or no outputs, pipes: 8, outputs: 0
11536 11:56:16.100460 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11537 11:56:16.106979 IGT-Ver<14>[ 23.985237] [IGT] kms_addfb_basic: exiting, ret=77
11538 11:56:16.110306 sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11539 11:56:16.113543 Opened device: /dev/dri/card0
11540 11:56:16.120683 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11542 11:56:16.123305 Tes<8>[ 23.998927] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11543 11:56:16.130121 t requirement not met in functio<8>[ 24.009328] <LAVA_SIGNAL_TESTSET STOP>
11544 11:56:16.130959 Received signal: <TESTSET> STOP
11545 11:56:16.131345 Closing test_set kms_addfb_basic
11546 11:56:16.133899 n igt_require_i915, file ../lib/drmtest.c:720:
11547 11:56:16.136631 Test requirement: is_i915_device(fd)
11548 11:56:16.143109 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11549 11:56:16.146651 Test requirement: is_i915_device(fd)
11550 11:56:16.150063 No KMS driver or no outputs, pipes: 8, outputs: 0
11551 11:56:16.159729 [1mSubtest addfb25-y-tiled-legacy: SKIP (0.00<8>[ 24.039561] <LAVA_SIGNAL_TESTSET START kms_atomic>
11552 11:56:16.160196 0s)[0m
11553 11:56:16.161054 Received signal: <TESTSET> START kms_atomic
11554 11:56:16.161451 Starting test_set kms_atomic
11555 11:56:16.166474 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11556 11:56:16.169671 Opened device: /dev/dri/card0
11557 11:56:16.176329 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11558 11:56:16.179753 Test requirement: is_i915_device(fd)
11559 11:56:16.186383 Test requirement not met i<14>[ 24.067670] [IGT] kms_atomic: executing
11560 11:56:16.193120 n function igt_r<14>[ 24.072967] [IGT] kms_atomic: exiting, ret=77
11561 11:56:16.196395 equire_i915, file ../lib/drmtest.c:720:
11562 11:56:16.199422 Test requirement: is_i915_device(fd)
11563 11:56:16.205825 N<8>[ 24.083777] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11564 11:56:16.206564 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11566 11:56:16.212462 o KMS driver or no outputs, pipes: 8, outputs: 0
11567 11:56:16.216015 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11568 11:56:16.222754 IGT-Version: 1.27.1-g621c2d3 (aarch64)<14>[ 24.104887] [IGT] kms_atomic: executing
11569 11:56:16.229065 (Linux: 6.1.62-<14>[ 24.109957] [IGT] kms_atomic: exiting, ret=77
11570 11:56:16.232762 cip9 aarch64)
11571 11:56:16.233216 Opened device: /dev/dri/card0
11572 11:56:16.245813 Test requirement not met in function igt_require_i<8>[ 24.122924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11573 11:56:16.246661 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11575 11:56:16.248840 915, file ../lib/drmtest.c:720:
11576 11:56:16.252416 Test requirement: is_i915_device(fd)
11577 11:56:16.259245 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11578 11:56:16.262328 Test requirement: is_i915_device(fd)
11579 11:56:16.269100 No KMS driver or no outputs, pipes: 8, outputs: 0
11580 11:56:16.272404 [1mSubtest a<14>[ 24.153521] [IGT] kms_atomic: executing
11581 11:56:16.278566 ddfb25-y-tiled-s<14>[ 24.158854] [IGT] kms_atomic: exiting, ret=77
11582 11:56:16.281872 mall-legacy: SKIP (0.000s)[0m
11583 11:56:16.295058 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<8>[ 24.170440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11584 11:56:16.295609 .1.62-cip9 aarch64)
11585 11:56:16.296256 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11587 11:56:16.298661 Opened device: /dev/dri/card0
11588 11:56:16.305067 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11589 11:56:16.308643 Test requirement: is_i915_device(fd)
11590 11:56:16.318516 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:
11591 11:56:16.321809 <14>[ 24.201604] [IGT] kms_atomic: executing
11592 11:56:16.328610 Test requirement<14>[ 24.207186] [IGT] kms_atomic: exiting, ret=77
11593 11:56:16.329170 : is_i915_device(fd)
11594 11:56:16.335471 No KMS driver or no outputs, pipes: 8, outputs: 0
11595 11:56:16.341680 [1mSub<8>[ 24.219133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11596 11:56:16.342529 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11598 11:56:16.344775 test addfb25-4-tiled: SKIP (0.000s)[0m
11599 11:56:16.351650 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11600 11:56:16.354458 Opened device: /dev/dri/card0
11601 11:56:16.358050 No KMS driver or no outputs, pipes: 8, outputs: 0
11602 11:56:16.364870 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11603 11:56:16.368084 IGT-Version<14>[ 24.249046] [IGT] kms_atomic: executing
11604 11:56:16.374544 : 1.27.1-g621c2d<14>[ 24.254313] [IGT] kms_atomic: exiting, ret=77
11605 11:56:16.378207 3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11606 11:56:16.381276 Opened device: /dev/dri/card0
11607 11:56:16.388012 No KMS <8>[ 24.266024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11608 11:56:16.388957 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11610 11:56:16.391293 driver or no outputs, pipes: 8, outputs: 0
11611 11:56:16.397727 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11612 11:56:16.404337 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: <14>[ 24.285417] [IGT] kms_atomic: executing
11613 11:56:16.411192 6.1.62-cip9 aarc<14>[ 24.290585] [IGT] kms_atomic: exiting, ret=77
11614 11:56:16.411757 h64)
11615 11:56:16.414427 Opened device: /dev/dri/card0
11616 11:56:16.424327 No KMS driver or no outputs, pipes: 8, outp<8>[ 24.302643] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11617 11:56:16.425237 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11619 11:56:16.427551 uts: 0
11620 11:56:16.431106 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11621 11:56:16.437714 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11622 11:56:16.440823 Opened device: /dev/dri/card0
11623 11:56:16.443966 No KMS driver or no outputs, pipes: 8, outputs: 0
11624 11:56:16.450905 [1mSubtest plane-immutable-zp<14>[ 24.332860] [IGT] kms_atomic: executing
11625 11:56:16.457399 os: SKIP (0.000s<14>[ 24.338176] [IGT] kms_atomic: exiting, ret=77
11626 11:56:16.457965 )[0m
11627 11:56:16.464176 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11628 11:56:16.473823 Open<8>[ 24.349226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11629 11:56:16.474383 ed device: /dev/dri/card0
11630 11:56:16.475031 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11632 11:56:16.480912 No KMS driver or no outputs, pipes: 8, outputs: 0
11633 11:56:16.484025 [1mSubtest test-only: SKIP (0.000s)[0m
11634 11:56:16.490391 IGT-Version: 1.27.1-g621c2d3 (aarch64) (<14>[ 24.370786] [IGT] kms_atomic: executing
11635 11:56:16.497117 Linux: 6.1.62-ci<14>[ 24.376739] [IGT] kms_atomic: exiting, ret=77
11636 11:56:16.497679 p9 aarch64)
11637 11:56:16.500349 Opened device: /dev/dri/card0
11638 11:56:16.503477 No KMS driver or no outputs, pipes: 8, outputs: 0
11639 11:56:16.513254 <8>[ 24.389593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11640 11:56:16.514079 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11642 11:56:16.516774 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11643 11:56:16.523467 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11644 11:56:16.526848 Opened device: /dev/dri/card0
11645 11:56:16.529918 No KMS driver or no outputs, pipes: 8, outputs: 0
11646 11:56:16.537109 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11647 11:56:16.540447 I<14>[ 24.420380] [IGT] kms_atomic: executing
11648 11:56:16.547086 GT-Version: 1.27<14>[ 24.426064] [IGT] kms_atomic: exiting, ret=77
11649 11:56:16.549934 .1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11650 11:56:16.559913 Opened device: /dev/dri/card<8>[ 24.437670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11651 11:56:16.560480 0
11652 11:56:16.561198 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11654 11:56:16.566594 No KMS driver or no outputs, pipes: 8, outputs: 0
11655 11:56:16.569781 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11656 11:56:16.576427 IGT-Version: 1.27.1-g621c2d3 (a<14>[ 24.457920] [IGT] kms_atomic: executing
11657 11:56:16.582666 arch64) (Linux: <14>[ 24.463120] [IGT] kms_atomic: exiting, ret=77
11658 11:56:16.586473 6.1.62-cip9 aarch64)
11659 11:56:16.589556 Opened device: /dev/dri/card0
11660 11:56:16.599666 No KMS driver or no outputs<8>[ 24.475233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11661 11:56:16.600236 , pipes: 8, outputs: 0
11662 11:56:16.600945 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11664 11:56:16.605807 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11665 11:56:16.612702 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11666 11:56:16.613163 Opened device: /dev/dri/card0
11667 11:56:16.619241 No KMS driver or no outputs, pipes: 8, outputs: 0
11668 11:56:16.625689 [1mSubtest crtc-invalid-para<14>[ 24.505704] [IGT] kms_atomic: executing
11669 11:56:16.632659 ms-fence: SKIP (<14>[ 24.511013] [IGT] kms_atomic: exiting, ret=77
11670 11:56:16.633266 0.000s)[0m
11671 11:56:16.645795 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)<8>[ 24.523190] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11672 11:56:16.646357
11673 11:56:16.647004 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11675 11:56:16.648986 Opened device: /dev/dri/card0
11676 11:56:16.652595 No KMS driver or no outputs, pipes: 8, outputs: 0
11677 11:56:16.658605 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11678 11:56:16.672764 <14>[ 24.552986] [IGT] kms_atomic: executing
11679 11:56:16.679086 IGT-Version: 1.2<14>[ 24.558116] [IGT] kms_atomic: exiting, ret=77
11680 11:56:16.682161 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11681 11:56:16.692446 Opened device: /dev/dri/car<8>[ 24.570554] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11682 11:56:16.693072 d0
11683 11:56:16.693726 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11685 11:56:16.698925 No KMS driver or no outputs,<8>[ 24.580496] <LAVA_SIGNAL_TESTSET STOP>
11686 11:56:16.699772 Received signal: <TESTSET> STOP
11687 11:56:16.700174 Closing test_set kms_atomic
11688 11:56:16.702169 pipes: 8, outputs: 0
11689 11:56:16.705701 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11690 11:56:16.730411 <8>[ 24.610786] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11691 11:56:16.731389 Received signal: <TESTSET> START kms_flip_event_leak
11692 11:56:16.731818 Starting test_set kms_flip_event_leak
11693 11:56:16.757003 <14>[ 24.637421] [IGT] kms_flip_event_leak: executing
11694 11:56:16.763499 IGT-Version: 1.2<14>[ 24.642990] [IGT] kms_flip_event_leak: exiting, ret=77
11695 11:56:16.770191 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11696 11:56:16.776781 Opened device: /dev/dri/car<8>[ 24.655141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11697 11:56:16.777344 d0
11698 11:56:16.777995 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11700 11:56:16.782932 No KMS driver or no outputs,<8>[ 24.664306] <LAVA_SIGNAL_TESTSET STOP>
11701 11:56:16.783662 Received signal: <TESTSET> STOP
11702 11:56:16.784061 Closing test_set kms_flip_event_leak
11703 11:56:16.786638 pipes: 8, outputs: 0
11704 11:56:16.789997 [1mSubtest basic: SKIP (0.000s)[0m
11705 11:56:16.803009 <8>[ 24.683798] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11706 11:56:16.803872 Received signal: <TESTSET> START kms_prop_blob
11707 11:56:16.804336 Starting test_set kms_prop_blob
11708 11:56:16.819324 <14>[ 24.699668] [IGT] kms_prop_blob: executing
11709 11:56:16.826177 IGT-Version: 1.2<14>[ 24.704562] [IGT] kms_prop_blob: starting subtest basic
11710 11:56:16.832771 7.1-g621c2d3 (aa<14>[ 24.711217] [IGT] kms_prop_blob: finished subtest basic, SUCCESS
11711 11:56:16.839179 <14>[ 24.719008] [IGT] kms_prop_blob: exiting, ret=0
11712 11:56:16.841995 rch64) (Linux: 6.1.62-cip9 aarch64)
11713 11:56:16.845639 Opened device: /dev/dri/card0
11714 11:56:16.846219 Starting subtest: basic
11715 11:56:16.852318 [1<8>[ 24.730849] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11716 11:56:16.853211 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11718 11:56:16.855024 mSubtest basic: SUCCESS (0.000s)[0m
11719 11:56:16.879935 <14>[ 24.760452] [IGT] kms_prop_blob: executing
11720 11:56:16.886588 IGT-Version: 1.2<14>[ 24.765536] [IGT] kms_prop_blob: starting subtest blob-prop-core
11721 11:56:16.896362 7.1-g621c2d3 (aa<14>[ 24.773141] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS
11722 11:56:16.902707 rch64) (Linux: 6<14>[ 24.781644] [IGT] kms_prop_blob: exiting, ret=0
11723 11:56:16.903282 .1.62-cip9 aarch64)
11724 11:56:16.906037 Opened device: /dev/dri/card0
11725 11:56:16.915972 Starting subtest: blob-prop-<8>[ 24.794802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11726 11:56:16.916617 core
11727 11:56:16.917278 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11729 11:56:16.922820 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11730 11:56:16.942791 <14>[ 24.823502] [IGT] kms_prop_blob: executing
11731 11:56:16.949565 IGT-Version: 1.2<14>[ 24.828566] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11732 11:56:16.959789 7.1-g621c2d3 (aa<14>[ 24.836519] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS
11733 11:56:16.966387 rch64) (Linux: 6<14>[ 24.845259] [IGT] kms_prop_blob: exiting, ret=0
11734 11:56:16.969251 .1.62-cip9 aarch64)
11735 11:56:16.969722 Opened device: /dev/dri/card0
11736 11:56:16.972668 Starting subtest: blob-prop-validate
11737 11:56:16.982576 [1mSu<8>[ 24.858508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11738 11:56:16.983515 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11740 11:56:16.985912 btest blob-prop-validate: SUCCESS (0.000s)[0m
11741 11:56:17.008252 <14>[ 24.889167] [IGT] kms_prop_blob: executing
11742 11:56:17.015121 IGT-Version: 1.2<14>[ 24.894231] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
11743 11:56:17.025102 7.1-g621c2d3 (aa<14>[ 24.902261] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS
11744 11:56:17.031681 rch64) (Linux: 6<14>[ 24.911055] [IGT] kms_prop_blob: exiting, ret=0
11745 11:56:17.034954 .1.62-cip9 aarch64)
11746 11:56:17.035565 Opened device: /dev/dri/card0
11747 11:56:17.044942 Starting subtest: blob-prop-<8>[ 24.924056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
11748 11:56:17.045827 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11750 11:56:17.048147 lifetime
11751 11:56:17.051570 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
11752 11:56:17.072827 <14>[ 24.953627] [IGT] kms_prop_blob: executing
11753 11:56:17.079556 IGT-Version: 1.2<14>[ 24.958608] [IGT] kms_prop_blob: starting subtest blob-multiple
11754 11:56:17.089462 7.1-g621c2d3 (aa<14>[ 24.966270] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS
11755 11:56:17.096744 rch64) (Linux: 6<14>[ 24.974588] [IGT] kms_prop_blob: exiting, ret=0
11756 11:56:17.097310 .1.62-cip9 aarch64)
11757 11:56:17.099274 Opened device: /dev/dri/card0
11758 11:56:17.109299 Starting subtest: blob-multi<8>[ 24.987734] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
11759 11:56:17.109882 ple
11760 11:56:17.110537 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
11762 11:56:17.112311 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
11763 11:56:17.136200 <14>[ 25.016692] [IGT] kms_prop_blob: executing
11764 11:56:17.142777 IGT-Version: 1.2<14>[ 25.021655] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
11765 11:56:17.152808 7.1-g621c2d3 (aa<14>[ 25.029799] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS
11766 11:56:17.159486 rch64) (Linux: 6<14>[ 25.038833] [IGT] kms_prop_blob: exiting, ret=0
11767 11:56:17.162982 .1.62-cip9 aarch64)
11768 11:56:17.163547 Opened device: /dev/dri/card0
11769 11:56:17.172601 Starting subtest: invalid-ge<8>[ 25.051951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11770 11:56:17.173425 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11772 11:56:17.175713 t-prop-any
11773 11:56:17.179082 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
11774 11:56:17.200789 <14>[ 25.081452] [IGT] kms_prop_blob: executing
11775 11:56:17.207419 IGT-Version: 1.2<14>[ 25.086494] [IGT] kms_prop_blob: starting subtest invalid-get-prop
11776 11:56:17.217169 7.1-g621c2d3 (aa<14>[ 25.094250] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS
11777 11:56:17.223763 rch64) (Linux: 6<14>[ 25.102937] [IGT] kms_prop_blob: exiting, ret=0
11778 11:56:17.224228 .1.62-cip9 aarch64)
11779 11:56:17.227239 Opened device: /dev/dri/card0
11780 11:56:17.237082 Starting subtest: invalid-ge<8>[ 25.115943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11781 11:56:17.237637 t-prop
11782 11:56:17.238283 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11784 11:56:17.243816 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
11785 11:56:17.264740 <14>[ 25.144977] [IGT] kms_prop_blob: executing
11786 11:56:17.270840 IGT-Version: 1.2<14>[ 25.150019] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
11787 11:56:17.280809 7.1-g621c2d3 (aa<14>[ 25.158116] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS
11788 11:56:17.287576 rch64) (Linux: 6<14>[ 25.167151] [IGT] kms_prop_blob: exiting, ret=0
11789 11:56:17.290681 .1.62-cip9 aarch64)
11790 11:56:17.293990 Opened device: /dev/dri/card0
11791 11:56:17.303615 Starting subtest: invalid-se<8>[ 25.180166] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11792 11:56:17.304209 t-prop-any
11793 11:56:17.304973 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11795 11:56:17.306751 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
11796 11:56:17.329089 <14>[ 25.209633] [IGT] kms_prop_blob: executing
11797 11:56:17.335909 IGT-Version: 1.2<14>[ 25.214689] [IGT] kms_prop_blob: starting subtest invalid-set-prop
11798 11:56:17.345574 7.1-g621c2d3 (aa<14>[ 25.222423] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS
11799 11:56:17.352291 rch64) (Linux: 6<14>[ 25.231111] [IGT] kms_prop_blob: exiting, ret=0
11800 11:56:17.352921 .1.62-cip9 aarch64)
11801 11:56:17.355808 Opened device: /dev/dri/card0
11802 11:56:17.365377 Starting subtest: invalid-se<8>[ 25.244092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11803 11:56:17.366041 t-prop
11804 11:56:17.366704 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11806 11:56:17.372085 [1mSubtest invalid-set-<8>[ 25.253553] <LAVA_SIGNAL_TESTSET STOP>
11807 11:56:17.372980 Received signal: <TESTSET> STOP
11808 11:56:17.373375 Closing test_set kms_prop_blob
11809 11:56:17.375165 prop: SUCCESS (0.000s)[0m
11810 11:56:17.403137 <8>[ 25.283923] <LAVA_SIGNAL_TESTSET START kms_setmode>
11811 11:56:17.403982 Received signal: <TESTSET> START kms_setmode
11812 11:56:17.404379 Starting test_set kms_setmode
11813 11:56:17.420316 <14>[ 25.300780] [IGT] kms_setmode: executing
11814 11:56:17.426837 IGT-Version: 1.2<14>[ 25.305416] [IGT] kms_setmode: starting subtest basic
11815 11:56:17.433335 7.1-g621c2d3 (aa<14>[ 25.312026] [IGT] kms_setmode: finished subtest basic, SKIP
11816 11:56:17.440141 <14>[ 25.319371] [IGT] kms_setmode: exiting, ret=77
11817 11:56:17.442955 rch64) (Linux: 6.1.62-cip9 aarch64)
11818 11:56:17.443417 Opened device: /dev/dri/card0
11819 11:56:17.453181 Starting sub<8>[ 25.330056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11820 11:56:17.453743 test: basic
11821 11:56:17.454450 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11823 11:56:17.456124 No dynamic tests executed.
11824 11:56:17.459865 [1mSubtest basic: SKIP (0.000s)[0m
11825 11:56:17.468742 <14>[ 25.349272] [IGT] kms_setmode: executing
11826 11:56:17.475234 IGT-Version: 1.2<14>[ 25.353983] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
11827 11:56:17.485233 7.1-g621c2d3 (aa<14>[ 25.362281] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP
11828 11:56:17.491651 <14>[ 25.371101] [IGT] kms_setmode: exiting, ret=77
11829 11:56:17.494868 rch64) (Linux: 6.1.62-cip9 aarch64)
11830 11:56:17.495432 Opened device: /dev/dri/card0
11831 11:56:17.505254 Starting sub<8>[ 25.381904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
11832 11:56:17.506158 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
11834 11:56:17.508096 test: basic-clone-single-crtc
11835 11:56:17.511261 No dynamic tests executed.
11836 11:56:17.514703 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
11837 11:56:17.521330 <14>[ 25.402198] [IGT] kms_setmode: executing
11838 11:56:17.528563 IGT-Version: 1.2<14>[ 25.406811] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
11839 11:56:17.538023 7.1-g621c2d3 (aa<14>[ 25.415190] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP
11840 11:56:17.544770 <14>[ 25.424257] [IGT] kms_setmode: exiting, ret=77
11841 11:56:17.548250 rch64) (Linux: 6.1.62-cip9 aarch64)
11842 11:56:17.548886 Opened device: /dev/dri/card0
11843 11:56:17.557691 Starting sub<8>[ 25.434882] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
11844 11:56:17.558537 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
11846 11:56:17.561025 test: invalid-clone-single-crtc
11847 11:56:17.564828 No dynamic tests executed.
11848 11:56:17.567991 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
11849 11:56:17.574841 <14>[ 25.455359] [IGT] kms_setmode: executing
11850 11:56:17.581440 IGT-Version: 1.2<14>[ 25.459962] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
11851 11:56:17.591374 7.1-g621c2d3 (aa<14>[ 25.468665] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP
11852 11:56:17.597722 <14>[ 25.477952] [IGT] kms_setmode: exiting, ret=77
11853 11:56:17.601391 rch64) (Linux: 6.1.62-cip9 aarch64)
11854 11:56:17.610827 Opened device: /dev/dri/car<8>[ 25.488085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
11855 11:56:17.611376 d0
11856 11:56:17.612017 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
11858 11:56:17.614026 Starting subtest: invalid-clone-exclusive-crtc
11859 11:56:17.617907 No dynamic tests executed.
11860 11:56:17.624198 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
11861 11:56:17.627496 <14>[ 25.507904] [IGT] kms_setmode: executing
11862 11:56:17.637238 IGT-Version: 1.2<14>[ 25.513619] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
11863 11:56:17.644165 7.1-g621c2d3 (aa<14>[ 25.521572] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP
11864 11:56:17.650354 <14>[ 25.530218] [IGT] kms_setmode: exiting, ret=77
11865 11:56:17.653862 rch64) (Linux: 6.1.62-cip9 aarch64)
11866 11:56:17.654420 Opened device: /dev/dri/card0
11867 11:56:17.664023 Starting sub<8>[ 25.540742] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
11868 11:56:17.664916 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
11870 11:56:17.667463 test: clone-exclusive-crtc
11871 11:56:17.670709 No dynamic tests executed.
11872 11:56:17.673564 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
11873 11:56:17.680384 <14>[ 25.560856] [IGT] kms_setmode: executing
11874 11:56:17.690326 IGT-Version: 1.2<14>[ 25.565444] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
11875 11:56:17.699970 7.1-g621c2d3 (aa<14>[ 25.574626] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP
11876 11:56:17.703378 <14>[ 25.584482] [IGT] kms_setmode: exiting, ret=77
11877 11:56:17.706386 rch64) (Linux: 6.1.62-cip9 aarch64)
11878 11:56:17.716262 Opened devi<8>[ 25.593382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
11879 11:56:17.717155 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
11881 11:56:17.723186 ce: /dev/dri/car<8>[ 25.603697] <LAVA_SIGNAL_TESTSET STOP>
11882 11:56:17.723753 d0
11883 11:56:17.724423 Received signal: <TESTSET> STOP
11884 11:56:17.724859 Closing test_set kms_setmode
11885 11:56:17.726166 Starting subtest: invalid-clone-single-crtc-stealing
11886 11:56:17.729550 No dynamic tests executed.
11887 11:56:17.736144 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
11888 11:56:17.739519 <8>[ 25.621097] <LAVA_SIGNAL_TESTSET START kms_vblank>
11889 11:56:17.740368 Received signal: <TESTSET> START kms_vblank
11890 11:56:17.740856 Starting test_set kms_vblank
11891 11:56:17.758933 <14>[ 25.639407] [IGT] kms_vblank: executing
11892 11:56:17.765451 IGT-Version: 1.2<14>[ 25.644340] [IGT] kms_vblank: exiting, ret=77
11893 11:56:17.768750 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11894 11:56:17.775621 Opened devi<8>[ 25.654347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
11895 11:56:17.776473 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
11897 11:56:17.778795 ce: /dev/dri/card0
11898 11:56:17.781927 No KMS driver or no outputs, pipes: 8, outputs: 0
11899 11:56:17.785265 [1mSubtest invalid: SKIP (0.000s)[0m
11900 11:56:17.792499 <14>[ 25.673199] [IGT] kms_vblank: executing
11901 11:56:17.799298 IGT-Version: 1.2<14>[ 25.677865] [IGT] kms_vblank: exiting, ret=77
11902 11:56:17.802402 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11903 11:56:17.812721 Opened device: /dev/dri/car<8>[ 25.689484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
11904 11:56:17.813308 d0
11905 11:56:17.813961 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
11907 11:56:17.815502 No KMS driver or no outputs, pipes: 8, outputs: 0
11908 11:56:17.818715 [1mSubtest crtc-id: SKIP (0.000s)[0m
11909 11:56:17.827953 <14>[ 25.708547] [IGT] kms_vblank: executing
11910 11:56:17.834782 IGT-Version: 1.2<14>[ 25.713200] [IGT] kms_vblank: exiting, ret=77
11911 11:56:17.837928 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11912 11:56:17.847803 Opened device: /dev/dri/car<8>[ 25.724529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
11913 11:56:17.848377 d0
11914 11:56:17.849086 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
11916 11:56:17.854194 No KMS driver or no outputs, pipes: 8, outputs: 0
11917 11:56:17.857976 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
11918 11:56:17.864470 <14>[ 25.744912] [IGT] kms_vblank: executing
11919 11:56:17.871014 IGT-Version: 1.2<14>[ 25.749563] [IGT] kms_vblank: exiting, ret=77
11920 11:56:17.874189 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11921 11:56:17.884091 Opened device: /dev/dri/car<8>[ 25.760954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
11922 11:56:17.884701 d0
11923 11:56:17.885367 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
11925 11:56:17.887387 No KMS driver or no outputs, pipes: 8, outputs: 0
11926 11:56:17.893973 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
11927 11:56:17.900714 <14>[ 25.781257] [IGT] kms_vblank: executing
11928 11:56:17.907102 IGT-Version: 1.2<14>[ 25.785963] [IGT] kms_vblank: exiting, ret=77
11929 11:56:17.910437 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11930 11:56:17.920856 Opened device: /dev/dri/car<8>[ 25.797549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
11931 11:56:17.921433 d0
11932 11:56:17.922081 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
11934 11:56:17.927360 No KMS driver or no outputs, pipes: 8, outputs: 0
11935 11:56:17.930616 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
11936 11:56:17.937006 <14>[ 25.817884] [IGT] kms_vblank: executing
11937 11:56:17.943769 IGT-Version: 1.2<14>[ 25.822632] [IGT] kms_vblank: exiting, ret=77
11938 11:56:17.946916 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11939 11:56:17.957110 Opened devi<8>[ 25.832922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
11940 11:56:17.957673 ce: /dev/dri/card0
11941 11:56:17.958319 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
11943 11:56:17.963473 No KMS driver or no outputs, pipes: 8, outputs: 0
11944 11:56:17.967049 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
11945 11:56:17.970250 <14>[ 25.851764] [IGT] kms_vblank: executing
11946 11:56:17.977275 IGT-Version: 1.2<14>[ 25.856836] [IGT] kms_vblank: exiting, ret=77
11947 11:56:17.979939 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11948 11:56:17.990380 Opened devi<8>[ 25.868171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
11949 11:56:17.991241 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
11951 11:56:17.993290 ce: /dev/dri/card0
11952 11:56:17.996964 No KMS driver or no outputs, pipes: 8, outputs: 0
11953 11:56:18.003336 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
11954 11:56:18.006893 <14>[ 25.887569] [IGT] kms_vblank: executing
11955 11:56:18.013442 IGT-Version: 1.2<14>[ 25.892282] [IGT] kms_vblank: exiting, ret=77
11956 11:56:18.016617 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11957 11:56:18.026143 Opened devi<8>[ 25.902213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
11958 11:56:18.026468 ce: /dev/dri/card0
11959 11:56:18.026958 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
11961 11:56:18.029345 No KMS driver or no outputs, pipes: 8, outputs: 0
11962 11:56:18.036707 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
11963 11:56:18.039777 <14>[ 25.920956] [IGT] kms_vblank: executing
11964 11:56:18.045866 IGT-Version: 1.2<14>[ 25.926119] [IGT] kms_vblank: exiting, ret=77
11965 11:56:18.049824 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11966 11:56:18.059367 Opened device: /dev/dri/car<8>[ 25.937844] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
11967 11:56:18.060124 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
11969 11:56:18.062643 d0
11970 11:56:18.065986 No KMS driver or no outputs, pipes: 8, outputs: 0
11971 11:56:18.069219 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
11972 11:56:18.077262 <14>[ 25.958171] [IGT] kms_vblank: executing
11973 11:56:18.083795 IGT-Version: 1.2<14>[ 25.962880] [IGT] kms_vblank: exiting, ret=77
11974 11:56:18.087030 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11975 11:56:18.097219 Opened devi<8>[ 25.973032] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
11976 11:56:18.097798 ce: /dev/dri/card0
11977 11:56:18.098451 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
11979 11:56:18.104048 No KMS driver or no outputs, pipes: 8, outputs: 0
11980 11:56:18.107111 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
11981 11:56:18.110728 <14>[ 25.992324] [IGT] kms_vblank: executing
11982 11:56:18.116634 IGT-Version: 1.2<14>[ 25.998003] [IGT] kms_vblank: exiting, ret=77
11983 11:56:18.123309 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11984 11:56:18.133502 Opened device: /dev/dri/car<8>[ 26.009654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
11985 11:56:18.134076 d0
11986 11:56:18.134732 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
11988 11:56:18.137236 No KMS driver or no outputs, pipes: 8, outputs: 0
11989 11:56:18.143699 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
11990 11:56:18.150349 <14>[ 26.030466] [IGT] kms_vblank: executing
11991 11:56:18.156829 IGT-Version: 1.2<14>[ 26.035113] [IGT] kms_vblank: exiting, ret=77
11992 11:56:18.159967 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
11993 11:56:18.166925 Opened devi<8>[ 26.045255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
11994 11:56:18.167749 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
11996 11:56:18.169855 ce: /dev/dri/card0
11997 11:56:18.173339 No KMS driver or no outputs, pipes: 8, outputs: 0
11998 11:56:18.179901 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
11999 11:56:18.183566 <14>[ 26.063707] [IGT] kms_vblank: executing
12000 11:56:18.190022 IGT-Version: 1.2<14>[ 26.068891] [IGT] kms_vblank: exiting, ret=77
12001 11:56:18.193152 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12002 11:56:18.203494 Opened devi<8>[ 26.079194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12003 11:56:18.204059 ce: /dev/dri/card0
12004 11:56:18.204715 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12006 11:56:18.210200 No KMS driver or no outputs, pipes: 8, outputs: 0
12007 11:56:18.213130 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12008 11:56:18.222771 <14>[ 26.103289] [IGT] kms_vblank: executing
12009 11:56:18.229448 IGT-Version: 1.2<14>[ 26.107987] [IGT] kms_vblank: exiting, ret=77
12010 11:56:18.232710 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12011 11:56:18.242678 Opened devi<8>[ 26.118108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12012 11:56:18.243253 ce: /dev/dri/card0
12013 11:56:18.243908 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12015 11:56:18.245566 No KMS driver or no outputs, pipes: 8, outputs: 0
12016 11:56:18.252423 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12017 11:56:18.255937 <14>[ 26.137909] [IGT] kms_vblank: executing
12018 11:56:18.262173 IGT-Version: 1.2<14>[ 26.142586] [IGT] kms_vblank: exiting, ret=77
12019 11:56:18.265714 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12020 11:56:18.275545 Opened devi<8>[ 26.152733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12021 11:56:18.276390 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12023 11:56:18.279146 ce: /dev/dri/card0
12024 11:56:18.282499 No KMS driver or no outputs, pipes: 8, outputs: 0
12025 11:56:18.288699 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12026 11:56:18.291946 <14>[ 26.171778] [IGT] kms_vblank: executing
12027 11:56:18.298667 IGT-Version: 1.2<14>[ 26.177599] [IGT] kms_vblank: exiting, ret=77
12028 11:56:18.301810 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12029 11:56:18.312229 Opened device: /dev/dri/car<8>[ 26.188988] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12030 11:56:18.312835 d0
12031 11:56:18.313490 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12033 11:56:18.315044 No KMS driver or no outputs, pipes: 8, outputs: 0
12034 11:56:18.321416 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12035 11:56:18.328666 <14>[ 26.209156] [IGT] kms_vblank: executing
12036 11:56:18.335120 IGT-Version: 1.2<14>[ 26.213828] [IGT] kms_vblank: exiting, ret=77
12037 11:56:18.338627 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12038 11:56:18.348688 Opened device: /dev/dri/car<8>[ 26.225385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12039 11:56:18.349252 d0
12040 11:56:18.349898 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12042 11:56:18.354975 No KMS driver or no outputs, pipes: 8, outputs: 0
12043 11:56:18.358446 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12044 11:56:18.365000 <14>[ 26.245632] [IGT] kms_vblank: executing
12045 11:56:18.371564 IGT-Version: 1.2<14>[ 26.250264] [IGT] kms_vblank: exiting, ret=77
12046 11:56:18.374990 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12047 11:56:18.385065 Opened devi<8>[ 26.260372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12048 11:56:18.385626 ce: /dev/dri/card0
12049 11:56:18.386276 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12051 11:56:18.391608 No KMS driver or no outputs, pipes: 8, outputs: 0
12052 11:56:18.394516 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12053 11:56:18.398058 <14>[ 26.279610] [IGT] kms_vblank: executing
12054 11:56:18.405000 IGT-Version: 1.2<14>[ 26.285424] [IGT] kms_vblank: exiting, ret=77
12055 11:56:18.411657 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12056 11:56:18.421152 Opened device: /dev/dri/car<8>[ 26.297011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12057 11:56:18.421710 d0
12058 11:56:18.422365 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12060 11:56:18.424243 No KMS driver or no outputs, pipes: 8, outputs: 0
12061 11:56:18.431124 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12062 11:56:18.437914 <14>[ 26.318040] [IGT] kms_vblank: executing
12063 11:56:18.444213 IGT-Version: 1.2<14>[ 26.322751] [IGT] kms_vblank: exiting, ret=77
12064 11:56:18.447790 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12065 11:56:18.457507 Opened device: /dev/dri/car<8>[ 26.334130] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12066 11:56:18.458069 d0
12067 11:56:18.458714 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12069 11:56:18.464293 No KMS driver or no outputs, pipes: 8, outputs: 0
12070 11:56:18.467688 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12071 11:56:18.474057 <14>[ 26.354820] [IGT] kms_vblank: executing
12072 11:56:18.480771 IGT-Version: 1.2<14>[ 26.359477] [IGT] kms_vblank: exiting, ret=77
12073 11:56:18.483726 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12074 11:56:18.494059 Opened devi<8>[ 26.369483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12075 11:56:18.494919 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12077 11:56:18.497113 ce: /dev/dri/card0
12078 11:56:18.500466 No KMS driver or no outputs, pipes: 8, outputs: 0
12079 11:56:18.510354 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000<14>[ 26.389631] [IGT] kms_vblank: executing
12080 11:56:18.510922 s)[0m
12081 11:56:18.513693 <14>[ 26.395332] [IGT] kms_vblank: exiting, ret=77
12082 11:56:18.527352 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12084 11:56:18.530351 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 26.405772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12085 11:56:18.530909 64)
12086 11:56:18.533318 Opened device: /dev/dri/card0
12087 11:56:18.537034 No KMS driver or no outputs, pipes: 8, outputs: 0
12088 11:56:18.546960 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s<14>[ 26.426188] [IGT] kms_vblank: executing
12089 11:56:18.547541 )[0m
12090 11:56:18.550179 <14>[ 26.431766] [IGT] kms_vblank: exiting, ret=77
12091 11:56:18.556807 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12092 11:56:18.566794 Opened devi<8>[ 26.442339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12093 11:56:18.567635 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12095 11:56:18.570185 ce: /dev/dri/card0
12096 11:56:18.573439 No KMS driver or no outputs, pipes: 8, outputs: 0
12097 11:56:18.580179 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12098 11:56:18.583454 <14>[ 26.464087] [IGT] kms_vblank: executing
12099 11:56:18.590076 IGT-Version: 1.2<14>[ 26.469470] [IGT] kms_vblank: exiting, ret=77
12100 11:56:18.593233 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12101 11:56:18.603435 Opened devi<8>[ 26.479382] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12102 11:56:18.604275 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12104 11:56:18.606236 ce: /dev/dri/card0
12105 11:56:18.609491 No KMS driver or no outputs, pipes: 8, outputs: 0
12106 11:56:18.619540 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)<14>[ 26.499206] [IGT] kms_vblank: executing
12107 11:56:18.620083 [0m
12108 11:56:18.623000 <14>[ 26.505131] [IGT] kms_vblank: exiting, ret=77
12109 11:56:18.629789 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12110 11:56:18.639835 Opened devi<8>[ 26.515689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12111 11:56:18.640654 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12113 11:56:18.642592 ce: /dev/dri/card0
12114 11:56:18.646471 No KMS driver or no outputs, pipes: 8, outputs: 0
12115 11:56:18.652999 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12116 11:56:18.656242 <14>[ 26.537170] [IGT] kms_vblank: executing
12117 11:56:18.662525 IGT-Version: 1.2<14>[ 26.541821] [IGT] kms_vblank: exiting, ret=77
12118 11:56:18.666098 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12119 11:56:18.676302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12121 11:56:18.679637 Opened device: /dev/dri/car<8>[ 26.553311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12122 11:56:18.680193 d0
12123 11:56:18.682822 No KMS driver or no outputs, pipes: 8, outputs: 0
12124 11:56:18.689455 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12125 11:56:18.692750 <14>[ 26.574958] [IGT] kms_vblank: executing
12126 11:56:18.699373 IGT-Version: 1.2<14>[ 26.579696] [IGT] kms_vblank: exiting, ret=77
12127 11:56:18.712448 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 26.589461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12128 11:56:18.713086 64)
12129 11:56:18.713752 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12131 11:56:18.715558 Opened device: /dev/dri/card0
12132 11:56:18.718742 No KMS driver or no outputs, pipes: 8, outputs: 0
12133 11:56:18.725288 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12134 11:56:18.733338 <14>[ 26.614223] [IGT] kms_vblank: executing
12135 11:56:18.740262 IGT-Version: 1.2<14>[ 26.618909] [IGT] kms_vblank: exiting, ret=77
12136 11:56:18.743422 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12137 11:56:18.753456 Opened devi<8>[ 26.629043] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12138 11:56:18.754017 ce: /dev/dri/card0
12139 11:56:18.754659 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12141 11:56:18.756441 No KMS driver or no outputs, pipes: 8, outputs: 0
12142 11:56:18.763284 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12143 11:56:18.771857 <14>[ 26.652584] [IGT] kms_vblank: executing
12144 11:56:18.778407 IGT-Version: 1.2<14>[ 26.657288] [IGT] kms_vblank: exiting, ret=77
12145 11:56:18.782088 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12146 11:56:18.791970 Opened devi<8>[ 26.667211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12147 11:56:18.792576 ce: /dev/dri/card0
12148 11:56:18.793237 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12150 11:56:18.795003 No KMS driver or no outputs, pipes: 8, outputs: 0
12151 11:56:18.802175 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12152 11:56:18.805195 <14>[ 26.687288] [IGT] kms_vblank: executing
12153 11:56:18.811650 IGT-Version: 1.2<14>[ 26.691991] [IGT] kms_vblank: exiting, ret=77
12154 11:56:18.815274 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12155 11:56:18.824701 Opened devi<8>[ 26.702036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12156 11:56:18.825453 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12158 11:56:18.828309 ce: /dev/dri/card0
12159 11:56:18.831526 No KMS driver or no outputs, pipes: 8, outputs: 0
12160 11:56:18.834881 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12161 11:56:18.841367 <14>[ 26.722124] [IGT] kms_vblank: executing
12162 11:56:18.848038 IGT-Version: 1.2<14>[ 26.726808] [IGT] kms_vblank: exiting, ret=77
12163 11:56:18.851325 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12164 11:56:18.858707 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12166 11:56:18.861648 Opened devi<8>[ 26.738068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12167 11:56:18.862210 ce: /dev/dri/card0
12168 11:56:18.865193 No KMS driver or no outputs, pipes: 8, outputs: 0
12169 11:56:18.871581 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12170 11:56:18.875120 <14>[ 26.757177] [IGT] kms_vblank: executing
12171 11:56:18.881462 IGT-Version: 1.2<14>[ 26.761809] [IGT] kms_vblank: exiting, ret=77
12172 11:56:18.888402 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12173 11:56:18.898058 Opened device: /dev/dri/car<8>[ 26.773350] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12174 11:56:18.898621 d0
12175 11:56:18.899269 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12177 11:56:18.900903 No KMS driver or no outputs, pipes: 8, outputs: 0
12178 11:56:18.907668 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12179 11:56:18.911300 <14>[ 26.794013] [IGT] kms_vblank: executing
12180 11:56:18.918005 IGT-Version: 1.2<14>[ 26.798656] [IGT] kms_vblank: exiting, ret=77
12181 11:56:18.924617 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12182 11:56:18.930860 Opened devi<8>[ 26.809960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12183 11:56:18.931687 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12185 11:56:18.934285 ce: /dev/dri/card0
12186 11:56:18.937382 No KMS driver or no outputs, pipes: 8, outputs: 0
12187 11:56:18.940591 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12188 11:56:18.948295 <14>[ 26.828763] [IGT] kms_vblank: executing
12189 11:56:18.954542 IGT-Version: 1.2<14>[ 26.833388] [IGT] kms_vblank: exiting, ret=77
12190 11:56:18.958668 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12191 11:56:18.967963 Opened device: /dev/dri/car<8>[ 26.844979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12192 11:56:18.968596 d0
12193 11:56:18.969440 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12195 11:56:18.974690 No KMS driver or no outputs, pipes: 8, outputs: 0
12196 11:56:18.977677 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12197 11:56:18.984784 <14>[ 26.865498] [IGT] kms_vblank: executing
12198 11:56:18.991451 IGT-Version: 1.2<14>[ 26.870131] [IGT] kms_vblank: exiting, ret=77
12199 11:56:18.994795 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12200 11:56:19.004652 Opened device: /dev/dri/car<8>[ 26.881902] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12201 11:56:19.005213 d0
12202 11:56:19.005868 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12204 11:56:19.011436 No KMS driver or no outputs, pipes: 8, outputs: 0
12205 11:56:19.014804 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12206 11:56:19.021313 <14>[ 26.902247] [IGT] kms_vblank: executing
12207 11:56:19.028099 IGT-Version: 1.2<14>[ 26.907064] [IGT] kms_vblank: exiting, ret=77
12208 11:56:19.031638 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12209 11:56:19.041349 Opened devi<8>[ 26.917214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12210 11:56:19.041914 ce: /dev/dri/card0
12211 11:56:19.042574 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12213 11:56:19.047837 No KMS driver or no outputs, pipes: 8, outputs: 0
12214 11:56:19.057498 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)<14>[ 26.936806] [IGT] kms_vblank: executing
12215 11:56:19.058044 [0m
12216 11:56:19.064491 IGT-Version: 1.2<14>[ 26.942654] [IGT] kms_vblank: exiting, ret=77
12217 11:56:19.067540 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12218 11:56:19.077474 Opened device: /dev/dri/car<8>[ 26.954497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12219 11:56:19.078054 d0
12220 11:56:19.078715 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12222 11:56:19.080802 No KMS driver or no outputs, pipes: 8, outputs: 0
12223 11:56:19.087566 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12224 11:56:19.094003 <14>[ 26.974193] [IGT] kms_vblank: executing
12225 11:56:19.097682 IGT-Version: 1.2<14>[ 26.978840] [IGT] kms_vblank: exiting, ret=77
12226 11:56:19.104004 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12227 11:56:19.110719 Opened devi<8>[ 26.989010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12228 11:56:19.111546 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12230 11:56:19.113931 ce: /dev/dri/card0
12231 11:56:19.117467 No KMS driver or no outputs, pipes: 8, outputs: 0
12232 11:56:19.124343 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12233 11:56:19.127552 <14>[ 27.008168] [IGT] kms_vblank: executing
12234 11:56:19.134089 IGT-Version: 1.2<14>[ 27.013538] [IGT] kms_vblank: exiting, ret=77
12235 11:56:19.138005 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12236 11:56:19.147528 Opened devi<8>[ 27.023791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12237 11:56:19.148092 ce: /dev/dri/card0
12238 11:56:19.148740 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12240 11:56:19.153771 No KMS driver or no outputs, pipes: 8, outputs: 0
12241 11:56:19.157458 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12242 11:56:19.160447 <14>[ 27.043271] [IGT] kms_vblank: executing
12243 11:56:19.167590 IGT-Version: 1.2<14>[ 27.047927] [IGT] kms_vblank: exiting, ret=77
12244 11:56:19.173957 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12245 11:56:19.180613 Opened devi<8>[ 27.057906] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12246 11:56:19.181451 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12248 11:56:19.183680 ce: /dev/dri/card0
12249 11:56:19.187083 No KMS driver or no outputs, pipes: 8, outputs: 0
12250 11:56:19.193558 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12251 11:56:19.196906 <14>[ 27.077728] [IGT] kms_vblank: executing
12252 11:56:19.203597 IGT-Version: 1.2<14>[ 27.082995] [IGT] kms_vblank: exiting, ret=77
12253 11:56:19.206958 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12254 11:56:19.217120 Opened devi<8>[ 27.094302] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12255 11:56:19.217684 ce: /dev/dri/card0
12256 11:56:19.218329 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12258 11:56:19.223441 No KMS driver or no outputs, pipes: 8, outputs: 0
12259 11:56:19.227034 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12260 11:56:19.229927 <14>[ 27.113040] [IGT] kms_vblank: executing
12261 11:56:19.236435 IGT-Version: 1.2<14>[ 27.117679] [IGT] kms_vblank: exiting, ret=77
12262 11:56:19.243498 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12263 11:56:19.253154 Opened device: /dev/dri/car<8>[ 27.129072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12264 11:56:19.253718 d0
12265 11:56:19.254365 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12267 11:56:19.256634 No KMS driver or no outputs, pipes: 8, outputs: 0
12268 11:56:19.263483 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12269 11:56:19.266638 <14>[ 27.149324] [IGT] kms_vblank: executing
12270 11:56:19.273221 IGT-Version: 1.2<14>[ 27.153982] [IGT] kms_vblank: exiting, ret=77
12271 11:56:19.279760 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12272 11:56:19.289693 Opened device: /dev/dri/car<8>[ 27.165500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12273 11:56:19.290294 d0
12274 11:56:19.290945 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12276 11:56:19.292993 No KMS driver or no outputs, pipes: 8, outputs: 0
12277 11:56:19.299689 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12278 11:56:19.302678 <14>[ 27.186199] [IGT] kms_vblank: executing
12279 11:56:19.309575 IGT-Version: 1.2<14>[ 27.190887] [IGT] kms_vblank: exiting, ret=77
12280 11:56:19.316481 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12281 11:56:19.322935 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12283 11:56:19.326333 Opened devi<8>[ 27.201016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12284 11:56:19.326890 ce: /dev/dri/card0
12285 11:56:19.329795 No KMS driver or no outputs, pipes: 8, outputs: 0
12286 11:56:19.339469 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[<14>[ 27.220513] [IGT] kms_vblank: executing
12287 11:56:19.340017 0m
12288 11:56:19.346157 IGT-Version: 1.2<14>[ 27.226413] [IGT] kms_vblank: exiting, ret=77
12289 11:56:19.352753 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12290 11:56:19.362730 Opened device: /dev/dri/car<8>[ 27.238071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12291 11:56:19.363438 d0
12292 11:56:19.364268 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12294 11:56:19.366802 No KMS driver or no outputs, pipes: 8, outputs: 0
12295 11:56:19.372618 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12296 11:56:19.375848 <14>[ 27.258687] [IGT] kms_vblank: executing
12297 11:56:19.382749 IGT-Version: 1.2<14>[ 27.263482] [IGT] kms_vblank: exiting, ret=77
12298 11:56:19.395646 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 27.273360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12299 11:56:19.396220 64)
12300 11:56:19.396981 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12302 11:56:19.398905 Opened device: /dev/dri/card0
12303 11:56:19.402092 No KMS driver or no outputs, pipes: 8, outputs: 0
12304 11:56:19.412178 [1mSubtest pipe-B-ts-continuation-idle-h<14>[ 27.292191] [IGT] kms_vblank: executing
12305 11:56:19.418795 ang: SKIP (0.000<14>[ 27.297963] [IGT] kms_vblank: exiting, ret=77
12306 11:56:19.419600 s)[0m
12307 11:56:19.425209 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12308 11:56:19.432246 Ope<8>[ 27.309377] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12309 11:56:19.433292 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12311 11:56:19.435581 ned device: /dev/dri/card0
12312 11:56:19.442001 No KMS driver or no outputs, pipes: 8, outputs: 0
12313 11:56:19.445093 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12314 11:56:19.448677 <14>[ 27.330905] [IGT] kms_vblank: executing
12315 11:56:19.455376 IGT-Version: 1.2<14>[ 27.336633] [IGT] kms_vblank: exiting, ret=77
12316 11:56:19.461877 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12317 11:56:19.471967 Opened devi<8>[ 27.346516] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12318 11:56:19.472568 ce: /dev/dri/card0
12319 11:56:19.473233 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12321 11:56:19.478433 No KMS driver or no outputs, pipes: 8, outputs: 0
12322 11:56:19.485203 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.<14>[ 27.367735] [IGT] kms_vblank: executing
12323 11:56:19.488569 000s)[0m
12324 11:56:19.491581 <14>[ 27.372869] [IGT] kms_vblank: exiting, ret=77
12325 11:56:19.505225 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 27.382124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12326 11:56:19.505816 64)
12327 11:56:19.506525 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12329 11:56:19.508095 Opened device: /dev/dri/card0
12330 11:56:19.514806 No KMS driver or no outputs, pipes: 8, outputs: 0
12331 11:56:19.521450 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)<14>[ 27.403213] [IGT] kms_vblank: executing
12332 11:56:19.524802 [0m
12333 11:56:19.528634 IGT-Version: 1.2<14>[ 27.409281] [IGT] kms_vblank: exiting, ret=77
12334 11:56:19.534895 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12335 11:56:19.544616 Opened devi<8>[ 27.419617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12336 11:56:19.545200 ce: /dev/dri/card0
12337 11:56:19.545856 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12339 11:56:19.551330 No KMS driver or no outputs, pipes: 8, outputs: 0
12340 11:56:19.557976 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)<14>[ 27.439732] [IGT] kms_vblank: executing
12341 11:56:19.558545 [0m
12342 11:56:19.564709 <14>[ 27.445426] [IGT] kms_vblank: exiting, ret=77
12343 11:56:19.577914 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 27.454860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12344 11:56:19.578485 64)
12345 11:56:19.579145 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12347 11:56:19.580952 Opened device: /dev/dri/card0
12348 11:56:19.587976 No KMS driver or no outputs, pipes: 8, outputs: 0
12349 11:56:19.594281 [1mSubtest pipe-B-ts-continuation-modese<14>[ 27.474626] [IGT] kms_vblank: executing
12350 11:56:19.600867 t-hang: SKIP (0.<14>[ 27.480779] [IGT] kms_vblank: exiting, ret=77
12351 11:56:19.601432 000s)[0m
12352 11:56:19.607545 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12353 11:56:19.617488 <8>[ 27.491969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12354 11:56:19.618057 Opened device: /dev/dri/card0
12355 11:56:19.618743 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12357 11:56:19.623750 No KMS driver or no outputs, pipes: 8, outputs: 0
12358 11:56:19.633987 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)<14>[ 27.513627] [IGT] kms_vblank: executing
12359 11:56:19.634562 [0m
12360 11:56:19.640596 IGT-Version: 1.2<14>[ 27.519329] [IGT] kms_vblank: exiting, ret=77
12361 11:56:19.644052 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12362 11:56:19.653645 Opened device: /dev/dri/car<8>[ 27.531188] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12363 11:56:19.654220 d0
12364 11:56:19.654884 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12366 11:56:19.660292 No KMS driver or no outputs, pipes: 8, outputs: 0
12367 11:56:19.663697 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12368 11:56:19.670435 <14>[ 27.551511] [IGT] kms_vblank: executing
12369 11:56:19.677236 IGT-Version: 1.2<14>[ 27.556284] [IGT] kms_vblank: exiting, ret=77
12370 11:56:19.680566 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12371 11:56:19.690553 Opened devi<8>[ 27.566118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12372 11:56:19.691128 ce: /dev/dri/card0
12373 11:56:19.691783 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12375 11:56:19.693505 No KMS driver or no outputs, pipes: 8, outputs: 0
12376 11:56:19.700194 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12377 11:56:19.703415 <14>[ 27.585056] [IGT] kms_vblank: executing
12378 11:56:19.710073 IGT-Version: 1.2<14>[ 27.590117] [IGT] kms_vblank: exiting, ret=77
12379 11:56:19.713475 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12380 11:56:19.723363 Opened device: /dev/dri/car<8>[ 27.601714] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12381 11:56:19.724370 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12383 11:56:19.726838 d0
12384 11:56:19.730032 No KMS driver or no outputs, pipes: 8, outputs: 0
12385 11:56:19.733400 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12386 11:56:19.741579 <14>[ 27.622149] [IGT] kms_vblank: executing
12387 11:56:19.748093 IGT-Version: 1.2<14>[ 27.626831] [IGT] kms_vblank: exiting, ret=77
12388 11:56:19.751748 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12389 11:56:19.761195 Opened device: /dev/dri/car<8>[ 27.638576] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12390 11:56:19.761745 d0
12391 11:56:19.762388 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12393 11:56:19.764465 No KMS driver or no outputs, pipes: 8, outputs: 0
12394 11:56:19.771303 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12395 11:56:19.781867 <14>[ 27.662787] [IGT] kms_vblank: executing
12396 11:56:19.788553 IGT-Version: 1.2<14>[ 27.667530] [IGT] kms_vblank: exiting, ret=77
12397 11:56:19.792006 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12398 11:56:19.801948 Opened devi<8>[ 27.677441] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12399 11:56:19.802520 ce: /dev/dri/card0
12400 11:56:19.803169 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12402 11:56:19.808615 No KMS driver or no outputs, pipes: 8, outputs: 0
12403 11:56:19.811498 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12404 11:56:19.815368 <14>[ 27.697887] [IGT] kms_vblank: executing
12405 11:56:19.821570 IGT-Version: 1.2<14>[ 27.702827] [IGT] kms_vblank: exiting, ret=77
12406 11:56:19.828617 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12407 11:56:19.838299 Opened device: /dev/dri/car<8>[ 27.714295] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12408 11:56:19.838861 d0
12409 11:56:19.839508 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12411 11:56:19.841457 No KMS driver or no outputs, pipes: 8, outputs: 0
12412 11:56:19.844961 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12413 11:56:19.853733 <14>[ 27.734408] [IGT] kms_vblank: executing
12414 11:56:19.860132 IGT-Version: 1.2<14>[ 27.739112] [IGT] kms_vblank: exiting, ret=77
12415 11:56:19.863433 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12416 11:56:19.873691 Opened devi<8>[ 27.749250] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12417 11:56:19.874266 ce: /dev/dri/card0
12418 11:56:19.874927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12420 11:56:19.880130 No KMS driver or no outputs, pipes: 8, outputs: 0
12421 11:56:19.883659 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12422 11:56:19.886713 <14>[ 27.768809] [IGT] kms_vblank: executing
12423 11:56:19.893038 IGT-Version: 1.2<14>[ 27.773900] [IGT] kms_vblank: exiting, ret=77
12424 11:56:19.900423 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12425 11:56:19.909707 Opened device: /dev/dri/car<8>[ 27.785450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12426 11:56:19.910292 d0
12427 11:56:19.911038 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12429 11:56:19.912993 No KMS driver or no outputs, pipes: 8, outputs: 0
12430 11:56:19.920069 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12431 11:56:19.923361 <14>[ 27.806237] [IGT] kms_vblank: executing
12432 11:56:19.929858 IGT-Version: 1.2<14>[ 27.810891] [IGT] kms_vblank: exiting, ret=77
12433 11:56:19.936638 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12434 11:56:19.946399 Opened device: /dev/dri/car<8>[ 27.823062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12435 11:56:19.946962 d0
12436 11:56:19.947609 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12438 11:56:19.949413 No KMS driver or no outputs, pipes: 8, outputs: 0
12439 11:56:19.955804 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12440 11:56:19.962924 <14>[ 27.843903] [IGT] kms_vblank: executing
12441 11:56:19.969400 IGT-Version: 1.2<14>[ 27.848722] [IGT] kms_vblank: exiting, ret=77
12442 11:56:19.972870 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12443 11:56:19.979848 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12445 11:56:19.982655 Opened devi<8>[ 27.858508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12446 11:56:19.983221 ce: /dev/dri/card0
12447 11:56:19.986030 No KMS driver or no outputs, pipes: 8, outputs: 0
12448 11:56:19.992567 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12449 11:56:19.996130 <14>[ 27.878837] [IGT] kms_vblank: executing
12450 11:56:20.002746 IGT-Version: 1.2<14>[ 27.883553] [IGT] kms_vblank: exiting, ret=77
12451 11:56:20.009424 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12452 11:56:20.015681 Opened devi<8>[ 27.893454] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12453 11:56:20.016426 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12455 11:56:20.019168 ce: /dev/dri/card0
12456 11:56:20.022217 No KMS driver or no outputs, pipes: 8, outputs: 0
12457 11:56:20.029507 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12458 11:56:20.032295 <14>[ 27.912768] [IGT] kms_vblank: executing
12459 11:56:20.038991 IGT-Version: 1.2<14>[ 27.918128] [IGT] kms_vblank: exiting, ret=77
12460 11:56:20.042061 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12461 11:56:20.052571 Opened device: /dev/dri/car<8>[ 27.929746] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12462 11:56:20.053164 d0
12463 11:56:20.053824 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12465 11:56:20.059220 No KMS driver or no outputs, pipes: 8, outputs: 0
12466 11:56:20.062029 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12467 11:56:20.069154 <14>[ 27.949784] [IGT] kms_vblank: executing
12468 11:56:20.075736 IGT-Version: 1.2<14>[ 27.954575] [IGT] kms_vblank: exiting, ret=77
12469 11:56:20.078842 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12470 11:56:20.088664 Opened devi<8>[ 27.964727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12471 11:56:20.089235 ce: /dev/dri/card0
12472 11:56:20.089890 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12474 11:56:20.095747 No KMS driver or no outputs, pipes: 8, outputs: 0
12475 11:56:20.098566 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12476 11:56:20.101988 <14>[ 27.984140] [IGT] kms_vblank: executing
12477 11:56:20.108579 IGT-Version: 1.2<14>[ 27.989583] [IGT] kms_vblank: exiting, ret=77
12478 11:56:20.114751 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12479 11:56:20.121790 Opened devi<8>[ 27.999872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12480 11:56:20.122629 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12482 11:56:20.124866 ce: /dev/dri/card0
12483 11:56:20.128200 No KMS driver or no outputs, pipes: 8, outputs: 0
12484 11:56:20.131693 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12485 11:56:20.138091 <14>[ 28.018800] [IGT] kms_vblank: executing
12486 11:56:20.144819 IGT-Version: 1.2<14>[ 28.023509] [IGT] kms_vblank: exiting, ret=77
12487 11:56:20.148459 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12488 11:56:20.158687 Opened devi<8>[ 28.033511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12489 11:56:20.159270 ce: /dev/dri/card0
12490 11:56:20.159924 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12492 11:56:20.161285 No KMS driver or no outputs, pipes: 8, outputs: 0
12493 11:56:20.167850 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12494 11:56:20.171458 <14>[ 28.052879] [IGT] kms_vblank: executing
12495 11:56:20.178271 IGT-Version: 1.2<14>[ 28.058175] [IGT] kms_vblank: exiting, ret=77
12496 11:56:20.181184 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12497 11:56:20.191677 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12499 11:56:20.194731 Opened device: /dev/dri/car<8>[ 28.069761] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12500 11:56:20.195303 d0
12501 11:56:20.198239 No KMS driver or no outputs, pipes: 8, outputs: 0
12502 11:56:20.201041 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12503 11:56:20.209364 <14>[ 28.090371] [IGT] kms_vblank: executing
12504 11:56:20.216045 IGT-Version: 1.2<14>[ 28.094998] [IGT] kms_vblank: exiting, ret=77
12505 11:56:20.219379 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12506 11:56:20.229607 Opened devi<8>[ 28.105335] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12507 11:56:20.230162 ce: /dev/dri/card0
12508 11:56:20.230802 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12510 11:56:20.236125 No KMS driver or no outputs, pipes: 8, outputs: 0
12511 11:56:20.242717 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[<14>[ 28.124895] [IGT] kms_vblank: executing
12512 11:56:20.245831 0m
12513 11:56:20.248829 IGT-Version: 1.2<14>[ 28.130525] [IGT] kms_vblank: exiting, ret=77
12514 11:56:20.255953 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12515 11:56:20.265856 Opened devi<8>[ 28.141959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12516 11:56:20.266434 ce: /dev/dri/card0
12517 11:56:20.267086 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12519 11:56:20.272492 No KMS driver or no outputs, pipes: 8, outputs: 0
12520 11:56:20.275721 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12521 11:56:20.278666 <14>[ 28.162275] [IGT] kms_vblank: executing
12522 11:56:20.285839 IGT-Version: 1.2<14>[ 28.166914] [IGT] kms_vblank: exiting, ret=77
12523 11:56:20.292288 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12524 11:56:20.302193 Opened devi<8>[ 28.178182] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12525 11:56:20.302756 ce: /dev/dri/card0
12526 11:56:20.303403 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12528 11:56:20.308865 No KMS driver or no outputs, pipes: 8, outputs: 0
12529 11:56:20.312219 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12530 11:56:20.318780 <14>[ 28.198316] [IGT] kms_vblank: executing
12531 11:56:20.321969 IGT-Version: 1.2<14>[ 28.203759] [IGT] kms_vblank: exiting, ret=77
12532 11:56:20.328569 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12533 11:56:20.338369 Opened devi<8>[ 28.213706] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12534 11:56:20.338937 ce: /dev/dri/card0
12535 11:56:20.339579 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12537 11:56:20.344762 No KMS driver or no outputs, pipes: 8, outputs: 0
12538 11:56:20.351778 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s<14>[ 28.233527] [IGT] kms_vblank: executing
12539 11:56:20.355375 )[0m
12540 11:56:20.358407 <14>[ 28.239516] [IGT] kms_vblank: exiting, ret=77
12541 11:56:20.364987 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12542 11:56:20.374982 Opened devi<8>[ 28.250172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12543 11:56:20.375545 ce: /dev/dri/card0
12544 11:56:20.376193 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12546 11:56:20.381582 No KMS driver or no outputs, pipes: 8, outputs: 0
12547 11:56:20.388642 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12548 11:56:20.391594 <14>[ 28.271693] [IGT] kms_vblank: executing
12549 11:56:20.398054 IGT-Version: 1.2<14>[ 28.277288] [IGT] kms_vblank: exiting, ret=77
12550 11:56:20.401378 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12551 11:56:20.411171 Opened devi<8>[ 28.287256] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12552 11:56:20.411866 ce: /dev/dri/card0
12553 11:56:20.412545 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12555 11:56:20.418015 No KMS driver or no outputs, pipes: 8, outputs: 0
12556 11:56:20.424763 [1mSubtest pipe-C-ts-continuation-suspen<14>[ 28.306793] [IGT] kms_vblank: executing
12557 11:56:20.430965 d: SKIP (0.000s)<14>[ 28.311502] [IGT] kms_vblank: exiting, ret=77
12558 11:56:20.431436 [0m
12559 11:56:20.437616 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12560 11:56:20.447643 Opene<8>[ 28.322941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12561 11:56:20.448216 d device: /dev/dri/card0
12562 11:56:20.448967 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12564 11:56:20.454525 No KMS driver or no outputs, pipes: 8, outputs: 0
12565 11:56:20.457975 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12566 11:56:20.464038 <14>[ 28.344314] [IGT] kms_vblank: executing
12567 11:56:20.470646 IGT-Version: 1.2<14>[ 28.349825] [IGT] kms_vblank: exiting, ret=77
12568 11:56:20.474039 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12569 11:56:20.484032 Opened device: /dev/dri/car<8>[ 28.361472] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12570 11:56:20.484957 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12572 11:56:20.487516 d0
12573 11:56:20.491035 No KMS driver or no outputs, pipes: 8, outputs: 0
12574 11:56:20.497011 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12575 11:56:20.513325 <14>[ 28.393991] [IGT] kms_vblank: executing
12576 11:56:20.519948 IGT-Version: 1.2<14>[ 28.399107] [IGT] kms_vblank: exiting, ret=77
12577 11:56:20.523055 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12578 11:56:20.532930 Opened device: /dev/dri/car<8>[ 28.410158] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12579 11:56:20.533787 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12581 11:56:20.536341 d0
12582 11:56:20.539226 No KMS driver or no outputs, pipes: 8, outputs: 0
12583 11:56:20.545906 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12584 11:56:20.549236 <14>[ 28.431770] [IGT] kms_vblank: executing
12585 11:56:20.556202 IGT-Version: 1.2<14>[ 28.436606] [IGT] kms_vblank: exiting, ret=77
12586 11:56:20.559611 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12587 11:56:20.569370 Opened devi<8>[ 28.446428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12588 11:56:20.570230 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12590 11:56:20.572548 ce: /dev/dri/card0
12591 11:56:20.576104 No KMS driver or no outputs, pipes: 8, outputs: 0
12592 11:56:20.579412 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12593 11:56:20.585848 <14>[ 28.466885] [IGT] kms_vblank: executing
12594 11:56:20.592211 IGT-Version: 1.2<14>[ 28.471599] [IGT] kms_vblank: exiting, ret=77
12595 11:56:20.595844 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12596 11:56:20.605632 Opened devi<8>[ 28.481585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12597 11:56:20.606205 ce: /dev/dri/card0
12598 11:56:20.607011 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12600 11:56:20.608903 No KMS driver or no outputs, pipes: 8, outputs: 0
12601 11:56:20.615558 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12602 11:56:20.619182 <14>[ 28.500892] [IGT] kms_vblank: executing
12603 11:56:20.625454 IGT-Version: 1.2<14>[ 28.505557] [IGT] kms_vblank: exiting, ret=77
12604 11:56:20.628850 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12605 11:56:20.639036 Opened device: /dev/dri/car<8>[ 28.517251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12606 11:56:20.639894 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12608 11:56:20.642013 d0
12609 11:56:20.645674 No KMS driver or no outputs, pipes: 8, outputs: 0
12610 11:56:20.648695 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12611 11:56:20.656589 <14>[ 28.537439] [IGT] kms_vblank: executing
12612 11:56:20.662905 IGT-Version: 1.2<14>[ 28.542139] [IGT] kms_vblank: exiting, ret=77
12613 11:56:20.666362 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12614 11:56:20.676342 Opened device: /dev/dri/car<8>[ 28.553872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12615 11:56:20.676963 d0
12616 11:56:20.677624 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12618 11:56:20.682811 No KMS driver or no outputs, pipes: 8, outputs: 0
12619 11:56:20.686536 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12620 11:56:20.692873 <14>[ 28.573655] [IGT] kms_vblank: executing
12621 11:56:20.699649 IGT-Version: 1.2<14>[ 28.578267] [IGT] kms_vblank: exiting, ret=77
12622 11:56:20.703158 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12623 11:56:20.712764 Opened devi<8>[ 28.588605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12624 11:56:20.713395 ce: /dev/dri/card0
12625 11:56:20.714053 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12627 11:56:20.719652 No KMS driver or no outputs, pipes: 8, outputs: 0
12628 11:56:20.722596 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12629 11:56:20.725796 <14>[ 28.607782] [IGT] kms_vblank: executing
12630 11:56:20.732830 IGT-Version: 1.2<14>[ 28.613501] [IGT] kms_vblank: exiting, ret=77
12631 11:56:20.739573 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12632 11:56:20.746269 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12634 11:56:20.749272 Opened device: /dev/dri/car<8>[ 28.624857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12635 11:56:20.749746 d0
12636 11:56:20.752500 No KMS driver or no outputs, pipes: 8, outputs: 0
12637 11:56:20.756003 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12638 11:56:20.764011 <14>[ 28.645009] [IGT] kms_vblank: executing
12639 11:56:20.770933 IGT-Version: 1.2<14>[ 28.649850] [IGT] kms_vblank: exiting, ret=77
12640 11:56:20.774016 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12641 11:56:20.783950 Opened device: /dev/dri/car<8>[ 28.661277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12642 11:56:20.784556 d0
12643 11:56:20.785220 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12645 11:56:20.790518 No KMS driver or no outputs, pipes: 8, outputs: 0
12646 11:56:20.793627 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12647 11:56:20.801369 <14>[ 28.681908] [IGT] kms_vblank: executing
12648 11:56:20.807573 IGT-Version: 1.2<14>[ 28.686614] [IGT] kms_vblank: exiting, ret=77
12649 11:56:20.817445 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 28.696490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12650 11:56:20.818026 64)
12651 11:56:20.818688 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12653 11:56:20.820652 Opened device: /dev/dri/card0
12654 11:56:20.827625 No KMS driver or no outputs, pipes: 8, outputs: 0
12655 11:56:20.834311 [1mSubtest pipe-D-query-forked-busy: SKI<14>[ 28.715652] [IGT] kms_vblank: executing
12656 11:56:20.834878 P (0.000s)[0m
12657 11:56:20.840576 <14>[ 28.720458] [IGT] kms_vblank: exiting, ret=77
12658 11:56:20.854096 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 28.730257] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12659 11:56:20.854669 64)
12660 11:56:20.855335 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12662 11:56:20.857051 Opened device: /dev/dri/card0
12663 11:56:20.860665 No KMS driver or no outputs, pipes: 8, outputs: 0
12664 11:56:20.867399 [1mSubtest pipe-D-query-<14>[ 28.749768] [IGT] kms_vblank: executing
12665 11:56:20.873627 forked-busy-hang<14>[ 28.754597] [IGT] kms_vblank: exiting, ret=77
12666 11:56:20.877621 : SKIP (0.000s)[0m
12667 11:56:20.886884 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 <8>[ 28.765965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12668 11:56:20.887750 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12670 11:56:20.890308 aarch64)
12671 11:56:20.893503 Opened device: /dev/dri/card0
12672 11:56:20.897034 No KMS driver or no outputs, pipes: 8, outputs: 0
12673 11:56:20.900321 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12674 11:56:20.903572 <14>[ 28.786117] [IGT] kms_vblank: executing
12675 11:56:20.910491 IGT-Version: 1.2<14>[ 28.791446] [IGT] kms_vblank: exiting, ret=77
12676 11:56:20.916434 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12677 11:56:20.923408 Opened devi<8>[ 28.801368] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12678 11:56:20.924258 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12680 11:56:20.926538 ce: /dev/dri/card0
12681 11:56:20.930261 No KMS driver or no outputs, pipes: 8, outputs: 0
12682 11:56:20.937051 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12683 11:56:20.939826 <14>[ 28.820630] [IGT] kms_vblank: executing
12684 11:56:20.946710 IGT-Version: 1.2<14>[ 28.826043] [IGT] kms_vblank: exiting, ret=77
12685 11:56:20.950389 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12686 11:56:20.960455 Opened device: /dev/dri/car<8>[ 28.837491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12687 11:56:20.961120 d0
12688 11:56:20.961781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12690 11:56:20.966645 No KMS driver or no outputs, pipes: 8, outputs: 0
12691 11:56:20.969799 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12692 11:56:20.976700 <14>[ 28.857555] [IGT] kms_vblank: executing
12693 11:56:20.982921 IGT-Version: 1.2<14>[ 28.862269] [IGT] kms_vblank: exiting, ret=77
12694 11:56:20.986708 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12695 11:56:20.996385 Opened devi<8>[ 28.872519] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12696 11:56:20.996969 ce: /dev/dri/card0
12697 11:56:20.997625 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12699 11:56:21.003012 No KMS driver or no outputs, pipes: 8, outputs: 0
12700 11:56:21.006118 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12701 11:56:21.009482 <14>[ 28.891813] [IGT] kms_vblank: executing
12702 11:56:21.016395 IGT-Version: 1.2<14>[ 28.897322] [IGT] kms_vblank: exiting, ret=77
12703 11:56:21.023112 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12704 11:56:21.029504 Opened devi<8>[ 28.907593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12705 11:56:21.030477 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12707 11:56:21.032694 ce: /dev/dri/card0
12708 11:56:21.036063 No KMS driver or no outputs, pipes: 8, outputs: 0
12709 11:56:21.039293 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12710 11:56:21.050253 <14>[ 28.931436] [IGT] kms_vblank: executing
12711 11:56:21.057295 IGT-Version: 1.2<14>[ 28.936137] [IGT] kms_vblank: exiting, ret=77
12712 11:56:21.060743 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12713 11:56:21.070593 Opened devi<8>[ 28.946401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12714 11:56:21.071183 ce: /dev/dri/card0
12715 11:56:21.071895 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12717 11:56:21.076747 No KMS driver or no outputs, pipes: 8, outputs: 0
12718 11:56:21.080272 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12719 11:56:21.083825 <14>[ 28.966504] [IGT] kms_vblank: executing
12720 11:56:21.090384 IGT-Version: 1.2<14>[ 28.971203] [IGT] kms_vblank: exiting, ret=77
12721 11:56:21.103543 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 28.981078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12722 11:56:21.104128 64)
12723 11:56:21.104825 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12725 11:56:21.107102 Opened device: /dev/dri/card0
12726 11:56:21.110469 No KMS driver or no outputs, pipes: 8, outputs: 0
12727 11:56:21.116738 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12728 11:56:21.120491 <14>[ 29.000466] [IGT] kms_vblank: executing
12729 11:56:21.126596 IGT-Version: 1.2<14>[ 29.006206] [IGT] kms_vblank: exiting, ret=77
12730 11:56:21.129842 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12731 11:56:21.139915 Opened device: /dev/dri/car<8>[ 29.017941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12732 11:56:21.140836 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12734 11:56:21.143497 d0
12735 11:56:21.146623 No KMS driver or no outputs, pipes: 8, outputs: 0
12736 11:56:21.149797 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12737 11:56:21.157458 <14>[ 29.038521] [IGT] kms_vblank: executing
12738 11:56:21.164111 IGT-Version: 1.2<14>[ 29.043250] [IGT] kms_vblank: exiting, ret=77
12739 11:56:21.167791 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12740 11:56:21.177421 Opened devi<8>[ 29.053349] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12741 11:56:21.177996 ce: /dev/dri/card0
12742 11:56:21.178653 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12744 11:56:21.184093 No KMS driver or no outputs, pipes: 8, outputs: 0
12745 11:56:21.190487 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0<14>[ 29.072824] [IGT] kms_vblank: executing
12746 11:56:21.193799 m
12747 11:56:21.196969 IGT-Version: 1.2<14>[ 29.078730] [IGT] kms_vblank: exiting, ret=77
12748 11:56:21.203660 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12749 11:56:21.213651 Opened device: /dev/dri/car<8>[ 29.090222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
12750 11:56:21.214218 d0
12751 11:56:21.214873 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
12753 11:56:21.220163 No KMS driver or no outputs, pipes: 8, outputs: 0
12754 11:56:21.223861 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
12755 11:56:21.230676 <14>[ 29.111511] [IGT] kms_vblank: executing
12756 11:56:21.236793 IGT-Version: 1.2<14>[ 29.116260] [IGT] kms_vblank: exiting, ret=77
12757 11:56:21.240705 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12758 11:56:21.250491 Opened devi<8>[ 29.126139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
12759 11:56:21.251057 ce: /dev/dri/card0
12760 11:56:21.251712 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
12762 11:56:21.256958 No KMS driver or no outputs, pipes: 8, outputs: 0
12763 11:56:21.267064 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s<14>[ 29.146131] [IGT] kms_vblank: executing
12764 11:56:21.267623 )[0m
12765 11:56:21.270236 <14>[ 29.151914] [IGT] kms_vblank: exiting, ret=77
12766 11:56:21.283963 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
12768 11:56:21.286749 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 29.162288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
12769 11:56:21.287221 64)
12770 11:56:21.290374 Opened device: /dev/dri/card0
12771 11:56:21.293582 No KMS driver or no outputs, pipes: 8, outputs: 0
12772 11:56:21.300209 [1mSubtest pipe-D-ts-continuation-dpms-s<14>[ 29.182381] [IGT] kms_vblank: executing
12773 11:56:21.307198 uspend: SKIP (0.<14>[ 29.187372] [IGT] kms_vblank: exiting, ret=77
12774 11:56:21.307768 000s)[0m
12775 11:56:21.320229 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62<8>[ 29.197167] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
12776 11:56:21.321203 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
12778 11:56:21.323468 -cip9 aarch64)
12779 11:56:21.326538 Opened device: /dev/dri/card0
12780 11:56:21.329825 No KMS driver or no outputs, pipes: 8, outputs: 0
12781 11:56:21.336419 [1mSubtest pipe-D-ts-continua<14>[ 29.217042] [IGT] kms_vblank: executing
12782 11:56:21.343342 tion-suspend: SK<14>[ 29.222879] [IGT] kms_vblank: exiting, ret=77
12783 11:56:21.343926 IP (0.000s)[0m
12784 11:56:21.356306 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarc<8>[ 29.234157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
12785 11:56:21.357208 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
12787 11:56:21.359708 h64)
12788 11:56:21.360275 Opened device: /dev/dri/card0
12789 11:56:21.366283 No KMS driver or no outputs, pipes: 8, outputs: 0
12790 11:56:21.376236 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s<14>[ 29.255735] [IGT] kms_vblank: executing
12791 11:56:21.376858 )[0m
12792 11:56:21.379619 <14>[ 29.261342] [IGT] kms_vblank: exiting, ret=77
12793 11:56:21.395946 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 29.270623] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
12794 11:56:21.396548 64)
12795 11:56:21.397220 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
12797 11:56:21.399131 Opened device: /dev/dri/card0
12798 11:56:21.403047 No KMS driver or no outputs, pipes: 8, outputs: 0
12799 11:56:21.409729 [1mSubtest pipe-D-ts-continuation-modese<14>[ 29.291729] [IGT] kms_vblank: executing
12800 11:56:21.416206 t-hang: SKIP (0.<14>[ 29.296772] [IGT] kms_vblank: exiting, ret=77
12801 11:56:21.416955 000s)[0m
12802 11:56:21.429205 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62<8>[ 29.306713] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
12803 11:56:21.430062 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
12805 11:56:21.432672 -cip9 aarch64)
12806 11:56:21.435696 Opened device: /dev/dri/card0
12807 11:56:21.439382 No KMS driver or no outputs, pipes: 8, outputs: 0
12808 11:56:21.445788 [1mSubtest pipe-D-ts-continua<14>[ 29.326886] [IGT] kms_vblank: executing
12809 11:56:21.452857 tion-modeset-rpm<14>[ 29.332616] [IGT] kms_vblank: exiting, ret=77
12810 11:56:21.453440 : SKIP (0.000s)[0m
12811 11:56:21.465532 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<8>[ 29.343704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
12812 11:56:21.466388 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
12814 11:56:21.468722 ux: 6.1.62-cip9 aarch64)
12815 11:56:21.469188 Opened device: /dev/dri/card0
12816 11:56:21.475587 No KMS driver or no outputs, pipes: 8, outputs: 0
12817 11:56:21.482232 [1mSubtest pipe-E-accuracy-idle: SK<14>[ 29.362698] [IGT] kms_vblank: executing
12818 11:56:21.482807 IP (0.000s)[0m
12819 11:56:21.488854 <14>[ 29.368853] [IGT] kms_vblank: exiting, ret=77
12820 11:56:21.489428
12821 11:56:21.502152 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarc<8>[ 29.378699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
12822 11:56:21.502746 h64)
12823 11:56:21.503412 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
12825 11:56:21.505308 Opened device: /dev/dri/card0
12826 11:56:21.508580 No KMS driver or no outputs, pipes: 8, outputs: 0
12827 11:56:21.511992 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
12828 11:56:21.529181 <14>[ 29.410415] [IGT] kms_vblank: executing
12829 11:56:21.535879 IGT-Version: 1.2<14>[ 29.415394] [IGT] kms_vblank: exiting, ret=77
12830 11:56:21.539412 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12831 11:56:21.549240 Opened device: /dev/dri/car<8>[ 29.426913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
12832 11:56:21.549802 d0
12833 11:56:21.550449 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
12835 11:56:21.555738 No KMS driver or no outputs, pipes: 8, outputs: 0
12836 11:56:21.558951 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
12837 11:56:21.565770 <14>[ 29.446932] [IGT] kms_vblank: executing
12838 11:56:21.572400 IGT-Version: 1.2<14>[ 29.451648] [IGT] kms_vblank: exiting, ret=77
12839 11:56:21.575789 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12840 11:56:21.585422 Opened devi<8>[ 29.461550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
12841 11:56:21.585897 ce: /dev/dri/card0
12842 11:56:21.586553 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
12844 11:56:21.592264 No KMS driver or no outputs, pipes: 8, outputs: 0
12845 11:56:21.595415 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
12846 11:56:21.598906 <14>[ 29.480718] [IGT] kms_vblank: executing
12847 11:56:21.605543 IGT-Version: 1.2<14>[ 29.485928] [IGT] kms_vblank: exiting, ret=77
12848 11:56:21.608657 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12849 11:56:21.619542 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
12851 11:56:21.622011 Opened device: /dev/dri/car<8>[ 29.497411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
12852 11:56:21.622479 d0
12853 11:56:21.625193 No KMS driver or no outputs, pipes: 8, outputs: 0
12854 11:56:21.631762 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
12855 11:56:21.635682 <14>[ 29.518103] [IGT] kms_vblank: executing
12856 11:56:21.642009 IGT-Version: 1.2<14>[ 29.522751] [IGT] kms_vblank: exiting, ret=77
12857 11:56:21.648559 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12858 11:56:21.655147 Opened devi<8>[ 29.532807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
12859 11:56:21.656015 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
12861 11:56:21.658502 ce: /dev/dri/card0
12862 11:56:21.662139 No KMS driver or no outputs, pipes: 8, outputs: 0
12863 11:56:21.665223 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
12864 11:56:21.668416 <14>[ 29.551780] [IGT] kms_vblank: executing
12865 11:56:21.675360 IGT-Version: 1.2<14>[ 29.556834] [IGT] kms_vblank: exiting, ret=77
12866 11:56:21.681901 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12867 11:56:21.691945 Opened device: /dev/dri/car<8>[ 29.568090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
12868 11:56:21.692667 d0
12869 11:56:21.693339 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
12871 11:56:21.695035 No KMS driver or no outputs, pipes: 8, outputs: 0
12872 11:56:21.702138 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
12873 11:56:21.705048 <14>[ 29.588789] [IGT] kms_vblank: executing
12874 11:56:21.712313 IGT-Version: 1.2<14>[ 29.593438] [IGT] kms_vblank: exiting, ret=77
12875 11:56:21.718729 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12876 11:56:21.728643 Opened device: /dev/dri/car<8>[ 29.605022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
12877 11:56:21.729216 d0
12878 11:56:21.729873 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
12880 11:56:21.731815 No KMS driver or no outputs, pipes: 8, outputs: 0
12881 11:56:21.738257 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
12882 11:56:21.744855 <14>[ 29.625692] [IGT] kms_vblank: executing
12883 11:56:21.748765 IGT-Version: 1.2<14>[ 29.630362] [IGT] kms_vblank: exiting, ret=77
12884 11:56:21.755067 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12885 11:56:21.764737 Opened device: /dev/dri/car<8>[ 29.641859] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
12886 11:56:21.765216 d0
12887 11:56:21.765860 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
12889 11:56:21.771618 No KMS driver or no outputs, pipes: 8, outputs: 0
12890 11:56:21.775239 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
12891 11:56:21.782104 <14>[ 29.663058] [IGT] kms_vblank: executing
12892 11:56:21.788973 IGT-Version: 1.2<14>[ 29.667848] [IGT] kms_vblank: exiting, ret=77
12893 11:56:21.791615 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12894 11:56:21.801869 Opened devi<8>[ 29.677884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
12895 11:56:21.802428 ce: /dev/dri/card0
12896 11:56:21.803083 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
12898 11:56:21.805151 No KMS driver or no outputs, pipes: 8, outputs: 0
12899 11:56:21.811839 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
12900 11:56:21.815036 <14>[ 29.697839] [IGT] kms_vblank: executing
12901 11:56:21.821741 IGT-Version: 1.2<14>[ 29.702542] [IGT] kms_vblank: exiting, ret=77
12902 11:56:21.828292 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12903 11:56:21.834623 Opened devi<8>[ 29.712733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
12904 11:56:21.835607 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
12906 11:56:21.838082 ce: /dev/dri/card0
12907 11:56:21.841465 No KMS driver or no outputs, pipes: 8, outputs: 0
12908 11:56:21.844650 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
12909 11:56:21.851366 <14>[ 29.731894] [IGT] kms_vblank: executing
12910 11:56:21.858029 IGT-Version: 1.2<14>[ 29.737222] [IGT] kms_vblank: exiting, ret=77
12911 11:56:21.861580 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12912 11:56:21.871310 Opened device: /dev/dri/car<8>[ 29.748681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
12913 11:56:21.871875 d0
12914 11:56:21.872556 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
12916 11:56:21.874844 No KMS driver or no outputs, pipes: 8, outputs: 0
12917 11:56:21.881504 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
12918 11:56:21.887999 <14>[ 29.768945] [IGT] kms_vblank: executing
12919 11:56:21.894769 IGT-Version: 1.2<14>[ 29.773585] [IGT] kms_vblank: exiting, ret=77
12920 11:56:21.897897 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12921 11:56:21.907920 Opened device: /dev/dri/car<8>[ 29.785157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
12922 11:56:21.908495 d0
12923 11:56:21.909193 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
12925 11:56:21.914533 No KMS driver or no outputs, pipes: 8, outputs: 0
12926 11:56:21.917775 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
12927 11:56:21.924774 <14>[ 29.805776] [IGT] kms_vblank: executing
12928 11:56:21.931790 IGT-Version: 1.2<14>[ 29.810426] [IGT] kms_vblank: exiting, ret=77
12929 11:56:21.934355 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12930 11:56:21.944541 Opened device: /dev/dri/car<8>[ 29.821955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
12931 11:56:21.945028 d0
12932 11:56:21.945724 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
12934 11:56:21.947733 No KMS driver or no outputs, pipes: 8, outputs: 0
12935 11:56:21.954613 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
12936 11:56:21.961493 <14>[ 29.842048] [IGT] kms_vblank: executing
12937 11:56:21.968027 IGT-Version: 1.2<14>[ 29.846746] [IGT] kms_vblank: exiting, ret=77
12938 11:56:21.971079 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12939 11:56:21.981474 Opened device: /dev/dri/car<8>[ 29.858174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
12940 11:56:21.982043 d0
12941 11:56:21.982695 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
12943 11:56:21.984338 No KMS driver or no outputs, pipes: 8, outputs: 0
12944 11:56:21.991431 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
12945 11:56:21.997454 <14>[ 29.878393] [IGT] kms_vblank: executing
12946 11:56:22.004255 IGT-Version: 1.2<14>[ 29.883175] [IGT] kms_vblank: exiting, ret=77
12947 11:56:22.008172 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12948 11:56:22.017218 Opened devi<8>[ 29.893153] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
12949 11:56:22.017691 ce: /dev/dri/card0
12950 11:56:22.018335 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
12952 11:56:22.024177 No KMS driver or no outputs, pipes: 8, outputs: 0
12953 11:56:22.027598 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
12954 11:56:22.030813 <14>[ 29.912920] [IGT] kms_vblank: executing
12955 11:56:22.037406 IGT-Version: 1.2<14>[ 29.918196] [IGT] kms_vblank: exiting, ret=77
12956 11:56:22.043773 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12957 11:56:22.053305 Opened device: /dev/dri/car<8>[ 29.929841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
12958 11:56:22.053638 d0
12959 11:56:22.054140 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
12961 11:56:22.056714 No KMS driver or no outputs, pipes: 8, outputs: 0
12962 11:56:22.063547 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
12963 11:56:22.066854 <14>[ 29.950446] [IGT] kms_vblank: executing
12964 11:56:22.073384 IGT-Version: 1.2<14>[ 29.955100] [IGT] kms_vblank: exiting, ret=77
12965 11:56:22.079972 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12966 11:56:22.086555 Opened devi<8>[ 29.965215] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
12967 11:56:22.087104 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
12969 11:56:22.090070 ce: /dev/dri/card0
12970 11:56:22.093423 No KMS driver or no outputs, pipes: 8, outputs: 0
12971 11:56:22.103691 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0<14>[ 29.984846] [IGT] kms_vblank: executing
12972 11:56:22.104304 m
12973 11:56:22.110181 IGT-Version: 1.2<14>[ 29.990539] [IGT] kms_vblank: exiting, ret=77
12974 11:56:22.113234 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12975 11:56:22.126837 Opened device: /dev/dri/car<8>[ 30.002099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
12976 11:56:22.127415 d0
12977 11:56:22.128064 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
12979 11:56:22.129682 No KMS driver or no outputs, pipes: 8, outputs: 0
12980 11:56:22.136570 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
12981 11:56:22.143049 <14>[ 30.023685] [IGT] kms_vblank: executing
12982 11:56:22.146510 IGT-Version: 1.2<14>[ 30.028472] [IGT] kms_vblank: exiting, ret=77
12983 11:56:22.153215 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12984 11:56:22.162961 Opened devi<8>[ 30.038399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
12985 11:56:22.163586 ce: /dev/dri/card0
12986 11:56:22.164243 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
12988 11:56:22.169338 No KMS driver or no outputs, pipes: 8, outputs: 0
12989 11:56:22.172892 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12990 11:56:22.179469 <14>[ 30.059492] [IGT] kms_vblank: executing
12991 11:56:22.182507 IGT-Version: 1.2<14>[ 30.064884] [IGT] kms_vblank: exiting, ret=77
12992 11:56:22.189293 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
12993 11:56:22.199650 Opened devi<8>[ 30.074972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
12994 11:56:22.200217 ce: /dev/dri/card0
12995 11:56:22.200927 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
12997 11:56:22.205845 No KMS driver or no outputs, pipes: 8, outputs: 0
12998 11:56:22.212588 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.<14>[ 30.095118] [IGT] kms_vblank: executing
12999 11:56:22.216173 000s)[0m
13000 11:56:22.219079 <14>[ 30.100907] [IGT] kms_vblank: exiting, ret=77
13001 11:56:22.226042 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13002 11:56:22.235771 Opened devi<8>[ 30.111830] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13003 11:56:22.236356 ce: /dev/dri/card0
13004 11:56:22.237144 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13006 11:56:22.242526 No KMS driver or no outputs, pipes: 8, outputs: 0
13007 11:56:22.245601 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13008 11:56:22.252395 <14>[ 30.133192] [IGT] kms_vblank: executing
13009 11:56:22.259020 IGT-Version: 1.2<14>[ 30.138049] [IGT] kms_vblank: exiting, ret=77
13010 11:56:22.262419 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13011 11:56:22.272239 Opened device: /dev/dri/car<8>[ 30.149509] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13012 11:56:22.272859 d0
13013 11:56:22.273516 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13015 11:56:22.278920 No KMS driver or no outputs, pipes: 8, outputs: 0
13016 11:56:22.281929 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13017 11:56:22.289110 <14>[ 30.170474] [IGT] kms_vblank: executing
13018 11:56:22.296050 IGT-Version: 1.2<14>[ 30.175146] [IGT] kms_vblank: exiting, ret=77
13019 11:56:22.299230 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13020 11:56:22.309173 Opened devi<8>[ 30.185137] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13021 11:56:22.310030 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13023 11:56:22.312408 ce: /dev/dri/card0
13024 11:56:22.315884 No KMS driver or no outputs, pipes: 8, outputs: 0
13025 11:56:22.325910 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.<14>[ 30.205288] [IGT] kms_vblank: executing
13026 11:56:22.326490 000s)[0m
13027 11:56:22.329209 <14>[ 30.211248] [IGT] kms_vblank: exiting, ret=77
13028 11:56:22.336110 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13029 11:56:22.345380 Opened devi<8>[ 30.222201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13030 11:56:22.346204 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13032 11:56:22.348809 ce: /dev/dri/card0
13033 11:56:22.352335 No KMS driver or no outputs, pipes: 8, outputs: 0
13034 11:56:22.359188 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13035 11:56:22.362209 <14>[ 30.243618] [IGT] kms_vblank: executing
13036 11:56:22.368998 IGT-Version: 1.2<14>[ 30.249161] [IGT] kms_vblank: exiting, ret=77
13037 11:56:22.382180 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 30.259010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13038 11:56:22.382751 64)
13039 11:56:22.383419 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13041 11:56:22.385360 Opened device: /dev/dri/card0
13042 11:56:22.388833 No KMS driver or no outputs, pipes: 8, outputs: 0
13043 11:56:22.392074 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13044 11:56:22.398793 <14>[ 30.278048] [IGT] kms_vblank: executing
13045 11:56:22.401664 IGT-Version: 1.2<14>[ 30.283711] [IGT] kms_vblank: exiting, ret=77
13046 11:56:22.408870 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13047 11:56:22.418516 Opened device: /dev/dri/car<8>[ 30.295276] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13048 11:56:22.419082 d0
13049 11:56:22.419734 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13051 11:56:22.421575 No KMS driver or no outputs, pipes: 8, outputs: 0
13052 11:56:22.428400 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13053 11:56:22.435137 <14>[ 30.315437] [IGT] kms_vblank: executing
13054 11:56:22.438294 IGT-Version: 1.2<14>[ 30.320108] [IGT] kms_vblank: exiting, ret=77
13055 11:56:22.445002 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13056 11:56:22.451296 Opened devi<8>[ 30.330164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13057 11:56:22.452039 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13059 11:56:22.454794 ce: /dev/dri/card0
13060 11:56:22.457960 No KMS driver or no outputs, pipes: 8, outputs: 0
13061 11:56:22.464443 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13062 11:56:22.468102 <14>[ 30.349344] [IGT] kms_vblank: executing
13063 11:56:22.474781 IGT-Version: 1.2<14>[ 30.354981] [IGT] kms_vblank: exiting, ret=77
13064 11:56:22.477934 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13065 11:56:22.487844 Opened device: /dev/dri/car<8>[ 30.366398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13066 11:56:22.488703 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13068 11:56:22.491030 d0
13069 11:56:22.494426 No KMS driver or no outputs, pipes: 8, outputs: 0
13070 11:56:22.497631 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13071 11:56:22.505178 <14>[ 30.386422] [IGT] kms_vblank: executing
13072 11:56:22.512158 IGT-Version: 1.2<14>[ 30.391171] [IGT] kms_vblank: exiting, ret=77
13073 11:56:22.514898 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13074 11:56:22.525159 Opened devi<8>[ 30.401112] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13075 11:56:22.525731 ce: /dev/dri/card0
13076 11:56:22.526386 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13078 11:56:22.531792 No KMS driver or no outputs, pipes: 8, outputs: 0
13079 11:56:22.535052 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13080 11:56:22.538148 <14>[ 30.420739] [IGT] kms_vblank: executing
13081 11:56:22.544783 IGT-Version: 1.2<14>[ 30.426323] [IGT] kms_vblank: exiting, ret=77
13082 11:56:22.551728 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13083 11:56:22.561368 Opened device: /dev/dri/car<8>[ 30.437972] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13084 11:56:22.561938 d0
13085 11:56:22.562592 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13087 11:56:22.564749 No KMS driver or no outputs, pipes: 8, outputs: 0
13088 11:56:22.568047 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13089 11:56:22.576660 <14>[ 30.457931] [IGT] kms_vblank: executing
13090 11:56:22.583233 IGT-Version: 1.2<14>[ 30.462633] [IGT] kms_vblank: exiting, ret=77
13091 11:56:22.586894 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13092 11:56:22.596752 Opened devi<8>[ 30.472903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13093 11:56:22.597362 ce: /dev/dri/card0
13094 11:56:22.598096 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13096 11:56:22.603267 No KMS driver or no outputs, pipes: 8, outputs: 0
13097 11:56:22.606745 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13098 11:56:22.609595 <14>[ 30.491790] [IGT] kms_vblank: executing
13099 11:56:22.616339 IGT-Version: 1.2<14>[ 30.497327] [IGT] kms_vblank: exiting, ret=77
13100 11:56:22.623162 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13101 11:56:22.633080 Opened device: /dev/dri/car<8>[ 30.509045] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13102 11:56:22.633651 d0
13103 11:56:22.634304 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13105 11:56:22.636354 No KMS driver or no outputs, pipes: 8, outputs: 0
13106 11:56:22.642940 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13107 11:56:22.646691 <14>[ 30.529697] [IGT] kms_vblank: executing
13108 11:56:22.653237 IGT-Version: 1.2<14>[ 30.534341] [IGT] kms_vblank: exiting, ret=77
13109 11:56:22.659588 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13110 11:56:22.669409 Opened device: /dev/dri/car<8>[ 30.545913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13111 11:56:22.669972 d0
13112 11:56:22.670617 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13114 11:56:22.672763 No KMS driver or no outputs, pipes: 8, outputs: 0
13115 11:56:22.679405 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13116 11:56:22.686133 <14>[ 30.566698] [IGT] kms_vblank: executing
13117 11:56:22.689110 IGT-Version: 1.2<14>[ 30.571403] [IGT] kms_vblank: exiting, ret=77
13118 11:56:22.695754 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13119 11:56:22.706003 Opened device: /dev/dri/car<8>[ 30.582926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13120 11:56:22.706579 d0
13121 11:56:22.707269 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13123 11:56:22.708846 No KMS driver or no outputs, pipes: 8, outputs: 0
13124 11:56:22.715764 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13125 11:56:22.719113 <14>[ 30.602315] [IGT] kms_vblank: executing
13126 11:56:22.725909 IGT-Version: 1.2<14>[ 30.606959] [IGT] kms_vblank: exiting, ret=77
13127 11:56:22.732292 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13128 11:56:22.741934 Opened device: /dev/dri/car<8>[ 30.618381] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13129 11:56:22.742480 d0
13130 11:56:22.743120 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13132 11:56:22.745325 No KMS driver or no outputs, pipes: 8, outputs: 0
13133 11:56:22.752606 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13134 11:56:22.755363 <14>[ 30.638793] [IGT] kms_vblank: executing
13135 11:56:22.761688 IGT-Version: 1.2<14>[ 30.643503] [IGT] kms_vblank: exiting, ret=77
13136 11:56:22.775059 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 30.653375] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13137 11:56:22.775633 64)
13138 11:56:22.776288 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13140 11:56:22.778745 Opened device: /dev/dri/card0
13141 11:56:22.781641 No KMS driver or no outputs, pipes: 8, outputs: 0
13142 11:56:22.788489 [1mSubtest pipe-F-wait-forked: SKIP (0.0<14>[ 30.672010] [IGT] kms_vblank: executing
13143 11:56:22.792050 00s)[0m
13144 11:56:22.795058 <14>[ 30.676875] [IGT] kms_vblank: exiting, ret=77
13145 11:56:22.808361 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 30.686083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13146 11:56:22.808962 64)
13147 11:56:22.809621 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13149 11:56:22.811456 Opened device: /dev/dri/card0
13150 11:56:22.818305 No KMS driver or no outputs, pipes: 8, outputs: 0
13151 11:56:22.825094 [1mSubtest pipe-F-wait-forked-hang: SKIP<14>[ 30.706346] [IGT] kms_vblank: executing
13152 11:56:22.825655 (0.000s)[0m
13153 11:56:22.831611 <14>[ 30.711196] [IGT] kms_vblank: exiting, ret=77
13154 11:56:22.835032 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13155 11:56:22.844895 Opened devi<8>[ 30.722479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13156 11:56:22.845745 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13158 11:56:22.848199 ce: /dev/dri/card0
13159 11:56:22.851684 No KMS driver or no outputs, pipes: 8, outputs: 0
13160 11:56:22.854979 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13161 11:56:22.861211 <14>[ 30.742478] [IGT] kms_vblank: executing
13162 11:56:22.867702 IGT-Version: 1.2<14>[ 30.747144] [IGT] kms_vblank: exiting, ret=77
13163 11:56:22.871094 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13164 11:56:22.881833 Opened device: /dev/dri/car<8>[ 30.758874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13165 11:56:22.882406 d0
13166 11:56:22.883063 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13168 11:56:22.884815 No KMS driver or no outputs, pipes: 8, outputs: 0
13169 11:56:22.891249 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13170 11:56:22.897867 <14>[ 30.778538] [IGT] kms_vblank: executing
13171 11:56:22.901050 IGT-Version: 1.2<14>[ 30.783164] [IGT] kms_vblank: exiting, ret=77
13172 11:56:22.907978 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13173 11:56:22.917420 Opened devi<8>[ 30.794308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13174 11:56:22.917985 ce: /dev/dri/card0
13175 11:56:22.918667 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13177 11:56:22.920810 No KMS driver or no outputs, pipes: 8, outputs: 0
13178 11:56:22.927629 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13179 11:56:22.930983 <14>[ 30.814065] [IGT] kms_vblank: executing
13180 11:56:22.937866 IGT-Version: 1.2<14>[ 30.818697] [IGT] kms_vblank: exiting, ret=77
13181 11:56:22.944172 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13182 11:56:22.951193 Opened devi<8>[ 30.828747] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13183 11:56:22.952048 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13185 11:56:22.953995 ce: /dev/dri/card0
13186 11:56:22.957433 No KMS driver or no outputs, pipes: 8, outputs: 0
13187 11:56:22.967673 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[<14>[ 30.848535] [IGT] kms_vblank: executing
13188 11:56:22.968261 0m
13189 11:56:22.974072 IGT-Version: 1.2<14>[ 30.854334] [IGT] kms_vblank: exiting, ret=77
13190 11:56:22.977122 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13191 11:56:22.990697 Opened device: /dev/dri/car<8>[ 30.865999] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13192 11:56:22.991268 d0
13193 11:56:22.991926 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13195 11:56:22.993570 No KMS driver or no outputs, pipes: 8, outputs: 0
13196 11:56:23.000318 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13197 11:56:23.003422 <14>[ 30.887024] [IGT] kms_vblank: executing
13198 11:56:23.010353 IGT-Version: 1.2<14>[ 30.891733] [IGT] kms_vblank: exiting, ret=77
13199 11:56:23.017123 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13200 11:56:23.027365 Opened devi<8>[ 30.901695] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13201 11:56:23.027944 ce: /dev/dri/card0
13202 11:56:23.028639 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13204 11:56:23.029905 No KMS driver or no outputs, pipes: 8, outputs: 0
13205 11:56:23.039795 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000<14>[ 30.921722] [IGT] kms_vblank: executing
13206 11:56:23.040671 s)[0m
13207 11:56:23.046556 <14>[ 30.927521] [IGT] kms_vblank: exiting, ret=77
13208 11:56:23.053260 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13209 11:56:23.063601 Opened devi<8>[ 30.938161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13210 11:56:23.064171 ce: /dev/dri/card0
13211 11:56:23.064891 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13213 11:56:23.066609 No KMS driver or no outputs, pipes: 8, outputs: 0
13214 11:56:23.073548 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13215 11:56:23.076804 <14>[ 30.959399] [IGT] kms_vblank: executing
13216 11:56:23.083582 IGT-Version: 1.2<14>[ 30.964847] [IGT] kms_vblank: exiting, ret=77
13217 11:56:23.089901 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13218 11:56:23.100283 Opened devi<8>[ 30.974762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13219 11:56:23.100896 ce: /dev/dri/card0
13220 11:56:23.101556 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13222 11:56:23.106511 No KMS driver or no outputs, pipes: 8, outputs: 0
13223 11:56:23.113260 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.<14>[ 30.995169] [IGT] kms_vblank: executing
13224 11:56:23.116642 000s)[0m
13225 11:56:23.119546 <14>[ 31.000825] [IGT] kms_vblank: exiting, ret=77
13226 11:56:23.126734 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13227 11:56:23.136163 Opened devi<8>[ 31.011828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13228 11:56:23.136765 ce: /dev/dri/card0
13229 11:56:23.137422 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13231 11:56:23.142625 No KMS driver or no outputs, pipes: 8, outputs: 0
13232 11:56:23.145981 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13233 11:56:23.152783 <14>[ 31.033088] [IGT] kms_vblank: executing
13234 11:56:23.156089 IGT-Version: 1.2<14>[ 31.038046] [IGT] kms_vblank: exiting, ret=77
13235 11:56:23.162523 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13236 11:56:23.165738 Opened device: /dev/dri/card0
13237 11:56:23.175739 No KMS drive<8>[ 31.050817] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13238 11:56:23.176635 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13240 11:56:23.179197 r or no outputs, pipes: 8, outputs: 0
13241 11:56:23.182278 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13242 11:56:23.191049 <14>[ 31.072115] [IGT] kms_vblank: executing
13243 11:56:23.197394 IGT-Version: 1.2<14>[ 31.076885] [IGT] kms_vblank: exiting, ret=77
13244 11:56:23.210643 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 31.086660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13245 11:56:23.211231 64)
13246 11:56:23.211898 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13248 11:56:23.213809 Opened device: /dev/dri/card0
13249 11:56:23.217061 No KMS driver or no outputs, pipes: 8, outputs: 0
13250 11:56:23.224281 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13251 11:56:23.231035 <14>[ 31.111129] [IGT] kms_vblank: executing
13252 11:56:23.233613 IGT-Version: 1.2<14>[ 31.115908] [IGT] kms_vblank: exiting, ret=77
13253 11:56:23.240623 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13254 11:56:23.250488 Opened devi<8>[ 31.126022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13255 11:56:23.251194 ce: /dev/dri/card0
13256 11:56:23.251864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13258 11:56:23.256737 No KMS driver or no outputs, pipes: 8, outputs: 0
13259 11:56:23.263756 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.0<14>[ 31.147109] [IGT] kms_vblank: executing
13260 11:56:23.267196 00s)[0m
13261 11:56:23.270406 <14>[ 31.152128] [IGT] kms_vblank: exiting, ret=77
13262 11:56:23.283465 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 31.161311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13263 11:56:23.284036 64)
13264 11:56:23.284705 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13266 11:56:23.286492 Opened device: /dev/dri/card0
13267 11:56:23.293271 No KMS driver or no outputs, pipes: 8, outputs: 0
13268 11:56:23.296420 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13269 11:56:23.300035 <14>[ 31.181715] [IGT] kms_vblank: executing
13270 11:56:23.306472 IGT-Version: 1.2<14>[ 31.187204] [IGT] kms_vblank: exiting, ret=77
13271 11:56:23.316781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13273 11:56:23.319981 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 31.197125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13274 11:56:23.320620 64)
13275 11:56:23.321043 Opened device: /dev/dri/card0
13276 11:56:23.326625 No KMS driver or no outputs, pipes: 8, outputs: 0
13277 11:56:23.329853 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13278 11:56:23.332954 <14>[ 31.215986] [IGT] kms_vblank: executing
13279 11:56:23.339939 IGT-Version: 1.2<14>[ 31.221201] [IGT] kms_vblank: exiting, ret=77
13280 11:56:23.346464 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13281 11:56:23.352968 Opened devi<8>[ 31.231340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13282 11:56:23.353725 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13284 11:56:23.356154 ce: /dev/dri/card0
13285 11:56:23.359383 No KMS driver or no outputs, pipes: 8, outputs: 0
13286 11:56:23.365802 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13287 11:56:23.369472 <14>[ 31.250756] [IGT] kms_vblank: executing
13288 11:56:23.376164 IGT-Version: 1.2<14>[ 31.256031] [IGT] kms_vblank: exiting, ret=77
13289 11:56:23.379615 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13290 11:56:23.389391 Opened device: /dev/dri/car<8>[ 31.267503] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13291 11:56:23.389959 d0
13292 11:56:23.390617 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13294 11:56:23.395884 No KMS driver or no outputs, pipes: 8, outputs: 0
13295 11:56:23.398895 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13296 11:56:23.406511 <14>[ 31.287652] [IGT] kms_vblank: executing
13297 11:56:23.413136 IGT-Version: 1.2<14>[ 31.292385] [IGT] kms_vblank: exiting, ret=77
13298 11:56:23.416639 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13299 11:56:23.426372 Opened devi<8>[ 31.302562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13300 11:56:23.426963 ce: /dev/dri/card0
13301 11:56:23.427623 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13303 11:56:23.432846 No KMS driver or no outputs, pipes: 8, outputs: 0
13304 11:56:23.435924 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13305 11:56:23.439693 <14>[ 31.323133] [IGT] kms_vblank: executing
13306 11:56:23.445995 IGT-Version: 1.2<14>[ 31.327854] [IGT] kms_vblank: exiting, ret=77
13307 11:56:23.452416 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13308 11:56:23.459375 Opened devi<8>[ 31.337843] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13309 11:56:23.460229 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13311 11:56:23.462398 ce: /dev/dri/card0
13312 11:56:23.465669 No KMS driver or no outputs, pipes: 8, outputs: 0
13313 11:56:23.468985 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13314 11:56:23.475955 <14>[ 31.356607] [IGT] kms_vblank: executing
13315 11:56:23.482738 IGT-Version: 1.2<14>[ 31.361812] [IGT] kms_vblank: exiting, ret=77
13316 11:56:23.485810 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13317 11:56:23.495589 Opened device: /dev/dri/car<8>[ 31.373515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13318 11:56:23.496152 d0
13319 11:56:23.496843 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13321 11:56:23.502261 No KMS driver or no outputs, pipes: 8, outputs: 0
13322 11:56:23.505529 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13323 11:56:23.512764 <14>[ 31.393840] [IGT] kms_vblank: executing
13324 11:56:23.518980 IGT-Version: 1.2<14>[ 31.398500] [IGT] kms_vblank: exiting, ret=77
13325 11:56:23.522802 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13326 11:56:23.532326 Opened devi<8>[ 31.408824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13327 11:56:23.532966 ce: /dev/dri/card0
13328 11:56:23.533629 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13330 11:56:23.539014 No KMS driver or no outputs, pipes: 8, outputs: 0
13331 11:56:23.542406 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13332 11:56:23.545333 <14>[ 31.428237] [IGT] kms_vblank: executing
13333 11:56:23.552201 IGT-Version: 1.2<14>[ 31.433741] [IGT] kms_vblank: exiting, ret=77
13334 11:56:23.558666 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13335 11:56:23.568691 Opened device: /dev/dri/car<8>[ 31.445388] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13336 11:56:23.569182 d0
13337 11:56:23.569900 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13339 11:56:23.571890 No KMS driver or no outputs, pipes: 8, outputs: 0
13340 11:56:23.579082 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13341 11:56:23.584986 <14>[ 31.466062] [IGT] kms_vblank: executing
13342 11:56:23.588670 IGT-Version: 1.2<14>[ 31.470776] [IGT] kms_vblank: exiting, ret=77
13343 11:56:23.595405 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13344 11:56:23.601852 Opened devi<8>[ 31.480889] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13345 11:56:23.602706 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13347 11:56:23.604942 ce: /dev/dri/card0
13348 11:56:23.608204 No KMS driver or no outputs, pipes: 8, outputs: 0
13349 11:56:23.615149 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13350 11:56:23.618444 <14>[ 31.500675] [IGT] kms_vblank: executing
13351 11:56:23.625361 IGT-Version: 1.2<14>[ 31.505381] [IGT] kms_vblank: exiting, ret=77
13352 11:56:23.628205 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13353 11:56:23.638639 Opened device: /dev/dri/car<8>[ 31.516767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13354 11:56:23.639212 d0
13355 11:56:23.639861 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13357 11:56:23.644708 No KMS driver or no outputs, pipes: 8, outputs: 0
13358 11:56:23.647935 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13359 11:56:23.656069 <14>[ 31.537309] [IGT] kms_vblank: executing
13360 11:56:23.662678 IGT-Version: 1.2<14>[ 31.541965] [IGT] kms_vblank: exiting, ret=77
13361 11:56:23.666207 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13362 11:56:23.675924 Opened device: /dev/dri/car<8>[ 31.553532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13363 11:56:23.676472 d0
13364 11:56:23.677184 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13366 11:56:23.679308 No KMS driver or no outputs, pipes: 8, outputs: 0
13367 11:56:23.686143 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13368 11:56:23.692425 <14>[ 31.573659] [IGT] kms_vblank: executing
13369 11:56:23.698856 IGT-Version: 1.2<14>[ 31.578446] [IGT] kms_vblank: exiting, ret=77
13370 11:56:23.702146 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13371 11:56:23.712144 Opened device: /dev/dri/car<8>[ 31.589974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13372 11:56:23.712658 d0
13373 11:56:23.713305 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13375 11:56:23.718882 No KMS driver or no outputs, pipes: 8, outputs: 0
13376 11:56:23.722159 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13377 11:56:23.729217 <14>[ 31.610363] [IGT] kms_vblank: executing
13378 11:56:23.735736 IGT-Version: 1.2<14>[ 31.615096] [IGT] kms_vblank: exiting, ret=77
13379 11:56:23.738685 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13380 11:56:23.745815 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13382 11:56:23.748849 Opened devi<8>[ 31.625179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13383 11:56:23.749314 ce: /dev/dri/card0
13384 11:56:23.752385 No KMS driver or no outputs, pipes: 8, outputs: 0
13385 11:56:23.758950 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13386 11:56:23.762072 <14>[ 31.644013] [IGT] kms_vblank: executing
13387 11:56:23.768809 IGT-Version: 1.2<14>[ 31.648876] [IGT] kms_vblank: exiting, ret=77
13388 11:56:23.772561 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13389 11:56:23.782163 Opened device: /dev/dri/car<8>[ 31.660260] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13390 11:56:23.782718 d0
13391 11:56:23.783408 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13393 11:56:23.788405 No KMS driver or no outputs, pipes: 8, outputs: 0
13394 11:56:23.791790 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13395 11:56:23.799242 <14>[ 31.680875] [IGT] kms_vblank: executing
13396 11:56:23.805952 IGT-Version: 1.2<14>[ 31.685519] [IGT] kms_vblank: exiting, ret=77
13397 11:56:23.809214 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13398 11:56:23.819292 Opened device: /dev/dri/car<8>[ 31.697036] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13399 11:56:23.819841 d0
13400 11:56:23.820486 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13402 11:56:23.826230 No KMS driver or no outputs, pipes: 8, outputs: 0
13403 11:56:23.829439 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13404 11:56:23.836456 <14>[ 31.717793] [IGT] kms_vblank: executing
13405 11:56:23.843263 IGT-Version: 1.2<14>[ 31.722462] [IGT] kms_vblank: exiting, ret=77
13406 11:56:23.846359 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13407 11:56:23.856269 Opened device: /dev/dri/car<8>[ 31.733951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13408 11:56:23.856882 d0
13409 11:56:23.857534 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13411 11:56:23.862835 No KMS driver or no outputs, pipes: 8, outputs: 0
13412 11:56:23.866165 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13413 11:56:23.873255 <14>[ 31.754802] [IGT] kms_vblank: executing
13414 11:56:23.880360 IGT-Version: 1.2<14>[ 31.759441] [IGT] kms_vblank: exiting, ret=77
13415 11:56:23.883685 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13416 11:56:23.893324 Opened devi<8>[ 31.769529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13417 11:56:23.893910 ce: /dev/dri/card0
13418 11:56:23.894589 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13420 11:56:23.899763 No KMS driver or no outputs, pipes: 8, outputs: 0
13421 11:56:23.906441 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0<14>[ 31.789022] [IGT] kms_vblank: executing
13422 11:56:23.909848 m
13423 11:56:23.913249 IGT-Version: 1.2<14>[ 31.794859] [IGT] kms_vblank: exiting, ret=77
13424 11:56:23.919601 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13425 11:56:23.929682 Opened device: /dev/dri/car<8>[ 31.806664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13426 11:56:23.930285 d0
13427 11:56:23.930934 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13429 11:56:23.936685 No KMS driver or no outputs, pipes: 8, outputs: 0
13430 11:56:23.939430 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13431 11:56:23.946142 <14>[ 31.827779] [IGT] kms_vblank: executing
13432 11:56:23.953136 IGT-Version: 1.2<14>[ 31.832539] [IGT] kms_vblank: exiting, ret=77
13433 11:56:23.956399 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13434 11:56:23.966244 Opened devi<8>[ 31.842458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13435 11:56:23.966810 ce: /dev/dri/card0
13436 11:56:23.967464 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13438 11:56:23.973365 No KMS driver or no outputs, pipes: 8, outputs: 0
13439 11:56:23.982918 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s<14>[ 31.862503] [IGT] kms_vblank: executing
13440 11:56:23.983485 )[0m
13441 11:56:23.985972 <14>[ 31.868151] [IGT] kms_vblank: exiting, ret=77
13442 11:56:24.002292 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 31.878429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13443 11:56:24.002847 64)
13444 11:56:24.003502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13446 11:56:24.006117 Opened device: /dev/dri/card0
13447 11:56:24.009233 No KMS driver or no outputs, pipes: 8, outputs: 0
13448 11:56:24.019164 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.<14>[ 31.898834] [IGT] kms_vblank: executing
13449 11:56:24.019724 000s)[0m
13450 11:56:24.022907 <14>[ 31.904991] [IGT] kms_vblank: exiting, ret=77
13451 11:56:24.039136 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 31.915507] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13452 11:56:24.039836 64)
13453 11:56:24.040866 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13455 11:56:24.042238 Opened device: /dev/dri/card0
13456 11:56:24.045772 No KMS driver or no outputs, pipes: 8, outputs: 0
13457 11:56:24.055614 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)<14>[ 31.935645] [IGT] kms_vblank: executing
13458 11:56:24.056195 [0m
13459 11:56:24.059185 <14>[ 31.941455] [IGT] kms_vblank: exiting, ret=77
13460 11:56:24.072687 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13462 11:56:24.075688 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch<8>[ 31.950705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13463 11:56:24.076257 64)
13464 11:56:24.076692 Opened device: /dev/dri/card0
13465 11:56:24.082058 No KMS driver or no outputs, pipes: 8, outputs: 0
13466 11:56:24.088578 [1mSubtest pipe-G-ts-continuation-modese<14>[ 31.971163] [IGT] kms_vblank: executing
13467 11:56:24.095328 t: SKIP (0.000s)<14>[ 31.976280] [IGT] kms_vblank: exiting, ret=77
13468 11:56:24.095892 [0m
13469 11:56:24.101766 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13470 11:56:24.111937 Opene<8>[ 31.987612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13471 11:56:24.112781 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13473 11:56:24.115396 d device: /dev/dri/card0
13474 11:56:24.118504 No KMS driver or no outputs, pipes: 8, outputs: 0
13475 11:56:24.128902 [1mSubtest pipe-G-ts-continuation-modeset-hang: SK<14>[ 32.009022] [IGT] kms_vblank: executing
13476 11:56:24.129468 IP (0.000s)[0m
13477 11:56:24.132010 <14>[ 32.013726] [IGT] kms_vblank: exiting, ret=77
13478 11:56:24.132623
13479 11:56:24.138403 IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13480 11:56:24.148124 Opened dev<8>[ 32.025194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13481 11:56:24.149002 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13483 11:56:24.151308 ice: /dev/dri/card0
13484 11:56:24.155263 No KMS driver or no outputs, pipes: 8, outputs: 0
13485 11:56:24.161685 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13486 11:56:24.164761 <14>[ 32.046811] [IGT] kms_vblank: executing
13487 11:56:24.171363 IGT-Version: 1.2<14>[ 32.052159] [IGT] kms_vblank: exiting, ret=77
13488 11:56:24.175104 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13489 11:56:24.184694 Opened devi<8>[ 32.062113] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13490 11:56:24.185555 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13492 11:56:24.188227 ce: /dev/dri/card0
13493 11:56:24.191509 No KMS driver or no outputs, pipes: 8, outputs: 0
13494 11:56:24.194918 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13495 11:56:24.201326 <14>[ 32.082071] [IGT] kms_vblank: executing
13496 11:56:24.204663 IGT-Version: 1.2<14>[ 32.086705] [IGT] kms_vblank: exiting, ret=77
13497 11:56:24.211450 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13498 11:56:24.221081 Opened device: /dev/dri/car<8>[ 32.098085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13499 11:56:24.221639 d0
13500 11:56:24.222310 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13502 11:56:24.223971 No KMS driver or no outputs, pipes: 8, outputs: 0
13503 11:56:24.230974 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13504 11:56:24.237469 <14>[ 32.118064] [IGT] kms_vblank: executing
13505 11:56:24.240882 IGT-Version: 1.2<14>[ 32.122761] [IGT] kms_vblank: exiting, ret=77
13506 11:56:24.247196 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13507 11:56:24.253992 Opened devi<8>[ 32.132698] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13508 11:56:24.254841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13510 11:56:24.257161 ce: /dev/dri/card0
13511 11:56:24.260641 No KMS driver or no outputs, pipes: 8, outputs: 0
13512 11:56:24.267152 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13513 11:56:24.270352 <14>[ 32.152102] [IGT] kms_vblank: executing
13514 11:56:24.277158 IGT-Version: 1.2<14>[ 32.157541] [IGT] kms_vblank: exiting, ret=77
13515 11:56:24.280445 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13516 11:56:24.290307 Opened devi<8>[ 32.168869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13517 11:56:24.291048 ce: /dev/dri/card0
13518 11:56:24.291720 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13520 11:56:24.297041 No KMS driver or no outputs, pipes: 8, outputs: 0
13521 11:56:24.299837 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13522 11:56:24.306794 <14>[ 32.188183] [IGT] kms_vblank: executing
13523 11:56:24.313486 IGT-Version: 1.2<14>[ 32.192952] [IGT] kms_vblank: exiting, ret=77
13524 11:56:24.316747 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13525 11:56:24.326799 Opened devi<8>[ 32.202884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13526 11:56:24.327363 ce: /dev/dri/card0
13527 11:56:24.328011 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13529 11:56:24.333543 No KMS driver or no outputs, pipes: 8, outputs: 0
13530 11:56:24.336676 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13531 11:56:24.340274 <14>[ 32.222837] [IGT] kms_vblank: executing
13532 11:56:24.346680 IGT-Version: 1.2<14>[ 32.228117] [IGT] kms_vblank: exiting, ret=77
13533 11:56:24.353195 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13534 11:56:24.363306 Opened device: /dev/dri/car<8>[ 32.239586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13535 11:56:24.363869 d0
13536 11:56:24.364563 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13538 11:56:24.366809 No KMS driver or no outputs, pipes: 8, outputs: 0
13539 11:56:24.370748 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13540 11:56:24.378145 <14>[ 32.259599] [IGT] kms_vblank: executing
13541 11:56:24.385045 IGT-Version: 1.2<14>[ 32.264656] [IGT] kms_vblank: exiting, ret=77
13542 11:56:24.388049 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13543 11:56:24.391443 Opened device: /dev/dri/card0
13544 11:56:24.401377 No KMS driver or no outputs,<8>[ 32.279563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13545 11:56:24.402399 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13547 11:56:24.404618 pipes: 8, outputs: 0
13548 11:56:24.407828 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13549 11:56:24.418473 <14>[ 32.299570] [IGT] kms_vblank: executing
13550 11:56:24.424782 IGT-Version: 1.2<14>[ 32.304292] [IGT] kms_vblank: exiting, ret=77
13551 11:56:24.428324 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13552 11:56:24.437871 Opened devi<8>[ 32.315413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13553 11:56:24.438433 ce: /dev/dri/card0
13554 11:56:24.439078 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13556 11:56:24.444585 No KMS driver or no outputs, pipes: 8, outputs: 0
13557 11:56:24.448097 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13558 11:56:24.464954 <14>[ 32.346382] [IGT] kms_vblank: executing
13559 11:56:24.471482 IGT-Version: 1.2<14>[ 32.351311] [IGT] kms_vblank: exiting, ret=77
13560 11:56:24.475098 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13561 11:56:24.478397 Opened device: /dev/dri/card0
13562 11:56:24.488387 No KMS drive<8>[ 32.364025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13563 11:56:24.489274 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13565 11:56:24.491685 r or no outputs, pipes: 8, outputs: 0
13566 11:56:24.494876 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13567 11:56:24.515317 <14>[ 32.396870] [IGT] kms_vblank: executing
13568 11:56:24.521921 IGT-Version: 1.2<14>[ 32.401926] [IGT] kms_vblank: exiting, ret=77
13569 11:56:24.525217 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13570 11:56:24.528685 Opened device: /dev/dri/card0
13571 11:56:24.538621 No KMS driver or no outputs,<8>[ 32.416759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13572 11:56:24.539189 pipes: 8, outputs: 0
13573 11:56:24.539838 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13575 11:56:24.545186 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13576 11:56:24.565263 <14>[ 32.446687] [IGT] kms_vblank: executing
13577 11:56:24.571743 IGT-Version: 1.2<14>[ 32.451861] [IGT] kms_vblank: exiting, ret=77
13578 11:56:24.575376 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13579 11:56:24.578555 Opened device: /dev/dri/card0
13580 11:56:24.589039 No KMS driver or no outputs,<8>[ 32.466692] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13581 11:56:24.589885 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13583 11:56:24.591602 pipes: 8, outputs: 0
13584 11:56:24.595129 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13585 11:56:24.615678 <14>[ 32.497171] [IGT] kms_vblank: executing
13586 11:56:24.622409 IGT-Version: 1.2<14>[ 32.502318] [IGT] kms_vblank: exiting, ret=77
13587 11:56:24.625633 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13588 11:56:24.629120 Opened device: /dev/dri/card0
13589 11:56:24.639368 No KMS driver or no outputs,<8>[ 32.517072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13590 11:56:24.640220 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13592 11:56:24.642501 pipes: 8, outputs: 0
13593 11:56:24.645503 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13594 11:56:24.665526 <14>[ 32.546903] [IGT] kms_vblank: executing
13595 11:56:24.672149 IGT-Version: 1.2<14>[ 32.552093] [IGT] kms_vblank: exiting, ret=77
13596 11:56:24.675540 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13597 11:56:24.685275 Opened device: /dev/dri/car<8>[ 32.563598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13598 11:56:24.685827 d0
13599 11:56:24.686464 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13601 11:56:24.692313 No KMS driver or no outputs, pipes: 8, outputs: 0
13602 11:56:24.695461 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13603 11:56:24.712744 <14>[ 32.594088] [IGT] kms_vblank: executing
13604 11:56:24.719445 IGT-Version: 1.2<14>[ 32.599328] [IGT] kms_vblank: exiting, ret=77
13605 11:56:24.722272 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13606 11:56:24.725927 Opened device: /dev/dri/card0
13607 11:56:24.736143 No KMS driver or no outputs,<8>[ 32.613650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13608 11:56:24.736743 pipes: 8, outputs: 0
13609 11:56:24.737395 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13611 11:56:24.742504 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13612 11:56:24.763884 <14>[ 32.645148] [IGT] kms_vblank: executing
13613 11:56:24.770628 IGT-Version: 1.2<14>[ 32.650333] [IGT] kms_vblank: exiting, ret=77
13614 11:56:24.773468 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13615 11:56:24.777014 Opened device: /dev/dri/card0
13616 11:56:24.787055 No KMS driver or no outputs,<8>[ 32.665105] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13617 11:56:24.787903 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13619 11:56:24.790329 pipes: 8, outputs: 0
13620 11:56:24.793526 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13621 11:56:24.814165 <14>[ 32.695679] [IGT] kms_vblank: executing
13622 11:56:24.820784 IGT-Version: 1.2<14>[ 32.701048] [IGT] kms_vblank: exiting, ret=77
13623 11:56:24.824025 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13624 11:56:24.827707 Opened device: /dev/dri/card0
13625 11:56:24.837093 No KMS driver or no outputs,<8>[ 32.715800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13626 11:56:24.837920 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13628 11:56:24.840570 pipes: 8, outputs: 0
13629 11:56:24.844013 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13630 11:56:24.864425 <14>[ 32.746170] [IGT] kms_vblank: executing
13631 11:56:24.871165 IGT-Version: 1.2<14>[ 32.751396] [IGT] kms_vblank: exiting, ret=77
13632 11:56:24.874671 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13633 11:56:24.884811 Opened device: /dev/dri/car<8>[ 32.762721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13634 11:56:24.885382 d0
13635 11:56:24.886030 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13637 11:56:24.891420 No KMS driver or no outputs, pipes: 8, outputs: 0
13638 11:56:24.894547 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13639 11:56:24.912710 <14>[ 32.794067] [IGT] kms_vblank: executing
13640 11:56:24.919408 IGT-Version: 1.2<14>[ 32.799237] [IGT] kms_vblank: exiting, ret=77
13641 11:56:24.922586 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13642 11:56:24.932594 Opened devi<8>[ 32.810123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13643 11:56:24.933160 ce: /dev/dri/card0
13644 11:56:24.933814 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13646 11:56:24.939575 No KMS driver or no outputs, pipes: 8, outputs: 0
13647 11:56:24.942039 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13648 11:56:24.959133 <14>[ 32.840702] [IGT] kms_vblank: executing
13649 11:56:24.965864 IGT-Version: 1.2<14>[ 32.845983] [IGT] kms_vblank: exiting, ret=77
13650 11:56:24.969152 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13651 11:56:24.979661 Opened device: /dev/dri/car<8>[ 32.857605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13652 11:56:24.980545 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13654 11:56:24.982148 d0
13655 11:56:24.985347 No KMS driver or no outputs, pipes: 8, outputs: 0
13656 11:56:24.992228 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13657 11:56:25.007691 <14>[ 32.888748] [IGT] kms_vblank: executing
13658 11:56:25.014143 IGT-Version: 1.2<14>[ 32.893859] [IGT] kms_vblank: exiting, ret=77
13659 11:56:25.017454 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13660 11:56:25.027399 Opened device: /dev/dri/car<8>[ 32.905333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13661 11:56:25.027966 d0
13662 11:56:25.028640 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13664 11:56:25.033865 No KMS driver or no outputs, pipes: 8, outputs: 0
13665 11:56:25.037213 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13666 11:56:25.054913 <14>[ 32.936417] [IGT] kms_vblank: executing
13667 11:56:25.061533 IGT-Version: 1.2<14>[ 32.941534] [IGT] kms_vblank: exiting, ret=77
13668 11:56:25.064892 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13669 11:56:25.074767 Opened device: /dev/dri/car<8>[ 32.952564] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13670 11:56:25.075618 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13672 11:56:25.078004 d0
13673 11:56:25.081268 No KMS driver or no outputs, pipes: 8, outputs: 0
13674 11:56:25.087777 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13675 11:56:25.102825 <14>[ 32.984545] [IGT] kms_vblank: executing
13676 11:56:25.109849 IGT-Version: 1.2<14>[ 32.989635] [IGT] kms_vblank: exiting, ret=77
13677 11:56:25.113338 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13678 11:56:25.123045 Opened devi<8>[ 33.000575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13679 11:56:25.123597 ce: /dev/dri/card0
13680 11:56:25.124234 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13682 11:56:25.129872 No KMS driver or no outputs, pipes: 8, outputs: 0
13683 11:56:25.133169 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13684 11:56:25.149730 <14>[ 33.031066] [IGT] kms_vblank: executing
13685 11:56:25.156057 IGT-Version: 1.2<14>[ 33.036242] [IGT] kms_vblank: exiting, ret=77
13686 11:56:25.159747 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13687 11:56:25.169546 Opened devi<8>[ 33.046934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13688 11:56:25.170114 ce: /dev/dri/card0
13689 11:56:25.170765 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13691 11:56:25.176199 No KMS driver or no outputs, pipes: 8, outputs: 0
13692 11:56:25.179290 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13693 11:56:25.197398 <14>[ 33.078537] [IGT] kms_vblank: executing
13694 11:56:25.203374 IGT-Version: 1.2<14>[ 33.083832] [IGT] kms_vblank: exiting, ret=77
13695 11:56:25.207298 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13696 11:56:25.210482 Opened device: /dev/dri/card0
13697 11:56:25.220237 No KMS driver or no outputs,<8>[ 33.098668] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13698 11:56:25.221130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13700 11:56:25.223708 pipes: 8, outputs: 0
13701 11:56:25.230067 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13702 11:56:25.248825 <14>[ 33.130269] [IGT] kms_vblank: executing
13703 11:56:25.255373 IGT-Version: 1.2<14>[ 33.135428] [IGT] kms_vblank: exiting, ret=77
13704 11:56:25.259084 7.1-g621c2d3 (aarch64) (Linux: 6.1.62-cip9 aarch64)
13705 11:56:25.268784 Opened devi<8>[ 33.146281] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13706 11:56:25.269643 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13708 11:56:25.272195 ce: /dev/dri/card0
13709 11:56:25.275351 No KMS drive<8>[ 33.157195] <LAVA_SIGNAL_TESTSET STOP>
13710 11:56:25.276191 Received signal: <TESTSET> STOP
13711 11:56:25.276633 Closing test_set kms_vblank
13712 11:56:25.285030 r or no outputs,<8>[ 33.163165] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12066548_1.5.2.3.1>
13713 11:56:25.285575 pipes: 8, outputs: 0
13714 11:56:25.286207 Received signal: <ENDRUN> 0_igt-kms-mediatek 12066548_1.5.2.3.1
13715 11:56:25.286639 Ending use of test pattern.
13716 11:56:25.286979 Ending test lava.0_igt-kms-mediatek (12066548_1.5.2.3.1), duration 12.74
13718 11:56:25.292326 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13719 11:56:25.292948 + set +x
13720 11:56:25.295056 <LAVA_TEST_RUNNER EXIT>
13721 11:56:25.295890 ok: lava_test_shell seems to have completed
13722 11:56:25.317720 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13723 11:56:25.318605 end: 3.1 lava-test-shell (duration 00:00:13) [common]
13724 11:56:25.318949 end: 3 lava-test-retry (duration 00:00:13) [common]
13725 11:56:25.319300 start: 4 finalize (timeout 00:07:47) [common]
13726 11:56:25.319646 start: 4.1 power-off (timeout 00:00:30) [common]
13727 11:56:25.320218 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-4' '--port=1' '--command=off'
13728 11:56:25.426248 >> Command sent successfully.
13729 11:56:25.436936 Returned 0 in 0 seconds
13730 11:56:25.538387 end: 4.1 power-off (duration 00:00:00) [common]
13732 11:56:25.539952 start: 4.2 read-feedback (timeout 00:07:47) [common]
13733 11:56:25.541394 Listened to connection for namespace 'common' for up to 1s
13734 11:56:26.541898 Finalising connection for namespace 'common'
13735 11:56:26.542637 Disconnecting from shell: Finalise
13736 11:56:26.543035 / #
13737 11:56:26.644202 end: 4.2 read-feedback (duration 00:00:01) [common]
13738 11:56:26.644992 end: 4 finalize (duration 00:00:01) [common]
13739 11:56:26.645617 Cleaning after the job
13740 11:56:26.646288 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/ramdisk
13741 11:56:26.677255 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/kernel
13742 11:56:26.691707 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/dtb
13743 11:56:26.691979 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066548/tftp-deploy-a36_81vh/modules
13744 11:56:26.701188 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066548
13745 11:56:26.817067 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066548
13746 11:56:26.817248 Job finished correctly