Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 35
- Kernel Warnings: 26
- Boot result: PASS
- Errors: 0
1 11:54:54.887178 lava-dispatcher, installed at version: 2023.10
2 11:54:54.887419 start: 0 validate
3 11:54:54.887551 Start time: 2023-11-23 11:54:54.887543+00:00 (UTC)
4 11:54:54.887678 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:54:54.887813 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:54:55.164985 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:54:55.165156 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:54:55.432011 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:54:55.432204 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:54:55.701238 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:54:55.701418 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:54:55.968544 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:54:55.968732 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:54:56.235852 validate duration: 1.35
16 11:54:56.236106 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:54:56.236202 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:54:56.236289 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:54:56.236491 Not decompressing ramdisk as can be used compressed.
20 11:54:56.236592 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:54:56.236654 saving as /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/ramdisk/initrd.cpio.gz
22 11:54:56.236716 total size: 5625687 (5 MB)
23 11:54:56.237778 progress 0 % (0 MB)
24 11:54:56.239580 progress 5 % (0 MB)
25 11:54:56.241199 progress 10 % (0 MB)
26 11:54:56.242684 progress 15 % (0 MB)
27 11:54:56.244278 progress 20 % (1 MB)
28 11:54:56.245680 progress 25 % (1 MB)
29 11:54:56.247266 progress 30 % (1 MB)
30 11:54:56.248787 progress 35 % (1 MB)
31 11:54:56.250141 progress 40 % (2 MB)
32 11:54:56.251710 progress 45 % (2 MB)
33 11:54:56.253064 progress 50 % (2 MB)
34 11:54:56.254628 progress 55 % (2 MB)
35 11:54:56.256182 progress 60 % (3 MB)
36 11:54:56.257539 progress 65 % (3 MB)
37 11:54:56.259167 progress 70 % (3 MB)
38 11:54:56.260519 progress 75 % (4 MB)
39 11:54:56.262083 progress 80 % (4 MB)
40 11:54:56.263491 progress 85 % (4 MB)
41 11:54:56.265013 progress 90 % (4 MB)
42 11:54:56.266607 progress 95 % (5 MB)
43 11:54:56.268015 progress 100 % (5 MB)
44 11:54:56.268208 5 MB downloaded in 0.03 s (170.37 MB/s)
45 11:54:56.268360 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:54:56.268595 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:54:56.268677 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:54:56.268756 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:54:56.268893 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:54:56.268963 saving as /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/kernel/Image
52 11:54:56.269019 total size: 49107456 (46 MB)
53 11:54:56.269078 No compression specified
54 11:54:56.270170 progress 0 % (0 MB)
55 11:54:56.282736 progress 5 % (2 MB)
56 11:54:56.295491 progress 10 % (4 MB)
57 11:54:56.308084 progress 15 % (7 MB)
58 11:54:56.320823 progress 20 % (9 MB)
59 11:54:56.333376 progress 25 % (11 MB)
60 11:54:56.346116 progress 30 % (14 MB)
61 11:54:56.358842 progress 35 % (16 MB)
62 11:54:56.371495 progress 40 % (18 MB)
63 11:54:56.384189 progress 45 % (21 MB)
64 11:54:56.396923 progress 50 % (23 MB)
65 11:54:56.409621 progress 55 % (25 MB)
66 11:54:56.422321 progress 60 % (28 MB)
67 11:54:56.434908 progress 65 % (30 MB)
68 11:54:56.447518 progress 70 % (32 MB)
69 11:54:56.459966 progress 75 % (35 MB)
70 11:54:56.472655 progress 80 % (37 MB)
71 11:54:56.485357 progress 85 % (39 MB)
72 11:54:56.498160 progress 90 % (42 MB)
73 11:54:56.510742 progress 95 % (44 MB)
74 11:54:56.523164 progress 100 % (46 MB)
75 11:54:56.523388 46 MB downloaded in 0.25 s (184.12 MB/s)
76 11:54:56.523538 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:54:56.523771 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:54:56.523856 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:54:56.523943 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:54:56.524086 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:54:56.524155 saving as /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/dtb/mt8192-asurada-spherion-r0.dtb
83 11:54:56.524215 total size: 47278 (0 MB)
84 11:54:56.524275 No compression specified
85 11:54:56.525437 progress 69 % (0 MB)
86 11:54:56.525711 progress 100 % (0 MB)
87 11:54:56.525867 0 MB downloaded in 0.00 s (27.33 MB/s)
88 11:54:56.525987 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:54:56.526207 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:54:56.526292 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:54:56.526373 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:54:56.526488 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:54:56.526554 saving as /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/nfsrootfs/full.rootfs.tar
95 11:54:56.526616 total size: 195204440 (186 MB)
96 11:54:56.526676 Using unxz to decompress xz
97 11:54:56.530767 progress 0 % (0 MB)
98 11:54:57.079102 progress 5 % (9 MB)
99 11:54:57.570165 progress 10 % (18 MB)
100 11:54:58.148298 progress 15 % (27 MB)
101 11:54:58.424636 progress 20 % (37 MB)
102 11:54:58.880353 progress 25 % (46 MB)
103 11:54:59.443753 progress 30 % (55 MB)
104 11:54:59.985810 progress 35 % (65 MB)
105 11:55:00.537526 progress 40 % (74 MB)
106 11:55:01.097220 progress 45 % (83 MB)
107 11:55:01.696579 progress 50 % (93 MB)
108 11:55:02.289893 progress 55 % (102 MB)
109 11:55:02.934661 progress 60 % (111 MB)
110 11:55:03.311535 progress 65 % (121 MB)
111 11:55:03.394090 progress 70 % (130 MB)
112 11:55:03.535266 progress 75 % (139 MB)
113 11:55:03.617672 progress 80 % (148 MB)
114 11:55:03.663758 progress 85 % (158 MB)
115 11:55:03.755440 progress 90 % (167 MB)
116 11:55:04.130802 progress 95 % (176 MB)
117 11:55:04.703603 progress 100 % (186 MB)
118 11:55:04.708504 186 MB downloaded in 8.18 s (22.75 MB/s)
119 11:55:04.708782 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:55:04.709055 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:55:04.709150 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:55:04.709237 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:55:04.709406 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:55:04.709481 saving as /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/modules/modules.tar
126 11:55:04.709549 total size: 8621364 (8 MB)
127 11:55:04.709618 Using unxz to decompress xz
128 11:55:04.713806 progress 0 % (0 MB)
129 11:55:04.735161 progress 5 % (0 MB)
130 11:55:04.759970 progress 10 % (0 MB)
131 11:55:04.784422 progress 15 % (1 MB)
132 11:55:04.808558 progress 20 % (1 MB)
133 11:55:04.832482 progress 25 % (2 MB)
134 11:55:04.858370 progress 30 % (2 MB)
135 11:55:04.884741 progress 35 % (2 MB)
136 11:55:04.908474 progress 40 % (3 MB)
137 11:55:04.933068 progress 45 % (3 MB)
138 11:55:04.958570 progress 50 % (4 MB)
139 11:55:04.983549 progress 55 % (4 MB)
140 11:55:05.009503 progress 60 % (4 MB)
141 11:55:05.038500 progress 65 % (5 MB)
142 11:55:05.063892 progress 70 % (5 MB)
143 11:55:05.088538 progress 75 % (6 MB)
144 11:55:05.117060 progress 80 % (6 MB)
145 11:55:05.144057 progress 85 % (7 MB)
146 11:55:05.170076 progress 90 % (7 MB)
147 11:55:05.203161 progress 95 % (7 MB)
148 11:55:05.235904 progress 100 % (8 MB)
149 11:55:05.240962 8 MB downloaded in 0.53 s (15.47 MB/s)
150 11:55:05.241217 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:55:05.241477 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:55:05.241577 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:55:05.241673 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:55:09.079363 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui
156 11:55:09.079562 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:55:09.079666 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:55:09.079837 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u
159 11:55:09.079970 makedir: /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin
160 11:55:09.080073 makedir: /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/tests
161 11:55:09.080172 makedir: /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/results
162 11:55:09.080275 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-add-keys
163 11:55:09.080420 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-add-sources
164 11:55:09.080551 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-background-process-start
165 11:55:09.080680 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-background-process-stop
166 11:55:09.080807 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-common-functions
167 11:55:09.080934 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-echo-ipv4
168 11:55:09.081060 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-install-packages
169 11:55:09.081185 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-installed-packages
170 11:55:09.081308 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-os-build
171 11:55:09.081432 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-probe-channel
172 11:55:09.081562 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-probe-ip
173 11:55:09.081728 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-target-ip
174 11:55:09.081855 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-target-mac
175 11:55:09.081981 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-target-storage
176 11:55:09.082109 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-case
177 11:55:09.082236 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-event
178 11:55:09.082360 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-feedback
179 11:55:09.082486 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-raise
180 11:55:09.082610 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-reference
181 11:55:09.082735 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-runner
182 11:55:09.082865 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-set
183 11:55:09.082993 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-test-shell
184 11:55:09.083121 Updating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-add-keys (debian)
185 11:55:09.083276 Updating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-add-sources (debian)
186 11:55:09.083427 Updating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-install-packages (debian)
187 11:55:09.083586 Updating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-installed-packages (debian)
188 11:55:09.083761 Updating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/bin/lava-os-build (debian)
189 11:55:09.083888 Creating /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/environment
190 11:55:09.083989 LAVA metadata
191 11:55:09.084059 - LAVA_JOB_ID=12066559
192 11:55:09.084122 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:55:09.084221 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:55:09.084288 skipped lava-vland-overlay
195 11:55:09.084362 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:55:09.084441 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:55:09.084502 skipped lava-multinode-overlay
198 11:55:09.084575 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:55:09.084653 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:55:09.084726 Loading test definitions
201 11:55:09.084811 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:55:09.084882 Using /lava-12066559 at stage 0
203 11:55:09.085167 uuid=12066559_1.6.2.3.1 testdef=None
204 11:55:09.085255 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:55:09.085339 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:55:09.085795 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:55:09.086014 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:55:09.086577 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:55:09.086805 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:55:09.087365 runner path: /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/0/tests/0_timesync-off test_uuid 12066559_1.6.2.3.1
213 11:55:09.087522 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:55:09.087808 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:55:09.087884 Using /lava-12066559 at stage 0
217 11:55:09.087982 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:55:09.088060 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/0/tests/1_kselftest-alsa'
219 11:55:21.345759 Running '/usr/bin/git checkout kernelci.org
220 11:55:21.493160 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:55:21.493918 uuid=12066559_1.6.2.3.5 testdef=None
222 11:55:21.494098 end: 1.6.2.3.5 git-repo-action (duration 00:00:12) [common]
224 11:55:21.494389 start: 1.6.2.3.6 test-overlay (timeout 00:09:35) [common]
225 11:55:21.495367 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:55:21.495641 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:35) [common]
228 11:55:21.497313 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:55:21.497606 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:35) [common]
231 11:55:21.499058 runner path: /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/0/tests/1_kselftest-alsa test_uuid 12066559_1.6.2.3.5
232 11:55:21.499162 BOARD='mt8192-asurada-spherion-r0'
233 11:55:21.499238 BRANCH='cip-gitlab'
234 11:55:21.499321 SKIPFILE='/dev/null'
235 11:55:21.499398 SKIP_INSTALL='True'
236 11:55:21.499473 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:55:21.499550 TST_CASENAME=''
238 11:55:21.499629 TST_CMDFILES='alsa'
239 11:55:21.499826 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:55:21.500194 Creating lava-test-runner.conf files
242 11:55:21.500295 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066559/lava-overlay-qbl4ub_u/lava-12066559/0 for stage 0
243 11:55:21.500432 - 0_timesync-off
244 11:55:21.500540 - 1_kselftest-alsa
245 11:55:21.500662 end: 1.6.2.3 test-definition (duration 00:00:12) [common]
246 11:55:21.500775 start: 1.6.2.4 compress-overlay (timeout 00:09:35) [common]
247 11:55:29.036849 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:55:29.037030 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:27) [common]
249 11:55:29.037118 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:55:29.037217 end: 1.6.2 lava-overlay (duration 00:00:20) [common]
251 11:55:29.037307 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:27) [common]
252 11:55:29.207951 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:55:29.208335 start: 1.6.4 extract-modules (timeout 00:09:27) [common]
254 11:55:29.208449 extracting modules file /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui
255 11:55:29.429361 extracting modules file /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066559/extract-overlay-ramdisk-8ivve29w/ramdisk
256 11:55:29.657583 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:55:29.657754 start: 1.6.5 apply-overlay-tftp (timeout 00:09:27) [common]
258 11:55:29.657845 [common] Applying overlay to NFS
259 11:55:29.657917 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066559/compress-overlay-7c3cca_s/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui
260 11:55:30.601973 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:55:30.602140 start: 1.6.6 configure-preseed-file (timeout 00:09:26) [common]
262 11:55:30.602240 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:55:30.602335 start: 1.6.7 compress-ramdisk (timeout 00:09:26) [common]
264 11:55:30.602417 Building ramdisk /var/lib/lava/dispatcher/tmp/12066559/extract-overlay-ramdisk-8ivve29w/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066559/extract-overlay-ramdisk-8ivve29w/ramdisk
265 11:55:30.924076 >> 130520 blocks
266 11:55:32.920683 rename /var/lib/lava/dispatcher/tmp/12066559/extract-overlay-ramdisk-8ivve29w/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/ramdisk/ramdisk.cpio.gz
267 11:55:32.921138 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:55:32.921260 start: 1.6.8 prepare-kernel (timeout 00:09:23) [common]
269 11:55:32.921365 start: 1.6.8.1 prepare-fit (timeout 00:09:23) [common]
270 11:55:32.921475 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/kernel/Image'
271 11:55:44.929526 Returned 0 in 12 seconds
272 11:55:45.030421 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/kernel/image.itb
273 11:55:45.386428 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:55:45.386815 output: Created: Thu Nov 23 11:55:45 2023
275 11:55:45.386948 output: Image 0 (kernel-1)
276 11:55:45.387017 output: Description:
277 11:55:45.387085 output: Created: Thu Nov 23 11:55:45 2023
278 11:55:45.387150 output: Type: Kernel Image
279 11:55:45.387210 output: Compression: lzma compressed
280 11:55:45.387267 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
281 11:55:45.387325 output: Architecture: AArch64
282 11:55:45.387382 output: OS: Linux
283 11:55:45.387435 output: Load Address: 0x00000000
284 11:55:45.387492 output: Entry Point: 0x00000000
285 11:55:45.387547 output: Hash algo: crc32
286 11:55:45.387608 output: Hash value: e6d7c86f
287 11:55:45.387668 output: Image 1 (fdt-1)
288 11:55:45.387721 output: Description: mt8192-asurada-spherion-r0
289 11:55:45.387774 output: Created: Thu Nov 23 11:55:45 2023
290 11:55:45.387826 output: Type: Flat Device Tree
291 11:55:45.387879 output: Compression: uncompressed
292 11:55:45.387931 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:55:45.387984 output: Architecture: AArch64
294 11:55:45.388036 output: Hash algo: crc32
295 11:55:45.388088 output: Hash value: cc4352de
296 11:55:45.388141 output: Image 2 (ramdisk-1)
297 11:55:45.388193 output: Description: unavailable
298 11:55:45.388245 output: Created: Thu Nov 23 11:55:45 2023
299 11:55:45.388298 output: Type: RAMDisk Image
300 11:55:45.388351 output: Compression: Unknown Compression
301 11:55:45.388403 output: Data Size: 18756327 Bytes = 18316.73 KiB = 17.89 MiB
302 11:55:45.388459 output: Architecture: AArch64
303 11:55:45.388514 output: OS: Linux
304 11:55:45.388567 output: Load Address: unavailable
305 11:55:45.388620 output: Entry Point: unavailable
306 11:55:45.388672 output: Hash algo: crc32
307 11:55:45.388724 output: Hash value: e46fce5d
308 11:55:45.388776 output: Default Configuration: 'conf-1'
309 11:55:45.388828 output: Configuration 0 (conf-1)
310 11:55:45.388880 output: Description: mt8192-asurada-spherion-r0
311 11:55:45.388933 output: Kernel: kernel-1
312 11:55:45.388984 output: Init Ramdisk: ramdisk-1
313 11:55:45.389036 output: FDT: fdt-1
314 11:55:45.389089 output: Loadables: kernel-1
315 11:55:45.389141 output:
316 11:55:45.389353 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 11:55:45.389453 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 11:55:45.389558 end: 1.6 prepare-tftp-overlay (duration 00:00:40) [common]
319 11:55:45.389651 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:11) [common]
320 11:55:45.389732 No LXC device requested
321 11:55:45.389812 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:55:45.389896 start: 1.8 deploy-device-env (timeout 00:09:11) [common]
323 11:55:45.389975 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:55:45.390045 Checking files for TFTP limit of 4294967296 bytes.
325 11:55:45.390568 end: 1 tftp-deploy (duration 00:00:49) [common]
326 11:55:45.390672 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:55:45.390773 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:55:45.390945 substitutions:
329 11:55:45.391016 - {DTB}: 12066559/tftp-deploy-4lvz1rte/dtb/mt8192-asurada-spherion-r0.dtb
330 11:55:45.391083 - {INITRD}: 12066559/tftp-deploy-4lvz1rte/ramdisk/ramdisk.cpio.gz
331 11:55:45.391142 - {KERNEL}: 12066559/tftp-deploy-4lvz1rte/kernel/Image
332 11:55:45.391198 - {LAVA_MAC}: None
333 11:55:45.391254 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui
334 11:55:45.391309 - {NFS_SERVER_IP}: 192.168.201.1
335 11:55:45.391365 - {PRESEED_CONFIG}: None
336 11:55:45.391424 - {PRESEED_LOCAL}: None
337 11:55:45.391477 - {RAMDISK}: 12066559/tftp-deploy-4lvz1rte/ramdisk/ramdisk.cpio.gz
338 11:55:45.391531 - {ROOT_PART}: None
339 11:55:45.391584 - {ROOT}: None
340 11:55:45.391638 - {SERVER_IP}: 192.168.201.1
341 11:55:45.391691 - {TEE}: None
342 11:55:45.391745 Parsed boot commands:
343 11:55:45.391800 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:55:45.391981 Parsed boot commands: tftpboot 192.168.201.1 12066559/tftp-deploy-4lvz1rte/kernel/image.itb 12066559/tftp-deploy-4lvz1rte/kernel/cmdline
345 11:55:45.392070 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:55:45.392152 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:55:45.392248 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:55:45.392337 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:55:45.392414 Not connected, no need to disconnect.
350 11:55:45.392487 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:55:45.392568 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:55:45.392635 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 11:55:45.396598 Setting prompt string to ['lava-test: # ']
354 11:55:45.396975 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:55:45.397094 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:55:45.397190 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:55:45.397283 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:55:45.397482 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 11:55:50.540222 >> Command sent successfully.
360 11:55:50.550749 Returned 0 in 5 seconds
361 11:55:50.651842 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:55:50.653891 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:55:50.654462 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:55:50.655311 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:55:50.655859 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:55:50.656296 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:55:50.657599 [Enter `^Ec?' for help]
369 11:55:50.823295
370 11:55:50.823794
371 11:55:50.824150 F0: 102B 0000
372 11:55:50.824499
373 11:55:50.824794 F3: 1001 0000 [0200]
374 11:55:50.826446
375 11:55:50.827059 F3: 1001 0000
376 11:55:50.827506
377 11:55:50.827830 F7: 102D 0000
378 11:55:50.828161
379 11:55:50.829856 F1: 0000 0000
380 11:55:50.830278
381 11:55:50.830611 V0: 0000 0000 [0001]
382 11:55:50.830987
383 11:55:50.833408 00: 0007 8000
384 11:55:50.833847
385 11:55:50.834178 01: 0000 0000
386 11:55:50.834497
387 11:55:50.836485 BP: 0C00 0209 [0000]
388 11:55:50.836903
389 11:55:50.837236 G0: 1182 0000
390 11:55:50.837545
391 11:55:50.840552 EC: 0000 0021 [4000]
392 11:55:50.840971
393 11:55:50.841320 S7: 0000 0000 [0000]
394 11:55:50.841742
395 11:55:50.843127 CC: 0000 0000 [0001]
396 11:55:50.843559
397 11:55:50.844001 T0: 0000 0040 [010F]
398 11:55:50.844418
399 11:55:50.846949 Jump to BL
400 11:55:50.847471
401 11:55:50.869984
402 11:55:50.870492
403 11:55:50.871032
404 11:55:50.877189 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:55:50.880293 ARM64: Exception handlers installed.
406 11:55:50.884074 ARM64: Testing exception
407 11:55:50.887390 ARM64: Done test exception
408 11:55:50.894093 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:55:50.904545 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:55:50.911066 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:55:50.921687 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:55:50.928509 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:55:50.935330 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:55:50.947050 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:55:50.953594 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:55:50.973103 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:55:50.976089 WDT: Last reset was cold boot
418 11:55:50.979945 SPI1(PAD0) initialized at 2873684 Hz
419 11:55:50.983187 SPI5(PAD0) initialized at 992727 Hz
420 11:55:50.986198 VBOOT: Loading verstage.
421 11:55:50.993324 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:55:50.996427 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:55:50.999837 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:55:51.003191 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:55:51.010336 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:55:51.016495 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:55:51.027561 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:55:51.028035
429 11:55:51.028468
430 11:55:51.037970 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:55:51.041575 ARM64: Exception handlers installed.
432 11:55:51.044917 ARM64: Testing exception
433 11:55:51.045512 ARM64: Done test exception
434 11:55:51.052040 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:55:51.054794 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:55:51.070130 Probing TPM: . done!
437 11:55:51.070757 TPM ready after 0 ms
438 11:55:51.076997 Connected to device vid:did:rid of 1ae0:0028:00
439 11:55:51.083333 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:55:51.141159 Initialized TPM device CR50 revision 0
441 11:55:51.152460 tlcl_send_startup: Startup return code is 0
442 11:55:51.152592 TPM: setup succeeded
443 11:55:51.164482 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:55:51.172847 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:55:51.184816 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:55:51.195104 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:55:51.198756 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:55:51.204097 in-header: 03 07 00 00 08 00 00 00
449 11:55:51.207638 in-data: aa e4 47 04 13 02 00 00
450 11:55:51.210873 Chrome EC: UHEPI supported
451 11:55:51.217981 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:55:51.222017 in-header: 03 ad 00 00 08 00 00 00
453 11:55:51.225594 in-data: 00 20 20 08 00 00 00 00
454 11:55:51.225701 Phase 1
455 11:55:51.228722 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:55:51.236432 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:55:51.240717 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:55:51.244259 Recovery requested (1009000e)
459 11:55:51.252642 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:55:51.258092 tlcl_extend: response is 0
461 11:55:51.267457 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:55:51.273018 tlcl_extend: response is 0
463 11:55:51.279777 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:55:51.299717 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:55:51.307207 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:55:51.307304
467 11:55:51.307369
468 11:55:51.316993 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:55:51.321117 ARM64: Exception handlers installed.
470 11:55:51.321192 ARM64: Testing exception
471 11:55:51.324605 ARM64: Done test exception
472 11:55:51.345202 pmic_efuse_setting: Set efuses in 11 msecs
473 11:55:51.348469 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:55:51.355866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:55:51.358929 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:55:51.366203 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:55:51.369853 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:55:51.373697 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:55:51.377447 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:55:51.384787 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:55:51.388620 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:55:51.393072 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:55:51.396798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:55:51.404325 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:55:51.407753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:55:51.411462 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:55:51.419184 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:55:51.423402 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:55:51.430557 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:55:51.434509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:55:51.441374 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:55:51.445274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:55:51.452683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:55:51.456558 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:55:51.463837 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:55:51.467607 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:55:51.475198 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:55:51.478840 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:55:51.486289 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:55:51.490080 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:55:51.493752 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:55:51.501013 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:55:51.505026 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:55:51.508238 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:55:51.515989 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:55:51.519253 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:55:51.523361 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:55:51.530650 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:55:51.534092 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:55:51.538035 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:55:51.546401 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:55:51.549682 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:55:51.553089 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:55:51.557339 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:55:51.560633 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:55:51.567922 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:55:51.571773 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:55:51.575345 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:55:51.579032 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:55:51.583231 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:55:51.586651 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:55:51.593984 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:55:51.597778 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:55:51.601044 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:55:51.609522 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:55:51.616756 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:55:51.620244 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:55:51.631704 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:55:51.638673 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:55:51.642723 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:55:51.646079 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:55:51.649881 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:55:51.658570 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x33
534 11:55:51.662181 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:55:51.670832 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:55:51.674191 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:55:51.682586 [RTC]rtc_get_frequency_meter,154: input=15, output=789
538 11:55:51.692935 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 11:55:51.702020 [RTC]rtc_get_frequency_meter,154: input=19, output=884
540 11:55:51.712144 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 11:55:51.721022 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 11:55:51.730930 [RTC]rtc_get_frequency_meter,154: input=15, output=789
543 11:55:51.740921 [RTC]rtc_get_frequency_meter,154: input=16, output=814
544 11:55:51.744474 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 11:55:51.748555 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 11:55:51.752173 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:55:51.755979 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:55:51.763453 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:55:51.767204 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:55:51.770655 ADC[4]: Raw value=901697 ID=7
551 11:55:51.770735 ADC[3]: Raw value=213336 ID=1
552 11:55:51.774584 RAM Code: 0x71
553 11:55:51.778567 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:55:51.781795 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:55:51.789367 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:55:51.796965 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:55:51.800316 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:55:51.804563 in-header: 03 07 00 00 08 00 00 00
559 11:55:51.808023 in-data: aa e4 47 04 13 02 00 00
560 11:55:51.811921 Chrome EC: UHEPI supported
561 11:55:51.819376 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:55:51.823110 in-header: 03 ed 00 00 08 00 00 00
563 11:55:51.823200 in-data: 80 20 60 08 00 00 00 00
564 11:55:51.827065 MRC: failed to locate region type 0.
565 11:55:51.834229 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:55:51.838077 DRAM-K: Running full calibration
567 11:55:51.845059 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:55:51.845157 header.status = 0x0
569 11:55:51.849246 header.version = 0x6 (expected: 0x6)
570 11:55:51.852939 header.size = 0xd00 (expected: 0xd00)
571 11:55:51.853031 header.flags = 0x0
572 11:55:51.859795 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:55:51.878087 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:55:51.885694 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:55:51.885787 dram_init: ddr_geometry: 2
576 11:55:51.889164 [EMI] MDL number = 2
577 11:55:51.893554 [EMI] Get MDL freq = 0
578 11:55:51.893639 dram_init: ddr_type: 0
579 11:55:51.897165 is_discrete_lpddr4: 1
580 11:55:51.897290 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:55:51.897404
582 11:55:51.901137
583 11:55:51.901219 [Bian_co] ETT version 0.0.0.1
584 11:55:51.904588 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:55:51.908484
586 11:55:51.911952 dramc_set_vcore_voltage set vcore to 650000
587 11:55:51.912034 Read voltage for 800, 4
588 11:55:51.912100 Vio18 = 0
589 11:55:51.915814 Vcore = 650000
590 11:55:51.915897 Vdram = 0
591 11:55:51.915963 Vddq = 0
592 11:55:51.916023 Vmddr = 0
593 11:55:51.919359 dram_init: config_dvfs: 1
594 11:55:51.923440 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:55:51.930691 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:55:51.934639 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 11:55:51.937882 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 11:55:51.941099 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 11:55:51.944768 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 11:55:51.948080 MEM_TYPE=3, freq_sel=18
601 11:55:51.951336 sv_algorithm_assistance_LP4_1600
602 11:55:51.954726 ============ PULL DRAM RESETB DOWN ============
603 11:55:51.958028 ========== PULL DRAM RESETB DOWN end =========
604 11:55:51.964527 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:55:51.967972 ===================================
606 11:55:51.968079 LPDDR4 DRAM CONFIGURATION
607 11:55:51.971590 ===================================
608 11:55:51.974774 EX_ROW_EN[0] = 0x0
609 11:55:51.974889 EX_ROW_EN[1] = 0x0
610 11:55:51.977941 LP4Y_EN = 0x0
611 11:55:51.978033 WORK_FSP = 0x0
612 11:55:51.981676 WL = 0x2
613 11:55:51.984916 RL = 0x2
614 11:55:51.985022 BL = 0x2
615 11:55:51.988899 RPST = 0x0
616 11:55:51.989004 RD_PRE = 0x0
617 11:55:51.991844 WR_PRE = 0x1
618 11:55:51.991920 WR_PST = 0x0
619 11:55:51.995139 DBI_WR = 0x0
620 11:55:51.995244 DBI_RD = 0x0
621 11:55:51.998547 OTF = 0x1
622 11:55:52.001965 ===================================
623 11:55:52.005319 ===================================
624 11:55:52.005427 ANA top config
625 11:55:52.008250 ===================================
626 11:55:52.011984 DLL_ASYNC_EN = 0
627 11:55:52.014894 ALL_SLAVE_EN = 1
628 11:55:52.014986 NEW_RANK_MODE = 1
629 11:55:52.018275 DLL_IDLE_MODE = 1
630 11:55:52.021699 LP45_APHY_COMB_EN = 1
631 11:55:52.025121 TX_ODT_DIS = 1
632 11:55:52.025223 NEW_8X_MODE = 1
633 11:55:52.028410 ===================================
634 11:55:52.031825 ===================================
635 11:55:52.035315 data_rate = 1600
636 11:55:52.038538 CKR = 1
637 11:55:52.041719 DQ_P2S_RATIO = 8
638 11:55:52.045252 ===================================
639 11:55:52.048468 CA_P2S_RATIO = 8
640 11:55:52.048582 DQ_CA_OPEN = 0
641 11:55:52.052313 DQ_SEMI_OPEN = 0
642 11:55:52.055607 CA_SEMI_OPEN = 0
643 11:55:52.058697 CA_FULL_RATE = 0
644 11:55:52.062522 DQ_CKDIV4_EN = 1
645 11:55:52.065242 CA_CKDIV4_EN = 1
646 11:55:52.065332 CA_PREDIV_EN = 0
647 11:55:52.068742 PH8_DLY = 0
648 11:55:52.072408 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:55:52.075482 DQ_AAMCK_DIV = 4
650 11:55:52.079210 CA_AAMCK_DIV = 4
651 11:55:52.082077 CA_ADMCK_DIV = 4
652 11:55:52.082186 DQ_TRACK_CA_EN = 0
653 11:55:52.085553 CA_PICK = 800
654 11:55:52.088840 CA_MCKIO = 800
655 11:55:52.092038 MCKIO_SEMI = 0
656 11:55:52.095762 PLL_FREQ = 3068
657 11:55:52.099840 DQ_UI_PI_RATIO = 32
658 11:55:52.099944 CA_UI_PI_RATIO = 0
659 11:55:52.103421 ===================================
660 11:55:52.107188 ===================================
661 11:55:52.111099 memory_type:LPDDR4
662 11:55:52.111182 GP_NUM : 10
663 11:55:52.114789 SRAM_EN : 1
664 11:55:52.114945 MD32_EN : 0
665 11:55:52.118582 ===================================
666 11:55:52.122662 [ANA_INIT] >>>>>>>>>>>>>>
667 11:55:52.125864 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:55:52.130136 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:55:52.130216 ===================================
670 11:55:52.133496 data_rate = 1600,PCW = 0X7600
671 11:55:52.136847 ===================================
672 11:55:52.140391 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:55:52.146723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:55:52.150183 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:55:52.156931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:55:52.159987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:55:52.163456 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:55:52.163560 [ANA_INIT] flow start
679 11:55:52.166998 [ANA_INIT] PLL >>>>>>>>
680 11:55:52.170100 [ANA_INIT] PLL <<<<<<<<
681 11:55:52.170179 [ANA_INIT] MIDPI >>>>>>>>
682 11:55:52.173610 [ANA_INIT] MIDPI <<<<<<<<
683 11:55:52.177238 [ANA_INIT] DLL >>>>>>>>
684 11:55:52.177341 [ANA_INIT] flow end
685 11:55:52.183959 ============ LP4 DIFF to SE enter ============
686 11:55:52.187329 ============ LP4 DIFF to SE exit ============
687 11:55:52.190547 [ANA_INIT] <<<<<<<<<<<<<
688 11:55:52.194095 [Flow] Enable top DCM control >>>>>
689 11:55:52.197512 [Flow] Enable top DCM control <<<<<
690 11:55:52.197621 Enable DLL master slave shuffle
691 11:55:52.204145 ==============================================================
692 11:55:52.207548 Gating Mode config
693 11:55:52.210585 ==============================================================
694 11:55:52.214434 Config description:
695 11:55:52.224037 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:55:52.230812 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:55:52.233923 SELPH_MODE 0: By rank 1: By Phase
698 11:55:52.241202 ==============================================================
699 11:55:52.244297 GAT_TRACK_EN = 1
700 11:55:52.244413 RX_GATING_MODE = 2
701 11:55:52.247696 RX_GATING_TRACK_MODE = 2
702 11:55:52.250747 SELPH_MODE = 1
703 11:55:52.254470 PICG_EARLY_EN = 1
704 11:55:52.257468 VALID_LAT_VALUE = 1
705 11:55:52.264480 ==============================================================
706 11:55:52.267737 Enter into Gating configuration >>>>
707 11:55:52.271214 Exit from Gating configuration <<<<
708 11:55:52.274430 Enter into DVFS_PRE_config >>>>>
709 11:55:52.284256 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:55:52.287655 Exit from DVFS_PRE_config <<<<<
711 11:55:52.291228 Enter into PICG configuration >>>>
712 11:55:52.294616 Exit from PICG configuration <<<<
713 11:55:52.298280 [RX_INPUT] configuration >>>>>
714 11:55:52.298395 [RX_INPUT] configuration <<<<<
715 11:55:52.304369 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:55:52.311201 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:55:52.314971 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:55:52.321986 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:55:52.328614 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:55:52.335709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:55:52.338750 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:55:52.342270 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:55:52.345278 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:55:52.352041 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:55:52.355797 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:55:52.359162 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:55:52.362568 ===================================
728 11:55:52.365734 LPDDR4 DRAM CONFIGURATION
729 11:55:52.368915 ===================================
730 11:55:52.369028 EX_ROW_EN[0] = 0x0
731 11:55:52.372685 EX_ROW_EN[1] = 0x0
732 11:55:52.372790 LP4Y_EN = 0x0
733 11:55:52.375958 WORK_FSP = 0x0
734 11:55:52.379108 WL = 0x2
735 11:55:52.379198 RL = 0x2
736 11:55:52.382319 BL = 0x2
737 11:55:52.382403 RPST = 0x0
738 11:55:52.386164 RD_PRE = 0x0
739 11:55:52.386246 WR_PRE = 0x1
740 11:55:52.388961 WR_PST = 0x0
741 11:55:52.389043 DBI_WR = 0x0
742 11:55:52.392795 DBI_RD = 0x0
743 11:55:52.392877 OTF = 0x1
744 11:55:52.395958 ===================================
745 11:55:52.398918 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:55:52.405878 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:55:52.409548 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:55:52.412684 ===================================
749 11:55:52.416476 LPDDR4 DRAM CONFIGURATION
750 11:55:52.419376 ===================================
751 11:55:52.419502 EX_ROW_EN[0] = 0x10
752 11:55:52.423663 EX_ROW_EN[1] = 0x0
753 11:55:52.423792 LP4Y_EN = 0x0
754 11:55:52.426192 WORK_FSP = 0x0
755 11:55:52.426325 WL = 0x2
756 11:55:52.429424 RL = 0x2
757 11:55:52.429534 BL = 0x2
758 11:55:52.433230 RPST = 0x0
759 11:55:52.433339 RD_PRE = 0x0
760 11:55:52.436299 WR_PRE = 0x1
761 11:55:52.436380 WR_PST = 0x0
762 11:55:52.439747 DBI_WR = 0x0
763 11:55:52.439843 DBI_RD = 0x0
764 11:55:52.442790 OTF = 0x1
765 11:55:52.446099 ===================================
766 11:55:52.453028 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:55:52.456249 nWR fixed to 40
768 11:55:52.459786 [ModeRegInit_LP4] CH0 RK0
769 11:55:52.459954 [ModeRegInit_LP4] CH0 RK1
770 11:55:52.462969 [ModeRegInit_LP4] CH1 RK0
771 11:55:52.466322 [ModeRegInit_LP4] CH1 RK1
772 11:55:52.466539 match AC timing 13
773 11:55:52.473064 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:55:52.476566 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:55:52.479963 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:55:52.483239 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:55:52.489690 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:55:52.489809 [EMI DOE] emi_dcm 0
779 11:55:52.496519 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:55:52.496634 ==
781 11:55:52.500271 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:55:52.503153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:55:52.503253 ==
784 11:55:52.506693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:55:52.513532 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:55:52.523352 [CA 0] Center 37 (7~68) winsize 62
787 11:55:52.526868 [CA 1] Center 37 (6~68) winsize 63
788 11:55:52.529953 [CA 2] Center 35 (5~66) winsize 62
789 11:55:52.533707 [CA 3] Center 34 (4~65) winsize 62
790 11:55:52.536933 [CA 4] Center 34 (3~65) winsize 63
791 11:55:52.540544 [CA 5] Center 33 (3~64) winsize 62
792 11:55:52.540628
793 11:55:52.543725 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:55:52.543854
795 11:55:52.546897 [CATrainingPosCal] consider 1 rank data
796 11:55:52.550208 u2DelayCellTimex100 = 270/100 ps
797 11:55:52.553722 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:55:52.556824 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:55:52.563656 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 11:55:52.566784 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:55:52.570597 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 11:55:52.573538 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:55:52.573645
804 11:55:52.577228 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:55:52.577331
806 11:55:52.580244 [CBTSetCACLKResult] CA Dly = 33
807 11:55:52.580330 CS Dly: 5 (0~36)
808 11:55:52.580397 ==
809 11:55:52.583576 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:55:52.590664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:55:52.590747 ==
812 11:55:52.593562 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:55:52.600359 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:55:52.609524 [CA 0] Center 37 (6~68) winsize 63
815 11:55:52.613084 [CA 1] Center 37 (7~68) winsize 62
816 11:55:52.616271 [CA 2] Center 35 (5~66) winsize 62
817 11:55:52.619669 [CA 3] Center 35 (4~66) winsize 63
818 11:55:52.623147 [CA 4] Center 34 (4~65) winsize 62
819 11:55:52.626635 [CA 5] Center 33 (3~64) winsize 62
820 11:55:52.626738
821 11:55:52.629813 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:55:52.629890
823 11:55:52.633165 [CATrainingPosCal] consider 2 rank data
824 11:55:52.636406 u2DelayCellTimex100 = 270/100 ps
825 11:55:52.640092 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:55:52.643187 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:55:52.646367 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 11:55:52.653321 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:55:52.656661 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
830 11:55:52.660012 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:55:52.660231
832 11:55:52.663412 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:55:52.663494
834 11:55:52.666724 [CBTSetCACLKResult] CA Dly = 33
835 11:55:52.666805 CS Dly: 6 (0~38)
836 11:55:52.666918
837 11:55:52.670772 ----->DramcWriteLeveling(PI) begin...
838 11:55:52.670868 ==
839 11:55:52.673381 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:55:52.677549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:55:52.680733 ==
842 11:55:52.680831 Write leveling (Byte 0): 29 => 29
843 11:55:52.684538 Write leveling (Byte 1): 27 => 27
844 11:55:52.687421 DramcWriteLeveling(PI) end<-----
845 11:55:52.687503
846 11:55:52.687568 ==
847 11:55:52.691222 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:55:52.694646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:55:52.694728 ==
850 11:55:52.698350 [Gating] SW mode calibration
851 11:55:52.705251 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:55:52.712387 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:55:52.715577 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:55:52.719075 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:55:52.725545 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
856 11:55:52.728987 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 11:55:52.732160 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:55:52.736066 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:55:52.742547 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:55:52.746001 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:55:52.749469 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:55:52.755915 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:55:52.759621 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:55:52.762662 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:55:52.769225 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:55:52.772499 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:55:52.776301 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:55:52.782922 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:55:52.786206 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:55:52.789318 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:55:52.796045 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
872 11:55:52.799333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 11:55:52.802802 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:55:52.806410 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:55:52.812692 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:55:52.816458 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:55:52.819588 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:55:52.826062 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:55:52.829218 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
880 11:55:52.832937 0 9 12 | B1->B0 | 2727 2f2f | 0 0 | (0 0) (0 0)
881 11:55:52.839939 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:55:52.843021 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:55:52.846505 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:55:52.853090 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:55:52.856303 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:55:52.860123 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 11:55:52.863298 0 10 8 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 0)
888 11:55:52.870222 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
889 11:55:52.873344 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:55:52.876758 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:55:52.883475 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:55:52.886976 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:55:52.890433 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:55:52.896804 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 11:55:52.900547 0 11 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
896 11:55:52.903777 0 11 12 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
897 11:55:52.906784 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:55:52.913518 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:55:52.916900 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:55:52.920607 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:55:52.926872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:55:52.930721 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:55:52.933900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 11:55:52.940729 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:55:52.944288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:55:52.947418 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:55:52.954003 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:55:52.957282 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:55:52.960612 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:55:52.967304 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:55:52.971044 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:55:52.974266 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:55:52.977262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:55:52.984655 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:55:52.987680 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:55:52.990839 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:55:52.997657 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:55:53.000967 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:55:53.004558 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 11:55:53.011153 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 11:55:53.011245 Total UI for P1: 0, mck2ui 16
922 11:55:53.017852 best dqsien dly found for B0: ( 0, 14, 8)
923 11:55:53.017935 Total UI for P1: 0, mck2ui 16
924 11:55:53.021137 best dqsien dly found for B1: ( 0, 14, 8)
925 11:55:53.024957 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 11:55:53.031245 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 11:55:53.031329
928 11:55:53.035336 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 11:55:53.037992 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:55:53.041496 [Gating] SW calibration Done
931 11:55:53.041608 ==
932 11:55:53.044947 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:55:53.048305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:55:53.048388 ==
935 11:55:53.048454 RX Vref Scan: 0
936 11:55:53.048525
937 11:55:53.051631 RX Vref 0 -> 0, step: 1
938 11:55:53.051713
939 11:55:53.055242 RX Delay -130 -> 252, step: 16
940 11:55:53.058394 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:55:53.061464 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:55:53.065157 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:55:53.072134 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:55:53.075291 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:55:53.078394 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 11:55:53.081829 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
947 11:55:53.085712 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
948 11:55:53.092376 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 11:55:53.095409 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
950 11:55:53.098823 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 11:55:53.102236 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 11:55:53.105514 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:55:53.112436 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 11:55:53.115809 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:55:53.119306 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 11:55:53.119578 ==
957 11:55:53.122606 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:55:53.125954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:55:53.126271 ==
960 11:55:53.129236 DQS Delay:
961 11:55:53.129597 DQS0 = 0, DQS1 = 0
962 11:55:53.129965 DQM Delay:
963 11:55:53.132841 DQM0 = 84, DQM1 = 79
964 11:55:53.133381 DQ Delay:
965 11:55:53.136201 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:55:53.139428 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
967 11:55:53.143029 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
968 11:55:53.146102 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 11:55:53.146550
970 11:55:53.147002
971 11:55:53.147390 ==
972 11:55:53.149447 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:55:53.156254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:55:53.156747 ==
975 11:55:53.157282
976 11:55:53.157658
977 11:55:53.158111 TX Vref Scan disable
978 11:55:53.159499 == TX Byte 0 ==
979 11:55:53.162722 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
980 11:55:53.166015 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
981 11:55:53.170081 == TX Byte 1 ==
982 11:55:53.172817 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 11:55:53.176353 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 11:55:53.179735 ==
985 11:55:53.182818 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:55:53.186753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:55:53.187250 ==
988 11:55:53.198814 TX Vref=22, minBit 3, minWin=27, winSum=438
989 11:55:53.202539 TX Vref=24, minBit 0, minWin=27, winSum=442
990 11:55:53.205953 TX Vref=26, minBit 8, minWin=27, winSum=447
991 11:55:53.209078 TX Vref=28, minBit 0, minWin=27, winSum=446
992 11:55:53.212452 TX Vref=30, minBit 12, minWin=27, winSum=453
993 11:55:53.215648 TX Vref=32, minBit 8, minWin=27, winSum=447
994 11:55:53.222477 [TxChooseVref] Worse bit 12, Min win 27, Win sum 453, Final Vref 30
995 11:55:53.222959
996 11:55:53.226097 Final TX Range 1 Vref 30
997 11:55:53.226550
998 11:55:53.227172 ==
999 11:55:53.229131 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:55:53.232977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:55:53.233456 ==
1002 11:55:53.233803
1003 11:55:53.234115
1004 11:55:53.235901 TX Vref Scan disable
1005 11:55:53.239389 == TX Byte 0 ==
1006 11:55:53.242716 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1007 11:55:53.246273 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1008 11:55:53.249607 == TX Byte 1 ==
1009 11:55:53.253158 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1010 11:55:53.256354 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1011 11:55:53.256778
1012 11:55:53.259609 [DATLAT]
1013 11:55:53.260030 Freq=800, CH0 RK0
1014 11:55:53.260381
1015 11:55:53.262803 DATLAT Default: 0xa
1016 11:55:53.263255 0, 0xFFFF, sum = 0
1017 11:55:53.266183 1, 0xFFFF, sum = 0
1018 11:55:53.266611 2, 0xFFFF, sum = 0
1019 11:55:53.269818 3, 0xFFFF, sum = 0
1020 11:55:53.270246 4, 0xFFFF, sum = 0
1021 11:55:53.272964 5, 0xFFFF, sum = 0
1022 11:55:53.273391 6, 0xFFFF, sum = 0
1023 11:55:53.276471 7, 0xFFFF, sum = 0
1024 11:55:53.276933 8, 0xFFFF, sum = 0
1025 11:55:53.280173 9, 0x0, sum = 1
1026 11:55:53.280592 10, 0x0, sum = 2
1027 11:55:53.283339 11, 0x0, sum = 3
1028 11:55:53.283760 12, 0x0, sum = 4
1029 11:55:53.286828 best_step = 10
1030 11:55:53.287264
1031 11:55:53.287593 ==
1032 11:55:53.290145 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:55:53.292963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:55:53.293381 ==
1035 11:55:53.293709 RX Vref Scan: 1
1036 11:55:53.294014
1037 11:55:53.296927 Set Vref Range= 32 -> 127
1038 11:55:53.297523
1039 11:55:53.299948 RX Vref 32 -> 127, step: 1
1040 11:55:53.300364
1041 11:55:53.303040 RX Delay -95 -> 252, step: 8
1042 11:55:53.303458
1043 11:55:53.306771 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:55:53.310038 [Byte1]: 32
1045 11:55:53.310451
1046 11:55:53.313533 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:55:53.316772 [Byte1]: 33
1048 11:55:53.317189
1049 11:55:53.320437 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:55:53.323922 [Byte1]: 34
1051 11:55:53.324002
1052 11:55:53.327182 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:55:53.330659 [Byte1]: 35
1054 11:55:53.334473
1055 11:55:53.337626 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:55:53.337707 [Byte1]: 36
1057 11:55:53.341644
1058 11:55:53.341724 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:55:53.345690 [Byte1]: 37
1060 11:55:53.349753
1061 11:55:53.349833 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:55:53.353378 [Byte1]: 38
1063 11:55:53.357882
1064 11:55:53.357962 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:55:53.360904 [Byte1]: 39
1066 11:55:53.364812
1067 11:55:53.364930 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:55:53.368126 [Byte1]: 40
1069 11:55:53.372561
1070 11:55:53.372641 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:55:53.375883 [Byte1]: 41
1072 11:55:53.380271
1073 11:55:53.380352 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:55:53.383389 [Byte1]: 42
1075 11:55:53.387810
1076 11:55:53.387890 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:55:53.390741 [Byte1]: 43
1078 11:55:53.394875
1079 11:55:53.394961 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:55:53.398003 [Byte1]: 44
1081 11:55:53.402655
1082 11:55:53.402736 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:55:53.405587 [Byte1]: 45
1084 11:55:53.410141
1085 11:55:53.410253 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:55:53.413130 [Byte1]: 46
1087 11:55:53.417464
1088 11:55:53.417550 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:55:53.420934 [Byte1]: 47
1090 11:55:53.425311
1091 11:55:53.425414 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:55:53.428599 [Byte1]: 48
1093 11:55:53.432875
1094 11:55:53.432976 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:55:53.436152 [Byte1]: 49
1096 11:55:53.440584
1097 11:55:53.440685 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:55:53.444021 [Byte1]: 50
1099 11:55:53.447791
1100 11:55:53.447869 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:55:53.451398 [Byte1]: 51
1102 11:55:53.455819
1103 11:55:53.455919 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:55:53.458660 [Byte1]: 52
1105 11:55:53.463042
1106 11:55:53.463152 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:55:53.466271 [Byte1]: 53
1108 11:55:53.470708
1109 11:55:53.470817 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:55:53.474274 [Byte1]: 54
1111 11:55:53.478291
1112 11:55:53.478386 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:55:53.482137 [Byte1]: 55
1114 11:55:53.486375
1115 11:55:53.486451 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:55:53.489638 [Byte1]: 56
1117 11:55:53.493684
1118 11:55:53.493757 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:55:53.496691 [Byte1]: 57
1120 11:55:53.500993
1121 11:55:53.501099 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:55:53.504362 [Byte1]: 58
1123 11:55:53.508682
1124 11:55:53.508786 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:55:53.512209 [Byte1]: 59
1126 11:55:53.516283
1127 11:55:53.516390 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:55:53.519695 [Byte1]: 60
1129 11:55:53.524052
1130 11:55:53.524133 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:55:53.527241 [Byte1]: 61
1132 11:55:53.531591
1133 11:55:53.531671 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:55:53.535043 [Byte1]: 62
1135 11:55:53.539218
1136 11:55:53.539324 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:55:53.542538 [Byte1]: 63
1138 11:55:53.546691
1139 11:55:53.546771 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:55:53.550028 [Byte1]: 64
1141 11:55:53.554464
1142 11:55:53.554551 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:55:53.557591 [Byte1]: 65
1144 11:55:53.562167
1145 11:55:53.562246 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:55:53.565814 [Byte1]: 66
1147 11:55:53.569475
1148 11:55:53.569556 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:55:53.572907 [Byte1]: 67
1150 11:55:53.577493
1151 11:55:53.577595 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:55:53.580435 [Byte1]: 68
1153 11:55:53.584761
1154 11:55:53.584833 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:55:53.587932 [Byte1]: 69
1156 11:55:53.592682
1157 11:55:53.592779 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:55:53.595833 [Byte1]: 70
1159 11:55:53.600231
1160 11:55:53.600310 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:55:53.603517 [Byte1]: 71
1162 11:55:53.607441
1163 11:55:53.607520 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:55:53.610575 [Byte1]: 72
1165 11:55:53.615244
1166 11:55:53.615314 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:55:53.618568 [Byte1]: 73
1168 11:55:53.622983
1169 11:55:53.623054 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:55:53.625969 [Byte1]: 74
1171 11:55:53.630633
1172 11:55:53.630731 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:55:53.633463 [Byte1]: 75
1174 11:55:53.638140
1175 11:55:53.638220 Final RX Vref Byte 0 = 62 to rank0
1176 11:55:53.641224 Final RX Vref Byte 1 = 57 to rank0
1177 11:55:53.644594 Final RX Vref Byte 0 = 62 to rank1
1178 11:55:53.647833 Final RX Vref Byte 1 = 57 to rank1==
1179 11:55:53.651417 Dram Type= 6, Freq= 0, CH_0, rank 0
1180 11:55:53.654660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1181 11:55:53.657925 ==
1182 11:55:53.658023 DQS Delay:
1183 11:55:53.658087 DQS0 = 0, DQS1 = 0
1184 11:55:53.661731 DQM Delay:
1185 11:55:53.661827 DQM0 = 87, DQM1 = 78
1186 11:55:53.664803 DQ Delay:
1187 11:55:53.664901 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1188 11:55:53.668181 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1189 11:55:53.671488 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =76
1190 11:55:53.675110 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1191 11:55:53.675180
1192 11:55:53.678327
1193 11:55:53.684850 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
1194 11:55:53.688409 CH0 RK0: MR19=606, MR18=2A11
1195 11:55:53.694999 CH0_RK0: MR19=0x606, MR18=0x2A11, DQSOSC=399, MR23=63, INC=92, DEC=61
1196 11:55:53.695072
1197 11:55:53.698547 ----->DramcWriteLeveling(PI) begin...
1198 11:55:53.698623 ==
1199 11:55:53.701864 Dram Type= 6, Freq= 0, CH_0, rank 1
1200 11:55:53.704774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1201 11:55:53.704847 ==
1202 11:55:53.708395 Write leveling (Byte 0): 31 => 31
1203 11:55:53.711947 Write leveling (Byte 1): 28 => 28
1204 11:55:53.715152 DramcWriteLeveling(PI) end<-----
1205 11:55:53.715233
1206 11:55:53.715296 ==
1207 11:55:53.718541 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 11:55:53.721786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 11:55:53.721889 ==
1210 11:55:53.725096 [Gating] SW mode calibration
1211 11:55:53.731960 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1212 11:55:53.735459 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1213 11:55:53.742206 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1214 11:55:53.745298 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1215 11:55:53.748955 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1216 11:55:53.755605 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:55:53.799558 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:55:53.799867 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:55:53.799967 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:55:53.800452 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:55:53.800874 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:55:53.801164 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:55:53.801261 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:55:53.801350 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:55:53.801655 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:55:53.802099 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:55:53.830064 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:55:53.830462 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:55:53.830562 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:55:53.831215 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1231 11:55:53.831489 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1232 11:55:53.831587 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:55:53.834716 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:55:53.834813 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:55:53.837946 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:55:53.841334 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:55:53.848545 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:55:53.851532 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1239 11:55:53.854751 0 9 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
1240 11:55:53.858451 0 9 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1241 11:55:53.865808 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:55:53.868357 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:55:53.872242 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:55:53.878320 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:55:53.882054 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:55:53.885530 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
1247 11:55:53.892144 0 10 8 | B1->B0 | 3333 2626 | 0 0 | (0 1) (0 0)
1248 11:55:53.895535 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1249 11:55:53.899262 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:55:53.901980 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:55:53.908948 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:55:53.912443 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:55:53.915526 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:55:53.922376 0 11 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
1255 11:55:53.926011 0 11 8 | B1->B0 | 2828 3f3f | 0 0 | (0 0) (0 0)
1256 11:55:53.929596 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:55:53.933155 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:55:53.941039 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:55:53.944087 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:55:53.947637 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:55:53.951346 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:55:53.958371 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1263 11:55:53.961850 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1264 11:55:53.964931 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1265 11:55:53.968538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:55:53.975517 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:55:53.978670 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:55:53.981872 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:55:53.988962 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:55:53.991994 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:55:53.995776 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:55:54.002175 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:55:54.005484 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:55:54.009042 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:55:54.012300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:55:54.019201 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:55:54.022393 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:55:54.025523 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1279 11:55:54.032037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1280 11:55:54.035411 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 11:55:54.038976 Total UI for P1: 0, mck2ui 16
1282 11:55:54.042518 best dqsien dly found for B0: ( 0, 14, 6)
1283 11:55:54.046012 Total UI for P1: 0, mck2ui 16
1284 11:55:54.049161 best dqsien dly found for B1: ( 0, 14, 8)
1285 11:55:54.052626 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1286 11:55:54.055803 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1287 11:55:54.055920
1288 11:55:54.059240 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1289 11:55:54.062357 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1290 11:55:54.065779 [Gating] SW calibration Done
1291 11:55:54.065881 ==
1292 11:55:54.069010 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 11:55:54.072782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 11:55:54.072891 ==
1295 11:55:54.076126 RX Vref Scan: 0
1296 11:55:54.076231
1297 11:55:54.079763 RX Vref 0 -> 0, step: 1
1298 11:55:54.079867
1299 11:55:54.079960 RX Delay -130 -> 252, step: 16
1300 11:55:54.085654 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1301 11:55:54.089075 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1302 11:55:54.092620 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1303 11:55:54.096151 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1304 11:55:54.099442 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1305 11:55:54.106461 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1306 11:55:54.109777 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1307 11:55:54.112596 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1308 11:55:54.115918 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1309 11:55:54.119957 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1310 11:55:54.122836 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1311 11:55:54.129505 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1312 11:55:54.132711 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1313 11:55:54.136346 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1314 11:55:54.139781 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1315 11:55:54.142951 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1316 11:55:54.146357 ==
1317 11:55:54.149667 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 11:55:54.152975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 11:55:54.153079 ==
1320 11:55:54.153169 DQS Delay:
1321 11:55:54.156605 DQS0 = 0, DQS1 = 0
1322 11:55:54.156677 DQM Delay:
1323 11:55:54.160033 DQM0 = 86, DQM1 = 76
1324 11:55:54.160130 DQ Delay:
1325 11:55:54.163164 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1326 11:55:54.166939 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =93
1327 11:55:54.170009 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1328 11:55:54.173523 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1329 11:55:54.173624
1330 11:55:54.173713
1331 11:55:54.173799 ==
1332 11:55:54.176384 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 11:55:54.180155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 11:55:54.180229 ==
1335 11:55:54.180298
1336 11:55:54.180356
1337 11:55:54.183235 TX Vref Scan disable
1338 11:55:54.186578 == TX Byte 0 ==
1339 11:55:54.190572 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1340 11:55:54.193616 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1341 11:55:54.197046 == TX Byte 1 ==
1342 11:55:54.200203 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1343 11:55:54.203471 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1344 11:55:54.203570 ==
1345 11:55:54.206784 Dram Type= 6, Freq= 0, CH_0, rank 1
1346 11:55:54.209881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1347 11:55:54.209961 ==
1348 11:55:54.225205 TX Vref=22, minBit 3, minWin=27, winSum=447
1349 11:55:54.228264 TX Vref=24, minBit 5, minWin=27, winSum=447
1350 11:55:54.231354 TX Vref=26, minBit 9, minWin=27, winSum=448
1351 11:55:54.234578 TX Vref=28, minBit 9, minWin=27, winSum=450
1352 11:55:54.238098 TX Vref=30, minBit 9, minWin=27, winSum=450
1353 11:55:54.241469 TX Vref=32, minBit 12, minWin=27, winSum=452
1354 11:55:54.248808 [TxChooseVref] Worse bit 12, Min win 27, Win sum 452, Final Vref 32
1355 11:55:54.248883
1356 11:55:54.251581 Final TX Range 1 Vref 32
1357 11:55:54.251654
1358 11:55:54.251722 ==
1359 11:55:54.255199 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:55:54.258486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:55:54.258560 ==
1362 11:55:54.258620
1363 11:55:54.261870
1364 11:55:54.261954 TX Vref Scan disable
1365 11:55:54.265025 == TX Byte 0 ==
1366 11:55:54.268311 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1367 11:55:54.271810 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1368 11:55:54.274884 == TX Byte 1 ==
1369 11:55:54.278138 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1370 11:55:54.282094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1371 11:55:54.282193
1372 11:55:54.285268 [DATLAT]
1373 11:55:54.285358 Freq=800, CH0 RK1
1374 11:55:54.285424
1375 11:55:54.288334 DATLAT Default: 0xa
1376 11:55:54.288406 0, 0xFFFF, sum = 0
1377 11:55:54.291739 1, 0xFFFF, sum = 0
1378 11:55:54.291813 2, 0xFFFF, sum = 0
1379 11:55:54.294989 3, 0xFFFF, sum = 0
1380 11:55:54.295071 4, 0xFFFF, sum = 0
1381 11:55:54.298680 5, 0xFFFF, sum = 0
1382 11:55:54.298798 6, 0xFFFF, sum = 0
1383 11:55:54.301803 7, 0xFFFF, sum = 0
1384 11:55:54.301883 8, 0xFFFF, sum = 0
1385 11:55:54.305287 9, 0x0, sum = 1
1386 11:55:54.305368 10, 0x0, sum = 2
1387 11:55:54.308683 11, 0x0, sum = 3
1388 11:55:54.308764 12, 0x0, sum = 4
1389 11:55:54.311864 best_step = 10
1390 11:55:54.311944
1391 11:55:54.312007 ==
1392 11:55:54.315461 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 11:55:54.318830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 11:55:54.318970 ==
1395 11:55:54.321980 RX Vref Scan: 0
1396 11:55:54.322060
1397 11:55:54.322130 RX Vref 0 -> 0, step: 1
1398 11:55:54.322218
1399 11:55:54.325125 RX Delay -95 -> 252, step: 8
1400 11:55:54.328640 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
1401 11:55:54.335854 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1402 11:55:54.339250 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1403 11:55:54.342289 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1404 11:55:54.345659 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1405 11:55:54.348982 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1406 11:55:54.355820 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1407 11:55:54.358820 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1408 11:55:54.362164 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1409 11:55:54.365942 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1410 11:55:54.369067 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1411 11:55:54.375661 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1412 11:55:54.379152 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1413 11:55:54.382696 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1414 11:55:54.385964 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1415 11:55:54.389544 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1416 11:55:54.389644 ==
1417 11:55:54.392692 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 11:55:54.399318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 11:55:54.399397 ==
1420 11:55:54.399461 DQS Delay:
1421 11:55:54.402818 DQS0 = 0, DQS1 = 0
1422 11:55:54.402940 DQM Delay:
1423 11:55:54.403002 DQM0 = 87, DQM1 = 78
1424 11:55:54.406431 DQ Delay:
1425 11:55:54.409339 DQ0 =84, DQ1 =88, DQ2 =84, DQ3 =84
1426 11:55:54.413021 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1427 11:55:54.413125 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1428 11:55:54.419544 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =88
1429 11:55:54.419622
1430 11:55:54.419685
1431 11:55:54.426436 [DQSOSCAuto] RK1, (LSB)MR18= 0x301a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1432 11:55:54.429770 CH0 RK1: MR19=606, MR18=301A
1433 11:55:54.436365 CH0_RK1: MR19=0x606, MR18=0x301A, DQSOSC=397, MR23=63, INC=93, DEC=62
1434 11:55:54.439526 [RxdqsGatingPostProcess] freq 800
1435 11:55:54.442761 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1436 11:55:54.446008 Pre-setting of DQS Precalculation
1437 11:55:54.452779 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1438 11:55:54.452884 ==
1439 11:55:54.456431 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:55:54.459579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:55:54.459677 ==
1442 11:55:54.466567 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1443 11:55:54.469828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1444 11:55:54.479672 [CA 0] Center 36 (6~66) winsize 61
1445 11:55:54.482949 [CA 1] Center 36 (6~66) winsize 61
1446 11:55:54.486207 [CA 2] Center 35 (5~65) winsize 61
1447 11:55:54.490143 [CA 3] Center 33 (3~64) winsize 62
1448 11:55:54.493085 [CA 4] Center 34 (4~65) winsize 62
1449 11:55:54.496810 [CA 5] Center 33 (3~64) winsize 62
1450 11:55:54.496910
1451 11:55:54.500024 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1452 11:55:54.500122
1453 11:55:54.503197 [CATrainingPosCal] consider 1 rank data
1454 11:55:54.506484 u2DelayCellTimex100 = 270/100 ps
1455 11:55:54.510010 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1456 11:55:54.513130 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1457 11:55:54.517000 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1458 11:55:54.523275 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1459 11:55:54.527024 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1460 11:55:54.530007 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1461 11:55:54.530091
1462 11:55:54.533432 CA PerBit enable=1, Macro0, CA PI delay=33
1463 11:55:54.533534
1464 11:55:54.536661 [CBTSetCACLKResult] CA Dly = 33
1465 11:55:54.536738 CS Dly: 5 (0~36)
1466 11:55:54.536828 ==
1467 11:55:54.540604 Dram Type= 6, Freq= 0, CH_1, rank 1
1468 11:55:54.547238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1469 11:55:54.547318 ==
1470 11:55:54.550549 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1471 11:55:54.557138 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1472 11:55:54.566197 [CA 0] Center 36 (6~66) winsize 61
1473 11:55:54.568937 [CA 1] Center 36 (6~66) winsize 61
1474 11:55:54.572675 [CA 2] Center 34 (4~64) winsize 61
1475 11:55:54.576074 [CA 3] Center 33 (3~64) winsize 62
1476 11:55:54.579260 [CA 4] Center 34 (4~65) winsize 62
1477 11:55:54.582618 [CA 5] Center 33 (3~64) winsize 62
1478 11:55:54.582719
1479 11:55:54.585987 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1480 11:55:54.586087
1481 11:55:54.589272 [CATrainingPosCal] consider 2 rank data
1482 11:55:54.593100 u2DelayCellTimex100 = 270/100 ps
1483 11:55:54.596629 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1484 11:55:54.600260 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1485 11:55:54.603960 CA2 delay=34 (5~64),Diff = 1 PI (7 cell)
1486 11:55:54.608230 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1487 11:55:54.611489 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1488 11:55:54.615868 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1489 11:55:54.615950
1490 11:55:54.619015 CA PerBit enable=1, Macro0, CA PI delay=33
1491 11:55:54.619090
1492 11:55:54.623380 [CBTSetCACLKResult] CA Dly = 33
1493 11:55:54.623461 CS Dly: 5 (0~37)
1494 11:55:54.623525
1495 11:55:54.626229 ----->DramcWriteLeveling(PI) begin...
1496 11:55:54.626330 ==
1497 11:55:54.630057 Dram Type= 6, Freq= 0, CH_1, rank 0
1498 11:55:54.633570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1499 11:55:54.633644 ==
1500 11:55:54.636999 Write leveling (Byte 0): 27 => 27
1501 11:55:54.640449 Write leveling (Byte 1): 27 => 27
1502 11:55:54.643660 DramcWriteLeveling(PI) end<-----
1503 11:55:54.643738
1504 11:55:54.643800 ==
1505 11:55:54.647107 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 11:55:54.650364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 11:55:54.653961 ==
1508 11:55:54.654034 [Gating] SW mode calibration
1509 11:55:54.660436 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1510 11:55:54.667766 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1511 11:55:54.670467 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1512 11:55:54.677297 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1513 11:55:54.680714 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1514 11:55:54.684282 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:55:54.691052 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:55:54.694306 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:55:54.697202 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:55:54.700942 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:55:54.707410 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:55:54.710655 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:55:54.714060 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:55:54.720967 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:55:54.724441 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:55:54.727984 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:55:54.734626 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:55:54.738209 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:55:54.741026 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1528 11:55:54.748032 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1529 11:55:54.751400 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:55:54.754538 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:55:54.757910 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:55:54.764661 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:55:54.767749 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:55:54.771244 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:55:54.777943 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:55:54.781237 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:55:54.784854 0 9 8 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1538 11:55:54.791559 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:55:54.794967 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:55:54.798064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:55:54.804684 0 9 24 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1542 11:55:54.808356 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:55:54.811591 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:55:54.815078 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
1545 11:55:54.821724 0 10 8 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (0 1)
1546 11:55:54.825319 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:55:54.828677 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:55:54.835529 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:55:54.838707 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:55:54.842330 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:55:54.849155 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:55:54.852249 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1553 11:55:54.855579 0 11 8 | B1->B0 | 3535 3131 | 0 0 | (0 0) (0 0)
1554 11:55:54.862393 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:55:54.865924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:55:54.869136 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:55:54.872559 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:55:54.879259 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:55:54.882264 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:55:54.886174 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:55:54.892567 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1562 11:55:54.895801 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:55:54.899207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:55:54.906102 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:55:54.909237 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:55:54.912812 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:55:54.919619 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:55:54.922929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:55:54.925929 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:55:54.929462 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:55:54.936805 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:55:54.939643 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:55:54.942775 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:55:54.949921 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:55:54.953191 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:55:54.956836 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:55:54.963297 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1578 11:55:54.966945 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 11:55:54.969857 Total UI for P1: 0, mck2ui 16
1580 11:55:54.973355 best dqsien dly found for B0: ( 0, 14, 8)
1581 11:55:54.977053 Total UI for P1: 0, mck2ui 16
1582 11:55:54.980084 best dqsien dly found for B1: ( 0, 14, 8)
1583 11:55:54.983680 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1584 11:55:54.986825 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1585 11:55:54.987392
1586 11:55:54.989836 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1587 11:55:54.993134 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1588 11:55:54.996119 [Gating] SW calibration Done
1589 11:55:54.996199 ==
1590 11:55:55 Dram Type= 6, Freq= 0, CH_1, rank 0
1591 11:55:55.002886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1592 11:55:55.002981 ==
1593 11:55:55.006186 RX Vref Scan: 0
1594 11:55:55.006267
1595 11:55:55.006330 RX Vref 0 -> 0, step: 1
1596 11:55:55.009684
1597 11:55:55.009765 RX Delay -130 -> 252, step: 16
1598 11:55:55.016388 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1599 11:55:55.019742 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1600 11:55:55.023172 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1601 11:55:55.026097 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1602 11:55:55.029488 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1603 11:55:55.036416 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1604 11:55:55.039619 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1605 11:55:55.042994 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1606 11:55:55.046339 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1607 11:55:55.049696 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1608 11:55:55.053078 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1609 11:55:55.059902 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1610 11:55:55.063229 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1611 11:55:55.066639 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1612 11:55:55.070525 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1613 11:55:55.073470 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1614 11:55:55.076891 ==
1615 11:55:55.079985 Dram Type= 6, Freq= 0, CH_1, rank 0
1616 11:55:55.083559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1617 11:55:55.083670 ==
1618 11:55:55.083757 DQS Delay:
1619 11:55:55.086844 DQS0 = 0, DQS1 = 0
1620 11:55:55.086963 DQM Delay:
1621 11:55:55.090065 DQM0 = 84, DQM1 = 77
1622 11:55:55.090197 DQ Delay:
1623 11:55:55.093190 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1624 11:55:55.096464 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1625 11:55:55.100117 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1626 11:55:55.103477 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1627 11:55:55.103554
1628 11:55:55.103616
1629 11:55:55.103680 ==
1630 11:55:55.106801 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 11:55:55.109949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 11:55:55.110027 ==
1633 11:55:55.110090
1634 11:55:55.110153
1635 11:55:55.113282 TX Vref Scan disable
1636 11:55:55.117046 == TX Byte 0 ==
1637 11:55:55.120292 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 11:55:55.123665 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 11:55:55.127088 == TX Byte 1 ==
1640 11:55:55.130355 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1641 11:55:55.134071 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1642 11:55:55.134249 ==
1643 11:55:55.136823 Dram Type= 6, Freq= 0, CH_1, rank 0
1644 11:55:55.140528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1645 11:55:55.140639 ==
1646 11:55:55.154901 TX Vref=22, minBit 13, minWin=26, winSum=435
1647 11:55:55.158141 TX Vref=24, minBit 10, minWin=26, winSum=437
1648 11:55:55.161323 TX Vref=26, minBit 8, minWin=27, winSum=447
1649 11:55:55.164807 TX Vref=28, minBit 4, minWin=27, winSum=447
1650 11:55:55.167769 TX Vref=30, minBit 0, minWin=27, winSum=451
1651 11:55:55.171247 TX Vref=32, minBit 0, minWin=28, winSum=454
1652 11:55:55.178239 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1653 11:55:55.178592
1654 11:55:55.181941 Final TX Range 1 Vref 32
1655 11:55:55.182487
1656 11:55:55.183004 ==
1657 11:55:55.185801 Dram Type= 6, Freq= 0, CH_1, rank 0
1658 11:55:55.188763 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1659 11:55:55.189349 ==
1660 11:55:55.189863
1661 11:55:55.190454
1662 11:55:55.192366 TX Vref Scan disable
1663 11:55:55.195620 == TX Byte 0 ==
1664 11:55:55.198546 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 11:55:55.202092 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 11:55:55.205413 == TX Byte 1 ==
1667 11:55:55.208919 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1668 11:55:55.212419 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1669 11:55:55.212979
1670 11:55:55.215892 [DATLAT]
1671 11:55:55.216488 Freq=800, CH1 RK0
1672 11:55:55.216998
1673 11:55:55.219187 DATLAT Default: 0xa
1674 11:55:55.219756 0, 0xFFFF, sum = 0
1675 11:55:55.221932 1, 0xFFFF, sum = 0
1676 11:55:55.222479 2, 0xFFFF, sum = 0
1677 11:55:55.225512 3, 0xFFFF, sum = 0
1678 11:55:55.225931 4, 0xFFFF, sum = 0
1679 11:55:55.229234 5, 0xFFFF, sum = 0
1680 11:55:55.229653 6, 0xFFFF, sum = 0
1681 11:55:55.232107 7, 0xFFFF, sum = 0
1682 11:55:55.232523 8, 0xFFFF, sum = 0
1683 11:55:55.235389 9, 0x0, sum = 1
1684 11:55:55.235808 10, 0x0, sum = 2
1685 11:55:55.239301 11, 0x0, sum = 3
1686 11:55:55.239720 12, 0x0, sum = 4
1687 11:55:55.242280 best_step = 10
1688 11:55:55.242691
1689 11:55:55.243091 ==
1690 11:55:55.245705 Dram Type= 6, Freq= 0, CH_1, rank 0
1691 11:55:55.249046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1692 11:55:55.249465 ==
1693 11:55:55.249791 RX Vref Scan: 1
1694 11:55:55.250096
1695 11:55:55.252509 Set Vref Range= 32 -> 127
1696 11:55:55.252922
1697 11:55:55.255903 RX Vref 32 -> 127, step: 1
1698 11:55:55.256313
1699 11:55:55.258816 RX Delay -95 -> 252, step: 8
1700 11:55:55.259294
1701 11:55:55.262229 Set Vref, RX VrefLevel [Byte0]: 32
1702 11:55:55.265610 [Byte1]: 32
1703 11:55:55.266176
1704 11:55:55.269349 Set Vref, RX VrefLevel [Byte0]: 33
1705 11:55:55.272827 [Byte1]: 33
1706 11:55:55.273254
1707 11:55:55.275997 Set Vref, RX VrefLevel [Byte0]: 34
1708 11:55:55.279046 [Byte1]: 34
1709 11:55:55.282667
1710 11:55:55.283126 Set Vref, RX VrefLevel [Byte0]: 35
1711 11:55:55.286013 [Byte1]: 35
1712 11:55:55.290406
1713 11:55:55.290822 Set Vref, RX VrefLevel [Byte0]: 36
1714 11:55:55.294159 [Byte1]: 36
1715 11:55:55.298125
1716 11:55:55.298536 Set Vref, RX VrefLevel [Byte0]: 37
1717 11:55:55.301589 [Byte1]: 37
1718 11:55:55.305438
1719 11:55:55.305847 Set Vref, RX VrefLevel [Byte0]: 38
1720 11:55:55.308483 [Byte1]: 38
1721 11:55:55.313422
1722 11:55:55.313856 Set Vref, RX VrefLevel [Byte0]: 39
1723 11:55:55.316482 [Byte1]: 39
1724 11:55:55.320998
1725 11:55:55.321436 Set Vref, RX VrefLevel [Byte0]: 40
1726 11:55:55.324154 [Byte1]: 40
1727 11:55:55.328291
1728 11:55:55.328705 Set Vref, RX VrefLevel [Byte0]: 41
1729 11:55:55.331422 [Byte1]: 41
1730 11:55:55.335810
1731 11:55:55.336282 Set Vref, RX VrefLevel [Byte0]: 42
1732 11:55:55.338971 [Byte1]: 42
1733 11:55:55.343604
1734 11:55:55.344017 Set Vref, RX VrefLevel [Byte0]: 43
1735 11:55:55.346685 [Byte1]: 43
1736 11:55:55.351173
1737 11:55:55.351603 Set Vref, RX VrefLevel [Byte0]: 44
1738 11:55:55.354375 [Byte1]: 44
1739 11:55:55.358969
1740 11:55:55.359382 Set Vref, RX VrefLevel [Byte0]: 45
1741 11:55:55.362106 [Byte1]: 45
1742 11:55:55.366211
1743 11:55:55.366846 Set Vref, RX VrefLevel [Byte0]: 46
1744 11:55:55.369514 [Byte1]: 46
1745 11:55:55.373655
1746 11:55:55.374182 Set Vref, RX VrefLevel [Byte0]: 47
1747 11:55:55.377222 [Byte1]: 47
1748 11:55:55.381776
1749 11:55:55.382374 Set Vref, RX VrefLevel [Byte0]: 48
1750 11:55:55.385111 [Byte1]: 48
1751 11:55:55.389162
1752 11:55:55.389792 Set Vref, RX VrefLevel [Byte0]: 49
1753 11:55:55.392592 [Byte1]: 49
1754 11:55:55.396638
1755 11:55:55.397278 Set Vref, RX VrefLevel [Byte0]: 50
1756 11:55:55.400191 [Byte1]: 50
1757 11:55:55.404226
1758 11:55:55.404688 Set Vref, RX VrefLevel [Byte0]: 51
1759 11:55:55.407710 [Byte1]: 51
1760 11:55:55.411954
1761 11:55:55.412387 Set Vref, RX VrefLevel [Byte0]: 52
1762 11:55:55.414976 [Byte1]: 52
1763 11:55:55.419642
1764 11:55:55.420219 Set Vref, RX VrefLevel [Byte0]: 53
1765 11:55:55.422642 [Byte1]: 53
1766 11:55:55.427345
1767 11:55:55.427875 Set Vref, RX VrefLevel [Byte0]: 54
1768 11:55:55.430764 [Byte1]: 54
1769 11:55:55.434569
1770 11:55:55.435142 Set Vref, RX VrefLevel [Byte0]: 55
1771 11:55:55.438219 [Byte1]: 55
1772 11:55:55.442180
1773 11:55:55.442587 Set Vref, RX VrefLevel [Byte0]: 56
1774 11:55:55.445383 [Byte1]: 56
1775 11:55:55.449745
1776 11:55:55.450206 Set Vref, RX VrefLevel [Byte0]: 57
1777 11:55:55.452985 [Byte1]: 57
1778 11:55:55.457694
1779 11:55:55.458198 Set Vref, RX VrefLevel [Byte0]: 58
1780 11:55:55.460843 [Byte1]: 58
1781 11:55:55.464873
1782 11:55:55.465499 Set Vref, RX VrefLevel [Byte0]: 59
1783 11:55:55.468532 [Byte1]: 59
1784 11:55:55.472634
1785 11:55:55.473212 Set Vref, RX VrefLevel [Byte0]: 60
1786 11:55:55.476113 [Byte1]: 60
1787 11:55:55.480375
1788 11:55:55.480811 Set Vref, RX VrefLevel [Byte0]: 61
1789 11:55:55.483434 [Byte1]: 61
1790 11:55:55.487733
1791 11:55:55.488146 Set Vref, RX VrefLevel [Byte0]: 62
1792 11:55:55.491291 [Byte1]: 62
1793 11:55:55.495108
1794 11:55:55.495571 Set Vref, RX VrefLevel [Byte0]: 63
1795 11:55:55.498546 [Byte1]: 63
1796 11:55:55.502823
1797 11:55:55.503447 Set Vref, RX VrefLevel [Byte0]: 64
1798 11:55:55.506262 [Byte1]: 64
1799 11:55:55.510567
1800 11:55:55.511207 Set Vref, RX VrefLevel [Byte0]: 65
1801 11:55:55.513796 [Byte1]: 65
1802 11:55:55.518700
1803 11:55:55.519202 Set Vref, RX VrefLevel [Byte0]: 66
1804 11:55:55.521375 [Byte1]: 66
1805 11:55:55.525934
1806 11:55:55.526362 Set Vref, RX VrefLevel [Byte0]: 67
1807 11:55:55.529323 [Byte1]: 67
1808 11:55:55.533583
1809 11:55:55.534041 Set Vref, RX VrefLevel [Byte0]: 68
1810 11:55:55.536868 [Byte1]: 68
1811 11:55:55.540883
1812 11:55:55.541462 Set Vref, RX VrefLevel [Byte0]: 69
1813 11:55:55.544158 [Byte1]: 69
1814 11:55:55.548420
1815 11:55:55.549004 Set Vref, RX VrefLevel [Byte0]: 70
1816 11:55:55.551923 [Byte1]: 70
1817 11:55:55.556401
1818 11:55:55.557007 Set Vref, RX VrefLevel [Byte0]: 71
1819 11:55:55.559338 [Byte1]: 71
1820 11:55:55.563781
1821 11:55:55.564419 Set Vref, RX VrefLevel [Byte0]: 72
1822 11:55:55.567202 [Byte1]: 72
1823 11:55:55.571117
1824 11:55:55.571688 Set Vref, RX VrefLevel [Byte0]: 73
1825 11:55:55.574773 [Byte1]: 73
1826 11:55:55.579163
1827 11:55:55.579652 Set Vref, RX VrefLevel [Byte0]: 74
1828 11:55:55.582472 [Byte1]: 74
1829 11:55:55.586768
1830 11:55:55.587222 Set Vref, RX VrefLevel [Byte0]: 75
1831 11:55:55.590068 [Byte1]: 75
1832 11:55:55.594241
1833 11:55:55.594649 Set Vref, RX VrefLevel [Byte0]: 76
1834 11:55:55.597964 [Byte1]: 76
1835 11:55:55.601787
1836 11:55:55.602192 Set Vref, RX VrefLevel [Byte0]: 77
1837 11:55:55.605051 [Byte1]: 77
1838 11:55:55.609548
1839 11:55:55.610112 Set Vref, RX VrefLevel [Byte0]: 78
1840 11:55:55.612951 [Byte1]: 78
1841 11:55:55.616730
1842 11:55:55.617335 Final RX Vref Byte 0 = 63 to rank0
1843 11:55:55.620154 Final RX Vref Byte 1 = 58 to rank0
1844 11:55:55.623979 Final RX Vref Byte 0 = 63 to rank1
1845 11:55:55.627250 Final RX Vref Byte 1 = 58 to rank1==
1846 11:55:55.630474 Dram Type= 6, Freq= 0, CH_1, rank 0
1847 11:55:55.633805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1848 11:55:55.636982 ==
1849 11:55:55.637546 DQS Delay:
1850 11:55:55.638060 DQS0 = 0, DQS1 = 0
1851 11:55:55.640808 DQM Delay:
1852 11:55:55.641387 DQM0 = 82, DQM1 = 74
1853 11:55:55.643972 DQ Delay:
1854 11:55:55.644573 DQ0 =84, DQ1 =76, DQ2 =72, DQ3 =84
1855 11:55:55.646924 DQ4 =80, DQ5 =92, DQ6 =96, DQ7 =76
1856 11:55:55.650350 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =72
1857 11:55:55.653892 DQ12 =84, DQ13 =80, DQ14 =80, DQ15 =80
1858 11:55:55.654361
1859 11:55:55.657255
1860 11:55:55.664155 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1861 11:55:55.667244 CH1 RK0: MR19=606, MR18=2C01
1862 11:55:55.674180 CH1_RK0: MR19=0x606, MR18=0x2C01, DQSOSC=398, MR23=63, INC=93, DEC=62
1863 11:55:55.674661
1864 11:55:55.677495 ----->DramcWriteLeveling(PI) begin...
1865 11:55:55.678080 ==
1866 11:55:55.680636 Dram Type= 6, Freq= 0, CH_1, rank 1
1867 11:55:55.684346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1868 11:55:55.684763 ==
1869 11:55:55.687387 Write leveling (Byte 0): 26 => 26
1870 11:55:55.690900 Write leveling (Byte 1): 27 => 27
1871 11:55:55.694452 DramcWriteLeveling(PI) end<-----
1872 11:55:55.694919
1873 11:55:55.695306 ==
1874 11:55:55.697612 Dram Type= 6, Freq= 0, CH_1, rank 1
1875 11:55:55.700894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1876 11:55:55.701509 ==
1877 11:55:55.704293 [Gating] SW mode calibration
1878 11:55:55.710831 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1879 11:55:55.717276 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1880 11:55:55.720575 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1881 11:55:55.724371 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:55:55.727603 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:55:55.734189 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:55:55.737832 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:55:55.741205 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:55:55.747886 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:55:55.751012 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:55:55.754230 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:55:55.760945 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:55:55.764318 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:55:55.767697 0 7 12 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1892 11:55:55.774766 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:55:55.777488 0 7 20 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1894 11:55:55.781309 0 7 24 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1895 11:55:55.784925 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:55:55.791260 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1897 11:55:55.795021 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1898 11:55:55.798146 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:55:55.805069 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:55:55.808159 0 8 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 11:55:55.811571 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:55:55.818555 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:55:55.821619 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:55:55.824888 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:55:55.828352 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1906 11:55:55.835144 0 9 8 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
1907 11:55:55.838808 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 11:55:55.841748 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 11:55:55.848502 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1910 11:55:55.852128 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1911 11:55:55.855307 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1912 11:55:55.861851 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
1913 11:55:55.865548 0 10 4 | B1->B0 | 3030 2d2d | 0 0 | (0 1) (0 1)
1914 11:55:55.868662 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
1915 11:55:55.875659 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:55:55.878536 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:55:55.882490 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:55:55.889257 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:55:55.892125 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:55:55.895503 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1921 11:55:55.898932 0 11 4 | B1->B0 | 2f2f 3a3a | 0 0 | (0 0) (0 0)
1922 11:55:55.905683 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1923 11:55:55.909253 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 11:55:55.912761 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 11:55:55.919433 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 11:55:55.922849 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 11:55:55.926149 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1928 11:55:55.932692 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1929 11:55:55.936276 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1930 11:55:55.939458 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:55:55.945784 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:55:55.949207 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:55:55.952899 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 11:55:55.955864 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 11:55:55.962550 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 11:55:55.966105 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:55:55.969408 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:55:55.976007 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:55:55.979739 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:55:55.982814 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:55:55.989474 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:55:55.993083 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:55:55.996300 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:55:56.003277 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:55:56.006483 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1946 11:55:56.009692 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1947 11:55:56.012996 Total UI for P1: 0, mck2ui 16
1948 11:55:56.016264 best dqsien dly found for B0: ( 0, 14, 4)
1949 11:55:56.019996 Total UI for P1: 0, mck2ui 16
1950 11:55:56.023528 best dqsien dly found for B1: ( 0, 14, 4)
1951 11:55:56.026717 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1952 11:55:56.029976 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1953 11:55:56.030401
1954 11:55:56.033446 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1955 11:55:56.036848 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1956 11:55:56.040089 [Gating] SW calibration Done
1957 11:55:56.040499 ==
1958 11:55:56.043845 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 11:55:56.046980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 11:55:56.047394 ==
1961 11:55:56.049939 RX Vref Scan: 0
1962 11:55:56.050351
1963 11:55:56.053458 RX Vref 0 -> 0, step: 1
1964 11:55:56.053867
1965 11:55:56.057042 RX Delay -130 -> 252, step: 16
1966 11:55:56.059960 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1967 11:55:56.064015 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1968 11:55:56.067001 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1969 11:55:56.070333 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1970 11:55:56.073787 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1971 11:55:56.081014 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1972 11:55:56.083913 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1973 11:55:56.087169 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1974 11:55:56.090571 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1975 11:55:56.093673 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1976 11:55:56.100544 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1977 11:55:56.103861 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1978 11:55:56.107153 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1979 11:55:56.110672 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1980 11:55:56.113995 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1981 11:55:56.120585 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1982 11:55:56.121164 ==
1983 11:55:56.123824 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 11:55:56.127881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 11:55:56.128464 ==
1986 11:55:56.128970 DQS Delay:
1987 11:55:56.130618 DQS0 = 0, DQS1 = 0
1988 11:55:56.131140 DQM Delay:
1989 11:55:56.134365 DQM0 = 80, DQM1 = 78
1990 11:55:56.134958 DQ Delay:
1991 11:55:56.137365 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1992 11:55:56.141112 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1993 11:55:56.143923 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1994 11:55:56.147474 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1995 11:55:56.147879
1996 11:55:56.148196
1997 11:55:56.148491 ==
1998 11:55:56.150837 Dram Type= 6, Freq= 0, CH_1, rank 1
1999 11:55:56.154565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2000 11:55:56.155207 ==
2001 11:55:56.155550
2002 11:55:56.155855
2003 11:55:56.157671 TX Vref Scan disable
2004 11:55:56.160889 == TX Byte 0 ==
2005 11:55:56.164420 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2006 11:55:56.167725 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2007 11:55:56.171035 == TX Byte 1 ==
2008 11:55:56.174094 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2009 11:55:56.177946 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2010 11:55:56.178509 ==
2011 11:55:56.180994 Dram Type= 6, Freq= 0, CH_1, rank 1
2012 11:55:56.184583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2013 11:55:56.185205 ==
2014 11:55:56.198703 TX Vref=22, minBit 1, minWin=27, winSum=442
2015 11:55:56.202455 TX Vref=24, minBit 0, minWin=27, winSum=444
2016 11:55:56.205680 TX Vref=26, minBit 8, minWin=27, winSum=444
2017 11:55:56.208908 TX Vref=28, minBit 15, minWin=27, winSum=449
2018 11:55:56.212390 TX Vref=30, minBit 15, minWin=27, winSum=449
2019 11:55:56.218483 TX Vref=32, minBit 8, minWin=27, winSum=448
2020 11:55:56.222536 [TxChooseVref] Worse bit 15, Min win 27, Win sum 449, Final Vref 28
2021 11:55:56.222987
2022 11:55:56.225788 Final TX Range 1 Vref 28
2023 11:55:56.226192
2024 11:55:56.226511 ==
2025 11:55:56.229208 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 11:55:56.232164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 11:55:56.232577 ==
2028 11:55:56.232899
2029 11:55:56.233202
2030 11:55:56.235685 TX Vref Scan disable
2031 11:55:56.239247 == TX Byte 0 ==
2032 11:55:56.242360 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2033 11:55:56.245675 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2034 11:55:56.249322 == TX Byte 1 ==
2035 11:55:56.252262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2036 11:55:56.255497 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2037 11:55:56.256079
2038 11:55:56.259258 [DATLAT]
2039 11:55:56.259907 Freq=800, CH1 RK1
2040 11:55:56.260491
2041 11:55:56.262175 DATLAT Default: 0xa
2042 11:55:56.262747 0, 0xFFFF, sum = 0
2043 11:55:56.265551 1, 0xFFFF, sum = 0
2044 11:55:56.266064 2, 0xFFFF, sum = 0
2045 11:55:56.269232 3, 0xFFFF, sum = 0
2046 11:55:56.269873 4, 0xFFFF, sum = 0
2047 11:55:56.272379 5, 0xFFFF, sum = 0
2048 11:55:56.272609 6, 0xFFFF, sum = 0
2049 11:55:56.275682 7, 0xFFFF, sum = 0
2050 11:55:56.275791 8, 0xFFFF, sum = 0
2051 11:55:56.278998 9, 0x0, sum = 1
2052 11:55:56.279089 10, 0x0, sum = 2
2053 11:55:56.282277 11, 0x0, sum = 3
2054 11:55:56.282385 12, 0x0, sum = 4
2055 11:55:56.285513 best_step = 10
2056 11:55:56.285624
2057 11:55:56.285717 ==
2058 11:55:56.288815 Dram Type= 6, Freq= 0, CH_1, rank 1
2059 11:55:56.292317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2060 11:55:56.292418 ==
2061 11:55:56.292512 RX Vref Scan: 0
2062 11:55:56.295707
2063 11:55:56.295802 RX Vref 0 -> 0, step: 1
2064 11:55:56.295890
2065 11:55:56.298824 RX Delay -95 -> 252, step: 8
2066 11:55:56.302654 iDelay=209, Bit 0, Center 84 (-31 ~ 200) 232
2067 11:55:56.308975 iDelay=209, Bit 1, Center 76 (-39 ~ 192) 232
2068 11:55:56.312744 iDelay=209, Bit 2, Center 68 (-47 ~ 184) 232
2069 11:55:56.315794 iDelay=209, Bit 3, Center 76 (-39 ~ 192) 232
2070 11:55:56.319068 iDelay=209, Bit 4, Center 76 (-39 ~ 192) 232
2071 11:55:56.322813 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
2072 11:55:56.329326 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2073 11:55:56.332836 iDelay=209, Bit 7, Center 76 (-39 ~ 192) 232
2074 11:55:56.336281 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2075 11:55:56.339287 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
2076 11:55:56.343449 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
2077 11:55:56.349939 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2078 11:55:56.353430 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
2079 11:55:56.356545 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2080 11:55:56.359742 iDelay=209, Bit 14, Center 84 (-31 ~ 200) 232
2081 11:55:56.362977 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
2082 11:55:56.363416 ==
2083 11:55:56.366594 Dram Type= 6, Freq= 0, CH_1, rank 1
2084 11:55:56.373207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2085 11:55:56.373859 ==
2086 11:55:56.374453 DQS Delay:
2087 11:55:56.376449 DQS0 = 0, DQS1 = 0
2088 11:55:56.377077 DQM Delay:
2089 11:55:56.377670 DQM0 = 79, DQM1 = 75
2090 11:55:56.379960 DQ Delay:
2091 11:55:56.383444 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2092 11:55:56.386768 DQ4 =76, DQ5 =88, DQ6 =92, DQ7 =76
2093 11:55:56.389870 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2094 11:55:56.393874 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2095 11:55:56.394554
2096 11:55:56.395222
2097 11:55:56.400073 [DQSOSCAuto] RK1, (LSB)MR18= 0x202b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2098 11:55:56.403597 CH1 RK1: MR19=606, MR18=202B
2099 11:55:56.410256 CH1_RK1: MR19=0x606, MR18=0x202B, DQSOSC=398, MR23=63, INC=93, DEC=62
2100 11:55:56.413643 [RxdqsGatingPostProcess] freq 800
2101 11:55:56.417167 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2102 11:55:56.420371 Pre-setting of DQS Precalculation
2103 11:55:56.426627 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2104 11:55:56.433580 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2105 11:55:56.440403 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2106 11:55:56.440819
2107 11:55:56.441180
2108 11:55:56.443676 [Calibration Summary] 1600 Mbps
2109 11:55:56.444019 CH 0, Rank 0
2110 11:55:56.446903 SW Impedance : PASS
2111 11:55:56.447255 DUTY Scan : NO K
2112 11:55:56.450820 ZQ Calibration : PASS
2113 11:55:56.453956 Jitter Meter : NO K
2114 11:55:56.454495 CBT Training : PASS
2115 11:55:56.457330 Write leveling : PASS
2116 11:55:56.460824 RX DQS gating : PASS
2117 11:55:56.461345 RX DQ/DQS(RDDQC) : PASS
2118 11:55:56.463833 TX DQ/DQS : PASS
2119 11:55:56.467485 RX DATLAT : PASS
2120 11:55:56.468068 RX DQ/DQS(Engine): PASS
2121 11:55:56.470426 TX OE : NO K
2122 11:55:56.471083 All Pass.
2123 11:55:56.471675
2124 11:55:56.474037 CH 0, Rank 1
2125 11:55:56.474634 SW Impedance : PASS
2126 11:55:56.477455 DUTY Scan : NO K
2127 11:55:56.478067 ZQ Calibration : PASS
2128 11:55:56.481072 Jitter Meter : NO K
2129 11:55:56.484495 CBT Training : PASS
2130 11:55:56.484939 Write leveling : PASS
2131 11:55:56.487486 RX DQS gating : PASS
2132 11:55:56.490821 RX DQ/DQS(RDDQC) : PASS
2133 11:55:56.491269 TX DQ/DQS : PASS
2134 11:55:56.494788 RX DATLAT : PASS
2135 11:55:56.497345 RX DQ/DQS(Engine): PASS
2136 11:55:56.497747 TX OE : NO K
2137 11:55:56.501312 All Pass.
2138 11:55:56.501714
2139 11:55:56.502033 CH 1, Rank 0
2140 11:55:56.504465 SW Impedance : PASS
2141 11:55:56.504870 DUTY Scan : NO K
2142 11:55:56.507635 ZQ Calibration : PASS
2143 11:55:56.511179 Jitter Meter : NO K
2144 11:55:56.511736 CBT Training : PASS
2145 11:55:56.514255 Write leveling : PASS
2146 11:55:56.514828 RX DQS gating : PASS
2147 11:55:56.517659 RX DQ/DQS(RDDQC) : PASS
2148 11:55:56.521045 TX DQ/DQS : PASS
2149 11:55:56.521563 RX DATLAT : PASS
2150 11:55:56.524507 RX DQ/DQS(Engine): PASS
2151 11:55:56.527861 TX OE : NO K
2152 11:55:56.528314 All Pass.
2153 11:55:56.528805
2154 11:55:56.529253 CH 1, Rank 1
2155 11:55:56.531093 SW Impedance : PASS
2156 11:55:56.534272 DUTY Scan : NO K
2157 11:55:56.534682 ZQ Calibration : PASS
2158 11:55:56.537674 Jitter Meter : NO K
2159 11:55:56.541331 CBT Training : PASS
2160 11:55:56.541904 Write leveling : PASS
2161 11:55:56.544370 RX DQS gating : PASS
2162 11:55:56.545001 RX DQ/DQS(RDDQC) : PASS
2163 11:55:56.547836 TX DQ/DQS : PASS
2164 11:55:56.551033 RX DATLAT : PASS
2165 11:55:56.551483 RX DQ/DQS(Engine): PASS
2166 11:55:56.554261 TX OE : NO K
2167 11:55:56.554792 All Pass.
2168 11:55:56.555341
2169 11:55:56.557843 DramC Write-DBI off
2170 11:55:56.561173 PER_BANK_REFRESH: Hybrid Mode
2171 11:55:56.561745 TX_TRACKING: ON
2172 11:55:56.564723 [GetDramInforAfterCalByMRR] Vendor 6.
2173 11:55:56.568235 [GetDramInforAfterCalByMRR] Revision 606.
2174 11:55:56.571397 [GetDramInforAfterCalByMRR] Revision 2 0.
2175 11:55:56.574669 MR0 0x3b3b
2176 11:55:56.575157 MR8 0x5151
2177 11:55:56.578125 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 11:55:56.578678
2179 11:55:56.579135 MR0 0x3b3b
2180 11:55:56.581354 MR8 0x5151
2181 11:55:56.584707 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2182 11:55:56.585288
2183 11:55:56.594805 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2184 11:55:56.598478 [FAST_K] Save calibration result to emmc
2185 11:55:56.601662 [FAST_K] Save calibration result to emmc
2186 11:55:56.602086 dram_init: config_dvfs: 1
2187 11:55:56.607822 dramc_set_vcore_voltage set vcore to 662500
2188 11:55:56.607920 Read voltage for 1200, 2
2189 11:55:56.611247 Vio18 = 0
2190 11:55:56.611320 Vcore = 662500
2191 11:55:56.611383 Vdram = 0
2192 11:55:56.611440 Vddq = 0
2193 11:55:56.614536 Vmddr = 0
2194 11:55:56.617709 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2195 11:55:56.624645 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2196 11:55:56.624745 MEM_TYPE=3, freq_sel=15
2197 11:55:56.627797 sv_algorithm_assistance_LP4_1600
2198 11:55:56.634696 ============ PULL DRAM RESETB DOWN ============
2199 11:55:56.638254 ========== PULL DRAM RESETB DOWN end =========
2200 11:55:56.641829 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2201 11:55:56.644741 ===================================
2202 11:55:56.648811 LPDDR4 DRAM CONFIGURATION
2203 11:55:56.651896 ===================================
2204 11:55:56.651971 EX_ROW_EN[0] = 0x0
2205 11:55:56.655233 EX_ROW_EN[1] = 0x0
2206 11:55:56.658785 LP4Y_EN = 0x0
2207 11:55:56.658910 WORK_FSP = 0x0
2208 11:55:56.661914 WL = 0x4
2209 11:55:56.661985 RL = 0x4
2210 11:55:56.664871 BL = 0x2
2211 11:55:56.664967 RPST = 0x0
2212 11:55:56.668661 RD_PRE = 0x0
2213 11:55:56.668759 WR_PRE = 0x1
2214 11:55:56.671965 WR_PST = 0x0
2215 11:55:56.672044 DBI_WR = 0x0
2216 11:55:56.675457 DBI_RD = 0x0
2217 11:55:56.675537 OTF = 0x1
2218 11:55:56.678631 ===================================
2219 11:55:56.682124 ===================================
2220 11:55:56.685141 ANA top config
2221 11:55:56.685253 ===================================
2222 11:55:56.688718 DLL_ASYNC_EN = 0
2223 11:55:56.691897 ALL_SLAVE_EN = 0
2224 11:55:56.695289 NEW_RANK_MODE = 1
2225 11:55:56.699307 DLL_IDLE_MODE = 1
2226 11:55:56.699397 LP45_APHY_COMB_EN = 1
2227 11:55:56.701985 TX_ODT_DIS = 1
2228 11:55:56.706022 NEW_8X_MODE = 1
2229 11:55:56.709215 ===================================
2230 11:55:56.712065 ===================================
2231 11:55:56.715567 data_rate = 2400
2232 11:55:56.718794 CKR = 1
2233 11:55:56.718915 DQ_P2S_RATIO = 8
2234 11:55:56.722015 ===================================
2235 11:55:56.725405 CA_P2S_RATIO = 8
2236 11:55:56.729312 DQ_CA_OPEN = 0
2237 11:55:56.732405 DQ_SEMI_OPEN = 0
2238 11:55:56.735787 CA_SEMI_OPEN = 0
2239 11:55:56.735884 CA_FULL_RATE = 0
2240 11:55:56.739056 DQ_CKDIV4_EN = 0
2241 11:55:56.742266 CA_CKDIV4_EN = 0
2242 11:55:56.745706 CA_PREDIV_EN = 0
2243 11:55:56.749061 PH8_DLY = 17
2244 11:55:56.752617 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2245 11:55:56.752688 DQ_AAMCK_DIV = 4
2246 11:55:56.755823 CA_AAMCK_DIV = 4
2247 11:55:56.758869 CA_ADMCK_DIV = 4
2248 11:55:56.762314 DQ_TRACK_CA_EN = 0
2249 11:55:56.765661 CA_PICK = 1200
2250 11:55:56.769210 CA_MCKIO = 1200
2251 11:55:56.772671 MCKIO_SEMI = 0
2252 11:55:56.772779 PLL_FREQ = 2366
2253 11:55:56.775929 DQ_UI_PI_RATIO = 32
2254 11:55:56.779606 CA_UI_PI_RATIO = 0
2255 11:55:56.782354 ===================================
2256 11:55:56.785889 ===================================
2257 11:55:56.789164 memory_type:LPDDR4
2258 11:55:56.789273 GP_NUM : 10
2259 11:55:56.792493 SRAM_EN : 1
2260 11:55:56.796000 MD32_EN : 0
2261 11:55:56.799727 ===================================
2262 11:55:56.799828 [ANA_INIT] >>>>>>>>>>>>>>
2263 11:55:56.802268 <<<<<< [CONFIGURE PHASE]: ANA_TX
2264 11:55:56.805912 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2265 11:55:56.809207 ===================================
2266 11:55:56.812663 data_rate = 2400,PCW = 0X5b00
2267 11:55:56.816417 ===================================
2268 11:55:56.819938 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2269 11:55:56.826524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2270 11:55:56.829564 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2271 11:55:56.836330 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2272 11:55:56.839465 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2273 11:55:56.842739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2274 11:55:56.842910 [ANA_INIT] flow start
2275 11:55:56.846346 [ANA_INIT] PLL >>>>>>>>
2276 11:55:56.849484 [ANA_INIT] PLL <<<<<<<<
2277 11:55:56.849660 [ANA_INIT] MIDPI >>>>>>>>
2278 11:55:56.853063 [ANA_INIT] MIDPI <<<<<<<<
2279 11:55:56.856403 [ANA_INIT] DLL >>>>>>>>
2280 11:55:56.856500 [ANA_INIT] DLL <<<<<<<<
2281 11:55:56.860188 [ANA_INIT] flow end
2282 11:55:56.863059 ============ LP4 DIFF to SE enter ============
2283 11:55:56.866462 ============ LP4 DIFF to SE exit ============
2284 11:55:56.869887 [ANA_INIT] <<<<<<<<<<<<<
2285 11:55:56.873172 [Flow] Enable top DCM control >>>>>
2286 11:55:56.876807 [Flow] Enable top DCM control <<<<<
2287 11:55:56.879784 Enable DLL master slave shuffle
2288 11:55:56.886579 ==============================================================
2289 11:55:56.886685 Gating Mode config
2290 11:55:56.893301 ==============================================================
2291 11:55:56.893404 Config description:
2292 11:55:56.903454 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2293 11:55:56.910047 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2294 11:55:56.916936 SELPH_MODE 0: By rank 1: By Phase
2295 11:55:56.920342 ==============================================================
2296 11:55:56.923670 GAT_TRACK_EN = 1
2297 11:55:56.926813 RX_GATING_MODE = 2
2298 11:55:56.930313 RX_GATING_TRACK_MODE = 2
2299 11:55:56.933578 SELPH_MODE = 1
2300 11:55:56.936907 PICG_EARLY_EN = 1
2301 11:55:56.940275 VALID_LAT_VALUE = 1
2302 11:55:56.943700 ==============================================================
2303 11:55:56.947270 Enter into Gating configuration >>>>
2304 11:55:56.950545 Exit from Gating configuration <<<<
2305 11:55:56.953654 Enter into DVFS_PRE_config >>>>>
2306 11:55:56.963890 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2307 11:55:56.967117 Exit from DVFS_PRE_config <<<<<
2308 11:55:56.970434 Enter into PICG configuration >>>>
2309 11:55:56.974273 Exit from PICG configuration <<<<
2310 11:55:56.977471 [RX_INPUT] configuration >>>>>
2311 11:55:56.980517 [RX_INPUT] configuration <<<<<
2312 11:55:56.984445 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2313 11:55:56.990561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2314 11:55:56.997814 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 11:55:57.004283 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 11:55:57.011262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2317 11:55:57.014493 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2318 11:55:57.020992 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2319 11:55:57.024525 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2320 11:55:57.027656 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2321 11:55:57.030983 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2322 11:55:57.034750 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2323 11:55:57.041169 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2324 11:55:57.044654 ===================================
2325 11:55:57.047996 LPDDR4 DRAM CONFIGURATION
2326 11:55:57.051357 ===================================
2327 11:55:57.051522 EX_ROW_EN[0] = 0x0
2328 11:55:57.054716 EX_ROW_EN[1] = 0x0
2329 11:55:57.054879 LP4Y_EN = 0x0
2330 11:55:57.058267 WORK_FSP = 0x0
2331 11:55:57.058436 WL = 0x4
2332 11:55:57.061864 RL = 0x4
2333 11:55:57.062077 BL = 0x2
2334 11:55:57.064753 RPST = 0x0
2335 11:55:57.064949 RD_PRE = 0x0
2336 11:55:57.068034 WR_PRE = 0x1
2337 11:55:57.068274 WR_PST = 0x0
2338 11:55:57.071612 DBI_WR = 0x0
2339 11:55:57.071936 DBI_RD = 0x0
2340 11:55:57.074926 OTF = 0x1
2341 11:55:57.078898 ===================================
2342 11:55:57.082534 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2343 11:55:57.085223 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2344 11:55:57.091870 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2345 11:55:57.095353 ===================================
2346 11:55:57.095787 LPDDR4 DRAM CONFIGURATION
2347 11:55:57.098737 ===================================
2348 11:55:57.102102 EX_ROW_EN[0] = 0x10
2349 11:55:57.102521 EX_ROW_EN[1] = 0x0
2350 11:55:57.105857 LP4Y_EN = 0x0
2351 11:55:57.106293 WORK_FSP = 0x0
2352 11:55:57.108962 WL = 0x4
2353 11:55:57.109542 RL = 0x4
2354 11:55:57.112026 BL = 0x2
2355 11:55:57.112565 RPST = 0x0
2356 11:55:57.115388 RD_PRE = 0x0
2357 11:55:57.119068 WR_PRE = 0x1
2358 11:55:57.119576 WR_PST = 0x0
2359 11:55:57.122051 DBI_WR = 0x0
2360 11:55:57.122590 DBI_RD = 0x0
2361 11:55:57.125440 OTF = 0x1
2362 11:55:57.129174 ===================================
2363 11:55:57.132189 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2364 11:55:57.132758 ==
2365 11:55:57.135425 Dram Type= 6, Freq= 0, CH_0, rank 0
2366 11:55:57.142295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 11:55:57.142897 ==
2368 11:55:57.143267 [Duty_Offset_Calibration]
2369 11:55:57.145831 B0:3 B1:-1 CA:1
2370 11:55:57.146208
2371 11:55:57.149190 [DutyScan_Calibration_Flow] k_type=0
2372 11:55:57.157468
2373 11:55:57.157877 ==CLK 0==
2374 11:55:57.160670 Final CLK duty delay cell = -4
2375 11:55:57.164023 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2376 11:55:57.167264 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2377 11:55:57.170723 [-4] AVG Duty = 4953%(X100)
2378 11:55:57.170828
2379 11:55:57.173905 CH0 CLK Duty spec in!! Max-Min= 156%
2380 11:55:57.177373 [DutyScan_Calibration_Flow] ====Done====
2381 11:55:57.177481
2382 11:55:57.180568 [DutyScan_Calibration_Flow] k_type=1
2383 11:55:57.195988
2384 11:55:57.196094 ==DQS 0 ==
2385 11:55:57.198997 Final DQS duty delay cell = 0
2386 11:55:57.202602 [0] MAX Duty = 5125%(X100), DQS PI = 44
2387 11:55:57.205762 [0] MIN Duty = 5000%(X100), DQS PI = 12
2388 11:55:57.205863 [0] AVG Duty = 5062%(X100)
2389 11:55:57.209403
2390 11:55:57.209506 ==DQS 1 ==
2391 11:55:57.212556 Final DQS duty delay cell = -4
2392 11:55:57.216095 [-4] MAX Duty = 5093%(X100), DQS PI = 6
2393 11:55:57.219210 [-4] MIN Duty = 5000%(X100), DQS PI = 42
2394 11:55:57.222466 [-4] AVG Duty = 5046%(X100)
2395 11:55:57.222563
2396 11:55:57.226011 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2397 11:55:57.226106
2398 11:55:57.229744 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2399 11:55:57.232625 [DutyScan_Calibration_Flow] ====Done====
2400 11:55:57.232705
2401 11:55:57.236073 [DutyScan_Calibration_Flow] k_type=3
2402 11:55:57.252770
2403 11:55:57.252849 ==DQM 0 ==
2404 11:55:57.255931 Final DQM duty delay cell = 0
2405 11:55:57.259623 [0] MAX Duty = 5000%(X100), DQS PI = 48
2406 11:55:57.262538 [0] MIN Duty = 4875%(X100), DQS PI = 4
2407 11:55:57.262616 [0] AVG Duty = 4937%(X100)
2408 11:55:57.265924
2409 11:55:57.266002 ==DQM 1 ==
2410 11:55:57.269369 Final DQM duty delay cell = 0
2411 11:55:57.273059 [0] MAX Duty = 5156%(X100), DQS PI = 62
2412 11:55:57.275927 [0] MIN Duty = 4969%(X100), DQS PI = 10
2413 11:55:57.276006 [0] AVG Duty = 5062%(X100)
2414 11:55:57.279365
2415 11:55:57.283034 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2416 11:55:57.283114
2417 11:55:57.286399 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2418 11:55:57.290118 [DutyScan_Calibration_Flow] ====Done====
2419 11:55:57.290197
2420 11:55:57.292923 [DutyScan_Calibration_Flow] k_type=2
2421 11:55:57.308636
2422 11:55:57.308715 ==DQ 0 ==
2423 11:55:57.311774 Final DQ duty delay cell = -4
2424 11:55:57.315423 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2425 11:55:57.318631 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2426 11:55:57.322009 [-4] AVG Duty = 4968%(X100)
2427 11:55:57.322114
2428 11:55:57.322204 ==DQ 1 ==
2429 11:55:57.325241 Final DQ duty delay cell = 0
2430 11:55:57.328387 [0] MAX Duty = 5031%(X100), DQS PI = 18
2431 11:55:57.331554 [0] MIN Duty = 4907%(X100), DQS PI = 46
2432 11:55:57.335290 [0] AVG Duty = 4969%(X100)
2433 11:55:57.335363
2434 11:55:57.338753 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2435 11:55:57.338870
2436 11:55:57.341717 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2437 11:55:57.344951 [DutyScan_Calibration_Flow] ====Done====
2438 11:55:57.345051 ==
2439 11:55:57.348202 Dram Type= 6, Freq= 0, CH_1, rank 0
2440 11:55:57.352216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2441 11:55:57.352315 ==
2442 11:55:57.355031 [Duty_Offset_Calibration]
2443 11:55:57.355101 B0:1 B1:1 CA:2
2444 11:55:57.355161
2445 11:55:57.358605 [DutyScan_Calibration_Flow] k_type=0
2446 11:55:57.368944
2447 11:55:57.369048 ==CLK 0==
2448 11:55:57.372291 Final CLK duty delay cell = 0
2449 11:55:57.375400 [0] MAX Duty = 5156%(X100), DQS PI = 24
2450 11:55:57.378562 [0] MIN Duty = 4938%(X100), DQS PI = 40
2451 11:55:57.378670 [0] AVG Duty = 5047%(X100)
2452 11:55:57.381978
2453 11:55:57.382092 CH1 CLK Duty spec in!! Max-Min= 218%
2454 11:55:57.389028 [DutyScan_Calibration_Flow] ====Done====
2455 11:55:57.389135
2456 11:55:57.391741 [DutyScan_Calibration_Flow] k_type=1
2457 11:55:57.408231
2458 11:55:57.408335 ==DQS 0 ==
2459 11:55:57.411192 Final DQS duty delay cell = 0
2460 11:55:57.414717 [0] MAX Duty = 5031%(X100), DQS PI = 18
2461 11:55:57.418085 [0] MIN Duty = 4844%(X100), DQS PI = 50
2462 11:55:57.418160 [0] AVG Duty = 4937%(X100)
2463 11:55:57.421141
2464 11:55:57.421238 ==DQS 1 ==
2465 11:55:57.424754 Final DQS duty delay cell = 0
2466 11:55:57.428029 [0] MAX Duty = 5062%(X100), DQS PI = 36
2467 11:55:57.431265 [0] MIN Duty = 4907%(X100), DQS PI = 8
2468 11:55:57.431366 [0] AVG Duty = 4984%(X100)
2469 11:55:57.431429
2470 11:55:57.438260 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2471 11:55:57.438367
2472 11:55:57.441341 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2473 11:55:57.445190 [DutyScan_Calibration_Flow] ====Done====
2474 11:55:57.445299
2475 11:55:57.448277 [DutyScan_Calibration_Flow] k_type=3
2476 11:55:57.464424
2477 11:55:57.464545 ==DQM 0 ==
2478 11:55:57.467757 Final DQM duty delay cell = 0
2479 11:55:57.470924 [0] MAX Duty = 5093%(X100), DQS PI = 18
2480 11:55:57.474235 [0] MIN Duty = 4875%(X100), DQS PI = 48
2481 11:55:57.474355 [0] AVG Duty = 4984%(X100)
2482 11:55:57.477606
2483 11:55:57.477708 ==DQM 1 ==
2484 11:55:57.480696 Final DQM duty delay cell = 0
2485 11:55:57.484588 [0] MAX Duty = 5156%(X100), DQS PI = 62
2486 11:55:57.487509 [0] MIN Duty = 4938%(X100), DQS PI = 22
2487 11:55:57.490889 [0] AVG Duty = 5047%(X100)
2488 11:55:57.490966
2489 11:55:57.494533 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2490 11:55:57.494638
2491 11:55:57.497935 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2492 11:55:57.500897 [DutyScan_Calibration_Flow] ====Done====
2493 11:55:57.501006
2494 11:55:57.504493 [DutyScan_Calibration_Flow] k_type=2
2495 11:55:57.521288
2496 11:55:57.521397 ==DQ 0 ==
2497 11:55:57.524118 Final DQ duty delay cell = 0
2498 11:55:57.527397 [0] MAX Duty = 5156%(X100), DQS PI = 18
2499 11:55:57.531263 [0] MIN Duty = 4938%(X100), DQS PI = 50
2500 11:55:57.531340 [0] AVG Duty = 5047%(X100)
2501 11:55:57.531432
2502 11:55:57.534539 ==DQ 1 ==
2503 11:55:57.537610 Final DQ duty delay cell = 0
2504 11:55:57.541654 [0] MAX Duty = 5093%(X100), DQS PI = 10
2505 11:55:57.544353 [0] MIN Duty = 5000%(X100), DQS PI = 2
2506 11:55:57.544427 [0] AVG Duty = 5046%(X100)
2507 11:55:57.544492
2508 11:55:57.547589 CH1 DQ 0 Duty spec in!! Max-Min= 218%
2509 11:55:57.547661
2510 11:55:57.551159 CH1 DQ 1 Duty spec in!! Max-Min= 93%
2511 11:55:57.554614 [DutyScan_Calibration_Flow] ====Done====
2512 11:55:57.559991 nWR fixed to 30
2513 11:55:57.563640 [ModeRegInit_LP4] CH0 RK0
2514 11:55:57.563734 [ModeRegInit_LP4] CH0 RK1
2515 11:55:57.566802 [ModeRegInit_LP4] CH1 RK0
2516 11:55:57.570233 [ModeRegInit_LP4] CH1 RK1
2517 11:55:57.570307 match AC timing 7
2518 11:55:57.577084 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2519 11:55:57.580015 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2520 11:55:57.583428 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2521 11:55:57.590266 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2522 11:55:57.593742 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2523 11:55:57.593849 ==
2524 11:55:57.596695 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 11:55:57.600180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 11:55:57.600286 ==
2527 11:55:57.607040 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2528 11:55:57.613797 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2529 11:55:57.620728 [CA 0] Center 40 (10~71) winsize 62
2530 11:55:57.624034 [CA 1] Center 39 (9~70) winsize 62
2531 11:55:57.627863 [CA 2] Center 36 (6~67) winsize 62
2532 11:55:57.631227 [CA 3] Center 36 (5~67) winsize 63
2533 11:55:57.634473 [CA 4] Center 34 (4~65) winsize 62
2534 11:55:57.637576 [CA 5] Center 34 (4~65) winsize 62
2535 11:55:57.637687
2536 11:55:57.641233 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2537 11:55:57.641349
2538 11:55:57.644642 [CATrainingPosCal] consider 1 rank data
2539 11:55:57.647895 u2DelayCellTimex100 = 270/100 ps
2540 11:55:57.651232 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2541 11:55:57.654569 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2542 11:55:57.657741 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2543 11:55:57.664729 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2544 11:55:57.668172 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2545 11:55:57.671488 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
2546 11:55:57.671562
2547 11:55:57.674592 CA PerBit enable=1, Macro0, CA PI delay=34
2548 11:55:57.674690
2549 11:55:57.678271 [CBTSetCACLKResult] CA Dly = 34
2550 11:55:57.678375 CS Dly: 7 (0~38)
2551 11:55:57.678465 ==
2552 11:55:57.681362 Dram Type= 6, Freq= 0, CH_0, rank 1
2553 11:55:57.688118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2554 11:55:57.688198 ==
2555 11:55:57.691711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2556 11:55:57.698343 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2557 11:55:57.706819 [CA 0] Center 39 (9~70) winsize 62
2558 11:55:57.710533 [CA 1] Center 40 (10~70) winsize 61
2559 11:55:57.713789 [CA 2] Center 36 (6~67) winsize 62
2560 11:55:57.716937 [CA 3] Center 36 (5~67) winsize 63
2561 11:55:57.720325 [CA 4] Center 34 (4~65) winsize 62
2562 11:55:57.723647 [CA 5] Center 34 (4~64) winsize 61
2563 11:55:57.723773
2564 11:55:57.727461 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2565 11:55:57.727573
2566 11:55:57.730478 [CATrainingPosCal] consider 2 rank data
2567 11:55:57.733824 u2DelayCellTimex100 = 270/100 ps
2568 11:55:57.737184 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2569 11:55:57.740804 CA1 delay=40 (10~70),Diff = 6 PI (28 cell)
2570 11:55:57.744066 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2571 11:55:57.750832 CA3 delay=36 (5~67),Diff = 2 PI (9 cell)
2572 11:55:57.753926 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2573 11:55:57.757839 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2574 11:55:57.758092
2575 11:55:57.760929 CA PerBit enable=1, Macro0, CA PI delay=34
2576 11:55:57.761306
2577 11:55:57.764053 [CBTSetCACLKResult] CA Dly = 34
2578 11:55:57.764424 CS Dly: 8 (0~41)
2579 11:55:57.764768
2580 11:55:57.767482 ----->DramcWriteLeveling(PI) begin...
2581 11:55:57.767992 ==
2582 11:55:57.771274 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 11:55:57.778020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 11:55:57.778592 ==
2585 11:55:57.780947 Write leveling (Byte 0): 31 => 31
2586 11:55:57.784824 Write leveling (Byte 1): 29 => 29
2587 11:55:57.785427 DramcWriteLeveling(PI) end<-----
2588 11:55:57.785973
2589 11:55:57.788046 ==
2590 11:55:57.788648 Dram Type= 6, Freq= 0, CH_0, rank 0
2591 11:55:57.794532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2592 11:55:57.795152 ==
2593 11:55:57.798239 [Gating] SW mode calibration
2594 11:55:57.804981 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2595 11:55:57.808183 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2596 11:55:57.815404 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:55:57.818342 0 15 4 | B1->B0 | 2424 3131 | 1 1 | (0 0) (1 1)
2598 11:55:57.821802 0 15 8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2599 11:55:57.825191 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 11:55:57.831683 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2601 11:55:57.834839 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2602 11:55:57.838386 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2603 11:55:57.844859 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2604 11:55:57.848844 1 0 0 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 0)
2605 11:55:57.851475 1 0 4 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
2606 11:55:57.858250 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 11:55:57.861801 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 11:55:57.865187 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2609 11:55:57.871847 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2610 11:55:57.875058 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2611 11:55:57.878340 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2612 11:55:57.885431 1 1 0 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
2613 11:55:57.888329 1 1 4 | B1->B0 | 3a3a 4343 | 0 0 | (1 1) (1 1)
2614 11:55:57.892016 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 11:55:57.895509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 11:55:57.901823 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2617 11:55:57.905197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2618 11:55:57.908903 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2619 11:55:57.915476 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2620 11:55:57.919158 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2621 11:55:57.922082 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:55:57.928970 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2623 11:55:57.932385 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 11:55:57.935950 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 11:55:57.942019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 11:55:57.945969 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 11:55:57.948882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 11:55:57.952752 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:55:57.959136 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:55:57.962194 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:55:57.965661 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:55:57.971963 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:55:57.975217 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:55:57.978644 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:55:57.985575 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2636 11:55:57.988687 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2637 11:55:57.992023 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2638 11:55:57.995488 Total UI for P1: 0, mck2ui 16
2639 11:55:57.998748 best dqsien dly found for B0: ( 1, 3, 30)
2640 11:55:58.002355 Total UI for P1: 0, mck2ui 16
2641 11:55:58.005749 best dqsien dly found for B1: ( 1, 4, 0)
2642 11:55:58.008865 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2643 11:55:58.012312 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2644 11:55:58.012414
2645 11:55:58.015826 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2646 11:55:58.019316 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2647 11:55:58.022302 [Gating] SW calibration Done
2648 11:55:58.022378 ==
2649 11:55:58.025744 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 11:55:58.032704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 11:55:58.032782 ==
2652 11:55:58.032874 RX Vref Scan: 0
2653 11:55:58.032964
2654 11:55:58.036174 RX Vref 0 -> 0, step: 1
2655 11:55:58.036245
2656 11:55:58.039214 RX Delay -40 -> 252, step: 8
2657 11:55:58.042962 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2658 11:55:58.046262 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2659 11:55:58.049575 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2660 11:55:58.052839 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2661 11:55:58.059393 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2662 11:55:58.063022 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2663 11:55:58.066260 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2664 11:55:58.069461 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2665 11:55:58.073031 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2666 11:55:58.076272 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2667 11:55:58.082836 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2668 11:55:58.086210 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2669 11:55:58.090138 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2670 11:55:58.093119 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2671 11:55:58.096533 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2672 11:55:58.103676 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
2673 11:55:58.103754 ==
2674 11:55:58.107014 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:55:58.109974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:55:58.110057 ==
2677 11:55:58.110119 DQS Delay:
2678 11:55:58.113353 DQS0 = 0, DQS1 = 0
2679 11:55:58.113431 DQM Delay:
2680 11:55:58.116548 DQM0 = 114, DQM1 = 107
2681 11:55:58.116626 DQ Delay:
2682 11:55:58.120350 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =111
2683 11:55:58.123552 DQ4 =115, DQ5 =107, DQ6 =119, DQ7 =123
2684 11:55:58.127024 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
2685 11:55:58.130163 DQ12 =115, DQ13 =115, DQ14 =119, DQ15 =115
2686 11:55:58.130247
2687 11:55:58.130314
2688 11:55:58.130446 ==
2689 11:55:58.133538 Dram Type= 6, Freq= 0, CH_0, rank 0
2690 11:55:58.140025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2691 11:55:58.140134 ==
2692 11:55:58.140223
2693 11:55:58.140307
2694 11:55:58.140401 TX Vref Scan disable
2695 11:55:58.143498 == TX Byte 0 ==
2696 11:55:58.147254 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2697 11:55:58.150196 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2698 11:55:58.153712 == TX Byte 1 ==
2699 11:55:58.157277 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2700 11:55:58.160224 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2701 11:55:58.163757 ==
2702 11:55:58.163837 Dram Type= 6, Freq= 0, CH_0, rank 0
2703 11:55:58.170814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2704 11:55:58.170954 ==
2705 11:55:58.181928 TX Vref=22, minBit 7, minWin=24, winSum=420
2706 11:55:58.184861 TX Vref=24, minBit 5, minWin=25, winSum=422
2707 11:55:58.188428 TX Vref=26, minBit 4, minWin=26, winSum=431
2708 11:55:58.192014 TX Vref=28, minBit 1, minWin=26, winSum=436
2709 11:55:58.194892 TX Vref=30, minBit 1, minWin=26, winSum=435
2710 11:55:58.198577 TX Vref=32, minBit 0, minWin=26, winSum=433
2711 11:55:58.205281 [TxChooseVref] Worse bit 1, Min win 26, Win sum 436, Final Vref 28
2712 11:55:58.205608
2713 11:55:58.208867 Final TX Range 1 Vref 28
2714 11:55:58.209187
2715 11:55:58.209501 ==
2716 11:55:58.212505 Dram Type= 6, Freq= 0, CH_0, rank 0
2717 11:55:58.215765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2718 11:55:58.216320 ==
2719 11:55:58.216801
2720 11:55:58.217278
2721 11:55:58.219102 TX Vref Scan disable
2722 11:55:58.222455 == TX Byte 0 ==
2723 11:55:58.225711 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2724 11:55:58.228914 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2725 11:55:58.232620 == TX Byte 1 ==
2726 11:55:58.235753 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2727 11:55:58.238718 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2728 11:55:58.239318
2729 11:55:58.241880 [DATLAT]
2730 11:55:58.241978 Freq=1200, CH0 RK0
2731 11:55:58.242067
2732 11:55:58.245390 DATLAT Default: 0xd
2733 11:55:58.245503 0, 0xFFFF, sum = 0
2734 11:55:58.248743 1, 0xFFFF, sum = 0
2735 11:55:58.248863 2, 0xFFFF, sum = 0
2736 11:55:58.252024 3, 0xFFFF, sum = 0
2737 11:55:58.252138 4, 0xFFFF, sum = 0
2738 11:55:58.255247 5, 0xFFFF, sum = 0
2739 11:55:58.255329 6, 0xFFFF, sum = 0
2740 11:55:58.258791 7, 0xFFFF, sum = 0
2741 11:55:58.258946 8, 0xFFFF, sum = 0
2742 11:55:58.262490 9, 0xFFFF, sum = 0
2743 11:55:58.262606 10, 0xFFFF, sum = 0
2744 11:55:58.265263 11, 0xFFFF, sum = 0
2745 11:55:58.265369 12, 0x0, sum = 1
2746 11:55:58.268968 13, 0x0, sum = 2
2747 11:55:58.269048 14, 0x0, sum = 3
2748 11:55:58.272348 15, 0x0, sum = 4
2749 11:55:58.272440 best_step = 13
2750 11:55:58.272546
2751 11:55:58.272634 ==
2752 11:55:58.275518 Dram Type= 6, Freq= 0, CH_0, rank 0
2753 11:55:58.282321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2754 11:55:58.282461 ==
2755 11:55:58.282555 RX Vref Scan: 1
2756 11:55:58.282655
2757 11:55:58.285547 Set Vref Range= 32 -> 127
2758 11:55:58.285645
2759 11:55:58.288654 RX Vref 32 -> 127, step: 1
2760 11:55:58.288770
2761 11:55:58.288891 RX Delay -21 -> 252, step: 4
2762 11:55:58.288988
2763 11:55:58.292250 Set Vref, RX VrefLevel [Byte0]: 32
2764 11:55:58.295605 [Byte1]: 32
2765 11:55:58.300489
2766 11:55:58.300596 Set Vref, RX VrefLevel [Byte0]: 33
2767 11:55:58.303227 [Byte1]: 33
2768 11:55:58.307796
2769 11:55:58.307899 Set Vref, RX VrefLevel [Byte0]: 34
2770 11:55:58.311001 [Byte1]: 34
2771 11:55:58.315825
2772 11:55:58.315936 Set Vref, RX VrefLevel [Byte0]: 35
2773 11:55:58.319168 [Byte1]: 35
2774 11:55:58.323389
2775 11:55:58.323504 Set Vref, RX VrefLevel [Byte0]: 36
2776 11:55:58.327074 [Byte1]: 36
2777 11:55:58.331511
2778 11:55:58.331616 Set Vref, RX VrefLevel [Byte0]: 37
2779 11:55:58.335085 [Byte1]: 37
2780 11:55:58.339646
2781 11:55:58.339757 Set Vref, RX VrefLevel [Byte0]: 38
2782 11:55:58.342971 [Byte1]: 38
2783 11:55:58.347619
2784 11:55:58.347702 Set Vref, RX VrefLevel [Byte0]: 39
2785 11:55:58.350606 [Byte1]: 39
2786 11:55:58.355397
2787 11:55:58.355508 Set Vref, RX VrefLevel [Byte0]: 40
2788 11:55:58.358425 [Byte1]: 40
2789 11:55:58.363104
2790 11:55:58.363200 Set Vref, RX VrefLevel [Byte0]: 41
2791 11:55:58.366443 [Byte1]: 41
2792 11:55:58.371115
2793 11:55:58.371214 Set Vref, RX VrefLevel [Byte0]: 42
2794 11:55:58.374382 [Byte1]: 42
2795 11:55:58.379623
2796 11:55:58.379702 Set Vref, RX VrefLevel [Byte0]: 43
2797 11:55:58.382691 [Byte1]: 43
2798 11:55:58.386832
2799 11:55:58.386960 Set Vref, RX VrefLevel [Byte0]: 44
2800 11:55:58.390457 [Byte1]: 44
2801 11:55:58.395329
2802 11:55:58.395402 Set Vref, RX VrefLevel [Byte0]: 45
2803 11:55:58.398455 [Byte1]: 45
2804 11:55:58.402955
2805 11:55:58.403025 Set Vref, RX VrefLevel [Byte0]: 46
2806 11:55:58.406176 [Byte1]: 46
2807 11:55:58.410845
2808 11:55:58.410946 Set Vref, RX VrefLevel [Byte0]: 47
2809 11:55:58.414005 [Byte1]: 47
2810 11:55:58.419096
2811 11:55:58.419166 Set Vref, RX VrefLevel [Byte0]: 48
2812 11:55:58.422414 [Byte1]: 48
2813 11:55:58.426722
2814 11:55:58.426826 Set Vref, RX VrefLevel [Byte0]: 49
2815 11:55:58.430051 [Byte1]: 49
2816 11:55:58.434406
2817 11:55:58.434507 Set Vref, RX VrefLevel [Byte0]: 50
2818 11:55:58.437927 [Byte1]: 50
2819 11:55:58.442426
2820 11:55:58.442500 Set Vref, RX VrefLevel [Byte0]: 51
2821 11:55:58.446138 [Byte1]: 51
2822 11:55:58.450340
2823 11:55:58.450447 Set Vref, RX VrefLevel [Byte0]: 52
2824 11:55:58.453741 [Byte1]: 52
2825 11:55:58.458062
2826 11:55:58.458144 Set Vref, RX VrefLevel [Byte0]: 53
2827 11:55:58.461524 [Byte1]: 53
2828 11:55:58.466518
2829 11:55:58.466624 Set Vref, RX VrefLevel [Byte0]: 54
2830 11:55:58.469520 [Byte1]: 54
2831 11:55:58.474424
2832 11:55:58.474525 Set Vref, RX VrefLevel [Byte0]: 55
2833 11:55:58.477789 [Byte1]: 55
2834 11:55:58.482070
2835 11:55:58.482141 Set Vref, RX VrefLevel [Byte0]: 56
2836 11:55:58.485830 [Byte1]: 56
2837 11:55:58.489670
2838 11:55:58.489771 Set Vref, RX VrefLevel [Byte0]: 57
2839 11:55:58.493240 [Byte1]: 57
2840 11:55:58.498163
2841 11:55:58.498266 Set Vref, RX VrefLevel [Byte0]: 58
2842 11:55:58.501546 [Byte1]: 58
2843 11:55:58.505721
2844 11:55:58.505805 Set Vref, RX VrefLevel [Byte0]: 59
2845 11:55:58.509012 [Byte1]: 59
2846 11:55:58.514186
2847 11:55:58.514296 Set Vref, RX VrefLevel [Byte0]: 60
2848 11:55:58.516951 [Byte1]: 60
2849 11:55:58.521619
2850 11:55:58.521720 Set Vref, RX VrefLevel [Byte0]: 61
2851 11:55:58.524713 [Byte1]: 61
2852 11:55:58.529813
2853 11:55:58.529911 Set Vref, RX VrefLevel [Byte0]: 62
2854 11:55:58.533026 [Byte1]: 62
2855 11:55:58.537344
2856 11:55:58.537453 Set Vref, RX VrefLevel [Byte0]: 63
2857 11:55:58.540926 [Byte1]: 63
2858 11:55:58.545589
2859 11:55:58.545693 Set Vref, RX VrefLevel [Byte0]: 64
2860 11:55:58.548749 [Byte1]: 64
2861 11:55:58.553292
2862 11:55:58.553400 Set Vref, RX VrefLevel [Byte0]: 65
2863 11:55:58.556791 [Byte1]: 65
2864 11:55:58.561575
2865 11:55:58.561680 Set Vref, RX VrefLevel [Byte0]: 66
2866 11:55:58.564418 [Byte1]: 66
2867 11:55:58.569549
2868 11:55:58.569649 Final RX Vref Byte 0 = 55 to rank0
2869 11:55:58.572655 Final RX Vref Byte 1 = 53 to rank0
2870 11:55:58.575860 Final RX Vref Byte 0 = 55 to rank1
2871 11:55:58.579672 Final RX Vref Byte 1 = 53 to rank1==
2872 11:55:58.582506 Dram Type= 6, Freq= 0, CH_0, rank 0
2873 11:55:58.586134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 11:55:58.589784 ==
2875 11:55:58.589892 DQS Delay:
2876 11:55:58.589959 DQS0 = 0, DQS1 = 0
2877 11:55:58.592983 DQM Delay:
2878 11:55:58.593090 DQM0 = 115, DQM1 = 106
2879 11:55:58.596449 DQ Delay:
2880 11:55:58.599366 DQ0 =114, DQ1 =114, DQ2 =112, DQ3 =112
2881 11:55:58.603193 DQ4 =116, DQ5 =110, DQ6 =120, DQ7 =122
2882 11:55:58.605941 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =96
2883 11:55:58.609715 DQ12 =112, DQ13 =112, DQ14 =120, DQ15 =116
2884 11:55:58.609823
2885 11:55:58.609913
2886 11:55:58.616138 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbeb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
2887 11:55:58.619390 CH0 RK0: MR19=303, MR18=FBEB
2888 11:55:58.626518 CH0_RK0: MR19=0x303, MR18=0xFBEB, DQSOSC=412, MR23=63, INC=38, DEC=25
2889 11:55:58.626619
2890 11:55:58.629725 ----->DramcWriteLeveling(PI) begin...
2891 11:55:58.629824 ==
2892 11:55:58.633126 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 11:55:58.636472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 11:55:58.636571 ==
2895 11:55:58.640083 Write leveling (Byte 0): 32 => 32
2896 11:55:58.643298 Write leveling (Byte 1): 30 => 30
2897 11:55:58.646826 DramcWriteLeveling(PI) end<-----
2898 11:55:58.646957
2899 11:55:58.647043 ==
2900 11:55:58.649688 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 11:55:58.653516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 11:55:58.653591 ==
2903 11:55:58.656697 [Gating] SW mode calibration
2904 11:55:58.663189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2905 11:55:58.669700 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2906 11:55:58.673050 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2907 11:55:58.679738 0 15 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
2908 11:55:58.683217 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 11:55:58.686567 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 11:55:58.689978 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 11:55:58.696823 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 11:55:58.700012 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2913 11:55:58.703888 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2914 11:55:58.710304 1 0 0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
2915 11:55:58.713503 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:55:58.717036 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:55:58.723815 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 11:55:58.727260 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 11:55:58.730244 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 11:55:58.737147 1 0 24 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2921 11:55:58.740494 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2922 11:55:58.743683 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2923 11:55:58.747375 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2924 11:55:58.753643 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:55:58.757158 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 11:55:58.760486 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 11:55:58.767604 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 11:55:58.770898 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 11:55:58.773932 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2930 11:55:58.780921 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2931 11:55:58.784538 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2932 11:55:58.787326 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:55:58.794484 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:55:58.797822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:55:58.801305 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:55:58.804328 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:55:58.811128 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:55:58.814166 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:55:58.817443 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:55:58.824537 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:55:58.827574 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 11:55:58.830809 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 11:55:58.838016 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 11:55:58.841466 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2945 11:55:58.844807 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2946 11:55:58.851877 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2947 11:55:58.851956 Total UI for P1: 0, mck2ui 16
2948 11:55:58.854811 best dqsien dly found for B0: ( 1, 3, 26)
2949 11:55:58.861402 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2950 11:55:58.864609 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2951 11:55:58.867793 Total UI for P1: 0, mck2ui 16
2952 11:55:58.871078 best dqsien dly found for B1: ( 1, 4, 0)
2953 11:55:58.874482 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2954 11:55:58.878145 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2955 11:55:58.878223
2956 11:55:58.881170 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2957 11:55:58.884762 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2958 11:55:58.887887 [Gating] SW calibration Done
2959 11:55:58.887966 ==
2960 11:55:58.891519 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 11:55:58.897891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 11:55:58.897970 ==
2963 11:55:58.898032 RX Vref Scan: 0
2964 11:55:58.898089
2965 11:55:58.901548 RX Vref 0 -> 0, step: 1
2966 11:55:58.901626
2967 11:55:58.904705 RX Delay -40 -> 252, step: 8
2968 11:55:58.908251 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2969 11:55:58.911243 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2970 11:55:58.914632 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2971 11:55:58.918088 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2972 11:55:58.924861 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2973 11:55:58.928079 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2974 11:55:58.931679 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2975 11:55:58.935090 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2976 11:55:58.938337 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2977 11:55:58.941145 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2978 11:55:58.948275 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2979 11:55:58.951439 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2980 11:55:58.954691 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2981 11:55:58.958035 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2982 11:55:58.961553 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2983 11:55:58.968362 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2984 11:55:58.968475 ==
2985 11:55:58.972091 Dram Type= 6, Freq= 0, CH_0, rank 1
2986 11:55:58.974872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2987 11:55:58.974963 ==
2988 11:55:58.975030 DQS Delay:
2989 11:55:58.978575 DQS0 = 0, DQS1 = 0
2990 11:55:58.978679 DQM Delay:
2991 11:55:58.981748 DQM0 = 116, DQM1 = 106
2992 11:55:58.981865 DQ Delay:
2993 11:55:58.985123 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2994 11:55:58.989010 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2995 11:55:58.991599 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2996 11:55:58.995287 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2997 11:55:58.995377
2998 11:55:58.995473
2999 11:55:58.995567 ==
3000 11:55:58.998722 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 11:55:59.005073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 11:55:59.005176 ==
3003 11:55:59.005266
3004 11:55:59.005371
3005 11:55:59.005459 TX Vref Scan disable
3006 11:55:59.008928 == TX Byte 0 ==
3007 11:55:59.012670 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3008 11:55:59.015366 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3009 11:55:59.018792 == TX Byte 1 ==
3010 11:55:59.022301 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3011 11:55:59.025341 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3012 11:55:59.028952 ==
3013 11:55:59.032434 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 11:55:59.035695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 11:55:59.035796 ==
3016 11:55:59.046976 TX Vref=22, minBit 3, minWin=25, winSum=422
3017 11:55:59.049873 TX Vref=24, minBit 3, minWin=25, winSum=425
3018 11:55:59.053552 TX Vref=26, minBit 0, minWin=26, winSum=430
3019 11:55:59.056812 TX Vref=28, minBit 0, minWin=27, winSum=436
3020 11:55:59.060676 TX Vref=30, minBit 2, minWin=26, winSum=436
3021 11:55:59.063812 TX Vref=32, minBit 3, minWin=26, winSum=435
3022 11:55:59.070393 [TxChooseVref] Worse bit 0, Min win 27, Win sum 436, Final Vref 28
3023 11:55:59.070527
3024 11:55:59.073760 Final TX Range 1 Vref 28
3025 11:55:59.073893
3026 11:55:59.074012 ==
3027 11:55:59.076608 Dram Type= 6, Freq= 0, CH_0, rank 1
3028 11:55:59.080872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3029 11:55:59.081285 ==
3030 11:55:59.081611
3031 11:55:59.081912
3032 11:55:59.083814 TX Vref Scan disable
3033 11:55:59.087084 == TX Byte 0 ==
3034 11:55:59.090724 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3035 11:55:59.093862 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3036 11:55:59.097493 == TX Byte 1 ==
3037 11:55:59.100683 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3038 11:55:59.104329 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3039 11:55:59.104738
3040 11:55:59.107563 [DATLAT]
3041 11:55:59.107968 Freq=1200, CH0 RK1
3042 11:55:59.108290
3043 11:55:59.110791 DATLAT Default: 0xd
3044 11:55:59.111226 0, 0xFFFF, sum = 0
3045 11:55:59.113954 1, 0xFFFF, sum = 0
3046 11:55:59.114364 2, 0xFFFF, sum = 0
3047 11:55:59.117680 3, 0xFFFF, sum = 0
3048 11:55:59.118091 4, 0xFFFF, sum = 0
3049 11:55:59.121222 5, 0xFFFF, sum = 0
3050 11:55:59.121635 6, 0xFFFF, sum = 0
3051 11:55:59.124514 7, 0xFFFF, sum = 0
3052 11:55:59.124993 8, 0xFFFF, sum = 0
3053 11:55:59.127602 9, 0xFFFF, sum = 0
3054 11:55:59.128065 10, 0xFFFF, sum = 0
3055 11:55:59.130722 11, 0xFFFF, sum = 0
3056 11:55:59.131164 12, 0x0, sum = 1
3057 11:55:59.134253 13, 0x0, sum = 2
3058 11:55:59.134664 14, 0x0, sum = 3
3059 11:55:59.137911 15, 0x0, sum = 4
3060 11:55:59.138478 best_step = 13
3061 11:55:59.138816
3062 11:55:59.139166 ==
3063 11:55:59.140927 Dram Type= 6, Freq= 0, CH_0, rank 1
3064 11:55:59.147895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3065 11:55:59.148303 ==
3066 11:55:59.148622 RX Vref Scan: 0
3067 11:55:59.148922
3068 11:55:59.151152 RX Vref 0 -> 0, step: 1
3069 11:55:59.151554
3070 11:55:59.154234 RX Delay -21 -> 252, step: 4
3071 11:55:59.157611 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3072 11:55:59.161165 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3073 11:55:59.164226 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3074 11:55:59.171535 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3075 11:55:59.174611 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3076 11:55:59.177678 iDelay=195, Bit 5, Center 106 (35 ~ 178) 144
3077 11:55:59.181020 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3078 11:55:59.184442 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3079 11:55:59.191149 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3080 11:55:59.194560 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3081 11:55:59.198049 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3082 11:55:59.201182 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3083 11:55:59.204906 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3084 11:55:59.208396 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3085 11:55:59.214571 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3086 11:55:59.218017 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3087 11:55:59.218500 ==
3088 11:55:59.221707 Dram Type= 6, Freq= 0, CH_0, rank 1
3089 11:55:59.224892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 11:55:59.225324 ==
3091 11:55:59.228185 DQS Delay:
3092 11:55:59.228506 DQS0 = 0, DQS1 = 0
3093 11:55:59.228573 DQM Delay:
3094 11:55:59.231381 DQM0 = 114, DQM1 = 105
3095 11:55:59.231459 DQ Delay:
3096 11:55:59.234670 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3097 11:55:59.237730 DQ4 =112, DQ5 =106, DQ6 =120, DQ7 =122
3098 11:55:59.241468 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =96
3099 11:55:59.244601 DQ12 =110, DQ13 =112, DQ14 =116, DQ15 =114
3100 11:55:59.247761
3101 11:55:59.247839
3102 11:55:59.255135 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3103 11:55:59.257989 CH0 RK1: MR19=403, MR18=5F7
3104 11:55:59.261250 CH0_RK1: MR19=0x403, MR18=0x5F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3105 11:55:59.264660 [RxdqsGatingPostProcess] freq 1200
3106 11:55:59.271855 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3107 11:55:59.274800 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 11:55:59.278625 best DQS1 dly(2T, 0.5T) = (0, 12)
3109 11:55:59.281753 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 11:55:59.285297 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3111 11:55:59.288388 best DQS0 dly(2T, 0.5T) = (0, 11)
3112 11:55:59.291780 best DQS1 dly(2T, 0.5T) = (0, 12)
3113 11:55:59.295062 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3114 11:55:59.298297 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3115 11:55:59.298376 Pre-setting of DQS Precalculation
3116 11:55:59.305265 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3117 11:55:59.305348 ==
3118 11:55:59.308532 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 11:55:59.311942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 11:55:59.312027 ==
3121 11:55:59.318443 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3122 11:55:59.325316 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3123 11:55:59.332611 [CA 0] Center 38 (9~68) winsize 60
3124 11:55:59.336021 [CA 1] Center 38 (8~68) winsize 61
3125 11:55:59.339239 [CA 2] Center 35 (5~65) winsize 61
3126 11:55:59.342895 [CA 3] Center 34 (4~65) winsize 62
3127 11:55:59.345794 [CA 4] Center 34 (4~65) winsize 62
3128 11:55:59.349406 [CA 5] Center 34 (4~64) winsize 61
3129 11:55:59.349573
3130 11:55:59.352608 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3131 11:55:59.352801
3132 11:55:59.356018 [CATrainingPosCal] consider 1 rank data
3133 11:55:59.359054 u2DelayCellTimex100 = 270/100 ps
3134 11:55:59.362738 CA0 delay=38 (9~68),Diff = 4 PI (19 cell)
3135 11:55:59.366422 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3136 11:55:59.369539 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3137 11:55:59.376008 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3138 11:55:59.379889 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3139 11:55:59.382941 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3140 11:55:59.383331
3141 11:55:59.386302 CA PerBit enable=1, Macro0, CA PI delay=34
3142 11:55:59.386839
3143 11:55:59.389641 [CBTSetCACLKResult] CA Dly = 34
3144 11:55:59.390048 CS Dly: 6 (0~37)
3145 11:55:59.390368 ==
3146 11:55:59.393399 Dram Type= 6, Freq= 0, CH_1, rank 1
3147 11:55:59.400141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3148 11:55:59.400776 ==
3149 11:55:59.403807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3150 11:55:59.410128 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3151 11:55:59.418551 [CA 0] Center 38 (8~68) winsize 61
3152 11:55:59.421925 [CA 1] Center 38 (9~67) winsize 59
3153 11:55:59.425427 [CA 2] Center 34 (4~65) winsize 62
3154 11:55:59.428251 [CA 3] Center 34 (4~65) winsize 62
3155 11:55:59.431927 [CA 4] Center 34 (4~65) winsize 62
3156 11:55:59.435122 [CA 5] Center 33 (3~63) winsize 61
3157 11:55:59.435547
3158 11:55:59.438619 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3159 11:55:59.439282
3160 11:55:59.442096 [CATrainingPosCal] consider 2 rank data
3161 11:55:59.445221 u2DelayCellTimex100 = 270/100 ps
3162 11:55:59.448483 CA0 delay=38 (9~68),Diff = 5 PI (24 cell)
3163 11:55:59.452305 CA1 delay=38 (9~67),Diff = 5 PI (24 cell)
3164 11:55:59.455389 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3165 11:55:59.461745 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3166 11:55:59.465179 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3167 11:55:59.468566 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3168 11:55:59.468973
3169 11:55:59.471997 CA PerBit enable=1, Macro0, CA PI delay=33
3170 11:55:59.472403
3171 11:55:59.475284 [CBTSetCACLKResult] CA Dly = 33
3172 11:55:59.475842 CS Dly: 7 (0~40)
3173 11:55:59.476177
3174 11:55:59.479000 ----->DramcWriteLeveling(PI) begin...
3175 11:55:59.479412 ==
3176 11:55:59.482805 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 11:55:59.488775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 11:55:59.489181 ==
3179 11:55:59.491999 Write leveling (Byte 0): 26 => 26
3180 11:55:59.492403 Write leveling (Byte 1): 30 => 30
3181 11:55:59.495403 DramcWriteLeveling(PI) end<-----
3182 11:55:59.496001
3183 11:55:59.499032 ==
3184 11:55:59.499437 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 11:55:59.505682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 11:55:59.506087 ==
3187 11:55:59.509116 [Gating] SW mode calibration
3188 11:55:59.515444 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3189 11:55:59.519192 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3190 11:55:59.526239 0 15 0 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)
3191 11:55:59.528919 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:55:59.532066 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 11:55:59.536089 0 15 12 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
3194 11:55:59.542413 0 15 16 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3195 11:55:59.545527 0 15 20 | B1->B0 | 3534 3434 | 1 1 | (1 1) (1 1)
3196 11:55:59.549302 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3197 11:55:59.556341 0 15 28 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 0)
3198 11:55:59.559154 1 0 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3199 11:55:59.562590 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:55:59.569327 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 11:55:59.572727 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 11:55:59.576136 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3203 11:55:59.582815 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3204 11:55:59.585769 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3205 11:55:59.589196 1 0 28 | B1->B0 | 2727 2424 | 0 0 | (0 0) (0 0)
3206 11:55:59.596184 1 1 0 | B1->B0 | 4141 3434 | 0 0 | (0 0) (0 0)
3207 11:55:59.599385 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:55:59.603368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 11:55:59.605919 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 11:55:59.613127 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3211 11:55:59.615883 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3212 11:55:59.619474 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3213 11:55:59.626245 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3214 11:55:59.629458 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:55:59.632713 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:55:59.639711 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:55:59.642841 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:55:59.646407 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:55:59.653034 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:55:59.656167 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:55:59.659974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:55:59.662931 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:55:59.669717 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:55:59.672883 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 11:55:59.676320 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 11:55:59.683379 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 11:55:59.686172 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 11:55:59.689860 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:55:59.696400 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3230 11:55:59.699948 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 11:55:59.703290 Total UI for P1: 0, mck2ui 16
3232 11:55:59.706599 best dqsien dly found for B0: ( 1, 3, 28)
3233 11:55:59.709924 Total UI for P1: 0, mck2ui 16
3234 11:55:59.713538 best dqsien dly found for B1: ( 1, 3, 30)
3235 11:55:59.716683 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3236 11:55:59.719963 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3237 11:55:59.720418
3238 11:55:59.723203 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3239 11:55:59.726605 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3240 11:55:59.730120 [Gating] SW calibration Done
3241 11:55:59.730574 ==
3242 11:55:59.733466 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 11:55:59.736958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 11:55:59.737389 ==
3245 11:55:59.740348 RX Vref Scan: 0
3246 11:55:59.741007
3247 11:55:59.743669 RX Vref 0 -> 0, step: 1
3248 11:55:59.744345
3249 11:55:59.744979 RX Delay -40 -> 252, step: 8
3250 11:55:59.750242 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3251 11:55:59.753600 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3252 11:55:59.756866 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3253 11:55:59.760064 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3254 11:55:59.763522 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3255 11:55:59.766775 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3256 11:55:59.773840 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3257 11:55:59.777070 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3258 11:55:59.780082 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3259 11:55:59.783473 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3260 11:55:59.786776 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3261 11:55:59.793461 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3262 11:55:59.797051 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3263 11:55:59.800260 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3264 11:55:59.804177 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3265 11:55:59.807070 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
3266 11:55:59.807153 ==
3267 11:55:59.810389 Dram Type= 6, Freq= 0, CH_1, rank 0
3268 11:55:59.817285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3269 11:55:59.817393 ==
3270 11:55:59.817496 DQS Delay:
3271 11:55:59.820515 DQS0 = 0, DQS1 = 0
3272 11:55:59.820598 DQM Delay:
3273 11:55:59.820682 DQM0 = 116, DQM1 = 109
3274 11:55:59.824494 DQ Delay:
3275 11:55:59.827235 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3276 11:55:59.830516 DQ4 =111, DQ5 =127, DQ6 =127, DQ7 =115
3277 11:55:59.834077 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3278 11:55:59.837778 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =115
3279 11:55:59.837863
3280 11:55:59.837929
3281 11:55:59.837991 ==
3282 11:55:59.840681 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 11:55:59.844001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 11:55:59.844085 ==
3285 11:55:59.847312
3286 11:55:59.847390
3287 11:55:59.847453 TX Vref Scan disable
3288 11:55:59.850698 == TX Byte 0 ==
3289 11:55:59.853871 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3290 11:55:59.857554 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3291 11:55:59.860751 == TX Byte 1 ==
3292 11:55:59.864260 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3293 11:55:59.867314 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3294 11:55:59.867429 ==
3295 11:55:59.870775 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 11:55:59.877260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 11:55:59.877341 ==
3298 11:55:59.888182 TX Vref=22, minBit 2, minWin=25, winSum=411
3299 11:55:59.891578 TX Vref=24, minBit 1, minWin=25, winSum=413
3300 11:55:59.894778 TX Vref=26, minBit 0, minWin=26, winSum=422
3301 11:55:59.898125 TX Vref=28, minBit 0, minWin=26, winSum=429
3302 11:55:59.901916 TX Vref=30, minBit 1, minWin=26, winSum=429
3303 11:55:59.905142 TX Vref=32, minBit 1, minWin=26, winSum=428
3304 11:55:59.911789 [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28
3305 11:55:59.911921
3306 11:55:59.915235 Final TX Range 1 Vref 28
3307 11:55:59.915381
3308 11:55:59.915496 ==
3309 11:55:59.918751 Dram Type= 6, Freq= 0, CH_1, rank 0
3310 11:55:59.922169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3311 11:55:59.922373 ==
3312 11:55:59.922528
3313 11:55:59.922669
3314 11:55:59.925362 TX Vref Scan disable
3315 11:55:59.928855 == TX Byte 0 ==
3316 11:55:59.932005 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3317 11:55:59.935732 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3318 11:55:59.939084 == TX Byte 1 ==
3319 11:55:59.942296 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3320 11:55:59.945767 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3321 11:55:59.946175
3322 11:55:59.948981 [DATLAT]
3323 11:55:59.949382 Freq=1200, CH1 RK0
3324 11:55:59.949703
3325 11:55:59.952433 DATLAT Default: 0xd
3326 11:55:59.952837 0, 0xFFFF, sum = 0
3327 11:55:59.956088 1, 0xFFFF, sum = 0
3328 11:55:59.956496 2, 0xFFFF, sum = 0
3329 11:55:59.959699 3, 0xFFFF, sum = 0
3330 11:55:59.960121 4, 0xFFFF, sum = 0
3331 11:55:59.963016 5, 0xFFFF, sum = 0
3332 11:55:59.963535 6, 0xFFFF, sum = 0
3333 11:55:59.965850 7, 0xFFFF, sum = 0
3334 11:55:59.966261 8, 0xFFFF, sum = 0
3335 11:55:59.968959 9, 0xFFFF, sum = 0
3336 11:55:59.969373 10, 0xFFFF, sum = 0
3337 11:55:59.972260 11, 0xFFFF, sum = 0
3338 11:55:59.972670 12, 0x0, sum = 1
3339 11:55:59.976323 13, 0x0, sum = 2
3340 11:55:59.976734 14, 0x0, sum = 3
3341 11:55:59.979358 15, 0x0, sum = 4
3342 11:55:59.979769 best_step = 13
3343 11:55:59.980090
3344 11:55:59.980387 ==
3345 11:55:59.982656 Dram Type= 6, Freq= 0, CH_1, rank 0
3346 11:55:59.986281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3347 11:55:59.989675 ==
3348 11:55:59.990196 RX Vref Scan: 1
3349 11:55:59.990523
3350 11:55:59.993195 Set Vref Range= 32 -> 127
3351 11:55:59.993603
3352 11:55:59.993920 RX Vref 32 -> 127, step: 1
3353 11:55:59.996783
3354 11:55:59.997293 RX Delay -21 -> 252, step: 4
3355 11:55:59.997619
3356 11:55:59.999720 Set Vref, RX VrefLevel [Byte0]: 32
3357 11:56:00.002897 [Byte1]: 32
3358 11:56:00.006822
3359 11:56:00.007287 Set Vref, RX VrefLevel [Byte0]: 33
3360 11:56:00.009887 [Byte1]: 33
3361 11:56:00.014416
3362 11:56:00.014958 Set Vref, RX VrefLevel [Byte0]: 34
3363 11:56:00.017735 [Byte1]: 34
3364 11:56:00.023098
3365 11:56:00.023597 Set Vref, RX VrefLevel [Byte0]: 35
3366 11:56:00.025816 [Byte1]: 35
3367 11:56:00.030714
3368 11:56:00.031302 Set Vref, RX VrefLevel [Byte0]: 36
3369 11:56:00.033977 [Byte1]: 36
3370 11:56:00.038333
3371 11:56:00.038723 Set Vref, RX VrefLevel [Byte0]: 37
3372 11:56:00.041657 [Byte1]: 37
3373 11:56:00.046179
3374 11:56:00.046481 Set Vref, RX VrefLevel [Byte0]: 38
3375 11:56:00.049643 [Byte1]: 38
3376 11:56:00.054555
3377 11:56:00.054840 Set Vref, RX VrefLevel [Byte0]: 39
3378 11:56:00.057898 [Byte1]: 39
3379 11:56:00.062821
3380 11:56:00.063242 Set Vref, RX VrefLevel [Byte0]: 40
3381 11:56:00.065630 [Byte1]: 40
3382 11:56:00.070053
3383 11:56:00.070441 Set Vref, RX VrefLevel [Byte0]: 41
3384 11:56:00.073828 [Byte1]: 41
3385 11:56:00.078615
3386 11:56:00.079199 Set Vref, RX VrefLevel [Byte0]: 42
3387 11:56:00.081844 [Byte1]: 42
3388 11:56:00.085987
3389 11:56:00.086430 Set Vref, RX VrefLevel [Byte0]: 43
3390 11:56:00.089428 [Byte1]: 43
3391 11:56:00.094257
3392 11:56:00.094800 Set Vref, RX VrefLevel [Byte0]: 44
3393 11:56:00.097625 [Byte1]: 44
3394 11:56:00.102256
3395 11:56:00.102812 Set Vref, RX VrefLevel [Byte0]: 45
3396 11:56:00.105274 [Byte1]: 45
3397 11:56:00.110262
3398 11:56:00.110808 Set Vref, RX VrefLevel [Byte0]: 46
3399 11:56:00.113865 [Byte1]: 46
3400 11:56:00.118058
3401 11:56:00.118613 Set Vref, RX VrefLevel [Byte0]: 47
3402 11:56:00.121140 [Byte1]: 47
3403 11:56:00.125966
3404 11:56:00.126517 Set Vref, RX VrefLevel [Byte0]: 48
3405 11:56:00.129041 [Byte1]: 48
3406 11:56:00.133735
3407 11:56:00.134283 Set Vref, RX VrefLevel [Byte0]: 49
3408 11:56:00.136687 [Byte1]: 49
3409 11:56:00.141085
3410 11:56:00.141682 Set Vref, RX VrefLevel [Byte0]: 50
3411 11:56:00.144546 [Byte1]: 50
3412 11:56:00.149050
3413 11:56:00.149497 Set Vref, RX VrefLevel [Byte0]: 51
3414 11:56:00.152827 [Byte1]: 51
3415 11:56:00.157306
3416 11:56:00.157852 Set Vref, RX VrefLevel [Byte0]: 52
3417 11:56:00.160969 [Byte1]: 52
3418 11:56:00.164854
3419 11:56:00.165446 Set Vref, RX VrefLevel [Byte0]: 53
3420 11:56:00.168534 [Byte1]: 53
3421 11:56:00.173209
3422 11:56:00.173610 Set Vref, RX VrefLevel [Byte0]: 54
3423 11:56:00.176454 [Byte1]: 54
3424 11:56:00.180976
3425 11:56:00.181382 Set Vref, RX VrefLevel [Byte0]: 55
3426 11:56:00.184689 [Byte1]: 55
3427 11:56:00.189192
3428 11:56:00.189713 Set Vref, RX VrefLevel [Byte0]: 56
3429 11:56:00.192114 [Byte1]: 56
3430 11:56:00.196671
3431 11:56:00.197079 Set Vref, RX VrefLevel [Byte0]: 57
3432 11:56:00.200340 [Byte1]: 57
3433 11:56:00.204860
3434 11:56:00.205269 Set Vref, RX VrefLevel [Byte0]: 58
3435 11:56:00.208300 [Byte1]: 58
3436 11:56:00.212861
3437 11:56:00.213270 Set Vref, RX VrefLevel [Byte0]: 59
3438 11:56:00.216017 [Byte1]: 59
3439 11:56:00.221060
3440 11:56:00.221488 Set Vref, RX VrefLevel [Byte0]: 60
3441 11:56:00.224066 [Byte1]: 60
3442 11:56:00.228402
3443 11:56:00.228826 Set Vref, RX VrefLevel [Byte0]: 61
3444 11:56:00.231718 [Byte1]: 61
3445 11:56:00.236168
3446 11:56:00.236571 Set Vref, RX VrefLevel [Byte0]: 62
3447 11:56:00.239745 [Byte1]: 62
3448 11:56:00.244143
3449 11:56:00.244564 Set Vref, RX VrefLevel [Byte0]: 63
3450 11:56:00.247893 [Byte1]: 63
3451 11:56:00.252286
3452 11:56:00.252840 Set Vref, RX VrefLevel [Byte0]: 64
3453 11:56:00.255857 [Byte1]: 64
3454 11:56:00.260080
3455 11:56:00.260530 Set Vref, RX VrefLevel [Byte0]: 65
3456 11:56:00.263263 [Byte1]: 65
3457 11:56:00.268226
3458 11:56:00.268663 Set Vref, RX VrefLevel [Byte0]: 66
3459 11:56:00.271396 [Byte1]: 66
3460 11:56:00.275913
3461 11:56:00.276443 Set Vref, RX VrefLevel [Byte0]: 67
3462 11:56:00.279301 [Byte1]: 67
3463 11:56:00.284000
3464 11:56:00.284429 Set Vref, RX VrefLevel [Byte0]: 68
3465 11:56:00.287243 [Byte1]: 68
3466 11:56:00.291633
3467 11:56:00.292072 Set Vref, RX VrefLevel [Byte0]: 69
3468 11:56:00.294946 [Byte1]: 69
3469 11:56:00.299831
3470 11:56:00.300260 Set Vref, RX VrefLevel [Byte0]: 70
3471 11:56:00.302992 [Byte1]: 70
3472 11:56:00.307851
3473 11:56:00.308272 Set Vref, RX VrefLevel [Byte0]: 71
3474 11:56:00.311093 [Byte1]: 71
3475 11:56:00.315697
3476 11:56:00.316223 Set Vref, RX VrefLevel [Byte0]: 72
3477 11:56:00.318721 [Byte1]: 72
3478 11:56:00.323405
3479 11:56:00.323827 Final RX Vref Byte 0 = 56 to rank0
3480 11:56:00.327060 Final RX Vref Byte 1 = 53 to rank0
3481 11:56:00.330227 Final RX Vref Byte 0 = 56 to rank1
3482 11:56:00.334086 Final RX Vref Byte 1 = 53 to rank1==
3483 11:56:00.337136 Dram Type= 6, Freq= 0, CH_1, rank 0
3484 11:56:00.340361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 11:56:00.343535 ==
3486 11:56:00.343960 DQS Delay:
3487 11:56:00.344395 DQS0 = 0, DQS1 = 0
3488 11:56:00.347498 DQM Delay:
3489 11:56:00.348023 DQM0 = 115, DQM1 = 110
3490 11:56:00.350850 DQ Delay:
3491 11:56:00.354462 DQ0 =116, DQ1 =108, DQ2 =106, DQ3 =112
3492 11:56:00.357800 DQ4 =116, DQ5 =124, DQ6 =128, DQ7 =112
3493 11:56:00.361004 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3494 11:56:00.363938 DQ12 =118, DQ13 =116, DQ14 =116, DQ15 =114
3495 11:56:00.364363
3496 11:56:00.364797
3497 11:56:00.370760 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3498 11:56:00.374034 CH1 RK0: MR19=403, MR18=1E6
3499 11:56:00.380844 CH1_RK0: MR19=0x403, MR18=0x1E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3500 11:56:00.381375
3501 11:56:00.384085 ----->DramcWriteLeveling(PI) begin...
3502 11:56:00.384613 ==
3503 11:56:00.387623 Dram Type= 6, Freq= 0, CH_1, rank 1
3504 11:56:00.391040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3505 11:56:00.391604 ==
3506 11:56:00.394416 Write leveling (Byte 0): 26 => 26
3507 11:56:00.397441 Write leveling (Byte 1): 29 => 29
3508 11:56:00.401405 DramcWriteLeveling(PI) end<-----
3509 11:56:00.401964
3510 11:56:00.402324 ==
3511 11:56:00.404519 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 11:56:00.408312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 11:56:00.408869 ==
3514 11:56:00.411218 [Gating] SW mode calibration
3515 11:56:00.417878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3516 11:56:00.425045 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3517 11:56:00.427753 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3518 11:56:00.431340 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 11:56:00.437916 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 11:56:00.441444 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 11:56:00.444766 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 11:56:00.451906 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3523 11:56:00.455395 0 15 24 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
3524 11:56:00.458198 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3525 11:56:00.465199 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 11:56:00.468196 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 11:56:00.471684 1 0 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3528 11:56:00.478207 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 11:56:00.481993 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3530 11:56:00.485126 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:56:00.491592 1 0 24 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
3532 11:56:00.495040 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (1 1) (0 0)
3533 11:56:00.498210 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 11:56:00.501779 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:56:00.508480 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:56:00.511490 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:56:00.515485 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:56:00.521044 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:56:00.525027 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3540 11:56:00.528077 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3541 11:56:00.534616 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:56:00.537762 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:56:00.541477 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:56:00.548348 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:56:00.551236 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:56:00.554614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:56:00.561507 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:56:00.564843 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:56:00.568358 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:56:00.574937 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:56:00.578504 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:56:00.581407 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:56:00.584940 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:56:00.591654 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:56:00.595020 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3556 11:56:00.598617 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3557 11:56:00.604877 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3558 11:56:00.608201 Total UI for P1: 0, mck2ui 16
3559 11:56:00.611710 best dqsien dly found for B0: ( 1, 3, 26)
3560 11:56:00.612270 Total UI for P1: 0, mck2ui 16
3561 11:56:00.618246 best dqsien dly found for B1: ( 1, 3, 26)
3562 11:56:00.621492 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3563 11:56:00.625047 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3564 11:56:00.625514
3565 11:56:00.628178 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3566 11:56:00.631757 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3567 11:56:00.635255 [Gating] SW calibration Done
3568 11:56:00.635707 ==
3569 11:56:00.638121 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:56:00.641746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:56:00.642217 ==
3572 11:56:00.645129 RX Vref Scan: 0
3573 11:56:00.645549
3574 11:56:00.645985 RX Vref 0 -> 0, step: 1
3575 11:56:00.646396
3576 11:56:00.648180 RX Delay -40 -> 252, step: 8
3577 11:56:00.651744 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3578 11:56:00.658551 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3579 11:56:00.661712 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3580 11:56:00.665275 iDelay=192, Bit 3, Center 111 (40 ~ 183) 144
3581 11:56:00.668643 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3582 11:56:00.671936 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3583 11:56:00.675468 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3584 11:56:00.681803 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3585 11:56:00.685310 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3586 11:56:00.688420 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3587 11:56:00.691719 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3588 11:56:00.695139 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3589 11:56:00.702226 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3590 11:56:00.705198 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3591 11:56:00.708659 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3592 11:56:00.712352 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3593 11:56:00.712880 ==
3594 11:56:00.715076 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 11:56:00.721902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 11:56:00.722330 ==
3597 11:56:00.722764 DQS Delay:
3598 11:56:00.723200 DQS0 = 0, DQS1 = 0
3599 11:56:00.725387 DQM Delay:
3600 11:56:00.725911 DQM0 = 112, DQM1 = 110
3601 11:56:00.728429 DQ Delay:
3602 11:56:00.732221 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =111
3603 11:56:00.735505 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3604 11:56:00.738970 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3605 11:56:00.742056 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3606 11:56:00.742588
3607 11:56:00.743069
3608 11:56:00.743480 ==
3609 11:56:00.745562 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 11:56:00.748473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 11:56:00.748941 ==
3612 11:56:00.752131
3613 11:56:00.752661
3614 11:56:00.753102 TX Vref Scan disable
3615 11:56:00.755428 == TX Byte 0 ==
3616 11:56:00.759231 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3617 11:56:00.762506 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3618 11:56:00.765246 == TX Byte 1 ==
3619 11:56:00.769222 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3620 11:56:00.772248 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3621 11:56:00.772660 ==
3622 11:56:00.775597 Dram Type= 6, Freq= 0, CH_1, rank 1
3623 11:56:00.782715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3624 11:56:00.783274 ==
3625 11:56:00.792763 TX Vref=22, minBit 1, minWin=25, winSum=417
3626 11:56:00.796393 TX Vref=24, minBit 2, minWin=25, winSum=423
3627 11:56:00.799499 TX Vref=26, minBit 2, minWin=25, winSum=426
3628 11:56:00.803152 TX Vref=28, minBit 1, minWin=25, winSum=432
3629 11:56:00.806546 TX Vref=30, minBit 15, minWin=26, winSum=433
3630 11:56:00.809352 TX Vref=32, minBit 0, minWin=27, winSum=435
3631 11:56:00.816247 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 32
3632 11:56:00.816794
3633 11:56:00.819201 Final TX Range 1 Vref 32
3634 11:56:00.819660
3635 11:56:00.820015 ==
3636 11:56:00.822571 Dram Type= 6, Freq= 0, CH_1, rank 1
3637 11:56:00.826156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3638 11:56:00.826705 ==
3639 11:56:00.827169
3640 11:56:00.829289
3641 11:56:00.829742 TX Vref Scan disable
3642 11:56:00.832809 == TX Byte 0 ==
3643 11:56:00.836300 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3644 11:56:00.839270 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3645 11:56:00.842724 == TX Byte 1 ==
3646 11:56:00.846178 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3647 11:56:00.849563 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3648 11:56:00.850138
3649 11:56:00.852789 [DATLAT]
3650 11:56:00.853245 Freq=1200, CH1 RK1
3651 11:56:00.853636
3652 11:56:00.856264 DATLAT Default: 0xd
3653 11:56:00.856811 0, 0xFFFF, sum = 0
3654 11:56:00.859408 1, 0xFFFF, sum = 0
3655 11:56:00.859872 2, 0xFFFF, sum = 0
3656 11:56:00.862935 3, 0xFFFF, sum = 0
3657 11:56:00.863490 4, 0xFFFF, sum = 0
3658 11:56:00.866013 5, 0xFFFF, sum = 0
3659 11:56:00.866479 6, 0xFFFF, sum = 0
3660 11:56:00.869401 7, 0xFFFF, sum = 0
3661 11:56:00.869823 8, 0xFFFF, sum = 0
3662 11:56:00.872609 9, 0xFFFF, sum = 0
3663 11:56:00.875963 10, 0xFFFF, sum = 0
3664 11:56:00.876383 11, 0xFFFF, sum = 0
3665 11:56:00.879446 12, 0x0, sum = 1
3666 11:56:00.879866 13, 0x0, sum = 2
3667 11:56:00.880200 14, 0x0, sum = 3
3668 11:56:00.882998 15, 0x0, sum = 4
3669 11:56:00.883511 best_step = 13
3670 11:56:00.883938
3671 11:56:00.884260 ==
3672 11:56:00.886021 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 11:56:00.892872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 11:56:00.893382 ==
3675 11:56:00.893710 RX Vref Scan: 0
3676 11:56:00.894014
3677 11:56:00.896543 RX Vref 0 -> 0, step: 1
3678 11:56:00.897048
3679 11:56:00.899622 RX Delay -21 -> 252, step: 4
3680 11:56:00.903047 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3681 11:56:00.906702 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3682 11:56:00.913311 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3683 11:56:00.916265 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3684 11:56:00.919542 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3685 11:56:00.922937 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3686 11:56:00.926592 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3687 11:56:00.933480 iDelay=191, Bit 7, Center 112 (47 ~ 178) 132
3688 11:56:00.936254 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3689 11:56:00.939534 iDelay=191, Bit 9, Center 96 (31 ~ 162) 132
3690 11:56:00.942816 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3691 11:56:00.946129 iDelay=191, Bit 11, Center 104 (39 ~ 170) 132
3692 11:56:00.952602 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3693 11:56:00.956337 iDelay=191, Bit 13, Center 120 (55 ~ 186) 132
3694 11:56:00.960087 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3695 11:56:00.963093 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3696 11:56:00.963639 ==
3697 11:56:00.966296 Dram Type= 6, Freq= 0, CH_1, rank 1
3698 11:56:00.969678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3699 11:56:00.972956 ==
3700 11:56:00.973413 DQS Delay:
3701 11:56:00.973771 DQS0 = 0, DQS1 = 0
3702 11:56:00.976403 DQM Delay:
3703 11:56:00.976949 DQM0 = 113, DQM1 = 109
3704 11:56:00.980312 DQ Delay:
3705 11:56:00.983042 DQ0 =112, DQ1 =110, DQ2 =104, DQ3 =112
3706 11:56:00.986429 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3707 11:56:00.989991 DQ8 =96, DQ9 =96, DQ10 =110, DQ11 =104
3708 11:56:00.993464 DQ12 =114, DQ13 =120, DQ14 =118, DQ15 =118
3709 11:56:00.994058
3710 11:56:00.994538
3711 11:56:00.999619 [DQSOSCAuto] RK1, (LSB)MR18= 0xf900, (MSB)MR19= 0x304, tDQSOscB0 = 410 ps tDQSOscB1 = 412 ps
3712 11:56:01.003088 CH1 RK1: MR19=304, MR18=F900
3713 11:56:01.009821 CH1_RK1: MR19=0x304, MR18=0xF900, DQSOSC=410, MR23=63, INC=39, DEC=26
3714 11:56:01.013006 [RxdqsGatingPostProcess] freq 1200
3715 11:56:01.019842 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3716 11:56:01.023041 best DQS0 dly(2T, 0.5T) = (0, 11)
3717 11:56:01.023635 best DQS1 dly(2T, 0.5T) = (0, 11)
3718 11:56:01.026576 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3719 11:56:01.029503 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3720 11:56:01.032858 best DQS0 dly(2T, 0.5T) = (0, 11)
3721 11:56:01.036265 best DQS1 dly(2T, 0.5T) = (0, 11)
3722 11:56:01.039758 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3723 11:56:01.042629 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3724 11:56:01.046028 Pre-setting of DQS Precalculation
3725 11:56:01.052546 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3726 11:56:01.059891 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3727 11:56:01.066432 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3728 11:56:01.067044
3729 11:56:01.067416
3730 11:56:01.069593 [Calibration Summary] 2400 Mbps
3731 11:56:01.070050 CH 0, Rank 0
3732 11:56:01.073304 SW Impedance : PASS
3733 11:56:01.073761 DUTY Scan : NO K
3734 11:56:01.076518 ZQ Calibration : PASS
3735 11:56:01.079548 Jitter Meter : NO K
3736 11:56:01.079965 CBT Training : PASS
3737 11:56:01.082995 Write leveling : PASS
3738 11:56:01.086445 RX DQS gating : PASS
3739 11:56:01.087014 RX DQ/DQS(RDDQC) : PASS
3740 11:56:01.090127 TX DQ/DQS : PASS
3741 11:56:01.093348 RX DATLAT : PASS
3742 11:56:01.093874 RX DQ/DQS(Engine): PASS
3743 11:56:01.096341 TX OE : NO K
3744 11:56:01.096853 All Pass.
3745 11:56:01.097184
3746 11:56:01.099479 CH 0, Rank 1
3747 11:56:01.099984 SW Impedance : PASS
3748 11:56:01.103255 DUTY Scan : NO K
3749 11:56:01.106742 ZQ Calibration : PASS
3750 11:56:01.107349 Jitter Meter : NO K
3751 11:56:01.110213 CBT Training : PASS
3752 11:56:01.110715 Write leveling : PASS
3753 11:56:01.113400 RX DQS gating : PASS
3754 11:56:01.116762 RX DQ/DQS(RDDQC) : PASS
3755 11:56:01.117267 TX DQ/DQS : PASS
3756 11:56:01.120537 RX DATLAT : PASS
3757 11:56:01.123497 RX DQ/DQS(Engine): PASS
3758 11:56:01.124016 TX OE : NO K
3759 11:56:01.126828 All Pass.
3760 11:56:01.127381
3761 11:56:01.127712 CH 1, Rank 0
3762 11:56:01.129976 SW Impedance : PASS
3763 11:56:01.130390 DUTY Scan : NO K
3764 11:56:01.133747 ZQ Calibration : PASS
3765 11:56:01.136504 Jitter Meter : NO K
3766 11:56:01.136914 CBT Training : PASS
3767 11:56:01.139818 Write leveling : PASS
3768 11:56:01.140225 RX DQS gating : PASS
3769 11:56:01.143176 RX DQ/DQS(RDDQC) : PASS
3770 11:56:01.146954 TX DQ/DQS : PASS
3771 11:56:01.147531 RX DATLAT : PASS
3772 11:56:01.150233 RX DQ/DQS(Engine): PASS
3773 11:56:01.153023 TX OE : NO K
3774 11:56:01.153493 All Pass.
3775 11:56:01.153928
3776 11:56:01.154337 CH 1, Rank 1
3777 11:56:01.156575 SW Impedance : PASS
3778 11:56:01.160133 DUTY Scan : NO K
3779 11:56:01.160553 ZQ Calibration : PASS
3780 11:56:01.163844 Jitter Meter : NO K
3781 11:56:01.167081 CBT Training : PASS
3782 11:56:01.167597 Write leveling : PASS
3783 11:56:01.170164 RX DQS gating : PASS
3784 11:56:01.173361 RX DQ/DQS(RDDQC) : PASS
3785 11:56:01.173782 TX DQ/DQS : PASS
3786 11:56:01.176985 RX DATLAT : PASS
3787 11:56:01.177514 RX DQ/DQS(Engine): PASS
3788 11:56:01.180373 TX OE : NO K
3789 11:56:01.180797 All Pass.
3790 11:56:01.181226
3791 11:56:01.183646 DramC Write-DBI off
3792 11:56:01.187091 PER_BANK_REFRESH: Hybrid Mode
3793 11:56:01.187618 TX_TRACKING: ON
3794 11:56:01.196901 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3795 11:56:01.200093 [FAST_K] Save calibration result to emmc
3796 11:56:01.203618 dramc_set_vcore_voltage set vcore to 650000
3797 11:56:01.206899 Read voltage for 600, 5
3798 11:56:01.207437 Vio18 = 0
3799 11:56:01.210825 Vcore = 650000
3800 11:56:01.211428 Vdram = 0
3801 11:56:01.211762 Vddq = 0
3802 11:56:01.212067 Vmddr = 0
3803 11:56:01.216946 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3804 11:56:01.220614 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3805 11:56:01.223621 MEM_TYPE=3, freq_sel=19
3806 11:56:01.227419 sv_algorithm_assistance_LP4_1600
3807 11:56:01.230654 ============ PULL DRAM RESETB DOWN ============
3808 11:56:01.233480 ========== PULL DRAM RESETB DOWN end =========
3809 11:56:01.240135 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3810 11:56:01.243742 ===================================
3811 11:56:01.247036 LPDDR4 DRAM CONFIGURATION
3812 11:56:01.250431 ===================================
3813 11:56:01.251057 EX_ROW_EN[0] = 0x0
3814 11:56:01.253585 EX_ROW_EN[1] = 0x0
3815 11:56:01.254133 LP4Y_EN = 0x0
3816 11:56:01.257034 WORK_FSP = 0x0
3817 11:56:01.257587 WL = 0x2
3818 11:56:01.260612 RL = 0x2
3819 11:56:01.261067 BL = 0x2
3820 11:56:01.263845 RPST = 0x0
3821 11:56:01.264391 RD_PRE = 0x0
3822 11:56:01.267235 WR_PRE = 0x1
3823 11:56:01.267688 WR_PST = 0x0
3824 11:56:01.270544 DBI_WR = 0x0
3825 11:56:01.271207 DBI_RD = 0x0
3826 11:56:01.273672 OTF = 0x1
3827 11:56:01.277280 ===================================
3828 11:56:01.280648 ===================================
3829 11:56:01.281202 ANA top config
3830 11:56:01.284506 ===================================
3831 11:56:01.287374 DLL_ASYNC_EN = 0
3832 11:56:01.291069 ALL_SLAVE_EN = 1
3833 11:56:01.293866 NEW_RANK_MODE = 1
3834 11:56:01.294345 DLL_IDLE_MODE = 1
3835 11:56:01.297501 LP45_APHY_COMB_EN = 1
3836 11:56:01.300896 TX_ODT_DIS = 1
3837 11:56:01.303709 NEW_8X_MODE = 1
3838 11:56:01.307410 ===================================
3839 11:56:01.310988 ===================================
3840 11:56:01.311550 data_rate = 1200
3841 11:56:01.314233 CKR = 1
3842 11:56:01.317736 DQ_P2S_RATIO = 8
3843 11:56:01.321036 ===================================
3844 11:56:01.323852 CA_P2S_RATIO = 8
3845 11:56:01.327277 DQ_CA_OPEN = 0
3846 11:56:01.330932 DQ_SEMI_OPEN = 0
3847 11:56:01.331479 CA_SEMI_OPEN = 0
3848 11:56:01.334000 CA_FULL_RATE = 0
3849 11:56:01.337352 DQ_CKDIV4_EN = 1
3850 11:56:01.341152 CA_CKDIV4_EN = 1
3851 11:56:01.343876 CA_PREDIV_EN = 0
3852 11:56:01.347421 PH8_DLY = 0
3853 11:56:01.347973 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3854 11:56:01.350808 DQ_AAMCK_DIV = 4
3855 11:56:01.354190 CA_AAMCK_DIV = 4
3856 11:56:01.357675 CA_ADMCK_DIV = 4
3857 11:56:01.361468 DQ_TRACK_CA_EN = 0
3858 11:56:01.364523 CA_PICK = 600
3859 11:56:01.365091 CA_MCKIO = 600
3860 11:56:01.367618 MCKIO_SEMI = 0
3861 11:56:01.370608 PLL_FREQ = 2288
3862 11:56:01.374086 DQ_UI_PI_RATIO = 32
3863 11:56:01.377700 CA_UI_PI_RATIO = 0
3864 11:56:01.381472 ===================================
3865 11:56:01.384670 ===================================
3866 11:56:01.385310 memory_type:LPDDR4
3867 11:56:01.387875 GP_NUM : 10
3868 11:56:01.391345 SRAM_EN : 1
3869 11:56:01.391960 MD32_EN : 0
3870 11:56:01.394361 ===================================
3871 11:56:01.397815 [ANA_INIT] >>>>>>>>>>>>>>
3872 11:56:01.401387 <<<<<< [CONFIGURE PHASE]: ANA_TX
3873 11:56:01.404336 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3874 11:56:01.407668 ===================================
3875 11:56:01.410786 data_rate = 1200,PCW = 0X5800
3876 11:56:01.414331 ===================================
3877 11:56:01.417829 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3878 11:56:01.420781 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 11:56:01.427547 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 11:56:01.431152 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3881 11:56:01.434542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3882 11:56:01.437597 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3883 11:56:01.440831 [ANA_INIT] flow start
3884 11:56:01.444300 [ANA_INIT] PLL >>>>>>>>
3885 11:56:01.444777 [ANA_INIT] PLL <<<<<<<<
3886 11:56:01.447748 [ANA_INIT] MIDPI >>>>>>>>
3887 11:56:01.451063 [ANA_INIT] MIDPI <<<<<<<<
3888 11:56:01.454357 [ANA_INIT] DLL >>>>>>>>
3889 11:56:01.454799 [ANA_INIT] flow end
3890 11:56:01.457873 ============ LP4 DIFF to SE enter ============
3891 11:56:01.464214 ============ LP4 DIFF to SE exit ============
3892 11:56:01.464630 [ANA_INIT] <<<<<<<<<<<<<
3893 11:56:01.467345 [Flow] Enable top DCM control >>>>>
3894 11:56:01.471039 [Flow] Enable top DCM control <<<<<
3895 11:56:01.473931 Enable DLL master slave shuffle
3896 11:56:01.481123 ==============================================================
3897 11:56:01.481540 Gating Mode config
3898 11:56:01.488173 ==============================================================
3899 11:56:01.488598 Config description:
3900 11:56:01.497637 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3901 11:56:01.504998 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3902 11:56:01.511297 SELPH_MODE 0: By rank 1: By Phase
3903 11:56:01.514447 ==============================================================
3904 11:56:01.517859 GAT_TRACK_EN = 1
3905 11:56:01.521305 RX_GATING_MODE = 2
3906 11:56:01.524540 RX_GATING_TRACK_MODE = 2
3907 11:56:01.528026 SELPH_MODE = 1
3908 11:56:01.531388 PICG_EARLY_EN = 1
3909 11:56:01.534810 VALID_LAT_VALUE = 1
3910 11:56:01.541065 ==============================================================
3911 11:56:01.545116 Enter into Gating configuration >>>>
3912 11:56:01.545568 Exit from Gating configuration <<<<
3913 11:56:01.548125 Enter into DVFS_PRE_config >>>>>
3914 11:56:01.561215 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3915 11:56:01.565122 Exit from DVFS_PRE_config <<<<<
3916 11:56:01.567932 Enter into PICG configuration >>>>
3917 11:56:01.568343 Exit from PICG configuration <<<<
3918 11:56:01.571240 [RX_INPUT] configuration >>>>>
3919 11:56:01.574424 [RX_INPUT] configuration <<<<<
3920 11:56:01.581706 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3921 11:56:01.584767 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3922 11:56:01.591302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3923 11:56:01.597913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3924 11:56:01.604843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3925 11:56:01.611484 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3926 11:56:01.614716 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3927 11:56:01.618134 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3928 11:56:01.621438 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3929 11:56:01.628011 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3930 11:56:01.631533 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3931 11:56:01.634760 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3932 11:56:01.638144 ===================================
3933 11:56:01.641755 LPDDR4 DRAM CONFIGURATION
3934 11:56:01.644644 ===================================
3935 11:56:01.648101 EX_ROW_EN[0] = 0x0
3936 11:56:01.648510 EX_ROW_EN[1] = 0x0
3937 11:56:01.651565 LP4Y_EN = 0x0
3938 11:56:01.651972 WORK_FSP = 0x0
3939 11:56:01.655234 WL = 0x2
3940 11:56:01.655742 RL = 0x2
3941 11:56:01.658244 BL = 0x2
3942 11:56:01.658751 RPST = 0x0
3943 11:56:01.661925 RD_PRE = 0x0
3944 11:56:01.662475 WR_PRE = 0x1
3945 11:56:01.665138 WR_PST = 0x0
3946 11:56:01.665546 DBI_WR = 0x0
3947 11:56:01.668436 DBI_RD = 0x0
3948 11:56:01.668988 OTF = 0x1
3949 11:56:01.671685 ===================================
3950 11:56:01.674589 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3951 11:56:01.681775 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3952 11:56:01.684912 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3953 11:56:01.688223 ===================================
3954 11:56:01.691563 LPDDR4 DRAM CONFIGURATION
3955 11:56:01.695013 ===================================
3956 11:56:01.695562 EX_ROW_EN[0] = 0x10
3957 11:56:01.698310 EX_ROW_EN[1] = 0x0
3958 11:56:01.698855 LP4Y_EN = 0x0
3959 11:56:01.701568 WORK_FSP = 0x0
3960 11:56:01.705041 WL = 0x2
3961 11:56:01.705562 RL = 0x2
3962 11:56:01.708155 BL = 0x2
3963 11:56:01.708608 RPST = 0x0
3964 11:56:01.711718 RD_PRE = 0x0
3965 11:56:01.712128 WR_PRE = 0x1
3966 11:56:01.715063 WR_PST = 0x0
3967 11:56:01.715545 DBI_WR = 0x0
3968 11:56:01.718512 DBI_RD = 0x0
3969 11:56:01.719194 OTF = 0x1
3970 11:56:01.721649 ===================================
3971 11:56:01.727928 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3972 11:56:01.731873 nWR fixed to 30
3973 11:56:01.735600 [ModeRegInit_LP4] CH0 RK0
3974 11:56:01.736108 [ModeRegInit_LP4] CH0 RK1
3975 11:56:01.738361 [ModeRegInit_LP4] CH1 RK0
3976 11:56:01.741631 [ModeRegInit_LP4] CH1 RK1
3977 11:56:01.742045 match AC timing 17
3978 11:56:01.748534 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3979 11:56:01.751833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3980 11:56:01.755434 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3981 11:56:01.762085 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3982 11:56:01.765599 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3983 11:56:01.766008 ==
3984 11:56:01.769080 Dram Type= 6, Freq= 0, CH_0, rank 0
3985 11:56:01.772196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 11:56:01.772607 ==
3987 11:56:01.779162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 11:56:01.785687 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3989 11:56:01.788956 [CA 0] Center 36 (6~66) winsize 61
3990 11:56:01.792778 [CA 1] Center 36 (6~66) winsize 61
3991 11:56:01.795809 [CA 2] Center 34 (4~65) winsize 62
3992 11:56:01.799342 [CA 3] Center 34 (4~65) winsize 62
3993 11:56:01.803037 [CA 4] Center 34 (4~64) winsize 61
3994 11:56:01.806035 [CA 5] Center 33 (3~64) winsize 62
3995 11:56:01.806446
3996 11:56:01.809238 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3997 11:56:01.809757
3998 11:56:01.812514 [CATrainingPosCal] consider 1 rank data
3999 11:56:01.816157 u2DelayCellTimex100 = 270/100 ps
4000 11:56:01.819335 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4001 11:56:01.823149 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4002 11:56:01.826124 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 11:56:01.829291 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 11:56:01.833035 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 11:56:01.835820 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 11:56:01.836232
4007 11:56:01.839681 CA PerBit enable=1, Macro0, CA PI delay=33
4008 11:56:01.840201
4009 11:56:01.842829 [CBTSetCACLKResult] CA Dly = 33
4010 11:56:01.845887 CS Dly: 4 (0~35)
4011 11:56:01.846402 ==
4012 11:56:01.848872 Dram Type= 6, Freq= 0, CH_0, rank 1
4013 11:56:01.852890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4014 11:56:01.853408 ==
4015 11:56:01.859507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4016 11:56:01.866348 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4017 11:56:01.869481 [CA 0] Center 36 (5~67) winsize 63
4018 11:56:01.872390 [CA 1] Center 35 (5~66) winsize 62
4019 11:56:01.875868 [CA 2] Center 34 (4~65) winsize 62
4020 11:56:01.879027 [CA 3] Center 34 (4~64) winsize 61
4021 11:56:01.882645 [CA 4] Center 33 (3~64) winsize 62
4022 11:56:01.885590 [CA 5] Center 33 (3~64) winsize 62
4023 11:56:01.886101
4024 11:56:01.889154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4025 11:56:01.889670
4026 11:56:01.892504 [CATrainingPosCal] consider 2 rank data
4027 11:56:01.895559 u2DelayCellTimex100 = 270/100 ps
4028 11:56:01.898838 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4029 11:56:01.902381 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4030 11:56:01.905711 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4031 11:56:01.909204 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4032 11:56:01.912200 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4033 11:56:01.915993 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 11:56:01.916508
4035 11:56:01.918970 CA PerBit enable=1, Macro0, CA PI delay=33
4036 11:56:01.922553
4037 11:56:01.923105 [CBTSetCACLKResult] CA Dly = 33
4038 11:56:01.925744 CS Dly: 5 (0~37)
4039 11:56:01.926252
4040 11:56:01.929085 ----->DramcWriteLeveling(PI) begin...
4041 11:56:01.929565 ==
4042 11:56:01.932798 Dram Type= 6, Freq= 0, CH_0, rank 0
4043 11:56:01.935899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4044 11:56:01.936418 ==
4045 11:56:01.939398 Write leveling (Byte 0): 31 => 31
4046 11:56:01.942474 Write leveling (Byte 1): 30 => 30
4047 11:56:01.946014 DramcWriteLeveling(PI) end<-----
4048 11:56:01.946533
4049 11:56:01.946858 ==
4050 11:56:01.949250 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 11:56:01.952820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 11:56:01.953336 ==
4053 11:56:01.956132 [Gating] SW mode calibration
4054 11:56:01.962705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4055 11:56:01.969613 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4056 11:56:01.972688 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 11:56:01.976175 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 11:56:01.983128 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 11:56:01.986184 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
4060 11:56:01.989949 0 9 16 | B1->B0 | 3232 2828 | 1 0 | (1 0) (0 1)
4061 11:56:01.996048 0 9 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4062 11:56:01.999852 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 11:56:02.002845 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 11:56:02.009941 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:56:02.012829 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:56:02.016068 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:56:02.023028 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:56:02.026186 0 10 16 | B1->B0 | 2c2c 3b3b | 0 0 | (0 0) (0 0)
4069 11:56:02.029330 0 10 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4070 11:56:02.036272 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:56:02.040154 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:56:02.042783 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:56:02.049318 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:56:02.053326 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:56:02.056419 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:56:02.059687 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4077 11:56:02.065927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4078 11:56:02.069314 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:56:02.072784 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:56:02.079475 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:56:02.083107 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:56:02.086038 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:56:02.092983 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:56:02.096027 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:56:02.099382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:56:02.106225 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:56:02.109309 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:56:02.113072 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:56:02.119859 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:56:02.122936 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:56:02.126246 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:56:02.132719 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4093 11:56:02.136379 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4094 11:56:02.139532 Total UI for P1: 0, mck2ui 16
4095 11:56:02.142847 best dqsien dly found for B0: ( 0, 13, 16)
4096 11:56:02.146419 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4097 11:56:02.149666 Total UI for P1: 0, mck2ui 16
4098 11:56:02.152910 best dqsien dly found for B1: ( 0, 13, 18)
4099 11:56:02.156243 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4100 11:56:02.159540 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4101 11:56:02.159969
4102 11:56:02.162745 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4103 11:56:02.169492 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4104 11:56:02.169920 [Gating] SW calibration Done
4105 11:56:02.170356 ==
4106 11:56:02.172766 Dram Type= 6, Freq= 0, CH_0, rank 0
4107 11:56:02.179514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4108 11:56:02.179945 ==
4109 11:56:02.180383 RX Vref Scan: 0
4110 11:56:02.180793
4111 11:56:02.182653 RX Vref 0 -> 0, step: 1
4112 11:56:02.183135
4113 11:56:02.186271 RX Delay -230 -> 252, step: 16
4114 11:56:02.189518 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4115 11:56:02.192867 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4116 11:56:02.196778 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4117 11:56:02.203197 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4118 11:56:02.206204 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4119 11:56:02.209458 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4120 11:56:02.212913 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4121 11:56:02.216492 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4122 11:56:02.223077 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4123 11:56:02.226789 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4124 11:56:02.229681 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4125 11:56:02.232907 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4126 11:56:02.239704 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4127 11:56:02.242966 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4128 11:56:02.247027 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4129 11:56:02.250100 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4130 11:56:02.250616 ==
4131 11:56:02.253653 Dram Type= 6, Freq= 0, CH_0, rank 0
4132 11:56:02.260166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4133 11:56:02.260692 ==
4134 11:56:02.261026 DQS Delay:
4135 11:56:02.263214 DQS0 = 0, DQS1 = 0
4136 11:56:02.263626 DQM Delay:
4137 11:56:02.263952 DQM0 = 40, DQM1 = 32
4138 11:56:02.266937 DQ Delay:
4139 11:56:02.270033 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4140 11:56:02.272931 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4141 11:56:02.276579 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4142 11:56:02.279575 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =49
4143 11:56:02.279987
4144 11:56:02.280315
4145 11:56:02.280616 ==
4146 11:56:02.283220 Dram Type= 6, Freq= 0, CH_0, rank 0
4147 11:56:02.286715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4148 11:56:02.287299 ==
4149 11:56:02.287636
4150 11:56:02.287943
4151 11:56:02.289699 TX Vref Scan disable
4152 11:56:02.290213 == TX Byte 0 ==
4153 11:56:02.297088 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4154 11:56:02.300500 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4155 11:56:02.301023 == TX Byte 1 ==
4156 11:56:02.306600 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4157 11:56:02.310320 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4158 11:56:02.310840 ==
4159 11:56:02.313327 Dram Type= 6, Freq= 0, CH_0, rank 0
4160 11:56:02.316754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4161 11:56:02.317174 ==
4162 11:56:02.317500
4163 11:56:02.319728
4164 11:56:02.320164 TX Vref Scan disable
4165 11:56:02.323241 == TX Byte 0 ==
4166 11:56:02.326459 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4167 11:56:02.329739 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4168 11:56:02.333080 == TX Byte 1 ==
4169 11:56:02.336379 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4170 11:56:02.339841 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4171 11:56:02.343597
4172 11:56:02.344007 [DATLAT]
4173 11:56:02.344332 Freq=600, CH0 RK0
4174 11:56:02.344657
4175 11:56:02.346649 DATLAT Default: 0x9
4176 11:56:02.347163 0, 0xFFFF, sum = 0
4177 11:56:02.350244 1, 0xFFFF, sum = 0
4178 11:56:02.350762 2, 0xFFFF, sum = 0
4179 11:56:02.353328 3, 0xFFFF, sum = 0
4180 11:56:02.353866 4, 0xFFFF, sum = 0
4181 11:56:02.356850 5, 0xFFFF, sum = 0
4182 11:56:02.357269 6, 0xFFFF, sum = 0
4183 11:56:02.359811 7, 0xFFFF, sum = 0
4184 11:56:02.360228 8, 0x0, sum = 1
4185 11:56:02.363205 9, 0x0, sum = 2
4186 11:56:02.363620 10, 0x0, sum = 3
4187 11:56:02.366595 11, 0x0, sum = 4
4188 11:56:02.367047 best_step = 9
4189 11:56:02.367378
4190 11:56:02.367683 ==
4191 11:56:02.370145 Dram Type= 6, Freq= 0, CH_0, rank 0
4192 11:56:02.376780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4193 11:56:02.377307 ==
4194 11:56:02.377639 RX Vref Scan: 1
4195 11:56:02.377947
4196 11:56:02.379799 RX Vref 0 -> 0, step: 1
4197 11:56:02.380215
4198 11:56:02.383412 RX Delay -195 -> 252, step: 8
4199 11:56:02.383825
4200 11:56:02.387008 Set Vref, RX VrefLevel [Byte0]: 55
4201 11:56:02.390352 [Byte1]: 53
4202 11:56:02.390905
4203 11:56:02.393434 Final RX Vref Byte 0 = 55 to rank0
4204 11:56:02.396827 Final RX Vref Byte 1 = 53 to rank0
4205 11:56:02.399681 Final RX Vref Byte 0 = 55 to rank1
4206 11:56:02.403274 Final RX Vref Byte 1 = 53 to rank1==
4207 11:56:02.406884 Dram Type= 6, Freq= 0, CH_0, rank 0
4208 11:56:02.410200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 11:56:02.410836 ==
4210 11:56:02.413121 DQS Delay:
4211 11:56:02.413535 DQS0 = 0, DQS1 = 0
4212 11:56:02.413862 DQM Delay:
4213 11:56:02.416696 DQM0 = 41, DQM1 = 33
4214 11:56:02.417111 DQ Delay:
4215 11:56:02.419794 DQ0 =40, DQ1 =44, DQ2 =40, DQ3 =40
4216 11:56:02.423323 DQ4 =40, DQ5 =32, DQ6 =48, DQ7 =48
4217 11:56:02.426770 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4218 11:56:02.430331 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4219 11:56:02.430945
4220 11:56:02.431334
4221 11:56:02.439777 [DQSOSCAuto] RK0, (LSB)MR18= 0x3e1d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 398 ps
4222 11:56:02.440285 CH0 RK0: MR19=808, MR18=3E1D
4223 11:56:02.447209 CH0_RK0: MR19=0x808, MR18=0x3E1D, DQSOSC=398, MR23=63, INC=165, DEC=110
4224 11:56:02.447734
4225 11:56:02.449782 ----->DramcWriteLeveling(PI) begin...
4226 11:56:02.450197 ==
4227 11:56:02.453595 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 11:56:02.459756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:56:02.460172 ==
4230 11:56:02.464083 Write leveling (Byte 0): 31 => 31
4231 11:56:02.467478 Write leveling (Byte 1): 31 => 31
4232 11:56:02.467980 DramcWriteLeveling(PI) end<-----
4233 11:56:02.468425
4234 11:56:02.469815 ==
4235 11:56:02.473564 Dram Type= 6, Freq= 0, CH_0, rank 1
4236 11:56:02.476998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4237 11:56:02.477524 ==
4238 11:56:02.480255 [Gating] SW mode calibration
4239 11:56:02.487421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4240 11:56:02.490153 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4241 11:56:02.496972 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 11:56:02.500487 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 11:56:02.503598 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4244 11:56:02.510096 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
4245 11:56:02.513514 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
4246 11:56:02.516659 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:56:02.523609 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:56:02.526857 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:56:02.530200 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 11:56:02.533331 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:56:02.540043 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4252 11:56:02.543682 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4253 11:56:02.546974 0 10 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
4254 11:56:02.554128 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:56:02.557146 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:56:02.560479 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:56:02.567116 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:56:02.570464 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:56:02.573461 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4260 11:56:02.580627 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4261 11:56:02.583857 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4262 11:56:02.587380 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:56:02.594075 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:56:02.597612 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:56:02.601259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:56:02.604300 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:56:02.610799 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:56:02.614167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:56:02.617218 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:56:02.624379 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:56:02.627806 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:56:02.630997 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:56:02.637779 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:56:02.640911 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:56:02.643922 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 11:56:02.651061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4277 11:56:02.654435 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4278 11:56:02.657509 Total UI for P1: 0, mck2ui 16
4279 11:56:02.660941 best dqsien dly found for B0: ( 0, 13, 12)
4280 11:56:02.664782 Total UI for P1: 0, mck2ui 16
4281 11:56:02.667826 best dqsien dly found for B1: ( 0, 13, 12)
4282 11:56:02.670942 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4283 11:56:02.673934 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4284 11:56:02.674405
4285 11:56:02.677632 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4286 11:56:02.681030 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4287 11:56:02.684342 [Gating] SW calibration Done
4288 11:56:02.684813 ==
4289 11:56:02.688409 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 11:56:02.690937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 11:56:02.691447 ==
4292 11:56:02.694818 RX Vref Scan: 0
4293 11:56:02.695452
4294 11:56:02.695940 RX Vref 0 -> 0, step: 1
4295 11:56:02.697714
4296 11:56:02.698193 RX Delay -230 -> 252, step: 16
4297 11:56:02.704736 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4298 11:56:02.707846 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4299 11:56:02.710898 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4300 11:56:02.714811 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4301 11:56:02.717422 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4302 11:56:02.724488 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4303 11:56:02.727333 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4304 11:56:02.730621 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4305 11:56:02.734642 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4306 11:56:02.741134 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4307 11:56:02.744029 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4308 11:56:02.747453 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4309 11:56:02.750939 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4310 11:56:02.753895 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4311 11:56:02.761407 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4312 11:56:02.764629 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4313 11:56:02.764859 ==
4314 11:56:02.767948 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 11:56:02.771017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 11:56:02.771213 ==
4317 11:56:02.774120 DQS Delay:
4318 11:56:02.774368 DQS0 = 0, DQS1 = 0
4319 11:56:02.777576 DQM Delay:
4320 11:56:02.777803 DQM0 = 38, DQM1 = 33
4321 11:56:02.777932 DQ Delay:
4322 11:56:02.780895 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4323 11:56:02.784699 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4324 11:56:02.787487 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4325 11:56:02.790959 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4326 11:56:02.791405
4327 11:56:02.791705
4328 11:56:02.791979 ==
4329 11:56:02.794443 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 11:56:02.801406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 11:56:02.801822 ==
4332 11:56:02.802148
4333 11:56:02.802468
4334 11:56:02.802988 TX Vref Scan disable
4335 11:56:02.804848 == TX Byte 0 ==
4336 11:56:02.808072 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4337 11:56:02.815228 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4338 11:56:02.815668 == TX Byte 1 ==
4339 11:56:02.818010 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4340 11:56:02.821781 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4341 11:56:02.825037 ==
4342 11:56:02.828592 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 11:56:02.831710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 11:56:02.832139 ==
4345 11:56:02.832578
4346 11:56:02.832988
4347 11:56:02.834819 TX Vref Scan disable
4348 11:56:02.835319 == TX Byte 0 ==
4349 11:56:02.841636 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4350 11:56:02.845243 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4351 11:56:02.845677 == TX Byte 1 ==
4352 11:56:02.851348 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4353 11:56:02.854612 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4354 11:56:02.855079
4355 11:56:02.855516 [DATLAT]
4356 11:56:02.858363 Freq=600, CH0 RK1
4357 11:56:02.858790
4358 11:56:02.859262 DATLAT Default: 0x9
4359 11:56:02.861631 0, 0xFFFF, sum = 0
4360 11:56:02.862177 1, 0xFFFF, sum = 0
4361 11:56:02.864693 2, 0xFFFF, sum = 0
4362 11:56:02.865210 3, 0xFFFF, sum = 0
4363 11:56:02.868173 4, 0xFFFF, sum = 0
4364 11:56:02.871445 5, 0xFFFF, sum = 0
4365 11:56:02.871959 6, 0xFFFF, sum = 0
4366 11:56:02.875181 7, 0xFFFF, sum = 0
4367 11:56:02.875607 8, 0x0, sum = 1
4368 11:56:02.875926 9, 0x0, sum = 2
4369 11:56:02.877904 10, 0x0, sum = 3
4370 11:56:02.878262 11, 0x0, sum = 4
4371 11:56:02.881042 best_step = 9
4372 11:56:02.881307
4373 11:56:02.881546 ==
4374 11:56:02.884713 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 11:56:02.888245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:56:02.888423 ==
4377 11:56:02.891232 RX Vref Scan: 0
4378 11:56:02.891496
4379 11:56:02.891643 RX Vref 0 -> 0, step: 1
4380 11:56:02.891778
4381 11:56:02.894477 RX Delay -179 -> 252, step: 8
4382 11:56:02.901822 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4383 11:56:02.905319 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4384 11:56:02.908693 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4385 11:56:02.911666 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4386 11:56:02.918588 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4387 11:56:02.922575 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4388 11:56:02.925478 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4389 11:56:02.928764 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4390 11:56:02.931961 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4391 11:56:02.938272 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4392 11:56:02.941959 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4393 11:56:02.945352 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4394 11:56:02.948598 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4395 11:56:02.955548 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4396 11:56:02.958763 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4397 11:56:02.962255 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4398 11:56:02.962823 ==
4399 11:56:02.965569 Dram Type= 6, Freq= 0, CH_0, rank 1
4400 11:56:02.969174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 11:56:02.971931 ==
4402 11:56:02.972384 DQS Delay:
4403 11:56:02.972736 DQS0 = 0, DQS1 = 0
4404 11:56:02.975560 DQM Delay:
4405 11:56:02.976010 DQM0 = 39, DQM1 = 33
4406 11:56:02.978816 DQ Delay:
4407 11:56:02.979324 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4408 11:56:02.981857 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4409 11:56:02.985545 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4410 11:56:02.988198 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4411 11:56:02.988611
4412 11:56:02.991779
4413 11:56:02.998711 [DQSOSCAuto] RK1, (LSB)MR18= 0x4829, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4414 11:56:03.002013 CH0 RK1: MR19=808, MR18=4829
4415 11:56:03.008414 CH0_RK1: MR19=0x808, MR18=0x4829, DQSOSC=396, MR23=63, INC=167, DEC=111
4416 11:56:03.011561 [RxdqsGatingPostProcess] freq 600
4417 11:56:03.015267 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4418 11:56:03.018220 Pre-setting of DQS Precalculation
4419 11:56:03.025562 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4420 11:56:03.026107 ==
4421 11:56:03.028650 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 11:56:03.032047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 11:56:03.032502 ==
4424 11:56:03.035288 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 11:56:03.041832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4426 11:56:03.045543 [CA 0] Center 35 (5~66) winsize 62
4427 11:56:03.048871 [CA 1] Center 35 (5~66) winsize 62
4428 11:56:03.052228 [CA 2] Center 34 (4~64) winsize 61
4429 11:56:03.055352 [CA 3] Center 33 (3~64) winsize 62
4430 11:56:03.058592 [CA 4] Center 34 (3~65) winsize 63
4431 11:56:03.062600 [CA 5] Center 33 (3~64) winsize 62
4432 11:56:03.063249
4433 11:56:03.065191 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4434 11:56:03.065666
4435 11:56:03.068530 [CATrainingPosCal] consider 1 rank data
4436 11:56:03.071797 u2DelayCellTimex100 = 270/100 ps
4437 11:56:03.075527 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 11:56:03.078543 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 11:56:03.085465 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4440 11:56:03.088964 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 11:56:03.092017 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4442 11:56:03.095552 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4443 11:56:03.095961
4444 11:56:03.098841 CA PerBit enable=1, Macro0, CA PI delay=33
4445 11:56:03.099292
4446 11:56:03.102129 [CBTSetCACLKResult] CA Dly = 33
4447 11:56:03.102538 CS Dly: 4 (0~35)
4448 11:56:03.102897 ==
4449 11:56:03.105509 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 11:56:03.112164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 11:56:03.112577 ==
4452 11:56:03.115137 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4453 11:56:03.122083 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4454 11:56:03.125417 [CA 0] Center 35 (5~66) winsize 62
4455 11:56:03.128665 [CA 1] Center 36 (6~66) winsize 61
4456 11:56:03.132064 [CA 2] Center 34 (4~65) winsize 62
4457 11:56:03.135594 [CA 3] Center 33 (3~64) winsize 62
4458 11:56:03.138790 [CA 4] Center 34 (4~65) winsize 62
4459 11:56:03.142316 [CA 5] Center 33 (3~64) winsize 62
4460 11:56:03.142888
4461 11:56:03.146021 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4462 11:56:03.146524
4463 11:56:03.149061 [CATrainingPosCal] consider 2 rank data
4464 11:56:03.152418 u2DelayCellTimex100 = 270/100 ps
4465 11:56:03.155503 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 11:56:03.159141 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4467 11:56:03.165668 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4468 11:56:03.169120 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 11:56:03.172534 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4470 11:56:03.175805 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 11:56:03.176215
4472 11:56:03.179241 CA PerBit enable=1, Macro0, CA PI delay=33
4473 11:56:03.179709
4474 11:56:03.182535 [CBTSetCACLKResult] CA Dly = 33
4475 11:56:03.182985 CS Dly: 4 (0~36)
4476 11:56:03.183333
4477 11:56:03.185851 ----->DramcWriteLeveling(PI) begin...
4478 11:56:03.186265 ==
4479 11:56:03.189229 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 11:56:03.195896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 11:56:03.196390 ==
4482 11:56:03.199223 Write leveling (Byte 0): 28 => 28
4483 11:56:03.202913 Write leveling (Byte 1): 28 => 28
4484 11:56:03.203334 DramcWriteLeveling(PI) end<-----
4485 11:56:03.203661
4486 11:56:03.206131 ==
4487 11:56:03.209470 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 11:56:03.212694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 11:56:03.213227 ==
4490 11:56:03.216053 [Gating] SW mode calibration
4491 11:56:03.222966 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4492 11:56:03.225977 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4493 11:56:03.233159 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 11:56:03.236404 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 11:56:03.239474 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4496 11:56:03.246531 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (0 0) (0 0)
4497 11:56:03.249611 0 9 16 | B1->B0 | 2727 2525 | 0 0 | (1 1) (0 0)
4498 11:56:03.253203 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 11:56:03.256505 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 11:56:03.263169 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4501 11:56:03.266370 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:56:03.270347 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:56:03.276456 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:56:03.279650 0 10 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4505 11:56:03.283691 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4506 11:56:03.290181 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:56:03.293072 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 11:56:03.297024 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:56:03.303271 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:56:03.306436 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:56:03.309808 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:56:03.316712 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:56:03.319945 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4514 11:56:03.323425 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:56:03.329965 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:56:03.333202 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:56:03.335936 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:56:03.343340 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:56:03.346301 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:56:03.349698 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:56:03.352888 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:56:03.359707 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:56:03.362974 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:56:03.366549 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:56:03.373302 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:56:03.376502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:56:03.379809 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:56:03.386421 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4529 11:56:03.389920 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:56:03.392966 Total UI for P1: 0, mck2ui 16
4531 11:56:03.396698 best dqsien dly found for B0: ( 0, 13, 12)
4532 11:56:03.399799 Total UI for P1: 0, mck2ui 16
4533 11:56:03.403139 best dqsien dly found for B1: ( 0, 13, 14)
4534 11:56:03.406482 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4535 11:56:03.409347 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4536 11:56:03.409903
4537 11:56:03.413066 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4538 11:56:03.415944 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4539 11:56:03.419576 [Gating] SW calibration Done
4540 11:56:03.420049 ==
4541 11:56:03.422835 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 11:56:03.426133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 11:56:03.429936 ==
4544 11:56:03.430526 RX Vref Scan: 0
4545 11:56:03.431114
4546 11:56:03.433071 RX Vref 0 -> 0, step: 1
4547 11:56:03.433663
4548 11:56:03.436096 RX Delay -230 -> 252, step: 16
4549 11:56:03.439772 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4550 11:56:03.443322 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4551 11:56:03.446051 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4552 11:56:03.452760 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4553 11:56:03.456639 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4554 11:56:03.459560 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4555 11:56:03.462948 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4556 11:56:03.465991 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4557 11:56:03.472933 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4558 11:56:03.475942 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4559 11:56:03.479688 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4560 11:56:03.482728 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4561 11:56:03.489682 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4562 11:56:03.492965 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4563 11:56:03.496444 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4564 11:56:03.499706 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4565 11:56:03.500181 ==
4566 11:56:03.503133 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:56:03.509462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:56:03.510029 ==
4569 11:56:03.510522 DQS Delay:
4570 11:56:03.511108 DQS0 = 0, DQS1 = 0
4571 11:56:03.512942 DQM Delay:
4572 11:56:03.513417 DQM0 = 43, DQM1 = 36
4573 11:56:03.516333 DQ Delay:
4574 11:56:03.519586 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4575 11:56:03.520059 DQ4 =41, DQ5 =49, DQ6 =57, DQ7 =41
4576 11:56:03.523156 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4577 11:56:03.526916 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4578 11:56:03.529641
4579 11:56:03.530111
4580 11:56:03.530592 ==
4581 11:56:03.533438 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 11:56:03.536325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 11:56:03.536803 ==
4584 11:56:03.537287
4585 11:56:03.537741
4586 11:56:03.539950 TX Vref Scan disable
4587 11:56:03.540421 == TX Byte 0 ==
4588 11:56:03.546422 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4589 11:56:03.550056 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4590 11:56:03.550636 == TX Byte 1 ==
4591 11:56:03.556305 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4592 11:56:03.559865 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4593 11:56:03.560442 ==
4594 11:56:03.563042 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 11:56:03.566141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 11:56:03.566716 ==
4597 11:56:03.567251
4598 11:56:03.567708
4599 11:56:03.569349 TX Vref Scan disable
4600 11:56:03.572954 == TX Byte 0 ==
4601 11:56:03.576123 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4602 11:56:03.579555 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4603 11:56:03.582812 == TX Byte 1 ==
4604 11:56:03.586912 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4605 11:56:03.590212 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4606 11:56:03.590792
4607 11:56:03.592868 [DATLAT]
4608 11:56:03.593338 Freq=600, CH1 RK0
4609 11:56:03.593820
4610 11:56:03.596702 DATLAT Default: 0x9
4611 11:56:03.597280 0, 0xFFFF, sum = 0
4612 11:56:03.599921 1, 0xFFFF, sum = 0
4613 11:56:03.600507 2, 0xFFFF, sum = 0
4614 11:56:03.603134 3, 0xFFFF, sum = 0
4615 11:56:03.603691 4, 0xFFFF, sum = 0
4616 11:56:03.606378 5, 0xFFFF, sum = 0
4617 11:56:03.606969 6, 0xFFFF, sum = 0
4618 11:56:03.609685 7, 0xFFFF, sum = 0
4619 11:56:03.610289 8, 0x0, sum = 1
4620 11:56:03.613238 9, 0x0, sum = 2
4621 11:56:03.613793 10, 0x0, sum = 3
4622 11:56:03.616231 11, 0x0, sum = 4
4623 11:56:03.616687 best_step = 9
4624 11:56:03.617042
4625 11:56:03.617373 ==
4626 11:56:03.619806 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 11:56:03.623227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 11:56:03.626081 ==
4629 11:56:03.626535 RX Vref Scan: 1
4630 11:56:03.626931
4631 11:56:03.630098 RX Vref 0 -> 0, step: 1
4632 11:56:03.630638
4633 11:56:03.633054 RX Delay -195 -> 252, step: 8
4634 11:56:03.633604
4635 11:56:03.636178 Set Vref, RX VrefLevel [Byte0]: 56
4636 11:56:03.639304 [Byte1]: 53
4637 11:56:03.639779
4638 11:56:03.643032 Final RX Vref Byte 0 = 56 to rank0
4639 11:56:03.646108 Final RX Vref Byte 1 = 53 to rank0
4640 11:56:03.649390 Final RX Vref Byte 0 = 56 to rank1
4641 11:56:03.653169 Final RX Vref Byte 1 = 53 to rank1==
4642 11:56:03.655966 Dram Type= 6, Freq= 0, CH_1, rank 0
4643 11:56:03.659602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 11:56:03.660202 ==
4645 11:56:03.660693 DQS Delay:
4646 11:56:03.663050 DQS0 = 0, DQS1 = 0
4647 11:56:03.663623 DQM Delay:
4648 11:56:03.666790 DQM0 = 40, DQM1 = 32
4649 11:56:03.667423 DQ Delay:
4650 11:56:03.669661 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4651 11:56:03.673084 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4652 11:56:03.676473 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4653 11:56:03.679759 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4654 11:56:03.680232
4655 11:56:03.680712
4656 11:56:03.689847 [DQSOSCAuto] RK0, (LSB)MR18= 0x4208, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 397 ps
4657 11:56:03.690429 CH1 RK0: MR19=808, MR18=4208
4658 11:56:03.696405 CH1_RK0: MR19=0x808, MR18=0x4208, DQSOSC=397, MR23=63, INC=166, DEC=110
4659 11:56:03.696985
4660 11:56:03.699599 ----->DramcWriteLeveling(PI) begin...
4661 11:56:03.700081 ==
4662 11:56:03.702970 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:56:03.709862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:56:03.710445 ==
4665 11:56:03.713083 Write leveling (Byte 0): 29 => 29
4666 11:56:03.713672 Write leveling (Byte 1): 29 => 29
4667 11:56:03.716464 DramcWriteLeveling(PI) end<-----
4668 11:56:03.716937
4669 11:56:03.717420 ==
4670 11:56:03.719769 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 11:56:03.726925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 11:56:03.727514 ==
4673 11:56:03.729819 [Gating] SW mode calibration
4674 11:56:03.736334 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4675 11:56:03.740122 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4676 11:56:03.746949 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 11:56:03.750050 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4678 11:56:03.753414 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4679 11:56:03.756982 0 9 12 | B1->B0 | 3030 2c2c | 0 1 | (0 0) (1 0)
4680 11:56:03.763594 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 11:56:03.766795 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 11:56:03.770329 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 11:56:03.776734 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 11:56:03.780322 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 11:56:03.783846 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:56:03.790515 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4687 11:56:03.794130 0 10 12 | B1->B0 | 3030 4141 | 0 0 | (1 1) (0 0)
4688 11:56:03.797020 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4689 11:56:03.803681 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:56:03.806933 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 11:56:03.810384 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 11:56:03.813980 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:56:03.819913 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:56:03.823682 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4695 11:56:03.826841 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4696 11:56:03.833942 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4697 11:56:03.836984 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:56:03.840046 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:56:03.846927 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:56:03.850385 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:56:03.853705 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:56:03.860142 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:56:03.863341 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:56:03.866957 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:56:03.873719 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:56:03.877283 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:56:03.880506 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:56:03.886844 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:56:03.890618 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:56:03.893511 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:56:03.900154 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4712 11:56:03.903452 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4713 11:56:03.906960 Total UI for P1: 0, mck2ui 16
4714 11:56:03.910471 best dqsien dly found for B0: ( 0, 13, 12)
4715 11:56:03.913418 Total UI for P1: 0, mck2ui 16
4716 11:56:03.916971 best dqsien dly found for B1: ( 0, 13, 14)
4717 11:56:03.920234 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4718 11:56:03.923472 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4719 11:56:03.924049
4720 11:56:03.927230 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4721 11:56:03.930379 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4722 11:56:03.933706 [Gating] SW calibration Done
4723 11:56:03.934139 ==
4724 11:56:03.937204 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 11:56:03.939982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 11:56:03.940429 ==
4727 11:56:03.943460 RX Vref Scan: 0
4728 11:56:03.943889
4729 11:56:03.944330 RX Vref 0 -> 0, step: 1
4730 11:56:03.947151
4731 11:56:03.947580 RX Delay -230 -> 252, step: 16
4732 11:56:03.954071 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4733 11:56:03.957214 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4734 11:56:03.960352 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4735 11:56:03.964232 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4736 11:56:03.967243 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4737 11:56:03.974288 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4738 11:56:03.977317 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4739 11:56:03.980558 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4740 11:56:03.984005 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4741 11:56:03.987561 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4742 11:56:03.994656 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4743 11:56:03.997631 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4744 11:56:04.001256 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4745 11:56:04.004089 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4746 11:56:04.010751 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4747 11:56:04.014272 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4748 11:56:04.014851 ==
4749 11:56:04.017888 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:56:04.020917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:56:04.021394 ==
4752 11:56:04.023992 DQS Delay:
4753 11:56:04.024463 DQS0 = 0, DQS1 = 0
4754 11:56:04.024939 DQM Delay:
4755 11:56:04.027463 DQM0 = 40, DQM1 = 36
4756 11:56:04.027951 DQ Delay:
4757 11:56:04.031208 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4758 11:56:04.033970 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4759 11:56:04.037699 DQ8 =17, DQ9 =17, DQ10 =41, DQ11 =25
4760 11:56:04.040869 DQ12 =41, DQ13 =49, DQ14 =49, DQ15 =49
4761 11:56:04.041344
4762 11:56:04.041709
4763 11:56:04.042077 ==
4764 11:56:04.044148 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 11:56:04.050936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 11:56:04.051417 ==
4767 11:56:04.051779
4768 11:56:04.052112
4769 11:56:04.052433 TX Vref Scan disable
4770 11:56:04.054095 == TX Byte 0 ==
4771 11:56:04.057656 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4772 11:56:04.064669 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4773 11:56:04.065223 == TX Byte 1 ==
4774 11:56:04.067751 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4775 11:56:04.071312 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4776 11:56:04.074661 ==
4777 11:56:04.077729 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 11:56:04.080936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 11:56:04.081393 ==
4780 11:56:04.081756
4781 11:56:04.082090
4782 11:56:04.084531 TX Vref Scan disable
4783 11:56:04.085084 == TX Byte 0 ==
4784 11:56:04.091070 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4785 11:56:04.094427 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4786 11:56:04.094930 == TX Byte 1 ==
4787 11:56:04.101392 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4788 11:56:04.104359 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4789 11:56:04.104915
4790 11:56:04.105277 [DATLAT]
4791 11:56:04.107891 Freq=600, CH1 RK1
4792 11:56:04.108345
4793 11:56:04.108702 DATLAT Default: 0x9
4794 11:56:04.111028 0, 0xFFFF, sum = 0
4795 11:56:04.111493 1, 0xFFFF, sum = 0
4796 11:56:04.114442 2, 0xFFFF, sum = 0
4797 11:56:04.114937 3, 0xFFFF, sum = 0
4798 11:56:04.117905 4, 0xFFFF, sum = 0
4799 11:56:04.118466 5, 0xFFFF, sum = 0
4800 11:56:04.121386 6, 0xFFFF, sum = 0
4801 11:56:04.121850 7, 0xFFFF, sum = 0
4802 11:56:04.124691 8, 0x0, sum = 1
4803 11:56:04.125257 9, 0x0, sum = 2
4804 11:56:04.127996 10, 0x0, sum = 3
4805 11:56:04.128553 11, 0x0, sum = 4
4806 11:56:04.131545 best_step = 9
4807 11:56:04.132098
4808 11:56:04.132492 ==
4809 11:56:04.134993 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 11:56:04.137772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 11:56:04.138233 ==
4812 11:56:04.140996 RX Vref Scan: 0
4813 11:56:04.141447
4814 11:56:04.141807 RX Vref 0 -> 0, step: 1
4815 11:56:04.142140
4816 11:56:04.144724 RX Delay -195 -> 252, step: 8
4817 11:56:04.151201 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4818 11:56:04.154900 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4819 11:56:04.158296 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4820 11:56:04.161225 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4821 11:56:04.167953 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4822 11:56:04.171444 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4823 11:56:04.174953 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4824 11:56:04.178080 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4825 11:56:04.181107 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4826 11:56:04.188189 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4827 11:56:04.191540 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4828 11:56:04.195502 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4829 11:56:04.198271 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4830 11:56:04.204963 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4831 11:56:04.208243 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4832 11:56:04.211594 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4833 11:56:04.212149 ==
4834 11:56:04.214785 Dram Type= 6, Freq= 0, CH_1, rank 1
4835 11:56:04.217868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4836 11:56:04.218419 ==
4837 11:56:04.221613 DQS Delay:
4838 11:56:04.222161 DQS0 = 0, DQS1 = 0
4839 11:56:04.224705 DQM Delay:
4840 11:56:04.225253 DQM0 = 39, DQM1 = 33
4841 11:56:04.225615 DQ Delay:
4842 11:56:04.228208 DQ0 =44, DQ1 =32, DQ2 =28, DQ3 =36
4843 11:56:04.231759 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4844 11:56:04.235064 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =24
4845 11:56:04.238065 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4846 11:56:04.238626
4847 11:56:04.239026
4848 11:56:04.248048 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a49, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
4849 11:56:04.251659 CH1 RK1: MR19=808, MR18=3A49
4850 11:56:04.258427 CH1_RK1: MR19=0x808, MR18=0x3A49, DQSOSC=396, MR23=63, INC=167, DEC=111
4851 11:56:04.259051 [RxdqsGatingPostProcess] freq 600
4852 11:56:04.264698 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4853 11:56:04.268588 Pre-setting of DQS Precalculation
4854 11:56:04.271499 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4855 11:56:04.281609 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4856 11:56:04.288049 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4857 11:56:04.288529
4858 11:56:04.289012
4859 11:56:04.291732 [Calibration Summary] 1200 Mbps
4860 11:56:04.292206 CH 0, Rank 0
4861 11:56:04.295024 SW Impedance : PASS
4862 11:56:04.295533 DUTY Scan : NO K
4863 11:56:04.298426 ZQ Calibration : PASS
4864 11:56:04.301622 Jitter Meter : NO K
4865 11:56:04.302196 CBT Training : PASS
4866 11:56:04.305108 Write leveling : PASS
4867 11:56:04.308184 RX DQS gating : PASS
4868 11:56:04.308659 RX DQ/DQS(RDDQC) : PASS
4869 11:56:04.311832 TX DQ/DQS : PASS
4870 11:56:04.312414 RX DATLAT : PASS
4871 11:56:04.315085 RX DQ/DQS(Engine): PASS
4872 11:56:04.318419 TX OE : NO K
4873 11:56:04.319012 All Pass.
4874 11:56:04.319377
4875 11:56:04.319709 CH 0, Rank 1
4876 11:56:04.321509 SW Impedance : PASS
4877 11:56:04.325059 DUTY Scan : NO K
4878 11:56:04.325606 ZQ Calibration : PASS
4879 11:56:04.328511 Jitter Meter : NO K
4880 11:56:04.331813 CBT Training : PASS
4881 11:56:04.332365 Write leveling : PASS
4882 11:56:04.334998 RX DQS gating : PASS
4883 11:56:04.338685 RX DQ/DQS(RDDQC) : PASS
4884 11:56:04.339304 TX DQ/DQS : PASS
4885 11:56:04.341771 RX DATLAT : PASS
4886 11:56:04.344912 RX DQ/DQS(Engine): PASS
4887 11:56:04.345362 TX OE : NO K
4888 11:56:04.345719 All Pass.
4889 11:56:04.348045
4890 11:56:04.348496 CH 1, Rank 0
4891 11:56:04.351674 SW Impedance : PASS
4892 11:56:04.352127 DUTY Scan : NO K
4893 11:56:04.354994 ZQ Calibration : PASS
4894 11:56:04.355445 Jitter Meter : NO K
4895 11:56:04.358328 CBT Training : PASS
4896 11:56:04.361445 Write leveling : PASS
4897 11:56:04.361918 RX DQS gating : PASS
4898 11:56:04.365139 RX DQ/DQS(RDDQC) : PASS
4899 11:56:04.368115 TX DQ/DQS : PASS
4900 11:56:04.368590 RX DATLAT : PASS
4901 11:56:04.371641 RX DQ/DQS(Engine): PASS
4902 11:56:04.374839 TX OE : NO K
4903 11:56:04.375346 All Pass.
4904 11:56:04.375823
4905 11:56:04.376273 CH 1, Rank 1
4906 11:56:04.378485 SW Impedance : PASS
4907 11:56:04.381424 DUTY Scan : NO K
4908 11:56:04.381834 ZQ Calibration : PASS
4909 11:56:04.384474 Jitter Meter : NO K
4910 11:56:04.388692 CBT Training : PASS
4911 11:56:04.389372 Write leveling : PASS
4912 11:56:04.391511 RX DQS gating : PASS
4913 11:56:04.394999 RX DQ/DQS(RDDQC) : PASS
4914 11:56:04.395539 TX DQ/DQS : PASS
4915 11:56:04.398805 RX DATLAT : PASS
4916 11:56:04.399403 RX DQ/DQS(Engine): PASS
4917 11:56:04.401872 TX OE : NO K
4918 11:56:04.402427 All Pass.
4919 11:56:04.403080
4920 11:56:04.404761 DramC Write-DBI off
4921 11:56:04.408611 PER_BANK_REFRESH: Hybrid Mode
4922 11:56:04.409158 TX_TRACKING: ON
4923 11:56:04.418522 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4924 11:56:04.421840 [FAST_K] Save calibration result to emmc
4925 11:56:04.425212 dramc_set_vcore_voltage set vcore to 662500
4926 11:56:04.428457 Read voltage for 933, 3
4927 11:56:04.429008 Vio18 = 0
4928 11:56:04.429367 Vcore = 662500
4929 11:56:04.432233 Vdram = 0
4930 11:56:04.432782 Vddq = 0
4931 11:56:04.433138 Vmddr = 0
4932 11:56:04.438653 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4933 11:56:04.441654 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4934 11:56:04.444854 MEM_TYPE=3, freq_sel=17
4935 11:56:04.448232 sv_algorithm_assistance_LP4_1600
4936 11:56:04.451663 ============ PULL DRAM RESETB DOWN ============
4937 11:56:04.455105 ========== PULL DRAM RESETB DOWN end =========
4938 11:56:04.461913 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4939 11:56:04.464986 ===================================
4940 11:56:04.468709 LPDDR4 DRAM CONFIGURATION
4941 11:56:04.469256 ===================================
4942 11:56:04.471487 EX_ROW_EN[0] = 0x0
4943 11:56:04.475129 EX_ROW_EN[1] = 0x0
4944 11:56:04.475594 LP4Y_EN = 0x0
4945 11:56:04.478222 WORK_FSP = 0x0
4946 11:56:04.478675 WL = 0x3
4947 11:56:04.481524 RL = 0x3
4948 11:56:04.481907 BL = 0x2
4949 11:56:04.484944 RPST = 0x0
4950 11:56:04.485414 RD_PRE = 0x0
4951 11:56:04.488358 WR_PRE = 0x1
4952 11:56:04.488806 WR_PST = 0x0
4953 11:56:04.492111 DBI_WR = 0x0
4954 11:56:04.492605 DBI_RD = 0x0
4955 11:56:04.494993 OTF = 0x1
4956 11:56:04.498568 ===================================
4957 11:56:04.501985 ===================================
4958 11:56:04.502490 ANA top config
4959 11:56:04.505361 ===================================
4960 11:56:04.508538 DLL_ASYNC_EN = 0
4961 11:56:04.511504 ALL_SLAVE_EN = 1
4962 11:56:04.515074 NEW_RANK_MODE = 1
4963 11:56:04.515589 DLL_IDLE_MODE = 1
4964 11:56:04.518479 LP45_APHY_COMB_EN = 1
4965 11:56:04.521811 TX_ODT_DIS = 1
4966 11:56:04.525428 NEW_8X_MODE = 1
4967 11:56:04.528410 ===================================
4968 11:56:04.531540 ===================================
4969 11:56:04.535028 data_rate = 1866
4970 11:56:04.535540 CKR = 1
4971 11:56:04.538310 DQ_P2S_RATIO = 8
4972 11:56:04.541947 ===================================
4973 11:56:04.545271 CA_P2S_RATIO = 8
4974 11:56:04.548426 DQ_CA_OPEN = 0
4975 11:56:04.551615 DQ_SEMI_OPEN = 0
4976 11:56:04.552052 CA_SEMI_OPEN = 0
4977 11:56:04.555300 CA_FULL_RATE = 0
4978 11:56:04.558145 DQ_CKDIV4_EN = 1
4979 11:56:04.561787 CA_CKDIV4_EN = 1
4980 11:56:04.565411 CA_PREDIV_EN = 0
4981 11:56:04.568261 PH8_DLY = 0
4982 11:56:04.568672 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4983 11:56:04.571725 DQ_AAMCK_DIV = 4
4984 11:56:04.575483 CA_AAMCK_DIV = 4
4985 11:56:04.578542 CA_ADMCK_DIV = 4
4986 11:56:04.581745 DQ_TRACK_CA_EN = 0
4987 11:56:04.584975 CA_PICK = 933
4988 11:56:04.585383 CA_MCKIO = 933
4989 11:56:04.588683 MCKIO_SEMI = 0
4990 11:56:04.591639 PLL_FREQ = 3732
4991 11:56:04.595125 DQ_UI_PI_RATIO = 32
4992 11:56:04.599035 CA_UI_PI_RATIO = 0
4993 11:56:04.601672 ===================================
4994 11:56:04.605248 ===================================
4995 11:56:04.608457 memory_type:LPDDR4
4996 11:56:04.608867 GP_NUM : 10
4997 11:56:04.611545 SRAM_EN : 1
4998 11:56:04.611954 MD32_EN : 0
4999 11:56:04.615564 ===================================
5000 11:56:04.618643 [ANA_INIT] >>>>>>>>>>>>>>
5001 11:56:04.621730 <<<<<< [CONFIGURE PHASE]: ANA_TX
5002 11:56:04.624943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5003 11:56:04.628948 ===================================
5004 11:56:04.632294 data_rate = 1866,PCW = 0X8f00
5005 11:56:04.635801 ===================================
5006 11:56:04.639167 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:56:04.642483 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 11:56:04.648799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 11:56:04.651910 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5010 11:56:04.655665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5011 11:56:04.661784 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5012 11:56:04.662237 [ANA_INIT] flow start
5013 11:56:04.665633 [ANA_INIT] PLL >>>>>>>>
5014 11:56:04.666186 [ANA_INIT] PLL <<<<<<<<
5015 11:56:04.668909 [ANA_INIT] MIDPI >>>>>>>>
5016 11:56:04.672199 [ANA_INIT] MIDPI <<<<<<<<
5017 11:56:04.675315 [ANA_INIT] DLL >>>>>>>>
5018 11:56:04.675769 [ANA_INIT] flow end
5019 11:56:04.678913 ============ LP4 DIFF to SE enter ============
5020 11:56:04.685254 ============ LP4 DIFF to SE exit ============
5021 11:56:04.685713 [ANA_INIT] <<<<<<<<<<<<<
5022 11:56:04.688846 [Flow] Enable top DCM control >>>>>
5023 11:56:04.692157 [Flow] Enable top DCM control <<<<<
5024 11:56:04.695589 Enable DLL master slave shuffle
5025 11:56:04.702538 ==============================================================
5026 11:56:04.703134 Gating Mode config
5027 11:56:04.708781 ==============================================================
5028 11:56:04.712065 Config description:
5029 11:56:04.718809 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5030 11:56:04.725287 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5031 11:56:04.732406 SELPH_MODE 0: By rank 1: By Phase
5032 11:56:04.738856 ==============================================================
5033 11:56:04.739460 GAT_TRACK_EN = 1
5034 11:56:04.741851 RX_GATING_MODE = 2
5035 11:56:04.745839 RX_GATING_TRACK_MODE = 2
5036 11:56:04.749136 SELPH_MODE = 1
5037 11:56:04.752133 PICG_EARLY_EN = 1
5038 11:56:04.755465 VALID_LAT_VALUE = 1
5039 11:56:04.762210 ==============================================================
5040 11:56:04.765856 Enter into Gating configuration >>>>
5041 11:56:04.769180 Exit from Gating configuration <<<<
5042 11:56:04.772178 Enter into DVFS_PRE_config >>>>>
5043 11:56:04.782240 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5044 11:56:04.785710 Exit from DVFS_PRE_config <<<<<
5045 11:56:04.789229 Enter into PICG configuration >>>>
5046 11:56:04.792066 Exit from PICG configuration <<<<
5047 11:56:04.795264 [RX_INPUT] configuration >>>>>
5048 11:56:04.795720 [RX_INPUT] configuration <<<<<
5049 11:56:04.802341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5050 11:56:04.809104 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5051 11:56:04.812344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 11:56:04.819255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 11:56:04.825478 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 11:56:04.832273 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 11:56:04.835579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5056 11:56:04.839033 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5057 11:56:04.845455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5058 11:56:04.848801 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5059 11:56:04.852506 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5060 11:56:04.855583 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 11:56:04.859274 ===================================
5062 11:56:04.862413 LPDDR4 DRAM CONFIGURATION
5063 11:56:04.866003 ===================================
5064 11:56:04.868899 EX_ROW_EN[0] = 0x0
5065 11:56:04.869456 EX_ROW_EN[1] = 0x0
5066 11:56:04.872166 LP4Y_EN = 0x0
5067 11:56:04.872620 WORK_FSP = 0x0
5068 11:56:04.875810 WL = 0x3
5069 11:56:04.876267 RL = 0x3
5070 11:56:04.878639 BL = 0x2
5071 11:56:04.879132 RPST = 0x0
5072 11:56:04.882293 RD_PRE = 0x0
5073 11:56:04.882745 WR_PRE = 0x1
5074 11:56:04.886271 WR_PST = 0x0
5075 11:56:04.886827 DBI_WR = 0x0
5076 11:56:04.889147 DBI_RD = 0x0
5077 11:56:04.889601 OTF = 0x1
5078 11:56:04.892344 ===================================
5079 11:56:04.899078 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5080 11:56:04.902539 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5081 11:56:04.905343 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 11:56:04.909249 ===================================
5083 11:56:04.912692 LPDDR4 DRAM CONFIGURATION
5084 11:56:04.916063 ===================================
5085 11:56:04.918967 EX_ROW_EN[0] = 0x10
5086 11:56:04.919521 EX_ROW_EN[1] = 0x0
5087 11:56:04.922436 LP4Y_EN = 0x0
5088 11:56:04.923034 WORK_FSP = 0x0
5089 11:56:04.926185 WL = 0x3
5090 11:56:04.926744 RL = 0x3
5091 11:56:04.929374 BL = 0x2
5092 11:56:04.929926 RPST = 0x0
5093 11:56:04.932870 RD_PRE = 0x0
5094 11:56:04.933428 WR_PRE = 0x1
5095 11:56:04.935567 WR_PST = 0x0
5096 11:56:04.936020 DBI_WR = 0x0
5097 11:56:04.939071 DBI_RD = 0x0
5098 11:56:04.939630 OTF = 0x1
5099 11:56:04.943034 ===================================
5100 11:56:04.949235 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5101 11:56:04.953415 nWR fixed to 30
5102 11:56:04.956641 [ModeRegInit_LP4] CH0 RK0
5103 11:56:04.957095 [ModeRegInit_LP4] CH0 RK1
5104 11:56:04.960237 [ModeRegInit_LP4] CH1 RK0
5105 11:56:04.963226 [ModeRegInit_LP4] CH1 RK1
5106 11:56:04.963682 match AC timing 9
5107 11:56:04.969741 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5108 11:56:04.972949 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5109 11:56:04.977093 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5110 11:56:04.983345 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5111 11:56:04.986369 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5112 11:56:04.986778 ==
5113 11:56:04.989759 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 11:56:04.992971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 11:56:04.993388 ==
5116 11:56:05.000242 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 11:56:05.007167 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5118 11:56:05.009881 [CA 0] Center 38 (8~69) winsize 62
5119 11:56:05.013503 [CA 1] Center 38 (7~69) winsize 63
5120 11:56:05.017036 [CA 2] Center 35 (5~66) winsize 62
5121 11:56:05.020020 [CA 3] Center 35 (5~66) winsize 62
5122 11:56:05.023376 [CA 4] Center 34 (4~64) winsize 61
5123 11:56:05.026620 [CA 5] Center 34 (4~64) winsize 61
5124 11:56:05.027077
5125 11:56:05.030031 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5126 11:56:05.030448
5127 11:56:05.033765 [CATrainingPosCal] consider 1 rank data
5128 11:56:05.036974 u2DelayCellTimex100 = 270/100 ps
5129 11:56:05.040144 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5130 11:56:05.043810 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5131 11:56:05.046508 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5132 11:56:05.050304 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5133 11:56:05.053096 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5134 11:56:05.056834 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5135 11:56:05.056964
5136 11:56:05.060329 CA PerBit enable=1, Macro0, CA PI delay=34
5137 11:56:05.060458
5138 11:56:05.063109 [CBTSetCACLKResult] CA Dly = 34
5139 11:56:05.066662 CS Dly: 6 (0~37)
5140 11:56:05.066809 ==
5141 11:56:05.070475 Dram Type= 6, Freq= 0, CH_0, rank 1
5142 11:56:05.073784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 11:56:05.074286 ==
5144 11:56:05.080096 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 11:56:05.086661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5146 11:56:05.089992 [CA 0] Center 38 (8~69) winsize 62
5147 11:56:05.093524 [CA 1] Center 38 (8~69) winsize 62
5148 11:56:05.096570 [CA 2] Center 35 (5~66) winsize 62
5149 11:56:05.100293 [CA 3] Center 34 (4~65) winsize 62
5150 11:56:05.103324 [CA 4] Center 34 (3~65) winsize 63
5151 11:56:05.103474 [CA 5] Center 33 (3~64) winsize 62
5152 11:56:05.106900
5153 11:56:05.109778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5154 11:56:05.109907
5155 11:56:05.113868 [CATrainingPosCal] consider 2 rank data
5156 11:56:05.116674 u2DelayCellTimex100 = 270/100 ps
5157 11:56:05.120201 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5158 11:56:05.123219 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5159 11:56:05.126707 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5160 11:56:05.130178 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5161 11:56:05.133902 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5162 11:56:05.137055 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5163 11:56:05.137135
5164 11:56:05.140167 CA PerBit enable=1, Macro0, CA PI delay=34
5165 11:56:05.140247
5166 11:56:05.143417 [CBTSetCACLKResult] CA Dly = 34
5167 11:56:05.146866 CS Dly: 7 (0~39)
5168 11:56:05.146980
5169 11:56:05.150403 ----->DramcWriteLeveling(PI) begin...
5170 11:56:05.150484 ==
5171 11:56:05.153923 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 11:56:05.156726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 11:56:05.156806 ==
5174 11:56:05.160391 Write leveling (Byte 0): 31 => 31
5175 11:56:05.163961 Write leveling (Byte 1): 26 => 26
5176 11:56:05.166665 DramcWriteLeveling(PI) end<-----
5177 11:56:05.166745
5178 11:56:05.166807 ==
5179 11:56:05.170512 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:56:05.174110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:56:05.174554 ==
5182 11:56:05.177289 [Gating] SW mode calibration
5183 11:56:05.184040 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5184 11:56:05.190612 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5185 11:56:05.193860 0 14 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5186 11:56:05.197412 0 14 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
5187 11:56:05.204179 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 11:56:05.207453 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 11:56:05.210560 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 11:56:05.217460 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 11:56:05.220807 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 11:56:05.225018 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5193 11:56:05.231110 0 15 0 | B1->B0 | 2f2f 2929 | 0 0 | (0 0) (0 1)
5194 11:56:05.234906 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 11:56:05.237856 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 11:56:05.241764 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 11:56:05.247608 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 11:56:05.251031 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 11:56:05.254169 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 11:56:05.261257 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 11:56:05.264566 1 0 0 | B1->B0 | 3434 4343 | 0 0 | (0 0) (0 0)
5202 11:56:05.267644 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 11:56:05.274706 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 11:56:05.277771 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 11:56:05.280913 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:56:05.287562 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:56:05.290777 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:56:05.294260 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:56:05.300893 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 11:56:05.304585 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:56:05.308046 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:56:05.314273 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:56:05.317807 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:56:05.321083 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:56:05.327645 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:56:05.331097 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:56:05.334423 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:56:05.337902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:56:05.344144 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:56:05.347415 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:56:05.351126 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:56:05.357667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:56:05.361228 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:56:05.364186 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 11:56:05.371561 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5226 11:56:05.374996 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5227 11:56:05.378039 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5228 11:56:05.381262 Total UI for P1: 0, mck2ui 16
5229 11:56:05.384422 best dqsien dly found for B0: ( 1, 3, 2)
5230 11:56:05.388081 Total UI for P1: 0, mck2ui 16
5231 11:56:05.391468 best dqsien dly found for B1: ( 1, 3, 4)
5232 11:56:05.394825 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5233 11:56:05.397906 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5234 11:56:05.398454
5235 11:56:05.401456 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5236 11:56:05.405020 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5237 11:56:05.408117 [Gating] SW calibration Done
5238 11:56:05.408663 ==
5239 11:56:05.411423 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 11:56:05.418224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 11:56:05.418774 ==
5242 11:56:05.419205 RX Vref Scan: 0
5243 11:56:05.419544
5244 11:56:05.421361 RX Vref 0 -> 0, step: 1
5245 11:56:05.421807
5246 11:56:05.424727 RX Delay -80 -> 252, step: 8
5247 11:56:05.428371 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5248 11:56:05.431239 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5249 11:56:05.435085 iDelay=200, Bit 2, Center 91 (-8 ~ 191) 200
5250 11:56:05.438234 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5251 11:56:05.441318 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5252 11:56:05.448202 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5253 11:56:05.451793 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5254 11:56:05.454429 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5255 11:56:05.458277 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5256 11:56:05.461429 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5257 11:56:05.468655 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5258 11:56:05.471773 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5259 11:56:05.475114 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5260 11:56:05.477932 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5261 11:56:05.481119 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5262 11:56:05.484806 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5263 11:56:05.485498 ==
5264 11:56:05.487984 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 11:56:05.494752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 11:56:05.495240 ==
5267 11:56:05.495603 DQS Delay:
5268 11:56:05.498189 DQS0 = 0, DQS1 = 0
5269 11:56:05.498585 DQM Delay:
5270 11:56:05.498978 DQM0 = 97, DQM1 = 87
5271 11:56:05.501612 DQ Delay:
5272 11:56:05.504566 DQ0 =95, DQ1 =103, DQ2 =91, DQ3 =91
5273 11:56:05.508444 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5274 11:56:05.511467 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5275 11:56:05.514951 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5276 11:56:05.515492
5277 11:56:05.515853
5278 11:56:05.516186 ==
5279 11:56:05.518109 Dram Type= 6, Freq= 0, CH_0, rank 0
5280 11:56:05.521484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 11:56:05.521939 ==
5282 11:56:05.522295
5283 11:56:05.522620
5284 11:56:05.525070 TX Vref Scan disable
5285 11:56:05.528292 == TX Byte 0 ==
5286 11:56:05.531700 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5287 11:56:05.535198 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5288 11:56:05.538243 == TX Byte 1 ==
5289 11:56:05.541720 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5290 11:56:05.544670 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5291 11:56:05.545172 ==
5292 11:56:05.547804 Dram Type= 6, Freq= 0, CH_0, rank 0
5293 11:56:05.551313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5294 11:56:05.554542 ==
5295 11:56:05.555123
5296 11:56:05.555484
5297 11:56:05.555818 TX Vref Scan disable
5298 11:56:05.558632 == TX Byte 0 ==
5299 11:56:05.562146 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5300 11:56:05.565275 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5301 11:56:05.568451 == TX Byte 1 ==
5302 11:56:05.571839 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5303 11:56:05.575785 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5304 11:56:05.578205
5305 11:56:05.578647 [DATLAT]
5306 11:56:05.579162 Freq=933, CH0 RK0
5307 11:56:05.579629
5308 11:56:05.581858 DATLAT Default: 0xd
5309 11:56:05.582301 0, 0xFFFF, sum = 0
5310 11:56:05.584964 1, 0xFFFF, sum = 0
5311 11:56:05.585489 2, 0xFFFF, sum = 0
5312 11:56:05.588610 3, 0xFFFF, sum = 0
5313 11:56:05.589060 4, 0xFFFF, sum = 0
5314 11:56:05.591734 5, 0xFFFF, sum = 0
5315 11:56:05.592217 6, 0xFFFF, sum = 0
5316 11:56:05.594842 7, 0xFFFF, sum = 0
5317 11:56:05.598829 8, 0xFFFF, sum = 0
5318 11:56:05.599347 9, 0xFFFF, sum = 0
5319 11:56:05.601937 10, 0x0, sum = 1
5320 11:56:05.602630 11, 0x0, sum = 2
5321 11:56:05.603073 12, 0x0, sum = 3
5322 11:56:05.605342 13, 0x0, sum = 4
5323 11:56:05.605815 best_step = 11
5324 11:56:05.606175
5325 11:56:05.606505 ==
5326 11:56:05.608383 Dram Type= 6, Freq= 0, CH_0, rank 0
5327 11:56:05.615409 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5328 11:56:05.615919 ==
5329 11:56:05.616244 RX Vref Scan: 1
5330 11:56:05.616548
5331 11:56:05.618528 RX Vref 0 -> 0, step: 1
5332 11:56:05.618978
5333 11:56:05.621991 RX Delay -61 -> 252, step: 4
5334 11:56:05.622501
5335 11:56:05.625058 Set Vref, RX VrefLevel [Byte0]: 55
5336 11:56:05.628766 [Byte1]: 53
5337 11:56:05.629271
5338 11:56:05.632037 Final RX Vref Byte 0 = 55 to rank0
5339 11:56:05.635769 Final RX Vref Byte 1 = 53 to rank0
5340 11:56:05.639029 Final RX Vref Byte 0 = 55 to rank1
5341 11:56:05.642117 Final RX Vref Byte 1 = 53 to rank1==
5342 11:56:05.645317 Dram Type= 6, Freq= 0, CH_0, rank 0
5343 11:56:05.648497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 11:56:05.648988 ==
5345 11:56:05.652437 DQS Delay:
5346 11:56:05.652883 DQS0 = 0, DQS1 = 0
5347 11:56:05.653239 DQM Delay:
5348 11:56:05.655505 DQM0 = 96, DQM1 = 89
5349 11:56:05.655951 DQ Delay:
5350 11:56:05.658572 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5351 11:56:05.662339 DQ4 =98, DQ5 =88, DQ6 =106, DQ7 =102
5352 11:56:05.665420 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5353 11:56:05.669085 DQ12 =96, DQ13 =92, DQ14 =100, DQ15 =100
5354 11:56:05.669636
5355 11:56:05.670059
5356 11:56:05.678781 [DQSOSCAuto] RK0, (LSB)MR18= 0x1804, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5357 11:56:05.681894 CH0 RK0: MR19=505, MR18=1804
5358 11:56:05.686021 CH0_RK0: MR19=0x505, MR18=0x1804, DQSOSC=414, MR23=63, INC=63, DEC=42
5359 11:56:05.686471
5360 11:56:05.688695 ----->DramcWriteLeveling(PI) begin...
5361 11:56:05.692084 ==
5362 11:56:05.695345 Dram Type= 6, Freq= 0, CH_0, rank 1
5363 11:56:05.698640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5364 11:56:05.699083 ==
5365 11:56:05.701737 Write leveling (Byte 0): 33 => 33
5366 11:56:05.705315 Write leveling (Byte 1): 31 => 31
5367 11:56:05.708558 DramcWriteLeveling(PI) end<-----
5368 11:56:05.708961
5369 11:56:05.709273 ==
5370 11:56:05.712417 Dram Type= 6, Freq= 0, CH_0, rank 1
5371 11:56:05.715448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5372 11:56:05.716233 ==
5373 11:56:05.718624 [Gating] SW mode calibration
5374 11:56:05.725626 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5375 11:56:05.729049 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5376 11:56:05.735737 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5377 11:56:05.738789 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5378 11:56:05.742737 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 11:56:05.748536 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 11:56:05.751982 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 11:56:05.755327 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5382 11:56:05.761838 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5383 11:56:05.765366 0 14 28 | B1->B0 | 3131 2d2d | 1 1 | (1 1) (1 0)
5384 11:56:05.768850 0 15 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
5385 11:56:05.775444 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 11:56:05.778307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 11:56:05.781834 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 11:56:05.788623 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 11:56:05.792216 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 11:56:05.795161 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5391 11:56:05.802300 0 15 28 | B1->B0 | 2525 3030 | 0 0 | (0 0) (0 0)
5392 11:56:05.805331 1 0 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
5393 11:56:05.808859 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 11:56:05.815374 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 11:56:05.818543 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:56:05.822103 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:56:05.825818 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5398 11:56:05.832151 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5399 11:56:05.835488 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5400 11:56:05.839161 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5401 11:56:05.845581 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5402 11:56:05.848581 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:56:05.851961 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:56:05.858590 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:56:05.862505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:56:05.865580 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:56:05.872266 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:56:05.875611 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:56:05.879166 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:56:05.885788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:56:05.888675 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:56:05.892075 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:56:05.898716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5414 11:56:05.902690 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5415 11:56:05.905586 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5416 11:56:05.909594 Total UI for P1: 0, mck2ui 16
5417 11:56:05.912078 best dqsien dly found for B0: ( 1, 2, 22)
5418 11:56:05.915489 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5419 11:56:05.922531 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 11:56:05.923030 Total UI for P1: 0, mck2ui 16
5421 11:56:05.929600 best dqsien dly found for B1: ( 1, 2, 30)
5422 11:56:05.932616 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5423 11:56:05.935799 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5424 11:56:05.936381
5425 11:56:05.939006 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5426 11:56:05.942999 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5427 11:56:05.945831 [Gating] SW calibration Done
5428 11:56:05.946285 ==
5429 11:56:05.949071 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 11:56:05.952415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 11:56:05.952872 ==
5432 11:56:05.955918 RX Vref Scan: 0
5433 11:56:05.956370
5434 11:56:05.956723 RX Vref 0 -> 0, step: 1
5435 11:56:05.957055
5436 11:56:05.958847 RX Delay -80 -> 252, step: 8
5437 11:56:05.962483 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5438 11:56:05.969450 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5439 11:56:05.972379 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5440 11:56:05.975885 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5441 11:56:05.979146 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5442 11:56:05.983103 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5443 11:56:05.986316 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5444 11:56:05.989662 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5445 11:56:05.996061 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5446 11:56:05.999323 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5447 11:56:06.002777 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5448 11:56:06.006174 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5449 11:56:06.009743 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5450 11:56:06.016088 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5451 11:56:06.019479 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5452 11:56:06.022538 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5453 11:56:06.023026 ==
5454 11:56:06.025838 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 11:56:06.029125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 11:56:06.029598 ==
5457 11:56:06.032303 DQS Delay:
5458 11:56:06.032779 DQS0 = 0, DQS1 = 0
5459 11:56:06.033134 DQM Delay:
5460 11:56:06.035727 DQM0 = 97, DQM1 = 87
5461 11:56:06.036228 DQ Delay:
5462 11:56:06.039560 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5463 11:56:06.042609 DQ4 =95, DQ5 =87, DQ6 =103, DQ7 =107
5464 11:56:06.046061 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =79
5465 11:56:06.049238 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =95
5466 11:56:06.049904
5467 11:56:06.050318
5468 11:56:06.050652 ==
5469 11:56:06.052504 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 11:56:06.059431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 11:56:06.059841 ==
5472 11:56:06.060160
5473 11:56:06.060454
5474 11:56:06.060736 TX Vref Scan disable
5475 11:56:06.062651 == TX Byte 0 ==
5476 11:56:06.065820 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5477 11:56:06.072651 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5478 11:56:06.073146 == TX Byte 1 ==
5479 11:56:06.075977 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5480 11:56:06.079465 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5481 11:56:06.082814 ==
5482 11:56:06.085988 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 11:56:06.089194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 11:56:06.089604 ==
5485 11:56:06.089925
5486 11:56:06.090222
5487 11:56:06.092680 TX Vref Scan disable
5488 11:56:06.093188 == TX Byte 0 ==
5489 11:56:06.099619 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5490 11:56:06.102450 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5491 11:56:06.102935 == TX Byte 1 ==
5492 11:56:06.109484 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5493 11:56:06.113047 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5494 11:56:06.113597
5495 11:56:06.113953 [DATLAT]
5496 11:56:06.115844 Freq=933, CH0 RK1
5497 11:56:06.116291
5498 11:56:06.116642 DATLAT Default: 0xb
5499 11:56:06.119770 0, 0xFFFF, sum = 0
5500 11:56:06.120324 1, 0xFFFF, sum = 0
5501 11:56:06.123092 2, 0xFFFF, sum = 0
5502 11:56:06.123641 3, 0xFFFF, sum = 0
5503 11:56:06.126258 4, 0xFFFF, sum = 0
5504 11:56:06.126824 5, 0xFFFF, sum = 0
5505 11:56:06.129110 6, 0xFFFF, sum = 0
5506 11:56:06.129566 7, 0xFFFF, sum = 0
5507 11:56:06.132403 8, 0xFFFF, sum = 0
5508 11:56:06.132884 9, 0xFFFF, sum = 0
5509 11:56:06.136080 10, 0x0, sum = 1
5510 11:56:06.136534 11, 0x0, sum = 2
5511 11:56:06.139227 12, 0x0, sum = 3
5512 11:56:06.139639 13, 0x0, sum = 4
5513 11:56:06.142675 best_step = 11
5514 11:56:06.143238
5515 11:56:06.143567 ==
5516 11:56:06.146183 Dram Type= 6, Freq= 0, CH_0, rank 1
5517 11:56:06.149797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 11:56:06.150365 ==
5519 11:56:06.152136 RX Vref Scan: 0
5520 11:56:06.152538
5521 11:56:06.152963 RX Vref 0 -> 0, step: 1
5522 11:56:06.153268
5523 11:56:06.155352 RX Delay -61 -> 252, step: 4
5524 11:56:06.162988 iDelay=199, Bit 0, Center 94 (-1 ~ 190) 192
5525 11:56:06.166174 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5526 11:56:06.169753 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5527 11:56:06.173237 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5528 11:56:06.176380 iDelay=199, Bit 4, Center 94 (3 ~ 186) 184
5529 11:56:06.179930 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5530 11:56:06.186659 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5531 11:56:06.189486 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5532 11:56:06.193311 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5533 11:56:06.196398 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5534 11:56:06.199588 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5535 11:56:06.203577 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5536 11:56:06.209761 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5537 11:56:06.212800 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5538 11:56:06.216513 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5539 11:56:06.219632 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5540 11:56:06.220047 ==
5541 11:56:06.223065 Dram Type= 6, Freq= 0, CH_0, rank 1
5542 11:56:06.226400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 11:56:06.229601 ==
5544 11:56:06.230013 DQS Delay:
5545 11:56:06.230341 DQS0 = 0, DQS1 = 0
5546 11:56:06.233421 DQM Delay:
5547 11:56:06.234021 DQM0 = 95, DQM1 = 88
5548 11:56:06.236208 DQ Delay:
5549 11:56:06.236620 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =94
5550 11:56:06.239530 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =104
5551 11:56:06.243465 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5552 11:56:06.246476 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =96
5553 11:56:06.249791
5554 11:56:06.250255
5555 11:56:06.256445 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a07, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5556 11:56:06.259504 CH0 RK1: MR19=505, MR18=1A07
5557 11:56:06.266155 CH0_RK1: MR19=0x505, MR18=0x1A07, DQSOSC=413, MR23=63, INC=63, DEC=42
5558 11:56:06.270073 [RxdqsGatingPostProcess] freq 933
5559 11:56:06.273522 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5560 11:56:06.276517 best DQS0 dly(2T, 0.5T) = (0, 11)
5561 11:56:06.279611 best DQS1 dly(2T, 0.5T) = (0, 11)
5562 11:56:06.283107 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5563 11:56:06.286511 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5564 11:56:06.289585 best DQS0 dly(2T, 0.5T) = (0, 10)
5565 11:56:06.293379 best DQS1 dly(2T, 0.5T) = (0, 10)
5566 11:56:06.296121 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5567 11:56:06.299694 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5568 11:56:06.303070 Pre-setting of DQS Precalculation
5569 11:56:06.306571 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5570 11:56:06.307161 ==
5571 11:56:06.309705 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 11:56:06.312959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 11:56:06.316329 ==
5574 11:56:06.319831 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 11:56:06.326489 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5576 11:56:06.329978 [CA 0] Center 37 (7~67) winsize 61
5577 11:56:06.333435 [CA 1] Center 36 (6~67) winsize 62
5578 11:56:06.336456 [CA 2] Center 34 (4~64) winsize 61
5579 11:56:06.339754 [CA 3] Center 33 (3~64) winsize 62
5580 11:56:06.343307 [CA 4] Center 33 (3~64) winsize 62
5581 11:56:06.346551 [CA 5] Center 33 (3~64) winsize 62
5582 11:56:06.347155
5583 11:56:06.349400 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5584 11:56:06.349855
5585 11:56:06.352915 [CATrainingPosCal] consider 1 rank data
5586 11:56:06.356256 u2DelayCellTimex100 = 270/100 ps
5587 11:56:06.359829 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5588 11:56:06.363222 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 11:56:06.366504 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5590 11:56:06.370091 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5591 11:56:06.373343 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5592 11:56:06.380266 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 11:56:06.380831
5594 11:56:06.383393 CA PerBit enable=1, Macro0, CA PI delay=33
5595 11:56:06.383862
5596 11:56:06.386154 [CBTSetCACLKResult] CA Dly = 33
5597 11:56:06.386687 CS Dly: 4 (0~35)
5598 11:56:06.387103 ==
5599 11:56:06.390020 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 11:56:06.392802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 11:56:06.396699 ==
5602 11:56:06.399856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 11:56:06.406350 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5604 11:56:06.409832 [CA 0] Center 36 (6~67) winsize 62
5605 11:56:06.412962 [CA 1] Center 36 (6~67) winsize 62
5606 11:56:06.416430 [CA 2] Center 34 (4~64) winsize 61
5607 11:56:06.419832 [CA 3] Center 33 (3~64) winsize 62
5608 11:56:06.423039 [CA 4] Center 34 (4~65) winsize 62
5609 11:56:06.426344 [CA 5] Center 32 (2~63) winsize 62
5610 11:56:06.426800
5611 11:56:06.430056 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5612 11:56:06.430600
5613 11:56:06.433701 [CATrainingPosCal] consider 2 rank data
5614 11:56:06.436676 u2DelayCellTimex100 = 270/100 ps
5615 11:56:06.439720 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5616 11:56:06.443876 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 11:56:06.447071 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 11:56:06.449831 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 11:56:06.453202 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 11:56:06.456902 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5621 11:56:06.459850
5622 11:56:06.463386 CA PerBit enable=1, Macro0, CA PI delay=33
5623 11:56:06.463849
5624 11:56:06.466820 [CBTSetCACLKResult] CA Dly = 33
5625 11:56:06.467401 CS Dly: 5 (0~38)
5626 11:56:06.467753
5627 11:56:06.470013 ----->DramcWriteLeveling(PI) begin...
5628 11:56:06.470568 ==
5629 11:56:06.473670 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 11:56:06.476820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 11:56:06.479816 ==
5632 11:56:06.480363 Write leveling (Byte 0): 28 => 28
5633 11:56:06.483097 Write leveling (Byte 1): 29 => 29
5634 11:56:06.486772 DramcWriteLeveling(PI) end<-----
5635 11:56:06.487382
5636 11:56:06.487745 ==
5637 11:56:06.490182 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 11:56:06.496948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 11:56:06.497522 ==
5640 11:56:06.497889 [Gating] SW mode calibration
5641 11:56:06.506571 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5642 11:56:06.510016 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5643 11:56:06.513638 0 14 0 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (1 1)
5644 11:56:06.520105 0 14 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
5645 11:56:06.523318 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 11:56:06.527009 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 11:56:06.533201 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 11:56:06.536918 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:56:06.540582 0 14 24 | B1->B0 | 3535 3434 | 0 1 | (0 1) (1 1)
5650 11:56:06.546792 0 14 28 | B1->B0 | 3030 3333 | 1 1 | (0 0) (1 0)
5651 11:56:06.549843 0 15 0 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
5652 11:56:06.553275 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 11:56:06.559802 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 11:56:06.563240 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5655 11:56:06.566982 0 15 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5656 11:56:06.573661 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:56:06.577074 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:56:06.580188 0 15 28 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
5659 11:56:06.586595 1 0 0 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
5660 11:56:06.589924 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:56:06.593555 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:56:06.596815 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:56:06.603642 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:56:06.607058 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:56:06.610154 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:56:06.617078 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5667 11:56:06.620227 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5668 11:56:06.623553 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:56:06.630444 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:56:06.634015 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:56:06.637049 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:56:06.643601 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:56:06.646774 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:56:06.650247 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:56:06.656981 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:56:06.659901 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:56:06.663418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:56:06.667345 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:56:06.674001 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:56:06.676768 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:56:06.680438 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:56:06.686695 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5683 11:56:06.690107 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5684 11:56:06.693368 Total UI for P1: 0, mck2ui 16
5685 11:56:06.696609 best dqsien dly found for B0: ( 1, 2, 28)
5686 11:56:06.700776 Total UI for P1: 0, mck2ui 16
5687 11:56:06.703330 best dqsien dly found for B1: ( 1, 2, 28)
5688 11:56:06.706858 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5689 11:56:06.710157 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5690 11:56:06.710713
5691 11:56:06.713818 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5692 11:56:06.717314 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5693 11:56:06.720241 [Gating] SW calibration Done
5694 11:56:06.720735 ==
5695 11:56:06.724193 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 11:56:06.727370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 11:56:06.730578 ==
5698 11:56:06.731182 RX Vref Scan: 0
5699 11:56:06.731550
5700 11:56:06.733799 RX Vref 0 -> 0, step: 1
5701 11:56:06.734351
5702 11:56:06.737325 RX Delay -80 -> 252, step: 8
5703 11:56:06.740296 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5704 11:56:06.743712 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5705 11:56:06.747263 iDelay=200, Bit 2, Center 83 (-8 ~ 175) 184
5706 11:56:06.750360 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5707 11:56:06.753315 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5708 11:56:06.757572 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5709 11:56:06.763478 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5710 11:56:06.767051 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5711 11:56:06.770303 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5712 11:56:06.773780 iDelay=200, Bit 9, Center 75 (-24 ~ 175) 200
5713 11:56:06.776683 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5714 11:56:06.783352 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5715 11:56:06.786966 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5716 11:56:06.790572 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5717 11:56:06.793606 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5718 11:56:06.797068 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5719 11:56:06.797615 ==
5720 11:56:06.800277 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:56:06.807954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:56:06.808515 ==
5723 11:56:06.808875 DQS Delay:
5724 11:56:06.809205 DQS0 = 0, DQS1 = 0
5725 11:56:06.810498 DQM Delay:
5726 11:56:06.811016 DQM0 = 95, DQM1 = 88
5727 11:56:06.813735 DQ Delay:
5728 11:56:06.817647 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =95
5729 11:56:06.820617 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5730 11:56:06.823588 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5731 11:56:06.827007 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5732 11:56:06.827561
5733 11:56:06.827919
5734 11:56:06.828250 ==
5735 11:56:06.830401 Dram Type= 6, Freq= 0, CH_1, rank 0
5736 11:56:06.834038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 11:56:06.834594 ==
5738 11:56:06.835007
5739 11:56:06.835480
5740 11:56:06.836787 TX Vref Scan disable
5741 11:56:06.837239 == TX Byte 0 ==
5742 11:56:06.843869 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5743 11:56:06.847258 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5744 11:56:06.847822 == TX Byte 1 ==
5745 11:56:06.853543 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5746 11:56:06.857239 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5747 11:56:06.857808 ==
5748 11:56:06.860836 Dram Type= 6, Freq= 0, CH_1, rank 0
5749 11:56:06.863946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5750 11:56:06.864407 ==
5751 11:56:06.864765
5752 11:56:06.865107
5753 11:56:06.867140 TX Vref Scan disable
5754 11:56:06.870587 == TX Byte 0 ==
5755 11:56:06.874453 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5756 11:56:06.877053 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5757 11:56:06.880800 == TX Byte 1 ==
5758 11:56:06.883870 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5759 11:56:06.887538 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5760 11:56:06.888097
5761 11:56:06.890722 [DATLAT]
5762 11:56:06.891314 Freq=933, CH1 RK0
5763 11:56:06.891684
5764 11:56:06.893769 DATLAT Default: 0xd
5765 11:56:06.894327 0, 0xFFFF, sum = 0
5766 11:56:06.897174 1, 0xFFFF, sum = 0
5767 11:56:06.897744 2, 0xFFFF, sum = 0
5768 11:56:06.900406 3, 0xFFFF, sum = 0
5769 11:56:06.900870 4, 0xFFFF, sum = 0
5770 11:56:06.903739 5, 0xFFFF, sum = 0
5771 11:56:06.904201 6, 0xFFFF, sum = 0
5772 11:56:06.907428 7, 0xFFFF, sum = 0
5773 11:56:06.907886 8, 0xFFFF, sum = 0
5774 11:56:06.910449 9, 0xFFFF, sum = 0
5775 11:56:06.910955 10, 0x0, sum = 1
5776 11:56:06.913907 11, 0x0, sum = 2
5777 11:56:06.914466 12, 0x0, sum = 3
5778 11:56:06.917433 13, 0x0, sum = 4
5779 11:56:06.917997 best_step = 11
5780 11:56:06.918361
5781 11:56:06.918774 ==
5782 11:56:06.920471 Dram Type= 6, Freq= 0, CH_1, rank 0
5783 11:56:06.923945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5784 11:56:06.927368 ==
5785 11:56:06.927826 RX Vref Scan: 1
5786 11:56:06.928183
5787 11:56:06.930829 RX Vref 0 -> 0, step: 1
5788 11:56:06.931426
5789 11:56:06.933878 RX Delay -69 -> 252, step: 4
5790 11:56:06.934436
5791 11:56:06.937619 Set Vref, RX VrefLevel [Byte0]: 56
5792 11:56:06.938178 [Byte1]: 53
5793 11:56:06.942838
5794 11:56:06.943434 Final RX Vref Byte 0 = 56 to rank0
5795 11:56:06.945701 Final RX Vref Byte 1 = 53 to rank0
5796 11:56:06.948712 Final RX Vref Byte 0 = 56 to rank1
5797 11:56:06.952257 Final RX Vref Byte 1 = 53 to rank1==
5798 11:56:06.955897 Dram Type= 6, Freq= 0, CH_1, rank 0
5799 11:56:06.959168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:56:06.962468 ==
5801 11:56:06.962973 DQS Delay:
5802 11:56:06.963342 DQS0 = 0, DQS1 = 0
5803 11:56:06.966095 DQM Delay:
5804 11:56:06.966751 DQM0 = 97, DQM1 = 89
5805 11:56:06.969062 DQ Delay:
5806 11:56:06.972089 DQ0 =100, DQ1 =92, DQ2 =86, DQ3 =96
5807 11:56:06.975939 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5808 11:56:06.979097 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =86
5809 11:56:06.982411 DQ12 =98, DQ13 =98, DQ14 =96, DQ15 =94
5810 11:56:06.983025
5811 11:56:06.983394
5812 11:56:06.988991 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5813 11:56:06.992459 CH1 RK0: MR19=504, MR18=17F3
5814 11:56:06.999392 CH1_RK0: MR19=0x504, MR18=0x17F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5815 11:56:06.999952
5816 11:56:07.002643 ----->DramcWriteLeveling(PI) begin...
5817 11:56:07.003257 ==
5818 11:56:07.006016 Dram Type= 6, Freq= 0, CH_1, rank 1
5819 11:56:07.009502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5820 11:56:07.010064 ==
5821 11:56:07.012390 Write leveling (Byte 0): 30 => 30
5822 11:56:07.015516 Write leveling (Byte 1): 30 => 30
5823 11:56:07.019188 DramcWriteLeveling(PI) end<-----
5824 11:56:07.019741
5825 11:56:07.020097 ==
5826 11:56:07.022411 Dram Type= 6, Freq= 0, CH_1, rank 1
5827 11:56:07.026053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5828 11:56:07.026702 ==
5829 11:56:07.028991 [Gating] SW mode calibration
5830 11:56:07.035723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5831 11:56:07.042445 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5832 11:56:07.046223 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5833 11:56:07.048903 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:56:07.055574 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 11:56:07.059344 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 11:56:07.062716 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 11:56:07.069221 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:56:07.072360 0 14 24 | B1->B0 | 3130 3030 | 1 0 | (0 0) (0 1)
5839 11:56:07.075905 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5840 11:56:07.082487 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5841 11:56:07.085689 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5842 11:56:07.088890 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 11:56:07.096299 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 11:56:07.099327 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:56:07.102955 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:56:07.109012 0 15 24 | B1->B0 | 2a2a 3030 | 0 0 | (1 1) (0 0)
5847 11:56:07.112544 0 15 28 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5848 11:56:07.115458 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5849 11:56:07.122347 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:56:07.125694 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:56:07.129361 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:56:07.132553 1 0 16 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
5853 11:56:07.139356 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:56:07.142405 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5855 11:56:07.145766 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5856 11:56:07.152548 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:56:07.155688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:56:07.159134 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:56:07.165740 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:56:07.169922 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:56:07.172653 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:56:07.179251 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:56:07.182773 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:56:07.185857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:56:07.192763 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:56:07.196172 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:56:07.199159 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:56:07.202432 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:56:07.209288 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:56:07.212628 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5871 11:56:07.219488 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 11:56:07.220046 Total UI for P1: 0, mck2ui 16
5873 11:56:07.222605 best dqsien dly found for B0: ( 1, 2, 24)
5874 11:56:07.225887 Total UI for P1: 0, mck2ui 16
5875 11:56:07.229973 best dqsien dly found for B1: ( 1, 2, 26)
5876 11:56:07.232399 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5877 11:56:07.235874 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5878 11:56:07.238990
5879 11:56:07.242280 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5880 11:56:07.245660 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5881 11:56:07.249014 [Gating] SW calibration Done
5882 11:56:07.249462 ==
5883 11:56:07.252596 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 11:56:07.255567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 11:56:07.256040 ==
5886 11:56:07.256515 RX Vref Scan: 0
5887 11:56:07.256964
5888 11:56:07.259314 RX Vref 0 -> 0, step: 1
5889 11:56:07.259777
5890 11:56:07.262470 RX Delay -80 -> 252, step: 8
5891 11:56:07.265607 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5892 11:56:07.269196 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5893 11:56:07.272806 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5894 11:56:07.278677 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5895 11:56:07.282114 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5896 11:56:07.285572 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5897 11:56:07.288974 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5898 11:56:07.292092 iDelay=200, Bit 7, Center 87 (-8 ~ 183) 192
5899 11:56:07.295539 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5900 11:56:07.302334 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5901 11:56:07.305930 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5902 11:56:07.309100 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5903 11:56:07.312450 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5904 11:56:07.315786 iDelay=200, Bit 13, Center 99 (0 ~ 199) 200
5905 11:56:07.319149 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5906 11:56:07.325940 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5907 11:56:07.326496 ==
5908 11:56:07.329222 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 11:56:07.332649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 11:56:07.333220 ==
5911 11:56:07.333588 DQS Delay:
5912 11:56:07.335986 DQS0 = 0, DQS1 = 0
5913 11:56:07.336440 DQM Delay:
5914 11:56:07.339292 DQM0 = 94, DQM1 = 89
5915 11:56:07.339853 DQ Delay:
5916 11:56:07.342817 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5917 11:56:07.346505 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =87
5918 11:56:07.349245 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5919 11:56:07.352746 DQ12 =95, DQ13 =99, DQ14 =95, DQ15 =95
5920 11:56:07.353313
5921 11:56:07.353677
5922 11:56:07.354012 ==
5923 11:56:07.355926 Dram Type= 6, Freq= 0, CH_1, rank 1
5924 11:56:07.359453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5925 11:56:07.359911 ==
5926 11:56:07.362769
5927 11:56:07.363263
5928 11:56:07.363625 TX Vref Scan disable
5929 11:56:07.366188 == TX Byte 0 ==
5930 11:56:07.369463 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5931 11:56:07.373249 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5932 11:56:07.375781 == TX Byte 1 ==
5933 11:56:07.379163 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5934 11:56:07.382761 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5935 11:56:07.383301 ==
5936 11:56:07.386176 Dram Type= 6, Freq= 0, CH_1, rank 1
5937 11:56:07.392852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5938 11:56:07.393397 ==
5939 11:56:07.393762
5940 11:56:07.394099
5941 11:56:07.394420 TX Vref Scan disable
5942 11:56:07.396588 == TX Byte 0 ==
5943 11:56:07.400578 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5944 11:56:07.406713 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5945 11:56:07.407314 == TX Byte 1 ==
5946 11:56:07.409912 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5947 11:56:07.416919 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5948 11:56:07.417483
5949 11:56:07.417841 [DATLAT]
5950 11:56:07.418177 Freq=933, CH1 RK1
5951 11:56:07.418498
5952 11:56:07.420303 DATLAT Default: 0xb
5953 11:56:07.420863 0, 0xFFFF, sum = 0
5954 11:56:07.423176 1, 0xFFFF, sum = 0
5955 11:56:07.423639 2, 0xFFFF, sum = 0
5956 11:56:07.426200 3, 0xFFFF, sum = 0
5957 11:56:07.426661 4, 0xFFFF, sum = 0
5958 11:56:07.430265 5, 0xFFFF, sum = 0
5959 11:56:07.433228 6, 0xFFFF, sum = 0
5960 11:56:07.433692 7, 0xFFFF, sum = 0
5961 11:56:07.436577 8, 0xFFFF, sum = 0
5962 11:56:07.437144 9, 0xFFFF, sum = 0
5963 11:56:07.439738 10, 0x0, sum = 1
5964 11:56:07.440302 11, 0x0, sum = 2
5965 11:56:07.440673 12, 0x0, sum = 3
5966 11:56:07.443190 13, 0x0, sum = 4
5967 11:56:07.443755 best_step = 11
5968 11:56:07.444115
5969 11:56:07.446636 ==
5970 11:56:07.447235 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 11:56:07.453105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 11:56:07.453691 ==
5973 11:56:07.454179 RX Vref Scan: 0
5974 11:56:07.454628
5975 11:56:07.456583 RX Vref 0 -> 0, step: 1
5976 11:56:07.457046
5977 11:56:07.459902 RX Delay -61 -> 252, step: 4
5978 11:56:07.463170 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5979 11:56:07.469946 iDelay=199, Bit 1, Center 88 (-5 ~ 182) 188
5980 11:56:07.473345 iDelay=199, Bit 2, Center 84 (-9 ~ 178) 188
5981 11:56:07.476743 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5982 11:56:07.479598 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5983 11:56:07.483589 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5984 11:56:07.486579 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5985 11:56:07.490049 iDelay=199, Bit 7, Center 92 (3 ~ 182) 180
5986 11:56:07.496349 iDelay=199, Bit 8, Center 82 (-9 ~ 174) 184
5987 11:56:07.500098 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5988 11:56:07.503640 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5989 11:56:07.507010 iDelay=199, Bit 11, Center 82 (-9 ~ 174) 184
5990 11:56:07.510601 iDelay=199, Bit 12, Center 98 (11 ~ 186) 176
5991 11:56:07.516620 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5992 11:56:07.520309 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5993 11:56:07.523297 iDelay=199, Bit 15, Center 100 (11 ~ 190) 180
5994 11:56:07.523840 ==
5995 11:56:07.526764 Dram Type= 6, Freq= 0, CH_1, rank 1
5996 11:56:07.529954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5997 11:56:07.530507 ==
5998 11:56:07.533533 DQS Delay:
5999 11:56:07.534077 DQS0 = 0, DQS1 = 0
6000 11:56:07.536468 DQM Delay:
6001 11:56:07.536925 DQM0 = 95, DQM1 = 91
6002 11:56:07.537286 DQ Delay:
6003 11:56:07.539694 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =94
6004 11:56:07.543743 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =92
6005 11:56:07.546646 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =82
6006 11:56:07.549964 DQ12 =98, DQ13 =100, DQ14 =100, DQ15 =100
6007 11:56:07.550513
6008 11:56:07.553510
6009 11:56:07.559627 [DQSOSCAuto] RK1, (LSB)MR18= 0x101a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
6010 11:56:07.563343 CH1 RK1: MR19=505, MR18=101A
6011 11:56:07.570130 CH1_RK1: MR19=0x505, MR18=0x101A, DQSOSC=413, MR23=63, INC=63, DEC=42
6012 11:56:07.570669 [RxdqsGatingPostProcess] freq 933
6013 11:56:07.576617 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6014 11:56:07.579567 best DQS0 dly(2T, 0.5T) = (0, 10)
6015 11:56:07.582958 best DQS1 dly(2T, 0.5T) = (0, 10)
6016 11:56:07.586256 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6017 11:56:07.589672 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6018 11:56:07.592995 best DQS0 dly(2T, 0.5T) = (0, 10)
6019 11:56:07.596993 best DQS1 dly(2T, 0.5T) = (0, 10)
6020 11:56:07.599841 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6021 11:56:07.603325 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6022 11:56:07.606812 Pre-setting of DQS Precalculation
6023 11:56:07.609429 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6024 11:56:07.616649 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6025 11:56:07.622846 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6026 11:56:07.623436
6027 11:56:07.627009
6028 11:56:07.627564 [Calibration Summary] 1866 Mbps
6029 11:56:07.630078 CH 0, Rank 0
6030 11:56:07.630623 SW Impedance : PASS
6031 11:56:07.633263 DUTY Scan : NO K
6032 11:56:07.637116 ZQ Calibration : PASS
6033 11:56:07.637667 Jitter Meter : NO K
6034 11:56:07.639969 CBT Training : PASS
6035 11:56:07.643378 Write leveling : PASS
6036 11:56:07.643930 RX DQS gating : PASS
6037 11:56:07.646670 RX DQ/DQS(RDDQC) : PASS
6038 11:56:07.650049 TX DQ/DQS : PASS
6039 11:56:07.650598 RX DATLAT : PASS
6040 11:56:07.653456 RX DQ/DQS(Engine): PASS
6041 11:56:07.656358 TX OE : NO K
6042 11:56:07.656816 All Pass.
6043 11:56:07.657175
6044 11:56:07.657511 CH 0, Rank 1
6045 11:56:07.659734 SW Impedance : PASS
6046 11:56:07.660184 DUTY Scan : NO K
6047 11:56:07.663273 ZQ Calibration : PASS
6048 11:56:07.666471 Jitter Meter : NO K
6049 11:56:07.667072 CBT Training : PASS
6050 11:56:07.669966 Write leveling : PASS
6051 11:56:07.673547 RX DQS gating : PASS
6052 11:56:07.674132 RX DQ/DQS(RDDQC) : PASS
6053 11:56:07.676224 TX DQ/DQS : PASS
6054 11:56:07.679818 RX DATLAT : PASS
6055 11:56:07.680368 RX DQ/DQS(Engine): PASS
6056 11:56:07.683159 TX OE : NO K
6057 11:56:07.683633 All Pass.
6058 11:56:07.684190
6059 11:56:07.686074 CH 1, Rank 0
6060 11:56:07.686539 SW Impedance : PASS
6061 11:56:07.689564 DUTY Scan : NO K
6062 11:56:07.693295 ZQ Calibration : PASS
6063 11:56:07.693862 Jitter Meter : NO K
6064 11:56:07.696471 CBT Training : PASS
6065 11:56:07.699490 Write leveling : PASS
6066 11:56:07.699959 RX DQS gating : PASS
6067 11:56:07.703303 RX DQ/DQS(RDDQC) : PASS
6068 11:56:07.706324 TX DQ/DQS : PASS
6069 11:56:07.706925 RX DATLAT : PASS
6070 11:56:07.709113 RX DQ/DQS(Engine): PASS
6071 11:56:07.712485 TX OE : NO K
6072 11:56:07.712956 All Pass.
6073 11:56:07.713430
6074 11:56:07.713877 CH 1, Rank 1
6075 11:56:07.716631 SW Impedance : PASS
6076 11:56:07.719214 DUTY Scan : NO K
6077 11:56:07.719684 ZQ Calibration : PASS
6078 11:56:07.722773 Jitter Meter : NO K
6079 11:56:07.723401 CBT Training : PASS
6080 11:56:07.725904 Write leveling : PASS
6081 11:56:07.729768 RX DQS gating : PASS
6082 11:56:07.730342 RX DQ/DQS(RDDQC) : PASS
6083 11:56:07.732578 TX DQ/DQS : PASS
6084 11:56:07.735946 RX DATLAT : PASS
6085 11:56:07.736411 RX DQ/DQS(Engine): PASS
6086 11:56:07.739586 TX OE : NO K
6087 11:56:07.740155 All Pass.
6088 11:56:07.740637
6089 11:56:07.742844 DramC Write-DBI off
6090 11:56:07.746193 PER_BANK_REFRESH: Hybrid Mode
6091 11:56:07.746762 TX_TRACKING: ON
6092 11:56:07.755991 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6093 11:56:07.759596 [FAST_K] Save calibration result to emmc
6094 11:56:07.762910 dramc_set_vcore_voltage set vcore to 650000
6095 11:56:07.765741 Read voltage for 400, 6
6096 11:56:07.766207 Vio18 = 0
6097 11:56:07.766680 Vcore = 650000
6098 11:56:07.769128 Vdram = 0
6099 11:56:07.769593 Vddq = 0
6100 11:56:07.770064 Vmddr = 0
6101 11:56:07.776668 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6102 11:56:07.779518 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6103 11:56:07.782740 MEM_TYPE=3, freq_sel=20
6104 11:56:07.786208 sv_algorithm_assistance_LP4_800
6105 11:56:07.789508 ============ PULL DRAM RESETB DOWN ============
6106 11:56:07.792615 ========== PULL DRAM RESETB DOWN end =========
6107 11:56:07.799568 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6108 11:56:07.803323 ===================================
6109 11:56:07.803893 LPDDR4 DRAM CONFIGURATION
6110 11:56:07.806024 ===================================
6111 11:56:07.809909 EX_ROW_EN[0] = 0x0
6112 11:56:07.813286 EX_ROW_EN[1] = 0x0
6113 11:56:07.813855 LP4Y_EN = 0x0
6114 11:56:07.816087 WORK_FSP = 0x0
6115 11:56:07.816651 WL = 0x2
6116 11:56:07.819628 RL = 0x2
6117 11:56:07.820096 BL = 0x2
6118 11:56:07.822419 RPST = 0x0
6119 11:56:07.822921 RD_PRE = 0x0
6120 11:56:07.825901 WR_PRE = 0x1
6121 11:56:07.826366 WR_PST = 0x0
6122 11:56:07.829511 DBI_WR = 0x0
6123 11:56:07.830074 DBI_RD = 0x0
6124 11:56:07.832678 OTF = 0x1
6125 11:56:07.836268 ===================================
6126 11:56:07.839583 ===================================
6127 11:56:07.840056 ANA top config
6128 11:56:07.842773 ===================================
6129 11:56:07.845808 DLL_ASYNC_EN = 0
6130 11:56:07.849685 ALL_SLAVE_EN = 1
6131 11:56:07.850253 NEW_RANK_MODE = 1
6132 11:56:07.852873 DLL_IDLE_MODE = 1
6133 11:56:07.856444 LP45_APHY_COMB_EN = 1
6134 11:56:07.859201 TX_ODT_DIS = 1
6135 11:56:07.862911 NEW_8X_MODE = 1
6136 11:56:07.866389 ===================================
6137 11:56:07.869884 ===================================
6138 11:56:07.870440 data_rate = 800
6139 11:56:07.872806 CKR = 1
6140 11:56:07.876347 DQ_P2S_RATIO = 4
6141 11:56:07.879432 ===================================
6142 11:56:07.883061 CA_P2S_RATIO = 4
6143 11:56:07.885904 DQ_CA_OPEN = 0
6144 11:56:07.889296 DQ_SEMI_OPEN = 1
6145 11:56:07.889867 CA_SEMI_OPEN = 1
6146 11:56:07.892976 CA_FULL_RATE = 0
6147 11:56:07.896365 DQ_CKDIV4_EN = 0
6148 11:56:07.899937 CA_CKDIV4_EN = 1
6149 11:56:07.903436 CA_PREDIV_EN = 0
6150 11:56:07.903999 PH8_DLY = 0
6151 11:56:07.906319 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6152 11:56:07.909855 DQ_AAMCK_DIV = 0
6153 11:56:07.913085 CA_AAMCK_DIV = 0
6154 11:56:07.917010 CA_ADMCK_DIV = 4
6155 11:56:07.920334 DQ_TRACK_CA_EN = 0
6156 11:56:07.920901 CA_PICK = 800
6157 11:56:07.923469 CA_MCKIO = 400
6158 11:56:07.926615 MCKIO_SEMI = 400
6159 11:56:07.930063 PLL_FREQ = 3016
6160 11:56:07.933255 DQ_UI_PI_RATIO = 32
6161 11:56:07.936538 CA_UI_PI_RATIO = 32
6162 11:56:07.939756 ===================================
6163 11:56:07.943358 ===================================
6164 11:56:07.943956 memory_type:LPDDR4
6165 11:56:07.946410 GP_NUM : 10
6166 11:56:07.949827 SRAM_EN : 1
6167 11:56:07.950360 MD32_EN : 0
6168 11:56:07.953268 ===================================
6169 11:56:07.956429 [ANA_INIT] >>>>>>>>>>>>>>
6170 11:56:07.959787 <<<<<< [CONFIGURE PHASE]: ANA_TX
6171 11:56:07.963252 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6172 11:56:07.966715 ===================================
6173 11:56:07.970136 data_rate = 800,PCW = 0X7400
6174 11:56:07.973207 ===================================
6175 11:56:07.976451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6176 11:56:07.980032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6177 11:56:07.993101 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 11:56:07.997095 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6179 11:56:07.999867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6180 11:56:08.003546 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6181 11:56:08.006548 [ANA_INIT] flow start
6182 11:56:08.007125 [ANA_INIT] PLL >>>>>>>>
6183 11:56:08.009820 [ANA_INIT] PLL <<<<<<<<
6184 11:56:08.013434 [ANA_INIT] MIDPI >>>>>>>>
6185 11:56:08.016579 [ANA_INIT] MIDPI <<<<<<<<
6186 11:56:08.017035 [ANA_INIT] DLL >>>>>>>>
6187 11:56:08.020205 [ANA_INIT] flow end
6188 11:56:08.023210 ============ LP4 DIFF to SE enter ============
6189 11:56:08.026782 ============ LP4 DIFF to SE exit ============
6190 11:56:08.029937 [ANA_INIT] <<<<<<<<<<<<<
6191 11:56:08.033383 [Flow] Enable top DCM control >>>>>
6192 11:56:08.036764 [Flow] Enable top DCM control <<<<<
6193 11:56:08.040084 Enable DLL master slave shuffle
6194 11:56:08.043031 ==============================================================
6195 11:56:08.046800 Gating Mode config
6196 11:56:08.053443 ==============================================================
6197 11:56:08.054042 Config description:
6198 11:56:08.063369 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6199 11:56:08.069948 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6200 11:56:08.073605 SELPH_MODE 0: By rank 1: By Phase
6201 11:56:08.080019 ==============================================================
6202 11:56:08.083609 GAT_TRACK_EN = 0
6203 11:56:08.086753 RX_GATING_MODE = 2
6204 11:56:08.090348 RX_GATING_TRACK_MODE = 2
6205 11:56:08.093257 SELPH_MODE = 1
6206 11:56:08.097310 PICG_EARLY_EN = 1
6207 11:56:08.100599 VALID_LAT_VALUE = 1
6208 11:56:08.103951 ==============================================================
6209 11:56:08.106907 Enter into Gating configuration >>>>
6210 11:56:08.109962 Exit from Gating configuration <<<<
6211 11:56:08.113435 Enter into DVFS_PRE_config >>>>>
6212 11:56:08.123571 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6213 11:56:08.127073 Exit from DVFS_PRE_config <<<<<
6214 11:56:08.130107 Enter into PICG configuration >>>>
6215 11:56:08.133720 Exit from PICG configuration <<<<
6216 11:56:08.137053 [RX_INPUT] configuration >>>>>
6217 11:56:08.140214 [RX_INPUT] configuration <<<<<
6218 11:56:08.147025 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6219 11:56:08.150263 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6220 11:56:08.156890 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6221 11:56:08.164150 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6222 11:56:08.170655 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6223 11:56:08.177466 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6224 11:56:08.180545 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6225 11:56:08.183820 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6226 11:56:08.186820 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6227 11:56:08.190122 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6228 11:56:08.197083 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6229 11:56:08.200436 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6230 11:56:08.203446 ===================================
6231 11:56:08.207278 LPDDR4 DRAM CONFIGURATION
6232 11:56:08.210291 ===================================
6233 11:56:08.210748 EX_ROW_EN[0] = 0x0
6234 11:56:08.213566 EX_ROW_EN[1] = 0x0
6235 11:56:08.214109 LP4Y_EN = 0x0
6236 11:56:08.217447 WORK_FSP = 0x0
6237 11:56:08.217999 WL = 0x2
6238 11:56:08.220440 RL = 0x2
6239 11:56:08.220892 BL = 0x2
6240 11:56:08.223430 RPST = 0x0
6241 11:56:08.226963 RD_PRE = 0x0
6242 11:56:08.227422 WR_PRE = 0x1
6243 11:56:08.230413 WR_PST = 0x0
6244 11:56:08.231006 DBI_WR = 0x0
6245 11:56:08.234217 DBI_RD = 0x0
6246 11:56:08.234769 OTF = 0x1
6247 11:56:08.237317 ===================================
6248 11:56:08.240492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6249 11:56:08.243593 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6250 11:56:08.250442 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6251 11:56:08.254126 ===================================
6252 11:56:08.257085 LPDDR4 DRAM CONFIGURATION
6253 11:56:08.260851 ===================================
6254 11:56:08.261619 EX_ROW_EN[0] = 0x10
6255 11:56:08.263979 EX_ROW_EN[1] = 0x0
6256 11:56:08.264434 LP4Y_EN = 0x0
6257 11:56:08.267096 WORK_FSP = 0x0
6258 11:56:08.267553 WL = 0x2
6259 11:56:08.270490 RL = 0x2
6260 11:56:08.271087 BL = 0x2
6261 11:56:08.273891 RPST = 0x0
6262 11:56:08.274346 RD_PRE = 0x0
6263 11:56:08.277028 WR_PRE = 0x1
6264 11:56:08.277575 WR_PST = 0x0
6265 11:56:08.280715 DBI_WR = 0x0
6266 11:56:08.281268 DBI_RD = 0x0
6267 11:56:08.284242 OTF = 0x1
6268 11:56:08.287143 ===================================
6269 11:56:08.293917 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6270 11:56:08.297184 nWR fixed to 30
6271 11:56:08.300453 [ModeRegInit_LP4] CH0 RK0
6272 11:56:08.300911 [ModeRegInit_LP4] CH0 RK1
6273 11:56:08.303730 [ModeRegInit_LP4] CH1 RK0
6274 11:56:08.307171 [ModeRegInit_LP4] CH1 RK1
6275 11:56:08.307718 match AC timing 19
6276 11:56:08.314260 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6277 11:56:08.316837 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6278 11:56:08.320462 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6279 11:56:08.327344 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6280 11:56:08.330660 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6281 11:56:08.331175 ==
6282 11:56:08.333959 Dram Type= 6, Freq= 0, CH_0, rank 0
6283 11:56:08.337073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 11:56:08.337637 ==
6285 11:56:08.343919 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 11:56:08.350259 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6287 11:56:08.353566 [CA 0] Center 36 (8~64) winsize 57
6288 11:56:08.354082 [CA 1] Center 36 (8~64) winsize 57
6289 11:56:08.357342 [CA 2] Center 36 (8~64) winsize 57
6290 11:56:08.360627 [CA 3] Center 36 (8~64) winsize 57
6291 11:56:08.363592 [CA 4] Center 36 (8~64) winsize 57
6292 11:56:08.367359 [CA 5] Center 36 (8~64) winsize 57
6293 11:56:08.367775
6294 11:56:08.370711 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6295 11:56:08.371193
6296 11:56:08.373867 [CATrainingPosCal] consider 1 rank data
6297 11:56:08.377059 u2DelayCellTimex100 = 270/100 ps
6298 11:56:08.380695 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:56:08.383743 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:56:08.390521 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:56:08.393554 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:56:08.397383 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:56:08.400586 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:56:08.401003
6305 11:56:08.403842 CA PerBit enable=1, Macro0, CA PI delay=36
6306 11:56:08.404259
6307 11:56:08.407078 [CBTSetCACLKResult] CA Dly = 36
6308 11:56:08.407493 CS Dly: 1 (0~32)
6309 11:56:08.407822 ==
6310 11:56:08.410500 Dram Type= 6, Freq= 0, CH_0, rank 1
6311 11:56:08.417326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 11:56:08.417836 ==
6313 11:56:08.420747 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6314 11:56:08.427550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6315 11:56:08.430927 [CA 0] Center 36 (8~64) winsize 57
6316 11:56:08.433940 [CA 1] Center 36 (8~64) winsize 57
6317 11:56:08.437627 [CA 2] Center 36 (8~64) winsize 57
6318 11:56:08.440372 [CA 3] Center 36 (8~64) winsize 57
6319 11:56:08.443739 [CA 4] Center 36 (8~64) winsize 57
6320 11:56:08.447183 [CA 5] Center 36 (8~64) winsize 57
6321 11:56:08.447598
6322 11:56:08.450501 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6323 11:56:08.450957
6324 11:56:08.453851 [CATrainingPosCal] consider 2 rank data
6325 11:56:08.457371 u2DelayCellTimex100 = 270/100 ps
6326 11:56:08.460662 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 11:56:08.463997 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:56:08.467540 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:56:08.470821 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:56:08.474014 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:56:08.478123 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:56:08.478631
6333 11:56:08.484118 CA PerBit enable=1, Macro0, CA PI delay=36
6334 11:56:08.484531
6335 11:56:08.484859 [CBTSetCACLKResult] CA Dly = 36
6336 11:56:08.488187 CS Dly: 1 (0~32)
6337 11:56:08.488698
6338 11:56:08.490683 ----->DramcWriteLeveling(PI) begin...
6339 11:56:08.491147 ==
6340 11:56:08.494543 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 11:56:08.497784 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 11:56:08.498293 ==
6343 11:56:08.500957 Write leveling (Byte 0): 40 => 8
6344 11:56:08.503881 Write leveling (Byte 1): 32 => 0
6345 11:56:08.507587 DramcWriteLeveling(PI) end<-----
6346 11:56:08.508097
6347 11:56:08.508429 ==
6348 11:56:08.510896 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 11:56:08.514225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 11:56:08.517844 ==
6351 11:56:08.518408 [Gating] SW mode calibration
6352 11:56:08.524430 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6353 11:56:08.531079 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6354 11:56:08.534101 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6355 11:56:08.540883 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 11:56:08.543687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6357 11:56:08.547856 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 11:56:08.554320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6359 11:56:08.557552 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 11:56:08.560885 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 11:56:08.567638 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 11:56:08.570721 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6363 11:56:08.574094 Total UI for P1: 0, mck2ui 16
6364 11:56:08.577238 best dqsien dly found for B0: ( 0, 14, 24)
6365 11:56:08.580847 Total UI for P1: 0, mck2ui 16
6366 11:56:08.583762 best dqsien dly found for B1: ( 0, 14, 24)
6367 11:56:08.587233 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6368 11:56:08.590768 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6369 11:56:08.591348
6370 11:56:08.594095 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6371 11:56:08.598411 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 11:56:08.600480 [Gating] SW calibration Done
6373 11:56:08.600890 ==
6374 11:56:08.603692 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 11:56:08.607247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 11:56:08.607756 ==
6377 11:56:08.611488 RX Vref Scan: 0
6378 11:56:08.611994
6379 11:56:08.614561 RX Vref 0 -> 0, step: 1
6380 11:56:08.615106
6381 11:56:08.615500 RX Delay -410 -> 252, step: 16
6382 11:56:08.620746 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6383 11:56:08.624141 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6384 11:56:08.627382 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6385 11:56:08.631090 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6386 11:56:08.637792 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6387 11:56:08.640559 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6388 11:56:08.644292 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6389 11:56:08.647878 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6390 11:56:08.654341 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6391 11:56:08.657796 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6392 11:56:08.660684 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6393 11:56:08.664355 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6394 11:56:08.670923 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6395 11:56:08.674091 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6396 11:56:08.677528 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6397 11:56:08.680830 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6398 11:56:08.684307 ==
6399 11:56:08.687734 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 11:56:08.690809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 11:56:08.691278 ==
6402 11:56:08.691605 DQS Delay:
6403 11:56:08.694235 DQS0 = 35, DQS1 = 51
6404 11:56:08.694735 DQM Delay:
6405 11:56:08.697529 DQM0 = 7, DQM1 = 10
6406 11:56:08.697937 DQ Delay:
6407 11:56:08.700977 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6408 11:56:08.703874 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6409 11:56:08.707289 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6410 11:56:08.711129 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6411 11:56:08.711638
6412 11:56:08.711967
6413 11:56:08.712271 ==
6414 11:56:08.714347 Dram Type= 6, Freq= 0, CH_0, rank 0
6415 11:56:08.717900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 11:56:08.718414 ==
6417 11:56:08.718745
6418 11:56:08.719099
6419 11:56:08.721096 TX Vref Scan disable
6420 11:56:08.721507 == TX Byte 0 ==
6421 11:56:08.724079 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6422 11:56:08.731457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6423 11:56:08.731968 == TX Byte 1 ==
6424 11:56:08.734758 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6425 11:56:08.740878 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6426 11:56:08.741382 ==
6427 11:56:08.744481 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 11:56:08.748040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 11:56:08.748551 ==
6430 11:56:08.748885
6431 11:56:08.749191
6432 11:56:08.751298 TX Vref Scan disable
6433 11:56:08.751712 == TX Byte 0 ==
6434 11:56:08.757410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 11:56:08.760936 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 11:56:08.761350 == TX Byte 1 ==
6437 11:56:08.768055 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6438 11:56:08.770845 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6439 11:56:08.771330
6440 11:56:08.771661 [DATLAT]
6441 11:56:08.774229 Freq=400, CH0 RK0
6442 11:56:08.774643
6443 11:56:08.774996 DATLAT Default: 0xf
6444 11:56:08.777830 0, 0xFFFF, sum = 0
6445 11:56:08.778339 1, 0xFFFF, sum = 0
6446 11:56:08.781166 2, 0xFFFF, sum = 0
6447 11:56:08.781678 3, 0xFFFF, sum = 0
6448 11:56:08.784533 4, 0xFFFF, sum = 0
6449 11:56:08.784947 5, 0xFFFF, sum = 0
6450 11:56:08.788004 6, 0xFFFF, sum = 0
6451 11:56:08.788469 7, 0xFFFF, sum = 0
6452 11:56:08.791223 8, 0xFFFF, sum = 0
6453 11:56:08.791687 9, 0xFFFF, sum = 0
6454 11:56:08.794952 10, 0xFFFF, sum = 0
6455 11:56:08.795505 11, 0xFFFF, sum = 0
6456 11:56:08.798020 12, 0xFFFF, sum = 0
6457 11:56:08.798578 13, 0x0, sum = 1
6458 11:56:08.801418 14, 0x0, sum = 2
6459 11:56:08.801974 15, 0x0, sum = 3
6460 11:56:08.804562 16, 0x0, sum = 4
6461 11:56:08.805026 best_step = 14
6462 11:56:08.805384
6463 11:56:08.805718 ==
6464 11:56:08.807814 Dram Type= 6, Freq= 0, CH_0, rank 0
6465 11:56:08.814479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 11:56:08.815110 ==
6467 11:56:08.815491 RX Vref Scan: 1
6468 11:56:08.815829
6469 11:56:08.817812 RX Vref 0 -> 0, step: 1
6470 11:56:08.818268
6471 11:56:08.821548 RX Delay -343 -> 252, step: 8
6472 11:56:08.822003
6473 11:56:08.824447 Set Vref, RX VrefLevel [Byte0]: 55
6474 11:56:08.827732 [Byte1]: 53
6475 11:56:08.828187
6476 11:56:08.831600 Final RX Vref Byte 0 = 55 to rank0
6477 11:56:08.835116 Final RX Vref Byte 1 = 53 to rank0
6478 11:56:08.838506 Final RX Vref Byte 0 = 55 to rank1
6479 11:56:08.841542 Final RX Vref Byte 1 = 53 to rank1==
6480 11:56:08.844922 Dram Type= 6, Freq= 0, CH_0, rank 0
6481 11:56:08.848405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 11:56:08.848957 ==
6483 11:56:08.851537 DQS Delay:
6484 11:56:08.852090 DQS0 = 44, DQS1 = 60
6485 11:56:08.854395 DQM Delay:
6486 11:56:08.854849 DQM0 = 11, DQM1 = 16
6487 11:56:08.855294 DQ Delay:
6488 11:56:08.857601 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6489 11:56:08.861401 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6490 11:56:08.864421 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6491 11:56:08.867999 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =28
6492 11:56:08.868454
6493 11:56:08.868812
6494 11:56:08.877915 [DQSOSCAuto] RK0, (LSB)MR18= 0x8957, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 392 ps
6495 11:56:08.881030 CH0 RK0: MR19=C0C, MR18=8957
6496 11:56:08.884535 CH0_RK0: MR19=0xC0C, MR18=0x8957, DQSOSC=392, MR23=63, INC=384, DEC=256
6497 11:56:08.888085 ==
6498 11:56:08.888498 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 11:56:08.895002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 11:56:08.895509 ==
6501 11:56:08.898136 [Gating] SW mode calibration
6502 11:56:08.905073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6503 11:56:08.908236 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6504 11:56:08.914905 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6505 11:56:08.918262 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 11:56:08.921546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6507 11:56:08.928257 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 11:56:08.931419 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6509 11:56:08.934521 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 11:56:08.941226 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 11:56:08.944762 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 11:56:08.948167 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6513 11:56:08.951757 Total UI for P1: 0, mck2ui 16
6514 11:56:08.955042 best dqsien dly found for B0: ( 0, 14, 24)
6515 11:56:08.957590 Total UI for P1: 0, mck2ui 16
6516 11:56:08.961071 best dqsien dly found for B1: ( 0, 14, 24)
6517 11:56:08.964859 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6518 11:56:08.967552 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6519 11:56:08.967964
6520 11:56:08.971121 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6521 11:56:08.977755 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 11:56:08.978251 [Gating] SW calibration Done
6523 11:56:08.978582 ==
6524 11:56:08.981012 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 11:56:08.988051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 11:56:08.988581 ==
6527 11:56:08.988920 RX Vref Scan: 0
6528 11:56:08.989228
6529 11:56:08.990893 RX Vref 0 -> 0, step: 1
6530 11:56:08.991312
6531 11:56:08.994630 RX Delay -410 -> 252, step: 16
6532 11:56:08.998383 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6533 11:56:09.000752 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6534 11:56:09.007513 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6535 11:56:09.011687 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6536 11:56:09.014775 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6537 11:56:09.018234 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6538 11:56:09.024255 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6539 11:56:09.027903 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6540 11:56:09.031265 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6541 11:56:09.034525 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6542 11:56:09.041139 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6543 11:56:09.044473 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6544 11:56:09.047992 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6545 11:56:09.051092 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6546 11:56:09.057907 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6547 11:56:09.061098 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6548 11:56:09.061558 ==
6549 11:56:09.064226 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 11:56:09.067352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 11:56:09.067806 ==
6552 11:56:09.071406 DQS Delay:
6553 11:56:09.071915 DQS0 = 35, DQS1 = 51
6554 11:56:09.074321 DQM Delay:
6555 11:56:09.074923 DQM0 = 4, DQM1 = 10
6556 11:56:09.075551 DQ Delay:
6557 11:56:09.077530 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6558 11:56:09.080696 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6559 11:56:09.084570 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6560 11:56:09.087523 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6561 11:56:09.087929
6562 11:56:09.088248
6563 11:56:09.088703 ==
6564 11:56:09.090682 Dram Type= 6, Freq= 0, CH_0, rank 1
6565 11:56:09.094589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6566 11:56:09.095055 ==
6567 11:56:09.097906
6568 11:56:09.098408
6569 11:56:09.098734 TX Vref Scan disable
6570 11:56:09.101029 == TX Byte 0 ==
6571 11:56:09.104488 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6572 11:56:09.107543 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6573 11:56:09.111665 == TX Byte 1 ==
6574 11:56:09.115160 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6575 11:56:09.117719 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6576 11:56:09.118183 ==
6577 11:56:09.121375 Dram Type= 6, Freq= 0, CH_0, rank 1
6578 11:56:09.124637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6579 11:56:09.127971 ==
6580 11:56:09.128425
6581 11:56:09.128786
6582 11:56:09.129119 TX Vref Scan disable
6583 11:56:09.131320 == TX Byte 0 ==
6584 11:56:09.134171 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6585 11:56:09.137971 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6586 11:56:09.141283 == TX Byte 1 ==
6587 11:56:09.144681 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6588 11:56:09.147813 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6589 11:56:09.148360
6590 11:56:09.148720 [DATLAT]
6591 11:56:09.151464 Freq=400, CH0 RK1
6592 11:56:09.152013
6593 11:56:09.154508 DATLAT Default: 0xe
6594 11:56:09.155108 0, 0xFFFF, sum = 0
6595 11:56:09.158086 1, 0xFFFF, sum = 0
6596 11:56:09.158547 2, 0xFFFF, sum = 0
6597 11:56:09.161506 3, 0xFFFF, sum = 0
6598 11:56:09.162062 4, 0xFFFF, sum = 0
6599 11:56:09.164262 5, 0xFFFF, sum = 0
6600 11:56:09.164775 6, 0xFFFF, sum = 0
6601 11:56:09.168187 7, 0xFFFF, sum = 0
6602 11:56:09.168742 8, 0xFFFF, sum = 0
6603 11:56:09.171572 9, 0xFFFF, sum = 0
6604 11:56:09.172039 10, 0xFFFF, sum = 0
6605 11:56:09.174729 11, 0xFFFF, sum = 0
6606 11:56:09.175266 12, 0xFFFF, sum = 0
6607 11:56:09.177940 13, 0x0, sum = 1
6608 11:56:09.178398 14, 0x0, sum = 2
6609 11:56:09.181289 15, 0x0, sum = 3
6610 11:56:09.181864 16, 0x0, sum = 4
6611 11:56:09.184630 best_step = 14
6612 11:56:09.185241
6613 11:56:09.185671 ==
6614 11:56:09.187719 Dram Type= 6, Freq= 0, CH_0, rank 1
6615 11:56:09.191051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6616 11:56:09.191487 ==
6617 11:56:09.191818 RX Vref Scan: 0
6618 11:56:09.194672
6619 11:56:09.195228 RX Vref 0 -> 0, step: 1
6620 11:56:09.195566
6621 11:56:09.197441 RX Delay -343 -> 252, step: 8
6622 11:56:09.205447 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6623 11:56:09.209072 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6624 11:56:09.211772 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6625 11:56:09.215718 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6626 11:56:09.222095 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6627 11:56:09.225375 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6628 11:56:09.229188 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6629 11:56:09.231947 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6630 11:56:09.238735 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6631 11:56:09.242230 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6632 11:56:09.245434 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6633 11:56:09.248710 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6634 11:56:09.255193 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6635 11:56:09.258293 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6636 11:56:09.262235 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6637 11:56:09.265424 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6638 11:56:09.268867 ==
6639 11:56:09.272125 Dram Type= 6, Freq= 0, CH_0, rank 1
6640 11:56:09.275427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 11:56:09.275936 ==
6642 11:56:09.276265 DQS Delay:
6643 11:56:09.278300 DQS0 = 48, DQS1 = 56
6644 11:56:09.278712 DQM Delay:
6645 11:56:09.281935 DQM0 = 13, DQM1 = 9
6646 11:56:09.282441 DQ Delay:
6647 11:56:09.284932 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6648 11:56:09.288627 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6649 11:56:09.292051 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6650 11:56:09.295237 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =20
6651 11:56:09.295651
6652 11:56:09.295975
6653 11:56:09.301691 [DQSOSCAuto] RK1, (LSB)MR18= 0x9164, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 391 ps
6654 11:56:09.305424 CH0 RK1: MR19=C0C, MR18=9164
6655 11:56:09.312215 CH0_RK1: MR19=0xC0C, MR18=0x9164, DQSOSC=391, MR23=63, INC=386, DEC=257
6656 11:56:09.315651 [RxdqsGatingPostProcess] freq 400
6657 11:56:09.319049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6658 11:56:09.322424 best DQS0 dly(2T, 0.5T) = (0, 10)
6659 11:56:09.325942 best DQS1 dly(2T, 0.5T) = (0, 10)
6660 11:56:09.328745 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6661 11:56:09.332159 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6662 11:56:09.335247 best DQS0 dly(2T, 0.5T) = (0, 10)
6663 11:56:09.338843 best DQS1 dly(2T, 0.5T) = (0, 10)
6664 11:56:09.343071 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6665 11:56:09.345898 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6666 11:56:09.348722 Pre-setting of DQS Precalculation
6667 11:56:09.352083 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6668 11:56:09.352597 ==
6669 11:56:09.355384 Dram Type= 6, Freq= 0, CH_1, rank 0
6670 11:56:09.362289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 11:56:09.362799 ==
6672 11:56:09.365627 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 11:56:09.372338 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6674 11:56:09.375521 [CA 0] Center 36 (8~64) winsize 57
6675 11:56:09.378660 [CA 1] Center 36 (8~64) winsize 57
6676 11:56:09.382004 [CA 2] Center 36 (8~64) winsize 57
6677 11:56:09.385717 [CA 3] Center 36 (8~64) winsize 57
6678 11:56:09.389074 [CA 4] Center 36 (8~64) winsize 57
6679 11:56:09.392272 [CA 5] Center 36 (8~64) winsize 57
6680 11:56:09.392691
6681 11:56:09.395569 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6682 11:56:09.396078
6683 11:56:09.398800 [CATrainingPosCal] consider 1 rank data
6684 11:56:09.401916 u2DelayCellTimex100 = 270/100 ps
6685 11:56:09.405475 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:56:09.409108 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:56:09.412293 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:56:09.415037 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:56:09.419088 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:56:09.422242 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:56:09.422648
6692 11:56:09.429099 CA PerBit enable=1, Macro0, CA PI delay=36
6693 11:56:09.429634
6694 11:56:09.430022 [CBTSetCACLKResult] CA Dly = 36
6695 11:56:09.432077 CS Dly: 1 (0~32)
6696 11:56:09.432487 ==
6697 11:56:09.435121 Dram Type= 6, Freq= 0, CH_1, rank 1
6698 11:56:09.438465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6699 11:56:09.438916 ==
6700 11:56:09.445313 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6701 11:56:09.452472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6702 11:56:09.455267 [CA 0] Center 36 (8~64) winsize 57
6703 11:56:09.459060 [CA 1] Center 36 (8~64) winsize 57
6704 11:56:09.462205 [CA 2] Center 36 (8~64) winsize 57
6705 11:56:09.462620 [CA 3] Center 36 (8~64) winsize 57
6706 11:56:09.465500 [CA 4] Center 36 (8~64) winsize 57
6707 11:56:09.469265 [CA 5] Center 36 (8~64) winsize 57
6708 11:56:09.469781
6709 11:56:09.472408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6710 11:56:09.472823
6711 11:56:09.479236 [CATrainingPosCal] consider 2 rank data
6712 11:56:09.479661 u2DelayCellTimex100 = 270/100 ps
6713 11:56:09.485257 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 11:56:09.488657 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:56:09.492132 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:56:09.495373 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:56:09.498722 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:56:09.502067 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:56:09.502469
6720 11:56:09.505361 CA PerBit enable=1, Macro0, CA PI delay=36
6721 11:56:09.505782
6722 11:56:09.509172 [CBTSetCACLKResult] CA Dly = 36
6723 11:56:09.512360 CS Dly: 1 (0~32)
6724 11:56:09.512866
6725 11:56:09.515602 ----->DramcWriteLeveling(PI) begin...
6726 11:56:09.516013 ==
6727 11:56:09.518739 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 11:56:09.522224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 11:56:09.522974 ==
6730 11:56:09.525887 Write leveling (Byte 0): 40 => 8
6731 11:56:09.528914 Write leveling (Byte 1): 40 => 8
6732 11:56:09.532046 DramcWriteLeveling(PI) end<-----
6733 11:56:09.532579
6734 11:56:09.532908 ==
6735 11:56:09.535399 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 11:56:09.539042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 11:56:09.539567 ==
6738 11:56:09.542290 [Gating] SW mode calibration
6739 11:56:09.549020 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6740 11:56:09.555420 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6741 11:56:09.559006 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6742 11:56:09.562264 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6743 11:56:09.565474 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6744 11:56:09.572400 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 11:56:09.575365 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6746 11:56:09.579397 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 11:56:09.586147 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 11:56:09.589269 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 11:56:09.592353 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6750 11:56:09.595589 Total UI for P1: 0, mck2ui 16
6751 11:56:09.598806 best dqsien dly found for B0: ( 0, 14, 24)
6752 11:56:09.602469 Total UI for P1: 0, mck2ui 16
6753 11:56:09.605863 best dqsien dly found for B1: ( 0, 14, 24)
6754 11:56:09.609217 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6755 11:56:09.612474 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6756 11:56:09.612982
6757 11:56:09.619325 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6758 11:56:09.622854 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 11:56:09.623395 [Gating] SW calibration Done
6760 11:56:09.626262 ==
6761 11:56:09.629427 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 11:56:09.632482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 11:56:09.632891 ==
6764 11:56:09.633213 RX Vref Scan: 0
6765 11:56:09.633509
6766 11:56:09.635964 RX Vref 0 -> 0, step: 1
6767 11:56:09.636473
6768 11:56:09.639309 RX Delay -410 -> 252, step: 16
6769 11:56:09.642687 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6770 11:56:09.645644 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6771 11:56:09.652362 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6772 11:56:09.656206 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6773 11:56:09.659396 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6774 11:56:09.662326 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6775 11:56:09.669070 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6776 11:56:09.672455 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6777 11:56:09.675831 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6778 11:56:09.678818 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6779 11:56:09.686008 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6780 11:56:09.689521 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6781 11:56:09.692824 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6782 11:56:09.696068 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6783 11:56:09.703052 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6784 11:56:09.706001 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6785 11:56:09.706540 ==
6786 11:56:09.709052 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 11:56:09.712637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 11:56:09.713175 ==
6789 11:56:09.715920 DQS Delay:
6790 11:56:09.716454 DQS0 = 51, DQS1 = 59
6791 11:56:09.719239 DQM Delay:
6792 11:56:09.719667 DQM0 = 19, DQM1 = 17
6793 11:56:09.720107 DQ Delay:
6794 11:56:09.722649 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6795 11:56:09.725987 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6796 11:56:09.729391 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6797 11:56:09.732898 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6798 11:56:09.733431
6799 11:56:09.733880
6800 11:56:09.734299 ==
6801 11:56:09.735679 Dram Type= 6, Freq= 0, CH_1, rank 0
6802 11:56:09.742768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 11:56:09.743401 ==
6804 11:56:09.743844
6805 11:56:09.744256
6806 11:56:09.744658 TX Vref Scan disable
6807 11:56:09.745758 == TX Byte 0 ==
6808 11:56:09.749348 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6809 11:56:09.752239 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6810 11:56:09.755812 == TX Byte 1 ==
6811 11:56:09.758881 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 11:56:09.762736 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 11:56:09.763356 ==
6814 11:56:09.766052 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 11:56:09.772275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 11:56:09.772783 ==
6817 11:56:09.773108
6818 11:56:09.773406
6819 11:56:09.773687 TX Vref Scan disable
6820 11:56:09.775594 == TX Byte 0 ==
6821 11:56:09.778890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 11:56:09.782453 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 11:56:09.785956 == TX Byte 1 ==
6824 11:56:09.788835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6825 11:56:09.792433 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6826 11:56:09.792966
6827 11:56:09.796411 [DATLAT]
6828 11:56:09.796839 Freq=400, CH1 RK0
6829 11:56:09.797163
6830 11:56:09.799629 DATLAT Default: 0xf
6831 11:56:09.800040 0, 0xFFFF, sum = 0
6832 11:56:09.802577 1, 0xFFFF, sum = 0
6833 11:56:09.803026 2, 0xFFFF, sum = 0
6834 11:56:09.805983 3, 0xFFFF, sum = 0
6835 11:56:09.806551 4, 0xFFFF, sum = 0
6836 11:56:09.809479 5, 0xFFFF, sum = 0
6837 11:56:09.810053 6, 0xFFFF, sum = 0
6838 11:56:09.813069 7, 0xFFFF, sum = 0
6839 11:56:09.813582 8, 0xFFFF, sum = 0
6840 11:56:09.816301 9, 0xFFFF, sum = 0
6841 11:56:09.816826 10, 0xFFFF, sum = 0
6842 11:56:09.819192 11, 0xFFFF, sum = 0
6843 11:56:09.822782 12, 0xFFFF, sum = 0
6844 11:56:09.823456 13, 0x0, sum = 1
6845 11:56:09.823797 14, 0x0, sum = 2
6846 11:56:09.826070 15, 0x0, sum = 3
6847 11:56:09.826588 16, 0x0, sum = 4
6848 11:56:09.829396 best_step = 14
6849 11:56:09.829898
6850 11:56:09.830225 ==
6851 11:56:09.832473 Dram Type= 6, Freq= 0, CH_1, rank 0
6852 11:56:09.836078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 11:56:09.836492 ==
6854 11:56:09.839357 RX Vref Scan: 1
6855 11:56:09.839764
6856 11:56:09.840084 RX Vref 0 -> 0, step: 1
6857 11:56:09.840386
6858 11:56:09.842612 RX Delay -359 -> 252, step: 8
6859 11:56:09.843193
6860 11:56:09.845852 Set Vref, RX VrefLevel [Byte0]: 56
6861 11:56:09.849603 [Byte1]: 53
6862 11:56:09.854037
6863 11:56:09.854444 Final RX Vref Byte 0 = 56 to rank0
6864 11:56:09.857710 Final RX Vref Byte 1 = 53 to rank0
6865 11:56:09.860986 Final RX Vref Byte 0 = 56 to rank1
6866 11:56:09.864085 Final RX Vref Byte 1 = 53 to rank1==
6867 11:56:09.867203 Dram Type= 6, Freq= 0, CH_1, rank 0
6868 11:56:09.874348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 11:56:09.874854 ==
6870 11:56:09.875255 DQS Delay:
6871 11:56:09.877594 DQS0 = 48, DQS1 = 60
6872 11:56:09.878310 DQM Delay:
6873 11:56:09.878660 DQM0 = 12, DQM1 = 13
6874 11:56:09.880841 DQ Delay:
6875 11:56:09.883894 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6876 11:56:09.884319 DQ4 =12, DQ5 =20, DQ6 =24, DQ7 =8
6877 11:56:09.887609 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =12
6878 11:56:09.890476 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6879 11:56:09.890927
6880 11:56:09.894379
6881 11:56:09.900800 [DQSOSCAuto] RK0, (LSB)MR18= 0x862d, (MSB)MR19= 0xc0c, tDQSOscB0 = 404 ps tDQSOscB1 = 393 ps
6882 11:56:09.904107 CH1 RK0: MR19=C0C, MR18=862D
6883 11:56:09.910687 CH1_RK0: MR19=0xC0C, MR18=0x862D, DQSOSC=393, MR23=63, INC=382, DEC=254
6884 11:56:09.911276 ==
6885 11:56:09.914610 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 11:56:09.917211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 11:56:09.917628 ==
6888 11:56:09.920997 [Gating] SW mode calibration
6889 11:56:09.927689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6890 11:56:09.930627 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6891 11:56:09.937674 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6892 11:56:09.940910 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6893 11:56:09.944596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6894 11:56:09.951400 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 11:56:09.954173 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6896 11:56:09.957251 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 11:56:09.964225 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 11:56:09.967411 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 11:56:09.970831 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6900 11:56:09.974353 Total UI for P1: 0, mck2ui 16
6901 11:56:09.977422 best dqsien dly found for B0: ( 0, 14, 24)
6902 11:56:09.980759 Total UI for P1: 0, mck2ui 16
6903 11:56:09.983943 best dqsien dly found for B1: ( 0, 14, 24)
6904 11:56:09.987838 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6905 11:56:09.990656 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6906 11:56:09.991105
6907 11:56:09.997607 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6908 11:56:10.000855 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 11:56:10.001267 [Gating] SW calibration Done
6910 11:56:10.004077 ==
6911 11:56:10.007751 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 11:56:10.011117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 11:56:10.011532 ==
6914 11:56:10.011857 RX Vref Scan: 0
6915 11:56:10.012159
6916 11:56:10.014257 RX Vref 0 -> 0, step: 1
6917 11:56:10.014669
6918 11:56:10.017526 RX Delay -410 -> 252, step: 16
6919 11:56:10.020753 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6920 11:56:10.024309 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6921 11:56:10.030708 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6922 11:56:10.034381 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6923 11:56:10.037565 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6924 11:56:10.041089 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6925 11:56:10.047287 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6926 11:56:10.050659 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6927 11:56:10.053922 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6928 11:56:10.057348 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6929 11:56:10.064470 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6930 11:56:10.067829 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6931 11:56:10.070571 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6932 11:56:10.074610 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6933 11:56:10.080745 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6934 11:56:10.084191 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6935 11:56:10.084606 ==
6936 11:56:10.087574 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 11:56:10.091233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 11:56:10.091648 ==
6939 11:56:10.094510 DQS Delay:
6940 11:56:10.094956 DQS0 = 43, DQS1 = 59
6941 11:56:10.097551 DQM Delay:
6942 11:56:10.097962 DQM0 = 11, DQM1 = 20
6943 11:56:10.098288 DQ Delay:
6944 11:56:10.100911 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6945 11:56:10.104017 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6946 11:56:10.107472 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6947 11:56:10.110592 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6948 11:56:10.111026
6949 11:56:10.111350
6950 11:56:10.111652 ==
6951 11:56:10.114109 Dram Type= 6, Freq= 0, CH_1, rank 1
6952 11:56:10.117675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6953 11:56:10.120507 ==
6954 11:56:10.120919
6955 11:56:10.121246
6956 11:56:10.121596 TX Vref Scan disable
6957 11:56:10.124390 == TX Byte 0 ==
6958 11:56:10.127215 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6959 11:56:10.130798 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6960 11:56:10.134219 == TX Byte 1 ==
6961 11:56:10.137300 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6962 11:56:10.141445 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6963 11:56:10.141857 ==
6964 11:56:10.143761 Dram Type= 6, Freq= 0, CH_1, rank 1
6965 11:56:10.150900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6966 11:56:10.151313 ==
6967 11:56:10.151638
6968 11:56:10.151938
6969 11:56:10.152276 TX Vref Scan disable
6970 11:56:10.154125 == TX Byte 0 ==
6971 11:56:10.157470 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6972 11:56:10.160471 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6973 11:56:10.164076 == TX Byte 1 ==
6974 11:56:10.167169 Update DQ dly =586 (4 ,2, 10) DQ OEN =(3 ,3)
6975 11:56:10.170977 Update DQM dly =586 (4 ,2, 10) DQM OEN =(3 ,3)
6976 11:56:10.174851
6977 11:56:10.175412 [DATLAT]
6978 11:56:10.175744 Freq=400, CH1 RK1
6979 11:56:10.176053
6980 11:56:10.177156 DATLAT Default: 0xe
6981 11:56:10.177565 0, 0xFFFF, sum = 0
6982 11:56:10.181062 1, 0xFFFF, sum = 0
6983 11:56:10.181593 2, 0xFFFF, sum = 0
6984 11:56:10.183668 3, 0xFFFF, sum = 0
6985 11:56:10.184086 4, 0xFFFF, sum = 0
6986 11:56:10.187110 5, 0xFFFF, sum = 0
6987 11:56:10.187530 6, 0xFFFF, sum = 0
6988 11:56:10.191054 7, 0xFFFF, sum = 0
6989 11:56:10.191576 8, 0xFFFF, sum = 0
6990 11:56:10.193987 9, 0xFFFF, sum = 0
6991 11:56:10.197181 10, 0xFFFF, sum = 0
6992 11:56:10.197598 11, 0xFFFF, sum = 0
6993 11:56:10.201080 12, 0xFFFF, sum = 0
6994 11:56:10.201604 13, 0x0, sum = 1
6995 11:56:10.204251 14, 0x0, sum = 2
6996 11:56:10.204777 15, 0x0, sum = 3
6997 11:56:10.207365 16, 0x0, sum = 4
6998 11:56:10.207782 best_step = 14
6999 11:56:10.208104
7000 11:56:10.208406 ==
7001 11:56:10.210582 Dram Type= 6, Freq= 0, CH_1, rank 1
7002 11:56:10.214455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7003 11:56:10.215019 ==
7004 11:56:10.217189 RX Vref Scan: 0
7005 11:56:10.217597
7006 11:56:10.220538 RX Vref 0 -> 0, step: 1
7007 11:56:10.220983
7008 11:56:10.221318 RX Delay -359 -> 252, step: 8
7009 11:56:10.229742 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
7010 11:56:10.232448 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7011 11:56:10.236024 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7012 11:56:10.239459 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7013 11:56:10.246319 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7014 11:56:10.249591 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7015 11:56:10.252833 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7016 11:56:10.256202 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7017 11:56:10.262927 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7018 11:56:10.266395 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7019 11:56:10.269762 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7020 11:56:10.272742 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7021 11:56:10.279624 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7022 11:56:10.282726 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7023 11:56:10.285793 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7024 11:56:10.289485 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7025 11:56:10.292717 ==
7026 11:56:10.293159 Dram Type= 6, Freq= 0, CH_1, rank 1
7027 11:56:10.299513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7028 11:56:10.300019 ==
7029 11:56:10.300348 DQS Delay:
7030 11:56:10.302803 DQS0 = 52, DQS1 = 56
7031 11:56:10.303238 DQM Delay:
7032 11:56:10.306549 DQM0 = 13, DQM1 = 9
7033 11:56:10.307103 DQ Delay:
7034 11:56:10.309993 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7035 11:56:10.312947 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7036 11:56:10.313459 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7037 11:56:10.316526 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7038 11:56:10.319828
7039 11:56:10.320241
7040 11:56:10.326311 [DQSOSCAuto] RK1, (LSB)MR18= 0x7f95, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
7041 11:56:10.329979 CH1 RK1: MR19=C0C, MR18=7F95
7042 11:56:10.336332 CH1_RK1: MR19=0xC0C, MR18=0x7F95, DQSOSC=391, MR23=63, INC=386, DEC=257
7043 11:56:10.339716 [RxdqsGatingPostProcess] freq 400
7044 11:56:10.343049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7045 11:56:10.346224 best DQS0 dly(2T, 0.5T) = (0, 10)
7046 11:56:10.349714 best DQS1 dly(2T, 0.5T) = (0, 10)
7047 11:56:10.352751 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7048 11:56:10.356621 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7049 11:56:10.359462 best DQS0 dly(2T, 0.5T) = (0, 10)
7050 11:56:10.363075 best DQS1 dly(2T, 0.5T) = (0, 10)
7051 11:56:10.366664 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7052 11:56:10.369781 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7053 11:56:10.372932 Pre-setting of DQS Precalculation
7054 11:56:10.375968 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7055 11:56:10.382848 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7056 11:56:10.393421 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7057 11:56:10.393982
7058 11:56:10.394342
7059 11:56:10.396089 [Calibration Summary] 800 Mbps
7060 11:56:10.396542 CH 0, Rank 0
7061 11:56:10.399249 SW Impedance : PASS
7062 11:56:10.399686 DUTY Scan : NO K
7063 11:56:10.402655 ZQ Calibration : PASS
7064 11:56:10.403123 Jitter Meter : NO K
7065 11:56:10.406225 CBT Training : PASS
7066 11:56:10.409433 Write leveling : PASS
7067 11:56:10.409952 RX DQS gating : PASS
7068 11:56:10.412480 RX DQ/DQS(RDDQC) : PASS
7069 11:56:10.416111 TX DQ/DQS : PASS
7070 11:56:10.416635 RX DATLAT : PASS
7071 11:56:10.419500 RX DQ/DQS(Engine): PASS
7072 11:56:10.422536 TX OE : NO K
7073 11:56:10.423015 All Pass.
7074 11:56:10.423347
7075 11:56:10.423650 CH 0, Rank 1
7076 11:56:10.425909 SW Impedance : PASS
7077 11:56:10.429600 DUTY Scan : NO K
7078 11:56:10.430010 ZQ Calibration : PASS
7079 11:56:10.433150 Jitter Meter : NO K
7080 11:56:10.436143 CBT Training : PASS
7081 11:56:10.436663 Write leveling : NO K
7082 11:56:10.439568 RX DQS gating : PASS
7083 11:56:10.442922 RX DQ/DQS(RDDQC) : PASS
7084 11:56:10.443443 TX DQ/DQS : PASS
7085 11:56:10.446265 RX DATLAT : PASS
7086 11:56:10.446779 RX DQ/DQS(Engine): PASS
7087 11:56:10.449779 TX OE : NO K
7088 11:56:10.450190 All Pass.
7089 11:56:10.450512
7090 11:56:10.453103 CH 1, Rank 0
7091 11:56:10.453621 SW Impedance : PASS
7092 11:56:10.456536 DUTY Scan : NO K
7093 11:56:10.459913 ZQ Calibration : PASS
7094 11:56:10.460435 Jitter Meter : NO K
7095 11:56:10.463053 CBT Training : PASS
7096 11:56:10.466236 Write leveling : PASS
7097 11:56:10.466751 RX DQS gating : PASS
7098 11:56:10.469583 RX DQ/DQS(RDDQC) : PASS
7099 11:56:10.473004 TX DQ/DQS : PASS
7100 11:56:10.473425 RX DATLAT : PASS
7101 11:56:10.476217 RX DQ/DQS(Engine): PASS
7102 11:56:10.479919 TX OE : NO K
7103 11:56:10.480333 All Pass.
7104 11:56:10.480661
7105 11:56:10.480966 CH 1, Rank 1
7106 11:56:10.482748 SW Impedance : PASS
7107 11:56:10.483204 DUTY Scan : NO K
7108 11:56:10.485944 ZQ Calibration : PASS
7109 11:56:10.489786 Jitter Meter : NO K
7110 11:56:10.490201 CBT Training : PASS
7111 11:56:10.493323 Write leveling : NO K
7112 11:56:10.496120 RX DQS gating : PASS
7113 11:56:10.496537 RX DQ/DQS(RDDQC) : PASS
7114 11:56:10.499828 TX DQ/DQS : PASS
7115 11:56:10.503020 RX DATLAT : PASS
7116 11:56:10.503532 RX DQ/DQS(Engine): PASS
7117 11:56:10.506592 TX OE : NO K
7118 11:56:10.507180 All Pass.
7119 11:56:10.507518
7120 11:56:10.509678 DramC Write-DBI off
7121 11:56:10.513193 PER_BANK_REFRESH: Hybrid Mode
7122 11:56:10.513712 TX_TRACKING: ON
7123 11:56:10.523120 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7124 11:56:10.526508 [FAST_K] Save calibration result to emmc
7125 11:56:10.529777 dramc_set_vcore_voltage set vcore to 725000
7126 11:56:10.532835 Read voltage for 1600, 0
7127 11:56:10.533247 Vio18 = 0
7128 11:56:10.533570 Vcore = 725000
7129 11:56:10.536392 Vdram = 0
7130 11:56:10.536805 Vddq = 0
7131 11:56:10.537197 Vmddr = 0
7132 11:56:10.543110 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7133 11:56:10.546304 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7134 11:56:10.549926 MEM_TYPE=3, freq_sel=13
7135 11:56:10.553345 sv_algorithm_assistance_LP4_3733
7136 11:56:10.556745 ============ PULL DRAM RESETB DOWN ============
7137 11:56:10.559965 ========== PULL DRAM RESETB DOWN end =========
7138 11:56:10.566730 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7139 11:56:10.569975 ===================================
7140 11:56:10.570385 LPDDR4 DRAM CONFIGURATION
7141 11:56:10.573017 ===================================
7142 11:56:10.576880 EX_ROW_EN[0] = 0x0
7143 11:56:10.577290 EX_ROW_EN[1] = 0x0
7144 11:56:10.580159 LP4Y_EN = 0x0
7145 11:56:10.583203 WORK_FSP = 0x1
7146 11:56:10.583613 WL = 0x5
7147 11:56:10.586899 RL = 0x5
7148 11:56:10.587312 BL = 0x2
7149 11:56:10.589750 RPST = 0x0
7150 11:56:10.590162 RD_PRE = 0x0
7151 11:56:10.593482 WR_PRE = 0x1
7152 11:56:10.593998 WR_PST = 0x1
7153 11:56:10.597055 DBI_WR = 0x0
7154 11:56:10.597569 DBI_RD = 0x0
7155 11:56:10.600214 OTF = 0x1
7156 11:56:10.603548 ===================================
7157 11:56:10.606801 ===================================
7158 11:56:10.607368 ANA top config
7159 11:56:10.610499 ===================================
7160 11:56:10.613109 DLL_ASYNC_EN = 0
7161 11:56:10.616678 ALL_SLAVE_EN = 0
7162 11:56:10.617195 NEW_RANK_MODE = 1
7163 11:56:10.619987 DLL_IDLE_MODE = 1
7164 11:56:10.623829 LP45_APHY_COMB_EN = 1
7165 11:56:10.626420 TX_ODT_DIS = 0
7166 11:56:10.626932 NEW_8X_MODE = 1
7167 11:56:10.630346 ===================================
7168 11:56:10.633597 ===================================
7169 11:56:10.636726 data_rate = 3200
7170 11:56:10.640399 CKR = 1
7171 11:56:10.643448 DQ_P2S_RATIO = 8
7172 11:56:10.646707 ===================================
7173 11:56:10.649864 CA_P2S_RATIO = 8
7174 11:56:10.653421 DQ_CA_OPEN = 0
7175 11:56:10.653940 DQ_SEMI_OPEN = 0
7176 11:56:10.656414 CA_SEMI_OPEN = 0
7177 11:56:10.660090 CA_FULL_RATE = 0
7178 11:56:10.663714 DQ_CKDIV4_EN = 0
7179 11:56:10.666650 CA_CKDIV4_EN = 0
7180 11:56:10.670373 CA_PREDIV_EN = 0
7181 11:56:10.670958 PH8_DLY = 12
7182 11:56:10.673339 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7183 11:56:10.676705 DQ_AAMCK_DIV = 4
7184 11:56:10.680436 CA_AAMCK_DIV = 4
7185 11:56:10.683308 CA_ADMCK_DIV = 4
7186 11:56:10.686451 DQ_TRACK_CA_EN = 0
7187 11:56:10.686895 CA_PICK = 1600
7188 11:56:10.690247 CA_MCKIO = 1600
7189 11:56:10.693707 MCKIO_SEMI = 0
7190 11:56:10.696730 PLL_FREQ = 3068
7191 11:56:10.700462 DQ_UI_PI_RATIO = 32
7192 11:56:10.703744 CA_UI_PI_RATIO = 0
7193 11:56:10.706618 ===================================
7194 11:56:10.710539 ===================================
7195 11:56:10.711094 memory_type:LPDDR4
7196 11:56:10.713735 GP_NUM : 10
7197 11:56:10.716783 SRAM_EN : 1
7198 11:56:10.717331 MD32_EN : 0
7199 11:56:10.720731 ===================================
7200 11:56:10.723833 [ANA_INIT] >>>>>>>>>>>>>>
7201 11:56:10.727245 <<<<<< [CONFIGURE PHASE]: ANA_TX
7202 11:56:10.730145 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7203 11:56:10.733849 ===================================
7204 11:56:10.737147 data_rate = 3200,PCW = 0X7600
7205 11:56:10.740302 ===================================
7206 11:56:10.743794 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7207 11:56:10.746692 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7208 11:56:10.753819 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 11:56:10.756761 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7210 11:56:10.760287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7211 11:56:10.763337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7212 11:56:10.767008 [ANA_INIT] flow start
7213 11:56:10.770080 [ANA_INIT] PLL >>>>>>>>
7214 11:56:10.770635 [ANA_INIT] PLL <<<<<<<<
7215 11:56:10.773373 [ANA_INIT] MIDPI >>>>>>>>
7216 11:56:10.776888 [ANA_INIT] MIDPI <<<<<<<<
7217 11:56:10.780393 [ANA_INIT] DLL >>>>>>>>
7218 11:56:10.780845 [ANA_INIT] DLL <<<<<<<<
7219 11:56:10.783616 [ANA_INIT] flow end
7220 11:56:10.786767 ============ LP4 DIFF to SE enter ============
7221 11:56:10.790292 ============ LP4 DIFF to SE exit ============
7222 11:56:10.793327 [ANA_INIT] <<<<<<<<<<<<<
7223 11:56:10.796852 [Flow] Enable top DCM control >>>>>
7224 11:56:10.800279 [Flow] Enable top DCM control <<<<<
7225 11:56:10.803676 Enable DLL master slave shuffle
7226 11:56:10.807038 ==============================================================
7227 11:56:10.810333 Gating Mode config
7228 11:56:10.817369 ==============================================================
7229 11:56:10.817889 Config description:
7230 11:56:10.827292 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7231 11:56:10.833849 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7232 11:56:10.836954 SELPH_MODE 0: By rank 1: By Phase
7233 11:56:10.843565 ==============================================================
7234 11:56:10.846961 GAT_TRACK_EN = 1
7235 11:56:10.850349 RX_GATING_MODE = 2
7236 11:56:10.853598 RX_GATING_TRACK_MODE = 2
7237 11:56:10.857058 SELPH_MODE = 1
7238 11:56:10.860496 PICG_EARLY_EN = 1
7239 11:56:10.863968 VALID_LAT_VALUE = 1
7240 11:56:10.867508 ==============================================================
7241 11:56:10.870664 Enter into Gating configuration >>>>
7242 11:56:10.873975 Exit from Gating configuration <<<<
7243 11:56:10.877500 Enter into DVFS_PRE_config >>>>>
7244 11:56:10.887316 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7245 11:56:10.890625 Exit from DVFS_PRE_config <<<<<
7246 11:56:10.894129 Enter into PICG configuration >>>>
7247 11:56:10.897427 Exit from PICG configuration <<<<
7248 11:56:10.900223 [RX_INPUT] configuration >>>>>
7249 11:56:10.903587 [RX_INPUT] configuration <<<<<
7250 11:56:10.910574 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7251 11:56:10.913592 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7252 11:56:10.920410 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7253 11:56:10.927468 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7254 11:56:10.934716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7255 11:56:10.941159 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7256 11:56:10.944332 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7257 11:56:10.947328 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7258 11:56:10.951360 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7259 11:56:10.953977 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7260 11:56:10.960966 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7261 11:56:10.964120 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7262 11:56:10.967800 ===================================
7263 11:56:10.971364 LPDDR4 DRAM CONFIGURATION
7264 11:56:10.974805 ===================================
7265 11:56:10.975515 EX_ROW_EN[0] = 0x0
7266 11:56:10.977688 EX_ROW_EN[1] = 0x0
7267 11:56:10.978143 LP4Y_EN = 0x0
7268 11:56:10.981401 WORK_FSP = 0x1
7269 11:56:10.981952 WL = 0x5
7270 11:56:10.984077 RL = 0x5
7271 11:56:10.984533 BL = 0x2
7272 11:56:10.987313 RPST = 0x0
7273 11:56:10.987763 RD_PRE = 0x0
7274 11:56:10.990766 WR_PRE = 0x1
7275 11:56:10.991265 WR_PST = 0x1
7276 11:56:10.994623 DBI_WR = 0x0
7277 11:56:10.995240 DBI_RD = 0x0
7278 11:56:10.998121 OTF = 0x1
7279 11:56:11.000833 ===================================
7280 11:56:11.004245 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7281 11:56:11.007789 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7282 11:56:11.014417 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7283 11:56:11.017382 ===================================
7284 11:56:11.018056 LPDDR4 DRAM CONFIGURATION
7285 11:56:11.020921 ===================================
7286 11:56:11.023690 EX_ROW_EN[0] = 0x10
7287 11:56:11.027193 EX_ROW_EN[1] = 0x0
7288 11:56:11.027603 LP4Y_EN = 0x0
7289 11:56:11.031007 WORK_FSP = 0x1
7290 11:56:11.031523 WL = 0x5
7291 11:56:11.034318 RL = 0x5
7292 11:56:11.034834 BL = 0x2
7293 11:56:11.037468 RPST = 0x0
7294 11:56:11.037879 RD_PRE = 0x0
7295 11:56:11.040707 WR_PRE = 0x1
7296 11:56:11.041218 WR_PST = 0x1
7297 11:56:11.044280 DBI_WR = 0x0
7298 11:56:11.044791 DBI_RD = 0x0
7299 11:56:11.047764 OTF = 0x1
7300 11:56:11.050851 ===================================
7301 11:56:11.058036 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7302 11:56:11.058559 ==
7303 11:56:11.061009 Dram Type= 6, Freq= 0, CH_0, rank 0
7304 11:56:11.064164 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 11:56:11.064659 ==
7306 11:56:11.067309 [Duty_Offset_Calibration]
7307 11:56:11.067720 B0:2 B1:-1 CA:1
7308 11:56:11.068041
7309 11:56:11.070646 [DutyScan_Calibration_Flow] k_type=0
7310 11:56:11.080799
7311 11:56:11.081334 ==CLK 0==
7312 11:56:11.083769 Final CLK duty delay cell = -4
7313 11:56:11.087546 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7314 11:56:11.090253 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7315 11:56:11.093942 [-4] AVG Duty = 4937%(X100)
7316 11:56:11.094460
7317 11:56:11.097554 CH0 CLK Duty spec in!! Max-Min= 187%
7318 11:56:11.100523 [DutyScan_Calibration_Flow] ====Done====
7319 11:56:11.101035
7320 11:56:11.103778 [DutyScan_Calibration_Flow] k_type=1
7321 11:56:11.120411
7322 11:56:11.120968 ==DQS 0 ==
7323 11:56:11.123365 Final DQS duty delay cell = 0
7324 11:56:11.126963 [0] MAX Duty = 5125%(X100), DQS PI = 20
7325 11:56:11.130836 [0] MIN Duty = 5000%(X100), DQS PI = 14
7326 11:56:11.133761 [0] AVG Duty = 5062%(X100)
7327 11:56:11.134321
7328 11:56:11.134682 ==DQS 1 ==
7329 11:56:11.137074 Final DQS duty delay cell = -4
7330 11:56:11.139758 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7331 11:56:11.143482 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7332 11:56:11.146509 [-4] AVG Duty = 5046%(X100)
7333 11:56:11.147004
7334 11:56:11.150153 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7335 11:56:11.150713
7336 11:56:11.153522 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7337 11:56:11.156986 [DutyScan_Calibration_Flow] ====Done====
7338 11:56:11.157459
7339 11:56:11.160135 [DutyScan_Calibration_Flow] k_type=3
7340 11:56:11.177392
7341 11:56:11.177942 ==DQM 0 ==
7342 11:56:11.180925 Final DQM duty delay cell = 0
7343 11:56:11.184471 [0] MAX Duty = 5000%(X100), DQS PI = 20
7344 11:56:11.187578 [0] MIN Duty = 4875%(X100), DQS PI = 4
7345 11:56:11.188053 [0] AVG Duty = 4937%(X100)
7346 11:56:11.191354
7347 11:56:11.191806 ==DQM 1 ==
7348 11:56:11.194214 Final DQM duty delay cell = 0
7349 11:56:11.197615 [0] MAX Duty = 5218%(X100), DQS PI = 58
7350 11:56:11.200929 [0] MIN Duty = 4969%(X100), DQS PI = 18
7351 11:56:11.201388 [0] AVG Duty = 5093%(X100)
7352 11:56:11.204200
7353 11:56:11.207800 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7354 11:56:11.208253
7355 11:56:11.211286 CH0 DQM 1 Duty spec in!! Max-Min= 249%
7356 11:56:11.214498 [DutyScan_Calibration_Flow] ====Done====
7357 11:56:11.215058
7358 11:56:11.217920 [DutyScan_Calibration_Flow] k_type=2
7359 11:56:11.234072
7360 11:56:11.234482 ==DQ 0 ==
7361 11:56:11.237247 Final DQ duty delay cell = -4
7362 11:56:11.240605 [-4] MAX Duty = 5000%(X100), DQS PI = 0
7363 11:56:11.244151 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7364 11:56:11.247552 [-4] AVG Duty = 4922%(X100)
7365 11:56:11.248068
7366 11:56:11.248393 ==DQ 1 ==
7367 11:56:11.250585 Final DQ duty delay cell = 0
7368 11:56:11.254247 [0] MAX Duty = 5031%(X100), DQS PI = 30
7369 11:56:11.257051 [0] MIN Duty = 4907%(X100), DQS PI = 18
7370 11:56:11.257468 [0] AVG Duty = 4969%(X100)
7371 11:56:11.260804
7372 11:56:11.264246 CH0 DQ 0 Duty spec in!! Max-Min= 156%
7373 11:56:11.264771
7374 11:56:11.267432 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7375 11:56:11.270358 [DutyScan_Calibration_Flow] ====Done====
7376 11:56:11.270767 ==
7377 11:56:11.273955 Dram Type= 6, Freq= 0, CH_1, rank 0
7378 11:56:11.276959 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7379 11:56:11.277574 ==
7380 11:56:11.280855 [Duty_Offset_Calibration]
7381 11:56:11.281403 B0:1 B1:1 CA:2
7382 11:56:11.281738
7383 11:56:11.283820 [DutyScan_Calibration_Flow] k_type=0
7384 11:56:11.294792
7385 11:56:11.295380 ==CLK 0==
7386 11:56:11.297877 Final CLK duty delay cell = 0
7387 11:56:11.301251 [0] MAX Duty = 5125%(X100), DQS PI = 58
7388 11:56:11.304386 [0] MIN Duty = 4969%(X100), DQS PI = 8
7389 11:56:11.304839 [0] AVG Duty = 5047%(X100)
7390 11:56:11.305199
7391 11:56:11.307541 CH1 CLK Duty spec in!! Max-Min= 156%
7392 11:56:11.314847 [DutyScan_Calibration_Flow] ====Done====
7393 11:56:11.315434
7394 11:56:11.317817 [DutyScan_Calibration_Flow] k_type=1
7395 11:56:11.334563
7396 11:56:11.335150 ==DQS 0 ==
7397 11:56:11.337654 Final DQS duty delay cell = 0
7398 11:56:11.340814 [0] MAX Duty = 5031%(X100), DQS PI = 52
7399 11:56:11.344082 [0] MIN Duty = 4844%(X100), DQS PI = 12
7400 11:56:11.347879 [0] AVG Duty = 4937%(X100)
7401 11:56:11.348433
7402 11:56:11.348788 ==DQS 1 ==
7403 11:56:11.350594 Final DQS duty delay cell = 0
7404 11:56:11.354707 [0] MAX Duty = 5062%(X100), DQS PI = 18
7405 11:56:11.357723 [0] MIN Duty = 4907%(X100), DQS PI = 46
7406 11:56:11.360970 [0] AVG Duty = 4984%(X100)
7407 11:56:11.361527
7408 11:56:11.364360 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7409 11:56:11.364913
7410 11:56:11.367440 CH1 DQS 1 Duty spec in!! Max-Min= 155%
7411 11:56:11.370808 [DutyScan_Calibration_Flow] ====Done====
7412 11:56:11.371412
7413 11:56:11.374324 [DutyScan_Calibration_Flow] k_type=3
7414 11:56:11.390945
7415 11:56:11.391503 ==DQM 0 ==
7416 11:56:11.394558 Final DQM duty delay cell = 0
7417 11:56:11.397893 [0] MAX Duty = 5093%(X100), DQS PI = 52
7418 11:56:11.401106 [0] MIN Duty = 4876%(X100), DQS PI = 18
7419 11:56:11.404371 [0] AVG Duty = 4984%(X100)
7420 11:56:11.404925
7421 11:56:11.405285 ==DQM 1 ==
7422 11:56:11.407997 Final DQM duty delay cell = 0
7423 11:56:11.411555 [0] MAX Duty = 5187%(X100), DQS PI = 28
7424 11:56:11.414549 [0] MIN Duty = 4875%(X100), DQS PI = 50
7425 11:56:11.415150 [0] AVG Duty = 5031%(X100)
7426 11:56:11.417865
7427 11:56:11.421635 CH1 DQM 0 Duty spec in!! Max-Min= 217%
7428 11:56:11.422194
7429 11:56:11.424782 CH1 DQM 1 Duty spec in!! Max-Min= 312%
7430 11:56:11.427804 [DutyScan_Calibration_Flow] ====Done====
7431 11:56:11.428258
7432 11:56:11.431450 [DutyScan_Calibration_Flow] k_type=2
7433 11:56:11.447332
7434 11:56:11.447882 ==DQ 0 ==
7435 11:56:11.450936 Final DQ duty delay cell = 0
7436 11:56:11.453662 [0] MAX Duty = 5125%(X100), DQS PI = 52
7437 11:56:11.457803 [0] MIN Duty = 4969%(X100), DQS PI = 0
7438 11:56:11.458355 [0] AVG Duty = 5047%(X100)
7439 11:56:11.458716
7440 11:56:11.460542 ==DQ 1 ==
7441 11:56:11.464150 Final DQ duty delay cell = -4
7442 11:56:11.467114 [-4] MAX Duty = 5000%(X100), DQS PI = 24
7443 11:56:11.470603 [-4] MIN Duty = 4876%(X100), DQS PI = 34
7444 11:56:11.471212 [-4] AVG Duty = 4938%(X100)
7445 11:56:11.474066
7446 11:56:11.477345 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7447 11:56:11.477902
7448 11:56:11.480733 CH1 DQ 1 Duty spec in!! Max-Min= 124%
7449 11:56:11.483676 [DutyScan_Calibration_Flow] ====Done====
7450 11:56:11.487494 nWR fixed to 30
7451 11:56:11.488058 [ModeRegInit_LP4] CH0 RK0
7452 11:56:11.490690 [ModeRegInit_LP4] CH0 RK1
7453 11:56:11.494281 [ModeRegInit_LP4] CH1 RK0
7454 11:56:11.497879 [ModeRegInit_LP4] CH1 RK1
7455 11:56:11.498437 match AC timing 5
7456 11:56:11.500428 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7457 11:56:11.507293 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7458 11:56:11.510950 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7459 11:56:11.513820 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7460 11:56:11.520569 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7461 11:56:11.521213 [MiockJmeterHQA]
7462 11:56:11.521588
7463 11:56:11.523919 [DramcMiockJmeter] u1RxGatingPI = 0
7464 11:56:11.527052 0 : 4257, 4030
7465 11:56:11.527517 4 : 4252, 4027
7466 11:56:11.527885 8 : 4253, 4027
7467 11:56:11.530563 12 : 4363, 4138
7468 11:56:11.531056 16 : 4363, 4137
7469 11:56:11.533686 20 : 4252, 4027
7470 11:56:11.534145 24 : 4253, 4027
7471 11:56:11.537689 28 : 4253, 4026
7472 11:56:11.538252 32 : 4363, 4138
7473 11:56:11.540287 36 : 4252, 4027
7474 11:56:11.540750 40 : 4363, 4137
7475 11:56:11.541273 44 : 4250, 4027
7476 11:56:11.543936 48 : 4252, 4027
7477 11:56:11.544477 52 : 4250, 4027
7478 11:56:11.547447 56 : 4252, 4029
7479 11:56:11.548022 60 : 4360, 4138
7480 11:56:11.551038 64 : 4250, 4027
7481 11:56:11.551599 68 : 4361, 4138
7482 11:56:11.551969 72 : 4250, 4027
7483 11:56:11.554375 76 : 4250, 4027
7484 11:56:11.554999 80 : 4250, 4027
7485 11:56:11.557521 84 : 4360, 4138
7486 11:56:11.557982 88 : 4250, 4026
7487 11:56:11.561148 92 : 4360, 4137
7488 11:56:11.561721 96 : 4250, 3031
7489 11:56:11.562086 100 : 4250, 0
7490 11:56:11.564067 104 : 4252, 0
7491 11:56:11.564645 108 : 4252, 0
7492 11:56:11.567428 112 : 4252, 0
7493 11:56:11.568017 116 : 4252, 0
7494 11:56:11.568445 120 : 4360, 0
7495 11:56:11.570918 124 : 4250, 0
7496 11:56:11.571386 128 : 4250, 0
7497 11:56:11.574015 132 : 4361, 0
7498 11:56:11.574577 136 : 4361, 0
7499 11:56:11.575009 140 : 4364, 0
7500 11:56:11.577466 144 : 4250, 0
7501 11:56:11.577928 148 : 4253, 0
7502 11:56:11.578297 152 : 4363, 0
7503 11:56:11.580592 156 : 4249, 0
7504 11:56:11.581056 160 : 4250, 0
7505 11:56:11.584461 164 : 4250, 0
7506 11:56:11.585031 168 : 4252, 0
7507 11:56:11.585405 172 : 4360, 0
7508 11:56:11.587253 176 : 4360, 0
7509 11:56:11.587716 180 : 4250, 0
7510 11:56:11.590353 184 : 4250, 0
7511 11:56:11.590817 188 : 4361, 0
7512 11:56:11.591281 192 : 4361, 0
7513 11:56:11.593789 196 : 4250, 0
7514 11:56:11.594250 200 : 4252, 0
7515 11:56:11.597562 204 : 4250, 0
7516 11:56:11.598085 208 : 4250, 0
7517 11:56:11.598423 212 : 4252, 187
7518 11:56:11.600314 216 : 4250, 3818
7519 11:56:11.600734 220 : 4250, 4027
7520 11:56:11.604292 224 : 4361, 4138
7521 11:56:11.604819 228 : 4360, 4137
7522 11:56:11.607784 232 : 4251, 4027
7523 11:56:11.608304 236 : 4360, 4137
7524 11:56:11.610238 240 : 4360, 4138
7525 11:56:11.610657 244 : 4250, 4027
7526 11:56:11.613670 248 : 4250, 4027
7527 11:56:11.614090 252 : 4250, 4027
7528 11:56:11.617185 256 : 4250, 4027
7529 11:56:11.617603 260 : 4250, 4027
7530 11:56:11.617936 264 : 4250, 4027
7531 11:56:11.620658 268 : 4249, 4027
7532 11:56:11.621075 272 : 4250, 4026
7533 11:56:11.624103 276 : 4360, 4138
7534 11:56:11.624818 280 : 4360, 4138
7535 11:56:11.626893 284 : 4250, 4027
7536 11:56:11.627449 288 : 4361, 4137
7537 11:56:11.630708 292 : 4360, 4138
7538 11:56:11.631166 296 : 4250, 4027
7539 11:56:11.634072 300 : 4250, 4027
7540 11:56:11.634490 304 : 4249, 4027
7541 11:56:11.637608 308 : 4250, 4026
7542 11:56:11.638138 312 : 4250, 4027
7543 11:56:11.638474 316 : 4250, 4027
7544 11:56:11.640706 320 : 4249, 4027
7545 11:56:11.641125 324 : 4250, 4026
7546 11:56:11.644107 328 : 4360, 4138
7547 11:56:11.644644 332 : 4360, 3122
7548 11:56:11.647163 336 : 4250, 57
7549 11:56:11.647643
7550 11:56:11.647975 MIOCK jitter meter ch=0
7551 11:56:11.648279
7552 11:56:11.651170 1T = (336-100) = 236 dly cells
7553 11:56:11.657046 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7554 11:56:11.657460 ==
7555 11:56:11.660915 Dram Type= 6, Freq= 0, CH_0, rank 0
7556 11:56:11.663850 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7557 11:56:11.664270 ==
7558 11:56:11.670833 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7559 11:56:11.674197 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7560 11:56:11.677889 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7561 11:56:11.684151 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7562 11:56:11.693924 [CA 0] Center 44 (14~75) winsize 62
7563 11:56:11.697389 [CA 1] Center 44 (14~74) winsize 61
7564 11:56:11.700667 [CA 2] Center 39 (10~68) winsize 59
7565 11:56:11.704538 [CA 3] Center 39 (10~68) winsize 59
7566 11:56:11.707838 [CA 4] Center 37 (7~67) winsize 61
7567 11:56:11.711034 [CA 5] Center 37 (7~67) winsize 61
7568 11:56:11.711551
7569 11:56:11.714494 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7570 11:56:11.715064
7571 11:56:11.717439 [CATrainingPosCal] consider 1 rank data
7572 11:56:11.720816 u2DelayCellTimex100 = 275/100 ps
7573 11:56:11.724239 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7574 11:56:11.731015 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7575 11:56:11.734083 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7576 11:56:11.737310 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7577 11:56:11.741053 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7578 11:56:11.744508 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7579 11:56:11.745022
7580 11:56:11.747580 CA PerBit enable=1, Macro0, CA PI delay=37
7581 11:56:11.747995
7582 11:56:11.751046 [CBTSetCACLKResult] CA Dly = 37
7583 11:56:11.754748 CS Dly: 11 (0~42)
7584 11:56:11.757589 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7585 11:56:11.760835 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7586 11:56:11.761248 ==
7587 11:56:11.764883 Dram Type= 6, Freq= 0, CH_0, rank 1
7588 11:56:11.767361 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 11:56:11.767781 ==
7590 11:56:11.774409 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7591 11:56:11.777566 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7592 11:56:11.784637 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7593 11:56:11.787847 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7594 11:56:11.797963 [CA 0] Center 43 (13~74) winsize 62
7595 11:56:11.801358 [CA 1] Center 43 (13~74) winsize 62
7596 11:56:11.804198 [CA 2] Center 39 (10~69) winsize 60
7597 11:56:11.807971 [CA 3] Center 38 (9~68) winsize 60
7598 11:56:11.810944 [CA 4] Center 37 (7~67) winsize 61
7599 11:56:11.814686 [CA 5] Center 37 (7~67) winsize 61
7600 11:56:11.815250
7601 11:56:11.818377 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7602 11:56:11.818928
7603 11:56:11.821650 [CATrainingPosCal] consider 2 rank data
7604 11:56:11.825072 u2DelayCellTimex100 = 275/100 ps
7605 11:56:11.828183 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7606 11:56:11.834729 CA1 delay=44 (14~74),Diff = 7 PI (24 cell)
7607 11:56:11.838016 CA2 delay=39 (10~68),Diff = 2 PI (7 cell)
7608 11:56:11.841278 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7609 11:56:11.844777 CA4 delay=37 (7~67),Diff = 0 PI (0 cell)
7610 11:56:11.848304 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7611 11:56:11.848829
7612 11:56:11.851154 CA PerBit enable=1, Macro0, CA PI delay=37
7613 11:56:11.851565
7614 11:56:11.855320 [CBTSetCACLKResult] CA Dly = 37
7615 11:56:11.855844 CS Dly: 12 (0~44)
7616 11:56:11.861666 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7617 11:56:11.865051 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7618 11:56:11.865498
7619 11:56:11.868092 ----->DramcWriteLeveling(PI) begin...
7620 11:56:11.868626 ==
7621 11:56:11.871483 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 11:56:11.875110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 11:56:11.875659 ==
7624 11:56:11.878366 Write leveling (Byte 0): 31 => 31
7625 11:56:11.881494 Write leveling (Byte 1): 28 => 28
7626 11:56:11.885596 DramcWriteLeveling(PI) end<-----
7627 11:56:11.886115
7628 11:56:11.886443 ==
7629 11:56:11.888139 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 11:56:11.891621 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 11:56:11.895404 ==
7632 11:56:11.895923 [Gating] SW mode calibration
7633 11:56:11.901891 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7634 11:56:11.908719 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7635 11:56:11.911723 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 11:56:11.918530 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 11:56:11.921847 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 11:56:11.925104 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:56:11.932079 1 4 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7640 11:56:11.935596 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7641 11:56:11.938339 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7642 11:56:11.945186 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7643 11:56:11.948854 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 11:56:11.951958 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 11:56:11.958753 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 11:56:11.961680 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7647 11:56:11.965140 1 5 16 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7648 11:56:11.968506 1 5 20 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
7649 11:56:11.975418 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
7650 11:56:11.978445 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7651 11:56:11.981845 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 11:56:11.988601 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 11:56:11.991954 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 11:56:11.995006 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 11:56:12.001658 1 6 16 | B1->B0 | 2323 3a39 | 0 1 | (0 0) (0 0)
7656 11:56:12.005224 1 6 20 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7657 11:56:12.008633 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7658 11:56:12.015293 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 11:56:12.018265 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 11:56:12.021684 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 11:56:12.028802 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 11:56:12.032275 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 11:56:12.035772 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7664 11:56:12.039170 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 11:56:12.045508 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7666 11:56:12.048942 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 11:56:12.052092 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:56:12.058722 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:56:12.062109 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:56:12.065258 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:56:12.072239 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:56:12.075252 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:56:12.078614 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 11:56:12.085560 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 11:56:12.088808 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 11:56:12.091790 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:56:12.098513 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:56:12.101878 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:56:12.105454 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7680 11:56:12.112132 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7681 11:56:12.112547 Total UI for P1: 0, mck2ui 16
7682 11:56:12.115615 best dqsien dly found for B0: ( 1, 9, 16)
7683 11:56:12.121918 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7684 11:56:12.125504 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 11:56:12.128744 Total UI for P1: 0, mck2ui 16
7686 11:56:12.132237 best dqsien dly found for B1: ( 1, 9, 22)
7687 11:56:12.135518 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7688 11:56:12.138851 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7689 11:56:12.139318
7690 11:56:12.142003 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7691 11:56:12.145675 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7692 11:56:12.148799 [Gating] SW calibration Done
7693 11:56:12.149212 ==
7694 11:56:12.152334 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 11:56:12.158732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 11:56:12.159315 ==
7697 11:56:12.159701 RX Vref Scan: 0
7698 11:56:12.160131
7699 11:56:12.162364 RX Vref 0 -> 0, step: 1
7700 11:56:12.162919
7701 11:56:12.165309 RX Delay 0 -> 252, step: 8
7702 11:56:12.168889 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7703 11:56:12.172114 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7704 11:56:12.175540 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7705 11:56:12.178837 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7706 11:56:12.185686 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7707 11:56:12.188765 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7708 11:56:12.192100 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7709 11:56:12.195811 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7710 11:56:12.199084 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7711 11:56:12.205756 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7712 11:56:12.208783 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7713 11:56:12.212109 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7714 11:56:12.215421 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7715 11:56:12.218575 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7716 11:56:12.225328 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7717 11:56:12.228748 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7718 11:56:12.229166 ==
7719 11:56:12.232321 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 11:56:12.235353 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 11:56:12.235780 ==
7722 11:56:12.238959 DQS Delay:
7723 11:56:12.239375 DQS0 = 0, DQS1 = 0
7724 11:56:12.239707 DQM Delay:
7725 11:56:12.242061 DQM0 = 131, DQM1 = 123
7726 11:56:12.242473 DQ Delay:
7727 11:56:12.245701 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7728 11:56:12.249320 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7729 11:56:12.252235 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7730 11:56:12.259549 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7731 11:56:12.260074
7732 11:56:12.260405
7733 11:56:12.260705 ==
7734 11:56:12.262171 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 11:56:12.265674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 11:56:12.266199 ==
7737 11:56:12.266560
7738 11:56:12.266938
7739 11:56:12.269193 TX Vref Scan disable
7740 11:56:12.269615 == TX Byte 0 ==
7741 11:56:12.275679 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7742 11:56:12.278858 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7743 11:56:12.279308 == TX Byte 1 ==
7744 11:56:12.285896 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7745 11:56:12.288969 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7746 11:56:12.289385 ==
7747 11:56:12.292603 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 11:56:12.296175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 11:56:12.296697 ==
7750 11:56:12.310912
7751 11:56:12.313905 TX Vref early break, caculate TX vref
7752 11:56:12.317298 TX Vref=16, minBit 0, minWin=21, winSum=359
7753 11:56:12.320544 TX Vref=18, minBit 7, minWin=21, winSum=366
7754 11:56:12.324003 TX Vref=20, minBit 0, minWin=22, winSum=378
7755 11:56:12.327404 TX Vref=22, minBit 1, minWin=22, winSum=387
7756 11:56:12.331048 TX Vref=24, minBit 0, minWin=23, winSum=398
7757 11:56:12.337278 TX Vref=26, minBit 1, minWin=24, winSum=407
7758 11:56:12.340728 TX Vref=28, minBit 1, minWin=24, winSum=418
7759 11:56:12.343644 TX Vref=30, minBit 4, minWin=24, winSum=415
7760 11:56:12.347498 TX Vref=32, minBit 3, minWin=24, winSum=409
7761 11:56:12.350708 TX Vref=34, minBit 0, minWin=24, winSum=398
7762 11:56:12.353908 TX Vref=36, minBit 0, minWin=22, winSum=392
7763 11:56:12.360436 [TxChooseVref] Worse bit 1, Min win 24, Win sum 418, Final Vref 28
7764 11:56:12.360961
7765 11:56:12.364494 Final TX Range 0 Vref 28
7766 11:56:12.365051
7767 11:56:12.365419 ==
7768 11:56:12.367411 Dram Type= 6, Freq= 0, CH_0, rank 0
7769 11:56:12.370628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7770 11:56:12.371241 ==
7771 11:56:12.371614
7772 11:56:12.371948
7773 11:56:12.374068 TX Vref Scan disable
7774 11:56:12.380871 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7775 11:56:12.381416 == TX Byte 0 ==
7776 11:56:12.384392 u2DelayCellOfst[0]=14 cells (4 PI)
7777 11:56:12.387516 u2DelayCellOfst[1]=21 cells (6 PI)
7778 11:56:12.390492 u2DelayCellOfst[2]=10 cells (3 PI)
7779 11:56:12.394358 u2DelayCellOfst[3]=14 cells (4 PI)
7780 11:56:12.397485 u2DelayCellOfst[4]=10 cells (3 PI)
7781 11:56:12.400521 u2DelayCellOfst[5]=0 cells (0 PI)
7782 11:56:12.404386 u2DelayCellOfst[6]=21 cells (6 PI)
7783 11:56:12.404944 u2DelayCellOfst[7]=17 cells (5 PI)
7784 11:56:12.411080 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7785 11:56:12.414166 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7786 11:56:12.417584 == TX Byte 1 ==
7787 11:56:12.418139 u2DelayCellOfst[8]=0 cells (0 PI)
7788 11:56:12.420791 u2DelayCellOfst[9]=0 cells (0 PI)
7789 11:56:12.423907 u2DelayCellOfst[10]=7 cells (2 PI)
7790 11:56:12.427715 u2DelayCellOfst[11]=0 cells (0 PI)
7791 11:56:12.431056 u2DelayCellOfst[12]=14 cells (4 PI)
7792 11:56:12.434263 u2DelayCellOfst[13]=10 cells (3 PI)
7793 11:56:12.437607 u2DelayCellOfst[14]=17 cells (5 PI)
7794 11:56:12.440905 u2DelayCellOfst[15]=14 cells (4 PI)
7795 11:56:12.444389 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7796 11:56:12.451034 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7797 11:56:12.451594 DramC Write-DBI on
7798 11:56:12.451953 ==
7799 11:56:12.454060 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 11:56:12.457287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 11:56:12.457748 ==
7802 11:56:12.460651
7803 11:56:12.461207
7804 11:56:12.461567 TX Vref Scan disable
7805 11:56:12.464058 == TX Byte 0 ==
7806 11:56:12.467515 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7807 11:56:12.470772 == TX Byte 1 ==
7808 11:56:12.474488 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7809 11:56:12.475094 DramC Write-DBI off
7810 11:56:12.475467
7811 11:56:12.477155 [DATLAT]
7812 11:56:12.477614 Freq=1600, CH0 RK0
7813 11:56:12.477968
7814 11:56:12.480851 DATLAT Default: 0xf
7815 11:56:12.481306 0, 0xFFFF, sum = 0
7816 11:56:12.484156 1, 0xFFFF, sum = 0
7817 11:56:12.484620 2, 0xFFFF, sum = 0
7818 11:56:12.487088 3, 0xFFFF, sum = 0
7819 11:56:12.487550 4, 0xFFFF, sum = 0
7820 11:56:12.490999 5, 0xFFFF, sum = 0
7821 11:56:12.491562 6, 0xFFFF, sum = 0
7822 11:56:12.494146 7, 0xFFFF, sum = 0
7823 11:56:12.494607 8, 0xFFFF, sum = 0
7824 11:56:12.497780 9, 0xFFFF, sum = 0
7825 11:56:12.500731 10, 0xFFFF, sum = 0
7826 11:56:12.501197 11, 0xFFFF, sum = 0
7827 11:56:12.504417 12, 0xFFFF, sum = 0
7828 11:56:12.504988 13, 0xFFFF, sum = 0
7829 11:56:12.507610 14, 0x0, sum = 1
7830 11:56:12.508074 15, 0x0, sum = 2
7831 11:56:12.511523 16, 0x0, sum = 3
7832 11:56:12.512097 17, 0x0, sum = 4
7833 11:56:12.512467 best_step = 15
7834 11:56:12.512801
7835 11:56:12.514249 ==
7836 11:56:12.517946 Dram Type= 6, Freq= 0, CH_0, rank 0
7837 11:56:12.520846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7838 11:56:12.521408 ==
7839 11:56:12.521773 RX Vref Scan: 1
7840 11:56:12.522107
7841 11:56:12.524402 Set Vref Range= 24 -> 127
7842 11:56:12.524966
7843 11:56:12.527887 RX Vref 24 -> 127, step: 1
7844 11:56:12.528588
7845 11:56:12.530891 RX Delay 11 -> 252, step: 4
7846 11:56:12.531599
7847 11:56:12.534156 Set Vref, RX VrefLevel [Byte0]: 24
7848 11:56:12.538232 [Byte1]: 24
7849 11:56:12.538786
7850 11:56:12.541078 Set Vref, RX VrefLevel [Byte0]: 25
7851 11:56:12.544729 [Byte1]: 25
7852 11:56:12.545285
7853 11:56:12.548171 Set Vref, RX VrefLevel [Byte0]: 26
7854 11:56:12.551241 [Byte1]: 26
7855 11:56:12.554397
7856 11:56:12.554987 Set Vref, RX VrefLevel [Byte0]: 27
7857 11:56:12.557897 [Byte1]: 27
7858 11:56:12.562059
7859 11:56:12.562612 Set Vref, RX VrefLevel [Byte0]: 28
7860 11:56:12.565515 [Byte1]: 28
7861 11:56:12.569728
7862 11:56:12.570289 Set Vref, RX VrefLevel [Byte0]: 29
7863 11:56:12.572941 [Byte1]: 29
7864 11:56:12.577155
7865 11:56:12.577708 Set Vref, RX VrefLevel [Byte0]: 30
7866 11:56:12.580267 [Byte1]: 30
7867 11:56:12.584817
7868 11:56:12.585274 Set Vref, RX VrefLevel [Byte0]: 31
7869 11:56:12.587800 [Byte1]: 31
7870 11:56:12.592614
7871 11:56:12.593124 Set Vref, RX VrefLevel [Byte0]: 32
7872 11:56:12.595424 [Byte1]: 32
7873 11:56:12.599816
7874 11:56:12.600370 Set Vref, RX VrefLevel [Byte0]: 33
7875 11:56:12.603272 [Byte1]: 33
7876 11:56:12.607781
7877 11:56:12.608328 Set Vref, RX VrefLevel [Byte0]: 34
7878 11:56:12.610844 [Byte1]: 34
7879 11:56:12.615245
7880 11:56:12.615797 Set Vref, RX VrefLevel [Byte0]: 35
7881 11:56:12.618514 [Byte1]: 35
7882 11:56:12.622851
7883 11:56:12.623462 Set Vref, RX VrefLevel [Byte0]: 36
7884 11:56:12.626032 [Byte1]: 36
7885 11:56:12.630326
7886 11:56:12.630920 Set Vref, RX VrefLevel [Byte0]: 37
7887 11:56:12.633827 [Byte1]: 37
7888 11:56:12.637945
7889 11:56:12.638499 Set Vref, RX VrefLevel [Byte0]: 38
7890 11:56:12.641268 [Byte1]: 38
7891 11:56:12.645773
7892 11:56:12.646326 Set Vref, RX VrefLevel [Byte0]: 39
7893 11:56:12.649127 [Byte1]: 39
7894 11:56:12.653396
7895 11:56:12.654053 Set Vref, RX VrefLevel [Byte0]: 40
7896 11:56:12.657061 [Byte1]: 40
7897 11:56:12.660959
7898 11:56:12.661518 Set Vref, RX VrefLevel [Byte0]: 41
7899 11:56:12.664364 [Byte1]: 41
7900 11:56:12.668748
7901 11:56:12.669302 Set Vref, RX VrefLevel [Byte0]: 42
7902 11:56:12.672193 [Byte1]: 42
7903 11:56:12.676115
7904 11:56:12.676665 Set Vref, RX VrefLevel [Byte0]: 43
7905 11:56:12.679804 [Byte1]: 43
7906 11:56:12.683928
7907 11:56:12.684430 Set Vref, RX VrefLevel [Byte0]: 44
7908 11:56:12.687270 [Byte1]: 44
7909 11:56:12.691378
7910 11:56:12.691940 Set Vref, RX VrefLevel [Byte0]: 45
7911 11:56:12.694490 [Byte1]: 45
7912 11:56:12.698642
7913 11:56:12.699138 Set Vref, RX VrefLevel [Byte0]: 46
7914 11:56:12.702032 [Byte1]: 46
7915 11:56:12.706597
7916 11:56:12.707086 Set Vref, RX VrefLevel [Byte0]: 47
7917 11:56:12.709833 [Byte1]: 47
7918 11:56:12.713985
7919 11:56:12.714437 Set Vref, RX VrefLevel [Byte0]: 48
7920 11:56:12.717628 [Byte1]: 48
7921 11:56:12.721734
7922 11:56:12.722287 Set Vref, RX VrefLevel [Byte0]: 49
7923 11:56:12.724831 [Byte1]: 49
7924 11:56:12.729348
7925 11:56:12.729804 Set Vref, RX VrefLevel [Byte0]: 50
7926 11:56:12.733354 [Byte1]: 50
7927 11:56:12.737300
7928 11:56:12.737755 Set Vref, RX VrefLevel [Byte0]: 51
7929 11:56:12.740144 [Byte1]: 51
7930 11:56:12.745219
7931 11:56:12.745777 Set Vref, RX VrefLevel [Byte0]: 52
7932 11:56:12.747947 [Byte1]: 52
7933 11:56:12.752133
7934 11:56:12.752546 Set Vref, RX VrefLevel [Byte0]: 53
7935 11:56:12.755563 [Byte1]: 53
7936 11:56:12.759461
7937 11:56:12.759874 Set Vref, RX VrefLevel [Byte0]: 54
7938 11:56:12.762846 [Byte1]: 54
7939 11:56:12.767338
7940 11:56:12.767753 Set Vref, RX VrefLevel [Byte0]: 55
7941 11:56:12.770393 [Byte1]: 55
7942 11:56:12.774783
7943 11:56:12.775238 Set Vref, RX VrefLevel [Byte0]: 56
7944 11:56:12.777991 [Byte1]: 56
7945 11:56:12.782686
7946 11:56:12.783152 Set Vref, RX VrefLevel [Byte0]: 57
7947 11:56:12.785707 [Byte1]: 57
7948 11:56:12.790039
7949 11:56:12.790449 Set Vref, RX VrefLevel [Byte0]: 58
7950 11:56:12.793459 [Byte1]: 58
7951 11:56:12.797656
7952 11:56:12.798172 Set Vref, RX VrefLevel [Byte0]: 59
7953 11:56:12.801691 [Byte1]: 59
7954 11:56:12.805506
7955 11:56:12.806072 Set Vref, RX VrefLevel [Byte0]: 60
7956 11:56:12.809260 [Byte1]: 60
7957 11:56:12.813463
7958 11:56:12.814030 Set Vref, RX VrefLevel [Byte0]: 61
7959 11:56:12.816837 [Byte1]: 61
7960 11:56:12.821303
7961 11:56:12.821858 Set Vref, RX VrefLevel [Byte0]: 62
7962 11:56:12.824885 [Byte1]: 62
7963 11:56:12.828301
7964 11:56:12.828851 Set Vref, RX VrefLevel [Byte0]: 63
7965 11:56:12.831480 [Byte1]: 63
7966 11:56:12.836187
7967 11:56:12.836764 Set Vref, RX VrefLevel [Byte0]: 64
7968 11:56:12.839595 [Byte1]: 64
7969 11:56:12.843417
7970 11:56:12.843872 Set Vref, RX VrefLevel [Byte0]: 65
7971 11:56:12.846744 [Byte1]: 65
7972 11:56:12.851345
7973 11:56:12.851908 Set Vref, RX VrefLevel [Byte0]: 66
7974 11:56:12.854380 [Byte1]: 66
7975 11:56:12.859013
7976 11:56:12.859575 Set Vref, RX VrefLevel [Byte0]: 67
7977 11:56:12.861921 [Byte1]: 67
7978 11:56:12.866951
7979 11:56:12.867509 Set Vref, RX VrefLevel [Byte0]: 68
7980 11:56:12.870149 [Byte1]: 68
7981 11:56:12.874300
7982 11:56:12.874909 Set Vref, RX VrefLevel [Byte0]: 69
7983 11:56:12.877482 [Byte1]: 69
7984 11:56:12.881940
7985 11:56:12.882502 Set Vref, RX VrefLevel [Byte0]: 70
7986 11:56:12.885024 [Byte1]: 70
7987 11:56:12.889315
7988 11:56:12.889927 Set Vref, RX VrefLevel [Byte0]: 71
7989 11:56:12.892640 [Byte1]: 71
7990 11:56:12.896693
7991 11:56:12.897147 Set Vref, RX VrefLevel [Byte0]: 72
7992 11:56:12.900189 [Byte1]: 72
7993 11:56:12.904621
7994 11:56:12.905075 Set Vref, RX VrefLevel [Byte0]: 73
7995 11:56:12.908167 [Byte1]: 73
7996 11:56:12.912578
7997 11:56:12.913135 Set Vref, RX VrefLevel [Byte0]: 74
7998 11:56:12.915342 [Byte1]: 74
7999 11:56:12.919796
8000 11:56:12.920361 Set Vref, RX VrefLevel [Byte0]: 75
8001 11:56:12.922982 [Byte1]: 75
8002 11:56:12.927486
8003 11:56:12.928048 Set Vref, RX VrefLevel [Byte0]: 76
8004 11:56:12.930495 [Byte1]: 76
8005 11:56:12.934853
8006 11:56:12.935461 Set Vref, RX VrefLevel [Byte0]: 77
8007 11:56:12.938401 [Byte1]: 77
8008 11:56:12.942339
8009 11:56:12.942790 Final RX Vref Byte 0 = 61 to rank0
8010 11:56:12.945882 Final RX Vref Byte 1 = 61 to rank0
8011 11:56:12.949656 Final RX Vref Byte 0 = 61 to rank1
8012 11:56:12.952471 Final RX Vref Byte 1 = 61 to rank1==
8013 11:56:12.956270 Dram Type= 6, Freq= 0, CH_0, rank 0
8014 11:56:12.959401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8015 11:56:12.962543 ==
8016 11:56:12.963154 DQS Delay:
8017 11:56:12.963525 DQS0 = 0, DQS1 = 0
8018 11:56:12.966522 DQM Delay:
8019 11:56:12.967121 DQM0 = 129, DQM1 = 121
8020 11:56:12.969684 DQ Delay:
8021 11:56:12.972902 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
8022 11:56:12.976492 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8023 11:56:12.979340 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
8024 11:56:12.983136 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
8025 11:56:12.983691
8026 11:56:12.984052
8027 11:56:12.984385
8028 11:56:12.986155 [DramC_TX_OE_Calibration] TA2
8029 11:56:12.989047 Original DQ_B0 (3 6) =30, OEN = 27
8030 11:56:12.992817 Original DQ_B1 (3 6) =30, OEN = 27
8031 11:56:12.995938 24, 0x0, End_B0=24 End_B1=24
8032 11:56:12.996403 25, 0x0, End_B0=25 End_B1=25
8033 11:56:12.999187 26, 0x0, End_B0=26 End_B1=26
8034 11:56:13.002697 27, 0x0, End_B0=27 End_B1=27
8035 11:56:13.005920 28, 0x0, End_B0=28 End_B1=28
8036 11:56:13.006482 29, 0x0, End_B0=29 End_B1=29
8037 11:56:13.009386 30, 0x0, End_B0=30 End_B1=30
8038 11:56:13.012695 31, 0x4141, End_B0=30 End_B1=30
8039 11:56:13.016361 Byte0 end_step=30 best_step=27
8040 11:56:13.019172 Byte1 end_step=30 best_step=27
8041 11:56:13.022684 Byte0 TX OE(2T, 0.5T) = (3, 3)
8042 11:56:13.023198 Byte1 TX OE(2T, 0.5T) = (3, 3)
8043 11:56:13.023565
8044 11:56:13.023902
8045 11:56:13.032608 [DQSOSCAuto] RK0, (LSB)MR18= 0x1307, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
8046 11:56:13.036116 CH0 RK0: MR19=303, MR18=1307
8047 11:56:13.039649 CH0_RK0: MR19=0x303, MR18=0x1307, DQSOSC=400, MR23=63, INC=23, DEC=15
8048 11:56:13.042931
8049 11:56:13.046117 ----->DramcWriteLeveling(PI) begin...
8050 11:56:13.046672 ==
8051 11:56:13.049610 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 11:56:13.052873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 11:56:13.053334 ==
8054 11:56:13.056085 Write leveling (Byte 0): 33 => 33
8055 11:56:13.059838 Write leveling (Byte 1): 25 => 25
8056 11:56:13.063417 DramcWriteLeveling(PI) end<-----
8057 11:56:13.063967
8058 11:56:13.064324 ==
8059 11:56:13.065918 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 11:56:13.069400 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 11:56:13.069862 ==
8062 11:56:13.072725 [Gating] SW mode calibration
8063 11:56:13.079556 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8064 11:56:13.086288 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8065 11:56:13.089724 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:56:13.093448 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:56:13.096604 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (0 0)
8068 11:56:13.103003 1 4 12 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8069 11:56:13.106182 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8070 11:56:13.109897 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8071 11:56:13.116052 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 11:56:13.119688 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 11:56:13.123358 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 11:56:13.129862 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8075 11:56:13.132930 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8076 11:56:13.136661 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8077 11:56:13.143465 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8078 11:56:13.146496 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8079 11:56:13.150040 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8080 11:56:13.156564 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 11:56:13.159449 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 11:56:13.162943 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 11:56:13.169672 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8084 11:56:13.173019 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8085 11:56:13.176779 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8086 11:56:13.180353 1 6 20 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8087 11:56:13.186583 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 11:56:13.189836 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 11:56:13.193149 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 11:56:13.199814 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8091 11:56:13.203518 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 11:56:13.206646 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8093 11:56:13.213001 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8094 11:56:13.216459 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 11:56:13.219795 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:56:13.227282 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:56:13.230229 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:56:13.233626 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:56:13.239580 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:56:13.243423 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:56:13.246433 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:56:13.253063 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:56:13.256628 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:56:13.259373 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:56:13.266340 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:56:13.270030 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8107 11:56:13.272942 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8108 11:56:13.276427 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8109 11:56:13.283073 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8110 11:56:13.286250 Total UI for P1: 0, mck2ui 16
8111 11:56:13.289485 best dqsien dly found for B0: ( 1, 9, 10)
8112 11:56:13.292938 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8113 11:56:13.296363 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8114 11:56:13.303015 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8115 11:56:13.306309 Total UI for P1: 0, mck2ui 16
8116 11:56:13.309654 best dqsien dly found for B1: ( 1, 9, 20)
8117 11:56:13.313574 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8118 11:56:13.316447 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8119 11:56:13.316929
8120 11:56:13.319642 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8121 11:56:13.323338 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8122 11:56:13.326645 [Gating] SW calibration Done
8123 11:56:13.327229 ==
8124 11:56:13.329694 Dram Type= 6, Freq= 0, CH_0, rank 1
8125 11:56:13.333139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8126 11:56:13.333712 ==
8127 11:56:13.336535 RX Vref Scan: 0
8128 11:56:13.337082
8129 11:56:13.337445 RX Vref 0 -> 0, step: 1
8130 11:56:13.337785
8131 11:56:13.339808 RX Delay 0 -> 252, step: 8
8132 11:56:13.342908 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8133 11:56:13.350373 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8134 11:56:13.353346 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8135 11:56:13.356495 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8136 11:56:13.359788 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8137 11:56:13.363395 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8138 11:56:13.369901 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8139 11:56:13.373303 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8140 11:56:13.377139 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8141 11:56:13.380279 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8142 11:56:13.383295 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8143 11:56:13.386828 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8144 11:56:13.393902 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8145 11:56:13.397022 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8146 11:56:13.400477 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8147 11:56:13.403271 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8148 11:56:13.403762 ==
8149 11:56:13.407047 Dram Type= 6, Freq= 0, CH_0, rank 1
8150 11:56:13.413466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8151 11:56:13.414086 ==
8152 11:56:13.414449 DQS Delay:
8153 11:56:13.417136 DQS0 = 0, DQS1 = 0
8154 11:56:13.417583 DQM Delay:
8155 11:56:13.418040 DQM0 = 131, DQM1 = 124
8156 11:56:13.419823 DQ Delay:
8157 11:56:13.423888 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8158 11:56:13.427010 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8159 11:56:13.430325 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =119
8160 11:56:13.433627 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =131
8161 11:56:13.434179
8162 11:56:13.434532
8163 11:56:13.434893 ==
8164 11:56:13.436959 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:56:13.440216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:56:13.443321 ==
8167 11:56:13.443868
8168 11:56:13.444223
8169 11:56:13.444552 TX Vref Scan disable
8170 11:56:13.447113 == TX Byte 0 ==
8171 11:56:13.450114 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8172 11:56:13.453560 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8173 11:56:13.456794 == TX Byte 1 ==
8174 11:56:13.460023 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8175 11:56:13.463074 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8176 11:56:13.463525 ==
8177 11:56:13.467154 Dram Type= 6, Freq= 0, CH_0, rank 1
8178 11:56:13.473691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8179 11:56:13.474144 ==
8180 11:56:13.487454
8181 11:56:13.490769 TX Vref early break, caculate TX vref
8182 11:56:13.494359 TX Vref=16, minBit 3, minWin=22, winSum=370
8183 11:56:13.497538 TX Vref=18, minBit 5, minWin=22, winSum=375
8184 11:56:13.501067 TX Vref=20, minBit 1, minWin=23, winSum=385
8185 11:56:13.503885 TX Vref=22, minBit 9, minWin=23, winSum=396
8186 11:56:13.507670 TX Vref=24, minBit 1, minWin=24, winSum=399
8187 11:56:13.511039 TX Vref=26, minBit 4, minWin=24, winSum=411
8188 11:56:13.517506 TX Vref=28, minBit 0, minWin=25, winSum=414
8189 11:56:13.521086 TX Vref=30, minBit 0, minWin=25, winSum=412
8190 11:56:13.524387 TX Vref=32, minBit 0, minWin=24, winSum=408
8191 11:56:13.527830 TX Vref=34, minBit 0, minWin=24, winSum=398
8192 11:56:13.530957 TX Vref=36, minBit 8, minWin=23, winSum=390
8193 11:56:13.537732 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 28
8194 11:56:13.538288
8195 11:56:13.540953 Final TX Range 0 Vref 28
8196 11:56:13.541584
8197 11:56:13.542139 ==
8198 11:56:13.543995 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 11:56:13.547768 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 11:56:13.548253 ==
8201 11:56:13.548613
8202 11:56:13.548941
8203 11:56:13.551131 TX Vref Scan disable
8204 11:56:13.558421 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8205 11:56:13.559030 == TX Byte 0 ==
8206 11:56:13.561024 u2DelayCellOfst[0]=14 cells (4 PI)
8207 11:56:13.564603 u2DelayCellOfst[1]=17 cells (5 PI)
8208 11:56:13.567427 u2DelayCellOfst[2]=10 cells (3 PI)
8209 11:56:13.571085 u2DelayCellOfst[3]=10 cells (3 PI)
8210 11:56:13.574044 u2DelayCellOfst[4]=7 cells (2 PI)
8211 11:56:13.578142 u2DelayCellOfst[5]=0 cells (0 PI)
8212 11:56:13.581588 u2DelayCellOfst[6]=17 cells (5 PI)
8213 11:56:13.582128 u2DelayCellOfst[7]=17 cells (5 PI)
8214 11:56:13.588156 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8215 11:56:13.590983 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8216 11:56:13.591522 == TX Byte 1 ==
8217 11:56:13.594269 u2DelayCellOfst[8]=3 cells (1 PI)
8218 11:56:13.597861 u2DelayCellOfst[9]=0 cells (0 PI)
8219 11:56:13.600887 u2DelayCellOfst[10]=7 cells (2 PI)
8220 11:56:13.604127 u2DelayCellOfst[11]=3 cells (1 PI)
8221 11:56:13.607493 u2DelayCellOfst[12]=14 cells (4 PI)
8222 11:56:13.611566 u2DelayCellOfst[13]=14 cells (4 PI)
8223 11:56:13.614570 u2DelayCellOfst[14]=17 cells (5 PI)
8224 11:56:13.618062 u2DelayCellOfst[15]=14 cells (4 PI)
8225 11:56:13.621027 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8226 11:56:13.624406 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8227 11:56:13.627517 DramC Write-DBI on
8228 11:56:13.627982 ==
8229 11:56:13.631578 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 11:56:13.634311 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 11:56:13.634903 ==
8232 11:56:13.635286
8233 11:56:13.637967
8234 11:56:13.638428 TX Vref Scan disable
8235 11:56:13.641047 == TX Byte 0 ==
8236 11:56:13.644016 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8237 11:56:13.648095 == TX Byte 1 ==
8238 11:56:13.651051 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8239 11:56:13.651507 DramC Write-DBI off
8240 11:56:13.651893
8241 11:56:13.654483 [DATLAT]
8242 11:56:13.654989 Freq=1600, CH0 RK1
8243 11:56:13.655464
8244 11:56:13.657804 DATLAT Default: 0xf
8245 11:56:13.658363 0, 0xFFFF, sum = 0
8246 11:56:13.660749 1, 0xFFFF, sum = 0
8247 11:56:13.661205 2, 0xFFFF, sum = 0
8248 11:56:13.664348 3, 0xFFFF, sum = 0
8249 11:56:13.665040 4, 0xFFFF, sum = 0
8250 11:56:13.667666 5, 0xFFFF, sum = 0
8251 11:56:13.668184 6, 0xFFFF, sum = 0
8252 11:56:13.670736 7, 0xFFFF, sum = 0
8253 11:56:13.674170 8, 0xFFFF, sum = 0
8254 11:56:13.674585 9, 0xFFFF, sum = 0
8255 11:56:13.677782 10, 0xFFFF, sum = 0
8256 11:56:13.678304 11, 0xFFFF, sum = 0
8257 11:56:13.681003 12, 0xFFFF, sum = 0
8258 11:56:13.681525 13, 0xFFFF, sum = 0
8259 11:56:13.684936 14, 0x0, sum = 1
8260 11:56:13.685459 15, 0x0, sum = 2
8261 11:56:13.688009 16, 0x0, sum = 3
8262 11:56:13.688529 17, 0x0, sum = 4
8263 11:56:13.688864 best_step = 15
8264 11:56:13.690836
8265 11:56:13.691306 ==
8266 11:56:13.694388 Dram Type= 6, Freq= 0, CH_0, rank 1
8267 11:56:13.697769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8268 11:56:13.698314 ==
8269 11:56:13.698646 RX Vref Scan: 0
8270 11:56:13.699016
8271 11:56:13.700789 RX Vref 0 -> 0, step: 1
8272 11:56:13.701194
8273 11:56:13.704434 RX Delay 11 -> 252, step: 4
8274 11:56:13.707855 iDelay=195, Bit 0, Center 126 (71 ~ 182) 112
8275 11:56:13.711109 iDelay=195, Bit 1, Center 130 (75 ~ 186) 112
8276 11:56:13.717648 iDelay=195, Bit 2, Center 126 (71 ~ 182) 112
8277 11:56:13.721596 iDelay=195, Bit 3, Center 126 (71 ~ 182) 112
8278 11:56:13.725231 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8279 11:56:13.727725 iDelay=195, Bit 5, Center 116 (63 ~ 170) 108
8280 11:56:13.731567 iDelay=195, Bit 6, Center 136 (79 ~ 194) 116
8281 11:56:13.738146 iDelay=195, Bit 7, Center 136 (83 ~ 190) 108
8282 11:56:13.741492 iDelay=195, Bit 8, Center 112 (59 ~ 166) 108
8283 11:56:13.744584 iDelay=195, Bit 9, Center 110 (55 ~ 166) 112
8284 11:56:13.748429 iDelay=195, Bit 10, Center 122 (67 ~ 178) 112
8285 11:56:13.751390 iDelay=195, Bit 11, Center 116 (63 ~ 170) 108
8286 11:56:13.758217 iDelay=195, Bit 12, Center 126 (75 ~ 178) 104
8287 11:56:13.761803 iDelay=195, Bit 13, Center 128 (75 ~ 182) 108
8288 11:56:13.764871 iDelay=195, Bit 14, Center 134 (79 ~ 190) 112
8289 11:56:13.768047 iDelay=195, Bit 15, Center 130 (75 ~ 186) 112
8290 11:56:13.768504 ==
8291 11:56:13.771169 Dram Type= 6, Freq= 0, CH_0, rank 1
8292 11:56:13.775000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8293 11:56:13.778200 ==
8294 11:56:13.778785 DQS Delay:
8295 11:56:13.779237 DQS0 = 0, DQS1 = 0
8296 11:56:13.781670 DQM Delay:
8297 11:56:13.782221 DQM0 = 128, DQM1 = 122
8298 11:56:13.784806 DQ Delay:
8299 11:56:13.788337 DQ0 =126, DQ1 =130, DQ2 =126, DQ3 =126
8300 11:56:13.791229 DQ4 =128, DQ5 =116, DQ6 =136, DQ7 =136
8301 11:56:13.794548 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8302 11:56:13.798522 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =130
8303 11:56:13.799214
8304 11:56:13.799803
8305 11:56:13.800250
8306 11:56:13.801130 [DramC_TX_OE_Calibration] TA2
8307 11:56:13.805037 Original DQ_B0 (3 6) =30, OEN = 27
8308 11:56:13.808564 Original DQ_B1 (3 6) =30, OEN = 27
8309 11:56:13.809149 24, 0x0, End_B0=24 End_B1=24
8310 11:56:13.811716 25, 0x0, End_B0=25 End_B1=25
8311 11:56:13.814964 26, 0x0, End_B0=26 End_B1=26
8312 11:56:13.818208 27, 0x0, End_B0=27 End_B1=27
8313 11:56:13.821504 28, 0x0, End_B0=28 End_B1=28
8314 11:56:13.821918 29, 0x0, End_B0=29 End_B1=29
8315 11:56:13.824659 30, 0x0, End_B0=30 End_B1=30
8316 11:56:13.827892 31, 0x4141, End_B0=30 End_B1=30
8317 11:56:13.831314 Byte0 end_step=30 best_step=27
8318 11:56:13.834652 Byte1 end_step=30 best_step=27
8319 11:56:13.838395 Byte0 TX OE(2T, 0.5T) = (3, 3)
8320 11:56:13.838800 Byte1 TX OE(2T, 0.5T) = (3, 3)
8321 11:56:13.839192
8322 11:56:13.839589
8323 11:56:13.848040 [DQSOSCAuto] RK1, (LSB)MR18= 0x190d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8324 11:56:13.851367 CH0 RK1: MR19=303, MR18=190D
8325 11:56:13.855140 CH0_RK1: MR19=0x303, MR18=0x190D, DQSOSC=397, MR23=63, INC=23, DEC=15
8326 11:56:13.858227 [RxdqsGatingPostProcess] freq 1600
8327 11:56:13.864613 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8328 11:56:13.868089 best DQS0 dly(2T, 0.5T) = (1, 1)
8329 11:56:13.871279 best DQS1 dly(2T, 0.5T) = (1, 1)
8330 11:56:13.874682 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8331 11:56:13.878299 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8332 11:56:13.881901 best DQS0 dly(2T, 0.5T) = (1, 1)
8333 11:56:13.882403 best DQS1 dly(2T, 0.5T) = (1, 1)
8334 11:56:13.884722 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8335 11:56:13.888757 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8336 11:56:13.891936 Pre-setting of DQS Precalculation
8337 11:56:13.897967 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8338 11:56:13.898372 ==
8339 11:56:13.901491 Dram Type= 6, Freq= 0, CH_1, rank 0
8340 11:56:13.904882 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8341 11:56:13.905314 ==
8342 11:56:13.911630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8343 11:56:13.914850 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8344 11:56:13.918331 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8345 11:56:13.925212 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8346 11:56:13.934434 [CA 0] Center 43 (15~72) winsize 58
8347 11:56:13.937218 [CA 1] Center 43 (14~72) winsize 59
8348 11:56:13.940450 [CA 2] Center 38 (10~67) winsize 58
8349 11:56:13.943778 [CA 3] Center 36 (7~66) winsize 60
8350 11:56:13.947178 [CA 4] Center 38 (9~68) winsize 60
8351 11:56:13.950413 [CA 5] Center 37 (8~66) winsize 59
8352 11:56:13.951047
8353 11:56:13.957094 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8354 11:56:13.957526
8355 11:56:13.957852 [CATrainingPosCal] consider 1 rank data
8356 11:56:13.960695 u2DelayCellTimex100 = 275/100 ps
8357 11:56:13.963526 CA0 delay=43 (15~72),Diff = 7 PI (24 cell)
8358 11:56:13.970535 CA1 delay=43 (14~72),Diff = 7 PI (24 cell)
8359 11:56:13.974176 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
8360 11:56:13.976918 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8361 11:56:13.980603 CA4 delay=38 (9~68),Diff = 2 PI (7 cell)
8362 11:56:13.983635 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8363 11:56:13.984047
8364 11:56:13.986980 CA PerBit enable=1, Macro0, CA PI delay=36
8365 11:56:13.987514
8366 11:56:13.990232 [CBTSetCACLKResult] CA Dly = 36
8367 11:56:13.993657 CS Dly: 8 (0~39)
8368 11:56:13.997613 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8369 11:56:14.000333 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8370 11:56:14.000750 ==
8371 11:56:14.003895 Dram Type= 6, Freq= 0, CH_1, rank 1
8372 11:56:14.007273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 11:56:14.007680 ==
8374 11:56:14.014276 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8375 11:56:14.017453 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8376 11:56:14.024170 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8377 11:56:14.027081 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8378 11:56:14.037624 [CA 0] Center 43 (14~73) winsize 60
8379 11:56:14.040424 [CA 1] Center 43 (15~72) winsize 58
8380 11:56:14.044315 [CA 2] Center 37 (8~67) winsize 60
8381 11:56:14.047145 [CA 3] Center 37 (9~66) winsize 58
8382 11:56:14.050494 [CA 4] Center 38 (9~68) winsize 60
8383 11:56:14.054802 [CA 5] Center 36 (7~66) winsize 60
8384 11:56:14.055359
8385 11:56:14.057042 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8386 11:56:14.057446
8387 11:56:14.061205 [CATrainingPosCal] consider 2 rank data
8388 11:56:14.064083 u2DelayCellTimex100 = 275/100 ps
8389 11:56:14.067261 CA0 delay=43 (15~72),Diff = 6 PI (21 cell)
8390 11:56:14.074554 CA1 delay=43 (15~72),Diff = 6 PI (21 cell)
8391 11:56:14.077440 CA2 delay=38 (10~67),Diff = 1 PI (3 cell)
8392 11:56:14.080709 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8393 11:56:14.084447 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8394 11:56:14.087839 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8395 11:56:14.088348
8396 11:56:14.090911 CA PerBit enable=1, Macro0, CA PI delay=37
8397 11:56:14.091326
8398 11:56:14.094114 [CBTSetCACLKResult] CA Dly = 37
8399 11:56:14.097537 CS Dly: 10 (0~44)
8400 11:56:14.100839 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8401 11:56:14.103868 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8402 11:56:14.104276
8403 11:56:14.107339 ----->DramcWriteLeveling(PI) begin...
8404 11:56:14.107853 ==
8405 11:56:14.110827 Dram Type= 6, Freq= 0, CH_1, rank 0
8406 11:56:14.114048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8407 11:56:14.117000 ==
8408 11:56:14.117402 Write leveling (Byte 0): 25 => 25
8409 11:56:14.120958 Write leveling (Byte 1): 28 => 28
8410 11:56:14.123731 DramcWriteLeveling(PI) end<-----
8411 11:56:14.124156
8412 11:56:14.124493 ==
8413 11:56:14.127444 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 11:56:14.134107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 11:56:14.134513 ==
8416 11:56:14.134833 [Gating] SW mode calibration
8417 11:56:14.144017 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8418 11:56:14.147232 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8419 11:56:14.150520 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:56:14.156914 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:56:14.160634 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 11:56:14.163619 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 11:56:14.170298 1 4 16 | B1->B0 | 2b2b 2525 | 1 0 | (0 0) (0 0)
8424 11:56:14.174006 1 4 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8425 11:56:14.176856 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 11:56:14.184154 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 11:56:14.187436 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 11:56:14.190536 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8429 11:56:14.196974 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8430 11:56:14.200509 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8431 11:56:14.203842 1 5 16 | B1->B0 | 3131 3333 | 0 0 | (1 0) (1 0)
8432 11:56:14.210446 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8433 11:56:14.213746 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 11:56:14.216907 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 11:56:14.223711 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 11:56:14.227171 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 11:56:14.230603 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8438 11:56:14.237290 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8439 11:56:14.240371 1 6 16 | B1->B0 | 3a3a 2d2d | 1 0 | (0 0) (0 0)
8440 11:56:14.243748 1 6 20 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8441 11:56:14.250372 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 11:56:14.253617 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 11:56:14.256895 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 11:56:14.260384 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8445 11:56:14.267220 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8446 11:56:14.270776 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8447 11:56:14.274103 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8448 11:56:14.280475 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8449 11:56:14.283861 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:56:14.287375 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:56:14.293960 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:56:14.297586 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:56:14.300676 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:56:14.307160 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:56:14.310353 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:56:14.313948 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:56:14.320515 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:56:14.323583 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:56:14.327062 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:56:14.334082 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8461 11:56:14.337761 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8462 11:56:14.340936 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8463 11:56:14.343879 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8464 11:56:14.350552 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8465 11:56:14.354260 Total UI for P1: 0, mck2ui 16
8466 11:56:14.356772 best dqsien dly found for B0: ( 1, 9, 14)
8467 11:56:14.360832 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8468 11:56:14.363798 Total UI for P1: 0, mck2ui 16
8469 11:56:14.367219 best dqsien dly found for B1: ( 1, 9, 16)
8470 11:56:14.370513 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8471 11:56:14.374348 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8472 11:56:14.374931
8473 11:56:14.377182 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8474 11:56:14.380489 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8475 11:56:14.384023 [Gating] SW calibration Done
8476 11:56:14.384575 ==
8477 11:56:14.387602 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 11:56:14.393734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 11:56:14.394311 ==
8480 11:56:14.394670 RX Vref Scan: 0
8481 11:56:14.395102
8482 11:56:14.397427 RX Vref 0 -> 0, step: 1
8483 11:56:14.397874
8484 11:56:14.401046 RX Delay 0 -> 252, step: 8
8485 11:56:14.403818 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8486 11:56:14.407169 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8487 11:56:14.410622 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8488 11:56:14.414166 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8489 11:56:14.420502 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8490 11:56:14.424276 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8491 11:56:14.427037 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8492 11:56:14.431003 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8493 11:56:14.433974 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8494 11:56:14.437854 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8495 11:56:14.444054 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8496 11:56:14.446960 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8497 11:56:14.450813 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8498 11:56:14.453945 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8499 11:56:14.460957 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8500 11:56:14.464466 iDelay=200, Bit 15, Center 131 (80 ~ 183) 104
8501 11:56:14.465024 ==
8502 11:56:14.467442 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 11:56:14.470683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 11:56:14.471280 ==
8505 11:56:14.471639 DQS Delay:
8506 11:56:14.474437 DQS0 = 0, DQS1 = 0
8507 11:56:14.474920 DQM Delay:
8508 11:56:14.477570 DQM0 = 134, DQM1 = 127
8509 11:56:14.478016 DQ Delay:
8510 11:56:14.480693 DQ0 =139, DQ1 =127, DQ2 =123, DQ3 =135
8511 11:56:14.484114 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8512 11:56:14.487317 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8513 11:56:14.490823 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8514 11:56:14.494488
8515 11:56:14.494993
8516 11:56:14.495499 ==
8517 11:56:14.497190 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 11:56:14.500620 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 11:56:14.501373 ==
8520 11:56:14.501761
8521 11:56:14.502097
8522 11:56:14.503861 TX Vref Scan disable
8523 11:56:14.504309 == TX Byte 0 ==
8524 11:56:14.511059 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8525 11:56:14.514789 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8526 11:56:14.515411 == TX Byte 1 ==
8527 11:56:14.521042 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8528 11:56:14.524246 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8529 11:56:14.524744 ==
8530 11:56:14.527355 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 11:56:14.531148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 11:56:14.531701 ==
8533 11:56:14.545069
8534 11:56:14.548198 TX Vref early break, caculate TX vref
8535 11:56:14.551482 TX Vref=16, minBit 8, minWin=21, winSum=361
8536 11:56:14.555099 TX Vref=18, minBit 8, minWin=20, winSum=370
8537 11:56:14.558611 TX Vref=20, minBit 8, minWin=22, winSum=382
8538 11:56:14.561544 TX Vref=22, minBit 8, minWin=23, winSum=390
8539 11:56:14.565061 TX Vref=24, minBit 5, minWin=24, winSum=402
8540 11:56:14.571824 TX Vref=26, minBit 8, minWin=24, winSum=409
8541 11:56:14.574797 TX Vref=28, minBit 8, minWin=24, winSum=415
8542 11:56:14.578481 TX Vref=30, minBit 8, minWin=24, winSum=413
8543 11:56:14.581907 TX Vref=32, minBit 8, minWin=24, winSum=406
8544 11:56:14.585364 TX Vref=34, minBit 8, minWin=23, winSum=396
8545 11:56:14.588584 TX Vref=36, minBit 8, minWin=22, winSum=388
8546 11:56:14.595531 [TxChooseVref] Worse bit 8, Min win 24, Win sum 415, Final Vref 28
8547 11:56:14.596204
8548 11:56:14.598547 Final TX Range 0 Vref 28
8549 11:56:14.599046
8550 11:56:14.599411 ==
8551 11:56:14.602006 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 11:56:14.605528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 11:56:14.605981 ==
8554 11:56:14.606355
8555 11:56:14.606683
8556 11:56:14.608608 TX Vref Scan disable
8557 11:56:14.615270 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8558 11:56:14.615948 == TX Byte 0 ==
8559 11:56:14.618991 u2DelayCellOfst[0]=14 cells (4 PI)
8560 11:56:14.621877 u2DelayCellOfst[1]=10 cells (3 PI)
8561 11:56:14.625768 u2DelayCellOfst[2]=0 cells (0 PI)
8562 11:56:14.628463 u2DelayCellOfst[3]=7 cells (2 PI)
8563 11:56:14.631705 u2DelayCellOfst[4]=10 cells (3 PI)
8564 11:56:14.635478 u2DelayCellOfst[5]=17 cells (5 PI)
8565 11:56:14.638762 u2DelayCellOfst[6]=17 cells (5 PI)
8566 11:56:14.639369 u2DelayCellOfst[7]=3 cells (1 PI)
8567 11:56:14.645532 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8568 11:56:14.649092 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8569 11:56:14.649649 == TX Byte 1 ==
8570 11:56:14.652325 u2DelayCellOfst[8]=0 cells (0 PI)
8571 11:56:14.655396 u2DelayCellOfst[9]=7 cells (2 PI)
8572 11:56:14.658635 u2DelayCellOfst[10]=14 cells (4 PI)
8573 11:56:14.661810 u2DelayCellOfst[11]=10 cells (3 PI)
8574 11:56:14.665266 u2DelayCellOfst[12]=14 cells (4 PI)
8575 11:56:14.668382 u2DelayCellOfst[13]=17 cells (5 PI)
8576 11:56:14.671802 u2DelayCellOfst[14]=17 cells (5 PI)
8577 11:56:14.675549 u2DelayCellOfst[15]=17 cells (5 PI)
8578 11:56:14.678639 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8579 11:56:14.682295 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8580 11:56:14.685598 DramC Write-DBI on
8581 11:56:14.686108 ==
8582 11:56:14.689150 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 11:56:14.692117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 11:56:14.692635 ==
8585 11:56:14.692965
8586 11:56:14.693268
8587 11:56:14.695234 TX Vref Scan disable
8588 11:56:14.698336 == TX Byte 0 ==
8589 11:56:14.701995 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8590 11:56:14.705417 == TX Byte 1 ==
8591 11:56:14.709040 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8592 11:56:14.709569 DramC Write-DBI off
8593 11:56:14.710012
8594 11:56:14.711774 [DATLAT]
8595 11:56:14.712195 Freq=1600, CH1 RK0
8596 11:56:14.712625
8597 11:56:14.715183 DATLAT Default: 0xf
8598 11:56:14.715602 0, 0xFFFF, sum = 0
8599 11:56:14.718650 1, 0xFFFF, sum = 0
8600 11:56:14.719228 2, 0xFFFF, sum = 0
8601 11:56:14.721857 3, 0xFFFF, sum = 0
8602 11:56:14.722334 4, 0xFFFF, sum = 0
8603 11:56:14.725881 5, 0xFFFF, sum = 0
8604 11:56:14.726415 6, 0xFFFF, sum = 0
8605 11:56:14.728951 7, 0xFFFF, sum = 0
8606 11:56:14.729484 8, 0xFFFF, sum = 0
8607 11:56:14.732161 9, 0xFFFF, sum = 0
8608 11:56:14.732709 10, 0xFFFF, sum = 0
8609 11:56:14.735507 11, 0xFFFF, sum = 0
8610 11:56:14.738972 12, 0xFFFF, sum = 0
8611 11:56:14.739502 13, 0xFFFF, sum = 0
8612 11:56:14.741942 14, 0x0, sum = 1
8613 11:56:14.742370 15, 0x0, sum = 2
8614 11:56:14.742806 16, 0x0, sum = 3
8615 11:56:14.745444 17, 0x0, sum = 4
8616 11:56:14.745870 best_step = 15
8617 11:56:14.746300
8618 11:56:14.746705 ==
8619 11:56:14.748812 Dram Type= 6, Freq= 0, CH_1, rank 0
8620 11:56:14.755862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8621 11:56:14.756436 ==
8622 11:56:14.756919 RX Vref Scan: 1
8623 11:56:14.757364
8624 11:56:14.758725 Set Vref Range= 24 -> 127
8625 11:56:14.759232
8626 11:56:14.762723 RX Vref 24 -> 127, step: 1
8627 11:56:14.763348
8628 11:56:14.765604 RX Delay 19 -> 252, step: 4
8629 11:56:14.766170
8630 11:56:14.768644 Set Vref, RX VrefLevel [Byte0]: 24
8631 11:56:14.772637 [Byte1]: 24
8632 11:56:14.773207
8633 11:56:14.775278 Set Vref, RX VrefLevel [Byte0]: 25
8634 11:56:14.778962 [Byte1]: 25
8635 11:56:14.779529
8636 11:56:14.781960 Set Vref, RX VrefLevel [Byte0]: 26
8637 11:56:14.785995 [Byte1]: 26
8638 11:56:14.786581
8639 11:56:14.788748 Set Vref, RX VrefLevel [Byte0]: 27
8640 11:56:14.792196 [Byte1]: 27
8641 11:56:14.796109
8642 11:56:14.796618 Set Vref, RX VrefLevel [Byte0]: 28
8643 11:56:14.799398 [Byte1]: 28
8644 11:56:14.803731
8645 11:56:14.804291 Set Vref, RX VrefLevel [Byte0]: 29
8646 11:56:14.806664 [Byte1]: 29
8647 11:56:14.810971
8648 11:56:14.811421 Set Vref, RX VrefLevel [Byte0]: 30
8649 11:56:14.814243 [Byte1]: 30
8650 11:56:14.818553
8651 11:56:14.819124 Set Vref, RX VrefLevel [Byte0]: 31
8652 11:56:14.822058 [Byte1]: 31
8653 11:56:14.826235
8654 11:56:14.826739 Set Vref, RX VrefLevel [Byte0]: 32
8655 11:56:14.829453 [Byte1]: 32
8656 11:56:14.833605
8657 11:56:14.834115 Set Vref, RX VrefLevel [Byte0]: 33
8658 11:56:14.837114 [Byte1]: 33
8659 11:56:14.841826
8660 11:56:14.842336 Set Vref, RX VrefLevel [Byte0]: 34
8661 11:56:14.844707 [Byte1]: 34
8662 11:56:14.849195
8663 11:56:14.849704 Set Vref, RX VrefLevel [Byte0]: 35
8664 11:56:14.852140 [Byte1]: 35
8665 11:56:14.856566
8666 11:56:14.857073 Set Vref, RX VrefLevel [Byte0]: 36
8667 11:56:14.860117 [Byte1]: 36
8668 11:56:14.864639
8669 11:56:14.865150 Set Vref, RX VrefLevel [Byte0]: 37
8670 11:56:14.867205 [Byte1]: 37
8671 11:56:14.871594
8672 11:56:14.872108 Set Vref, RX VrefLevel [Byte0]: 38
8673 11:56:14.874823 [Byte1]: 38
8674 11:56:14.879337
8675 11:56:14.879740 Set Vref, RX VrefLevel [Byte0]: 39
8676 11:56:14.882520 [Byte1]: 39
8677 11:56:14.886495
8678 11:56:14.886958 Set Vref, RX VrefLevel [Byte0]: 40
8679 11:56:14.890148 [Byte1]: 40
8680 11:56:14.894325
8681 11:56:14.894730 Set Vref, RX VrefLevel [Byte0]: 41
8682 11:56:14.897665 [Byte1]: 41
8683 11:56:14.901965
8684 11:56:14.902495 Set Vref, RX VrefLevel [Byte0]: 42
8685 11:56:14.904959 [Byte1]: 42
8686 11:56:14.909156
8687 11:56:14.909561 Set Vref, RX VrefLevel [Byte0]: 43
8688 11:56:14.913038 [Byte1]: 43
8689 11:56:14.916909
8690 11:56:14.917345 Set Vref, RX VrefLevel [Byte0]: 44
8691 11:56:14.920012 [Byte1]: 44
8692 11:56:14.924692
8693 11:56:14.925102 Set Vref, RX VrefLevel [Byte0]: 45
8694 11:56:14.928030 [Byte1]: 45
8695 11:56:14.932687
8696 11:56:14.933198 Set Vref, RX VrefLevel [Byte0]: 46
8697 11:56:14.935751 [Byte1]: 46
8698 11:56:14.939623
8699 11:56:14.940026 Set Vref, RX VrefLevel [Byte0]: 47
8700 11:56:14.943197 [Byte1]: 47
8701 11:56:14.947127
8702 11:56:14.947582 Set Vref, RX VrefLevel [Byte0]: 48
8703 11:56:14.950652 [Byte1]: 48
8704 11:56:14.954958
8705 11:56:14.955364 Set Vref, RX VrefLevel [Byte0]: 49
8706 11:56:14.958180 [Byte1]: 49
8707 11:56:14.962361
8708 11:56:14.962770 Set Vref, RX VrefLevel [Byte0]: 50
8709 11:56:14.965655 [Byte1]: 50
8710 11:56:14.970411
8711 11:56:14.970950 Set Vref, RX VrefLevel [Byte0]: 51
8712 11:56:14.973620 [Byte1]: 51
8713 11:56:14.977982
8714 11:56:14.978497 Set Vref, RX VrefLevel [Byte0]: 52
8715 11:56:14.981088 [Byte1]: 52
8716 11:56:14.985431
8717 11:56:14.985981 Set Vref, RX VrefLevel [Byte0]: 53
8718 11:56:14.989248 [Byte1]: 53
8719 11:56:14.992973
8720 11:56:14.993523 Set Vref, RX VrefLevel [Byte0]: 54
8721 11:56:14.996532 [Byte1]: 54
8722 11:56:15.000217
8723 11:56:15.000663 Set Vref, RX VrefLevel [Byte0]: 55
8724 11:56:15.003862 [Byte1]: 55
8725 11:56:15.008175
8726 11:56:15.008771 Set Vref, RX VrefLevel [Byte0]: 56
8727 11:56:15.011346 [Byte1]: 56
8728 11:56:15.015383
8729 11:56:15.015795 Set Vref, RX VrefLevel [Byte0]: 57
8730 11:56:15.018718 [Byte1]: 57
8731 11:56:15.023015
8732 11:56:15.023426 Set Vref, RX VrefLevel [Byte0]: 58
8733 11:56:15.026554 [Byte1]: 58
8734 11:56:15.030679
8735 11:56:15.031293 Set Vref, RX VrefLevel [Byte0]: 59
8736 11:56:15.034259 [Byte1]: 59
8737 11:56:15.038097
8738 11:56:15.038645 Set Vref, RX VrefLevel [Byte0]: 60
8739 11:56:15.041239 [Byte1]: 60
8740 11:56:15.045943
8741 11:56:15.046508 Set Vref, RX VrefLevel [Byte0]: 61
8742 11:56:15.048822 [Byte1]: 61
8743 11:56:15.053759
8744 11:56:15.054308 Set Vref, RX VrefLevel [Byte0]: 62
8745 11:56:15.056715 [Byte1]: 62
8746 11:56:15.061046
8747 11:56:15.061597 Set Vref, RX VrefLevel [Byte0]: 63
8748 11:56:15.064591 [Byte1]: 63
8749 11:56:15.068643
8750 11:56:15.069200 Set Vref, RX VrefLevel [Byte0]: 64
8751 11:56:15.072079 [Byte1]: 64
8752 11:56:15.076315
8753 11:56:15.076862 Set Vref, RX VrefLevel [Byte0]: 65
8754 11:56:15.079849 [Byte1]: 65
8755 11:56:15.084080
8756 11:56:15.084628 Set Vref, RX VrefLevel [Byte0]: 66
8757 11:56:15.087083 [Byte1]: 66
8758 11:56:15.091604
8759 11:56:15.092156 Set Vref, RX VrefLevel [Byte0]: 67
8760 11:56:15.094719 [Byte1]: 67
8761 11:56:15.099152
8762 11:56:15.099602 Set Vref, RX VrefLevel [Byte0]: 68
8763 11:56:15.101823 [Byte1]: 68
8764 11:56:15.106552
8765 11:56:15.107390 Set Vref, RX VrefLevel [Byte0]: 69
8766 11:56:15.109948 [Byte1]: 69
8767 11:56:15.113963
8768 11:56:15.114521 Set Vref, RX VrefLevel [Byte0]: 70
8769 11:56:15.117846 [Byte1]: 70
8770 11:56:15.121863
8771 11:56:15.122418 Set Vref, RX VrefLevel [Byte0]: 71
8772 11:56:15.124672 [Byte1]: 71
8773 11:56:15.129774
8774 11:56:15.130326 Set Vref, RX VrefLevel [Byte0]: 72
8775 11:56:15.132741 [Byte1]: 72
8776 11:56:15.136851
8777 11:56:15.137300 Set Vref, RX VrefLevel [Byte0]: 73
8778 11:56:15.140158 [Byte1]: 73
8779 11:56:15.144337
8780 11:56:15.144886 Set Vref, RX VrefLevel [Byte0]: 74
8781 11:56:15.147497 [Byte1]: 74
8782 11:56:15.151845
8783 11:56:15.152393 Set Vref, RX VrefLevel [Byte0]: 75
8784 11:56:15.155372 [Byte1]: 75
8785 11:56:15.159369
8786 11:56:15.160011 Set Vref, RX VrefLevel [Byte0]: 76
8787 11:56:15.162941 [Byte1]: 76
8788 11:56:15.166994
8789 11:56:15.167566 Final RX Vref Byte 0 = 62 to rank0
8790 11:56:15.170314 Final RX Vref Byte 1 = 58 to rank0
8791 11:56:15.173902 Final RX Vref Byte 0 = 62 to rank1
8792 11:56:15.177516 Final RX Vref Byte 1 = 58 to rank1==
8793 11:56:15.180536 Dram Type= 6, Freq= 0, CH_1, rank 0
8794 11:56:15.187139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8795 11:56:15.187698 ==
8796 11:56:15.188061 DQS Delay:
8797 11:56:15.188392 DQS0 = 0, DQS1 = 0
8798 11:56:15.190773 DQM Delay:
8799 11:56:15.191385 DQM0 = 131, DQM1 = 124
8800 11:56:15.193997 DQ Delay:
8801 11:56:15.197008 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =130
8802 11:56:15.200336 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =126
8803 11:56:15.203503 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =118
8804 11:56:15.207117 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8805 11:56:15.207700
8806 11:56:15.208064
8807 11:56:15.208397
8808 11:56:15.210389 [DramC_TX_OE_Calibration] TA2
8809 11:56:15.213950 Original DQ_B0 (3 6) =30, OEN = 27
8810 11:56:15.217622 Original DQ_B1 (3 6) =30, OEN = 27
8811 11:56:15.220540 24, 0x0, End_B0=24 End_B1=24
8812 11:56:15.221011 25, 0x0, End_B0=25 End_B1=25
8813 11:56:15.223494 26, 0x0, End_B0=26 End_B1=26
8814 11:56:15.227484 27, 0x0, End_B0=27 End_B1=27
8815 11:56:15.230743 28, 0x0, End_B0=28 End_B1=28
8816 11:56:15.231348 29, 0x0, End_B0=29 End_B1=29
8817 11:56:15.234083 30, 0x0, End_B0=30 End_B1=30
8818 11:56:15.237542 31, 0x4141, End_B0=30 End_B1=30
8819 11:56:15.240893 Byte0 end_step=30 best_step=27
8820 11:56:15.244146 Byte1 end_step=30 best_step=27
8821 11:56:15.247124 Byte0 TX OE(2T, 0.5T) = (3, 3)
8822 11:56:15.247677 Byte1 TX OE(2T, 0.5T) = (3, 3)
8823 11:56:15.248038
8824 11:56:15.248370
8825 11:56:15.256809 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8826 11:56:15.260426 CH1 RK0: MR19=303, MR18=1600
8827 11:56:15.266918 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8828 11:56:15.267334
8829 11:56:15.270059 ----->DramcWriteLeveling(PI) begin...
8830 11:56:15.270480 ==
8831 11:56:15.273726 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 11:56:15.276880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 11:56:15.277174 ==
8834 11:56:15.280502 Write leveling (Byte 0): 26 => 26
8835 11:56:15.283911 Write leveling (Byte 1): 26 => 26
8836 11:56:15.287134 DramcWriteLeveling(PI) end<-----
8837 11:56:15.287521
8838 11:56:15.287760 ==
8839 11:56:15.290281 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 11:56:15.293852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 11:56:15.294238 ==
8842 11:56:15.296804 [Gating] SW mode calibration
8843 11:56:15.303552 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8844 11:56:15.310111 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8845 11:56:15.313823 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8846 11:56:15.317565 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8847 11:56:15.324126 1 4 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
8848 11:56:15.327784 1 4 12 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8849 11:56:15.331014 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8850 11:56:15.333907 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8851 11:56:15.340715 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8852 11:56:15.343700 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8853 11:56:15.347523 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8854 11:56:15.354012 1 5 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8855 11:56:15.357584 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 0)
8856 11:56:15.360819 1 5 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8857 11:56:15.367629 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8858 11:56:15.370500 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8859 11:56:15.373977 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8860 11:56:15.380540 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8861 11:56:15.384059 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8862 11:56:15.387264 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8863 11:56:15.393716 1 6 8 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
8864 11:56:15.397312 1 6 12 | B1->B0 | 3636 4545 | 0 0 | (0 0) (0 0)
8865 11:56:15.400356 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8866 11:56:15.407099 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8867 11:56:15.410834 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8868 11:56:15.414070 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8869 11:56:15.420369 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8870 11:56:15.424244 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8871 11:56:15.427259 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8872 11:56:15.433691 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8873 11:56:15.437005 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8874 11:56:15.440880 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:56:15.444144 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:56:15.450586 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 11:56:15.454370 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 11:56:15.457402 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 11:56:15.464188 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8880 11:56:15.467034 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8881 11:56:15.470455 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8882 11:56:15.477354 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8883 11:56:15.480831 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8884 11:56:15.484239 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8885 11:56:15.490752 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8886 11:56:15.494253 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8887 11:56:15.497077 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8888 11:56:15.503946 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8889 11:56:15.504402 Total UI for P1: 0, mck2ui 16
8890 11:56:15.510418 best dqsien dly found for B0: ( 1, 9, 6)
8891 11:56:15.514504 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 11:56:15.517505 Total UI for P1: 0, mck2ui 16
8893 11:56:15.520644 best dqsien dly found for B1: ( 1, 9, 12)
8894 11:56:15.523619 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8895 11:56:15.527627 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8896 11:56:15.528175
8897 11:56:15.531092 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8898 11:56:15.534372 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8899 11:56:15.537772 [Gating] SW calibration Done
8900 11:56:15.538322 ==
8901 11:56:15.540991 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 11:56:15.543740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 11:56:15.544200 ==
8904 11:56:15.547539 RX Vref Scan: 0
8905 11:56:15.548084
8906 11:56:15.550484 RX Vref 0 -> 0, step: 1
8907 11:56:15.551068
8908 11:56:15.551431 RX Delay 0 -> 252, step: 8
8909 11:56:15.557298 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8910 11:56:15.560534 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8911 11:56:15.564038 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8912 11:56:15.567568 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8913 11:56:15.570985 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8914 11:56:15.574643 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8915 11:56:15.580663 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8916 11:56:15.584727 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8917 11:56:15.587848 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8918 11:56:15.590654 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8919 11:56:15.594510 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8920 11:56:15.600656 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8921 11:56:15.603812 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8922 11:56:15.607859 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8923 11:56:15.610911 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8924 11:56:15.614493 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8925 11:56:15.617709 ==
8926 11:56:15.620919 Dram Type= 6, Freq= 0, CH_1, rank 1
8927 11:56:15.624206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8928 11:56:15.624757 ==
8929 11:56:15.625122 DQS Delay:
8930 11:56:15.627389 DQS0 = 0, DQS1 = 0
8931 11:56:15.627843 DQM Delay:
8932 11:56:15.630752 DQM0 = 133, DQM1 = 128
8933 11:56:15.631376 DQ Delay:
8934 11:56:15.634295 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =135
8935 11:56:15.637576 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8936 11:56:15.641281 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8937 11:56:15.643826 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8938 11:56:15.644283
8939 11:56:15.644637
8940 11:56:15.644966 ==
8941 11:56:15.647470 Dram Type= 6, Freq= 0, CH_1, rank 1
8942 11:56:15.654017 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8943 11:56:15.654573 ==
8944 11:56:15.654995
8945 11:56:15.655393
8946 11:56:15.655916 TX Vref Scan disable
8947 11:56:15.657330 == TX Byte 0 ==
8948 11:56:15.660889 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8949 11:56:15.664253 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8950 11:56:15.667509 == TX Byte 1 ==
8951 11:56:15.670941 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8952 11:56:15.674780 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8953 11:56:15.677738 ==
8954 11:56:15.681157 Dram Type= 6, Freq= 0, CH_1, rank 1
8955 11:56:15.684048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8956 11:56:15.684507 ==
8957 11:56:15.697164
8958 11:56:15.701073 TX Vref early break, caculate TX vref
8959 11:56:15.703909 TX Vref=16, minBit 8, minWin=22, winSum=381
8960 11:56:15.707553 TX Vref=18, minBit 8, minWin=23, winSum=389
8961 11:56:15.710562 TX Vref=20, minBit 8, minWin=23, winSum=392
8962 11:56:15.714058 TX Vref=22, minBit 8, minWin=24, winSum=401
8963 11:56:15.717170 TX Vref=24, minBit 0, minWin=25, winSum=413
8964 11:56:15.724331 TX Vref=26, minBit 8, minWin=25, winSum=420
8965 11:56:15.727602 TX Vref=28, minBit 0, minWin=25, winSum=422
8966 11:56:15.731097 TX Vref=30, minBit 4, minWin=25, winSum=424
8967 11:56:15.733875 TX Vref=32, minBit 0, minWin=25, winSum=416
8968 11:56:15.737852 TX Vref=34, minBit 0, minWin=24, winSum=406
8969 11:56:15.740868 TX Vref=36, minBit 0, minWin=23, winSum=395
8970 11:56:15.747201 [TxChooseVref] Worse bit 4, Min win 25, Win sum 424, Final Vref 30
8971 11:56:15.747651
8972 11:56:15.751236 Final TX Range 0 Vref 30
8973 11:56:15.751789
8974 11:56:15.752145 ==
8975 11:56:15.754207 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 11:56:15.757136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 11:56:15.757590 ==
8978 11:56:15.757949
8979 11:56:15.758276
8980 11:56:15.761148 TX Vref Scan disable
8981 11:56:15.767731 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8982 11:56:15.768394 == TX Byte 0 ==
8983 11:56:15.770843 u2DelayCellOfst[0]=17 cells (5 PI)
8984 11:56:15.774239 u2DelayCellOfst[1]=10 cells (3 PI)
8985 11:56:15.777199 u2DelayCellOfst[2]=0 cells (0 PI)
8986 11:56:15.780669 u2DelayCellOfst[3]=7 cells (2 PI)
8987 11:56:15.784113 u2DelayCellOfst[4]=10 cells (3 PI)
8988 11:56:15.787640 u2DelayCellOfst[5]=21 cells (6 PI)
8989 11:56:15.790721 u2DelayCellOfst[6]=17 cells (5 PI)
8990 11:56:15.791200 u2DelayCellOfst[7]=7 cells (2 PI)
8991 11:56:15.798203 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8992 11:56:15.800880 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8993 11:56:15.801622 == TX Byte 1 ==
8994 11:56:15.804130 u2DelayCellOfst[8]=0 cells (0 PI)
8995 11:56:15.807409 u2DelayCellOfst[9]=3 cells (1 PI)
8996 11:56:15.810684 u2DelayCellOfst[10]=10 cells (3 PI)
8997 11:56:15.814622 u2DelayCellOfst[11]=7 cells (2 PI)
8998 11:56:15.817990 u2DelayCellOfst[12]=14 cells (4 PI)
8999 11:56:15.821106 u2DelayCellOfst[13]=17 cells (5 PI)
9000 11:56:15.824279 u2DelayCellOfst[14]=17 cells (5 PI)
9001 11:56:15.827538 u2DelayCellOfst[15]=17 cells (5 PI)
9002 11:56:15.830974 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9003 11:56:15.834569 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9004 11:56:15.837981 DramC Write-DBI on
9005 11:56:15.838512 ==
9006 11:56:15.840720 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 11:56:15.844308 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 11:56:15.844870 ==
9009 11:56:15.845228
9010 11:56:15.847745
9011 11:56:15.848294 TX Vref Scan disable
9012 11:56:15.851460 == TX Byte 0 ==
9013 11:56:15.854508 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9014 11:56:15.857661 == TX Byte 1 ==
9015 11:56:15.860611 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9016 11:56:15.861062 DramC Write-DBI off
9017 11:56:15.861420
9018 11:56:15.864218 [DATLAT]
9019 11:56:15.864667 Freq=1600, CH1 RK1
9020 11:56:15.865025
9021 11:56:15.867977 DATLAT Default: 0xf
9022 11:56:15.868424 0, 0xFFFF, sum = 0
9023 11:56:15.871146 1, 0xFFFF, sum = 0
9024 11:56:15.871606 2, 0xFFFF, sum = 0
9025 11:56:15.874228 3, 0xFFFF, sum = 0
9026 11:56:15.874639 4, 0xFFFF, sum = 0
9027 11:56:15.877888 5, 0xFFFF, sum = 0
9028 11:56:15.878298 6, 0xFFFF, sum = 0
9029 11:56:15.880823 7, 0xFFFF, sum = 0
9030 11:56:15.881236 8, 0xFFFF, sum = 0
9031 11:56:15.884332 9, 0xFFFF, sum = 0
9032 11:56:15.884745 10, 0xFFFF, sum = 0
9033 11:56:15.887850 11, 0xFFFF, sum = 0
9034 11:56:15.891383 12, 0xFFFF, sum = 0
9035 11:56:15.891792 13, 0xFFFF, sum = 0
9036 11:56:15.894938 14, 0x0, sum = 1
9037 11:56:15.895351 15, 0x0, sum = 2
9038 11:56:15.895677 16, 0x0, sum = 3
9039 11:56:15.898067 17, 0x0, sum = 4
9040 11:56:15.898517 best_step = 15
9041 11:56:15.898849
9042 11:56:15.899199 ==
9043 11:56:15.900909 Dram Type= 6, Freq= 0, CH_1, rank 1
9044 11:56:15.907656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9045 11:56:15.908065 ==
9046 11:56:15.908389 RX Vref Scan: 0
9047 11:56:15.908692
9048 11:56:15.911215 RX Vref 0 -> 0, step: 1
9049 11:56:15.911756
9050 11:56:15.914316 RX Delay 11 -> 252, step: 4
9051 11:56:15.918217 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
9052 11:56:15.921384 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
9053 11:56:15.925046 iDelay=191, Bit 2, Center 118 (67 ~ 170) 104
9054 11:56:15.931356 iDelay=191, Bit 3, Center 128 (75 ~ 182) 108
9055 11:56:15.934311 iDelay=191, Bit 4, Center 130 (79 ~ 182) 104
9056 11:56:15.937757 iDelay=191, Bit 5, Center 142 (95 ~ 190) 96
9057 11:56:15.941749 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
9058 11:56:15.945051 iDelay=191, Bit 7, Center 126 (75 ~ 178) 104
9059 11:56:15.951519 iDelay=191, Bit 8, Center 114 (59 ~ 170) 112
9060 11:56:15.955249 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
9061 11:56:15.957752 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
9062 11:56:15.962071 iDelay=191, Bit 11, Center 118 (63 ~ 174) 112
9063 11:56:15.965054 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
9064 11:56:15.971338 iDelay=191, Bit 13, Center 136 (87 ~ 186) 100
9065 11:56:15.974848 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
9066 11:56:15.978068 iDelay=191, Bit 15, Center 136 (83 ~ 190) 108
9067 11:56:15.978603 ==
9068 11:56:15.981418 Dram Type= 6, Freq= 0, CH_1, rank 1
9069 11:56:15.984703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9070 11:56:15.985115 ==
9071 11:56:15.988365 DQS Delay:
9072 11:56:15.988772 DQS0 = 0, DQS1 = 0
9073 11:56:15.991362 DQM Delay:
9074 11:56:15.991764 DQM0 = 129, DQM1 = 126
9075 11:56:15.992083 DQ Delay:
9076 11:56:15.994523 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =128
9077 11:56:16.001454 DQ4 =130, DQ5 =142, DQ6 =138, DQ7 =126
9078 11:56:16.004446 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9079 11:56:16.008069 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =136
9080 11:56:16.008487
9081 11:56:16.008811
9082 11:56:16.009110
9083 11:56:16.011151 [DramC_TX_OE_Calibration] TA2
9084 11:56:16.014437 Original DQ_B0 (3 6) =30, OEN = 27
9085 11:56:16.017934 Original DQ_B1 (3 6) =30, OEN = 27
9086 11:56:16.018346 24, 0x0, End_B0=24 End_B1=24
9087 11:56:16.021507 25, 0x0, End_B0=25 End_B1=25
9088 11:56:16.024820 26, 0x0, End_B0=26 End_B1=26
9089 11:56:16.028275 27, 0x0, End_B0=27 End_B1=27
9090 11:56:16.028693 28, 0x0, End_B0=28 End_B1=28
9091 11:56:16.031531 29, 0x0, End_B0=29 End_B1=29
9092 11:56:16.034692 30, 0x0, End_B0=30 End_B1=30
9093 11:56:16.037915 31, 0x4141, End_B0=30 End_B1=30
9094 11:56:16.041570 Byte0 end_step=30 best_step=27
9095 11:56:16.044982 Byte1 end_step=30 best_step=27
9096 11:56:16.045394 Byte0 TX OE(2T, 0.5T) = (3, 3)
9097 11:56:16.047918 Byte1 TX OE(2T, 0.5T) = (3, 3)
9098 11:56:16.048333
9099 11:56:16.048657
9100 11:56:16.058280 [DQSOSCAuto] RK1, (LSB)MR18= 0x1319, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 400 ps
9101 11:56:16.061438 CH1 RK1: MR19=303, MR18=1319
9102 11:56:16.064796 CH1_RK1: MR19=0x303, MR18=0x1319, DQSOSC=397, MR23=63, INC=23, DEC=15
9103 11:56:16.068082 [RxdqsGatingPostProcess] freq 1600
9104 11:56:16.074952 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9105 11:56:16.078224 best DQS0 dly(2T, 0.5T) = (1, 1)
9106 11:56:16.081463 best DQS1 dly(2T, 0.5T) = (1, 1)
9107 11:56:16.084901 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9108 11:56:16.088263 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9109 11:56:16.088782 best DQS0 dly(2T, 0.5T) = (1, 1)
9110 11:56:16.091581 best DQS1 dly(2T, 0.5T) = (1, 1)
9111 11:56:16.094713 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9112 11:56:16.097906 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9113 11:56:16.101339 Pre-setting of DQS Precalculation
9114 11:56:16.107865 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9115 11:56:16.115151 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9116 11:56:16.121588 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9117 11:56:16.121997
9118 11:56:16.122315
9119 11:56:16.124944 [Calibration Summary] 3200 Mbps
9120 11:56:16.125352 CH 0, Rank 0
9121 11:56:16.128458 SW Impedance : PASS
9122 11:56:16.131674 DUTY Scan : NO K
9123 11:56:16.132086 ZQ Calibration : PASS
9124 11:56:16.134914 Jitter Meter : NO K
9125 11:56:16.137967 CBT Training : PASS
9126 11:56:16.138373 Write leveling : PASS
9127 11:56:16.141443 RX DQS gating : PASS
9128 11:56:16.141952 RX DQ/DQS(RDDQC) : PASS
9129 11:56:16.145174 TX DQ/DQS : PASS
9130 11:56:16.148440 RX DATLAT : PASS
9131 11:56:16.148856 RX DQ/DQS(Engine): PASS
9132 11:56:16.151652 TX OE : PASS
9133 11:56:16.152164 All Pass.
9134 11:56:16.152490
9135 11:56:16.155339 CH 0, Rank 1
9136 11:56:16.155853 SW Impedance : PASS
9137 11:56:16.158283 DUTY Scan : NO K
9138 11:56:16.161949 ZQ Calibration : PASS
9139 11:56:16.162465 Jitter Meter : NO K
9140 11:56:16.165422 CBT Training : PASS
9141 11:56:16.168705 Write leveling : PASS
9142 11:56:16.169220 RX DQS gating : PASS
9143 11:56:16.171488 RX DQ/DQS(RDDQC) : PASS
9144 11:56:16.174992 TX DQ/DQS : PASS
9145 11:56:16.175409 RX DATLAT : PASS
9146 11:56:16.178773 RX DQ/DQS(Engine): PASS
9147 11:56:16.179328 TX OE : PASS
9148 11:56:16.181576 All Pass.
9149 11:56:16.182041
9150 11:56:16.182384 CH 1, Rank 0
9151 11:56:16.185552 SW Impedance : PASS
9152 11:56:16.186101 DUTY Scan : NO K
9153 11:56:16.188897 ZQ Calibration : PASS
9154 11:56:16.191948 Jitter Meter : NO K
9155 11:56:16.192472 CBT Training : PASS
9156 11:56:16.195156 Write leveling : PASS
9157 11:56:16.199046 RX DQS gating : PASS
9158 11:56:16.199606 RX DQ/DQS(RDDQC) : PASS
9159 11:56:16.201843 TX DQ/DQS : PASS
9160 11:56:16.205027 RX DATLAT : PASS
9161 11:56:16.205500 RX DQ/DQS(Engine): PASS
9162 11:56:16.209039 TX OE : PASS
9163 11:56:16.209596 All Pass.
9164 11:56:16.209953
9165 11:56:16.211953 CH 1, Rank 1
9166 11:56:16.212407 SW Impedance : PASS
9167 11:56:16.215276 DUTY Scan : NO K
9168 11:56:16.218758 ZQ Calibration : PASS
9169 11:56:16.219269 Jitter Meter : NO K
9170 11:56:16.222029 CBT Training : PASS
9171 11:56:16.222578 Write leveling : PASS
9172 11:56:16.225787 RX DQS gating : PASS
9173 11:56:16.229226 RX DQ/DQS(RDDQC) : PASS
9174 11:56:16.229780 TX DQ/DQS : PASS
9175 11:56:16.232286 RX DATLAT : PASS
9176 11:56:16.235120 RX DQ/DQS(Engine): PASS
9177 11:56:16.235575 TX OE : PASS
9178 11:56:16.238618 All Pass.
9179 11:56:16.239227
9180 11:56:16.239593 DramC Write-DBI on
9181 11:56:16.242405 PER_BANK_REFRESH: Hybrid Mode
9182 11:56:16.243011 TX_TRACKING: ON
9183 11:56:16.252103 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9184 11:56:16.261892 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9185 11:56:16.268757 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9186 11:56:16.271876 [FAST_K] Save calibration result to emmc
9187 11:56:16.275406 sync common calibartion params.
9188 11:56:16.275859 sync cbt_mode0:1, 1:1
9189 11:56:16.278837 dram_init: ddr_geometry: 2
9190 11:56:16.282070 dram_init: ddr_geometry: 2
9191 11:56:16.282526 dram_init: ddr_geometry: 2
9192 11:56:16.285191 0:dram_rank_size:100000000
9193 11:56:16.289203 1:dram_rank_size:100000000
9194 11:56:16.295630 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9195 11:56:16.296183 DFS_SHUFFLE_HW_MODE: ON
9196 11:56:16.299130 dramc_set_vcore_voltage set vcore to 725000
9197 11:56:16.302442 Read voltage for 1600, 0
9198 11:56:16.303069 Vio18 = 0
9199 11:56:16.305758 Vcore = 725000
9200 11:56:16.306364 Vdram = 0
9201 11:56:16.306770 Vddq = 0
9202 11:56:16.309108 Vmddr = 0
9203 11:56:16.309658 switch to 3200 Mbps bootup
9204 11:56:16.312288 [DramcRunTimeConfig]
9205 11:56:16.312833 PHYPLL
9206 11:56:16.315345 DPM_CONTROL_AFTERK: ON
9207 11:56:16.315801 PER_BANK_REFRESH: ON
9208 11:56:16.318647 REFRESH_OVERHEAD_REDUCTION: ON
9209 11:56:16.322246 CMD_PICG_NEW_MODE: OFF
9210 11:56:16.322793 XRTWTW_NEW_MODE: ON
9211 11:56:16.325286 XRTRTR_NEW_MODE: ON
9212 11:56:16.325842 TX_TRACKING: ON
9213 11:56:16.329058 RDSEL_TRACKING: OFF
9214 11:56:16.332189 DQS Precalculation for DVFS: ON
9215 11:56:16.332739 RX_TRACKING: OFF
9216 11:56:16.336112 HW_GATING DBG: ON
9217 11:56:16.336666 ZQCS_ENABLE_LP4: ON
9218 11:56:16.338574 RX_PICG_NEW_MODE: ON
9219 11:56:16.339063 TX_PICG_NEW_MODE: ON
9220 11:56:16.342650 ENABLE_RX_DCM_DPHY: ON
9221 11:56:16.345295 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9222 11:56:16.345843 DUMMY_READ_FOR_TRACKING: OFF
9223 11:56:16.348956 !!! SPM_CONTROL_AFTERK: OFF
9224 11:56:16.352631 !!! SPM could not control APHY
9225 11:56:16.355493 IMPEDANCE_TRACKING: ON
9226 11:56:16.355946 TEMP_SENSOR: ON
9227 11:56:16.359364 HW_SAVE_FOR_SR: OFF
9228 11:56:16.362248 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9229 11:56:16.365472 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9230 11:56:16.365923 Read ODT Tracking: ON
9231 11:56:16.368903 Refresh Rate DeBounce: ON
9232 11:56:16.372354 DFS_NO_QUEUE_FLUSH: ON
9233 11:56:16.372761 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9234 11:56:16.376127 ENABLE_DFS_RUNTIME_MRW: OFF
9235 11:56:16.379154 DDR_RESERVE_NEW_MODE: ON
9236 11:56:16.382044 MR_CBT_SWITCH_FREQ: ON
9237 11:56:16.382455 =========================
9238 11:56:16.402335 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9239 11:56:16.405115 dram_init: ddr_geometry: 2
9240 11:56:16.423837 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9241 11:56:16.427298 dram_init: dram init end (result: 0)
9242 11:56:16.433829 DRAM-K: Full calibration passed in 24584 msecs
9243 11:56:16.437412 MRC: failed to locate region type 0.
9244 11:56:16.437960 DRAM rank0 size:0x100000000,
9245 11:56:16.440762 DRAM rank1 size=0x100000000
9246 11:56:16.450488 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9247 11:56:16.457327 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9248 11:56:16.463705 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9249 11:56:16.470412 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9250 11:56:16.473378 DRAM rank0 size:0x100000000,
9251 11:56:16.477344 DRAM rank1 size=0x100000000
9252 11:56:16.477897 CBMEM:
9253 11:56:16.481028 IMD: root @ 0xfffff000 254 entries.
9254 11:56:16.483699 IMD: root @ 0xffffec00 62 entries.
9255 11:56:16.486973 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9256 11:56:16.490361 WARNING: RO_VPD is uninitialized or empty.
9257 11:56:16.496767 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9258 11:56:16.503277 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9259 11:56:16.516347 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9260 11:56:16.527911 BS: romstage times (exec / console): total (unknown) / 24091 ms
9261 11:56:16.528470
9262 11:56:16.528826
9263 11:56:16.537976 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9264 11:56:16.540904 ARM64: Exception handlers installed.
9265 11:56:16.544771 ARM64: Testing exception
9266 11:56:16.547776 ARM64: Done test exception
9267 11:56:16.548354 Enumerating buses...
9268 11:56:16.551323 Show all devs... Before device enumeration.
9269 11:56:16.554608 Root Device: enabled 1
9270 11:56:16.557737 CPU_CLUSTER: 0: enabled 1
9271 11:56:16.558290 CPU: 00: enabled 1
9272 11:56:16.561476 Compare with tree...
9273 11:56:16.561926 Root Device: enabled 1
9274 11:56:16.564990 CPU_CLUSTER: 0: enabled 1
9275 11:56:16.567972 CPU: 00: enabled 1
9276 11:56:16.568425 Root Device scanning...
9277 11:56:16.571251 scan_static_bus for Root Device
9278 11:56:16.574840 CPU_CLUSTER: 0 enabled
9279 11:56:16.578306 scan_static_bus for Root Device done
9280 11:56:16.581720 scan_bus: bus Root Device finished in 8 msecs
9281 11:56:16.582279 done
9282 11:56:16.587735 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9283 11:56:16.591536 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9284 11:56:16.597543 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9285 11:56:16.601082 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9286 11:56:16.604943 Allocating resources...
9287 11:56:16.605547 Reading resources...
9288 11:56:16.611293 Root Device read_resources bus 0 link: 0
9289 11:56:16.611772 DRAM rank0 size:0x100000000,
9290 11:56:16.614198 DRAM rank1 size=0x100000000
9291 11:56:16.617300 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9292 11:56:16.621041 CPU: 00 missing read_resources
9293 11:56:16.624783 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9294 11:56:16.631339 Root Device read_resources bus 0 link: 0 done
9295 11:56:16.631890 Done reading resources.
9296 11:56:16.638041 Show resources in subtree (Root Device)...After reading.
9297 11:56:16.640780 Root Device child on link 0 CPU_CLUSTER: 0
9298 11:56:16.644334 CPU_CLUSTER: 0 child on link 0 CPU: 00
9299 11:56:16.653844 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9300 11:56:16.654395 CPU: 00
9301 11:56:16.657412 Root Device assign_resources, bus 0 link: 0
9302 11:56:16.660872 CPU_CLUSTER: 0 missing set_resources
9303 11:56:16.663818 Root Device assign_resources, bus 0 link: 0 done
9304 11:56:16.667445 Done setting resources.
9305 11:56:16.674175 Show resources in subtree (Root Device)...After assigning values.
9306 11:56:16.677701 Root Device child on link 0 CPU_CLUSTER: 0
9307 11:56:16.681146 CPU_CLUSTER: 0 child on link 0 CPU: 00
9308 11:56:16.690985 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9309 11:56:16.691547 CPU: 00
9310 11:56:16.694046 Done allocating resources.
9311 11:56:16.697688 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9312 11:56:16.700489 Enabling resources...
9313 11:56:16.701030 done.
9314 11:56:16.707062 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9315 11:56:16.707518 Initializing devices...
9316 11:56:16.710820 Root Device init
9317 11:56:16.711312 init hardware done!
9318 11:56:16.714404 0x00000018: ctrlr->caps
9319 11:56:16.717312 52.000 MHz: ctrlr->f_max
9320 11:56:16.717774 0.400 MHz: ctrlr->f_min
9321 11:56:16.720524 0x40ff8080: ctrlr->voltages
9322 11:56:16.720983 sclk: 390625
9323 11:56:16.723915 Bus Width = 1
9324 11:56:16.724450 sclk: 390625
9325 11:56:16.724811 Bus Width = 1
9326 11:56:16.727431 Early init status = 3
9327 11:56:16.731035 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9328 11:56:16.735632 in-header: 03 fc 00 00 01 00 00 00
9329 11:56:16.738777 in-data: 00
9330 11:56:16.742661 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9331 11:56:16.747208 in-header: 03 fd 00 00 00 00 00 00
9332 11:56:16.750894 in-data:
9333 11:56:16.753842 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9334 11:56:16.758209 in-header: 03 fc 00 00 01 00 00 00
9335 11:56:16.762188 in-data: 00
9336 11:56:16.765171 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9337 11:56:16.771039 in-header: 03 fd 00 00 00 00 00 00
9338 11:56:16.773967 in-data:
9339 11:56:16.778014 [SSUSB] Setting up USB HOST controller...
9340 11:56:16.780833 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9341 11:56:16.783679 [SSUSB] phy power-on done.
9342 11:56:16.787318 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9343 11:56:16.794303 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9344 11:56:16.797610 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9345 11:56:16.804059 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9346 11:56:16.810520 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9347 11:56:16.817545 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9348 11:56:16.823959 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9349 11:56:16.830554 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9350 11:56:16.833702 SPM: binary array size = 0x9dc
9351 11:56:16.836699 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9352 11:56:16.843762 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9353 11:56:16.850329 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9354 11:56:16.853693 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9355 11:56:16.857282 configure_display: Starting display init
9356 11:56:16.893715 anx7625_power_on_init: Init interface.
9357 11:56:16.897057 anx7625_disable_pd_protocol: Disabled PD feature.
9358 11:56:16.900201 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9359 11:56:16.928059 anx7625_start_dp_work: Secure OCM version=00
9360 11:56:16.931238 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9361 11:56:16.946609 sp_tx_get_edid_block: EDID Block = 1
9362 11:56:17.048830 Extracted contents:
9363 11:56:17.052278 header: 00 ff ff ff ff ff ff 00
9364 11:56:17.055548 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9365 11:56:17.059071 version: 01 04
9366 11:56:17.062195 basic params: 95 1f 11 78 0a
9367 11:56:17.065431 chroma info: 76 90 94 55 54 90 27 21 50 54
9368 11:56:17.069387 established: 00 00 00
9369 11:56:17.072351 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9370 11:56:17.079166 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9371 11:56:17.085408 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9372 11:56:17.092156 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9373 11:56:17.099269 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9374 11:56:17.099835 extensions: 00
9375 11:56:17.102431 checksum: fb
9376 11:56:17.102911
9377 11:56:17.105419 Manufacturer: IVO Model 57d Serial Number 0
9378 11:56:17.109011 Made week 0 of 2020
9379 11:56:17.109476 EDID version: 1.4
9380 11:56:17.112518 Digital display
9381 11:56:17.116092 6 bits per primary color channel
9382 11:56:17.116652 DisplayPort interface
9383 11:56:17.119055 Maximum image size: 31 cm x 17 cm
9384 11:56:17.119508 Gamma: 220%
9385 11:56:17.122957 Check DPMS levels
9386 11:56:17.125829 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9387 11:56:17.129189 First detailed timing is preferred timing
9388 11:56:17.132632 Established timings supported:
9389 11:56:17.135393 Standard timings supported:
9390 11:56:17.135847 Detailed timings
9391 11:56:17.142221 Hex of detail: 383680a07038204018303c0035ae10000019
9392 11:56:17.145972 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9393 11:56:17.149072 0780 0798 07c8 0820 hborder 0
9394 11:56:17.155605 0438 043b 0447 0458 vborder 0
9395 11:56:17.156056 -hsync -vsync
9396 11:56:17.158980 Did detailed timing
9397 11:56:17.162159 Hex of detail: 000000000000000000000000000000000000
9398 11:56:17.165528 Manufacturer-specified data, tag 0
9399 11:56:17.172392 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9400 11:56:17.172932 ASCII string: InfoVision
9401 11:56:17.178986 Hex of detail: 000000fe00523134304e574635205248200a
9402 11:56:17.179619 ASCII string: R140NWF5 RH
9403 11:56:17.182130 Checksum
9404 11:56:17.182576 Checksum: 0xfb (valid)
9405 11:56:17.188934 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9406 11:56:17.189483 DSI data_rate: 832800000 bps
9407 11:56:17.196354 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9408 11:56:17.199615 anx7625_parse_edid: pixelclock(138800).
9409 11:56:17.202983 hactive(1920), hsync(48), hfp(24), hbp(88)
9410 11:56:17.206270 vactive(1080), vsync(12), vfp(3), vbp(17)
9411 11:56:17.209763 anx7625_dsi_config: config dsi.
9412 11:56:17.216646 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9413 11:56:17.231013 anx7625_dsi_config: success to config DSI
9414 11:56:17.234697 anx7625_dp_start: MIPI phy setup OK.
9415 11:56:17.237894 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9416 11:56:17.240826 mtk_ddp_mode_set invalid vrefresh 60
9417 11:56:17.244202 main_disp_path_setup
9418 11:56:17.244652 ovl_layer_smi_id_en
9419 11:56:17.247694 ovl_layer_smi_id_en
9420 11:56:17.248106 ccorr_config
9421 11:56:17.248430 aal_config
9422 11:56:17.250599 gamma_config
9423 11:56:17.251048 postmask_config
9424 11:56:17.254274 dither_config
9425 11:56:17.257521 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9426 11:56:17.264036 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9427 11:56:17.267339 Root Device init finished in 554 msecs
9428 11:56:17.267793 CPU_CLUSTER: 0 init
9429 11:56:17.277543 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9430 11:56:17.280631 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9431 11:56:17.284288 APU_MBOX 0x190000b0 = 0x10001
9432 11:56:17.287709 APU_MBOX 0x190001b0 = 0x10001
9433 11:56:17.290937 APU_MBOX 0x190005b0 = 0x10001
9434 11:56:17.294450 APU_MBOX 0x190006b0 = 0x10001
9435 11:56:17.297579 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9436 11:56:17.309547 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9437 11:56:17.322057 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9438 11:56:17.328620 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9439 11:56:17.340644 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9440 11:56:17.349749 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9441 11:56:17.353445 CPU_CLUSTER: 0 init finished in 81 msecs
9442 11:56:17.356409 Devices initialized
9443 11:56:17.359786 Show all devs... After init.
9444 11:56:17.360234 Root Device: enabled 1
9445 11:56:17.363425 CPU_CLUSTER: 0: enabled 1
9446 11:56:17.366281 CPU: 00: enabled 1
9447 11:56:17.369527 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9448 11:56:17.373261 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9449 11:56:17.376132 ELOG: NV offset 0x57f000 size 0x1000
9450 11:56:17.382900 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9451 11:56:17.389769 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9452 11:56:17.393156 ELOG: Event(17) added with size 13 at 2023-11-23 11:56:17 UTC
9453 11:56:17.396425 out: cmd=0x121: 03 db 21 01 00 00 00 00
9454 11:56:17.400208 in-header: 03 d1 00 00 2c 00 00 00
9455 11:56:17.413578 in-data: 8e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9456 11:56:17.420729 ELOG: Event(A1) added with size 10 at 2023-11-23 11:56:17 UTC
9457 11:56:17.426823 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9458 11:56:17.433622 ELOG: Event(A0) added with size 9 at 2023-11-23 11:56:17 UTC
9459 11:56:17.437031 elog_add_boot_reason: Logged dev mode boot
9460 11:56:17.440876 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9461 11:56:17.443804 Finalize devices...
9462 11:56:17.444227 Devices finalized
9463 11:56:17.450653 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9464 11:56:17.453837 Writing coreboot table at 0xffe64000
9465 11:56:17.456955 0. 000000000010a000-0000000000113fff: RAMSTAGE
9466 11:56:17.460375 1. 0000000040000000-00000000400fffff: RAM
9467 11:56:17.463689 2. 0000000040100000-000000004032afff: RAMSTAGE
9468 11:56:17.471047 3. 000000004032b000-00000000545fffff: RAM
9469 11:56:17.473893 4. 0000000054600000-000000005465ffff: BL31
9470 11:56:17.477199 5. 0000000054660000-00000000ffe63fff: RAM
9471 11:56:17.480458 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9472 11:56:17.487192 7. 0000000100000000-000000023fffffff: RAM
9473 11:56:17.487615 Passing 5 GPIOs to payload:
9474 11:56:17.493455 NAME | PORT | POLARITY | VALUE
9475 11:56:17.497043 EC in RW | 0x000000aa | low | undefined
9476 11:56:17.503412 EC interrupt | 0x00000005 | low | undefined
9477 11:56:17.506821 TPM interrupt | 0x000000ab | high | undefined
9478 11:56:17.510194 SD card detect | 0x00000011 | high | undefined
9479 11:56:17.516993 speaker enable | 0x00000093 | high | undefined
9480 11:56:17.520267 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9481 11:56:17.523562 in-header: 03 f9 00 00 02 00 00 00
9482 11:56:17.523983 in-data: 02 00
9483 11:56:17.526704 ADC[4]: Raw value=900590 ID=7
9484 11:56:17.530609 ADC[3]: Raw value=213336 ID=1
9485 11:56:17.531132 RAM Code: 0x71
9486 11:56:17.534028 ADC[6]: Raw value=74926 ID=0
9487 11:56:17.537255 ADC[5]: Raw value=212229 ID=1
9488 11:56:17.537793 SKU Code: 0x1
9489 11:56:17.543248 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bd5
9490 11:56:17.546655 coreboot table: 964 bytes.
9491 11:56:17.550154 IMD ROOT 0. 0xfffff000 0x00001000
9492 11:56:17.553798 IMD SMALL 1. 0xffffe000 0x00001000
9493 11:56:17.556977 RO MCACHE 2. 0xffffc000 0x00001104
9494 11:56:17.560473 CONSOLE 3. 0xfff7c000 0x00080000
9495 11:56:17.563470 FMAP 4. 0xfff7b000 0x00000452
9496 11:56:17.566989 TIME STAMP 5. 0xfff7a000 0x00000910
9497 11:56:17.570079 VBOOT WORK 6. 0xfff66000 0x00014000
9498 11:56:17.573647 RAMOOPS 7. 0xffe66000 0x00100000
9499 11:56:17.577216 COREBOOT 8. 0xffe64000 0x00002000
9500 11:56:17.577771 IMD small region:
9501 11:56:17.580501 IMD ROOT 0. 0xffffec00 0x00000400
9502 11:56:17.584151 VPD 1. 0xffffeb80 0x0000006c
9503 11:56:17.587231 MMC STATUS 2. 0xffffeb60 0x00000004
9504 11:56:17.593580 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9505 11:56:17.593989 Probing TPM: done!
9506 11:56:17.600414 Connected to device vid:did:rid of 1ae0:0028:00
9507 11:56:17.607159 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9508 11:56:17.610676 Initialized TPM device CR50 revision 0
9509 11:56:17.614357 Checking cr50 for pending updates
9510 11:56:17.619724 Reading cr50 TPM mode
9511 11:56:17.629209 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9512 11:56:17.635584 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9513 11:56:17.675501 read SPI 0x3990ec 0x4f1b0: 34846 us, 9298 KB/s, 74.384 Mbps
9514 11:56:17.678572 Checking segment from ROM address 0x40100000
9515 11:56:17.681997 Checking segment from ROM address 0x4010001c
9516 11:56:17.688943 Loading segment from ROM address 0x40100000
9517 11:56:17.689462 code (compression=0)
9518 11:56:17.695536 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9519 11:56:17.705981 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9520 11:56:17.706533 it's not compressed!
9521 11:56:17.712512 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9522 11:56:17.715626 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9523 11:56:17.735722 Loading segment from ROM address 0x4010001c
9524 11:56:17.736200 Entry Point 0x80000000
9525 11:56:17.739248 Loaded segments
9526 11:56:17.742643 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9527 11:56:17.749038 Jumping to boot code at 0x80000000(0xffe64000)
9528 11:56:17.756134 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9529 11:56:17.762444 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9530 11:56:17.770143 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9531 11:56:17.773777 Checking segment from ROM address 0x40100000
9532 11:56:17.777131 Checking segment from ROM address 0x4010001c
9533 11:56:17.780296 Loading segment from ROM address 0x40100000
9534 11:56:17.783790 code (compression=1)
9535 11:56:17.790398 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9536 11:56:17.800384 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9537 11:56:17.800795 using LZMA
9538 11:56:17.808885 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9539 11:56:17.815658 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9540 11:56:17.818788 Loading segment from ROM address 0x4010001c
9541 11:56:17.819243 Entry Point 0x54601000
9542 11:56:17.822138 Loaded segments
9543 11:56:17.825223 NOTICE: MT8192 bl31_setup
9544 11:56:17.832096 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9545 11:56:17.835539 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9546 11:56:17.838782 WARNING: region 0:
9547 11:56:17.842357 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9548 11:56:17.842766 WARNING: region 1:
9549 11:56:17.849264 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9550 11:56:17.849672 WARNING: region 2:
9551 11:56:17.855810 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9552 11:56:17.859254 WARNING: region 3:
9553 11:56:17.862680 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9554 11:56:17.865855 WARNING: region 4:
9555 11:56:17.869617 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9556 11:56:17.872617 WARNING: region 5:
9557 11:56:17.876200 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9558 11:56:17.879521 WARNING: region 6:
9559 11:56:17.882615 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9560 11:56:17.883051 WARNING: region 7:
9561 11:56:17.886092 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9562 11:56:17.894796 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9563 11:56:17.898024 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9564 11:56:17.904485 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9565 11:56:17.908040 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9566 11:56:17.911418 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9567 11:56:17.917924 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9568 11:56:17.921751 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9569 11:56:17.924941 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9570 11:56:17.931522 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9571 11:56:17.934708 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9572 11:56:17.938204 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9573 11:56:17.945259 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9574 11:56:17.948117 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9575 11:56:17.951988 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9576 11:56:17.958690 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9577 11:56:17.961818 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9578 11:56:17.968529 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9579 11:56:17.972334 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9580 11:56:17.975142 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9581 11:56:17.982009 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9582 11:56:17.985098 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9583 11:56:17.988687 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9584 11:56:17.995232 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9585 11:56:17.998716 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9586 11:56:18.005388 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9587 11:56:18.008835 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9588 11:56:18.012329 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9589 11:56:18.019006 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9590 11:56:18.022929 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9591 11:56:18.026007 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9592 11:56:18.032366 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9593 11:56:18.035966 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9594 11:56:18.039500 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9595 11:56:18.046240 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9596 11:56:18.049460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9597 11:56:18.052798 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9598 11:56:18.056294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9599 11:56:18.062780 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9600 11:56:18.066044 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9601 11:56:18.069681 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9602 11:56:18.072716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9603 11:56:18.076138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9604 11:56:18.082969 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9605 11:56:18.086245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9606 11:56:18.089740 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9607 11:56:18.092829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9608 11:56:18.100232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9609 11:56:18.102996 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9610 11:56:18.106471 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9611 11:56:18.113487 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9612 11:56:18.116527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9613 11:56:18.123088 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9614 11:56:18.126587 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9615 11:56:18.129925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9616 11:56:18.136536 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9617 11:56:18.139647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9618 11:56:18.146457 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9619 11:56:18.150060 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9620 11:56:18.156554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9621 11:56:18.160115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9622 11:56:18.163365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9623 11:56:18.170171 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9624 11:56:18.173719 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9625 11:56:18.180516 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9626 11:56:18.184031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9627 11:56:18.190558 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9628 11:56:18.193932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9629 11:56:18.197150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9630 11:56:18.203817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9631 11:56:18.207263 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9632 11:56:18.213579 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9633 11:56:18.217434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9634 11:56:18.220692 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9635 11:56:18.227057 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9636 11:56:18.230635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9637 11:56:18.237201 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9638 11:56:18.240642 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9639 11:56:18.247221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9640 11:56:18.250520 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9641 11:56:18.254209 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9642 11:56:18.260967 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9643 11:56:18.264344 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9644 11:56:18.270899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9645 11:56:18.274280 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9646 11:56:18.280992 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9647 11:56:18.284274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9648 11:56:18.287572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9649 11:56:18.294408 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9650 11:56:18.297731 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9651 11:56:18.304577 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9652 11:56:18.308073 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9653 11:56:18.311385 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9654 11:56:18.318365 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9655 11:56:18.321807 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9656 11:56:18.328241 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9657 11:56:18.331718 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9658 11:56:18.334336 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9659 11:56:18.340989 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9660 11:56:18.344332 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9661 11:56:18.347715 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9662 11:56:18.351043 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9663 11:56:18.357858 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9664 11:56:18.361252 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9665 11:56:18.368210 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9666 11:56:18.370966 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9667 11:56:18.374442 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9668 11:56:18.381148 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9669 11:56:18.385005 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9670 11:56:18.391546 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9671 11:56:18.395084 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9672 11:56:18.398180 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9673 11:56:18.404625 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9674 11:56:18.408262 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9675 11:56:18.411586 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9676 11:56:18.418751 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9677 11:56:18.421740 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9678 11:56:18.425342 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9679 11:56:18.432304 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9680 11:56:18.435456 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9681 11:56:18.438648 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9682 11:56:18.442008 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9683 11:56:18.448859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9684 11:56:18.452113 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9685 11:56:18.455084 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9686 11:56:18.462298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9687 11:56:18.465506 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9688 11:56:18.468729 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9689 11:56:18.475400 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9690 11:56:18.478684 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9691 11:56:18.482316 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9692 11:56:18.488977 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9693 11:56:18.492708 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9694 11:56:18.499530 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9695 11:56:18.502994 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9696 11:56:18.506035 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9697 11:56:18.513360 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9698 11:56:18.516019 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9699 11:56:18.519740 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9700 11:56:18.526212 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9701 11:56:18.529682 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9702 11:56:18.536590 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9703 11:56:18.539916 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9704 11:56:18.543270 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9705 11:56:18.550190 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9706 11:56:18.552979 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9707 11:56:18.556546 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9708 11:56:18.563483 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9709 11:56:18.566693 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9710 11:56:18.573274 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9711 11:56:18.576956 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9712 11:56:18.580128 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9713 11:56:18.587016 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9714 11:56:18.590322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9715 11:56:18.593774 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9716 11:56:18.600239 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9717 11:56:18.603421 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9718 11:56:18.610476 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9719 11:56:18.613876 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9720 11:56:18.617000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9721 11:56:18.623502 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9722 11:56:18.627035 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9723 11:56:18.630788 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9724 11:56:18.637247 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9725 11:56:18.640468 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9726 11:56:18.647382 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9727 11:56:18.650673 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9728 11:56:18.653693 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9729 11:56:18.661031 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9730 11:56:18.664138 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9731 11:56:18.667288 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9732 11:56:18.674207 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9733 11:56:18.677363 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9734 11:56:18.684234 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9735 11:56:18.687124 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9736 11:56:18.690945 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9737 11:56:18.697384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9738 11:56:18.700760 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9739 11:56:18.704079 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9740 11:56:18.711245 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9741 11:56:18.714531 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9742 11:56:18.721476 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9743 11:56:18.724413 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9744 11:56:18.727458 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9745 11:56:18.734523 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9746 11:56:18.737505 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9747 11:56:18.744571 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9748 11:56:18.747673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9749 11:56:18.750933 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9750 11:56:18.757640 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9751 11:56:18.761246 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9752 11:56:18.767412 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9753 11:56:18.771107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9754 11:56:18.774161 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9755 11:56:18.781319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9756 11:56:18.784473 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9757 11:56:18.791494 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9758 11:56:18.794469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9759 11:56:18.797467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9760 11:56:18.804467 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9761 11:56:18.807592 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9762 11:56:18.814435 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9763 11:56:18.817540 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9764 11:56:18.821211 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9765 11:56:18.827922 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9766 11:56:18.831328 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9767 11:56:18.837818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9768 11:56:18.841070 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9769 11:56:18.844247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9770 11:56:18.850994 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9771 11:56:18.854044 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9772 11:56:18.861427 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9773 11:56:18.864557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9774 11:56:18.870999 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9775 11:56:18.874568 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9776 11:56:18.878098 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9777 11:56:18.884545 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9778 11:56:18.887562 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9779 11:56:18.894384 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9780 11:56:18.897631 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9781 11:56:18.901150 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9782 11:56:18.907824 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9783 11:56:18.911222 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9784 11:56:18.917764 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9785 11:56:18.921319 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9786 11:56:18.924486 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9787 11:56:18.931376 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9788 11:56:18.934837 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9789 11:56:18.941153 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9790 11:56:18.944894 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9791 11:56:18.947762 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9792 11:56:18.951208 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9793 11:56:18.958133 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9794 11:56:18.961897 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9795 11:56:18.965298 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9796 11:56:18.968144 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9797 11:56:18.974930 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9798 11:56:18.978425 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9799 11:56:18.984572 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9800 11:56:18.988187 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9801 11:56:18.991655 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9802 11:56:18.998464 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9803 11:56:19.001253 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9804 11:56:19.005222 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9805 11:56:19.011459 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9806 11:56:19.014701 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9807 11:56:19.018052 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9808 11:56:19.024924 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9809 11:56:19.028392 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9810 11:56:19.031578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9811 11:56:19.038426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9812 11:56:19.041863 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9813 11:56:19.048513 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9814 11:56:19.051796 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9815 11:56:19.054663 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9816 11:56:19.061982 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9817 11:56:19.065289 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9818 11:56:19.068668 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9819 11:56:19.075507 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9820 11:56:19.078834 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9821 11:56:19.082004 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9822 11:56:19.088726 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9823 11:56:19.091685 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9824 11:56:19.095247 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9825 11:56:19.101635 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9826 11:56:19.105025 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9827 11:56:19.111941 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9828 11:56:19.115017 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9829 11:56:19.118415 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9830 11:56:19.125321 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9831 11:56:19.128312 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9832 11:56:19.131767 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9833 11:56:19.134923 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9834 11:56:19.138785 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9835 11:56:19.144968 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9836 11:56:19.148402 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9837 11:56:19.151725 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9838 11:56:19.155217 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9839 11:56:19.161960 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9840 11:56:19.164910 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9841 11:56:19.168732 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9842 11:56:19.171886 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9843 11:56:19.178590 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9844 11:56:19.181732 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9845 11:56:19.188581 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9846 11:56:19.191945 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9847 11:56:19.195154 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9848 11:56:19.201813 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9849 11:56:19.205016 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9850 11:56:19.211948 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9851 11:56:19.215004 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9852 11:56:19.218621 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9853 11:56:19.225431 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9854 11:56:19.228788 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9855 11:56:19.235240 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9856 11:56:19.238808 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9857 11:56:19.242141 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9858 11:56:19.248618 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9859 11:56:19.251816 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9860 11:56:19.255358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9861 11:56:19.261904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9862 11:56:19.265500 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9863 11:56:19.271771 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9864 11:56:19.275336 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9865 11:56:19.282392 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9866 11:56:19.285401 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9867 11:56:19.288533 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9868 11:56:19.295820 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9869 11:56:19.298986 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9870 11:56:19.305494 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9871 11:56:19.308537 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9872 11:56:19.311957 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9873 11:56:19.318992 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9874 11:56:19.322338 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9875 11:56:19.325279 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9876 11:56:19.331680 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9877 11:56:19.335281 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9878 11:56:19.341923 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9879 11:56:19.345464 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9880 11:56:19.352065 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9881 11:56:19.355299 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9882 11:56:19.358294 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9883 11:56:19.365478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9884 11:56:19.368694 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9885 11:56:19.375070 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9886 11:56:19.378172 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9887 11:56:19.382283 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9888 11:56:19.388309 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9889 11:56:19.392464 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9890 11:56:19.398958 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9891 11:56:19.402370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9892 11:56:19.405663 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9893 11:56:19.412433 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9894 11:56:19.415650 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9895 11:56:19.421966 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9896 11:56:19.425623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9897 11:56:19.428811 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9898 11:56:19.435439 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9899 11:56:19.438854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9900 11:56:19.442393 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9901 11:56:19.449484 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9902 11:56:19.452449 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9903 11:56:19.459204 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9904 11:56:19.462666 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9905 11:56:19.466196 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9906 11:56:19.473080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9907 11:56:19.476191 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9908 11:56:19.483229 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9909 11:56:19.486076 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9910 11:56:19.489201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9911 11:56:19.496142 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9912 11:56:19.499501 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9913 11:56:19.505874 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9914 11:56:19.509429 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9915 11:56:19.512718 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9916 11:56:19.520017 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9917 11:56:19.522903 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9918 11:56:19.529577 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9919 11:56:19.533307 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9920 11:56:19.539797 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9921 11:56:19.542929 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9922 11:56:19.546479 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9923 11:56:19.552999 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9924 11:56:19.556746 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9925 11:56:19.563073 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9926 11:56:19.566401 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9927 11:56:19.569730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9928 11:56:19.576305 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9929 11:56:19.579934 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9930 11:56:19.586539 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9931 11:56:19.589789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9932 11:56:19.596621 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9933 11:56:19.599900 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9934 11:56:19.602999 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9935 11:56:19.609688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9936 11:56:19.612988 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9937 11:56:19.619879 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9938 11:56:19.623350 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9939 11:56:19.626371 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9940 11:56:19.633638 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9941 11:56:19.636552 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9942 11:56:19.643595 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9943 11:56:19.646789 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9944 11:56:19.653283 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9945 11:56:19.656686 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9946 11:56:19.663331 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9947 11:56:19.666520 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9948 11:56:19.669969 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9949 11:56:19.676847 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9950 11:56:19.680348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9951 11:56:19.686730 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9952 11:56:19.690306 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9953 11:56:19.697122 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9954 11:56:19.700419 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9955 11:56:19.703954 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9956 11:56:19.710442 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9957 11:56:19.713803 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9958 11:56:19.720545 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9959 11:56:19.723498 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9960 11:56:19.726728 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9961 11:56:19.733678 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9962 11:56:19.736689 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9963 11:56:19.743153 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9964 11:56:19.746825 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9965 11:56:19.750410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9966 11:56:19.756897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9967 11:56:19.760647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9968 11:56:19.766978 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9969 11:56:19.770334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9970 11:56:19.776756 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9971 11:56:19.780247 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9972 11:56:19.786918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9973 11:56:19.790306 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9974 11:56:19.797447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9975 11:56:19.800113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9976 11:56:19.807134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9977 11:56:19.810562 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9978 11:56:19.817051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9979 11:56:19.820332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9980 11:56:19.823727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9981 11:56:19.830907 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9982 11:56:19.834241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9983 11:56:19.840949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9984 11:56:19.844016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9985 11:56:19.850964 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9986 11:56:19.854099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9987 11:56:19.861012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9988 11:56:19.863850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9989 11:56:19.870552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9990 11:56:19.874078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9991 11:56:19.880367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9992 11:56:19.883912 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9993 11:56:19.890982 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9994 11:56:19.894238 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9995 11:56:19.900497 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9996 11:56:19.903733 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9997 11:56:19.907501 INFO: [APUAPC] vio 0
9998 11:56:19.911094 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9999 11:56:19.917525 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10000 11:56:19.920685 INFO: [APUAPC] D0_APC_0: 0x400510
10001 11:56:19.921098 INFO: [APUAPC] D0_APC_1: 0x0
10002 11:56:19.923729 INFO: [APUAPC] D0_APC_2: 0x1540
10003 11:56:19.927516 INFO: [APUAPC] D0_APC_3: 0x0
10004 11:56:19.931003 INFO: [APUAPC] D1_APC_0: 0xffffffff
10005 11:56:19.934327 INFO: [APUAPC] D1_APC_1: 0xffffffff
10006 11:56:19.937363 INFO: [APUAPC] D1_APC_2: 0x3fffff
10007 11:56:19.940797 INFO: [APUAPC] D1_APC_3: 0x0
10008 11:56:19.943953 INFO: [APUAPC] D2_APC_0: 0xffffffff
10009 11:56:19.947636 INFO: [APUAPC] D2_APC_1: 0xffffffff
10010 11:56:19.951026 INFO: [APUAPC] D2_APC_2: 0x3fffff
10011 11:56:19.954227 INFO: [APUAPC] D2_APC_3: 0x0
10012 11:56:19.958008 INFO: [APUAPC] D3_APC_0: 0xffffffff
10013 11:56:19.961089 INFO: [APUAPC] D3_APC_1: 0xffffffff
10014 11:56:19.964470 INFO: [APUAPC] D3_APC_2: 0x3fffff
10015 11:56:19.967556 INFO: [APUAPC] D3_APC_3: 0x0
10016 11:56:19.971432 INFO: [APUAPC] D4_APC_0: 0xffffffff
10017 11:56:19.974110 INFO: [APUAPC] D4_APC_1: 0xffffffff
10018 11:56:19.977638 INFO: [APUAPC] D4_APC_2: 0x3fffff
10019 11:56:19.980917 INFO: [APUAPC] D4_APC_3: 0x0
10020 11:56:19.984578 INFO: [APUAPC] D5_APC_0: 0xffffffff
10021 11:56:19.987359 INFO: [APUAPC] D5_APC_1: 0xffffffff
10022 11:56:19.990691 INFO: [APUAPC] D5_APC_2: 0x3fffff
10023 11:56:19.994081 INFO: [APUAPC] D5_APC_3: 0x0
10024 11:56:19.997825 INFO: [APUAPC] D6_APC_0: 0xffffffff
10025 11:56:20.001309 INFO: [APUAPC] D6_APC_1: 0xffffffff
10026 11:56:20.004146 INFO: [APUAPC] D6_APC_2: 0x3fffff
10027 11:56:20.004556 INFO: [APUAPC] D6_APC_3: 0x0
10028 11:56:20.010734 INFO: [APUAPC] D7_APC_0: 0xffffffff
10029 11:56:20.014587 INFO: [APUAPC] D7_APC_1: 0xffffffff
10030 11:56:20.017845 INFO: [APUAPC] D7_APC_2: 0x3fffff
10031 11:56:20.018258 INFO: [APUAPC] D7_APC_3: 0x0
10032 11:56:20.021080 INFO: [APUAPC] D8_APC_0: 0xffffffff
10033 11:56:20.024808 INFO: [APUAPC] D8_APC_1: 0xffffffff
10034 11:56:20.028038 INFO: [APUAPC] D8_APC_2: 0x3fffff
10035 11:56:20.031031 INFO: [APUAPC] D8_APC_3: 0x0
10036 11:56:20.034942 INFO: [APUAPC] D9_APC_0: 0xffffffff
10037 11:56:20.037497 INFO: [APUAPC] D9_APC_1: 0xffffffff
10038 11:56:20.040712 INFO: [APUAPC] D9_APC_2: 0x3fffff
10039 11:56:20.044430 INFO: [APUAPC] D9_APC_3: 0x0
10040 11:56:20.047406 INFO: [APUAPC] D10_APC_0: 0xffffffff
10041 11:56:20.051239 INFO: [APUAPC] D10_APC_1: 0xffffffff
10042 11:56:20.054804 INFO: [APUAPC] D10_APC_2: 0x3fffff
10043 11:56:20.057705 INFO: [APUAPC] D10_APC_3: 0x0
10044 11:56:20.061693 INFO: [APUAPC] D11_APC_0: 0xffffffff
10045 11:56:20.064521 INFO: [APUAPC] D11_APC_1: 0xffffffff
10046 11:56:20.067868 INFO: [APUAPC] D11_APC_2: 0x3fffff
10047 11:56:20.071267 INFO: [APUAPC] D11_APC_3: 0x0
10048 11:56:20.074632 INFO: [APUAPC] D12_APC_0: 0xffffffff
10049 11:56:20.078040 INFO: [APUAPC] D12_APC_1: 0xffffffff
10050 11:56:20.081379 INFO: [APUAPC] D12_APC_2: 0x3fffff
10051 11:56:20.084550 INFO: [APUAPC] D12_APC_3: 0x0
10052 11:56:20.088043 INFO: [APUAPC] D13_APC_0: 0xffffffff
10053 11:56:20.090810 INFO: [APUAPC] D13_APC_1: 0xffffffff
10054 11:56:20.094320 INFO: [APUAPC] D13_APC_2: 0x3fffff
10055 11:56:20.098001 INFO: [APUAPC] D13_APC_3: 0x0
10056 11:56:20.101185 INFO: [APUAPC] D14_APC_0: 0xffffffff
10057 11:56:20.104081 INFO: [APUAPC] D14_APC_1: 0xffffffff
10058 11:56:20.107702 INFO: [APUAPC] D14_APC_2: 0x3fffff
10059 11:56:20.110936 INFO: [APUAPC] D14_APC_3: 0x0
10060 11:56:20.114508 INFO: [APUAPC] D15_APC_0: 0xffffffff
10061 11:56:20.117437 INFO: [APUAPC] D15_APC_1: 0xffffffff
10062 11:56:20.120862 INFO: [APUAPC] D15_APC_2: 0x3fffff
10063 11:56:20.124490 INFO: [APUAPC] D15_APC_3: 0x0
10064 11:56:20.127741 INFO: [APUAPC] APC_CON: 0x4
10065 11:56:20.131613 INFO: [NOCDAPC] D0_APC_0: 0x0
10066 11:56:20.135084 INFO: [NOCDAPC] D0_APC_1: 0x0
10067 11:56:20.137521 INFO: [NOCDAPC] D1_APC_0: 0x0
10068 11:56:20.141130 INFO: [NOCDAPC] D1_APC_1: 0xfff
10069 11:56:20.141682 INFO: [NOCDAPC] D2_APC_0: 0x0
10070 11:56:20.144411 INFO: [NOCDAPC] D2_APC_1: 0xfff
10071 11:56:20.147885 INFO: [NOCDAPC] D3_APC_0: 0x0
10072 11:56:20.151071 INFO: [NOCDAPC] D3_APC_1: 0xfff
10073 11:56:20.155019 INFO: [NOCDAPC] D4_APC_0: 0x0
10074 11:56:20.158185 INFO: [NOCDAPC] D4_APC_1: 0xfff
10075 11:56:20.161463 INFO: [NOCDAPC] D5_APC_0: 0x0
10076 11:56:20.164539 INFO: [NOCDAPC] D5_APC_1: 0xfff
10077 11:56:20.167837 INFO: [NOCDAPC] D6_APC_0: 0x0
10078 11:56:20.171122 INFO: [NOCDAPC] D6_APC_1: 0xfff
10079 11:56:20.174821 INFO: [NOCDAPC] D7_APC_0: 0x0
10080 11:56:20.175418 INFO: [NOCDAPC] D7_APC_1: 0xfff
10081 11:56:20.178102 INFO: [NOCDAPC] D8_APC_0: 0x0
10082 11:56:20.181210 INFO: [NOCDAPC] D8_APC_1: 0xfff
10083 11:56:20.185068 INFO: [NOCDAPC] D9_APC_0: 0x0
10084 11:56:20.188603 INFO: [NOCDAPC] D9_APC_1: 0xfff
10085 11:56:20.191039 INFO: [NOCDAPC] D10_APC_0: 0x0
10086 11:56:20.195255 INFO: [NOCDAPC] D10_APC_1: 0xfff
10087 11:56:20.198214 INFO: [NOCDAPC] D11_APC_0: 0x0
10088 11:56:20.201669 INFO: [NOCDAPC] D11_APC_1: 0xfff
10089 11:56:20.204810 INFO: [NOCDAPC] D12_APC_0: 0x0
10090 11:56:20.208464 INFO: [NOCDAPC] D12_APC_1: 0xfff
10091 11:56:20.208917 INFO: [NOCDAPC] D13_APC_0: 0x0
10092 11:56:20.211683 INFO: [NOCDAPC] D13_APC_1: 0xfff
10093 11:56:20.215277 INFO: [NOCDAPC] D14_APC_0: 0x0
10094 11:56:20.218208 INFO: [NOCDAPC] D14_APC_1: 0xfff
10095 11:56:20.221950 INFO: [NOCDAPC] D15_APC_0: 0x0
10096 11:56:20.224717 INFO: [NOCDAPC] D15_APC_1: 0xfff
10097 11:56:20.228630 INFO: [NOCDAPC] APC_CON: 0x4
10098 11:56:20.231659 INFO: [APUAPC] set_apusys_apc done
10099 11:56:20.235127 INFO: [DEVAPC] devapc_init done
10100 11:56:20.238525 INFO: GICv3 without legacy support detected.
10101 11:56:20.241708 INFO: ARM GICv3 driver initialized in EL3
10102 11:56:20.245596 INFO: Maximum SPI INTID supported: 639
10103 11:56:20.252168 INFO: BL31: Initializing runtime services
10104 11:56:20.255035 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10105 11:56:20.258316 INFO: SPM: enable CPC mode
10106 11:56:20.264858 INFO: mcdi ready for mcusys-off-idle and system suspend
10107 11:56:20.268760 INFO: BL31: Preparing for EL3 exit to normal world
10108 11:56:20.271872 INFO: Entry point address = 0x80000000
10109 11:56:20.274789 INFO: SPSR = 0x8
10110 11:56:20.280491
10111 11:56:20.281052
10112 11:56:20.281414
10113 11:56:20.283495 Starting depthcharge on Spherion...
10114 11:56:20.283948
10115 11:56:20.284304 Wipe memory regions:
10116 11:56:20.284637
10117 11:56:20.287372 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10118 11:56:20.287907 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10119 11:56:20.288336 Setting prompt string to ['asurada:']
10120 11:56:20.288755 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10121 11:56:20.289458 [0x00000040000000, 0x00000054600000)
10122 11:56:20.409258
10123 11:56:20.409804 [0x00000054660000, 0x00000080000000)
10124 11:56:20.669562
10125 11:56:20.670077 [0x000000821a7280, 0x000000ffe64000)
10126 11:56:21.414600
10127 11:56:21.415192 [0x00000100000000, 0x00000240000000)
10128 11:56:23.304415
10129 11:56:23.307097 Initializing XHCI USB controller at 0x11200000.
10130 11:56:24.345579
10131 11:56:24.349002 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10132 11:56:24.349464
10133 11:56:24.349824
10134 11:56:24.350156
10135 11:56:24.351090 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10137 11:56:24.452722 asurada: tftpboot 192.168.201.1 12066559/tftp-deploy-4lvz1rte/kernel/image.itb 12066559/tftp-deploy-4lvz1rte/kernel/cmdline
10138 11:56:24.453370 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10139 11:56:24.453815 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10140 11:56:24.458616 tftpboot 192.168.201.1 12066559/tftp-deploy-4lvz1rte/kernel/image.ittp-deploy-4lvz1rte/kernel/cmdline
10141 11:56:24.459140
10142 11:56:24.459508 Waiting for link
10143 11:56:24.619306
10144 11:56:24.619885 R8152: Initializing
10145 11:56:24.620253
10146 11:56:24.622197 Version 6 (ocp_data = 5c30)
10147 11:56:24.622655
10148 11:56:24.625688 R8152: Done initializing
10149 11:56:24.626245
10150 11:56:24.626604 Adding net device
10151 11:56:26.523879
10152 11:56:26.524498 done.
10153 11:56:26.524871
10154 11:56:26.525206 MAC: 00:24:32:30:78:52
10155 11:56:26.525525
10156 11:56:26.526911 Sending DHCP discover... done.
10157 11:56:26.527364
10158 11:56:26.530324 Waiting for reply... done.
10159 11:56:26.531051
10160 11:56:26.534159 Sending DHCP request... done.
10161 11:56:26.534726
10162 11:56:26.537156 Waiting for reply... done.
10163 11:56:26.537608
10164 11:56:26.537965 My ip is 192.168.201.14
10165 11:56:26.538296
10166 11:56:26.540318 The DHCP server ip is 192.168.201.1
10167 11:56:26.540771
10168 11:56:26.544430 TFTP server IP predefined by user: 192.168.201.1
10169 11:56:26.544994
10170 11:56:26.550954 Bootfile predefined by user: 12066559/tftp-deploy-4lvz1rte/kernel/image.itb
10171 11:56:26.551516
10172 11:56:26.554178 Sending tftp read request... done.
10173 11:56:26.554731
10174 11:56:26.563356 Waiting for the transfer...
10175 11:56:26.563908
10176 11:56:27.266386 00000000 ################################################################
10177 11:56:27.266946
10178 11:56:27.971540 00080000 ################################################################
10179 11:56:27.972040
10180 11:56:28.648861 00100000 ################################################################
10181 11:56:28.649353
10182 11:56:29.298204 00180000 ################################################################
10183 11:56:29.298687
10184 11:56:29.918023 00200000 ################################################################
10185 11:56:29.918531
10186 11:56:30.594623 00280000 ################################################################
10187 11:56:30.595183
10188 11:56:31.290856 00300000 ################################################################
10189 11:56:31.291025
10190 11:56:31.983527 00380000 ################################################################
10191 11:56:31.984051
10192 11:56:32.703199 00400000 ################################################################
10193 11:56:32.703708
10194 11:56:33.367217 00480000 ################################################################
10195 11:56:33.367736
10196 11:56:34.075782 00500000 ################################################################
10197 11:56:34.076298
10198 11:56:34.778041 00580000 ################################################################
10199 11:56:34.778552
10200 11:56:35.423587 00600000 ################################################################
10201 11:56:35.424103
10202 11:56:36.070395 00680000 ################################################################
10203 11:56:36.070532
10204 11:56:36.689471 00700000 ################################################################
10205 11:56:36.689606
10206 11:56:37.356773 00780000 ################################################################
10207 11:56:37.357312
10208 11:56:38.053919 00800000 ################################################################
10209 11:56:38.054157
10210 11:56:38.758521 00880000 ################################################################
10211 11:56:38.758673
10212 11:56:39.419759 00900000 ################################################################
10213 11:56:39.420344
10214 11:56:40.112654 00980000 ################################################################
10215 11:56:40.112800
10216 11:56:40.773805 00a00000 ################################################################
10217 11:56:40.774408
10218 11:56:41.464373 00a80000 ################################################################
10219 11:56:41.464883
10220 11:56:42.169833 00b00000 ################################################################
10221 11:56:42.170455
10222 11:56:42.871504 00b80000 ################################################################
10223 11:56:42.872016
10224 11:56:43.557655 00c00000 ################################################################
10225 11:56:43.558150
10226 11:56:44.272982 00c80000 ################################################################
10227 11:56:44.273596
10228 11:56:44.995404 00d00000 ################################################################
10229 11:56:44.995903
10230 11:56:45.712427 00d80000 ################################################################
10231 11:56:45.713042
10232 11:56:46.411494 00e00000 ################################################################
10233 11:56:46.412010
10234 11:56:47.114851 00e80000 ################################################################
10235 11:56:47.115403
10236 11:56:47.811429 00f00000 ################################################################
10237 11:56:47.811930
10238 11:56:48.468561 00f80000 ################################################################
10239 11:56:48.468705
10240 11:56:49.181490 01000000 ################################################################
10241 11:56:49.181990
10242 11:56:49.914536 01080000 ################################################################
10243 11:56:49.915202
10244 11:56:50.639460 01100000 ################################################################
10245 11:56:50.639984
10246 11:56:51.371655 01180000 ################################################################
10247 11:56:51.372162
10248 11:56:52.055674 01200000 ################################################################
10249 11:56:52.056205
10250 11:56:52.757073 01280000 ################################################################
10251 11:56:52.757597
10252 11:56:53.478445 01300000 ################################################################
10253 11:56:53.478975
10254 11:56:54.206379 01380000 ################################################################
10255 11:56:54.206970
10256 11:56:54.904947 01400000 ################################################################
10257 11:56:54.905459
10258 11:56:55.640269 01480000 ################################################################
10259 11:56:55.640792
10260 11:56:56.336100 01500000 ################################################################
10261 11:56:56.336622
10262 11:56:57.041232 01580000 ################################################################
10263 11:56:57.041827
10264 11:56:57.781278 01600000 ################################################################
10265 11:56:57.781909
10266 11:56:58.436028 01680000 ################################################################
10267 11:56:58.436165
10268 11:56:59.063679 01700000 ################################################################
10269 11:56:59.063813
10270 11:56:59.699637 01780000 ################################################################
10271 11:56:59.699779
10272 11:57:00.389370 01800000 ################################################################
10273 11:57:00.389893
10274 11:57:01.078748 01880000 ################################################################
10275 11:57:01.079351
10276 11:57:01.769248 01900000 ################################################################
10277 11:57:01.769762
10278 11:57:02.450820 01980000 ################################################################
10279 11:57:02.451421
10280 11:57:03.123803 01a00000 ################################################################
10281 11:57:03.124328
10282 11:57:03.812192 01a80000 ################################################################
10283 11:57:03.812709
10284 11:57:04.511866 01b00000 ################################################################
10285 11:57:04.512414
10286 11:57:05.170211 01b80000 ################################################################
10287 11:57:05.170349
10288 11:57:05.822825 01c00000 ############################################################# done.
10289 11:57:05.823455
10290 11:57:05.826054 The bootfile was 29852822 bytes long.
10291 11:57:05.826614
10292 11:57:05.829595 Sending tftp read request... done.
10293 11:57:05.830195
10294 11:57:05.832922 Waiting for the transfer...
10295 11:57:05.833380
10296 11:57:05.836061 00000000 # done.
10297 11:57:05.836527
10298 11:57:05.842776 Command line loaded dynamically from TFTP file: 12066559/tftp-deploy-4lvz1rte/kernel/cmdline
10299 11:57:05.843298
10300 11:57:05.866729 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10301 11:57:05.867325
10302 11:57:05.867661 Loading FIT.
10303 11:57:05.867972
10304 11:57:05.869551 Image ramdisk-1 has 18756327 bytes.
10305 11:57:05.869964
10306 11:57:05.873514 Image fdt-1 has 47278 bytes.
10307 11:57:05.874024
10308 11:57:05.876864 Image kernel-1 has 11047184 bytes.
10309 11:57:05.877380
10310 11:57:05.882816 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10311 11:57:05.883319
10312 11:57:05.903467 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10313 11:57:05.904002
10314 11:57:05.906315 Choosing best match conf-1 for compat google,spherion-rev2.
10315 11:57:05.911251
10316 11:57:05.916118 Connected to device vid:did:rid of 1ae0:0028:00
10317 11:57:05.922736
10318 11:57:05.926157 tpm_get_response: command 0x17b, return code 0x0
10319 11:57:05.926670
10320 11:57:05.929619 ec_init: CrosEC protocol v3 supported (256, 248)
10321 11:57:05.935017
10322 11:57:05.938316 tpm_cleanup: add release locality here.
10323 11:57:05.938942
10324 11:57:05.939500 Shutting down all USB controllers.
10325 11:57:05.941157
10326 11:57:05.941569 Removing current net device
10327 11:57:05.941895
10328 11:57:05.948227 Exiting depthcharge with code 4 at timestamp: 75074423
10329 11:57:05.948744
10330 11:57:05.951650 LZMA decompressing kernel-1 to 0x821a6718
10331 11:57:05.952070
10332 11:57:05.954481 LZMA decompressing kernel-1 to 0x40000000
10333 11:57:07.343458
10334 11:57:07.344061 jumping to kernel
10335 11:57:07.345787 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10336 11:57:07.346309 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10337 11:57:07.346716 Setting prompt string to ['Linux version [0-9]']
10338 11:57:07.347136 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10339 11:57:07.347515 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10340 11:57:07.426301
10341 11:57:07.429698 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10342 11:57:07.433534 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10343 11:57:07.434130 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10344 11:57:07.434530 Setting prompt string to []
10345 11:57:07.435052 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10346 11:57:07.435644 Using line separator: #'\n'#
10347 11:57:07.436018 No login prompt set.
10348 11:57:07.436376 Parsing kernel messages
10349 11:57:07.436695 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10350 11:57:07.437254 [login-action] Waiting for messages, (timeout 00:03:38)
10351 11:57:07.452881 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10352 11:57:07.456240 [ 0.000000] random: crng init done
10353 11:57:07.459301 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10354 11:57:07.462732 [ 0.000000] efi: UEFI not found.
10355 11:57:07.472652 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10356 11:57:07.479787 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10357 11:57:07.489998 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10358 11:57:07.499776 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10359 11:57:07.506543 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10360 11:57:07.510049 [ 0.000000] printk: bootconsole [mtk8250] enabled
10361 11:57:07.518086 [ 0.000000] NUMA: No NUMA configuration found
10362 11:57:07.524670 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10363 11:57:07.531341 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10364 11:57:07.531901 [ 0.000000] Zone ranges:
10365 11:57:07.538267 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10366 11:57:07.541337 [ 0.000000] DMA32 empty
10367 11:57:07.547831 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10368 11:57:07.551208 [ 0.000000] Movable zone start for each node
10369 11:57:07.554810 [ 0.000000] Early memory node ranges
10370 11:57:07.561542 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10371 11:57:07.568155 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10372 11:57:07.574542 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10373 11:57:07.581532 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10374 11:57:07.587850 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10375 11:57:07.594356 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10376 11:57:07.650499 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10377 11:57:07.657326 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10378 11:57:07.663971 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10379 11:57:07.666986 [ 0.000000] psci: probing for conduit method from DT.
10380 11:57:07.673693 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10381 11:57:07.677349 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10382 11:57:07.683842 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10383 11:57:07.687365 [ 0.000000] psci: SMC Calling Convention v1.2
10384 11:57:07.693943 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10385 11:57:07.697229 [ 0.000000] Detected VIPT I-cache on CPU0
10386 11:57:07.704029 [ 0.000000] CPU features: detected: GIC system register CPU interface
10387 11:57:07.710658 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10388 11:57:07.717408 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10389 11:57:07.724156 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10390 11:57:07.730761 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10391 11:57:07.737377 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10392 11:57:07.743849 [ 0.000000] alternatives: applying boot alternatives
10393 11:57:07.747493 [ 0.000000] Fallback order for Node 0: 0
10394 11:57:07.753594 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10395 11:57:07.757643 [ 0.000000] Policy zone: Normal
10396 11:57:07.780548 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10397 11:57:07.790982 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10398 11:57:07.803465 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10399 11:57:07.813505 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10400 11:57:07.820380 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10401 11:57:07.823774 <6>[ 0.000000] software IO TLB: area num 8.
10402 11:57:07.880262 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10403 11:57:08.029461 <6>[ 0.000000] Memory: 7951300K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 401468K reserved, 32768K cma-reserved)
10404 11:57:08.036300 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10405 11:57:08.042573 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10406 11:57:08.046091 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10407 11:57:08.053091 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10408 11:57:08.059704 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10409 11:57:08.063251 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10410 11:57:08.072755 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10411 11:57:08.079430 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10412 11:57:08.083096 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10413 11:57:08.090933 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10414 11:57:08.094341 <6>[ 0.000000] GICv3: 608 SPIs implemented
10415 11:57:08.100963 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10416 11:57:08.104141 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10417 11:57:08.107478 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10418 11:57:08.114070 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10419 11:57:08.127459 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10420 11:57:08.140685 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10421 11:57:08.147261 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10422 11:57:08.156081 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10423 11:57:08.169673 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10424 11:57:08.176103 <6>[ 0.000001] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10425 11:57:08.182696 <6>[ 0.009179] Console: colour dummy device 80x25
10426 11:57:08.192654 <6>[ 0.013925] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10427 11:57:08.196063 <6>[ 0.024367] pid_max: default: 32768 minimum: 301
10428 11:57:08.202473 <6>[ 0.029269] LSM: Security Framework initializing
10429 11:57:08.209287 <6>[ 0.034206] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10430 11:57:08.219282 <6>[ 0.042019] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10431 11:57:08.225847 <6>[ 0.051485] cblist_init_generic: Setting adjustable number of callback queues.
10432 11:57:08.232661 <6>[ 0.058928] cblist_init_generic: Setting shift to 3 and lim to 1.
10433 11:57:08.242333 <6>[ 0.065266] cblist_init_generic: Setting adjustable number of callback queues.
10434 11:57:08.245678 <6>[ 0.072693] cblist_init_generic: Setting shift to 3 and lim to 1.
10435 11:57:08.252784 <6>[ 0.079133] rcu: Hierarchical SRCU implementation.
10436 11:57:08.259167 <6>[ 0.084149] rcu: Max phase no-delay instances is 1000.
10437 11:57:08.265562 <6>[ 0.091206] EFI services will not be available.
10438 11:57:08.268974 <6>[ 0.096157] smp: Bringing up secondary CPUs ...
10439 11:57:08.277040 <6>[ 0.101204] Detected VIPT I-cache on CPU1
10440 11:57:08.283501 <6>[ 0.101275] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10441 11:57:08.290301 <6>[ 0.101306] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10442 11:57:08.293360 <6>[ 0.101646] Detected VIPT I-cache on CPU2
10443 11:57:08.300234 <6>[ 0.101697] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10444 11:57:08.306982 <6>[ 0.101714] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10445 11:57:08.313779 <6>[ 0.101972] Detected VIPT I-cache on CPU3
10446 11:57:08.320074 <6>[ 0.102018] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10447 11:57:08.326809 <6>[ 0.102032] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10448 11:57:08.330116 <6>[ 0.102332] CPU features: detected: Spectre-v4
10449 11:57:08.337121 <6>[ 0.102339] CPU features: detected: Spectre-BHB
10450 11:57:08.340538 <6>[ 0.102344] Detected PIPT I-cache on CPU4
10451 11:57:08.346566 <6>[ 0.102402] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10452 11:57:08.353699 <6>[ 0.102419] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10453 11:57:08.356679 <6>[ 0.102709] Detected PIPT I-cache on CPU5
10454 11:57:08.367050 <6>[ 0.102770] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10455 11:57:08.373718 <6>[ 0.102787] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10456 11:57:08.377136 <6>[ 0.103065] Detected PIPT I-cache on CPU6
10457 11:57:08.383480 <6>[ 0.103129] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10458 11:57:08.390194 <6>[ 0.103145] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10459 11:57:08.393790 <6>[ 0.103440] Detected PIPT I-cache on CPU7
10460 11:57:08.403541 <6>[ 0.103504] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10461 11:57:08.410183 <6>[ 0.103520] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10462 11:57:08.413358 <6>[ 0.103567] smp: Brought up 1 node, 8 CPUs
10463 11:57:08.417297 <6>[ 0.244890] SMP: Total of 8 processors activated.
10464 11:57:08.423847 <6>[ 0.249810] CPU features: detected: 32-bit EL0 Support
10465 11:57:08.433208 <6>[ 0.255206] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10466 11:57:08.439822 <6>[ 0.264061] CPU features: detected: Common not Private translations
10467 11:57:08.443312 <6>[ 0.270576] CPU features: detected: CRC32 instructions
10468 11:57:08.449598 <6>[ 0.275960] CPU features: detected: RCpc load-acquire (LDAPR)
10469 11:57:08.456693 <6>[ 0.281957] CPU features: detected: LSE atomic instructions
10470 11:57:08.463163 <6>[ 0.287739] CPU features: detected: Privileged Access Never
10471 11:57:08.466304 <6>[ 0.293518] CPU features: detected: RAS Extension Support
10472 11:57:08.473357 <6>[ 0.299162] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10473 11:57:08.479727 <6>[ 0.306384] CPU: All CPU(s) started at EL2
10474 11:57:08.486182 <6>[ 0.310727] alternatives: applying system-wide alternatives
10475 11:57:08.494946 <6>[ 0.321427] devtmpfs: initialized
10476 11:57:08.507100 <6>[ 0.330356] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10477 11:57:08.516897 <6>[ 0.340317] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10478 11:57:08.523794 <6>[ 0.348531] pinctrl core: initialized pinctrl subsystem
10479 11:57:08.527001 <6>[ 0.355188] DMI not present or invalid.
10480 11:57:08.534051 <6>[ 0.359599] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10481 11:57:08.544017 <6>[ 0.366403] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10482 11:57:08.550475 <6>[ 0.373985] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10483 11:57:08.560483 <6>[ 0.382211] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10484 11:57:08.564165 <6>[ 0.390457] audit: initializing netlink subsys (disabled)
10485 11:57:08.573900 <5>[ 0.396147] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10486 11:57:08.577422 <6>[ 0.396847] thermal_sys: Registered thermal governor 'step_wise'
10487 11:57:08.587182 <6>[ 0.404116] thermal_sys: Registered thermal governor 'power_allocator'
10488 11:57:08.590447 <6>[ 0.410371] cpuidle: using governor menu
10489 11:57:08.593347 <6>[ 0.421332] NET: Registered PF_QIPCRTR protocol family
10490 11:57:08.603444 <6>[ 0.426834] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10491 11:57:08.607087 <6>[ 0.433940] ASID allocator initialised with 32768 entries
10492 11:57:08.614064 <6>[ 0.440501] Serial: AMBA PL011 UART driver
10493 11:57:08.622804 <4>[ 0.449278] Trying to register duplicate clock ID: 134
10494 11:57:08.676847 <6>[ 0.506915] KASLR enabled
10495 11:57:08.691843 <6>[ 0.514595] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10496 11:57:08.697918 <6>[ 0.521612] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10497 11:57:08.704372 <6>[ 0.528102] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10498 11:57:08.711658 <6>[ 0.535108] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10499 11:57:08.717676 <6>[ 0.541596] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10500 11:57:08.724557 <6>[ 0.548602] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10501 11:57:08.731515 <6>[ 0.555091] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10502 11:57:08.738378 <6>[ 0.562097] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10503 11:57:08.741595 <6>[ 0.569592] ACPI: Interpreter disabled.
10504 11:57:08.749438 <6>[ 0.575994] iommu: Default domain type: Translated
10505 11:57:08.756062 <6>[ 0.581106] iommu: DMA domain TLB invalidation policy: strict mode
10506 11:57:08.759076 <5>[ 0.587767] SCSI subsystem initialized
10507 11:57:08.766040 <6>[ 0.591935] usbcore: registered new interface driver usbfs
10508 11:57:08.772589 <6>[ 0.597669] usbcore: registered new interface driver hub
10509 11:57:08.775786 <6>[ 0.603221] usbcore: registered new device driver usb
10510 11:57:08.782642 <6>[ 0.609328] pps_core: LinuxPPS API ver. 1 registered
10511 11:57:08.792706 <6>[ 0.614522] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10512 11:57:08.796227 <6>[ 0.623870] PTP clock support registered
10513 11:57:08.799242 <6>[ 0.628113] EDAC MC: Ver: 3.0.0
10514 11:57:08.806781 <6>[ 0.633286] FPGA manager framework
10515 11:57:08.809915 <6>[ 0.636966] Advanced Linux Sound Architecture Driver Initialized.
10516 11:57:08.813744 <6>[ 0.643739] vgaarb: loaded
10517 11:57:08.820431 <6>[ 0.646911] clocksource: Switched to clocksource arch_sys_counter
10518 11:57:08.826765 <5>[ 0.653343] VFS: Disk quotas dquot_6.6.0
10519 11:57:08.833615 <6>[ 0.657527] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10520 11:57:08.837212 <6>[ 0.664713] pnp: PnP ACPI: disabled
10521 11:57:08.845036 <6>[ 0.671359] NET: Registered PF_INET protocol family
10522 11:57:08.854786 <6>[ 0.676956] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10523 11:57:08.866054 <6>[ 0.689277] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10524 11:57:08.876056 <6>[ 0.698091] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10525 11:57:08.882850 <6>[ 0.706063] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10526 11:57:08.889330 <6>[ 0.714765] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10527 11:57:08.901006 <6>[ 0.724518] TCP: Hash tables configured (established 65536 bind 65536)
10528 11:57:08.907712 <6>[ 0.731375] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10529 11:57:08.914380 <6>[ 0.738574] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10530 11:57:08.920900 <6>[ 0.746274] NET: Registered PF_UNIX/PF_LOCAL protocol family
10531 11:57:08.927459 <6>[ 0.752449] RPC: Registered named UNIX socket transport module.
10532 11:57:08.930558 <6>[ 0.758602] RPC: Registered udp transport module.
10533 11:57:08.937642 <6>[ 0.763537] RPC: Registered tcp transport module.
10534 11:57:08.944157 <6>[ 0.768469] RPC: Registered tcp NFSv4.1 backchannel transport module.
10535 11:57:08.947637 <6>[ 0.775140] PCI: CLS 0 bytes, default 64
10536 11:57:08.950487 <6>[ 0.779529] Unpacking initramfs...
10537 11:57:08.976131 <6>[ 0.799023] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10538 11:57:08.985855 <6>[ 0.807668] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10539 11:57:08.989370 <6>[ 0.816530] kvm [1]: IPA Size Limit: 40 bits
10540 11:57:08.995324 <6>[ 0.821059] kvm [1]: GICv3: no GICV resource entry
10541 11:57:08.998595 <6>[ 0.826083] kvm [1]: disabling GICv2 emulation
10542 11:57:09.005399 <6>[ 0.830778] kvm [1]: GIC system register CPU interface enabled
10543 11:57:09.009183 <6>[ 0.836945] kvm [1]: vgic interrupt IRQ18
10544 11:57:09.015466 <6>[ 0.841311] kvm [1]: VHE mode initialized successfully
10545 11:57:09.022317 <5>[ 0.847804] Initialise system trusted keyrings
10546 11:57:09.029101 <6>[ 0.852684] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10547 11:57:09.036252 <6>[ 0.862701] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10548 11:57:09.042648 <5>[ 0.869109] NFS: Registering the id_resolver key type
10549 11:57:09.046410 <5>[ 0.874413] Key type id_resolver registered
10550 11:57:09.052525 <5>[ 0.878829] Key type id_legacy registered
10551 11:57:09.059390 <6>[ 0.883106] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10552 11:57:09.066184 <6>[ 0.890029] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10553 11:57:09.073028 <6>[ 0.897751] 9p: Installing v9fs 9p2000 file system support
10554 11:57:09.109903 <5>[ 0.936258] Key type asymmetric registered
10555 11:57:09.112751 <5>[ 0.940589] Asymmetric key parser 'x509' registered
10556 11:57:09.122943 <6>[ 0.945793] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10557 11:57:09.126230 <6>[ 0.953418] io scheduler mq-deadline registered
10558 11:57:09.129795 <6>[ 0.958187] io scheduler kyber registered
10559 11:57:09.148827 <6>[ 0.975365] EINJ: ACPI disabled.
10560 11:57:09.181090 <4>[ 1.001076] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10561 11:57:09.191143 <4>[ 1.011708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10562 11:57:09.205832 <6>[ 1.032479] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10563 11:57:09.214002 <6>[ 1.040539] printk: console [ttyS0] disabled
10564 11:57:09.242152 <6>[ 1.065183] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10565 11:57:09.248161 <6>[ 1.074660] printk: console [ttyS0] enabled
10566 11:57:09.251866 <6>[ 1.074660] printk: console [ttyS0] enabled
10567 11:57:09.258235 <6>[ 1.083553] printk: bootconsole [mtk8250] disabled
10568 11:57:09.261774 <6>[ 1.083553] printk: bootconsole [mtk8250] disabled
10569 11:57:09.268229 <6>[ 1.094770] SuperH (H)SCI(F) driver initialized
10570 11:57:09.271677 <6>[ 1.100045] msm_serial: driver initialized
10571 11:57:09.285671 <6>[ 1.109062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10572 11:57:09.295371 <6>[ 1.117609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10573 11:57:09.302033 <6>[ 1.126152] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10574 11:57:09.312531 <6>[ 1.134781] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10575 11:57:09.318841 <6>[ 1.143487] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10576 11:57:09.329193 <6>[ 1.152203] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10577 11:57:09.338761 <6>[ 1.160743] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10578 11:57:09.345486 <6>[ 1.169550] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10579 11:57:09.355135 <6>[ 1.178096] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10580 11:57:09.367066 <6>[ 1.193663] loop: module loaded
10581 11:57:09.373467 <6>[ 1.199767] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10582 11:57:09.396342 <4>[ 1.223172] mtk-pmic-keys: Failed to locate of_node [id: -1]
10583 11:57:09.403846 <6>[ 1.230280] megasas: 07.719.03.00-rc1
10584 11:57:09.413278 <6>[ 1.239772] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10585 11:57:09.419928 <6>[ 1.246284] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10586 11:57:09.436704 <6>[ 1.262898] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10587 11:57:09.493108 <6>[ 1.313058] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10588 11:57:09.744578 <6>[ 1.571434] Freeing initrd memory: 18312K
10589 11:57:09.756869 <6>[ 1.583230] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10590 11:57:09.767494 <6>[ 1.594081] tun: Universal TUN/TAP device driver, 1.6
10591 11:57:09.770491 <6>[ 1.600137] thunder_xcv, ver 1.0
10592 11:57:09.774044 <6>[ 1.603638] thunder_bgx, ver 1.0
10593 11:57:09.777587 <6>[ 1.607135] nicpf, ver 1.0
10594 11:57:09.787337 <6>[ 1.611147] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10595 11:57:09.790791 <6>[ 1.618621] hns3: Copyright (c) 2017 Huawei Corporation.
10596 11:57:09.797609 <6>[ 1.624210] hclge is initializing
10597 11:57:09.801002 <6>[ 1.627787] e1000: Intel(R) PRO/1000 Network Driver
10598 11:57:09.807492 <6>[ 1.632916] e1000: Copyright (c) 1999-2006 Intel Corporation.
10599 11:57:09.810939 <6>[ 1.638928] e1000e: Intel(R) PRO/1000 Network Driver
10600 11:57:09.817281 <6>[ 1.644144] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10601 11:57:09.824682 <6>[ 1.650328] igb: Intel(R) Gigabit Ethernet Network Driver
10602 11:57:09.831369 <6>[ 1.655977] igb: Copyright (c) 2007-2014 Intel Corporation.
10603 11:57:09.837967 <6>[ 1.661812] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10604 11:57:09.841457 <6>[ 1.668330] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10605 11:57:09.848438 <6>[ 1.674795] sky2: driver version 1.30
10606 11:57:09.855009 <6>[ 1.679787] VFIO - User Level meta-driver version: 0.3
10607 11:57:09.861065 <6>[ 1.688020] usbcore: registered new interface driver usb-storage
10608 11:57:09.868048 <6>[ 1.694468] usbcore: registered new device driver onboard-usb-hub
10609 11:57:09.876770 <6>[ 1.703636] mt6397-rtc mt6359-rtc: registered as rtc0
10610 11:57:09.886855 <6>[ 1.709102] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:57:09 UTC (1700740629)
10611 11:57:09.890113 <6>[ 1.718662] i2c_dev: i2c /dev entries driver
10612 11:57:09.907142 <6>[ 1.730386] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10613 11:57:09.927248 <6>[ 1.753384] cpu cpu0: EM: created perf domain
10614 11:57:09.930123 <6>[ 1.758311] cpu cpu4: EM: created perf domain
10615 11:57:09.937389 <6>[ 1.763897] sdhci: Secure Digital Host Controller Interface driver
10616 11:57:09.944178 <6>[ 1.770329] sdhci: Copyright(c) Pierre Ossman
10617 11:57:09.950342 <6>[ 1.775284] Synopsys Designware Multimedia Card Interface Driver
10618 11:57:09.957095 <6>[ 1.781916] sdhci-pltfm: SDHCI platform and OF driver helper
10619 11:57:09.961268 <6>[ 1.781946] mmc0: CQHCI version 5.10
10620 11:57:09.967102 <6>[ 1.792147] ledtrig-cpu: registered to indicate activity on CPUs
10621 11:57:09.974350 <6>[ 1.799125] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10622 11:57:09.980821 <6>[ 1.806180] usbcore: registered new interface driver usbhid
10623 11:57:09.984254 <6>[ 1.812005] usbhid: USB HID core driver
10624 11:57:09.990704 <6>[ 1.816201] spi_master spi0: will run message pump with realtime priority
10625 11:57:10.034536 <6>[ 1.854994] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10626 11:57:10.049930 <6>[ 1.870033] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10627 11:57:10.058282 <6>[ 1.884928] cros-ec-spi spi0.0: Chrome EC device registered
10628 11:57:10.064662 <6>[ 1.890944] mmc0: Command Queue Engine enabled
10629 11:57:10.071581 <6>[ 1.895676] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10630 11:57:10.074690 <6>[ 1.903277] mmcblk0: mmc0:0001 DA4128 116 GiB
10631 11:57:10.085224 <6>[ 1.903822] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10632 11:57:10.092539 <6>[ 1.913412] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10633 11:57:10.095176 <6>[ 1.918384] NET: Registered PF_PACKET protocol family
10634 11:57:10.101632 <6>[ 1.924433] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10635 11:57:10.104921 <6>[ 1.928594] 9pnet: Installing 9P2000 support
10636 11:57:10.111642 <6>[ 1.934355] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10637 11:57:10.114950 <5>[ 1.938294] Key type dns_resolver registered
10638 11:57:10.121683 <6>[ 1.944139] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10639 11:57:10.128291 <6>[ 1.948457] registered taskstats version 1
10640 11:57:10.131828 <5>[ 1.958912] Loading compiled-in X.509 certificates
10641 11:57:10.161634 <4>[ 1.982040] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 11:57:10.172098 <4>[ 1.992736] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10643 11:57:10.178833 <3>[ 2.003262] debugfs: File 'uA_load' in directory '/' already present!
10644 11:57:10.185545 <3>[ 2.009960] debugfs: File 'min_uV' in directory '/' already present!
10645 11:57:10.192447 <3>[ 2.016625] debugfs: File 'max_uV' in directory '/' already present!
10646 11:57:10.198619 <3>[ 2.023238] debugfs: File 'constraint_flags' in directory '/' already present!
10647 11:57:10.209093 <3>[ 2.032740] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10648 11:57:10.218094 <6>[ 2.044861] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10649 11:57:10.224952 <6>[ 2.051785] xhci-mtk 11200000.usb: xHCI Host Controller
10650 11:57:10.231536 <6>[ 2.057279] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10651 11:57:10.241896 <6>[ 2.065226] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10652 11:57:10.249144 <6>[ 2.074665] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10653 11:57:10.255488 <6>[ 2.080749] xhci-mtk 11200000.usb: xHCI Host Controller
10654 11:57:10.261864 <6>[ 2.086233] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10655 11:57:10.268578 <6>[ 2.093880] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10656 11:57:10.275070 <6>[ 2.101731] hub 1-0:1.0: USB hub found
10657 11:57:10.278260 <6>[ 2.105750] hub 1-0:1.0: 1 port detected
10658 11:57:10.285226 <6>[ 2.110020] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10659 11:57:10.292413 <6>[ 2.118758] hub 2-0:1.0: USB hub found
10660 11:57:10.295182 <6>[ 2.122775] hub 2-0:1.0: 1 port detected
10661 11:57:10.304123 <6>[ 2.130972] mtk-msdc 11f70000.mmc: Got CD GPIO
10662 11:57:10.314027 <6>[ 2.137424] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10663 11:57:10.321072 <6>[ 2.145453] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10664 11:57:10.331051 <4>[ 2.153360] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10665 11:57:10.337834 <6>[ 2.162882] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10666 11:57:10.347871 <6>[ 2.170958] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10667 11:57:10.354233 <6>[ 2.178979] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10668 11:57:10.364375 <6>[ 2.186901] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10669 11:57:10.371033 <6>[ 2.194720] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10670 11:57:10.381044 <6>[ 2.202537] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10671 11:57:10.390617 <6>[ 2.212909] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10672 11:57:10.397888 <6>[ 2.221270] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10673 11:57:10.407898 <6>[ 2.229610] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10674 11:57:10.414645 <6>[ 2.237948] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10675 11:57:10.421206 <6>[ 2.246287] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10676 11:57:10.431476 <6>[ 2.254636] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10677 11:57:10.438088 <6>[ 2.262976] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10678 11:57:10.448038 <6>[ 2.271315] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10679 11:57:10.454738 <6>[ 2.279652] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10680 11:57:10.464469 <6>[ 2.287992] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10681 11:57:10.471131 <6>[ 2.296330] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10682 11:57:10.481676 <6>[ 2.304669] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10683 11:57:10.491209 <6>[ 2.313011] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10684 11:57:10.497907 <6>[ 2.321349] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10685 11:57:10.507320 <6>[ 2.329688] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10686 11:57:10.514224 <6>[ 2.338422] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10687 11:57:10.521174 <6>[ 2.345557] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10688 11:57:10.527474 <6>[ 2.352326] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10689 11:57:10.534405 <6>[ 2.359093] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10690 11:57:10.541110 <6>[ 2.366032] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10691 11:57:10.550906 <6>[ 2.372878] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10692 11:57:10.560834 <6>[ 2.382006] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10693 11:57:10.567709 <6>[ 2.391126] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10694 11:57:10.576919 <6>[ 2.400418] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10695 11:57:10.587521 <6>[ 2.409889] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10696 11:57:10.597133 <6>[ 2.419356] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10697 11:57:10.607204 <6>[ 2.428476] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10698 11:57:10.613720 <6>[ 2.437954] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10699 11:57:10.623755 <6>[ 2.447074] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10700 11:57:10.633793 <6>[ 2.456369] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10701 11:57:10.643742 <6>[ 2.466529] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10702 11:57:10.654385 <6>[ 2.477837] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10703 11:57:10.660854 <6>[ 2.487682] Trying to probe devices needed for running init ...
10704 11:57:10.703700 <6>[ 2.527189] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10705 11:57:10.858322 <6>[ 2.685033] hub 1-1:1.0: USB hub found
10706 11:57:10.862032 <6>[ 2.689542] hub 1-1:1.0: 4 ports detected
10707 11:57:10.870717 <6>[ 2.697952] hub 1-1:1.0: USB hub found
10708 11:57:10.874050 <6>[ 2.702441] hub 1-1:1.0: 4 ports detected
10709 11:57:10.983733 <6>[ 2.807327] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10710 11:57:11.009943 <6>[ 2.836783] hub 2-1:1.0: USB hub found
10711 11:57:11.013524 <6>[ 2.841282] hub 2-1:1.0: 3 ports detected
10712 11:57:11.022480 <6>[ 2.849117] hub 2-1:1.0: USB hub found
10713 11:57:11.025719 <6>[ 2.853570] hub 2-1:1.0: 3 ports detected
10714 11:57:11.199139 <6>[ 3.023209] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10715 11:57:11.331899 <6>[ 3.158692] hub 1-1.4:1.0: USB hub found
10716 11:57:11.335009 <6>[ 3.163295] hub 1-1.4:1.0: 2 ports detected
10717 11:57:11.344036 <6>[ 3.170821] hub 1-1.4:1.0: USB hub found
10718 11:57:11.346825 <6>[ 3.175427] hub 1-1.4:1.0: 2 ports detected
10719 11:57:11.411668 <6>[ 3.235384] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10720 11:57:11.643389 <6>[ 3.467226] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10721 11:57:11.835631 <6>[ 3.659210] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10722 11:57:22.936379 <6>[ 14.768192] ALSA device list:
10723 11:57:22.942730 <6>[ 14.771487] No soundcards found.
10724 11:57:22.950995 <6>[ 14.779446] Freeing unused kernel memory: 8384K
10725 11:57:22.954395 <6>[ 14.784432] Run /init as init process
10726 11:57:22.966475 Loading, please wait...
10727 11:57:22.996162 Starting systemd-udevd version 252.6-1
10728 11:57:23.282480 <6>[ 15.107508] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10729 11:57:23.288986 <6>[ 15.107838] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10730 11:57:23.298798 <6>[ 15.115296] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10731 11:57:23.305647 <3>[ 15.117698] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10732 11:57:23.315425 <3>[ 15.117707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 11:57:23.321900 <3>[ 15.117710] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10734 11:57:23.328598 <3>[ 15.117776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10735 11:57:23.338644 <3>[ 15.117780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10736 11:57:23.345130 <3>[ 15.117783] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10737 11:57:23.355591 <3>[ 15.117787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10738 11:57:23.362160 <3>[ 15.117789] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10739 11:57:23.371836 <3>[ 15.117807] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10740 11:57:23.378720 <3>[ 15.117825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10741 11:57:23.385623 <3>[ 15.117828] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10742 11:57:23.394968 <3>[ 15.117831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10743 11:57:23.402041 <3>[ 15.117846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10744 11:57:23.412146 <3>[ 15.117848] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 11:57:23.418582 <3>[ 15.117852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 11:57:23.428203 <3>[ 15.117854] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 11:57:23.435121 <3>[ 15.117857] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 11:57:23.445054 <3>[ 15.117869] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 11:57:23.451746 <4>[ 15.132336] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10750 11:57:23.458613 <6>[ 15.139699] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10751 11:57:23.464816 <6>[ 15.140128] remoteproc remoteproc0: scp is available
10752 11:57:23.468268 <6>[ 15.140199] remoteproc remoteproc0: powering up scp
10753 11:57:23.478191 <6>[ 15.140204] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10754 11:57:23.485254 <6>[ 15.140216] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10755 11:57:23.491494 <4>[ 15.154493] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10756 11:57:23.498353 <6>[ 15.159995] usbcore: registered new interface driver r8152
10757 11:57:23.502180 <6>[ 15.173694] mc: Linux media interface: v0.10
10758 11:57:23.508859 <6>[ 15.182504] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10759 11:57:23.515803 <6>[ 15.259405] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10760 11:57:23.522702 <6>[ 15.261738] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10761 11:57:23.533007 <6>[ 15.261780] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10762 11:57:23.539279 <6>[ 15.261787] remoteproc remoteproc0: remote processor scp is now up
10763 11:57:23.545914 <6>[ 15.280162] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10764 11:57:23.555956 <6>[ 15.286600] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10765 11:57:23.562610 <6>[ 15.292820] pci_bus 0000:00: root bus resource [bus 00-ff]
10766 11:57:23.569242 <6>[ 15.292824] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10767 11:57:23.579284 <6>[ 15.292826] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10768 11:57:23.585892 <6>[ 15.292859] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10769 11:57:23.592516 <6>[ 15.292872] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10770 11:57:23.596066 <6>[ 15.292939] pci 0000:00:00.0: supports D1 D2
10771 11:57:23.603052 <6>[ 15.292940] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10772 11:57:23.612726 <6>[ 15.293840] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10773 11:57:23.622716 <6>[ 15.298455] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10774 11:57:23.628778 <6>[ 15.298823] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10775 11:57:23.639463 <4>[ 15.301368] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10776 11:57:23.645836 <4>[ 15.301374] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10777 11:57:23.652103 <6>[ 15.303423] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10778 11:57:23.662189 <4>[ 15.305736] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10779 11:57:23.665715 <4>[ 15.305736] Fallback method does not support PEC.
10780 11:57:23.672482 <6>[ 15.332199] videodev: Linux video capture interface: v2.00
10781 11:57:23.682542 <3>[ 15.334825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10782 11:57:23.689320 <6>[ 15.335331] usbcore: registered new interface driver cdc_ether
10783 11:57:23.695616 <6>[ 15.336880] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10784 11:57:23.702059 <6>[ 15.336900] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10785 11:57:23.708757 <6>[ 15.336915] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10786 11:57:23.715528 <6>[ 15.337031] pci 0000:01:00.0: supports D1 D2
10787 11:57:23.722076 <6>[ 15.337033] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10788 11:57:23.728323 <6>[ 15.344859] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10789 11:57:23.732079 <6>[ 15.350655] Bluetooth: Core ver 2.22
10790 11:57:23.742270 <6>[ 15.351013] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10791 11:57:23.748744 <6>[ 15.351057] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10792 11:57:23.754985 <6>[ 15.351062] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10793 11:57:23.765628 <6>[ 15.351070] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10794 11:57:23.772042 <6>[ 15.351083] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10795 11:57:23.782072 <6>[ 15.351096] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10796 11:57:23.785203 <6>[ 15.351109] pci 0000:00:00.0: PCI bridge to [bus 01]
10797 11:57:23.792129 <6>[ 15.351114] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10798 11:57:23.799041 <6>[ 15.351246] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10799 11:57:23.805306 <6>[ 15.351760] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10800 11:57:23.812050 <6>[ 15.352238] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10801 11:57:23.821854 <3>[ 15.355721] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10802 11:57:23.825233 <6>[ 15.359066] r8152 2-1.3:1.0 eth0: v1.12.13
10803 11:57:23.832033 <6>[ 15.361008] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10804 11:57:23.838099 <6>[ 15.365684] NET: Registered PF_BLUETOOTH protocol family
10805 11:57:23.847953 <5>[ 15.391835] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10806 11:57:23.854976 <6>[ 15.394721] Bluetooth: HCI device and connection manager initialized
10807 11:57:23.857876 <6>[ 15.394998] usbcore: registered new interface driver r8153_ecm
10808 11:57:23.864827 <6>[ 15.396035] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10809 11:57:23.878540 <6>[ 15.402096] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10810 11:57:23.885432 <6>[ 15.408427] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10811 11:57:23.891541 <6>[ 15.411818] Bluetooth: HCI socket layer initialized
10812 11:57:23.898407 <5>[ 15.417861] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10813 11:57:23.901155 <6>[ 15.418262] usbcore: registered new interface driver uvcvideo
10814 11:57:23.908318 <6>[ 15.425536] Bluetooth: L2CAP socket layer initialized
10815 11:57:23.914817 <6>[ 15.437695] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10816 11:57:23.918446 <6>[ 15.445182] Bluetooth: SCO socket layer initialized
10817 11:57:23.928491 <6>[ 15.756936] usbcore: registered new interface driver btusb
10818 11:57:23.938251 <4>[ 15.757875] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10819 11:57:23.944810 <3>[ 15.773269] Bluetooth: hci0: Failed to load firmware file (-2)
10820 11:57:23.951525 <3>[ 15.779505] Bluetooth: hci0: Failed to set up firmware (-2)
10821 11:57:23.961739 <4>[ 15.785451] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10822 11:57:23.964900 <6>[ 15.794332] cfg80211: failed to load regulatory.db
10823 11:57:23.974958 <4>[ 15.799388] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10824 11:57:24.015131 <6>[ 15.839863] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10825 11:57:24.021280 <6>[ 15.847378] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10826 11:57:24.045674 <6>[ 15.874087] mt7921e 0000:01:00.0: ASIC revision: 79610010
10827 11:57:24.153575 <4>[ 15.975051] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10828 11:57:24.156250 Begin: Loading essential drivers ... done.
10829 11:57:24.163273 Begin: Running /scripts/init-premount ... done.
10830 11:57:24.169555 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10831 11:57:24.176737 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10832 11:57:24.183194 Device /sys/class/net/enx002432307852 found
10833 11:57:24.183763 done.
10834 11:57:24.193363 Begin: Waiting up to 180 secs for any network device to become available ... done.
10835 11:57:24.266546 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10836 11:57:24.276330 <4>[ 16.099256] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10837 11:57:24.395710 <4>[ 16.217747] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10838 11:57:24.512811 <4>[ 16.334535] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10839 11:57:24.632873 <4>[ 16.454606] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10840 11:57:24.752232 <4>[ 16.574509] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10841 11:57:24.872881 <4>[ 16.694582] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10842 11:57:24.992892 <4>[ 16.814427] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 11:57:25.104598 <4>[ 16.926452] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10844 11:57:25.224344 <4>[ 17.046402] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 11:57:25.251864 <6>[ 17.080633] r8152 2-1.3:1.0 enx002432307852: carrier on
10846 11:57:25.335978 <3>[ 17.164719] mt7921e 0000:01:00.0: hardware init failed
10847 11:57:25.380721 IP-Config: no response after 2 secs - giving up
10848 11:57:25.414344 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10849 11:57:25.422703 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10850 11:57:25.429174 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10851 11:57:25.435787 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10852 11:57:25.443197 host : mt8192-asurada-spherion-r0-cbg-3
10853 11:57:25.449297 domain : lava-rack
10854 11:57:25.452221 rootserver: 192.168.201.1 rootpath:
10855 11:57:25.456029 filename :
10856 11:57:25.571692 done.
10857 11:57:25.579498 Begin: Running /scripts/nfs-bottom ... done.
10858 11:57:25.602726 Begin: Running /scripts/init-bottom ... done.
10859 11:57:26.960999 <6>[ 18.790423] NET: Registered PF_INET6 protocol family
10860 11:57:26.968248 <6>[ 18.797380] Segment Routing with IPv6
10861 11:57:26.971323 <6>[ 18.801343] In-situ OAM (IOAM) with IPv6
10862 11:57:27.161927 <30>[ 18.964328] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10863 11:57:27.168744 <30>[ 18.996692] systemd[1]: Detected architecture arm64.
10864 11:57:27.179421
10865 11:57:27.182417 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10866 11:57:27.182922
10867 11:57:27.208249 <30>[ 19.037359] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10868 11:57:28.425247 <30>[ 20.251421] systemd[1]: Queued start job for default target graphical.target.
10869 11:57:28.470224 <30>[ 20.295930] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10870 11:57:28.476956 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10871 11:57:28.499147 <30>[ 20.325072] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10872 11:57:28.508838 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10873 11:57:28.527277 <30>[ 20.352999] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10874 11:57:28.537321 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10875 11:57:28.555563 <30>[ 20.381238] systemd[1]: Created slice user.slice - User and Session Slice.
10876 11:57:28.561959 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10877 11:57:28.585983 <30>[ 20.408120] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10878 11:57:28.592506 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10879 11:57:28.612993 <30>[ 20.435450] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10880 11:57:28.619482 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10881 11:57:28.648640 <30>[ 20.463868] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10882 11:57:28.658572 <30>[ 20.483866] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10883 11:57:28.664898 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10884 11:57:28.686304 <30>[ 20.511693] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10885 11:57:28.696148 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10886 11:57:28.711031 <30>[ 20.539646] systemd[1]: Reached target paths.target - Path Units.
10887 11:57:28.717726 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10888 11:57:28.738095 <30>[ 20.563688] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10889 11:57:28.744501 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10890 11:57:28.758297 <30>[ 20.587186] systemd[1]: Reached target slices.target - Slice Units.
10891 11:57:28.768125 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10892 11:57:28.782382 <30>[ 20.611698] systemd[1]: Reached target swap.target - Swaps.
10893 11:57:28.789546 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10894 11:57:28.809855 <30>[ 20.635637] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10895 11:57:28.819524 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10896 11:57:28.838131 <30>[ 20.663695] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10897 11:57:28.847679 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10898 11:57:28.869384 <30>[ 20.694889] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10899 11:57:28.879458 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10900 11:57:28.894753 <30>[ 20.720853] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10901 11:57:28.904699 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10902 11:57:28.922112 <30>[ 20.747903] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10903 11:57:28.928316 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10904 11:57:28.947182 <30>[ 20.772870] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10905 11:57:28.957373 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10906 11:57:28.977538 <30>[ 20.802869] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10907 11:57:28.986918 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10908 11:57:29.001877 <30>[ 20.827670] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10909 11:57:29.008478 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10910 11:57:29.073814 <30>[ 20.899697] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10911 11:57:29.080118 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10912 11:57:29.099614 <30>[ 20.926042] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10913 11:57:29.106011 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10914 11:57:29.129220 <30>[ 20.955554] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10915 11:57:29.136004 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10916 11:57:29.164007 <30>[ 20.983461] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10917 11:57:29.217872 <30>[ 21.043822] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10918 11:57:29.227844 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10919 11:57:29.250803 <30>[ 21.076707] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10920 11:57:29.257506 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10921 11:57:29.322576 <30>[ 21.147789] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10922 11:57:29.328332 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10923 11:57:29.355545 <30>[ 21.181266] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10924 11:57:29.361685 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10925 11:57:29.387495 <30>[ 21.213185] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10926 11:57:29.400617 Starting [0;1;39mmodpr<6>[ 21.224822] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10927 11:57:29.403964 obe@efi_psto…- Load Kernel Module efi_pstore...
10928 11:57:29.426756 <30>[ 21.252831] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10929 11:57:29.433460 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10930 11:57:29.457954 <30>[ 21.283612] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10931 11:57:29.464285 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop...
10932 11:57:29.487023 <6>[ 21.316615] fuse: init (API version 7.37)
10933 11:57:29.534147 <30>[ 21.360157] systemd[1]: Starting systemd-journald.service - Journal Service...
10934 11:57:29.541049 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10935 11:57:29.574222 <30>[ 21.400218] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10936 11:57:29.581089 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10937 11:57:29.608530 <30>[ 21.431168] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10938 11:57:29.614975 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10939 11:57:29.673985 <30>[ 21.500004] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10940 11:57:29.683907 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10941 11:57:29.705243 <30>[ 21.531221] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10942 11:57:29.711887 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10943 11:57:29.739597 <30>[ 21.565710] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10944 11:57:29.746680 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10945 11:57:29.767123 <30>[ 21.593394] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10946 11:57:29.774201 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10947 11:57:29.791765 <3>[ 21.617521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:57:29.801550 <30>[ 21.627095] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10949 11:57:29.808270 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10950 11:57:29.826175 <30>[ 21.652023] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10951 11:57:29.836063 <3>[ 21.655934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10952 11:57:29.842712 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10953 11:57:29.862418 <30>[ 21.688045] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10954 11:57:29.868925 <30>[ 21.695938] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10955 11:57:29.886374 [[0;32m OK [0m] Finished [0;1;39mmodprobe@configfs…[0m - <3>[ 21.708971] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10956 11:57:29.886966 Load Kernel Module configfs.
10957 11:57:29.903035 <30>[ 21.731912] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10958 11:57:29.913334 <3>[ 21.739329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10959 11:57:29.923068 <30>[ 21.739578] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10960 11:57:29.930553 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10961 11:57:29.942394 <3>[ 21.768035] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10962 11:57:29.952688 <30>[ 21.778659] systemd[1]: modprobe@drm.service: Deactivated successfully.
10963 11:57:29.959657 <30>[ 21.786369] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10964 11:57:29.973743 [[0;32m OK [0m] Finished [0;1;39mmodprobe@d<3>[ 21.797099] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:57:29.977326 rm.service[0m - Load Kernel Module drm.
10966 11:57:29.994720 <30>[ 21.820220] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10967 11:57:30.001099 <3>[ 21.827708] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10968 11:57:30.010981 <30>[ 21.828464] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10969 11:57:30.018013 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10970 11:57:30.032029 <3>[ 21.857742] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 11:57:30.042256 <30>[ 21.868496] systemd[1]: modprobe@fuse.service: Deactivated successfully.
10972 11:57:30.049415 <30>[ 21.876404] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
10973 11:57:30.063030 [[0;32m OK [0m] Finished [0;1;39mmodprobe@f<3>[ 21.887446] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 11:57:30.066276 use.service[0m - Load Kernel Module fuse.
10975 11:57:30.088179 <30>[ 21.914008] systemd[1]: modprobe@loop.service: Deactivated successfully.
10976 11:57:30.094420 <30>[ 21.922071] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
10977 11:57:30.108880 [[0;32m OK [0m] Finished [0;1;39mmodprobe@l<3>[ 21.933387] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10978 11:57:30.111555 oop.service[0m - Load Kernel Module loop.
10979 11:57:30.130733 <30>[ 21.956531] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
10980 11:57:30.137717 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
10981 11:57:30.162094 <30>[ 21.983804] systemd[1]: Finished systemd-network-generator.service - Generate network units from Kernel command line.
10982 11:57:30.178705 [[0;32m OK [0m] Finished [0;1;39msystemd-ne<4>[ 21.997694] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10983 11:57:30.188645 <3>[ 22.014677] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10984 11:57:30.191938 twork-g…rk units from Kernel command line.
10985 11:57:30.212230 <30>[ 22.037625] systemd[1]: Started systemd-journald.service - Journal Service.
10986 11:57:30.218824 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
10987 11:57:30.241534 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
10988 11:57:30.258922 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
10989 11:57:30.280295 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
10990 11:57:30.329961 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
10991 11:57:30.352139 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
10992 11:57:30.375245 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
10993 11:57:30.399366 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
10994 11:57:30.449393 <46>[ 22.275506] systemd-journald[302]: Received client request to flush runtime journal.
10995 11:57:30.455889 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
10996 11:57:30.482059 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
10997 11:57:30.776248 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
10998 11:57:30.793581 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
10999 11:57:30.820674 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11000 11:57:31.230394 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11001 11:57:31.852857 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11002 11:57:31.872187 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11003 11:57:31.934357 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11004 11:57:32.050781 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11005 11:57:32.074498 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11006 11:57:32.093713 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11007 11:57:32.145443 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11008 11:57:32.166592 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11009 11:57:32.191750 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11010 11:57:32.233852 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11011 11:57:32.249465 See 'systemctl status systemd-binfmt.service' for details.
11012 11:57:32.451049 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11013 11:57:32.502994 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11014 11:57:32.590402 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11015 11:57:32.808023 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11016 11:57:32.965775 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11017 11:57:32.988193 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11018 11:57:33.087176 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11019 11:57:33.104906 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11020 11:57:33.121183 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11021 11:57:33.161402 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11022 11:57:33.181659 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11023 11:57:33.223944 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11024 11:57:33.286789 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11025 11:57:33.311963 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11026 11:57:33.339022 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11027 11:57:33.359387 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11028 11:57:33.382670 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11029 11:57:33.413439 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11030 11:57:33.431819 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11031 11:57:33.459731 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11032 11:57:33.480545 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11033 11:57:33.496215 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11034 11:57:33.519345 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11035 11:57:33.542059 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11036 11:57:33.560684 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11037 11:57:33.576345 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11038 11:57:33.592879 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11039 11:57:33.610387 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11040 11:57:33.626008 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11041 11:57:33.679392 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11042 11:57:33.776000 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11043 11:57:33.875518 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11044 11:57:33.901074 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11045 11:57:34.034752 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11046 11:57:34.085127 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11047 11:57:34.119838 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11048 11:57:34.126302 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11049 11:57:34.148080 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11050 11:57:34.183401 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11051 11:57:34.209903 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11052 11:57:34.242533 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11053 11:57:34.261202 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11054 11:57:34.338626 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11055 11:57:34.360525 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11056 11:57:34.424376 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11057 11:57:34.524396 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11058 11:57:34.612664
11059 11:57:34.613273
11060 11:57:34.615781 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11061 11:57:34.616243
11062 11:57:34.619409 debian-bookworm-arm64 login: root (automatic login)
11063 11:57:34.619822
11064 11:57:34.620146
11065 11:57:34.971857 Linux debian-bookworm-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
11066 11:57:34.972352
11067 11:57:34.978358 The programs included with the Debian GNU/Linux system are free software;
11068 11:57:34.985148 the exact distribution terms for each program are described in the
11069 11:57:34.988315 individual files in /usr/share/doc/*/copyright.
11070 11:57:34.988808
11071 11:57:34.994681 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11072 11:57:34.998407 permitted by applicable law.
11073 11:57:36.176360 Matched prompt #10: / #
11075 11:57:36.177492 Setting prompt string to ['/ #']
11076 11:57:36.177923 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11078 11:57:36.178928 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11079 11:57:36.179376 start: 2.2.6 expect-shell-connection (timeout 00:03:09) [common]
11080 11:57:36.179718 Setting prompt string to ['/ #']
11081 11:57:36.180022 Forcing a shell prompt, looking for ['/ #']
11083 11:57:36.230814 / #
11084 11:57:36.231479 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11085 11:57:36.231935 Waiting using forced prompt support (timeout 00:02:30)
11086 11:57:36.237509
11087 11:57:36.238445 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11088 11:57:36.239031 start: 2.2.7 export-device-env (timeout 00:03:09) [common]
11090 11:57:36.340510 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui'
11091 11:57:36.346845 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066559/extract-nfsrootfs-x6fko5ui'
11093 11:57:36.448518 / # export NFS_SERVER_IP='192.168.201.1'
11094 11:57:36.455442 export NFS_SERVER_IP='192.168.201.1'
11095 11:57:36.456376 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11096 11:57:36.456927 end: 2.2 depthcharge-retry (duration 00:01:51) [common]
11097 11:57:36.457417 end: 2 depthcharge-action (duration 00:01:51) [common]
11098 11:57:36.457919 start: 3 lava-test-retry (timeout 00:07:20) [common]
11099 11:57:36.458467 start: 3.1 lava-test-shell (timeout 00:07:20) [common]
11100 11:57:36.458904 Using namespace: common
11102 11:57:36.560098 / # #
11103 11:57:36.560727 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11104 11:57:36.566812 #
11105 11:57:36.567790 Using /lava-12066559
11107 11:57:36.668961 / # export SHELL=/bin/bash
11108 11:57:36.675536 export SHELL=/bin/bash
11110 11:57:36.776985 / # . /lava-12066559/environment
11111 11:57:36.783386 . /lava-12066559/environment
11113 11:57:36.890838 / # /lava-12066559/bin/lava-test-runner /lava-12066559/0
11114 11:57:36.891543 Test shell timeout: 10s (minimum of the action and connection timeout)
11115 11:57:36.897541 /lava-12066559/bin/lava-test-runner /lava-12066559/0
11116 11:57:37.182025 + export TESTRUN_ID=0_timesync-off
11117 11:57:37.185456 + TESTRUN_ID=0_timesync-off
11118 11:57:37.188587 + cd /lava-12066559/0/tests/0_timesync-off
11119 11:57:37.191614 ++ cat uuid
11120 11:57:37.199120 + UUID=12066559_1.6.2.3.1
11121 11:57:37.199198 + set +x
11122 11:57:37.206127 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12066559_1.6.2.3.1>
11123 11:57:37.206393 Received signal: <STARTRUN> 0_timesync-off 12066559_1.6.2.3.1
11124 11:57:37.206495 Starting test lava.0_timesync-off (12066559_1.6.2.3.1)
11125 11:57:37.206612 Skipping test definition patterns.
11126 11:57:37.209905 + systemctl stop systemd-timesyncd
11127 11:57:37.283157 + set +x
11128 11:57:37.285604 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12066559_1.6.2.3.1>
11129 11:57:37.286358 Received signal: <ENDRUN> 0_timesync-off 12066559_1.6.2.3.1
11130 11:57:37.286763 Ending use of test pattern.
11131 11:57:37.287208 Ending test lava.0_timesync-off (12066559_1.6.2.3.1), duration 0.08
11133 11:57:37.385613 + export TESTRUN_ID=1_kselftest-alsa
11134 11:57:37.388669 + TESTRUN_ID=1_kselftest-alsa
11135 11:57:37.391948 + cd /lava-12066559/0/tests/1_kselftest-alsa
11136 11:57:37.395928 ++ cat uuid
11137 11:57:37.406974 + UUID=12066559_1.6.2.3.5
11138 11:57:37.407401 + set +x
11139 11:57:37.413511 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 12066559_1.6.2.3.5>
11140 11:57:37.414192 Received signal: <STARTRUN> 1_kselftest-alsa 12066559_1.6.2.3.5
11141 11:57:37.414542 Starting test lava.1_kselftest-alsa (12066559_1.6.2.3.5)
11142 11:57:37.414958 Skipping test definition patterns.
11143 11:57:37.417320 + cd ./automated/linux/kselftest/
11144 11:57:37.443508 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11145 11:57:37.509327 INFO: install_deps skipped
11146 11:57:38.037951 --2023-11-23 11:57:37-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11147 11:57:38.051718 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11148 11:57:38.185571 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11149 11:57:38.319884 HTTP request sent, awaiting response... 200 OK
11150 11:57:38.322726 Length: 2962844 (2.8M) [application/octet-stream]
11151 11:57:38.326136 Saving to: 'kselftest.tar.xz'
11152 11:57:38.326690
11153 11:57:38.327114
11154 11:57:38.587605 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11155 11:57:38.855273 kselftest.tar.xz 1%[ ] 44.98K 165KB/s
11156 11:57:39.305117 kselftest.tar.xz 7%[> ] 217.50K 398KB/s
11157 11:57:39.527800 kselftest.tar.xz 28%[====> ] 832.13K 826KB/s
11158 11:57:39.583766 kselftest.tar.xz 80%[===============> ] 2.28M 1.85MB/s
11159 11:57:39.590052 kselftest.tar.xz 100%[===================>] 2.83M 2.19MB/s in 1.3s
11160 11:57:39.590133
11161 11:57:39.848514 2023-11-23 11:57:39 (2.19 MB/s) - 'kselftest.tar.xz' saved [2962844/2962844]
11162 11:57:39.848668
11163 11:57:46.725589 skiplist:
11164 11:57:46.729130 ========================================
11165 11:57:46.732199 ========================================
11166 11:57:46.791772 alsa:mixer-test
11167 11:57:46.817533 ============== Tests to run ===============
11168 11:57:46.820621 alsa:mixer-test
11169 11:57:46.823892 ===========End Tests to run ===============
11170 11:57:46.830410 shardfile-alsa pass
11171 11:57:46.961958 <12>[ 38.793553] kselftest: Running tests in alsa
11172 11:57:46.974364 TAP version 13
11173 11:57:46.991758 1..1
11174 11:57:47.010969 # selftests: alsa: mixer-test
11175 11:57:47.542616 # TAP version 13
11176 11:57:47.542803 # 1..0
11177 11:57:47.549033 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11178 11:57:47.552227 ok 1 selftests: alsa: mixer-test
11179 11:57:48.311873 alsa_mixer-test pass
11180 11:57:48.358187 + ../../utils/send-to-lava.sh ./output/result.txt
11181 11:57:48.455221 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-alsa RESULT=pass>
11182 11:57:48.455951 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-alsa RESULT=pass
11184 11:57:48.525122 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11185 11:57:48.525556 + set +x
11186 11:57:48.526147 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11188 11:57:48.531531 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 12066559_1.6.2.3.5>
11189 11:57:48.532200 Received signal: <ENDRUN> 1_kselftest-alsa 12066559_1.6.2.3.5
11190 11:57:48.532563 Ending use of test pattern.
11191 11:57:48.532877 Ending test lava.1_kselftest-alsa (12066559_1.6.2.3.5), duration 11.12
11193 11:57:48.535297 <LAVA_TEST_RUNNER EXIT>
11194 11:57:48.535963 ok: lava_test_shell seems to have completed
11195 11:57:48.536459 alsa_mixer-test: pass
shardfile-alsa: pass
11196 11:57:48.536872 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11197 11:57:48.537285 end: 3 lava-test-retry (duration 00:00:12) [common]
11198 11:57:48.537739 start: 4 finalize (timeout 00:07:08) [common]
11199 11:57:48.538196 start: 4.1 power-off (timeout 00:00:30) [common]
11200 11:57:48.538964 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11201 11:57:48.654988 >> Command sent successfully.
11202 11:57:48.658951 Returned 0 in 0 seconds
11203 11:57:48.759892 end: 4.1 power-off (duration 00:00:00) [common]
11205 11:57:48.761667 start: 4.2 read-feedback (timeout 00:07:07) [common]
11206 11:57:48.763045 Listened to connection for namespace 'common' for up to 1s
11207 11:57:49.763167 Finalising connection for namespace 'common'
11208 11:57:49.763847 Disconnecting from shell: Finalise
11209 11:57:49.764271 / #
11210 11:57:49.865319 end: 4.2 read-feedback (duration 00:00:01) [common]
11211 11:57:49.866026 end: 4 finalize (duration 00:00:01) [common]
11212 11:57:49.866650 Cleaning after the job
11213 11:57:49.867203 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/ramdisk
11214 11:57:49.882853 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/kernel
11215 11:57:49.914052 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/dtb
11216 11:57:49.914352 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/nfsrootfs
11217 11:57:50.016431 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066559/tftp-deploy-4lvz1rte/modules
11218 11:57:50.023652 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066559
11219 11:57:50.673004 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066559
11220 11:57:50.673183 Job finished correctly