Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 38
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:50:34.637649 lava-dispatcher, installed at version: 2023.10
2 11:50:34.637876 start: 0 validate
3 11:50:34.638011 Start time: 2023-11-23 11:50:34.638003+00:00 (UTC)
4 11:50:34.638135 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:50:34.638267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:50:34.906180 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:50:34.906362 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:50:35.171864 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:50:35.172057 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:51:02.987046 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:51:02.987774 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:51:03.516825 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:51:03.517545 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:51:03.793890 validate duration: 29.16
16 11:51:03.795215 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:51:03.795769 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:51:03.796272 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:51:03.796888 Not decompressing ramdisk as can be used compressed.
20 11:51:03.797461 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:51:03.797826 saving as /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/ramdisk/initrd.cpio.gz
22 11:51:03.798183 total size: 4665395 (4 MB)
23 11:51:11.095554 progress 0 % (0 MB)
24 11:51:11.104294 progress 5 % (0 MB)
25 11:51:11.111489 progress 10 % (0 MB)
26 11:51:11.118599 progress 15 % (0 MB)
27 11:51:11.125379 progress 20 % (0 MB)
28 11:51:11.130014 progress 25 % (1 MB)
29 11:51:11.133584 progress 30 % (1 MB)
30 11:51:11.136649 progress 35 % (1 MB)
31 11:51:11.139466 progress 40 % (1 MB)
32 11:51:11.142158 progress 45 % (2 MB)
33 11:51:11.144512 progress 50 % (2 MB)
34 11:51:11.146582 progress 55 % (2 MB)
35 11:51:11.148624 progress 60 % (2 MB)
36 11:51:11.150537 progress 65 % (2 MB)
37 11:51:11.152317 progress 70 % (3 MB)
38 11:51:11.154152 progress 75 % (3 MB)
39 11:51:11.155816 progress 80 % (3 MB)
40 11:51:11.157610 progress 85 % (3 MB)
41 11:51:11.159192 progress 90 % (4 MB)
42 11:51:11.160701 progress 95 % (4 MB)
43 11:51:11.162136 progress 100 % (4 MB)
44 11:51:11.162309 4 MB downloaded in 7.36 s (0.60 MB/s)
45 11:51:11.162471 end: 1.1.1 http-download (duration 00:00:07) [common]
47 11:51:11.162732 end: 1.1 download-retry (duration 00:00:07) [common]
48 11:51:11.162825 start: 1.2 download-retry (timeout 00:09:53) [common]
49 11:51:11.162938 start: 1.2.1 http-download (timeout 00:09:53) [common]
50 11:51:11.163080 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:51:11.163164 saving as /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/kernel/Image
52 11:51:11.163245 total size: 49107456 (46 MB)
53 11:51:11.163322 No compression specified
54 11:51:11.164541 progress 0 % (0 MB)
55 11:51:11.177677 progress 5 % (2 MB)
56 11:51:11.190514 progress 10 % (4 MB)
57 11:51:11.203386 progress 15 % (7 MB)
58 11:51:11.216261 progress 20 % (9 MB)
59 11:51:11.228846 progress 25 % (11 MB)
60 11:51:11.241613 progress 30 % (14 MB)
61 11:51:11.254434 progress 35 % (16 MB)
62 11:51:11.267582 progress 40 % (18 MB)
63 11:51:11.280745 progress 45 % (21 MB)
64 11:51:11.294032 progress 50 % (23 MB)
65 11:51:11.306964 progress 55 % (25 MB)
66 11:51:11.319992 progress 60 % (28 MB)
67 11:51:11.333059 progress 65 % (30 MB)
68 11:51:11.345978 progress 70 % (32 MB)
69 11:51:11.358895 progress 75 % (35 MB)
70 11:51:11.372061 progress 80 % (37 MB)
71 11:51:11.385185 progress 85 % (39 MB)
72 11:51:11.398485 progress 90 % (42 MB)
73 11:51:11.412040 progress 95 % (44 MB)
74 11:51:11.424935 progress 100 % (46 MB)
75 11:51:11.425190 46 MB downloaded in 0.26 s (178.79 MB/s)
76 11:51:11.425344 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:51:11.425578 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:51:11.425664 start: 1.3 download-retry (timeout 00:09:52) [common]
80 11:51:11.425750 start: 1.3.1 http-download (timeout 00:09:52) [common]
81 11:51:11.425887 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:51:11.425954 saving as /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/dtb/mt8192-asurada-spherion-r0.dtb
83 11:51:11.426013 total size: 47278 (0 MB)
84 11:51:11.426088 No compression specified
85 11:51:11.427311 progress 69 % (0 MB)
86 11:51:11.427588 progress 100 % (0 MB)
87 11:51:11.427744 0 MB downloaded in 0.00 s (26.08 MB/s)
88 11:51:11.427864 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:51:11.428082 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:51:11.428168 start: 1.4 download-retry (timeout 00:09:52) [common]
92 11:51:11.428250 start: 1.4.1 http-download (timeout 00:09:52) [common]
93 11:51:11.428372 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:51:11.428439 saving as /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/nfsrootfs/full.rootfs.tar
95 11:51:11.428498 total size: 200813988 (191 MB)
96 11:51:11.428559 Using unxz to decompress xz
97 11:51:11.432897 progress 0 % (0 MB)
98 11:51:11.980789 progress 5 % (9 MB)
99 11:51:12.528140 progress 10 % (19 MB)
100 11:51:13.146483 progress 15 % (28 MB)
101 11:51:13.536383 progress 20 % (38 MB)
102 11:51:13.878467 progress 25 % (47 MB)
103 11:51:14.501537 progress 30 % (57 MB)
104 11:51:15.074397 progress 35 % (67 MB)
105 11:51:15.686464 progress 40 % (76 MB)
106 11:51:16.275092 progress 45 % (86 MB)
107 11:51:16.901862 progress 50 % (95 MB)
108 11:51:17.554389 progress 55 % (105 MB)
109 11:51:18.237630 progress 60 % (114 MB)
110 11:51:18.377954 progress 65 % (124 MB)
111 11:51:18.542010 progress 70 % (134 MB)
112 11:51:18.655650 progress 75 % (143 MB)
113 11:51:18.753157 progress 80 % (153 MB)
114 11:51:18.846152 progress 85 % (162 MB)
115 11:51:18.964332 progress 90 % (172 MB)
116 11:51:19.314320 progress 95 % (181 MB)
117 11:51:19.965318 progress 100 % (191 MB)
118 11:51:19.970727 191 MB downloaded in 8.54 s (22.42 MB/s)
119 11:51:19.971127 end: 1.4.1 http-download (duration 00:00:09) [common]
121 11:51:19.971532 end: 1.4 download-retry (duration 00:00:09) [common]
122 11:51:19.971661 start: 1.5 download-retry (timeout 00:09:44) [common]
123 11:51:19.971798 start: 1.5.1 http-download (timeout 00:09:44) [common]
124 11:51:19.972010 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:51:19.972120 saving as /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/modules/modules.tar
126 11:51:19.972218 total size: 8621364 (8 MB)
127 11:51:19.972323 Using unxz to decompress xz
128 11:51:20.241965 progress 0 % (0 MB)
129 11:51:20.263318 progress 5 % (0 MB)
130 11:51:20.287070 progress 10 % (0 MB)
131 11:51:20.311174 progress 15 % (1 MB)
132 11:51:20.335051 progress 20 % (1 MB)
133 11:51:20.359567 progress 25 % (2 MB)
134 11:51:20.387246 progress 30 % (2 MB)
135 11:51:20.416105 progress 35 % (2 MB)
136 11:51:20.441428 progress 40 % (3 MB)
137 11:51:20.468953 progress 45 % (3 MB)
138 11:51:20.498765 progress 50 % (4 MB)
139 11:51:20.526711 progress 55 % (4 MB)
140 11:51:20.553527 progress 60 % (4 MB)
141 11:51:20.583880 progress 65 % (5 MB)
142 11:51:20.609992 progress 70 % (5 MB)
143 11:51:20.635321 progress 75 % (6 MB)
144 11:51:20.664266 progress 80 % (6 MB)
145 11:51:20.692506 progress 85 % (7 MB)
146 11:51:20.719799 progress 90 % (7 MB)
147 11:51:20.751997 progress 95 % (7 MB)
148 11:51:20.783613 progress 100 % (8 MB)
149 11:51:20.788721 8 MB downloaded in 0.82 s (10.07 MB/s)
150 11:51:20.789090 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:51:20.789500 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:51:20.789636 start: 1.6 prepare-tftp-overlay (timeout 00:09:43) [common]
154 11:51:20.789772 start: 1.6.1 extract-nfsrootfs (timeout 00:09:43) [common]
155 11:51:24.435462 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj
156 11:51:24.435679 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:51:24.435788 start: 1.6.2 lava-overlay (timeout 00:09:39) [common]
158 11:51:24.435956 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t
159 11:51:24.436091 makedir: /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin
160 11:51:24.436193 makedir: /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/tests
161 11:51:24.436293 makedir: /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/results
162 11:51:24.436395 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-add-keys
163 11:51:24.436547 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-add-sources
164 11:51:24.436680 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-background-process-start
165 11:51:24.436810 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-background-process-stop
166 11:51:24.436938 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-common-functions
167 11:51:24.437063 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-echo-ipv4
168 11:51:24.437189 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-install-packages
169 11:51:24.437313 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-installed-packages
170 11:51:24.437437 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-os-build
171 11:51:24.437563 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-probe-channel
172 11:51:24.437687 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-probe-ip
173 11:51:24.437812 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-target-ip
174 11:51:24.437936 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-target-mac
175 11:51:24.438063 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-target-storage
176 11:51:24.438189 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-case
177 11:51:24.438317 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-event
178 11:51:24.438440 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-feedback
179 11:51:24.438566 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-raise
180 11:51:24.438690 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-reference
181 11:51:24.438814 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-runner
182 11:51:24.438958 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-set
183 11:51:24.439086 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-test-shell
184 11:51:24.439213 Updating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-add-keys (debian)
185 11:51:24.439370 Updating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-add-sources (debian)
186 11:51:24.439514 Updating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-install-packages (debian)
187 11:51:24.439654 Updating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-installed-packages (debian)
188 11:51:24.439792 Updating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/bin/lava-os-build (debian)
189 11:51:24.439914 Creating /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/environment
190 11:51:24.440011 LAVA metadata
191 11:51:24.440082 - LAVA_JOB_ID=12066512
192 11:51:24.440145 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:51:24.440270 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:39) [common]
194 11:51:24.440336 skipped lava-vland-overlay
195 11:51:24.440410 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:51:24.440490 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:39) [common]
197 11:51:24.440549 skipped lava-multinode-overlay
198 11:51:24.440634 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:51:24.440713 start: 1.6.2.3 test-definition (timeout 00:09:39) [common]
200 11:51:24.440787 Loading test definitions
201 11:51:24.440877 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:39) [common]
202 11:51:24.440947 Using /lava-12066512 at stage 0
203 11:51:24.441243 uuid=12066512_1.6.2.3.1 testdef=None
204 11:51:24.441332 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:51:24.441416 start: 1.6.2.3.2 test-overlay (timeout 00:09:39) [common]
206 11:51:24.441883 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:51:24.442099 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:39) [common]
209 11:51:24.442686 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:51:24.443040 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:39) [common]
212 11:51:24.443596 runner path: /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/0/tests/0_timesync-off test_uuid 12066512_1.6.2.3.1
213 11:51:24.443753 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:51:24.443977 start: 1.6.2.3.5 git-repo-action (timeout 00:09:39) [common]
216 11:51:24.444049 Using /lava-12066512 at stage 0
217 11:51:24.444149 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:51:24.444235 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/0/tests/1_kselftest-arm64'
219 11:51:35.012623 Running '/usr/bin/git checkout kernelci.org
220 11:51:35.024059 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:51:35.024813 uuid=12066512_1.6.2.3.5 testdef=None
222 11:51:35.024976 end: 1.6.2.3.5 git-repo-action (duration 00:00:11) [common]
224 11:51:35.025232 start: 1.6.2.3.6 test-overlay (timeout 00:09:29) [common]
225 11:51:35.025979 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:51:35.026206 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:29) [common]
228 11:51:35.027226 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:51:35.027456 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:29) [common]
231 11:51:35.028379 runner path: /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/0/tests/1_kselftest-arm64 test_uuid 12066512_1.6.2.3.5
232 11:51:35.028470 BOARD='mt8192-asurada-spherion-r0'
233 11:51:35.028535 BRANCH='cip-gitlab'
234 11:51:35.028594 SKIPFILE='/dev/null'
235 11:51:35.028651 SKIP_INSTALL='True'
236 11:51:35.028705 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:51:35.028762 TST_CASENAME=''
238 11:51:35.028816 TST_CMDFILES='arm64'
239 11:51:35.028957 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:51:35.029159 Creating lava-test-runner.conf files
242 11:51:35.029222 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066512/lava-overlay-rcp8422t/lava-12066512/0 for stage 0
243 11:51:35.029315 - 0_timesync-off
244 11:51:35.029379 - 1_kselftest-arm64
245 11:51:35.029474 end: 1.6.2.3 test-definition (duration 00:00:11) [common]
246 11:51:35.029563 start: 1.6.2.4 compress-overlay (timeout 00:09:29) [common]
247 11:51:42.591363 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:51:42.591552 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:21) [common]
249 11:51:42.591644 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:51:42.591746 end: 1.6.2 lava-overlay (duration 00:00:18) [common]
251 11:51:42.591835 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:21) [common]
252 11:51:42.716459 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:51:42.716858 start: 1.6.4 extract-modules (timeout 00:09:21) [common]
254 11:51:42.716980 extracting modules file /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj
255 11:51:42.942737 extracting modules file /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066512/extract-overlay-ramdisk-2895chws/ramdisk
256 11:51:43.172065 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:51:43.172221 start: 1.6.5 apply-overlay-tftp (timeout 00:09:21) [common]
258 11:51:43.172315 [common] Applying overlay to NFS
259 11:51:43.172386 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066512/compress-overlay-u99oa26y/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj
260 11:51:44.100113 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:51:44.100273 start: 1.6.6 configure-preseed-file (timeout 00:09:20) [common]
262 11:51:44.100368 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:51:44.100454 start: 1.6.7 compress-ramdisk (timeout 00:09:20) [common]
264 11:51:44.100537 Building ramdisk /var/lib/lava/dispatcher/tmp/12066512/extract-overlay-ramdisk-2895chws/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066512/extract-overlay-ramdisk-2895chws/ramdisk
265 11:51:44.398851 >> 119398 blocks
266 11:51:46.357482 rename /var/lib/lava/dispatcher/tmp/12066512/extract-overlay-ramdisk-2895chws/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/ramdisk/ramdisk.cpio.gz
267 11:51:46.357953 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:51:46.358085 start: 1.6.8 prepare-kernel (timeout 00:09:17) [common]
269 11:51:46.358204 start: 1.6.8.1 prepare-fit (timeout 00:09:17) [common]
270 11:51:46.358312 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/kernel/Image'
271 11:52:00.050930 Returned 0 in 13 seconds
272 11:52:00.151557 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/kernel/image.itb
273 11:52:00.503078 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:52:00.503500 output: Created: Thu Nov 23 11:52:00 2023
275 11:52:00.503614 output: Image 0 (kernel-1)
276 11:52:00.503715 output: Description:
277 11:52:00.503808 output: Created: Thu Nov 23 11:52:00 2023
278 11:52:00.503900 output: Type: Kernel Image
279 11:52:00.503989 output: Compression: lzma compressed
280 11:52:00.504076 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
281 11:52:00.504168 output: Architecture: AArch64
282 11:52:00.504256 output: OS: Linux
283 11:52:00.504342 output: Load Address: 0x00000000
284 11:52:00.504431 output: Entry Point: 0x00000000
285 11:52:00.504515 output: Hash algo: crc32
286 11:52:00.504600 output: Hash value: e6d7c86f
287 11:52:00.504690 output: Image 1 (fdt-1)
288 11:52:00.504773 output: Description: mt8192-asurada-spherion-r0
289 11:52:00.504856 output: Created: Thu Nov 23 11:52:00 2023
290 11:52:00.504941 output: Type: Flat Device Tree
291 11:52:00.505023 output: Compression: uncompressed
292 11:52:00.505105 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:52:00.505191 output: Architecture: AArch64
294 11:52:00.505272 output: Hash algo: crc32
295 11:52:00.505354 output: Hash value: cc4352de
296 11:52:00.505438 output: Image 2 (ramdisk-1)
297 11:52:00.505521 output: Description: unavailable
298 11:52:00.505602 output: Created: Thu Nov 23 11:52:00 2023
299 11:52:00.505687 output: Type: RAMDisk Image
300 11:52:00.505769 output: Compression: Unknown Compression
301 11:52:00.505850 output: Data Size: 17793302 Bytes = 17376.27 KiB = 16.97 MiB
302 11:52:00.505936 output: Architecture: AArch64
303 11:52:00.506018 output: OS: Linux
304 11:52:00.506099 output: Load Address: unavailable
305 11:52:00.506187 output: Entry Point: unavailable
306 11:52:00.506270 output: Hash algo: crc32
307 11:52:00.506351 output: Hash value: 2ea497e5
308 11:52:00.506436 output: Default Configuration: 'conf-1'
309 11:52:00.506518 output: Configuration 0 (conf-1)
310 11:52:00.506600 output: Description: mt8192-asurada-spherion-r0
311 11:52:00.506684 output: Kernel: kernel-1
312 11:52:00.506766 output: Init Ramdisk: ramdisk-1
313 11:52:00.506848 output: FDT: fdt-1
314 11:52:00.506943 output: Loadables: kernel-1
315 11:52:00.507003 output:
316 11:52:00.507213 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:52:00.507319 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:52:00.507427 end: 1.6 prepare-tftp-overlay (duration 00:00:40) [common]
319 11:52:00.507532 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:03) [common]
320 11:52:00.507616 No LXC device requested
321 11:52:00.507698 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:52:00.507787 start: 1.8 deploy-device-env (timeout 00:09:03) [common]
323 11:52:00.507865 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:52:00.507932 Checking files for TFTP limit of 4294967296 bytes.
325 11:52:00.508468 end: 1 tftp-deploy (duration 00:00:57) [common]
326 11:52:00.508580 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:52:00.508674 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:52:00.508801 substitutions:
329 11:52:00.508870 - {DTB}: 12066512/tftp-deploy-1a1n6lk2/dtb/mt8192-asurada-spherion-r0.dtb
330 11:52:00.508933 - {INITRD}: 12066512/tftp-deploy-1a1n6lk2/ramdisk/ramdisk.cpio.gz
331 11:52:00.509000 - {KERNEL}: 12066512/tftp-deploy-1a1n6lk2/kernel/Image
332 11:52:00.509088 - {LAVA_MAC}: None
333 11:52:00.509173 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj
334 11:52:00.509262 - {NFS_SERVER_IP}: 192.168.201.1
335 11:52:00.509346 - {PRESEED_CONFIG}: None
336 11:52:00.509430 - {PRESEED_LOCAL}: None
337 11:52:00.509515 - {RAMDISK}: 12066512/tftp-deploy-1a1n6lk2/ramdisk/ramdisk.cpio.gz
338 11:52:00.509600 - {ROOT_PART}: None
339 11:52:00.509684 - {ROOT}: None
340 11:52:00.509769 - {SERVER_IP}: 192.168.201.1
341 11:52:00.509853 - {TEE}: None
342 11:52:00.509936 Parsed boot commands:
343 11:52:00.510020 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:52:00.510256 Parsed boot commands: tftpboot 192.168.201.1 12066512/tftp-deploy-1a1n6lk2/kernel/image.itb 12066512/tftp-deploy-1a1n6lk2/kernel/cmdline
345 11:52:00.510356 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:52:00.510437 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:52:00.510530 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:52:00.510647 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:52:00.510747 Not connected, no need to disconnect.
350 11:52:00.510854 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:52:00.510976 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:52:00.511071 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-3'
353 11:52:00.515394 Setting prompt string to ['lava-test: # ']
354 11:52:00.515809 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:52:00.515933 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:52:00.516037 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:52:00.516136 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:52:00.516339 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
359 11:52:05.649698 >> Command sent successfully.
360 11:52:05.652731 Returned 0 in 5 seconds
361 11:52:05.753180 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:52:05.753543 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:52:05.753658 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:52:05.753748 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:52:05.753815 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:52:05.753883 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:52:05.754171 [Enter `^Ec?' for help]
369 11:52:05.929813
370 11:52:05.929967
371 11:52:05.930055 F0: 102B 0000
372 11:52:05.930135
373 11:52:05.930198 F3: 1001 0000 [0200]
374 11:52:05.930259
375 11:52:05.933124 F3: 1001 0000
376 11:52:05.933225
377 11:52:05.933295 F7: 102D 0000
378 11:52:05.933361
379 11:52:05.933424 F1: 0000 0000
380 11:52:05.937147
381 11:52:05.937255 V0: 0000 0000 [0001]
382 11:52:05.937358
383 11:52:05.937460 00: 0007 8000
384 11:52:05.937530
385 11:52:05.940578 01: 0000 0000
386 11:52:05.940687
387 11:52:05.940780 BP: 0C00 0209 [0000]
388 11:52:05.940870
389 11:52:05.944339 G0: 1182 0000
390 11:52:05.944445
391 11:52:05.944541 EC: 0000 0021 [4000]
392 11:52:05.944631
393 11:52:05.947908 S7: 0000 0000 [0000]
394 11:52:05.948013
395 11:52:05.948106 CC: 0000 0000 [0001]
396 11:52:05.948199
397 11:52:05.951558 T0: 0000 0040 [010F]
398 11:52:05.951638
399 11:52:05.951702 Jump to BL
400 11:52:05.951768
401 11:52:05.976138
402 11:52:05.976288
403 11:52:05.976358
404 11:52:05.983988 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:52:05.987909 ARM64: Exception handlers installed.
406 11:52:05.991547 ARM64: Testing exception
407 11:52:05.995243 ARM64: Done test exception
408 11:52:05.998675 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:52:06.010732 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:52:06.017118 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:52:06.027331 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:52:06.034212 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:52:06.040617 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:52:06.052592 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:52:06.059799 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:52:06.078890 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:52:06.082155 WDT: Last reset was cold boot
418 11:52:06.085638 SPI1(PAD0) initialized at 2873684 Hz
419 11:52:06.089178 SPI5(PAD0) initialized at 992727 Hz
420 11:52:06.092893 VBOOT: Loading verstage.
421 11:52:06.099330 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:52:06.102655 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:52:06.105656 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:52:06.109141 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:52:06.116669 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:52:06.123163 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:52:06.133987 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 11:52:06.134091
429 11:52:06.134175
430 11:52:06.144051 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:52:06.147665 ARM64: Exception handlers installed.
432 11:52:06.151115 ARM64: Testing exception
433 11:52:06.151208 ARM64: Done test exception
434 11:52:06.157650 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:52:06.160947 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:52:06.176313 Probing TPM: . done!
437 11:52:06.176439 TPM ready after 0 ms
438 11:52:06.180774 Connected to device vid:did:rid of 1ae0:0028:00
439 11:52:06.190762 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 11:52:06.245915 Initialized TPM device CR50 revision 0
441 11:52:06.258071 tlcl_send_startup: Startup return code is 0
442 11:52:06.258194 TPM: setup succeeded
443 11:52:06.269637 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:52:06.278742 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:52:06.289951 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:52:06.299283 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:52:06.302762 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:52:06.310465 in-header: 03 07 00 00 08 00 00 00
449 11:52:06.314509 in-data: aa e4 47 04 13 02 00 00
450 11:52:06.318088 Chrome EC: UHEPI supported
451 11:52:06.325265 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:52:06.329331 in-header: 03 ad 00 00 08 00 00 00
453 11:52:06.332607 in-data: 00 20 20 08 00 00 00 00
454 11:52:06.332703 Phase 1
455 11:52:06.336725 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:52:06.340244 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:52:06.347767 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:52:06.351476 Recovery requested (1009000e)
459 11:52:06.359473 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:52:06.364471 tlcl_extend: response is 0
461 11:52:06.374442 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:52:06.379853 tlcl_extend: response is 0
463 11:52:06.386811 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:52:06.406477 read SPI 0x210d4 0x2173b: 15149 us, 9044 KB/s, 72.352 Mbps
465 11:52:06.413455 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:52:06.413552
467 11:52:06.413621
468 11:52:06.424066 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:52:06.427556 ARM64: Exception handlers installed.
470 11:52:06.427678 ARM64: Testing exception
471 11:52:06.430940 ARM64: Done test exception
472 11:52:06.452112 pmic_efuse_setting: Set efuses in 11 msecs
473 11:52:06.455563 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:52:06.462353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:52:06.466749 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:52:06.469056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:52:06.476810 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:52:06.480043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:52:06.487600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:52:06.491043 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:52:06.494690 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:52:06.498252 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:52:06.506097 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:52:06.510412 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:52:06.513682 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:52:06.517152 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:52:06.524981 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:52:06.528686 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:52:06.535831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:52:06.543137 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:52:06.547337 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:52:06.554450 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:52:06.558504 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:52:06.561961 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:52:06.569642 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:52:06.576625 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:52:06.580624 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:52:06.583616 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:52:06.591209 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:52:06.595172 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:52:06.602216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:52:06.606114 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:52:06.609623 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:52:06.617084 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:52:06.620366 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:52:06.624610 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:52:06.631807 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:52:06.635415 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:52:06.642478 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:52:06.646821 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:52:06.650752 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:52:06.654428 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:52:06.661350 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:52:06.664971 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:52:06.668703 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:52:06.672264 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:52:06.676515 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:52:06.680217 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:52:06.687513 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:52:06.691262 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:52:06.694778 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:52:06.698179 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:52:06.702165 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:52:06.705779 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:52:06.716878 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:52:06.723622 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:52:06.728209 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:52:06.735419 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:52:06.745785 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:52:06.749251 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:52:06.753451 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:52:06.756092 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:52:06.764906 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x33
534 11:52:06.768777 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:52:06.777039 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 11:52:06.780374 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:52:06.789633 [RTC]rtc_get_frequency_meter,154: input=15, output=790
538 11:52:06.799421 [RTC]rtc_get_frequency_meter,154: input=23, output=978
539 11:52:06.808662 [RTC]rtc_get_frequency_meter,154: input=19, output=885
540 11:52:06.817680 [RTC]rtc_get_frequency_meter,154: input=17, output=837
541 11:52:06.827902 [RTC]rtc_get_frequency_meter,154: input=16, output=814
542 11:52:06.837343 [RTC]rtc_get_frequency_meter,154: input=15, output=790
543 11:52:06.846530 [RTC]rtc_get_frequency_meter,154: input=16, output=813
544 11:52:06.849909 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
545 11:52:06.857629 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
546 11:52:06.861937 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:52:06.865556 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
548 11:52:06.869308 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:52:06.872867 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
550 11:52:06.876818 ADC[4]: Raw value=901328 ID=7
551 11:52:06.876911 ADC[3]: Raw value=213336 ID=1
552 11:52:06.880070 RAM Code: 0x71
553 11:52:06.883901 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:52:06.887762 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:52:06.898603 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:52:06.903249 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:52:06.906094 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:52:06.909890 in-header: 03 07 00 00 08 00 00 00
559 11:52:06.914347 in-data: aa e4 47 04 13 02 00 00
560 11:52:06.917687 Chrome EC: UHEPI supported
561 11:52:06.925254 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:52:06.928762 in-header: 03 ed 00 00 08 00 00 00
563 11:52:06.928851 in-data: 80 20 60 08 00 00 00 00
564 11:52:06.932790 MRC: failed to locate region type 0.
565 11:52:06.940270 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:52:06.943900 DRAM-K: Running full calibration
567 11:52:06.951158 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:52:06.951262 header.status = 0x0
569 11:52:06.954528 header.version = 0x6 (expected: 0x6)
570 11:52:06.958073 header.size = 0xd00 (expected: 0xd00)
571 11:52:06.958193 header.flags = 0x0
572 11:52:06.964979 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:52:06.983822 read SPI 0x72590 0x1c583: 12505 us, 9284 KB/s, 74.272 Mbps
574 11:52:06.990392 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:52:06.994659 dram_init: ddr_geometry: 2
576 11:52:06.994750 [EMI] MDL number = 2
577 11:52:06.998038 [EMI] Get MDL freq = 0
578 11:52:06.998157 dram_init: ddr_type: 0
579 11:52:07.001784 is_discrete_lpddr4: 1
580 11:52:07.005128 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:52:07.005236
582 11:52:07.005325
583 11:52:07.008843 [Bian_co] ETT version 0.0.0.1
584 11:52:07.012256 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:52:07.012342
586 11:52:07.015365 dramc_set_vcore_voltage set vcore to 650000
587 11:52:07.018696 Read voltage for 800, 4
588 11:52:07.018809 Vio18 = 0
589 11:52:07.018914 Vcore = 650000
590 11:52:07.022469 Vdram = 0
591 11:52:07.022551 Vddq = 0
592 11:52:07.022653 Vmddr = 0
593 11:52:07.026147 dram_init: config_dvfs: 1
594 11:52:07.028563 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:52:07.035747 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:52:07.038673 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
597 11:52:07.042484 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
598 11:52:07.049409 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
599 11:52:07.052601 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
600 11:52:07.052714 MEM_TYPE=3, freq_sel=18
601 11:52:07.055599 sv_algorithm_assistance_LP4_1600
602 11:52:07.059150 ============ PULL DRAM RESETB DOWN ============
603 11:52:07.065703 ========== PULL DRAM RESETB DOWN end =========
604 11:52:07.069137 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:52:07.072684 ===================================
606 11:52:07.075588 LPDDR4 DRAM CONFIGURATION
607 11:52:07.079116 ===================================
608 11:52:07.079202 EX_ROW_EN[0] = 0x0
609 11:52:07.083179 EX_ROW_EN[1] = 0x0
610 11:52:07.083310 LP4Y_EN = 0x0
611 11:52:07.086152 WORK_FSP = 0x0
612 11:52:07.086238 WL = 0x2
613 11:52:07.089582 RL = 0x2
614 11:52:07.089666 BL = 0x2
615 11:52:07.093235 RPST = 0x0
616 11:52:07.093357 RD_PRE = 0x0
617 11:52:07.095913 WR_PRE = 0x1
618 11:52:07.096000 WR_PST = 0x0
619 11:52:07.099308 DBI_WR = 0x0
620 11:52:07.102935 DBI_RD = 0x0
621 11:52:07.103081 OTF = 0x1
622 11:52:07.106375 ===================================
623 11:52:07.109272 ===================================
624 11:52:07.109351 ANA top config
625 11:52:07.112635 ===================================
626 11:52:07.116156 DLL_ASYNC_EN = 0
627 11:52:07.119676 ALL_SLAVE_EN = 1
628 11:52:07.123090 NEW_RANK_MODE = 1
629 11:52:07.123170 DLL_IDLE_MODE = 1
630 11:52:07.126541 LP45_APHY_COMB_EN = 1
631 11:52:07.129968 TX_ODT_DIS = 1
632 11:52:07.133217 NEW_8X_MODE = 1
633 11:52:07.136657 ===================================
634 11:52:07.139871 ===================================
635 11:52:07.143071 data_rate = 1600
636 11:52:07.143168 CKR = 1
637 11:52:07.146970 DQ_P2S_RATIO = 8
638 11:52:07.149774 ===================================
639 11:52:07.153556 CA_P2S_RATIO = 8
640 11:52:07.156417 DQ_CA_OPEN = 0
641 11:52:07.160318 DQ_SEMI_OPEN = 0
642 11:52:07.160408 CA_SEMI_OPEN = 0
643 11:52:07.163330 CA_FULL_RATE = 0
644 11:52:07.166894 DQ_CKDIV4_EN = 1
645 11:52:07.169820 CA_CKDIV4_EN = 1
646 11:52:07.173108 CA_PREDIV_EN = 0
647 11:52:07.176705 PH8_DLY = 0
648 11:52:07.176808 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:52:07.180107 DQ_AAMCK_DIV = 4
650 11:52:07.183462 CA_AAMCK_DIV = 4
651 11:52:07.186934 CA_ADMCK_DIV = 4
652 11:52:07.190314 DQ_TRACK_CA_EN = 0
653 11:52:07.193726 CA_PICK = 800
654 11:52:07.193813 CA_MCKIO = 800
655 11:52:07.197517 MCKIO_SEMI = 0
656 11:52:07.200051 PLL_FREQ = 3068
657 11:52:07.205077 DQ_UI_PI_RATIO = 32
658 11:52:07.207900 CA_UI_PI_RATIO = 0
659 11:52:07.211493 ===================================
660 11:52:07.211583 ===================================
661 11:52:07.215775 memory_type:LPDDR4
662 11:52:07.218695 GP_NUM : 10
663 11:52:07.218815 SRAM_EN : 1
664 11:52:07.222700 MD32_EN : 0
665 11:52:07.226775 ===================================
666 11:52:07.226930 [ANA_INIT] >>>>>>>>>>>>>>
667 11:52:07.230254 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:52:07.234300 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:52:07.238174 ===================================
670 11:52:07.238281 data_rate = 1600,PCW = 0X7600
671 11:52:07.241066 ===================================
672 11:52:07.244261 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:52:07.251329 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:52:07.258158 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:52:07.261773 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:52:07.265098 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:52:07.268422 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:52:07.271662 [ANA_INIT] flow start
679 11:52:07.271789 [ANA_INIT] PLL >>>>>>>>
680 11:52:07.274981 [ANA_INIT] PLL <<<<<<<<
681 11:52:07.278666 [ANA_INIT] MIDPI >>>>>>>>
682 11:52:07.282162 [ANA_INIT] MIDPI <<<<<<<<
683 11:52:07.282246 [ANA_INIT] DLL >>>>>>>>
684 11:52:07.284850 [ANA_INIT] flow end
685 11:52:07.288507 ============ LP4 DIFF to SE enter ============
686 11:52:07.291436 ============ LP4 DIFF to SE exit ============
687 11:52:07.294802 [ANA_INIT] <<<<<<<<<<<<<
688 11:52:07.298187 [Flow] Enable top DCM control >>>>>
689 11:52:07.301957 [Flow] Enable top DCM control <<<<<
690 11:52:07.305230 Enable DLL master slave shuffle
691 11:52:07.308698 ==============================================================
692 11:52:07.311855 Gating Mode config
693 11:52:07.318472 ==============================================================
694 11:52:07.318568 Config description:
695 11:52:07.328569 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:52:07.335275 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:52:07.338782 SELPH_MODE 0: By rank 1: By Phase
698 11:52:07.345403 ==============================================================
699 11:52:07.348510 GAT_TRACK_EN = 1
700 11:52:07.352058 RX_GATING_MODE = 2
701 11:52:07.355564 RX_GATING_TRACK_MODE = 2
702 11:52:07.358519 SELPH_MODE = 1
703 11:52:07.362113 PICG_EARLY_EN = 1
704 11:52:07.362210 VALID_LAT_VALUE = 1
705 11:52:07.368994 ==============================================================
706 11:52:07.372262 Enter into Gating configuration >>>>
707 11:52:07.375654 Exit from Gating configuration <<<<
708 11:52:07.379096 Enter into DVFS_PRE_config >>>>>
709 11:52:07.389463 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:52:07.392577 Exit from DVFS_PRE_config <<<<<
711 11:52:07.396201 Enter into PICG configuration >>>>
712 11:52:07.399324 Exit from PICG configuration <<<<
713 11:52:07.402660 [RX_INPUT] configuration >>>>>
714 11:52:07.405683 [RX_INPUT] configuration <<<<<
715 11:52:07.409058 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:52:07.415999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:52:07.423484 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:52:07.426672 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:52:07.433458 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:52:07.439953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:52:07.443308 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:52:07.446769 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:52:07.453767 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:52:07.457425 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:52:07.460572 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:52:07.463775 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:52:07.467322 ===================================
728 11:52:07.470332 LPDDR4 DRAM CONFIGURATION
729 11:52:07.474008 ===================================
730 11:52:07.477218 EX_ROW_EN[0] = 0x0
731 11:52:07.477336 EX_ROW_EN[1] = 0x0
732 11:52:07.480318 LP4Y_EN = 0x0
733 11:52:07.480409 WORK_FSP = 0x0
734 11:52:07.483828 WL = 0x2
735 11:52:07.483906 RL = 0x2
736 11:52:07.487228 BL = 0x2
737 11:52:07.487308 RPST = 0x0
738 11:52:07.490488 RD_PRE = 0x0
739 11:52:07.490566 WR_PRE = 0x1
740 11:52:07.493767 WR_PST = 0x0
741 11:52:07.493840 DBI_WR = 0x0
742 11:52:07.497655 DBI_RD = 0x0
743 11:52:07.497735 OTF = 0x1
744 11:52:07.500947 ===================================
745 11:52:07.507642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:52:07.510549 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:52:07.513901 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:52:07.517130 ===================================
749 11:52:07.520812 LPDDR4 DRAM CONFIGURATION
750 11:52:07.524232 ===================================
751 11:52:07.524311 EX_ROW_EN[0] = 0x10
752 11:52:07.527786 EX_ROW_EN[1] = 0x0
753 11:52:07.531047 LP4Y_EN = 0x0
754 11:52:07.531126 WORK_FSP = 0x0
755 11:52:07.534388 WL = 0x2
756 11:52:07.534500 RL = 0x2
757 11:52:07.537629 BL = 0x2
758 11:52:07.537739 RPST = 0x0
759 11:52:07.541076 RD_PRE = 0x0
760 11:52:07.541185 WR_PRE = 0x1
761 11:52:07.543997 WR_PST = 0x0
762 11:52:07.544107 DBI_WR = 0x0
763 11:52:07.547780 DBI_RD = 0x0
764 11:52:07.547859 OTF = 0x1
765 11:52:07.550620 ===================================
766 11:52:07.557468 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:52:07.561616 nWR fixed to 40
768 11:52:07.565110 [ModeRegInit_LP4] CH0 RK0
769 11:52:07.565195 [ModeRegInit_LP4] CH0 RK1
770 11:52:07.568494 [ModeRegInit_LP4] CH1 RK0
771 11:52:07.571846 [ModeRegInit_LP4] CH1 RK1
772 11:52:07.571925 match AC timing 13
773 11:52:07.578305 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:52:07.581531 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:52:07.585268 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:52:07.591682 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:52:07.595197 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:52:07.595282 [EMI DOE] emi_dcm 0
779 11:52:07.601740 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:52:07.601825 ==
781 11:52:07.605265 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:52:07.608399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:52:07.608481 ==
784 11:52:07.615172 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:52:07.618253 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:52:07.628932 [CA 0] Center 37 (7~68) winsize 62
787 11:52:07.632272 [CA 1] Center 37 (7~68) winsize 62
788 11:52:07.635937 [CA 2] Center 35 (5~66) winsize 62
789 11:52:07.639462 [CA 3] Center 34 (4~65) winsize 62
790 11:52:07.642513 [CA 4] Center 34 (3~65) winsize 63
791 11:52:07.645794 [CA 5] Center 33 (3~64) winsize 62
792 11:52:07.645882
793 11:52:07.649504 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:52:07.649588
795 11:52:07.652662 [CATrainingPosCal] consider 1 rank data
796 11:52:07.656174 u2DelayCellTimex100 = 270/100 ps
797 11:52:07.659087 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:52:07.662839 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 11:52:07.666035 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
800 11:52:07.672755 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:52:07.676576 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
802 11:52:07.679349 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:52:07.679425
804 11:52:07.682871 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:52:07.682947
806 11:52:07.686266 [CBTSetCACLKResult] CA Dly = 33
807 11:52:07.686336 CS Dly: 5 (0~36)
808 11:52:07.686399 ==
809 11:52:07.689590 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:52:07.696184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:52:07.696263 ==
812 11:52:07.699665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:52:07.705908 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:52:07.715130 [CA 0] Center 37 (7~68) winsize 62
815 11:52:07.719029 [CA 1] Center 37 (7~68) winsize 62
816 11:52:07.722033 [CA 2] Center 35 (5~66) winsize 62
817 11:52:07.725326 [CA 3] Center 35 (4~66) winsize 63
818 11:52:07.728493 [CA 4] Center 34 (4~65) winsize 62
819 11:52:07.731875 [CA 5] Center 33 (3~64) winsize 62
820 11:52:07.732004
821 11:52:07.735469 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:52:07.735562
823 11:52:07.739022 [CATrainingPosCal] consider 2 rank data
824 11:52:07.742284 u2DelayCellTimex100 = 270/100 ps
825 11:52:07.745294 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:52:07.748911 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:52:07.755336 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
828 11:52:07.759153 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:52:07.762489 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
830 11:52:07.765912 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:52:07.766009
832 11:52:07.769135 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:52:07.769213
834 11:52:07.772493 [CBTSetCACLKResult] CA Dly = 33
835 11:52:07.772571 CS Dly: 6 (0~38)
836 11:52:07.772654
837 11:52:07.775921 ----->DramcWriteLeveling(PI) begin...
838 11:52:07.776007 ==
839 11:52:07.779317 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:52:07.785711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:52:07.785803 ==
842 11:52:07.789755 Write leveling (Byte 0): 30 => 30
843 11:52:07.789840 Write leveling (Byte 1): 29 => 29
844 11:52:07.793223 DramcWriteLeveling(PI) end<-----
845 11:52:07.793318
846 11:52:07.793404 ==
847 11:52:07.797195 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:52:07.801300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:52:07.801388 ==
850 11:52:07.804796 [Gating] SW mode calibration
851 11:52:07.811638 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:52:07.818481 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:52:07.821862 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:52:07.824861 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:52:07.828423 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:52:07.835264 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 11:52:07.838818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:52:07.841529 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:52:07.848747 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:52:07.851844 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:52:07.855393 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:52:07.861690 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:52:07.865246 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:52:07.868970 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:52:07.875389 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:52:07.878343 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:52:07.882088 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:52:07.888745 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:52:07.892280 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:52:07.895150 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:52:07.898642 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
872 11:52:07.905561 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 11:52:07.908741 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:52:07.912343 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:52:07.918999 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:52:07.922078 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:52:07.925770 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:52:07.932248 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:52:07.936162 0 9 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
880 11:52:07.939074 0 9 12 | B1->B0 | 2929 3333 | 0 1 | (0 0) (1 1)
881 11:52:07.945874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:52:07.949254 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:52:07.952701 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:52:07.956169 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:52:07.963014 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:52:07.966146 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 11:52:07.969637 0 10 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 1)
888 11:52:07.976105 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
889 11:52:07.979490 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:52:07.983088 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:52:07.989877 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:52:07.993400 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:52:07.996625 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:52:07.999802 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 11:52:08.006260 0 11 8 | B1->B0 | 2424 3232 | 0 1 | (0 0) (0 0)
896 11:52:08.009609 0 11 12 | B1->B0 | 3838 3f3f | 0 0 | (0 0) (0 0)
897 11:52:08.013106 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:52:08.019649 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:52:08.023294 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:52:08.026250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:52:08.033195 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:52:08.036335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:52:08.040403 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
904 11:52:08.046931 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 11:52:08.050403 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:52:08.053354 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:52:08.056911 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:52:08.063798 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:52:08.067210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:52:08.070059 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:52:08.077305 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:52:08.080694 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:52:08.083744 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:52:08.090692 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:52:08.093722 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:52:08.097607 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:52:08.104227 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:52:08.107256 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:52:08.110686 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 11:52:08.114001 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 11:52:08.117453 Total UI for P1: 0, mck2ui 16
922 11:52:08.120941 best dqsien dly found for B0: ( 0, 14, 8)
923 11:52:08.127669 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:52:08.127805 Total UI for P1: 0, mck2ui 16
925 11:52:08.134176 best dqsien dly found for B1: ( 0, 14, 12)
926 11:52:08.137964 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 11:52:08.141184 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 11:52:08.141294
929 11:52:08.144899 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:52:08.147603 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 11:52:08.151069 [Gating] SW calibration Done
932 11:52:08.151174 ==
933 11:52:08.154796 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:52:08.157884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:52:08.157998 ==
936 11:52:08.161188 RX Vref Scan: 0
937 11:52:08.161298
938 11:52:08.161390 RX Vref 0 -> 0, step: 1
939 11:52:08.161527
940 11:52:08.164862 RX Delay -130 -> 252, step: 16
941 11:52:08.167872 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 11:52:08.174842 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 11:52:08.178204 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 11:52:08.181110 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 11:52:08.184625 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 11:52:08.188139 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
947 11:52:08.191558 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
948 11:52:08.198398 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
949 11:52:08.201440 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 11:52:08.205215 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
951 11:52:08.208421 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 11:52:08.211786 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 11:52:08.218467 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 11:52:08.221773 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
955 11:52:08.225389 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 11:52:08.228639 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 11:52:08.228738 ==
958 11:52:08.232034 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:52:08.235419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:52:08.238341 ==
961 11:52:08.238449 DQS Delay:
962 11:52:08.238540 DQS0 = 0, DQS1 = 0
963 11:52:08.241965 DQM Delay:
964 11:52:08.242075 DQM0 = 84, DQM1 = 77
965 11:52:08.245520 DQ Delay:
966 11:52:08.245630 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 11:52:08.248404 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
968 11:52:08.251997 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
969 11:52:08.255419 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
970 11:52:08.255520
971 11:52:08.255611
972 11:52:08.259407 ==
973 11:52:08.262136 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:52:08.265478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:52:08.265556 ==
976 11:52:08.265622
977 11:52:08.265681
978 11:52:08.269132 TX Vref Scan disable
979 11:52:08.269231 == TX Byte 0 ==
980 11:52:08.272420 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
981 11:52:08.279032 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
982 11:52:08.279147 == TX Byte 1 ==
983 11:52:08.282731 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 11:52:08.289067 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 11:52:08.289156 ==
986 11:52:08.292289 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:52:08.295854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:52:08.295941 ==
989 11:52:08.308800 TX Vref=22, minBit 4, minWin=27, winSum=441
990 11:52:08.312376 TX Vref=24, minBit 5, minWin=27, winSum=443
991 11:52:08.315698 TX Vref=26, minBit 0, minWin=27, winSum=446
992 11:52:08.318616 TX Vref=28, minBit 1, minWin=28, winSum=455
993 11:52:08.322422 TX Vref=30, minBit 1, minWin=28, winSum=453
994 11:52:08.325599 TX Vref=32, minBit 9, minWin=27, winSum=451
995 11:52:08.331983 [TxChooseVref] Worse bit 1, Min win 28, Win sum 455, Final Vref 28
996 11:52:08.332076
997 11:52:08.335262 Final TX Range 1 Vref 28
998 11:52:08.335340
999 11:52:08.335404 ==
1000 11:52:08.338804 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:52:08.342457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:52:08.342537 ==
1003 11:52:08.342601
1004 11:52:08.342662
1005 11:52:08.345685 TX Vref Scan disable
1006 11:52:08.348786 == TX Byte 0 ==
1007 11:52:08.352270 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1008 11:52:08.355761 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1009 11:52:08.359191 == TX Byte 1 ==
1010 11:52:08.362324 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 11:52:08.366045 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 11:52:08.366161
1013 11:52:08.368858 [DATLAT]
1014 11:52:08.368933 Freq=800, CH0 RK0
1015 11:52:08.368996
1016 11:52:08.372124 DATLAT Default: 0xa
1017 11:52:08.372198 0, 0xFFFF, sum = 0
1018 11:52:08.375472 1, 0xFFFF, sum = 0
1019 11:52:08.375553 2, 0xFFFF, sum = 0
1020 11:52:08.379252 3, 0xFFFF, sum = 0
1021 11:52:08.379360 4, 0xFFFF, sum = 0
1022 11:52:08.382265 5, 0xFFFF, sum = 0
1023 11:52:08.382336 6, 0xFFFF, sum = 0
1024 11:52:08.385687 7, 0xFFFF, sum = 0
1025 11:52:08.385779 8, 0xFFFF, sum = 0
1026 11:52:08.389171 9, 0x0, sum = 1
1027 11:52:08.389263 10, 0x0, sum = 2
1028 11:52:08.392495 11, 0x0, sum = 3
1029 11:52:08.392585 12, 0x0, sum = 4
1030 11:52:08.396038 best_step = 10
1031 11:52:08.396137
1032 11:52:08.396226 ==
1033 11:52:08.399339 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:52:08.402329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:52:08.402428 ==
1036 11:52:08.405688 RX Vref Scan: 1
1037 11:52:08.405767
1038 11:52:08.405851 Set Vref Range= 32 -> 127
1039 11:52:08.405912
1040 11:52:08.409189 RX Vref 32 -> 127, step: 1
1041 11:52:08.409289
1042 11:52:08.412475 RX Delay -95 -> 252, step: 8
1043 11:52:08.412573
1044 11:52:08.415977 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:52:08.419072 [Byte1]: 32
1046 11:52:08.419201
1047 11:52:08.422829 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:52:08.426323 [Byte1]: 33
1049 11:52:08.426400
1050 11:52:08.429639 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:52:08.432950 [Byte1]: 34
1052 11:52:08.437141
1053 11:52:08.437220 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:52:08.439824 [Byte1]: 35
1055 11:52:08.444091
1056 11:52:08.444190 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:52:08.447531 [Byte1]: 36
1058 11:52:08.452459
1059 11:52:08.452598 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:52:08.455812 [Byte1]: 37
1061 11:52:08.459600
1062 11:52:08.459708 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:52:08.463238 [Byte1]: 38
1064 11:52:08.467159
1065 11:52:08.467239 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:52:08.470876 [Byte1]: 39
1067 11:52:08.475040
1068 11:52:08.475132 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:52:08.478394 [Byte1]: 40
1070 11:52:08.482664
1071 11:52:08.482771 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:52:08.485688 [Byte1]: 41
1073 11:52:08.490229
1074 11:52:08.490301 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:52:08.493166 [Byte1]: 42
1076 11:52:08.497257
1077 11:52:08.497344 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:52:08.500767 [Byte1]: 43
1079 11:52:08.504881
1080 11:52:08.504956 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:52:08.508391 [Byte1]: 44
1082 11:52:08.512344
1083 11:52:08.512436 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:52:08.515858 [Byte1]: 45
1085 11:52:08.519840
1086 11:52:08.519913 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:52:08.523235 [Byte1]: 46
1088 11:52:08.527935
1089 11:52:08.528013 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:52:08.530874 [Byte1]: 47
1091 11:52:08.535143
1092 11:52:08.535226 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:52:08.541533 [Byte1]: 48
1094 11:52:08.541610
1095 11:52:08.545178 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:52:08.548171 [Byte1]: 49
1097 11:52:08.548246
1098 11:52:08.552377 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:52:08.555101 [Byte1]: 50
1100 11:52:08.555180
1101 11:52:08.558531 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:52:08.561565 [Byte1]: 51
1103 11:52:08.565612
1104 11:52:08.565701 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:52:08.568978 [Byte1]: 52
1106 11:52:08.573069
1107 11:52:08.573146 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:52:08.576804 [Byte1]: 53
1109 11:52:08.580694
1110 11:52:08.580769 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:52:08.583993 [Byte1]: 54
1112 11:52:08.588863
1113 11:52:08.588954 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:52:08.591910 [Byte1]: 55
1115 11:52:08.596005
1116 11:52:08.596083 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:52:08.599185 [Byte1]: 56
1118 11:52:08.603459
1119 11:52:08.603569 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:52:08.607122 [Byte1]: 57
1121 11:52:08.611248
1122 11:52:08.611353 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:52:08.614599 [Byte1]: 58
1124 11:52:08.618792
1125 11:52:08.618896 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:52:08.622413 [Byte1]: 59
1127 11:52:08.626619
1128 11:52:08.626717 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:52:08.629480 [Byte1]: 60
1130 11:52:08.634257
1131 11:52:08.634330 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:52:08.637422 [Byte1]: 61
1133 11:52:08.641380
1134 11:52:08.641467 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:52:08.645031 [Byte1]: 62
1136 11:52:08.649115
1137 11:52:08.649202 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:52:08.652615 [Byte1]: 63
1139 11:52:08.656986
1140 11:52:08.657123 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:52:08.659842 [Byte1]: 64
1142 11:52:08.664528
1143 11:52:08.664609 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:52:08.667747 [Byte1]: 65
1145 11:52:08.672050
1146 11:52:08.672124 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:52:08.675517 [Byte1]: 66
1148 11:52:08.679283
1149 11:52:08.679358 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:52:08.683041 [Byte1]: 67
1151 11:52:08.687205
1152 11:52:08.687286 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:52:08.690569 [Byte1]: 68
1154 11:52:08.694515
1155 11:52:08.694586 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:52:08.697835 [Byte1]: 69
1157 11:52:08.702535
1158 11:52:08.702605 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:52:08.705751 [Byte1]: 70
1160 11:52:08.710040
1161 11:52:08.710113 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:52:08.713171 [Byte1]: 71
1163 11:52:08.717624
1164 11:52:08.717703 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:52:08.721169 [Byte1]: 72
1166 11:52:08.725350
1167 11:52:08.725429 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:52:08.728534 [Byte1]: 73
1169 11:52:08.732604
1170 11:52:08.732676 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:52:08.736217 [Byte1]: 74
1172 11:52:08.740163
1173 11:52:08.740246 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:52:08.743541 [Byte1]: 75
1175 11:52:08.748050
1176 11:52:08.748126 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:52:08.751042 [Byte1]: 76
1178 11:52:08.755732
1179 11:52:08.755810 Final RX Vref Byte 0 = 63 to rank0
1180 11:52:08.758997 Final RX Vref Byte 1 = 59 to rank0
1181 11:52:08.762549 Final RX Vref Byte 0 = 63 to rank1
1182 11:52:08.765924 Final RX Vref Byte 1 = 59 to rank1==
1183 11:52:08.769278 Dram Type= 6, Freq= 0, CH_0, rank 0
1184 11:52:08.772137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1185 11:52:08.776011 ==
1186 11:52:08.776096 DQS Delay:
1187 11:52:08.776184 DQS0 = 0, DQS1 = 0
1188 11:52:08.778896 DQM Delay:
1189 11:52:08.779008 DQM0 = 87, DQM1 = 79
1190 11:52:08.782426 DQ Delay:
1191 11:52:08.782520 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1192 11:52:08.785849 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1193 11:52:08.789173 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1194 11:52:08.792573 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =88
1195 11:52:08.792653
1196 11:52:08.792734
1197 11:52:08.802263 [DQSOSCAuto] RK0, (LSB)MR18= 0x280e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 399 ps
1198 11:52:08.806313 CH0 RK0: MR19=606, MR18=280E
1199 11:52:08.812294 CH0_RK0: MR19=0x606, MR18=0x280E, DQSOSC=399, MR23=63, INC=92, DEC=61
1200 11:52:08.812383
1201 11:52:08.815976 ----->DramcWriteLeveling(PI) begin...
1202 11:52:08.816055 ==
1203 11:52:08.819197 Dram Type= 6, Freq= 0, CH_0, rank 1
1204 11:52:08.822659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1205 11:52:08.822739 ==
1206 11:52:08.825988 Write leveling (Byte 0): 29 => 29
1207 11:52:08.829490 Write leveling (Byte 1): 28 => 28
1208 11:52:08.832400 DramcWriteLeveling(PI) end<-----
1209 11:52:08.832516
1210 11:52:08.832605 ==
1211 11:52:08.835886 Dram Type= 6, Freq= 0, CH_0, rank 1
1212 11:52:08.839403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1213 11:52:08.839481 ==
1214 11:52:08.842959 [Gating] SW mode calibration
1215 11:52:08.849344 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1216 11:52:08.856211 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1217 11:52:08.859798 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 11:52:08.862704 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1219 11:52:08.907077 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1220 11:52:08.907505 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:52:08.907619 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:52:08.907697 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:52:08.907792 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:52:08.908054 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:52:08.908317 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:52:08.908573 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:52:08.908648 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:52:08.908745 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:52:08.935958 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:52:08.936294 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:52:08.936557 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:52:08.936630 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:52:08.937284 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:52:08.937632 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1235 11:52:08.939979 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1236 11:52:08.943676 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:52:08.946515 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:52:08.949773 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:52:08.956625 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:52:08.960210 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:52:08.963354 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:52:08.969912 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:52:08.973358 0 9 8 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
1244 11:52:08.976834 0 9 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
1245 11:52:08.983736 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:52:08.986591 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:52:08.990067 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:52:08.993278 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:52:09.000540 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:52:09.003359 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
1251 11:52:09.007095 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1252 11:52:09.013605 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1253 11:52:09.017113 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:52:09.020244 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:52:09.027176 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:52:09.030433 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:52:09.033794 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:52:09.037435 0 11 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1259 11:52:09.044910 0 11 8 | B1->B0 | 2929 3a3a | 0 0 | (0 0) (0 0)
1260 11:52:09.049033 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1261 11:52:09.052744 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:52:09.056184 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:52:09.062244 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:52:09.066312 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:52:09.069796 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:52:09.073273 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:52:09.079451 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1268 11:52:09.082892 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1269 11:52:09.086225 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:52:09.093252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:52:09.096669 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:52:09.099914 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:52:09.106753 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:52:09.110384 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:52:09.113044 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:52:09.116527 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:52:09.123518 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:52:09.127049 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:52:09.129753 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:52:09.136446 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:52:09.140282 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:52:09.143337 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1283 11:52:09.150330 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1284 11:52:09.150410 Total UI for P1: 0, mck2ui 16
1285 11:52:09.156554 best dqsien dly found for B0: ( 0, 14, 4)
1286 11:52:09.159951 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 11:52:09.163308 Total UI for P1: 0, mck2ui 16
1288 11:52:09.166892 best dqsien dly found for B1: ( 0, 14, 8)
1289 11:52:09.170426 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1290 11:52:09.173770 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1291 11:52:09.173842
1292 11:52:09.177011 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1293 11:52:09.180620 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1294 11:52:09.183546 [Gating] SW calibration Done
1295 11:52:09.183622 ==
1296 11:52:09.187007 Dram Type= 6, Freq= 0, CH_0, rank 1
1297 11:52:09.190263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1298 11:52:09.190335 ==
1299 11:52:09.193675 RX Vref Scan: 0
1300 11:52:09.193752
1301 11:52:09.193814 RX Vref 0 -> 0, step: 1
1302 11:52:09.193873
1303 11:52:09.196950 RX Delay -130 -> 252, step: 16
1304 11:52:09.203544 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1305 11:52:09.206928 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1306 11:52:09.210459 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1307 11:52:09.213889 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1308 11:52:09.216939 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1309 11:52:09.220248 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1310 11:52:09.227325 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1311 11:52:09.230442 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1312 11:52:09.234308 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1313 11:52:09.237502 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1314 11:52:09.240453 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1315 11:52:09.247591 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1316 11:52:09.250896 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1317 11:52:09.254233 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1318 11:52:09.257370 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1319 11:52:09.260662 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1320 11:52:09.264236 ==
1321 11:52:09.264317 Dram Type= 6, Freq= 0, CH_0, rank 1
1322 11:52:09.271006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1323 11:52:09.271099 ==
1324 11:52:09.271190 DQS Delay:
1325 11:52:09.274621 DQS0 = 0, DQS1 = 0
1326 11:52:09.274698 DQM Delay:
1327 11:52:09.274798 DQM0 = 87, DQM1 = 77
1328 11:52:09.277761 DQ Delay:
1329 11:52:09.280910 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1330 11:52:09.284255 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
1331 11:52:09.287615 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1332 11:52:09.291075 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1333 11:52:09.291151
1334 11:52:09.291216
1335 11:52:09.291276 ==
1336 11:52:09.294235 Dram Type= 6, Freq= 0, CH_0, rank 1
1337 11:52:09.297947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1338 11:52:09.298023 ==
1339 11:52:09.298086
1340 11:52:09.298145
1341 11:52:09.300793 TX Vref Scan disable
1342 11:52:09.304397 == TX Byte 0 ==
1343 11:52:09.307692 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1344 11:52:09.311128 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1345 11:52:09.311197 == TX Byte 1 ==
1346 11:52:09.317820 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1347 11:52:09.321382 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1348 11:52:09.321477 ==
1349 11:52:09.325063 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 11:52:09.327687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 11:52:09.327757 ==
1352 11:52:09.341975 TX Vref=22, minBit 2, minWin=27, winSum=439
1353 11:52:09.345708 TX Vref=24, minBit 2, minWin=27, winSum=443
1354 11:52:09.349032 TX Vref=26, minBit 2, minWin=27, winSum=448
1355 11:52:09.352321 TX Vref=28, minBit 12, minWin=27, winSum=449
1356 11:52:09.355860 TX Vref=30, minBit 0, minWin=28, winSum=456
1357 11:52:09.359022 TX Vref=32, minBit 0, minWin=28, winSum=453
1358 11:52:09.365663 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1359 11:52:09.365847
1360 11:52:09.369095 Final TX Range 1 Vref 30
1361 11:52:09.369188
1362 11:52:09.369252 ==
1363 11:52:09.372412 Dram Type= 6, Freq= 0, CH_0, rank 1
1364 11:52:09.375425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1365 11:52:09.375508 ==
1366 11:52:09.375571
1367 11:52:09.375628
1368 11:52:09.379171 TX Vref Scan disable
1369 11:52:09.382348 == TX Byte 0 ==
1370 11:52:09.385734 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1371 11:52:09.389203 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1372 11:52:09.392937 == TX Byte 1 ==
1373 11:52:09.396021 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1374 11:52:09.399406 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1375 11:52:09.399487
1376 11:52:09.403079 [DATLAT]
1377 11:52:09.403158 Freq=800, CH0 RK1
1378 11:52:09.403221
1379 11:52:09.406042 DATLAT Default: 0xa
1380 11:52:09.406122 0, 0xFFFF, sum = 0
1381 11:52:09.409354 1, 0xFFFF, sum = 0
1382 11:52:09.409435 2, 0xFFFF, sum = 0
1383 11:52:09.412950 3, 0xFFFF, sum = 0
1384 11:52:09.413032 4, 0xFFFF, sum = 0
1385 11:52:09.416090 5, 0xFFFF, sum = 0
1386 11:52:09.416170 6, 0xFFFF, sum = 0
1387 11:52:09.419332 7, 0xFFFF, sum = 0
1388 11:52:09.419412 8, 0xFFFF, sum = 0
1389 11:52:09.423056 9, 0x0, sum = 1
1390 11:52:09.423137 10, 0x0, sum = 2
1391 11:52:09.426299 11, 0x0, sum = 3
1392 11:52:09.426379 12, 0x0, sum = 4
1393 11:52:09.429781 best_step = 10
1394 11:52:09.429860
1395 11:52:09.429921 ==
1396 11:52:09.433436 Dram Type= 6, Freq= 0, CH_0, rank 1
1397 11:52:09.436278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1398 11:52:09.436358 ==
1399 11:52:09.436421 RX Vref Scan: 0
1400 11:52:09.436478
1401 11:52:09.439754 RX Vref 0 -> 0, step: 1
1402 11:52:09.439833
1403 11:52:09.443223 RX Delay -95 -> 252, step: 8
1404 11:52:09.446569 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1405 11:52:09.453127 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1406 11:52:09.456773 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1407 11:52:09.459980 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1408 11:52:09.463460 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1409 11:52:09.466366 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1410 11:52:09.469995 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1411 11:52:09.476700 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1412 11:52:09.480108 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1413 11:52:09.483114 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1414 11:52:09.486974 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1415 11:52:09.490220 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1416 11:52:09.497048 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1417 11:52:09.499831 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1418 11:52:09.503312 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1419 11:52:09.507092 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1420 11:52:09.507197 ==
1421 11:52:09.510526 Dram Type= 6, Freq= 0, CH_0, rank 1
1422 11:52:09.516533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1423 11:52:09.516613 ==
1424 11:52:09.516675 DQS Delay:
1425 11:52:09.516748 DQS0 = 0, DQS1 = 0
1426 11:52:09.520146 DQM Delay:
1427 11:52:09.520224 DQM0 = 87, DQM1 = 77
1428 11:52:09.523551 DQ Delay:
1429 11:52:09.527132 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1430 11:52:09.527212 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1431 11:52:09.530294 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1432 11:52:09.533736 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1433 11:52:09.533815
1434 11:52:09.536774
1435 11:52:09.544052 [DQSOSCAuto] RK1, (LSB)MR18= 0x301a, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1436 11:52:09.547147 CH0 RK1: MR19=606, MR18=301A
1437 11:52:09.553685 CH0_RK1: MR19=0x606, MR18=0x301A, DQSOSC=397, MR23=63, INC=93, DEC=62
1438 11:52:09.553794 [RxdqsGatingPostProcess] freq 800
1439 11:52:09.560396 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1440 11:52:09.563698 Pre-setting of DQS Precalculation
1441 11:52:09.567036 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1442 11:52:09.570950 ==
1443 11:52:09.574109 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 11:52:09.577588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 11:52:09.577667 ==
1446 11:52:09.580759 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1447 11:52:09.587637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1448 11:52:09.597052 [CA 0] Center 36 (6~66) winsize 61
1449 11:52:09.600430 [CA 1] Center 36 (6~66) winsize 61
1450 11:52:09.603569 [CA 2] Center 34 (4~64) winsize 61
1451 11:52:09.606803 [CA 3] Center 33 (3~64) winsize 62
1452 11:52:09.610108 [CA 4] Center 34 (4~65) winsize 62
1453 11:52:09.613612 [CA 5] Center 33 (3~64) winsize 62
1454 11:52:09.613692
1455 11:52:09.617204 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1456 11:52:09.617285
1457 11:52:09.620195 [CATrainingPosCal] consider 1 rank data
1458 11:52:09.623739 u2DelayCellTimex100 = 270/100 ps
1459 11:52:09.627273 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1460 11:52:09.630345 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1461 11:52:09.633935 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1462 11:52:09.640398 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1463 11:52:09.643903 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1464 11:52:09.647483 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1465 11:52:09.647563
1466 11:52:09.651090 CA PerBit enable=1, Macro0, CA PI delay=33
1467 11:52:09.651171
1468 11:52:09.654407 [CBTSetCACLKResult] CA Dly = 33
1469 11:52:09.654486 CS Dly: 3 (0~34)
1470 11:52:09.654549 ==
1471 11:52:09.657400 Dram Type= 6, Freq= 0, CH_1, rank 1
1472 11:52:09.660856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1473 11:52:09.663863 ==
1474 11:52:09.667548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1475 11:52:09.674416 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1476 11:52:09.682957 [CA 0] Center 36 (6~66) winsize 61
1477 11:52:09.686297 [CA 1] Center 36 (6~66) winsize 61
1478 11:52:09.689941 [CA 2] Center 34 (4~65) winsize 62
1479 11:52:09.693015 [CA 3] Center 33 (3~64) winsize 62
1480 11:52:09.696418 [CA 4] Center 34 (4~65) winsize 62
1481 11:52:09.699847 [CA 5] Center 33 (3~64) winsize 62
1482 11:52:09.699928
1483 11:52:09.703199 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1484 11:52:09.703312
1485 11:52:09.707039 [CATrainingPosCal] consider 2 rank data
1486 11:52:09.711062 u2DelayCellTimex100 = 270/100 ps
1487 11:52:09.714640 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1488 11:52:09.718145 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1489 11:52:09.722095 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1490 11:52:09.725825 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1491 11:52:09.729571 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1492 11:52:09.733497 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1493 11:52:09.733577
1494 11:52:09.736937 CA PerBit enable=1, Macro0, CA PI delay=33
1495 11:52:09.737017
1496 11:52:09.740465 [CBTSetCACLKResult] CA Dly = 33
1497 11:52:09.740549 CS Dly: 4 (0~37)
1498 11:52:09.740619
1499 11:52:09.743842 ----->DramcWriteLeveling(PI) begin...
1500 11:52:09.743924 ==
1501 11:52:09.747054 Dram Type= 6, Freq= 0, CH_1, rank 0
1502 11:52:09.750419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1503 11:52:09.753826 ==
1504 11:52:09.753931 Write leveling (Byte 0): 28 => 28
1505 11:52:09.757167 Write leveling (Byte 1): 28 => 28
1506 11:52:09.760730 DramcWriteLeveling(PI) end<-----
1507 11:52:09.760840
1508 11:52:09.760902 ==
1509 11:52:09.763671 Dram Type= 6, Freq= 0, CH_1, rank 0
1510 11:52:09.770772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1511 11:52:09.770913 ==
1512 11:52:09.770978 [Gating] SW mode calibration
1513 11:52:09.780780 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1514 11:52:09.784356 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1515 11:52:09.787624 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1516 11:52:09.794088 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1517 11:52:09.797595 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:52:09.801318 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:52:09.807555 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:52:09.811257 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:52:09.814506 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:52:09.817610 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:52:09.824507 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:52:09.827649 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:52:09.831139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:52:09.838055 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:52:09.841230 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:52:09.844656 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:52:09.851524 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:52:09.854743 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:52:09.858007 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:52:09.864762 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:52:09.868315 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1534 11:52:09.872136 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:52:09.874634 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:52:09.881586 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:52:09.885183 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:52:09.888468 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:52:09.895322 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:52:09.898517 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:52:09.901998 0 9 8 | B1->B0 | 2424 2828 | 0 0 | (1 1) (0 0)
1542 11:52:09.908525 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1543 11:52:09.912034 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:52:09.915586 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:52:09.921995 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:52:09.925594 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:52:09.928842 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:52:09.932031 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1549 11:52:09.938840 0 10 8 | B1->B0 | 2f2f 2c2c | 0 0 | (1 1) (1 1)
1550 11:52:09.942381 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:52:09.945843 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:52:09.952343 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:52:09.956020 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:52:09.959043 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:52:09.965433 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:52:09.969108 0 11 4 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
1557 11:52:09.972278 0 11 8 | B1->B0 | 3535 3434 | 0 0 | (1 1) (0 0)
1558 11:52:09.978822 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:52:09.982394 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:52:09.985795 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:52:09.989331 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:52:09.995896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:52:09.999338 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:52:10.003022 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1565 11:52:10.009401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:52:10.012852 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:52:10.016295 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:52:10.022852 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:52:10.026111 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:52:10.029704 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:52:10.036184 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:52:10.039625 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:52:10.042664 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:52:10.046157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:52:10.052960 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:52:10.056135 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:52:10.059748 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:52:10.066276 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:52:10.069876 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:52:10.073066 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1581 11:52:10.076882 Total UI for P1: 0, mck2ui 16
1582 11:52:10.079919 best dqsien dly found for B0: ( 0, 14, 2)
1583 11:52:10.086407 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 11:52:10.086496 Total UI for P1: 0, mck2ui 16
1585 11:52:10.092946 best dqsien dly found for B1: ( 0, 14, 4)
1586 11:52:10.096666 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1587 11:52:10.099737 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1588 11:52:10.099813
1589 11:52:10.103260 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1590 11:52:10.106592 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1591 11:52:10.110010 [Gating] SW calibration Done
1592 11:52:10.110091 ==
1593 11:52:10.112975 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:52:10.116387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:52:10.116469 ==
1596 11:52:10.116532 RX Vref Scan: 0
1597 11:52:10.119976
1598 11:52:10.120055 RX Vref 0 -> 0, step: 1
1599 11:52:10.120117
1600 11:52:10.123120 RX Delay -130 -> 252, step: 16
1601 11:52:10.126727 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1602 11:52:10.130518 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1603 11:52:10.137085 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1604 11:52:10.139942 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1605 11:52:10.143311 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1606 11:52:10.146800 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1607 11:52:10.150348 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1608 11:52:10.157494 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1609 11:52:10.160579 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1610 11:52:10.163765 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1611 11:52:10.167195 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1612 11:52:10.170151 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1613 11:52:10.173800 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1614 11:52:10.180180 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1615 11:52:10.183602 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1616 11:52:10.187088 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1617 11:52:10.187168 ==
1618 11:52:10.190436 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 11:52:10.194133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 11:52:10.194209 ==
1621 11:52:10.197423 DQS Delay:
1622 11:52:10.197496 DQS0 = 0, DQS1 = 0
1623 11:52:10.200953 DQM Delay:
1624 11:52:10.201031 DQM0 = 84, DQM1 = 77
1625 11:52:10.201113 DQ Delay:
1626 11:52:10.204383 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
1627 11:52:10.207413 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1628 11:52:10.210799 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1629 11:52:10.214042 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 11:52:10.214120
1631 11:52:10.214202
1632 11:52:10.214298 ==
1633 11:52:10.217324 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 11:52:10.224024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 11:52:10.224102 ==
1636 11:52:10.224185
1637 11:52:10.224263
1638 11:52:10.224348 TX Vref Scan disable
1639 11:52:10.228211 == TX Byte 0 ==
1640 11:52:10.231610 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1641 11:52:10.234752 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1642 11:52:10.238112 == TX Byte 1 ==
1643 11:52:10.241697 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1644 11:52:10.244611 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1645 11:52:10.248071 ==
1646 11:52:10.248147 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:52:10.255083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 11:52:10.255165 ==
1649 11:52:10.266986 TX Vref=22, minBit 11, minWin=26, winSum=440
1650 11:52:10.270548 TX Vref=24, minBit 5, minWin=27, winSum=441
1651 11:52:10.273775 TX Vref=26, minBit 0, minWin=27, winSum=445
1652 11:52:10.277367 TX Vref=28, minBit 1, minWin=27, winSum=446
1653 11:52:10.280291 TX Vref=30, minBit 11, minWin=27, winSum=451
1654 11:52:10.284202 TX Vref=32, minBit 0, minWin=28, winSum=452
1655 11:52:10.291572 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 32
1656 11:52:10.291667
1657 11:52:10.294486 Final TX Range 1 Vref 32
1658 11:52:10.294566
1659 11:52:10.294666 ==
1660 11:52:10.297908 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 11:52:10.301330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 11:52:10.301408 ==
1663 11:52:10.301490
1664 11:52:10.301576
1665 11:52:10.304422 TX Vref Scan disable
1666 11:52:10.308347 == TX Byte 0 ==
1667 11:52:10.311485 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1668 11:52:10.314707 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1669 11:52:10.318155 == TX Byte 1 ==
1670 11:52:10.321612 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1671 11:52:10.325009 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1672 11:52:10.325090
1673 11:52:10.325179 [DATLAT]
1674 11:52:10.327941 Freq=800, CH1 RK0
1675 11:52:10.328014
1676 11:52:10.331419 DATLAT Default: 0xa
1677 11:52:10.331497 0, 0xFFFF, sum = 0
1678 11:52:10.335131 1, 0xFFFF, sum = 0
1679 11:52:10.335210 2, 0xFFFF, sum = 0
1680 11:52:10.338387 3, 0xFFFF, sum = 0
1681 11:52:10.338463 4, 0xFFFF, sum = 0
1682 11:52:10.341241 5, 0xFFFF, sum = 0
1683 11:52:10.341320 6, 0xFFFF, sum = 0
1684 11:52:10.345328 7, 0xFFFF, sum = 0
1685 11:52:10.345402 8, 0xFFFF, sum = 0
1686 11:52:10.348313 9, 0x0, sum = 1
1687 11:52:10.348385 10, 0x0, sum = 2
1688 11:52:10.351821 11, 0x0, sum = 3
1689 11:52:10.351894 12, 0x0, sum = 4
1690 11:52:10.351957 best_step = 10
1691 11:52:10.352013
1692 11:52:10.355108 ==
1693 11:52:10.358120 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 11:52:10.361987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 11:52:10.362063 ==
1696 11:52:10.362126 RX Vref Scan: 1
1697 11:52:10.362190
1698 11:52:10.364874 Set Vref Range= 32 -> 127
1699 11:52:10.364940
1700 11:52:10.368368 RX Vref 32 -> 127, step: 1
1701 11:52:10.368446
1702 11:52:10.371556 RX Delay -95 -> 252, step: 8
1703 11:52:10.371624
1704 11:52:10.374984 Set Vref, RX VrefLevel [Byte0]: 32
1705 11:52:10.378243 [Byte1]: 32
1706 11:52:10.378313
1707 11:52:10.381488 Set Vref, RX VrefLevel [Byte0]: 33
1708 11:52:10.384872 [Byte1]: 33
1709 11:52:10.384948
1710 11:52:10.388581 Set Vref, RX VrefLevel [Byte0]: 34
1711 11:52:10.391593 [Byte1]: 34
1712 11:52:10.391670
1713 11:52:10.394981 Set Vref, RX VrefLevel [Byte0]: 35
1714 11:52:10.398596 [Byte1]: 35
1715 11:52:10.402368
1716 11:52:10.402441 Set Vref, RX VrefLevel [Byte0]: 36
1717 11:52:10.405882 [Byte1]: 36
1718 11:52:10.410378
1719 11:52:10.410453 Set Vref, RX VrefLevel [Byte0]: 37
1720 11:52:10.413589 [Byte1]: 37
1721 11:52:10.417613
1722 11:52:10.417687 Set Vref, RX VrefLevel [Byte0]: 38
1723 11:52:10.421266 [Byte1]: 38
1724 11:52:10.425341
1725 11:52:10.425448 Set Vref, RX VrefLevel [Byte0]: 39
1726 11:52:10.428654 [Byte1]: 39
1727 11:52:10.432699
1728 11:52:10.432771 Set Vref, RX VrefLevel [Byte0]: 40
1729 11:52:10.436269 [Byte1]: 40
1730 11:52:10.440287
1731 11:52:10.440362 Set Vref, RX VrefLevel [Byte0]: 41
1732 11:52:10.443809 [Byte1]: 41
1733 11:52:10.448120
1734 11:52:10.448193 Set Vref, RX VrefLevel [Byte0]: 42
1735 11:52:10.451636 [Byte1]: 42
1736 11:52:10.455644
1737 11:52:10.455724 Set Vref, RX VrefLevel [Byte0]: 43
1738 11:52:10.459031 [Byte1]: 43
1739 11:52:10.463606
1740 11:52:10.463684 Set Vref, RX VrefLevel [Byte0]: 44
1741 11:52:10.466829 [Byte1]: 44
1742 11:52:10.471094
1743 11:52:10.471165 Set Vref, RX VrefLevel [Byte0]: 45
1744 11:52:10.474375 [Byte1]: 45
1745 11:52:10.478698
1746 11:52:10.478771 Set Vref, RX VrefLevel [Byte0]: 46
1747 11:52:10.482163 [Byte1]: 46
1748 11:52:10.486253
1749 11:52:10.486332 Set Vref, RX VrefLevel [Byte0]: 47
1750 11:52:10.489239 [Byte1]: 47
1751 11:52:10.493960
1752 11:52:10.494032 Set Vref, RX VrefLevel [Byte0]: 48
1753 11:52:10.497339 [Byte1]: 48
1754 11:52:10.501432
1755 11:52:10.501512 Set Vref, RX VrefLevel [Byte0]: 49
1756 11:52:10.504935 [Byte1]: 49
1757 11:52:10.508797
1758 11:52:10.508878 Set Vref, RX VrefLevel [Byte0]: 50
1759 11:52:10.512239 [Byte1]: 50
1760 11:52:10.516456
1761 11:52:10.516527 Set Vref, RX VrefLevel [Byte0]: 51
1762 11:52:10.519803 [Byte1]: 51
1763 11:52:10.524218
1764 11:52:10.524288 Set Vref, RX VrefLevel [Byte0]: 52
1765 11:52:10.527379 [Byte1]: 52
1766 11:52:10.531508
1767 11:52:10.531579 Set Vref, RX VrefLevel [Byte0]: 53
1768 11:52:10.535099 [Byte1]: 53
1769 11:52:10.539448
1770 11:52:10.539529 Set Vref, RX VrefLevel [Byte0]: 54
1771 11:52:10.542940 [Byte1]: 54
1772 11:52:10.546569
1773 11:52:10.546653 Set Vref, RX VrefLevel [Byte0]: 55
1774 11:52:10.550310 [Byte1]: 55
1775 11:52:10.554272
1776 11:52:10.554352 Set Vref, RX VrefLevel [Byte0]: 56
1777 11:52:10.557787 [Byte1]: 56
1778 11:52:10.561870
1779 11:52:10.561949 Set Vref, RX VrefLevel [Byte0]: 57
1780 11:52:10.565482 [Byte1]: 57
1781 11:52:10.569846
1782 11:52:10.569925 Set Vref, RX VrefLevel [Byte0]: 58
1783 11:52:10.572813 [Byte1]: 58
1784 11:52:10.577044
1785 11:52:10.577115 Set Vref, RX VrefLevel [Byte0]: 59
1786 11:52:10.580736 [Byte1]: 59
1787 11:52:10.584892
1788 11:52:10.584970 Set Vref, RX VrefLevel [Byte0]: 60
1789 11:52:10.588059 [Byte1]: 60
1790 11:52:10.592660
1791 11:52:10.592739 Set Vref, RX VrefLevel [Byte0]: 61
1792 11:52:10.595683 [Byte1]: 61
1793 11:52:10.600337
1794 11:52:10.600417 Set Vref, RX VrefLevel [Byte0]: 62
1795 11:52:10.602994 [Byte1]: 62
1796 11:52:10.607888
1797 11:52:10.607966 Set Vref, RX VrefLevel [Byte0]: 63
1798 11:52:10.611070 [Byte1]: 63
1799 11:52:10.615157
1800 11:52:10.615239 Set Vref, RX VrefLevel [Byte0]: 64
1801 11:52:10.618645 [Byte1]: 64
1802 11:52:10.623000
1803 11:52:10.623078 Set Vref, RX VrefLevel [Byte0]: 65
1804 11:52:10.626001 [Byte1]: 65
1805 11:52:10.630730
1806 11:52:10.630808 Set Vref, RX VrefLevel [Byte0]: 66
1807 11:52:10.633799 [Byte1]: 66
1808 11:52:10.638021
1809 11:52:10.638105 Set Vref, RX VrefLevel [Byte0]: 67
1810 11:52:10.641456 [Byte1]: 67
1811 11:52:10.645555
1812 11:52:10.645629 Set Vref, RX VrefLevel [Byte0]: 68
1813 11:52:10.648942 [Byte1]: 68
1814 11:52:10.653040
1815 11:52:10.653119 Set Vref, RX VrefLevel [Byte0]: 69
1816 11:52:10.656270 [Byte1]: 69
1817 11:52:10.660715
1818 11:52:10.660809 Set Vref, RX VrefLevel [Byte0]: 70
1819 11:52:10.664362 [Byte1]: 70
1820 11:52:10.668746
1821 11:52:10.668823 Set Vref, RX VrefLevel [Byte0]: 71
1822 11:52:10.671526 [Byte1]: 71
1823 11:52:10.676231
1824 11:52:10.676310 Set Vref, RX VrefLevel [Byte0]: 72
1825 11:52:10.679137 [Byte1]: 72
1826 11:52:10.683897
1827 11:52:10.683980 Set Vref, RX VrefLevel [Byte0]: 73
1828 11:52:10.686789 [Byte1]: 73
1829 11:52:10.691062
1830 11:52:10.691140 Set Vref, RX VrefLevel [Byte0]: 74
1831 11:52:10.694672 [Byte1]: 74
1832 11:52:10.698979
1833 11:52:10.699064 Set Vref, RX VrefLevel [Byte0]: 75
1834 11:52:10.702323 [Byte1]: 75
1835 11:52:10.706581
1836 11:52:10.706658 Set Vref, RX VrefLevel [Byte0]: 76
1837 11:52:10.709944 [Byte1]: 76
1838 11:52:10.714277
1839 11:52:10.714375 Set Vref, RX VrefLevel [Byte0]: 77
1840 11:52:10.717023 [Byte1]: 77
1841 11:52:10.721411
1842 11:52:10.721486 Set Vref, RX VrefLevel [Byte0]: 78
1843 11:52:10.724661 [Byte1]: 78
1844 11:52:10.729318
1845 11:52:10.729394 Set Vref, RX VrefLevel [Byte0]: 79
1846 11:52:10.732308 [Byte1]: 79
1847 11:52:10.736772
1848 11:52:10.736852 Final RX Vref Byte 0 = 62 to rank0
1849 11:52:10.740341 Final RX Vref Byte 1 = 57 to rank0
1850 11:52:10.743443 Final RX Vref Byte 0 = 62 to rank1
1851 11:52:10.746959 Final RX Vref Byte 1 = 57 to rank1==
1852 11:52:10.749969 Dram Type= 6, Freq= 0, CH_1, rank 0
1853 11:52:10.756966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 11:52:10.757048 ==
1855 11:52:10.757131 DQS Delay:
1856 11:52:10.757209 DQS0 = 0, DQS1 = 0
1857 11:52:10.760375 DQM Delay:
1858 11:52:10.760450 DQM0 = 83, DQM1 = 73
1859 11:52:10.763618 DQ Delay:
1860 11:52:10.766627 DQ0 =88, DQ1 =76, DQ2 =72, DQ3 =84
1861 11:52:10.766728 DQ4 =80, DQ5 =96, DQ6 =92, DQ7 =76
1862 11:52:10.770227 DQ8 =60, DQ9 =60, DQ10 =72, DQ11 =68
1863 11:52:10.773706 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =76
1864 11:52:10.773783
1865 11:52:10.776868
1866 11:52:10.783708 [DQSOSCAuto] RK0, (LSB)MR18= 0x28fd, (MSB)MR19= 0x605, tDQSOscB0 = 410 ps tDQSOscB1 = 399 ps
1867 11:52:10.787081 CH1 RK0: MR19=605, MR18=28FD
1868 11:52:10.793724 CH1_RK0: MR19=0x605, MR18=0x28FD, DQSOSC=399, MR23=63, INC=92, DEC=61
1869 11:52:10.793806
1870 11:52:10.797437 ----->DramcWriteLeveling(PI) begin...
1871 11:52:10.797536 ==
1872 11:52:10.800770 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 11:52:10.803795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 11:52:10.803874 ==
1875 11:52:10.807231 Write leveling (Byte 0): 28 => 28
1876 11:52:10.811030 Write leveling (Byte 1): 29 => 29
1877 11:52:10.814044 DramcWriteLeveling(PI) end<-----
1878 11:52:10.814146
1879 11:52:10.814230 ==
1880 11:52:10.817317 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 11:52:10.820743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 11:52:10.820820 ==
1883 11:52:10.824248 [Gating] SW mode calibration
1884 11:52:10.830698 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1885 11:52:10.834206 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1886 11:52:10.840877 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1887 11:52:10.844533 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1888 11:52:10.847878 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:52:10.854501 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:52:10.857818 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:52:10.861211 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:52:10.867831 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:52:10.871591 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:52:10.874441 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:52:10.878035 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:52:10.884387 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:52:10.888118 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:52:10.891729 0 7 16 | B1->B0 | 2323 2323 | 1 0 | (0 0) (0 0)
1899 11:52:10.898053 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:52:10.901232 0 7 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1901 11:52:10.904882 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:52:10.911435 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1903 11:52:10.914759 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1904 11:52:10.918573 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:52:10.924893 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:52:10.928289 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:52:10.931932 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:52:10.938204 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:52:10.941771 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:52:10.944856 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:52:10.948343 0 9 4 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
1912 11:52:10.954950 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1913 11:52:10.958555 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1914 11:52:10.961872 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1915 11:52:10.968823 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1916 11:52:10.971846 0 9 24 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
1917 11:52:10.975702 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:52:10.982024 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1919 11:52:10.985363 0 10 4 | B1->B0 | 3131 2828 | 0 0 | (0 1) (0 0)
1920 11:52:10.988850 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1921 11:52:10.992431 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:52:10.999230 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:52:11.002232 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:52:11.005666 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:52:11.012441 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:52:11.015967 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:52:11.019283 0 11 4 | B1->B0 | 2d2d 2929 | 0 0 | (0 0) (0 0)
1928 11:52:11.026000 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1929 11:52:11.029674 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1930 11:52:11.032684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1931 11:52:11.039580 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:52:11.042485 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1933 11:52:11.046083 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:52:11.049576 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:52:11.056323 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1936 11:52:11.059712 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 11:52:11.062629 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 11:52:11.069497 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 11:52:11.072807 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 11:52:11.076002 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:52:11.082650 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:52:11.086473 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:52:11.089984 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:52:11.096104 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:52:11.099696 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:52:11.103049 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:52:11.109653 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:52:11.113004 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:52:11.116769 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:52:11.119523 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:52:11.126963 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1952 11:52:11.129969 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1953 11:52:11.133231 Total UI for P1: 0, mck2ui 16
1954 11:52:11.136998 best dqsien dly found for B0: ( 0, 14, 4)
1955 11:52:11.140300 Total UI for P1: 0, mck2ui 16
1956 11:52:11.143248 best dqsien dly found for B1: ( 0, 14, 4)
1957 11:52:11.146976 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1958 11:52:11.149977 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1959 11:52:11.150051
1960 11:52:11.153618 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1961 11:52:11.156827 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1962 11:52:11.160500 [Gating] SW calibration Done
1963 11:52:11.160574 ==
1964 11:52:11.164097 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 11:52:11.166952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 11:52:11.167026 ==
1967 11:52:11.170451 RX Vref Scan: 0
1968 11:52:11.170518
1969 11:52:11.173934 RX Vref 0 -> 0, step: 1
1970 11:52:11.174006
1971 11:52:11.174066 RX Delay -130 -> 252, step: 16
1972 11:52:11.180329 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1973 11:52:11.183526 iDelay=206, Bit 1, Center 69 (-50 ~ 189) 240
1974 11:52:11.186978 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1975 11:52:11.190680 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1976 11:52:11.193995 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1977 11:52:11.197639 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1978 11:52:11.204089 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1979 11:52:11.207570 iDelay=206, Bit 7, Center 69 (-50 ~ 189) 240
1980 11:52:11.210980 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1981 11:52:11.213982 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1982 11:52:11.217575 iDelay=206, Bit 10, Center 77 (-50 ~ 205) 256
1983 11:52:11.224445 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1984 11:52:11.227410 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1985 11:52:11.230803 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1986 11:52:11.234389 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1987 11:52:11.238180 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1988 11:52:11.240986 ==
1989 11:52:11.241057 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:52:11.247644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:52:11.247719 ==
1992 11:52:11.247781 DQS Delay:
1993 11:52:11.251470 DQS0 = 0, DQS1 = 0
1994 11:52:11.251558 DQM Delay:
1995 11:52:11.251618 DQM0 = 80, DQM1 = 77
1996 11:52:11.254663 DQ Delay:
1997 11:52:11.258234 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =85
1998 11:52:11.261353 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =69
1999 11:52:11.264758 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
2000 11:52:11.267810 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2001 11:52:11.267910
2002 11:52:11.267975
2003 11:52:11.268033 ==
2004 11:52:11.271284 Dram Type= 6, Freq= 0, CH_1, rank 1
2005 11:52:11.274761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2006 11:52:11.274833 ==
2007 11:52:11.274936
2008 11:52:11.274994
2009 11:52:11.278429 TX Vref Scan disable
2010 11:52:11.278507 == TX Byte 0 ==
2011 11:52:11.284839 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2012 11:52:11.288187 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2013 11:52:11.288260 == TX Byte 1 ==
2014 11:52:11.294772 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2015 11:52:11.298219 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2016 11:52:11.298295 ==
2017 11:52:11.301748 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:52:11.304736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:52:11.304814 ==
2020 11:52:11.318700 TX Vref=22, minBit 5, minWin=27, winSum=443
2021 11:52:11.321663 TX Vref=24, minBit 1, minWin=27, winSum=444
2022 11:52:11.324921 TX Vref=26, minBit 0, minWin=27, winSum=448
2023 11:52:11.328244 TX Vref=28, minBit 0, minWin=28, winSum=450
2024 11:52:11.331590 TX Vref=30, minBit 0, minWin=28, winSum=454
2025 11:52:11.335395 TX Vref=32, minBit 0, minWin=28, winSum=454
2026 11:52:11.341710 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 30
2027 11:52:11.341800
2028 11:52:11.345336 Final TX Range 1 Vref 30
2029 11:52:11.345415
2030 11:52:11.345480 ==
2031 11:52:11.348912 Dram Type= 6, Freq= 0, CH_1, rank 1
2032 11:52:11.351795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2033 11:52:11.351914 ==
2034 11:52:11.351986
2035 11:52:11.352044
2036 11:52:11.355396 TX Vref Scan disable
2037 11:52:11.358688 == TX Byte 0 ==
2038 11:52:11.362148 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2039 11:52:11.365263 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2040 11:52:11.368825 == TX Byte 1 ==
2041 11:52:11.372367 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2042 11:52:11.375439 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2043 11:52:11.375518
2044 11:52:11.378906 [DATLAT]
2045 11:52:11.378983 Freq=800, CH1 RK1
2046 11:52:11.379067
2047 11:52:11.382774 DATLAT Default: 0xa
2048 11:52:11.382900 0, 0xFFFF, sum = 0
2049 11:52:11.385857 1, 0xFFFF, sum = 0
2050 11:52:11.385939 2, 0xFFFF, sum = 0
2051 11:52:11.388931 3, 0xFFFF, sum = 0
2052 11:52:11.389011 4, 0xFFFF, sum = 0
2053 11:52:11.392572 5, 0xFFFF, sum = 0
2054 11:52:11.392647 6, 0xFFFF, sum = 0
2055 11:52:11.395937 7, 0xFFFF, sum = 0
2056 11:52:11.396010 8, 0xFFFF, sum = 0
2057 11:52:11.399300 9, 0x0, sum = 1
2058 11:52:11.399376 10, 0x0, sum = 2
2059 11:52:11.402550 11, 0x0, sum = 3
2060 11:52:11.402630 12, 0x0, sum = 4
2061 11:52:11.405810 best_step = 10
2062 11:52:11.405881
2063 11:52:11.405958 ==
2064 11:52:11.409382 Dram Type= 6, Freq= 0, CH_1, rank 1
2065 11:52:11.412955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2066 11:52:11.413032 ==
2067 11:52:11.413116 RX Vref Scan: 0
2068 11:52:11.413188
2069 11:52:11.415822 RX Vref 0 -> 0, step: 1
2070 11:52:11.415893
2071 11:52:11.419491 RX Delay -111 -> 252, step: 8
2072 11:52:11.422856 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2073 11:52:11.429609 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2074 11:52:11.433002 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2075 11:52:11.436080 iDelay=201, Bit 3, Center 76 (-39 ~ 192) 232
2076 11:52:11.439332 iDelay=201, Bit 4, Center 76 (-39 ~ 192) 232
2077 11:52:11.442497 iDelay=201, Bit 5, Center 88 (-23 ~ 200) 224
2078 11:52:11.446142 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2079 11:52:11.452629 iDelay=201, Bit 7, Center 76 (-39 ~ 192) 232
2080 11:52:11.456376 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2081 11:52:11.459756 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2082 11:52:11.462833 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2083 11:52:11.466115 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2084 11:52:11.472720 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2085 11:52:11.476308 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2086 11:52:11.479564 iDelay=201, Bit 14, Center 84 (-31 ~ 200) 232
2087 11:52:11.482913 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2088 11:52:11.482988 ==
2089 11:52:11.486712 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 11:52:11.493304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 11:52:11.493377 ==
2092 11:52:11.493439 DQS Delay:
2093 11:52:11.493498 DQS0 = 0, DQS1 = 0
2094 11:52:11.497066 DQM Delay:
2095 11:52:11.497134 DQM0 = 79, DQM1 = 75
2096 11:52:11.500358 DQ Delay:
2097 11:52:11.503265 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
2098 11:52:11.503334 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2099 11:52:11.506957 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2100 11:52:11.510113 DQ12 =80, DQ13 =84, DQ14 =84, DQ15 =84
2101 11:52:11.510183
2102 11:52:11.513629
2103 11:52:11.519932 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2104 11:52:11.523524 CH1 RK1: MR19=606, MR18=222D
2105 11:52:11.530250 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2106 11:52:11.530326 [RxdqsGatingPostProcess] freq 800
2107 11:52:11.536564 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2108 11:52:11.540202 Pre-setting of DQS Precalculation
2109 11:52:11.543906 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2110 11:52:11.553628 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2111 11:52:11.560112 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2112 11:52:11.560192
2113 11:52:11.560259
2114 11:52:11.563613 [Calibration Summary] 1600 Mbps
2115 11:52:11.563698 CH 0, Rank 0
2116 11:52:11.566949 SW Impedance : PASS
2117 11:52:11.567023 DUTY Scan : NO K
2118 11:52:11.570398 ZQ Calibration : PASS
2119 11:52:11.574000 Jitter Meter : NO K
2120 11:52:11.574070 CBT Training : PASS
2121 11:52:11.576699 Write leveling : PASS
2122 11:52:11.580279 RX DQS gating : PASS
2123 11:52:11.580358 RX DQ/DQS(RDDQC) : PASS
2124 11:52:11.583781 TX DQ/DQS : PASS
2125 11:52:11.587255 RX DATLAT : PASS
2126 11:52:11.587329 RX DQ/DQS(Engine): PASS
2127 11:52:11.590230 TX OE : NO K
2128 11:52:11.590297 All Pass.
2129 11:52:11.590355
2130 11:52:11.593727 CH 0, Rank 1
2131 11:52:11.593797 SW Impedance : PASS
2132 11:52:11.597122 DUTY Scan : NO K
2133 11:52:11.600484 ZQ Calibration : PASS
2134 11:52:11.600552 Jitter Meter : NO K
2135 11:52:11.603538 CBT Training : PASS
2136 11:52:11.603609 Write leveling : PASS
2137 11:52:11.607118 RX DQS gating : PASS
2138 11:52:11.610301 RX DQ/DQS(RDDQC) : PASS
2139 11:52:11.610374 TX DQ/DQS : PASS
2140 11:52:11.613793 RX DATLAT : PASS
2141 11:52:11.617281 RX DQ/DQS(Engine): PASS
2142 11:52:11.617349 TX OE : NO K
2143 11:52:11.620737 All Pass.
2144 11:52:11.620824
2145 11:52:11.620883 CH 1, Rank 0
2146 11:52:11.624024 SW Impedance : PASS
2147 11:52:11.624091 DUTY Scan : NO K
2148 11:52:11.627423 ZQ Calibration : PASS
2149 11:52:11.630596 Jitter Meter : NO K
2150 11:52:11.630687 CBT Training : PASS
2151 11:52:11.633899 Write leveling : PASS
2152 11:52:11.633968 RX DQS gating : PASS
2153 11:52:11.637568 RX DQ/DQS(RDDQC) : PASS
2154 11:52:11.640755 TX DQ/DQS : PASS
2155 11:52:11.640827 RX DATLAT : PASS
2156 11:52:11.644041 RX DQ/DQS(Engine): PASS
2157 11:52:11.647166 TX OE : NO K
2158 11:52:11.647271 All Pass.
2159 11:52:11.647333
2160 11:52:11.647391 CH 1, Rank 1
2161 11:52:11.650748 SW Impedance : PASS
2162 11:52:11.653972 DUTY Scan : NO K
2163 11:52:11.654046 ZQ Calibration : PASS
2164 11:52:11.657404 Jitter Meter : NO K
2165 11:52:11.661105 CBT Training : PASS
2166 11:52:11.661203 Write leveling : PASS
2167 11:52:11.663862 RX DQS gating : PASS
2168 11:52:11.663936 RX DQ/DQS(RDDQC) : PASS
2169 11:52:11.667477 TX DQ/DQS : PASS
2170 11:52:11.670814 RX DATLAT : PASS
2171 11:52:11.670957 RX DQ/DQS(Engine): PASS
2172 11:52:11.674489 TX OE : NO K
2173 11:52:11.674563 All Pass.
2174 11:52:11.674623
2175 11:52:11.677577 DramC Write-DBI off
2176 11:52:11.680734 PER_BANK_REFRESH: Hybrid Mode
2177 11:52:11.680807 TX_TRACKING: ON
2178 11:52:11.683985 [GetDramInforAfterCalByMRR] Vendor 6.
2179 11:52:11.687444 [GetDramInforAfterCalByMRR] Revision 606.
2180 11:52:11.690747 [GetDramInforAfterCalByMRR] Revision 2 0.
2181 11:52:11.694042 MR0 0x3b3b
2182 11:52:11.694150 MR8 0x5151
2183 11:52:11.697268 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2184 11:52:11.697365
2185 11:52:11.700810 MR0 0x3b3b
2186 11:52:11.700899 MR8 0x5151
2187 11:52:11.703995 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2188 11:52:11.704065
2189 11:52:11.714453 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2190 11:52:11.717369 [FAST_K] Save calibration result to emmc
2191 11:52:11.721156 [FAST_K] Save calibration result to emmc
2192 11:52:11.721305 dram_init: config_dvfs: 1
2193 11:52:11.728099 dramc_set_vcore_voltage set vcore to 662500
2194 11:52:11.728173 Read voltage for 1200, 2
2195 11:52:11.731342 Vio18 = 0
2196 11:52:11.731414 Vcore = 662500
2197 11:52:11.731474 Vdram = 0
2198 11:52:11.731531 Vddq = 0
2199 11:52:11.734921 Vmddr = 0
2200 11:52:11.737938 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2201 11:52:11.744353 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2202 11:52:11.747888 MEM_TYPE=3, freq_sel=15
2203 11:52:11.747964 sv_algorithm_assistance_LP4_1600
2204 11:52:11.754880 ============ PULL DRAM RESETB DOWN ============
2205 11:52:11.758226 ========== PULL DRAM RESETB DOWN end =========
2206 11:52:11.761557 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2207 11:52:11.765053 ===================================
2208 11:52:11.768508 LPDDR4 DRAM CONFIGURATION
2209 11:52:11.771579 ===================================
2210 11:52:11.774788 EX_ROW_EN[0] = 0x0
2211 11:52:11.774894 EX_ROW_EN[1] = 0x0
2212 11:52:11.778326 LP4Y_EN = 0x0
2213 11:52:11.778406 WORK_FSP = 0x0
2214 11:52:11.781361 WL = 0x4
2215 11:52:11.781431 RL = 0x4
2216 11:52:11.785111 BL = 0x2
2217 11:52:11.785189 RPST = 0x0
2218 11:52:11.788377 RD_PRE = 0x0
2219 11:52:11.788453 WR_PRE = 0x1
2220 11:52:11.791445 WR_PST = 0x0
2221 11:52:11.791519 DBI_WR = 0x0
2222 11:52:11.794961 DBI_RD = 0x0
2223 11:52:11.795032 OTF = 0x1
2224 11:52:11.798009 ===================================
2225 11:52:11.801596 ===================================
2226 11:52:11.805258 ANA top config
2227 11:52:11.808376 ===================================
2228 11:52:11.808447 DLL_ASYNC_EN = 0
2229 11:52:11.811860 ALL_SLAVE_EN = 0
2230 11:52:11.815268 NEW_RANK_MODE = 1
2231 11:52:11.818523 DLL_IDLE_MODE = 1
2232 11:52:11.818600 LP45_APHY_COMB_EN = 1
2233 11:52:11.821732 TX_ODT_DIS = 1
2234 11:52:11.825251 NEW_8X_MODE = 1
2235 11:52:11.828533 ===================================
2236 11:52:11.831988 ===================================
2237 11:52:11.834946 data_rate = 2400
2238 11:52:11.838451 CKR = 1
2239 11:52:11.842013 DQ_P2S_RATIO = 8
2240 11:52:11.842087 ===================================
2241 11:52:11.845036 CA_P2S_RATIO = 8
2242 11:52:11.848637 DQ_CA_OPEN = 0
2243 11:52:11.852142 DQ_SEMI_OPEN = 0
2244 11:52:11.855364 CA_SEMI_OPEN = 0
2245 11:52:11.858774 CA_FULL_RATE = 0
2246 11:52:11.858850 DQ_CKDIV4_EN = 0
2247 11:52:11.861772 CA_CKDIV4_EN = 0
2248 11:52:11.865549 CA_PREDIV_EN = 0
2249 11:52:11.868707 PH8_DLY = 17
2250 11:52:11.871870 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2251 11:52:11.875379 DQ_AAMCK_DIV = 4
2252 11:52:11.875457 CA_AAMCK_DIV = 4
2253 11:52:11.879054 CA_ADMCK_DIV = 4
2254 11:52:11.881984 DQ_TRACK_CA_EN = 0
2255 11:52:11.885619 CA_PICK = 1200
2256 11:52:11.889264 CA_MCKIO = 1200
2257 11:52:11.892205 MCKIO_SEMI = 0
2258 11:52:11.895589 PLL_FREQ = 2366
2259 11:52:11.895670 DQ_UI_PI_RATIO = 32
2260 11:52:11.899289 CA_UI_PI_RATIO = 0
2261 11:52:11.902132 ===================================
2262 11:52:11.905781 ===================================
2263 11:52:11.908992 memory_type:LPDDR4
2264 11:52:11.909069 GP_NUM : 10
2265 11:52:11.912313 SRAM_EN : 1
2266 11:52:11.916091 MD32_EN : 0
2267 11:52:11.918987 ===================================
2268 11:52:11.919060 [ANA_INIT] >>>>>>>>>>>>>>
2269 11:52:11.922313 <<<<<< [CONFIGURE PHASE]: ANA_TX
2270 11:52:11.925731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2271 11:52:11.929071 ===================================
2272 11:52:11.932538 data_rate = 2400,PCW = 0X5b00
2273 11:52:11.936004 ===================================
2274 11:52:11.939254 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2275 11:52:11.945720 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2276 11:52:11.949366 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2277 11:52:11.956179 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2278 11:52:11.959287 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2279 11:52:11.962715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2280 11:52:11.962827 [ANA_INIT] flow start
2281 11:52:11.966173 [ANA_INIT] PLL >>>>>>>>
2282 11:52:11.969435 [ANA_INIT] PLL <<<<<<<<
2283 11:52:11.969519 [ANA_INIT] MIDPI >>>>>>>>
2284 11:52:11.972985 [ANA_INIT] MIDPI <<<<<<<<
2285 11:52:11.976143 [ANA_INIT] DLL >>>>>>>>
2286 11:52:11.976221 [ANA_INIT] DLL <<<<<<<<
2287 11:52:11.979557 [ANA_INIT] flow end
2288 11:52:11.982842 ============ LP4 DIFF to SE enter ============
2289 11:52:11.989534 ============ LP4 DIFF to SE exit ============
2290 11:52:11.989617 [ANA_INIT] <<<<<<<<<<<<<
2291 11:52:11.993038 [Flow] Enable top DCM control >>>>>
2292 11:52:11.996066 [Flow] Enable top DCM control <<<<<
2293 11:52:11.999772 Enable DLL master slave shuffle
2294 11:52:12.006277 ==============================================================
2295 11:52:12.006357 Gating Mode config
2296 11:52:12.013430 ==============================================================
2297 11:52:12.013512 Config description:
2298 11:52:12.022967 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2299 11:52:12.030101 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2300 11:52:12.036783 SELPH_MODE 0: By rank 1: By Phase
2301 11:52:12.040026 ==============================================================
2302 11:52:12.043616 GAT_TRACK_EN = 1
2303 11:52:12.046684 RX_GATING_MODE = 2
2304 11:52:12.050053 RX_GATING_TRACK_MODE = 2
2305 11:52:12.053770 SELPH_MODE = 1
2306 11:52:12.057021 PICG_EARLY_EN = 1
2307 11:52:12.059991 VALID_LAT_VALUE = 1
2308 11:52:12.063670 ==============================================================
2309 11:52:12.067204 Enter into Gating configuration >>>>
2310 11:52:12.070298 Exit from Gating configuration <<<<
2311 11:52:12.073643 Enter into DVFS_PRE_config >>>>>
2312 11:52:12.086983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2313 11:52:12.087068 Exit from DVFS_PRE_config <<<<<
2314 11:52:12.090487 Enter into PICG configuration >>>>
2315 11:52:12.093524 Exit from PICG configuration <<<<
2316 11:52:12.096863 [RX_INPUT] configuration >>>>>
2317 11:52:12.100452 [RX_INPUT] configuration <<<<<
2318 11:52:12.107031 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2319 11:52:12.110466 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2320 11:52:12.117274 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2321 11:52:12.124477 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2322 11:52:12.131030 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2323 11:52:12.134050 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2324 11:52:12.141348 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2325 11:52:12.144356 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2326 11:52:12.147714 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2327 11:52:12.151299 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2328 11:52:12.157753 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2329 11:52:12.161154 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 11:52:12.164099 ===================================
2331 11:52:12.167645 LPDDR4 DRAM CONFIGURATION
2332 11:52:12.170885 ===================================
2333 11:52:12.170981 EX_ROW_EN[0] = 0x0
2334 11:52:12.174366 EX_ROW_EN[1] = 0x0
2335 11:52:12.174449 LP4Y_EN = 0x0
2336 11:52:12.177941 WORK_FSP = 0x0
2337 11:52:12.178027 WL = 0x4
2338 11:52:12.181027 RL = 0x4
2339 11:52:12.181101 BL = 0x2
2340 11:52:12.184388 RPST = 0x0
2341 11:52:12.184463 RD_PRE = 0x0
2342 11:52:12.187734 WR_PRE = 0x1
2343 11:52:12.187812 WR_PST = 0x0
2344 11:52:12.190942 DBI_WR = 0x0
2345 11:52:12.191023 DBI_RD = 0x0
2346 11:52:12.194481 OTF = 0x1
2347 11:52:12.197573 ===================================
2348 11:52:12.200978 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2349 11:52:12.204624 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2350 11:52:12.211245 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2351 11:52:12.214767 ===================================
2352 11:52:12.214870 LPDDR4 DRAM CONFIGURATION
2353 11:52:12.217936 ===================================
2354 11:52:12.221396 EX_ROW_EN[0] = 0x10
2355 11:52:12.224879 EX_ROW_EN[1] = 0x0
2356 11:52:12.224959 LP4Y_EN = 0x0
2357 11:52:12.228187 WORK_FSP = 0x0
2358 11:52:12.228253 WL = 0x4
2359 11:52:12.231099 RL = 0x4
2360 11:52:12.231170 BL = 0x2
2361 11:52:12.234753 RPST = 0x0
2362 11:52:12.234841 RD_PRE = 0x0
2363 11:52:12.238638 WR_PRE = 0x1
2364 11:52:12.238707 WR_PST = 0x0
2365 11:52:12.241440 DBI_WR = 0x0
2366 11:52:12.241512 DBI_RD = 0x0
2367 11:52:12.244990 OTF = 0x1
2368 11:52:12.248109 ===================================
2369 11:52:12.251844 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2370 11:52:12.255072 ==
2371 11:52:12.258235 Dram Type= 6, Freq= 0, CH_0, rank 0
2372 11:52:12.261524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 11:52:12.261596 ==
2374 11:52:12.264685 [Duty_Offset_Calibration]
2375 11:52:12.264763 B0:3 B1:-1 CA:1
2376 11:52:12.264825
2377 11:52:12.268001 [DutyScan_Calibration_Flow] k_type=0
2378 11:52:12.277126
2379 11:52:12.277205 ==CLK 0==
2380 11:52:12.280365 Final CLK duty delay cell = -4
2381 11:52:12.283821 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2382 11:52:12.286840 [-4] MIN Duty = 4875%(X100), DQS PI = 32
2383 11:52:12.290369 [-4] AVG Duty = 4953%(X100)
2384 11:52:12.290446
2385 11:52:12.293914 CH0 CLK Duty spec in!! Max-Min= 156%
2386 11:52:12.296860 [DutyScan_Calibration_Flow] ====Done====
2387 11:52:12.296948
2388 11:52:12.300167 [DutyScan_Calibration_Flow] k_type=1
2389 11:52:12.316030
2390 11:52:12.316109 ==DQS 0 ==
2391 11:52:12.319118 Final DQS duty delay cell = 0
2392 11:52:12.322777 [0] MAX Duty = 5125%(X100), DQS PI = 46
2393 11:52:12.326201 [0] MIN Duty = 5000%(X100), DQS PI = 12
2394 11:52:12.326280 [0] AVG Duty = 5062%(X100)
2395 11:52:12.329095
2396 11:52:12.329174 ==DQS 1 ==
2397 11:52:12.332875 Final DQS duty delay cell = -4
2398 11:52:12.336106 [-4] MAX Duty = 5124%(X100), DQS PI = 6
2399 11:52:12.339525 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2400 11:52:12.343120 [-4] AVG Duty = 5062%(X100)
2401 11:52:12.343230
2402 11:52:12.346267 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2403 11:52:12.346360
2404 11:52:12.349373 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2405 11:52:12.353024 [DutyScan_Calibration_Flow] ====Done====
2406 11:52:12.353117
2407 11:52:12.355964 [DutyScan_Calibration_Flow] k_type=3
2408 11:52:12.372488
2409 11:52:12.372564 ==DQM 0 ==
2410 11:52:12.376202 Final DQM duty delay cell = 0
2411 11:52:12.379693 [0] MAX Duty = 5031%(X100), DQS PI = 54
2412 11:52:12.382531 [0] MIN Duty = 4906%(X100), DQS PI = 2
2413 11:52:12.382598 [0] AVG Duty = 4968%(X100)
2414 11:52:12.386160
2415 11:52:12.386241 ==DQM 1 ==
2416 11:52:12.389289 Final DQM duty delay cell = 0
2417 11:52:12.392527 [0] MAX Duty = 5124%(X100), DQS PI = 32
2418 11:52:12.396288 [0] MIN Duty = 4969%(X100), DQS PI = 10
2419 11:52:12.396360 [0] AVG Duty = 5046%(X100)
2420 11:52:12.396424
2421 11:52:12.399859 CH0 DQM 0 Duty spec in!! Max-Min= 125%
2422 11:52:12.402986
2423 11:52:12.406737 CH0 DQM 1 Duty spec in!! Max-Min= 155%
2424 11:52:12.409862 [DutyScan_Calibration_Flow] ====Done====
2425 11:52:12.409936
2426 11:52:12.412651 [DutyScan_Calibration_Flow] k_type=2
2427 11:52:12.428709
2428 11:52:12.428792 ==DQ 0 ==
2429 11:52:12.431693 Final DQ duty delay cell = -4
2430 11:52:12.435017 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2431 11:52:12.438530 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2432 11:52:12.441674 [-4] AVG Duty = 4968%(X100)
2433 11:52:12.441752
2434 11:52:12.441813 ==DQ 1 ==
2435 11:52:12.445292 Final DQ duty delay cell = 0
2436 11:52:12.448699 [0] MAX Duty = 5031%(X100), DQS PI = 18
2437 11:52:12.452525 [0] MIN Duty = 4907%(X100), DQS PI = 46
2438 11:52:12.452599 [0] AVG Duty = 4969%(X100)
2439 11:52:12.452660
2440 11:52:12.455275 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2441 11:52:12.455347
2442 11:52:12.462387 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2443 11:52:12.465517 [DutyScan_Calibration_Flow] ====Done====
2444 11:52:12.465600 ==
2445 11:52:12.469107 Dram Type= 6, Freq= 0, CH_1, rank 0
2446 11:52:12.472159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2447 11:52:12.472236 ==
2448 11:52:12.475571 [Duty_Offset_Calibration]
2449 11:52:12.475643 B0:1 B1:1 CA:2
2450 11:52:12.475722
2451 11:52:12.478942 [DutyScan_Calibration_Flow] k_type=0
2452 11:52:12.489024
2453 11:52:12.489104 ==CLK 0==
2454 11:52:12.492164 Final CLK duty delay cell = 0
2455 11:52:12.495393 [0] MAX Duty = 5187%(X100), DQS PI = 24
2456 11:52:12.498881 [0] MIN Duty = 4938%(X100), DQS PI = 48
2457 11:52:12.498955 [0] AVG Duty = 5062%(X100)
2458 11:52:12.499035
2459 11:52:12.502165 CH1 CLK Duty spec in!! Max-Min= 249%
2460 11:52:12.508924 [DutyScan_Calibration_Flow] ====Done====
2461 11:52:12.509002
2462 11:52:12.511900 [DutyScan_Calibration_Flow] k_type=1
2463 11:52:12.528664
2464 11:52:12.528748 ==DQS 0 ==
2465 11:52:12.531119 Final DQS duty delay cell = 0
2466 11:52:12.534846 [0] MAX Duty = 5031%(X100), DQS PI = 18
2467 11:52:12.537923 [0] MIN Duty = 4813%(X100), DQS PI = 50
2468 11:52:12.537997 [0] AVG Duty = 4922%(X100)
2469 11:52:12.538077
2470 11:52:12.541269 ==DQS 1 ==
2471 11:52:12.544829 Final DQS duty delay cell = 0
2472 11:52:12.548376 [0] MAX Duty = 5062%(X100), DQS PI = 36
2473 11:52:12.551420 [0] MIN Duty = 4907%(X100), DQS PI = 14
2474 11:52:12.551494 [0] AVG Duty = 4984%(X100)
2475 11:52:12.551574
2476 11:52:12.558620 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2477 11:52:12.558698
2478 11:52:12.561701 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2479 11:52:12.565050 [DutyScan_Calibration_Flow] ====Done====
2480 11:52:12.565137
2481 11:52:12.568279 [DutyScan_Calibration_Flow] k_type=3
2482 11:52:12.584786
2483 11:52:12.584864 ==DQM 0 ==
2484 11:52:12.588285 Final DQM duty delay cell = 0
2485 11:52:12.591367 [0] MAX Duty = 5093%(X100), DQS PI = 18
2486 11:52:12.594669 [0] MIN Duty = 4875%(X100), DQS PI = 48
2487 11:52:12.594743 [0] AVG Duty = 4984%(X100)
2488 11:52:12.598061
2489 11:52:12.598138 ==DQM 1 ==
2490 11:52:12.602176 Final DQM duty delay cell = 0
2491 11:52:12.604538 [0] MAX Duty = 5156%(X100), DQS PI = 62
2492 11:52:12.608015 [0] MIN Duty = 4938%(X100), DQS PI = 22
2493 11:52:12.608088 [0] AVG Duty = 5047%(X100)
2494 11:52:12.608168
2495 11:52:12.614585 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2496 11:52:12.614664
2497 11:52:12.618192 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2498 11:52:12.621183 [DutyScan_Calibration_Flow] ====Done====
2499 11:52:12.621262
2500 11:52:12.624389 [DutyScan_Calibration_Flow] k_type=2
2501 11:52:12.640803
2502 11:52:12.640880 ==DQ 0 ==
2503 11:52:12.644722 Final DQ duty delay cell = 0
2504 11:52:12.647852 [0] MAX Duty = 5093%(X100), DQS PI = 18
2505 11:52:12.650855 [0] MIN Duty = 4907%(X100), DQS PI = 50
2506 11:52:12.650992 [0] AVG Duty = 5000%(X100)
2507 11:52:12.651096
2508 11:52:12.654362 ==DQ 1 ==
2509 11:52:12.657711 Final DQ duty delay cell = 0
2510 11:52:12.661431 [0] MAX Duty = 5093%(X100), DQS PI = 10
2511 11:52:12.664382 [0] MIN Duty = 5031%(X100), DQS PI = 2
2512 11:52:12.664492 [0] AVG Duty = 5062%(X100)
2513 11:52:12.664609
2514 11:52:12.667791 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2515 11:52:12.667864
2516 11:52:12.671519 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2517 11:52:12.674394 [DutyScan_Calibration_Flow] ====Done====
2518 11:52:12.679822 nWR fixed to 30
2519 11:52:12.683188 [ModeRegInit_LP4] CH0 RK0
2520 11:52:12.683281 [ModeRegInit_LP4] CH0 RK1
2521 11:52:12.686742 [ModeRegInit_LP4] CH1 RK0
2522 11:52:12.690279 [ModeRegInit_LP4] CH1 RK1
2523 11:52:12.690379 match AC timing 7
2524 11:52:12.696822 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2525 11:52:12.700223 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2526 11:52:12.703298 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2527 11:52:12.709959 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2528 11:52:12.713860 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2529 11:52:12.714013 ==
2530 11:52:12.716985 Dram Type= 6, Freq= 0, CH_0, rank 0
2531 11:52:12.720325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2532 11:52:12.720406 ==
2533 11:52:12.727413 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2534 11:52:12.733828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2535 11:52:12.741150 [CA 0] Center 40 (10~71) winsize 62
2536 11:52:12.744230 [CA 1] Center 39 (9~70) winsize 62
2537 11:52:12.747663 [CA 2] Center 36 (6~67) winsize 62
2538 11:52:12.751488 [CA 3] Center 36 (6~66) winsize 61
2539 11:52:12.754267 [CA 4] Center 34 (4~65) winsize 62
2540 11:52:12.757750 [CA 5] Center 34 (4~64) winsize 61
2541 11:52:12.757823
2542 11:52:12.761060 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2543 11:52:12.761138
2544 11:52:12.764145 [CATrainingPosCal] consider 1 rank data
2545 11:52:12.767992 u2DelayCellTimex100 = 270/100 ps
2546 11:52:12.771037 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2547 11:52:12.774711 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2548 11:52:12.781623 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2549 11:52:12.784569 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2550 11:52:12.787815 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2551 11:52:12.791475 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2552 11:52:12.791546
2553 11:52:12.795080 CA PerBit enable=1, Macro0, CA PI delay=34
2554 11:52:12.795154
2555 11:52:12.797962 [CBTSetCACLKResult] CA Dly = 34
2556 11:52:12.798035 CS Dly: 7 (0~38)
2557 11:52:12.798095 ==
2558 11:52:12.801537 Dram Type= 6, Freq= 0, CH_0, rank 1
2559 11:52:12.808052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2560 11:52:12.808128 ==
2561 11:52:12.811640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2562 11:52:12.818019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2563 11:52:12.827129 [CA 0] Center 39 (9~70) winsize 62
2564 11:52:12.830114 [CA 1] Center 39 (9~70) winsize 62
2565 11:52:12.833679 [CA 2] Center 36 (6~67) winsize 62
2566 11:52:12.837170 [CA 3] Center 36 (5~67) winsize 63
2567 11:52:12.840094 [CA 4] Center 34 (4~65) winsize 62
2568 11:52:12.843593 [CA 5] Center 34 (4~64) winsize 61
2569 11:52:12.843664
2570 11:52:12.846871 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2571 11:52:12.846976
2572 11:52:12.850710 [CATrainingPosCal] consider 2 rank data
2573 11:52:12.853682 u2DelayCellTimex100 = 270/100 ps
2574 11:52:12.857255 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2575 11:52:12.860580 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2576 11:52:12.863969 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2577 11:52:12.870394 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2578 11:52:12.874179 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2579 11:52:12.877419 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2580 11:52:12.877567
2581 11:52:12.880585 CA PerBit enable=1, Macro0, CA PI delay=34
2582 11:52:12.880660
2583 11:52:12.884100 [CBTSetCACLKResult] CA Dly = 34
2584 11:52:12.884185 CS Dly: 8 (0~41)
2585 11:52:12.884270
2586 11:52:12.887105 ----->DramcWriteLeveling(PI) begin...
2587 11:52:12.887186 ==
2588 11:52:12.890585 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 11:52:12.897615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 11:52:12.897693 ==
2591 11:52:12.900941 Write leveling (Byte 0): 30 => 30
2592 11:52:12.904449 Write leveling (Byte 1): 29 => 29
2593 11:52:12.904527 DramcWriteLeveling(PI) end<-----
2594 11:52:12.904608
2595 11:52:12.907305 ==
2596 11:52:12.907379 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 11:52:12.914321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 11:52:12.914414 ==
2599 11:52:12.917445 [Gating] SW mode calibration
2600 11:52:12.924563 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2601 11:52:12.927702 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2602 11:52:12.934101 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 11:52:12.937999 0 15 4 | B1->B0 | 2322 3030 | 1 0 | (0 0) (1 1)
2604 11:52:12.940920 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2605 11:52:12.944673 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2606 11:52:12.951053 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2607 11:52:12.954465 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:52:12.957849 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:52:12.964913 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 11:52:12.967897 1 0 0 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
2611 11:52:12.971379 1 0 4 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
2612 11:52:12.977696 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2613 11:52:12.981515 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2614 11:52:12.984695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2615 11:52:12.991667 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:52:12.994855 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:52:12.998385 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 11:52:13.001451 1 1 0 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
2619 11:52:13.008506 1 1 4 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
2620 11:52:13.011887 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2621 11:52:13.014763 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2622 11:52:13.022033 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2623 11:52:13.025407 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:52:13.028306 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:52:13.035346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:52:13.039055 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:52:13.042110 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2628 11:52:13.048680 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 11:52:13.052111 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 11:52:13.055192 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 11:52:13.058614 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:52:13.065763 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:52:13.069088 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:52:13.072534 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:52:13.079092 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:52:13.082079 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:52:13.085408 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:52:13.092234 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:52:13.096000 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:52:13.099159 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:52:13.105666 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:52:13.109191 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2643 11:52:13.112847 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2644 11:52:13.115821 Total UI for P1: 0, mck2ui 16
2645 11:52:13.119234 best dqsien dly found for B0: ( 1, 4, 0)
2646 11:52:13.122718 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2647 11:52:13.125809 Total UI for P1: 0, mck2ui 16
2648 11:52:13.129441 best dqsien dly found for B1: ( 1, 4, 2)
2649 11:52:13.133026 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2650 11:52:13.135769 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2651 11:52:13.135881
2652 11:52:13.142907 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2653 11:52:13.146597 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2654 11:52:13.146681 [Gating] SW calibration Done
2655 11:52:13.146746 ==
2656 11:52:13.149638 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 11:52:13.155964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 11:52:13.156051 ==
2659 11:52:13.156116 RX Vref Scan: 0
2660 11:52:13.156178
2661 11:52:13.159657 RX Vref 0 -> 0, step: 1
2662 11:52:13.159776
2663 11:52:13.162667 RX Delay -40 -> 252, step: 8
2664 11:52:13.166176 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2665 11:52:13.169701 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2666 11:52:13.172786 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2667 11:52:13.179591 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2668 11:52:13.183252 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2669 11:52:13.186035 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2670 11:52:13.189516 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2671 11:52:13.192705 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2672 11:52:13.196381 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2673 11:52:13.202777 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2674 11:52:13.206239 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2675 11:52:13.209698 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2676 11:52:13.213148 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2677 11:52:13.216612 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2678 11:52:13.223286 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2679 11:52:13.226338 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2680 11:52:13.226422 ==
2681 11:52:13.229901 Dram Type= 6, Freq= 0, CH_0, rank 0
2682 11:52:13.232895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2683 11:52:13.232979 ==
2684 11:52:13.236406 DQS Delay:
2685 11:52:13.236488 DQS0 = 0, DQS1 = 0
2686 11:52:13.236553 DQM Delay:
2687 11:52:13.239891 DQM0 = 116, DQM1 = 107
2688 11:52:13.239974 DQ Delay:
2689 11:52:13.242850 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
2690 11:52:13.246476 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
2691 11:52:13.250076 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2692 11:52:13.253504 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2693 11:52:13.253587
2694 11:52:13.256759
2695 11:52:13.256841 ==
2696 11:52:13.260259 Dram Type= 6, Freq= 0, CH_0, rank 0
2697 11:52:13.263063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2698 11:52:13.263149 ==
2699 11:52:13.263215
2700 11:52:13.263276
2701 11:52:13.266750 TX Vref Scan disable
2702 11:52:13.266834 == TX Byte 0 ==
2703 11:52:13.269927 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2704 11:52:13.276696 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2705 11:52:13.276779 == TX Byte 1 ==
2706 11:52:13.280185 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2707 11:52:13.287148 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2708 11:52:13.287262 ==
2709 11:52:13.290039 Dram Type= 6, Freq= 0, CH_0, rank 0
2710 11:52:13.293538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 11:52:13.293623 ==
2712 11:52:13.305250 TX Vref=22, minBit 1, minWin=25, winSum=419
2713 11:52:13.308640 TX Vref=24, minBit 1, minWin=26, winSum=428
2714 11:52:13.312274 TX Vref=26, minBit 0, minWin=26, winSum=428
2715 11:52:13.315941 TX Vref=28, minBit 1, minWin=26, winSum=431
2716 11:52:13.318874 TX Vref=30, minBit 4, minWin=26, winSum=436
2717 11:52:13.322526 TX Vref=32, minBit 0, minWin=26, winSum=431
2718 11:52:13.329050 [TxChooseVref] Worse bit 4, Min win 26, Win sum 436, Final Vref 30
2719 11:52:13.329132
2720 11:52:13.332434 Final TX Range 1 Vref 30
2721 11:52:13.332571
2722 11:52:13.332638 ==
2723 11:52:13.335891 Dram Type= 6, Freq= 0, CH_0, rank 0
2724 11:52:13.338719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2725 11:52:13.338829 ==
2726 11:52:13.338917
2727 11:52:13.338979
2728 11:52:13.342240 TX Vref Scan disable
2729 11:52:13.345847 == TX Byte 0 ==
2730 11:52:13.349663 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2731 11:52:13.352249 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2732 11:52:13.355941 == TX Byte 1 ==
2733 11:52:13.359097 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2734 11:52:13.362667 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2735 11:52:13.362750
2736 11:52:13.366139 [DATLAT]
2737 11:52:13.366222 Freq=1200, CH0 RK0
2738 11:52:13.366287
2739 11:52:13.369457 DATLAT Default: 0xd
2740 11:52:13.369540 0, 0xFFFF, sum = 0
2741 11:52:13.372492 1, 0xFFFF, sum = 0
2742 11:52:13.372574 2, 0xFFFF, sum = 0
2743 11:52:13.376004 3, 0xFFFF, sum = 0
2744 11:52:13.376085 4, 0xFFFF, sum = 0
2745 11:52:13.379508 5, 0xFFFF, sum = 0
2746 11:52:13.379590 6, 0xFFFF, sum = 0
2747 11:52:13.383053 7, 0xFFFF, sum = 0
2748 11:52:13.383136 8, 0xFFFF, sum = 0
2749 11:52:13.386427 9, 0xFFFF, sum = 0
2750 11:52:13.386508 10, 0xFFFF, sum = 0
2751 11:52:13.389491 11, 0xFFFF, sum = 0
2752 11:52:13.389591 12, 0x0, sum = 1
2753 11:52:13.393175 13, 0x0, sum = 2
2754 11:52:13.393256 14, 0x0, sum = 3
2755 11:52:13.396361 15, 0x0, sum = 4
2756 11:52:13.396443 best_step = 13
2757 11:52:13.396556
2758 11:52:13.396711 ==
2759 11:52:13.399263 Dram Type= 6, Freq= 0, CH_0, rank 0
2760 11:52:13.403031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2761 11:52:13.406614 ==
2762 11:52:13.406694 RX Vref Scan: 1
2763 11:52:13.406757
2764 11:52:13.409391 Set Vref Range= 32 -> 127
2765 11:52:13.409471
2766 11:52:13.409533 RX Vref 32 -> 127, step: 1
2767 11:52:13.413303
2768 11:52:13.413383 RX Delay -21 -> 252, step: 4
2769 11:52:13.413446
2770 11:52:13.416385 Set Vref, RX VrefLevel [Byte0]: 32
2771 11:52:13.419405 [Byte1]: 32
2772 11:52:13.423683
2773 11:52:13.423765 Set Vref, RX VrefLevel [Byte0]: 33
2774 11:52:13.426768 [Byte1]: 33
2775 11:52:13.431635
2776 11:52:13.431718 Set Vref, RX VrefLevel [Byte0]: 34
2777 11:52:13.435143 [Byte1]: 34
2778 11:52:13.439614
2779 11:52:13.439696 Set Vref, RX VrefLevel [Byte0]: 35
2780 11:52:13.442780 [Byte1]: 35
2781 11:52:13.447388
2782 11:52:13.447470 Set Vref, RX VrefLevel [Byte0]: 36
2783 11:52:13.450648 [Byte1]: 36
2784 11:52:13.455347
2785 11:52:13.455430 Set Vref, RX VrefLevel [Byte0]: 37
2786 11:52:13.458965 [Byte1]: 37
2787 11:52:13.463508
2788 11:52:13.463590 Set Vref, RX VrefLevel [Byte0]: 38
2789 11:52:13.466435 [Byte1]: 38
2790 11:52:13.471106
2791 11:52:13.471188 Set Vref, RX VrefLevel [Byte0]: 39
2792 11:52:13.474723 [Byte1]: 39
2793 11:52:13.479367
2794 11:52:13.479449 Set Vref, RX VrefLevel [Byte0]: 40
2795 11:52:13.482755 [Byte1]: 40
2796 11:52:13.486756
2797 11:52:13.486873 Set Vref, RX VrefLevel [Byte0]: 41
2798 11:52:13.490507 [Byte1]: 41
2799 11:52:13.495107
2800 11:52:13.495189 Set Vref, RX VrefLevel [Byte0]: 42
2801 11:52:13.498015 [Byte1]: 42
2802 11:52:13.502973
2803 11:52:13.503056 Set Vref, RX VrefLevel [Byte0]: 43
2804 11:52:13.506202 [Byte1]: 43
2805 11:52:13.510993
2806 11:52:13.511079 Set Vref, RX VrefLevel [Byte0]: 44
2807 11:52:13.513888 [Byte1]: 44
2808 11:52:13.518677
2809 11:52:13.518786 Set Vref, RX VrefLevel [Byte0]: 45
2810 11:52:13.522178 [Byte1]: 45
2811 11:52:13.526739
2812 11:52:13.526868 Set Vref, RX VrefLevel [Byte0]: 46
2813 11:52:13.530061 [Byte1]: 46
2814 11:52:13.534772
2815 11:52:13.534904 Set Vref, RX VrefLevel [Byte0]: 47
2816 11:52:13.537921 [Byte1]: 47
2817 11:52:13.542627
2818 11:52:13.545518 Set Vref, RX VrefLevel [Byte0]: 48
2819 11:52:13.545599 [Byte1]: 48
2820 11:52:13.550235
2821 11:52:13.550348 Set Vref, RX VrefLevel [Byte0]: 49
2822 11:52:13.553957 [Byte1]: 49
2823 11:52:13.558251
2824 11:52:13.558357 Set Vref, RX VrefLevel [Byte0]: 50
2825 11:52:13.561873 [Byte1]: 50
2826 11:52:13.566117
2827 11:52:13.566233 Set Vref, RX VrefLevel [Byte0]: 51
2828 11:52:13.569731 [Byte1]: 51
2829 11:52:13.573923
2830 11:52:13.574027 Set Vref, RX VrefLevel [Byte0]: 52
2831 11:52:13.577268 [Byte1]: 52
2832 11:52:13.582049
2833 11:52:13.582131 Set Vref, RX VrefLevel [Byte0]: 53
2834 11:52:13.585672 [Byte1]: 53
2835 11:52:13.589970
2836 11:52:13.590046 Set Vref, RX VrefLevel [Byte0]: 54
2837 11:52:13.593547 [Byte1]: 54
2838 11:52:13.597709
2839 11:52:13.597821 Set Vref, RX VrefLevel [Byte0]: 55
2840 11:52:13.601328 [Byte1]: 55
2841 11:52:13.606077
2842 11:52:13.606163 Set Vref, RX VrefLevel [Byte0]: 56
2843 11:52:13.609474 [Byte1]: 56
2844 11:52:13.613825
2845 11:52:13.613899 Set Vref, RX VrefLevel [Byte0]: 57
2846 11:52:13.617123 [Byte1]: 57
2847 11:52:13.621959
2848 11:52:13.622034 Set Vref, RX VrefLevel [Byte0]: 58
2849 11:52:13.625568 [Byte1]: 58
2850 11:52:13.629530
2851 11:52:13.629608 Set Vref, RX VrefLevel [Byte0]: 59
2852 11:52:13.633057 [Byte1]: 59
2853 11:52:13.637580
2854 11:52:13.637651 Set Vref, RX VrefLevel [Byte0]: 60
2855 11:52:13.640856 [Byte1]: 60
2856 11:52:13.645749
2857 11:52:13.645823 Set Vref, RX VrefLevel [Byte0]: 61
2858 11:52:13.649051 [Byte1]: 61
2859 11:52:13.653644
2860 11:52:13.653773 Set Vref, RX VrefLevel [Byte0]: 62
2861 11:52:13.656608 [Byte1]: 62
2862 11:52:13.661335
2863 11:52:13.661408 Set Vref, RX VrefLevel [Byte0]: 63
2864 11:52:13.664848 [Byte1]: 63
2865 11:52:13.669285
2866 11:52:13.669388 Set Vref, RX VrefLevel [Byte0]: 64
2867 11:52:13.672476 [Byte1]: 64
2868 11:52:13.677075
2869 11:52:13.677174 Set Vref, RX VrefLevel [Byte0]: 65
2870 11:52:13.680625 [Byte1]: 65
2871 11:52:13.685531
2872 11:52:13.685614 Set Vref, RX VrefLevel [Byte0]: 66
2873 11:52:13.688581 [Byte1]: 66
2874 11:52:13.693404
2875 11:52:13.693484 Set Vref, RX VrefLevel [Byte0]: 67
2876 11:52:13.696427 [Byte1]: 67
2877 11:52:13.701019
2878 11:52:13.701121 Set Vref, RX VrefLevel [Byte0]: 68
2879 11:52:13.704575 [Byte1]: 68
2880 11:52:13.709343
2881 11:52:13.709448 Final RX Vref Byte 0 = 55 to rank0
2882 11:52:13.713089 Final RX Vref Byte 1 = 50 to rank0
2883 11:52:13.715643 Final RX Vref Byte 0 = 55 to rank1
2884 11:52:13.719445 Final RX Vref Byte 1 = 50 to rank1==
2885 11:52:13.722326 Dram Type= 6, Freq= 0, CH_0, rank 0
2886 11:52:13.725934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 11:52:13.729696 ==
2888 11:52:13.729776 DQS Delay:
2889 11:52:13.729840 DQS0 = 0, DQS1 = 0
2890 11:52:13.732454 DQM Delay:
2891 11:52:13.732534 DQM0 = 114, DQM1 = 104
2892 11:52:13.735832 DQ Delay:
2893 11:52:13.739574 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =112
2894 11:52:13.742553 DQ4 =116, DQ5 =108, DQ6 =120, DQ7 =122
2895 11:52:13.746168 DQ8 =92, DQ9 =90, DQ10 =106, DQ11 =96
2896 11:52:13.749421 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =114
2897 11:52:13.749501
2898 11:52:13.749563
2899 11:52:13.755731 [DQSOSCAuto] RK0, (LSB)MR18= 0xfceb, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 411 ps
2900 11:52:13.759266 CH0 RK0: MR19=303, MR18=FCEB
2901 11:52:13.766034 CH0_RK0: MR19=0x303, MR18=0xFCEB, DQSOSC=411, MR23=63, INC=38, DEC=25
2902 11:52:13.766118
2903 11:52:13.769421 ----->DramcWriteLeveling(PI) begin...
2904 11:52:13.769503 ==
2905 11:52:13.772462 Dram Type= 6, Freq= 0, CH_0, rank 1
2906 11:52:13.775835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2907 11:52:13.775916 ==
2908 11:52:13.779666 Write leveling (Byte 0): 32 => 32
2909 11:52:13.783108 Write leveling (Byte 1): 28 => 28
2910 11:52:13.786392 DramcWriteLeveling(PI) end<-----
2911 11:52:13.786473
2912 11:52:13.786574 ==
2913 11:52:13.789662 Dram Type= 6, Freq= 0, CH_0, rank 1
2914 11:52:13.792864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2915 11:52:13.792964 ==
2916 11:52:13.796106 [Gating] SW mode calibration
2917 11:52:13.803258 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2918 11:52:13.809719 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2919 11:52:13.813028 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
2920 11:52:13.816346 0 15 4 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
2921 11:52:13.823401 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 11:52:13.826251 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2923 11:52:13.829905 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2924 11:52:13.836425 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2925 11:52:13.839895 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2926 11:52:13.843330 0 15 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
2927 11:52:13.850420 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2928 11:52:13.853806 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2929 11:52:13.857257 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2930 11:52:13.863835 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2931 11:52:13.866654 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2932 11:52:13.869852 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2933 11:52:13.876521 1 0 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
2934 11:52:13.880094 1 0 28 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
2935 11:52:13.883474 1 1 0 | B1->B0 | 2a2a 3939 | 0 0 | (0 0) (1 1)
2936 11:52:13.887019 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 11:52:13.893421 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 11:52:13.896917 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2939 11:52:13.900164 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2940 11:52:13.906780 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2941 11:52:13.910221 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2942 11:52:13.913798 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2943 11:52:13.920773 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2944 11:52:13.923858 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 11:52:13.927252 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 11:52:13.934044 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 11:52:13.937146 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 11:52:13.940716 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 11:52:13.944199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 11:52:13.950609 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 11:52:13.954158 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 11:52:13.957544 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 11:52:13.964320 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 11:52:13.967374 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 11:52:13.971013 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 11:52:13.977693 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 11:52:13.981271 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 11:52:13.984183 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2959 11:52:13.991342 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2960 11:52:13.991425 Total UI for P1: 0, mck2ui 16
2961 11:52:13.994308 best dqsien dly found for B0: ( 1, 3, 28)
2962 11:52:14.000934 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2963 11:52:14.004439 Total UI for P1: 0, mck2ui 16
2964 11:52:14.008005 best dqsien dly found for B1: ( 1, 3, 30)
2965 11:52:14.011443 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2966 11:52:14.014810 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2967 11:52:14.014926
2968 11:52:14.018213 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2969 11:52:14.021328 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2970 11:52:14.024650 [Gating] SW calibration Done
2971 11:52:14.024721 ==
2972 11:52:14.027859 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 11:52:14.031299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 11:52:14.031371 ==
2975 11:52:14.034631 RX Vref Scan: 0
2976 11:52:14.034698
2977 11:52:14.034755 RX Vref 0 -> 0, step: 1
2978 11:52:14.034811
2979 11:52:14.038361 RX Delay -40 -> 252, step: 8
2980 11:52:14.041853 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2981 11:52:14.048070 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2982 11:52:14.051516 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2983 11:52:14.055153 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2984 11:52:14.058777 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2985 11:52:14.061521 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2986 11:52:14.065034 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2987 11:52:14.072047 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2988 11:52:14.075047 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2989 11:52:14.078497 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2990 11:52:14.081965 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2991 11:52:14.085121 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2992 11:52:14.092363 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2993 11:52:14.095535 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2994 11:52:14.098464 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2995 11:52:14.102072 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2996 11:52:14.102152 ==
2997 11:52:14.104998 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 11:52:14.108853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 11:52:14.111855 ==
3000 11:52:14.111936 DQS Delay:
3001 11:52:14.112001 DQS0 = 0, DQS1 = 0
3002 11:52:14.115474 DQM Delay:
3003 11:52:14.115556 DQM0 = 116, DQM1 = 106
3004 11:52:14.118732 DQ Delay:
3005 11:52:14.121780 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =115
3006 11:52:14.125958 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
3007 11:52:14.128621 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =95
3008 11:52:14.131929 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
3009 11:52:14.132034
3010 11:52:14.132112
3011 11:52:14.132171 ==
3012 11:52:14.135601 Dram Type= 6, Freq= 0, CH_0, rank 1
3013 11:52:14.138774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3014 11:52:14.138898 ==
3015 11:52:14.138963
3016 11:52:14.139023
3017 11:52:14.141998 TX Vref Scan disable
3018 11:52:14.145462 == TX Byte 0 ==
3019 11:52:14.148644 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3020 11:52:14.152054 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3021 11:52:14.155499 == TX Byte 1 ==
3022 11:52:14.158921 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3023 11:52:14.162143 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3024 11:52:14.162216 ==
3025 11:52:14.165403 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 11:52:14.168952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 11:52:14.172106 ==
3028 11:52:14.182643 TX Vref=22, minBit 0, minWin=26, winSum=426
3029 11:52:14.185749 TX Vref=24, minBit 0, minWin=26, winSum=431
3030 11:52:14.189470 TX Vref=26, minBit 6, minWin=26, winSum=436
3031 11:52:14.192258 TX Vref=28, minBit 3, minWin=26, winSum=437
3032 11:52:14.195769 TX Vref=30, minBit 0, minWin=27, winSum=442
3033 11:52:14.199622 TX Vref=32, minBit 0, minWin=27, winSum=439
3034 11:52:14.206048 [TxChooseVref] Worse bit 0, Min win 27, Win sum 442, Final Vref 30
3035 11:52:14.206149
3036 11:52:14.209115 Final TX Range 1 Vref 30
3037 11:52:14.209185
3038 11:52:14.209245 ==
3039 11:52:14.212593 Dram Type= 6, Freq= 0, CH_0, rank 1
3040 11:52:14.216214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3041 11:52:14.216286 ==
3042 11:52:14.216347
3043 11:52:14.216404
3044 11:52:14.219712 TX Vref Scan disable
3045 11:52:14.222625 == TX Byte 0 ==
3046 11:52:14.226216 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3047 11:52:14.229358 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3048 11:52:14.232706 == TX Byte 1 ==
3049 11:52:14.236121 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3050 11:52:14.239404 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3051 11:52:14.239518
3052 11:52:14.242509 [DATLAT]
3053 11:52:14.242589 Freq=1200, CH0 RK1
3054 11:52:14.242652
3055 11:52:14.246137 DATLAT Default: 0xd
3056 11:52:14.246228 0, 0xFFFF, sum = 0
3057 11:52:14.249125 1, 0xFFFF, sum = 0
3058 11:52:14.249213 2, 0xFFFF, sum = 0
3059 11:52:14.253012 3, 0xFFFF, sum = 0
3060 11:52:14.253094 4, 0xFFFF, sum = 0
3061 11:52:14.256397 5, 0xFFFF, sum = 0
3062 11:52:14.256506 6, 0xFFFF, sum = 0
3063 11:52:14.259811 7, 0xFFFF, sum = 0
3064 11:52:14.259893 8, 0xFFFF, sum = 0
3065 11:52:14.262999 9, 0xFFFF, sum = 0
3066 11:52:14.263072 10, 0xFFFF, sum = 0
3067 11:52:14.266442 11, 0xFFFF, sum = 0
3068 11:52:14.266515 12, 0x0, sum = 1
3069 11:52:14.269819 13, 0x0, sum = 2
3070 11:52:14.270003 14, 0x0, sum = 3
3071 11:52:14.272910 15, 0x0, sum = 4
3072 11:52:14.273011 best_step = 13
3073 11:52:14.273100
3074 11:52:14.273186 ==
3075 11:52:14.276753 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 11:52:14.279922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 11:52:14.283394 ==
3078 11:52:14.283468 RX Vref Scan: 0
3079 11:52:14.283536
3080 11:52:14.286679 RX Vref 0 -> 0, step: 1
3081 11:52:14.286774
3082 11:52:14.290017 RX Delay -21 -> 252, step: 4
3083 11:52:14.293534 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3084 11:52:14.296360 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3085 11:52:14.299797 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3086 11:52:14.306713 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3087 11:52:14.310037 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3088 11:52:14.313634 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3089 11:52:14.316576 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3090 11:52:14.319952 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3091 11:52:14.323641 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3092 11:52:14.330105 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3093 11:52:14.333258 iDelay=195, Bit 10, Center 106 (39 ~ 174) 136
3094 11:52:14.336948 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3095 11:52:14.340230 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3096 11:52:14.343767 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3097 11:52:14.350865 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3098 11:52:14.353522 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3099 11:52:14.353598 ==
3100 11:52:14.357537 Dram Type= 6, Freq= 0, CH_0, rank 1
3101 11:52:14.360440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 11:52:14.360513 ==
3103 11:52:14.363794 DQS Delay:
3104 11:52:14.363866 DQS0 = 0, DQS1 = 0
3105 11:52:14.363925 DQM Delay:
3106 11:52:14.366854 DQM0 = 114, DQM1 = 104
3107 11:52:14.366970 DQ Delay:
3108 11:52:14.370533 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3109 11:52:14.374033 DQ4 =112, DQ5 =106, DQ6 =122, DQ7 =122
3110 11:52:14.377227 DQ8 =94, DQ9 =92, DQ10 =106, DQ11 =94
3111 11:52:14.380229 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =112
3112 11:52:14.380303
3113 11:52:14.383698
3114 11:52:14.390644 [DQSOSCAuto] RK1, (LSB)MR18= 0x5f6, (MSB)MR19= 0x403, tDQSOscB0 = 414 ps tDQSOscB1 = 408 ps
3115 11:52:14.393956 CH0 RK1: MR19=403, MR18=5F6
3116 11:52:14.397079 CH0_RK1: MR19=0x403, MR18=0x5F6, DQSOSC=408, MR23=63, INC=39, DEC=26
3117 11:52:14.400776 [RxdqsGatingPostProcess] freq 1200
3118 11:52:14.407062 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3119 11:52:14.410625 best DQS0 dly(2T, 0.5T) = (0, 12)
3120 11:52:14.414154 best DQS1 dly(2T, 0.5T) = (0, 12)
3121 11:52:14.417233 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3122 11:52:14.420966 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3123 11:52:14.424208 best DQS0 dly(2T, 0.5T) = (0, 11)
3124 11:52:14.427659 best DQS1 dly(2T, 0.5T) = (0, 11)
3125 11:52:14.430561 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3126 11:52:14.434273 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3127 11:52:14.434385 Pre-setting of DQS Precalculation
3128 11:52:14.440934 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3129 11:52:14.441044 ==
3130 11:52:14.444224 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 11:52:14.447814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 11:52:14.447891 ==
3133 11:52:14.454083 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 11:52:14.460903 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 11:52:14.468007 [CA 0] Center 38 (8~68) winsize 61
3136 11:52:14.471563 [CA 1] Center 38 (8~68) winsize 61
3137 11:52:14.474555 [CA 2] Center 35 (5~65) winsize 61
3138 11:52:14.478025 [CA 3] Center 34 (4~65) winsize 62
3139 11:52:14.481549 [CA 4] Center 34 (4~65) winsize 62
3140 11:52:14.484977 [CA 5] Center 34 (4~64) winsize 61
3141 11:52:14.485078
3142 11:52:14.488157 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3143 11:52:14.488271
3144 11:52:14.491605 [CATrainingPosCal] consider 1 rank data
3145 11:52:14.495159 u2DelayCellTimex100 = 270/100 ps
3146 11:52:14.498401 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3147 11:52:14.501848 CA1 delay=38 (8~68),Diff = 4 PI (19 cell)
3148 11:52:14.505019 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3149 11:52:14.508655 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
3150 11:52:14.515215 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3151 11:52:14.518661 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3152 11:52:14.518762
3153 11:52:14.521814 CA PerBit enable=1, Macro0, CA PI delay=34
3154 11:52:14.521912
3155 11:52:14.525082 [CBTSetCACLKResult] CA Dly = 34
3156 11:52:14.525180 CS Dly: 6 (0~37)
3157 11:52:14.525269 ==
3158 11:52:14.528745 Dram Type= 6, Freq= 0, CH_1, rank 1
3159 11:52:14.531825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3160 11:52:14.535295 ==
3161 11:52:14.538731 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3162 11:52:14.545295 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3163 11:52:14.553931 [CA 0] Center 38 (8~68) winsize 61
3164 11:52:14.556862 [CA 1] Center 38 (8~68) winsize 61
3165 11:52:14.560470 [CA 2] Center 35 (5~65) winsize 61
3166 11:52:14.564049 [CA 3] Center 34 (4~65) winsize 62
3167 11:52:14.567009 [CA 4] Center 34 (4~65) winsize 62
3168 11:52:14.570540 [CA 5] Center 33 (3~63) winsize 61
3169 11:52:14.570646
3170 11:52:14.573784 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3171 11:52:14.573888
3172 11:52:14.577256 [CATrainingPosCal] consider 2 rank data
3173 11:52:14.580845 u2DelayCellTimex100 = 270/100 ps
3174 11:52:14.583634 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3175 11:52:14.586994 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3176 11:52:14.590631 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3177 11:52:14.597129 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3178 11:52:14.600526 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3179 11:52:14.604055 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3180 11:52:14.604160
3181 11:52:14.607657 CA PerBit enable=1, Macro0, CA PI delay=33
3182 11:52:14.607769
3183 11:52:14.610621 [CBTSetCACLKResult] CA Dly = 33
3184 11:52:14.610722 CS Dly: 7 (0~40)
3185 11:52:14.610812
3186 11:52:14.614408 ----->DramcWriteLeveling(PI) begin...
3187 11:52:14.614514 ==
3188 11:52:14.617229 Dram Type= 6, Freq= 0, CH_1, rank 0
3189 11:52:14.624189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3190 11:52:14.624297 ==
3191 11:52:14.627649 Write leveling (Byte 0): 24 => 24
3192 11:52:14.627732 Write leveling (Byte 1): 31 => 31
3193 11:52:14.630637 DramcWriteLeveling(PI) end<-----
3194 11:52:14.630735
3195 11:52:14.634180 ==
3196 11:52:14.634279 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:52:14.640963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:52:14.641038 ==
3199 11:52:14.644516 [Gating] SW mode calibration
3200 11:52:14.650777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3201 11:52:14.654404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3202 11:52:14.661137 0 15 0 | B1->B0 | 2929 2727 | 1 0 | (0 0) (0 0)
3203 11:52:14.664322 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3204 11:52:14.667792 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3205 11:52:14.670922 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3206 11:52:14.677459 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3207 11:52:14.681258 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
3208 11:52:14.684460 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3209 11:52:14.691123 0 15 28 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
3210 11:52:14.694500 1 0 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3211 11:52:14.698030 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 11:52:14.704725 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3213 11:52:14.707861 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3214 11:52:14.711721 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3215 11:52:14.718067 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3216 11:52:14.721309 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 11:52:14.724750 1 0 28 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
3218 11:52:14.731326 1 1 0 | B1->B0 | 4444 3535 | 0 1 | (0 0) (0 0)
3219 11:52:14.735078 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 11:52:14.737954 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 11:52:14.741392 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3222 11:52:14.748462 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3223 11:52:14.751690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:52:14.755299 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 11:52:14.762126 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 11:52:14.764916 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3227 11:52:14.768496 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 11:52:14.774986 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 11:52:14.778654 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 11:52:14.781752 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 11:52:14.788623 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 11:52:14.791711 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 11:52:14.795295 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 11:52:14.798716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 11:52:14.805322 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 11:52:14.808982 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 11:52:14.812011 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 11:52:14.818697 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 11:52:14.821873 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 11:52:14.825364 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 11:52:14.832391 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3242 11:52:14.835770 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3243 11:52:14.839054 Total UI for P1: 0, mck2ui 16
3244 11:52:14.842040 best dqsien dly found for B1: ( 1, 3, 30)
3245 11:52:14.845976 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3246 11:52:14.849135 Total UI for P1: 0, mck2ui 16
3247 11:52:14.852474 best dqsien dly found for B0: ( 1, 3, 30)
3248 11:52:14.856006 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3249 11:52:14.858992 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3250 11:52:14.859091
3251 11:52:14.862405 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3252 11:52:14.865951 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3253 11:52:14.869096 [Gating] SW calibration Done
3254 11:52:14.869199 ==
3255 11:52:14.872547 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 11:52:14.879095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 11:52:14.879176 ==
3258 11:52:14.879241 RX Vref Scan: 0
3259 11:52:14.879300
3260 11:52:14.882571 RX Vref 0 -> 0, step: 1
3261 11:52:14.882662
3262 11:52:14.886061 RX Delay -40 -> 252, step: 8
3263 11:52:14.889061 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3264 11:52:14.893054 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3265 11:52:14.896164 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3266 11:52:14.899323 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3267 11:52:14.906214 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3268 11:52:14.909241 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3269 11:52:14.912774 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3270 11:52:14.916303 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3271 11:52:14.919701 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3272 11:52:14.923328 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3273 11:52:14.929331 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3274 11:52:14.933292 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3275 11:52:14.936383 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3276 11:52:14.939890 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3277 11:52:14.943119 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3278 11:52:14.949799 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3279 11:52:14.949876 ==
3280 11:52:14.953271 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 11:52:14.956679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 11:52:14.956780 ==
3283 11:52:14.956870 DQS Delay:
3284 11:52:14.959951 DQS0 = 0, DQS1 = 0
3285 11:52:14.960066 DQM Delay:
3286 11:52:14.963043 DQM0 = 115, DQM1 = 108
3287 11:52:14.963113 DQ Delay:
3288 11:52:14.966426 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3289 11:52:14.969757 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3290 11:52:14.973545 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3291 11:52:14.976346 DQ12 =119, DQ13 =115, DQ14 =111, DQ15 =111
3292 11:52:14.976423
3293 11:52:14.976490
3294 11:52:14.976580 ==
3295 11:52:14.980012 Dram Type= 6, Freq= 0, CH_1, rank 0
3296 11:52:14.986525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3297 11:52:14.986628 ==
3298 11:52:14.986717
3299 11:52:14.986803
3300 11:52:14.986910 TX Vref Scan disable
3301 11:52:14.990051 == TX Byte 0 ==
3302 11:52:14.993622 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3303 11:52:14.997140 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3304 11:52:15.000248 == TX Byte 1 ==
3305 11:52:15.003653 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3306 11:52:15.007132 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3307 11:52:15.010158 ==
3308 11:52:15.013456 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 11:52:15.016770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 11:52:15.016871 ==
3311 11:52:15.028610 TX Vref=22, minBit 1, minWin=24, winSum=407
3312 11:52:15.031903 TX Vref=24, minBit 4, minWin=25, winSum=414
3313 11:52:15.034965 TX Vref=26, minBit 11, minWin=25, winSum=418
3314 11:52:15.038713 TX Vref=28, minBit 0, minWin=26, winSum=426
3315 11:52:15.042449 TX Vref=30, minBit 13, minWin=25, winSum=424
3316 11:52:15.045104 TX Vref=32, minBit 15, minWin=25, winSum=429
3317 11:52:15.052059 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
3318 11:52:15.052136
3319 11:52:15.055642 Final TX Range 1 Vref 28
3320 11:52:15.055799
3321 11:52:15.055892 ==
3322 11:52:15.058979 Dram Type= 6, Freq= 0, CH_1, rank 0
3323 11:52:15.062128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3324 11:52:15.062235 ==
3325 11:52:15.062335
3326 11:52:15.062434
3327 11:52:15.065563 TX Vref Scan disable
3328 11:52:15.068991 == TX Byte 0 ==
3329 11:52:15.072509 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3330 11:52:15.075570 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3331 11:52:15.078962 == TX Byte 1 ==
3332 11:52:15.082478 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3333 11:52:15.085792 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3334 11:52:15.085890
3335 11:52:15.089066 [DATLAT]
3336 11:52:15.089164 Freq=1200, CH1 RK0
3337 11:52:15.089256
3338 11:52:15.092619 DATLAT Default: 0xd
3339 11:52:15.092718 0, 0xFFFF, sum = 0
3340 11:52:15.095622 1, 0xFFFF, sum = 0
3341 11:52:15.095721 2, 0xFFFF, sum = 0
3342 11:52:15.099123 3, 0xFFFF, sum = 0
3343 11:52:15.099203 4, 0xFFFF, sum = 0
3344 11:52:15.102688 5, 0xFFFF, sum = 0
3345 11:52:15.102784 6, 0xFFFF, sum = 0
3346 11:52:15.105784 7, 0xFFFF, sum = 0
3347 11:52:15.105880 8, 0xFFFF, sum = 0
3348 11:52:15.109242 9, 0xFFFF, sum = 0
3349 11:52:15.109337 10, 0xFFFF, sum = 0
3350 11:52:15.112799 11, 0xFFFF, sum = 0
3351 11:52:15.112899 12, 0x0, sum = 1
3352 11:52:15.116040 13, 0x0, sum = 2
3353 11:52:15.116148 14, 0x0, sum = 3
3354 11:52:15.119411 15, 0x0, sum = 4
3355 11:52:15.119509 best_step = 13
3356 11:52:15.119606
3357 11:52:15.119691 ==
3358 11:52:15.122420 Dram Type= 6, Freq= 0, CH_1, rank 0
3359 11:52:15.129309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3360 11:52:15.129415 ==
3361 11:52:15.129510 RX Vref Scan: 1
3362 11:52:15.129602
3363 11:52:15.132864 Set Vref Range= 32 -> 127
3364 11:52:15.132962
3365 11:52:15.135841 RX Vref 32 -> 127, step: 1
3366 11:52:15.135937
3367 11:52:15.136025 RX Delay -21 -> 252, step: 4
3368 11:52:15.136110
3369 11:52:15.139331 Set Vref, RX VrefLevel [Byte0]: 32
3370 11:52:15.142614 [Byte1]: 32
3371 11:52:15.147007
3372 11:52:15.147082 Set Vref, RX VrefLevel [Byte0]: 33
3373 11:52:15.150317 [Byte1]: 33
3374 11:52:15.155135
3375 11:52:15.155209 Set Vref, RX VrefLevel [Byte0]: 34
3376 11:52:15.158517 [Byte1]: 34
3377 11:52:15.163014
3378 11:52:15.163112 Set Vref, RX VrefLevel [Byte0]: 35
3379 11:52:15.166086 [Byte1]: 35
3380 11:52:15.171131
3381 11:52:15.171236 Set Vref, RX VrefLevel [Byte0]: 36
3382 11:52:15.174587 [Byte1]: 36
3383 11:52:15.178780
3384 11:52:15.178889 Set Vref, RX VrefLevel [Byte0]: 37
3385 11:52:15.182014 [Byte1]: 37
3386 11:52:15.187129
3387 11:52:15.187201 Set Vref, RX VrefLevel [Byte0]: 38
3388 11:52:15.189773 [Byte1]: 38
3389 11:52:15.194679
3390 11:52:15.194779 Set Vref, RX VrefLevel [Byte0]: 39
3391 11:52:15.197634 [Byte1]: 39
3392 11:52:15.202667
3393 11:52:15.202772 Set Vref, RX VrefLevel [Byte0]: 40
3394 11:52:15.205586 [Byte1]: 40
3395 11:52:15.210456
3396 11:52:15.210557 Set Vref, RX VrefLevel [Byte0]: 41
3397 11:52:15.214066 [Byte1]: 41
3398 11:52:15.218179
3399 11:52:15.218277 Set Vref, RX VrefLevel [Byte0]: 42
3400 11:52:15.221774 [Byte1]: 42
3401 11:52:15.226596
3402 11:52:15.226699 Set Vref, RX VrefLevel [Byte0]: 43
3403 11:52:15.229645 [Byte1]: 43
3404 11:52:15.234080
3405 11:52:15.234158 Set Vref, RX VrefLevel [Byte0]: 44
3406 11:52:15.237624 [Byte1]: 44
3407 11:52:15.241911
3408 11:52:15.242010 Set Vref, RX VrefLevel [Byte0]: 45
3409 11:52:15.245535 [Byte1]: 45
3410 11:52:15.249756
3411 11:52:15.249856 Set Vref, RX VrefLevel [Byte0]: 46
3412 11:52:15.253401 [Byte1]: 46
3413 11:52:15.258160
3414 11:52:15.258235 Set Vref, RX VrefLevel [Byte0]: 47
3415 11:52:15.261166 [Byte1]: 47
3416 11:52:15.265860
3417 11:52:15.265959 Set Vref, RX VrefLevel [Byte0]: 48
3418 11:52:15.269579 [Byte1]: 48
3419 11:52:15.273759
3420 11:52:15.273889 Set Vref, RX VrefLevel [Byte0]: 49
3421 11:52:15.276946 [Byte1]: 49
3422 11:52:15.281923
3423 11:52:15.282010 Set Vref, RX VrefLevel [Byte0]: 50
3424 11:52:15.285253 [Byte1]: 50
3425 11:52:15.289434
3426 11:52:15.289535 Set Vref, RX VrefLevel [Byte0]: 51
3427 11:52:15.292994 [Byte1]: 51
3428 11:52:15.297363
3429 11:52:15.297461 Set Vref, RX VrefLevel [Byte0]: 52
3430 11:52:15.300771 [Byte1]: 52
3431 11:52:15.305741
3432 11:52:15.305839 Set Vref, RX VrefLevel [Byte0]: 53
3433 11:52:15.308970 [Byte1]: 53
3434 11:52:15.313456
3435 11:52:15.313532 Set Vref, RX VrefLevel [Byte0]: 54
3436 11:52:15.316839 [Byte1]: 54
3437 11:52:15.321636
3438 11:52:15.321739 Set Vref, RX VrefLevel [Byte0]: 55
3439 11:52:15.324460 [Byte1]: 55
3440 11:52:15.329329
3441 11:52:15.329427 Set Vref, RX VrefLevel [Byte0]: 56
3442 11:52:15.332420 [Byte1]: 56
3443 11:52:15.337451
3444 11:52:15.337551 Set Vref, RX VrefLevel [Byte0]: 57
3445 11:52:15.340402 [Byte1]: 57
3446 11:52:15.344921
3447 11:52:15.345021 Set Vref, RX VrefLevel [Byte0]: 58
3448 11:52:15.348889 [Byte1]: 58
3449 11:52:15.353423
3450 11:52:15.353524 Set Vref, RX VrefLevel [Byte0]: 59
3451 11:52:15.356567 [Byte1]: 59
3452 11:52:15.361238
3453 11:52:15.361339 Set Vref, RX VrefLevel [Byte0]: 60
3454 11:52:15.364186 [Byte1]: 60
3455 11:52:15.368721
3456 11:52:15.368823 Set Vref, RX VrefLevel [Byte0]: 61
3457 11:52:15.372575 [Byte1]: 61
3458 11:52:15.376420
3459 11:52:15.376523 Set Vref, RX VrefLevel [Byte0]: 62
3460 11:52:15.380020 [Byte1]: 62
3461 11:52:15.384844
3462 11:52:15.384945 Set Vref, RX VrefLevel [Byte0]: 63
3463 11:52:15.388218 [Byte1]: 63
3464 11:52:15.392548
3465 11:52:15.392647 Set Vref, RX VrefLevel [Byte0]: 64
3466 11:52:15.395975 [Byte1]: 64
3467 11:52:15.400538
3468 11:52:15.400642 Set Vref, RX VrefLevel [Byte0]: 65
3469 11:52:15.403508 [Byte1]: 65
3470 11:52:15.408222
3471 11:52:15.408302 Set Vref, RX VrefLevel [Byte0]: 66
3472 11:52:15.411903 [Byte1]: 66
3473 11:52:15.416453
3474 11:52:15.416528 Set Vref, RX VrefLevel [Byte0]: 67
3475 11:52:15.420132 [Byte1]: 67
3476 11:52:15.424435
3477 11:52:15.424533 Set Vref, RX VrefLevel [Byte0]: 68
3478 11:52:15.427548 [Byte1]: 68
3479 11:52:15.432279
3480 11:52:15.432372 Final RX Vref Byte 0 = 60 to rank0
3481 11:52:15.435868 Final RX Vref Byte 1 = 53 to rank0
3482 11:52:15.438751 Final RX Vref Byte 0 = 60 to rank1
3483 11:52:15.442231 Final RX Vref Byte 1 = 53 to rank1==
3484 11:52:15.445334 Dram Type= 6, Freq= 0, CH_1, rank 0
3485 11:52:15.452407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3486 11:52:15.452512 ==
3487 11:52:15.452602 DQS Delay:
3488 11:52:15.452699 DQS0 = 0, DQS1 = 0
3489 11:52:15.455375 DQM Delay:
3490 11:52:15.455448 DQM0 = 115, DQM1 = 110
3491 11:52:15.458994 DQ Delay:
3492 11:52:15.462711 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =114
3493 11:52:15.465441 DQ4 =116, DQ5 =122, DQ6 =126, DQ7 =114
3494 11:52:15.469162 DQ8 =98, DQ9 =98, DQ10 =114, DQ11 =106
3495 11:52:15.472221 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =114
3496 11:52:15.472325
3497 11:52:15.472419
3498 11:52:15.478817 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 409 ps
3499 11:52:15.482837 CH1 RK0: MR19=403, MR18=2E6
3500 11:52:15.489498 CH1_RK0: MR19=0x403, MR18=0x2E6, DQSOSC=409, MR23=63, INC=39, DEC=26
3501 11:52:15.489607
3502 11:52:15.492641 ----->DramcWriteLeveling(PI) begin...
3503 11:52:15.492743 ==
3504 11:52:15.495721 Dram Type= 6, Freq= 0, CH_1, rank 1
3505 11:52:15.499152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3506 11:52:15.499230 ==
3507 11:52:15.502505 Write leveling (Byte 0): 26 => 26
3508 11:52:15.505913 Write leveling (Byte 1): 28 => 28
3509 11:52:15.509376 DramcWriteLeveling(PI) end<-----
3510 11:52:15.509479
3511 11:52:15.509575 ==
3512 11:52:15.512411 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 11:52:15.515954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 11:52:15.516125 ==
3515 11:52:15.519600 [Gating] SW mode calibration
3516 11:52:15.526269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3517 11:52:15.532883 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3518 11:52:15.536566 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3519 11:52:15.539700 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 11:52:15.546899 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 11:52:15.549758 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3522 11:52:15.553336 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3523 11:52:15.559676 0 15 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
3524 11:52:15.563103 0 15 24 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
3525 11:52:15.566853 0 15 28 | B1->B0 | 2929 2323 | 1 0 | (1 0) (0 0)
3526 11:52:15.573352 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3527 11:52:15.576696 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 11:52:15.580074 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 11:52:15.583818 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 11:52:15.590516 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3531 11:52:15.593428 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
3532 11:52:15.597195 1 0 24 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
3533 11:52:15.603810 1 0 28 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
3534 11:52:15.607222 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:52:15.610296 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:52:15.616836 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 11:52:15.620370 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3538 11:52:15.623478 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3539 11:52:15.630067 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3540 11:52:15.633422 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3541 11:52:15.637029 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3542 11:52:15.643471 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:52:15.646857 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:52:15.650276 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 11:52:15.657304 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 11:52:15.660389 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 11:52:15.663442 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 11:52:15.667012 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 11:52:15.673599 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 11:52:15.677007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 11:52:15.680195 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 11:52:15.686779 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 11:52:15.690195 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 11:52:15.694017 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 11:52:15.700575 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3556 11:52:15.703576 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3557 11:52:15.707107 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3558 11:52:15.713535 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 11:52:15.713640 Total UI for P1: 0, mck2ui 16
3560 11:52:15.720604 best dqsien dly found for B0: ( 1, 3, 24)
3561 11:52:15.720709 Total UI for P1: 0, mck2ui 16
3562 11:52:15.727109 best dqsien dly found for B1: ( 1, 3, 28)
3563 11:52:15.730511 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3564 11:52:15.733454 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3565 11:52:15.733565
3566 11:52:15.736971 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3567 11:52:15.740392 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3568 11:52:15.743894 [Gating] SW calibration Done
3569 11:52:15.743996 ==
3570 11:52:15.746956 Dram Type= 6, Freq= 0, CH_1, rank 1
3571 11:52:15.750439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3572 11:52:15.750548 ==
3573 11:52:15.753997 RX Vref Scan: 0
3574 11:52:15.754072
3575 11:52:15.754161 RX Vref 0 -> 0, step: 1
3576 11:52:15.754250
3577 11:52:15.757112 RX Delay -40 -> 252, step: 8
3578 11:52:15.760805 iDelay=192, Bit 0, Center 111 (40 ~ 183) 144
3579 11:52:15.763607 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3580 11:52:15.770935 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3581 11:52:15.773615 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3582 11:52:15.777174 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3583 11:52:15.781031 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3584 11:52:15.783750 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3585 11:52:15.790845 iDelay=192, Bit 7, Center 111 (48 ~ 175) 128
3586 11:52:15.794104 iDelay=192, Bit 8, Center 103 (32 ~ 175) 144
3587 11:52:15.797445 iDelay=192, Bit 9, Center 95 (24 ~ 167) 144
3588 11:52:15.800865 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3589 11:52:15.804189 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3590 11:52:15.810625 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3591 11:52:15.814040 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3592 11:52:15.817348 iDelay=192, Bit 14, Center 119 (48 ~ 191) 144
3593 11:52:15.820916 iDelay=192, Bit 15, Center 119 (48 ~ 191) 144
3594 11:52:15.821023 ==
3595 11:52:15.824171 Dram Type= 6, Freq= 0, CH_1, rank 1
3596 11:52:15.830840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3597 11:52:15.830962 ==
3598 11:52:15.831033 DQS Delay:
3599 11:52:15.831093 DQS0 = 0, DQS1 = 0
3600 11:52:15.833899 DQM Delay:
3601 11:52:15.833982 DQM0 = 113, DQM1 = 110
3602 11:52:15.837471 DQ Delay:
3603 11:52:15.840591 DQ0 =111, DQ1 =111, DQ2 =103, DQ3 =115
3604 11:52:15.843999 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =111
3605 11:52:15.847604 DQ8 =103, DQ9 =95, DQ10 =111, DQ11 =103
3606 11:52:15.850887 DQ12 =115, DQ13 =119, DQ14 =119, DQ15 =119
3607 11:52:15.851000
3608 11:52:15.851090
3609 11:52:15.851175 ==
3610 11:52:15.854199 Dram Type= 6, Freq= 0, CH_1, rank 1
3611 11:52:15.857554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3612 11:52:15.857656 ==
3613 11:52:15.857746
3614 11:52:15.860765
3615 11:52:15.860883 TX Vref Scan disable
3616 11:52:15.864459 == TX Byte 0 ==
3617 11:52:15.867867 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3618 11:52:15.870677 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3619 11:52:15.874218 == TX Byte 1 ==
3620 11:52:15.877532 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3621 11:52:15.880986 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3622 11:52:15.881116 ==
3623 11:52:15.884025 Dram Type= 6, Freq= 0, CH_1, rank 1
3624 11:52:15.887634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3625 11:52:15.891194 ==
3626 11:52:15.901127 TX Vref=22, minBit 1, minWin=25, winSum=419
3627 11:52:15.904488 TX Vref=24, minBit 2, minWin=25, winSum=423
3628 11:52:15.908005 TX Vref=26, minBit 0, minWin=25, winSum=427
3629 11:52:15.911547 TX Vref=28, minBit 1, minWin=26, winSum=433
3630 11:52:15.914835 TX Vref=30, minBit 1, minWin=26, winSum=434
3631 11:52:15.918039 TX Vref=32, minBit 1, minWin=26, winSum=434
3632 11:52:15.924650 [TxChooseVref] Worse bit 1, Min win 26, Win sum 434, Final Vref 30
3633 11:52:15.924757
3634 11:52:15.927802 Final TX Range 1 Vref 30
3635 11:52:15.927880
3636 11:52:15.927945 ==
3637 11:52:15.931290 Dram Type= 6, Freq= 0, CH_1, rank 1
3638 11:52:15.934753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3639 11:52:15.934871 ==
3640 11:52:15.934941
3641 11:52:15.935016
3642 11:52:15.938455 TX Vref Scan disable
3643 11:52:15.941622 == TX Byte 0 ==
3644 11:52:15.944981 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3645 11:52:15.948107 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3646 11:52:15.951873 == TX Byte 1 ==
3647 11:52:15.954833 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3648 11:52:15.957805 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3649 11:52:15.957912
3650 11:52:15.961195 [DATLAT]
3651 11:52:15.961315 Freq=1200, CH1 RK1
3652 11:52:15.961413
3653 11:52:15.964673 DATLAT Default: 0xd
3654 11:52:15.964777 0, 0xFFFF, sum = 0
3655 11:52:15.967846 1, 0xFFFF, sum = 0
3656 11:52:15.967952 2, 0xFFFF, sum = 0
3657 11:52:15.971594 3, 0xFFFF, sum = 0
3658 11:52:15.971705 4, 0xFFFF, sum = 0
3659 11:52:15.974575 5, 0xFFFF, sum = 0
3660 11:52:15.974687 6, 0xFFFF, sum = 0
3661 11:52:15.978283 7, 0xFFFF, sum = 0
3662 11:52:15.978396 8, 0xFFFF, sum = 0
3663 11:52:15.981566 9, 0xFFFF, sum = 0
3664 11:52:15.981673 10, 0xFFFF, sum = 0
3665 11:52:15.984851 11, 0xFFFF, sum = 0
3666 11:52:15.984954 12, 0x0, sum = 1
3667 11:52:15.987983 13, 0x0, sum = 2
3668 11:52:15.988090 14, 0x0, sum = 3
3669 11:52:15.991352 15, 0x0, sum = 4
3670 11:52:15.991459 best_step = 13
3671 11:52:15.991564
3672 11:52:15.991654 ==
3673 11:52:15.994777 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 11:52:16.001641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 11:52:16.001755 ==
3676 11:52:16.001855 RX Vref Scan: 0
3677 11:52:16.001945
3678 11:52:16.004898 RX Vref 0 -> 0, step: 1
3679 11:52:16.005000
3680 11:52:16.008003 RX Delay -21 -> 252, step: 4
3681 11:52:16.011544 iDelay=191, Bit 0, Center 112 (43 ~ 182) 140
3682 11:52:16.014683 iDelay=191, Bit 1, Center 108 (43 ~ 174) 132
3683 11:52:16.021637 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3684 11:52:16.024705 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3685 11:52:16.028329 iDelay=191, Bit 4, Center 112 (47 ~ 178) 132
3686 11:52:16.031311 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3687 11:52:16.034779 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3688 11:52:16.038558 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3689 11:52:16.044859 iDelay=191, Bit 8, Center 98 (31 ~ 166) 136
3690 11:52:16.048072 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3691 11:52:16.051987 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3692 11:52:16.054849 iDelay=191, Bit 11, Center 102 (35 ~ 170) 136
3693 11:52:16.058371 iDelay=191, Bit 12, Center 116 (51 ~ 182) 132
3694 11:52:16.065207 iDelay=191, Bit 13, Center 118 (51 ~ 186) 136
3695 11:52:16.068731 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3696 11:52:16.071552 iDelay=191, Bit 15, Center 118 (51 ~ 186) 136
3697 11:52:16.071658 ==
3698 11:52:16.074851 Dram Type= 6, Freq= 0, CH_1, rank 1
3699 11:52:16.078417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3700 11:52:16.078519 ==
3701 11:52:16.081621 DQS Delay:
3702 11:52:16.081726 DQS0 = 0, DQS1 = 0
3703 11:52:16.085049 DQM Delay:
3704 11:52:16.085148 DQM0 = 113, DQM1 = 109
3705 11:52:16.085240 DQ Delay:
3706 11:52:16.091694 DQ0 =112, DQ1 =108, DQ2 =104, DQ3 =112
3707 11:52:16.095262 DQ4 =112, DQ5 =124, DQ6 =122, DQ7 =110
3708 11:52:16.098289 DQ8 =98, DQ9 =98, DQ10 =110, DQ11 =102
3709 11:52:16.101969 DQ12 =116, DQ13 =118, DQ14 =118, DQ15 =118
3710 11:52:16.102045
3711 11:52:16.102141
3712 11:52:16.108351 [DQSOSCAuto] RK1, (LSB)MR18= 0xf8ff, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 413 ps
3713 11:52:16.111936 CH1 RK1: MR19=303, MR18=F8FF
3714 11:52:16.118872 CH1_RK1: MR19=0x303, MR18=0xF8FF, DQSOSC=410, MR23=63, INC=39, DEC=26
3715 11:52:16.121966 [RxdqsGatingPostProcess] freq 1200
3716 11:52:16.125481 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3717 11:52:16.128570 best DQS0 dly(2T, 0.5T) = (0, 11)
3718 11:52:16.131770 best DQS1 dly(2T, 0.5T) = (0, 11)
3719 11:52:16.135526 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3720 11:52:16.138782 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3721 11:52:16.141856 best DQS0 dly(2T, 0.5T) = (0, 11)
3722 11:52:16.145434 best DQS1 dly(2T, 0.5T) = (0, 11)
3723 11:52:16.149004 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3724 11:52:16.152006 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3725 11:52:16.155604 Pre-setting of DQS Precalculation
3726 11:52:16.158494 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3727 11:52:16.168656 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3728 11:52:16.175616 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3729 11:52:16.175724
3730 11:52:16.175820
3731 11:52:16.178660 [Calibration Summary] 2400 Mbps
3732 11:52:16.178761 CH 0, Rank 0
3733 11:52:16.182358 SW Impedance : PASS
3734 11:52:16.182457 DUTY Scan : NO K
3735 11:52:16.185368 ZQ Calibration : PASS
3736 11:52:16.189014 Jitter Meter : NO K
3737 11:52:16.189116 CBT Training : PASS
3738 11:52:16.192025 Write leveling : PASS
3739 11:52:16.195314 RX DQS gating : PASS
3740 11:52:16.195392 RX DQ/DQS(RDDQC) : PASS
3741 11:52:16.198571 TX DQ/DQS : PASS
3742 11:52:16.198681 RX DATLAT : PASS
3743 11:52:16.202173 RX DQ/DQS(Engine): PASS
3744 11:52:16.205099 TX OE : NO K
3745 11:52:16.205215 All Pass.
3746 11:52:16.205309
3747 11:52:16.205400 CH 0, Rank 1
3748 11:52:16.208665 SW Impedance : PASS
3749 11:52:16.212179 DUTY Scan : NO K
3750 11:52:16.212283 ZQ Calibration : PASS
3751 11:52:16.215513 Jitter Meter : NO K
3752 11:52:16.218613 CBT Training : PASS
3753 11:52:16.218717 Write leveling : PASS
3754 11:52:16.221724 RX DQS gating : PASS
3755 11:52:16.225196 RX DQ/DQS(RDDQC) : PASS
3756 11:52:16.225300 TX DQ/DQS : PASS
3757 11:52:16.228357 RX DATLAT : PASS
3758 11:52:16.232066 RX DQ/DQS(Engine): PASS
3759 11:52:16.232173 TX OE : NO K
3760 11:52:16.232275 All Pass.
3761 11:52:16.235215
3762 11:52:16.235323 CH 1, Rank 0
3763 11:52:16.238767 SW Impedance : PASS
3764 11:52:16.238886 DUTY Scan : NO K
3765 11:52:16.242080 ZQ Calibration : PASS
3766 11:52:16.242184 Jitter Meter : NO K
3767 11:52:16.245618 CBT Training : PASS
3768 11:52:16.248394 Write leveling : PASS
3769 11:52:16.248495 RX DQS gating : PASS
3770 11:52:16.251972 RX DQ/DQS(RDDQC) : PASS
3771 11:52:16.255555 TX DQ/DQS : PASS
3772 11:52:16.255658 RX DATLAT : PASS
3773 11:52:16.258691 RX DQ/DQS(Engine): PASS
3774 11:52:16.262113 TX OE : NO K
3775 11:52:16.262188 All Pass.
3776 11:52:16.262261
3777 11:52:16.262351 CH 1, Rank 1
3778 11:52:16.265158 SW Impedance : PASS
3779 11:52:16.268614 DUTY Scan : NO K
3780 11:52:16.268714 ZQ Calibration : PASS
3781 11:52:16.271624 Jitter Meter : NO K
3782 11:52:16.275078 CBT Training : PASS
3783 11:52:16.275157 Write leveling : PASS
3784 11:52:16.278589 RX DQS gating : PASS
3785 11:52:16.281825 RX DQ/DQS(RDDQC) : PASS
3786 11:52:16.281928 TX DQ/DQS : PASS
3787 11:52:16.285477 RX DATLAT : PASS
3788 11:52:16.285574 RX DQ/DQS(Engine): PASS
3789 11:52:16.288676 TX OE : NO K
3790 11:52:16.288763 All Pass.
3791 11:52:16.288832
3792 11:52:16.291512 DramC Write-DBI off
3793 11:52:16.295093 PER_BANK_REFRESH: Hybrid Mode
3794 11:52:16.295198 TX_TRACKING: ON
3795 11:52:16.305257 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3796 11:52:16.308470 [FAST_K] Save calibration result to emmc
3797 11:52:16.312044 dramc_set_vcore_voltage set vcore to 650000
3798 11:52:16.315266 Read voltage for 600, 5
3799 11:52:16.315365 Vio18 = 0
3800 11:52:16.318681 Vcore = 650000
3801 11:52:16.318780 Vdram = 0
3802 11:52:16.318880 Vddq = 0
3803 11:52:16.318944 Vmddr = 0
3804 11:52:16.325338 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3805 11:52:16.328655 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3806 11:52:16.331664 MEM_TYPE=3, freq_sel=19
3807 11:52:16.335400 sv_algorithm_assistance_LP4_1600
3808 11:52:16.338459 ============ PULL DRAM RESETB DOWN ============
3809 11:52:16.345056 ========== PULL DRAM RESETB DOWN end =========
3810 11:52:16.348701 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3811 11:52:16.351788 ===================================
3812 11:52:16.355174 LPDDR4 DRAM CONFIGURATION
3813 11:52:16.358475 ===================================
3814 11:52:16.358584 EX_ROW_EN[0] = 0x0
3815 11:52:16.362211 EX_ROW_EN[1] = 0x0
3816 11:52:16.362315 LP4Y_EN = 0x0
3817 11:52:16.365123 WORK_FSP = 0x0
3818 11:52:16.365221 WL = 0x2
3819 11:52:16.368733 RL = 0x2
3820 11:52:16.368833 BL = 0x2
3821 11:52:16.371675 RPST = 0x0
3822 11:52:16.371787 RD_PRE = 0x0
3823 11:52:16.375284 WR_PRE = 0x1
3824 11:52:16.375381 WR_PST = 0x0
3825 11:52:16.378857 DBI_WR = 0x0
3826 11:52:16.378939 DBI_RD = 0x0
3827 11:52:16.382005 OTF = 0x1
3828 11:52:16.385308 ===================================
3829 11:52:16.388783 ===================================
3830 11:52:16.388886 ANA top config
3831 11:52:16.391931 ===================================
3832 11:52:16.395428 DLL_ASYNC_EN = 0
3833 11:52:16.398912 ALL_SLAVE_EN = 1
3834 11:52:16.401925 NEW_RANK_MODE = 1
3835 11:52:16.402027 DLL_IDLE_MODE = 1
3836 11:52:16.405621 LP45_APHY_COMB_EN = 1
3837 11:52:16.408432 TX_ODT_DIS = 1
3838 11:52:16.411990 NEW_8X_MODE = 1
3839 11:52:16.415669 ===================================
3840 11:52:16.418767 ===================================
3841 11:52:16.422679 data_rate = 1200
3842 11:52:16.422781 CKR = 1
3843 11:52:16.425557 DQ_P2S_RATIO = 8
3844 11:52:16.428931 ===================================
3845 11:52:16.431888 CA_P2S_RATIO = 8
3846 11:52:16.435224 DQ_CA_OPEN = 0
3847 11:52:16.438749 DQ_SEMI_OPEN = 0
3848 11:52:16.438845 CA_SEMI_OPEN = 0
3849 11:52:16.442132 CA_FULL_RATE = 0
3850 11:52:16.445658 DQ_CKDIV4_EN = 1
3851 11:52:16.448948 CA_CKDIV4_EN = 1
3852 11:52:16.452128 CA_PREDIV_EN = 0
3853 11:52:16.455465 PH8_DLY = 0
3854 11:52:16.455566 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3855 11:52:16.459131 DQ_AAMCK_DIV = 4
3856 11:52:16.461939 CA_AAMCK_DIV = 4
3857 11:52:16.465564 CA_ADMCK_DIV = 4
3858 11:52:16.468686 DQ_TRACK_CA_EN = 0
3859 11:52:16.472164 CA_PICK = 600
3860 11:52:16.475874 CA_MCKIO = 600
3861 11:52:16.475977 MCKIO_SEMI = 0
3862 11:52:16.478691 PLL_FREQ = 2288
3863 11:52:16.482253 DQ_UI_PI_RATIO = 32
3864 11:52:16.485715 CA_UI_PI_RATIO = 0
3865 11:52:16.488819 ===================================
3866 11:52:16.492606 ===================================
3867 11:52:16.495932 memory_type:LPDDR4
3868 11:52:16.496019 GP_NUM : 10
3869 11:52:16.498706 SRAM_EN : 1
3870 11:52:16.498812 MD32_EN : 0
3871 11:52:16.502296 ===================================
3872 11:52:16.505321 [ANA_INIT] >>>>>>>>>>>>>>
3873 11:52:16.508910 <<<<<< [CONFIGURE PHASE]: ANA_TX
3874 11:52:16.512454 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3875 11:52:16.515530 ===================================
3876 11:52:16.519224 data_rate = 1200,PCW = 0X5800
3877 11:52:16.522580 ===================================
3878 11:52:16.525531 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3879 11:52:16.529106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3880 11:52:16.535792 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3881 11:52:16.539076 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3882 11:52:16.542199 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3883 11:52:16.548937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3884 11:52:16.549045 [ANA_INIT] flow start
3885 11:52:16.552446 [ANA_INIT] PLL >>>>>>>>
3886 11:52:16.552549 [ANA_INIT] PLL <<<<<<<<
3887 11:52:16.555876 [ANA_INIT] MIDPI >>>>>>>>
3888 11:52:16.559245 [ANA_INIT] MIDPI <<<<<<<<
3889 11:52:16.562255 [ANA_INIT] DLL >>>>>>>>
3890 11:52:16.562357 [ANA_INIT] flow end
3891 11:52:16.565720 ============ LP4 DIFF to SE enter ============
3892 11:52:16.572628 ============ LP4 DIFF to SE exit ============
3893 11:52:16.572738 [ANA_INIT] <<<<<<<<<<<<<
3894 11:52:16.575634 [Flow] Enable top DCM control >>>>>
3895 11:52:16.579270 [Flow] Enable top DCM control <<<<<
3896 11:52:16.582239 Enable DLL master slave shuffle
3897 11:52:16.589306 ==============================================================
3898 11:52:16.589413 Gating Mode config
3899 11:52:16.595979 ==============================================================
3900 11:52:16.599203 Config description:
3901 11:52:16.606232 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3902 11:52:16.613145 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3903 11:52:16.619555 SELPH_MODE 0: By rank 1: By Phase
3904 11:52:16.622555 ==============================================================
3905 11:52:16.626368 GAT_TRACK_EN = 1
3906 11:52:16.629650 RX_GATING_MODE = 2
3907 11:52:16.632588 RX_GATING_TRACK_MODE = 2
3908 11:52:16.636359 SELPH_MODE = 1
3909 11:52:16.639301 PICG_EARLY_EN = 1
3910 11:52:16.642856 VALID_LAT_VALUE = 1
3911 11:52:16.649716 ==============================================================
3912 11:52:16.652990 Enter into Gating configuration >>>>
3913 11:52:16.656107 Exit from Gating configuration <<<<
3914 11:52:16.659631 Enter into DVFS_PRE_config >>>>>
3915 11:52:16.669811 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3916 11:52:16.672808 Exit from DVFS_PRE_config <<<<<
3917 11:52:16.676690 Enter into PICG configuration >>>>
3918 11:52:16.679544 Exit from PICG configuration <<<<
3919 11:52:16.679622 [RX_INPUT] configuration >>>>>
3920 11:52:16.682847 [RX_INPUT] configuration <<<<<
3921 11:52:16.689628 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3922 11:52:16.692884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3923 11:52:16.699465 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 11:52:16.706024 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 11:52:16.712833 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3926 11:52:16.719720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3927 11:52:16.722780 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3928 11:52:16.726618 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3929 11:52:16.729919 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3930 11:52:16.736279 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3931 11:52:16.739826 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3932 11:52:16.743038 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3933 11:52:16.746560 ===================================
3934 11:52:16.749528 LPDDR4 DRAM CONFIGURATION
3935 11:52:16.753203 ===================================
3936 11:52:16.756796 EX_ROW_EN[0] = 0x0
3937 11:52:16.756902 EX_ROW_EN[1] = 0x0
3938 11:52:16.759907 LP4Y_EN = 0x0
3939 11:52:16.760010 WORK_FSP = 0x0
3940 11:52:16.763248 WL = 0x2
3941 11:52:16.763351 RL = 0x2
3942 11:52:16.766284 BL = 0x2
3943 11:52:16.766370 RPST = 0x0
3944 11:52:16.769940 RD_PRE = 0x0
3945 11:52:16.770049 WR_PRE = 0x1
3946 11:52:16.772972 WR_PST = 0x0
3947 11:52:16.773086 DBI_WR = 0x0
3948 11:52:16.776743 DBI_RD = 0x0
3949 11:52:16.776855 OTF = 0x1
3950 11:52:16.779937 ===================================
3951 11:52:16.783543 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3952 11:52:16.789696 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3953 11:52:16.793473 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3954 11:52:16.796690 ===================================
3955 11:52:16.799854 LPDDR4 DRAM CONFIGURATION
3956 11:52:16.803229 ===================================
3957 11:52:16.803312 EX_ROW_EN[0] = 0x10
3958 11:52:16.806803 EX_ROW_EN[1] = 0x0
3959 11:52:16.806913 LP4Y_EN = 0x0
3960 11:52:16.809705 WORK_FSP = 0x0
3961 11:52:16.813459 WL = 0x2
3962 11:52:16.813538 RL = 0x2
3963 11:52:16.816539 BL = 0x2
3964 11:52:16.816612 RPST = 0x0
3965 11:52:16.819929 RD_PRE = 0x0
3966 11:52:16.819998 WR_PRE = 0x1
3967 11:52:16.822946 WR_PST = 0x0
3968 11:52:16.823048 DBI_WR = 0x0
3969 11:52:16.826705 DBI_RD = 0x0
3970 11:52:16.826802 OTF = 0x1
3971 11:52:16.829634 ===================================
3972 11:52:16.836216 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3973 11:52:16.840662 nWR fixed to 30
3974 11:52:16.844134 [ModeRegInit_LP4] CH0 RK0
3975 11:52:16.844210 [ModeRegInit_LP4] CH0 RK1
3976 11:52:16.847156 [ModeRegInit_LP4] CH1 RK0
3977 11:52:16.850685 [ModeRegInit_LP4] CH1 RK1
3978 11:52:16.850786 match AC timing 17
3979 11:52:16.857343 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3980 11:52:16.860804 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3981 11:52:16.863900 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3982 11:52:16.870625 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3983 11:52:16.873850 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3984 11:52:16.873955 ==
3985 11:52:16.877520 Dram Type= 6, Freq= 0, CH_0, rank 0
3986 11:52:16.880464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3987 11:52:16.880541 ==
3988 11:52:16.887604 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3989 11:52:16.893963 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3990 11:52:16.897319 [CA 0] Center 36 (6~67) winsize 62
3991 11:52:16.900760 [CA 1] Center 36 (6~66) winsize 61
3992 11:52:16.904347 [CA 2] Center 34 (4~65) winsize 62
3993 11:52:16.907487 [CA 3] Center 34 (4~64) winsize 61
3994 11:52:16.910566 [CA 4] Center 33 (3~64) winsize 62
3995 11:52:16.914148 [CA 5] Center 33 (3~64) winsize 62
3996 11:52:16.914228
3997 11:52:16.917454 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3998 11:52:16.917530
3999 11:52:16.920490 [CATrainingPosCal] consider 1 rank data
4000 11:52:16.923884 u2DelayCellTimex100 = 270/100 ps
4001 11:52:16.927500 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4002 11:52:16.930438 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4003 11:52:16.933925 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 11:52:16.937620 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4005 11:52:16.940842 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 11:52:16.944143 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4007 11:52:16.944245
4008 11:52:16.947581 CA PerBit enable=1, Macro0, CA PI delay=33
4009 11:52:16.950520
4010 11:52:16.950594 [CBTSetCACLKResult] CA Dly = 33
4011 11:52:16.954284 CS Dly: 4 (0~35)
4012 11:52:16.954357 ==
4013 11:52:16.957217 Dram Type= 6, Freq= 0, CH_0, rank 1
4014 11:52:16.960864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4015 11:52:16.960942 ==
4016 11:52:16.967638 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4017 11:52:16.973886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4018 11:52:16.977751 [CA 0] Center 36 (6~66) winsize 61
4019 11:52:16.980535 [CA 1] Center 36 (6~66) winsize 61
4020 11:52:16.984110 [CA 2] Center 34 (4~65) winsize 62
4021 11:52:16.987087 [CA 3] Center 34 (4~65) winsize 62
4022 11:52:16.990631 [CA 4] Center 33 (3~64) winsize 62
4023 11:52:16.994003 [CA 5] Center 33 (3~64) winsize 62
4024 11:52:16.994083
4025 11:52:16.997525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4026 11:52:16.997626
4027 11:52:17.000905 [CATrainingPosCal] consider 2 rank data
4028 11:52:17.004111 u2DelayCellTimex100 = 270/100 ps
4029 11:52:17.007320 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4030 11:52:17.010864 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4031 11:52:17.013829 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4032 11:52:17.017622 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4033 11:52:17.021049 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4034 11:52:17.023796 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4035 11:52:17.023871
4036 11:52:17.031164 CA PerBit enable=1, Macro0, CA PI delay=33
4037 11:52:17.031243
4038 11:52:17.031305 [CBTSetCACLKResult] CA Dly = 33
4039 11:52:17.034122 CS Dly: 4 (0~36)
4040 11:52:17.034189
4041 11:52:17.037354 ----->DramcWriteLeveling(PI) begin...
4042 11:52:17.037435 ==
4043 11:52:17.040832 Dram Type= 6, Freq= 0, CH_0, rank 0
4044 11:52:17.044097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4045 11:52:17.044196 ==
4046 11:52:17.047809 Write leveling (Byte 0): 31 => 31
4047 11:52:17.050499 Write leveling (Byte 1): 31 => 31
4048 11:52:17.054028 DramcWriteLeveling(PI) end<-----
4049 11:52:17.054102
4050 11:52:17.054166 ==
4051 11:52:17.057686 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 11:52:17.060614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 11:52:17.060687 ==
4054 11:52:17.064547 [Gating] SW mode calibration
4055 11:52:17.070644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4056 11:52:17.077482 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4057 11:52:17.080853 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 11:52:17.087555 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4059 11:52:17.091102 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4060 11:52:17.093921 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4061 11:52:17.101389 0 9 16 | B1->B0 | 3030 2525 | 0 1 | (0 1) (1 0)
4062 11:52:17.104272 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4063 11:52:17.107903 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 11:52:17.110743 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 11:52:17.117824 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 11:52:17.121121 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4067 11:52:17.124220 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4068 11:52:17.131086 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 11:52:17.134615 0 10 16 | B1->B0 | 2f2f 3838 | 0 0 | (0 0) (0 0)
4070 11:52:17.137785 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 11:52:17.144714 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:52:17.148088 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 11:52:17.151044 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 11:52:17.157818 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4075 11:52:17.161499 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4076 11:52:17.164651 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4077 11:52:17.171128 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4078 11:52:17.174837 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:52:17.177698 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:52:17.181264 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:52:17.188116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 11:52:17.191159 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 11:52:17.194533 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 11:52:17.201159 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 11:52:17.204759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 11:52:17.207878 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 11:52:17.214867 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 11:52:17.218283 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 11:52:17.221086 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 11:52:17.228129 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 11:52:17.231109 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 11:52:17.234533 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4093 11:52:17.241201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4094 11:52:17.241284 Total UI for P1: 0, mck2ui 16
4095 11:52:17.244419 best dqsien dly found for B0: ( 0, 13, 12)
4096 11:52:17.247711 Total UI for P1: 0, mck2ui 16
4097 11:52:17.251373 best dqsien dly found for B1: ( 0, 13, 14)
4098 11:52:17.254439 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4099 11:52:17.261250 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4100 11:52:17.261361
4101 11:52:17.264481 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4102 11:52:17.268011 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4103 11:52:17.271362 [Gating] SW calibration Done
4104 11:52:17.271444 ==
4105 11:52:17.274906 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 11:52:17.278100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 11:52:17.278187 ==
4108 11:52:17.281491 RX Vref Scan: 0
4109 11:52:17.281607
4110 11:52:17.281706 RX Vref 0 -> 0, step: 1
4111 11:52:17.281793
4112 11:52:17.285031 RX Delay -230 -> 252, step: 16
4113 11:52:17.288116 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4114 11:52:17.294757 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4115 11:52:17.298622 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4116 11:52:17.301979 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4117 11:52:17.305103 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4118 11:52:17.308612 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4119 11:52:17.315194 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4120 11:52:17.318308 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4121 11:52:17.321416 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4122 11:52:17.324664 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4123 11:52:17.328102 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4124 11:52:17.335257 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4125 11:52:17.338087 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4126 11:52:17.341679 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4127 11:52:17.345035 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4128 11:52:17.351407 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4129 11:52:17.351490 ==
4130 11:52:17.354616 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 11:52:17.358324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 11:52:17.358408 ==
4133 11:52:17.358473 DQS Delay:
4134 11:52:17.361375 DQS0 = 0, DQS1 = 0
4135 11:52:17.361457 DQM Delay:
4136 11:52:17.364693 DQM0 = 41, DQM1 = 31
4137 11:52:17.364776 DQ Delay:
4138 11:52:17.368056 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4139 11:52:17.371796 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4140 11:52:17.375175 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4141 11:52:17.378016 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4142 11:52:17.378090
4143 11:52:17.378153
4144 11:52:17.378213 ==
4145 11:52:17.381867 Dram Type= 6, Freq= 0, CH_0, rank 0
4146 11:52:17.385135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 11:52:17.385219 ==
4148 11:52:17.385284
4149 11:52:17.388270
4150 11:52:17.388353 TX Vref Scan disable
4151 11:52:17.391740 == TX Byte 0 ==
4152 11:52:17.395171 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4153 11:52:17.398590 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4154 11:52:17.401536 == TX Byte 1 ==
4155 11:52:17.405154 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4156 11:52:17.408354 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4157 11:52:17.408437 ==
4158 11:52:17.411693 Dram Type= 6, Freq= 0, CH_0, rank 0
4159 11:52:17.418406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 11:52:17.418490 ==
4161 11:52:17.418560
4162 11:52:17.418635
4163 11:52:17.418695 TX Vref Scan disable
4164 11:52:17.422730 == TX Byte 0 ==
4165 11:52:17.426191 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4166 11:52:17.429838 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4167 11:52:17.432553 == TX Byte 1 ==
4168 11:52:17.436198 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4169 11:52:17.439790 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4170 11:52:17.442662
4171 11:52:17.442743 [DATLAT]
4172 11:52:17.442808 Freq=600, CH0 RK0
4173 11:52:17.442878
4174 11:52:17.446101 DATLAT Default: 0x9
4175 11:52:17.446182 0, 0xFFFF, sum = 0
4176 11:52:17.449782 1, 0xFFFF, sum = 0
4177 11:52:17.449866 2, 0xFFFF, sum = 0
4178 11:52:17.452660 3, 0xFFFF, sum = 0
4179 11:52:17.452743 4, 0xFFFF, sum = 0
4180 11:52:17.456193 5, 0xFFFF, sum = 0
4181 11:52:17.456308 6, 0xFFFF, sum = 0
4182 11:52:17.459694 7, 0xFFFF, sum = 0
4183 11:52:17.459778 8, 0x0, sum = 1
4184 11:52:17.462626 9, 0x0, sum = 2
4185 11:52:17.462709 10, 0x0, sum = 3
4186 11:52:17.466249 11, 0x0, sum = 4
4187 11:52:17.466365 best_step = 9
4188 11:52:17.466459
4189 11:52:17.466557 ==
4190 11:52:17.469686 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 11:52:17.476275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 11:52:17.476393 ==
4193 11:52:17.476492 RX Vref Scan: 1
4194 11:52:17.476591
4195 11:52:17.479481 RX Vref 0 -> 0, step: 1
4196 11:52:17.479593
4197 11:52:17.482842 RX Delay -195 -> 252, step: 8
4198 11:52:17.482960
4199 11:52:17.486587 Set Vref, RX VrefLevel [Byte0]: 55
4200 11:52:17.489348 [Byte1]: 50
4201 11:52:17.489463
4202 11:52:17.493101 Final RX Vref Byte 0 = 55 to rank0
4203 11:52:17.496302 Final RX Vref Byte 1 = 50 to rank0
4204 11:52:17.499520 Final RX Vref Byte 0 = 55 to rank1
4205 11:52:17.503279 Final RX Vref Byte 1 = 50 to rank1==
4206 11:52:17.506642 Dram Type= 6, Freq= 0, CH_0, rank 0
4207 11:52:17.509622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 11:52:17.509720 ==
4209 11:52:17.509786 DQS Delay:
4210 11:52:17.513542 DQS0 = 0, DQS1 = 0
4211 11:52:17.513654 DQM Delay:
4212 11:52:17.516375 DQM0 = 42, DQM1 = 33
4213 11:52:17.516455 DQ Delay:
4214 11:52:17.519923 DQ0 =44, DQ1 =40, DQ2 =40, DQ3 =40
4215 11:52:17.523530 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4216 11:52:17.526613 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4217 11:52:17.530191 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4218 11:52:17.530299
4219 11:52:17.530392
4220 11:52:17.536844 [DQSOSCAuto] RK0, (LSB)MR18= 0x4524, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 396 ps
4221 11:52:17.540109 CH0 RK0: MR19=808, MR18=4524
4222 11:52:17.546714 CH0_RK0: MR19=0x808, MR18=0x4524, DQSOSC=396, MR23=63, INC=167, DEC=111
4223 11:52:17.546796
4224 11:52:17.550138 ----->DramcWriteLeveling(PI) begin...
4225 11:52:17.550222 ==
4226 11:52:17.553249 Dram Type= 6, Freq= 0, CH_0, rank 1
4227 11:52:17.560111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4228 11:52:17.560195 ==
4229 11:52:17.563135 Write leveling (Byte 0): 31 => 31
4230 11:52:17.563218 Write leveling (Byte 1): 31 => 31
4231 11:52:17.566678 DramcWriteLeveling(PI) end<-----
4232 11:52:17.566760
4233 11:52:17.566825 ==
4234 11:52:17.570161 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 11:52:17.576456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 11:52:17.576571 ==
4237 11:52:17.580070 [Gating] SW mode calibration
4238 11:52:17.586709 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4239 11:52:17.589852 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4240 11:52:17.593417 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 11:52:17.599970 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4242 11:52:17.603510 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4243 11:52:17.606453 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4244 11:52:17.613331 0 9 16 | B1->B0 | 3030 2424 | 0 0 | (0 1) (0 0)
4245 11:52:17.617117 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 11:52:17.620355 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 11:52:17.627208 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 11:52:17.630062 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 11:52:17.633693 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4250 11:52:17.640209 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4251 11:52:17.643588 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4252 11:52:17.647067 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4253 11:52:17.653607 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 11:52:17.656772 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 11:52:17.660443 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 11:52:17.667074 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 11:52:17.670417 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:52:17.673402 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4259 11:52:17.676901 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4260 11:52:17.683435 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4261 11:52:17.686688 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:52:17.690253 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:52:17.696848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:52:17.700413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 11:52:17.703857 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 11:52:17.710196 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 11:52:17.714021 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 11:52:17.717295 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 11:52:17.723562 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 11:52:17.727062 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 11:52:17.730304 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 11:52:17.737144 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 11:52:17.740289 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 11:52:17.743925 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 11:52:17.750677 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4276 11:52:17.753682 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4277 11:52:17.756930 Total UI for P1: 0, mck2ui 16
4278 11:52:17.760688 best dqsien dly found for B0: ( 0, 13, 12)
4279 11:52:17.764171 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4280 11:52:17.767405 Total UI for P1: 0, mck2ui 16
4281 11:52:17.770686 best dqsien dly found for B1: ( 0, 13, 14)
4282 11:52:17.773949 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4283 11:52:17.777535 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4284 11:52:17.777608
4285 11:52:17.780345 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4286 11:52:17.787306 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4287 11:52:17.787404 [Gating] SW calibration Done
4288 11:52:17.787471 ==
4289 11:52:17.790194 Dram Type= 6, Freq= 0, CH_0, rank 1
4290 11:52:17.797196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4291 11:52:17.797306 ==
4292 11:52:17.797406 RX Vref Scan: 0
4293 11:52:17.797495
4294 11:52:17.800840 RX Vref 0 -> 0, step: 1
4295 11:52:17.800937
4296 11:52:17.803959 RX Delay -230 -> 252, step: 16
4297 11:52:17.807259 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4298 11:52:17.810821 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4299 11:52:17.813830 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4300 11:52:17.820481 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4301 11:52:17.824435 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4302 11:52:17.827188 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4303 11:52:17.830817 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4304 11:52:17.833750 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4305 11:52:17.840902 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4306 11:52:17.844042 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4307 11:52:17.847381 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4308 11:52:17.850543 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4309 11:52:17.857407 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4310 11:52:17.861034 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4311 11:52:17.864286 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4312 11:52:17.867260 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4313 11:52:17.867337 ==
4314 11:52:17.870818 Dram Type= 6, Freq= 0, CH_0, rank 1
4315 11:52:17.877329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4316 11:52:17.877434 ==
4317 11:52:17.877525 DQS Delay:
4318 11:52:17.877624 DQS0 = 0, DQS1 = 0
4319 11:52:17.880912 DQM Delay:
4320 11:52:17.881009 DQM0 = 39, DQM1 = 32
4321 11:52:17.884594 DQ Delay:
4322 11:52:17.887917 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4323 11:52:17.888000 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4324 11:52:17.891555 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4325 11:52:17.894417 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4326 11:52:17.894526
4327 11:52:17.897764
4328 11:52:17.897873 ==
4329 11:52:17.901462 Dram Type= 6, Freq= 0, CH_0, rank 1
4330 11:52:17.904583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 11:52:17.904690 ==
4332 11:52:17.904780
4333 11:52:17.904874
4334 11:52:17.907901 TX Vref Scan disable
4335 11:52:17.907973 == TX Byte 0 ==
4336 11:52:17.914369 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4337 11:52:17.917624 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4338 11:52:17.917723 == TX Byte 1 ==
4339 11:52:17.924421 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4340 11:52:17.927606 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4341 11:52:17.927680 ==
4342 11:52:17.930868 Dram Type= 6, Freq= 0, CH_0, rank 1
4343 11:52:17.934436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4344 11:52:17.934537 ==
4345 11:52:17.934635
4346 11:52:17.934725
4347 11:52:17.938064 TX Vref Scan disable
4348 11:52:17.941168 == TX Byte 0 ==
4349 11:52:17.944219 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4350 11:52:17.947670 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4351 11:52:17.951275 == TX Byte 1 ==
4352 11:52:17.954287 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4353 11:52:17.958132 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4354 11:52:17.958207
4355 11:52:17.961271 [DATLAT]
4356 11:52:17.961370 Freq=600, CH0 RK1
4357 11:52:17.961459
4358 11:52:17.964391 DATLAT Default: 0x9
4359 11:52:17.964487 0, 0xFFFF, sum = 0
4360 11:52:17.967662 1, 0xFFFF, sum = 0
4361 11:52:17.967740 2, 0xFFFF, sum = 0
4362 11:52:17.971224 3, 0xFFFF, sum = 0
4363 11:52:17.971326 4, 0xFFFF, sum = 0
4364 11:52:17.974301 5, 0xFFFF, sum = 0
4365 11:52:17.974405 6, 0xFFFF, sum = 0
4366 11:52:17.977631 7, 0xFFFF, sum = 0
4367 11:52:17.977709 8, 0x0, sum = 1
4368 11:52:17.981134 9, 0x0, sum = 2
4369 11:52:17.981207 10, 0x0, sum = 3
4370 11:52:17.984723 11, 0x0, sum = 4
4371 11:52:17.984806 best_step = 9
4372 11:52:17.984871
4373 11:52:17.984931 ==
4374 11:52:17.987487 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 11:52:17.990996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:52:17.994517 ==
4377 11:52:17.994598 RX Vref Scan: 0
4378 11:52:17.994662
4379 11:52:17.997484 RX Vref 0 -> 0, step: 1
4380 11:52:17.997566
4381 11:52:18.001087 RX Delay -179 -> 252, step: 8
4382 11:52:18.004344 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4383 11:52:18.007524 iDelay=205, Bit 1, Center 40 (-115 ~ 196) 312
4384 11:52:18.014350 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4385 11:52:18.017588 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4386 11:52:18.021099 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4387 11:52:18.024774 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4388 11:52:18.027579 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4389 11:52:18.034646 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4390 11:52:18.037514 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4391 11:52:18.041120 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4392 11:52:18.044729 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4393 11:52:18.051229 iDelay=205, Bit 11, Center 24 (-123 ~ 172) 296
4394 11:52:18.054775 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4395 11:52:18.057712 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4396 11:52:18.061319 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4397 11:52:18.067919 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4398 11:52:18.068000 ==
4399 11:52:18.071469 Dram Type= 6, Freq= 0, CH_0, rank 1
4400 11:52:18.074761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 11:52:18.074844 ==
4402 11:52:18.074948 DQS Delay:
4403 11:52:18.078148 DQS0 = 0, DQS1 = 0
4404 11:52:18.078253 DQM Delay:
4405 11:52:18.081391 DQM0 = 39, DQM1 = 33
4406 11:52:18.081497 DQ Delay:
4407 11:52:18.084274 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =40
4408 11:52:18.087758 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =48
4409 11:52:18.091373 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4410 11:52:18.094486 DQ12 =36, DQ13 =40, DQ14 =40, DQ15 =44
4411 11:52:18.094559
4412 11:52:18.094636
4413 11:52:18.100882 [DQSOSCAuto] RK1, (LSB)MR18= 0x4f31, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4414 11:52:18.104292 CH0 RK1: MR19=808, MR18=4F31
4415 11:52:18.111099 CH0_RK1: MR19=0x808, MR18=0x4F31, DQSOSC=394, MR23=63, INC=168, DEC=112
4416 11:52:18.114504 [RxdqsGatingPostProcess] freq 600
4417 11:52:18.121041 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4418 11:52:18.121122 Pre-setting of DQS Precalculation
4419 11:52:18.128297 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4420 11:52:18.128421 ==
4421 11:52:18.131477 Dram Type= 6, Freq= 0, CH_1, rank 0
4422 11:52:18.134699 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 11:52:18.134779 ==
4424 11:52:18.141014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4425 11:52:18.147981 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4426 11:52:18.151157 [CA 0] Center 35 (5~66) winsize 62
4427 11:52:18.154686 [CA 1] Center 35 (5~66) winsize 62
4428 11:52:18.158185 [CA 2] Center 34 (4~64) winsize 61
4429 11:52:18.161110 [CA 3] Center 33 (3~64) winsize 62
4430 11:52:18.164738 [CA 4] Center 34 (3~65) winsize 63
4431 11:52:18.168259 [CA 5] Center 33 (2~64) winsize 63
4432 11:52:18.168338
4433 11:52:18.171166 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4434 11:52:18.171243
4435 11:52:18.174685 [CATrainingPosCal] consider 1 rank data
4436 11:52:18.178303 u2DelayCellTimex100 = 270/100 ps
4437 11:52:18.181169 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 11:52:18.184907 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4439 11:52:18.188095 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4440 11:52:18.191578 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4441 11:52:18.194665 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4442 11:52:18.198090 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4443 11:52:18.198167
4444 11:52:18.201334 CA PerBit enable=1, Macro0, CA PI delay=33
4445 11:52:18.201419
4446 11:52:18.204691 [CBTSetCACLKResult] CA Dly = 33
4447 11:52:18.208074 CS Dly: 5 (0~36)
4448 11:52:18.208149 ==
4449 11:52:18.211481 Dram Type= 6, Freq= 0, CH_1, rank 1
4450 11:52:18.214496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4451 11:52:18.214573 ==
4452 11:52:18.221471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4453 11:52:18.227780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4454 11:52:18.231450 [CA 0] Center 35 (5~66) winsize 62
4455 11:52:18.234909 [CA 1] Center 35 (5~66) winsize 62
4456 11:52:18.237992 [CA 2] Center 34 (4~65) winsize 62
4457 11:52:18.241169 [CA 3] Center 34 (3~65) winsize 63
4458 11:52:18.244614 [CA 4] Center 34 (3~65) winsize 63
4459 11:52:18.248184 [CA 5] Center 33 (3~64) winsize 62
4460 11:52:18.248275
4461 11:52:18.251198 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4462 11:52:18.251282
4463 11:52:18.255017 [CATrainingPosCal] consider 2 rank data
4464 11:52:18.258134 u2DelayCellTimex100 = 270/100 ps
4465 11:52:18.261663 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4466 11:52:18.264675 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4467 11:52:18.267686 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4468 11:52:18.271364 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4469 11:52:18.274879 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4470 11:52:18.277734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4471 11:52:18.277815
4472 11:52:18.281192 CA PerBit enable=1, Macro0, CA PI delay=33
4473 11:52:18.284400
4474 11:52:18.284474 [CBTSetCACLKResult] CA Dly = 33
4475 11:52:18.288008 CS Dly: 5 (0~36)
4476 11:52:18.288105
4477 11:52:18.291113 ----->DramcWriteLeveling(PI) begin...
4478 11:52:18.291221 ==
4479 11:52:18.294661 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 11:52:18.298162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 11:52:18.298264 ==
4482 11:52:18.301324 Write leveling (Byte 0): 32 => 32
4483 11:52:18.304700 Write leveling (Byte 1): 32 => 32
4484 11:52:18.307771 DramcWriteLeveling(PI) end<-----
4485 11:52:18.307871
4486 11:52:18.307969 ==
4487 11:52:18.311213 Dram Type= 6, Freq= 0, CH_1, rank 0
4488 11:52:18.314949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4489 11:52:18.315056 ==
4490 11:52:18.318108 [Gating] SW mode calibration
4491 11:52:18.324742 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4492 11:52:18.331778 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4493 11:52:18.335068 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4494 11:52:18.338041 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4495 11:52:18.345076 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4496 11:52:18.348439 0 9 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4497 11:52:18.351620 0 9 16 | B1->B0 | 2d2d 2a2a | 0 0 | (0 0) (0 0)
4498 11:52:18.358463 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 11:52:18.361947 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 11:52:18.365127 0 9 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4501 11:52:18.371483 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4502 11:52:18.374999 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4503 11:52:18.378217 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4504 11:52:18.384921 0 10 12 | B1->B0 | 2727 2424 | 0 1 | (0 0) (0 0)
4505 11:52:18.388645 0 10 16 | B1->B0 | 3e3e 4343 | 1 0 | (0 0) (0 0)
4506 11:52:18.391424 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 11:52:18.398445 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 11:52:18.401842 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 11:52:18.405359 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:52:18.411935 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4511 11:52:18.415430 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4512 11:52:18.418450 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4513 11:52:18.422179 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:52:18.428905 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:52:18.431707 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:52:18.435050 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 11:52:18.441605 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 11:52:18.445195 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 11:52:18.448695 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 11:52:18.454953 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 11:52:18.458339 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 11:52:18.461832 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 11:52:18.468446 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 11:52:18.472208 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 11:52:18.475084 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 11:52:18.481993 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 11:52:18.485724 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 11:52:18.488900 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4529 11:52:18.491972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4530 11:52:18.495389 Total UI for P1: 0, mck2ui 16
4531 11:52:18.498909 best dqsien dly found for B0: ( 0, 13, 14)
4532 11:52:18.502252 Total UI for P1: 0, mck2ui 16
4533 11:52:18.505232 best dqsien dly found for B1: ( 0, 13, 12)
4534 11:52:18.508967 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4535 11:52:18.515478 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4536 11:52:18.515598
4537 11:52:18.518515 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4538 11:52:18.522172 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4539 11:52:18.525079 [Gating] SW calibration Done
4540 11:52:18.525156 ==
4541 11:52:18.528727 Dram Type= 6, Freq= 0, CH_1, rank 0
4542 11:52:18.532141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4543 11:52:18.532218 ==
4544 11:52:18.532283 RX Vref Scan: 0
4545 11:52:18.535580
4546 11:52:18.535660 RX Vref 0 -> 0, step: 1
4547 11:52:18.535723
4548 11:52:18.538668 RX Delay -230 -> 252, step: 16
4549 11:52:18.542046 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4550 11:52:18.548773 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4551 11:52:18.552103 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4552 11:52:18.555305 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4553 11:52:18.558796 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4554 11:52:18.562436 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4555 11:52:18.569378 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4556 11:52:18.571876 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4557 11:52:18.575304 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4558 11:52:18.579217 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4559 11:52:18.582182 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4560 11:52:18.588724 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4561 11:52:18.592350 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4562 11:52:18.595457 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4563 11:52:18.598955 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4564 11:52:18.605926 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4565 11:52:18.606010 ==
4566 11:52:18.609069 Dram Type= 6, Freq= 0, CH_1, rank 0
4567 11:52:18.612612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4568 11:52:18.612693 ==
4569 11:52:18.612757 DQS Delay:
4570 11:52:18.615893 DQS0 = 0, DQS1 = 0
4571 11:52:18.615972 DQM Delay:
4572 11:52:18.619013 DQM0 = 44, DQM1 = 35
4573 11:52:18.619091 DQ Delay:
4574 11:52:18.622670 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4575 11:52:18.625590 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4576 11:52:18.629278 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =33
4577 11:52:18.632241 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4578 11:52:18.632315
4579 11:52:18.632376
4580 11:52:18.632436 ==
4581 11:52:18.635953 Dram Type= 6, Freq= 0, CH_1, rank 0
4582 11:52:18.639111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4583 11:52:18.639189 ==
4584 11:52:18.639256
4585 11:52:18.639314
4586 11:52:18.642508 TX Vref Scan disable
4587 11:52:18.645740 == TX Byte 0 ==
4588 11:52:18.649321 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4589 11:52:18.652364 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4590 11:52:18.655931 == TX Byte 1 ==
4591 11:52:18.658866 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4592 11:52:18.662585 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4593 11:52:18.662686 ==
4594 11:52:18.665776 Dram Type= 6, Freq= 0, CH_1, rank 0
4595 11:52:18.672622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4596 11:52:18.672708 ==
4597 11:52:18.672774
4598 11:52:18.672832
4599 11:52:18.672894 TX Vref Scan disable
4600 11:52:18.676259 == TX Byte 0 ==
4601 11:52:18.680182 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4602 11:52:18.683191 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4603 11:52:18.686257 == TX Byte 1 ==
4604 11:52:18.689796 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4605 11:52:18.693576 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4606 11:52:18.696345
4607 11:52:18.696425 [DATLAT]
4608 11:52:18.696489 Freq=600, CH1 RK0
4609 11:52:18.696551
4610 11:52:18.699768 DATLAT Default: 0x9
4611 11:52:18.699862 0, 0xFFFF, sum = 0
4612 11:52:18.703232 1, 0xFFFF, sum = 0
4613 11:52:18.703304 2, 0xFFFF, sum = 0
4614 11:52:18.706172 3, 0xFFFF, sum = 0
4615 11:52:18.706241 4, 0xFFFF, sum = 0
4616 11:52:18.709805 5, 0xFFFF, sum = 0
4617 11:52:18.709877 6, 0xFFFF, sum = 0
4618 11:52:18.713073 7, 0xFFFF, sum = 0
4619 11:52:18.713150 8, 0x0, sum = 1
4620 11:52:18.716577 9, 0x0, sum = 2
4621 11:52:18.716650 10, 0x0, sum = 3
4622 11:52:18.720138 11, 0x0, sum = 4
4623 11:52:18.720210 best_step = 9
4624 11:52:18.720277
4625 11:52:18.720339 ==
4626 11:52:18.723175 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 11:52:18.730294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 11:52:18.730371 ==
4629 11:52:18.730441 RX Vref Scan: 1
4630 11:52:18.730503
4631 11:52:18.733284 RX Vref 0 -> 0, step: 1
4632 11:52:18.733352
4633 11:52:18.737166 RX Delay -195 -> 252, step: 8
4634 11:52:18.737235
4635 11:52:18.739912 Set Vref, RX VrefLevel [Byte0]: 60
4636 11:52:18.743492 [Byte1]: 53
4637 11:52:18.743567
4638 11:52:18.746519 Final RX Vref Byte 0 = 60 to rank0
4639 11:52:18.749772 Final RX Vref Byte 1 = 53 to rank0
4640 11:52:18.753279 Final RX Vref Byte 0 = 60 to rank1
4641 11:52:18.756960 Final RX Vref Byte 1 = 53 to rank1==
4642 11:52:18.759938 Dram Type= 6, Freq= 0, CH_1, rank 0
4643 11:52:18.763486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 11:52:18.763570 ==
4645 11:52:18.766452 DQS Delay:
4646 11:52:18.766524 DQS0 = 0, DQS1 = 0
4647 11:52:18.766590 DQM Delay:
4648 11:52:18.769955 DQM0 = 40, DQM1 = 34
4649 11:52:18.770027 DQ Delay:
4650 11:52:18.773531 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4651 11:52:18.777114 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4652 11:52:18.780009 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =32
4653 11:52:18.783603 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =40
4654 11:52:18.783683
4655 11:52:18.783746
4656 11:52:18.793219 [DQSOSCAuto] RK0, (LSB)MR18= 0x480e, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 396 ps
4657 11:52:18.793294 CH1 RK0: MR19=808, MR18=480E
4658 11:52:18.799895 CH1_RK0: MR19=0x808, MR18=0x480E, DQSOSC=396, MR23=63, INC=167, DEC=111
4659 11:52:18.799973
4660 11:52:18.803250 ----->DramcWriteLeveling(PI) begin...
4661 11:52:18.803331 ==
4662 11:52:18.806580 Dram Type= 6, Freq= 0, CH_1, rank 1
4663 11:52:18.813340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4664 11:52:18.813421 ==
4665 11:52:18.816676 Write leveling (Byte 0): 28 => 28
4666 11:52:18.820351 Write leveling (Byte 1): 29 => 29
4667 11:52:18.820432 DramcWriteLeveling(PI) end<-----
4668 11:52:18.820494
4669 11:52:18.823785 ==
4670 11:52:18.823869 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 11:52:18.830294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 11:52:18.830372 ==
4673 11:52:18.833966 [Gating] SW mode calibration
4674 11:52:18.840582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4675 11:52:18.843935 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4676 11:52:18.850625 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4677 11:52:18.854052 0 9 4 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
4678 11:52:18.856939 0 9 8 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 0)
4679 11:52:18.860370 0 9 12 | B1->B0 | 3232 2c2c | 0 0 | (0 1) (0 0)
4680 11:52:18.866873 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4681 11:52:18.870513 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 11:52:18.873521 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 11:52:18.880482 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 11:52:18.883910 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4685 11:52:18.887204 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4686 11:52:18.893575 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4687 11:52:18.897239 0 10 12 | B1->B0 | 2d2d 3939 | 0 1 | (0 0) (0 0)
4688 11:52:18.900766 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4689 11:52:18.907104 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:52:18.910305 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 11:52:18.913571 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 11:52:18.920603 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4693 11:52:18.923799 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4694 11:52:18.927203 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4695 11:52:18.933896 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4696 11:52:18.937279 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:52:18.940339 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:52:18.947432 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:52:18.950441 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 11:52:18.953964 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 11:52:18.957288 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 11:52:18.963915 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 11:52:18.967494 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 11:52:18.970710 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 11:52:18.977011 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 11:52:18.980578 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 11:52:18.984161 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 11:52:18.990437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 11:52:18.993627 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 11:52:18.997520 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 11:52:19.003857 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4712 11:52:19.003935 Total UI for P1: 0, mck2ui 16
4713 11:52:19.010849 best dqsien dly found for B0: ( 0, 13, 10)
4714 11:52:19.014047 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4715 11:52:19.017209 Total UI for P1: 0, mck2ui 16
4716 11:52:19.020433 best dqsien dly found for B1: ( 0, 13, 12)
4717 11:52:19.023788 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4718 11:52:19.026824 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4719 11:52:19.026943
4720 11:52:19.030565 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4721 11:52:19.033928 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4722 11:52:19.037101 [Gating] SW calibration Done
4723 11:52:19.037179 ==
4724 11:52:19.040212 Dram Type= 6, Freq= 0, CH_1, rank 1
4725 11:52:19.043913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 11:52:19.047022 ==
4727 11:52:19.047101 RX Vref Scan: 0
4728 11:52:19.047163
4729 11:52:19.050578 RX Vref 0 -> 0, step: 1
4730 11:52:19.050679
4731 11:52:19.053746 RX Delay -230 -> 252, step: 16
4732 11:52:19.056927 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4733 11:52:19.060176 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4734 11:52:19.063983 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4735 11:52:19.070552 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4736 11:52:19.073948 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4737 11:52:19.076992 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4738 11:52:19.080383 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4739 11:52:19.083579 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4740 11:52:19.090541 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4741 11:52:19.093375 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4742 11:52:19.096903 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4743 11:52:19.100558 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4744 11:52:19.104007 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4745 11:52:19.110406 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4746 11:52:19.113812 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4747 11:52:19.116926 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4748 11:52:19.117009 ==
4749 11:52:19.120217 Dram Type= 6, Freq= 0, CH_1, rank 1
4750 11:52:19.127136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4751 11:52:19.127221 ==
4752 11:52:19.127283 DQS Delay:
4753 11:52:19.127344 DQS0 = 0, DQS1 = 0
4754 11:52:19.130795 DQM Delay:
4755 11:52:19.130933 DQM0 = 41, DQM1 = 36
4756 11:52:19.133686 DQ Delay:
4757 11:52:19.137125 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4758 11:52:19.137205 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4759 11:52:19.140452 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4760 11:52:19.143698 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4761 11:52:19.143768
4762 11:52:19.147243
4763 11:52:19.147339 ==
4764 11:52:19.150676 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 11:52:19.153795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 11:52:19.153910 ==
4767 11:52:19.154040
4768 11:52:19.154158
4769 11:52:19.157056 TX Vref Scan disable
4770 11:52:19.157169 == TX Byte 0 ==
4771 11:52:19.163943 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4772 11:52:19.167382 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4773 11:52:19.167464 == TX Byte 1 ==
4774 11:52:19.174369 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4775 11:52:19.177364 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4776 11:52:19.177447 ==
4777 11:52:19.180779 Dram Type= 6, Freq= 0, CH_1, rank 1
4778 11:52:19.183920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4779 11:52:19.184006 ==
4780 11:52:19.184065
4781 11:52:19.184121
4782 11:52:19.187369 TX Vref Scan disable
4783 11:52:19.190529 == TX Byte 0 ==
4784 11:52:19.194282 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4785 11:52:19.197024 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4786 11:52:19.200791 == TX Byte 1 ==
4787 11:52:19.203788 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4788 11:52:19.207248 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4789 11:52:19.207321
4790 11:52:19.210545 [DATLAT]
4791 11:52:19.210647 Freq=600, CH1 RK1
4792 11:52:19.210737
4793 11:52:19.213826 DATLAT Default: 0x9
4794 11:52:19.213901 0, 0xFFFF, sum = 0
4795 11:52:19.217498 1, 0xFFFF, sum = 0
4796 11:52:19.217603 2, 0xFFFF, sum = 0
4797 11:52:19.220597 3, 0xFFFF, sum = 0
4798 11:52:19.220674 4, 0xFFFF, sum = 0
4799 11:52:19.223976 5, 0xFFFF, sum = 0
4800 11:52:19.224052 6, 0xFFFF, sum = 0
4801 11:52:19.227748 7, 0xFFFF, sum = 0
4802 11:52:19.227817 8, 0x0, sum = 1
4803 11:52:19.231063 9, 0x0, sum = 2
4804 11:52:19.231131 10, 0x0, sum = 3
4805 11:52:19.233922 11, 0x0, sum = 4
4806 11:52:19.233992 best_step = 9
4807 11:52:19.234058
4808 11:52:19.234118 ==
4809 11:52:19.237427 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 11:52:19.240817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 11:52:19.240888 ==
4812 11:52:19.243967 RX Vref Scan: 0
4813 11:52:19.244034
4814 11:52:19.247013 RX Vref 0 -> 0, step: 1
4815 11:52:19.247086
4816 11:52:19.247185 RX Delay -195 -> 252, step: 8
4817 11:52:19.255581 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4818 11:52:19.258514 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4819 11:52:19.262294 iDelay=205, Bit 2, Center 28 (-123 ~ 180) 304
4820 11:52:19.265401 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4821 11:52:19.272104 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4822 11:52:19.275248 iDelay=205, Bit 5, Center 52 (-99 ~ 204) 304
4823 11:52:19.278560 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4824 11:52:19.282042 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4825 11:52:19.285579 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4826 11:52:19.292554 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4827 11:52:19.295370 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4828 11:52:19.299004 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4829 11:52:19.302245 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4830 11:52:19.308568 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4831 11:52:19.312361 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4832 11:52:19.315685 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4833 11:52:19.315786 ==
4834 11:52:19.319157 Dram Type= 6, Freq= 0, CH_1, rank 1
4835 11:52:19.322406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4836 11:52:19.322480 ==
4837 11:52:19.325967 DQS Delay:
4838 11:52:19.326051 DQS0 = 0, DQS1 = 0
4839 11:52:19.329394 DQM Delay:
4840 11:52:19.329478 DQM0 = 39, DQM1 = 32
4841 11:52:19.329563 DQ Delay:
4842 11:52:19.332069 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =36
4843 11:52:19.335545 DQ4 =40, DQ5 =52, DQ6 =48, DQ7 =36
4844 11:52:19.339057 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =24
4845 11:52:19.342001 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4846 11:52:19.342086
4847 11:52:19.342185
4848 11:52:19.352601 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c4a, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
4849 11:52:19.355626 CH1 RK1: MR19=808, MR18=3C4A
4850 11:52:19.359150 CH1_RK1: MR19=0x808, MR18=0x3C4A, DQSOSC=395, MR23=63, INC=168, DEC=112
4851 11:52:19.362316 [RxdqsGatingPostProcess] freq 600
4852 11:52:19.369225 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4853 11:52:19.372330 Pre-setting of DQS Precalculation
4854 11:52:19.376349 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4855 11:52:19.382570 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4856 11:52:19.392554 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4857 11:52:19.392634
4858 11:52:19.392701
4859 11:52:19.395804 [Calibration Summary] 1200 Mbps
4860 11:52:19.395912 CH 0, Rank 0
4861 11:52:19.399317 SW Impedance : PASS
4862 11:52:19.399423 DUTY Scan : NO K
4863 11:52:19.402430 ZQ Calibration : PASS
4864 11:52:19.405781 Jitter Meter : NO K
4865 11:52:19.405855 CBT Training : PASS
4866 11:52:19.409300 Write leveling : PASS
4867 11:52:19.409374 RX DQS gating : PASS
4868 11:52:19.412326 RX DQ/DQS(RDDQC) : PASS
4869 11:52:19.416002 TX DQ/DQS : PASS
4870 11:52:19.416084 RX DATLAT : PASS
4871 11:52:19.418928 RX DQ/DQS(Engine): PASS
4872 11:52:19.422662 TX OE : NO K
4873 11:52:19.422752 All Pass.
4874 11:52:19.422820
4875 11:52:19.422906 CH 0, Rank 1
4876 11:52:19.426065 SW Impedance : PASS
4877 11:52:19.429530 DUTY Scan : NO K
4878 11:52:19.429630 ZQ Calibration : PASS
4879 11:52:19.432539 Jitter Meter : NO K
4880 11:52:19.436327 CBT Training : PASS
4881 11:52:19.436410 Write leveling : PASS
4882 11:52:19.439176 RX DQS gating : PASS
4883 11:52:19.442602 RX DQ/DQS(RDDQC) : PASS
4884 11:52:19.442681 TX DQ/DQS : PASS
4885 11:52:19.446311 RX DATLAT : PASS
4886 11:52:19.446388 RX DQ/DQS(Engine): PASS
4887 11:52:19.449166 TX OE : NO K
4888 11:52:19.449237 All Pass.
4889 11:52:19.449297
4890 11:52:19.452201 CH 1, Rank 0
4891 11:52:19.452274 SW Impedance : PASS
4892 11:52:19.455687 DUTY Scan : NO K
4893 11:52:19.459339 ZQ Calibration : PASS
4894 11:52:19.459418 Jitter Meter : NO K
4895 11:52:19.462824 CBT Training : PASS
4896 11:52:19.465669 Write leveling : PASS
4897 11:52:19.465743 RX DQS gating : PASS
4898 11:52:19.468933 RX DQ/DQS(RDDQC) : PASS
4899 11:52:19.472190 TX DQ/DQS : PASS
4900 11:52:19.472293 RX DATLAT : PASS
4901 11:52:19.475640 RX DQ/DQS(Engine): PASS
4902 11:52:19.479560 TX OE : NO K
4903 11:52:19.479658 All Pass.
4904 11:52:19.479753
4905 11:52:19.479831 CH 1, Rank 1
4906 11:52:19.482574 SW Impedance : PASS
4907 11:52:19.486091 DUTY Scan : NO K
4908 11:52:19.486201 ZQ Calibration : PASS
4909 11:52:19.489336 Jitter Meter : NO K
4910 11:52:19.489469 CBT Training : PASS
4911 11:52:19.493151 Write leveling : PASS
4912 11:52:19.495650 RX DQS gating : PASS
4913 11:52:19.495724 RX DQ/DQS(RDDQC) : PASS
4914 11:52:19.499539 TX DQ/DQS : PASS
4915 11:52:19.502742 RX DATLAT : PASS
4916 11:52:19.502834 RX DQ/DQS(Engine): PASS
4917 11:52:19.505843 TX OE : NO K
4918 11:52:19.505963 All Pass.
4919 11:52:19.506068
4920 11:52:19.509480 DramC Write-DBI off
4921 11:52:19.512568 PER_BANK_REFRESH: Hybrid Mode
4922 11:52:19.512697 TX_TRACKING: ON
4923 11:52:19.522613 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4924 11:52:19.525657 [FAST_K] Save calibration result to emmc
4925 11:52:19.528924 dramc_set_vcore_voltage set vcore to 662500
4926 11:52:19.532550 Read voltage for 933, 3
4927 11:52:19.532628 Vio18 = 0
4928 11:52:19.532694 Vcore = 662500
4929 11:52:19.536096 Vdram = 0
4930 11:52:19.536172 Vddq = 0
4931 11:52:19.536233 Vmddr = 0
4932 11:52:19.542600 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4933 11:52:19.545877 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4934 11:52:19.549439 MEM_TYPE=3, freq_sel=17
4935 11:52:19.552412 sv_algorithm_assistance_LP4_1600
4936 11:52:19.556087 ============ PULL DRAM RESETB DOWN ============
4937 11:52:19.559142 ========== PULL DRAM RESETB DOWN end =========
4938 11:52:19.565966 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4939 11:52:19.569191 ===================================
4940 11:52:19.569264 LPDDR4 DRAM CONFIGURATION
4941 11:52:19.572678 ===================================
4942 11:52:19.576128 EX_ROW_EN[0] = 0x0
4943 11:52:19.579532 EX_ROW_EN[1] = 0x0
4944 11:52:19.579609 LP4Y_EN = 0x0
4945 11:52:19.582589 WORK_FSP = 0x0
4946 11:52:19.582656 WL = 0x3
4947 11:52:19.586164 RL = 0x3
4948 11:52:19.586229 BL = 0x2
4949 11:52:19.589383 RPST = 0x0
4950 11:52:19.589454 RD_PRE = 0x0
4951 11:52:19.592564 WR_PRE = 0x1
4952 11:52:19.592632 WR_PST = 0x0
4953 11:52:19.596097 DBI_WR = 0x0
4954 11:52:19.596174 DBI_RD = 0x0
4955 11:52:19.599331 OTF = 0x1
4956 11:52:19.602894 ===================================
4957 11:52:19.606167 ===================================
4958 11:52:19.606238 ANA top config
4959 11:52:19.609435 ===================================
4960 11:52:19.612779 DLL_ASYNC_EN = 0
4961 11:52:19.616231 ALL_SLAVE_EN = 1
4962 11:52:19.616313 NEW_RANK_MODE = 1
4963 11:52:19.619828 DLL_IDLE_MODE = 1
4964 11:52:19.622842 LP45_APHY_COMB_EN = 1
4965 11:52:19.626465 TX_ODT_DIS = 1
4966 11:52:19.626539 NEW_8X_MODE = 1
4967 11:52:19.629476 ===================================
4968 11:52:19.632837 ===================================
4969 11:52:19.636420 data_rate = 1866
4970 11:52:19.640072 CKR = 1
4971 11:52:19.643482 DQ_P2S_RATIO = 8
4972 11:52:19.646361 ===================================
4973 11:52:19.650149 CA_P2S_RATIO = 8
4974 11:52:19.653239 DQ_CA_OPEN = 0
4975 11:52:19.653313 DQ_SEMI_OPEN = 0
4976 11:52:19.657049 CA_SEMI_OPEN = 0
4977 11:52:19.659813 CA_FULL_RATE = 0
4978 11:52:19.663521 DQ_CKDIV4_EN = 1
4979 11:52:19.666407 CA_CKDIV4_EN = 1
4980 11:52:19.670038 CA_PREDIV_EN = 0
4981 11:52:19.670112 PH8_DLY = 0
4982 11:52:19.673385 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4983 11:52:19.676399 DQ_AAMCK_DIV = 4
4984 11:52:19.679872 CA_AAMCK_DIV = 4
4985 11:52:19.683596 CA_ADMCK_DIV = 4
4986 11:52:19.683664 DQ_TRACK_CA_EN = 0
4987 11:52:19.686830 CA_PICK = 933
4988 11:52:19.690049 CA_MCKIO = 933
4989 11:52:19.693552 MCKIO_SEMI = 0
4990 11:52:19.696620 PLL_FREQ = 3732
4991 11:52:19.700100 DQ_UI_PI_RATIO = 32
4992 11:52:19.703364 CA_UI_PI_RATIO = 0
4993 11:52:19.706670 ===================================
4994 11:52:19.710233 ===================================
4995 11:52:19.710309 memory_type:LPDDR4
4996 11:52:19.713394 GP_NUM : 10
4997 11:52:19.716562 SRAM_EN : 1
4998 11:52:19.716644 MD32_EN : 0
4999 11:52:19.719934 ===================================
5000 11:52:19.723710 [ANA_INIT] >>>>>>>>>>>>>>
5001 11:52:19.727016 <<<<<< [CONFIGURE PHASE]: ANA_TX
5002 11:52:19.729822 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5003 11:52:19.733435 ===================================
5004 11:52:19.736837 data_rate = 1866,PCW = 0X8f00
5005 11:52:19.736918 ===================================
5006 11:52:19.743309 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5007 11:52:19.746905 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5008 11:52:19.753827 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 11:52:19.756796 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5010 11:52:19.760429 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5011 11:52:19.763879 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5012 11:52:19.766648 [ANA_INIT] flow start
5013 11:52:19.770368 [ANA_INIT] PLL >>>>>>>>
5014 11:52:19.770448 [ANA_INIT] PLL <<<<<<<<
5015 11:52:19.773819 [ANA_INIT] MIDPI >>>>>>>>
5016 11:52:19.776789 [ANA_INIT] MIDPI <<<<<<<<
5017 11:52:19.776869 [ANA_INIT] DLL >>>>>>>>
5018 11:52:19.780228 [ANA_INIT] flow end
5019 11:52:19.783840 ============ LP4 DIFF to SE enter ============
5020 11:52:19.786846 ============ LP4 DIFF to SE exit ============
5021 11:52:19.790194 [ANA_INIT] <<<<<<<<<<<<<
5022 11:52:19.793907 [Flow] Enable top DCM control >>>>>
5023 11:52:19.796953 [Flow] Enable top DCM control <<<<<
5024 11:52:19.800429 Enable DLL master slave shuffle
5025 11:52:19.806993 ==============================================================
5026 11:52:19.807077 Gating Mode config
5027 11:52:19.814095 ==============================================================
5028 11:52:19.814209 Config description:
5029 11:52:19.823775 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5030 11:52:19.830181 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5031 11:52:19.837194 SELPH_MODE 0: By rank 1: By Phase
5032 11:52:19.840363 ==============================================================
5033 11:52:19.843611 GAT_TRACK_EN = 1
5034 11:52:19.846886 RX_GATING_MODE = 2
5035 11:52:19.850404 RX_GATING_TRACK_MODE = 2
5036 11:52:19.853948 SELPH_MODE = 1
5037 11:52:19.857141 PICG_EARLY_EN = 1
5038 11:52:19.860549 VALID_LAT_VALUE = 1
5039 11:52:19.863872 ==============================================================
5040 11:52:19.867109 Enter into Gating configuration >>>>
5041 11:52:19.870780 Exit from Gating configuration <<<<
5042 11:52:19.873867 Enter into DVFS_PRE_config >>>>>
5043 11:52:19.887123 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5044 11:52:19.887209 Exit from DVFS_PRE_config <<<<<
5045 11:52:19.890618 Enter into PICG configuration >>>>
5046 11:52:19.894142 Exit from PICG configuration <<<<
5047 11:52:19.897075 [RX_INPUT] configuration >>>>>
5048 11:52:19.900871 [RX_INPUT] configuration <<<<<
5049 11:52:19.907223 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5050 11:52:19.910747 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5051 11:52:19.917366 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5052 11:52:19.924367 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5053 11:52:19.931162 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 11:52:19.937405 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 11:52:19.940841 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5056 11:52:19.944392 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5057 11:52:19.947246 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5058 11:52:19.953983 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5059 11:52:19.957228 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5060 11:52:19.960529 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5061 11:52:19.964182 ===================================
5062 11:52:19.967346 LPDDR4 DRAM CONFIGURATION
5063 11:52:19.970759 ===================================
5064 11:52:19.970837 EX_ROW_EN[0] = 0x0
5065 11:52:19.974477 EX_ROW_EN[1] = 0x0
5066 11:52:19.974556 LP4Y_EN = 0x0
5067 11:52:19.977483 WORK_FSP = 0x0
5068 11:52:19.977568 WL = 0x3
5069 11:52:19.980845 RL = 0x3
5070 11:52:19.984337 BL = 0x2
5071 11:52:19.984419 RPST = 0x0
5072 11:52:19.987154 RD_PRE = 0x0
5073 11:52:19.987229 WR_PRE = 0x1
5074 11:52:19.990643 WR_PST = 0x0
5075 11:52:19.990718 DBI_WR = 0x0
5076 11:52:19.994148 DBI_RD = 0x0
5077 11:52:19.994222 OTF = 0x1
5078 11:52:19.997565 ===================================
5079 11:52:20.000538 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5080 11:52:20.007318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5081 11:52:20.010753 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5082 11:52:20.013889 ===================================
5083 11:52:20.017378 LPDDR4 DRAM CONFIGURATION
5084 11:52:20.020722 ===================================
5085 11:52:20.020804 EX_ROW_EN[0] = 0x10
5086 11:52:20.024328 EX_ROW_EN[1] = 0x0
5087 11:52:20.024400 LP4Y_EN = 0x0
5088 11:52:20.027041 WORK_FSP = 0x0
5089 11:52:20.027114 WL = 0x3
5090 11:52:20.030581 RL = 0x3
5091 11:52:20.030653 BL = 0x2
5092 11:52:20.034154 RPST = 0x0
5093 11:52:20.034233 RD_PRE = 0x0
5094 11:52:20.037562 WR_PRE = 0x1
5095 11:52:20.037635 WR_PST = 0x0
5096 11:52:20.040812 DBI_WR = 0x0
5097 11:52:20.040885 DBI_RD = 0x0
5098 11:52:20.044236 OTF = 0x1
5099 11:52:20.047731 ===================================
5100 11:52:20.054472 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5101 11:52:20.057391 nWR fixed to 30
5102 11:52:20.060694 [ModeRegInit_LP4] CH0 RK0
5103 11:52:20.060769 [ModeRegInit_LP4] CH0 RK1
5104 11:52:20.064011 [ModeRegInit_LP4] CH1 RK0
5105 11:52:20.067203 [ModeRegInit_LP4] CH1 RK1
5106 11:52:20.067292 match AC timing 9
5107 11:52:20.074105 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5108 11:52:20.077304 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5109 11:52:20.080810 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5110 11:52:20.087477 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5111 11:52:20.090767 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5112 11:52:20.090853 ==
5113 11:52:20.094218 Dram Type= 6, Freq= 0, CH_0, rank 0
5114 11:52:20.097108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5115 11:52:20.097189 ==
5116 11:52:20.104134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5117 11:52:20.110676 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5118 11:52:20.114331 [CA 0] Center 38 (7~69) winsize 63
5119 11:52:20.117234 [CA 1] Center 38 (7~69) winsize 63
5120 11:52:20.120976 [CA 2] Center 35 (5~66) winsize 62
5121 11:52:20.124429 [CA 3] Center 34 (4~65) winsize 62
5122 11:52:20.127298 [CA 4] Center 34 (4~65) winsize 62
5123 11:52:20.130659 [CA 5] Center 33 (3~64) winsize 62
5124 11:52:20.130744
5125 11:52:20.134122 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5126 11:52:20.134198
5127 11:52:20.137019 [CATrainingPosCal] consider 1 rank data
5128 11:52:20.140652 u2DelayCellTimex100 = 270/100 ps
5129 11:52:20.144234 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5130 11:52:20.147105 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5131 11:52:20.150761 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5132 11:52:20.153804 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5133 11:52:20.157335 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5134 11:52:20.161184 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5135 11:52:20.161258
5136 11:52:20.167235 CA PerBit enable=1, Macro0, CA PI delay=33
5137 11:52:20.167315
5138 11:52:20.167379 [CBTSetCACLKResult] CA Dly = 33
5139 11:52:20.170304 CS Dly: 6 (0~37)
5140 11:52:20.170375 ==
5141 11:52:20.173943 Dram Type= 6, Freq= 0, CH_0, rank 1
5142 11:52:20.177338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 11:52:20.177414 ==
5144 11:52:20.183858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5145 11:52:20.190326 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5146 11:52:20.194082 [CA 0] Center 38 (7~69) winsize 63
5147 11:52:20.197516 [CA 1] Center 38 (7~69) winsize 63
5148 11:52:20.200875 [CA 2] Center 35 (5~66) winsize 62
5149 11:52:20.203961 [CA 3] Center 35 (4~66) winsize 63
5150 11:52:20.207420 [CA 4] Center 33 (3~64) winsize 62
5151 11:52:20.210617 [CA 5] Center 33 (3~64) winsize 62
5152 11:52:20.210715
5153 11:52:20.214210 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5154 11:52:20.214283
5155 11:52:20.217433 [CATrainingPosCal] consider 2 rank data
5156 11:52:20.221097 u2DelayCellTimex100 = 270/100 ps
5157 11:52:20.224457 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5158 11:52:20.227195 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5159 11:52:20.230663 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5160 11:52:20.234396 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5161 11:52:20.237596 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5162 11:52:20.240637 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5163 11:52:20.240725
5164 11:52:20.247263 CA PerBit enable=1, Macro0, CA PI delay=33
5165 11:52:20.247337
5166 11:52:20.247398 [CBTSetCACLKResult] CA Dly = 33
5167 11:52:20.250689 CS Dly: 7 (0~39)
5168 11:52:20.250765
5169 11:52:20.254283 ----->DramcWriteLeveling(PI) begin...
5170 11:52:20.254353 ==
5171 11:52:20.257402 Dram Type= 6, Freq= 0, CH_0, rank 0
5172 11:52:20.260756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5173 11:52:20.260830 ==
5174 11:52:20.264171 Write leveling (Byte 0): 29 => 29
5175 11:52:20.267328 Write leveling (Byte 1): 28 => 28
5176 11:52:20.270975 DramcWriteLeveling(PI) end<-----
5177 11:52:20.271065
5178 11:52:20.271140 ==
5179 11:52:20.274272 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:52:20.277260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:52:20.277336 ==
5182 11:52:20.280795 [Gating] SW mode calibration
5183 11:52:20.287321 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5184 11:52:20.294194 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5185 11:52:20.297492 0 14 0 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
5186 11:52:20.304251 0 14 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
5187 11:52:20.307251 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 11:52:20.310649 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5189 11:52:20.317304 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 11:52:20.320554 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 11:52:20.324312 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 11:52:20.327640 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 11:52:20.334122 0 15 0 | B1->B0 | 3131 2929 | 1 0 | (1 0) (0 1)
5194 11:52:20.337559 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5195 11:52:20.341120 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 11:52:20.347393 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5197 11:52:20.351156 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 11:52:20.353915 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 11:52:20.360700 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 11:52:20.364367 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5201 11:52:20.367780 1 0 0 | B1->B0 | 3131 3c3c | 0 1 | (0 0) (0 0)
5202 11:52:20.374017 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5203 11:52:20.377710 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 11:52:20.380754 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5205 11:52:20.387425 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:52:20.390966 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 11:52:20.394479 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 11:52:20.400969 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 11:52:20.404480 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5210 11:52:20.407526 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5211 11:52:20.414271 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 11:52:20.417509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 11:52:20.421137 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 11:52:20.424360 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 11:52:20.430998 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 11:52:20.434471 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 11:52:20.437793 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 11:52:20.444225 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 11:52:20.447634 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 11:52:20.451278 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 11:52:20.457653 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 11:52:20.461233 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 11:52:20.464730 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 11:52:20.471723 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5225 11:52:20.474787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 11:52:20.478330 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5227 11:52:20.481477 Total UI for P1: 0, mck2ui 16
5228 11:52:20.484430 best dqsien dly found for B0: ( 1, 3, 2)
5229 11:52:20.488384 Total UI for P1: 0, mck2ui 16
5230 11:52:20.491210 best dqsien dly found for B1: ( 1, 3, 2)
5231 11:52:20.494703 best DQS0 dly(MCK, UI, PI) = (1, 3, 2)
5232 11:52:20.498382 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5233 11:52:20.498459
5234 11:52:20.501285 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 2)
5235 11:52:20.504996 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5236 11:52:20.508953 [Gating] SW calibration Done
5237 11:52:20.509032 ==
5238 11:52:20.511399 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 11:52:20.514849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 11:52:20.518496 ==
5241 11:52:20.518575 RX Vref Scan: 0
5242 11:52:20.518649
5243 11:52:20.521765 RX Vref 0 -> 0, step: 1
5244 11:52:20.521844
5245 11:52:20.521906 RX Delay -80 -> 252, step: 8
5246 11:52:20.529102 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5247 11:52:20.531709 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5248 11:52:20.535337 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5249 11:52:20.538166 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5250 11:52:20.541569 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5251 11:52:20.545786 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5252 11:52:20.551667 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5253 11:52:20.555139 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5254 11:52:20.558373 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5255 11:52:20.561870 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5256 11:52:20.565521 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5257 11:52:20.568539 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5258 11:52:20.575031 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5259 11:52:20.578680 iDelay=208, Bit 13, Center 91 (0 ~ 183) 184
5260 11:52:20.581793 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5261 11:52:20.585060 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5262 11:52:20.585161 ==
5263 11:52:20.588787 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 11:52:20.591978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 11:52:20.592059 ==
5266 11:52:20.595455 DQS Delay:
5267 11:52:20.595535 DQS0 = 0, DQS1 = 0
5268 11:52:20.598974 DQM Delay:
5269 11:52:20.599053 DQM0 = 99, DQM1 = 87
5270 11:52:20.599117 DQ Delay:
5271 11:52:20.601931 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5272 11:52:20.605462 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =103
5273 11:52:20.608442 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =79
5274 11:52:20.611777 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5275 11:52:20.611862
5276 11:52:20.615128
5277 11:52:20.615202 ==
5278 11:52:20.618623 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 11:52:20.622222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 11:52:20.622324 ==
5281 11:52:20.622419
5282 11:52:20.622503
5283 11:52:20.625122 TX Vref Scan disable
5284 11:52:20.625193 == TX Byte 0 ==
5285 11:52:20.631759 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5286 11:52:20.635437 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5287 11:52:20.635509 == TX Byte 1 ==
5288 11:52:20.641678 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5289 11:52:20.645278 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5290 11:52:20.645349 ==
5291 11:52:20.648852 Dram Type= 6, Freq= 0, CH_0, rank 0
5292 11:52:20.652274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 11:52:20.652347 ==
5294 11:52:20.652408
5295 11:52:20.652464
5296 11:52:20.655077 TX Vref Scan disable
5297 11:52:20.658602 == TX Byte 0 ==
5298 11:52:20.661790 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5299 11:52:20.665427 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5300 11:52:20.668471 == TX Byte 1 ==
5301 11:52:20.672166 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5302 11:52:20.675582 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5303 11:52:20.675656
5304 11:52:20.675717 [DATLAT]
5305 11:52:20.678584 Freq=933, CH0 RK0
5306 11:52:20.678687
5307 11:52:20.682578 DATLAT Default: 0xd
5308 11:52:20.682656 0, 0xFFFF, sum = 0
5309 11:52:20.685586 1, 0xFFFF, sum = 0
5310 11:52:20.685659 2, 0xFFFF, sum = 0
5311 11:52:20.689105 3, 0xFFFF, sum = 0
5312 11:52:20.689174 4, 0xFFFF, sum = 0
5313 11:52:20.692047 5, 0xFFFF, sum = 0
5314 11:52:20.692120 6, 0xFFFF, sum = 0
5315 11:52:20.695255 7, 0xFFFF, sum = 0
5316 11:52:20.695338 8, 0xFFFF, sum = 0
5317 11:52:20.698714 9, 0xFFFF, sum = 0
5318 11:52:20.698793 10, 0x0, sum = 1
5319 11:52:20.702490 11, 0x0, sum = 2
5320 11:52:20.702567 12, 0x0, sum = 3
5321 11:52:20.705606 13, 0x0, sum = 4
5322 11:52:20.705677 best_step = 11
5323 11:52:20.705736
5324 11:52:20.705807 ==
5325 11:52:20.709037 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 11:52:20.712567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 11:52:20.712642 ==
5328 11:52:20.715353 RX Vref Scan: 1
5329 11:52:20.715427
5330 11:52:20.718989 RX Vref 0 -> 0, step: 1
5331 11:52:20.719068
5332 11:52:20.719131 RX Delay -61 -> 252, step: 4
5333 11:52:20.719189
5334 11:52:20.722298 Set Vref, RX VrefLevel [Byte0]: 55
5335 11:52:20.725296 [Byte1]: 50
5336 11:52:20.730018
5337 11:52:20.730094 Final RX Vref Byte 0 = 55 to rank0
5338 11:52:20.733529 Final RX Vref Byte 1 = 50 to rank0
5339 11:52:20.736722 Final RX Vref Byte 0 = 55 to rank1
5340 11:52:20.740078 Final RX Vref Byte 1 = 50 to rank1==
5341 11:52:20.743471 Dram Type= 6, Freq= 0, CH_0, rank 0
5342 11:52:20.750049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 11:52:20.750137 ==
5344 11:52:20.750201 DQS Delay:
5345 11:52:20.750259 DQS0 = 0, DQS1 = 0
5346 11:52:20.753630 DQM Delay:
5347 11:52:20.753703 DQM0 = 96, DQM1 = 89
5348 11:52:20.757132 DQ Delay:
5349 11:52:20.760501 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5350 11:52:20.763505 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =102
5351 11:52:20.763581 DQ8 =78, DQ9 =76, DQ10 =88, DQ11 =82
5352 11:52:20.770120 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =98
5353 11:52:20.770195
5354 11:52:20.770257
5355 11:52:20.776946 [DQSOSCAuto] RK0, (LSB)MR18= 0x13fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 415 ps
5356 11:52:20.780029 CH0 RK0: MR19=504, MR18=13FE
5357 11:52:20.786793 CH0_RK0: MR19=0x504, MR18=0x13FE, DQSOSC=415, MR23=63, INC=62, DEC=41
5358 11:52:20.786916
5359 11:52:20.789964 ----->DramcWriteLeveling(PI) begin...
5360 11:52:20.790111 ==
5361 11:52:20.793427 Dram Type= 6, Freq= 0, CH_0, rank 1
5362 11:52:20.796653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5363 11:52:20.796727 ==
5364 11:52:20.799985 Write leveling (Byte 0): 29 => 29
5365 11:52:20.803692 Write leveling (Byte 1): 29 => 29
5366 11:52:20.807379 DramcWriteLeveling(PI) end<-----
5367 11:52:20.807508
5368 11:52:20.807600 ==
5369 11:52:20.810417 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 11:52:20.813320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 11:52:20.813394 ==
5372 11:52:20.816857 [Gating] SW mode calibration
5373 11:52:20.823804 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5374 11:52:20.830001 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5375 11:52:20.833683 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5376 11:52:20.837222 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5377 11:52:20.843463 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 11:52:20.847088 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5379 11:52:20.850632 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5380 11:52:20.856946 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5381 11:52:20.860181 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5382 11:52:20.863922 0 14 28 | B1->B0 | 3333 3030 | 0 0 | (1 0) (1 1)
5383 11:52:20.870688 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (0 0) (0 0)
5384 11:52:20.874006 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5385 11:52:20.877091 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 11:52:20.880710 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5387 11:52:20.887032 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5388 11:52:20.890421 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5389 11:52:20.893753 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5390 11:52:20.900394 0 15 28 | B1->B0 | 2929 3636 | 0 0 | (0 0) (0 0)
5391 11:52:20.903742 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5392 11:52:20.907329 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 11:52:20.914002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 11:52:20.917023 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 11:52:20.920727 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:52:20.927675 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5397 11:52:20.930354 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5398 11:52:20.934107 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5399 11:52:20.940406 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:52:20.943889 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5401 11:52:20.947611 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 11:52:20.953579 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 11:52:20.957193 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 11:52:20.960754 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 11:52:20.967507 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 11:52:20.970665 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 11:52:20.974182 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 11:52:20.977093 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 11:52:20.983705 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 11:52:20.987546 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 11:52:20.990390 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 11:52:20.997007 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 11:52:21.000543 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5414 11:52:21.003969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5415 11:52:21.010649 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5416 11:52:21.013780 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5417 11:52:21.017491 Total UI for P1: 0, mck2ui 16
5418 11:52:21.020547 best dqsien dly found for B0: ( 1, 2, 28)
5419 11:52:21.023625 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5420 11:52:21.027033 Total UI for P1: 0, mck2ui 16
5421 11:52:21.030525 best dqsien dly found for B1: ( 1, 3, 0)
5422 11:52:21.033719 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5423 11:52:21.037197 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5424 11:52:21.037293
5425 11:52:21.043965 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5426 11:52:21.047348 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5427 11:52:21.047427 [Gating] SW calibration Done
5428 11:52:21.047489 ==
5429 11:52:21.050803 Dram Type= 6, Freq= 0, CH_0, rank 1
5430 11:52:21.057401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5431 11:52:21.057485 ==
5432 11:52:21.057581 RX Vref Scan: 0
5433 11:52:21.057656
5434 11:52:21.060362 RX Vref 0 -> 0, step: 1
5435 11:52:21.060460
5436 11:52:21.063764 RX Delay -80 -> 252, step: 8
5437 11:52:21.067165 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5438 11:52:21.070554 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5439 11:52:21.074187 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5440 11:52:21.077939 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5441 11:52:21.083732 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5442 11:52:21.087327 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5443 11:52:21.090709 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5444 11:52:21.094396 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5445 11:52:21.097468 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5446 11:52:21.100804 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5447 11:52:21.107307 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5448 11:52:21.110820 iDelay=208, Bit 11, Center 75 (-16 ~ 167) 184
5449 11:52:21.114368 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5450 11:52:21.117695 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5451 11:52:21.120904 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5452 11:52:21.124164 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5453 11:52:21.127439 ==
5454 11:52:21.130980 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 11:52:21.134062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 11:52:21.134157 ==
5457 11:52:21.134227 DQS Delay:
5458 11:52:21.137624 DQS0 = 0, DQS1 = 0
5459 11:52:21.137713 DQM Delay:
5460 11:52:21.141220 DQM0 = 97, DQM1 = 86
5461 11:52:21.141296 DQ Delay:
5462 11:52:21.144489 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5463 11:52:21.147834 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5464 11:52:21.151036 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =75
5465 11:52:21.154369 DQ12 =87, DQ13 =95, DQ14 =99, DQ15 =95
5466 11:52:21.154461
5467 11:52:21.154526
5468 11:52:21.154591 ==
5469 11:52:21.157414 Dram Type= 6, Freq= 0, CH_0, rank 1
5470 11:52:21.161050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5471 11:52:21.161126 ==
5472 11:52:21.161212
5473 11:52:21.161277
5474 11:52:21.164486 TX Vref Scan disable
5475 11:52:21.167436 == TX Byte 0 ==
5476 11:52:21.170955 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5477 11:52:21.173954 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5478 11:52:21.177546 == TX Byte 1 ==
5479 11:52:21.180881 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5480 11:52:21.184539 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5481 11:52:21.184616 ==
5482 11:52:21.187278 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 11:52:21.190697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 11:52:21.190773 ==
5485 11:52:21.194341
5486 11:52:21.194429
5487 11:52:21.194494 TX Vref Scan disable
5488 11:52:21.197582 == TX Byte 0 ==
5489 11:52:21.200665 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5490 11:52:21.207476 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5491 11:52:21.207564 == TX Byte 1 ==
5492 11:52:21.210809 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5493 11:52:21.214404 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5494 11:52:21.217424
5495 11:52:21.217506 [DATLAT]
5496 11:52:21.217571 Freq=933, CH0 RK1
5497 11:52:21.217632
5498 11:52:21.221007 DATLAT Default: 0xb
5499 11:52:21.221089 0, 0xFFFF, sum = 0
5500 11:52:21.224280 1, 0xFFFF, sum = 0
5501 11:52:21.224365 2, 0xFFFF, sum = 0
5502 11:52:21.227870 3, 0xFFFF, sum = 0
5503 11:52:21.227959 4, 0xFFFF, sum = 0
5504 11:52:21.230764 5, 0xFFFF, sum = 0
5505 11:52:21.230882 6, 0xFFFF, sum = 0
5506 11:52:21.234297 7, 0xFFFF, sum = 0
5507 11:52:21.237694 8, 0xFFFF, sum = 0
5508 11:52:21.237776 9, 0xFFFF, sum = 0
5509 11:52:21.237842 10, 0x0, sum = 1
5510 11:52:21.240899 11, 0x0, sum = 2
5511 11:52:21.241011 12, 0x0, sum = 3
5512 11:52:21.244360 13, 0x0, sum = 4
5513 11:52:21.244452 best_step = 11
5514 11:52:21.244522
5515 11:52:21.244586 ==
5516 11:52:21.247713 Dram Type= 6, Freq= 0, CH_0, rank 1
5517 11:52:21.254272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 11:52:21.254358 ==
5519 11:52:21.254430 RX Vref Scan: 0
5520 11:52:21.254490
5521 11:52:21.258011 RX Vref 0 -> 0, step: 1
5522 11:52:21.258099
5523 11:52:21.261046 RX Delay -61 -> 252, step: 4
5524 11:52:21.264367 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5525 11:52:21.267749 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5526 11:52:21.274457 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5527 11:52:21.277453 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5528 11:52:21.281123 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5529 11:52:21.284307 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5530 11:52:21.288120 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5531 11:52:21.291145 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5532 11:52:21.297653 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5533 11:52:21.300883 iDelay=199, Bit 9, Center 78 (-13 ~ 170) 184
5534 11:52:21.304606 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5535 11:52:21.308247 iDelay=199, Bit 11, Center 80 (-5 ~ 166) 172
5536 11:52:21.311052 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5537 11:52:21.314710 iDelay=199, Bit 13, Center 90 (3 ~ 178) 176
5538 11:52:21.321240 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5539 11:52:21.324744 iDelay=199, Bit 15, Center 94 (7 ~ 182) 176
5540 11:52:21.324822 ==
5541 11:52:21.327666 Dram Type= 6, Freq= 0, CH_0, rank 1
5542 11:52:21.331109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 11:52:21.331197 ==
5544 11:52:21.331266 DQS Delay:
5545 11:52:21.334721 DQS0 = 0, DQS1 = 0
5546 11:52:21.334829 DQM Delay:
5547 11:52:21.337777 DQM0 = 95, DQM1 = 87
5548 11:52:21.337852 DQ Delay:
5549 11:52:21.341251 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5550 11:52:21.344623 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5551 11:52:21.348083 DQ8 =82, DQ9 =78, DQ10 =88, DQ11 =80
5552 11:52:21.350940 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94
5553 11:52:21.351047
5554 11:52:21.351138
5555 11:52:21.361600 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5556 11:52:21.361693 CH0 RK1: MR19=505, MR18=1D0B
5557 11:52:21.367863 CH0_RK1: MR19=0x505, MR18=0x1D0B, DQSOSC=412, MR23=63, INC=63, DEC=42
5558 11:52:21.371181 [RxdqsGatingPostProcess] freq 933
5559 11:52:21.377800 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5560 11:52:21.381462 best DQS0 dly(2T, 0.5T) = (0, 11)
5561 11:52:21.384489 best DQS1 dly(2T, 0.5T) = (0, 11)
5562 11:52:21.388034 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5563 11:52:21.391031 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5564 11:52:21.394694 best DQS0 dly(2T, 0.5T) = (0, 10)
5565 11:52:21.394805 best DQS1 dly(2T, 0.5T) = (0, 11)
5566 11:52:21.397612 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5567 11:52:21.401252 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5568 11:52:21.404784 Pre-setting of DQS Precalculation
5569 11:52:21.411122 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5570 11:52:21.411215 ==
5571 11:52:21.414620 Dram Type= 6, Freq= 0, CH_1, rank 0
5572 11:52:21.418255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 11:52:21.418367 ==
5574 11:52:21.424913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 11:52:21.427853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5576 11:52:21.432458 [CA 0] Center 36 (6~67) winsize 62
5577 11:52:21.436046 [CA 1] Center 36 (6~67) winsize 62
5578 11:52:21.439224 [CA 2] Center 34 (4~64) winsize 61
5579 11:52:21.442441 [CA 3] Center 33 (3~64) winsize 62
5580 11:52:21.445923 [CA 4] Center 34 (4~64) winsize 61
5581 11:52:21.449238 [CA 5] Center 33 (3~63) winsize 61
5582 11:52:21.449328
5583 11:52:21.452687 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5584 11:52:21.452770
5585 11:52:21.455592 [CATrainingPosCal] consider 1 rank data
5586 11:52:21.459243 u2DelayCellTimex100 = 270/100 ps
5587 11:52:21.462202 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5588 11:52:21.465739 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5589 11:52:21.472632 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5590 11:52:21.475479 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5591 11:52:21.479226 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 11:52:21.482273 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5593 11:52:21.482357
5594 11:52:21.485731 CA PerBit enable=1, Macro0, CA PI delay=33
5595 11:52:21.485846
5596 11:52:21.488955 [CBTSetCACLKResult] CA Dly = 33
5597 11:52:21.489043 CS Dly: 4 (0~35)
5598 11:52:21.489117 ==
5599 11:52:21.492718 Dram Type= 6, Freq= 0, CH_1, rank 1
5600 11:52:21.499077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5601 11:52:21.499159 ==
5602 11:52:21.502657 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5603 11:52:21.509237 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5604 11:52:21.512398 [CA 0] Center 36 (6~67) winsize 62
5605 11:52:21.516288 [CA 1] Center 36 (6~67) winsize 62
5606 11:52:21.518783 [CA 2] Center 34 (4~64) winsize 61
5607 11:52:21.522568 [CA 3] Center 33 (3~64) winsize 62
5608 11:52:21.525522 [CA 4] Center 34 (4~64) winsize 61
5609 11:52:21.529261 [CA 5] Center 33 (3~63) winsize 61
5610 11:52:21.529337
5611 11:52:21.532002 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5612 11:52:21.532076
5613 11:52:21.535437 [CATrainingPosCal] consider 2 rank data
5614 11:52:21.539165 u2DelayCellTimex100 = 270/100 ps
5615 11:52:21.542682 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5616 11:52:21.545493 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5617 11:52:21.552531 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5618 11:52:21.556037 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5619 11:52:21.559545 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5620 11:52:21.562831 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5621 11:52:21.562943
5622 11:52:21.565865 CA PerBit enable=1, Macro0, CA PI delay=33
5623 11:52:21.565949
5624 11:52:21.569394 [CBTSetCACLKResult] CA Dly = 33
5625 11:52:21.569473 CS Dly: 5 (0~37)
5626 11:52:21.569540
5627 11:52:21.572814 ----->DramcWriteLeveling(PI) begin...
5628 11:52:21.572902 ==
5629 11:52:21.575803 Dram Type= 6, Freq= 0, CH_1, rank 0
5630 11:52:21.582363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5631 11:52:21.582475 ==
5632 11:52:21.585973 Write leveling (Byte 0): 25 => 25
5633 11:52:21.589165 Write leveling (Byte 1): 30 => 30
5634 11:52:21.589244 DramcWriteLeveling(PI) end<-----
5635 11:52:21.592604
5636 11:52:21.592681 ==
5637 11:52:21.595697 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 11:52:21.599226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 11:52:21.599306 ==
5640 11:52:21.602400 [Gating] SW mode calibration
5641 11:52:21.609567 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5642 11:52:21.612714 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5643 11:52:21.619087 0 14 0 | B1->B0 | 3030 3131 | 0 1 | (0 0) (1 1)
5644 11:52:21.622655 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5645 11:52:21.626053 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5646 11:52:21.633087 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5647 11:52:21.635886 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5648 11:52:21.639801 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5649 11:52:21.645964 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5650 11:52:21.649270 0 14 28 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (1 0)
5651 11:52:21.652756 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
5652 11:52:21.659235 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5653 11:52:21.662508 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5654 11:52:21.666026 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5655 11:52:21.669255 0 15 16 | B1->B0 | 2423 2323 | 1 0 | (0 0) (0 0)
5656 11:52:21.676006 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5657 11:52:21.679714 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5658 11:52:21.682597 0 15 28 | B1->B0 | 2e2e 2e2e | 0 0 | (0 0) (1 1)
5659 11:52:21.689217 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 11:52:21.692800 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:52:21.696434 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5662 11:52:21.703027 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:52:21.706161 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5664 11:52:21.709389 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5665 11:52:21.716562 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5666 11:52:21.719947 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5667 11:52:21.723286 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5668 11:52:21.726833 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 11:52:21.733237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 11:52:21.736825 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 11:52:21.739742 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 11:52:21.746472 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 11:52:21.750112 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 11:52:21.753269 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 11:52:21.759945 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 11:52:21.762758 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 11:52:21.766268 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 11:52:21.772843 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 11:52:21.776113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 11:52:21.779735 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 11:52:21.786751 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 11:52:21.789807 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5683 11:52:21.793404 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5684 11:52:21.800030 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5685 11:52:21.800112 Total UI for P1: 0, mck2ui 16
5686 11:52:21.802913 best dqsien dly found for B0: ( 1, 2, 30)
5687 11:52:21.806632 Total UI for P1: 0, mck2ui 16
5688 11:52:21.809790 best dqsien dly found for B1: ( 1, 2, 30)
5689 11:52:21.813337 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5690 11:52:21.819983 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5691 11:52:21.820093
5692 11:52:21.823350 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5693 11:52:21.826417 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5694 11:52:21.830220 [Gating] SW calibration Done
5695 11:52:21.830308 ==
5696 11:52:21.833584 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:52:21.836632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:52:21.836716 ==
5699 11:52:21.836787 RX Vref Scan: 0
5700 11:52:21.840035
5701 11:52:21.840116 RX Vref 0 -> 0, step: 1
5702 11:52:21.840187
5703 11:52:21.843033 RX Delay -80 -> 252, step: 8
5704 11:52:21.846641 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5705 11:52:21.850289 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5706 11:52:21.856725 iDelay=208, Bit 2, Center 79 (-16 ~ 175) 192
5707 11:52:21.860198 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5708 11:52:21.863495 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5709 11:52:21.866364 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5710 11:52:21.870166 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5711 11:52:21.873468 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5712 11:52:21.876733 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5713 11:52:21.883326 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5714 11:52:21.886784 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5715 11:52:21.890484 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5716 11:52:21.893451 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5717 11:52:21.897154 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5718 11:52:21.903700 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5719 11:52:21.906750 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5720 11:52:21.906874 ==
5721 11:52:21.910423 Dram Type= 6, Freq= 0, CH_1, rank 0
5722 11:52:21.913337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5723 11:52:21.913425 ==
5724 11:52:21.913498 DQS Delay:
5725 11:52:21.916936 DQS0 = 0, DQS1 = 0
5726 11:52:21.917011 DQM Delay:
5727 11:52:21.920704 DQM0 = 95, DQM1 = 88
5728 11:52:21.920794 DQ Delay:
5729 11:52:21.924372 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =95
5730 11:52:21.926870 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =91
5731 11:52:21.930670 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5732 11:52:21.934381 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5733 11:52:21.934455
5734 11:52:21.934523
5735 11:52:21.934589 ==
5736 11:52:21.937175 Dram Type= 6, Freq= 0, CH_1, rank 0
5737 11:52:21.940547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5738 11:52:21.940626 ==
5739 11:52:21.940689
5740 11:52:21.944160
5741 11:52:21.944253 TX Vref Scan disable
5742 11:52:21.947413 == TX Byte 0 ==
5743 11:52:21.950292 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5744 11:52:21.954035 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5745 11:52:21.957596 == TX Byte 1 ==
5746 11:52:21.960598 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5747 11:52:21.964106 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5748 11:52:21.964188 ==
5749 11:52:21.967304 Dram Type= 6, Freq= 0, CH_1, rank 0
5750 11:52:21.973798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5751 11:52:21.973881 ==
5752 11:52:21.973945
5753 11:52:21.974005
5754 11:52:21.974062 TX Vref Scan disable
5755 11:52:21.978338 == TX Byte 0 ==
5756 11:52:21.981319 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5757 11:52:21.984528 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5758 11:52:21.987800 == TX Byte 1 ==
5759 11:52:21.991686 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5760 11:52:21.994854 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5761 11:52:21.997844
5762 11:52:21.997924 [DATLAT]
5763 11:52:21.997987 Freq=933, CH1 RK0
5764 11:52:21.998059
5765 11:52:22.001288 DATLAT Default: 0xd
5766 11:52:22.001365 0, 0xFFFF, sum = 0
5767 11:52:22.005006 1, 0xFFFF, sum = 0
5768 11:52:22.005095 2, 0xFFFF, sum = 0
5769 11:52:22.007900 3, 0xFFFF, sum = 0
5770 11:52:22.007983 4, 0xFFFF, sum = 0
5771 11:52:22.011452 5, 0xFFFF, sum = 0
5772 11:52:22.011541 6, 0xFFFF, sum = 0
5773 11:52:22.014473 7, 0xFFFF, sum = 0
5774 11:52:22.018119 8, 0xFFFF, sum = 0
5775 11:52:22.018204 9, 0xFFFF, sum = 0
5776 11:52:22.018272 10, 0x0, sum = 1
5777 11:52:22.021324 11, 0x0, sum = 2
5778 11:52:22.021398 12, 0x0, sum = 3
5779 11:52:22.024484 13, 0x0, sum = 4
5780 11:52:22.024561 best_step = 11
5781 11:52:22.024625
5782 11:52:22.027786 ==
5783 11:52:22.027906 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 11:52:22.034380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 11:52:22.034526 ==
5786 11:52:22.034595 RX Vref Scan: 1
5787 11:52:22.034656
5788 11:52:22.037936 RX Vref 0 -> 0, step: 1
5789 11:52:22.038089
5790 11:52:22.041166 RX Delay -69 -> 252, step: 4
5791 11:52:22.041270
5792 11:52:22.044623 Set Vref, RX VrefLevel [Byte0]: 60
5793 11:52:22.047914 [Byte1]: 53
5794 11:52:22.048068
5795 11:52:22.051466 Final RX Vref Byte 0 = 60 to rank0
5796 11:52:22.054564 Final RX Vref Byte 1 = 53 to rank0
5797 11:52:22.058636 Final RX Vref Byte 0 = 60 to rank1
5798 11:52:22.061254 Final RX Vref Byte 1 = 53 to rank1==
5799 11:52:22.064567 Dram Type= 6, Freq= 0, CH_1, rank 0
5800 11:52:22.068197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 11:52:22.068309 ==
5802 11:52:22.071238 DQS Delay:
5803 11:52:22.071322 DQS0 = 0, DQS1 = 0
5804 11:52:22.074763 DQM Delay:
5805 11:52:22.074883 DQM0 = 97, DQM1 = 90
5806 11:52:22.074952 DQ Delay:
5807 11:52:22.078244 DQ0 =102, DQ1 =92, DQ2 =86, DQ3 =96
5808 11:52:22.081332 DQ4 =98, DQ5 =106, DQ6 =108, DQ7 =94
5809 11:52:22.084477 DQ8 =78, DQ9 =78, DQ10 =92, DQ11 =86
5810 11:52:22.087838 DQ12 =100, DQ13 =96, DQ14 =98, DQ15 =96
5811 11:52:22.087949
5812 11:52:22.088044
5813 11:52:22.098231 [DQSOSCAuto] RK0, (LSB)MR18= 0x17f3, (MSB)MR19= 0x504, tDQSOscB0 = 426 ps tDQSOscB1 = 414 ps
5814 11:52:22.101449 CH1 RK0: MR19=504, MR18=17F3
5815 11:52:22.104602 CH1_RK0: MR19=0x504, MR18=0x17F3, DQSOSC=414, MR23=63, INC=63, DEC=42
5816 11:52:22.108162
5817 11:52:22.111480 ----->DramcWriteLeveling(PI) begin...
5818 11:52:22.111565 ==
5819 11:52:22.114900 Dram Type= 6, Freq= 0, CH_1, rank 1
5820 11:52:22.117850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 11:52:22.117933 ==
5822 11:52:22.121446 Write leveling (Byte 0): 27 => 27
5823 11:52:22.124565 Write leveling (Byte 1): 28 => 28
5824 11:52:22.128109 DramcWriteLeveling(PI) end<-----
5825 11:52:22.128191
5826 11:52:22.128256 ==
5827 11:52:22.131571 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 11:52:22.134562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 11:52:22.134676 ==
5830 11:52:22.137920 [Gating] SW mode calibration
5831 11:52:22.144541 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5832 11:52:22.151823 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5833 11:52:22.154935 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5834 11:52:22.157995 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5835 11:52:22.161827 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5836 11:52:22.168066 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5837 11:52:22.171276 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5838 11:52:22.174706 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5839 11:52:22.181570 0 14 24 | B1->B0 | 3030 2e2e | 1 1 | (1 1) (1 0)
5840 11:52:22.184908 0 14 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
5841 11:52:22.188708 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5842 11:52:22.194736 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5843 11:52:22.198307 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5844 11:52:22.201463 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5845 11:52:22.208381 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5846 11:52:22.211693 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5847 11:52:22.215275 0 15 24 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
5848 11:52:22.221658 0 15 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5849 11:52:22.225318 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:52:22.228375 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5851 11:52:22.232075 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:52:22.238363 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5853 11:52:22.241920 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5854 11:52:22.244967 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5855 11:52:22.251942 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5856 11:52:22.254844 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 11:52:22.258500 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 11:52:22.264985 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 11:52:22.268257 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 11:52:22.272214 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 11:52:22.278669 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 11:52:22.392807 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 11:52:22.392983 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 11:52:22.393094 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5865 11:52:22.393188 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 11:52:22.393282 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 11:52:22.393378 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 11:52:22.393469 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 11:52:22.393565 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 11:52:22.393660 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 11:52:22.393746 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5872 11:52:22.393831 Total UI for P1: 0, mck2ui 16
5873 11:52:22.393917 best dqsien dly found for B0: ( 1, 2, 22)
5874 11:52:22.394002 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 11:52:22.394070 Total UI for P1: 0, mck2ui 16
5876 11:52:22.394131 best dqsien dly found for B1: ( 1, 2, 24)
5877 11:52:22.394187 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5878 11:52:22.394242 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5879 11:52:22.394296
5880 11:52:22.394351 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5881 11:52:22.394405 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5882 11:52:22.394459 [Gating] SW calibration Done
5883 11:52:22.394512 ==
5884 11:52:22.394567 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:52:22.394654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:52:22.394740 ==
5887 11:52:22.394824 RX Vref Scan: 0
5888 11:52:22.394904
5889 11:52:22.394960 RX Vref 0 -> 0, step: 1
5890 11:52:22.395014
5891 11:52:22.395068 RX Delay -80 -> 252, step: 8
5892 11:52:22.395128 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5893 11:52:22.395189 iDelay=200, Bit 1, Center 87 (-8 ~ 183) 192
5894 11:52:22.395244 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5895 11:52:22.395298 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5896 11:52:22.395352 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5897 11:52:22.395768 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5898 11:52:22.398664 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5899 11:52:22.402023 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5900 11:52:22.405212 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5901 11:52:22.408832 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5902 11:52:22.412197 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5903 11:52:22.419242 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5904 11:52:22.422220 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5905 11:52:22.425414 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5906 11:52:22.429007 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5907 11:52:22.432725 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5908 11:52:22.432831 ==
5909 11:52:22.435675 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:52:22.439027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:52:22.442273 ==
5912 11:52:22.442425 DQS Delay:
5913 11:52:22.442524 DQS0 = 0, DQS1 = 0
5914 11:52:22.445410 DQM Delay:
5915 11:52:22.445536 DQM0 = 94, DQM1 = 88
5916 11:52:22.448862 DQ Delay:
5917 11:52:22.451952 DQ0 =95, DQ1 =87, DQ2 =87, DQ3 =95
5918 11:52:22.455588 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5919 11:52:22.480246 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5920 11:52:22.480348 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5921 11:52:22.480415
5922 11:52:22.480475
5923 11:52:22.480532 ==
5924 11:52:22.480589 Dram Type= 6, Freq= 0, CH_1, rank 1
5925 11:52:22.480645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5926 11:52:22.480701 ==
5927 11:52:22.480755
5928 11:52:22.480808
5929 11:52:22.480860 TX Vref Scan disable
5930 11:52:22.480914 == TX Byte 0 ==
5931 11:52:22.480967 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5932 11:52:22.481915 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5933 11:52:22.481986 == TX Byte 1 ==
5934 11:52:22.489591 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5935 11:52:22.492455 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5936 11:52:22.492545 ==
5937 11:52:22.495665 Dram Type= 6, Freq= 0, CH_1, rank 1
5938 11:52:22.499106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5939 11:52:22.499222 ==
5940 11:52:22.499317
5941 11:52:22.499420
5942 11:52:22.502525 TX Vref Scan disable
5943 11:52:22.505774 == TX Byte 0 ==
5944 11:52:22.508775 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5945 11:52:22.511995 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5946 11:52:22.515479 == TX Byte 1 ==
5947 11:52:22.518661 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5948 11:52:22.521824 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5949 11:52:22.521916
5950 11:52:22.525601 [DATLAT]
5951 11:52:22.525707 Freq=933, CH1 RK1
5952 11:52:22.525799
5953 11:52:22.528732 DATLAT Default: 0xb
5954 11:52:22.528845 0, 0xFFFF, sum = 0
5955 11:52:22.532375 1, 0xFFFF, sum = 0
5956 11:52:22.532482 2, 0xFFFF, sum = 0
5957 11:52:22.535713 3, 0xFFFF, sum = 0
5958 11:52:22.535826 4, 0xFFFF, sum = 0
5959 11:52:22.538958 5, 0xFFFF, sum = 0
5960 11:52:22.539078 6, 0xFFFF, sum = 0
5961 11:52:22.542510 7, 0xFFFF, sum = 0
5962 11:52:22.542612 8, 0xFFFF, sum = 0
5963 11:52:22.545572 9, 0xFFFF, sum = 0
5964 11:52:22.545651 10, 0x0, sum = 1
5965 11:52:22.548591 11, 0x0, sum = 2
5966 11:52:22.548697 12, 0x0, sum = 3
5967 11:52:22.552516 13, 0x0, sum = 4
5968 11:52:22.552593 best_step = 11
5969 11:52:22.552666
5970 11:52:22.552731 ==
5971 11:52:22.555222 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 11:52:22.558749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 11:52:22.562557 ==
5974 11:52:22.562663 RX Vref Scan: 0
5975 11:52:22.562769
5976 11:52:22.565552 RX Vref 0 -> 0, step: 1
5977 11:52:22.565654
5978 11:52:22.568850 RX Delay -61 -> 252, step: 4
5979 11:52:22.572597 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5980 11:52:22.575348 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5981 11:52:22.578997 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5982 11:52:22.585708 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5983 11:52:22.589097 iDelay=195, Bit 4, Center 96 (7 ~ 186) 180
5984 11:52:22.592406 iDelay=195, Bit 5, Center 104 (15 ~ 194) 180
5985 11:52:22.595937 iDelay=195, Bit 6, Center 102 (11 ~ 194) 184
5986 11:52:22.599121 iDelay=195, Bit 7, Center 90 (3 ~ 178) 176
5987 11:52:22.602358 iDelay=195, Bit 8, Center 82 (-9 ~ 174) 184
5988 11:52:22.608828 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5989 11:52:22.612046 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5990 11:52:22.615751 iDelay=195, Bit 11, Center 84 (-9 ~ 178) 188
5991 11:52:22.619315 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5992 11:52:22.622200 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5993 11:52:22.625551 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5994 11:52:22.632264 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5995 11:52:22.632353 ==
5996 11:52:22.635579 Dram Type= 6, Freq= 0, CH_1, rank 1
5997 11:52:22.639291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5998 11:52:22.639378 ==
5999 11:52:22.639459 DQS Delay:
6000 11:52:22.642340 DQS0 = 0, DQS1 = 0
6001 11:52:22.642417 DQM Delay:
6002 11:52:22.645600 DQM0 = 95, DQM1 = 90
6003 11:52:22.645682 DQ Delay:
6004 11:52:22.648954 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
6005 11:52:22.652335 DQ4 =96, DQ5 =104, DQ6 =102, DQ7 =90
6006 11:52:22.655667 DQ8 =82, DQ9 =80, DQ10 =90, DQ11 =84
6007 11:52:22.659189 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =98
6008 11:52:22.659265
6009 11:52:22.659328
6010 11:52:22.666084 [DQSOSCAuto] RK1, (LSB)MR18= 0xe16, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 417 ps
6011 11:52:22.669455 CH1 RK1: MR19=505, MR18=E16
6012 11:52:22.675919 CH1_RK1: MR19=0x505, MR18=0xE16, DQSOSC=414, MR23=63, INC=63, DEC=42
6013 11:52:22.679228 [RxdqsGatingPostProcess] freq 933
6014 11:52:22.682769 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6015 11:52:22.686185 best DQS0 dly(2T, 0.5T) = (0, 10)
6016 11:52:22.689115 best DQS1 dly(2T, 0.5T) = (0, 10)
6017 11:52:22.692741 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6018 11:52:22.695710 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6019 11:52:22.699374 best DQS0 dly(2T, 0.5T) = (0, 10)
6020 11:52:22.702524 best DQS1 dly(2T, 0.5T) = (0, 10)
6021 11:52:22.706012 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6022 11:52:22.709547 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6023 11:52:22.712691 Pre-setting of DQS Precalculation
6024 11:52:22.716038 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6025 11:52:22.725839 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6026 11:52:22.732980 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6027 11:52:22.733072
6028 11:52:22.733157
6029 11:52:22.736191 [Calibration Summary] 1866 Mbps
6030 11:52:22.736326 CH 0, Rank 0
6031 11:52:22.739148 SW Impedance : PASS
6032 11:52:22.739240 DUTY Scan : NO K
6033 11:52:22.742774 ZQ Calibration : PASS
6034 11:52:22.746264 Jitter Meter : NO K
6035 11:52:22.746345 CBT Training : PASS
6036 11:52:22.749251 Write leveling : PASS
6037 11:52:22.752643 RX DQS gating : PASS
6038 11:52:22.752742 RX DQ/DQS(RDDQC) : PASS
6039 11:52:22.756078 TX DQ/DQS : PASS
6040 11:52:22.756177 RX DATLAT : PASS
6041 11:52:22.759211 RX DQ/DQS(Engine): PASS
6042 11:52:22.762466 TX OE : NO K
6043 11:52:22.762566 All Pass.
6044 11:52:22.762656
6045 11:52:22.762741 CH 0, Rank 1
6046 11:52:22.765954 SW Impedance : PASS
6047 11:52:22.769710 DUTY Scan : NO K
6048 11:52:22.769784 ZQ Calibration : PASS
6049 11:52:22.772891 Jitter Meter : NO K
6050 11:52:22.775824 CBT Training : PASS
6051 11:52:22.775900 Write leveling : PASS
6052 11:52:22.779323 RX DQS gating : PASS
6053 11:52:22.782583 RX DQ/DQS(RDDQC) : PASS
6054 11:52:22.782684 TX DQ/DQS : PASS
6055 11:52:22.786204 RX DATLAT : PASS
6056 11:52:22.789204 RX DQ/DQS(Engine): PASS
6057 11:52:22.789320 TX OE : NO K
6058 11:52:22.789438 All Pass.
6059 11:52:22.789530
6060 11:52:22.792820 CH 1, Rank 0
6061 11:52:22.792910 SW Impedance : PASS
6062 11:52:22.796383 DUTY Scan : NO K
6063 11:52:22.799469 ZQ Calibration : PASS
6064 11:52:22.799543 Jitter Meter : NO K
6065 11:52:22.802874 CBT Training : PASS
6066 11:52:22.806502 Write leveling : PASS
6067 11:52:22.806602 RX DQS gating : PASS
6068 11:52:22.809408 RX DQ/DQS(RDDQC) : PASS
6069 11:52:22.813011 TX DQ/DQS : PASS
6070 11:52:22.813088 RX DATLAT : PASS
6071 11:52:22.816068 RX DQ/DQS(Engine): PASS
6072 11:52:22.819538 TX OE : NO K
6073 11:52:22.819617 All Pass.
6074 11:52:22.819707
6075 11:52:22.819787 CH 1, Rank 1
6076 11:52:22.822968 SW Impedance : PASS
6077 11:52:22.826404 DUTY Scan : NO K
6078 11:52:22.826483 ZQ Calibration : PASS
6079 11:52:22.829292 Jitter Meter : NO K
6080 11:52:22.832725 CBT Training : PASS
6081 11:52:22.832806 Write leveling : PASS
6082 11:52:22.836301 RX DQS gating : PASS
6083 11:52:22.836384 RX DQ/DQS(RDDQC) : PASS
6084 11:52:22.839206 TX DQ/DQS : PASS
6085 11:52:22.842734 RX DATLAT : PASS
6086 11:52:22.842840 RX DQ/DQS(Engine): PASS
6087 11:52:22.846240 TX OE : NO K
6088 11:52:22.846321 All Pass.
6089 11:52:22.846424
6090 11:52:22.849234 DramC Write-DBI off
6091 11:52:22.852832 PER_BANK_REFRESH: Hybrid Mode
6092 11:52:22.852915 TX_TRACKING: ON
6093 11:52:22.862964 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6094 11:52:22.866357 [FAST_K] Save calibration result to emmc
6095 11:52:22.869840 dramc_set_vcore_voltage set vcore to 650000
6096 11:52:22.872735 Read voltage for 400, 6
6097 11:52:22.872824 Vio18 = 0
6098 11:52:22.872926 Vcore = 650000
6099 11:52:22.876618 Vdram = 0
6100 11:52:22.876692 Vddq = 0
6101 11:52:22.876771 Vmddr = 0
6102 11:52:22.883019 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6103 11:52:22.886106 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6104 11:52:22.889663 MEM_TYPE=3, freq_sel=20
6105 11:52:22.893083 sv_algorithm_assistance_LP4_800
6106 11:52:22.896385 ============ PULL DRAM RESETB DOWN ============
6107 11:52:22.899591 ========== PULL DRAM RESETB DOWN end =========
6108 11:52:22.906496 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6109 11:52:22.909951 ===================================
6110 11:52:22.910036 LPDDR4 DRAM CONFIGURATION
6111 11:52:22.912902 ===================================
6112 11:52:22.916586 EX_ROW_EN[0] = 0x0
6113 11:52:22.919534 EX_ROW_EN[1] = 0x0
6114 11:52:22.919609 LP4Y_EN = 0x0
6115 11:52:22.923050 WORK_FSP = 0x0
6116 11:52:22.923130 WL = 0x2
6117 11:52:22.926469 RL = 0x2
6118 11:52:22.926548 BL = 0x2
6119 11:52:22.929890 RPST = 0x0
6120 11:52:22.929987 RD_PRE = 0x0
6121 11:52:22.933517 WR_PRE = 0x1
6122 11:52:22.933597 WR_PST = 0x0
6123 11:52:22.936467 DBI_WR = 0x0
6124 11:52:22.936548 DBI_RD = 0x0
6125 11:52:22.939716 OTF = 0x1
6126 11:52:22.943301 ===================================
6127 11:52:22.946637 ===================================
6128 11:52:22.946712 ANA top config
6129 11:52:22.949617 ===================================
6130 11:52:22.953325 DLL_ASYNC_EN = 0
6131 11:52:22.956261 ALL_SLAVE_EN = 1
6132 11:52:22.956349 NEW_RANK_MODE = 1
6133 11:52:22.959839 DLL_IDLE_MODE = 1
6134 11:52:22.963176 LP45_APHY_COMB_EN = 1
6135 11:52:22.966793 TX_ODT_DIS = 1
6136 11:52:22.969673 NEW_8X_MODE = 1
6137 11:52:22.973224 ===================================
6138 11:52:22.976811 ===================================
6139 11:52:22.976915 data_rate = 800
6140 11:52:22.979993 CKR = 1
6141 11:52:22.983364 DQ_P2S_RATIO = 4
6142 11:52:22.986603 ===================================
6143 11:52:22.990192 CA_P2S_RATIO = 4
6144 11:52:22.993296 DQ_CA_OPEN = 0
6145 11:52:22.996420 DQ_SEMI_OPEN = 1
6146 11:52:22.996505 CA_SEMI_OPEN = 1
6147 11:52:22.999881 CA_FULL_RATE = 0
6148 11:52:23.003522 DQ_CKDIV4_EN = 0
6149 11:52:23.006587 CA_CKDIV4_EN = 1
6150 11:52:23.010366 CA_PREDIV_EN = 0
6151 11:52:23.010454 PH8_DLY = 0
6152 11:52:23.013189 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6153 11:52:23.016641 DQ_AAMCK_DIV = 0
6154 11:52:23.020071 CA_AAMCK_DIV = 0
6155 11:52:23.023392 CA_ADMCK_DIV = 4
6156 11:52:23.026822 DQ_TRACK_CA_EN = 0
6157 11:52:23.026933 CA_PICK = 800
6158 11:52:23.030205 CA_MCKIO = 400
6159 11:52:23.033598 MCKIO_SEMI = 400
6160 11:52:23.036890 PLL_FREQ = 3016
6161 11:52:23.040325 DQ_UI_PI_RATIO = 32
6162 11:52:23.043229 CA_UI_PI_RATIO = 32
6163 11:52:23.046781 ===================================
6164 11:52:23.050535 ===================================
6165 11:52:23.053342 memory_type:LPDDR4
6166 11:52:23.053423 GP_NUM : 10
6167 11:52:23.056916 SRAM_EN : 1
6168 11:52:23.056999 MD32_EN : 0
6169 11:52:23.060679 ===================================
6170 11:52:23.063570 [ANA_INIT] >>>>>>>>>>>>>>
6171 11:52:23.067062 <<<<<< [CONFIGURE PHASE]: ANA_TX
6172 11:52:23.070280 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6173 11:52:23.073929 ===================================
6174 11:52:23.077414 data_rate = 800,PCW = 0X7400
6175 11:52:23.080428 ===================================
6176 11:52:23.083580 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6177 11:52:23.087130 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6178 11:52:23.100349 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6179 11:52:23.103755 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6180 11:52:23.107097 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6181 11:52:23.110337 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6182 11:52:23.113870 [ANA_INIT] flow start
6183 11:52:23.113951 [ANA_INIT] PLL >>>>>>>>
6184 11:52:23.117394 [ANA_INIT] PLL <<<<<<<<
6185 11:52:23.120346 [ANA_INIT] MIDPI >>>>>>>>
6186 11:52:23.123760 [ANA_INIT] MIDPI <<<<<<<<
6187 11:52:23.123839 [ANA_INIT] DLL >>>>>>>>
6188 11:52:23.126939 [ANA_INIT] flow end
6189 11:52:23.130238 ============ LP4 DIFF to SE enter ============
6190 11:52:23.133786 ============ LP4 DIFF to SE exit ============
6191 11:52:23.137148 [ANA_INIT] <<<<<<<<<<<<<
6192 11:52:23.140610 [Flow] Enable top DCM control >>>>>
6193 11:52:23.143809 [Flow] Enable top DCM control <<<<<
6194 11:52:23.147202 Enable DLL master slave shuffle
6195 11:52:23.150788 ==============================================================
6196 11:52:23.154233 Gating Mode config
6197 11:52:23.160612 ==============================================================
6198 11:52:23.160709 Config description:
6199 11:52:23.170639 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6200 11:52:23.177547 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6201 11:52:23.180835 SELPH_MODE 0: By rank 1: By Phase
6202 11:52:23.187699 ==============================================================
6203 11:52:23.191135 GAT_TRACK_EN = 0
6204 11:52:23.193969 RX_GATING_MODE = 2
6205 11:52:23.197456 RX_GATING_TRACK_MODE = 2
6206 11:52:23.200822 SELPH_MODE = 1
6207 11:52:23.203876 PICG_EARLY_EN = 1
6208 11:52:23.207517 VALID_LAT_VALUE = 1
6209 11:52:23.210940 ==============================================================
6210 11:52:23.214309 Enter into Gating configuration >>>>
6211 11:52:23.217796 Exit from Gating configuration <<<<
6212 11:52:23.220844 Enter into DVFS_PRE_config >>>>>
6213 11:52:23.230769 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6214 11:52:23.234432 Exit from DVFS_PRE_config <<<<<
6215 11:52:23.237525 Enter into PICG configuration >>>>
6216 11:52:23.240980 Exit from PICG configuration <<<<
6217 11:52:23.244321 [RX_INPUT] configuration >>>>>
6218 11:52:23.247425 [RX_INPUT] configuration <<<<<
6219 11:52:23.250876 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6220 11:52:23.257413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6221 11:52:23.264269 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6222 11:52:23.271004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6223 11:52:23.277476 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6224 11:52:23.284347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6225 11:52:23.287722 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6226 11:52:23.290747 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6227 11:52:23.294333 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6228 11:52:23.297792 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6229 11:52:23.304336 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6230 11:52:23.308117 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6231 11:52:23.310967 ===================================
6232 11:52:23.314581 LPDDR4 DRAM CONFIGURATION
6233 11:52:23.317526 ===================================
6234 11:52:23.317607 EX_ROW_EN[0] = 0x0
6235 11:52:23.321245 EX_ROW_EN[1] = 0x0
6236 11:52:23.321327 LP4Y_EN = 0x0
6237 11:52:23.324324 WORK_FSP = 0x0
6238 11:52:23.324405 WL = 0x2
6239 11:52:23.327585 RL = 0x2
6240 11:52:23.327673 BL = 0x2
6241 11:52:23.331383 RPST = 0x0
6242 11:52:23.331491 RD_PRE = 0x0
6243 11:52:23.334234 WR_PRE = 0x1
6244 11:52:23.334316 WR_PST = 0x0
6245 11:52:23.337621 DBI_WR = 0x0
6246 11:52:23.337724 DBI_RD = 0x0
6247 11:52:23.341267 OTF = 0x1
6248 11:52:23.344746 ===================================
6249 11:52:23.348039 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6250 11:52:23.351436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6251 11:52:23.357970 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6252 11:52:23.360938 ===================================
6253 11:52:23.361015 LPDDR4 DRAM CONFIGURATION
6254 11:52:23.364440 ===================================
6255 11:52:23.367980 EX_ROW_EN[0] = 0x10
6256 11:52:23.370983 EX_ROW_EN[1] = 0x0
6257 11:52:23.371093 LP4Y_EN = 0x0
6258 11:52:23.374365 WORK_FSP = 0x0
6259 11:52:23.374447 WL = 0x2
6260 11:52:23.377746 RL = 0x2
6261 11:52:23.377828 BL = 0x2
6262 11:52:23.381734 RPST = 0x0
6263 11:52:23.381817 RD_PRE = 0x0
6264 11:52:23.384727 WR_PRE = 0x1
6265 11:52:23.384810 WR_PST = 0x0
6266 11:52:23.387657 DBI_WR = 0x0
6267 11:52:23.387739 DBI_RD = 0x0
6268 11:52:23.391680 OTF = 0x1
6269 11:52:23.394619 ===================================
6270 11:52:23.401063 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6271 11:52:23.404702 nWR fixed to 30
6272 11:52:23.404785 [ModeRegInit_LP4] CH0 RK0
6273 11:52:23.407657 [ModeRegInit_LP4] CH0 RK1
6274 11:52:23.411336 [ModeRegInit_LP4] CH1 RK0
6275 11:52:23.414682 [ModeRegInit_LP4] CH1 RK1
6276 11:52:23.414790 match AC timing 19
6277 11:52:23.417804 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6278 11:52:23.424422 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6279 11:52:23.427965 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6280 11:52:23.431490 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6281 11:52:23.437968 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6282 11:52:23.438050 ==
6283 11:52:23.441630 Dram Type= 6, Freq= 0, CH_0, rank 0
6284 11:52:23.444900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6285 11:52:23.445008 ==
6286 11:52:23.451231 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6287 11:52:23.454796 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6288 11:52:23.457942 [CA 0] Center 36 (8~64) winsize 57
6289 11:52:23.461607 [CA 1] Center 36 (8~64) winsize 57
6290 11:52:23.464869 [CA 2] Center 36 (8~64) winsize 57
6291 11:52:23.468080 [CA 3] Center 36 (8~64) winsize 57
6292 11:52:23.471643 [CA 4] Center 36 (8~64) winsize 57
6293 11:52:23.475115 [CA 5] Center 36 (8~64) winsize 57
6294 11:52:23.475197
6295 11:52:23.478059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6296 11:52:23.478141
6297 11:52:23.481415 [CATrainingPosCal] consider 1 rank data
6298 11:52:23.485386 u2DelayCellTimex100 = 270/100 ps
6299 11:52:23.488409 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:52:23.491696 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:52:23.495301 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 11:52:23.498307 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:52:23.504916 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:52:23.508528 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:52:23.508632
6306 11:52:23.511732 CA PerBit enable=1, Macro0, CA PI delay=36
6307 11:52:23.511820
6308 11:52:23.515288 [CBTSetCACLKResult] CA Dly = 36
6309 11:52:23.515376 CS Dly: 1 (0~32)
6310 11:52:23.515442 ==
6311 11:52:23.518450 Dram Type= 6, Freq= 0, CH_0, rank 1
6312 11:52:23.521485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 11:52:23.525092 ==
6314 11:52:23.528623 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 11:52:23.535471 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6316 11:52:23.538226 [CA 0] Center 36 (8~64) winsize 57
6317 11:52:23.541913 [CA 1] Center 36 (8~64) winsize 57
6318 11:52:23.544864 [CA 2] Center 36 (8~64) winsize 57
6319 11:52:23.548452 [CA 3] Center 36 (8~64) winsize 57
6320 11:52:23.551411 [CA 4] Center 36 (8~64) winsize 57
6321 11:52:23.555081 [CA 5] Center 36 (8~64) winsize 57
6322 11:52:23.555162
6323 11:52:23.557969 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6324 11:52:23.558050
6325 11:52:23.561335 [CATrainingPosCal] consider 2 rank data
6326 11:52:23.565203 u2DelayCellTimex100 = 270/100 ps
6327 11:52:23.568033 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 11:52:23.571818 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 11:52:23.575219 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 11:52:23.578037 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:52:23.581742 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:52:23.584759 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:52:23.584846
6334 11:52:23.588402 CA PerBit enable=1, Macro0, CA PI delay=36
6335 11:52:23.591928
6336 11:52:23.592009 [CBTSetCACLKResult] CA Dly = 36
6337 11:52:23.595189 CS Dly: 1 (0~32)
6338 11:52:23.595269
6339 11:52:23.598134 ----->DramcWriteLeveling(PI) begin...
6340 11:52:23.598230 ==
6341 11:52:23.601730 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:52:23.604849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:52:23.604931 ==
6344 11:52:23.608354 Write leveling (Byte 0): 40 => 8
6345 11:52:23.611845 Write leveling (Byte 1): 32 => 0
6346 11:52:23.615029 DramcWriteLeveling(PI) end<-----
6347 11:52:23.615109
6348 11:52:23.615172 ==
6349 11:52:23.618175 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 11:52:23.621536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 11:52:23.621648 ==
6352 11:52:23.625223 [Gating] SW mode calibration
6353 11:52:23.631454 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6354 11:52:23.638591 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6355 11:52:23.641888 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6356 11:52:23.648274 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6357 11:52:23.651303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 11:52:23.654998 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6359 11:52:23.657943 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6360 11:52:23.664666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6361 11:52:23.668218 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6362 11:52:23.671655 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6363 11:52:23.678384 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6364 11:52:23.681758 Total UI for P1: 0, mck2ui 16
6365 11:52:23.685058 best dqsien dly found for B0: ( 0, 14, 24)
6366 11:52:23.685141 Total UI for P1: 0, mck2ui 16
6367 11:52:23.692375 best dqsien dly found for B1: ( 0, 14, 24)
6368 11:52:23.694827 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6369 11:52:23.698294 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6370 11:52:23.698375
6371 11:52:23.701609 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6372 11:52:23.705159 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6373 11:52:23.708190 [Gating] SW calibration Done
6374 11:52:23.708311 ==
6375 11:52:23.711577 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 11:52:23.715149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 11:52:23.715229 ==
6378 11:52:23.718138 RX Vref Scan: 0
6379 11:52:23.718243
6380 11:52:23.718334 RX Vref 0 -> 0, step: 1
6381 11:52:23.718413
6382 11:52:23.721781 RX Delay -410 -> 252, step: 16
6383 11:52:23.728337 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6384 11:52:23.731918 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6385 11:52:23.735179 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6386 11:52:23.738113 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6387 11:52:23.745029 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6388 11:52:23.748703 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6389 11:52:23.751729 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6390 11:52:23.755178 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6391 11:52:23.761694 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6392 11:52:23.764788 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6393 11:52:23.768467 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6394 11:52:23.771537 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6395 11:52:23.778211 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6396 11:52:23.781742 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6397 11:52:23.784990 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6398 11:52:23.788186 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6399 11:52:23.788295 ==
6400 11:52:23.791535 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 11:52:23.798054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 11:52:23.798134 ==
6403 11:52:23.798255 DQS Delay:
6404 11:52:23.801751 DQS0 = 35, DQS1 = 51
6405 11:52:23.801830 DQM Delay:
6406 11:52:23.804912 DQM0 = 7, DQM1 = 10
6407 11:52:23.804993 DQ Delay:
6408 11:52:23.807962 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6409 11:52:23.811441 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6410 11:52:23.811522 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6411 11:52:23.814765 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6412 11:52:23.817925
6413 11:52:23.818005
6414 11:52:23.818068 ==
6415 11:52:23.821539 Dram Type= 6, Freq= 0, CH_0, rank 0
6416 11:52:23.825136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6417 11:52:23.825216 ==
6418 11:52:23.825279
6419 11:52:23.825337
6420 11:52:23.828213 TX Vref Scan disable
6421 11:52:23.828292 == TX Byte 0 ==
6422 11:52:23.831855 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6423 11:52:23.838336 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6424 11:52:23.838423 == TX Byte 1 ==
6425 11:52:23.841365 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6426 11:52:23.848554 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6427 11:52:23.848638 ==
6428 11:52:23.851744 Dram Type= 6, Freq= 0, CH_0, rank 0
6429 11:52:23.855120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6430 11:52:23.855205 ==
6431 11:52:23.855289
6432 11:52:23.855368
6433 11:52:23.858393 TX Vref Scan disable
6434 11:52:23.858477 == TX Byte 0 ==
6435 11:52:23.861572 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6436 11:52:23.868166 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6437 11:52:23.868302 == TX Byte 1 ==
6438 11:52:23.871601 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6439 11:52:23.878156 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6440 11:52:23.878238
6441 11:52:23.878303 [DATLAT]
6442 11:52:23.881767 Freq=400, CH0 RK0
6443 11:52:23.881847
6444 11:52:23.881910 DATLAT Default: 0xf
6445 11:52:23.884845 0, 0xFFFF, sum = 0
6446 11:52:23.884928 1, 0xFFFF, sum = 0
6447 11:52:23.888385 2, 0xFFFF, sum = 0
6448 11:52:23.888466 3, 0xFFFF, sum = 0
6449 11:52:23.891430 4, 0xFFFF, sum = 0
6450 11:52:23.891512 5, 0xFFFF, sum = 0
6451 11:52:23.895137 6, 0xFFFF, sum = 0
6452 11:52:23.895218 7, 0xFFFF, sum = 0
6453 11:52:23.898191 8, 0xFFFF, sum = 0
6454 11:52:23.898275 9, 0xFFFF, sum = 0
6455 11:52:23.901696 10, 0xFFFF, sum = 0
6456 11:52:23.901777 11, 0xFFFF, sum = 0
6457 11:52:23.905051 12, 0xFFFF, sum = 0
6458 11:52:23.905132 13, 0x0, sum = 1
6459 11:52:23.908605 14, 0x0, sum = 2
6460 11:52:23.908687 15, 0x0, sum = 3
6461 11:52:23.911467 16, 0x0, sum = 4
6462 11:52:23.911547 best_step = 14
6463 11:52:23.911610
6464 11:52:23.911668 ==
6465 11:52:23.914796 Dram Type= 6, Freq= 0, CH_0, rank 0
6466 11:52:23.921977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 11:52:23.922057 ==
6468 11:52:23.922121 RX Vref Scan: 1
6469 11:52:23.922180
6470 11:52:23.924759 RX Vref 0 -> 0, step: 1
6471 11:52:23.924839
6472 11:52:23.928283 RX Delay -343 -> 252, step: 8
6473 11:52:23.928382
6474 11:52:23.931959 Set Vref, RX VrefLevel [Byte0]: 55
6475 11:52:23.935495 [Byte1]: 50
6476 11:52:23.935576
6477 11:52:23.938785 Final RX Vref Byte 0 = 55 to rank0
6478 11:52:23.941447 Final RX Vref Byte 1 = 50 to rank0
6479 11:52:23.945053 Final RX Vref Byte 0 = 55 to rank1
6480 11:52:23.948338 Final RX Vref Byte 1 = 50 to rank1==
6481 11:52:23.951630 Dram Type= 6, Freq= 0, CH_0, rank 0
6482 11:52:23.955216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6483 11:52:23.955298 ==
6484 11:52:23.958440 DQS Delay:
6485 11:52:23.958521 DQS0 = 44, DQS1 = 56
6486 11:52:23.961820 DQM Delay:
6487 11:52:23.961915 DQM0 = 12, DQM1 = 12
6488 11:52:23.961993 DQ Delay:
6489 11:52:23.964720 DQ0 =12, DQ1 =12, DQ2 =12, DQ3 =8
6490 11:52:23.968295 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6491 11:52:23.972111 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6492 11:52:23.974926 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6493 11:52:23.975025
6494 11:52:23.975105
6495 11:52:23.985310 [DQSOSCAuto] RK0, (LSB)MR18= 0x8352, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6496 11:52:23.988240 CH0 RK0: MR19=C0C, MR18=8352
6497 11:52:23.991872 CH0_RK0: MR19=0xC0C, MR18=0x8352, DQSOSC=393, MR23=63, INC=382, DEC=254
6498 11:52:23.991971 ==
6499 11:52:23.994905 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 11:52:24.002083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:52:24.002169 ==
6502 11:52:24.005030 [Gating] SW mode calibration
6503 11:52:24.012068 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6504 11:52:24.015197 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6505 11:52:24.021544 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6506 11:52:24.025050 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6507 11:52:24.028361 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 11:52:24.035063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6509 11:52:24.038356 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6510 11:52:24.041907 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6511 11:52:24.045261 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6512 11:52:24.051858 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6513 11:52:24.055087 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6514 11:52:24.058544 Total UI for P1: 0, mck2ui 16
6515 11:52:24.062022 best dqsien dly found for B0: ( 0, 14, 24)
6516 11:52:24.065066 Total UI for P1: 0, mck2ui 16
6517 11:52:24.068381 best dqsien dly found for B1: ( 0, 14, 24)
6518 11:52:24.071731 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6519 11:52:24.074978 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6520 11:52:24.075065
6521 11:52:24.078414 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6522 11:52:24.081872 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6523 11:52:24.085671 [Gating] SW calibration Done
6524 11:52:24.085780 ==
6525 11:52:24.088467 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 11:52:24.095410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 11:52:24.095492 ==
6528 11:52:24.095556 RX Vref Scan: 0
6529 11:52:24.095616
6530 11:52:24.098422 RX Vref 0 -> 0, step: 1
6531 11:52:24.098490
6532 11:52:24.101947 RX Delay -410 -> 252, step: 16
6533 11:52:24.105060 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6534 11:52:24.108672 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6535 11:52:24.111923 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6536 11:52:24.118623 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6537 11:52:24.122011 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6538 11:52:24.125047 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6539 11:52:24.128813 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6540 11:52:24.135251 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6541 11:52:24.138797 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6542 11:52:24.141958 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6543 11:52:24.145719 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6544 11:52:24.151815 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6545 11:52:24.155330 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6546 11:52:24.158879 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6547 11:52:24.162010 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6548 11:52:24.168325 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6549 11:52:24.168405 ==
6550 11:52:24.172062 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 11:52:24.175441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 11:52:24.175522 ==
6553 11:52:24.175586 DQS Delay:
6554 11:52:24.178719 DQS0 = 43, DQS1 = 51
6555 11:52:24.178809 DQM Delay:
6556 11:52:24.181559 DQM0 = 11, DQM1 = 9
6557 11:52:24.181635 DQ Delay:
6558 11:52:24.185113 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6559 11:52:24.188749 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6560 11:52:24.192457 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6561 11:52:24.195235 DQ12 =8, DQ13 =16, DQ14 =16, DQ15 =16
6562 11:52:24.195311
6563 11:52:24.195373
6564 11:52:24.195437 ==
6565 11:52:24.198612 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 11:52:24.201663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 11:52:24.201739 ==
6568 11:52:24.201809
6569 11:52:24.201872
6570 11:52:24.205338 TX Vref Scan disable
6571 11:52:24.205433 == TX Byte 0 ==
6572 11:52:24.211990 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6573 11:52:24.215482 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6574 11:52:24.215563 == TX Byte 1 ==
6575 11:52:24.221963 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6576 11:52:24.225594 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6577 11:52:24.225675 ==
6578 11:52:24.228542 Dram Type= 6, Freq= 0, CH_0, rank 1
6579 11:52:24.231696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6580 11:52:24.231778 ==
6581 11:52:24.231862
6582 11:52:24.231941
6583 11:52:24.235331 TX Vref Scan disable
6584 11:52:24.235414 == TX Byte 0 ==
6585 11:52:24.241778 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6586 11:52:24.245367 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6587 11:52:24.245480 == TX Byte 1 ==
6588 11:52:24.251808 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6589 11:52:24.255306 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6590 11:52:24.255382
6591 11:52:24.255444 [DATLAT]
6592 11:52:24.258771 Freq=400, CH0 RK1
6593 11:52:24.258876
6594 11:52:24.258955 DATLAT Default: 0xe
6595 11:52:24.262055 0, 0xFFFF, sum = 0
6596 11:52:24.262130 1, 0xFFFF, sum = 0
6597 11:52:24.265276 2, 0xFFFF, sum = 0
6598 11:52:24.265363 3, 0xFFFF, sum = 0
6599 11:52:24.268875 4, 0xFFFF, sum = 0
6600 11:52:24.268964 5, 0xFFFF, sum = 0
6601 11:52:24.271996 6, 0xFFFF, sum = 0
6602 11:52:24.272077 7, 0xFFFF, sum = 0
6603 11:52:24.275823 8, 0xFFFF, sum = 0
6604 11:52:24.275909 9, 0xFFFF, sum = 0
6605 11:52:24.278758 10, 0xFFFF, sum = 0
6606 11:52:24.278857 11, 0xFFFF, sum = 0
6607 11:52:24.282014 12, 0xFFFF, sum = 0
6608 11:52:24.282091 13, 0x0, sum = 1
6609 11:52:24.285443 14, 0x0, sum = 2
6610 11:52:24.285523 15, 0x0, sum = 3
6611 11:52:24.288911 16, 0x0, sum = 4
6612 11:52:24.289020 best_step = 14
6613 11:52:24.289114
6614 11:52:24.289195 ==
6615 11:52:24.292445 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 11:52:24.299383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 11:52:24.299473 ==
6618 11:52:24.299545 RX Vref Scan: 0
6619 11:52:24.299617
6620 11:52:24.302789 RX Vref 0 -> 0, step: 1
6621 11:52:24.302911
6622 11:52:24.305379 RX Delay -343 -> 252, step: 8
6623 11:52:24.312447 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6624 11:52:24.315601 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6625 11:52:24.319435 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6626 11:52:24.322109 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6627 11:52:24.329129 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6628 11:52:24.332177 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6629 11:52:24.335788 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6630 11:52:24.339267 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6631 11:52:24.345671 iDelay=217, Bit 8, Center -60 (-303 ~ 184) 488
6632 11:52:24.349257 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6633 11:52:24.352313 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6634 11:52:24.355869 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6635 11:52:24.362237 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6636 11:52:24.365805 iDelay=217, Bit 13, Center -44 (-287 ~ 200) 488
6637 11:52:24.368973 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6638 11:52:24.372139 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6639 11:52:24.372224 ==
6640 11:52:24.375848 Dram Type= 6, Freq= 0, CH_0, rank 1
6641 11:52:24.382233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6642 11:52:24.382315 ==
6643 11:52:24.382380 DQS Delay:
6644 11:52:24.385800 DQS0 = 48, DQS1 = 60
6645 11:52:24.385897 DQM Delay:
6646 11:52:24.385963 DQM0 = 13, DQM1 = 12
6647 11:52:24.389407 DQ Delay:
6648 11:52:24.392336 DQ0 =16, DQ1 =16, DQ2 =8, DQ3 =12
6649 11:52:24.395905 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6650 11:52:24.395988 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6651 11:52:24.402815 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =24
6652 11:52:24.402923
6653 11:52:24.402990
6654 11:52:24.408934 [DQSOSCAuto] RK1, (LSB)MR18= 0x9769, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6655 11:52:24.412412 CH0 RK1: MR19=C0C, MR18=9769
6656 11:52:24.418980 CH0_RK1: MR19=0xC0C, MR18=0x9769, DQSOSC=390, MR23=63, INC=388, DEC=258
6657 11:52:24.422271 [RxdqsGatingPostProcess] freq 400
6658 11:52:24.425826 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6659 11:52:24.428923 best DQS0 dly(2T, 0.5T) = (0, 10)
6660 11:52:24.432518 best DQS1 dly(2T, 0.5T) = (0, 10)
6661 11:52:24.436000 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6662 11:52:24.439370 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6663 11:52:24.442570 best DQS0 dly(2T, 0.5T) = (0, 10)
6664 11:52:24.446172 best DQS1 dly(2T, 0.5T) = (0, 10)
6665 11:52:24.449127 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6666 11:52:24.452748 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6667 11:52:24.455805 Pre-setting of DQS Precalculation
6668 11:52:24.459140 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6669 11:52:24.459222 ==
6670 11:52:24.462692 Dram Type= 6, Freq= 0, CH_1, rank 0
6671 11:52:24.469512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6672 11:52:24.469594 ==
6673 11:52:24.472575 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6674 11:52:24.479550 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6675 11:52:24.482552 [CA 0] Center 36 (8~64) winsize 57
6676 11:52:24.485908 [CA 1] Center 36 (8~64) winsize 57
6677 11:52:24.489539 [CA 2] Center 36 (8~64) winsize 57
6678 11:52:24.492608 [CA 3] Center 36 (8~64) winsize 57
6679 11:52:24.495643 [CA 4] Center 36 (8~64) winsize 57
6680 11:52:24.499045 [CA 5] Center 36 (8~64) winsize 57
6681 11:52:24.499126
6682 11:52:24.502290 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6683 11:52:24.502390
6684 11:52:24.505971 [CATrainingPosCal] consider 1 rank data
6685 11:52:24.509296 u2DelayCellTimex100 = 270/100 ps
6686 11:52:24.512458 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:52:24.515704 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:52:24.519336 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 11:52:24.522349 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:52:24.526174 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:52:24.529512 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:52:24.529613
6693 11:52:24.532552 CA PerBit enable=1, Macro0, CA PI delay=36
6694 11:52:24.536174
6695 11:52:24.536246 [CBTSetCACLKResult] CA Dly = 36
6696 11:52:24.539244 CS Dly: 1 (0~32)
6697 11:52:24.539315 ==
6698 11:52:24.542938 Dram Type= 6, Freq= 0, CH_1, rank 1
6699 11:52:24.546000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 11:52:24.546084 ==
6701 11:52:24.552736 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6702 11:52:24.559296 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6703 11:52:24.562501 [CA 0] Center 36 (8~64) winsize 57
6704 11:52:24.562613 [CA 1] Center 36 (8~64) winsize 57
6705 11:52:24.566262 [CA 2] Center 36 (8~64) winsize 57
6706 11:52:24.569267 [CA 3] Center 36 (8~64) winsize 57
6707 11:52:24.572816 [CA 4] Center 36 (8~64) winsize 57
6708 11:52:24.575868 [CA 5] Center 36 (8~64) winsize 57
6709 11:52:24.575950
6710 11:52:24.579458 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6711 11:52:24.579540
6712 11:52:24.582365 [CATrainingPosCal] consider 2 rank data
6713 11:52:24.586015 u2DelayCellTimex100 = 270/100 ps
6714 11:52:24.589292 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6715 11:52:24.595931 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6716 11:52:24.599364 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6717 11:52:24.602518 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:52:24.605942 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:52:24.609671 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:52:24.609771
6721 11:52:24.612429 CA PerBit enable=1, Macro0, CA PI delay=36
6722 11:52:24.612512
6723 11:52:24.616382 [CBTSetCACLKResult] CA Dly = 36
6724 11:52:24.616464 CS Dly: 1 (0~32)
6725 11:52:24.616528
6726 11:52:24.619276 ----->DramcWriteLeveling(PI) begin...
6727 11:52:24.622789 ==
6728 11:52:24.626142 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:52:24.629526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:52:24.629606 ==
6731 11:52:24.632870 Write leveling (Byte 0): 40 => 8
6732 11:52:24.636030 Write leveling (Byte 1): 40 => 8
6733 11:52:24.636114 DramcWriteLeveling(PI) end<-----
6734 11:52:24.639459
6735 11:52:24.639539 ==
6736 11:52:24.643001 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 11:52:24.646129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 11:52:24.646209 ==
6739 11:52:24.649786 [Gating] SW mode calibration
6740 11:52:24.656082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6741 11:52:24.659148 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6742 11:52:24.666254 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6743 11:52:24.669537 0 11 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
6744 11:52:24.673015 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 11:52:24.679222 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6746 11:52:24.682721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6747 11:52:24.686605 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6748 11:52:24.693018 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6749 11:52:24.696499 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6750 11:52:24.699831 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6751 11:52:24.702615 Total UI for P1: 0, mck2ui 16
6752 11:52:24.705906 best dqsien dly found for B0: ( 0, 14, 24)
6753 11:52:24.709577 Total UI for P1: 0, mck2ui 16
6754 11:52:24.712740 best dqsien dly found for B1: ( 0, 14, 24)
6755 11:52:24.716086 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6756 11:52:24.719296 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6757 11:52:24.719369
6758 11:52:24.726005 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6759 11:52:24.729301 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6760 11:52:24.729373 [Gating] SW calibration Done
6761 11:52:24.732481 ==
6762 11:52:24.732558 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 11:52:24.739960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 11:52:24.740039 ==
6765 11:52:24.740119 RX Vref Scan: 0
6766 11:52:24.740263
6767 11:52:24.742665 RX Vref 0 -> 0, step: 1
6768 11:52:24.742790
6769 11:52:24.745878 RX Delay -410 -> 252, step: 16
6770 11:52:24.749339 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6771 11:52:24.752609 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6772 11:52:24.759727 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6773 11:52:24.762755 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6774 11:52:24.766155 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6775 11:52:24.769746 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6776 11:52:24.776097 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6777 11:52:24.779834 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6778 11:52:24.782969 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6779 11:52:24.786062 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6780 11:52:24.792892 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6781 11:52:24.796665 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6782 11:52:24.799744 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6783 11:52:24.803218 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6784 11:52:24.809744 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6785 11:52:24.812880 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6786 11:52:24.812998 ==
6787 11:52:24.816491 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 11:52:24.819774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 11:52:24.819885 ==
6790 11:52:24.822897 DQS Delay:
6791 11:52:24.822974 DQS0 = 51, DQS1 = 59
6792 11:52:24.823038 DQM Delay:
6793 11:52:24.826507 DQM0 = 18, DQM1 = 16
6794 11:52:24.826590 DQ Delay:
6795 11:52:24.829874 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6796 11:52:24.832956 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6797 11:52:24.836405 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6798 11:52:24.839912 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6799 11:52:24.839993
6800 11:52:24.840061
6801 11:52:24.840120 ==
6802 11:52:24.843119 Dram Type= 6, Freq= 0, CH_1, rank 0
6803 11:52:24.846473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6804 11:52:24.849994 ==
6805 11:52:24.850079
6806 11:52:24.850144
6807 11:52:24.850203 TX Vref Scan disable
6808 11:52:24.852769 == TX Byte 0 ==
6809 11:52:24.856146 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6810 11:52:24.859831 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6811 11:52:24.862802 == TX Byte 1 ==
6812 11:52:24.866143 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6813 11:52:24.869592 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6814 11:52:24.869706 ==
6815 11:52:24.873141 Dram Type= 6, Freq= 0, CH_1, rank 0
6816 11:52:24.879801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6817 11:52:24.879890 ==
6818 11:52:24.879956
6819 11:52:24.880016
6820 11:52:24.880103 TX Vref Scan disable
6821 11:52:24.883364 == TX Byte 0 ==
6822 11:52:24.886898 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6823 11:52:24.889563 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6824 11:52:24.893188 == TX Byte 1 ==
6825 11:52:24.896937 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6826 11:52:24.900207 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6827 11:52:24.900287
6828 11:52:24.900358 [DATLAT]
6829 11:52:24.902879 Freq=400, CH1 RK0
6830 11:52:24.902959
6831 11:52:24.906570 DATLAT Default: 0xf
6832 11:52:24.906651 0, 0xFFFF, sum = 0
6833 11:52:24.910028 1, 0xFFFF, sum = 0
6834 11:52:24.910112 2, 0xFFFF, sum = 0
6835 11:52:24.913164 3, 0xFFFF, sum = 0
6836 11:52:24.913245 4, 0xFFFF, sum = 0
6837 11:52:24.916524 5, 0xFFFF, sum = 0
6838 11:52:24.916609 6, 0xFFFF, sum = 0
6839 11:52:24.920182 7, 0xFFFF, sum = 0
6840 11:52:24.920262 8, 0xFFFF, sum = 0
6841 11:52:24.922907 9, 0xFFFF, sum = 0
6842 11:52:24.922987 10, 0xFFFF, sum = 0
6843 11:52:24.926436 11, 0xFFFF, sum = 0
6844 11:52:24.926516 12, 0xFFFF, sum = 0
6845 11:52:24.929724 13, 0x0, sum = 1
6846 11:52:24.929839 14, 0x0, sum = 2
6847 11:52:24.933452 15, 0x0, sum = 3
6848 11:52:24.933547 16, 0x0, sum = 4
6849 11:52:24.936340 best_step = 14
6850 11:52:24.936422
6851 11:52:24.936487 ==
6852 11:52:24.939723 Dram Type= 6, Freq= 0, CH_1, rank 0
6853 11:52:24.943195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 11:52:24.943275 ==
6855 11:52:24.946509 RX Vref Scan: 1
6856 11:52:24.946592
6857 11:52:24.946656 RX Vref 0 -> 0, step: 1
6858 11:52:24.946716
6859 11:52:24.950163 RX Delay -359 -> 252, step: 8
6860 11:52:24.950242
6861 11:52:24.953716 Set Vref, RX VrefLevel [Byte0]: 60
6862 11:52:24.956489 [Byte1]: 53
6863 11:52:24.961162
6864 11:52:24.961267 Final RX Vref Byte 0 = 60 to rank0
6865 11:52:24.964364 Final RX Vref Byte 1 = 53 to rank0
6866 11:52:24.967851 Final RX Vref Byte 0 = 60 to rank1
6867 11:52:24.970673 Final RX Vref Byte 1 = 53 to rank1==
6868 11:52:24.974012 Dram Type= 6, Freq= 0, CH_1, rank 0
6869 11:52:24.981209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6870 11:52:24.981295 ==
6871 11:52:24.981360 DQS Delay:
6872 11:52:24.984124 DQS0 = 52, DQS1 = 64
6873 11:52:24.984210 DQM Delay:
6874 11:52:24.984276 DQM0 = 15, DQM1 = 16
6875 11:52:24.987338 DQ Delay:
6876 11:52:24.990664 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6877 11:52:24.990784 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =16
6878 11:52:24.994007 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =16
6879 11:52:24.998040 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6880 11:52:24.998129
6881 11:52:25.001094
6882 11:52:25.007494 [DQSOSCAuto] RK0, (LSB)MR18= 0x933a, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 391 ps
6883 11:52:25.011045 CH1 RK0: MR19=C0C, MR18=933A
6884 11:52:25.017752 CH1_RK0: MR19=0xC0C, MR18=0x933A, DQSOSC=391, MR23=63, INC=386, DEC=257
6885 11:52:25.017865 ==
6886 11:52:25.020830 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 11:52:25.024818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:52:25.024905 ==
6889 11:52:25.027420 [Gating] SW mode calibration
6890 11:52:25.034644 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6891 11:52:25.038064 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6892 11:52:25.044596 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6893 11:52:25.047707 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6894 11:52:25.050852 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 11:52:25.057969 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6896 11:52:25.061430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6897 11:52:25.064293 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6898 11:52:25.070881 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6899 11:52:25.074438 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6900 11:52:25.077959 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6901 11:52:25.081036 Total UI for P1: 0, mck2ui 16
6902 11:52:25.084595 best dqsien dly found for B0: ( 0, 14, 24)
6903 11:52:25.087757 Total UI for P1: 0, mck2ui 16
6904 11:52:25.091029 best dqsien dly found for B1: ( 0, 14, 24)
6905 11:52:25.094168 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6906 11:52:25.097727 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6907 11:52:25.097872
6908 11:52:25.101218 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6909 11:52:25.107826 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6910 11:52:25.107927 [Gating] SW calibration Done
6911 11:52:25.107994 ==
6912 11:52:25.111331 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 11:52:25.118179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 11:52:25.118268 ==
6915 11:52:25.118358 RX Vref Scan: 0
6916 11:52:25.118455
6917 11:52:25.121884 RX Vref 0 -> 0, step: 1
6918 11:52:25.121968
6919 11:52:25.124910 RX Delay -410 -> 252, step: 16
6920 11:52:25.127750 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6921 11:52:25.131205 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6922 11:52:25.138027 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6923 11:52:25.140928 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6924 11:52:25.144594 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6925 11:52:25.147584 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6926 11:52:25.154590 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6927 11:52:25.157565 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6928 11:52:25.161265 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6929 11:52:25.164668 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6930 11:52:25.170904 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6931 11:52:25.174786 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6932 11:52:25.177587 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6933 11:52:25.180964 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6934 11:52:25.187710 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6935 11:52:25.191361 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6936 11:52:25.191443 ==
6937 11:52:25.194808 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 11:52:25.197885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 11:52:25.197989 ==
6940 11:52:25.201092 DQS Delay:
6941 11:52:25.201197 DQS0 = 51, DQS1 = 59
6942 11:52:25.204438 DQM Delay:
6943 11:52:25.204540 DQM0 = 16, DQM1 = 19
6944 11:52:25.204630 DQ Delay:
6945 11:52:25.207776 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16
6946 11:52:25.211312 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6947 11:52:25.214382 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6948 11:52:25.217818 DQ12 =24, DQ13 =32, DQ14 =32, DQ15 =32
6949 11:52:25.217917
6950 11:52:25.217985
6951 11:52:25.218044 ==
6952 11:52:25.221478 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 11:52:25.227732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 11:52:25.227820 ==
6955 11:52:25.227885
6956 11:52:25.227946
6957 11:52:25.228004 TX Vref Scan disable
6958 11:52:25.231225 == TX Byte 0 ==
6959 11:52:25.234733 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6960 11:52:25.238000 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6961 11:52:25.241371 == TX Byte 1 ==
6962 11:52:25.244741 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6963 11:52:25.247669 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6964 11:52:25.247751 ==
6965 11:52:25.251300 Dram Type= 6, Freq= 0, CH_1, rank 1
6966 11:52:25.257843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6967 11:52:25.257925 ==
6968 11:52:25.257991
6969 11:52:25.258050
6970 11:52:25.258108 TX Vref Scan disable
6971 11:52:25.261101 == TX Byte 0 ==
6972 11:52:25.264764 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6973 11:52:25.267709 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6974 11:52:25.271436 == TX Byte 1 ==
6975 11:52:25.274835 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6976 11:52:25.278491 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6977 11:52:25.278595
6978 11:52:25.281254 [DATLAT]
6979 11:52:25.281354 Freq=400, CH1 RK1
6980 11:52:25.281445
6981 11:52:25.284777 DATLAT Default: 0xe
6982 11:52:25.284873 0, 0xFFFF, sum = 0
6983 11:52:25.288080 1, 0xFFFF, sum = 0
6984 11:52:25.288183 2, 0xFFFF, sum = 0
6985 11:52:25.291536 3, 0xFFFF, sum = 0
6986 11:52:25.291613 4, 0xFFFF, sum = 0
6987 11:52:25.294988 5, 0xFFFF, sum = 0
6988 11:52:25.295064 6, 0xFFFF, sum = 0
6989 11:52:25.298011 7, 0xFFFF, sum = 0
6990 11:52:25.298086 8, 0xFFFF, sum = 0
6991 11:52:25.301471 9, 0xFFFF, sum = 0
6992 11:52:25.301546 10, 0xFFFF, sum = 0
6993 11:52:25.305000 11, 0xFFFF, sum = 0
6994 11:52:25.305105 12, 0xFFFF, sum = 0
6995 11:52:25.308178 13, 0x0, sum = 1
6996 11:52:25.308285 14, 0x0, sum = 2
6997 11:52:25.311324 15, 0x0, sum = 3
6998 11:52:25.311401 16, 0x0, sum = 4
6999 11:52:25.314927 best_step = 14
7000 11:52:25.315008
7001 11:52:25.315093 ==
7002 11:52:25.318413 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 11:52:25.321421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 11:52:25.321524 ==
7005 11:52:25.321617 RX Vref Scan: 0
7006 11:52:25.325146
7007 11:52:25.325247 RX Vref 0 -> 0, step: 1
7008 11:52:25.325337
7009 11:52:25.328342 RX Delay -359 -> 252, step: 8
7010 11:52:25.335534 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
7011 11:52:25.339118 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
7012 11:52:25.342372 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
7013 11:52:25.345851 iDelay=217, Bit 3, Center -44 (-287 ~ 200) 488
7014 11:52:25.352596 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
7015 11:52:25.356371 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7016 11:52:25.359494 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7017 11:52:25.362750 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
7018 11:52:25.369109 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
7019 11:52:25.373121 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
7020 11:52:25.376238 iDelay=217, Bit 10, Center -48 (-295 ~ 200) 496
7021 11:52:25.379028 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7022 11:52:25.385968 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
7023 11:52:25.389405 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
7024 11:52:25.392254 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
7025 11:52:25.395607 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
7026 11:52:25.399011 ==
7027 11:52:25.402773 Dram Type= 6, Freq= 0, CH_1, rank 1
7028 11:52:25.406218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 11:52:25.406327 ==
7030 11:52:25.406428 DQS Delay:
7031 11:52:25.409687 DQS0 = 52, DQS1 = 56
7032 11:52:25.409793 DQM Delay:
7033 11:52:25.412723 DQM0 = 13, DQM1 = 9
7034 11:52:25.412830 DQ Delay:
7035 11:52:25.416149 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7036 11:52:25.419485 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7037 11:52:25.422506 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
7038 11:52:25.425798 DQ12 =12, DQ13 =16, DQ14 =16, DQ15 =16
7039 11:52:25.425903
7040 11:52:25.425996
7041 11:52:25.432679 [DQSOSCAuto] RK1, (LSB)MR18= 0x7f94, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 393 ps
7042 11:52:25.435496 CH1 RK1: MR19=C0C, MR18=7F94
7043 11:52:25.442540 CH1_RK1: MR19=0xC0C, MR18=0x7F94, DQSOSC=391, MR23=63, INC=386, DEC=257
7044 11:52:25.445839 [RxdqsGatingPostProcess] freq 400
7045 11:52:25.449374 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7046 11:52:25.452200 best DQS0 dly(2T, 0.5T) = (0, 10)
7047 11:52:25.456127 best DQS1 dly(2T, 0.5T) = (0, 10)
7048 11:52:25.459102 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7049 11:52:25.462267 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7050 11:52:25.465561 best DQS0 dly(2T, 0.5T) = (0, 10)
7051 11:52:25.469227 best DQS1 dly(2T, 0.5T) = (0, 10)
7052 11:52:25.472697 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7053 11:52:25.476198 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7054 11:52:25.479052 Pre-setting of DQS Precalculation
7055 11:52:25.482295 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7056 11:52:25.489126 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7057 11:52:25.499407 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7058 11:52:25.499507
7059 11:52:25.499573
7060 11:52:25.502449 [Calibration Summary] 800 Mbps
7061 11:52:25.502553 CH 0, Rank 0
7062 11:52:25.506268 SW Impedance : PASS
7063 11:52:25.506380 DUTY Scan : NO K
7064 11:52:25.509625 ZQ Calibration : PASS
7065 11:52:25.512364 Jitter Meter : NO K
7066 11:52:25.512469 CBT Training : PASS
7067 11:52:25.515758 Write leveling : PASS
7068 11:52:25.515835 RX DQS gating : PASS
7069 11:52:25.518932 RX DQ/DQS(RDDQC) : PASS
7070 11:52:25.522221 TX DQ/DQS : PASS
7071 11:52:25.522294 RX DATLAT : PASS
7072 11:52:25.525926 RX DQ/DQS(Engine): PASS
7073 11:52:25.529393 TX OE : NO K
7074 11:52:25.529497 All Pass.
7075 11:52:25.529588
7076 11:52:25.529676 CH 0, Rank 1
7077 11:52:25.532307 SW Impedance : PASS
7078 11:52:25.535865 DUTY Scan : NO K
7079 11:52:25.535945 ZQ Calibration : PASS
7080 11:52:25.538868 Jitter Meter : NO K
7081 11:52:25.542358 CBT Training : PASS
7082 11:52:25.542436 Write leveling : NO K
7083 11:52:25.545762 RX DQS gating : PASS
7084 11:52:25.549391 RX DQ/DQS(RDDQC) : PASS
7085 11:52:25.549468 TX DQ/DQS : PASS
7086 11:52:25.552735 RX DATLAT : PASS
7087 11:52:25.555994 RX DQ/DQS(Engine): PASS
7088 11:52:25.556084 TX OE : NO K
7089 11:52:25.556191 All Pass.
7090 11:52:25.556283
7091 11:52:25.559144 CH 1, Rank 0
7092 11:52:25.562375 SW Impedance : PASS
7093 11:52:25.562478 DUTY Scan : NO K
7094 11:52:25.565838 ZQ Calibration : PASS
7095 11:52:25.565942 Jitter Meter : NO K
7096 11:52:25.569241 CBT Training : PASS
7097 11:52:25.572475 Write leveling : PASS
7098 11:52:25.572584 RX DQS gating : PASS
7099 11:52:25.575513 RX DQ/DQS(RDDQC) : PASS
7100 11:52:25.578975 TX DQ/DQS : PASS
7101 11:52:25.579081 RX DATLAT : PASS
7102 11:52:25.582513 RX DQ/DQS(Engine): PASS
7103 11:52:25.585747 TX OE : NO K
7104 11:52:25.585854 All Pass.
7105 11:52:25.585947
7106 11:52:25.586036 CH 1, Rank 1
7107 11:52:25.589367 SW Impedance : PASS
7108 11:52:25.592887 DUTY Scan : NO K
7109 11:52:25.592991 ZQ Calibration : PASS
7110 11:52:25.596136 Jitter Meter : NO K
7111 11:52:25.599481 CBT Training : PASS
7112 11:52:25.599586 Write leveling : NO K
7113 11:52:25.602642 RX DQS gating : PASS
7114 11:52:25.602744 RX DQ/DQS(RDDQC) : PASS
7115 11:52:25.605633 TX DQ/DQS : PASS
7116 11:52:25.608942 RX DATLAT : PASS
7117 11:52:25.609049 RX DQ/DQS(Engine): PASS
7118 11:52:25.612770 TX OE : NO K
7119 11:52:25.612886 All Pass.
7120 11:52:25.612981
7121 11:52:25.615684 DramC Write-DBI off
7122 11:52:25.619179 PER_BANK_REFRESH: Hybrid Mode
7123 11:52:25.619260 TX_TRACKING: ON
7124 11:52:25.629426 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7125 11:52:25.632405 [FAST_K] Save calibration result to emmc
7126 11:52:25.636180 dramc_set_vcore_voltage set vcore to 725000
7127 11:52:25.639007 Read voltage for 1600, 0
7128 11:52:25.639115 Vio18 = 0
7129 11:52:25.639209 Vcore = 725000
7130 11:52:25.642445 Vdram = 0
7131 11:52:25.642548 Vddq = 0
7132 11:52:25.642639 Vmddr = 0
7133 11:52:25.649344 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7134 11:52:25.652768 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7135 11:52:25.656315 MEM_TYPE=3, freq_sel=13
7136 11:52:25.659258 sv_algorithm_assistance_LP4_3733
7137 11:52:25.662607 ============ PULL DRAM RESETB DOWN ============
7138 11:52:25.666085 ========== PULL DRAM RESETB DOWN end =========
7139 11:52:25.672916 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7140 11:52:25.676354 ===================================
7141 11:52:25.676458 LPDDR4 DRAM CONFIGURATION
7142 11:52:25.679272 ===================================
7143 11:52:25.682693 EX_ROW_EN[0] = 0x0
7144 11:52:25.685986 EX_ROW_EN[1] = 0x0
7145 11:52:25.686093 LP4Y_EN = 0x0
7146 11:52:25.689650 WORK_FSP = 0x1
7147 11:52:25.689759 WL = 0x5
7148 11:52:25.692955 RL = 0x5
7149 11:52:25.693062 BL = 0x2
7150 11:52:25.696018 RPST = 0x0
7151 11:52:25.696121 RD_PRE = 0x0
7152 11:52:25.699179 WR_PRE = 0x1
7153 11:52:25.699285 WR_PST = 0x1
7154 11:52:25.703201 DBI_WR = 0x0
7155 11:52:25.703307 DBI_RD = 0x0
7156 11:52:25.706399 OTF = 0x1
7157 11:52:25.709233 ===================================
7158 11:52:25.712648 ===================================
7159 11:52:25.712763 ANA top config
7160 11:52:25.716017 ===================================
7161 11:52:25.719690 DLL_ASYNC_EN = 0
7162 11:52:25.723229 ALL_SLAVE_EN = 0
7163 11:52:25.723308 NEW_RANK_MODE = 1
7164 11:52:25.726320 DLL_IDLE_MODE = 1
7165 11:52:25.729752 LP45_APHY_COMB_EN = 1
7166 11:52:25.733295 TX_ODT_DIS = 0
7167 11:52:25.736799 NEW_8X_MODE = 1
7168 11:52:25.739390 ===================================
7169 11:52:25.742871 ===================================
7170 11:52:25.742955 data_rate = 3200
7171 11:52:25.746360 CKR = 1
7172 11:52:25.749367 DQ_P2S_RATIO = 8
7173 11:52:25.752820 ===================================
7174 11:52:25.756717 CA_P2S_RATIO = 8
7175 11:52:25.759371 DQ_CA_OPEN = 0
7176 11:52:25.762954 DQ_SEMI_OPEN = 0
7177 11:52:25.763036 CA_SEMI_OPEN = 0
7178 11:52:25.766454 CA_FULL_RATE = 0
7179 11:52:25.769943 DQ_CKDIV4_EN = 0
7180 11:52:25.773220 CA_CKDIV4_EN = 0
7181 11:52:25.776667 CA_PREDIV_EN = 0
7182 11:52:25.776774 PH8_DLY = 12
7183 11:52:25.779604 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7184 11:52:25.783183 DQ_AAMCK_DIV = 4
7185 11:52:25.786259 CA_AAMCK_DIV = 4
7186 11:52:25.789497 CA_ADMCK_DIV = 4
7187 11:52:25.793001 DQ_TRACK_CA_EN = 0
7188 11:52:25.795998 CA_PICK = 1600
7189 11:52:25.796090 CA_MCKIO = 1600
7190 11:52:25.799425 MCKIO_SEMI = 0
7191 11:52:25.803297 PLL_FREQ = 3068
7192 11:52:25.806711 DQ_UI_PI_RATIO = 32
7193 11:52:25.809854 CA_UI_PI_RATIO = 0
7194 11:52:25.812962 ===================================
7195 11:52:25.816786 ===================================
7196 11:52:25.819834 memory_type:LPDDR4
7197 11:52:25.819921 GP_NUM : 10
7198 11:52:25.822836 SRAM_EN : 1
7199 11:52:25.822935 MD32_EN : 0
7200 11:52:25.826004 ===================================
7201 11:52:25.829899 [ANA_INIT] >>>>>>>>>>>>>>
7202 11:52:25.833050 <<<<<< [CONFIGURE PHASE]: ANA_TX
7203 11:52:25.836348 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7204 11:52:25.839627 ===================================
7205 11:52:25.843300 data_rate = 3200,PCW = 0X7600
7206 11:52:25.846197 ===================================
7207 11:52:25.849563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7208 11:52:25.853430 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7209 11:52:25.859695 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7210 11:52:25.862825 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7211 11:52:25.869921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7212 11:52:25.873048 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7213 11:52:25.873137 [ANA_INIT] flow start
7214 11:52:25.876511 [ANA_INIT] PLL >>>>>>>>
7215 11:52:25.879570 [ANA_INIT] PLL <<<<<<<<
7216 11:52:25.879657 [ANA_INIT] MIDPI >>>>>>>>
7217 11:52:25.882987 [ANA_INIT] MIDPI <<<<<<<<
7218 11:52:25.886578 [ANA_INIT] DLL >>>>>>>>
7219 11:52:25.886666 [ANA_INIT] DLL <<<<<<<<
7220 11:52:25.889956 [ANA_INIT] flow end
7221 11:52:25.893199 ============ LP4 DIFF to SE enter ============
7222 11:52:25.896129 ============ LP4 DIFF to SE exit ============
7223 11:52:25.899381 [ANA_INIT] <<<<<<<<<<<<<
7224 11:52:25.902768 [Flow] Enable top DCM control >>>>>
7225 11:52:25.906022 [Flow] Enable top DCM control <<<<<
7226 11:52:25.909910 Enable DLL master slave shuffle
7227 11:52:25.916607 ==============================================================
7228 11:52:25.916695 Gating Mode config
7229 11:52:25.922976 ==============================================================
7230 11:52:25.923063 Config description:
7231 11:52:25.932921 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7232 11:52:25.939291 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7233 11:52:25.946341 SELPH_MODE 0: By rank 1: By Phase
7234 11:52:25.949701 ==============================================================
7235 11:52:25.952661 GAT_TRACK_EN = 1
7236 11:52:25.956215 RX_GATING_MODE = 2
7237 11:52:25.959444 RX_GATING_TRACK_MODE = 2
7238 11:52:25.963530 SELPH_MODE = 1
7239 11:52:25.966544 PICG_EARLY_EN = 1
7240 11:52:25.970009 VALID_LAT_VALUE = 1
7241 11:52:25.972783 ==============================================================
7242 11:52:25.976179 Enter into Gating configuration >>>>
7243 11:52:25.979591 Exit from Gating configuration <<<<
7244 11:52:25.982987 Enter into DVFS_PRE_config >>>>>
7245 11:52:25.995996 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7246 11:52:25.999630 Exit from DVFS_PRE_config <<<<<
7247 11:52:26.003207 Enter into PICG configuration >>>>
7248 11:52:26.003291 Exit from PICG configuration <<<<
7249 11:52:26.006505 [RX_INPUT] configuration >>>>>
7250 11:52:26.009333 [RX_INPUT] configuration <<<<<
7251 11:52:26.016718 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7252 11:52:26.019543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7253 11:52:26.026185 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7254 11:52:26.032775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7255 11:52:26.039791 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7256 11:52:26.046582 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7257 11:52:26.049682 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7258 11:52:26.052990 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7259 11:52:26.056405 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7260 11:52:26.063408 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7261 11:52:26.066011 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7262 11:52:26.069378 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7263 11:52:26.072971 ===================================
7264 11:52:26.076204 LPDDR4 DRAM CONFIGURATION
7265 11:52:26.079453 ===================================
7266 11:52:26.079540 EX_ROW_EN[0] = 0x0
7267 11:52:26.082857 EX_ROW_EN[1] = 0x0
7268 11:52:26.086308 LP4Y_EN = 0x0
7269 11:52:26.086393 WORK_FSP = 0x1
7270 11:52:26.089412 WL = 0x5
7271 11:52:26.089494 RL = 0x5
7272 11:52:26.093063 BL = 0x2
7273 11:52:26.093174 RPST = 0x0
7274 11:52:26.096706 RD_PRE = 0x0
7275 11:52:26.096803 WR_PRE = 0x1
7276 11:52:26.100013 WR_PST = 0x1
7277 11:52:26.100110 DBI_WR = 0x0
7278 11:52:26.102900 DBI_RD = 0x0
7279 11:52:26.103011 OTF = 0x1
7280 11:52:26.106365 ===================================
7281 11:52:26.109619 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7282 11:52:26.116510 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7283 11:52:26.119944 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7284 11:52:26.123207 ===================================
7285 11:52:26.126594 LPDDR4 DRAM CONFIGURATION
7286 11:52:26.130061 ===================================
7287 11:52:26.130138 EX_ROW_EN[0] = 0x10
7288 11:52:26.133098 EX_ROW_EN[1] = 0x0
7289 11:52:26.133169 LP4Y_EN = 0x0
7290 11:52:26.136647 WORK_FSP = 0x1
7291 11:52:26.136723 WL = 0x5
7292 11:52:26.139942 RL = 0x5
7293 11:52:26.140012 BL = 0x2
7294 11:52:26.143171 RPST = 0x0
7295 11:52:26.143253 RD_PRE = 0x0
7296 11:52:26.146364 WR_PRE = 0x1
7297 11:52:26.149732 WR_PST = 0x1
7298 11:52:26.149814 DBI_WR = 0x0
7299 11:52:26.153191 DBI_RD = 0x0
7300 11:52:26.153273 OTF = 0x1
7301 11:52:26.156300 ===================================
7302 11:52:26.163251 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7303 11:52:26.163336 ==
7304 11:52:26.166352 Dram Type= 6, Freq= 0, CH_0, rank 0
7305 11:52:26.169866 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7306 11:52:26.169950 ==
7307 11:52:26.173336 [Duty_Offset_Calibration]
7308 11:52:26.173418 B0:2 B1:-1 CA:1
7309 11:52:26.177132
7310 11:52:26.177241 [DutyScan_Calibration_Flow] k_type=0
7311 11:52:26.187175
7312 11:52:26.187263 ==CLK 0==
7313 11:52:26.190337 Final CLK duty delay cell = -4
7314 11:52:26.193829 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7315 11:52:26.197012 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7316 11:52:26.200475 [-4] AVG Duty = 4937%(X100)
7317 11:52:26.200549
7318 11:52:26.203952 CH0 CLK Duty spec in!! Max-Min= 187%
7319 11:52:26.206802 [DutyScan_Calibration_Flow] ====Done====
7320 11:52:26.206904
7321 11:52:26.210318 [DutyScan_Calibration_Flow] k_type=1
7322 11:52:26.226525
7323 11:52:26.226638 ==DQS 0 ==
7324 11:52:26.229816 Final DQS duty delay cell = 0
7325 11:52:26.233374 [0] MAX Duty = 5125%(X100), DQS PI = 20
7326 11:52:26.236669 [0] MIN Duty = 5000%(X100), DQS PI = 14
7327 11:52:26.236746 [0] AVG Duty = 5062%(X100)
7328 11:52:26.239984
7329 11:52:26.240060 ==DQS 1 ==
7330 11:52:26.243499 Final DQS duty delay cell = -4
7331 11:52:26.246543 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7332 11:52:26.249971 [-4] MIN Duty = 5031%(X100), DQS PI = 8
7333 11:52:26.253450 [-4] AVG Duty = 5062%(X100)
7334 11:52:26.253534
7335 11:52:26.256741 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7336 11:52:26.256825
7337 11:52:26.260001 CH0 DQS 1 Duty spec in!! Max-Min= 62%
7338 11:52:26.263379 [DutyScan_Calibration_Flow] ====Done====
7339 11:52:26.263462
7340 11:52:26.266917 [DutyScan_Calibration_Flow] k_type=3
7341 11:52:26.283903
7342 11:52:26.284012 ==DQM 0 ==
7343 11:52:26.287144 Final DQM duty delay cell = 0
7344 11:52:26.290232 [0] MAX Duty = 5000%(X100), DQS PI = 18
7345 11:52:26.293519 [0] MIN Duty = 4875%(X100), DQS PI = 4
7346 11:52:26.293604 [0] AVG Duty = 4937%(X100)
7347 11:52:26.297067
7348 11:52:26.297150 ==DQM 1 ==
7349 11:52:26.300766 Final DQM duty delay cell = 0
7350 11:52:26.304011 [0] MAX Duty = 5187%(X100), DQS PI = 58
7351 11:52:26.307322 [0] MIN Duty = 4969%(X100), DQS PI = 18
7352 11:52:26.307408 [0] AVG Duty = 5078%(X100)
7353 11:52:26.310760
7354 11:52:26.313575 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7355 11:52:26.313659
7356 11:52:26.317050 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7357 11:52:26.320670 [DutyScan_Calibration_Flow] ====Done====
7358 11:52:26.320752
7359 11:52:26.323981 [DutyScan_Calibration_Flow] k_type=2
7360 11:52:26.340905
7361 11:52:26.341011 ==DQ 0 ==
7362 11:52:26.344506 Final DQ duty delay cell = 0
7363 11:52:26.347368 [0] MAX Duty = 5156%(X100), DQS PI = 0
7364 11:52:26.351057 [0] MIN Duty = 5031%(X100), DQS PI = 12
7365 11:52:26.351139 [0] AVG Duty = 5093%(X100)
7366 11:52:26.351204
7367 11:52:26.354320 ==DQ 1 ==
7368 11:52:26.354403 Final DQ duty delay cell = 0
7369 11:52:26.361212 [0] MAX Duty = 5031%(X100), DQS PI = 14
7370 11:52:26.364617 [0] MIN Duty = 4907%(X100), DQS PI = 18
7371 11:52:26.364701 [0] AVG Duty = 4969%(X100)
7372 11:52:26.364766
7373 11:52:26.367920 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7374 11:52:26.368004
7375 11:52:26.370762 CH0 DQ 1 Duty spec in!! Max-Min= 124%
7376 11:52:26.377581 [DutyScan_Calibration_Flow] ====Done====
7377 11:52:26.377664 ==
7378 11:52:26.381306 Dram Type= 6, Freq= 0, CH_1, rank 0
7379 11:52:26.384297 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7380 11:52:26.384379 ==
7381 11:52:26.387931 [Duty_Offset_Calibration]
7382 11:52:26.388016 B0:1 B1:1 CA:2
7383 11:52:26.388079
7384 11:52:26.390974 [DutyScan_Calibration_Flow] k_type=0
7385 11:52:26.400600
7386 11:52:26.400720 ==CLK 0==
7387 11:52:26.404168 Final CLK duty delay cell = 0
7388 11:52:26.407818 [0] MAX Duty = 5187%(X100), DQS PI = 24
7389 11:52:26.410780 [0] MIN Duty = 4938%(X100), DQS PI = 48
7390 11:52:26.410896 [0] AVG Duty = 5062%(X100)
7391 11:52:26.414135
7392 11:52:26.414209 CH1 CLK Duty spec in!! Max-Min= 249%
7393 11:52:26.420862 [DutyScan_Calibration_Flow] ====Done====
7394 11:52:26.420966
7395 11:52:26.424169 [DutyScan_Calibration_Flow] k_type=1
7396 11:52:26.440756
7397 11:52:26.440870 ==DQS 0 ==
7398 11:52:26.443985 Final DQS duty delay cell = 0
7399 11:52:26.447419 [0] MAX Duty = 5062%(X100), DQS PI = 20
7400 11:52:26.450875 [0] MIN Duty = 4813%(X100), DQS PI = 52
7401 11:52:26.450959 [0] AVG Duty = 4937%(X100)
7402 11:52:26.454142
7403 11:52:26.454226 ==DQS 1 ==
7404 11:52:26.457157 Final DQS duty delay cell = 0
7405 11:52:26.460947 [0] MAX Duty = 5031%(X100), DQS PI = 36
7406 11:52:26.464200 [0] MIN Duty = 4938%(X100), DQS PI = 12
7407 11:52:26.464291 [0] AVG Duty = 4984%(X100)
7408 11:52:26.464356
7409 11:52:26.470602 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7410 11:52:26.470685
7411 11:52:26.474006 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7412 11:52:26.477487 [DutyScan_Calibration_Flow] ====Done====
7413 11:52:26.477593
7414 11:52:26.480642 [DutyScan_Calibration_Flow] k_type=3
7415 11:52:26.497946
7416 11:52:26.498068 ==DQM 0 ==
7417 11:52:26.501125 Final DQM duty delay cell = 0
7418 11:52:26.503975 [0] MAX Duty = 5156%(X100), DQS PI = 20
7419 11:52:26.507135 [0] MIN Duty = 4844%(X100), DQS PI = 50
7420 11:52:26.510418 [0] AVG Duty = 5000%(X100)
7421 11:52:26.510502
7422 11:52:26.510567 ==DQM 1 ==
7423 11:52:26.513713 Final DQM duty delay cell = 0
7424 11:52:26.517445 [0] MAX Duty = 5125%(X100), DQS PI = 8
7425 11:52:26.520551 [0] MIN Duty = 4875%(X100), DQS PI = 20
7426 11:52:26.523775 [0] AVG Duty = 5000%(X100)
7427 11:52:26.523862
7428 11:52:26.527671 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7429 11:52:26.527754
7430 11:52:26.530659 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7431 11:52:26.534262 [DutyScan_Calibration_Flow] ====Done====
7432 11:52:26.534361
7433 11:52:26.537022 [DutyScan_Calibration_Flow] k_type=2
7434 11:52:26.554168
7435 11:52:26.554320 ==DQ 0 ==
7436 11:52:26.557475 Final DQ duty delay cell = 0
7437 11:52:26.560935 [0] MAX Duty = 5156%(X100), DQS PI = 20
7438 11:52:26.564623 [0] MIN Duty = 4907%(X100), DQS PI = 52
7439 11:52:26.564706 [0] AVG Duty = 5031%(X100)
7440 11:52:26.564772
7441 11:52:26.567564 ==DQ 1 ==
7442 11:52:26.571049 Final DQ duty delay cell = 0
7443 11:52:26.574505 [0] MAX Duty = 5093%(X100), DQS PI = 6
7444 11:52:26.577950 [0] MIN Duty = 5031%(X100), DQS PI = 0
7445 11:52:26.578056 [0] AVG Duty = 5062%(X100)
7446 11:52:26.578148
7447 11:52:26.580772 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7448 11:52:26.580848
7449 11:52:26.584372 CH1 DQ 1 Duty spec in!! Max-Min= 62%
7450 11:52:26.590939 [DutyScan_Calibration_Flow] ====Done====
7451 11:52:26.594378 nWR fixed to 30
7452 11:52:26.594455 [ModeRegInit_LP4] CH0 RK0
7453 11:52:26.597619 [ModeRegInit_LP4] CH0 RK1
7454 11:52:26.600790 [ModeRegInit_LP4] CH1 RK0
7455 11:52:26.600864 [ModeRegInit_LP4] CH1 RK1
7456 11:52:26.604477 match AC timing 5
7457 11:52:26.607702 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7458 11:52:26.610765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7459 11:52:26.617379 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7460 11:52:26.621065 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7461 11:52:26.627967 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7462 11:52:26.628050 [MiockJmeterHQA]
7463 11:52:26.628115
7464 11:52:26.631270 [DramcMiockJmeter] u1RxGatingPI = 0
7465 11:52:26.631352 0 : 4363, 4137
7466 11:52:26.634640 4 : 4363, 4137
7467 11:52:26.634723 8 : 4368, 4140
7468 11:52:26.637434 12 : 4257, 4029
7469 11:52:26.637512 16 : 4255, 4030
7470 11:52:26.641036 20 : 4363, 4138
7471 11:52:26.641114 24 : 4252, 4027
7472 11:52:26.641176 28 : 4365, 4140
7473 11:52:26.644751 32 : 4257, 4029
7474 11:52:26.644854 36 : 4255, 4030
7475 11:52:26.647857 40 : 4257, 4029
7476 11:52:26.647968 44 : 4258, 4029
7477 11:52:26.651026 48 : 4364, 4137
7478 11:52:26.651100 52 : 4252, 4027
7479 11:52:26.654574 56 : 4258, 4029
7480 11:52:26.654649 60 : 4361, 4137
7481 11:52:26.654711 64 : 4252, 4027
7482 11:52:26.657809 68 : 4252, 4029
7483 11:52:26.657891 72 : 4252, 4029
7484 11:52:26.661326 76 : 4253, 4029
7485 11:52:26.661414 80 : 4360, 4138
7486 11:52:26.664422 84 : 4252, 4029
7487 11:52:26.664503 88 : 4252, 4030
7488 11:52:26.664573 92 : 4250, 4027
7489 11:52:26.667881 96 : 4258, 3485
7490 11:52:26.667970 100 : 4253, 0
7491 11:52:26.671308 104 : 4360, 0
7492 11:52:26.671414 108 : 4250, 0
7493 11:52:26.671485 112 : 4361, 0
7494 11:52:26.674831 116 : 4361, 0
7495 11:52:26.674925 120 : 4248, 0
7496 11:52:26.678025 124 : 4253, 0
7497 11:52:26.678126 128 : 4361, 0
7498 11:52:26.678212 132 : 4252, 0
7499 11:52:26.681708 136 : 4252, 0
7500 11:52:26.681788 140 : 4252, 0
7501 11:52:26.685008 144 : 4255, 0
7502 11:52:26.685080 148 : 4250, 0
7503 11:52:26.685141 152 : 4255, 0
7504 11:52:26.687684 156 : 4255, 0
7505 11:52:26.687796 160 : 4250, 0
7506 11:52:26.687906 164 : 4363, 0
7507 11:52:26.691262 168 : 4254, 0
7508 11:52:26.691376 172 : 4250, 0
7509 11:52:26.694721 176 : 4363, 0
7510 11:52:26.694825 180 : 4362, 0
7511 11:52:26.694931 184 : 4255, 0
7512 11:52:26.697710 188 : 4360, 0
7513 11:52:26.697815 192 : 4252, 0
7514 11:52:26.701115 196 : 4250, 0
7515 11:52:26.701217 200 : 4254, 0
7516 11:52:26.701315 204 : 4250, 0
7517 11:52:26.704547 208 : 4250, 0
7518 11:52:26.704648 212 : 4361, 92
7519 11:52:26.707906 216 : 4252, 3713
7520 11:52:26.708013 220 : 4249, 4027
7521 11:52:26.711329 224 : 4255, 4030
7522 11:52:26.711438 228 : 4255, 4032
7523 11:52:26.711535 232 : 4253, 4029
7524 11:52:26.714367 236 : 4360, 4137
7525 11:52:26.714473 240 : 4250, 4027
7526 11:52:26.718458 244 : 4250, 4026
7527 11:52:26.718536 248 : 4361, 4137
7528 11:52:26.721522 252 : 4255, 4029
7529 11:52:26.721624 256 : 4252, 4029
7530 11:52:26.724573 260 : 4252, 4027
7531 11:52:26.724678 264 : 4258, 4035
7532 11:52:26.727922 268 : 4255, 4030
7533 11:52:26.728023 272 : 4363, 4138
7534 11:52:26.731420 276 : 4252, 4030
7535 11:52:26.731525 280 : 4255, 4029
7536 11:52:26.734419 284 : 4252, 4029
7537 11:52:26.734519 288 : 4363, 4140
7538 11:52:26.734614 292 : 4363, 4140
7539 11:52:26.737825 296 : 4250, 4027
7540 11:52:26.737932 300 : 4252, 4030
7541 11:52:26.741243 304 : 4252, 4027
7542 11:52:26.741322 308 : 4252, 4029
7543 11:52:26.744638 312 : 4257, 4031
7544 11:52:26.744737 316 : 4363, 4140
7545 11:52:26.747947 320 : 4250, 4027
7546 11:52:26.748019 324 : 4253, 4029
7547 11:52:26.751484 328 : 4250, 4026
7548 11:52:26.751562 332 : 4258, 2967
7549 11:52:26.754327 336 : 4254, 123
7550 11:52:26.754434
7551 11:52:26.754525 MIOCK jitter meter ch=0
7552 11:52:26.754612
7553 11:52:26.757792 1T = (336-100) = 236 dly cells
7554 11:52:26.764487 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7555 11:52:26.764570 ==
7556 11:52:26.768201 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 11:52:26.771334 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 11:52:26.771414 ==
7559 11:52:26.777901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7560 11:52:26.781228 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7561 11:52:26.784569 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7562 11:52:26.791220 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7563 11:52:26.800425 [CA 0] Center 44 (14~75) winsize 62
7564 11:52:26.804120 [CA 1] Center 44 (13~75) winsize 63
7565 11:52:26.807496 [CA 2] Center 40 (11~69) winsize 59
7566 11:52:26.810866 [CA 3] Center 39 (10~69) winsize 60
7567 11:52:26.814067 [CA 4] Center 38 (8~68) winsize 61
7568 11:52:26.817316 [CA 5] Center 37 (7~67) winsize 61
7569 11:52:26.817398
7570 11:52:26.821224 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7571 11:52:26.821305
7572 11:52:26.824184 [CATrainingPosCal] consider 1 rank data
7573 11:52:26.827183 u2DelayCellTimex100 = 275/100 ps
7574 11:52:26.830564 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7575 11:52:26.837264 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7576 11:52:26.840739 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7577 11:52:26.844275 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7578 11:52:26.847583 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7579 11:52:26.851041 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7580 11:52:26.851124
7581 11:52:26.853896 CA PerBit enable=1, Macro0, CA PI delay=37
7582 11:52:26.853978
7583 11:52:26.857502 [CBTSetCACLKResult] CA Dly = 37
7584 11:52:26.860931 CS Dly: 10 (0~41)
7585 11:52:26.864450 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7586 11:52:26.867599 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7587 11:52:26.867681 ==
7588 11:52:26.870831 Dram Type= 6, Freq= 0, CH_0, rank 1
7589 11:52:26.874481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 11:52:26.877175 ==
7591 11:52:26.880922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7592 11:52:26.883951 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7593 11:52:26.891217 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7594 11:52:26.894013 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7595 11:52:26.904305 [CA 0] Center 43 (13~74) winsize 62
7596 11:52:26.908085 [CA 1] Center 43 (13~74) winsize 62
7597 11:52:26.911215 [CA 2] Center 39 (10~69) winsize 60
7598 11:52:26.914423 [CA 3] Center 38 (9~68) winsize 60
7599 11:52:26.917927 [CA 4] Center 37 (7~67) winsize 61
7600 11:52:26.921287 [CA 5] Center 37 (7~67) winsize 61
7601 11:52:26.921390
7602 11:52:26.924701 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7603 11:52:26.924802
7604 11:52:26.927798 [CATrainingPosCal] consider 2 rank data
7605 11:52:26.931367 u2DelayCellTimex100 = 275/100 ps
7606 11:52:26.934791 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7607 11:52:26.941204 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7608 11:52:26.944236 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7609 11:52:26.947498 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7610 11:52:26.950768 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7611 11:52:26.954212 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7612 11:52:26.954319
7613 11:52:26.957944 CA PerBit enable=1, Macro0, CA PI delay=37
7614 11:52:26.958018
7615 11:52:26.961423 [CBTSetCACLKResult] CA Dly = 37
7616 11:52:26.964968 CS Dly: 11 (0~44)
7617 11:52:26.967867 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7618 11:52:26.971148 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7619 11:52:26.971229
7620 11:52:26.974282 ----->DramcWriteLeveling(PI) begin...
7621 11:52:26.974383 ==
7622 11:52:26.978153 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 11:52:26.984369 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 11:52:26.984449 ==
7625 11:52:26.987860 Write leveling (Byte 0): 31 => 31
7626 11:52:26.987964 Write leveling (Byte 1): 26 => 26
7627 11:52:26.991472 DramcWriteLeveling(PI) end<-----
7628 11:52:26.991548
7629 11:52:26.991617 ==
7630 11:52:26.994691 Dram Type= 6, Freq= 0, CH_0, rank 0
7631 11:52:27.001167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7632 11:52:27.001269 ==
7633 11:52:27.001362 [Gating] SW mode calibration
7634 11:52:27.011076 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7635 11:52:27.014229 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7636 11:52:27.020972 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 11:52:27.024406 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 11:52:27.027852 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:52:27.030973 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7640 11:52:27.037802 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
7641 11:52:27.041251 1 4 20 | B1->B0 | 2322 3333 | 1 0 | (0 0) (0 0)
7642 11:52:27.044411 1 4 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
7643 11:52:27.050941 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7644 11:52:27.054521 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7645 11:52:27.057759 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7646 11:52:27.064337 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7647 11:52:27.068263 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7648 11:52:27.071280 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7649 11:52:27.078255 1 5 20 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)
7650 11:52:27.081115 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 1) (0 0)
7651 11:52:27.084721 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 11:52:27.091472 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 11:52:27.094274 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 11:52:27.097776 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 11:52:27.104651 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7656 11:52:27.107875 1 6 16 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7657 11:52:27.111699 1 6 20 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
7658 11:52:27.114489 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7659 11:52:27.121492 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7660 11:52:27.124417 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 11:52:27.127819 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7662 11:52:27.134508 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 11:52:27.138252 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7664 11:52:27.141647 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7665 11:52:27.148122 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7666 11:52:27.151126 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7667 11:52:27.154755 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7668 11:52:27.161275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7669 11:52:27.164851 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7670 11:52:27.168197 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7671 11:52:27.174733 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7672 11:52:27.178031 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7673 11:52:27.181736 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7674 11:52:27.184669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7675 11:52:27.191419 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7676 11:52:27.194581 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7677 11:52:27.197993 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7678 11:52:27.204982 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7679 11:52:27.208274 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7680 11:52:27.211641 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7681 11:52:27.218179 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7682 11:52:27.218274 Total UI for P1: 0, mck2ui 16
7683 11:52:27.225209 best dqsien dly found for B0: ( 1, 9, 16)
7684 11:52:27.228520 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7685 11:52:27.231396 Total UI for P1: 0, mck2ui 16
7686 11:52:27.234786 best dqsien dly found for B1: ( 1, 9, 20)
7687 11:52:27.238300 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
7688 11:52:27.241681 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7689 11:52:27.241778
7690 11:52:27.245133 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
7691 11:52:27.248375 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7692 11:52:27.251936 [Gating] SW calibration Done
7693 11:52:27.252031 ==
7694 11:52:27.255295 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 11:52:27.258419 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 11:52:27.261800 ==
7697 11:52:27.261895 RX Vref Scan: 0
7698 11:52:27.261973
7699 11:52:27.264994 RX Vref 0 -> 0, step: 1
7700 11:52:27.265090
7701 11:52:27.265166 RX Delay 0 -> 252, step: 8
7702 11:52:27.271606 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7703 11:52:27.274961 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
7704 11:52:27.278305 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7705 11:52:27.282070 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7706 11:52:27.285156 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7707 11:52:27.292194 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7708 11:52:27.295481 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7709 11:52:27.298466 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7710 11:52:27.301877 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7711 11:52:27.305219 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7712 11:52:27.312323 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7713 11:52:27.315043 iDelay=200, Bit 11, Center 119 (72 ~ 167) 96
7714 11:52:27.318536 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7715 11:52:27.322215 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7716 11:52:27.325384 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7717 11:52:27.332176 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7718 11:52:27.332257 ==
7719 11:52:27.335171 Dram Type= 6, Freq= 0, CH_0, rank 0
7720 11:52:27.338375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7721 11:52:27.338482 ==
7722 11:52:27.338577 DQS Delay:
7723 11:52:27.341926 DQS0 = 0, DQS1 = 0
7724 11:52:27.342007 DQM Delay:
7725 11:52:27.345306 DQM0 = 132, DQM1 = 125
7726 11:52:27.345387 DQ Delay:
7727 11:52:27.348866 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7728 11:52:27.352170 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
7729 11:52:27.355649 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
7730 11:52:27.358512 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7731 11:52:27.358593
7732 11:52:27.358657
7733 11:52:27.362046 ==
7734 11:52:27.362127 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 11:52:27.368736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 11:52:27.368824 ==
7737 11:52:27.368890
7738 11:52:27.368949
7739 11:52:27.371962 TX Vref Scan disable
7740 11:52:27.372043 == TX Byte 0 ==
7741 11:52:27.375419 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7742 11:52:27.382244 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7743 11:52:27.382359 == TX Byte 1 ==
7744 11:52:27.385361 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7745 11:52:27.391910 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7746 11:52:27.391994 ==
7747 11:52:27.395200 Dram Type= 6, Freq= 0, CH_0, rank 0
7748 11:52:27.398801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7749 11:52:27.398890 ==
7750 11:52:27.412058
7751 11:52:27.415527 TX Vref early break, caculate TX vref
7752 11:52:27.418874 TX Vref=16, minBit 4, minWin=21, winSum=355
7753 11:52:27.421885 TX Vref=18, minBit 0, minWin=22, winSum=369
7754 11:52:27.425290 TX Vref=20, minBit 1, minWin=22, winSum=380
7755 11:52:27.428702 TX Vref=22, minBit 1, minWin=23, winSum=386
7756 11:52:27.431929 TX Vref=24, minBit 7, minWin=23, winSum=397
7757 11:52:27.438616 TX Vref=26, minBit 4, minWin=24, winSum=409
7758 11:52:27.442257 TX Vref=28, minBit 0, minWin=25, winSum=418
7759 11:52:27.445229 TX Vref=30, minBit 0, minWin=25, winSum=412
7760 11:52:27.448591 TX Vref=32, minBit 0, minWin=24, winSum=406
7761 11:52:27.452140 TX Vref=34, minBit 2, minWin=24, winSum=394
7762 11:52:27.458604 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
7763 11:52:27.458689
7764 11:52:27.462188 Final TX Range 0 Vref 28
7765 11:52:27.462284
7766 11:52:27.462348 ==
7767 11:52:27.465608 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 11:52:27.468508 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 11:52:27.468604 ==
7770 11:52:27.468681
7771 11:52:27.468768
7772 11:52:27.471864 TX Vref Scan disable
7773 11:52:27.478784 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7774 11:52:27.478873 == TX Byte 0 ==
7775 11:52:27.481862 u2DelayCellOfst[0]=14 cells (4 PI)
7776 11:52:27.485539 u2DelayCellOfst[1]=21 cells (6 PI)
7777 11:52:27.488941 u2DelayCellOfst[2]=14 cells (4 PI)
7778 11:52:27.492863 u2DelayCellOfst[3]=17 cells (5 PI)
7779 11:52:27.495376 u2DelayCellOfst[4]=10 cells (3 PI)
7780 11:52:27.498613 u2DelayCellOfst[5]=0 cells (0 PI)
7781 11:52:27.501856 u2DelayCellOfst[6]=21 cells (6 PI)
7782 11:52:27.501974 u2DelayCellOfst[7]=21 cells (6 PI)
7783 11:52:27.508995 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7784 11:52:27.511831 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7785 11:52:27.511921 == TX Byte 1 ==
7786 11:52:27.515138 u2DelayCellOfst[8]=0 cells (0 PI)
7787 11:52:27.518541 u2DelayCellOfst[9]=0 cells (0 PI)
7788 11:52:27.522306 u2DelayCellOfst[10]=7 cells (2 PI)
7789 11:52:27.525113 u2DelayCellOfst[11]=0 cells (0 PI)
7790 11:52:27.528587 u2DelayCellOfst[12]=10 cells (3 PI)
7791 11:52:27.531858 u2DelayCellOfst[13]=10 cells (3 PI)
7792 11:52:27.535221 u2DelayCellOfst[14]=14 cells (4 PI)
7793 11:52:27.538821 u2DelayCellOfst[15]=10 cells (3 PI)
7794 11:52:27.542277 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7795 11:52:27.545431 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7796 11:52:27.548850 DramC Write-DBI on
7797 11:52:27.548948 ==
7798 11:52:27.551908 Dram Type= 6, Freq= 0, CH_0, rank 0
7799 11:52:27.555379 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7800 11:52:27.555466 ==
7801 11:52:27.555531
7802 11:52:27.555590
7803 11:52:27.558683 TX Vref Scan disable
7804 11:52:27.562213 == TX Byte 0 ==
7805 11:52:27.565140 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7806 11:52:27.568597 == TX Byte 1 ==
7807 11:52:27.571910 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7808 11:52:27.571992 DramC Write-DBI off
7809 11:52:27.572063
7810 11:52:27.575835 [DATLAT]
7811 11:52:27.575926 Freq=1600, CH0 RK0
7812 11:52:27.575992
7813 11:52:27.579126 DATLAT Default: 0xf
7814 11:52:27.579226 0, 0xFFFF, sum = 0
7815 11:52:27.581907 1, 0xFFFF, sum = 0
7816 11:52:27.582007 2, 0xFFFF, sum = 0
7817 11:52:27.585205 3, 0xFFFF, sum = 0
7818 11:52:27.585304 4, 0xFFFF, sum = 0
7819 11:52:27.589091 5, 0xFFFF, sum = 0
7820 11:52:27.589176 6, 0xFFFF, sum = 0
7821 11:52:27.592072 7, 0xFFFF, sum = 0
7822 11:52:27.592147 8, 0xFFFF, sum = 0
7823 11:52:27.595278 9, 0xFFFF, sum = 0
7824 11:52:27.595359 10, 0xFFFF, sum = 0
7825 11:52:27.598621 11, 0xFFFF, sum = 0
7826 11:52:27.602383 12, 0xFFFF, sum = 0
7827 11:52:27.602502 13, 0xFFFF, sum = 0
7828 11:52:27.605662 14, 0x0, sum = 1
7829 11:52:27.605769 15, 0x0, sum = 2
7830 11:52:27.605875 16, 0x0, sum = 3
7831 11:52:27.609137 17, 0x0, sum = 4
7832 11:52:27.609244 best_step = 15
7833 11:52:27.609338
7834 11:52:27.612314 ==
7835 11:52:27.612418 Dram Type= 6, Freq= 0, CH_0, rank 0
7836 11:52:27.619124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7837 11:52:27.619231 ==
7838 11:52:27.619326 RX Vref Scan: 1
7839 11:52:27.619416
7840 11:52:27.622552 Set Vref Range= 24 -> 127
7841 11:52:27.622653
7842 11:52:27.625777 RX Vref 24 -> 127, step: 1
7843 11:52:27.625873
7844 11:52:27.629354 RX Delay 11 -> 252, step: 4
7845 11:52:27.629463
7846 11:52:27.629558 Set Vref, RX VrefLevel [Byte0]: 24
7847 11:52:27.632205 [Byte1]: 24
7848 11:52:27.636911
7849 11:52:27.637015 Set Vref, RX VrefLevel [Byte0]: 25
7850 11:52:27.640133 [Byte1]: 25
7851 11:52:27.644259
7852 11:52:27.644330 Set Vref, RX VrefLevel [Byte0]: 26
7853 11:52:27.647622 [Byte1]: 26
7854 11:52:27.652264
7855 11:52:27.652345 Set Vref, RX VrefLevel [Byte0]: 27
7856 11:52:27.655163 [Byte1]: 27
7857 11:52:27.659529
7858 11:52:27.659602 Set Vref, RX VrefLevel [Byte0]: 28
7859 11:52:27.663116 [Byte1]: 28
7860 11:52:27.667430
7861 11:52:27.667532 Set Vref, RX VrefLevel [Byte0]: 29
7862 11:52:27.670412 [Byte1]: 29
7863 11:52:27.674837
7864 11:52:27.674980 Set Vref, RX VrefLevel [Byte0]: 30
7865 11:52:27.678436 [Byte1]: 30
7866 11:52:27.682392
7867 11:52:27.682504 Set Vref, RX VrefLevel [Byte0]: 31
7868 11:52:27.686006 [Byte1]: 31
7869 11:52:27.689884
7870 11:52:27.689990 Set Vref, RX VrefLevel [Byte0]: 32
7871 11:52:27.693206 [Byte1]: 32
7872 11:52:27.697381
7873 11:52:27.697483 Set Vref, RX VrefLevel [Byte0]: 33
7874 11:52:27.701245 [Byte1]: 33
7875 11:52:27.705389
7876 11:52:27.705488 Set Vref, RX VrefLevel [Byte0]: 34
7877 11:52:27.708504 [Byte1]: 34
7878 11:52:27.712660
7879 11:52:27.712760 Set Vref, RX VrefLevel [Byte0]: 35
7880 11:52:27.716368 [Byte1]: 35
7881 11:52:27.720632
7882 11:52:27.720728 Set Vref, RX VrefLevel [Byte0]: 36
7883 11:52:27.723906 [Byte1]: 36
7884 11:52:27.728223
7885 11:52:27.728303 Set Vref, RX VrefLevel [Byte0]: 37
7886 11:52:27.731692 [Byte1]: 37
7887 11:52:27.735920
7888 11:52:27.735999 Set Vref, RX VrefLevel [Byte0]: 38
7889 11:52:27.739275 [Byte1]: 38
7890 11:52:27.743581
7891 11:52:27.743661 Set Vref, RX VrefLevel [Byte0]: 39
7892 11:52:27.746501 [Byte1]: 39
7893 11:52:27.751144
7894 11:52:27.751223 Set Vref, RX VrefLevel [Byte0]: 40
7895 11:52:27.754267 [Byte1]: 40
7896 11:52:27.758990
7897 11:52:27.759096 Set Vref, RX VrefLevel [Byte0]: 41
7898 11:52:27.762128 [Byte1]: 41
7899 11:52:27.766374
7900 11:52:27.766486 Set Vref, RX VrefLevel [Byte0]: 42
7901 11:52:27.769353 [Byte1]: 42
7902 11:52:27.773676
7903 11:52:27.773774 Set Vref, RX VrefLevel [Byte0]: 43
7904 11:52:27.777373 [Byte1]: 43
7905 11:52:27.781560
7906 11:52:27.781673 Set Vref, RX VrefLevel [Byte0]: 44
7907 11:52:27.784858 [Byte1]: 44
7908 11:52:27.789185
7909 11:52:27.789308 Set Vref, RX VrefLevel [Byte0]: 45
7910 11:52:27.792317 [Byte1]: 45
7911 11:52:27.796918
7912 11:52:27.797015 Set Vref, RX VrefLevel [Byte0]: 46
7913 11:52:27.799817 [Byte1]: 46
7914 11:52:27.804215
7915 11:52:27.804302 Set Vref, RX VrefLevel [Byte0]: 47
7916 11:52:27.807305 [Byte1]: 47
7917 11:52:27.811599
7918 11:52:27.811706 Set Vref, RX VrefLevel [Byte0]: 48
7919 11:52:27.815138 [Byte1]: 48
7920 11:52:27.819413
7921 11:52:27.819510 Set Vref, RX VrefLevel [Byte0]: 49
7922 11:52:27.822714 [Byte1]: 49
7923 11:52:27.827072
7924 11:52:27.827177 Set Vref, RX VrefLevel [Byte0]: 50
7925 11:52:27.830358 [Byte1]: 50
7926 11:52:27.834822
7927 11:52:27.834962 Set Vref, RX VrefLevel [Byte0]: 51
7928 11:52:27.837818 [Byte1]: 51
7929 11:52:27.842450
7930 11:52:27.842558 Set Vref, RX VrefLevel [Byte0]: 52
7931 11:52:27.845673 [Byte1]: 52
7932 11:52:27.849680
7933 11:52:27.849783 Set Vref, RX VrefLevel [Byte0]: 53
7934 11:52:27.853138 [Byte1]: 53
7935 11:52:27.857416
7936 11:52:27.857517 Set Vref, RX VrefLevel [Byte0]: 54
7937 11:52:27.860560 [Byte1]: 54
7938 11:52:27.864858
7939 11:52:27.864959 Set Vref, RX VrefLevel [Byte0]: 55
7940 11:52:27.868380 [Byte1]: 55
7941 11:52:27.872891
7942 11:52:27.872990 Set Vref, RX VrefLevel [Byte0]: 56
7943 11:52:27.876284 [Byte1]: 56
7944 11:52:27.880539
7945 11:52:27.880642 Set Vref, RX VrefLevel [Byte0]: 57
7946 11:52:27.883933 [Byte1]: 57
7947 11:52:27.888123
7948 11:52:27.888225 Set Vref, RX VrefLevel [Byte0]: 58
7949 11:52:27.891441 [Byte1]: 58
7950 11:52:27.896170
7951 11:52:27.896273 Set Vref, RX VrefLevel [Byte0]: 59
7952 11:52:27.898820 [Byte1]: 59
7953 11:52:27.902963
7954 11:52:27.903057 Set Vref, RX VrefLevel [Byte0]: 60
7955 11:52:27.906317 [Byte1]: 60
7956 11:52:27.910749
7957 11:52:27.910855 Set Vref, RX VrefLevel [Byte0]: 61
7958 11:52:27.914312 [Byte1]: 61
7959 11:52:27.918489
7960 11:52:27.918590 Set Vref, RX VrefLevel [Byte0]: 62
7961 11:52:27.921585 [Byte1]: 62
7962 11:52:27.926408
7963 11:52:27.926510 Set Vref, RX VrefLevel [Byte0]: 63
7964 11:52:27.929430 [Byte1]: 63
7965 11:52:27.933483
7966 11:52:27.933650 Set Vref, RX VrefLevel [Byte0]: 64
7967 11:52:27.937130 [Byte1]: 64
7968 11:52:27.941439
7969 11:52:27.941559 Set Vref, RX VrefLevel [Byte0]: 65
7970 11:52:27.944610 [Byte1]: 65
7971 11:52:27.949116
7972 11:52:27.949224 Set Vref, RX VrefLevel [Byte0]: 66
7973 11:52:27.951975 [Byte1]: 66
7974 11:52:27.956581
7975 11:52:27.956681 Set Vref, RX VrefLevel [Byte0]: 67
7976 11:52:27.959489 [Byte1]: 67
7977 11:52:27.964200
7978 11:52:27.964299 Set Vref, RX VrefLevel [Byte0]: 68
7979 11:52:27.967549 [Byte1]: 68
7980 11:52:27.971392
7981 11:52:27.971492 Set Vref, RX VrefLevel [Byte0]: 69
7982 11:52:27.974990 [Byte1]: 69
7983 11:52:27.979509
7984 11:52:27.979621 Set Vref, RX VrefLevel [Byte0]: 70
7985 11:52:27.982842 [Byte1]: 70
7986 11:52:27.986813
7987 11:52:27.986956 Set Vref, RX VrefLevel [Byte0]: 71
7988 11:52:27.990608 [Byte1]: 71
7989 11:52:27.994627
7990 11:52:27.994728 Set Vref, RX VrefLevel [Byte0]: 72
7991 11:52:27.998290 [Byte1]: 72
7992 11:52:28.001936
7993 11:52:28.002041 Set Vref, RX VrefLevel [Byte0]: 73
7994 11:52:28.005720 [Byte1]: 73
7995 11:52:28.009662
7996 11:52:28.009762 Set Vref, RX VrefLevel [Byte0]: 74
7997 11:52:28.012893 [Byte1]: 74
7998 11:52:28.017446
7999 11:52:28.017546 Set Vref, RX VrefLevel [Byte0]: 75
8000 11:52:28.021320 [Byte1]: 75
8001 11:52:28.024940
8002 11:52:28.025040 Set Vref, RX VrefLevel [Byte0]: 76
8003 11:52:28.028443 [Byte1]: 76
8004 11:52:28.032829
8005 11:52:28.032930 Set Vref, RX VrefLevel [Byte0]: 77
8006 11:52:28.036110 [Byte1]: 77
8007 11:52:28.040015
8008 11:52:28.040116 Final RX Vref Byte 0 = 55 to rank0
8009 11:52:28.043246 Final RX Vref Byte 1 = 63 to rank0
8010 11:52:28.046617 Final RX Vref Byte 0 = 55 to rank1
8011 11:52:28.050172 Final RX Vref Byte 1 = 63 to rank1==
8012 11:52:28.053732 Dram Type= 6, Freq= 0, CH_0, rank 0
8013 11:52:28.060743 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8014 11:52:28.060829 ==
8015 11:52:28.060921 DQS Delay:
8016 11:52:28.061019 DQS0 = 0, DQS1 = 0
8017 11:52:28.063277 DQM Delay:
8018 11:52:28.063350 DQM0 = 129, DQM1 = 122
8019 11:52:28.066935 DQ Delay:
8020 11:52:28.070260 DQ0 =130, DQ1 =132, DQ2 =122, DQ3 =126
8021 11:52:28.073232 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
8022 11:52:28.076948 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8023 11:52:28.080110 DQ12 =128, DQ13 =128, DQ14 =130, DQ15 =134
8024 11:52:28.080212
8025 11:52:28.080304
8026 11:52:28.080392
8027 11:52:28.083540 [DramC_TX_OE_Calibration] TA2
8028 11:52:28.086884 Original DQ_B0 (3 6) =30, OEN = 27
8029 11:52:28.090229 Original DQ_B1 (3 6) =30, OEN = 27
8030 11:52:28.093558 24, 0x0, End_B0=24 End_B1=24
8031 11:52:28.093665 25, 0x0, End_B0=25 End_B1=25
8032 11:52:28.097147 26, 0x0, End_B0=26 End_B1=26
8033 11:52:28.100651 27, 0x0, End_B0=27 End_B1=27
8034 11:52:28.103724 28, 0x0, End_B0=28 End_B1=28
8035 11:52:28.103831 29, 0x0, End_B0=29 End_B1=29
8036 11:52:28.107044 30, 0x0, End_B0=30 End_B1=30
8037 11:52:28.110425 31, 0x4141, End_B0=30 End_B1=30
8038 11:52:28.113905 Byte0 end_step=30 best_step=27
8039 11:52:28.116682 Byte1 end_step=30 best_step=27
8040 11:52:28.120361 Byte0 TX OE(2T, 0.5T) = (3, 3)
8041 11:52:28.120460 Byte1 TX OE(2T, 0.5T) = (3, 3)
8042 11:52:28.120552
8043 11:52:28.120642
8044 11:52:28.130402 [DQSOSCAuto] RK0, (LSB)MR18= 0x1106, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 401 ps
8045 11:52:28.133691 CH0 RK0: MR19=303, MR18=1106
8046 11:52:28.140203 CH0_RK0: MR19=0x303, MR18=0x1106, DQSOSC=401, MR23=63, INC=22, DEC=15
8047 11:52:28.140307
8048 11:52:28.143529 ----->DramcWriteLeveling(PI) begin...
8049 11:52:28.143636 ==
8050 11:52:28.146812 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 11:52:28.150494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 11:52:28.150596 ==
8053 11:52:28.153485 Write leveling (Byte 0): 35 => 35
8054 11:52:28.157241 Write leveling (Byte 1): 27 => 27
8055 11:52:28.160575 DramcWriteLeveling(PI) end<-----
8056 11:52:28.160678
8057 11:52:28.160767 ==
8058 11:52:28.163697 Dram Type= 6, Freq= 0, CH_0, rank 1
8059 11:52:28.167236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8060 11:52:28.167336 ==
8061 11:52:28.170789 [Gating] SW mode calibration
8062 11:52:28.177449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8063 11:52:28.183851 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8064 11:52:28.187570 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8065 11:52:28.190785 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:52:28.193918 1 4 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8067 11:52:28.200856 1 4 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
8068 11:52:28.204134 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8069 11:52:28.207206 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8070 11:52:28.214029 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8071 11:52:28.217374 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8072 11:52:28.220656 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8073 11:52:28.227333 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8074 11:52:28.230711 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8075 11:52:28.234027 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8076 11:52:28.240734 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8077 11:52:28.244031 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
8078 11:52:28.247961 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8079 11:52:28.251420 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8080 11:52:28.258060 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8081 11:52:28.261554 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8082 11:52:28.264386 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8083 11:52:28.270965 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8084 11:52:28.274762 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
8085 11:52:28.277774 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
8086 11:52:28.284278 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8087 11:52:28.287612 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8088 11:52:28.290931 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 11:52:28.297938 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8090 11:52:28.300945 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8091 11:52:28.304581 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8092 11:52:28.311316 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8093 11:52:28.314389 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8094 11:52:28.317935 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8095 11:52:28.324472 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 11:52:28.327702 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 11:52:28.331182 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8098 11:52:28.337890 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8099 11:52:28.341156 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8100 11:52:28.344549 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8101 11:52:28.350822 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8102 11:52:28.354246 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8103 11:52:28.357429 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8104 11:52:28.360707 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8105 11:52:28.367801 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8106 11:52:28.371043 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8107 11:52:28.374633 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8108 11:52:28.377660 Total UI for P1: 0, mck2ui 16
8109 11:52:28.381585 best dqsien dly found for B0: ( 1, 9, 8)
8110 11:52:28.387869 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8111 11:52:28.390838 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8112 11:52:28.395093 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8113 11:52:28.397695 Total UI for P1: 0, mck2ui 16
8114 11:52:28.401229 best dqsien dly found for B1: ( 1, 9, 18)
8115 11:52:28.404727 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8116 11:52:28.408052 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8117 11:52:28.408153
8118 11:52:28.411567 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8119 11:52:28.418121 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8120 11:52:28.418225 [Gating] SW calibration Done
8121 11:52:28.421319 ==
8122 11:52:28.421393 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 11:52:28.428128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 11:52:28.428205 ==
8125 11:52:28.428267 RX Vref Scan: 0
8126 11:52:28.428346
8127 11:52:28.431367 RX Vref 0 -> 0, step: 1
8128 11:52:28.431437
8129 11:52:28.434223 RX Delay 0 -> 252, step: 8
8130 11:52:28.438023 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8131 11:52:28.441404 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8132 11:52:28.444843 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8133 11:52:28.447729 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8134 11:52:28.454780 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8135 11:52:28.458400 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8136 11:52:28.461058 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8137 11:52:28.464610 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8138 11:52:28.468078 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8139 11:52:28.474534 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8140 11:52:28.477989 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8141 11:52:28.481354 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8142 11:52:28.484562 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8143 11:52:28.487891 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8144 11:52:28.494954 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8145 11:52:28.497892 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8146 11:52:28.497972 ==
8147 11:52:28.501233 Dram Type= 6, Freq= 0, CH_0, rank 1
8148 11:52:28.504844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8149 11:52:28.504922 ==
8150 11:52:28.507694 DQS Delay:
8151 11:52:28.507763 DQS0 = 0, DQS1 = 0
8152 11:52:28.507822 DQM Delay:
8153 11:52:28.511492 DQM0 = 131, DQM1 = 124
8154 11:52:28.511563 DQ Delay:
8155 11:52:28.514382 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8156 11:52:28.517919 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8157 11:52:28.521303 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
8158 11:52:28.528285 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
8159 11:52:28.528386
8160 11:52:28.528480
8161 11:52:28.528568 ==
8162 11:52:28.531554 Dram Type= 6, Freq= 0, CH_0, rank 1
8163 11:52:28.535057 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8164 11:52:28.535129 ==
8165 11:52:28.535190
8166 11:52:28.535248
8167 11:52:28.537911 TX Vref Scan disable
8168 11:52:28.538006 == TX Byte 0 ==
8169 11:52:28.545254 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8170 11:52:28.548328 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8171 11:52:28.548403 == TX Byte 1 ==
8172 11:52:28.554665 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8173 11:52:28.558144 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8174 11:52:28.558246 ==
8175 11:52:28.561483 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 11:52:28.564684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 11:52:28.564760 ==
8178 11:52:28.580704
8179 11:52:28.584144 TX Vref early break, caculate TX vref
8180 11:52:28.587599 TX Vref=16, minBit 8, minWin=22, winSum=377
8181 11:52:28.591002 TX Vref=18, minBit 9, minWin=22, winSum=388
8182 11:52:28.594518 TX Vref=20, minBit 9, minWin=23, winSum=395
8183 11:52:28.597455 TX Vref=22, minBit 9, minWin=24, winSum=403
8184 11:52:28.600890 TX Vref=24, minBit 11, minWin=24, winSum=411
8185 11:52:28.607692 TX Vref=26, minBit 3, minWin=25, winSum=420
8186 11:52:28.610679 TX Vref=28, minBit 4, minWin=25, winSum=429
8187 11:52:28.614317 TX Vref=30, minBit 4, minWin=26, winSum=427
8188 11:52:28.617759 TX Vref=32, minBit 8, minWin=24, winSum=415
8189 11:52:28.620652 TX Vref=34, minBit 0, minWin=25, winSum=409
8190 11:52:28.624152 TX Vref=36, minBit 9, minWin=24, winSum=400
8191 11:52:28.630730 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 30
8192 11:52:28.630843
8193 11:52:28.634469 Final TX Range 0 Vref 30
8194 11:52:28.634572
8195 11:52:28.634662 ==
8196 11:52:28.638081 Dram Type= 6, Freq= 0, CH_0, rank 1
8197 11:52:28.640825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8198 11:52:28.640902 ==
8199 11:52:28.640971
8200 11:52:28.641031
8201 11:52:28.644250 TX Vref Scan disable
8202 11:52:28.650886 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8203 11:52:28.650993 == TX Byte 0 ==
8204 11:52:28.654346 u2DelayCellOfst[0]=14 cells (4 PI)
8205 11:52:28.657916 u2DelayCellOfst[1]=21 cells (6 PI)
8206 11:52:28.661384 u2DelayCellOfst[2]=14 cells (4 PI)
8207 11:52:28.664611 u2DelayCellOfst[3]=14 cells (4 PI)
8208 11:52:28.667834 u2DelayCellOfst[4]=10 cells (3 PI)
8209 11:52:28.670770 u2DelayCellOfst[5]=0 cells (0 PI)
8210 11:52:28.674479 u2DelayCellOfst[6]=17 cells (5 PI)
8211 11:52:28.677579 u2DelayCellOfst[7]=21 cells (6 PI)
8212 11:52:28.681027 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8213 11:52:28.684497 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8214 11:52:28.688185 == TX Byte 1 ==
8215 11:52:28.688286 u2DelayCellOfst[8]=0 cells (0 PI)
8216 11:52:28.691158 u2DelayCellOfst[9]=0 cells (0 PI)
8217 11:52:28.694576 u2DelayCellOfst[10]=3 cells (1 PI)
8218 11:52:28.697950 u2DelayCellOfst[11]=0 cells (0 PI)
8219 11:52:28.701416 u2DelayCellOfst[12]=10 cells (3 PI)
8220 11:52:28.704632 u2DelayCellOfst[13]=7 cells (2 PI)
8221 11:52:28.708210 u2DelayCellOfst[14]=14 cells (4 PI)
8222 11:52:28.711765 u2DelayCellOfst[15]=10 cells (3 PI)
8223 11:52:28.714967 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8224 11:52:28.718137 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8225 11:52:28.721279 DramC Write-DBI on
8226 11:52:28.721355 ==
8227 11:52:28.724880 Dram Type= 6, Freq= 0, CH_0, rank 1
8228 11:52:28.728096 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8229 11:52:28.728169 ==
8230 11:52:28.728234
8231 11:52:28.728292
8232 11:52:28.731542 TX Vref Scan disable
8233 11:52:28.735221 == TX Byte 0 ==
8234 11:52:28.738633 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8235 11:52:28.738741 == TX Byte 1 ==
8236 11:52:28.744959 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8237 11:52:28.745054 DramC Write-DBI off
8238 11:52:28.745140
8239 11:52:28.748488 [DATLAT]
8240 11:52:28.748553 Freq=1600, CH0 RK1
8241 11:52:28.748611
8242 11:52:28.751906 DATLAT Default: 0xf
8243 11:52:28.751969 0, 0xFFFF, sum = 0
8244 11:52:28.754821 1, 0xFFFF, sum = 0
8245 11:52:28.754937 2, 0xFFFF, sum = 0
8246 11:52:28.758235 3, 0xFFFF, sum = 0
8247 11:52:28.758340 4, 0xFFFF, sum = 0
8248 11:52:28.761448 5, 0xFFFF, sum = 0
8249 11:52:28.761575 6, 0xFFFF, sum = 0
8250 11:52:28.764944 7, 0xFFFF, sum = 0
8251 11:52:28.765038 8, 0xFFFF, sum = 0
8252 11:52:28.768436 9, 0xFFFF, sum = 0
8253 11:52:28.768533 10, 0xFFFF, sum = 0
8254 11:52:28.771275 11, 0xFFFF, sum = 0
8255 11:52:28.774747 12, 0xFFFF, sum = 0
8256 11:52:28.774823 13, 0xFFFF, sum = 0
8257 11:52:28.778061 14, 0x0, sum = 1
8258 11:52:28.778168 15, 0x0, sum = 2
8259 11:52:28.781508 16, 0x0, sum = 3
8260 11:52:28.781617 17, 0x0, sum = 4
8261 11:52:28.781707 best_step = 15
8262 11:52:28.781820
8263 11:52:28.784664 ==
8264 11:52:28.787971 Dram Type= 6, Freq= 0, CH_0, rank 1
8265 11:52:28.791441 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8266 11:52:28.791529 ==
8267 11:52:28.791610 RX Vref Scan: 0
8268 11:52:28.791667
8269 11:52:28.794634 RX Vref 0 -> 0, step: 1
8270 11:52:28.794716
8271 11:52:28.798139 RX Delay 11 -> 252, step: 4
8272 11:52:28.801705 iDelay=191, Bit 0, Center 126 (71 ~ 182) 112
8273 11:52:28.804497 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8274 11:52:28.811187 iDelay=191, Bit 2, Center 122 (67 ~ 178) 112
8275 11:52:28.814729 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8276 11:52:28.817688 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8277 11:52:28.821529 iDelay=191, Bit 5, Center 114 (59 ~ 170) 112
8278 11:52:28.824430 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8279 11:52:28.831568 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8280 11:52:28.834729 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8281 11:52:28.838393 iDelay=191, Bit 9, Center 112 (59 ~ 166) 108
8282 11:52:28.841492 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8283 11:52:28.844577 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8284 11:52:28.851320 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8285 11:52:28.854513 iDelay=191, Bit 13, Center 130 (75 ~ 186) 112
8286 11:52:28.857650 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8287 11:52:28.861337 iDelay=191, Bit 15, Center 132 (75 ~ 190) 116
8288 11:52:28.861410 ==
8289 11:52:28.864605 Dram Type= 6, Freq= 0, CH_0, rank 1
8290 11:52:28.871285 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8291 11:52:28.871391 ==
8292 11:52:28.871472 DQS Delay:
8293 11:52:28.871537 DQS0 = 0, DQS1 = 0
8294 11:52:28.874498 DQM Delay:
8295 11:52:28.874587 DQM0 = 126, DQM1 = 123
8296 11:52:28.878317 DQ Delay:
8297 11:52:28.881333 DQ0 =126, DQ1 =130, DQ2 =122, DQ3 =126
8298 11:52:28.884697 DQ4 =124, DQ5 =114, DQ6 =134, DQ7 =134
8299 11:52:28.887907 DQ8 =112, DQ9 =112, DQ10 =122, DQ11 =116
8300 11:52:28.891497 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8301 11:52:28.891573
8302 11:52:28.891634
8303 11:52:28.891691
8304 11:52:28.894564 [DramC_TX_OE_Calibration] TA2
8305 11:52:28.897805 Original DQ_B0 (3 6) =30, OEN = 27
8306 11:52:28.901641 Original DQ_B1 (3 6) =30, OEN = 27
8307 11:52:28.904695 24, 0x0, End_B0=24 End_B1=24
8308 11:52:28.904766 25, 0x0, End_B0=25 End_B1=25
8309 11:52:28.907894 26, 0x0, End_B0=26 End_B1=26
8310 11:52:28.911511 27, 0x0, End_B0=27 End_B1=27
8311 11:52:28.914542 28, 0x0, End_B0=28 End_B1=28
8312 11:52:28.914641 29, 0x0, End_B0=29 End_B1=29
8313 11:52:28.917905 30, 0x0, End_B0=30 End_B1=30
8314 11:52:28.921505 31, 0x4141, End_B0=30 End_B1=30
8315 11:52:28.924718 Byte0 end_step=30 best_step=27
8316 11:52:28.928216 Byte1 end_step=30 best_step=27
8317 11:52:28.931452 Byte0 TX OE(2T, 0.5T) = (3, 3)
8318 11:52:28.931525 Byte1 TX OE(2T, 0.5T) = (3, 3)
8319 11:52:28.931587
8320 11:52:28.934480
8321 11:52:28.941265 [DQSOSCAuto] RK1, (LSB)MR18= 0x170c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8322 11:52:28.944486 CH0 RK1: MR19=303, MR18=170C
8323 11:52:28.951800 CH0_RK1: MR19=0x303, MR18=0x170C, DQSOSC=398, MR23=63, INC=23, DEC=15
8324 11:52:28.951879 [RxdqsGatingPostProcess] freq 1600
8325 11:52:28.958112 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8326 11:52:28.961508 best DQS0 dly(2T, 0.5T) = (1, 1)
8327 11:52:28.964775 best DQS1 dly(2T, 0.5T) = (1, 1)
8328 11:52:28.968331 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8329 11:52:28.971862 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8330 11:52:28.974565 best DQS0 dly(2T, 0.5T) = (1, 1)
8331 11:52:28.977856 best DQS1 dly(2T, 0.5T) = (1, 1)
8332 11:52:28.981548 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8333 11:52:28.981650 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8334 11:52:28.984677 Pre-setting of DQS Precalculation
8335 11:52:28.991489 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8336 11:52:28.991595 ==
8337 11:52:28.994761 Dram Type= 6, Freq= 0, CH_1, rank 0
8338 11:52:28.998385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 11:52:28.998483 ==
8340 11:52:29.004646 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 11:52:29.008048 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 11:52:29.011343 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 11:52:29.018529 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 11:52:29.027468 [CA 0] Center 43 (14~73) winsize 60
8345 11:52:29.030953 [CA 1] Center 43 (14~72) winsize 59
8346 11:52:29.033948 [CA 2] Center 38 (9~67) winsize 59
8347 11:52:29.037403 [CA 3] Center 37 (8~66) winsize 59
8348 11:52:29.040721 [CA 4] Center 38 (9~68) winsize 60
8349 11:52:29.044162 [CA 5] Center 37 (9~66) winsize 58
8350 11:52:29.044255
8351 11:52:29.047606 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 11:52:29.047702
8353 11:52:29.051083 [CATrainingPosCal] consider 1 rank data
8354 11:52:29.054790 u2DelayCellTimex100 = 275/100 ps
8355 11:52:29.057733 CA0 delay=43 (14~73),Diff = 6 PI (21 cell)
8356 11:52:29.064465 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8357 11:52:29.067811 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8358 11:52:29.070847 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8359 11:52:29.074566 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8360 11:52:29.077441 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8361 11:52:29.077538
8362 11:52:29.081405 CA PerBit enable=1, Macro0, CA PI delay=37
8363 11:52:29.081504
8364 11:52:29.084552 [CBTSetCACLKResult] CA Dly = 37
8365 11:52:29.084659 CS Dly: 8 (0~39)
8366 11:52:29.091027 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 11:52:29.094464 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 11:52:29.094564 ==
8369 11:52:29.097970 Dram Type= 6, Freq= 0, CH_1, rank 1
8370 11:52:29.100745 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8371 11:52:29.100843 ==
8372 11:52:29.107961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8373 11:52:29.110822 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8374 11:52:29.114167 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8375 11:52:29.120919 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8376 11:52:29.130516 [CA 0] Center 42 (13~72) winsize 60
8377 11:52:29.134175 [CA 1] Center 43 (14~72) winsize 59
8378 11:52:29.137152 [CA 2] Center 37 (8~67) winsize 60
8379 11:52:29.140620 [CA 3] Center 37 (8~66) winsize 59
8380 11:52:29.144035 [CA 4] Center 37 (8~67) winsize 60
8381 11:52:29.147533 [CA 5] Center 36 (7~66) winsize 60
8382 11:52:29.147627
8383 11:52:29.150644 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8384 11:52:29.150736
8385 11:52:29.154120 [CATrainingPosCal] consider 2 rank data
8386 11:52:29.157199 u2DelayCellTimex100 = 275/100 ps
8387 11:52:29.161274 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8388 11:52:29.167555 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8389 11:52:29.170531 CA2 delay=38 (9~67),Diff = 1 PI (3 cell)
8390 11:52:29.174082 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8391 11:52:29.177188 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8392 11:52:29.180732 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8393 11:52:29.180805
8394 11:52:29.184280 CA PerBit enable=1, Macro0, CA PI delay=37
8395 11:52:29.184376
8396 11:52:29.188061 [CBTSetCACLKResult] CA Dly = 37
8397 11:52:29.188145 CS Dly: 10 (0~44)
8398 11:52:29.194001 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8399 11:52:29.197689 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8400 11:52:29.197785
8401 11:52:29.200846 ----->DramcWriteLeveling(PI) begin...
8402 11:52:29.200919 ==
8403 11:52:29.204335 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 11:52:29.207825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 11:52:29.207896 ==
8406 11:52:29.210949 Write leveling (Byte 0): 23 => 23
8407 11:52:29.214159 Write leveling (Byte 1): 28 => 28
8408 11:52:29.217486 DramcWriteLeveling(PI) end<-----
8409 11:52:29.217560
8410 11:52:29.217649 ==
8411 11:52:29.220968 Dram Type= 6, Freq= 0, CH_1, rank 0
8412 11:52:29.224333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8413 11:52:29.227625 ==
8414 11:52:29.227696 [Gating] SW mode calibration
8415 11:52:29.234253 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8416 11:52:29.241004 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8417 11:52:29.244471 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 11:52:29.251126 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:52:29.254252 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:52:29.258097 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:52:29.264548 1 4 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8422 11:52:29.267807 1 4 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
8423 11:52:29.270776 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8424 11:52:29.274858 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8425 11:52:29.281201 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8426 11:52:29.284807 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8427 11:52:29.288299 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8428 11:52:29.295088 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8429 11:52:29.297701 1 5 16 | B1->B0 | 2d2d 3232 | 1 1 | (1 0) (1 0)
8430 11:52:29.301253 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8431 11:52:29.308257 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8432 11:52:29.311459 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8433 11:52:29.314689 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8434 11:52:29.321750 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 11:52:29.325052 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 11:52:29.328192 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 11:52:29.335076 1 6 16 | B1->B0 | 4545 3838 | 0 0 | (0 0) (1 1)
8438 11:52:29.338511 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8439 11:52:29.341768 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 11:52:29.345164 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8441 11:52:29.351910 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8442 11:52:29.354689 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8443 11:52:29.358201 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8444 11:52:29.364660 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8445 11:52:29.368470 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8446 11:52:29.371832 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8447 11:52:29.378063 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 11:52:29.381484 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8449 11:52:29.384827 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8450 11:52:29.391786 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8451 11:52:29.395131 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8452 11:52:29.398149 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8453 11:52:29.404663 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8454 11:52:29.408578 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8455 11:52:29.411340 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8456 11:52:29.418499 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8457 11:52:29.421387 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8458 11:52:29.424822 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8459 11:52:29.428446 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8460 11:52:29.435044 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8461 11:52:29.438293 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8462 11:52:29.441439 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8463 11:52:29.444962 Total UI for P1: 0, mck2ui 16
8464 11:52:29.448329 best dqsien dly found for B0: ( 1, 9, 14)
8465 11:52:29.451598 Total UI for P1: 0, mck2ui 16
8466 11:52:29.455196 best dqsien dly found for B1: ( 1, 9, 16)
8467 11:52:29.458705 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8468 11:52:29.461556 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8469 11:52:29.461662
8470 11:52:29.468390 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8471 11:52:29.472109 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8472 11:52:29.475149 [Gating] SW calibration Done
8473 11:52:29.475250 ==
8474 11:52:29.478705 Dram Type= 6, Freq= 0, CH_1, rank 0
8475 11:52:29.481594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8476 11:52:29.481673 ==
8477 11:52:29.481737 RX Vref Scan: 0
8478 11:52:29.481797
8479 11:52:29.485124 RX Vref 0 -> 0, step: 1
8480 11:52:29.485201
8481 11:52:29.488625 RX Delay 0 -> 252, step: 8
8482 11:52:29.492316 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8483 11:52:29.495189 iDelay=208, Bit 1, Center 127 (72 ~ 183) 112
8484 11:52:29.498398 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8485 11:52:29.505370 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8486 11:52:29.508773 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8487 11:52:29.512274 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8488 11:52:29.515159 iDelay=208, Bit 6, Center 143 (96 ~ 191) 96
8489 11:52:29.518628 iDelay=208, Bit 7, Center 131 (80 ~ 183) 104
8490 11:52:29.522239 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8491 11:52:29.528533 iDelay=208, Bit 9, Center 115 (64 ~ 167) 104
8492 11:52:29.531919 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8493 11:52:29.535141 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8494 11:52:29.538699 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8495 11:52:29.545601 iDelay=208, Bit 13, Center 135 (80 ~ 191) 112
8496 11:52:29.548400 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8497 11:52:29.552008 iDelay=208, Bit 15, Center 131 (80 ~ 183) 104
8498 11:52:29.552098 ==
8499 11:52:29.555224 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 11:52:29.559088 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 11:52:29.559169 ==
8502 11:52:29.561833 DQS Delay:
8503 11:52:29.561930 DQS0 = 0, DQS1 = 0
8504 11:52:29.565174 DQM Delay:
8505 11:52:29.565273 DQM0 = 134, DQM1 = 126
8506 11:52:29.565365 DQ Delay:
8507 11:52:29.568764 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8508 11:52:29.572233 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =131
8509 11:52:29.578911 DQ8 =111, DQ9 =115, DQ10 =127, DQ11 =123
8510 11:52:29.582263 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =131
8511 11:52:29.582340
8512 11:52:29.582403
8513 11:52:29.582462 ==
8514 11:52:29.585489 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 11:52:29.588977 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 11:52:29.589054 ==
8517 11:52:29.589116
8518 11:52:29.589175
8519 11:52:29.591965 TX Vref Scan disable
8520 11:52:29.595915 == TX Byte 0 ==
8521 11:52:29.598764 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8522 11:52:29.602023 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8523 11:52:29.605571 == TX Byte 1 ==
8524 11:52:29.608736 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8525 11:52:29.611842 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8526 11:52:29.611915 ==
8527 11:52:29.615265 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 11:52:29.618530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 11:52:29.618627 ==
8530 11:52:29.632761
8531 11:52:29.636164 TX Vref early break, caculate TX vref
8532 11:52:29.639628 TX Vref=16, minBit 8, minWin=20, winSum=363
8533 11:52:29.643073 TX Vref=18, minBit 8, minWin=21, winSum=375
8534 11:52:29.646413 TX Vref=20, minBit 8, minWin=21, winSum=383
8535 11:52:29.649997 TX Vref=22, minBit 8, minWin=23, winSum=397
8536 11:52:29.652981 TX Vref=24, minBit 8, minWin=23, winSum=406
8537 11:52:29.659462 TX Vref=26, minBit 8, minWin=24, winSum=413
8538 11:52:29.663372 TX Vref=28, minBit 9, minWin=25, winSum=423
8539 11:52:29.666538 TX Vref=30, minBit 8, minWin=25, winSum=418
8540 11:52:29.669622 TX Vref=32, minBit 0, minWin=24, winSum=408
8541 11:52:29.673311 TX Vref=34, minBit 8, minWin=23, winSum=398
8542 11:52:29.680039 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
8543 11:52:29.680142
8544 11:52:29.683125 Final TX Range 0 Vref 28
8545 11:52:29.683198
8546 11:52:29.683260 ==
8547 11:52:29.686297 Dram Type= 6, Freq= 0, CH_1, rank 0
8548 11:52:29.689539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8549 11:52:29.689637 ==
8550 11:52:29.689726
8551 11:52:29.689822
8552 11:52:29.693007 TX Vref Scan disable
8553 11:52:29.700066 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8554 11:52:29.700156 == TX Byte 0 ==
8555 11:52:29.702900 u2DelayCellOfst[0]=17 cells (5 PI)
8556 11:52:29.706477 u2DelayCellOfst[1]=10 cells (3 PI)
8557 11:52:29.709853 u2DelayCellOfst[2]=0 cells (0 PI)
8558 11:52:29.713163 u2DelayCellOfst[3]=7 cells (2 PI)
8559 11:52:29.716640 u2DelayCellOfst[4]=7 cells (2 PI)
8560 11:52:29.719927 u2DelayCellOfst[5]=17 cells (5 PI)
8561 11:52:29.720027 u2DelayCellOfst[6]=17 cells (5 PI)
8562 11:52:29.722848 u2DelayCellOfst[7]=7 cells (2 PI)
8563 11:52:29.729788 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8564 11:52:29.733333 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8565 11:52:29.733409 == TX Byte 1 ==
8566 11:52:29.736445 u2DelayCellOfst[8]=0 cells (0 PI)
8567 11:52:29.739663 u2DelayCellOfst[9]=3 cells (1 PI)
8568 11:52:29.743140 u2DelayCellOfst[10]=10 cells (3 PI)
8569 11:52:29.746532 u2DelayCellOfst[11]=7 cells (2 PI)
8570 11:52:29.749832 u2DelayCellOfst[12]=14 cells (4 PI)
8571 11:52:29.753235 u2DelayCellOfst[13]=17 cells (5 PI)
8572 11:52:29.756391 u2DelayCellOfst[14]=17 cells (5 PI)
8573 11:52:29.760081 u2DelayCellOfst[15]=17 cells (5 PI)
8574 11:52:29.763414 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8575 11:52:29.766652 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8576 11:52:29.769749 DramC Write-DBI on
8577 11:52:29.769855 ==
8578 11:52:29.773350 Dram Type= 6, Freq= 0, CH_1, rank 0
8579 11:52:29.776572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8580 11:52:29.776650 ==
8581 11:52:29.776713
8582 11:52:29.776783
8583 11:52:29.780162 TX Vref Scan disable
8584 11:52:29.782924 == TX Byte 0 ==
8585 11:52:29.786489 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8586 11:52:29.786606 == TX Byte 1 ==
8587 11:52:29.793132 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8588 11:52:29.793212 DramC Write-DBI off
8589 11:52:29.793284
8590 11:52:29.796474 [DATLAT]
8591 11:52:29.796560 Freq=1600, CH1 RK0
8592 11:52:29.796634
8593 11:52:29.800237 DATLAT Default: 0xf
8594 11:52:29.800335 0, 0xFFFF, sum = 0
8595 11:52:29.803711 1, 0xFFFF, sum = 0
8596 11:52:29.803797 2, 0xFFFF, sum = 0
8597 11:52:29.806855 3, 0xFFFF, sum = 0
8598 11:52:29.806939 4, 0xFFFF, sum = 0
8599 11:52:29.810336 5, 0xFFFF, sum = 0
8600 11:52:29.810438 6, 0xFFFF, sum = 0
8601 11:52:29.813345 7, 0xFFFF, sum = 0
8602 11:52:29.813455 8, 0xFFFF, sum = 0
8603 11:52:29.816609 9, 0xFFFF, sum = 0
8604 11:52:29.816711 10, 0xFFFF, sum = 0
8605 11:52:29.819884 11, 0xFFFF, sum = 0
8606 11:52:29.819986 12, 0xFFFF, sum = 0
8607 11:52:29.823358 13, 0xFFFF, sum = 0
8608 11:52:29.823431 14, 0x0, sum = 1
8609 11:52:29.826968 15, 0x0, sum = 2
8610 11:52:29.827040 16, 0x0, sum = 3
8611 11:52:29.830188 17, 0x0, sum = 4
8612 11:52:29.830285 best_step = 15
8613 11:52:29.830380
8614 11:52:29.830465 ==
8615 11:52:29.833740 Dram Type= 6, Freq= 0, CH_1, rank 0
8616 11:52:29.839906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8617 11:52:29.840006 ==
8618 11:52:29.840103 RX Vref Scan: 1
8619 11:52:29.840189
8620 11:52:29.843350 Set Vref Range= 24 -> 127
8621 11:52:29.843460
8622 11:52:29.846654 RX Vref 24 -> 127, step: 1
8623 11:52:29.846756
8624 11:52:29.846867 RX Delay 11 -> 252, step: 4
8625 11:52:29.846971
8626 11:52:29.850412 Set Vref, RX VrefLevel [Byte0]: 24
8627 11:52:29.853723 [Byte1]: 24
8628 11:52:29.857311
8629 11:52:29.857415 Set Vref, RX VrefLevel [Byte0]: 25
8630 11:52:29.861039 [Byte1]: 25
8631 11:52:29.864792
8632 11:52:29.864889 Set Vref, RX VrefLevel [Byte0]: 26
8633 11:52:29.868167 [Byte1]: 26
8634 11:52:29.873019
8635 11:52:29.873120 Set Vref, RX VrefLevel [Byte0]: 27
8636 11:52:29.876152 [Byte1]: 27
8637 11:52:29.880189
8638 11:52:29.880263 Set Vref, RX VrefLevel [Byte0]: 28
8639 11:52:29.883410 [Byte1]: 28
8640 11:52:29.888235
8641 11:52:29.888306 Set Vref, RX VrefLevel [Byte0]: 29
8642 11:52:29.891425 [Byte1]: 29
8643 11:52:29.895579
8644 11:52:29.895653 Set Vref, RX VrefLevel [Byte0]: 30
8645 11:52:29.898666 [Byte1]: 30
8646 11:52:29.902851
8647 11:52:29.902944 Set Vref, RX VrefLevel [Byte0]: 31
8648 11:52:29.906914 [Byte1]: 31
8649 11:52:29.910945
8650 11:52:29.911015 Set Vref, RX VrefLevel [Byte0]: 32
8651 11:52:29.914045 [Byte1]: 32
8652 11:52:29.918133
8653 11:52:29.918235 Set Vref, RX VrefLevel [Byte0]: 33
8654 11:52:29.921671 [Byte1]: 33
8655 11:52:29.925881
8656 11:52:29.925983 Set Vref, RX VrefLevel [Byte0]: 34
8657 11:52:29.929310 [Byte1]: 34
8658 11:52:29.933903
8659 11:52:29.934001 Set Vref, RX VrefLevel [Byte0]: 35
8660 11:52:29.936708 [Byte1]: 35
8661 11:52:29.941257
8662 11:52:29.941361 Set Vref, RX VrefLevel [Byte0]: 36
8663 11:52:29.944922 [Byte1]: 36
8664 11:52:29.948735
8665 11:52:29.948832 Set Vref, RX VrefLevel [Byte0]: 37
8666 11:52:29.952258 [Byte1]: 37
8667 11:52:29.956601
8668 11:52:29.956670 Set Vref, RX VrefLevel [Byte0]: 38
8669 11:52:29.960039 [Byte1]: 38
8670 11:52:29.963894
8671 11:52:29.963993 Set Vref, RX VrefLevel [Byte0]: 39
8672 11:52:29.967974 [Byte1]: 39
8673 11:52:29.971800
8674 11:52:29.971900 Set Vref, RX VrefLevel [Byte0]: 40
8675 11:52:29.974986 [Byte1]: 40
8676 11:52:29.979041
8677 11:52:29.979114 Set Vref, RX VrefLevel [Byte0]: 41
8678 11:52:29.982376 [Byte1]: 41
8679 11:52:29.986961
8680 11:52:29.987062 Set Vref, RX VrefLevel [Byte0]: 42
8681 11:52:29.990091 [Byte1]: 42
8682 11:52:29.994225
8683 11:52:29.994326 Set Vref, RX VrefLevel [Byte0]: 43
8684 11:52:29.998104 [Byte1]: 43
8685 11:52:30.002244
8686 11:52:30.002339 Set Vref, RX VrefLevel [Byte0]: 44
8687 11:52:30.005372 [Byte1]: 44
8688 11:52:30.009537
8689 11:52:30.009630 Set Vref, RX VrefLevel [Byte0]: 45
8690 11:52:30.013362 [Byte1]: 45
8691 11:52:30.017271
8692 11:52:30.017343 Set Vref, RX VrefLevel [Byte0]: 46
8693 11:52:30.020960 [Byte1]: 46
8694 11:52:30.025683
8695 11:52:30.025779 Set Vref, RX VrefLevel [Byte0]: 47
8696 11:52:30.028394 [Byte1]: 47
8697 11:52:30.032473
8698 11:52:30.032568 Set Vref, RX VrefLevel [Byte0]: 48
8699 11:52:30.035920 [Byte1]: 48
8700 11:52:30.040013
8701 11:52:30.040079 Set Vref, RX VrefLevel [Byte0]: 49
8702 11:52:30.043781 [Byte1]: 49
8703 11:52:30.047744
8704 11:52:30.047838 Set Vref, RX VrefLevel [Byte0]: 50
8705 11:52:30.051441 [Byte1]: 50
8706 11:52:30.055373
8707 11:52:30.055471 Set Vref, RX VrefLevel [Byte0]: 51
8708 11:52:30.058994 [Byte1]: 51
8709 11:52:30.062883
8710 11:52:30.062993 Set Vref, RX VrefLevel [Byte0]: 52
8711 11:52:30.066605 [Byte1]: 52
8712 11:52:30.070514
8713 11:52:30.070609 Set Vref, RX VrefLevel [Byte0]: 53
8714 11:52:30.074380 [Byte1]: 53
8715 11:52:30.078266
8716 11:52:30.078365 Set Vref, RX VrefLevel [Byte0]: 54
8717 11:52:30.081523 [Byte1]: 54
8718 11:52:30.085689
8719 11:52:30.085785 Set Vref, RX VrefLevel [Byte0]: 55
8720 11:52:30.089099 [Byte1]: 55
8721 11:52:30.093479
8722 11:52:30.093608 Set Vref, RX VrefLevel [Byte0]: 56
8723 11:52:30.096689 [Byte1]: 56
8724 11:52:30.101398
8725 11:52:30.101467 Set Vref, RX VrefLevel [Byte0]: 57
8726 11:52:30.104244 [Byte1]: 57
8727 11:52:30.108603
8728 11:52:30.108676 Set Vref, RX VrefLevel [Byte0]: 58
8729 11:52:30.111871 [Byte1]: 58
8730 11:52:30.116409
8731 11:52:30.116474 Set Vref, RX VrefLevel [Byte0]: 59
8732 11:52:30.120016 [Byte1]: 59
8733 11:52:30.123705
8734 11:52:30.123772 Set Vref, RX VrefLevel [Byte0]: 60
8735 11:52:30.126973 [Byte1]: 60
8736 11:52:30.131248
8737 11:52:30.131317 Set Vref, RX VrefLevel [Byte0]: 61
8738 11:52:30.134582 [Byte1]: 61
8739 11:52:30.139223
8740 11:52:30.139319 Set Vref, RX VrefLevel [Byte0]: 62
8741 11:52:30.142181 [Byte1]: 62
8742 11:52:30.146822
8743 11:52:30.146909 Set Vref, RX VrefLevel [Byte0]: 63
8744 11:52:30.149939 [Byte1]: 63
8745 11:52:30.154107
8746 11:52:30.154177 Set Vref, RX VrefLevel [Byte0]: 64
8747 11:52:30.157418 [Byte1]: 64
8748 11:52:30.161766
8749 11:52:30.161860 Set Vref, RX VrefLevel [Byte0]: 65
8750 11:52:30.165260 [Byte1]: 65
8751 11:52:30.169451
8752 11:52:30.169544 Set Vref, RX VrefLevel [Byte0]: 66
8753 11:52:30.173102 [Byte1]: 66
8754 11:52:30.176950
8755 11:52:30.177047 Set Vref, RX VrefLevel [Byte0]: 67
8756 11:52:30.180428 [Byte1]: 67
8757 11:52:30.185148
8758 11:52:30.185248 Set Vref, RX VrefLevel [Byte0]: 68
8759 11:52:30.188390 [Byte1]: 68
8760 11:52:30.192519
8761 11:52:30.192615 Set Vref, RX VrefLevel [Byte0]: 69
8762 11:52:30.195590 [Byte1]: 69
8763 11:52:30.200340
8764 11:52:30.200436 Set Vref, RX VrefLevel [Byte0]: 70
8765 11:52:30.203211 [Byte1]: 70
8766 11:52:30.207831
8767 11:52:30.207905 Set Vref, RX VrefLevel [Byte0]: 71
8768 11:52:30.211151 [Byte1]: 71
8769 11:52:30.215372
8770 11:52:30.215448 Set Vref, RX VrefLevel [Byte0]: 72
8771 11:52:30.218793 [Byte1]: 72
8772 11:52:30.222585
8773 11:52:30.222680 Set Vref, RX VrefLevel [Byte0]: 73
8774 11:52:30.226424 [Byte1]: 73
8775 11:52:30.230194
8776 11:52:30.230288 Set Vref, RX VrefLevel [Byte0]: 74
8777 11:52:30.234112 [Byte1]: 74
8778 11:52:30.238061
8779 11:52:30.238153 Final RX Vref Byte 0 = 55 to rank0
8780 11:52:30.241635 Final RX Vref Byte 1 = 55 to rank0
8781 11:52:30.245194 Final RX Vref Byte 0 = 55 to rank1
8782 11:52:30.247906 Final RX Vref Byte 1 = 55 to rank1==
8783 11:52:30.251553 Dram Type= 6, Freq= 0, CH_1, rank 0
8784 11:52:30.258148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8785 11:52:30.258240 ==
8786 11:52:30.258328 DQS Delay:
8787 11:52:30.258414 DQS0 = 0, DQS1 = 0
8788 11:52:30.261180 DQM Delay:
8789 11:52:30.261272 DQM0 = 130, DQM1 = 124
8790 11:52:30.264587 DQ Delay:
8791 11:52:30.267938 DQ0 =134, DQ1 =124, DQ2 =118, DQ3 =130
8792 11:52:30.271188 DQ4 =128, DQ5 =142, DQ6 =140, DQ7 =126
8793 11:52:30.274741 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
8794 11:52:30.278006 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8795 11:52:30.278138
8796 11:52:30.278224
8797 11:52:30.278309
8798 11:52:30.281515 [DramC_TX_OE_Calibration] TA2
8799 11:52:30.285237 Original DQ_B0 (3 6) =30, OEN = 27
8800 11:52:30.287995 Original DQ_B1 (3 6) =30, OEN = 27
8801 11:52:30.291273 24, 0x0, End_B0=24 End_B1=24
8802 11:52:30.291411 25, 0x0, End_B0=25 End_B1=25
8803 11:52:30.294770 26, 0x0, End_B0=26 End_B1=26
8804 11:52:30.298211 27, 0x0, End_B0=27 End_B1=27
8805 11:52:30.301434 28, 0x0, End_B0=28 End_B1=28
8806 11:52:30.301520 29, 0x0, End_B0=29 End_B1=29
8807 11:52:30.304826 30, 0x0, End_B0=30 End_B1=30
8808 11:52:30.307713 31, 0x4545, End_B0=30 End_B1=30
8809 11:52:30.311118 Byte0 end_step=30 best_step=27
8810 11:52:30.314656 Byte1 end_step=30 best_step=27
8811 11:52:30.317862 Byte0 TX OE(2T, 0.5T) = (3, 3)
8812 11:52:30.317955 Byte1 TX OE(2T, 0.5T) = (3, 3)
8813 11:52:30.321140
8814 11:52:30.321229
8815 11:52:30.328101 [DQSOSCAuto] RK0, (LSB)MR18= 0x1802, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 397 ps
8816 11:52:30.331481 CH1 RK0: MR19=303, MR18=1802
8817 11:52:30.337845 CH1_RK0: MR19=0x303, MR18=0x1802, DQSOSC=397, MR23=63, INC=23, DEC=15
8818 11:52:30.337945
8819 11:52:30.341477 ----->DramcWriteLeveling(PI) begin...
8820 11:52:30.341560 ==
8821 11:52:30.344467 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 11:52:30.348431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 11:52:30.348503 ==
8824 11:52:30.351365 Write leveling (Byte 0): 23 => 23
8825 11:52:30.354733 Write leveling (Byte 1): 26 => 26
8826 11:52:30.358203 DramcWriteLeveling(PI) end<-----
8827 11:52:30.358307
8828 11:52:30.358384 ==
8829 11:52:30.361202 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 11:52:30.364490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 11:52:30.364601 ==
8832 11:52:30.368090 [Gating] SW mode calibration
8833 11:52:30.374713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8834 11:52:30.381454 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8835 11:52:30.384617 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8836 11:52:30.387975 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8837 11:52:30.394821 1 4 8 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
8838 11:52:30.398206 1 4 12 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8839 11:52:30.401323 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8840 11:52:30.408148 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8841 11:52:30.411367 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 11:52:30.414679 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 11:52:30.421705 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 11:52:30.424555 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8845 11:52:30.428334 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
8846 11:52:30.431820 1 5 12 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
8847 11:52:30.438173 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8848 11:52:30.441327 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8849 11:52:30.444677 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 11:52:30.451396 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 11:52:30.455221 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 11:52:30.458278 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 11:52:30.464737 1 6 8 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8854 11:52:30.468702 1 6 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
8855 11:52:30.471511 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8856 11:52:30.478446 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 11:52:30.481479 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 11:52:30.484864 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 11:52:30.491406 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 11:52:30.494805 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8861 11:52:30.498445 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8862 11:52:30.501708 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8863 11:52:30.508650 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8864 11:52:30.511548 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 11:52:30.514734 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 11:52:30.521811 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 11:52:30.525410 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 11:52:30.528118 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 11:52:30.535228 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 11:52:30.538103 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 11:52:30.541439 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 11:52:30.548366 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 11:52:30.551751 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 11:52:30.554838 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 11:52:30.561569 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 11:52:30.564882 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8877 11:52:30.568361 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8878 11:52:30.575473 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8879 11:52:30.575548 Total UI for P1: 0, mck2ui 16
8880 11:52:30.578702 best dqsien dly found for B0: ( 1, 9, 6)
8881 11:52:30.585243 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8882 11:52:30.588385 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8883 11:52:30.591827 Total UI for P1: 0, mck2ui 16
8884 11:52:30.595168 best dqsien dly found for B1: ( 1, 9, 14)
8885 11:52:30.598363 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8886 11:52:30.601958 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8887 11:52:30.602029
8888 11:52:30.605186 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8889 11:52:30.608913 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8890 11:52:30.611713 [Gating] SW calibration Done
8891 11:52:30.611812 ==
8892 11:52:30.615305 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 11:52:30.621954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 11:52:30.622036 ==
8895 11:52:30.622100 RX Vref Scan: 0
8896 11:52:30.622159
8897 11:52:30.625235 RX Vref 0 -> 0, step: 1
8898 11:52:30.625341
8899 11:52:30.628283 RX Delay 0 -> 252, step: 8
8900 11:52:30.631725 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8901 11:52:30.635147 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8902 11:52:30.638666 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8903 11:52:30.642076 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8904 11:52:30.648507 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8905 11:52:30.651807 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8906 11:52:30.655156 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8907 11:52:30.658778 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8908 11:52:30.662350 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8909 11:52:30.665686 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8910 11:52:30.672387 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8911 11:52:30.675949 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8912 11:52:30.678832 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8913 11:52:30.682410 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8914 11:52:30.685613 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8915 11:52:30.692219 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8916 11:52:30.692367 ==
8917 11:52:30.695595 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 11:52:30.698688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 11:52:30.698812 ==
8920 11:52:30.698926 DQS Delay:
8921 11:52:30.702492 DQS0 = 0, DQS1 = 0
8922 11:52:30.702594 DQM Delay:
8923 11:52:30.705977 DQM0 = 132, DQM1 = 128
8924 11:52:30.706106 DQ Delay:
8925 11:52:30.709229 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8926 11:52:30.712648 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8927 11:52:30.715400 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8928 11:52:30.719466 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =139
8929 11:52:30.719550
8930 11:52:30.719615
8931 11:52:30.722694 ==
8932 11:52:30.725606 Dram Type= 6, Freq= 0, CH_1, rank 1
8933 11:52:30.728901 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8934 11:52:30.729004 ==
8935 11:52:30.729094
8936 11:52:30.729210
8937 11:52:30.732280 TX Vref Scan disable
8938 11:52:30.732348 == TX Byte 0 ==
8939 11:52:30.735310 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8940 11:52:30.741976 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8941 11:52:30.742073 == TX Byte 1 ==
8942 11:52:30.745551 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8943 11:52:30.752428 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8944 11:52:30.752538 ==
8945 11:52:30.755716 Dram Type= 6, Freq= 0, CH_1, rank 1
8946 11:52:30.758574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8947 11:52:30.758659 ==
8948 11:52:30.773062
8949 11:52:30.776642 TX Vref early break, caculate TX vref
8950 11:52:30.779965 TX Vref=16, minBit 5, minWin=23, winSum=382
8951 11:52:30.783268 TX Vref=18, minBit 8, minWin=23, winSum=391
8952 11:52:30.786673 TX Vref=20, minBit 1, minWin=24, winSum=402
8953 11:52:30.789824 TX Vref=22, minBit 9, minWin=24, winSum=408
8954 11:52:30.793359 TX Vref=24, minBit 0, minWin=25, winSum=415
8955 11:52:30.796750 TX Vref=26, minBit 0, minWin=26, winSum=427
8956 11:52:30.803141 TX Vref=28, minBit 5, minWin=26, winSum=433
8957 11:52:30.806617 TX Vref=30, minBit 5, minWin=26, winSum=431
8958 11:52:30.810189 TX Vref=32, minBit 0, minWin=25, winSum=423
8959 11:52:30.813208 TX Vref=34, minBit 8, minWin=24, winSum=412
8960 11:52:30.817236 TX Vref=36, minBit 0, minWin=24, winSum=402
8961 11:52:30.823370 [TxChooseVref] Worse bit 5, Min win 26, Win sum 433, Final Vref 28
8962 11:52:30.823472
8963 11:52:30.826536 Final TX Range 0 Vref 28
8964 11:52:30.826634
8965 11:52:30.826721 ==
8966 11:52:30.829999 Dram Type= 6, Freq= 0, CH_1, rank 1
8967 11:52:30.833326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8968 11:52:30.833402 ==
8969 11:52:30.833466
8970 11:52:30.833554
8971 11:52:30.836709 TX Vref Scan disable
8972 11:52:30.843564 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8973 11:52:30.843642 == TX Byte 0 ==
8974 11:52:30.846714 u2DelayCellOfst[0]=17 cells (5 PI)
8975 11:52:30.850166 u2DelayCellOfst[1]=14 cells (4 PI)
8976 11:52:30.853388 u2DelayCellOfst[2]=0 cells (0 PI)
8977 11:52:30.856678 u2DelayCellOfst[3]=7 cells (2 PI)
8978 11:52:30.860230 u2DelayCellOfst[4]=7 cells (2 PI)
8979 11:52:30.863698 u2DelayCellOfst[5]=17 cells (5 PI)
8980 11:52:30.866994 u2DelayCellOfst[6]=17 cells (5 PI)
8981 11:52:30.867094 u2DelayCellOfst[7]=3 cells (1 PI)
8982 11:52:30.873166 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8983 11:52:30.876540 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8984 11:52:30.876615 == TX Byte 1 ==
8985 11:52:30.880245 u2DelayCellOfst[8]=0 cells (0 PI)
8986 11:52:30.883589 u2DelayCellOfst[9]=3 cells (1 PI)
8987 11:52:30.886916 u2DelayCellOfst[10]=10 cells (3 PI)
8988 11:52:30.890195 u2DelayCellOfst[11]=7 cells (2 PI)
8989 11:52:30.893257 u2DelayCellOfst[12]=14 cells (4 PI)
8990 11:52:30.896833 u2DelayCellOfst[13]=14 cells (4 PI)
8991 11:52:30.900563 u2DelayCellOfst[14]=17 cells (5 PI)
8992 11:52:30.903790 u2DelayCellOfst[15]=14 cells (4 PI)
8993 11:52:30.906753 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8994 11:52:30.910495 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8995 11:52:30.913722 DramC Write-DBI on
8996 11:52:30.913795 ==
8997 11:52:30.916991 Dram Type= 6, Freq= 0, CH_1, rank 1
8998 11:52:30.920432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8999 11:52:30.920505 ==
9000 11:52:30.920566
9001 11:52:30.920624
9002 11:52:30.923524 TX Vref Scan disable
9003 11:52:30.926853 == TX Byte 0 ==
9004 11:52:30.930488 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9005 11:52:30.930585 == TX Byte 1 ==
9006 11:52:30.936917 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9007 11:52:30.936994 DramC Write-DBI off
9008 11:52:30.937058
9009 11:52:30.940357 [DATLAT]
9010 11:52:30.940456 Freq=1600, CH1 RK1
9011 11:52:30.940545
9012 11:52:30.943754 DATLAT Default: 0xf
9013 11:52:30.943828 0, 0xFFFF, sum = 0
9014 11:52:30.946902 1, 0xFFFF, sum = 0
9015 11:52:30.946985 2, 0xFFFF, sum = 0
9016 11:52:30.951097 3, 0xFFFF, sum = 0
9017 11:52:30.951168 4, 0xFFFF, sum = 0
9018 11:52:30.953924 5, 0xFFFF, sum = 0
9019 11:52:30.954021 6, 0xFFFF, sum = 0
9020 11:52:30.957443 7, 0xFFFF, sum = 0
9021 11:52:30.957540 8, 0xFFFF, sum = 0
9022 11:52:30.960692 9, 0xFFFF, sum = 0
9023 11:52:30.960793 10, 0xFFFF, sum = 0
9024 11:52:30.964159 11, 0xFFFF, sum = 0
9025 11:52:30.964257 12, 0xFFFF, sum = 0
9026 11:52:30.967482 13, 0xFFFF, sum = 0
9027 11:52:30.967552 14, 0x0, sum = 1
9028 11:52:30.970341 15, 0x0, sum = 2
9029 11:52:30.970438 16, 0x0, sum = 3
9030 11:52:30.973765 17, 0x0, sum = 4
9031 11:52:30.973889 best_step = 15
9032 11:52:30.973979
9033 11:52:30.974066 ==
9034 11:52:30.977222 Dram Type= 6, Freq= 0, CH_1, rank 1
9035 11:52:30.983676 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9036 11:52:30.983752 ==
9037 11:52:30.983814 RX Vref Scan: 0
9038 11:52:30.983872
9039 11:52:30.987084 RX Vref 0 -> 0, step: 1
9040 11:52:30.987196
9041 11:52:30.990645 RX Delay 11 -> 252, step: 4
9042 11:52:30.993857 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
9043 11:52:30.997860 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
9044 11:52:31.000514 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
9045 11:52:31.007387 iDelay=195, Bit 3, Center 128 (79 ~ 178) 100
9046 11:52:31.010593 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
9047 11:52:31.013804 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9048 11:52:31.017172 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
9049 11:52:31.020729 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
9050 11:52:31.027450 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9051 11:52:31.030882 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9052 11:52:31.033728 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9053 11:52:31.037290 iDelay=195, Bit 11, Center 118 (67 ~ 170) 104
9054 11:52:31.040693 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
9055 11:52:31.047604 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9056 11:52:31.050747 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9057 11:52:31.054052 iDelay=195, Bit 15, Center 134 (83 ~ 186) 104
9058 11:52:31.054132 ==
9059 11:52:31.057485 Dram Type= 6, Freq= 0, CH_1, rank 1
9060 11:52:31.060780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9061 11:52:31.060861 ==
9062 11:52:31.063822 DQS Delay:
9063 11:52:31.063902 DQS0 = 0, DQS1 = 0
9064 11:52:31.067489 DQM Delay:
9065 11:52:31.067569 DQM0 = 129, DQM1 = 126
9066 11:52:31.067632 DQ Delay:
9067 11:52:31.074477 DQ0 =132, DQ1 =124, DQ2 =116, DQ3 =128
9068 11:52:31.077306 DQ4 =128, DQ5 =142, DQ6 =138, DQ7 =124
9069 11:52:31.080937 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =118
9070 11:52:31.084325 DQ12 =134, DQ13 =136, DQ14 =134, DQ15 =134
9071 11:52:31.084405
9072 11:52:31.084467
9073 11:52:31.084543
9074 11:52:31.087683 [DramC_TX_OE_Calibration] TA2
9075 11:52:31.091155 Original DQ_B0 (3 6) =30, OEN = 27
9076 11:52:31.094383 Original DQ_B1 (3 6) =30, OEN = 27
9077 11:52:31.094497 24, 0x0, End_B0=24 End_B1=24
9078 11:52:31.097242 25, 0x0, End_B0=25 End_B1=25
9079 11:52:31.100665 26, 0x0, End_B0=26 End_B1=26
9080 11:52:31.103877 27, 0x0, End_B0=27 End_B1=27
9081 11:52:31.103958 28, 0x0, End_B0=28 End_B1=28
9082 11:52:31.107751 29, 0x0, End_B0=29 End_B1=29
9083 11:52:31.110879 30, 0x0, End_B0=30 End_B1=30
9084 11:52:31.114744 31, 0x4141, End_B0=30 End_B1=30
9085 11:52:31.117932 Byte0 end_step=30 best_step=27
9086 11:52:31.118012 Byte1 end_step=30 best_step=27
9087 11:52:31.121264 Byte0 TX OE(2T, 0.5T) = (3, 3)
9088 11:52:31.124507 Byte1 TX OE(2T, 0.5T) = (3, 3)
9089 11:52:31.124577
9090 11:52:31.124638
9091 11:52:31.134530 [DQSOSCAuto] RK1, (LSB)MR18= 0xf14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 402 ps
9092 11:52:31.134636 CH1 RK1: MR19=303, MR18=F14
9093 11:52:31.141109 CH1_RK1: MR19=0x303, MR18=0xF14, DQSOSC=399, MR23=63, INC=23, DEC=15
9094 11:52:31.144377 [RxdqsGatingPostProcess] freq 1600
9095 11:52:31.150954 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9096 11:52:31.154292 best DQS0 dly(2T, 0.5T) = (1, 1)
9097 11:52:31.157786 best DQS1 dly(2T, 0.5T) = (1, 1)
9098 11:52:31.160945 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9099 11:52:31.161044 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9100 11:52:31.164267 best DQS0 dly(2T, 0.5T) = (1, 1)
9101 11:52:31.167745 best DQS1 dly(2T, 0.5T) = (1, 1)
9102 11:52:31.171176 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9103 11:52:31.174460 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9104 11:52:31.177943 Pre-setting of DQS Precalculation
9105 11:52:31.181178 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9106 11:52:31.191091 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9107 11:52:31.198366 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9108 11:52:31.198469
9109 11:52:31.198559
9110 11:52:31.201092 [Calibration Summary] 3200 Mbps
9111 11:52:31.201183 CH 0, Rank 0
9112 11:52:31.204699 SW Impedance : PASS
9113 11:52:31.204765 DUTY Scan : NO K
9114 11:52:31.207694 ZQ Calibration : PASS
9115 11:52:31.211179 Jitter Meter : NO K
9116 11:52:31.211245 CBT Training : PASS
9117 11:52:31.214369 Write leveling : PASS
9118 11:52:31.217983 RX DQS gating : PASS
9119 11:52:31.218081 RX DQ/DQS(RDDQC) : PASS
9120 11:52:31.221700 TX DQ/DQS : PASS
9121 11:52:31.224402 RX DATLAT : PASS
9122 11:52:31.224473 RX DQ/DQS(Engine): PASS
9123 11:52:31.227862 TX OE : PASS
9124 11:52:31.227929 All Pass.
9125 11:52:31.227988
9126 11:52:31.231107 CH 0, Rank 1
9127 11:52:31.231172 SW Impedance : PASS
9128 11:52:31.234586 DUTY Scan : NO K
9129 11:52:31.237946 ZQ Calibration : PASS
9130 11:52:31.238041 Jitter Meter : NO K
9131 11:52:31.241395 CBT Training : PASS
9132 11:52:31.241488 Write leveling : PASS
9133 11:52:31.244413 RX DQS gating : PASS
9134 11:52:31.247887 RX DQ/DQS(RDDQC) : PASS
9135 11:52:31.247985 TX DQ/DQS : PASS
9136 11:52:31.251162 RX DATLAT : PASS
9137 11:52:31.254574 RX DQ/DQS(Engine): PASS
9138 11:52:31.254674 TX OE : PASS
9139 11:52:31.257947 All Pass.
9140 11:52:31.258044
9141 11:52:31.258133 CH 1, Rank 0
9142 11:52:31.261715 SW Impedance : PASS
9143 11:52:31.261812 DUTY Scan : NO K
9144 11:52:31.264992 ZQ Calibration : PASS
9145 11:52:31.267926 Jitter Meter : NO K
9146 11:52:31.268001 CBT Training : PASS
9147 11:52:31.271377 Write leveling : PASS
9148 11:52:31.274708 RX DQS gating : PASS
9149 11:52:31.274808 RX DQ/DQS(RDDQC) : PASS
9150 11:52:31.278600 TX DQ/DQS : PASS
9151 11:52:31.278675 RX DATLAT : PASS
9152 11:52:31.281775 RX DQ/DQS(Engine): PASS
9153 11:52:31.284785 TX OE : PASS
9154 11:52:31.284884 All Pass.
9155 11:52:31.284971
9156 11:52:31.285056 CH 1, Rank 1
9157 11:52:31.288001 SW Impedance : PASS
9158 11:52:31.291556 DUTY Scan : NO K
9159 11:52:31.291632 ZQ Calibration : PASS
9160 11:52:31.294743 Jitter Meter : NO K
9161 11:52:31.298195 CBT Training : PASS
9162 11:52:31.298293 Write leveling : PASS
9163 11:52:31.301391 RX DQS gating : PASS
9164 11:52:31.305227 RX DQ/DQS(RDDQC) : PASS
9165 11:52:31.305300 TX DQ/DQS : PASS
9166 11:52:31.308217 RX DATLAT : PASS
9167 11:52:31.308289 RX DQ/DQS(Engine): PASS
9168 11:52:31.311443 TX OE : PASS
9169 11:52:31.311525 All Pass.
9170 11:52:31.311606
9171 11:52:31.314743 DramC Write-DBI on
9172 11:52:31.318107 PER_BANK_REFRESH: Hybrid Mode
9173 11:52:31.318178 TX_TRACKING: ON
9174 11:52:31.328170 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9175 11:52:31.334992 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9176 11:52:31.341437 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9177 11:52:31.348636 [FAST_K] Save calibration result to emmc
9178 11:52:31.348717 sync common calibartion params.
9179 11:52:31.351381 sync cbt_mode0:1, 1:1
9180 11:52:31.355159 dram_init: ddr_geometry: 2
9181 11:52:31.355256 dram_init: ddr_geometry: 2
9182 11:52:31.358068 dram_init: ddr_geometry: 2
9183 11:52:31.361396 0:dram_rank_size:100000000
9184 11:52:31.364838 1:dram_rank_size:100000000
9185 11:52:31.368097 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9186 11:52:31.371436 DFS_SHUFFLE_HW_MODE: ON
9187 11:52:31.374667 dramc_set_vcore_voltage set vcore to 725000
9188 11:52:31.378591 Read voltage for 1600, 0
9189 11:52:31.378671 Vio18 = 0
9190 11:52:31.378734 Vcore = 725000
9191 11:52:31.381433 Vdram = 0
9192 11:52:31.381513 Vddq = 0
9193 11:52:31.381576 Vmddr = 0
9194 11:52:31.385108 switch to 3200 Mbps bootup
9195 11:52:31.388247 [DramcRunTimeConfig]
9196 11:52:31.388327 PHYPLL
9197 11:52:31.388430 DPM_CONTROL_AFTERK: ON
9198 11:52:31.391689 PER_BANK_REFRESH: ON
9199 11:52:31.395069 REFRESH_OVERHEAD_REDUCTION: ON
9200 11:52:31.395185 CMD_PICG_NEW_MODE: OFF
9201 11:52:31.398469 XRTWTW_NEW_MODE: ON
9202 11:52:31.401586 XRTRTR_NEW_MODE: ON
9203 11:52:31.401665 TX_TRACKING: ON
9204 11:52:31.405020 RDSEL_TRACKING: OFF
9205 11:52:31.405099 DQS Precalculation for DVFS: ON
9206 11:52:31.408272 RX_TRACKING: OFF
9207 11:52:31.408354 HW_GATING DBG: ON
9208 11:52:31.411883 ZQCS_ENABLE_LP4: ON
9209 11:52:31.411980 RX_PICG_NEW_MODE: ON
9210 11:52:31.414988 TX_PICG_NEW_MODE: ON
9211 11:52:31.418304 ENABLE_RX_DCM_DPHY: ON
9212 11:52:31.421619 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9213 11:52:31.421691 DUMMY_READ_FOR_TRACKING: OFF
9214 11:52:31.425119 !!! SPM_CONTROL_AFTERK: OFF
9215 11:52:31.428230 !!! SPM could not control APHY
9216 11:52:31.431453 IMPEDANCE_TRACKING: ON
9217 11:52:31.431551 TEMP_SENSOR: ON
9218 11:52:31.431638 HW_SAVE_FOR_SR: OFF
9219 11:52:31.435322 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9220 11:52:31.442257 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9221 11:52:31.442357 Read ODT Tracking: ON
9222 11:52:31.444959 Refresh Rate DeBounce: ON
9223 11:52:31.445047 DFS_NO_QUEUE_FLUSH: ON
9224 11:52:31.448593 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9225 11:52:31.451899 ENABLE_DFS_RUNTIME_MRW: OFF
9226 11:52:31.454881 DDR_RESERVE_NEW_MODE: ON
9227 11:52:31.454975 MR_CBT_SWITCH_FREQ: ON
9228 11:52:31.458248 =========================
9229 11:52:31.478073 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9230 11:52:31.481091 dram_init: ddr_geometry: 2
9231 11:52:31.499190 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9232 11:52:31.502525 dram_init: dram init end (result: 0)
9233 11:52:31.508859 DRAM-K: Full calibration passed in 24554 msecs
9234 11:52:31.512623 MRC: failed to locate region type 0.
9235 11:52:31.512703 DRAM rank0 size:0x100000000,
9236 11:52:31.515637 DRAM rank1 size=0x100000000
9237 11:52:31.525882 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9238 11:52:31.532821 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9239 11:52:31.539138 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9240 11:52:31.545720 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9241 11:52:31.549504 DRAM rank0 size:0x100000000,
9242 11:52:31.553002 DRAM rank1 size=0x100000000
9243 11:52:31.553083 CBMEM:
9244 11:52:31.556288 IMD: root @ 0xfffff000 254 entries.
9245 11:52:31.559109 IMD: root @ 0xffffec00 62 entries.
9246 11:52:31.562539 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9247 11:52:31.565795 WARNING: RO_VPD is uninitialized or empty.
9248 11:52:31.572660 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9249 11:52:31.579317 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9250 11:52:31.591914 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9251 11:52:31.603331 BS: romstage times (exec / console): total (unknown) / 24062 ms
9252 11:52:31.603412
9253 11:52:31.603475
9254 11:52:31.613256 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9255 11:52:31.616714 ARM64: Exception handlers installed.
9256 11:52:31.620291 ARM64: Testing exception
9257 11:52:31.623328 ARM64: Done test exception
9258 11:52:31.623435 Enumerating buses...
9259 11:52:31.626644 Show all devs... Before device enumeration.
9260 11:52:31.630104 Root Device: enabled 1
9261 11:52:31.633605 CPU_CLUSTER: 0: enabled 1
9262 11:52:31.633684 CPU: 00: enabled 1
9263 11:52:31.636650 Compare with tree...
9264 11:52:31.636730 Root Device: enabled 1
9265 11:52:31.639866 CPU_CLUSTER: 0: enabled 1
9266 11:52:31.643209 CPU: 00: enabled 1
9267 11:52:31.643315 Root Device scanning...
9268 11:52:31.646641 scan_static_bus for Root Device
9269 11:52:31.650123 CPU_CLUSTER: 0 enabled
9270 11:52:31.653392 scan_static_bus for Root Device done
9271 11:52:31.656576 scan_bus: bus Root Device finished in 8 msecs
9272 11:52:31.656656 done
9273 11:52:31.663566 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9274 11:52:31.666373 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9275 11:52:31.673511 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9276 11:52:31.676485 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9277 11:52:31.679907 Allocating resources...
9278 11:52:31.679987 Reading resources...
9279 11:52:31.686587 Root Device read_resources bus 0 link: 0
9280 11:52:31.686668 DRAM rank0 size:0x100000000,
9281 11:52:31.690634 DRAM rank1 size=0x100000000
9282 11:52:31.693560 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9283 11:52:31.696939 CPU: 00 missing read_resources
9284 11:52:31.699903 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9285 11:52:31.706727 Root Device read_resources bus 0 link: 0 done
9286 11:52:31.706808 Done reading resources.
9287 11:52:31.713359 Show resources in subtree (Root Device)...After reading.
9288 11:52:31.716756 Root Device child on link 0 CPU_CLUSTER: 0
9289 11:52:31.720415 CPU_CLUSTER: 0 child on link 0 CPU: 00
9290 11:52:31.729795 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9291 11:52:31.729876 CPU: 00
9292 11:52:31.733436 Root Device assign_resources, bus 0 link: 0
9293 11:52:31.736751 CPU_CLUSTER: 0 missing set_resources
9294 11:52:31.740151 Root Device assign_resources, bus 0 link: 0 done
9295 11:52:31.743391 Done setting resources.
9296 11:52:31.749997 Show resources in subtree (Root Device)...After assigning values.
9297 11:52:31.753581 Root Device child on link 0 CPU_CLUSTER: 0
9298 11:52:31.757132 CPU_CLUSTER: 0 child on link 0 CPU: 00
9299 11:52:31.766918 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9300 11:52:31.767000 CPU: 00
9301 11:52:31.770468 Done allocating resources.
9302 11:52:31.773558 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9303 11:52:31.776578 Enabling resources...
9304 11:52:31.776653 done.
9305 11:52:31.780170 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9306 11:52:31.783384 Initializing devices...
9307 11:52:31.783464 Root Device init
9308 11:52:31.786562 init hardware done!
9309 11:52:31.790062 0x00000018: ctrlr->caps
9310 11:52:31.790144 52.000 MHz: ctrlr->f_max
9311 11:52:31.793418 0.400 MHz: ctrlr->f_min
9312 11:52:31.796738 0x40ff8080: ctrlr->voltages
9313 11:52:31.796820 sclk: 390625
9314 11:52:31.796884 Bus Width = 1
9315 11:52:31.800116 sclk: 390625
9316 11:52:31.800196 Bus Width = 1
9317 11:52:31.803294 Early init status = 3
9318 11:52:31.806557 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9319 11:52:31.810918 in-header: 03 fb 00 00 01 00 00 00
9320 11:52:31.814504 in-data: 01
9321 11:52:31.818035 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9322 11:52:31.822594 in-header: 03 fb 00 00 01 00 00 00
9323 11:52:31.826437 in-data: 01
9324 11:52:31.829625 [SSUSB] Setting up USB HOST controller...
9325 11:52:31.832747 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9326 11:52:31.835620 [SSUSB] phy power-on done.
9327 11:52:31.839005 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9328 11:52:31.846277 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9329 11:52:31.849358 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9330 11:52:31.856048 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9331 11:52:31.862476 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9332 11:52:31.869067 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9333 11:52:31.875907 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9334 11:52:31.882367 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9335 11:52:31.886096 SPM: binary array size = 0x9dc
9336 11:52:31.888757 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9337 11:52:31.895679 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9338 11:52:31.902299 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9339 11:52:31.905731 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9340 11:52:31.912478 configure_display: Starting display init
9341 11:52:31.946008 anx7625_power_on_init: Init interface.
9342 11:52:31.949638 anx7625_disable_pd_protocol: Disabled PD feature.
9343 11:52:31.952405 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9344 11:52:31.980681 anx7625_start_dp_work: Secure OCM version=00
9345 11:52:31.983750 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9346 11:52:31.998429 sp_tx_get_edid_block: EDID Block = 1
9347 11:52:32.100894 Extracted contents:
9348 11:52:32.104310 header: 00 ff ff ff ff ff ff 00
9349 11:52:32.107884 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9350 11:52:32.111098 version: 01 04
9351 11:52:32.114629 basic params: 95 1f 11 78 0a
9352 11:52:32.117949 chroma info: 76 90 94 55 54 90 27 21 50 54
9353 11:52:32.121259 established: 00 00 00
9354 11:52:32.124717 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9355 11:52:32.131313 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9356 11:52:32.137818 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9357 11:52:32.144880 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9358 11:52:32.151047 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9359 11:52:32.151128 extensions: 00
9360 11:52:32.154600 checksum: fb
9361 11:52:32.154680
9362 11:52:32.158052 Manufacturer: IVO Model 57d Serial Number 0
9363 11:52:32.161088 Made week 0 of 2020
9364 11:52:32.161167 EDID version: 1.4
9365 11:52:32.164628 Digital display
9366 11:52:32.168227 6 bits per primary color channel
9367 11:52:32.168331 DisplayPort interface
9368 11:52:32.171029 Maximum image size: 31 cm x 17 cm
9369 11:52:32.171107 Gamma: 220%
9370 11:52:32.174575 Check DPMS levels
9371 11:52:32.177910 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9372 11:52:32.181382 First detailed timing is preferred timing
9373 11:52:32.184530 Established timings supported:
9374 11:52:32.187785 Standard timings supported:
9375 11:52:32.187863 Detailed timings
9376 11:52:32.194398 Hex of detail: 383680a07038204018303c0035ae10000019
9377 11:52:32.197799 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9378 11:52:32.201252 0780 0798 07c8 0820 hborder 0
9379 11:52:32.207893 0438 043b 0447 0458 vborder 0
9380 11:52:32.207973 -hsync -vsync
9381 11:52:32.211598 Did detailed timing
9382 11:52:32.214935 Hex of detail: 000000000000000000000000000000000000
9383 11:52:32.217984 Manufacturer-specified data, tag 0
9384 11:52:32.224718 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9385 11:52:32.224798 ASCII string: InfoVision
9386 11:52:32.231291 Hex of detail: 000000fe00523134304e574635205248200a
9387 11:52:32.231371 ASCII string: R140NWF5 RH
9388 11:52:32.234619 Checksum
9389 11:52:32.234697 Checksum: 0xfb (valid)
9390 11:52:32.241606 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9391 11:52:32.241686 DSI data_rate: 832800000 bps
9392 11:52:32.249068 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9393 11:52:32.252300 anx7625_parse_edid: pixelclock(138800).
9394 11:52:32.255397 hactive(1920), hsync(48), hfp(24), hbp(88)
9395 11:52:32.258490 vactive(1080), vsync(12), vfp(3), vbp(17)
9396 11:52:32.261912 anx7625_dsi_config: config dsi.
9397 11:52:32.268938 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9398 11:52:32.283343 anx7625_dsi_config: success to config DSI
9399 11:52:32.286201 anx7625_dp_start: MIPI phy setup OK.
9400 11:52:32.289637 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9401 11:52:32.292845 mtk_ddp_mode_set invalid vrefresh 60
9402 11:52:32.296602 main_disp_path_setup
9403 11:52:32.296681 ovl_layer_smi_id_en
9404 11:52:32.300146 ovl_layer_smi_id_en
9405 11:52:32.300225 ccorr_config
9406 11:52:32.300288 aal_config
9407 11:52:32.303280 gamma_config
9408 11:52:32.303364 postmask_config
9409 11:52:32.306282 dither_config
9410 11:52:32.309597 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9411 11:52:32.316665 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9412 11:52:32.319840 Root Device init finished in 530 msecs
9413 11:52:32.319919 CPU_CLUSTER: 0 init
9414 11:52:32.329592 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9415 11:52:32.333163 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9416 11:52:32.336324 APU_MBOX 0x190000b0 = 0x10001
9417 11:52:32.340028 APU_MBOX 0x190001b0 = 0x10001
9418 11:52:32.343326 APU_MBOX 0x190005b0 = 0x10001
9419 11:52:32.346632 APU_MBOX 0x190006b0 = 0x10001
9420 11:52:32.349919 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9421 11:52:32.361948 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9422 11:52:32.374515 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9423 11:52:32.380847 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9424 11:52:32.392596 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9425 11:52:32.402028 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9426 11:52:32.405174 CPU_CLUSTER: 0 init finished in 81 msecs
9427 11:52:32.408558 Devices initialized
9428 11:52:32.412268 Show all devs... After init.
9429 11:52:32.412350 Root Device: enabled 1
9430 11:52:32.414961 CPU_CLUSTER: 0: enabled 1
9431 11:52:32.418431 CPU: 00: enabled 1
9432 11:52:32.421936 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9433 11:52:32.425189 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9434 11:52:32.428546 ELOG: NV offset 0x57f000 size 0x1000
9435 11:52:32.435577 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9436 11:52:32.441941 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9437 11:52:32.445375 ELOG: Event(17) added with size 13 at 2023-11-23 11:52:33 UTC
9438 11:52:32.448534 out: cmd=0x121: 03 db 21 01 00 00 00 00
9439 11:52:32.453076 in-header: 03 07 00 00 2c 00 00 00
9440 11:52:32.466697 in-data: 58 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9441 11:52:32.473241 ELOG: Event(A1) added with size 10 at 2023-11-23 11:52:33 UTC
9442 11:52:32.479714 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9443 11:52:32.486272 ELOG: Event(A0) added with size 9 at 2023-11-23 11:52:33 UTC
9444 11:52:32.490109 elog_add_boot_reason: Logged dev mode boot
9445 11:52:32.493274 BS: BS_POST_DEVICE entry times (exec / console): 3 / 64 ms
9446 11:52:32.496541 Finalize devices...
9447 11:52:32.496638 Devices finalized
9448 11:52:32.503018 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9449 11:52:32.506501 Writing coreboot table at 0xffe64000
9450 11:52:32.509891 0. 000000000010a000-0000000000113fff: RAMSTAGE
9451 11:52:32.513048 1. 0000000040000000-00000000400fffff: RAM
9452 11:52:32.516357 2. 0000000040100000-000000004032afff: RAMSTAGE
9453 11:52:32.523342 3. 000000004032b000-00000000545fffff: RAM
9454 11:52:32.526915 4. 0000000054600000-000000005465ffff: BL31
9455 11:52:32.529956 5. 0000000054660000-00000000ffe63fff: RAM
9456 11:52:32.533612 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9457 11:52:32.540356 7. 0000000100000000-000000023fffffff: RAM
9458 11:52:32.540436 Passing 5 GPIOs to payload:
9459 11:52:32.546608 NAME | PORT | POLARITY | VALUE
9460 11:52:32.550230 EC in RW | 0x000000aa | low | undefined
9461 11:52:32.556326 EC interrupt | 0x00000005 | low | undefined
9462 11:52:32.559956 TPM interrupt | 0x000000ab | high | undefined
9463 11:52:32.563357 SD card detect | 0x00000011 | high | undefined
9464 11:52:32.570268 speaker enable | 0x00000093 | high | undefined
9465 11:52:32.573226 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9466 11:52:32.576961 in-header: 03 f9 00 00 02 00 00 00
9467 11:52:32.577044 in-data: 02 00
9468 11:52:32.580019 ADC[4]: Raw value=900590 ID=7
9469 11:52:32.583532 ADC[3]: Raw value=213336 ID=1
9470 11:52:32.583613 RAM Code: 0x71
9471 11:52:32.587087 ADC[6]: Raw value=74557 ID=0
9472 11:52:32.589934 ADC[5]: Raw value=211860 ID=1
9473 11:52:32.590014 SKU Code: 0x1
9474 11:52:32.596722 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4bd5
9475 11:52:32.599953 coreboot table: 964 bytes.
9476 11:52:32.603346 IMD ROOT 0. 0xfffff000 0x00001000
9477 11:52:32.607290 IMD SMALL 1. 0xffffe000 0x00001000
9478 11:52:32.610088 RO MCACHE 2. 0xffffc000 0x00001104
9479 11:52:32.613606 CONSOLE 3. 0xfff7c000 0x00080000
9480 11:52:32.616948 FMAP 4. 0xfff7b000 0x00000452
9481 11:52:32.619785 TIME STAMP 5. 0xfff7a000 0x00000910
9482 11:52:32.623324 VBOOT WORK 6. 0xfff66000 0x00014000
9483 11:52:32.626781 RAMOOPS 7. 0xffe66000 0x00100000
9484 11:52:32.629870 COREBOOT 8. 0xffe64000 0x00002000
9485 11:52:32.629950 IMD small region:
9486 11:52:32.633310 IMD ROOT 0. 0xffffec00 0x00000400
9487 11:52:32.636729 VPD 1. 0xffffeb80 0x0000006c
9488 11:52:32.640369 MMC STATUS 2. 0xffffeb60 0x00000004
9489 11:52:32.646613 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9490 11:52:32.646726 Probing TPM: done!
9491 11:52:32.653421 Connected to device vid:did:rid of 1ae0:0028:00
9492 11:52:32.660202 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9493 11:52:32.663292 Initialized TPM device CR50 revision 0
9494 11:52:32.667263 Checking cr50 for pending updates
9495 11:52:32.672757 Reading cr50 TPM mode
9496 11:52:32.681532 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9497 11:52:32.688359 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9498 11:52:32.728172 read SPI 0x3990ec 0x4f1b0: 34857 us, 9295 KB/s, 74.360 Mbps
9499 11:52:32.731306 Checking segment from ROM address 0x40100000
9500 11:52:32.734754 Checking segment from ROM address 0x4010001c
9501 11:52:32.741686 Loading segment from ROM address 0x40100000
9502 11:52:32.741766 code (compression=0)
9503 11:52:32.748440 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9504 11:52:32.758049 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9505 11:52:32.758130 it's not compressed!
9506 11:52:32.764851 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9507 11:52:32.768317 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9508 11:52:32.788848 Loading segment from ROM address 0x4010001c
9509 11:52:32.788930 Entry Point 0x80000000
9510 11:52:32.791721 Loaded segments
9511 11:52:32.795396 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9512 11:52:32.798877 Jumping to boot code at 0x80000000(0xffe64000)
9513 11:52:32.808669 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9514 11:52:32.815466 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9515 11:52:32.823164 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9516 11:52:32.826164 Checking segment from ROM address 0x40100000
9517 11:52:32.829421 Checking segment from ROM address 0x4010001c
9518 11:52:32.836077 Loading segment from ROM address 0x40100000
9519 11:52:32.836157 code (compression=1)
9520 11:52:32.843312 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9521 11:52:32.852958 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9522 11:52:32.853039 using LZMA
9523 11:52:32.861478 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9524 11:52:32.868163 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9525 11:52:32.871514 Loading segment from ROM address 0x4010001c
9526 11:52:32.871595 Entry Point 0x54601000
9527 11:52:32.874466 Loaded segments
9528 11:52:32.878002 NOTICE: MT8192 bl31_setup
9529 11:52:32.884649 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9530 11:52:32.888174 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9531 11:52:32.891744 WARNING: region 0:
9532 11:52:32.894645 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9533 11:52:32.894762 WARNING: region 1:
9534 11:52:32.901893 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9535 11:52:32.905098 WARNING: region 2:
9536 11:52:32.908644 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9537 11:52:32.911536 WARNING: region 3:
9538 11:52:32.915118 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9539 11:52:32.918358 WARNING: region 4:
9540 11:52:32.921928 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9541 11:52:32.925214 WARNING: region 5:
9542 11:52:32.928347 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9543 11:52:32.931927 WARNING: region 6:
9544 11:52:32.935207 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9545 11:52:32.935291 WARNING: region 7:
9546 11:52:32.941633 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9547 11:52:32.948372 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9548 11:52:32.951818 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9549 11:52:32.955017 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9550 11:52:32.962043 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9551 11:52:32.965295 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9552 11:52:32.968896 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9553 11:52:32.975481 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9554 11:52:32.978468 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9555 11:52:32.981984 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9556 11:52:32.989044 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9557 11:52:32.991918 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9558 11:52:32.995203 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9559 11:52:33.002112 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9560 11:52:33.005573 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9561 11:52:33.012059 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9562 11:52:33.015573 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9563 11:52:33.018774 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9564 11:52:33.025391 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9565 11:52:33.028716 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9566 11:52:33.032260 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9567 11:52:33.038827 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9568 11:52:33.042413 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9569 11:52:33.049045 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9570 11:52:33.052295 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9571 11:52:33.056139 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9572 11:52:33.062426 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9573 11:52:33.065901 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9574 11:52:33.069210 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9575 11:52:33.076187 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9576 11:52:33.079506 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9577 11:52:33.085757 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9578 11:52:33.089286 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9579 11:52:33.092584 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9580 11:52:33.096086 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9581 11:52:33.102773 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9582 11:52:33.106428 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9583 11:52:33.109857 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9584 11:52:33.113031 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9585 11:52:33.120456 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9586 11:52:33.122868 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9587 11:52:33.126560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9588 11:52:33.129538 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9589 11:52:33.133096 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9590 11:52:33.139826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9591 11:52:33.143463 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9592 11:52:33.146558 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9593 11:52:33.149831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9594 11:52:33.156737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9595 11:52:33.160323 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9596 11:52:33.166741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9597 11:52:33.170122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9598 11:52:33.173579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9599 11:52:33.180180 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9600 11:52:33.183527 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9601 11:52:33.190387 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9602 11:52:33.193761 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9603 11:52:33.197135 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9604 11:52:33.203941 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9605 11:52:33.207250 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9606 11:52:33.213520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9607 11:52:33.217115 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9608 11:52:33.223585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9609 11:52:33.227437 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9610 11:52:33.233613 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9611 11:52:33.237350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9612 11:52:33.240563 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9613 11:52:33.246997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9614 11:52:33.250719 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9615 11:52:33.257086 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9616 11:52:33.260573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9617 11:52:33.263743 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9618 11:52:33.270959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9619 11:52:33.274004 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9620 11:52:33.280585 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9621 11:52:33.284123 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9622 11:52:33.290706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9623 11:52:33.294082 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9624 11:52:33.297502 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9625 11:52:33.304592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9626 11:52:33.307233 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9627 11:52:33.314204 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9628 11:52:33.317893 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9629 11:52:33.324138 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9630 11:52:33.327510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9631 11:52:33.331094 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9632 11:52:33.337962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9633 11:52:33.341238 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9634 11:52:33.347587 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9635 11:52:33.351321 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9636 11:52:33.354422 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9637 11:52:33.361210 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9638 11:52:33.364697 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9639 11:52:33.370907 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9640 11:52:33.374769 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9641 11:52:33.381715 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9642 11:52:33.385212 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9643 11:52:33.388126 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9644 11:52:33.391634 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9645 11:52:33.398406 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9646 11:52:33.401973 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9647 11:52:33.404659 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9648 11:52:33.411616 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9649 11:52:33.414901 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9650 11:52:33.418556 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9651 11:52:33.425171 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9652 11:52:33.428787 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9653 11:52:33.435268 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9654 11:52:33.438503 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9655 11:52:33.442109 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9656 11:52:33.448824 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9657 11:52:33.452045 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9658 11:52:33.455108 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9659 11:52:33.462346 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9660 11:52:33.465479 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9661 11:52:33.472052 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9662 11:52:33.475463 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9663 11:52:33.478756 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9664 11:52:33.485540 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9665 11:52:33.489015 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9666 11:52:33.492486 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9667 11:52:33.495345 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9668 11:52:33.502046 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9669 11:52:33.505374 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9670 11:52:33.509097 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9671 11:52:33.512267 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9672 11:52:33.519193 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9673 11:52:33.522592 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9674 11:52:33.529829 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9675 11:52:33.532628 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9676 11:52:33.535961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9677 11:52:33.542446 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9678 11:52:33.546007 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9679 11:52:33.549697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9680 11:52:33.556189 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9681 11:52:33.559341 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9682 11:52:33.566185 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9683 11:52:33.569472 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9684 11:52:33.572738 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9685 11:52:33.579698 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9686 11:52:33.583246 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9687 11:52:33.586211 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9688 11:52:33.593093 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9689 11:52:33.596318 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9690 11:52:33.603029 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9691 11:52:33.606193 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9692 11:52:33.609880 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9693 11:52:33.616404 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9694 11:52:33.619940 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9695 11:52:33.623390 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9696 11:52:33.630202 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9697 11:52:33.633208 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9698 11:52:33.636585 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9699 11:52:33.643621 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9700 11:52:33.646715 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9701 11:52:33.653492 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9702 11:52:33.657000 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9703 11:52:33.660429 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9704 11:52:33.667249 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9705 11:52:33.670153 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9706 11:52:33.673392 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9707 11:52:33.680210 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9708 11:52:33.683600 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9709 11:52:33.690242 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9710 11:52:33.693292 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9711 11:52:33.696969 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9712 11:52:33.703672 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9713 11:52:33.706670 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9714 11:52:33.713593 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9715 11:52:33.716865 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9716 11:52:33.720240 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9717 11:52:33.727069 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9718 11:52:33.730258 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9719 11:52:33.733403 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9720 11:52:33.740391 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9721 11:52:33.743844 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9722 11:52:33.750155 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9723 11:52:33.753864 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9724 11:52:33.757362 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9725 11:52:33.763719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9726 11:52:33.767137 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9727 11:52:33.773535 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9728 11:52:33.776805 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9729 11:52:33.780430 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9730 11:52:33.787045 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9731 11:52:33.790454 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9732 11:52:33.797264 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9733 11:52:33.800536 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9734 11:52:33.803893 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9735 11:52:33.810316 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9736 11:52:33.813805 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9737 11:52:33.820511 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9738 11:52:33.823878 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9739 11:52:33.827402 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9740 11:52:33.833782 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9741 11:52:33.837178 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9742 11:52:33.843751 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9743 11:52:33.847693 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9744 11:52:33.850535 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9745 11:52:33.856817 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9746 11:52:33.860601 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9747 11:52:33.867176 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9748 11:52:33.870372 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9749 11:52:33.873647 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9750 11:52:33.880653 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9751 11:52:33.883585 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9752 11:52:33.890247 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9753 11:52:33.894017 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9754 11:52:33.897069 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9755 11:52:33.904321 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9756 11:52:33.907046 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9757 11:52:33.913796 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9758 11:52:33.917049 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9759 11:52:33.923909 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9760 11:52:33.927460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9761 11:52:33.930900 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9762 11:52:33.937290 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9763 11:52:33.940448 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9764 11:52:33.947132 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9765 11:52:33.950484 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9766 11:52:33.953920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9767 11:52:33.960402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9768 11:52:33.963756 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9769 11:52:33.970733 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9770 11:52:33.973878 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9771 11:52:33.977042 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9772 11:52:33.983999 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9773 11:52:33.987522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9774 11:52:33.993813 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9775 11:52:33.997500 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9776 11:52:34.000576 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9777 11:52:34.003928 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9778 11:52:34.010777 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9779 11:52:34.014199 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9780 11:52:34.017750 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9781 11:52:34.020959 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9782 11:52:34.027668 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9783 11:52:34.030753 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9784 11:52:34.037610 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9785 11:52:34.040879 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9786 11:52:34.044287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9787 11:52:34.050904 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9788 11:52:34.054252 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9789 11:52:34.057605 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9790 11:52:34.064162 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9791 11:52:34.067287 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9792 11:52:34.071236 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9793 11:52:34.077871 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9794 11:52:34.081016 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9795 11:52:34.084321 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9796 11:52:34.090933 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9797 11:52:34.094394 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9798 11:52:34.100727 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9799 11:52:34.104257 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9800 11:52:34.107697 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9801 11:52:34.114319 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9802 11:52:34.117903 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9803 11:52:34.121006 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9804 11:52:34.127680 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9805 11:52:34.130901 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9806 11:52:34.134636 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9807 11:52:34.140807 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9808 11:52:34.144501 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9809 11:52:34.150655 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9810 11:52:34.154507 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9811 11:52:34.157343 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9812 11:52:34.164226 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9813 11:52:34.167607 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9814 11:52:34.170808 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9815 11:52:34.178057 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9816 11:52:34.180727 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9817 11:52:34.184476 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9818 11:52:34.187825 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9819 11:52:34.191020 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9820 11:52:34.197723 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9821 11:52:34.201396 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9822 11:52:34.204364 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9823 11:52:34.207709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9824 11:52:34.214534 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9825 11:52:34.218307 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9826 11:52:34.221178 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9827 11:52:34.224616 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9828 11:52:34.230994 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9829 11:52:34.234820 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9830 11:52:34.241263 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9831 11:52:34.244654 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9832 11:52:34.247822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9833 11:52:34.254798 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9834 11:52:34.258429 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9835 11:52:34.264944 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9836 11:52:34.268236 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9837 11:52:34.271838 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9838 11:52:34.278405 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9839 11:52:34.282085 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9840 11:52:34.288126 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9841 11:52:34.291567 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9842 11:52:34.295206 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9843 11:52:34.302108 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9844 11:52:34.304958 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9845 11:52:34.311526 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9846 11:52:34.314973 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9847 11:52:34.318467 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9848 11:52:34.325002 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9849 11:52:34.328616 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9850 11:52:34.335266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9851 11:52:34.338099 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9852 11:52:34.341458 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9853 11:52:34.348185 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9854 11:52:34.352099 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9855 11:52:34.358108 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9856 11:52:34.362113 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9857 11:52:34.365428 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9858 11:52:34.371523 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9859 11:52:34.375727 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9860 11:52:34.378362 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9861 11:52:34.385667 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9862 11:52:34.388948 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9863 11:52:34.395439 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9864 11:52:34.398430 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9865 11:52:34.405245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9866 11:52:34.408703 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9867 11:52:34.412117 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9868 11:52:34.418944 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9869 11:52:34.422252 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9870 11:52:34.425578 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9871 11:52:34.432249 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9872 11:52:34.435557 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9873 11:52:34.442257 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9874 11:52:34.446017 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9875 11:52:34.452352 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9876 11:52:34.455501 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9877 11:52:34.459092 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9878 11:52:34.465498 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9879 11:52:34.468475 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9880 11:52:34.472025 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9881 11:52:34.478559 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9882 11:52:34.481958 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9883 11:52:34.489039 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9884 11:52:34.491958 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9885 11:52:34.495433 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9886 11:52:34.502349 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9887 11:52:34.505340 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9888 11:52:34.512261 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9889 11:52:34.515336 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9890 11:52:34.522311 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9891 11:52:34.525797 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9892 11:52:34.528582 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9893 11:52:34.535575 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9894 11:52:34.539026 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9895 11:52:34.541969 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9896 11:52:34.548661 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9897 11:52:34.552205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9898 11:52:34.559283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9899 11:52:34.562408 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9900 11:52:34.565992 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9901 11:52:34.572482 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9902 11:52:34.575542 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9903 11:52:34.582144 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9904 11:52:34.585557 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9905 11:52:34.592589 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9906 11:52:34.595548 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9907 11:52:34.602263 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9908 11:52:34.605696 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9909 11:52:34.608784 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9910 11:52:34.615615 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9911 11:52:34.619205 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9912 11:52:34.625991 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9913 11:52:34.628923 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9914 11:52:34.632297 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9915 11:52:34.638945 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9916 11:52:34.642828 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9917 11:52:34.649538 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9918 11:52:34.652306 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9919 11:52:34.659169 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9920 11:52:34.663018 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9921 11:52:34.665628 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9922 11:52:34.672588 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9923 11:52:34.676092 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9924 11:52:34.682254 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9925 11:52:34.685974 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9926 11:52:34.692666 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9927 11:52:34.695773 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9928 11:52:34.699091 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9929 11:52:34.706007 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9930 11:52:34.708937 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9931 11:52:34.715793 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9932 11:52:34.719216 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9933 11:52:34.725869 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9934 11:52:34.729048 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9935 11:52:34.732381 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9936 11:52:34.738984 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9937 11:52:34.742801 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9938 11:52:34.749161 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9939 11:52:34.752429 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9940 11:52:34.755686 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9941 11:52:34.762421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9942 11:52:34.765757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9943 11:52:34.772421 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9944 11:52:34.775806 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9945 11:52:34.783132 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9946 11:52:34.785692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9947 11:52:34.792418 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9948 11:52:34.795985 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9949 11:52:34.799520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9950 11:52:34.806193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9951 11:52:34.809375 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9952 11:52:34.815771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9953 11:52:34.819241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9954 11:52:34.825611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9955 11:52:34.829100 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9956 11:52:34.832528 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9957 11:52:34.839368 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9958 11:52:34.842830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9959 11:52:34.849007 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9960 11:52:34.852616 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9961 11:52:34.859163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9962 11:52:34.862778 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9963 11:52:34.869069 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9964 11:52:34.872739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9965 11:52:34.879644 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9966 11:52:34.883310 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9967 11:52:34.889356 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9968 11:52:34.892638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9969 11:52:34.899416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9970 11:52:34.902717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9971 11:52:34.909739 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9972 11:52:34.912987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9973 11:52:34.919846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9974 11:52:34.922831 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9975 11:52:34.929473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9976 11:52:34.933181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9977 11:52:34.939560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9978 11:52:34.942817 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9979 11:52:34.949338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9980 11:52:34.953361 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9981 11:52:34.956056 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9982 11:52:34.959589 INFO: [APUAPC] vio 0
9983 11:52:34.962984 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9984 11:52:34.969739 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9985 11:52:34.973209 INFO: [APUAPC] D0_APC_0: 0x400510
9986 11:52:34.976251 INFO: [APUAPC] D0_APC_1: 0x0
9987 11:52:34.979557 INFO: [APUAPC] D0_APC_2: 0x1540
9988 11:52:34.979970 INFO: [APUAPC] D0_APC_3: 0x0
9989 11:52:34.983060 INFO: [APUAPC] D1_APC_0: 0xffffffff
9990 11:52:34.986476 INFO: [APUAPC] D1_APC_1: 0xffffffff
9991 11:52:34.989830 INFO: [APUAPC] D1_APC_2: 0x3fffff
9992 11:52:34.992647 INFO: [APUAPC] D1_APC_3: 0x0
9993 11:52:34.996059 INFO: [APUAPC] D2_APC_0: 0xffffffff
9994 11:52:34.999925 INFO: [APUAPC] D2_APC_1: 0xffffffff
9995 11:52:35.002775 INFO: [APUAPC] D2_APC_2: 0x3fffff
9996 11:52:35.006056 INFO: [APUAPC] D2_APC_3: 0x0
9997 11:52:35.009771 INFO: [APUAPC] D3_APC_0: 0xffffffff
9998 11:52:35.013373 INFO: [APUAPC] D3_APC_1: 0xffffffff
9999 11:52:35.016156 INFO: [APUAPC] D3_APC_2: 0x3fffff
10000 11:52:35.019394 INFO: [APUAPC] D3_APC_3: 0x0
10001 11:52:35.022847 INFO: [APUAPC] D4_APC_0: 0xffffffff
10002 11:52:35.026374 INFO: [APUAPC] D4_APC_1: 0xffffffff
10003 11:52:35.029484 INFO: [APUAPC] D4_APC_2: 0x3fffff
10004 11:52:35.032645 INFO: [APUAPC] D4_APC_3: 0x0
10005 11:52:35.035781 INFO: [APUAPC] D5_APC_0: 0xffffffff
10006 11:52:35.039589 INFO: [APUAPC] D5_APC_1: 0xffffffff
10007 11:52:35.042782 INFO: [APUAPC] D5_APC_2: 0x3fffff
10008 11:52:35.046481 INFO: [APUAPC] D5_APC_3: 0x0
10009 11:52:35.049732 INFO: [APUAPC] D6_APC_0: 0xffffffff
10010 11:52:35.053023 INFO: [APUAPC] D6_APC_1: 0xffffffff
10011 11:52:35.056128 INFO: [APUAPC] D6_APC_2: 0x3fffff
10012 11:52:35.059378 INFO: [APUAPC] D6_APC_3: 0x0
10013 11:52:35.063044 INFO: [APUAPC] D7_APC_0: 0xffffffff
10014 11:52:35.066259 INFO: [APUAPC] D7_APC_1: 0xffffffff
10015 11:52:35.070060 INFO: [APUAPC] D7_APC_2: 0x3fffff
10016 11:52:35.073172 INFO: [APUAPC] D7_APC_3: 0x0
10017 11:52:35.076242 INFO: [APUAPC] D8_APC_0: 0xffffffff
10018 11:52:35.079738 INFO: [APUAPC] D8_APC_1: 0xffffffff
10019 11:52:35.083043 INFO: [APUAPC] D8_APC_2: 0x3fffff
10020 11:52:35.086340 INFO: [APUAPC] D8_APC_3: 0x0
10021 11:52:35.089798 INFO: [APUAPC] D9_APC_0: 0xffffffff
10022 11:52:35.093125 INFO: [APUAPC] D9_APC_1: 0xffffffff
10023 11:52:35.096680 INFO: [APUAPC] D9_APC_2: 0x3fffff
10024 11:52:35.097098 INFO: [APUAPC] D9_APC_3: 0x0
10025 11:52:35.102803 INFO: [APUAPC] D10_APC_0: 0xffffffff
10026 11:52:35.106276 INFO: [APUAPC] D10_APC_1: 0xffffffff
10027 11:52:35.109575 INFO: [APUAPC] D10_APC_2: 0x3fffff
10028 11:52:35.109992 INFO: [APUAPC] D10_APC_3: 0x0
10029 11:52:35.116662 INFO: [APUAPC] D11_APC_0: 0xffffffff
10030 11:52:35.119561 INFO: [APUAPC] D11_APC_1: 0xffffffff
10031 11:52:35.123000 INFO: [APUAPC] D11_APC_2: 0x3fffff
10032 11:52:35.126291 INFO: [APUAPC] D11_APC_3: 0x0
10033 11:52:35.129605 INFO: [APUAPC] D12_APC_0: 0xffffffff
10034 11:52:35.133027 INFO: [APUAPC] D12_APC_1: 0xffffffff
10035 11:52:35.136257 INFO: [APUAPC] D12_APC_2: 0x3fffff
10036 11:52:35.140050 INFO: [APUAPC] D12_APC_3: 0x0
10037 11:52:35.143132 INFO: [APUAPC] D13_APC_0: 0xffffffff
10038 11:52:35.146777 INFO: [APUAPC] D13_APC_1: 0xffffffff
10039 11:52:35.150066 INFO: [APUAPC] D13_APC_2: 0x3fffff
10040 11:52:35.150483 INFO: [APUAPC] D13_APC_3: 0x0
10041 11:52:35.156594 INFO: [APUAPC] D14_APC_0: 0xffffffff
10042 11:52:35.160092 INFO: [APUAPC] D14_APC_1: 0xffffffff
10043 11:52:35.163381 INFO: [APUAPC] D14_APC_2: 0x3fffff
10044 11:52:35.166538 INFO: [APUAPC] D14_APC_3: 0x0
10045 11:52:35.170120 INFO: [APUAPC] D15_APC_0: 0xffffffff
10046 11:52:35.172842 INFO: [APUAPC] D15_APC_1: 0xffffffff
10047 11:52:35.176525 INFO: [APUAPC] D15_APC_2: 0x3fffff
10048 11:52:35.180031 INFO: [APUAPC] D15_APC_3: 0x0
10049 11:52:35.180444 INFO: [APUAPC] APC_CON: 0x4
10050 11:52:35.183424 INFO: [NOCDAPC] D0_APC_0: 0x0
10051 11:52:35.186342 INFO: [NOCDAPC] D0_APC_1: 0x0
10052 11:52:35.189909 INFO: [NOCDAPC] D1_APC_0: 0x0
10053 11:52:35.192783 INFO: [NOCDAPC] D1_APC_1: 0xfff
10054 11:52:35.196591 INFO: [NOCDAPC] D2_APC_0: 0x0
10055 11:52:35.199460 INFO: [NOCDAPC] D2_APC_1: 0xfff
10056 11:52:35.203261 INFO: [NOCDAPC] D3_APC_0: 0x0
10057 11:52:35.206432 INFO: [NOCDAPC] D3_APC_1: 0xfff
10058 11:52:35.206847 INFO: [NOCDAPC] D4_APC_0: 0x0
10059 11:52:35.209771 INFO: [NOCDAPC] D4_APC_1: 0xfff
10060 11:52:35.213395 INFO: [NOCDAPC] D5_APC_0: 0x0
10061 11:52:35.216568 INFO: [NOCDAPC] D5_APC_1: 0xfff
10062 11:52:35.219741 INFO: [NOCDAPC] D6_APC_0: 0x0
10063 11:52:35.222850 INFO: [NOCDAPC] D6_APC_1: 0xfff
10064 11:52:35.226381 INFO: [NOCDAPC] D7_APC_0: 0x0
10065 11:52:35.229610 INFO: [NOCDAPC] D7_APC_1: 0xfff
10066 11:52:35.233140 INFO: [NOCDAPC] D8_APC_0: 0x0
10067 11:52:35.236564 INFO: [NOCDAPC] D8_APC_1: 0xfff
10068 11:52:35.236982 INFO: [NOCDAPC] D9_APC_0: 0x0
10069 11:52:35.240163 INFO: [NOCDAPC] D9_APC_1: 0xfff
10070 11:52:35.243297 INFO: [NOCDAPC] D10_APC_0: 0x0
10071 11:52:35.246338 INFO: [NOCDAPC] D10_APC_1: 0xfff
10072 11:52:35.249880 INFO: [NOCDAPC] D11_APC_0: 0x0
10073 11:52:35.252972 INFO: [NOCDAPC] D11_APC_1: 0xfff
10074 11:52:35.256883 INFO: [NOCDAPC] D12_APC_0: 0x0
10075 11:52:35.259570 INFO: [NOCDAPC] D12_APC_1: 0xfff
10076 11:52:35.263269 INFO: [NOCDAPC] D13_APC_0: 0x0
10077 11:52:35.266616 INFO: [NOCDAPC] D13_APC_1: 0xfff
10078 11:52:35.269528 INFO: [NOCDAPC] D14_APC_0: 0x0
10079 11:52:35.273431 INFO: [NOCDAPC] D14_APC_1: 0xfff
10080 11:52:35.276459 INFO: [NOCDAPC] D15_APC_0: 0x0
10081 11:52:35.279701 INFO: [NOCDAPC] D15_APC_1: 0xfff
10082 11:52:35.280112 INFO: [NOCDAPC] APC_CON: 0x4
10083 11:52:35.283059 INFO: [APUAPC] set_apusys_apc done
10084 11:52:35.286605 INFO: [DEVAPC] devapc_init done
10085 11:52:35.292729 INFO: GICv3 without legacy support detected.
10086 11:52:35.296234 INFO: ARM GICv3 driver initialized in EL3
10087 11:52:35.299953 INFO: Maximum SPI INTID supported: 639
10088 11:52:35.303057 INFO: BL31: Initializing runtime services
10089 11:52:35.309839 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10090 11:52:35.313396 INFO: SPM: enable CPC mode
10091 11:52:35.316191 INFO: mcdi ready for mcusys-off-idle and system suspend
10092 11:52:35.322979 INFO: BL31: Preparing for EL3 exit to normal world
10093 11:52:35.326186 INFO: Entry point address = 0x80000000
10094 11:52:35.326634 INFO: SPSR = 0x8
10095 11:52:35.333314
10096 11:52:35.333721
10097 11:52:35.334040
10098 11:52:35.336817 Starting depthcharge on Spherion...
10099 11:52:35.337228
10100 11:52:35.337557 Wipe memory regions:
10101 11:52:35.337860
10102 11:52:35.340332 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10103 11:52:35.340812 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10104 11:52:35.341200 Setting prompt string to ['asurada:']
10105 11:52:35.341594 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10106 11:52:35.342238 [0x00000040000000, 0x00000054600000)
10107 11:52:35.462445
10108 11:52:35.462941 [0x00000054660000, 0x00000080000000)
10109 11:52:35.722575
10110 11:52:35.723099 [0x000000821a7280, 0x000000ffe64000)
10111 11:52:36.467246
10112 11:52:36.467379 [0x00000100000000, 0x00000240000000)
10113 11:52:38.358225
10114 11:52:38.361441 Initializing XHCI USB controller at 0x11200000.
10115 11:52:39.400378
10116 11:52:39.403108 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10117 11:52:39.403190
10118 11:52:39.403260
10119 11:52:39.403320
10120 11:52:39.403599 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10122 11:52:39.503955 asurada: tftpboot 192.168.201.1 12066512/tftp-deploy-1a1n6lk2/kernel/image.itb 12066512/tftp-deploy-1a1n6lk2/kernel/cmdline
10123 11:52:39.504103 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10124 11:52:39.504183 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10125 11:52:39.508310 tftpboot 192.168.201.1 12066512/tftp-deploy-1a1n6lk2/kernel/image.itp-deploy-1a1n6lk2/kernel/cmdline
10126 11:52:39.508393
10127 11:52:39.508457 Waiting for link
10128 11:52:39.668904
10129 11:52:39.669033 R8152: Initializing
10130 11:52:39.669099
10131 11:52:39.672062 Version 6 (ocp_data = 5c30)
10132 11:52:39.672143
10133 11:52:39.675522 R8152: Done initializing
10134 11:52:39.675602
10135 11:52:39.675666 Adding net device
10136 11:52:41.641482
10137 11:52:41.641965 done.
10138 11:52:41.642293
10139 11:52:41.642597 MAC: 00:24:32:30:78:52
10140 11:52:41.642933
10141 11:52:41.644756 Sending DHCP discover... done.
10142 11:52:41.645193
10143 11:52:46.416870 Waiting for reply... done.
10144 11:52:46.417365
10145 11:52:46.417693 Sending DHCP request... done.
10146 11:52:46.420213
10147 11:52:46.423877 Waiting for reply... done.
10148 11:52:46.424290
10149 11:52:46.424615 My ip is 192.168.201.14
10150 11:52:46.424915
10151 11:52:46.426987 The DHCP server ip is 192.168.201.1
10152 11:52:46.427403
10153 11:52:46.433622 TFTP server IP predefined by user: 192.168.201.1
10154 11:52:46.434036
10155 11:52:46.440493 Bootfile predefined by user: 12066512/tftp-deploy-1a1n6lk2/kernel/image.itb
10156 11:52:46.441118
10157 11:52:46.441650 Sending tftp read request... done.
10158 11:52:46.443907
10159 11:52:46.450830 Waiting for the transfer...
10160 11:52:46.451383
10161 11:52:47.091210 00000000 ################################################################
10162 11:52:47.091343
10163 11:52:47.736176 00080000 ################################################################
10164 11:52:47.736734
10165 11:52:48.445137 00100000 ################################################################
10166 11:52:48.445646
10167 11:52:49.177558 00180000 ################################################################
10168 11:52:49.178211
10169 11:52:49.888742 00200000 ################################################################
10170 11:52:49.889245
10171 11:52:50.593360 00280000 ################################################################
10172 11:52:50.593871
10173 11:52:51.304755 00300000 ################################################################
10174 11:52:51.305323
10175 11:52:52.010611 00380000 ################################################################
10176 11:52:52.011332
10177 11:52:52.721038 00400000 ################################################################
10178 11:52:52.721578
10179 11:52:53.394796 00480000 ################################################################
10180 11:52:53.394964
10181 11:52:54.037472 00500000 ################################################################
10182 11:52:54.037638
10183 11:52:54.606430 00580000 ################################################################
10184 11:52:54.606590
10185 11:52:55.215996 00600000 ################################################################
10186 11:52:55.216483
10187 11:52:55.867097 00680000 ################################################################
10188 11:52:55.867602
10189 11:52:56.454725 00700000 ################################################################
10190 11:52:56.454867
10191 11:52:57.092195 00780000 ################################################################
10192 11:52:57.092692
10193 11:52:57.755834 00800000 ################################################################
10194 11:52:57.756402
10195 11:52:58.460574 00880000 ################################################################
10196 11:52:58.460710
10197 11:52:59.122462 00900000 ################################################################
10198 11:52:59.122599
10199 11:52:59.754943 00980000 ################################################################
10200 11:52:59.755449
10201 11:53:00.326359 00a00000 ################################################################
10202 11:53:00.326525
10203 11:53:00.902711 00a80000 ################################################################
10204 11:53:00.902921
10205 11:53:01.519879 00b00000 ################################################################
10206 11:53:01.520557
10207 11:53:02.116456 00b80000 ################################################################
10208 11:53:02.116596
10209 11:53:02.683585 00c00000 ################################################################
10210 11:53:02.683716
10211 11:53:03.257607 00c80000 ################################################################
10212 11:53:03.257776
10213 11:53:03.921882 00d00000 ################################################################
10214 11:53:03.922387
10215 11:53:04.550726 00d80000 ################################################################
10216 11:53:04.550889
10217 11:53:05.199687 00e00000 ################################################################
10218 11:53:05.199830
10219 11:53:05.890092 00e80000 ################################################################
10220 11:53:05.890636
10221 11:53:06.515084 00f00000 ################################################################
10222 11:53:06.515218
10223 11:53:07.173038 00f80000 ################################################################
10224 11:53:07.173185
10225 11:53:07.781176 01000000 ################################################################
10226 11:53:07.781389
10227 11:53:08.397375 01080000 ################################################################
10228 11:53:08.397540
10229 11:53:08.991191 01100000 ################################################################
10230 11:53:08.991322
10231 11:53:09.592167 01180000 ################################################################
10232 11:53:09.592331
10233 11:53:10.153908 01200000 ################################################################
10234 11:53:10.154068
10235 11:53:10.794677 01280000 ################################################################
10236 11:53:10.794840
10237 11:53:11.492940 01300000 ################################################################
10238 11:53:11.493084
10239 11:53:12.161473 01380000 ################################################################
10240 11:53:12.161650
10241 11:53:12.764622 01400000 ################################################################
10242 11:53:12.764783
10243 11:53:13.402829 01480000 ################################################################
10244 11:53:13.403011
10245 11:53:13.976334 01500000 ################################################################
10246 11:53:13.976488
10247 11:53:14.542240 01580000 ################################################################
10248 11:53:14.542376
10249 11:53:15.114258 01600000 ################################################################
10250 11:53:15.114414
10251 11:53:15.749934 01680000 ################################################################
10252 11:53:15.750485
10253 11:53:16.370487 01700000 ################################################################
10254 11:53:16.370629
10255 11:53:16.960477 01780000 ################################################################
10256 11:53:16.960627
10257 11:53:17.560780 01800000 ################################################################
10258 11:53:17.560922
10259 11:53:18.148156 01880000 ################################################################
10260 11:53:18.148303
10261 11:53:18.728762 01900000 ################################################################
10262 11:53:18.728921
10263 11:53:19.309978 01980000 ################################################################
10264 11:53:19.310136
10265 11:53:19.886691 01a00000 ################################################################
10266 11:53:19.886828
10267 11:53:20.466465 01a80000 ################################################################
10268 11:53:20.466614
10269 11:53:21.064172 01b00000 ################################################################
10270 11:53:21.064318
10271 11:53:21.126249 01b80000 ####### done.
10272 11:53:21.126391
10273 11:53:21.129365 The bootfile was 28889798 bytes long.
10274 11:53:21.129449
10275 11:53:21.132924 Sending tftp read request... done.
10276 11:53:21.133006
10277 11:53:21.133077 Waiting for the transfer...
10278 11:53:21.133138
10279 11:53:21.135991 00000000 # done.
10280 11:53:21.136074
10281 11:53:21.142600 Command line loaded dynamically from TFTP file: 12066512/tftp-deploy-1a1n6lk2/kernel/cmdline
10282 11:53:21.142689
10283 11:53:21.166159 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10284 11:53:21.166297
10285 11:53:21.166364 Loading FIT.
10286 11:53:21.166424
10287 11:53:21.169448 Image ramdisk-1 has 17793302 bytes.
10288 11:53:21.169529
10289 11:53:21.172633 Image fdt-1 has 47278 bytes.
10290 11:53:21.172738
10291 11:53:21.176696 Image kernel-1 has 11047184 bytes.
10292 11:53:21.176784
10293 11:53:21.185991 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10294 11:53:21.186082
10295 11:53:21.202847 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10296 11:53:21.203006
10297 11:53:21.206069 Choosing best match conf-1 for compat google,spherion-rev2.
10298 11:53:21.211409
10299 11:53:21.216397 Connected to device vid:did:rid of 1ae0:0028:00
10300 11:53:21.222814
10301 11:53:21.226235 tpm_get_response: command 0x17b, return code 0x0
10302 11:53:21.226322
10303 11:53:21.229984 ec_init: CrosEC protocol v3 supported (256, 248)
10304 11:53:21.233530
10305 11:53:21.236943 tpm_cleanup: add release locality here.
10306 11:53:21.237026
10307 11:53:21.237091 Shutting down all USB controllers.
10308 11:53:21.240598
10309 11:53:21.240681 Removing current net device
10310 11:53:21.240745
10311 11:53:21.247133 Exiting depthcharge with code 4 at timestamp: 75267294
10312 11:53:21.247215
10313 11:53:21.250408 LZMA decompressing kernel-1 to 0x821a6718
10314 11:53:21.250490
10315 11:53:21.253917 LZMA decompressing kernel-1 to 0x40000000
10316 11:53:22.642084
10317 11:53:22.642236 jumping to kernel
10318 11:53:22.642685 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10319 11:53:22.642781 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10320 11:53:22.642855 Setting prompt string to ['Linux version [0-9]']
10321 11:53:22.642932 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10322 11:53:22.642999 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10323 11:53:22.723741
10324 11:53:22.726973 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10325 11:53:22.730566 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10326 11:53:22.730655 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10327 11:53:22.730723 Setting prompt string to []
10328 11:53:22.730798 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 11:53:22.730891 Using line separator: #'\n'#
10330 11:53:22.730963 No login prompt set.
10331 11:53:22.731023 Parsing kernel messages
10332 11:53:22.731075 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 11:53:22.731172 [login-action] Waiting for messages, (timeout 00:03:38)
10334 11:53:22.750821 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10335 11:53:22.753815 [ 0.000000] random: crng init done
10336 11:53:22.757537 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 11:53:22.760424 [ 0.000000] efi: UEFI not found.
10338 11:53:22.771334 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 11:53:22.777364 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 11:53:22.787225 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 11:53:22.797255 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 11:53:22.804037 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 11:53:22.807301 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 11:53:22.815521 [ 0.000000] NUMA: No NUMA configuration found
10345 11:53:22.822442 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 11:53:22.828614 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10347 11:53:22.828700 [ 0.000000] Zone ranges:
10348 11:53:22.835778 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 11:53:22.838586 [ 0.000000] DMA32 empty
10350 11:53:22.845313 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 11:53:22.848952 [ 0.000000] Movable zone start for each node
10352 11:53:22.852002 [ 0.000000] Early memory node ranges
10353 11:53:22.859074 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 11:53:22.865255 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 11:53:22.872300 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 11:53:22.878923 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 11:53:22.885238 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 11:53:22.892021 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 11:53:22.948109 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 11:53:22.955107 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 11:53:22.961578 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 11:53:22.964633 [ 0.000000] psci: probing for conduit method from DT.
10363 11:53:22.971512 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 11:53:22.974808 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 11:53:22.981493 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 11:53:22.984651 [ 0.000000] psci: SMC Calling Convention v1.2
10367 11:53:22.991446 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10368 11:53:22.994478 [ 0.000000] Detected VIPT I-cache on CPU0
10369 11:53:23.001313 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 11:53:23.008171 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 11:53:23.014998 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 11:53:23.021170 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 11:53:23.027910 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 11:53:23.034402 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 11:53:23.041293 [ 0.000000] alternatives: applying boot alternatives
10376 11:53:23.044337 [ 0.000000] Fallback order for Node 0: 0
10377 11:53:23.051262 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 11:53:23.054376 [ 0.000000] Policy zone: Normal
10379 11:53:23.078220 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10380 11:53:23.090845 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 11:53:23.101016 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 11:53:23.111263 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 11:53:23.118012 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 11:53:23.121120 <6>[ 0.000000] software IO TLB: area num 8.
10385 11:53:23.177463 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 11:53:23.326498 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10387 11:53:23.333521 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 11:53:23.340067 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 11:53:23.343748 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 11:53:23.350064 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 11:53:23.356781 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 11:53:23.360098 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 11:53:23.370311 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 11:53:23.377002 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 11:53:23.380143 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 11:53:23.387617 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 11:53:23.391343 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 11:53:23.397668 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 11:53:23.401113 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 11:53:23.404268 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 11:53:23.414894 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 11:53:23.424533 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 11:53:23.437810 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 11:53:23.444109 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 11:53:23.453175 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 11:53:23.466780 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 11:53:23.473227 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 11:53:23.479925 <6>[ 0.009176] Console: colour dummy device 80x25
10409 11:53:23.489997 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 11:53:23.493143 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10411 11:53:23.499819 <6>[ 0.029217] LSM: Security Framework initializing
10412 11:53:23.506857 <6>[ 0.034155] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 11:53:23.516781 <6>[ 0.041969] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 11:53:23.523063 <6>[ 0.051377] cblist_init_generic: Setting adjustable number of callback queues.
10415 11:53:23.530176 <6>[ 0.058820] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 11:53:23.536569 <6>[ 0.065167] cblist_init_generic: Setting adjustable number of callback queues.
10417 11:53:23.543123 <6>[ 0.072639] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 11:53:23.549878 <6>[ 0.079038] rcu: Hierarchical SRCU implementation.
10419 11:53:23.554235 <6>[ 0.084083] rcu: Max phase no-delay instances is 1000.
10420 11:53:23.561786 <6>[ 0.091104] EFI services will not be available.
10421 11:53:23.565364 <6>[ 0.096057] smp: Bringing up secondary CPUs ...
10422 11:53:23.574468 <6>[ 0.101100] Detected VIPT I-cache on CPU1
10423 11:53:23.580815 <6>[ 0.101169] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 11:53:23.587633 <6>[ 0.101201] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 11:53:23.590967 <6>[ 0.101540] Detected VIPT I-cache on CPU2
10426 11:53:23.597487 <6>[ 0.101594] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 11:53:23.604040 <6>[ 0.101610] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 11:53:23.610804 <6>[ 0.101872] Detected VIPT I-cache on CPU3
10429 11:53:23.617579 <6>[ 0.101917] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 11:53:23.624342 <6>[ 0.101931] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 11:53:23.627603 <6>[ 0.102233] CPU features: detected: Spectre-v4
10432 11:53:23.634489 <6>[ 0.102240] CPU features: detected: Spectre-BHB
10433 11:53:23.638083 <6>[ 0.102244] Detected PIPT I-cache on CPU4
10434 11:53:23.645134 <6>[ 0.102303] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 11:53:23.651086 <6>[ 0.102319] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 11:53:23.654378 <6>[ 0.102609] Detected PIPT I-cache on CPU5
10437 11:53:23.664345 <6>[ 0.102672] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 11:53:23.671199 <6>[ 0.102688] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 11:53:23.674611 <6>[ 0.102966] Detected PIPT I-cache on CPU6
10440 11:53:23.681507 <6>[ 0.103032] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 11:53:23.688354 <6>[ 0.103047] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 11:53:23.691008 <6>[ 0.103340] Detected PIPT I-cache on CPU7
10443 11:53:23.697679 <6>[ 0.103405] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 11:53:23.704275 <6>[ 0.103421] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 11:53:23.711411 <6>[ 0.103468] smp: Brought up 1 node, 8 CPUs
10446 11:53:23.714451 <6>[ 0.244828] SMP: Total of 8 processors activated.
10447 11:53:23.721120 <6>[ 0.249748] CPU features: detected: 32-bit EL0 Support
10448 11:53:23.730796 <6>[ 0.255143] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 11:53:23.734547 <6>[ 0.263998] CPU features: detected: Common not Private translations
10450 11:53:23.740871 <6>[ 0.270474] CPU features: detected: CRC32 instructions
10451 11:53:23.747482 <6>[ 0.275825] CPU features: detected: RCpc load-acquire (LDAPR)
10452 11:53:23.754487 <6>[ 0.281785] CPU features: detected: LSE atomic instructions
10453 11:53:23.757516 <6>[ 0.287566] CPU features: detected: Privileged Access Never
10454 11:53:23.764423 <6>[ 0.293346] CPU features: detected: RAS Extension Support
10455 11:53:23.770655 <6>[ 0.298990] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 11:53:23.777352 <6>[ 0.306209] CPU: All CPU(s) started at EL2
10457 11:53:23.780762 <6>[ 0.310525] alternatives: applying system-wide alternatives
10458 11:53:23.791793 <6>[ 0.321263] devtmpfs: initialized
10459 11:53:23.804131 <6>[ 0.330171] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10460 11:53:23.814014 <6>[ 0.340133] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10461 11:53:23.821397 <6>[ 0.348348] pinctrl core: initialized pinctrl subsystem
10462 11:53:23.823723 <6>[ 0.355011] DMI not present or invalid.
10463 11:53:23.830777 <6>[ 0.359423] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10464 11:53:23.840413 <6>[ 0.366315] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10465 11:53:23.847410 <6>[ 0.373896] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10466 11:53:23.857254 <6>[ 0.382122] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10467 11:53:23.860711 <6>[ 0.390367] audit: initializing netlink subsys (disabled)
10468 11:53:23.870734 <5>[ 0.396058] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10469 11:53:23.874269 <6>[ 0.396761] thermal_sys: Registered thermal governor 'step_wise'
10470 11:53:23.884474 <6>[ 0.404024] thermal_sys: Registered thermal governor 'power_allocator'
10471 11:53:23.887502 <6>[ 0.410279] cpuidle: using governor menu
10472 11:53:23.890984 <6>[ 0.421235] NET: Registered PF_QIPCRTR protocol family
10473 11:53:23.900839 <6>[ 0.426731] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10474 11:53:23.904344 <6>[ 0.433835] ASID allocator initialised with 32768 entries
10475 11:53:23.910695 <6>[ 0.440390] Serial: AMBA PL011 UART driver
10476 11:53:23.919507 <4>[ 0.449171] Trying to register duplicate clock ID: 134
10477 11:53:23.973776 <6>[ 0.506651] KASLR enabled
10478 11:53:23.988435 <6>[ 0.514333] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10479 11:53:23.994845 <6>[ 0.521348] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10480 11:53:24.001410 <6>[ 0.527837] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10481 11:53:24.007884 <6>[ 0.534844] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10482 11:53:24.014670 <6>[ 0.541330] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10483 11:53:24.021647 <6>[ 0.548335] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10484 11:53:24.028365 <6>[ 0.554822] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10485 11:53:24.034784 <6>[ 0.561829] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10486 11:53:24.037935 <6>[ 0.569321] ACPI: Interpreter disabled.
10487 11:53:24.046517 <6>[ 0.575705] iommu: Default domain type: Translated
10488 11:53:24.052581 <6>[ 0.580816] iommu: DMA domain TLB invalidation policy: strict mode
10489 11:53:24.056442 <5>[ 0.587471] SCSI subsystem initialized
10490 11:53:24.062814 <6>[ 0.591638] usbcore: registered new interface driver usbfs
10491 11:53:24.069395 <6>[ 0.597369] usbcore: registered new interface driver hub
10492 11:53:24.072895 <6>[ 0.602921] usbcore: registered new device driver usb
10493 11:53:24.079693 <6>[ 0.609016] pps_core: LinuxPPS API ver. 1 registered
10494 11:53:24.089811 <6>[ 0.614212] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10495 11:53:24.092931 <6>[ 0.623557] PTP clock support registered
10496 11:53:24.095922 <6>[ 0.627798] EDAC MC: Ver: 3.0.0
10497 11:53:24.103135 <6>[ 0.632954] FPGA manager framework
10498 11:53:24.110262 <6>[ 0.636634] Advanced Linux Sound Architecture Driver Initialized.
10499 11:53:24.113257 <6>[ 0.643405] vgaarb: loaded
10500 11:53:24.119750 <6>[ 0.646587] clocksource: Switched to clocksource arch_sys_counter
10501 11:53:24.123401 <5>[ 0.653017] VFS: Disk quotas dquot_6.6.0
10502 11:53:24.130009 <6>[ 0.657200] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10503 11:53:24.133488 <6>[ 0.664387] pnp: PnP ACPI: disabled
10504 11:53:24.141794 <6>[ 0.671011] NET: Registered PF_INET protocol family
10505 11:53:24.151334 <6>[ 0.676590] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10506 11:53:24.162520 <6>[ 0.688870] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10507 11:53:24.172860 <6>[ 0.697685] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10508 11:53:24.179485 <6>[ 0.705655] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10509 11:53:24.186254 <6>[ 0.714351] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10510 11:53:24.194658 <6>[ 0.724088] TCP: Hash tables configured (established 65536 bind 65536)
10511 11:53:24.204909 <6>[ 0.730949] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 11:53:24.211037 <6>[ 0.738151] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 11:53:24.217981 <6>[ 0.745846] NET: Registered PF_UNIX/PF_LOCAL protocol family
10514 11:53:24.224331 <6>[ 0.752015] RPC: Registered named UNIX socket transport module.
10515 11:53:24.227842 <6>[ 0.758167] RPC: Registered udp transport module.
10516 11:53:24.234441 <6>[ 0.763101] RPC: Registered tcp transport module.
10517 11:53:24.240988 <6>[ 0.768032] RPC: Registered tcp NFSv4.1 backchannel transport module.
10518 11:53:24.244605 <6>[ 0.774698] PCI: CLS 0 bytes, default 64
10519 11:53:24.248090 <6>[ 0.779122] Unpacking initramfs...
10520 11:53:24.258163 <6>[ 0.783318] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10521 11:53:24.264534 <6>[ 0.791954] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10522 11:53:24.271205 <6>[ 0.800791] kvm [1]: IPA Size Limit: 40 bits
10523 11:53:24.274395 <6>[ 0.805318] kvm [1]: GICv3: no GICV resource entry
10524 11:53:24.281298 <6>[ 0.810339] kvm [1]: disabling GICv2 emulation
10525 11:53:24.288204 <6>[ 0.815026] kvm [1]: GIC system register CPU interface enabled
10526 11:53:24.291437 <6>[ 0.821197] kvm [1]: vgic interrupt IRQ18
10527 11:53:24.297534 <6>[ 0.825564] kvm [1]: VHE mode initialized successfully
10528 11:53:24.301441 <5>[ 0.832138] Initialise system trusted keyrings
10529 11:53:24.307729 <6>[ 0.836937] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10530 11:53:24.317374 <6>[ 0.846973] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10531 11:53:24.324306 <5>[ 0.853391] NFS: Registering the id_resolver key type
10532 11:53:24.327230 <5>[ 0.858710] Key type id_resolver registered
10533 11:53:24.334208 <5>[ 0.863127] Key type id_legacy registered
10534 11:53:24.340667 <6>[ 0.867406] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10535 11:53:24.347531 <6>[ 0.874329] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10536 11:53:24.353970 <6>[ 0.882038] 9p: Installing v9fs 9p2000 file system support
10537 11:53:24.390534 <5>[ 0.920061] Key type asymmetric registered
10538 11:53:24.393768 <5>[ 0.924393] Asymmetric key parser 'x509' registered
10539 11:53:24.403651 <6>[ 0.929536] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10540 11:53:24.406974 <6>[ 0.937146] io scheduler mq-deadline registered
10541 11:53:24.410248 <6>[ 0.941908] io scheduler kyber registered
10542 11:53:24.429508 <6>[ 0.959049] EINJ: ACPI disabled.
10543 11:53:24.461755 <4>[ 0.984815] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 11:53:24.472078 <4>[ 0.995558] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 11:53:24.486825 <6>[ 1.016360] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10546 11:53:24.494568 <6>[ 1.024333] printk: console [ttyS0] disabled
10547 11:53:24.522752 <6>[ 1.048979] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10548 11:53:24.529226 <6>[ 1.058459] printk: console [ttyS0] enabled
10549 11:53:24.532824 <6>[ 1.058459] printk: console [ttyS0] enabled
10550 11:53:24.539438 <6>[ 1.067352] printk: bootconsole [mtk8250] disabled
10551 11:53:24.542970 <6>[ 1.067352] printk: bootconsole [mtk8250] disabled
10552 11:53:24.549124 <6>[ 1.078623] SuperH (H)SCI(F) driver initialized
10553 11:53:24.552907 <6>[ 1.083896] msm_serial: driver initialized
10554 11:53:24.566688 <6>[ 1.092900] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10555 11:53:24.576932 <6>[ 1.101446] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10556 11:53:24.583356 <6>[ 1.109989] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10557 11:53:24.593662 <6>[ 1.118618] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10558 11:53:24.600025 <6>[ 1.127325] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10559 11:53:24.609731 <6>[ 1.136038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10560 11:53:24.619583 <6>[ 1.144578] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10561 11:53:24.626802 <6>[ 1.153396] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10562 11:53:24.636062 <6>[ 1.161941] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10563 11:53:24.647735 <6>[ 1.177435] loop: module loaded
10564 11:53:24.654623 <6>[ 1.183469] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10565 11:53:24.677245 <4>[ 1.206943] mtk-pmic-keys: Failed to locate of_node [id: -1]
10566 11:53:24.684652 <6>[ 1.213814] megasas: 07.719.03.00-rc1
10567 11:53:24.694047 <6>[ 1.223574] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10568 11:53:24.704245 <6>[ 1.233961] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 11:53:24.720445 <6>[ 1.249928] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 11:53:24.776426 <6>[ 1.299434] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10571 11:53:24.989367 <6>[ 1.519038] Freeing initrd memory: 17372K
10572 11:53:24.999647 <6>[ 1.529502] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10573 11:53:25.010822 <6>[ 1.540484] tun: Universal TUN/TAP device driver, 1.6
10574 11:53:25.014335 <6>[ 1.546550] thunder_xcv, ver 1.0
10575 11:53:25.017681 <6>[ 1.550055] thunder_bgx, ver 1.0
10576 11:53:25.020974 <6>[ 1.553555] nicpf, ver 1.0
10577 11:53:25.031554 <6>[ 1.557569] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10578 11:53:25.034755 <6>[ 1.565045] hns3: Copyright (c) 2017 Huawei Corporation.
10579 11:53:25.038122 <6>[ 1.570635] hclge is initializing
10580 11:53:25.044712 <6>[ 1.574206] e1000: Intel(R) PRO/1000 Network Driver
10581 11:53:25.051221 <6>[ 1.579337] e1000: Copyright (c) 1999-2006 Intel Corporation.
10582 11:53:25.054924 <6>[ 1.585350] e1000e: Intel(R) PRO/1000 Network Driver
10583 11:53:25.061517 <6>[ 1.590566] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10584 11:53:25.068326 <6>[ 1.596751] igb: Intel(R) Gigabit Ethernet Network Driver
10585 11:53:25.075274 <6>[ 1.602400] igb: Copyright (c) 2007-2014 Intel Corporation.
10586 11:53:25.082610 <6>[ 1.608236] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10587 11:53:25.084664 <6>[ 1.614754] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10588 11:53:25.091511 <6>[ 1.621219] sky2: driver version 1.30
10589 11:53:25.098454 <6>[ 1.626231] VFIO - User Level meta-driver version: 0.3
10590 11:53:25.105212 <6>[ 1.634475] usbcore: registered new interface driver usb-storage
10591 11:53:25.111804 <6>[ 1.640931] usbcore: registered new device driver onboard-usb-hub
10592 11:53:25.120369 <6>[ 1.650118] mt6397-rtc mt6359-rtc: registered as rtc0
10593 11:53:25.130521 <6>[ 1.655585] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:53:26 UTC (1700740406)
10594 11:53:25.134157 <6>[ 1.665151] i2c_dev: i2c /dev entries driver
10595 11:53:25.150497 <6>[ 1.676986] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10596 11:53:25.171329 <6>[ 1.701001] cpu cpu0: EM: created perf domain
10597 11:53:25.174664 <6>[ 1.705934] cpu cpu4: EM: created perf domain
10598 11:53:25.182247 <6>[ 1.711562] sdhci: Secure Digital Host Controller Interface driver
10599 11:53:25.188686 <6>[ 1.717991] sdhci: Copyright(c) Pierre Ossman
10600 11:53:25.195068 <6>[ 1.722948] Synopsys Designware Multimedia Card Interface Driver
10601 11:53:25.201954 <6>[ 1.729577] sdhci-pltfm: SDHCI platform and OF driver helper
10602 11:53:25.205290 <6>[ 1.729679] mmc0: CQHCI version 5.10
10603 11:53:25.211715 <6>[ 1.739590] ledtrig-cpu: registered to indicate activity on CPUs
10604 11:53:25.218867 <6>[ 1.746432] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10605 11:53:25.225347 <6>[ 1.753482] usbcore: registered new interface driver usbhid
10606 11:53:25.228664 <6>[ 1.759306] usbhid: USB HID core driver
10607 11:53:25.235146 <6>[ 1.763476] spi_master spi0: will run message pump with realtime priority
10608 11:53:25.276951 <6>[ 1.800069] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10609 11:53:25.295367 <6>[ 1.815217] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10610 11:53:25.299194 <6>[ 1.828832] mmc0: Command Queue Engine enabled
10611 11:53:25.305639 <6>[ 1.833605] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10612 11:53:25.312427 <6>[ 1.840582] cros-ec-spi spi0.0: Chrome EC device registered
10613 11:53:25.315723 <6>[ 1.840938] mmcblk0: mmc0:0001 DA4128 116 GiB
10614 11:53:25.325514 <6>[ 1.855277] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10615 11:53:25.333122 <6>[ 1.862763] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10616 11:53:25.339998 <6>[ 1.868631] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10617 11:53:25.346533 <6>[ 1.874474] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 11:53:25.361963 <6>[ 1.888228] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10619 11:53:25.369014 <6>[ 1.898867] NET: Registered PF_PACKET protocol family
10620 11:53:25.372350 <6>[ 1.904265] 9pnet: Installing 9P2000 support
10621 11:53:25.378977 <5>[ 1.908831] Key type dns_resolver registered
10622 11:53:25.382327 <6>[ 1.913831] registered taskstats version 1
10623 11:53:25.389500 <5>[ 1.918216] Loading compiled-in X.509 certificates
10624 11:53:25.420118 <4>[ 1.942919] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10625 11:53:25.429815 <4>[ 1.953700] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10626 11:53:25.437011 <3>[ 1.964237] debugfs: File 'uA_load' in directory '/' already present!
10627 11:53:25.443637 <3>[ 1.970940] debugfs: File 'min_uV' in directory '/' already present!
10628 11:53:25.450416 <3>[ 1.977547] debugfs: File 'max_uV' in directory '/' already present!
10629 11:53:25.457033 <3>[ 1.984154] debugfs: File 'constraint_flags' in directory '/' already present!
10630 11:53:25.467840 <3>[ 1.993939] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10631 11:53:25.476756 <6>[ 2.006525] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10632 11:53:25.483681 <6>[ 2.013338] xhci-mtk 11200000.usb: xHCI Host Controller
10633 11:53:25.490549 <6>[ 2.018836] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10634 11:53:25.500640 <6>[ 2.026679] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10635 11:53:25.507131 <6>[ 2.036106] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10636 11:53:25.513912 <6>[ 2.042159] xhci-mtk 11200000.usb: xHCI Host Controller
10637 11:53:25.520727 <6>[ 2.047634] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10638 11:53:25.527295 <6>[ 2.055281] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10639 11:53:25.533723 <6>[ 2.062976] hub 1-0:1.0: USB hub found
10640 11:53:25.537129 <6>[ 2.066985] hub 1-0:1.0: 1 port detected
10641 11:53:25.544017 <6>[ 2.071256] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10642 11:53:25.550636 <6>[ 2.079925] hub 2-0:1.0: USB hub found
10643 11:53:25.554019 <6>[ 2.083949] hub 2-0:1.0: 1 port detected
10644 11:53:25.561514 <6>[ 2.091312] mtk-msdc 11f70000.mmc: Got CD GPIO
10645 11:53:25.572350 <6>[ 2.098809] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10646 11:53:25.579387 <6>[ 2.106828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10647 11:53:25.589463 <4>[ 2.114748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10648 11:53:25.596113 <6>[ 2.124274] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10649 11:53:25.606213 <6>[ 2.132351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10650 11:53:25.612789 <6>[ 2.140468] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10651 11:53:25.622805 <6>[ 2.148393] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10652 11:53:25.629731 <6>[ 2.156211] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10653 11:53:25.639680 <6>[ 2.164029] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10654 11:53:25.649547 <6>[ 2.174481] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10655 11:53:25.656193 <6>[ 2.182843] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10656 11:53:25.666289 <6>[ 2.191182] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10657 11:53:25.672839 <6>[ 2.199521] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10658 11:53:25.682725 <6>[ 2.207861] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10659 11:53:25.689560 <6>[ 2.216201] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10660 11:53:25.699424 <6>[ 2.224540] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10661 11:53:25.706669 <6>[ 2.232879] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10662 11:53:25.716024 <6>[ 2.241217] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10663 11:53:25.722985 <6>[ 2.249555] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10664 11:53:25.732915 <6>[ 2.257905] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10665 11:53:25.739577 <6>[ 2.266244] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10666 11:53:25.749613 <6>[ 2.274582] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10667 11:53:25.756442 <6>[ 2.282920] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10668 11:53:25.766217 <6>[ 2.291258] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10669 11:53:25.772657 <6>[ 2.299910] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10670 11:53:25.779732 <6>[ 2.307082] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10671 11:53:25.786469 <6>[ 2.313850] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10672 11:53:25.792762 <6>[ 2.320603] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10673 11:53:25.800058 <6>[ 2.327532] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10674 11:53:25.809529 <6>[ 2.334377] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10675 11:53:25.819331 <6>[ 2.343503] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10676 11:53:25.826288 <6>[ 2.352622] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10677 11:53:25.835710 <6>[ 2.361916] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10678 11:53:25.845651 <6>[ 2.371386] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10679 11:53:25.855919 <6>[ 2.380855] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10680 11:53:25.866260 <6>[ 2.389987] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10681 11:53:25.872252 <6>[ 2.399455] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10682 11:53:25.882131 <6>[ 2.408573] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10683 11:53:25.892519 <6>[ 2.417867] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10684 11:53:25.901923 <6>[ 2.428028] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10685 11:53:25.913911 <6>[ 2.440098] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10686 11:53:25.920316 <6>[ 2.449837] Trying to probe devices needed for running init ...
10687 11:53:25.944694 <6>[ 2.471139] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10688 11:53:25.973229 <6>[ 2.502533] hub 2-1:1.0: USB hub found
10689 11:53:25.976219 <6>[ 2.507018] hub 2-1:1.0: 3 ports detected
10690 11:53:25.984337 <6>[ 2.514316] hub 2-1:1.0: USB hub found
10691 11:53:25.987882 <6>[ 2.518747] hub 2-1:1.0: 3 ports detected
10692 11:53:26.096376 <6>[ 2.622860] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10693 11:53:26.250518 <6>[ 2.780352] hub 1-1:1.0: USB hub found
10694 11:53:26.253644 <6>[ 2.784823] hub 1-1:1.0: 4 ports detected
10695 11:53:26.263464 <6>[ 2.792774] hub 1-1:1.0: USB hub found
10696 11:53:26.266039 <6>[ 2.797255] hub 1-1:1.0: 4 ports detected
10697 11:53:26.332490 <6>[ 2.858938] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10698 11:53:26.588347 <6>[ 3.114899] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10699 11:53:26.720906 <6>[ 3.250880] hub 1-1.4:1.0: USB hub found
10700 11:53:26.724666 <6>[ 3.255555] hub 1-1.4:1.0: 2 ports detected
10701 11:53:26.734422 <6>[ 3.264068] hub 1-1.4:1.0: USB hub found
10702 11:53:26.737630 <6>[ 3.268671] hub 1-1.4:1.0: 2 ports detected
10703 11:53:27.036392 <6>[ 3.562897] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10704 11:53:27.228345 <6>[ 3.754899] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10705 11:53:38.201219 <6>[ 14.735816] ALSA device list:
10706 11:53:38.207871 <6>[ 14.739101] No soundcards found.
10707 11:53:38.215743 <6>[ 14.746890] Freeing unused kernel memory: 8384K
10708 11:53:38.218967 <6>[ 14.751842] Run /init as init process
10709 11:53:38.230213 Loading, please wait...
10710 11:53:38.256764 Starting version 247.3-7+deb11u2
10711 11:53:38.474109 <6>[ 15.001569] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10712 11:53:38.486002 <6>[ 15.016998] remoteproc remoteproc0: scp is available
10713 11:53:38.493669 <6>[ 15.024762] remoteproc remoteproc0: powering up scp
10714 11:53:38.503694 <6>[ 15.029935] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10715 11:53:38.510458 <6>[ 15.032407] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10716 11:53:38.517016 <3>[ 15.035719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10717 11:53:38.526996 <3>[ 15.035741] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 11:53:38.534071 <3>[ 15.035750] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 11:53:38.543872 <3>[ 15.035826] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10720 11:53:38.550534 <3>[ 15.035834] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10721 11:53:38.556511 <3>[ 15.035843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 11:53:38.566670 <3>[ 15.035858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 11:53:38.573272 <3>[ 15.035866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10724 11:53:38.579802 <6>[ 15.038409] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10725 11:53:38.586703 <6>[ 15.039150] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10726 11:53:38.596508 <6>[ 15.039171] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10727 11:53:38.606433 <6>[ 15.039176] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10728 11:53:38.609732 <6>[ 15.051092] usbcore: registered new interface driver r8152
10729 11:53:38.619510 <4>[ 15.054797] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10730 11:53:38.626417 <4>[ 15.074182] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10731 11:53:38.633483 <4>[ 15.074182] Fallback method does not support PEC.
10732 11:53:38.639619 <3>[ 15.168536] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10733 11:53:38.646841 <4>[ 15.168608] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10734 11:53:38.656479 <6>[ 15.168838] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10735 11:53:38.659727 <6>[ 15.168851] pci_bus 0000:00: root bus resource [bus 00-ff]
10736 11:53:38.667131 <6>[ 15.168863] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10737 11:53:38.673532 <6>[ 15.168871] mc: Linux media interface: v0.10
10738 11:53:38.683463 <6>[ 15.168873] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10739 11:53:38.686828 <6>[ 15.168929] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10740 11:53:38.696696 <6>[ 15.168959] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10741 11:53:38.699982 <6>[ 15.169058] pci 0000:00:00.0: supports D1 D2
10742 11:53:38.706915 <6>[ 15.169065] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10743 11:53:38.717177 <6>[ 15.172200] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10744 11:53:38.720335 <6>[ 15.172415] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10745 11:53:38.729999 <6>[ 15.172455] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10746 11:53:38.736754 <6>[ 15.172482] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10747 11:53:38.743136 <6>[ 15.172507] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10748 11:53:38.750072 <6>[ 15.172647] pci 0000:01:00.0: supports D1 D2
10749 11:53:38.756526 <6>[ 15.172654] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10750 11:53:38.763807 <3>[ 15.176707] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10751 11:53:38.769904 <6>[ 15.176944] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10752 11:53:38.776584 <6>[ 15.182806] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10753 11:53:38.784210 <6>[ 15.182852] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10754 11:53:38.793661 <6>[ 15.182867] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10755 11:53:38.800282 <6>[ 15.182890] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10756 11:53:38.810175 <6>[ 15.182914] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10757 11:53:38.816853 <6>[ 15.182939] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10758 11:53:38.823635 <6>[ 15.182962] pci 0000:00:00.0: PCI bridge to [bus 01]
10759 11:53:38.830371 <6>[ 15.182976] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10760 11:53:38.836704 <6>[ 15.183195] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10761 11:53:38.846583 <3>[ 15.204480] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10762 11:53:38.853401 <6>[ 15.208234] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10763 11:53:38.863143 <3>[ 15.209052] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10764 11:53:38.870095 <3>[ 15.209058] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 11:53:38.876447 <6>[ 15.210207] videodev: Linux video capture interface: v2.00
10766 11:53:38.883234 <3>[ 15.213016] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 11:53:38.893170 <3>[ 15.213025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 11:53:38.899509 <3>[ 15.213029] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 11:53:38.909746 <3>[ 15.213033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 11:53:38.916191 <3>[ 15.213036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10771 11:53:38.926543 <3>[ 15.213464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10772 11:53:38.932628 <6>[ 15.215808] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10773 11:53:38.936255 <6>[ 15.219321] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10774 11:53:38.942666 <6>[ 15.224418] remoteproc remoteproc0: remote processor scp is now up
10775 11:53:38.952410 <6>[ 15.292778] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10776 11:53:38.962514 <6>[ 15.294543] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10777 11:53:38.969277 <3>[ 15.321900] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10778 11:53:38.979057 <6>[ 15.332587] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10779 11:53:38.989638 <6>[ 15.347402] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10780 11:53:38.995967 <6>[ 15.367151] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10781 11:53:39.005825 <6>[ 15.374361] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10782 11:53:39.012865 <4>[ 15.403154] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10783 11:53:39.019030 <6>[ 15.430008] usbcore: registered new interface driver cdc_ether
10784 11:53:39.029372 <5>[ 15.430921] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10785 11:53:39.035747 <4>[ 15.437783] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10786 11:53:39.042885 <6>[ 15.453590] usbcore: registered new interface driver r8153_ecm
10787 11:53:39.049340 <5>[ 15.454717] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10788 11:53:39.056278 <4>[ 15.455003] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 11:53:39.062936 <6>[ 15.455014] cfg80211: failed to load regulatory.db
10790 11:53:39.066035 <6>[ 15.463383] Bluetooth: Core ver 2.22
10791 11:53:39.072911 <6>[ 15.469273] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10792 11:53:39.079491 <6>[ 15.473570] NET: Registered PF_BLUETOOTH protocol family
10793 11:53:39.092729 <6>[ 15.481615] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10794 11:53:39.099246 <6>[ 15.488189] Bluetooth: HCI device and connection manager initialized
10795 11:53:39.102471 <6>[ 15.488221] Bluetooth: HCI socket layer initialized
10796 11:53:39.109162 <6>[ 15.497715] usbcore: registered new interface driver uvcvideo
10797 11:53:39.116322 <6>[ 15.506287] Bluetooth: L2CAP socket layer initialized
10798 11:53:39.122936 <6>[ 15.507288] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10799 11:53:39.126016 <6>[ 15.538875] r8152 2-1.3:1.0 eth0: v1.12.13
10800 11:53:39.129193 <6>[ 15.540764] Bluetooth: SCO socket layer initialized
10801 11:53:39.135804 <6>[ 15.567243] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10802 11:53:39.142400 <6>[ 15.568066] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10803 11:53:39.148995 <6>[ 15.568158] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10804 11:53:39.155802 <6>[ 15.586709] mt7921e 0000:01:00.0: ASIC revision: 79610010
10805 11:53:39.163016 <6>[ 15.634597] usbcore: registered new interface driver btusb
10806 11:53:39.172323 <4>[ 15.635612] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10807 11:53:39.179794 <3>[ 15.635625] Bluetooth: hci0: Failed to load firmware file (-2)
10808 11:53:39.185697 <3>[ 15.635630] Bluetooth: hci0: Failed to set up firmware (-2)
10809 11:53:39.196060 <4>[ 15.635636] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10810 11:53:39.210168 <4>[ 15.734080] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10811 11:53:39.213455 Begin: Loading essential drivers ... done.
10812 11:53:39.221538 Begin: Running /scripts/init-premount ... done.
10813 11:53:39.228621 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10814 11:53:39.238064 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10815 11:53:39.241572 Device /sys/class/net/enx002432307852 found
10816 11:53:39.242096 done.
10817 11:53:39.283813 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10818 11:53:39.328823 <4>[ 15.852749] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10819 11:53:39.443724 <4>[ 15.968048] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10820 11:53:39.560207 <4>[ 16.084018] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10821 11:53:39.675771 <4>[ 16.199960] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10822 11:53:39.791696 <4>[ 16.315868] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10823 11:53:39.907574 <4>[ 16.431822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10824 11:53:40.023571 <4>[ 16.547798] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10825 11:53:40.139204 <4>[ 16.663675] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10826 11:53:40.255290 <4>[ 16.779662] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10827 11:53:40.362944 <3>[ 16.893590] mt7921e 0000:01:00.0: hardware init failed
10828 11:53:40.624876 IP-Config: no response after 2 secs - giving up
10829 11:53:40.656071 IP-Config: enx002432307852 hardware address 00:24:32:30:78:52 mtu 1500 DHCP
10830 11:53:40.719598 <6>[ 17.250659] r8152 2-1.3:1.0 enx002432307852: carrier on
10831 11:53:41.763368 IP-Config: enx002432307852 complete (dhcp from 192.168.201.1):
10832 11:53:41.769772 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10833 11:53:41.776217 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10834 11:53:41.783307 host : mt8192-asurada-spherion-r0-cbg-3
10835 11:53:41.789959 domain : lava-rack
10836 11:53:41.793146 rootserver: 192.168.201.1 rootpath:
10837 11:53:41.796034 filename :
10838 11:53:41.867265 done.
10839 11:53:41.875996 Begin: Running /scripts/nfs-bottom ... done.
10840 11:53:41.895362 Begin: Running /scripts/init-bottom ... done.
10841 11:53:43.163704 <6>[ 19.695262] NET: Registered PF_INET6 protocol family
10842 11:53:43.171344 <6>[ 19.702790] Segment Routing with IPv6
10843 11:53:43.174420 <6>[ 19.706757] In-situ OAM (IOAM) with IPv6
10844 11:53:43.301762 <30>[ 19.816194] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10845 11:53:43.309035 <30>[ 19.840615] systemd[1]: Detected architecture arm64.
10846 11:53:43.329987
10847 11:53:43.333957 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10848 11:53:43.334148
10849 11:53:43.350327 <30>[ 19.881813] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10850 11:53:44.302650 <30>[ 20.830960] systemd[1]: Queued start job for default target Graphical Interface.
10851 11:53:44.329867 <30>[ 20.861212] systemd[1]: Created slice system-getty.slice.
10852 11:53:44.336159 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10853 11:53:44.352712 <30>[ 20.884258] systemd[1]: Created slice system-modprobe.slice.
10854 11:53:44.359145 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10855 11:53:44.376557 <30>[ 20.908088] systemd[1]: Created slice system-serial\x2dgetty.slice.
10856 11:53:44.386966 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10857 11:53:44.400743 <30>[ 20.931912] systemd[1]: Created slice User and Session Slice.
10858 11:53:44.407553 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10859 11:53:44.427662 <30>[ 20.955722] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10860 11:53:44.437622 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10861 11:53:44.455832 <30>[ 20.983643] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10862 11:53:44.462326 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10863 11:53:44.486027 <30>[ 21.011016] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10864 11:53:44.492578 <30>[ 21.023160] systemd[1]: Reached target Local Encrypted Volumes.
10865 11:53:44.499575 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10866 11:53:44.515693 <30>[ 21.047440] systemd[1]: Reached target Paths.
10867 11:53:44.522263 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10868 11:53:44.535745 <30>[ 21.066887] systemd[1]: Reached target Remote File Systems.
10869 11:53:44.542530 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10870 11:53:44.560327 <30>[ 21.091151] systemd[1]: Reached target Slices.
10871 11:53:44.566175 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10872 11:53:44.579160 <30>[ 21.110880] systemd[1]: Reached target Swap.
10873 11:53:44.582580 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10874 11:53:44.602922 <30>[ 21.131328] systemd[1]: Listening on initctl Compatibility Named Pipe.
10875 11:53:44.609824 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10876 11:53:44.616717 <30>[ 21.147667] systemd[1]: Listening on Journal Audit Socket.
10877 11:53:44.623463 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10878 11:53:44.640784 <30>[ 21.172316] systemd[1]: Listening on Journal Socket (/dev/log).
10879 11:53:44.647391 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10880 11:53:44.663951 <30>[ 21.195473] systemd[1]: Listening on Journal Socket.
10881 11:53:44.670252 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10882 11:53:44.688093 <30>[ 21.216504] systemd[1]: Listening on Network Service Netlink Socket.
10883 11:53:44.695262 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10884 11:53:44.710632 <30>[ 21.242195] systemd[1]: Listening on udev Control Socket.
10885 11:53:44.717358 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10886 11:53:44.732183 <30>[ 21.263380] systemd[1]: Listening on udev Kernel Socket.
10887 11:53:44.738847 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10888 11:53:44.795789 <30>[ 21.327193] systemd[1]: Mounting Huge Pages File System...
10889 11:53:44.802462 Mounting [0;1;39mHuge Pages File System[0m...
10890 11:53:44.820164 <30>[ 21.351654] systemd[1]: Mounting POSIX Message Queue File System...
10891 11:53:44.827197 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10892 11:53:44.871951 <30>[ 21.403227] systemd[1]: Mounting Kernel Debug File System...
10893 11:53:44.878122 Mounting [0;1;39mKernel Debug File System[0m...
10894 11:53:44.894729 <30>[ 21.423209] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10895 11:53:44.911136 <30>[ 21.439262] systemd[1]: Starting Create list of static device nodes for the current kernel...
10896 11:53:44.917747 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10897 11:53:44.963885 <30>[ 21.495590] systemd[1]: Starting Load Kernel Module configfs...
10898 11:53:44.970494 Starting [0;1;39mLoad Kernel Module configfs[0m...
10899 11:53:44.988311 <30>[ 21.519987] systemd[1]: Starting Load Kernel Module drm...
10900 11:53:44.995303 Starting [0;1;39mLoad Kernel Module drm[0m...
10901 11:53:45.010658 <30>[ 21.542176] systemd[1]: Starting Load Kernel Module fuse...
10902 11:53:45.017212 Starting [0;1;39mLoad Kernel Module fuse[0m...
10903 11:53:45.041064 <30>[ 21.569209] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10904 11:53:45.069487 <6>[ 21.600869] fuse: init (API version 7.37)
10905 11:53:45.079685 <30>[ 21.611532] systemd[1]: Starting Journal Service...
10906 11:53:45.083428 Starting [0;1;39mJournal Service[0m...
10907 11:53:45.109550 <30>[ 21.641360] systemd[1]: Starting Load Kernel Modules...
10908 11:53:45.116410 Starting [0;1;39mLoad Kernel Modules[0m...
10909 11:53:45.137637 <30>[ 21.665805] systemd[1]: Starting Remount Root and Kernel File Systems...
10910 11:53:45.143874 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10911 11:53:45.164256 <30>[ 21.695917] systemd[1]: Starting Coldplug All udev Devices...
10912 11:53:45.170721 Starting [0;1;39mColdplug All udev Devices[0m...
10913 11:53:45.188081 <30>[ 21.719129] systemd[1]: Mounted Huge Pages File System.
10914 11:53:45.193942 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10915 11:53:45.208331 <30>[ 21.739778] systemd[1]: Mounted POSIX Message Queue File System.
10916 11:53:45.214819 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10917 11:53:45.232204 <30>[ 21.763664] systemd[1]: Mounted Kernel Debug File System.
10918 11:53:45.238520 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10919 11:53:45.260173 <30>[ 21.787969] systemd[1]: Finished Create list of static device nodes for the current kernel.
10920 11:53:45.270287 <3>[ 21.790718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:53:45.276665 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10922 11:53:45.292469 <30>[ 21.823865] systemd[1]: modprobe@configfs.service: Succeeded.
10923 11:53:45.302943 <3>[ 21.827464] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 11:53:45.309320 <30>[ 21.830842] systemd[1]: Finished Load Kernel Module configfs.
10925 11:53:45.315998 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10926 11:53:45.332054 <30>[ 21.863625] systemd[1]: modprobe@drm.service: Succeeded.
10927 11:53:45.339026 <30>[ 21.869934] systemd[1]: Finished Load Kernel Module drm.
10928 11:53:45.349483 [[0;32m OK [0m] Finished [0<3>[ 21.878187] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:53:45.352670 ;1;39mLoad Kernel Module drm[0m.
10930 11:53:45.369404 <30>[ 21.900228] systemd[1]: modprobe@fuse.service: Succeeded.
10931 11:53:45.375692 <30>[ 21.906869] systemd[1]: Finished Load Kernel Module fuse.
10932 11:53:45.385792 <3>[ 21.908330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10933 11:53:45.392237 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10934 11:53:45.409350 <30>[ 21.940685] systemd[1]: Finished Load Kernel Modules.
10935 11:53:45.419150 <3>[ 21.943859] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10936 11:53:45.422528 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10937 11:53:45.441996 <30>[ 21.973016] systemd[1]: Finished Remount Root and Kernel File Systems.
10938 11:53:45.452628 <3>[ 21.979100] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10939 11:53:45.458948 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10940 11:53:45.483601 <3>[ 22.011782] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10941 11:53:45.513967 <3>[ 22.042491] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10942 11:53:45.520401 <30>[ 22.044193] systemd[1]: Mounting FUSE Control File System...
10943 11:53:45.527408 Mounting [0;1;39mFUSE Control File System[0m...
10944 11:53:45.543594 <3>[ 22.071925] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 11:53:45.550801 <30>[ 22.073516] systemd[1]: Mounting Kernel Configuration File System...
10946 11:53:45.557303 Mounting [0;1;39mKernel Configuration File System[0m...
10947 11:53:45.576164 <3>[ 22.104213] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:53:45.591422 <30>[ 22.119868] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10949 11:53:45.601836 <30>[ 22.129059] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10950 11:53:45.628131 <30>[ 22.159340] systemd[1]: Starting Load/Save Random Seed...
10951 11:53:45.634772 Starting [0;1;39mLoad/Save Random Seed[0m...
10952 11:53:45.654180 <30>[ 22.185958] systemd[1]: Starting Apply Kernel Variables...
10953 11:53:45.661157 Starting [0;1;39mApply Kernel Variables[0m...
10954 11:53:45.692779 <4>[ 22.214544] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10955 11:53:45.699695 <30>[ 22.215768] systemd[1]: Starting Create System Users...
10956 11:53:45.706230 <3>[ 22.230307] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10957 11:53:45.712852 Starting [0;1;39mCreate System Users[0m...
10958 11:53:45.733179 <30>[ 22.264477] systemd[1]: Started Journal Service.
10959 11:53:45.736241 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10960 11:53:45.759013 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10961 11:53:45.775184 See 'systemctl status systemd-udev-trigger.service' for details.
10962 11:53:45.796405 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10963 11:53:45.815399 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10964 11:53:45.831576 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10965 11:53:45.852175 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10966 11:53:45.873264 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10967 11:53:45.928276 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10968 11:53:45.950332 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10969 11:53:45.985882 <46>[ 22.514644] systemd-journald[298]: Received client request to flush runtime journal.
10970 11:53:46.842259 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10971 11:53:46.855949 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10972 11:53:46.871375 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10973 11:53:46.914316 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10974 11:53:47.407498 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10975 11:53:47.443968 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10976 11:53:47.525486 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10977 11:53:47.605359 Starting [0;1;39mNetwork Service[0m...
10978 11:53:47.925519 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10979 11:53:47.944443 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10980 11:53:47.988663 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10981 11:53:48.230377 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10982 11:53:48.250022 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10983 11:53:48.316208 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10984 11:53:48.332264 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10985 11:53:48.352655 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10986 11:53:48.387293 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10987 11:53:48.444112 Starting [0;1;39mNetwork Name Resolution[0m...
10988 11:53:48.473686 Starting [0;1;39mNetwork Time Synchronization[0m...
10989 11:53:48.492047 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10990 11:53:48.508047 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10991 11:53:48.562790 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10992 11:53:48.741902 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10993 11:53:48.763283 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10994 11:53:48.782288 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10995 11:53:48.794252 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10996 11:53:48.810744 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10997 11:53:48.930661 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10998 11:53:48.964107 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10999 11:53:48.998064 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11000 11:53:49.017463 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11001 11:53:49.030619 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11002 11:53:49.151750 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11003 11:53:49.162310 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11004 11:53:49.182854 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11005 11:53:49.235369 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11006 11:53:49.846897 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11007 11:53:50.171322 Starting [0;1;39mUser Login Management[0m...
11008 11:53:50.188414 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11009 11:53:50.209071 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11010 11:53:50.225699 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11011 11:53:50.270994 Starting [0;1;39mPermit User Sessions[0m...
11012 11:53:50.409271 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11013 11:53:50.455172 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11014 11:53:50.499872 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11015 11:53:50.507826 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11016 11:53:50.529503 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11017 11:53:50.549127 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11018 11:53:50.572753 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11019 11:53:50.591196 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11020 11:53:50.644196 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11021 11:53:50.693101 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11022 11:53:50.802665
11023 11:53:50.802827
11024 11:53:50.805540 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11025 11:53:50.805641
11026 11:53:50.808824 debian-bullseye-arm64 login: root (automatic login)
11027 11:53:50.808930
11028 11:53:50.809019
11029 11:53:51.160651 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
11030 11:53:51.160820
11031 11:53:51.167442 The programs included with the Debian GNU/Linux system are free software;
11032 11:53:51.174125 the exact distribution terms for each program are described in the
11033 11:53:51.177447 individual files in /usr/share/doc/*/copyright.
11034 11:53:51.177554
11035 11:53:51.183887 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11036 11:53:51.187298 permitted by applicable law.
11037 11:53:52.281518 Matched prompt #10: / #
11039 11:53:52.281889 Setting prompt string to ['/ #']
11040 11:53:52.282009 end: 2.2.5.1 login-action (duration 00:00:30) [common]
11042 11:53:52.282207 end: 2.2.5 auto-login-action (duration 00:00:30) [common]
11043 11:53:52.282301 start: 2.2.6 expect-shell-connection (timeout 00:03:08) [common]
11044 11:53:52.282399 Setting prompt string to ['/ #']
11045 11:53:52.282487 Forcing a shell prompt, looking for ['/ #']
11047 11:53:52.332733 / #
11048 11:53:52.332869 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11049 11:53:52.332978 Waiting using forced prompt support (timeout 00:02:30)
11050 11:53:52.337907
11051 11:53:52.338212 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11052 11:53:52.338334 start: 2.2.7 export-device-env (timeout 00:03:08) [common]
11054 11:53:52.438676 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj'
11055 11:53:52.443883 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066512/extract-nfsrootfs-8sggwipj'
11057 11:53:52.544393 / # export NFS_SERVER_IP='192.168.201.1'
11058 11:53:52.549455 export NFS_SERVER_IP='192.168.201.1'
11059 11:53:52.549758 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11060 11:53:52.549887 end: 2.2 depthcharge-retry (duration 00:01:52) [common]
11061 11:53:52.550018 end: 2 depthcharge-action (duration 00:01:52) [common]
11062 11:53:52.550140 start: 3 lava-test-retry (timeout 00:07:11) [common]
11063 11:53:52.550265 start: 3.1 lava-test-shell (timeout 00:07:11) [common]
11064 11:53:52.550365 Using namespace: common
11066 11:53:52.650707 / # #
11067 11:53:52.650902 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11068 11:53:52.655712 #
11069 11:53:52.656006 Using /lava-12066512
11071 11:53:52.756341 / # export SHELL=/bin/bash
11072 11:53:52.761471 export SHELL=/bin/bash
11074 11:53:52.861976 / # . /lava-12066512/environment
11075 11:53:52.866824 . /lava-12066512/environment
11077 11:53:52.973417 / # /lava-12066512/bin/lava-test-runner /lava-12066512/0
11078 11:53:52.973562 Test shell timeout: 10s (minimum of the action and connection timeout)
11079 11:53:52.978809 /lava-12066512/bin/lava-test-runner /lava-12066512/0
11080 11:53:53.277240 + export TESTRUN_ID=0_timesync-off
11081 11:53:53.279983 + TESTRUN_ID=0_timesync-off
11082 11:53:53.283328 + cd /lava-12066512/0/tests/0_timesync-off
11083 11:53:53.286571 ++ cat uuid
11084 11:53:53.291071 + UUID=12066512_1.6.2.3.1
11085 11:53:53.291180 + set +x
11086 11:53:53.297956 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12066512_1.6.2.3.1>
11087 11:53:53.298228 Received signal: <STARTRUN> 0_timesync-off 12066512_1.6.2.3.1
11088 11:53:53.298335 Starting test lava.0_timesync-off (12066512_1.6.2.3.1)
11089 11:53:53.298454 Skipping test definition patterns.
11090 11:53:53.300954 + systemctl stop systemd-timesyncd
11091 11:53:53.357224 + set +x
11092 11:53:53.360399 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12066512_1.6.2.3.1>
11093 11:53:53.360679 Received signal: <ENDRUN> 0_timesync-off 12066512_1.6.2.3.1
11094 11:53:53.360791 Ending use of test pattern.
11095 11:53:53.360889 Ending test lava.0_timesync-off (12066512_1.6.2.3.1), duration 0.06
11097 11:53:53.448104 + export TESTRUN_ID=1_kselftest-arm64
11098 11:53:53.448242 + TESTRUN_ID=1_kselftest-arm64
11099 11:53:53.455025 + cd /lava-12066512/0/tests/1_kselftest-arm64
11100 11:53:53.455108 ++ cat uuid
11101 11:53:53.460052 + UUID=12066512_1.6.2.3.5
11102 11:53:53.460135 + set +x
11103 11:53:53.466620 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 12066512_1.6.2.3.5>
11104 11:53:53.466885 Received signal: <STARTRUN> 1_kselftest-arm64 12066512_1.6.2.3.5
11105 11:53:53.466986 Starting test lava.1_kselftest-arm64 (12066512_1.6.2.3.5)
11106 11:53:53.467097 Skipping test definition patterns.
11107 11:53:53.469898 + cd ./automated/linux/kselftest/
11108 11:53:53.496320 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11109 11:53:53.543948 INFO: install_deps skipped
11110 11:53:53.667544 --2023-11-23 11:53:53-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11111 11:53:53.704908 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11112 11:53:53.838583 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11113 11:53:53.974200 HTTP request sent, awaiting response... 200 OK
11114 11:53:53.977551 Length: 2962844 (2.8M) [application/octet-stream]
11115 11:53:53.980763 Saving to: 'kselftest.tar.xz'
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11128 11:53:55.896882
11129 11:54:01.934822 skiplist:
11130 11:54:01.938250 ========================================
11131 11:54:01.941241 ========================================
11132 11:54:01.987690 arm64:tags_test
11133 11:54:01.991452 arm64:run_tags_test.sh
11134 11:54:01.991554 arm64:fake_sigreturn_bad_magic
11135 11:54:01.994235 arm64:fake_sigreturn_bad_size
11136 11:54:01.997854 arm64:fake_sigreturn_bad_size_for_magic0
11137 11:54:02.001490 arm64:fake_sigreturn_duplicated_fpsimd
11138 11:54:02.004626 arm64:fake_sigreturn_misaligned_sp
11139 11:54:02.007754 arm64:fake_sigreturn_missing_fpsimd
11140 11:54:02.011488 arm64:fake_sigreturn_sme_change_vl
11141 11:54:02.014540 arm64:fake_sigreturn_sve_change_vl
11142 11:54:02.017606 arm64:mangle_pstate_invalid_compat_toggle
11143 11:54:02.021284 arm64:mangle_pstate_invalid_daif_bits
11144 11:54:02.024513 arm64:mangle_pstate_invalid_mode_el1h
11145 11:54:02.028046 arm64:mangle_pstate_invalid_mode_el1t
11146 11:54:02.031153 arm64:mangle_pstate_invalid_mode_el2h
11147 11:54:02.034484 arm64:mangle_pstate_invalid_mode_el2t
11148 11:54:02.037701 arm64:mangle_pstate_invalid_mode_el3h
11149 11:54:02.041145 arm64:mangle_pstate_invalid_mode_el3t
11150 11:54:02.044183 arm64:sme_trap_no_sm
11151 11:54:02.047603 arm64:sme_trap_non_streaming
11152 11:54:02.047716 arm64:sme_trap_za
11153 11:54:02.050830 arm64:sme_vl
11154 11:54:02.050934 arm64:ssve_regs
11155 11:54:02.050999 arm64:sve_regs
11156 11:54:02.054867 arm64:sve_vl
11157 11:54:02.054951 arm64:za_no_regs
11158 11:54:02.057660 arm64:za_regs
11159 11:54:02.057764 arm64:pac
11160 11:54:02.057845 arm64:fp-stress
11161 11:54:02.060972 arm64:sve-ptrace
11162 11:54:02.061053 arm64:sve-probe-vls
11163 11:54:02.064691 arm64:vec-syscfg
11164 11:54:02.064789 arm64:za-fork
11165 11:54:02.067535 arm64:za-ptrace
11166 11:54:02.067619 arm64:check_buffer_fill
11167 11:54:02.071154 arm64:check_child_memory
11168 11:54:02.074068 arm64:check_gcr_el1_cswitch
11169 11:54:02.077648 arm64:check_ksm_options
11170 11:54:02.077732 arm64:check_mmap_options
11171 11:54:02.081554 arm64:check_prctl
11172 11:54:02.081636 arm64:check_tags_inclusion
11173 11:54:02.084454 arm64:check_user_mem
11174 11:54:02.084535 arm64:btitest
11175 11:54:02.087626 arm64:nobtitest
11176 11:54:02.087711 arm64:hwcap
11177 11:54:02.090733 arm64:ptrace
11178 11:54:02.090829 arm64:syscall-abi
11179 11:54:02.090919 arm64:tpidr2
11180 11:54:02.097455 ============== Tests to run ===============
11181 11:54:02.097568 arm64:tags_test
11182 11:54:02.100998 arm64:run_tags_test.sh
11183 11:54:02.101097 arm64:fake_sigreturn_bad_magic
11184 11:54:02.104440 arm64:fake_sigreturn_bad_size
11185 11:54:02.107284 arm64:fake_sigreturn_bad_size_for_magic0
11186 11:54:02.110612 arm64:fake_sigreturn_duplicated_fpsimd
11187 11:54:02.114080 arm64:fake_sigreturn_misaligned_sp
11188 11:54:02.117434 arm64:fake_sigreturn_missing_fpsimd
11189 11:54:02.120774 arm64:fake_sigreturn_sme_change_vl
11190 11:54:02.124202 arm64:fake_sigreturn_sve_change_vl
11191 11:54:02.127419 arm64:mangle_pstate_invalid_compat_toggle
11192 11:54:02.130656 arm64:mangle_pstate_invalid_daif_bits
11193 11:54:02.134185 arm64:mangle_pstate_invalid_mode_el1h
11194 11:54:02.137896 arm64:mangle_pstate_invalid_mode_el1t
11195 11:54:02.141016 arm64:mangle_pstate_invalid_mode_el2h
11196 11:54:02.144227 arm64:mangle_pstate_invalid_mode_el2t
11197 11:54:02.147569 arm64:mangle_pstate_invalid_mode_el3h
11198 11:54:02.150512 arm64:mangle_pstate_invalid_mode_el3t
11199 11:54:02.154225 arm64:sme_trap_no_sm
11200 11:54:02.157652 arm64:sme_trap_non_streaming
11201 11:54:02.157732 arm64:sme_trap_za
11202 11:54:02.160536 arm64:sme_vl
11203 11:54:02.160616 arm64:ssve_regs
11204 11:54:02.163953 arm64:sve_regs
11205 11:54:02.164033 arm64:sve_vl
11206 11:54:02.164096 arm64:za_no_regs
11207 11:54:02.167327 arm64:za_regs
11208 11:54:02.167406 arm64:pac
11209 11:54:02.170325 arm64:fp-stress
11210 11:54:02.170433 arm64:sve-ptrace
11211 11:54:02.173734 arm64:sve-probe-vls
11212 11:54:02.173836 arm64:vec-syscfg
11213 11:54:02.173923 arm64:za-fork
11214 11:54:02.177145 arm64:za-ptrace
11215 11:54:02.177246 arm64:check_buffer_fill
11216 11:54:02.180460 arm64:check_child_memory
11217 11:54:02.183900 arm64:check_gcr_el1_cswitch
11218 11:54:02.187377 arm64:check_ksm_options
11219 11:54:02.187472 arm64:check_mmap_options
11220 11:54:02.190624 arm64:check_prctl
11221 11:54:02.190721 arm64:check_tags_inclusion
11222 11:54:02.193586 arm64:check_user_mem
11223 11:54:02.193681 arm64:btitest
11224 11:54:02.197120 arm64:nobtitest
11225 11:54:02.197219 arm64:hwcap
11226 11:54:02.200345 arm64:ptrace
11227 11:54:02.200445 arm64:syscall-abi
11228 11:54:02.200540 arm64:tpidr2
11229 11:54:02.207082 ===========End Tests to run ===============
11230 11:54:02.207168 shardfile-arm64 pass
11231 11:54:02.499447 <12>[ 39.033545] kselftest: Running tests in arm64
11232 11:54:02.510425 TAP version 13
11233 11:54:02.523453 1..48
11234 11:54:02.542509 # selftests: arm64: tags_test
11235 11:54:02.990826 ok 1 selftests: arm64: tags_test
11236 11:54:03.008094 # selftests: arm64: run_tags_test.sh
11237 11:54:03.067820 # --------------------
11238 11:54:03.070832 # running tags test
11239 11:54:03.070954 # --------------------
11240 11:54:03.074454 # [PASS]
11241 11:54:03.077528 ok 2 selftests: arm64: run_tags_test.sh
11242 11:54:03.091093 # selftests: arm64: fake_sigreturn_bad_magic
11243 11:54:03.144663 # Registered handlers for all signals.
11244 11:54:03.144808 # Detected MINSTKSIGSZ:4720
11245 11:54:03.147779 # Testcase initialized.
11246 11:54:03.151006 # uc context validated.
11247 11:54:03.154344 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11248 11:54:03.157528 # Handled SIG_COPYCTX
11249 11:54:03.157611 # Available space:3568
11250 11:54:03.164539 # Using badly built context - ERR: BAD MAGIC !
11251 11:54:03.171294 # SIG_OK -- SP:0xFFFFF7126E60 si_addr@:0xfffff7126e60 si_code:2 token@:0xfffff7125c00 offset:-4704
11252 11:54:03.174506 # ==>> completed. PASS(1)
11253 11:54:03.180816 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11254 11:54:03.187700 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF7125C00
11255 11:54:03.191414 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11256 11:54:03.197624 # selftests: arm64: fake_sigreturn_bad_size
11257 11:54:03.206056 # Registered handlers for all signals.
11258 11:54:03.206153 # Detected MINSTKSIGSZ:4720
11259 11:54:03.209749 # Testcase initialized.
11260 11:54:03.212614 # uc context validated.
11261 11:54:03.216213 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11262 11:54:03.219390 # Handled SIG_COPYCTX
11263 11:54:03.219472 # Available space:3568
11264 11:54:03.222634 # uc context validated.
11265 11:54:03.229631 # Using badly built context - ERR: Bad size for esr_context
11266 11:54:03.236072 # SIG_OK -- SP:0xFFFFCF399640 si_addr@:0xffffcf399640 si_code:2 token@:0xffffcf3983e0 offset:-4704
11267 11:54:03.239659 # ==>> completed. PASS(1)
11268 11:54:03.245991 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11269 11:54:03.252921 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFCF3983E0
11270 11:54:03.256193 ok 4 selftests: arm64: fake_sigreturn_bad_size
11271 11:54:03.262520 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11272 11:54:03.304512 # Registered handlers for all signals.
11273 11:54:03.307781 # Detected MINSTKSIGSZ:4720
11274 11:54:03.311155 # Testcase initialized.
11275 11:54:03.314719 # uc context validated.
11276 11:54:03.317675 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11277 11:54:03.321065 # Handled SIG_COPYCTX
11278 11:54:03.321167 # Available space:3568
11279 11:54:03.327703 # Using badly built context - ERR: Bad size for terminator
11280 11:54:03.337963 # SIG_OK -- SP:0xFFFFF8B72670 si_addr@:0xfffff8b72670 si_code:2 token@:0xfffff8b71410 offset:-4704
11281 11:54:03.338121 # ==>> completed. PASS(1)
11282 11:54:03.347858 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11283 11:54:03.354259 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF8B71410
11284 11:54:03.358073 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11285 11:54:03.364367 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11286 11:54:03.388268 # Registered handlers for all signals.
11287 11:54:03.388411 # Detected MINSTKSIGSZ:4720
11288 11:54:03.391128 # Testcase initialized.
11289 11:54:03.394465 # uc context validated.
11290 11:54:03.397893 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11291 11:54:03.400997 # Handled SIG_COPYCTX
11292 11:54:03.401082 # Available space:3568
11293 11:54:03.407967 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11294 11:54:03.417485 # SIG_OK -- SP:0xFFFFD30B36A0 si_addr@:0xffffd30b36a0 si_code:2 token@:0xffffd30b2440 offset:-4704
11295 11:54:03.417610 # ==>> completed. PASS(1)
11296 11:54:03.427870 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11297 11:54:03.434455 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD30B2440
11298 11:54:03.437628 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11299 11:54:03.441226 # selftests: arm64: fake_sigreturn_misaligned_sp
11300 11:54:03.489740 # Registered handlers for all signals.
11301 11:54:03.489881 # Detected MINSTKSIGSZ:4720
11302 11:54:03.492861 # Testcase initialized.
11303 11:54:03.496267 # uc context validated.
11304 11:54:03.500039 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11305 11:54:03.503243 # Handled SIG_COPYCTX
11306 11:54:03.509907 # SIG_OK -- SP:0xFFFFD6A92053 si_addr@:0xffffd6a92053 si_code:2 token@:0xffffd6a92053 offset:0
11307 11:54:03.512972 # ==>> completed. PASS(1)
11308 11:54:03.519693 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11309 11:54:03.526287 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD6A92053
11310 11:54:03.533064 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11311 11:54:03.536532 # selftests: arm64: fake_sigreturn_missing_fpsimd
11312 11:54:03.581234 # Registered handlers for all signals.
11313 11:54:03.581381 # Detected MINSTKSIGSZ:4720
11314 11:54:03.583854 # Testcase initialized.
11315 11:54:03.587428 # uc context validated.
11316 11:54:03.591021 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11317 11:54:03.594093 # Handled SIG_COPYCTX
11318 11:54:03.597245 # Mangling template header. Spare space:4096
11319 11:54:03.600974 # Using badly built context - ERR: Missing FPSIMD
11320 11:54:03.610239 # SIG_OK -- SP:0xFFFFF3920670 si_addr@:0xfffff3920670 si_code:2 token@:0xfffff391f410 offset:-4704
11321 11:54:03.614034 # ==>> completed. PASS(1)
11322 11:54:03.620425 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11323 11:54:03.627197 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFF391F410
11324 11:54:03.630290 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11325 11:54:03.637217 # selftests: arm64: fake_sigreturn_sme_change_vl
11326 11:54:03.674671 # Registered handlers for all signals.
11327 11:54:03.674833 # Detected MINSTKSIGSZ:4720
11328 11:54:03.677708 # ==>> completed. SKIP.
11329 11:54:03.684554 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11330 11:54:03.688089 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11331 11:54:03.697722 # selftests: arm64: fake_sigreturn_sve_change_vl
11332 11:54:03.765095 # Registered handlers for all signals.
11333 11:54:03.765277 # Detected MINSTKSIGSZ:4720
11334 11:54:03.768422 # ==>> completed. SKIP.
11335 11:54:03.772219 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11336 11:54:03.778844 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11337 11:54:03.788418 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11338 11:54:03.859522 # Registered handlers for all signals.
11339 11:54:03.859666 # Detected MINSTKSIGSZ:4720
11340 11:54:03.862531 # Testcase initialized.
11341 11:54:03.866346 # uc context validated.
11342 11:54:03.866428 # Handled SIG_TRIG
11343 11:54:03.876002 # SIG_OK -- SP:0xFFFFD166A420 si_addr@:0xffffd166a420 si_code:2 token@:(nil) offset:-281474194908192
11344 11:54:03.879580 # ==>> completed. PASS(1)
11345 11:54:03.886198 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11346 11:54:03.892870 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11347 11:54:03.895883 # selftests: arm64: mangle_pstate_invalid_daif_bits
11348 11:54:03.940300 # Registered handlers for all signals.
11349 11:54:03.940473 # Detected MINSTKSIGSZ:4720
11350 11:54:03.943516 # Testcase initialized.
11351 11:54:03.946754 # uc context validated.
11352 11:54:03.946829 # Handled SIG_TRIG
11353 11:54:03.956641 # SIG_OK -- SP:0xFFFFD5CD33D0 si_addr@:0xffffd5cd33d0 si_code:2 token@:(nil) offset:-281474268738512
11354 11:54:03.960075 # ==>> completed. PASS(1)
11355 11:54:03.966610 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11356 11:54:03.970306 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11357 11:54:03.976596 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11358 11:54:04.032475 # Registered handlers for all signals.
11359 11:54:04.032620 # Detected MINSTKSIGSZ:4720
11360 11:54:04.036258 # Testcase initialized.
11361 11:54:04.039195 # uc context validated.
11362 11:54:04.039278 # Handled SIG_TRIG
11363 11:54:04.049240 # SIG_OK -- SP:0xFFFFF28B4E20 si_addr@:0xfffff28b4e20 si_code:2 token@:(nil) offset:-281474750959136
11364 11:54:04.052913 # ==>> completed. PASS(1)
11365 11:54:04.059442 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11366 11:54:04.062508 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11367 11:54:04.066045 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11368 11:54:04.126209 # Registered handlers for all signals.
11369 11:54:04.126356 # Detected MINSTKSIGSZ:4720
11370 11:54:04.129250 # Testcase initialized.
11371 11:54:04.132353 # uc context validated.
11372 11:54:04.132434 # Handled SIG_TRIG
11373 11:54:04.142630 # SIG_OK -- SP:0xFFFFD62384E0 si_addr@:0xffffd62384e0 si_code:2 token@:(nil) offset:-281474274395360
11374 11:54:04.146155 # ==>> completed. PASS(1)
11375 11:54:04.152807 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11376 11:54:04.155899 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11377 11:54:04.162198 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11378 11:54:04.215400 # Registered handlers for all signals.
11379 11:54:04.215545 # Detected MINSTKSIGSZ:4720
11380 11:54:04.218550 # Testcase initialized.
11381 11:54:04.221988 # uc context validated.
11382 11:54:04.222069 # Handled SIG_TRIG
11383 11:54:04.231801 # SIG_OK -- SP:0xFFFFDDF34030 si_addr@:0xffffddf34030 si_code:2 token@:(nil) offset:-281474405449776
11384 11:54:04.235253 # ==>> completed. PASS(1)
11385 11:54:04.241784 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11386 11:54:04.245508 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11387 11:54:04.248664 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11388 11:54:04.290620 # Registered handlers for all signals.
11389 11:54:04.290759 # Detected MINSTKSIGSZ:4720
11390 11:54:04.293667 # Testcase initialized.
11391 11:54:04.297160 # uc context validated.
11392 11:54:04.297242 # Handled SIG_TRIG
11393 11:54:04.307059 # SIG_OK -- SP:0xFFFFCECE9670 si_addr@:0xffffcece9670 si_code:2 token@:(nil) offset:-281474151388784
11394 11:54:04.310378 # ==>> completed. PASS(1)
11395 11:54:04.317219 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11396 11:54:04.320461 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11397 11:54:04.327015 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11398 11:54:04.367887 # Registered handlers for all signals.
11399 11:54:04.368026 # Detected MINSTKSIGSZ:4720
11400 11:54:04.370606 # Testcase initialized.
11401 11:54:04.374169 # uc context validated.
11402 11:54:04.374251 # Handled SIG_TRIG
11403 11:54:04.383971 # SIG_OK -- SP:0xFFFFDA1AC4B0 si_addr@:0xffffda1ac4b0 si_code:2 token@:(nil) offset:-281474340930736
11404 11:54:04.387059 # ==>> completed. PASS(1)
11405 11:54:04.394363 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11406 11:54:04.397026 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11407 11:54:04.403656 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11408 11:54:04.443290 # Registered handlers for all signals.
11409 11:54:04.443420 # Detected MINSTKSIGSZ:4720
11410 11:54:04.446639 # Testcase initialized.
11411 11:54:04.449736 # uc context validated.
11412 11:54:04.449824 # Handled SIG_TRIG
11413 11:54:04.459918 # SIG_OK -- SP:0xFFFFC9EB6B10 si_addr@:0xffffc9eb6b10 si_code:2 token@:(nil) offset:-281474069392144
11414 11:54:04.463312 # ==>> completed. PASS(1)
11415 11:54:04.470223 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11416 11:54:04.473199 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11417 11:54:04.476377 # selftests: arm64: sme_trap_no_sm
11418 11:54:04.527425 # Registered handlers for all signals.
11419 11:54:04.527552 # Detected MINSTKSIGSZ:4720
11420 11:54:04.530558 # ==>> completed. SKIP.
11421 11:54:04.540452 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11422 11:54:04.543822 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11423 11:54:04.546795 # selftests: arm64: sme_trap_non_streaming
11424 11:54:04.605589 # Registered handlers for all signals.
11425 11:54:04.605735 # Detected MINSTKSIGSZ:4720
11426 11:54:04.608992 # ==>> completed. SKIP.
11427 11:54:04.618615 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11428 11:54:04.625674 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11429 11:54:04.628821 # selftests: arm64: sme_trap_za
11430 11:54:04.688468 # Registered handlers for all signals.
11431 11:54:04.688601 # Detected MINSTKSIGSZ:4720
11432 11:54:04.691312 # Testcase initialized.
11433 11:54:04.701300 # SIG_OK -- SP:0xFFFFD50BECA0 si_addr@:0xaaaab3f12510 si_code:1 token@:(nil) offset:-187650140087568
11434 11:54:04.701393 # ==>> completed. PASS(1)
11435 11:54:04.707863 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11436 11:54:04.711495 ok 21 selftests: arm64: sme_trap_za
11437 11:54:04.714699 # selftests: arm64: sme_vl
11438 11:54:04.764094 # Registered handlers for all signals.
11439 11:54:04.764226 # Detected MINSTKSIGSZ:4720
11440 11:54:04.766805 # ==>> completed. SKIP.
11441 11:54:04.770388 # # SME VL :: Check that we get the right SME VL reported
11442 11:54:04.773821 ok 22 selftests: arm64: sme_vl # SKIP
11443 11:54:04.782212 # selftests: arm64: ssve_regs
11444 11:54:04.829187 # Registered handlers for all signals.
11445 11:54:04.829320 # Detected MINSTKSIGSZ:4720
11446 11:54:04.832526 # ==>> completed. SKIP.
11447 11:54:04.839047 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11448 11:54:04.845854 ok 23 selftests: arm64: ssve_regs # SKIP
11449 11:54:04.848662 # selftests: arm64: sve_regs
11450 11:54:04.907848 # Registered handlers for all signals.
11451 11:54:04.907984 # Detected MINSTKSIGSZ:4720
11452 11:54:04.910773 # ==>> completed. SKIP.
11453 11:54:04.917835 # # SVE registers :: Check that we get the right SVE registers reported
11454 11:54:04.920864 ok 24 selftests: arm64: sve_regs # SKIP
11455 11:54:04.926927 # selftests: arm64: sve_vl
11456 11:54:05.011080 # Registered handlers for all signals.
11457 11:54:05.011217 # Detected MINSTKSIGSZ:4720
11458 11:54:05.014668 # ==>> completed. SKIP.
11459 11:54:05.021488 # # SVE VL :: Check that we get the right SVE VL reported
11460 11:54:05.024186 ok 25 selftests: arm64: sve_vl # SKIP
11461 11:54:05.031427 # selftests: arm64: za_no_regs
11462 11:54:05.095267 # Registered handlers for all signals.
11463 11:54:05.095398 # Detected MINSTKSIGSZ:4720
11464 11:54:05.098491 # ==>> completed. SKIP.
11465 11:54:05.105597 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11466 11:54:05.108454 ok 26 selftests: arm64: za_no_regs # SKIP
11467 11:54:05.112881 # selftests: arm64: za_regs
11468 11:54:05.183836 # Registered handlers for all signals.
11469 11:54:05.183971 # Detected MINSTKSIGSZ:4720
11470 11:54:05.186880 # ==>> completed. SKIP.
11471 11:54:05.193747 # # ZA register :: Check that we get the right ZA registers reported
11472 11:54:05.197340 ok 27 selftests: arm64: za_regs # SKIP
11473 11:54:05.204367 # selftests: arm64: pac
11474 11:54:05.266769 # TAP version 13
11475 11:54:05.266936 # 1..7
11476 11:54:05.269898 # # Starting 7 tests from 1 test cases.
11477 11:54:05.273606 # # RUN global.corrupt_pac ...
11478 11:54:05.276919 # # SKIP PAUTH not enabled
11479 11:54:05.279643 # # OK global.corrupt_pac
11480 11:54:05.282903 # ok 1 # SKIP PAUTH not enabled
11481 11:54:05.290173 # # RUN global.pac_instructions_not_nop ...
11482 11:54:05.293145 # # SKIP PAUTH not enabled
11483 11:54:05.296168 # # OK global.pac_instructions_not_nop
11484 11:54:05.299780 # ok 2 # SKIP PAUTH not enabled
11485 11:54:05.306348 # # RUN global.pac_instructions_not_nop_generic ...
11486 11:54:05.309709 # # SKIP Generic PAUTH not enabled
11487 11:54:05.313207 # # OK global.pac_instructions_not_nop_generic
11488 11:54:05.316333 # ok 3 # SKIP Generic PAUTH not enabled
11489 11:54:05.322847 # # RUN global.single_thread_different_keys ...
11490 11:54:05.326234 # # SKIP PAUTH not enabled
11491 11:54:05.329650 # # OK global.single_thread_different_keys
11492 11:54:05.332717 # ok 4 # SKIP PAUTH not enabled
11493 11:54:05.339464 # # RUN global.exec_changed_keys ...
11494 11:54:05.342761 # # SKIP PAUTH not enabled
11495 11:54:05.346827 # # OK global.exec_changed_keys
11496 11:54:05.349647 # ok 5 # SKIP PAUTH not enabled
11497 11:54:05.353100 # # RUN global.context_switch_keep_keys ...
11498 11:54:05.356226 # # SKIP PAUTH not enabled
11499 11:54:05.359316 # # OK global.context_switch_keep_keys
11500 11:54:05.362871 # ok 6 # SKIP PAUTH not enabled
11501 11:54:05.369994 # # RUN global.context_switch_keep_keys_generic ...
11502 11:54:05.372854 # # SKIP Generic PAUTH not enabled
11503 11:54:05.379565 # # OK global.context_switch_keep_keys_generic
11504 11:54:05.383066 # ok 7 # SKIP Generic PAUTH not enabled
11505 11:54:05.385928 # # PASSED: 7 / 7 tests passed.
11506 11:54:05.389164 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11507 11:54:05.392568 ok 28 selftests: arm64: pac
11508 11:54:05.396119 # selftests: arm64: fp-stress
11509 11:54:09.621133 <6>[ 46.158661] vpu: disabling
11510 11:54:09.623859 <6>[ 46.161709] vproc2: disabling
11511 11:54:09.627402 <6>[ 46.165256] vproc1: disabling
11512 11:54:09.630589 <6>[ 46.168534] vaud18: disabling
11513 11:54:09.637501 <6>[ 46.171956] vsram_others: disabling
11514 11:54:09.640856 <6>[ 46.175840] va09: disabling
11515 11:54:09.644383 <6>[ 46.178955] vsram_md: disabling
11516 11:54:09.647052 <6>[ 46.182447] Vgpu: disabling
11517 11:54:15.342068 # TAP version 13
11518 11:54:15.342638 # 1..16
11519 11:54:15.345175 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11520 11:54:15.348582 # # Will run for 10s
11521 11:54:15.349134 # # Started FPSIMD-0-0
11522 11:54:15.352115 # # Started FPSIMD-0-1
11523 11:54:15.355538 # # Started FPSIMD-1-0
11524 11:54:15.355999 # # Started FPSIMD-1-1
11525 11:54:15.358547 # # Started FPSIMD-2-0
11526 11:54:15.359022 # # Started FPSIMD-2-1
11527 11:54:15.361820 # # Started FPSIMD-3-0
11528 11:54:15.365448 # # Started FPSIMD-3-1
11529 11:54:15.365964 # # Started FPSIMD-4-0
11530 11:54:15.368499 # # Started FPSIMD-4-1
11531 11:54:15.371740 # # Started FPSIMD-5-0
11532 11:54:15.372201 # # Started FPSIMD-5-1
11533 11:54:15.375279 # # Started FPSIMD-6-0
11534 11:54:15.375748 # # Started FPSIMD-6-1
11535 11:54:15.378283 # # Started FPSIMD-7-0
11536 11:54:15.381693 # # Started FPSIMD-7-1
11537 11:54:15.384971 # # FPSIMD-0-0: Vector length: 128 bits
11538 11:54:15.385391 # # FPSIMD-0-0: PID: 1163
11539 11:54:15.391431 # # FPSIMD-0-1: Vector length: 128 bits
11540 11:54:15.391850 # # FPSIMD-0-1: PID: 1164
11541 11:54:15.394941 # # FPSIMD-1-0: Vector length: 128 bits
11542 11:54:15.398283 # # FPSIMD-1-0: PID: 1165
11543 11:54:15.402057 # # FPSIMD-2-0: Vector length: 128 bits
11544 11:54:15.405088 # # FPSIMD-2-0: PID: 1167
11545 11:54:15.408131 # # FPSIMD-2-1: Vector length: 128 bits
11546 11:54:15.411564 # # FPSIMD-2-1: PID: 1168
11547 11:54:15.414947 # # FPSIMD-3-1: Vector length: 128 bits
11548 11:54:15.418586 # # FPSIMD-1-1: Vector length: 128 bits
11549 11:54:15.419064 # # FPSIMD-1-1: PID: 1166
11550 11:54:15.421425 # # FPSIMD-3-1: PID: 1170
11551 11:54:15.424521 # # FPSIMD-6-1: Vector length: 128 bits
11552 11:54:15.428029 # # FPSIMD-6-1: PID: 1176
11553 11:54:15.431763 # # FPSIMD-5-0: Vector length: 128 bits
11554 11:54:15.435048 # # FPSIMD-5-1: Vector length: 128 bits
11555 11:54:15.438590 # # FPSIMD-5-0: PID: 1173
11556 11:54:15.439146 # # FPSIMD-5-1: PID: 1174
11557 11:54:15.444753 # # FPSIMD-3-0: Vector length: 128 bits
11558 11:54:15.445172 # # FPSIMD-3-0: PID: 1169
11559 11:54:15.448026 # # FPSIMD-7-1: Vector length: 128 bits
11560 11:54:15.451193 # # FPSIMD-7-1: PID: 1178
11561 11:54:15.454670 # # FPSIMD-4-1: Vector length: 128 bits
11562 11:54:15.457952 # # FPSIMD-4-1: PID: 1172
11563 11:54:15.461101 # # FPSIMD-6-0: Vector length: 128 bits
11564 11:54:15.464968 # # FPSIMD-6-0: PID: 1175
11565 11:54:15.468274 # # FPSIMD-4-0: Vector length: 128 bits
11566 11:54:15.468698 # # FPSIMD-4-0: PID: 1171
11567 11:54:15.471084 # # FPSIMD-7-0: Vector length: 128 bits
11568 11:54:15.474667 # # FPSIMD-7-0: PID: 1177
11569 11:54:15.478459 # # Finishing up...
11570 11:54:15.484482 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=1032876, signals=10
11571 11:54:15.491405 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1355453, signals=10
11572 11:54:15.497885 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=1271513, signals=10
11573 11:54:15.504538 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1963974, signals=10
11574 11:54:15.514436 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=944042, signals=10
11575 11:54:15.520987 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=2153425, signals=10
11576 11:54:15.527750 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=995908, signals=10
11577 11:54:15.528202 # ok 1 FPSIMD-0-0
11578 11:54:15.531236 # ok 2 FPSIMD-0-1
11579 11:54:15.531848 # ok 3 FPSIMD-1-0
11580 11:54:15.534582 # ok 4 FPSIMD-1-1
11581 11:54:15.535135 # ok 5 FPSIMD-2-0
11582 11:54:15.537882 # ok 6 FPSIMD-2-1
11583 11:54:15.538298 # ok 7 FPSIMD-3-0
11584 11:54:15.541327 # ok 8 FPSIMD-3-1
11585 11:54:15.541835 # ok 9 FPSIMD-4-0
11586 11:54:15.544642 # ok 10 FPSIMD-4-1
11587 11:54:15.545153 # ok 11 FPSIMD-5-0
11588 11:54:15.548181 # ok 12 FPSIMD-5-1
11589 11:54:15.548597 # ok 13 FPSIMD-6-0
11590 11:54:15.550904 # ok 14 FPSIMD-6-1
11591 11:54:15.551328 # ok 15 FPSIMD-7-0
11592 11:54:15.554536 # ok 16 FPSIMD-7-1
11593 11:54:15.560892 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=1029559, signals=9
11594 11:54:15.567681 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=986766, signals=9
11595 11:54:15.574404 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=1631107, signals=10
11596 11:54:15.584198 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=1047693, signals=10
11597 11:54:15.590755 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=999277, signals=10
11598 11:54:15.597826 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=1476775, signals=10
11599 11:54:15.604156 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=1329599, signals=10
11600 11:54:15.610765 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1209321, signals=10
11601 11:54:15.617440 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=990767, signals=9
11602 11:54:15.624277 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11603 11:54:15.627516 ok 29 selftests: arm64: fp-stress
11604 11:54:15.630631 # selftests: arm64: sve-ptrace
11605 11:54:15.631203 # TAP version 13
11606 11:54:15.631542 # 1..4104
11607 11:54:15.634283 # ok 2 # SKIP SVE not available
11608 11:54:15.637486 # # Planned tests != run tests (4104 != 1)
11609 11:54:15.643860 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11610 11:54:15.647145 ok 30 selftests: arm64: sve-ptrace # SKIP
11611 11:54:15.650589 # selftests: arm64: sve-probe-vls
11612 11:54:15.651072 # TAP version 13
11613 11:54:15.653938 # 1..2
11614 11:54:15.657451 # ok 2 # SKIP SVE not available
11615 11:54:15.660388 # # Planned tests != run tests (2 != 1)
11616 11:54:15.664075 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11617 11:54:15.667167 ok 31 selftests: arm64: sve-probe-vls # SKIP
11618 11:54:15.670442 # selftests: arm64: vec-syscfg
11619 11:54:15.673640 # TAP version 13
11620 11:54:15.674056 # 1..20
11621 11:54:15.677010 # ok 1 # SKIP SVE not supported
11622 11:54:15.680219 # ok 2 # SKIP SVE not supported
11623 11:54:15.680637 # ok 3 # SKIP SVE not supported
11624 11:54:15.683745 # ok 4 # SKIP SVE not supported
11625 11:54:15.687015 # ok 5 # SKIP SVE not supported
11626 11:54:15.690310 # ok 6 # SKIP SVE not supported
11627 11:54:15.693710 # ok 7 # SKIP SVE not supported
11628 11:54:15.697031 # ok 8 # SKIP SVE not supported
11629 11:54:15.700470 # ok 9 # SKIP SVE not supported
11630 11:54:15.703461 # ok 10 # SKIP SVE not supported
11631 11:54:15.703878 # ok 11 # SKIP SME not supported
11632 11:54:15.706942 # ok 12 # SKIP SME not supported
11633 11:54:15.710768 # ok 13 # SKIP SME not supported
11634 11:54:15.713273 # ok 14 # SKIP SME not supported
11635 11:54:15.716962 # ok 15 # SKIP SME not supported
11636 11:54:15.720163 # ok 16 # SKIP SME not supported
11637 11:54:15.723063 # ok 17 # SKIP SME not supported
11638 11:54:15.726980 # ok 18 # SKIP SME not supported
11639 11:54:15.730378 # ok 19 # SKIP SME not supported
11640 11:54:15.730793 # ok 20 # SKIP SME not supported
11641 11:54:15.736715 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11642 11:54:15.740253 ok 32 selftests: arm64: vec-syscfg
11643 11:54:15.743394 # selftests: arm64: za-fork
11644 11:54:15.743831 # TAP version 13
11645 11:54:15.744171 # 1..1
11646 11:54:15.746416 # # PID: 1253
11647 11:54:15.746831 # # SME support not present
11648 11:54:15.749960 # ok 0 skipped
11649 11:54:15.753487 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11650 11:54:15.756527 ok 33 selftests: arm64: za-fork
11651 11:54:15.760342 # selftests: arm64: za-ptrace
11652 11:54:15.826646 # TAP version 13
11653 11:54:15.827291 # 1..1
11654 11:54:15.829928 # ok 2 # SKIP SME not available
11655 11:54:15.836831 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11656 11:54:15.840586 ok 34 selftests: arm64: za-ptrace # SKIP
11657 11:54:15.852987 # selftests: arm64: check_buffer_fill
11658 11:54:15.929214 # # SKIP: MTE features unavailable
11659 11:54:15.937771 ok 35 selftests: arm64: check_buffer_fill # SKIP
11660 11:54:15.956357 # selftests: arm64: check_child_memory
11661 11:54:16.014370 # # SKIP: MTE features unavailable
11662 11:54:16.021881 ok 36 selftests: arm64: check_child_memory # SKIP
11663 11:54:16.040681 # selftests: arm64: check_gcr_el1_cswitch
11664 11:54:16.106149 # # SKIP: MTE features unavailable
11665 11:54:16.113600 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11666 11:54:16.129564 # selftests: arm64: check_ksm_options
11667 11:54:16.196284 # # SKIP: MTE features unavailable
11668 11:54:16.203519 ok 38 selftests: arm64: check_ksm_options # SKIP
11669 11:54:16.221964 # selftests: arm64: check_mmap_options
11670 11:54:16.288062 # # SKIP: MTE features unavailable
11671 11:54:16.295203 ok 39 selftests: arm64: check_mmap_options # SKIP
11672 11:54:16.309372 # selftests: arm64: check_prctl
11673 11:54:16.380035 # TAP version 13
11674 11:54:16.380548 # 1..5
11675 11:54:16.382906 # ok 1 check_basic_read
11676 11:54:16.383346 # ok 2 NONE
11677 11:54:16.386247 # ok 3 # SKIP SYNC
11678 11:54:16.386667 # ok 4 # SKIP ASYNC
11679 11:54:16.389647 # ok 5 # SKIP SYNC+ASYNC
11680 11:54:16.393029 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11681 11:54:16.395871 ok 40 selftests: arm64: check_prctl
11682 11:54:16.406273 # selftests: arm64: check_tags_inclusion
11683 11:54:16.471734 # # SKIP: MTE features unavailable
11684 11:54:16.479137 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11685 11:54:16.493069 # selftests: arm64: check_user_mem
11686 11:54:16.558334 # # SKIP: MTE features unavailable
11687 11:54:16.566102 ok 42 selftests: arm64: check_user_mem # SKIP
11688 11:54:16.578600 # selftests: arm64: btitest
11689 11:54:16.637131 # TAP version 13
11690 11:54:16.637313 # 1..18
11691 11:54:16.640601 # # HWCAP_PACA not present
11692 11:54:16.643873 # # HWCAP2_BTI not present
11693 11:54:16.643955 # # Test binary built for BTI
11694 11:54:16.650263 # ok 1 nohint_func/call_using_br_x0 # SKIP
11695 11:54:16.653652 # ok 1 nohint_func/call_using_br_x16 # SKIP
11696 11:54:16.657101 # ok 1 nohint_func/call_using_blr # SKIP
11697 11:54:16.660246 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11698 11:54:16.663387 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11699 11:54:16.666799 # ok 1 bti_none_func/call_using_blr # SKIP
11700 11:54:16.674038 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11701 11:54:16.676840 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11702 11:54:16.680733 # ok 1 bti_c_func/call_using_blr # SKIP
11703 11:54:16.683738 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11704 11:54:16.686782 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11705 11:54:16.690446 # ok 1 bti_j_func/call_using_blr # SKIP
11706 11:54:16.693698 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11707 11:54:16.697375 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11708 11:54:16.704250 # ok 1 bti_jc_func/call_using_blr # SKIP
11709 11:54:16.706930 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11710 11:54:16.710248 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11711 11:54:16.713805 # ok 1 paciasp_func/call_using_blr # SKIP
11712 11:54:16.720454 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11713 11:54:16.723870 # # WARNING - EXPECTED TEST COUNT WRONG
11714 11:54:16.727613 ok 43 selftests: arm64: btitest
11715 11:54:16.728066 # selftests: arm64: nobtitest
11716 11:54:16.732870 # TAP version 13
11717 11:54:16.733289 # 1..18
11718 11:54:16.735949 # # HWCAP_PACA not present
11719 11:54:16.739415 # # HWCAP2_BTI not present
11720 11:54:16.743351 # # Test binary not built for BTI
11721 11:54:16.746022 # ok 1 nohint_func/call_using_br_x0 # SKIP
11722 11:54:16.749294 # ok 1 nohint_func/call_using_br_x16 # SKIP
11723 11:54:16.752580 # ok 1 nohint_func/call_using_blr # SKIP
11724 11:54:16.756129 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11725 11:54:16.759135 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11726 11:54:16.765736 # ok 1 bti_none_func/call_using_blr # SKIP
11727 11:54:16.769126 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11728 11:54:16.772917 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11729 11:54:16.776009 # ok 1 bti_c_func/call_using_blr # SKIP
11730 11:54:16.779399 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11731 11:54:16.782648 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11732 11:54:16.786051 # ok 1 bti_j_func/call_using_blr # SKIP
11733 11:54:16.789190 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11734 11:54:16.796202 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11735 11:54:16.799329 # ok 1 bti_jc_func/call_using_blr # SKIP
11736 11:54:16.802822 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11737 11:54:16.805488 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11738 11:54:16.809126 # ok 1 paciasp_func/call_using_blr # SKIP
11739 11:54:16.816390 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11740 11:54:16.818983 # # WARNING - EXPECTED TEST COUNT WRONG
11741 11:54:16.822345 ok 44 selftests: arm64: nobtitest
11742 11:54:16.822765 # selftests: arm64: hwcap
11743 11:54:16.825826 # TAP version 13
11744 11:54:16.826255 # 1..28
11745 11:54:16.828999 # ok 1 cpuinfo_match_RNG
11746 11:54:16.832705 # # SIGILL reported for RNG
11747 11:54:16.833124 # ok 2 # SKIP sigill_RNG
11748 11:54:16.835748 # ok 3 cpuinfo_match_SME
11749 11:54:16.836267 # ok 4 sigill_SME
11750 11:54:16.838841 # ok 5 cpuinfo_match_SVE
11751 11:54:16.842325 # ok 6 sigill_SVE
11752 11:54:16.842741 # ok 7 cpuinfo_match_SVE 2
11753 11:54:16.845818 # # SIGILL reported for SVE 2
11754 11:54:16.848782 # ok 8 # SKIP sigill_SVE 2
11755 11:54:16.852331 # ok 9 cpuinfo_match_SVE AES
11756 11:54:16.855741 # # SIGILL reported for SVE AES
11757 11:54:16.856159 # ok 10 # SKIP sigill_SVE AES
11758 11:54:16.858928 # ok 11 cpuinfo_match_SVE2 PMULL
11759 11:54:16.862590 # # SIGILL reported for SVE2 PMULL
11760 11:54:16.865604 # ok 12 # SKIP sigill_SVE2 PMULL
11761 11:54:16.868960 # ok 13 cpuinfo_match_SVE2 BITPERM
11762 11:54:16.872204 # # SIGILL reported for SVE2 BITPERM
11763 11:54:16.875637 # ok 14 # SKIP sigill_SVE2 BITPERM
11764 11:54:16.878846 # ok 15 cpuinfo_match_SVE2 SHA3
11765 11:54:16.882434 # # SIGILL reported for SVE2 SHA3
11766 11:54:16.885941 # ok 16 # SKIP sigill_SVE2 SHA3
11767 11:54:16.886357 # ok 17 cpuinfo_match_SVE2 SM4
11768 11:54:16.888793 # # SIGILL reported for SVE2 SM4
11769 11:54:16.892440 # ok 18 # SKIP sigill_SVE2 SM4
11770 11:54:16.895570 # ok 19 cpuinfo_match_SVE2 I8MM
11771 11:54:16.899029 # # SIGILL reported for SVE2 I8MM
11772 11:54:16.901996 # ok 20 # SKIP sigill_SVE2 I8MM
11773 11:54:16.905985 # ok 21 cpuinfo_match_SVE2 F32MM
11774 11:54:16.908656 # # SIGILL reported for SVE2 F32MM
11775 11:54:16.909100 # ok 22 # SKIP sigill_SVE2 F32MM
11776 11:54:16.912411 # ok 23 cpuinfo_match_SVE2 F64MM
11777 11:54:16.915377 # # SIGILL reported for SVE2 F64MM
11778 11:54:16.918900 # ok 24 # SKIP sigill_SVE2 F64MM
11779 11:54:16.922049 # ok 25 cpuinfo_match_SVE2 BF16
11780 11:54:16.925694 # # SIGILL reported for SVE2 BF16
11781 11:54:16.928816 # ok 26 # SKIP sigill_SVE2 BF16
11782 11:54:16.932157 # ok 27 cpuinfo_match_SVE2 EBF16
11783 11:54:16.935510 # ok 28 # SKIP sigill_SVE2 EBF16
11784 11:54:16.938647 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11785 11:54:16.941786 ok 45 selftests: arm64: hwcap
11786 11:54:16.945265 # selftests: arm64: ptrace
11787 11:54:16.945830 # TAP version 13
11788 11:54:16.946335 # 1..7
11789 11:54:16.949038 # # Parent is 1495, child is 1496
11790 11:54:16.951785 # ok 1 read_tpidr_one
11791 11:54:16.955046 # ok 2 write_tpidr_one
11792 11:54:16.955543 # ok 3 verify_tpidr_one
11793 11:54:16.958800 # ok 4 count_tpidrs
11794 11:54:16.959257 # ok 5 tpidr2_write
11795 11:54:16.961848 # ok 6 tpidr2_read
11796 11:54:16.962262 # ok 7 write_tpidr_only
11797 11:54:16.968666 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11798 11:54:16.971783 ok 46 selftests: arm64: ptrace
11799 11:54:16.974833 # selftests: arm64: syscall-abi
11800 11:54:16.993448 # TAP version 13
11801 11:54:16.993865 # 1..2
11802 11:54:16.996746 # ok 1 getpid() FPSIMD
11803 11:54:16.999881 # ok 2 sched_yield() FPSIMD
11804 11:54:17.003201 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11805 11:54:17.006199 ok 47 selftests: arm64: syscall-abi
11806 11:54:17.016297 # selftests: arm64: tpidr2
11807 11:54:17.083454 # TAP version 13
11808 11:54:17.083962 # 1..5
11809 11:54:17.086852 # # PID: 1532
11810 11:54:17.087464 # # SME support not present
11811 11:54:17.089872 # ok 0 skipped, TPIDR2 not supported
11812 11:54:17.093175 # ok 1 skipped, TPIDR2 not supported
11813 11:54:17.096920 # ok 2 skipped, TPIDR2 not supported
11814 11:54:17.100055 # ok 3 skipped, TPIDR2 not supported
11815 11:54:17.103317 # ok 4 skipped, TPIDR2 not supported
11816 11:54:17.110034 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11817 11:54:17.113106 ok 48 selftests: arm64: tpidr2
11818 11:54:17.759046 arm64_tags_test pass
11819 11:54:17.762240 arm64_run_tags_test_sh pass
11820 11:54:17.765514 arm64_fake_sigreturn_bad_magic pass
11821 11:54:17.768982 arm64_fake_sigreturn_bad_size pass
11822 11:54:17.772663 arm64_fake_sigreturn_bad_size_for_magic0 pass
11823 11:54:17.775968 arm64_fake_sigreturn_duplicated_fpsimd pass
11824 11:54:17.779689 arm64_fake_sigreturn_misaligned_sp pass
11825 11:54:17.782279 arm64_fake_sigreturn_missing_fpsimd pass
11826 11:54:17.785832 arm64_fake_sigreturn_sme_change_vl skip
11827 11:54:17.788742 arm64_fake_sigreturn_sve_change_vl skip
11828 11:54:17.795561 arm64_mangle_pstate_invalid_compat_toggle pass
11829 11:54:17.798736 arm64_mangle_pstate_invalid_daif_bits pass
11830 11:54:17.802495 arm64_mangle_pstate_invalid_mode_el1h pass
11831 11:54:17.805389 arm64_mangle_pstate_invalid_mode_el1t pass
11832 11:54:17.808603 arm64_mangle_pstate_invalid_mode_el2h pass
11833 11:54:17.811895 arm64_mangle_pstate_invalid_mode_el2t pass
11834 11:54:17.818634 arm64_mangle_pstate_invalid_mode_el3h pass
11835 11:54:17.822001 arm64_mangle_pstate_invalid_mode_el3t pass
11836 11:54:17.822122 arm64_sme_trap_no_sm skip
11837 11:54:17.825560 arm64_sme_trap_non_streaming skip
11838 11:54:17.828932 arm64_sme_trap_za pass
11839 11:54:17.832601 arm64_sme_vl skip
11840 11:54:17.832681 arm64_ssve_regs skip
11841 11:54:17.835844 arm64_sve_regs skip
11842 11:54:17.835924 arm64_sve_vl skip
11843 11:54:17.838545 arm64_za_no_regs skip
11844 11:54:17.838626 arm64_za_regs skip
11845 11:54:17.841815 arm64_pac_pauth_not_enabled skip
11846 11:54:17.845706 arm64_pac_pauth_not_enabled skip
11847 11:54:17.848981 arm64_pac_generic_pauth_not_enabled skip
11848 11:54:17.852186 arm64_pac_pauth_not_enabled skip
11849 11:54:17.855234 arm64_pac_pauth_not_enabled skip
11850 11:54:17.858399 arm64_pac_pauth_not_enabled skip
11851 11:54:17.861806 arm64_pac_generic_pauth_not_enabled skip
11852 11:54:17.861890 arm64_pac pass
11853 11:54:17.865093 arm64_fp-stress_FPSIMD-0-0 pass
11854 11:54:17.868529 arm64_fp-stress_FPSIMD-0-1 pass
11855 11:54:17.871832 arm64_fp-stress_FPSIMD-1-0 pass
11856 11:54:17.875759 arm64_fp-stress_FPSIMD-1-1 pass
11857 11:54:17.878445 arm64_fp-stress_FPSIMD-2-0 pass
11858 11:54:17.878526 arm64_fp-stress_FPSIMD-2-1 pass
11859 11:54:17.881817 arm64_fp-stress_FPSIMD-3-0 pass
11860 11:54:17.885205 arm64_fp-stress_FPSIMD-3-1 pass
11861 11:54:17.888510 arm64_fp-stress_FPSIMD-4-0 pass
11862 11:54:17.891963 arm64_fp-stress_FPSIMD-4-1 pass
11863 11:54:17.895087 arm64_fp-stress_FPSIMD-5-0 pass
11864 11:54:17.898400 arm64_fp-stress_FPSIMD-5-1 pass
11865 11:54:17.901816 arm64_fp-stress_FPSIMD-6-0 pass
11866 11:54:17.901897 arm64_fp-stress_FPSIMD-6-1 pass
11867 11:54:17.904954 arm64_fp-stress_FPSIMD-7-0 pass
11868 11:54:17.908326 arm64_fp-stress_FPSIMD-7-1 pass
11869 11:54:17.912177 arm64_fp-stress pass
11870 11:54:17.915091 arm64_sve-ptrace_sve_not_available skip
11871 11:54:17.915174 arm64_sve-ptrace skip
11872 11:54:17.918771 arm64_sve-probe-vls_sve_not_available skip
11873 11:54:17.921759 arm64_sve-probe-vls skip
11874 11:54:17.925286 arm64_vec-syscfg_sve_not_supported skip
11875 11:54:17.928533 arm64_vec-syscfg_sve_not_supported skip
11876 11:54:17.931553 arm64_vec-syscfg_sve_not_supported skip
11877 11:54:17.934846 arm64_vec-syscfg_sve_not_supported skip
11878 11:54:17.942157 arm64_vec-syscfg_sve_not_supported skip
11879 11:54:17.945501 arm64_vec-syscfg_sve_not_supported skip
11880 11:54:17.948551 arm64_vec-syscfg_sve_not_supported skip
11881 11:54:17.951816 arm64_vec-syscfg_sve_not_supported skip
11882 11:54:17.954832 arm64_vec-syscfg_sve_not_supported skip
11883 11:54:17.958781 arm64_vec-syscfg_sve_not_supported skip
11884 11:54:17.962007 arm64_vec-syscfg_sme_not_supported skip
11885 11:54:17.965172 arm64_vec-syscfg_sme_not_supported skip
11886 11:54:17.968716 arm64_vec-syscfg_sme_not_supported skip
11887 11:54:17.971540 arm64_vec-syscfg_sme_not_supported skip
11888 11:54:17.974912 arm64_vec-syscfg_sme_not_supported skip
11889 11:54:17.978170 arm64_vec-syscfg_sme_not_supported skip
11890 11:54:17.981605 arm64_vec-syscfg_sme_not_supported skip
11891 11:54:17.984889 arm64_vec-syscfg_sme_not_supported skip
11892 11:54:17.988402 arm64_vec-syscfg_sme_not_supported skip
11893 11:54:17.994685 arm64_vec-syscfg_sme_not_supported skip
11894 11:54:17.994765 arm64_vec-syscfg pass
11895 11:54:17.998013 arm64_za-fork_skipped pass
11896 11:54:17.998093 arm64_za-fork pass
11897 11:54:18.001968 arm64_za-ptrace_sme_not_available skip
11898 11:54:18.004987 arm64_za-ptrace skip
11899 11:54:18.008150 arm64_check_buffer_fill skip
11900 11:54:18.011463 arm64_check_child_memory skip
11901 11:54:18.014548 arm64_check_gcr_el1_cswitch skip
11902 11:54:18.014629 arm64_check_ksm_options skip
11903 11:54:18.017840 arm64_check_mmap_options skip
11904 11:54:18.021533 arm64_check_prctl_check_basic_read pass
11905 11:54:18.024972 arm64_check_prctl_NONE pass
11906 11:54:18.027933 arm64_check_prctl_sync skip
11907 11:54:18.031742 arm64_check_prctl_async skip
11908 11:54:18.031829 arm64_check_prctl_sync_async skip
11909 11:54:18.034853 arm64_check_prctl pass
11910 11:54:18.038247 arm64_check_tags_inclusion skip
11911 11:54:18.041730 arm64_check_user_mem skip
11912 11:54:18.044716 arm64_btitest_nohint_func_call_using_br_x0 skip
11913 11:54:18.048240 arm64_btitest_nohint_func_call_using_br_x16 skip
11914 11:54:18.051480 arm64_btitest_nohint_func_call_using_blr skip
11915 11:54:18.058300 arm64_btitest_bti_none_func_call_using_br_x0 skip
11916 11:54:18.061284 arm64_btitest_bti_none_func_call_using_br_x16 skip
11917 11:54:18.065156 arm64_btitest_bti_none_func_call_using_blr skip
11918 11:54:18.071454 arm64_btitest_bti_c_func_call_using_br_x0 skip
11919 11:54:18.074472 arm64_btitest_bti_c_func_call_using_br_x16 skip
11920 11:54:18.077960 arm64_btitest_bti_c_func_call_using_blr skip
11921 11:54:18.081068 arm64_btitest_bti_j_func_call_using_br_x0 skip
11922 11:54:18.087964 arm64_btitest_bti_j_func_call_using_br_x16 skip
11923 11:54:18.091088 arm64_btitest_bti_j_func_call_using_blr skip
11924 11:54:18.094543 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11925 11:54:18.098181 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11926 11:54:18.104417 arm64_btitest_bti_jc_func_call_using_blr skip
11927 11:54:18.107866 arm64_btitest_paciasp_func_call_using_br_x0 skip
11928 11:54:18.111192 arm64_btitest_paciasp_func_call_using_br_x16 skip
11929 11:54:18.117757 arm64_btitest_paciasp_func_call_using_blr skip
11930 11:54:18.117840 arm64_btitest pass
11931 11:54:18.121082 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11932 11:54:18.127911 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11933 11:54:18.130774 arm64_nobtitest_nohint_func_call_using_blr skip
11934 11:54:18.134303 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11935 11:54:18.140848 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11936 11:54:18.144829 arm64_nobtitest_bti_none_func_call_using_blr skip
11937 11:54:18.150805 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11938 11:54:18.154002 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11939 11:54:18.157345 arm64_nobtitest_bti_c_func_call_using_blr skip
11940 11:54:18.160880 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11941 11:54:18.167266 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11942 11:54:18.170509 arm64_nobtitest_bti_j_func_call_using_blr skip
11943 11:54:18.174184 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11944 11:54:18.180890 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11945 11:54:18.184297 arm64_nobtitest_bti_jc_func_call_using_blr skip
11946 11:54:18.187537 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11947 11:54:18.193903 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11948 11:54:18.197219 arm64_nobtitest_paciasp_func_call_using_blr skip
11949 11:54:18.200398 arm64_nobtitest pass
11950 11:54:18.203810 arm64_hwcap_cpuinfo_match_RNG pass
11951 11:54:18.203891 arm64_hwcap_sigill_rng skip
11952 11:54:18.206983 arm64_hwcap_cpuinfo_match_SME pass
11953 11:54:18.210484 arm64_hwcap_sigill_SME pass
11954 11:54:18.213977 arm64_hwcap_cpuinfo_match_SVE pass
11955 11:54:18.217078 arm64_hwcap_sigill_SVE pass
11956 11:54:18.220895 arm64_hwcap_cpuinfo_match_SVE_2 pass
11957 11:54:18.223692 arm64_hwcap_sigill_sve_2 skip
11958 11:54:18.227342 arm64_hwcap_cpuinfo_match_SVE_AES pass
11959 11:54:18.227424 arm64_hwcap_sigill_sve_aes skip
11960 11:54:18.233604 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11961 11:54:18.236656 arm64_hwcap_sigill_sve2_pmull skip
11962 11:54:18.240465 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11963 11:54:18.243554 arm64_hwcap_sigill_sve2_bitperm skip
11964 11:54:18.246810 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11965 11:54:18.250195 arm64_hwcap_sigill_sve2_sha3 skip
11966 11:54:18.253557 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11967 11:54:18.256811 arm64_hwcap_sigill_sve2_sm4 skip
11968 11:54:18.260206 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11969 11:54:18.263370 arm64_hwcap_sigill_sve2_i8mm skip
11970 11:54:18.266471 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11971 11:54:18.270047 arm64_hwcap_sigill_sve2_f32mm skip
11972 11:54:18.273083 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11973 11:54:18.276850 arm64_hwcap_sigill_sve2_f64mm skip
11974 11:54:18.279663 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
11975 11:54:18.282902 arm64_hwcap_sigill_sve2_bf16 skip
11976 11:54:18.286477 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
11977 11:54:18.289880 arm64_hwcap_sigill_sve2_ebf16 skip
11978 11:54:18.289962 arm64_hwcap pass
11979 11:54:18.293370 arm64_ptrace_read_tpidr_one pass
11980 11:54:18.296257 arm64_ptrace_write_tpidr_one pass
11981 11:54:18.299749 arm64_ptrace_verify_tpidr_one pass
11982 11:54:18.302823 arm64_ptrace_count_tpidrs pass
11983 11:54:18.306448 arm64_ptrace_tpidr2_write pass
11984 11:54:18.309734 arm64_ptrace_tpidr2_read pass
11985 11:54:18.313179 arm64_ptrace_write_tpidr_only pass
11986 11:54:18.313260 arm64_ptrace pass
11987 11:54:18.316404 arm64_syscall-abi_getpid_FPSIMD pass
11988 11:54:18.320004 arm64_syscall-abi_sched_yield_FPSIMD pass
11989 11:54:18.322968 arm64_syscall-abi pass
11990 11:54:18.326658 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11991 11:54:18.329387 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11992 11:54:18.336362 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11993 11:54:18.339874 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11994 11:54:18.343385 arm64_tpidr2_skipped_TPIDR2_not_supported pass
11995 11:54:18.346136 arm64_tpidr2 pass
11996 11:54:18.349560 + ../../utils/send-to-lava.sh ./output/result.txt
11997 11:54:18.356216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-arm64 RESULT=pass>
11998 11:54:18.356497 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-arm64 RESULT=pass
12000 11:54:18.359328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12001 11:54:18.359585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12003 11:54:18.365896 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12004 11:54:18.366151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12006 11:54:18.372442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12007 11:54:18.372697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12009 11:54:18.406453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12011 11:54:18.409180 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12012 11:54:18.469147 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12013 11:54:18.469430 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12015 11:54:18.524654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12016 11:54:18.524928 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12018 11:54:18.582227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12019 11:54:18.582506 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12021 11:54:18.641702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12022 11:54:18.641989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12024 11:54:18.699316 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12025 11:54:18.699590 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12027 11:54:18.757309 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12028 11:54:18.757587 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12030 11:54:18.812856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12031 11:54:18.813133 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12033 11:54:18.866514 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12034 11:54:18.866787 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12036 11:54:18.925569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12037 11:54:18.925850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12039 11:54:18.984642 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12040 11:54:18.984921 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12042 11:54:19.041667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12043 11:54:19.041956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12045 11:54:19.100133 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12046 11:54:19.100402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12048 11:54:19.157434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12049 11:54:19.157745 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12051 11:54:19.213136 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12052 11:54:19.213408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12054 11:54:19.268074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12055 11:54:19.268345 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12057 11:54:19.329157 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12059 11:54:19.331881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12060 11:54:19.385753 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12061 11:54:19.386024 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12063 11:54:19.444803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12064 11:54:19.445080 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12066 11:54:19.504395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12067 11:54:19.504661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12069 11:54:19.563878 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12070 11:54:19.564143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12072 11:54:19.621492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12073 11:54:19.621759 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12075 11:54:19.679295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12076 11:54:19.679564 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12078 11:54:19.737070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12079 11:54:19.737344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12081 11:54:19.796827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12083 11:54:19.800039 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12084 11:54:19.854279 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12086 11:54:19.857528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12087 11:54:19.917332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12088 11:54:19.917602 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12090 11:54:19.972128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12092 11:54:19.975067 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12093 11:54:20.028762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12095 11:54:20.031752 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12096 11:54:20.083389 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip
12098 11:54:20.086255 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_pauth_not_enabled RESULT=skip>
12099 11:54:20.143302 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip>
12100 11:54:20.143573 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_generic_pauth_not_enabled RESULT=skip
12102 11:54:20.200478 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12103 11:54:20.200738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12105 11:54:20.258701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12106 11:54:20.259165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12108 11:54:20.316269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12109 11:54:20.316543 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12111 11:54:20.368648 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12112 11:54:20.368914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12114 11:54:20.428002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12115 11:54:20.428274 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12117 11:54:20.485596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12118 11:54:20.485866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12120 11:54:20.543423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12121 11:54:20.543691 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12123 11:54:20.603760 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12124 11:54:20.604027 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12126 11:54:20.662356 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12127 11:54:20.662628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12129 11:54:20.721166 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12130 11:54:20.721433 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12132 11:54:20.779245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12133 11:54:20.779510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12135 11:54:20.837617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12136 11:54:20.837889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12138 11:54:20.895007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12139 11:54:20.895271 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12141 11:54:20.953393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12142 11:54:20.953660 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12144 11:54:21.010539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12145 11:54:21.010839 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12147 11:54:21.067297 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12148 11:54:21.067561 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12150 11:54:21.125877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12151 11:54:21.126165 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12153 11:54:21.183347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12154 11:54:21.183619 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12156 11:54:21.243922 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip>
12157 11:54:21.244198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_sve_not_available RESULT=skip
12159 11:54:21.300149 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12160 11:54:21.300414 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12162 11:54:21.361425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip>
12163 11:54:21.361722 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_sve_not_available RESULT=skip
12165 11:54:21.416045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12166 11:54:21.416325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12168 11:54:21.477654 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12169 11:54:21.477929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12171 11:54:21.529385 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12172 11:54:21.529659 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12174 11:54:21.583979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12175 11:54:21.584260 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12177 11:54:21.638598 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12178 11:54:21.638881 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12180 11:54:21.691789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12181 11:54:21.692056 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12183 11:54:21.747120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12184 11:54:21.747396 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12186 11:54:21.802857 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12187 11:54:21.803164 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12189 11:54:21.860212 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12190 11:54:21.860491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12192 11:54:21.912784 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12193 11:54:21.913061 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12195 11:54:21.964223 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip>
12196 11:54:21.964491 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sve_not_supported RESULT=skip
12198 11:54:22.022045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12199 11:54:22.022338 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12201 11:54:22.077942 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12202 11:54:22.078217 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12204 11:54:22.133830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12205 11:54:22.134104 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12207 11:54:22.191539 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12208 11:54:22.191807 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12210 11:54:22.247409 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12211 11:54:22.247686 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12213 11:54:22.309197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12214 11:54:22.309465 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12216 11:54:22.366990 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12217 11:54:22.367268 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12219 11:54:22.421045 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12220 11:54:22.421349 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12222 11:54:22.479435 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12223 11:54:22.479724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12225 11:54:22.538775 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip>
12226 11:54:22.539054 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_sme_not_supported RESULT=skip
12228 11:54:22.596365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12229 11:54:22.596630 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12231 11:54:22.656838 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12232 11:54:22.657114 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12234 11:54:22.715555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12235 11:54:22.715825 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12237 11:54:22.776673 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip>
12238 11:54:22.776935 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_sme_not_available RESULT=skip
12240 11:54:22.833114 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12241 11:54:22.833385 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12243 11:54:22.894421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12244 11:54:22.894692 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12246 11:54:22.953159 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12247 11:54:22.953431 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12249 11:54:23.013086 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12250 11:54:23.013347 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12252 11:54:23.076058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12253 11:54:23.076337 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12255 11:54:23.136049 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12256 11:54:23.136324 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12258 11:54:23.200497 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12259 11:54:23.200770 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12261 11:54:23.258219 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12262 11:54:23.258485 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12264 11:54:23.313568 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip>
12265 11:54:23.313827 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync RESULT=skip
12267 11:54:23.372664 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_async RESULT=skip>
12268 11:54:23.372936 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_async RESULT=skip
12270 11:54:23.430972 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip
12272 11:54:23.433773 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_sync_async RESULT=skip>
12273 11:54:23.486120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12274 11:54:23.486401 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12276 11:54:23.541998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12277 11:54:23.542284 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12279 11:54:23.598800 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12280 11:54:23.599099 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12282 11:54:23.657117 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12283 11:54:23.657388 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12285 11:54:23.711667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12286 11:54:23.711925 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12288 11:54:23.767256 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12289 11:54:23.767582 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12291 11:54:23.825820 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12292 11:54:23.826094 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12294 11:54:23.881747 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12295 11:54:23.882014 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12297 11:54:23.938137 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12298 11:54:23.938402 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12300 11:54:23.998425 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12301 11:54:23.998694 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12303 11:54:24.049952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12304 11:54:24.050259 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12306 11:54:24.109933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12307 11:54:24.110200 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12309 11:54:24.168414 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12310 11:54:24.168724 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12312 11:54:24.227163 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12313 11:54:24.227428 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12315 11:54:24.281810 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12316 11:54:24.282083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12318 11:54:24.337382 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12319 11:54:24.337646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12321 11:54:24.396421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12322 11:54:24.396703 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12324 11:54:24.456146 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12325 11:54:24.456445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12327 11:54:24.514348 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12328 11:54:24.514618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12330 11:54:24.570118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12331 11:54:24.570403 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12333 11:54:24.628392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12334 11:54:24.628682 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12336 11:54:24.685555 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12337 11:54:24.685823 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12339 11:54:24.745330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12340 11:54:24.745607 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12342 11:54:24.799905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12343 11:54:24.800175 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12345 11:54:24.859023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12346 11:54:24.859298 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12348 11:54:24.916321 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12349 11:54:24.916616 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12351 11:54:24.978593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12352 11:54:24.978914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12354 11:54:25.037200 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12355 11:54:25.037476 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12357 11:54:25.098262 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12358 11:54:25.098535 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12360 11:54:25.153758 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12361 11:54:25.154058 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12363 11:54:25.212175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12364 11:54:25.212448 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12366 11:54:25.272487 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12367 11:54:25.272766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12369 11:54:25.331043 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12370 11:54:25.331316 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12372 11:54:25.385884 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12373 11:54:25.386168 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12375 11:54:25.445629 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12376 11:54:25.445927 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12378 11:54:25.502580 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12379 11:54:25.502854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12381 11:54:25.561337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12382 11:54:25.561646 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12384 11:54:25.617002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12385 11:54:25.617325 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12387 11:54:25.673144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12388 11:54:25.673477 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12390 11:54:25.729139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12391 11:54:25.729441 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12393 11:54:25.780732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12394 11:54:25.781007 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12396 11:54:25.836661 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12398 11:54:25.839999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12399 11:54:25.892586 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip>
12400 11:54:25.892914 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_rng RESULT=skip
12402 11:54:25.952991 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12403 11:54:25.953318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12405 11:54:26.007874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12406 11:54:26.008159 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12408 11:54:26.067192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12410 11:54:26.070365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12411 11:54:26.127394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12412 11:54:26.127701 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12414 11:54:26.190490 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12415 11:54:26.190802 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12417 11:54:26.247735 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip>
12418 11:54:26.248028 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_2 RESULT=skip
12420 11:54:26.309505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12421 11:54:26.309788 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12423 11:54:26.367612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip>
12424 11:54:26.367889 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve_aes RESULT=skip
12426 11:54:26.427723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12427 11:54:26.428004 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12429 11:54:26.485390 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip>
12430 11:54:26.485676 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_pmull RESULT=skip
12432 11:54:26.543813 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12433 11:54:26.544120 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12435 11:54:26.600667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip>
12436 11:54:26.600944 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bitperm RESULT=skip
12438 11:54:26.659442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12439 11:54:26.659738 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12441 11:54:26.712170 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip
12443 11:54:26.714914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sha3 RESULT=skip>
12444 11:54:26.769034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12445 11:54:26.769344 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12447 11:54:26.820384 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip
12449 11:54:26.823777 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_sm4 RESULT=skip>
12450 11:54:26.882036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12451 11:54:26.882348 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12453 11:54:26.937390 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip
12455 11:54:26.940569 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_i8mm RESULT=skip>
12456 11:54:26.997398 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12457 11:54:26.997697 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12459 11:54:27.061333 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip>
12460 11:54:27.061643 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f32mm RESULT=skip
12462 11:54:27.124589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12463 11:54:27.124904 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12465 11:54:27.184567 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip
12467 11:54:27.187186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_f64mm RESULT=skip>
12468 11:54:27.244825 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12469 11:54:27.245131 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12471 11:54:27.300951 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip
12473 11:54:27.304134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_bf16 RESULT=skip>
12474 11:54:27.356144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12475 11:54:27.356483 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12477 11:54:27.418994 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip>
12478 11:54:27.419334 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_sve2_ebf16 RESULT=skip
12480 11:54:27.474098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12481 11:54:27.474408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12483 11:54:27.533071 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12485 11:54:27.536161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12486 11:54:27.595435 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12488 11:54:27.598231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12489 11:54:27.657433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12490 11:54:27.657756 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12492 11:54:27.711967 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12493 11:54:27.712270 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12495 11:54:27.768113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12496 11:54:27.768436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12498 11:54:27.821002 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12499 11:54:27.821314 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12501 11:54:27.877617 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12502 11:54:27.877940 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12504 11:54:27.926305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12505 11:54:27.926618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12507 11:54:27.984656 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12508 11:54:27.984956 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12510 11:54:28.038976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12511 11:54:28.039265 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12513 11:54:28.089770 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12514 11:54:28.090059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12516 11:54:28.146959 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12517 11:54:28.147248 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12519 11:54:28.200702 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12520 11:54:28.200983 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12522 11:54:28.254437 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12523 11:54:28.254750 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12525 11:54:28.309410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12526 11:54:28.309725 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12528 11:54:28.362506 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12529 11:54:28.362818 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12531 11:54:28.412919 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12532 11:54:28.413034 + set +x
12533 11:54:28.413272 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12535 11:54:28.419333 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 12066512_1.6.2.3.5>
12536 11:54:28.419586 Received signal: <ENDRUN> 1_kselftest-arm64 12066512_1.6.2.3.5
12537 11:54:28.419663 Ending use of test pattern.
12538 11:54:28.419725 Ending test lava.1_kselftest-arm64 (12066512_1.6.2.3.5), duration 34.95
12540 11:54:28.422424 <LAVA_TEST_RUNNER EXIT>
12541 11:54:28.422676 ok: lava_test_shell seems to have completed
12542 11:54:28.423650 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_NONE: pass
arm64_check_prctl_async: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_prctl_sync: skip
arm64_check_prctl_sync_async: skip
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_rng: skip
arm64_hwcap_sigill_sve2_bf16: skip
arm64_hwcap_sigill_sve2_bitperm: skip
arm64_hwcap_sigill_sve2_ebf16: skip
arm64_hwcap_sigill_sve2_f32mm: skip
arm64_hwcap_sigill_sve2_f64mm: skip
arm64_hwcap_sigill_sve2_i8mm: skip
arm64_hwcap_sigill_sve2_pmull: skip
arm64_hwcap_sigill_sve2_sha3: skip
arm64_hwcap_sigill_sve2_sm4: skip
arm64_hwcap_sigill_sve_2: skip
arm64_hwcap_sigill_sve_aes: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_generic_pauth_not_enabled: skip
arm64_pac_pauth_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_sve_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_sve_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_sme_not_supported: skip
arm64_vec-syscfg_sve_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_sme_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
shardfile-arm64: pass
12543 11:54:28.423818 end: 3.1 lava-test-shell (duration 00:00:36) [common]
12544 11:54:28.423927 end: 3 lava-test-retry (duration 00:00:36) [common]
12545 11:54:28.424016 start: 4 finalize (timeout 00:06:35) [common]
12546 11:54:28.424104 start: 4.1 power-off (timeout 00:00:30) [common]
12547 11:54:28.424254 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
12548 11:54:28.500911 >> Command sent successfully.
12549 11:54:28.503249 Returned 0 in 0 seconds
12550 11:54:28.604025 end: 4.1 power-off (duration 00:00:00) [common]
12552 11:54:28.605927 start: 4.2 read-feedback (timeout 00:06:35) [common]
12553 11:54:28.607310 Listened to connection for namespace 'common' for up to 1s
12554 11:54:29.607763 Finalising connection for namespace 'common'
12555 11:54:29.607938 Disconnecting from shell: Finalise
12556 11:54:29.608014 / #
12557 11:54:29.708344 end: 4.2 read-feedback (duration 00:00:01) [common]
12558 11:54:29.708509 end: 4 finalize (duration 00:00:01) [common]
12559 11:54:29.708618 Cleaning after the job
12560 11:54:29.708720 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/ramdisk
12561 11:54:29.711281 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/kernel
12562 11:54:29.723493 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/dtb
12563 11:54:29.723670 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/nfsrootfs
12564 11:54:29.814242 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066512/tftp-deploy-1a1n6lk2/modules
12565 11:54:29.821731 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066512
12566 11:54:30.492430 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066512
12567 11:54:30.492598 Job finished correctly