Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 36
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:54:27.983855 lava-dispatcher, installed at version: 2023.10
2 11:54:27.984049 start: 0 validate
3 11:54:27.984188 Start time: 2023-11-23 11:54:27.984180+00:00 (UTC)
4 11:54:27.984305 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:54:27.984432 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:54:28.246556 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:54:28.247213 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:54:28.509398 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:54:28.510198 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:54:28.781569 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:54:28.782378 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:54:29.053138 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:54:29.053910 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:54:29.331469 validate duration: 1.35
16 11:54:29.332874 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:54:29.333439 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:54:29.334047 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:54:29.334821 Not decompressing ramdisk as can be used compressed.
20 11:54:29.335342 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:54:29.335708 saving as /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/ramdisk/initrd.cpio.gz
22 11:54:29.336073 total size: 4665395 (4 MB)
23 11:54:29.341424 progress 0 % (0 MB)
24 11:54:29.348852 progress 5 % (0 MB)
25 11:54:29.355452 progress 10 % (0 MB)
26 11:54:29.360029 progress 15 % (0 MB)
27 11:54:29.363710 progress 20 % (0 MB)
28 11:54:29.366995 progress 25 % (1 MB)
29 11:54:29.369745 progress 30 % (1 MB)
30 11:54:29.372244 progress 35 % (1 MB)
31 11:54:29.374526 progress 40 % (1 MB)
32 11:54:29.376914 progress 45 % (2 MB)
33 11:54:29.378897 progress 50 % (2 MB)
34 11:54:29.380799 progress 55 % (2 MB)
35 11:54:29.382529 progress 60 % (2 MB)
36 11:54:29.384235 progress 65 % (2 MB)
37 11:54:29.385894 progress 70 % (3 MB)
38 11:54:29.387424 progress 75 % (3 MB)
39 11:54:29.388931 progress 80 % (3 MB)
40 11:54:29.390648 progress 85 % (3 MB)
41 11:54:29.392009 progress 90 % (4 MB)
42 11:54:29.393369 progress 95 % (4 MB)
43 11:54:29.394758 progress 100 % (4 MB)
44 11:54:29.394936 4 MB downloaded in 0.06 s (75.55 MB/s)
45 11:54:29.395101 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:54:29.395361 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:54:29.395457 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:54:29.395549 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:54:29.395696 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:54:29.395769 saving as /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/kernel/Image
52 11:54:29.395830 total size: 49107456 (46 MB)
53 11:54:29.395892 No compression specified
54 11:54:29.396966 progress 0 % (0 MB)
55 11:54:29.409531 progress 5 % (2 MB)
56 11:54:29.422351 progress 10 % (4 MB)
57 11:54:29.435052 progress 15 % (7 MB)
58 11:54:29.447719 progress 20 % (9 MB)
59 11:54:29.460336 progress 25 % (11 MB)
60 11:54:29.473264 progress 30 % (14 MB)
61 11:54:29.485987 progress 35 % (16 MB)
62 11:54:29.498626 progress 40 % (18 MB)
63 11:54:29.510956 progress 45 % (21 MB)
64 11:54:29.523529 progress 50 % (23 MB)
65 11:54:29.535998 progress 55 % (25 MB)
66 11:54:29.548583 progress 60 % (28 MB)
67 11:54:29.561307 progress 65 % (30 MB)
68 11:54:29.574162 progress 70 % (32 MB)
69 11:54:29.586783 progress 75 % (35 MB)
70 11:54:29.599170 progress 80 % (37 MB)
71 11:54:29.611523 progress 85 % (39 MB)
72 11:54:29.623879 progress 90 % (42 MB)
73 11:54:29.636308 progress 95 % (44 MB)
74 11:54:29.648434 progress 100 % (46 MB)
75 11:54:29.648632 46 MB downloaded in 0.25 s (185.26 MB/s)
76 11:54:29.648774 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:54:29.649003 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:54:29.649089 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:54:29.649175 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:54:29.649312 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:54:29.649380 saving as /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/dtb/mt8192-asurada-spherion-r0.dtb
83 11:54:29.649438 total size: 47278 (0 MB)
84 11:54:29.649497 No compression specified
85 11:54:29.650628 progress 69 % (0 MB)
86 11:54:29.650897 progress 100 % (0 MB)
87 11:54:29.651048 0 MB downloaded in 0.00 s (28.04 MB/s)
88 11:54:29.651166 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:54:29.651380 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:54:29.651465 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:54:29.651545 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:54:29.651656 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:54:29.651721 saving as /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/nfsrootfs/full.rootfs.tar
95 11:54:29.651782 total size: 200813988 (191 MB)
96 11:54:29.651841 Using unxz to decompress xz
97 11:54:29.655754 progress 0 % (0 MB)
98 11:54:30.183719 progress 5 % (9 MB)
99 11:54:30.700020 progress 10 % (19 MB)
100 11:54:31.287159 progress 15 % (28 MB)
101 11:54:31.667082 progress 20 % (38 MB)
102 11:54:31.990407 progress 25 % (47 MB)
103 11:54:32.587767 progress 30 % (57 MB)
104 11:54:33.131185 progress 35 % (67 MB)
105 11:54:33.718771 progress 40 % (76 MB)
106 11:54:34.273961 progress 45 % (86 MB)
107 11:54:34.866473 progress 50 % (95 MB)
108 11:54:35.510254 progress 55 % (105 MB)
109 11:54:36.185978 progress 60 % (114 MB)
110 11:54:36.305222 progress 65 % (124 MB)
111 11:54:36.446562 progress 70 % (134 MB)
112 11:54:36.547233 progress 75 % (143 MB)
113 11:54:36.620554 progress 80 % (153 MB)
114 11:54:36.691420 progress 85 % (162 MB)
115 11:54:36.795273 progress 90 % (172 MB)
116 11:54:37.081310 progress 95 % (181 MB)
117 11:54:37.667878 progress 100 % (191 MB)
118 11:54:37.673170 191 MB downloaded in 8.02 s (23.88 MB/s)
119 11:54:37.673471 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:54:37.673769 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:54:37.673882 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:54:37.674003 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:54:37.674186 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:54:37.674304 saving as /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/modules/modules.tar
126 11:54:37.674403 total size: 8621364 (8 MB)
127 11:54:37.674513 Using unxz to decompress xz
128 11:54:37.679044 progress 0 % (0 MB)
129 11:54:37.700274 progress 5 % (0 MB)
130 11:54:37.723902 progress 10 % (0 MB)
131 11:54:37.747758 progress 15 % (1 MB)
132 11:54:37.771378 progress 20 % (1 MB)
133 11:54:37.795637 progress 25 % (2 MB)
134 11:54:37.821562 progress 30 % (2 MB)
135 11:54:37.847963 progress 35 % (2 MB)
136 11:54:37.871516 progress 40 % (3 MB)
137 11:54:37.896030 progress 45 % (3 MB)
138 11:54:37.921582 progress 50 % (4 MB)
139 11:54:37.946141 progress 55 % (4 MB)
140 11:54:37.971174 progress 60 % (4 MB)
141 11:54:37.999007 progress 65 % (5 MB)
142 11:54:38.024196 progress 70 % (5 MB)
143 11:54:38.047848 progress 75 % (6 MB)
144 11:54:38.074956 progress 80 % (6 MB)
145 11:54:38.100977 progress 85 % (7 MB)
146 11:54:38.126210 progress 90 % (7 MB)
147 11:54:38.156307 progress 95 % (7 MB)
148 11:54:38.186399 progress 100 % (8 MB)
149 11:54:38.191262 8 MB downloaded in 0.52 s (15.91 MB/s)
150 11:54:38.191523 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:54:38.191798 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:54:38.191924 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:54:38.192055 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:54:41.847432 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl
156 11:54:41.847625 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:54:41.847731 start: 1.6.2 lava-overlay (timeout 00:09:47) [common]
158 11:54:41.847899 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159
159 11:54:41.848039 makedir: /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin
160 11:54:41.848142 makedir: /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/tests
161 11:54:41.848247 makedir: /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/results
162 11:54:41.848349 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-add-keys
163 11:54:41.848496 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-add-sources
164 11:54:41.848627 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-background-process-start
165 11:54:41.848760 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-background-process-stop
166 11:54:41.848903 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-common-functions
167 11:54:41.849034 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-echo-ipv4
168 11:54:41.849166 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-install-packages
169 11:54:41.849292 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-installed-packages
170 11:54:41.849417 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-os-build
171 11:54:41.849547 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-probe-channel
172 11:54:41.849672 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-probe-ip
173 11:54:41.849801 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-target-ip
174 11:54:41.850032 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-target-mac
175 11:54:41.850183 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-target-storage
176 11:54:41.850335 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-case
177 11:54:41.850468 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-event
178 11:54:41.850601 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-feedback
179 11:54:41.850735 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-raise
180 11:54:41.850859 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-reference
181 11:54:41.850988 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-runner
182 11:54:41.851112 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-set
183 11:54:41.851244 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-test-shell
184 11:54:41.851370 Updating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-add-keys (debian)
185 11:54:41.851526 Updating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-add-sources (debian)
186 11:54:41.851677 Updating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-install-packages (debian)
187 11:54:41.851825 Updating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-installed-packages (debian)
188 11:54:41.851970 Updating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/bin/lava-os-build (debian)
189 11:54:41.852092 Creating /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/environment
190 11:54:41.852196 LAVA metadata
191 11:54:41.852267 - LAVA_JOB_ID=12066552
192 11:54:41.852330 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:54:41.852434 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:47) [common]
194 11:54:41.852502 skipped lava-vland-overlay
195 11:54:41.852575 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:54:41.852656 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:47) [common]
197 11:54:41.852720 skipped lava-multinode-overlay
198 11:54:41.852793 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:54:41.852871 start: 1.6.2.3 test-definition (timeout 00:09:47) [common]
200 11:54:41.852945 Loading test definitions
201 11:54:41.853038 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:47) [common]
202 11:54:41.853112 Using /lava-12066552 at stage 0
203 11:54:41.853398 uuid=12066552_1.6.2.3.1 testdef=None
204 11:54:41.853485 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:54:41.853575 start: 1.6.2.3.2 test-overlay (timeout 00:09:47) [common]
206 11:54:41.854072 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:54:41.854528 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:47) [common]
209 11:54:41.855101 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:54:41.855334 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:47) [common]
212 11:54:41.855913 runner path: /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/0/tests/0_timesync-off test_uuid 12066552_1.6.2.3.1
213 11:54:41.856070 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:54:41.856299 start: 1.6.2.3.5 git-repo-action (timeout 00:09:47) [common]
216 11:54:41.856372 Using /lava-12066552 at stage 0
217 11:54:41.856472 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:54:41.856549 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/0/tests/1_kselftest-rtc'
219 11:54:46.235655 Running '/usr/bin/git checkout kernelci.org
220 11:54:46.383515 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 11:54:46.384518 uuid=12066552_1.6.2.3.5 testdef=None
222 11:54:46.384715 end: 1.6.2.3.5 git-repo-action (duration 00:00:05) [common]
224 11:54:46.385079 start: 1.6.2.3.6 test-overlay (timeout 00:09:43) [common]
225 11:54:46.386384 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:54:46.386776 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:43) [common]
228 11:54:46.388476 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:54:46.388878 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:43) [common]
231 11:54:46.390544 runner path: /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/0/tests/1_kselftest-rtc test_uuid 12066552_1.6.2.3.5
232 11:54:46.390668 BOARD='mt8192-asurada-spherion-r0'
233 11:54:46.390761 BRANCH='cip-gitlab'
234 11:54:46.390851 SKIPFILE='/dev/null'
235 11:54:46.390937 SKIP_INSTALL='True'
236 11:54:46.391023 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:54:46.391109 TST_CASENAME=''
238 11:54:46.391192 TST_CMDFILES='rtc'
239 11:54:46.391379 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:54:46.391734 Creating lava-test-runner.conf files
242 11:54:46.391834 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066552/lava-overlay-wktmw159/lava-12066552/0 for stage 0
243 11:54:46.391971 - 0_timesync-off
244 11:54:46.392071 - 1_kselftest-rtc
245 11:54:46.392186 end: 1.6.2.3 test-definition (duration 00:00:05) [common]
246 11:54:46.392280 start: 1.6.2.4 compress-overlay (timeout 00:09:43) [common]
247 11:54:54.114984 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:54:54.115167 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 11:54:54.115256 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:54:54.115370 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 11:54:54.115460 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 11:54:54.237235 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:54:54.237654 start: 1.6.4 extract-modules (timeout 00:09:35) [common]
254 11:54:54.237810 extracting modules file /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl
255 11:54:54.470536 extracting modules file /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066552/extract-overlay-ramdisk-je1gjau4/ramdisk
256 11:54:54.707040 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:54:54.707204 start: 1.6.5 apply-overlay-tftp (timeout 00:09:35) [common]
258 11:54:54.707302 [common] Applying overlay to NFS
259 11:54:54.707376 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066552/compress-overlay-90ykl1k6/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl
260 11:54:55.668061 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:54:55.668229 start: 1.6.6 configure-preseed-file (timeout 00:09:34) [common]
262 11:54:55.668354 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:54:55.668446 start: 1.6.7 compress-ramdisk (timeout 00:09:34) [common]
264 11:54:55.668566 Building ramdisk /var/lib/lava/dispatcher/tmp/12066552/extract-overlay-ramdisk-je1gjau4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066552/extract-overlay-ramdisk-je1gjau4/ramdisk
265 11:54:56.007750 >> 119398 blocks
266 11:54:57.919676 rename /var/lib/lava/dispatcher/tmp/12066552/extract-overlay-ramdisk-je1gjau4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/ramdisk/ramdisk.cpio.gz
267 11:54:57.920120 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:54:57.920256 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 11:54:57.920365 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 11:54:57.920474 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/kernel/Image'
271 11:55:09.834862 Returned 0 in 11 seconds
272 11:55:09.935852 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/kernel/image.itb
273 11:55:10.327436 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:55:10.327877 output: Created: Thu Nov 23 11:55:10 2023
275 11:55:10.328033 output: Image 0 (kernel-1)
276 11:55:10.328130 output: Description:
277 11:55:10.328225 output: Created: Thu Nov 23 11:55:10 2023
278 11:55:10.328316 output: Type: Kernel Image
279 11:55:10.328405 output: Compression: lzma compressed
280 11:55:10.328527 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
281 11:55:10.328629 output: Architecture: AArch64
282 11:55:10.328729 output: OS: Linux
283 11:55:10.328828 output: Load Address: 0x00000000
284 11:55:10.328926 output: Entry Point: 0x00000000
285 11:55:10.329012 output: Hash algo: crc32
286 11:55:10.329097 output: Hash value: e6d7c86f
287 11:55:10.329182 output: Image 1 (fdt-1)
288 11:55:10.329237 output: Description: mt8192-asurada-spherion-r0
289 11:55:10.329290 output: Created: Thu Nov 23 11:55:10 2023
290 11:55:10.329344 output: Type: Flat Device Tree
291 11:55:10.329442 output: Compression: uncompressed
292 11:55:10.329508 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:55:10.329575 output: Architecture: AArch64
294 11:55:10.329641 output: Hash algo: crc32
295 11:55:10.329693 output: Hash value: cc4352de
296 11:55:10.329744 output: Image 2 (ramdisk-1)
297 11:55:10.329796 output: Description: unavailable
298 11:55:10.329862 output: Created: Thu Nov 23 11:55:10 2023
299 11:55:10.329928 output: Type: RAMDisk Image
300 11:55:10.329979 output: Compression: Unknown Compression
301 11:55:10.330030 output: Data Size: 17793070 Bytes = 17376.04 KiB = 16.97 MiB
302 11:55:10.330082 output: Architecture: AArch64
303 11:55:10.330133 output: OS: Linux
304 11:55:10.330184 output: Load Address: unavailable
305 11:55:10.330256 output: Entry Point: unavailable
306 11:55:10.330323 output: Hash algo: crc32
307 11:55:10.330374 output: Hash value: baced620
308 11:55:10.330426 output: Default Configuration: 'conf-1'
309 11:55:10.330477 output: Configuration 0 (conf-1)
310 11:55:10.330528 output: Description: mt8192-asurada-spherion-r0
311 11:55:10.330579 output: Kernel: kernel-1
312 11:55:10.330630 output: Init Ramdisk: ramdisk-1
313 11:55:10.330681 output: FDT: fdt-1
314 11:55:10.330732 output: Loadables: kernel-1
315 11:55:10.330783 output:
316 11:55:10.330983 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 11:55:10.331082 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 11:55:10.331188 end: 1.6 prepare-tftp-overlay (duration 00:00:32) [common]
319 11:55:10.331301 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 11:55:10.331383 No LXC device requested
321 11:55:10.331462 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:55:10.331547 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 11:55:10.331625 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:55:10.331700 Checking files for TFTP limit of 4294967296 bytes.
325 11:55:10.332208 end: 1 tftp-deploy (duration 00:00:41) [common]
326 11:55:10.332318 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:55:10.332415 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:55:10.332541 substitutions:
329 11:55:10.332609 - {DTB}: 12066552/tftp-deploy-2cwi2ezc/dtb/mt8192-asurada-spherion-r0.dtb
330 11:55:10.332673 - {INITRD}: 12066552/tftp-deploy-2cwi2ezc/ramdisk/ramdisk.cpio.gz
331 11:55:10.332731 - {KERNEL}: 12066552/tftp-deploy-2cwi2ezc/kernel/Image
332 11:55:10.332788 - {LAVA_MAC}: None
333 11:55:10.332844 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl
334 11:55:10.332899 - {NFS_SERVER_IP}: 192.168.201.1
335 11:55:10.332953 - {PRESEED_CONFIG}: None
336 11:55:10.333007 - {PRESEED_LOCAL}: None
337 11:55:10.333060 - {RAMDISK}: 12066552/tftp-deploy-2cwi2ezc/ramdisk/ramdisk.cpio.gz
338 11:55:10.333113 - {ROOT_PART}: None
339 11:55:10.333166 - {ROOT}: None
340 11:55:10.333230 - {SERVER_IP}: 192.168.201.1
341 11:55:10.333316 - {TEE}: None
342 11:55:10.333387 Parsed boot commands:
343 11:55:10.333440 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:55:10.333623 Parsed boot commands: tftpboot 192.168.201.1 12066552/tftp-deploy-2cwi2ezc/kernel/image.itb 12066552/tftp-deploy-2cwi2ezc/kernel/cmdline
345 11:55:10.333709 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:55:10.333862 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:55:10.334012 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:55:10.334210 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:55:10.334329 Not connected, no need to disconnect.
350 11:55:10.334407 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:55:10.334488 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:55:10.334556 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 11:55:10.338522 Setting prompt string to ['lava-test: # ']
354 11:55:10.338891 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:55:10.339006 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:55:10.339101 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:55:10.339187 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:55:10.339386 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 11:55:15.490379 >> Command sent successfully.
360 11:55:15.492882 Returned 0 in 5 seconds
361 11:55:15.593342 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:55:15.593957 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:55:15.594155 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:55:15.594341 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:55:15.594456 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:55:15.594562 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:55:15.594960 [Enter `^Ec?' for help]
369 11:55:15.766314
370 11:55:15.766657
371 11:55:15.766851 F0: 102B 0000
372 11:55:15.767027
373 11:55:15.767188 F3: 1001 0000 [0200]
374 11:55:15.769023
375 11:55:15.769225 F3: 1001 0000
376 11:55:15.769372
377 11:55:15.769504 F7: 102D 0000
378 11:55:15.769632
379 11:55:15.772535 F1: 0000 0000
380 11:55:15.772719
381 11:55:15.772863 V0: 0000 0000 [0001]
382 11:55:15.773004
383 11:55:15.775648 00: 0007 8000
384 11:55:15.775808
385 11:55:15.775930 01: 0000 0000
386 11:55:15.776095
387 11:55:15.779388 BP: 0C00 0209 [0000]
388 11:55:15.779541
389 11:55:15.779662 G0: 1182 0000
390 11:55:15.779774
391 11:55:15.782533 EC: 0000 0021 [4000]
392 11:55:15.782685
393 11:55:15.782804 S7: 0000 0000 [0000]
394 11:55:15.782915
395 11:55:15.786825 CC: 0000 0000 [0001]
396 11:55:15.787247
397 11:55:15.787583 T0: 0000 0040 [010F]
398 11:55:15.787892
399 11:55:15.788187 Jump to BL
400 11:55:15.788476
401 11:55:15.814245
402 11:55:15.814768
403 11:55:15.815110
404 11:55:15.820591 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:55:15.824370 ARM64: Exception handlers installed.
406 11:55:15.827591 ARM64: Testing exception
407 11:55:15.831208 ARM64: Done test exception
408 11:55:15.837840 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:55:15.847832 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:55:15.854102 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:55:15.864353 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:55:15.870718 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:55:15.877876 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:55:15.889493 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:55:15.896584 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:55:15.916015 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:55:15.918949 WDT: Last reset was cold boot
418 11:55:15.922610 SPI1(PAD0) initialized at 2873684 Hz
419 11:55:15.925577 SPI5(PAD0) initialized at 992727 Hz
420 11:55:15.928926 VBOOT: Loading verstage.
421 11:55:15.936141 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:55:15.939434 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:55:15.942909 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:55:15.945850 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:55:15.953603 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:55:15.960278 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:55:15.970832 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:55:15.971154
429 11:55:15.971400
430 11:55:15.981402 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:55:15.983894 ARM64: Exception handlers installed.
432 11:55:15.987419 ARM64: Testing exception
433 11:55:15.987826 ARM64: Done test exception
434 11:55:15.994915 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:55:15.998666 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:55:16.012750 Probing TPM: . done!
437 11:55:16.013158 TPM ready after 0 ms
438 11:55:16.021647 Connected to device vid:did:rid of 1ae0:0028:00
439 11:55:16.027767 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 11:55:16.084666 Initialized TPM device CR50 revision 0
441 11:55:16.095836 tlcl_send_startup: Startup return code is 0
442 11:55:16.096269 TPM: setup succeeded
443 11:55:16.107532 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:55:16.116943 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:55:16.128634 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:55:16.139187 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:55:16.142214 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:55:16.147542 in-header: 03 07 00 00 08 00 00 00
449 11:55:16.150335 in-data: aa e4 47 04 13 02 00 00
450 11:55:16.153664 Chrome EC: UHEPI supported
451 11:55:16.160772 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:55:16.164897 in-header: 03 95 00 00 08 00 00 00
453 11:55:16.167927 in-data: 18 20 20 08 00 00 00 00
454 11:55:16.168383 Phase 1
455 11:55:16.171883 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:55:16.179537 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:55:16.182939 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:55:16.186466 Recovery requested (1009000e)
459 11:55:16.195534 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:55:16.200621 tlcl_extend: response is 0
461 11:55:16.210483 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:55:16.216288 tlcl_extend: response is 0
463 11:55:16.223702 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:55:16.243561 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:55:16.249767 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:55:16.250332
467 11:55:16.250680
468 11:55:16.259646 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:55:16.263005 ARM64: Exception handlers installed.
470 11:55:16.266177 ARM64: Testing exception
471 11:55:16.266763 ARM64: Done test exception
472 11:55:16.288743 pmic_efuse_setting: Set efuses in 11 msecs
473 11:55:16.292001 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:55:16.298519 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:55:16.301460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:55:16.308869 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:55:16.312283 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:55:16.316026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:55:16.323546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:55:16.326660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:55:16.330167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:55:16.337467 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:55:16.341318 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:55:16.344985 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:55:16.348823 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:55:16.353011 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:55:16.360623 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:55:16.367398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:55:16.371236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:55:16.378870 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:55:16.382182 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:55:16.390395 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:55:16.393525 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:55:16.400246 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:55:16.407544 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:55:16.411145 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:55:16.414792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:55:16.422927 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:55:16.429701 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:55:16.433087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:55:16.436369 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:55:16.444014 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:55:16.447539 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:55:16.450737 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:55:16.458030 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:55:16.462354 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:55:16.468924 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:55:16.473149 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:55:16.476148 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:55:16.483365 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:55:16.487206 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:55:16.491383 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:55:16.494664 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:55:16.501796 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:55:16.505382 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:55:16.508615 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:55:16.513249 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:55:16.516600 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:55:16.524103 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:55:16.527215 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:55:16.530844 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:55:16.534283 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:55:16.538329 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:55:16.542336 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:55:16.553041 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:55:16.559911 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:55:16.563425 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:55:16.574348 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:55:16.582113 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:55:16.585555 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:55:16.590081 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:55:16.592755 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:55:16.602204 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 11:55:16.605089 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:55:16.613739 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 11:55:16.616910 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:55:16.625850 [RTC]rtc_get_frequency_meter,154: input=15, output=852
538 11:55:16.635111 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 11:55:16.644638 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 11:55:16.654760 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 11:55:16.663716 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 11:55:16.673080 [RTC]rtc_get_frequency_meter,154: input=11, output=790
543 11:55:16.683903 [RTC]rtc_get_frequency_meter,154: input=12, output=804
544 11:55:16.687060 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 11:55:16.690745 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 11:55:16.694464 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:55:16.701762 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:55:16.705514 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:55:16.709328 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:55:16.712564 ADC[4]: Raw value=904064 ID=7
551 11:55:16.712993 ADC[3]: Raw value=213916 ID=1
552 11:55:16.716961 RAM Code: 0x71
553 11:55:16.720256 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:55:16.723883 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:55:16.735115 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:55:16.738685 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:55:16.742036 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:55:16.746663 in-header: 03 07 00 00 08 00 00 00
559 11:55:16.749904 in-data: aa e4 47 04 13 02 00 00
560 11:55:16.753843 Chrome EC: UHEPI supported
561 11:55:16.761579 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:55:16.764211 in-header: 03 95 00 00 08 00 00 00
563 11:55:16.768570 in-data: 18 20 20 08 00 00 00 00
564 11:55:16.772737 MRC: failed to locate region type 0.
565 11:55:16.775390 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:55:16.779039 DRAM-K: Running full calibration
567 11:55:16.786689 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:55:16.787213 header.status = 0x0
569 11:55:16.790412 header.version = 0x6 (expected: 0x6)
570 11:55:16.793539 header.size = 0xd00 (expected: 0xd00)
571 11:55:16.797676 header.flags = 0x0
572 11:55:16.800850 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:55:16.820574 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:55:16.827702 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:55:16.831391 dram_init: ddr_geometry: 2
576 11:55:16.831816 [EMI] MDL number = 2
577 11:55:16.834984 [EMI] Get MDL freq = 0
578 11:55:16.835449 dram_init: ddr_type: 0
579 11:55:16.838999 is_discrete_lpddr4: 1
580 11:55:16.842848 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:55:16.843378
582 11:55:16.843821
583 11:55:16.844144 [Bian_co] ETT version 0.0.0.1
584 11:55:16.849981 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:55:16.850561
586 11:55:16.854163 dramc_set_vcore_voltage set vcore to 650000
587 11:55:16.854776 Read voltage for 800, 4
588 11:55:16.857954 Vio18 = 0
589 11:55:16.858563 Vcore = 650000
590 11:55:16.858911 Vdram = 0
591 11:55:16.859228 Vddq = 0
592 11:55:16.861558 Vmddr = 0
593 11:55:16.862092 dram_init: config_dvfs: 1
594 11:55:16.869316 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:55:16.872357 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:55:16.875620 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 11:55:16.878636 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 11:55:16.885547 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 11:55:16.889560 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 11:55:16.890096 MEM_TYPE=3, freq_sel=18
601 11:55:16.892940 sv_algorithm_assistance_LP4_1600
602 11:55:16.896316 ============ PULL DRAM RESETB DOWN ============
603 11:55:16.903196 ========== PULL DRAM RESETB DOWN end =========
604 11:55:16.906521 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:55:16.909845 ===================================
606 11:55:16.912890 LPDDR4 DRAM CONFIGURATION
607 11:55:16.916744 ===================================
608 11:55:16.917171 EX_ROW_EN[0] = 0x0
609 11:55:16.920358 EX_ROW_EN[1] = 0x0
610 11:55:16.920884 LP4Y_EN = 0x0
611 11:55:16.923259 WORK_FSP = 0x0
612 11:55:16.923708 WL = 0x2
613 11:55:16.926301 RL = 0x2
614 11:55:16.926827 BL = 0x2
615 11:55:16.929800 RPST = 0x0
616 11:55:16.930427 RD_PRE = 0x0
617 11:55:16.932908 WR_PRE = 0x1
618 11:55:16.933335 WR_PST = 0x0
619 11:55:16.936729 DBI_WR = 0x0
620 11:55:16.937252 DBI_RD = 0x0
621 11:55:16.940109 OTF = 0x1
622 11:55:16.943719 ===================================
623 11:55:16.946789 ===================================
624 11:55:16.947500 ANA top config
625 11:55:16.949431 ===================================
626 11:55:16.953024 DLL_ASYNC_EN = 0
627 11:55:16.956300 ALL_SLAVE_EN = 1
628 11:55:16.960085 NEW_RANK_MODE = 1
629 11:55:16.960618 DLL_IDLE_MODE = 1
630 11:55:16.962949 LP45_APHY_COMB_EN = 1
631 11:55:16.966563 TX_ODT_DIS = 1
632 11:55:16.969530 NEW_8X_MODE = 1
633 11:55:16.972813 ===================================
634 11:55:16.976547 ===================================
635 11:55:16.979708 data_rate = 1600
636 11:55:16.982962 CKR = 1
637 11:55:16.983535 DQ_P2S_RATIO = 8
638 11:55:16.986197 ===================================
639 11:55:16.989813 CA_P2S_RATIO = 8
640 11:55:16.993251 DQ_CA_OPEN = 0
641 11:55:16.996120 DQ_SEMI_OPEN = 0
642 11:55:16.999536 CA_SEMI_OPEN = 0
643 11:55:16.999962 CA_FULL_RATE = 0
644 11:55:17.003000 DQ_CKDIV4_EN = 1
645 11:55:17.006792 CA_CKDIV4_EN = 1
646 11:55:17.010426 CA_PREDIV_EN = 0
647 11:55:17.013199 PH8_DLY = 0
648 11:55:17.016692 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:55:17.017267 DQ_AAMCK_DIV = 4
650 11:55:17.019488 CA_AAMCK_DIV = 4
651 11:55:17.023547 CA_ADMCK_DIV = 4
652 11:55:17.026538 DQ_TRACK_CA_EN = 0
653 11:55:17.029683 CA_PICK = 800
654 11:55:17.033884 CA_MCKIO = 800
655 11:55:17.034345 MCKIO_SEMI = 0
656 11:55:17.036970 PLL_FREQ = 3068
657 11:55:17.040541 DQ_UI_PI_RATIO = 32
658 11:55:17.044841 CA_UI_PI_RATIO = 0
659 11:55:17.048388 ===================================
660 11:55:17.048954 ===================================
661 11:55:17.052003 memory_type:LPDDR4
662 11:55:17.055523 GP_NUM : 10
663 11:55:17.056045 SRAM_EN : 1
664 11:55:17.059177 MD32_EN : 0
665 11:55:17.063158 ===================================
666 11:55:17.063731 [ANA_INIT] >>>>>>>>>>>>>>
667 11:55:17.066744 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:55:17.070861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:55:17.074448 ===================================
670 11:55:17.077175 data_rate = 1600,PCW = 0X7600
671 11:55:17.080573 ===================================
672 11:55:17.084402 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:55:17.087138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:55:17.093856 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:55:17.097357 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:55:17.100187 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:55:17.106926 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:55:17.107490 [ANA_INIT] flow start
679 11:55:17.110645 [ANA_INIT] PLL >>>>>>>>
680 11:55:17.114107 [ANA_INIT] PLL <<<<<<<<
681 11:55:17.114726 [ANA_INIT] MIDPI >>>>>>>>
682 11:55:17.116840 [ANA_INIT] MIDPI <<<<<<<<
683 11:55:17.120413 [ANA_INIT] DLL >>>>>>>>
684 11:55:17.120982 [ANA_INIT] flow end
685 11:55:17.123476 ============ LP4 DIFF to SE enter ============
686 11:55:17.130104 ============ LP4 DIFF to SE exit ============
687 11:55:17.130740 [ANA_INIT] <<<<<<<<<<<<<
688 11:55:17.133732 [Flow] Enable top DCM control >>>>>
689 11:55:17.137092 [Flow] Enable top DCM control <<<<<
690 11:55:17.139946 Enable DLL master slave shuffle
691 11:55:17.146127 ==============================================================
692 11:55:17.149744 Gating Mode config
693 11:55:17.152828 ==============================================================
694 11:55:17.156340 Config description:
695 11:55:17.166416 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:55:17.173181 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:55:17.176671 SELPH_MODE 0: By rank 1: By Phase
698 11:55:17.183654 ==============================================================
699 11:55:17.186406 GAT_TRACK_EN = 1
700 11:55:17.189787 RX_GATING_MODE = 2
701 11:55:17.193406 RX_GATING_TRACK_MODE = 2
702 11:55:17.193982 SELPH_MODE = 1
703 11:55:17.196246 PICG_EARLY_EN = 1
704 11:55:17.199661 VALID_LAT_VALUE = 1
705 11:55:17.206844 ==============================================================
706 11:55:17.209371 Enter into Gating configuration >>>>
707 11:55:17.212505 Exit from Gating configuration <<<<
708 11:55:17.216145 Enter into DVFS_PRE_config >>>>>
709 11:55:17.226223 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:55:17.229385 Exit from DVFS_PRE_config <<<<<
711 11:55:17.233476 Enter into PICG configuration >>>>
712 11:55:17.235841 Exit from PICG configuration <<<<
713 11:55:17.239762 [RX_INPUT] configuration >>>>>
714 11:55:17.243168 [RX_INPUT] configuration <<<<<
715 11:55:17.245863 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:55:17.252710 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:55:17.259211 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:55:17.265983 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:55:17.268944 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:55:17.275694 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:55:17.282401 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:55:17.286358 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:55:17.289601 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:55:17.292532 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:55:17.295878 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:55:17.302711 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:55:17.306093 ===================================
728 11:55:17.309091 LPDDR4 DRAM CONFIGURATION
729 11:55:17.312519 ===================================
730 11:55:17.313060 EX_ROW_EN[0] = 0x0
731 11:55:17.315440 EX_ROW_EN[1] = 0x0
732 11:55:17.315874 LP4Y_EN = 0x0
733 11:55:17.318618 WORK_FSP = 0x0
734 11:55:17.319052 WL = 0x2
735 11:55:17.322452 RL = 0x2
736 11:55:17.322993 BL = 0x2
737 11:55:17.325772 RPST = 0x0
738 11:55:17.326333 RD_PRE = 0x0
739 11:55:17.329065 WR_PRE = 0x1
740 11:55:17.329502 WR_PST = 0x0
741 11:55:17.332563 DBI_WR = 0x0
742 11:55:17.333034 DBI_RD = 0x0
743 11:55:17.335792 OTF = 0x1
744 11:55:17.339016 ===================================
745 11:55:17.342695 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:55:17.345514 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:55:17.352533 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:55:17.355310 ===================================
749 11:55:17.355850 LPDDR4 DRAM CONFIGURATION
750 11:55:17.358554 ===================================
751 11:55:17.361817 EX_ROW_EN[0] = 0x10
752 11:55:17.365215 EX_ROW_EN[1] = 0x0
753 11:55:17.365753 LP4Y_EN = 0x0
754 11:55:17.368974 WORK_FSP = 0x0
755 11:55:17.369513 WL = 0x2
756 11:55:17.372133 RL = 0x2
757 11:55:17.372736 BL = 0x2
758 11:55:17.375275 RPST = 0x0
759 11:55:17.375710 RD_PRE = 0x0
760 11:55:17.378387 WR_PRE = 0x1
761 11:55:17.378823 WR_PST = 0x0
762 11:55:17.382079 DBI_WR = 0x0
763 11:55:17.382554 DBI_RD = 0x0
764 11:55:17.385093 OTF = 0x1
765 11:55:17.389014 ===================================
766 11:55:17.394964 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:55:17.399184 nWR fixed to 40
768 11:55:17.402074 [ModeRegInit_LP4] CH0 RK0
769 11:55:17.402571 [ModeRegInit_LP4] CH0 RK1
770 11:55:17.405351 [ModeRegInit_LP4] CH1 RK0
771 11:55:17.408264 [ModeRegInit_LP4] CH1 RK1
772 11:55:17.408703 match AC timing 13
773 11:55:17.415243 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:55:17.418627 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:55:17.422170 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:55:17.428926 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:55:17.432024 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:55:17.432533 [EMI DOE] emi_dcm 0
779 11:55:17.438440 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:55:17.438977 ==
781 11:55:17.442009 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:55:17.445518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:55:17.446056 ==
784 11:55:17.451539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:55:17.458413 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:55:17.465692 [CA 0] Center 37 (7~68) winsize 62
787 11:55:17.468713 [CA 1] Center 37 (6~68) winsize 63
788 11:55:17.472020 [CA 2] Center 35 (5~65) winsize 61
789 11:55:17.475780 [CA 3] Center 34 (4~65) winsize 62
790 11:55:17.478754 [CA 4] Center 33 (3~64) winsize 62
791 11:55:17.481729 [CA 5] Center 33 (3~64) winsize 62
792 11:55:17.482163
793 11:55:17.485873 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:55:17.486465
795 11:55:17.489807 [CATrainingPosCal] consider 1 rank data
796 11:55:17.492287 u2DelayCellTimex100 = 270/100 ps
797 11:55:17.495996 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:55:17.502436 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:55:17.505864 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
800 11:55:17.508581 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:55:17.512243 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:55:17.515055 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:55:17.515489
804 11:55:17.518341 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:55:17.518865
806 11:55:17.521811 [CBTSetCACLKResult] CA Dly = 33
807 11:55:17.525498 CS Dly: 5 (0~36)
808 11:55:17.525930 ==
809 11:55:17.528342 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:55:17.531588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:55:17.532021 ==
812 11:55:17.538687 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:55:17.542129 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:55:17.552528 [CA 0] Center 38 (7~69) winsize 63
815 11:55:17.555432 [CA 1] Center 37 (7~68) winsize 62
816 11:55:17.558859 [CA 2] Center 35 (4~66) winsize 63
817 11:55:17.562007 [CA 3] Center 35 (4~66) winsize 63
818 11:55:17.565526 [CA 4] Center 34 (3~65) winsize 63
819 11:55:17.569063 [CA 5] Center 33 (3~64) winsize 62
820 11:55:17.569645
821 11:55:17.571709 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:55:17.572191
823 11:55:17.575766 [CATrainingPosCal] consider 2 rank data
824 11:55:17.578676 u2DelayCellTimex100 = 270/100 ps
825 11:55:17.581989 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:55:17.585421 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:55:17.592107 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
828 11:55:17.595456 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:55:17.598932 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:55:17.602215 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:55:17.602746
832 11:55:17.605918 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:55:17.606557
834 11:55:17.608677 [CBTSetCACLKResult] CA Dly = 33
835 11:55:17.609156 CS Dly: 6 (0~38)
836 11:55:17.609534
837 11:55:17.615132 ----->DramcWriteLeveling(PI) begin...
838 11:55:17.615572 ==
839 11:55:17.619067 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:55:17.622720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:55:17.623296 ==
842 11:55:17.626614 Write leveling (Byte 0): 28 => 28
843 11:55:17.627152 Write leveling (Byte 1): 26 => 26
844 11:55:17.630127 DramcWriteLeveling(PI) end<-----
845 11:55:17.630609
846 11:55:17.630970 ==
847 11:55:17.633304 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:55:17.636558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:55:17.640408 ==
850 11:55:17.640945 [Gating] SW mode calibration
851 11:55:17.647086 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:55:17.654093 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:55:17.657691 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:55:17.664157 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:55:17.668268 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:55:17.670720 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 11:55:17.677056 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:55:17.680832 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:55:17.684424 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:55:17.687474 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:55:17.693889 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:55:17.697263 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:55:17.700735 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:55:17.707073 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:55:17.710596 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:55:17.713967 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:55:17.720091 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:55:17.723638 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:55:17.727493 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:55:17.733813 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
871 11:55:17.736822 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 11:55:17.739960 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:55:17.747284 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:55:17.750192 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:55:17.753355 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:55:17.760201 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:55:17.763439 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:55:17.766334 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:55:17.773254 0 9 8 | B1->B0 | 2323 3232 | 1 0 | (1 1) (0 0)
880 11:55:17.777080 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
881 11:55:17.780001 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:55:17.786699 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:55:17.789879 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:55:17.793236 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:55:17.799748 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:55:17.803158 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 11:55:17.806536 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 1) (0 0)
888 11:55:17.813426 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 11:55:17.816706 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:55:17.819738 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:55:17.826474 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:55:17.829638 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:55:17.832781 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:55:17.836195 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
895 11:55:17.843065 0 11 8 | B1->B0 | 2d2d 3f3f | 0 0 | (1 1) (0 0)
896 11:55:17.846501 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
897 11:55:17.850097 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:55:17.856669 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:55:17.860314 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:55:17.863689 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:55:17.869898 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:55:17.873509 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:55:17.875972 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 11:55:17.883152 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:55:17.886619 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:55:17.889984 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:55:17.896458 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:55:17.899950 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:55:17.902810 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:55:17.909964 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:55:17.913087 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:55:17.916921 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:55:17.922906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:55:17.926330 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:55:17.930318 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:55:17.935996 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:55:17.939481 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:55:17.942627 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:55:17.949182 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 11:55:17.952439 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 11:55:17.956529 Total UI for P1: 0, mck2ui 16
922 11:55:17.959106 best dqsien dly found for B0: ( 0, 14, 8)
923 11:55:17.962637 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:55:17.965943 Total UI for P1: 0, mck2ui 16
925 11:55:17.969811 best dqsien dly found for B1: ( 0, 14, 10)
926 11:55:17.972476 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 11:55:17.975512 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 11:55:17.976008
929 11:55:17.979310 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:55:17.986131 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 11:55:17.986767 [Gating] SW calibration Done
932 11:55:17.987159 ==
933 11:55:17.990565 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:55:17.993716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:55:17.996500 ==
936 11:55:17.996972 RX Vref Scan: 0
937 11:55:17.997343
938 11:55:18.000377 RX Vref 0 -> 0, step: 1
939 11:55:18.000954
940 11:55:18.002959 RX Delay -130 -> 252, step: 16
941 11:55:18.006887 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
942 11:55:18.010210 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 11:55:18.012953 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
944 11:55:18.016838 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
945 11:55:18.023227 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 11:55:18.026737 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 11:55:18.029818 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 11:55:18.033289 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
949 11:55:18.036785 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
950 11:55:18.043647 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
951 11:55:18.046355 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 11:55:18.050359 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 11:55:18.052790 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 11:55:18.056693 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 11:55:18.063228 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 11:55:18.066881 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 11:55:18.067313 ==
958 11:55:18.069672 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:55:18.072958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:55:18.073389 ==
961 11:55:18.075932 DQS Delay:
962 11:55:18.076629 DQS0 = 0, DQS1 = 0
963 11:55:18.077095 DQM Delay:
964 11:55:18.080025 DQM0 = 92, DQM1 = 76
965 11:55:18.080450 DQ Delay:
966 11:55:18.083126 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
967 11:55:18.086373 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
968 11:55:18.089670 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
969 11:55:18.093229 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 11:55:18.093764
971 11:55:18.094104
972 11:55:18.094475 ==
973 11:55:18.096252 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:55:18.102797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:55:18.103330 ==
976 11:55:18.103674
977 11:55:18.103985
978 11:55:18.104280 TX Vref Scan disable
979 11:55:18.106280 == TX Byte 0 ==
980 11:55:18.109788 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
981 11:55:18.116996 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
982 11:55:18.117529 == TX Byte 1 ==
983 11:55:18.119866 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
984 11:55:18.126795 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
985 11:55:18.127329 ==
986 11:55:18.130407 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:55:18.133179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:55:18.133662 ==
989 11:55:18.145531 TX Vref=22, minBit 1, minWin=26, winSum=434
990 11:55:18.149524 TX Vref=24, minBit 0, minWin=27, winSum=442
991 11:55:18.151974 TX Vref=26, minBit 0, minWin=27, winSum=446
992 11:55:18.155340 TX Vref=28, minBit 7, minWin=27, winSum=450
993 11:55:18.158706 TX Vref=30, minBit 1, minWin=27, winSum=450
994 11:55:18.165408 TX Vref=32, minBit 1, minWin=27, winSum=445
995 11:55:18.169127 [TxChooseVref] Worse bit 7, Min win 27, Win sum 450, Final Vref 28
996 11:55:18.169660
997 11:55:18.172138 Final TX Range 1 Vref 28
998 11:55:18.172566
999 11:55:18.172903 ==
1000 11:55:18.175196 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:55:18.178758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:55:18.179192 ==
1003 11:55:18.181962
1004 11:55:18.182425
1005 11:55:18.182765 TX Vref Scan disable
1006 11:55:18.186208 == TX Byte 0 ==
1007 11:55:18.188735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1008 11:55:18.191882 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1009 11:55:18.195568 == TX Byte 1 ==
1010 11:55:18.198805 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1011 11:55:18.202825 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1012 11:55:18.205176
1013 11:55:18.205604 [DATLAT]
1014 11:55:18.205944 Freq=800, CH0 RK0
1015 11:55:18.206308
1016 11:55:18.208718 DATLAT Default: 0xa
1017 11:55:18.209146 0, 0xFFFF, sum = 0
1018 11:55:18.212313 1, 0xFFFF, sum = 0
1019 11:55:18.212875 2, 0xFFFF, sum = 0
1020 11:55:18.215537 3, 0xFFFF, sum = 0
1021 11:55:18.215974 4, 0xFFFF, sum = 0
1022 11:55:18.218864 5, 0xFFFF, sum = 0
1023 11:55:18.221906 6, 0xFFFF, sum = 0
1024 11:55:18.222529 7, 0xFFFF, sum = 0
1025 11:55:18.225743 8, 0xFFFF, sum = 0
1026 11:55:18.226328 9, 0x0, sum = 1
1027 11:55:18.226689 10, 0x0, sum = 2
1028 11:55:18.228825 11, 0x0, sum = 3
1029 11:55:18.229360 12, 0x0, sum = 4
1030 11:55:18.231630 best_step = 10
1031 11:55:18.232053
1032 11:55:18.232385 ==
1033 11:55:18.235216 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:55:18.238664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:55:18.239199 ==
1036 11:55:18.241710 RX Vref Scan: 1
1037 11:55:18.242233
1038 11:55:18.244834 Set Vref Range= 32 -> 127
1039 11:55:18.245261
1040 11:55:18.245598 RX Vref 32 -> 127, step: 1
1041 11:55:18.245915
1042 11:55:18.248503 RX Delay -111 -> 252, step: 8
1043 11:55:18.249033
1044 11:55:18.251692 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:55:18.255231 [Byte1]: 32
1046 11:55:18.258287
1047 11:55:18.258825 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:55:18.264839 [Byte1]: 33
1049 11:55:18.265411
1050 11:55:18.268144 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:55:18.271663 [Byte1]: 34
1052 11:55:18.272227
1053 11:55:18.274877 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:55:18.277563 [Byte1]: 35
1055 11:55:18.281299
1056 11:55:18.281821 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:55:18.284788 [Byte1]: 36
1058 11:55:18.288980
1059 11:55:18.289505 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:55:18.292369 [Byte1]: 37
1061 11:55:18.297010
1062 11:55:18.297436 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:55:18.299578 [Byte1]: 38
1064 11:55:18.304486
1065 11:55:18.304910 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:55:18.307643 [Byte1]: 39
1067 11:55:18.311969
1068 11:55:18.312390 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:55:18.315276 [Byte1]: 40
1070 11:55:18.319808
1071 11:55:18.320347 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:55:18.322764 [Byte1]: 41
1073 11:55:18.326947
1074 11:55:18.327487 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:55:18.330320 [Byte1]: 42
1076 11:55:18.334939
1077 11:55:18.335416 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:55:18.338055 [Byte1]: 43
1079 11:55:18.342680
1080 11:55:18.343205 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:55:18.345702 [Byte1]: 44
1082 11:55:18.350542
1083 11:55:18.351070 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:55:18.353501 [Byte1]: 45
1085 11:55:18.357942
1086 11:55:18.358515 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:55:18.361216 [Byte1]: 46
1088 11:55:18.365415
1089 11:55:18.365943 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:55:18.368763 [Byte1]: 47
1091 11:55:18.372893
1092 11:55:18.373418 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:55:18.376263 [Byte1]: 48
1094 11:55:18.380628
1095 11:55:18.381052 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:55:18.383753 [Byte1]: 49
1097 11:55:18.388550
1098 11:55:18.389079 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:55:18.392289 [Byte1]: 50
1100 11:55:18.395823
1101 11:55:18.396352 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:55:18.398988 [Byte1]: 51
1103 11:55:18.403661
1104 11:55:18.404190 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:55:18.406474 [Byte1]: 52
1106 11:55:18.411741
1107 11:55:18.412270 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:55:18.414037 [Byte1]: 53
1109 11:55:18.418674
1110 11:55:18.419197 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:55:18.422360 [Byte1]: 54
1112 11:55:18.426079
1113 11:55:18.429929 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:55:18.433005 [Byte1]: 55
1115 11:55:18.433434
1116 11:55:18.436455 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:55:18.439778 [Byte1]: 56
1118 11:55:18.440307
1119 11:55:18.443009 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:55:18.446294 [Byte1]: 57
1121 11:55:18.449280
1122 11:55:18.449806 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:55:18.453042 [Byte1]: 58
1124 11:55:18.456879
1125 11:55:18.457402 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:55:18.460899 [Byte1]: 59
1127 11:55:18.465119
1128 11:55:18.465644 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:55:18.468496 [Byte1]: 60
1130 11:55:18.472718
1131 11:55:18.473245 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:55:18.475407 [Byte1]: 61
1133 11:55:18.480077
1134 11:55:18.480499 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:55:18.482974 [Byte1]: 62
1136 11:55:18.487974
1137 11:55:18.488500 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:55:18.491111 [Byte1]: 63
1139 11:55:18.495345
1140 11:55:18.495871 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:55:18.498352 [Byte1]: 64
1142 11:55:18.502836
1143 11:55:18.503355 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:55:18.506405 [Byte1]: 65
1145 11:55:18.511043
1146 11:55:18.511603 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:55:18.513838 [Byte1]: 66
1148 11:55:18.517982
1149 11:55:18.518458 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:55:18.521613 [Byte1]: 67
1151 11:55:18.526080
1152 11:55:18.526641 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:55:18.529671 [Byte1]: 68
1154 11:55:18.533896
1155 11:55:18.534513 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:55:18.536761 [Byte1]: 69
1157 11:55:18.541394
1158 11:55:18.541962 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:55:18.544912 [Byte1]: 70
1160 11:55:18.549226
1161 11:55:18.549693 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:55:18.552154 [Byte1]: 71
1163 11:55:18.556772
1164 11:55:18.557298 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:55:18.559839 [Byte1]: 72
1166 11:55:18.564375
1167 11:55:18.564905 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:55:18.567802 [Byte1]: 73
1169 11:55:18.572144
1170 11:55:18.572669 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:55:18.575036 [Byte1]: 74
1172 11:55:18.579108
1173 11:55:18.579710 Final RX Vref Byte 0 = 52 to rank0
1174 11:55:18.582815 Final RX Vref Byte 1 = 59 to rank0
1175 11:55:18.586173 Final RX Vref Byte 0 = 52 to rank1
1176 11:55:18.589672 Final RX Vref Byte 1 = 59 to rank1==
1177 11:55:18.592696 Dram Type= 6, Freq= 0, CH_0, rank 0
1178 11:55:18.598826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 11:55:18.599371 ==
1180 11:55:18.599712 DQS Delay:
1181 11:55:18.600027 DQS0 = 0, DQS1 = 0
1182 11:55:18.602637 DQM Delay:
1183 11:55:18.603063 DQM0 = 88, DQM1 = 77
1184 11:55:18.605787 DQ Delay:
1185 11:55:18.609250 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =80
1186 11:55:18.612709 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1187 11:55:18.615791 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =72
1188 11:55:18.619102 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1189 11:55:18.619528
1190 11:55:18.619862
1191 11:55:18.625958 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1192 11:55:18.629491 CH0 RK0: MR19=606, MR18=342D
1193 11:55:18.635671 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1194 11:55:18.636251
1195 11:55:18.638994 ----->DramcWriteLeveling(PI) begin...
1196 11:55:18.639426 ==
1197 11:55:18.641978 Dram Type= 6, Freq= 0, CH_0, rank 1
1198 11:55:18.645765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1199 11:55:18.646342 ==
1200 11:55:18.649049 Write leveling (Byte 0): 30 => 30
1201 11:55:18.652197 Write leveling (Byte 1): 29 => 29
1202 11:55:18.656044 DramcWriteLeveling(PI) end<-----
1203 11:55:18.656573
1204 11:55:18.656908 ==
1205 11:55:18.658679 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:55:18.662241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:55:18.662804 ==
1208 11:55:18.665580 [Gating] SW mode calibration
1209 11:55:18.672211 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1210 11:55:18.679280 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1211 11:55:18.722891 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 11:55:18.723476 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1213 11:55:18.724239 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1214 11:55:18.724736 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:55:18.725282 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:55:18.725729 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:55:18.726084 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 11:55:18.726456 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:55:18.726783 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:55:18.727100 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:55:18.728197 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:55:18.731734 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:55:18.735196 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:55:18.738364 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:55:18.745364 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:55:18.748711 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:55:18.751989 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:55:18.758477 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1229 11:55:18.762120 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:55:18.765241 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:55:18.772211 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:55:18.775272 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:55:18.778861 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:55:18.785575 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:55:18.788590 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:55:18.792125 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1237 11:55:18.798856 0 9 8 | B1->B0 | 2626 3333 | 0 0 | (0 0) (0 0)
1238 11:55:18.801824 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1239 11:55:18.805060 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 11:55:18.811514 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 11:55:18.815136 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 11:55:18.818144 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 11:55:18.824492 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1244 11:55:18.828304 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1245 11:55:18.832320 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (1 1) (0 0)
1246 11:55:18.838192 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1247 11:55:18.841174 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:55:18.844724 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:55:18.851243 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:55:18.854298 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:55:18.857979 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:55:18.861245 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1253 11:55:18.868484 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1254 11:55:18.872303 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 11:55:18.877095 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 11:55:18.879891 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 11:55:18.886891 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 11:55:18.889488 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:55:18.893433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 11:55:18.896752 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:55:18.903921 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 11:55:18.906826 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 11:55:18.909997 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 11:55:18.917108 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 11:55:18.920367 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 11:55:18.924040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 11:55:18.930474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:55:18.933937 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:55:18.936864 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:55:18.943773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:55:18.946785 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:55:18.949988 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:55:18.956633 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:55:18.959940 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:55:18.962920 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:55:18.969630 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1277 11:55:18.973451 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1278 11:55:18.976707 Total UI for P1: 0, mck2ui 16
1279 11:55:18.979613 best dqsien dly found for B0: ( 0, 14, 4)
1280 11:55:18.982768 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 11:55:18.986806 Total UI for P1: 0, mck2ui 16
1282 11:55:18.989618 best dqsien dly found for B1: ( 0, 14, 8)
1283 11:55:18.992953 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1284 11:55:18.997032 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1285 11:55:18.997564
1286 11:55:18.999646 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1287 11:55:19.003205 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1288 11:55:19.006850 [Gating] SW calibration Done
1289 11:55:19.007419 ==
1290 11:55:19.010240 Dram Type= 6, Freq= 0, CH_0, rank 1
1291 11:55:19.016140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1292 11:55:19.016657 ==
1293 11:55:19.017124 RX Vref Scan: 0
1294 11:55:19.017590
1295 11:55:19.019503 RX Vref 0 -> 0, step: 1
1296 11:55:19.020036
1297 11:55:19.023229 RX Delay -130 -> 252, step: 16
1298 11:55:19.026486 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1299 11:55:19.029560 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1300 11:55:19.033301 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1301 11:55:19.040103 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1302 11:55:19.042805 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1303 11:55:19.046127 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1304 11:55:19.049277 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1305 11:55:19.052735 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1306 11:55:19.059269 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1307 11:55:19.062638 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1308 11:55:19.066592 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1309 11:55:19.069463 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1310 11:55:19.072937 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1311 11:55:19.079382 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1312 11:55:19.082732 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1313 11:55:19.085985 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1314 11:55:19.086450 ==
1315 11:55:19.089227 Dram Type= 6, Freq= 0, CH_0, rank 1
1316 11:55:19.093445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1317 11:55:19.094010 ==
1318 11:55:19.096816 DQS Delay:
1319 11:55:19.097370 DQS0 = 0, DQS1 = 0
1320 11:55:19.099353 DQM Delay:
1321 11:55:19.099833 DQM0 = 86, DQM1 = 77
1322 11:55:19.100202 DQ Delay:
1323 11:55:19.103005 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1324 11:55:19.106212 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1325 11:55:19.109704 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1326 11:55:19.113430 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1327 11:55:19.114004
1328 11:55:19.114434
1329 11:55:19.114787 ==
1330 11:55:19.115732 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 11:55:19.122948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 11:55:19.123522 ==
1333 11:55:19.123969
1334 11:55:19.124509
1335 11:55:19.124876 TX Vref Scan disable
1336 11:55:19.126227 == TX Byte 0 ==
1337 11:55:19.130910 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1338 11:55:19.136708 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1339 11:55:19.137325 == TX Byte 1 ==
1340 11:55:19.139834 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1341 11:55:19.146950 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1342 11:55:19.147519 ==
1343 11:55:19.149716 Dram Type= 6, Freq= 0, CH_0, rank 1
1344 11:55:19.152690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1345 11:55:19.153168 ==
1346 11:55:19.165590 TX Vref=22, minBit 1, minWin=27, winSum=441
1347 11:55:19.169096 TX Vref=24, minBit 2, minWin=26, winSum=443
1348 11:55:19.172543 TX Vref=26, minBit 1, minWin=27, winSum=446
1349 11:55:19.175312 TX Vref=28, minBit 2, minWin=27, winSum=453
1350 11:55:19.179073 TX Vref=30, minBit 2, minWin=27, winSum=451
1351 11:55:19.185187 TX Vref=32, minBit 7, minWin=27, winSum=451
1352 11:55:19.188403 [TxChooseVref] Worse bit 2, Min win 27, Win sum 453, Final Vref 28
1353 11:55:19.188980
1354 11:55:19.191944 Final TX Range 1 Vref 28
1355 11:55:19.192508
1356 11:55:19.192872 ==
1357 11:55:19.195359 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:55:19.198545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:55:19.198971 ==
1360 11:55:19.201446
1361 11:55:19.201858
1362 11:55:19.202199 TX Vref Scan disable
1363 11:55:19.205386 == TX Byte 0 ==
1364 11:55:19.208347 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1365 11:55:19.214998 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1366 11:55:19.215417 == TX Byte 1 ==
1367 11:55:19.218164 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1368 11:55:19.224721 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1369 11:55:19.225132
1370 11:55:19.225366 [DATLAT]
1371 11:55:19.225586 Freq=800, CH0 RK1
1372 11:55:19.225799
1373 11:55:19.228313 DATLAT Default: 0xa
1374 11:55:19.228719 0, 0xFFFF, sum = 0
1375 11:55:19.231379 1, 0xFFFF, sum = 0
1376 11:55:19.231769 2, 0xFFFF, sum = 0
1377 11:55:19.235165 3, 0xFFFF, sum = 0
1378 11:55:19.238286 4, 0xFFFF, sum = 0
1379 11:55:19.238607 5, 0xFFFF, sum = 0
1380 11:55:19.241693 6, 0xFFFF, sum = 0
1381 11:55:19.242081 7, 0xFFFF, sum = 0
1382 11:55:19.244970 8, 0xFFFF, sum = 0
1383 11:55:19.245361 9, 0x0, sum = 1
1384 11:55:19.245603 10, 0x0, sum = 2
1385 11:55:19.248505 11, 0x0, sum = 3
1386 11:55:19.248978 12, 0x0, sum = 4
1387 11:55:19.252119 best_step = 10
1388 11:55:19.252600
1389 11:55:19.252905 ==
1390 11:55:19.254802 Dram Type= 6, Freq= 0, CH_0, rank 1
1391 11:55:19.258443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1392 11:55:19.258865 ==
1393 11:55:19.261865 RX Vref Scan: 0
1394 11:55:19.262318
1395 11:55:19.262656 RX Vref 0 -> 0, step: 1
1396 11:55:19.262967
1397 11:55:19.265097 RX Delay -95 -> 252, step: 8
1398 11:55:19.272153 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1399 11:55:19.275182 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1400 11:55:19.278498 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1401 11:55:19.282336 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1402 11:55:19.284990 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1403 11:55:19.292221 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1404 11:55:19.295054 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1405 11:55:19.298625 iDelay=209, Bit 7, Center 92 (-15 ~ 200) 216
1406 11:55:19.301963 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1407 11:55:19.305617 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1408 11:55:19.311457 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1409 11:55:19.314922 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1410 11:55:19.318202 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1411 11:55:19.322870 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1412 11:55:19.324967 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1413 11:55:19.331876 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1414 11:55:19.332401 ==
1415 11:55:19.335156 Dram Type= 6, Freq= 0, CH_0, rank 1
1416 11:55:19.338808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1417 11:55:19.339232 ==
1418 11:55:19.339564 DQS Delay:
1419 11:55:19.342083 DQS0 = 0, DQS1 = 0
1420 11:55:19.342650 DQM Delay:
1421 11:55:19.345150 DQM0 = 86, DQM1 = 76
1422 11:55:19.345671 DQ Delay:
1423 11:55:19.348544 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1424 11:55:19.351742 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =92
1425 11:55:19.355938 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1426 11:55:19.358244 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1427 11:55:19.358762
1428 11:55:19.359124
1429 11:55:19.368696 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f2c, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
1430 11:55:19.369266 CH0 RK1: MR19=606, MR18=2F2C
1431 11:55:19.374934 CH0_RK1: MR19=0x606, MR18=0x2F2C, DQSOSC=397, MR23=63, INC=93, DEC=62
1432 11:55:19.378284 [RxdqsGatingPostProcess] freq 800
1433 11:55:19.384890 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1434 11:55:19.388360 Pre-setting of DQS Precalculation
1435 11:55:19.391920 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1436 11:55:19.392491 ==
1437 11:55:19.394771 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 11:55:19.398152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 11:55:19.401688 ==
1440 11:55:19.404712 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1441 11:55:19.410993 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1442 11:55:19.420427 [CA 0] Center 36 (6~67) winsize 62
1443 11:55:19.423663 [CA 1] Center 37 (6~68) winsize 63
1444 11:55:19.426885 [CA 2] Center 35 (5~65) winsize 61
1445 11:55:19.430290 [CA 3] Center 34 (4~65) winsize 62
1446 11:55:19.433410 [CA 4] Center 34 (4~65) winsize 62
1447 11:55:19.436815 [CA 5] Center 34 (3~65) winsize 63
1448 11:55:19.437284
1449 11:55:19.440639 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1450 11:55:19.441343
1451 11:55:19.443514 [CATrainingPosCal] consider 1 rank data
1452 11:55:19.446523 u2DelayCellTimex100 = 270/100 ps
1453 11:55:19.450469 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 11:55:19.456890 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1455 11:55:19.460465 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1456 11:55:19.463286 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1457 11:55:19.467268 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 11:55:19.469507 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1459 11:55:19.469932
1460 11:55:19.473325 CA PerBit enable=1, Macro0, CA PI delay=34
1461 11:55:19.473836
1462 11:55:19.476356 [CBTSetCACLKResult] CA Dly = 34
1463 11:55:19.476778 CS Dly: 4 (0~35)
1464 11:55:19.479920 ==
1465 11:55:19.483184 Dram Type= 6, Freq= 0, CH_1, rank 1
1466 11:55:19.486646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1467 11:55:19.487075 ==
1468 11:55:19.493295 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1469 11:55:19.496260 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1470 11:55:19.506566 [CA 0] Center 36 (6~67) winsize 62
1471 11:55:19.510016 [CA 1] Center 36 (6~67) winsize 62
1472 11:55:19.513053 [CA 2] Center 34 (4~65) winsize 62
1473 11:55:19.516095 [CA 3] Center 34 (3~65) winsize 63
1474 11:55:19.519698 [CA 4] Center 34 (3~65) winsize 63
1475 11:55:19.522984 [CA 5] Center 33 (3~64) winsize 62
1476 11:55:19.523541
1477 11:55:19.526552 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1478 11:55:19.527111
1479 11:55:19.530402 [CATrainingPosCal] consider 2 rank data
1480 11:55:19.533640 u2DelayCellTimex100 = 270/100 ps
1481 11:55:19.537532 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1482 11:55:19.541031 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1483 11:55:19.544522 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1484 11:55:19.548315 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1485 11:55:19.551425 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1486 11:55:19.555632 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1487 11:55:19.556172
1488 11:55:19.559488 CA PerBit enable=1, Macro0, CA PI delay=33
1489 11:55:19.560000
1490 11:55:19.562632 [CBTSetCACLKResult] CA Dly = 33
1491 11:55:19.563143 CS Dly: 5 (0~37)
1492 11:55:19.566360
1493 11:55:19.566780 ----->DramcWriteLeveling(PI) begin...
1494 11:55:19.569125 ==
1495 11:55:19.572597 Dram Type= 6, Freq= 0, CH_1, rank 0
1496 11:55:19.576276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1497 11:55:19.576795 ==
1498 11:55:19.579407 Write leveling (Byte 0): 28 => 28
1499 11:55:19.582853 Write leveling (Byte 1): 29 => 29
1500 11:55:19.586071 DramcWriteLeveling(PI) end<-----
1501 11:55:19.586543
1502 11:55:19.586876 ==
1503 11:55:19.589851 Dram Type= 6, Freq= 0, CH_1, rank 0
1504 11:55:19.593010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 11:55:19.593526 ==
1506 11:55:19.596437 [Gating] SW mode calibration
1507 11:55:19.603144 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1508 11:55:19.609652 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1509 11:55:19.612393 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1510 11:55:19.616288 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1511 11:55:19.622619 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:55:19.626378 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:55:19.629850 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:55:19.636143 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:55:19.639301 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 11:55:19.642731 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 11:55:19.646243 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:55:19.652103 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:55:19.655980 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:55:19.658957 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:55:19.665773 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:55:19.668723 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:55:19.672384 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:55:19.678560 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:55:19.682302 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:55:19.685191 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1527 11:55:19.692184 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1528 11:55:19.695329 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:55:19.698873 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:55:19.705506 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:55:19.708703 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:55:19.711974 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:55:19.718229 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:55:19.721658 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:55:19.725247 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1536 11:55:19.731916 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 11:55:19.734938 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 11:55:19.738893 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 11:55:19.745601 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 11:55:19.748439 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 11:55:19.751823 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1542 11:55:19.758879 0 10 4 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
1543 11:55:19.761394 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (1 1) (0 0)
1544 11:55:19.765167 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:55:19.771440 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:55:19.774833 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:55:19.778154 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:55:19.784523 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:55:19.788671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:55:19.791381 0 11 4 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
1551 11:55:19.798149 0 11 8 | B1->B0 | 3f3f 4545 | 0 0 | (0 0) (0 0)
1552 11:55:19.801377 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 11:55:19.805063 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 11:55:19.811198 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 11:55:19.815063 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 11:55:19.817589 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 11:55:19.824676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:55:19.827781 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1559 11:55:19.831303 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1560 11:55:19.837335 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 11:55:19.841005 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 11:55:19.844821 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 11:55:19.851230 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 11:55:19.854335 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 11:55:19.857567 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:55:19.864227 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:55:19.868035 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:55:19.871044 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:55:19.874304 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:55:19.880963 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:55:19.884300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:55:19.887495 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:55:19.894144 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1574 11:55:19.897572 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1575 11:55:19.901030 Total UI for P1: 0, mck2ui 16
1576 11:55:19.904165 best dqsien dly found for B0: ( 0, 14, 0)
1577 11:55:19.907521 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 11:55:19.910452 Total UI for P1: 0, mck2ui 16
1579 11:55:19.914021 best dqsien dly found for B1: ( 0, 14, 4)
1580 11:55:19.918073 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1581 11:55:19.920597 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1582 11:55:19.923968
1583 11:55:19.927421 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1584 11:55:19.930649 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1585 11:55:19.933833 [Gating] SW calibration Done
1586 11:55:19.934297 ==
1587 11:55:19.937249 Dram Type= 6, Freq= 0, CH_1, rank 0
1588 11:55:19.940049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1589 11:55:19.940496 ==
1590 11:55:19.940829 RX Vref Scan: 0
1591 11:55:19.941136
1592 11:55:19.943648 RX Vref 0 -> 0, step: 1
1593 11:55:19.944115
1594 11:55:19.946689 RX Delay -130 -> 252, step: 16
1595 11:55:19.950006 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1596 11:55:19.953297 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1597 11:55:19.960258 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1598 11:55:19.963567 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1599 11:55:19.966946 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1600 11:55:19.970315 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1601 11:55:19.973746 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1602 11:55:19.980506 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1603 11:55:19.983477 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1604 11:55:19.986922 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1605 11:55:19.990176 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1606 11:55:19.996429 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1607 11:55:19.999882 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1608 11:55:20.003255 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1609 11:55:20.006703 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1610 11:55:20.010244 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1611 11:55:20.013174 ==
1612 11:55:20.013710 Dram Type= 6, Freq= 0, CH_1, rank 0
1613 11:55:20.020145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1614 11:55:20.020682 ==
1615 11:55:20.021129 DQS Delay:
1616 11:55:20.023666 DQS0 = 0, DQS1 = 0
1617 11:55:20.024198 DQM Delay:
1618 11:55:20.026695 DQM0 = 88, DQM1 = 79
1619 11:55:20.027177 DQ Delay:
1620 11:55:20.029609 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1621 11:55:20.033060 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1622 11:55:20.036022 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1623 11:55:20.039975 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1624 11:55:20.040451
1625 11:55:20.040791
1626 11:55:20.041102 ==
1627 11:55:20.043088 Dram Type= 6, Freq= 0, CH_1, rank 0
1628 11:55:20.046312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1629 11:55:20.046745 ==
1630 11:55:20.047077
1631 11:55:20.047382
1632 11:55:20.049599 TX Vref Scan disable
1633 11:55:20.053096 == TX Byte 0 ==
1634 11:55:20.056128 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1635 11:55:20.060325 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1636 11:55:20.062780 == TX Byte 1 ==
1637 11:55:20.066074 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1638 11:55:20.069909 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1639 11:55:20.070396 ==
1640 11:55:20.073173 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 11:55:20.076355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 11:55:20.079692 ==
1643 11:55:20.091161 TX Vref=22, minBit 2, minWin=27, winSum=445
1644 11:55:20.094068 TX Vref=24, minBit 3, minWin=27, winSum=451
1645 11:55:20.097616 TX Vref=26, minBit 1, minWin=27, winSum=451
1646 11:55:20.101131 TX Vref=28, minBit 1, minWin=27, winSum=456
1647 11:55:20.103733 TX Vref=30, minBit 1, minWin=27, winSum=454
1648 11:55:20.110811 TX Vref=32, minBit 1, minWin=27, winSum=452
1649 11:55:20.114612 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 28
1650 11:55:20.115071
1651 11:55:20.117806 Final TX Range 1 Vref 28
1652 11:55:20.118318
1653 11:55:20.118695 ==
1654 11:55:20.121025 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 11:55:20.124418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 11:55:20.124934 ==
1657 11:55:20.125269
1658 11:55:20.127562
1659 11:55:20.128100 TX Vref Scan disable
1660 11:55:20.130609 == TX Byte 0 ==
1661 11:55:20.134217 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1662 11:55:20.137845 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1663 11:55:20.140933 == TX Byte 1 ==
1664 11:55:20.144365 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1665 11:55:20.151389 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1666 11:55:20.151914
1667 11:55:20.152312 [DATLAT]
1668 11:55:20.152634 Freq=800, CH1 RK0
1669 11:55:20.152937
1670 11:55:20.154179 DATLAT Default: 0xa
1671 11:55:20.154635 0, 0xFFFF, sum = 0
1672 11:55:20.157647 1, 0xFFFF, sum = 0
1673 11:55:20.158182 2, 0xFFFF, sum = 0
1674 11:55:20.160655 3, 0xFFFF, sum = 0
1675 11:55:20.163770 4, 0xFFFF, sum = 0
1676 11:55:20.164297 5, 0xFFFF, sum = 0
1677 11:55:20.167293 6, 0xFFFF, sum = 0
1678 11:55:20.167720 7, 0xFFFF, sum = 0
1679 11:55:20.170795 8, 0xFFFF, sum = 0
1680 11:55:20.171342 9, 0x0, sum = 1
1681 11:55:20.174450 10, 0x0, sum = 2
1682 11:55:20.174972 11, 0x0, sum = 3
1683 11:55:20.175316 12, 0x0, sum = 4
1684 11:55:20.177509 best_step = 10
1685 11:55:20.178034
1686 11:55:20.178417 ==
1687 11:55:20.180835 Dram Type= 6, Freq= 0, CH_1, rank 0
1688 11:55:20.183899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1689 11:55:20.184426 ==
1690 11:55:20.186977 RX Vref Scan: 1
1691 11:55:20.187450
1692 11:55:20.190355 Set Vref Range= 32 -> 127
1693 11:55:20.190773
1694 11:55:20.191100 RX Vref 32 -> 127, step: 1
1695 11:55:20.191408
1696 11:55:20.193700 RX Delay -95 -> 252, step: 8
1697 11:55:20.194225
1698 11:55:20.196989 Set Vref, RX VrefLevel [Byte0]: 32
1699 11:55:20.200158 [Byte1]: 32
1700 11:55:20.203990
1701 11:55:20.204511 Set Vref, RX VrefLevel [Byte0]: 33
1702 11:55:20.207235 [Byte1]: 33
1703 11:55:20.211692
1704 11:55:20.212218 Set Vref, RX VrefLevel [Byte0]: 34
1705 11:55:20.214453 [Byte1]: 34
1706 11:55:20.219228
1707 11:55:20.219694 Set Vref, RX VrefLevel [Byte0]: 35
1708 11:55:20.221732 [Byte1]: 35
1709 11:55:20.226690
1710 11:55:20.227206 Set Vref, RX VrefLevel [Byte0]: 36
1711 11:55:20.229946 [Byte1]: 36
1712 11:55:20.234295
1713 11:55:20.234716 Set Vref, RX VrefLevel [Byte0]: 37
1714 11:55:20.236965 [Byte1]: 37
1715 11:55:20.241218
1716 11:55:20.241634 Set Vref, RX VrefLevel [Byte0]: 38
1717 11:55:20.244949 [Byte1]: 38
1718 11:55:20.249173
1719 11:55:20.249692 Set Vref, RX VrefLevel [Byte0]: 39
1720 11:55:20.252652 [Byte1]: 39
1721 11:55:20.257148
1722 11:55:20.257670 Set Vref, RX VrefLevel [Byte0]: 40
1723 11:55:20.260324 [Byte1]: 40
1724 11:55:20.264358
1725 11:55:20.264881 Set Vref, RX VrefLevel [Byte0]: 41
1726 11:55:20.267412 [Byte1]: 41
1727 11:55:20.272150
1728 11:55:20.272673 Set Vref, RX VrefLevel [Byte0]: 42
1729 11:55:20.275389 [Byte1]: 42
1730 11:55:20.279548
1731 11:55:20.279994 Set Vref, RX VrefLevel [Byte0]: 43
1732 11:55:20.283720 [Byte1]: 43
1733 11:55:20.287069
1734 11:55:20.287581 Set Vref, RX VrefLevel [Byte0]: 44
1735 11:55:20.290416 [Byte1]: 44
1736 11:55:20.294924
1737 11:55:20.295441 Set Vref, RX VrefLevel [Byte0]: 45
1738 11:55:20.298175 [Byte1]: 45
1739 11:55:20.302296
1740 11:55:20.302821 Set Vref, RX VrefLevel [Byte0]: 46
1741 11:55:20.306118 [Byte1]: 46
1742 11:55:20.309880
1743 11:55:20.310330 Set Vref, RX VrefLevel [Byte0]: 47
1744 11:55:20.313275 [Byte1]: 47
1745 11:55:20.317856
1746 11:55:20.318490 Set Vref, RX VrefLevel [Byte0]: 48
1747 11:55:20.321010 [Byte1]: 48
1748 11:55:20.325193
1749 11:55:20.325756 Set Vref, RX VrefLevel [Byte0]: 49
1750 11:55:20.328947 [Byte1]: 49
1751 11:55:20.333049
1752 11:55:20.333611 Set Vref, RX VrefLevel [Byte0]: 50
1753 11:55:20.335913 [Byte1]: 50
1754 11:55:20.340470
1755 11:55:20.340940 Set Vref, RX VrefLevel [Byte0]: 51
1756 11:55:20.343577 [Byte1]: 51
1757 11:55:20.348596
1758 11:55:20.349116 Set Vref, RX VrefLevel [Byte0]: 52
1759 11:55:20.350913 [Byte1]: 52
1760 11:55:20.355602
1761 11:55:20.356123 Set Vref, RX VrefLevel [Byte0]: 53
1762 11:55:20.359302 [Byte1]: 53
1763 11:55:20.363275
1764 11:55:20.363795 Set Vref, RX VrefLevel [Byte0]: 54
1765 11:55:20.366349 [Byte1]: 54
1766 11:55:20.371322
1767 11:55:20.371838 Set Vref, RX VrefLevel [Byte0]: 55
1768 11:55:20.374288 [Byte1]: 55
1769 11:55:20.378154
1770 11:55:20.378616 Set Vref, RX VrefLevel [Byte0]: 56
1771 11:55:20.381746 [Byte1]: 56
1772 11:55:20.385838
1773 11:55:20.386471 Set Vref, RX VrefLevel [Byte0]: 57
1774 11:55:20.389023 [Byte1]: 57
1775 11:55:20.393343
1776 11:55:20.393865 Set Vref, RX VrefLevel [Byte0]: 58
1777 11:55:20.396833 [Byte1]: 58
1778 11:55:20.401008
1779 11:55:20.401580 Set Vref, RX VrefLevel [Byte0]: 59
1780 11:55:20.404289 [Byte1]: 59
1781 11:55:20.408787
1782 11:55:20.409345 Set Vref, RX VrefLevel [Byte0]: 60
1783 11:55:20.412273 [Byte1]: 60
1784 11:55:20.416671
1785 11:55:20.417386 Set Vref, RX VrefLevel [Byte0]: 61
1786 11:55:20.419939 [Byte1]: 61
1787 11:55:20.424012
1788 11:55:20.424564 Set Vref, RX VrefLevel [Byte0]: 62
1789 11:55:20.426991 [Byte1]: 62
1790 11:55:20.431366
1791 11:55:20.431882 Set Vref, RX VrefLevel [Byte0]: 63
1792 11:55:20.434608 [Byte1]: 63
1793 11:55:20.439343
1794 11:55:20.439802 Set Vref, RX VrefLevel [Byte0]: 64
1795 11:55:20.442282 [Byte1]: 64
1796 11:55:20.446971
1797 11:55:20.447505 Set Vref, RX VrefLevel [Byte0]: 65
1798 11:55:20.450129 [Byte1]: 65
1799 11:55:20.454391
1800 11:55:20.454910 Set Vref, RX VrefLevel [Byte0]: 66
1801 11:55:20.457699 [Byte1]: 66
1802 11:55:20.461995
1803 11:55:20.462570 Set Vref, RX VrefLevel [Byte0]: 67
1804 11:55:20.465561 [Byte1]: 67
1805 11:55:20.470108
1806 11:55:20.470667 Set Vref, RX VrefLevel [Byte0]: 68
1807 11:55:20.472946 [Byte1]: 68
1808 11:55:20.476924
1809 11:55:20.477440 Set Vref, RX VrefLevel [Byte0]: 69
1810 11:55:20.479998 [Byte1]: 69
1811 11:55:20.485115
1812 11:55:20.485626 Set Vref, RX VrefLevel [Byte0]: 70
1813 11:55:20.488028 [Byte1]: 70
1814 11:55:20.492275
1815 11:55:20.492874 Set Vref, RX VrefLevel [Byte0]: 71
1816 11:55:20.495662 [Byte1]: 71
1817 11:55:20.499882
1818 11:55:20.500398 Set Vref, RX VrefLevel [Byte0]: 72
1819 11:55:20.503008 [Byte1]: 72
1820 11:55:20.507473
1821 11:55:20.507889 Set Vref, RX VrefLevel [Byte0]: 73
1822 11:55:20.510420 [Byte1]: 73
1823 11:55:20.515034
1824 11:55:20.515450 Set Vref, RX VrefLevel [Byte0]: 74
1825 11:55:20.518533 [Byte1]: 74
1826 11:55:20.522965
1827 11:55:20.523529 Set Vref, RX VrefLevel [Byte0]: 75
1828 11:55:20.526197 [Byte1]: 75
1829 11:55:20.530915
1830 11:55:20.531463 Final RX Vref Byte 0 = 55 to rank0
1831 11:55:20.533604 Final RX Vref Byte 1 = 57 to rank0
1832 11:55:20.536631 Final RX Vref Byte 0 = 55 to rank1
1833 11:55:20.539916 Final RX Vref Byte 1 = 57 to rank1==
1834 11:55:20.543453 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 11:55:20.550153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 11:55:20.550761 ==
1837 11:55:20.551139 DQS Delay:
1838 11:55:20.553322 DQS0 = 0, DQS1 = 0
1839 11:55:20.553786 DQM Delay:
1840 11:55:20.554168 DQM0 = 85, DQM1 = 80
1841 11:55:20.556661 DQ Delay:
1842 11:55:20.560125 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1843 11:55:20.563858 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1844 11:55:20.566583 DQ8 =68, DQ9 =72, DQ10 =76, DQ11 =72
1845 11:55:20.569839 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1846 11:55:20.570436
1847 11:55:20.570808
1848 11:55:20.576503 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a2d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
1849 11:55:20.580046 CH1 RK0: MR19=606, MR18=1A2D
1850 11:55:20.586962 CH1_RK0: MR19=0x606, MR18=0x1A2D, DQSOSC=398, MR23=63, INC=93, DEC=62
1851 11:55:20.587521
1852 11:55:20.590246 ----->DramcWriteLeveling(PI) begin...
1853 11:55:20.590917 ==
1854 11:55:20.592763 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 11:55:20.596276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 11:55:20.597001 ==
1857 11:55:20.600081 Write leveling (Byte 0): 24 => 24
1858 11:55:20.602610 Write leveling (Byte 1): 29 => 29
1859 11:55:20.605998 DramcWriteLeveling(PI) end<-----
1860 11:55:20.606519
1861 11:55:20.606890 ==
1862 11:55:20.609228 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 11:55:20.612788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 11:55:20.613339 ==
1865 11:55:20.616151 [Gating] SW mode calibration
1866 11:55:20.623483 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 11:55:20.629519 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 11:55:20.632334 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1869 11:55:20.638969 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1870 11:55:20.642607 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:55:20.646077 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:55:20.652509 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:55:20.655759 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:55:20.659197 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:55:20.665787 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:55:20.668750 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:55:20.672721 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:55:20.679358 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:55:20.682886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:55:20.685825 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:55:20.691996 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:55:20.695746 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:55:20.699357 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:55:20.702357 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1885 11:55:20.709092 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1886 11:55:20.712198 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:55:20.715222 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:55:20.722650 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:55:20.726076 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:55:20.729104 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:55:20.735696 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:55:20.738483 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:55:20.741676 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
1894 11:55:20.749124 0 9 8 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
1895 11:55:20.752029 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:55:20.755175 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:55:20.761848 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:55:20.765038 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:55:20.768505 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:55:20.774972 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 11:55:20.778285 0 10 4 | B1->B0 | 3333 2e2e | 0 0 | (0 0) (0 0)
1902 11:55:20.781909 0 10 8 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
1903 11:55:20.788651 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:55:20.791419 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:55:20.794516 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:55:20.801321 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:55:20.804612 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:55:20.807503 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:55:20.814629 0 11 4 | B1->B0 | 2626 3333 | 0 0 | (0 0) (1 1)
1910 11:55:20.818214 0 11 8 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
1911 11:55:20.821317 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:55:20.827808 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:55:20.831292 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:55:20.834406 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:55:20.841221 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:55:20.844938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1917 11:55:20.847907 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1918 11:55:20.854365 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:55:20.857312 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:55:20.861396 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:55:20.867352 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:55:20.870865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:55:20.873944 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:55:20.880286 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:55:20.883673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:55:20.886769 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:55:20.893674 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:55:20.897140 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:55:20.900151 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:55:20.906982 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:55:20.910466 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:55:20.913575 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:55:20.920543 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1934 11:55:20.923449 Total UI for P1: 0, mck2ui 16
1935 11:55:20.926756 best dqsien dly found for B0: ( 0, 14, 2)
1936 11:55:20.930559 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 11:55:20.933900 Total UI for P1: 0, mck2ui 16
1938 11:55:20.936628 best dqsien dly found for B1: ( 0, 14, 4)
1939 11:55:20.940501 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1940 11:55:20.943163 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1941 11:55:20.943589
1942 11:55:20.946883 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1943 11:55:20.950205 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1944 11:55:20.953432 [Gating] SW calibration Done
1945 11:55:20.953856 ==
1946 11:55:20.956483 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 11:55:20.959680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 11:55:20.962961 ==
1949 11:55:20.963382 RX Vref Scan: 0
1950 11:55:20.963713
1951 11:55:20.966655 RX Vref 0 -> 0, step: 1
1952 11:55:20.967171
1953 11:55:20.970284 RX Delay -130 -> 252, step: 16
1954 11:55:20.973333 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1955 11:55:20.976978 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1956 11:55:20.980157 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1957 11:55:20.983110 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1958 11:55:20.989843 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1959 11:55:20.992615 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1960 11:55:20.996622 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1961 11:55:20.999308 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1962 11:55:21.002729 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1963 11:55:21.009803 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1964 11:55:21.012623 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1965 11:55:21.015859 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1966 11:55:21.019428 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1967 11:55:21.022913 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1968 11:55:21.029188 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1969 11:55:21.032519 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1970 11:55:21.032946 ==
1971 11:55:21.035757 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 11:55:21.039378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 11:55:21.039802 ==
1974 11:55:21.042748 DQS Delay:
1975 11:55:21.043183 DQS0 = 0, DQS1 = 0
1976 11:55:21.043622 DQM Delay:
1977 11:55:21.045874 DQM0 = 82, DQM1 = 80
1978 11:55:21.046330 DQ Delay:
1979 11:55:21.049418 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1980 11:55:21.052389 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1981 11:55:21.055518 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1982 11:55:21.058808 DQ12 =93, DQ13 =85, DQ14 =85, DQ15 =85
1983 11:55:21.059038
1984 11:55:21.059272
1985 11:55:21.059493 ==
1986 11:55:21.062762 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 11:55:21.069044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 11:55:21.069204 ==
1989 11:55:21.069362
1990 11:55:21.069511
1991 11:55:21.069656 TX Vref Scan disable
1992 11:55:21.072953 == TX Byte 0 ==
1993 11:55:21.076446 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1994 11:55:21.082651 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1995 11:55:21.082987 == TX Byte 1 ==
1996 11:55:21.085981 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1997 11:55:21.092459 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1998 11:55:21.092708 ==
1999 11:55:21.096601 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:55:21.099320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:55:21.099743 ==
2002 11:55:21.112577 TX Vref=22, minBit 4, minWin=26, winSum=442
2003 11:55:21.116019 TX Vref=24, minBit 1, minWin=27, winSum=450
2004 11:55:21.118816 TX Vref=26, minBit 1, minWin=27, winSum=452
2005 11:55:21.122311 TX Vref=28, minBit 1, minWin=27, winSum=453
2006 11:55:21.125782 TX Vref=30, minBit 0, minWin=28, winSum=456
2007 11:55:21.131947 TX Vref=32, minBit 1, minWin=27, winSum=449
2008 11:55:21.135672 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
2009 11:55:21.136103
2010 11:55:21.138984 Final TX Range 1 Vref 30
2011 11:55:21.139478
2012 11:55:21.139925 ==
2013 11:55:21.142383 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 11:55:21.145757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 11:55:21.146197 ==
2016 11:55:21.149078
2017 11:55:21.149516
2018 11:55:21.149958 TX Vref Scan disable
2019 11:55:21.152339 == TX Byte 0 ==
2020 11:55:21.156088 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2021 11:55:21.162419 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2022 11:55:21.162861 == TX Byte 1 ==
2023 11:55:21.166306 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2024 11:55:21.172306 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2025 11:55:21.172748
2026 11:55:21.173188 [DATLAT]
2027 11:55:21.173607 Freq=800, CH1 RK1
2028 11:55:21.174019
2029 11:55:21.175697 DATLAT Default: 0xa
2030 11:55:21.176134 0, 0xFFFF, sum = 0
2031 11:55:21.178661 1, 0xFFFF, sum = 0
2032 11:55:21.182221 2, 0xFFFF, sum = 0
2033 11:55:21.182681 3, 0xFFFF, sum = 0
2034 11:55:21.185572 4, 0xFFFF, sum = 0
2035 11:55:21.186015 5, 0xFFFF, sum = 0
2036 11:55:21.188442 6, 0xFFFF, sum = 0
2037 11:55:21.188886 7, 0xFFFF, sum = 0
2038 11:55:21.192568 8, 0xFFFF, sum = 0
2039 11:55:21.193026 9, 0x0, sum = 1
2040 11:55:21.195126 10, 0x0, sum = 2
2041 11:55:21.195557 11, 0x0, sum = 3
2042 11:55:21.196038 12, 0x0, sum = 4
2043 11:55:21.198637 best_step = 10
2044 11:55:21.199307
2045 11:55:21.199931 ==
2046 11:55:21.201906 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 11:55:21.205091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 11:55:21.205796 ==
2049 11:55:21.208730 RX Vref Scan: 0
2050 11:55:21.209150
2051 11:55:21.212716 RX Vref 0 -> 0, step: 1
2052 11:55:21.213230
2053 11:55:21.213576 RX Delay -95 -> 252, step: 8
2054 11:55:21.219340 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2055 11:55:21.222225 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2056 11:55:21.225412 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2057 11:55:21.229108 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2058 11:55:21.232726 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2059 11:55:21.239382 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2060 11:55:21.242316 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2061 11:55:21.245502 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2062 11:55:21.248958 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2063 11:55:21.252605 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2064 11:55:21.258864 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2065 11:55:21.262864 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2066 11:55:21.265244 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2067 11:55:21.269054 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2068 11:55:21.275096 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2069 11:55:21.278976 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2070 11:55:21.279496 ==
2071 11:55:21.281699 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 11:55:21.285244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 11:55:21.285807 ==
2074 11:55:21.289018 DQS Delay:
2075 11:55:21.289544 DQS0 = 0, DQS1 = 0
2076 11:55:21.289880 DQM Delay:
2077 11:55:21.291947 DQM0 = 87, DQM1 = 81
2078 11:55:21.292371 DQ Delay:
2079 11:55:21.295318 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2080 11:55:21.299234 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2081 11:55:21.301858 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =72
2082 11:55:21.305347 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2083 11:55:21.305874
2084 11:55:21.306209
2085 11:55:21.314959 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f3a, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2086 11:55:21.315387 CH1 RK1: MR19=606, MR18=1F3A
2087 11:55:21.321835 CH1_RK1: MR19=0x606, MR18=0x1F3A, DQSOSC=395, MR23=63, INC=94, DEC=63
2088 11:55:21.325151 [RxdqsGatingPostProcess] freq 800
2089 11:55:21.332004 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 11:55:21.335636 Pre-setting of DQS Precalculation
2091 11:55:21.338740 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 11:55:21.345187 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 11:55:21.355084 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 11:55:21.355606
2095 11:55:21.355943
2096 11:55:21.358624 [Calibration Summary] 1600 Mbps
2097 11:55:21.359153 CH 0, Rank 0
2098 11:55:21.363190 SW Impedance : PASS
2099 11:55:21.363716 DUTY Scan : NO K
2100 11:55:21.365122 ZQ Calibration : PASS
2101 11:55:21.365543 Jitter Meter : NO K
2102 11:55:21.368600 CBT Training : PASS
2103 11:55:21.371974 Write leveling : PASS
2104 11:55:21.372500 RX DQS gating : PASS
2105 11:55:21.375186 RX DQ/DQS(RDDQC) : PASS
2106 11:55:21.378423 TX DQ/DQS : PASS
2107 11:55:21.378953 RX DATLAT : PASS
2108 11:55:21.381811 RX DQ/DQS(Engine): PASS
2109 11:55:21.385102 TX OE : NO K
2110 11:55:21.385525 All Pass.
2111 11:55:21.385859
2112 11:55:21.386169 CH 0, Rank 1
2113 11:55:21.388883 SW Impedance : PASS
2114 11:55:21.391610 DUTY Scan : NO K
2115 11:55:21.392137 ZQ Calibration : PASS
2116 11:55:21.394594 Jitter Meter : NO K
2117 11:55:21.398826 CBT Training : PASS
2118 11:55:21.399355 Write leveling : PASS
2119 11:55:21.401815 RX DQS gating : PASS
2120 11:55:21.405228 RX DQ/DQS(RDDQC) : PASS
2121 11:55:21.405749 TX DQ/DQS : PASS
2122 11:55:21.408266 RX DATLAT : PASS
2123 11:55:21.411551 RX DQ/DQS(Engine): PASS
2124 11:55:21.411974 TX OE : NO K
2125 11:55:21.412317 All Pass.
2126 11:55:21.412628
2127 11:55:21.415314 CH 1, Rank 0
2128 11:55:21.418094 SW Impedance : PASS
2129 11:55:21.418590 DUTY Scan : NO K
2130 11:55:21.421458 ZQ Calibration : PASS
2131 11:55:21.421879 Jitter Meter : NO K
2132 11:55:21.425383 CBT Training : PASS
2133 11:55:21.428411 Write leveling : PASS
2134 11:55:21.428935 RX DQS gating : PASS
2135 11:55:21.431596 RX DQ/DQS(RDDQC) : PASS
2136 11:55:21.434727 TX DQ/DQS : PASS
2137 11:55:21.435154 RX DATLAT : PASS
2138 11:55:21.438104 RX DQ/DQS(Engine): PASS
2139 11:55:21.441221 TX OE : NO K
2140 11:55:21.441650 All Pass.
2141 11:55:21.441987
2142 11:55:21.442350 CH 1, Rank 1
2143 11:55:21.445056 SW Impedance : PASS
2144 11:55:21.448168 DUTY Scan : NO K
2145 11:55:21.448686 ZQ Calibration : PASS
2146 11:55:21.451146 Jitter Meter : NO K
2147 11:55:21.454783 CBT Training : PASS
2148 11:55:21.455327 Write leveling : PASS
2149 11:55:21.458407 RX DQS gating : PASS
2150 11:55:21.461185 RX DQ/DQS(RDDQC) : PASS
2151 11:55:21.461652 TX DQ/DQS : PASS
2152 11:55:21.464167 RX DATLAT : PASS
2153 11:55:21.467589 RX DQ/DQS(Engine): PASS
2154 11:55:21.468111 TX OE : NO K
2155 11:55:21.468521 All Pass.
2156 11:55:21.471314
2157 11:55:21.471735 DramC Write-DBI off
2158 11:55:21.474545 PER_BANK_REFRESH: Hybrid Mode
2159 11:55:21.474970 TX_TRACKING: ON
2160 11:55:21.477809 [GetDramInforAfterCalByMRR] Vendor 6.
2161 11:55:21.481275 [GetDramInforAfterCalByMRR] Revision 606.
2162 11:55:21.488486 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 11:55:21.489012 MR0 0x3b3b
2164 11:55:21.489349 MR8 0x5151
2165 11:55:21.491064 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 11:55:21.491483
2167 11:55:21.494613 MR0 0x3b3b
2168 11:55:21.495151 MR8 0x5151
2169 11:55:21.497577 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 11:55:21.498002
2171 11:55:21.507591 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 11:55:21.510552 [FAST_K] Save calibration result to emmc
2173 11:55:21.514133 [FAST_K] Save calibration result to emmc
2174 11:55:21.517318 dram_init: config_dvfs: 1
2175 11:55:21.521538 dramc_set_vcore_voltage set vcore to 662500
2176 11:55:21.524375 Read voltage for 1200, 2
2177 11:55:21.524912 Vio18 = 0
2178 11:55:21.525250 Vcore = 662500
2179 11:55:21.527172 Vdram = 0
2180 11:55:21.527590 Vddq = 0
2181 11:55:21.527922 Vmddr = 0
2182 11:55:21.534031 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 11:55:21.537363 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 11:55:21.540440 MEM_TYPE=3, freq_sel=15
2185 11:55:21.544139 sv_algorithm_assistance_LP4_1600
2186 11:55:21.547527 ============ PULL DRAM RESETB DOWN ============
2187 11:55:21.550920 ========== PULL DRAM RESETB DOWN end =========
2188 11:55:21.557120 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 11:55:21.560954 ===================================
2190 11:55:21.561483 LPDDR4 DRAM CONFIGURATION
2191 11:55:21.563890 ===================================
2192 11:55:21.567604 EX_ROW_EN[0] = 0x0
2193 11:55:21.570873 EX_ROW_EN[1] = 0x0
2194 11:55:21.571300 LP4Y_EN = 0x0
2195 11:55:21.574076 WORK_FSP = 0x0
2196 11:55:21.574640 WL = 0x4
2197 11:55:21.577288 RL = 0x4
2198 11:55:21.577980 BL = 0x2
2199 11:55:21.580233 RPST = 0x0
2200 11:55:21.580656 RD_PRE = 0x0
2201 11:55:21.583649 WR_PRE = 0x1
2202 11:55:21.584071 WR_PST = 0x0
2203 11:55:21.586850 DBI_WR = 0x0
2204 11:55:21.587274 DBI_RD = 0x0
2205 11:55:21.590309 OTF = 0x1
2206 11:55:21.593774 ===================================
2207 11:55:21.597182 ===================================
2208 11:55:21.597611 ANA top config
2209 11:55:21.600122 ===================================
2210 11:55:21.603480 DLL_ASYNC_EN = 0
2211 11:55:21.607093 ALL_SLAVE_EN = 0
2212 11:55:21.611016 NEW_RANK_MODE = 1
2213 11:55:21.611547 DLL_IDLE_MODE = 1
2214 11:55:21.613710 LP45_APHY_COMB_EN = 1
2215 11:55:21.616905 TX_ODT_DIS = 1
2216 11:55:21.620339 NEW_8X_MODE = 1
2217 11:55:21.624066 ===================================
2218 11:55:21.627041 ===================================
2219 11:55:21.629922 data_rate = 2400
2220 11:55:21.630477 CKR = 1
2221 11:55:21.633627 DQ_P2S_RATIO = 8
2222 11:55:21.636838 ===================================
2223 11:55:21.639872 CA_P2S_RATIO = 8
2224 11:55:21.643122 DQ_CA_OPEN = 0
2225 11:55:21.647030 DQ_SEMI_OPEN = 0
2226 11:55:21.650342 CA_SEMI_OPEN = 0
2227 11:55:21.650869 CA_FULL_RATE = 0
2228 11:55:21.653381 DQ_CKDIV4_EN = 0
2229 11:55:21.656936 CA_CKDIV4_EN = 0
2230 11:55:21.660482 CA_PREDIV_EN = 0
2231 11:55:21.662952 PH8_DLY = 17
2232 11:55:21.666852 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 11:55:21.667373 DQ_AAMCK_DIV = 4
2234 11:55:21.670119 CA_AAMCK_DIV = 4
2235 11:55:21.673479 CA_ADMCK_DIV = 4
2236 11:55:21.676558 DQ_TRACK_CA_EN = 0
2237 11:55:21.680113 CA_PICK = 1200
2238 11:55:21.683657 CA_MCKIO = 1200
2239 11:55:21.686344 MCKIO_SEMI = 0
2240 11:55:21.686945 PLL_FREQ = 2366
2241 11:55:21.689805 DQ_UI_PI_RATIO = 32
2242 11:55:21.693417 CA_UI_PI_RATIO = 0
2243 11:55:21.696321 ===================================
2244 11:55:21.699752 ===================================
2245 11:55:21.702826 memory_type:LPDDR4
2246 11:55:21.703287 GP_NUM : 10
2247 11:55:21.706240 SRAM_EN : 1
2248 11:55:21.709413 MD32_EN : 0
2249 11:55:21.712995 ===================================
2250 11:55:21.713416 [ANA_INIT] >>>>>>>>>>>>>>
2251 11:55:21.716569 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 11:55:21.719966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 11:55:21.723113 ===================================
2254 11:55:21.726213 data_rate = 2400,PCW = 0X5b00
2255 11:55:21.730138 ===================================
2256 11:55:21.733239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 11:55:21.739955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 11:55:21.742576 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 11:55:21.749660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 11:55:21.752995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 11:55:21.756059 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 11:55:21.759847 [ANA_INIT] flow start
2263 11:55:21.760413 [ANA_INIT] PLL >>>>>>>>
2264 11:55:21.763155 [ANA_INIT] PLL <<<<<<<<
2265 11:55:21.767013 [ANA_INIT] MIDPI >>>>>>>>
2266 11:55:21.767581 [ANA_INIT] MIDPI <<<<<<<<
2267 11:55:21.769457 [ANA_INIT] DLL >>>>>>>>
2268 11:55:21.772815 [ANA_INIT] DLL <<<<<<<<
2269 11:55:21.773386 [ANA_INIT] flow end
2270 11:55:21.779248 ============ LP4 DIFF to SE enter ============
2271 11:55:21.782487 ============ LP4 DIFF to SE exit ============
2272 11:55:21.782960 [ANA_INIT] <<<<<<<<<<<<<
2273 11:55:21.785933 [Flow] Enable top DCM control >>>>>
2274 11:55:21.789603 [Flow] Enable top DCM control <<<<<
2275 11:55:21.793511 Enable DLL master slave shuffle
2276 11:55:21.798950 ==============================================================
2277 11:55:21.802745 Gating Mode config
2278 11:55:21.805861 ==============================================================
2279 11:55:21.809119 Config description:
2280 11:55:21.819261 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 11:55:21.826680 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 11:55:21.829134 SELPH_MODE 0: By rank 1: By Phase
2283 11:55:21.835894 ==============================================================
2284 11:55:21.839644 GAT_TRACK_EN = 1
2285 11:55:21.842863 RX_GATING_MODE = 2
2286 11:55:21.843334 RX_GATING_TRACK_MODE = 2
2287 11:55:21.846412 SELPH_MODE = 1
2288 11:55:21.849075 PICG_EARLY_EN = 1
2289 11:55:21.852811 VALID_LAT_VALUE = 1
2290 11:55:21.859262 ==============================================================
2291 11:55:21.862712 Enter into Gating configuration >>>>
2292 11:55:21.865797 Exit from Gating configuration <<<<
2293 11:55:21.869485 Enter into DVFS_PRE_config >>>>>
2294 11:55:21.878958 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 11:55:21.882395 Exit from DVFS_PRE_config <<<<<
2296 11:55:21.885787 Enter into PICG configuration >>>>
2297 11:55:21.888872 Exit from PICG configuration <<<<
2298 11:55:21.892231 [RX_INPUT] configuration >>>>>
2299 11:55:21.895237 [RX_INPUT] configuration <<<<<
2300 11:55:21.899056 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 11:55:21.905452 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 11:55:21.912022 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 11:55:21.918559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 11:55:21.925160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 11:55:21.928765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 11:55:21.935589 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 11:55:21.938623 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 11:55:21.941881 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 11:55:21.945097 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 11:55:21.951828 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 11:55:21.955752 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 11:55:21.958786 ===================================
2313 11:55:21.962056 LPDDR4 DRAM CONFIGURATION
2314 11:55:21.965007 ===================================
2315 11:55:21.965576 EX_ROW_EN[0] = 0x0
2316 11:55:21.968452 EX_ROW_EN[1] = 0x0
2317 11:55:21.969017 LP4Y_EN = 0x0
2318 11:55:21.971604 WORK_FSP = 0x0
2319 11:55:21.972069 WL = 0x4
2320 11:55:21.975048 RL = 0x4
2321 11:55:21.975613 BL = 0x2
2322 11:55:21.978341 RPST = 0x0
2323 11:55:21.978902 RD_PRE = 0x0
2324 11:55:21.982391 WR_PRE = 0x1
2325 11:55:21.982935 WR_PST = 0x0
2326 11:55:21.985169 DBI_WR = 0x0
2327 11:55:21.988317 DBI_RD = 0x0
2328 11:55:21.988836 OTF = 0x1
2329 11:55:21.991343 ===================================
2330 11:55:21.994648 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 11:55:21.998461 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 11:55:22.004796 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 11:55:22.008451 ===================================
2334 11:55:22.011319 LPDDR4 DRAM CONFIGURATION
2335 11:55:22.014724 ===================================
2336 11:55:22.015363 EX_ROW_EN[0] = 0x10
2337 11:55:22.017666 EX_ROW_EN[1] = 0x0
2338 11:55:22.018159 LP4Y_EN = 0x0
2339 11:55:22.021155 WORK_FSP = 0x0
2340 11:55:22.021665 WL = 0x4
2341 11:55:22.024702 RL = 0x4
2342 11:55:22.025244 BL = 0x2
2343 11:55:22.027825 RPST = 0x0
2344 11:55:22.028285 RD_PRE = 0x0
2345 11:55:22.031632 WR_PRE = 0x1
2346 11:55:22.032161 WR_PST = 0x0
2347 11:55:22.034502 DBI_WR = 0x0
2348 11:55:22.034927 DBI_RD = 0x0
2349 11:55:22.038513 OTF = 0x1
2350 11:55:22.041324 ===================================
2351 11:55:22.048338 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 11:55:22.048871 ==
2353 11:55:22.051460 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 11:55:22.055062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 11:55:22.055596 ==
2356 11:55:22.058095 [Duty_Offset_Calibration]
2357 11:55:22.058670 B0:2 B1:0 CA:4
2358 11:55:22.059012
2359 11:55:22.061114 [DutyScan_Calibration_Flow] k_type=0
2360 11:55:22.071088
2361 11:55:22.071503 ==CLK 0==
2362 11:55:22.074052 Final CLK duty delay cell = -4
2363 11:55:22.078017 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2364 11:55:22.081328 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2365 11:55:22.084241 [-4] AVG Duty = 4937%(X100)
2366 11:55:22.084763
2367 11:55:22.087773 CH0 CLK Duty spec in!! Max-Min= 187%
2368 11:55:22.091129 [DutyScan_Calibration_Flow] ====Done====
2369 11:55:22.091652
2370 11:55:22.094031 [DutyScan_Calibration_Flow] k_type=1
2371 11:55:22.110448
2372 11:55:22.110869 ==DQS 0 ==
2373 11:55:22.114150 Final DQS duty delay cell = 0
2374 11:55:22.118702 [0] MAX Duty = 5156%(X100), DQS PI = 14
2375 11:55:22.120895 [0] MIN Duty = 5093%(X100), DQS PI = 2
2376 11:55:22.121316 [0] AVG Duty = 5124%(X100)
2377 11:55:22.124536
2378 11:55:22.124954 ==DQS 1 ==
2379 11:55:22.127407 Final DQS duty delay cell = 0
2380 11:55:22.130428 [0] MAX Duty = 5125%(X100), DQS PI = 4
2381 11:55:22.133728 [0] MIN Duty = 4969%(X100), DQS PI = 62
2382 11:55:22.134151 [0] AVG Duty = 5047%(X100)
2383 11:55:22.136997
2384 11:55:22.140742 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2385 11:55:22.141159
2386 11:55:22.143817 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2387 11:55:22.148023 [DutyScan_Calibration_Flow] ====Done====
2388 11:55:22.148547
2389 11:55:22.150677 [DutyScan_Calibration_Flow] k_type=3
2390 11:55:22.167176
2391 11:55:22.167697 ==DQM 0 ==
2392 11:55:22.170248 Final DQM duty delay cell = 0
2393 11:55:22.174374 [0] MAX Duty = 5125%(X100), DQS PI = 18
2394 11:55:22.177500 [0] MIN Duty = 4844%(X100), DQS PI = 54
2395 11:55:22.180539 [0] AVG Duty = 4984%(X100)
2396 11:55:22.181099
2397 11:55:22.181466 ==DQM 1 ==
2398 11:55:22.183468 Final DQM duty delay cell = 0
2399 11:55:22.187628 [0] MAX Duty = 5000%(X100), DQS PI = 8
2400 11:55:22.189820 [0] MIN Duty = 4875%(X100), DQS PI = 20
2401 11:55:22.193616 [0] AVG Duty = 4937%(X100)
2402 11:55:22.194184
2403 11:55:22.196991 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2404 11:55:22.197574
2405 11:55:22.200090 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2406 11:55:22.203176 [DutyScan_Calibration_Flow] ====Done====
2407 11:55:22.203640
2408 11:55:22.207248 [DutyScan_Calibration_Flow] k_type=2
2409 11:55:22.223808
2410 11:55:22.224446 ==DQ 0 ==
2411 11:55:22.226798 Final DQ duty delay cell = 0
2412 11:55:22.230390 [0] MAX Duty = 5156%(X100), DQS PI = 18
2413 11:55:22.233325 [0] MIN Duty = 4969%(X100), DQS PI = 56
2414 11:55:22.233747 [0] AVG Duty = 5062%(X100)
2415 11:55:22.237191
2416 11:55:22.237722 ==DQ 1 ==
2417 11:55:22.239986 Final DQ duty delay cell = 0
2418 11:55:22.243315 [0] MAX Duty = 5156%(X100), DQS PI = 6
2419 11:55:22.246540 [0] MIN Duty = 4938%(X100), DQS PI = 16
2420 11:55:22.246959 [0] AVG Duty = 5047%(X100)
2421 11:55:22.247288
2422 11:55:22.252926 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2423 11:55:22.253472
2424 11:55:22.256964 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2425 11:55:22.259668 [DutyScan_Calibration_Flow] ====Done====
2426 11:55:22.260379 ==
2427 11:55:22.263083 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 11:55:22.266309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 11:55:22.266786 ==
2430 11:55:22.269511 [Duty_Offset_Calibration]
2431 11:55:22.269931 B0:0 B1:-1 CA:3
2432 11:55:22.270305
2433 11:55:22.272865 [DutyScan_Calibration_Flow] k_type=0
2434 11:55:22.282588
2435 11:55:22.283006 ==CLK 0==
2436 11:55:22.286045 Final CLK duty delay cell = -4
2437 11:55:22.289168 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2438 11:55:22.292911 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2439 11:55:22.295809 [-4] AVG Duty = 4938%(X100)
2440 11:55:22.296252
2441 11:55:22.299608 CH1 CLK Duty spec in!! Max-Min= 124%
2442 11:55:22.302753 [DutyScan_Calibration_Flow] ====Done====
2443 11:55:22.303179
2444 11:55:22.305663 [DutyScan_Calibration_Flow] k_type=1
2445 11:55:22.322593
2446 11:55:22.323195 ==DQS 0 ==
2447 11:55:22.325601 Final DQS duty delay cell = 0
2448 11:55:22.329519 [0] MAX Duty = 5187%(X100), DQS PI = 28
2449 11:55:22.332260 [0] MIN Duty = 4907%(X100), DQS PI = 38
2450 11:55:22.335432 [0] AVG Duty = 5047%(X100)
2451 11:55:22.335944
2452 11:55:22.336281 ==DQS 1 ==
2453 11:55:22.339286 Final DQS duty delay cell = 0
2454 11:55:22.341941 [0] MAX Duty = 5156%(X100), DQS PI = 8
2455 11:55:22.345795 [0] MIN Duty = 5031%(X100), DQS PI = 20
2456 11:55:22.348602 [0] AVG Duty = 5093%(X100)
2457 11:55:22.349024
2458 11:55:22.352393 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2459 11:55:22.352920
2460 11:55:22.355630 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2461 11:55:22.359108 [DutyScan_Calibration_Flow] ====Done====
2462 11:55:22.359678
2463 11:55:22.361915 [DutyScan_Calibration_Flow] k_type=3
2464 11:55:22.379310
2465 11:55:22.379877 ==DQM 0 ==
2466 11:55:22.382242 Final DQM duty delay cell = 0
2467 11:55:22.385423 [0] MAX Duty = 5031%(X100), DQS PI = 28
2468 11:55:22.388951 [0] MIN Duty = 4813%(X100), DQS PI = 38
2469 11:55:22.392111 [0] AVG Duty = 4922%(X100)
2470 11:55:22.392807
2471 11:55:22.393187 ==DQM 1 ==
2472 11:55:22.395447 Final DQM duty delay cell = 0
2473 11:55:22.398872 [0] MAX Duty = 5000%(X100), DQS PI = 34
2474 11:55:22.401735 [0] MIN Duty = 4844%(X100), DQS PI = 0
2475 11:55:22.405816 [0] AVG Duty = 4922%(X100)
2476 11:55:22.406588
2477 11:55:22.408516 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2478 11:55:22.408982
2479 11:55:22.411876 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2480 11:55:22.415308 [DutyScan_Calibration_Flow] ====Done====
2481 11:55:22.415773
2482 11:55:22.418569 [DutyScan_Calibration_Flow] k_type=2
2483 11:55:22.434852
2484 11:55:22.435413 ==DQ 0 ==
2485 11:55:22.438214 Final DQ duty delay cell = -4
2486 11:55:22.441651 [-4] MAX Duty = 5000%(X100), DQS PI = 14
2487 11:55:22.444762 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2488 11:55:22.448405 [-4] AVG Duty = 4922%(X100)
2489 11:55:22.448972
2490 11:55:22.449346 ==DQ 1 ==
2491 11:55:22.451141 Final DQ duty delay cell = 0
2492 11:55:22.454868 [0] MAX Duty = 5031%(X100), DQS PI = 34
2493 11:55:22.458047 [0] MIN Duty = 4844%(X100), DQS PI = 0
2494 11:55:22.460912 [0] AVG Duty = 4937%(X100)
2495 11:55:22.461379
2496 11:55:22.464806 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 11:55:22.465375
2498 11:55:22.467593 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2499 11:55:22.471216 [DutyScan_Calibration_Flow] ====Done====
2500 11:55:22.474293 nWR fixed to 30
2501 11:55:22.478081 [ModeRegInit_LP4] CH0 RK0
2502 11:55:22.478693 [ModeRegInit_LP4] CH0 RK1
2503 11:55:22.481530 [ModeRegInit_LP4] CH1 RK0
2504 11:55:22.484434 [ModeRegInit_LP4] CH1 RK1
2505 11:55:22.485001 match AC timing 7
2506 11:55:22.491081 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 11:55:22.494574 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 11:55:22.497494 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 11:55:22.504413 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 11:55:22.508072 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 11:55:22.508543 ==
2512 11:55:22.510762 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:55:22.513935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:55:22.514455 ==
2515 11:55:22.521036 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 11:55:22.527379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2517 11:55:22.534990 [CA 0] Center 39 (9~70) winsize 62
2518 11:55:22.538908 [CA 1] Center 39 (9~70) winsize 62
2519 11:55:22.541659 [CA 2] Center 35 (5~66) winsize 62
2520 11:55:22.544655 [CA 3] Center 35 (4~66) winsize 63
2521 11:55:22.548247 [CA 4] Center 33 (3~64) winsize 62
2522 11:55:22.551335 [CA 5] Center 33 (3~64) winsize 62
2523 11:55:22.551803
2524 11:55:22.555594 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 11:55:22.556167
2526 11:55:22.558380 [CATrainingPosCal] consider 1 rank data
2527 11:55:22.561503 u2DelayCellTimex100 = 270/100 ps
2528 11:55:22.564576 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 11:55:22.568155 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 11:55:22.574655 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 11:55:22.578127 CA3 delay=35 (4~66),Diff = 2 PI (9 cell)
2532 11:55:22.581490 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2533 11:55:22.584656 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2534 11:55:22.585227
2535 11:55:22.587548 CA PerBit enable=1, Macro0, CA PI delay=33
2536 11:55:22.588014
2537 11:55:22.591152 [CBTSetCACLKResult] CA Dly = 33
2538 11:55:22.594798 CS Dly: 7 (0~38)
2539 11:55:22.595357 ==
2540 11:55:22.597686 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 11:55:22.601155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 11:55:22.601628 ==
2543 11:55:22.607875 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 11:55:22.611068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 11:55:22.620842 [CA 0] Center 39 (9~70) winsize 62
2546 11:55:22.623777 [CA 1] Center 39 (9~70) winsize 62
2547 11:55:22.626990 [CA 2] Center 35 (5~66) winsize 62
2548 11:55:22.630521 [CA 3] Center 35 (5~66) winsize 62
2549 11:55:22.633905 [CA 4] Center 34 (4~65) winsize 62
2550 11:55:22.637542 [CA 5] Center 33 (3~64) winsize 62
2551 11:55:22.638011
2552 11:55:22.640913 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2553 11:55:22.641480
2554 11:55:22.644559 [CATrainingPosCal] consider 2 rank data
2555 11:55:22.647035 u2DelayCellTimex100 = 270/100 ps
2556 11:55:22.650532 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 11:55:22.657330 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 11:55:22.660491 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2559 11:55:22.664104 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 11:55:22.667760 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2561 11:55:22.670802 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2562 11:55:22.671363
2563 11:55:22.673872 CA PerBit enable=1, Macro0, CA PI delay=33
2564 11:55:22.674468
2565 11:55:22.677289 [CBTSetCACLKResult] CA Dly = 33
2566 11:55:22.677842 CS Dly: 8 (0~41)
2567 11:55:22.680659
2568 11:55:22.683530 ----->DramcWriteLeveling(PI) begin...
2569 11:55:22.684093 ==
2570 11:55:22.686864 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 11:55:22.690161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 11:55:22.690761 ==
2573 11:55:22.693897 Write leveling (Byte 0): 31 => 31
2574 11:55:22.696884 Write leveling (Byte 1): 29 => 29
2575 11:55:22.701005 DramcWriteLeveling(PI) end<-----
2576 11:55:22.701565
2577 11:55:22.701936 ==
2578 11:55:22.703030 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:55:22.706822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:55:22.707294 ==
2581 11:55:22.709671 [Gating] SW mode calibration
2582 11:55:22.716403 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 11:55:22.723245 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 11:55:22.726944 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2585 11:55:22.730570 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2586 11:55:22.737291 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:55:22.740170 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:55:22.743374 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:55:22.749675 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:55:22.753323 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2591 11:55:22.756789 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 1)
2592 11:55:22.762861 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2593 11:55:22.766776 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 11:55:22.769773 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:55:22.776358 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:55:22.779709 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:55:22.783260 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:55:22.790192 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2599 11:55:22.793052 1 0 28 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
2600 11:55:22.796413 1 1 0 | B1->B0 | 2f2f 4646 | 1 0 | (0 0) (0 0)
2601 11:55:22.802655 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2602 11:55:22.807138 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:55:22.809132 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:55:22.815595 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:55:22.819148 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:55:22.822493 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:55:22.826042 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 11:55:22.833023 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 11:55:22.836152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:55:22.839158 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:55:22.845763 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:55:22.849398 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:55:22.852816 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:55:22.859032 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:55:22.862434 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:55:22.865955 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:55:22.872980 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:55:22.875531 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:55:22.879260 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:55:22.886547 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:55:22.889378 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:55:22.892331 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 11:55:22.899197 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2624 11:55:22.902450 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2625 11:55:22.905729 Total UI for P1: 0, mck2ui 16
2626 11:55:22.909331 best dqsien dly found for B0: ( 1, 3, 26)
2627 11:55:22.913021 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 11:55:22.915549 Total UI for P1: 0, mck2ui 16
2629 11:55:22.918775 best dqsien dly found for B1: ( 1, 4, 0)
2630 11:55:22.922185 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2631 11:55:22.925276 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 11:55:22.925743
2633 11:55:22.932375 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2634 11:55:22.935560 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 11:55:22.936135 [Gating] SW calibration Done
2636 11:55:22.938399 ==
2637 11:55:22.938866 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:55:22.945177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:55:22.945648 ==
2640 11:55:22.946019 RX Vref Scan: 0
2641 11:55:22.946420
2642 11:55:22.948596 RX Vref 0 -> 0, step: 1
2643 11:55:22.949170
2644 11:55:22.952048 RX Delay -40 -> 252, step: 8
2645 11:55:22.954928 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2646 11:55:22.958512 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2647 11:55:22.961889 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 11:55:22.968548 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2649 11:55:22.971938 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2650 11:55:22.975410 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2651 11:55:22.978481 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 11:55:22.982172 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2653 11:55:22.988646 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2654 11:55:22.991791 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2655 11:55:22.995346 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2656 11:55:22.998794 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2657 11:55:23.002220 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 11:55:23.008747 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2659 11:55:23.011931 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2660 11:55:23.015383 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2661 11:55:23.015937 ==
2662 11:55:23.018378 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 11:55:23.022087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 11:55:23.022712 ==
2665 11:55:23.025291 DQS Delay:
2666 11:55:23.025844 DQS0 = 0, DQS1 = 0
2667 11:55:23.028381 DQM Delay:
2668 11:55:23.028936 DQM0 = 118, DQM1 = 107
2669 11:55:23.032173 DQ Delay:
2670 11:55:23.034674 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2671 11:55:23.038925 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2672 11:55:23.041431 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2673 11:55:23.045107 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2674 11:55:23.045577
2675 11:55:23.045961
2676 11:55:23.046350 ==
2677 11:55:23.048606 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 11:55:23.051588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 11:55:23.052015 ==
2680 11:55:23.052347
2681 11:55:23.052654
2682 11:55:23.054601 TX Vref Scan disable
2683 11:55:23.058367 == TX Byte 0 ==
2684 11:55:23.061861 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2685 11:55:23.065009 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2686 11:55:23.068696 == TX Byte 1 ==
2687 11:55:23.071589 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2688 11:55:23.076561 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2689 11:55:23.077077 ==
2690 11:55:23.078138 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:55:23.081591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:55:23.084799 ==
2693 11:55:23.094627 TX Vref=22, minBit 1, minWin=25, winSum=408
2694 11:55:23.098793 TX Vref=24, minBit 3, minWin=25, winSum=418
2695 11:55:23.101723 TX Vref=26, minBit 3, minWin=25, winSum=422
2696 11:55:23.105317 TX Vref=28, minBit 4, minWin=26, winSum=427
2697 11:55:23.108563 TX Vref=30, minBit 3, minWin=26, winSum=428
2698 11:55:23.115214 TX Vref=32, minBit 2, minWin=26, winSum=428
2699 11:55:23.118295 [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 30
2700 11:55:23.118819
2701 11:55:23.121719 Final TX Range 1 Vref 30
2702 11:55:23.122228
2703 11:55:23.122602 ==
2704 11:55:23.124936 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 11:55:23.128513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 11:55:23.129030 ==
2707 11:55:23.132564
2708 11:55:23.133083
2709 11:55:23.133419 TX Vref Scan disable
2710 11:55:23.135096 == TX Byte 0 ==
2711 11:55:23.137866 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2712 11:55:23.144511 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2713 11:55:23.145013 == TX Byte 1 ==
2714 11:55:23.147662 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2715 11:55:23.154549 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2716 11:55:23.154973
2717 11:55:23.155307 [DATLAT]
2718 11:55:23.155618 Freq=1200, CH0 RK0
2719 11:55:23.155917
2720 11:55:23.157387 DATLAT Default: 0xd
2721 11:55:23.157809 0, 0xFFFF, sum = 0
2722 11:55:23.161335 1, 0xFFFF, sum = 0
2723 11:55:23.161855 2, 0xFFFF, sum = 0
2724 11:55:23.164915 3, 0xFFFF, sum = 0
2725 11:55:23.167866 4, 0xFFFF, sum = 0
2726 11:55:23.168386 5, 0xFFFF, sum = 0
2727 11:55:23.170968 6, 0xFFFF, sum = 0
2728 11:55:23.171396 7, 0xFFFF, sum = 0
2729 11:55:23.174473 8, 0xFFFF, sum = 0
2730 11:55:23.175078 9, 0xFFFF, sum = 0
2731 11:55:23.177640 10, 0xFFFF, sum = 0
2732 11:55:23.178161 11, 0xFFFF, sum = 0
2733 11:55:23.181405 12, 0x0, sum = 1
2734 11:55:23.181920 13, 0x0, sum = 2
2735 11:55:23.184135 14, 0x0, sum = 3
2736 11:55:23.184562 15, 0x0, sum = 4
2737 11:55:23.187753 best_step = 13
2738 11:55:23.188173
2739 11:55:23.188505 ==
2740 11:55:23.191250 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 11:55:23.194126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 11:55:23.194686 ==
2743 11:55:23.195025 RX Vref Scan: 1
2744 11:55:23.195337
2745 11:55:23.198051 Set Vref Range= 32 -> 127
2746 11:55:23.198613
2747 11:55:23.200923 RX Vref 32 -> 127, step: 1
2748 11:55:23.201435
2749 11:55:23.204024 RX Delay -21 -> 252, step: 4
2750 11:55:23.204447
2751 11:55:23.208316 Set Vref, RX VrefLevel [Byte0]: 32
2752 11:55:23.210859 [Byte1]: 32
2753 11:55:23.211431
2754 11:55:23.214279 Set Vref, RX VrefLevel [Byte0]: 33
2755 11:55:23.217576 [Byte1]: 33
2756 11:55:23.220746
2757 11:55:23.221168 Set Vref, RX VrefLevel [Byte0]: 34
2758 11:55:23.224582 [Byte1]: 34
2759 11:55:23.229497
2760 11:55:23.230009 Set Vref, RX VrefLevel [Byte0]: 35
2761 11:55:23.232839 [Byte1]: 35
2762 11:55:23.237500
2763 11:55:23.238010 Set Vref, RX VrefLevel [Byte0]: 36
2764 11:55:23.240181 [Byte1]: 36
2765 11:55:23.245029
2766 11:55:23.245545 Set Vref, RX VrefLevel [Byte0]: 37
2767 11:55:23.248530 [Byte1]: 37
2768 11:55:23.253223
2769 11:55:23.253736 Set Vref, RX VrefLevel [Byte0]: 38
2770 11:55:23.256423 [Byte1]: 38
2771 11:55:23.261084
2772 11:55:23.261594 Set Vref, RX VrefLevel [Byte0]: 39
2773 11:55:23.264036 [Byte1]: 39
2774 11:55:23.269201
2775 11:55:23.269720 Set Vref, RX VrefLevel [Byte0]: 40
2776 11:55:23.272459 [Byte1]: 40
2777 11:55:23.277678
2778 11:55:23.278205 Set Vref, RX VrefLevel [Byte0]: 41
2779 11:55:23.279706 [Byte1]: 41
2780 11:55:23.284936
2781 11:55:23.285445 Set Vref, RX VrefLevel [Byte0]: 42
2782 11:55:23.288177 [Byte1]: 42
2783 11:55:23.292369
2784 11:55:23.292877 Set Vref, RX VrefLevel [Byte0]: 43
2785 11:55:23.296005 [Byte1]: 43
2786 11:55:23.300439
2787 11:55:23.300937 Set Vref, RX VrefLevel [Byte0]: 44
2788 11:55:23.303449 [Byte1]: 44
2789 11:55:23.308894
2790 11:55:23.309395 Set Vref, RX VrefLevel [Byte0]: 45
2791 11:55:23.311503 [Byte1]: 45
2792 11:55:23.315996
2793 11:55:23.316537 Set Vref, RX VrefLevel [Byte0]: 46
2794 11:55:23.319799 [Byte1]: 46
2795 11:55:23.324231
2796 11:55:23.324928 Set Vref, RX VrefLevel [Byte0]: 47
2797 11:55:23.327353 [Byte1]: 47
2798 11:55:23.332390
2799 11:55:23.332901 Set Vref, RX VrefLevel [Byte0]: 48
2800 11:55:23.335056 [Byte1]: 48
2801 11:55:23.339785
2802 11:55:23.340247 Set Vref, RX VrefLevel [Byte0]: 49
2803 11:55:23.343154 [Byte1]: 49
2804 11:55:23.348086
2805 11:55:23.348506 Set Vref, RX VrefLevel [Byte0]: 50
2806 11:55:23.351097 [Byte1]: 50
2807 11:55:23.356183
2808 11:55:23.356698 Set Vref, RX VrefLevel [Byte0]: 51
2809 11:55:23.358861 [Byte1]: 51
2810 11:55:23.363417
2811 11:55:23.363837 Set Vref, RX VrefLevel [Byte0]: 52
2812 11:55:23.366933 [Byte1]: 52
2813 11:55:23.371609
2814 11:55:23.372026 Set Vref, RX VrefLevel [Byte0]: 53
2815 11:55:23.375066 [Byte1]: 53
2816 11:55:23.379754
2817 11:55:23.380259 Set Vref, RX VrefLevel [Byte0]: 54
2818 11:55:23.382879 [Byte1]: 54
2819 11:55:23.387678
2820 11:55:23.388188 Set Vref, RX VrefLevel [Byte0]: 55
2821 11:55:23.391155 [Byte1]: 55
2822 11:55:23.395742
2823 11:55:23.396244 Set Vref, RX VrefLevel [Byte0]: 56
2824 11:55:23.398425 [Byte1]: 56
2825 11:55:23.403460
2826 11:55:23.403907 Set Vref, RX VrefLevel [Byte0]: 57
2827 11:55:23.406461 [Byte1]: 57
2828 11:55:23.411106
2829 11:55:23.411527 Set Vref, RX VrefLevel [Byte0]: 58
2830 11:55:23.414413 [Byte1]: 58
2831 11:55:23.419477
2832 11:55:23.419984 Set Vref, RX VrefLevel [Byte0]: 59
2833 11:55:23.422826 [Byte1]: 59
2834 11:55:23.427136
2835 11:55:23.427556 Set Vref, RX VrefLevel [Byte0]: 60
2836 11:55:23.431497 [Byte1]: 60
2837 11:55:23.434967
2838 11:55:23.435592 Set Vref, RX VrefLevel [Byte0]: 61
2839 11:55:23.438802 [Byte1]: 61
2840 11:55:23.443052
2841 11:55:23.443615 Set Vref, RX VrefLevel [Byte0]: 62
2842 11:55:23.446177 [Byte1]: 62
2843 11:55:23.451121
2844 11:55:23.451633 Set Vref, RX VrefLevel [Byte0]: 63
2845 11:55:23.454349 [Byte1]: 63
2846 11:55:23.459158
2847 11:55:23.459669 Set Vref, RX VrefLevel [Byte0]: 64
2848 11:55:23.462457 [Byte1]: 64
2849 11:55:23.466922
2850 11:55:23.467452 Set Vref, RX VrefLevel [Byte0]: 65
2851 11:55:23.470419 [Byte1]: 65
2852 11:55:23.474968
2853 11:55:23.475540 Set Vref, RX VrefLevel [Byte0]: 66
2854 11:55:23.478665 [Byte1]: 66
2855 11:55:23.482907
2856 11:55:23.483454 Set Vref, RX VrefLevel [Byte0]: 67
2857 11:55:23.487240 [Byte1]: 67
2858 11:55:23.490817
2859 11:55:23.491371 Set Vref, RX VrefLevel [Byte0]: 68
2860 11:55:23.494060 [Byte1]: 68
2861 11:55:23.498915
2862 11:55:23.499459 Set Vref, RX VrefLevel [Byte0]: 69
2863 11:55:23.501612 [Byte1]: 69
2864 11:55:23.506865
2865 11:55:23.507428 Final RX Vref Byte 0 = 53 to rank0
2866 11:55:23.509927 Final RX Vref Byte 1 = 59 to rank0
2867 11:55:23.513416 Final RX Vref Byte 0 = 53 to rank1
2868 11:55:23.516272 Final RX Vref Byte 1 = 59 to rank1==
2869 11:55:23.519977 Dram Type= 6, Freq= 0, CH_0, rank 0
2870 11:55:23.526378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2871 11:55:23.526937 ==
2872 11:55:23.527307 DQS Delay:
2873 11:55:23.527648 DQS0 = 0, DQS1 = 0
2874 11:55:23.529726 DQM Delay:
2875 11:55:23.530336 DQM0 = 117, DQM1 = 105
2876 11:55:23.533439 DQ Delay:
2877 11:55:23.535910 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2878 11:55:23.539469 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2879 11:55:23.543269 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2880 11:55:23.546237 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2881 11:55:23.546750
2882 11:55:23.547112
2883 11:55:23.553580 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2884 11:55:23.556183 CH0 RK0: MR19=403, MR18=3FE
2885 11:55:23.562655 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2886 11:55:23.563163
2887 11:55:23.566224 ----->DramcWriteLeveling(PI) begin...
2888 11:55:23.566683 ==
2889 11:55:23.569586 Dram Type= 6, Freq= 0, CH_0, rank 1
2890 11:55:23.573097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2891 11:55:23.576379 ==
2892 11:55:23.576805 Write leveling (Byte 0): 31 => 31
2893 11:55:23.580180 Write leveling (Byte 1): 27 => 27
2894 11:55:23.582993 DramcWriteLeveling(PI) end<-----
2895 11:55:23.583542
2896 11:55:23.583908 ==
2897 11:55:23.586473 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 11:55:23.592983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 11:55:23.593536 ==
2900 11:55:23.593908 [Gating] SW mode calibration
2901 11:55:23.602902 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2902 11:55:23.606326 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2903 11:55:23.609879 0 15 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
2904 11:55:23.616511 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2905 11:55:23.619048 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:55:23.622524 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:55:23.629165 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 11:55:23.633315 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2909 11:55:23.636620 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2910 11:55:23.642816 0 15 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
2911 11:55:23.645943 1 0 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (0 0)
2912 11:55:23.649454 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:55:23.655867 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:55:23.659511 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2915 11:55:23.662696 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 11:55:23.669276 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 11:55:23.672920 1 0 24 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
2918 11:55:23.675719 1 0 28 | B1->B0 | 2a2a 4646 | 1 0 | (0 0) (0 0)
2919 11:55:23.683662 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
2920 11:55:23.685868 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:55:23.688876 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:55:23.696187 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:55:23.699634 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 11:55:23.702607 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 11:55:23.709004 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2926 11:55:23.712564 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
2927 11:55:23.716519 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2928 11:55:23.722170 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:55:23.725786 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:55:23.729286 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:55:23.732730 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:55:23.738929 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:55:23.742227 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:55:23.745792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:55:23.752610 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:55:23.755786 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:55:23.759520 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:55:23.765114 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:55:23.768850 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 11:55:23.772435 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 11:55:23.778811 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2942 11:55:23.782655 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2943 11:55:23.785412 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2944 11:55:23.789022 Total UI for P1: 0, mck2ui 16
2945 11:55:23.792010 best dqsien dly found for B0: ( 1, 3, 26)
2946 11:55:23.799245 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 11:55:23.801806 Total UI for P1: 0, mck2ui 16
2948 11:55:23.805137 best dqsien dly found for B1: ( 1, 4, 0)
2949 11:55:23.808532 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2950 11:55:23.811771 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2951 11:55:23.812322
2952 11:55:23.814875 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2953 11:55:23.818579 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2954 11:55:23.821534 [Gating] SW calibration Done
2955 11:55:23.821996 ==
2956 11:55:23.825184 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 11:55:23.827698 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 11:55:23.828167 ==
2959 11:55:23.831788 RX Vref Scan: 0
2960 11:55:23.832337
2961 11:55:23.834399 RX Vref 0 -> 0, step: 1
2962 11:55:23.834864
2963 11:55:23.835224 RX Delay -40 -> 252, step: 8
2964 11:55:23.841806 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2965 11:55:23.844641 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2966 11:55:23.847740 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2967 11:55:23.851162 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2968 11:55:23.854657 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2969 11:55:23.861080 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2970 11:55:23.864502 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2971 11:55:23.868044 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2972 11:55:23.871258 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2973 11:55:23.874303 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2974 11:55:23.881442 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2975 11:55:23.884448 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2976 11:55:23.888479 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2977 11:55:23.890662 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2978 11:55:23.894133 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2979 11:55:23.901728 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2980 11:55:23.902356 ==
2981 11:55:23.904730 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:55:23.907841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:55:23.908307 ==
2984 11:55:23.908669 DQS Delay:
2985 11:55:23.910484 DQS0 = 0, DQS1 = 0
2986 11:55:23.910941 DQM Delay:
2987 11:55:23.914642 DQM0 = 116, DQM1 = 109
2988 11:55:23.915193 DQ Delay:
2989 11:55:23.917298 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2990 11:55:23.921002 DQ4 =119, DQ5 =107, DQ6 =127, DQ7 =123
2991 11:55:23.924217 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2992 11:55:23.927874 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2993 11:55:23.928427
2994 11:55:23.930802
2995 11:55:23.931352 ==
2996 11:55:23.934036 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 11:55:23.937537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 11:55:23.938094 ==
2999 11:55:23.938683
3000 11:55:23.939164
3001 11:55:23.940373 TX Vref Scan disable
3002 11:55:23.940832 == TX Byte 0 ==
3003 11:55:23.946911 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3004 11:55:23.950553 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3005 11:55:23.951071 == TX Byte 1 ==
3006 11:55:23.957438 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3007 11:55:23.960584 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3008 11:55:23.961094 ==
3009 11:55:23.963797 Dram Type= 6, Freq= 0, CH_0, rank 1
3010 11:55:23.966874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3011 11:55:23.967295 ==
3012 11:55:23.979596 TX Vref=22, minBit 0, minWin=25, winSum=412
3013 11:55:23.982945 TX Vref=24, minBit 9, minWin=25, winSum=419
3014 11:55:23.986636 TX Vref=26, minBit 0, minWin=26, winSum=422
3015 11:55:23.990121 TX Vref=28, minBit 0, minWin=26, winSum=424
3016 11:55:23.993071 TX Vref=30, minBit 14, minWin=25, winSum=424
3017 11:55:23.999753 TX Vref=32, minBit 12, minWin=25, winSum=419
3018 11:55:24.002977 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
3019 11:55:24.003536
3020 11:55:24.006490 Final TX Range 1 Vref 28
3021 11:55:24.007043
3022 11:55:24.007410 ==
3023 11:55:24.009342 Dram Type= 6, Freq= 0, CH_0, rank 1
3024 11:55:24.012560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3025 11:55:24.015759 ==
3026 11:55:24.016263
3027 11:55:24.016752
3028 11:55:24.017079 TX Vref Scan disable
3029 11:55:24.019559 == TX Byte 0 ==
3030 11:55:24.022848 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3031 11:55:24.029287 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3032 11:55:24.029790 == TX Byte 1 ==
3033 11:55:24.032980 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3034 11:55:24.039293 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3035 11:55:24.039894
3036 11:55:24.040234 [DATLAT]
3037 11:55:24.040541 Freq=1200, CH0 RK1
3038 11:55:24.040842
3039 11:55:24.042869 DATLAT Default: 0xd
3040 11:55:24.043285 0, 0xFFFF, sum = 0
3041 11:55:24.046300 1, 0xFFFF, sum = 0
3042 11:55:24.046727 2, 0xFFFF, sum = 0
3043 11:55:24.049469 3, 0xFFFF, sum = 0
3044 11:55:24.053914 4, 0xFFFF, sum = 0
3045 11:55:24.054473 5, 0xFFFF, sum = 0
3046 11:55:24.056880 6, 0xFFFF, sum = 0
3047 11:55:24.057399 7, 0xFFFF, sum = 0
3048 11:55:24.059480 8, 0xFFFF, sum = 0
3049 11:55:24.059999 9, 0xFFFF, sum = 0
3050 11:55:24.062858 10, 0xFFFF, sum = 0
3051 11:55:24.063373 11, 0xFFFF, sum = 0
3052 11:55:24.066174 12, 0x0, sum = 1
3053 11:55:24.066735 13, 0x0, sum = 2
3054 11:55:24.069517 14, 0x0, sum = 3
3055 11:55:24.069943 15, 0x0, sum = 4
3056 11:55:24.070306 best_step = 13
3057 11:55:24.072883
3058 11:55:24.073321 ==
3059 11:55:24.076490 Dram Type= 6, Freq= 0, CH_0, rank 1
3060 11:55:24.079673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3061 11:55:24.080116 ==
3062 11:55:24.080451 RX Vref Scan: 0
3063 11:55:24.080761
3064 11:55:24.083113 RX Vref 0 -> 0, step: 1
3065 11:55:24.083629
3066 11:55:24.086149 RX Delay -21 -> 252, step: 4
3067 11:55:24.089218 iDelay=195, Bit 0, Center 112 (47 ~ 178) 132
3068 11:55:24.095960 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3069 11:55:24.099668 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3070 11:55:24.102653 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3071 11:55:24.106007 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3072 11:55:24.109760 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3073 11:55:24.116257 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3074 11:55:24.119065 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3075 11:55:24.122519 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3076 11:55:24.125962 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3077 11:55:24.129252 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3078 11:55:24.135505 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3079 11:55:24.139297 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3080 11:55:24.141859 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3081 11:55:24.145772 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3082 11:55:24.152702 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3083 11:55:24.153213 ==
3084 11:55:24.155427 Dram Type= 6, Freq= 0, CH_0, rank 1
3085 11:55:24.158834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3086 11:55:24.159343 ==
3087 11:55:24.159678 DQS Delay:
3088 11:55:24.163206 DQS0 = 0, DQS1 = 0
3089 11:55:24.163711 DQM Delay:
3090 11:55:24.165826 DQM0 = 115, DQM1 = 106
3091 11:55:24.166374 DQ Delay:
3092 11:55:24.169589 DQ0 =112, DQ1 =116, DQ2 =110, DQ3 =112
3093 11:55:24.172646 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3094 11:55:24.175445 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3095 11:55:24.179027 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =112
3096 11:55:24.179532
3097 11:55:24.179930
3098 11:55:24.188808 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3099 11:55:24.192666 CH0 RK1: MR19=403, MR18=1FE
3100 11:55:24.195459 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3101 11:55:24.198807 [RxdqsGatingPostProcess] freq 1200
3102 11:55:24.205325 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3103 11:55:24.208816 best DQS0 dly(2T, 0.5T) = (0, 11)
3104 11:55:24.211656 best DQS1 dly(2T, 0.5T) = (0, 12)
3105 11:55:24.215142 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3106 11:55:24.218818 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3107 11:55:24.221826 best DQS0 dly(2T, 0.5T) = (0, 11)
3108 11:55:24.225495 best DQS1 dly(2T, 0.5T) = (0, 12)
3109 11:55:24.228824 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3110 11:55:24.229265 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3111 11:55:24.231837 Pre-setting of DQS Precalculation
3112 11:55:24.238604 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3113 11:55:24.239131 ==
3114 11:55:24.241977 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 11:55:24.245537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 11:55:24.246100 ==
3117 11:55:24.252051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3118 11:55:24.258615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3119 11:55:24.265931 [CA 0] Center 38 (8~68) winsize 61
3120 11:55:24.269565 [CA 1] Center 37 (7~68) winsize 62
3121 11:55:24.272248 [CA 2] Center 35 (6~65) winsize 60
3122 11:55:24.275439 [CA 3] Center 34 (4~64) winsize 61
3123 11:55:24.278747 [CA 4] Center 34 (4~65) winsize 62
3124 11:55:24.282857 [CA 5] Center 33 (3~63) winsize 61
3125 11:55:24.283425
3126 11:55:24.285879 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3127 11:55:24.286485
3128 11:55:24.288317 [CATrainingPosCal] consider 1 rank data
3129 11:55:24.291926 u2DelayCellTimex100 = 270/100 ps
3130 11:55:24.295304 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3131 11:55:24.301856 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3132 11:55:24.305414 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3133 11:55:24.308671 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3134 11:55:24.312105 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3135 11:55:24.314956 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3136 11:55:24.315420
3137 11:55:24.318326 CA PerBit enable=1, Macro0, CA PI delay=33
3138 11:55:24.318793
3139 11:55:24.321606 [CBTSetCACLKResult] CA Dly = 33
3140 11:55:24.325112 CS Dly: 5 (0~36)
3141 11:55:24.325663 ==
3142 11:55:24.328396 Dram Type= 6, Freq= 0, CH_1, rank 1
3143 11:55:24.331367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3144 11:55:24.331834 ==
3145 11:55:24.338236 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3146 11:55:24.341791 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3147 11:55:24.351190 [CA 0] Center 37 (7~68) winsize 62
3148 11:55:24.354713 [CA 1] Center 38 (8~68) winsize 61
3149 11:55:24.357662 [CA 2] Center 35 (5~65) winsize 61
3150 11:55:24.361789 [CA 3] Center 33 (3~63) winsize 61
3151 11:55:24.364698 [CA 4] Center 34 (4~64) winsize 61
3152 11:55:24.368004 [CA 5] Center 33 (3~63) winsize 61
3153 11:55:24.368512
3154 11:55:24.371161 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3155 11:55:24.371719
3156 11:55:24.374913 [CATrainingPosCal] consider 2 rank data
3157 11:55:24.377900 u2DelayCellTimex100 = 270/100 ps
3158 11:55:24.381254 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3159 11:55:24.384656 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3160 11:55:24.391329 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3161 11:55:24.394200 CA3 delay=33 (4~63),Diff = 0 PI (0 cell)
3162 11:55:24.398106 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3163 11:55:24.401203 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3164 11:55:24.401623
3165 11:55:24.404316 CA PerBit enable=1, Macro0, CA PI delay=33
3166 11:55:24.404825
3167 11:55:24.407945 [CBTSetCACLKResult] CA Dly = 33
3168 11:55:24.408455 CS Dly: 6 (0~39)
3169 11:55:24.408790
3170 11:55:24.410908 ----->DramcWriteLeveling(PI) begin...
3171 11:55:24.414776 ==
3172 11:55:24.417226 Dram Type= 6, Freq= 0, CH_1, rank 0
3173 11:55:24.420831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 11:55:24.421256 ==
3175 11:55:24.423844 Write leveling (Byte 0): 24 => 24
3176 11:55:24.427414 Write leveling (Byte 1): 28 => 28
3177 11:55:24.430885 DramcWriteLeveling(PI) end<-----
3178 11:55:24.431308
3179 11:55:24.431639 ==
3180 11:55:24.433873 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 11:55:24.437400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 11:55:24.437827 ==
3183 11:55:24.440818 [Gating] SW mode calibration
3184 11:55:24.447356 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3185 11:55:24.453768 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3186 11:55:24.457517 0 15 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
3187 11:55:24.461644 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:55:24.467055 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:55:24.470031 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 11:55:24.473899 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 11:55:24.480213 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 11:55:24.483886 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3193 11:55:24.487120 0 15 28 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (1 0)
3194 11:55:24.494744 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:55:24.496678 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:55:24.500303 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:55:24.506972 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 11:55:24.510156 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 11:55:24.513357 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 11:55:24.520112 1 0 24 | B1->B0 | 2626 2d2d | 0 1 | (0 0) (0 0)
3201 11:55:24.523237 1 0 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
3202 11:55:24.526555 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:55:24.529954 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:55:24.537621 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:55:24.540509 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:55:24.543601 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 11:55:24.550041 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 11:55:24.553761 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3209 11:55:24.556680 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3210 11:55:24.563366 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3211 11:55:24.566594 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:55:24.569733 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:55:24.577086 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:55:24.579856 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:55:24.583570 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:55:24.590021 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:55:24.593564 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:55:24.597066 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:55:24.603479 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:55:24.606999 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:55:24.610514 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 11:55:24.616440 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 11:55:24.619492 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 11:55:24.623534 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3225 11:55:24.629437 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3226 11:55:24.632881 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 11:55:24.635799 Total UI for P1: 0, mck2ui 16
3228 11:55:24.640420 best dqsien dly found for B0: ( 1, 3, 26)
3229 11:55:24.643064 Total UI for P1: 0, mck2ui 16
3230 11:55:24.646303 best dqsien dly found for B1: ( 1, 3, 26)
3231 11:55:24.649309 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3232 11:55:24.653132 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3233 11:55:24.653687
3234 11:55:24.656348 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3235 11:55:24.659390 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3236 11:55:24.662525 [Gating] SW calibration Done
3237 11:55:24.662953 ==
3238 11:55:24.666044 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:55:24.669368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:55:24.672645 ==
3241 11:55:24.673194 RX Vref Scan: 0
3242 11:55:24.673537
3243 11:55:24.676328 RX Vref 0 -> 0, step: 1
3244 11:55:24.676851
3245 11:55:24.679404 RX Delay -40 -> 252, step: 8
3246 11:55:24.682434 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3247 11:55:24.686234 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3248 11:55:24.689432 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3249 11:55:24.693235 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3250 11:55:24.699303 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3251 11:55:24.703362 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3252 11:55:24.706132 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3253 11:55:24.709498 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3254 11:55:24.712324 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3255 11:55:24.718785 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3256 11:55:24.722027 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3257 11:55:24.725617 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3258 11:55:24.729041 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3259 11:55:24.732666 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3260 11:55:24.738721 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3261 11:55:24.742144 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3262 11:55:24.742765 ==
3263 11:55:24.745503 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:55:24.748764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:55:24.749280 ==
3266 11:55:24.752003 DQS Delay:
3267 11:55:24.752423 DQS0 = 0, DQS1 = 0
3268 11:55:24.752757 DQM Delay:
3269 11:55:24.755720 DQM0 = 115, DQM1 = 113
3270 11:55:24.756141 DQ Delay:
3271 11:55:24.758584 DQ0 =119, DQ1 =111, DQ2 =107, DQ3 =115
3272 11:55:24.762237 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3273 11:55:24.765698 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3274 11:55:24.772568 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3275 11:55:24.773093
3276 11:55:24.773465
3277 11:55:24.773777 ==
3278 11:55:24.775204 Dram Type= 6, Freq= 0, CH_1, rank 0
3279 11:55:24.778936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3280 11:55:24.779457 ==
3281 11:55:24.779795
3282 11:55:24.780102
3283 11:55:24.782174 TX Vref Scan disable
3284 11:55:24.782726 == TX Byte 0 ==
3285 11:55:24.789220 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3286 11:55:24.792401 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3287 11:55:24.792829 == TX Byte 1 ==
3288 11:55:24.798784 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3289 11:55:24.802040 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3290 11:55:24.802605 ==
3291 11:55:24.805380 Dram Type= 6, Freq= 0, CH_1, rank 0
3292 11:55:24.809048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3293 11:55:24.809639 ==
3294 11:55:24.821792 TX Vref=22, minBit 3, minWin=24, winSum=410
3295 11:55:24.824865 TX Vref=24, minBit 3, minWin=24, winSum=416
3296 11:55:24.828263 TX Vref=26, minBit 3, minWin=25, winSum=425
3297 11:55:24.832162 TX Vref=28, minBit 9, minWin=25, winSum=427
3298 11:55:24.834771 TX Vref=30, minBit 9, minWin=25, winSum=426
3299 11:55:24.839471 TX Vref=32, minBit 9, minWin=25, winSum=429
3300 11:55:24.845300 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 32
3301 11:55:24.845858
3302 11:55:24.848863 Final TX Range 1 Vref 32
3303 11:55:24.849354
3304 11:55:24.849751 ==
3305 11:55:24.851696 Dram Type= 6, Freq= 0, CH_1, rank 0
3306 11:55:24.855085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3307 11:55:24.855604 ==
3308 11:55:24.855942
3309 11:55:24.858948
3310 11:55:24.859458 TX Vref Scan disable
3311 11:55:24.862153 == TX Byte 0 ==
3312 11:55:24.864859 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3313 11:55:24.868426 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3314 11:55:24.872185 == TX Byte 1 ==
3315 11:55:24.875084 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3316 11:55:24.878761 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3317 11:55:24.879274
3318 11:55:24.881644 [DATLAT]
3319 11:55:24.882177 Freq=1200, CH1 RK0
3320 11:55:24.882751
3321 11:55:24.884793 DATLAT Default: 0xd
3322 11:55:24.885304 0, 0xFFFF, sum = 0
3323 11:55:24.888337 1, 0xFFFF, sum = 0
3324 11:55:24.888856 2, 0xFFFF, sum = 0
3325 11:55:24.891666 3, 0xFFFF, sum = 0
3326 11:55:24.892208 4, 0xFFFF, sum = 0
3327 11:55:24.895492 5, 0xFFFF, sum = 0
3328 11:55:24.896006 6, 0xFFFF, sum = 0
3329 11:55:24.898619 7, 0xFFFF, sum = 0
3330 11:55:24.899208 8, 0xFFFF, sum = 0
3331 11:55:24.901729 9, 0xFFFF, sum = 0
3332 11:55:24.905018 10, 0xFFFF, sum = 0
3333 11:55:24.905539 11, 0xFFFF, sum = 0
3334 11:55:24.908298 12, 0x0, sum = 1
3335 11:55:24.908820 13, 0x0, sum = 2
3336 11:55:24.909161 14, 0x0, sum = 3
3337 11:55:24.911516 15, 0x0, sum = 4
3338 11:55:24.912040 best_step = 13
3339 11:55:24.912379
3340 11:55:24.914833 ==
3341 11:55:24.915254 Dram Type= 6, Freq= 0, CH_1, rank 0
3342 11:55:24.921352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3343 11:55:24.921877 ==
3344 11:55:24.922222 RX Vref Scan: 1
3345 11:55:24.922591
3346 11:55:24.925103 Set Vref Range= 32 -> 127
3347 11:55:24.925609
3348 11:55:24.928821 RX Vref 32 -> 127, step: 1
3349 11:55:24.929340
3350 11:55:24.931141 RX Delay -13 -> 252, step: 4
3351 11:55:24.931562
3352 11:55:24.934559 Set Vref, RX VrefLevel [Byte0]: 32
3353 11:55:24.938117 [Byte1]: 32
3354 11:55:24.938704
3355 11:55:24.941113 Set Vref, RX VrefLevel [Byte0]: 33
3356 11:55:24.945050 [Byte1]: 33
3357 11:55:24.945474
3358 11:55:24.947760 Set Vref, RX VrefLevel [Byte0]: 34
3359 11:55:24.951225 [Byte1]: 34
3360 11:55:24.955438
3361 11:55:24.955853 Set Vref, RX VrefLevel [Byte0]: 35
3362 11:55:24.958930 [Byte1]: 35
3363 11:55:24.963192
3364 11:55:24.963762 Set Vref, RX VrefLevel [Byte0]: 36
3365 11:55:24.966742 [Byte1]: 36
3366 11:55:24.971018
3367 11:55:24.971434 Set Vref, RX VrefLevel [Byte0]: 37
3368 11:55:24.974720 [Byte1]: 37
3369 11:55:24.979491
3370 11:55:24.980007 Set Vref, RX VrefLevel [Byte0]: 38
3371 11:55:24.982682 [Byte1]: 38
3372 11:55:24.986870
3373 11:55:24.987303 Set Vref, RX VrefLevel [Byte0]: 39
3374 11:55:24.990452 [Byte1]: 39
3375 11:55:24.994850
3376 11:55:24.995371 Set Vref, RX VrefLevel [Byte0]: 40
3377 11:55:24.998793 [Byte1]: 40
3378 11:55:25.002660
3379 11:55:25.003201 Set Vref, RX VrefLevel [Byte0]: 41
3380 11:55:25.006156 [Byte1]: 41
3381 11:55:25.011066
3382 11:55:25.011610 Set Vref, RX VrefLevel [Byte0]: 42
3383 11:55:25.013977 [Byte1]: 42
3384 11:55:25.018449
3385 11:55:25.018872 Set Vref, RX VrefLevel [Byte0]: 43
3386 11:55:25.022331 [Byte1]: 43
3387 11:55:25.026623
3388 11:55:25.027040 Set Vref, RX VrefLevel [Byte0]: 44
3389 11:55:25.030082 [Byte1]: 44
3390 11:55:25.034389
3391 11:55:25.034891 Set Vref, RX VrefLevel [Byte0]: 45
3392 11:55:25.037740 [Byte1]: 45
3393 11:55:25.042411
3394 11:55:25.042957 Set Vref, RX VrefLevel [Byte0]: 46
3395 11:55:25.049036 [Byte1]: 46
3396 11:55:25.049472
3397 11:55:25.052550 Set Vref, RX VrefLevel [Byte0]: 47
3398 11:55:25.055137 [Byte1]: 47
3399 11:55:25.055559
3400 11:55:25.059192 Set Vref, RX VrefLevel [Byte0]: 48
3401 11:55:25.062076 [Byte1]: 48
3402 11:55:25.066047
3403 11:55:25.066647 Set Vref, RX VrefLevel [Byte0]: 49
3404 11:55:25.069298 [Byte1]: 49
3405 11:55:25.074660
3406 11:55:25.075212 Set Vref, RX VrefLevel [Byte0]: 50
3407 11:55:25.077194 [Byte1]: 50
3408 11:55:25.081707
3409 11:55:25.082294 Set Vref, RX VrefLevel [Byte0]: 51
3410 11:55:25.085527 [Byte1]: 51
3411 11:55:25.089599
3412 11:55:25.090235 Set Vref, RX VrefLevel [Byte0]: 52
3413 11:55:25.092746 [Byte1]: 52
3414 11:55:25.097571
3415 11:55:25.098130 Set Vref, RX VrefLevel [Byte0]: 53
3416 11:55:25.101081 [Byte1]: 53
3417 11:55:25.105529
3418 11:55:25.106080 Set Vref, RX VrefLevel [Byte0]: 54
3419 11:55:25.108965 [Byte1]: 54
3420 11:55:25.113308
3421 11:55:25.113863 Set Vref, RX VrefLevel [Byte0]: 55
3422 11:55:25.116220 [Byte1]: 55
3423 11:55:25.121169
3424 11:55:25.121718 Set Vref, RX VrefLevel [Byte0]: 56
3425 11:55:25.124258 [Byte1]: 56
3426 11:55:25.129488
3427 11:55:25.130062 Set Vref, RX VrefLevel [Byte0]: 57
3428 11:55:25.132277 [Byte1]: 57
3429 11:55:25.137219
3430 11:55:25.137770 Set Vref, RX VrefLevel [Byte0]: 58
3431 11:55:25.140047 [Byte1]: 58
3432 11:55:25.144868
3433 11:55:25.145430 Set Vref, RX VrefLevel [Byte0]: 59
3434 11:55:25.147915 [Byte1]: 59
3435 11:55:25.152870
3436 11:55:25.153289 Set Vref, RX VrefLevel [Byte0]: 60
3437 11:55:25.157295 [Byte1]: 60
3438 11:55:25.160597
3439 11:55:25.161125 Set Vref, RX VrefLevel [Byte0]: 61
3440 11:55:25.163801 [Byte1]: 61
3441 11:55:25.168288
3442 11:55:25.168800 Set Vref, RX VrefLevel [Byte0]: 62
3443 11:55:25.171837 [Byte1]: 62
3444 11:55:25.176264
3445 11:55:25.176819 Set Vref, RX VrefLevel [Byte0]: 63
3446 11:55:25.179897 [Byte1]: 63
3447 11:55:25.183750
3448 11:55:25.184214 Set Vref, RX VrefLevel [Byte0]: 64
3449 11:55:25.187675 [Byte1]: 64
3450 11:55:25.192090
3451 11:55:25.192637 Set Vref, RX VrefLevel [Byte0]: 65
3452 11:55:25.195408 [Byte1]: 65
3453 11:55:25.200050
3454 11:55:25.200603 Final RX Vref Byte 0 = 51 to rank0
3455 11:55:25.203136 Final RX Vref Byte 1 = 51 to rank0
3456 11:55:25.207348 Final RX Vref Byte 0 = 51 to rank1
3457 11:55:25.210365 Final RX Vref Byte 1 = 51 to rank1==
3458 11:55:25.213135 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 11:55:25.219899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 11:55:25.220368 ==
3461 11:55:25.220734 DQS Delay:
3462 11:55:25.221080 DQS0 = 0, DQS1 = 0
3463 11:55:25.222789 DQM Delay:
3464 11:55:25.223251 DQM0 = 114, DQM1 = 112
3465 11:55:25.226314 DQ Delay:
3466 11:55:25.229821 DQ0 =120, DQ1 =112, DQ2 =104, DQ3 =114
3467 11:55:25.233826 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3468 11:55:25.236279 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3469 11:55:25.239745 DQ12 =122, DQ13 =120, DQ14 =118, DQ15 =122
3470 11:55:25.240301
3471 11:55:25.240662
3472 11:55:25.249154 [DQSOSCAuto] RK0, (LSB)MR18= 0xf704, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3473 11:55:25.249704 CH1 RK0: MR19=304, MR18=F704
3474 11:55:25.255920 CH1_RK0: MR19=0x304, MR18=0xF704, DQSOSC=408, MR23=63, INC=39, DEC=26
3475 11:55:25.256483
3476 11:55:25.259043 ----->DramcWriteLeveling(PI) begin...
3477 11:55:25.259602 ==
3478 11:55:25.262563 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 11:55:25.269584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 11:55:25.270141 ==
3481 11:55:25.272448 Write leveling (Byte 0): 26 => 26
3482 11:55:25.275821 Write leveling (Byte 1): 27 => 27
3483 11:55:25.276375 DramcWriteLeveling(PI) end<-----
3484 11:55:25.279125
3485 11:55:25.279593 ==
3486 11:55:25.282537 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:55:25.285805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:55:25.286419 ==
3489 11:55:25.289149 [Gating] SW mode calibration
3490 11:55:25.295678 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 11:55:25.298713 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 11:55:25.305744 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3493 11:55:25.308937 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 11:55:25.312415 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 11:55:25.319140 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 11:55:25.322032 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 11:55:25.325438 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 11:55:25.331943 0 15 24 | B1->B0 | 3434 2323 | 1 1 | (1 1) (1 0)
3499 11:55:25.335482 0 15 28 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
3500 11:55:25.338526 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 11:55:25.345622 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 11:55:25.348288 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 11:55:25.352137 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 11:55:25.359239 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:55:25.362724 1 0 20 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
3506 11:55:25.365009 1 0 24 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
3507 11:55:25.371532 1 0 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
3508 11:55:25.375003 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 11:55:25.378565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 11:55:25.385237 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:55:25.388192 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 11:55:25.391934 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:55:25.398324 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:55:25.401370 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3515 11:55:25.405212 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 11:55:25.411112 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 11:55:25.414606 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:55:25.417552 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:55:25.424122 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:55:25.428033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:55:25.430956 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:55:25.437908 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:55:25.441052 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:55:25.444417 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:55:25.450703 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:55:25.454171 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:55:25.457300 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:55:25.463707 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:55:25.467229 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3530 11:55:25.470426 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3531 11:55:25.477120 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3532 11:55:25.480105 Total UI for P1: 0, mck2ui 16
3533 11:55:25.483814 best dqsien dly found for B0: ( 1, 3, 22)
3534 11:55:25.487944 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 11:55:25.490111 Total UI for P1: 0, mck2ui 16
3536 11:55:25.493812 best dqsien dly found for B1: ( 1, 3, 28)
3537 11:55:25.496535 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3538 11:55:25.500275 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3539 11:55:25.500739
3540 11:55:25.503539 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3541 11:55:25.506530 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3542 11:55:25.509971 [Gating] SW calibration Done
3543 11:55:25.510518 ==
3544 11:55:25.512810 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 11:55:25.520054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 11:55:25.520639 ==
3547 11:55:25.521037 RX Vref Scan: 0
3548 11:55:25.521456
3549 11:55:25.522986 RX Vref 0 -> 0, step: 1
3550 11:55:25.523609
3551 11:55:25.525944 RX Delay -40 -> 252, step: 8
3552 11:55:25.529183 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3553 11:55:25.532763 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3554 11:55:25.536383 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3555 11:55:25.543348 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3556 11:55:25.546545 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3557 11:55:25.549200 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3558 11:55:25.552960 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3559 11:55:25.556418 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3560 11:55:25.562477 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3561 11:55:25.565949 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3562 11:55:25.568992 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3563 11:55:25.573124 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3564 11:55:25.575521 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3565 11:55:25.582356 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3566 11:55:25.585517 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3567 11:55:25.588908 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3568 11:55:25.589429 ==
3569 11:55:25.592691 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 11:55:25.595622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 11:55:25.598663 ==
3572 11:55:25.599135 DQS Delay:
3573 11:55:25.599466 DQS0 = 0, DQS1 = 0
3574 11:55:25.602635 DQM Delay:
3575 11:55:25.603192 DQM0 = 114, DQM1 = 111
3576 11:55:25.605713 DQ Delay:
3577 11:55:25.609196 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3578 11:55:25.612821 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =111
3579 11:55:25.615909 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3580 11:55:25.618587 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3581 11:55:25.619110
3582 11:55:25.619542
3583 11:55:25.619894 ==
3584 11:55:25.622306 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:55:25.625329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:55:25.625879 ==
3587 11:55:25.626333
3588 11:55:25.626719
3589 11:55:25.628933 TX Vref Scan disable
3590 11:55:25.631744 == TX Byte 0 ==
3591 11:55:25.635556 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 11:55:25.639033 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 11:55:25.642088 == TX Byte 1 ==
3594 11:55:25.645192 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3595 11:55:25.648490 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3596 11:55:25.648951 ==
3597 11:55:25.651648 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 11:55:25.658406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 11:55:25.658968 ==
3600 11:55:25.669083 TX Vref=22, minBit 9, minWin=24, winSum=417
3601 11:55:25.672061 TX Vref=24, minBit 9, minWin=25, winSum=423
3602 11:55:25.675188 TX Vref=26, minBit 9, minWin=24, winSum=424
3603 11:55:25.679011 TX Vref=28, minBit 9, minWin=25, winSum=425
3604 11:55:25.681937 TX Vref=30, minBit 9, minWin=25, winSum=431
3605 11:55:25.688710 TX Vref=32, minBit 9, minWin=24, winSum=429
3606 11:55:25.691599 [TxChooseVref] Worse bit 9, Min win 25, Win sum 431, Final Vref 30
3607 11:55:25.692060
3608 11:55:25.695666 Final TX Range 1 Vref 30
3609 11:55:25.696330
3610 11:55:25.696719 ==
3611 11:55:25.699301 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:55:25.701705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:55:25.705421 ==
3614 11:55:25.705986
3615 11:55:25.706404
3616 11:55:25.706752 TX Vref Scan disable
3617 11:55:25.708118 == TX Byte 0 ==
3618 11:55:25.712256 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 11:55:25.718797 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 11:55:25.719378 == TX Byte 1 ==
3621 11:55:25.721455 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3622 11:55:25.728671 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3623 11:55:25.729280
3624 11:55:25.729770 [DATLAT]
3625 11:55:25.730228 Freq=1200, CH1 RK1
3626 11:55:25.730719
3627 11:55:25.731515 DATLAT Default: 0xd
3628 11:55:25.734957 0, 0xFFFF, sum = 0
3629 11:55:25.735439 1, 0xFFFF, sum = 0
3630 11:55:25.738429 2, 0xFFFF, sum = 0
3631 11:55:25.739009 3, 0xFFFF, sum = 0
3632 11:55:25.741559 4, 0xFFFF, sum = 0
3633 11:55:25.742145 5, 0xFFFF, sum = 0
3634 11:55:25.744576 6, 0xFFFF, sum = 0
3635 11:55:25.745167 7, 0xFFFF, sum = 0
3636 11:55:25.748114 8, 0xFFFF, sum = 0
3637 11:55:25.748613 9, 0xFFFF, sum = 0
3638 11:55:25.751326 10, 0xFFFF, sum = 0
3639 11:55:25.751812 11, 0xFFFF, sum = 0
3640 11:55:25.754972 12, 0x0, sum = 1
3641 11:55:25.755555 13, 0x0, sum = 2
3642 11:55:25.758420 14, 0x0, sum = 3
3643 11:55:25.759049 15, 0x0, sum = 4
3644 11:55:25.761032 best_step = 13
3645 11:55:25.761609
3646 11:55:25.762095 ==
3647 11:55:25.764408 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 11:55:25.767890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 11:55:25.768430 ==
3650 11:55:25.770884 RX Vref Scan: 0
3651 11:55:25.771414
3652 11:55:25.771859 RX Vref 0 -> 0, step: 1
3653 11:55:25.772275
3654 11:55:25.773954 RX Delay -13 -> 252, step: 4
3655 11:55:25.780594 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3656 11:55:25.784091 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3657 11:55:25.787369 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3658 11:55:25.790732 iDelay=195, Bit 3, Center 112 (43 ~ 182) 140
3659 11:55:25.794086 iDelay=195, Bit 4, Center 114 (47 ~ 182) 136
3660 11:55:25.800804 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3661 11:55:25.804083 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3662 11:55:25.807165 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3663 11:55:25.810081 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3664 11:55:25.816989 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3665 11:55:25.820099 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3666 11:55:25.823568 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3667 11:55:25.827040 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3668 11:55:25.830312 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3669 11:55:25.836425 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3670 11:55:25.840396 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3671 11:55:25.840931 ==
3672 11:55:25.843822 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 11:55:25.846629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 11:55:25.847171 ==
3675 11:55:25.850633 DQS Delay:
3676 11:55:25.851064 DQS0 = 0, DQS1 = 0
3677 11:55:25.851509 DQM Delay:
3678 11:55:25.853643 DQM0 = 115, DQM1 = 111
3679 11:55:25.854175 DQ Delay:
3680 11:55:25.856395 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3681 11:55:25.859851 DQ4 =114, DQ5 =124, DQ6 =122, DQ7 =112
3682 11:55:25.866205 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3683 11:55:25.869637 DQ12 =118, DQ13 =118, DQ14 =116, DQ15 =120
3684 11:55:25.870181
3685 11:55:25.870673
3686 11:55:25.876202 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3687 11:55:25.879644 CH1 RK1: MR19=304, MR18=F90B
3688 11:55:25.886340 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3689 11:55:25.889124 [RxdqsGatingPostProcess] freq 1200
3690 11:55:25.895982 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 11:55:25.896518 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 11:55:25.899346 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 11:55:25.902689 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 11:55:25.905943 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 11:55:25.908896 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 11:55:25.912206 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 11:55:25.915868 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 11:55:25.919231 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 11:55:25.922342 Pre-setting of DQS Precalculation
3700 11:55:25.929123 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 11:55:25.935379 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 11:55:25.942198 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 11:55:25.942792
3704 11:55:25.943246
3705 11:55:25.945870 [Calibration Summary] 2400 Mbps
3706 11:55:25.946451 CH 0, Rank 0
3707 11:55:25.949059 SW Impedance : PASS
3708 11:55:25.951742 DUTY Scan : NO K
3709 11:55:25.952176 ZQ Calibration : PASS
3710 11:55:25.955893 Jitter Meter : NO K
3711 11:55:25.958580 CBT Training : PASS
3712 11:55:25.959015 Write leveling : PASS
3713 11:55:25.962787 RX DQS gating : PASS
3714 11:55:25.965443 RX DQ/DQS(RDDQC) : PASS
3715 11:55:25.965978 TX DQ/DQS : PASS
3716 11:55:25.968833 RX DATLAT : PASS
3717 11:55:25.972085 RX DQ/DQS(Engine): PASS
3718 11:55:25.972621 TX OE : NO K
3719 11:55:25.973076 All Pass.
3720 11:55:25.975940
3721 11:55:25.976368 CH 0, Rank 1
3722 11:55:25.978754 SW Impedance : PASS
3723 11:55:25.979196 DUTY Scan : NO K
3724 11:55:25.982155 ZQ Calibration : PASS
3725 11:55:25.984957 Jitter Meter : NO K
3726 11:55:25.985493 CBT Training : PASS
3727 11:55:25.988968 Write leveling : PASS
3728 11:55:25.989501 RX DQS gating : PASS
3729 11:55:25.992038 RX DQ/DQS(RDDQC) : PASS
3730 11:55:25.994792 TX DQ/DQS : PASS
3731 11:55:25.995323 RX DATLAT : PASS
3732 11:55:25.997712 RX DQ/DQS(Engine): PASS
3733 11:55:26.001413 TX OE : NO K
3734 11:55:26.001986 All Pass.
3735 11:55:26.002515
3736 11:55:26.002940 CH 1, Rank 0
3737 11:55:26.004609 SW Impedance : PASS
3738 11:55:26.008023 DUTY Scan : NO K
3739 11:55:26.008561 ZQ Calibration : PASS
3740 11:55:26.011515 Jitter Meter : NO K
3741 11:55:26.014415 CBT Training : PASS
3742 11:55:26.014949 Write leveling : PASS
3743 11:55:26.017489 RX DQS gating : PASS
3744 11:55:26.020951 RX DQ/DQS(RDDQC) : PASS
3745 11:55:26.021384 TX DQ/DQS : PASS
3746 11:55:26.024063 RX DATLAT : PASS
3747 11:55:26.027210 RX DQ/DQS(Engine): PASS
3748 11:55:26.027645 TX OE : NO K
3749 11:55:26.030874 All Pass.
3750 11:55:26.031403
3751 11:55:26.031847 CH 1, Rank 1
3752 11:55:26.034064 SW Impedance : PASS
3753 11:55:26.034629 DUTY Scan : NO K
3754 11:55:26.038204 ZQ Calibration : PASS
3755 11:55:26.040711 Jitter Meter : NO K
3756 11:55:26.041247 CBT Training : PASS
3757 11:55:26.043956 Write leveling : PASS
3758 11:55:26.047442 RX DQS gating : PASS
3759 11:55:26.047875 RX DQ/DQS(RDDQC) : PASS
3760 11:55:26.051137 TX DQ/DQS : PASS
3761 11:55:26.053962 RX DATLAT : PASS
3762 11:55:26.054418 RX DQ/DQS(Engine): PASS
3763 11:55:26.057650 TX OE : NO K
3764 11:55:26.058187 All Pass.
3765 11:55:26.058682
3766 11:55:26.060611 DramC Write-DBI off
3767 11:55:26.064366 PER_BANK_REFRESH: Hybrid Mode
3768 11:55:26.064906 TX_TRACKING: ON
3769 11:55:26.073676 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 11:55:26.076875 [FAST_K] Save calibration result to emmc
3771 11:55:26.080714 dramc_set_vcore_voltage set vcore to 650000
3772 11:55:26.083957 Read voltage for 600, 5
3773 11:55:26.084492 Vio18 = 0
3774 11:55:26.084943 Vcore = 650000
3775 11:55:26.086849 Vdram = 0
3776 11:55:26.087280 Vddq = 0
3777 11:55:26.087725 Vmddr = 0
3778 11:55:26.093630 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 11:55:26.096618 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 11:55:26.100188 MEM_TYPE=3, freq_sel=19
3781 11:55:26.103438 sv_algorithm_assistance_LP4_1600
3782 11:55:26.106800 ============ PULL DRAM RESETB DOWN ============
3783 11:55:26.110417 ========== PULL DRAM RESETB DOWN end =========
3784 11:55:26.117140 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 11:55:26.120102 ===================================
3786 11:55:26.123248 LPDDR4 DRAM CONFIGURATION
3787 11:55:26.126925 ===================================
3788 11:55:26.127451 EX_ROW_EN[0] = 0x0
3789 11:55:26.130278 EX_ROW_EN[1] = 0x0
3790 11:55:26.130817 LP4Y_EN = 0x0
3791 11:55:26.133204 WORK_FSP = 0x0
3792 11:55:26.133737 WL = 0x2
3793 11:55:26.136583 RL = 0x2
3794 11:55:26.137116 BL = 0x2
3795 11:55:26.140265 RPST = 0x0
3796 11:55:26.140696 RD_PRE = 0x0
3797 11:55:26.142964 WR_PRE = 0x1
3798 11:55:26.143397 WR_PST = 0x0
3799 11:55:26.146306 DBI_WR = 0x0
3800 11:55:26.149981 DBI_RD = 0x0
3801 11:55:26.150564 OTF = 0x1
3802 11:55:26.153063 ===================================
3803 11:55:26.156512 ===================================
3804 11:55:26.156954 ANA top config
3805 11:55:26.159603 ===================================
3806 11:55:26.162981 DLL_ASYNC_EN = 0
3807 11:55:26.166246 ALL_SLAVE_EN = 1
3808 11:55:26.169404 NEW_RANK_MODE = 1
3809 11:55:26.173085 DLL_IDLE_MODE = 1
3810 11:55:26.173621 LP45_APHY_COMB_EN = 1
3811 11:55:26.176468 TX_ODT_DIS = 1
3812 11:55:26.179534 NEW_8X_MODE = 1
3813 11:55:26.183028 ===================================
3814 11:55:26.185996 ===================================
3815 11:55:26.189719 data_rate = 1200
3816 11:55:26.192615 CKR = 1
3817 11:55:26.193148 DQ_P2S_RATIO = 8
3818 11:55:26.196592 ===================================
3819 11:55:26.198905 CA_P2S_RATIO = 8
3820 11:55:26.202812 DQ_CA_OPEN = 0
3821 11:55:26.206027 DQ_SEMI_OPEN = 0
3822 11:55:26.209099 CA_SEMI_OPEN = 0
3823 11:55:26.212289 CA_FULL_RATE = 0
3824 11:55:26.212820 DQ_CKDIV4_EN = 1
3825 11:55:26.215867 CA_CKDIV4_EN = 1
3826 11:55:26.218857 CA_PREDIV_EN = 0
3827 11:55:26.221927 PH8_DLY = 0
3828 11:55:26.225254 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 11:55:26.229028 DQ_AAMCK_DIV = 4
3830 11:55:26.232376 CA_AAMCK_DIV = 4
3831 11:55:26.232930 CA_ADMCK_DIV = 4
3832 11:55:26.235862 DQ_TRACK_CA_EN = 0
3833 11:55:26.238651 CA_PICK = 600
3834 11:55:26.242103 CA_MCKIO = 600
3835 11:55:26.245141 MCKIO_SEMI = 0
3836 11:55:26.248566 PLL_FREQ = 2288
3837 11:55:26.251639 DQ_UI_PI_RATIO = 32
3838 11:55:26.252067 CA_UI_PI_RATIO = 0
3839 11:55:26.255061 ===================================
3840 11:55:26.258504 ===================================
3841 11:55:26.261700 memory_type:LPDDR4
3842 11:55:26.264954 GP_NUM : 10
3843 11:55:26.265521 SRAM_EN : 1
3844 11:55:26.268545 MD32_EN : 0
3845 11:55:26.271594 ===================================
3846 11:55:26.275347 [ANA_INIT] >>>>>>>>>>>>>>
3847 11:55:26.278502 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 11:55:26.281649 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 11:55:26.285176 ===================================
3850 11:55:26.285741 data_rate = 1200,PCW = 0X5800
3851 11:55:26.288372 ===================================
3852 11:55:26.291682 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 11:55:26.297730 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 11:55:26.304483 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 11:55:26.308006 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 11:55:26.311558 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 11:55:26.314664 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 11:55:26.317613 [ANA_INIT] flow start
3859 11:55:26.320975 [ANA_INIT] PLL >>>>>>>>
3860 11:55:26.321440 [ANA_INIT] PLL <<<<<<<<
3861 11:55:26.324231 [ANA_INIT] MIDPI >>>>>>>>
3862 11:55:26.327343 [ANA_INIT] MIDPI <<<<<<<<
3863 11:55:26.327811 [ANA_INIT] DLL >>>>>>>>
3864 11:55:26.330803 [ANA_INIT] flow end
3865 11:55:26.334343 ============ LP4 DIFF to SE enter ============
3866 11:55:26.341102 ============ LP4 DIFF to SE exit ============
3867 11:55:26.341638 [ANA_INIT] <<<<<<<<<<<<<
3868 11:55:26.344386 [Flow] Enable top DCM control >>>>>
3869 11:55:26.347511 [Flow] Enable top DCM control <<<<<
3870 11:55:26.350935 Enable DLL master slave shuffle
3871 11:55:26.357160 ==============================================================
3872 11:55:26.357730 Gating Mode config
3873 11:55:26.363865 ==============================================================
3874 11:55:26.367098 Config description:
3875 11:55:26.377188 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 11:55:26.383774 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 11:55:26.387954 SELPH_MODE 0: By rank 1: By Phase
3878 11:55:26.393774 ==============================================================
3879 11:55:26.397257 GAT_TRACK_EN = 1
3880 11:55:26.397691 RX_GATING_MODE = 2
3881 11:55:26.400443 RX_GATING_TRACK_MODE = 2
3882 11:55:26.403438 SELPH_MODE = 1
3883 11:55:26.406370 PICG_EARLY_EN = 1
3884 11:55:26.410679 VALID_LAT_VALUE = 1
3885 11:55:26.416676 ==============================================================
3886 11:55:26.419605 Enter into Gating configuration >>>>
3887 11:55:26.423082 Exit from Gating configuration <<<<
3888 11:55:26.426268 Enter into DVFS_PRE_config >>>>>
3889 11:55:26.435893 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 11:55:26.439012 Exit from DVFS_PRE_config <<<<<
3891 11:55:26.442310 Enter into PICG configuration >>>>
3892 11:55:26.445893 Exit from PICG configuration <<<<
3893 11:55:26.449258 [RX_INPUT] configuration >>>>>
3894 11:55:26.452665 [RX_INPUT] configuration <<<<<
3895 11:55:26.455811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 11:55:26.462231 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 11:55:26.469436 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 11:55:26.475309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 11:55:26.481925 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 11:55:26.486054 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 11:55:26.492024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 11:55:26.495232 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 11:55:26.498668 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 11:55:26.502026 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 11:55:26.508648 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 11:55:26.512465 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 11:55:26.515323 ===================================
3908 11:55:26.518600 LPDDR4 DRAM CONFIGURATION
3909 11:55:26.521725 ===================================
3910 11:55:26.522165 EX_ROW_EN[0] = 0x0
3911 11:55:26.525194 EX_ROW_EN[1] = 0x0
3912 11:55:26.525492 LP4Y_EN = 0x0
3913 11:55:26.528153 WORK_FSP = 0x0
3914 11:55:26.528415 WL = 0x2
3915 11:55:26.531565 RL = 0x2
3916 11:55:26.534664 BL = 0x2
3917 11:55:26.534845 RPST = 0x0
3918 11:55:26.538434 RD_PRE = 0x0
3919 11:55:26.538585 WR_PRE = 0x1
3920 11:55:26.541326 WR_PST = 0x0
3921 11:55:26.541476 DBI_WR = 0x0
3922 11:55:26.544797 DBI_RD = 0x0
3923 11:55:26.544934 OTF = 0x1
3924 11:55:26.548042 ===================================
3925 11:55:26.551311 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 11:55:26.557675 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 11:55:26.561143 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 11:55:26.564314 ===================================
3929 11:55:26.567205 LPDDR4 DRAM CONFIGURATION
3930 11:55:26.571619 ===================================
3931 11:55:26.571703 EX_ROW_EN[0] = 0x10
3932 11:55:26.574265 EX_ROW_EN[1] = 0x0
3933 11:55:26.574349 LP4Y_EN = 0x0
3934 11:55:26.577708 WORK_FSP = 0x0
3935 11:55:26.581038 WL = 0x2
3936 11:55:26.581456 RL = 0x2
3937 11:55:26.584515 BL = 0x2
3938 11:55:26.584933 RPST = 0x0
3939 11:55:26.587608 RD_PRE = 0x0
3940 11:55:26.588024 WR_PRE = 0x1
3941 11:55:26.591216 WR_PST = 0x0
3942 11:55:26.591631 DBI_WR = 0x0
3943 11:55:26.594446 DBI_RD = 0x0
3944 11:55:26.594863 OTF = 0x1
3945 11:55:26.597492 ===================================
3946 11:55:26.603809 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 11:55:26.608269 nWR fixed to 30
3948 11:55:26.611745 [ModeRegInit_LP4] CH0 RK0
3949 11:55:26.612163 [ModeRegInit_LP4] CH0 RK1
3950 11:55:26.614728 [ModeRegInit_LP4] CH1 RK0
3951 11:55:26.618314 [ModeRegInit_LP4] CH1 RK1
3952 11:55:26.618731 match AC timing 17
3953 11:55:26.624883 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 11:55:26.627898 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 11:55:26.631559 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 11:55:26.638023 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 11:55:26.641146 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 11:55:26.641382 ==
3959 11:55:26.644139 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:55:26.647405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:55:26.647636 ==
3962 11:55:26.654451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 11:55:26.660992 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3964 11:55:26.664693 [CA 0] Center 36 (6~67) winsize 62
3965 11:55:26.667745 [CA 1] Center 36 (6~67) winsize 62
3966 11:55:26.670760 [CA 2] Center 34 (4~65) winsize 62
3967 11:55:26.674359 [CA 3] Center 34 (4~65) winsize 62
3968 11:55:26.677632 [CA 4] Center 33 (3~64) winsize 62
3969 11:55:26.680956 [CA 5] Center 33 (3~64) winsize 62
3970 11:55:26.681617
3971 11:55:26.683928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3972 11:55:26.684355
3973 11:55:26.687474 [CATrainingPosCal] consider 1 rank data
3974 11:55:26.690790 u2DelayCellTimex100 = 270/100 ps
3975 11:55:26.694056 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3976 11:55:26.697298 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3977 11:55:26.701486 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3978 11:55:26.707898 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3979 11:55:26.710460 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3980 11:55:26.713843 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3981 11:55:26.714445
3982 11:55:26.717035 CA PerBit enable=1, Macro0, CA PI delay=33
3983 11:55:26.717513
3984 11:55:26.720339 [CBTSetCACLKResult] CA Dly = 33
3985 11:55:26.720854 CS Dly: 5 (0~36)
3986 11:55:26.721225 ==
3987 11:55:26.723628 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 11:55:26.730732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:55:26.731174 ==
3990 11:55:26.733807 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 11:55:26.740415 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3992 11:55:26.744181 [CA 0] Center 36 (6~67) winsize 62
3993 11:55:26.747104 [CA 1] Center 36 (6~67) winsize 62
3994 11:55:26.750522 [CA 2] Center 34 (4~65) winsize 62
3995 11:55:26.754051 [CA 3] Center 34 (4~65) winsize 62
3996 11:55:26.757272 [CA 4] Center 34 (3~65) winsize 63
3997 11:55:26.760220 [CA 5] Center 33 (3~64) winsize 62
3998 11:55:26.760774
3999 11:55:26.763777 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4000 11:55:26.764356
4001 11:55:26.766870 [CATrainingPosCal] consider 2 rank data
4002 11:55:26.771223 u2DelayCellTimex100 = 270/100 ps
4003 11:55:26.773550 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4004 11:55:26.780067 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4005 11:55:26.783557 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4006 11:55:26.786673 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4007 11:55:26.790221 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4008 11:55:26.793334 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4009 11:55:26.793908
4010 11:55:26.796228 CA PerBit enable=1, Macro0, CA PI delay=33
4011 11:55:26.796683
4012 11:55:26.800107 [CBTSetCACLKResult] CA Dly = 33
4013 11:55:26.803268 CS Dly: 5 (0~37)
4014 11:55:26.803819
4015 11:55:26.806899 ----->DramcWriteLeveling(PI) begin...
4016 11:55:26.807466 ==
4017 11:55:26.810167 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 11:55:26.813071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 11:55:26.813630 ==
4020 11:55:26.816477 Write leveling (Byte 0): 34 => 34
4021 11:55:26.819699 Write leveling (Byte 1): 31 => 31
4022 11:55:26.822856 DramcWriteLeveling(PI) end<-----
4023 11:55:26.823402
4024 11:55:26.823789 ==
4025 11:55:26.826047 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 11:55:26.829340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 11:55:26.829799 ==
4028 11:55:26.833219 [Gating] SW mode calibration
4029 11:55:26.840564 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 11:55:26.845890 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 11:55:26.849612 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 11:55:26.852362 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 11:55:26.859155 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 11:55:26.862600 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)
4035 11:55:26.866159 0 9 16 | B1->B0 | 2e2e 2a2a | 1 1 | (1 1) (1 0)
4036 11:55:26.872780 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:55:26.876254 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:55:26.879227 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:55:26.886654 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:55:26.889063 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:55:26.891937 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:55:26.898878 0 10 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
4043 11:55:26.901924 0 10 16 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
4044 11:55:26.905282 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:55:26.912262 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 11:55:26.915773 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:55:26.918385 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:55:26.924695 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:55:26.929046 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:55:26.931529 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:55:26.938064 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4052 11:55:26.941572 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:55:26.948517 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:55:26.951297 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:55:26.954749 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:55:26.961787 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:55:26.964522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:55:26.967703 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:55:26.974530 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:55:26.978201 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:55:26.981247 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:55:26.987661 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:55:26.991107 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:55:26.993935 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:55:27.001036 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:55:27.004238 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4067 11:55:27.007529 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4068 11:55:27.011257 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 11:55:27.013844 Total UI for P1: 0, mck2ui 16
4070 11:55:27.017201 best dqsien dly found for B0: ( 0, 13, 14)
4071 11:55:27.020455 Total UI for P1: 0, mck2ui 16
4072 11:55:27.024077 best dqsien dly found for B1: ( 0, 13, 18)
4073 11:55:27.030235 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4074 11:55:27.033967 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4075 11:55:27.034643
4076 11:55:27.036707 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 11:55:27.040026 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4078 11:55:27.043267 [Gating] SW calibration Done
4079 11:55:27.043732 ==
4080 11:55:27.046824 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 11:55:27.050304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 11:55:27.050832 ==
4083 11:55:27.053119 RX Vref Scan: 0
4084 11:55:27.053542
4085 11:55:27.053879 RX Vref 0 -> 0, step: 1
4086 11:55:27.054190
4087 11:55:27.056616 RX Delay -230 -> 252, step: 16
4088 11:55:27.063240 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4089 11:55:27.066637 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4090 11:55:27.069727 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4091 11:55:27.073652 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4092 11:55:27.076211 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4093 11:55:27.082889 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4094 11:55:27.086425 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 11:55:27.089624 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 11:55:27.092697 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4097 11:55:27.100171 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4098 11:55:27.102660 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4099 11:55:27.106341 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4100 11:55:27.109964 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4101 11:55:27.115945 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4102 11:55:27.119686 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4103 11:55:27.122963 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4104 11:55:27.123520 ==
4105 11:55:27.126018 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 11:55:27.128943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 11:55:27.132488 ==
4108 11:55:27.133055 DQS Delay:
4109 11:55:27.133425 DQS0 = 0, DQS1 = 0
4110 11:55:27.135882 DQM Delay:
4111 11:55:27.136348 DQM0 = 44, DQM1 = 35
4112 11:55:27.138770 DQ Delay:
4113 11:55:27.142532 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4114 11:55:27.143140 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4115 11:55:27.145531 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4116 11:55:27.149288 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4117 11:55:27.152068
4118 11:55:27.152566
4119 11:55:27.152935 ==
4120 11:55:27.155654 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:55:27.158708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:55:27.159183 ==
4123 11:55:27.159558
4124 11:55:27.159886
4125 11:55:27.162786 TX Vref Scan disable
4126 11:55:27.163295 == TX Byte 0 ==
4127 11:55:27.168439 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4128 11:55:27.172045 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4129 11:55:27.172560 == TX Byte 1 ==
4130 11:55:27.178910 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4131 11:55:27.182308 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4132 11:55:27.182851 ==
4133 11:55:27.184903 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 11:55:27.188618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 11:55:27.189138 ==
4136 11:55:27.189471
4137 11:55:27.191910
4138 11:55:27.192425 TX Vref Scan disable
4139 11:55:27.195278 == TX Byte 0 ==
4140 11:55:27.198385 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4141 11:55:27.205085 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4142 11:55:27.205650 == TX Byte 1 ==
4143 11:55:27.208140 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4144 11:55:27.215085 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4145 11:55:27.215637
4146 11:55:27.216000 [DATLAT]
4147 11:55:27.216335 Freq=600, CH0 RK0
4148 11:55:27.216708
4149 11:55:27.218869 DATLAT Default: 0x9
4150 11:55:27.221508 0, 0xFFFF, sum = 0
4151 11:55:27.222069 1, 0xFFFF, sum = 0
4152 11:55:27.225811 2, 0xFFFF, sum = 0
4153 11:55:27.226535 3, 0xFFFF, sum = 0
4154 11:55:27.228117 4, 0xFFFF, sum = 0
4155 11:55:27.228587 5, 0xFFFF, sum = 0
4156 11:55:27.231280 6, 0xFFFF, sum = 0
4157 11:55:27.231748 7, 0xFFFF, sum = 0
4158 11:55:27.234639 8, 0x0, sum = 1
4159 11:55:27.235104 9, 0x0, sum = 2
4160 11:55:27.237836 10, 0x0, sum = 3
4161 11:55:27.238353 11, 0x0, sum = 4
4162 11:55:27.238738 best_step = 9
4163 11:55:27.239092
4164 11:55:27.241592 ==
4165 11:55:27.244603 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 11:55:27.247563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 11:55:27.248030 ==
4168 11:55:27.248382 RX Vref Scan: 1
4169 11:55:27.248687
4170 11:55:27.250835 RX Vref 0 -> 0, step: 1
4171 11:55:27.251250
4172 11:55:27.254960 RX Delay -195 -> 252, step: 8
4173 11:55:27.255375
4174 11:55:27.258028 Set Vref, RX VrefLevel [Byte0]: 53
4175 11:55:27.261260 [Byte1]: 59
4176 11:55:27.261777
4177 11:55:27.264592 Final RX Vref Byte 0 = 53 to rank0
4178 11:55:27.267561 Final RX Vref Byte 1 = 59 to rank0
4179 11:55:27.271485 Final RX Vref Byte 0 = 53 to rank1
4180 11:55:27.275487 Final RX Vref Byte 1 = 59 to rank1==
4181 11:55:27.277671 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 11:55:27.281050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 11:55:27.285047 ==
4184 11:55:27.285567 DQS Delay:
4185 11:55:27.285905 DQS0 = 0, DQS1 = 0
4186 11:55:27.287986 DQM Delay:
4187 11:55:27.288447 DQM0 = 41, DQM1 = 32
4188 11:55:27.290911 DQ Delay:
4189 11:55:27.294625 DQ0 =40, DQ1 =40, DQ2 =36, DQ3 =36
4190 11:55:27.295191 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4191 11:55:27.297328 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4192 11:55:27.304107 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4193 11:55:27.304666
4194 11:55:27.305030
4195 11:55:27.310570 [DQSOSCAuto] RK0, (LSB)MR18= 0x5047, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4196 11:55:27.313955 CH0 RK0: MR19=808, MR18=5047
4197 11:55:27.320317 CH0_RK0: MR19=0x808, MR18=0x5047, DQSOSC=394, MR23=63, INC=168, DEC=112
4198 11:55:27.320891
4199 11:55:27.323814 ----->DramcWriteLeveling(PI) begin...
4200 11:55:27.324381 ==
4201 11:55:27.326744 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 11:55:27.330017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 11:55:27.330545 ==
4204 11:55:27.333194 Write leveling (Byte 0): 34 => 34
4205 11:55:27.336565 Write leveling (Byte 1): 30 => 30
4206 11:55:27.339804 DramcWriteLeveling(PI) end<-----
4207 11:55:27.340224
4208 11:55:27.340553 ==
4209 11:55:27.343091 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:55:27.346335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:55:27.349438 ==
4212 11:55:27.349856 [Gating] SW mode calibration
4213 11:55:27.360414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 11:55:27.362889 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 11:55:27.366214 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 11:55:27.373334 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 11:55:27.376101 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4218 11:55:27.379601 0 9 12 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
4219 11:55:27.385760 0 9 16 | B1->B0 | 2e2e 2424 | 0 0 | (0 1) (0 0)
4220 11:55:27.389650 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:55:27.393152 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:55:27.399279 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 11:55:27.402681 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:55:27.406157 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:55:27.412433 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:55:27.415547 0 10 12 | B1->B0 | 2a2a 3737 | 0 0 | (0 0) (0 0)
4227 11:55:27.419282 0 10 16 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
4228 11:55:27.425742 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:55:27.428617 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:55:27.432150 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:55:27.439060 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:55:27.442597 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:55:27.445314 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:55:27.451795 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4235 11:55:27.455741 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4236 11:55:27.458416 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:55:27.465454 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:55:27.468703 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:55:27.472322 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:55:27.478695 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:55:27.481711 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:55:27.485172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:55:27.491887 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:55:27.494799 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:55:27.498387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:55:27.504734 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:55:27.508561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:55:27.511390 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:55:27.518315 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:55:27.521659 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4251 11:55:27.524848 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 11:55:27.527468 Total UI for P1: 0, mck2ui 16
4253 11:55:27.531283 best dqsien dly found for B0: ( 0, 13, 12)
4254 11:55:27.534335 Total UI for P1: 0, mck2ui 16
4255 11:55:27.537975 best dqsien dly found for B1: ( 0, 13, 12)
4256 11:55:27.540873 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4257 11:55:27.544006 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4258 11:55:27.547968
4259 11:55:27.550915 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 11:55:27.554105 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4261 11:55:27.557281 [Gating] SW calibration Done
4262 11:55:27.557697 ==
4263 11:55:27.560914 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 11:55:27.564040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 11:55:27.564567 ==
4266 11:55:27.567199 RX Vref Scan: 0
4267 11:55:27.567717
4268 11:55:27.568047 RX Vref 0 -> 0, step: 1
4269 11:55:27.568354
4270 11:55:27.570643 RX Delay -230 -> 252, step: 16
4271 11:55:27.574320 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4272 11:55:27.580565 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4273 11:55:27.584334 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4274 11:55:27.587709 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4275 11:55:27.590372 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4276 11:55:27.597026 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4277 11:55:27.600349 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4278 11:55:27.603498 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4279 11:55:27.607224 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4280 11:55:27.610147 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4281 11:55:27.616732 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4282 11:55:27.619923 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4283 11:55:27.623016 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4284 11:55:27.629719 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4285 11:55:27.633385 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4286 11:55:27.636103 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4287 11:55:27.636597 ==
4288 11:55:27.640252 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 11:55:27.643082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 11:55:27.643500 ==
4291 11:55:27.646497 DQS Delay:
4292 11:55:27.647003 DQS0 = 0, DQS1 = 0
4293 11:55:27.649618 DQM Delay:
4294 11:55:27.650127 DQM0 = 42, DQM1 = 31
4295 11:55:27.653103 DQ Delay:
4296 11:55:27.653547 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4297 11:55:27.655912 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4298 11:55:27.659533 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4299 11:55:27.662331 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =41
4300 11:55:27.662753
4301 11:55:27.665797
4302 11:55:27.666232 ==
4303 11:55:27.668940 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 11:55:27.672426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 11:55:27.672940 ==
4306 11:55:27.673273
4307 11:55:27.673579
4308 11:55:27.676426 TX Vref Scan disable
4309 11:55:27.677163 == TX Byte 0 ==
4310 11:55:27.682062 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4311 11:55:27.685675 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4312 11:55:27.686148 == TX Byte 1 ==
4313 11:55:27.692436 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4314 11:55:27.695884 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4315 11:55:27.696308 ==
4316 11:55:27.698943 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 11:55:27.702674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 11:55:27.703094 ==
4319 11:55:27.703426
4320 11:55:27.703727
4321 11:55:27.705587 TX Vref Scan disable
4322 11:55:27.708698 == TX Byte 0 ==
4323 11:55:27.711935 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4324 11:55:27.718854 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4325 11:55:27.719434 == TX Byte 1 ==
4326 11:55:27.721905 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4327 11:55:27.728682 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4328 11:55:27.729110
4329 11:55:27.729439 [DATLAT]
4330 11:55:27.729745 Freq=600, CH0 RK1
4331 11:55:27.730040
4332 11:55:27.732117 DATLAT Default: 0x9
4333 11:55:27.735023 0, 0xFFFF, sum = 0
4334 11:55:27.735447 1, 0xFFFF, sum = 0
4335 11:55:27.738238 2, 0xFFFF, sum = 0
4336 11:55:27.738663 3, 0xFFFF, sum = 0
4337 11:55:27.741658 4, 0xFFFF, sum = 0
4338 11:55:27.742083 5, 0xFFFF, sum = 0
4339 11:55:27.744861 6, 0xFFFF, sum = 0
4340 11:55:27.745281 7, 0xFFFF, sum = 0
4341 11:55:27.748323 8, 0x0, sum = 1
4342 11:55:27.748746 9, 0x0, sum = 2
4343 11:55:27.751883 10, 0x0, sum = 3
4344 11:55:27.752305 11, 0x0, sum = 4
4345 11:55:27.752764 best_step = 9
4346 11:55:27.753080
4347 11:55:27.754738 ==
4348 11:55:27.758419 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 11:55:27.761654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 11:55:27.762075 ==
4351 11:55:27.762495 RX Vref Scan: 0
4352 11:55:27.762817
4353 11:55:27.764850 RX Vref 0 -> 0, step: 1
4354 11:55:27.765268
4355 11:55:27.768458 RX Delay -195 -> 252, step: 8
4356 11:55:27.775128 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4357 11:55:27.778077 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4358 11:55:27.780852 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4359 11:55:27.784206 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4360 11:55:27.791273 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4361 11:55:27.793846 iDelay=197, Bit 5, Center 28 (-123 ~ 180) 304
4362 11:55:27.797500 iDelay=197, Bit 6, Center 48 (-99 ~ 196) 296
4363 11:55:27.800567 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4364 11:55:27.803833 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4365 11:55:27.810554 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4366 11:55:27.813898 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4367 11:55:27.817667 iDelay=197, Bit 11, Center 24 (-131 ~ 180) 312
4368 11:55:27.820364 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4369 11:55:27.827268 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4370 11:55:27.830000 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4371 11:55:27.833727 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4372 11:55:27.833831 ==
4373 11:55:27.836733 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 11:55:27.840188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 11:55:27.843469 ==
4376 11:55:27.843553 DQS Delay:
4377 11:55:27.843618 DQS0 = 0, DQS1 = 0
4378 11:55:27.846752 DQM Delay:
4379 11:55:27.846835 DQM0 = 40, DQM1 = 32
4380 11:55:27.850294 DQ Delay:
4381 11:55:27.853468 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4382 11:55:27.853551 DQ4 =44, DQ5 =28, DQ6 =48, DQ7 =44
4383 11:55:27.856871 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =24
4384 11:55:27.860145 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4385 11:55:27.863192
4386 11:55:27.863274
4387 11:55:27.870000 [DQSOSCAuto] RK1, (LSB)MR18= 0x4843, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4388 11:55:27.873794 CH0 RK1: MR19=808, MR18=4843
4389 11:55:27.879668 CH0_RK1: MR19=0x808, MR18=0x4843, DQSOSC=396, MR23=63, INC=167, DEC=111
4390 11:55:27.883100 [RxdqsGatingPostProcess] freq 600
4391 11:55:27.886505 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 11:55:27.889872 Pre-setting of DQS Precalculation
4393 11:55:27.896150 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 11:55:27.896235 ==
4395 11:55:27.899630 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:55:27.903371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:55:27.903467 ==
4398 11:55:27.909536 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 11:55:27.912749 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4400 11:55:27.917149 [CA 0] Center 35 (5~66) winsize 62
4401 11:55:27.920421 [CA 1] Center 35 (5~66) winsize 62
4402 11:55:27.923636 [CA 2] Center 34 (4~65) winsize 62
4403 11:55:27.927254 [CA 3] Center 34 (4~64) winsize 61
4404 11:55:27.930880 [CA 4] Center 34 (4~65) winsize 62
4405 11:55:27.933917 [CA 5] Center 33 (3~64) winsize 62
4406 11:55:27.934012
4407 11:55:27.936929 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4408 11:55:27.937012
4409 11:55:27.940857 [CATrainingPosCal] consider 1 rank data
4410 11:55:27.943750 u2DelayCellTimex100 = 270/100 ps
4411 11:55:27.947527 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4412 11:55:27.953833 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4413 11:55:27.957280 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 11:55:27.960001 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4415 11:55:27.963707 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 11:55:27.967059 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 11:55:27.967149
4418 11:55:27.969974 CA PerBit enable=1, Macro0, CA PI delay=33
4419 11:55:27.970056
4420 11:55:27.973380 [CBTSetCACLKResult] CA Dly = 33
4421 11:55:27.976902 CS Dly: 3 (0~34)
4422 11:55:27.976984 ==
4423 11:55:27.980246 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 11:55:27.982974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 11:55:27.983059 ==
4426 11:55:27.990099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 11:55:27.993037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4428 11:55:27.997296 [CA 0] Center 35 (5~66) winsize 62
4429 11:55:28.000741 [CA 1] Center 35 (5~66) winsize 62
4430 11:55:28.003798 [CA 2] Center 34 (4~65) winsize 62
4431 11:55:28.007696 [CA 3] Center 34 (3~65) winsize 63
4432 11:55:28.010311 [CA 4] Center 34 (4~65) winsize 62
4433 11:55:28.014172 [CA 5] Center 33 (3~64) winsize 62
4434 11:55:28.014284
4435 11:55:28.016921 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4436 11:55:28.017002
4437 11:55:28.020356 [CATrainingPosCal] consider 2 rank data
4438 11:55:28.024043 u2DelayCellTimex100 = 270/100 ps
4439 11:55:28.027626 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4440 11:55:28.033814 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4441 11:55:28.037235 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 11:55:28.040562 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4443 11:55:28.043756 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 11:55:28.046815 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 11:55:28.046974
4446 11:55:28.050505 CA PerBit enable=1, Macro0, CA PI delay=33
4447 11:55:28.050670
4448 11:55:28.053516 [CBTSetCACLKResult] CA Dly = 33
4449 11:55:28.057055 CS Dly: 4 (0~37)
4450 11:55:28.057202
4451 11:55:28.059727 ----->DramcWriteLeveling(PI) begin...
4452 11:55:28.059831 ==
4453 11:55:28.063883 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 11:55:28.066975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:55:28.067490 ==
4456 11:55:28.071299 Write leveling (Byte 0): 28 => 28
4457 11:55:28.074305 Write leveling (Byte 1): 29 => 29
4458 11:55:28.077512 DramcWriteLeveling(PI) end<-----
4459 11:55:28.078059
4460 11:55:28.078487 ==
4461 11:55:28.080506 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:55:28.083951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:55:28.084504 ==
4464 11:55:28.086784 [Gating] SW mode calibration
4465 11:55:28.093929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 11:55:28.100269 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 11:55:28.103741 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 11:55:28.106601 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 11:55:28.114089 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 11:55:28.116614 0 9 12 | B1->B0 | 2f2f 3030 | 0 1 | (0 0) (0 0)
4471 11:55:28.120521 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:55:28.126877 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 11:55:28.130038 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 11:55:28.132944 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 11:55:28.139886 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 11:55:28.142732 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:55:28.146812 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 11:55:28.152504 0 10 12 | B1->B0 | 3232 3837 | 0 1 | (0 0) (0 0)
4479 11:55:28.155833 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:55:28.159446 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:55:28.165958 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 11:55:28.169418 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:55:28.172872 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:55:28.179219 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:55:28.182563 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:55:28.186298 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4487 11:55:28.192588 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:55:28.195632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:55:28.198378 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:55:28.205499 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:55:28.208764 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:55:28.212311 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:55:28.218598 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:55:28.222193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:55:28.225311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:55:28.232046 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:55:28.235051 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:55:28.237994 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:55:28.244852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:55:28.248492 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:55:28.251308 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:55:28.258418 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4503 11:55:28.261535 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 11:55:28.265147 Total UI for P1: 0, mck2ui 16
4505 11:55:28.268405 best dqsien dly found for B0: ( 0, 13, 14)
4506 11:55:28.271506 Total UI for P1: 0, mck2ui 16
4507 11:55:28.274904 best dqsien dly found for B1: ( 0, 13, 12)
4508 11:55:28.277868 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4509 11:55:28.281343 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 11:55:28.281810
4511 11:55:28.284288 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4512 11:55:28.291533 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 11:55:28.292091 [Gating] SW calibration Done
4514 11:55:28.292460 ==
4515 11:55:28.294108 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 11:55:28.301359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 11:55:28.301918 ==
4518 11:55:28.302337 RX Vref Scan: 0
4519 11:55:28.302691
4520 11:55:28.304571 RX Vref 0 -> 0, step: 1
4521 11:55:28.305127
4522 11:55:28.307925 RX Delay -230 -> 252, step: 16
4523 11:55:28.311004 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4524 11:55:28.313946 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4525 11:55:28.320730 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4526 11:55:28.324160 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4527 11:55:28.327532 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4528 11:55:28.330522 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4529 11:55:28.334098 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4530 11:55:28.340443 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4531 11:55:28.344064 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4532 11:55:28.346932 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4533 11:55:28.350489 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4534 11:55:28.357404 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4535 11:55:28.360899 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4536 11:55:28.363855 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4537 11:55:28.366952 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4538 11:55:28.373697 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4539 11:55:28.374293 ==
4540 11:55:28.376826 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 11:55:28.380397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 11:55:28.380865 ==
4543 11:55:28.381282 DQS Delay:
4544 11:55:28.383598 DQS0 = 0, DQS1 = 0
4545 11:55:28.384122 DQM Delay:
4546 11:55:28.386682 DQM0 = 41, DQM1 = 38
4547 11:55:28.387117 DQ Delay:
4548 11:55:28.390300 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4549 11:55:28.393403 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4550 11:55:28.397069 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =33
4551 11:55:28.400222 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4552 11:55:28.400644
4553 11:55:28.400971
4554 11:55:28.401276 ==
4555 11:55:28.403718 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 11:55:28.407070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 11:55:28.410407 ==
4558 11:55:28.410930
4559 11:55:28.411265
4560 11:55:28.411568 TX Vref Scan disable
4561 11:55:28.413399 == TX Byte 0 ==
4562 11:55:28.417429 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4563 11:55:28.420605 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4564 11:55:28.423475 == TX Byte 1 ==
4565 11:55:28.427181 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 11:55:28.429650 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 11:55:28.433598 ==
4568 11:55:28.436434 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 11:55:28.439648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 11:55:28.440067 ==
4571 11:55:28.440396
4572 11:55:28.440701
4573 11:55:28.442936 TX Vref Scan disable
4574 11:55:28.443351 == TX Byte 0 ==
4575 11:55:28.449528 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4576 11:55:28.452862 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4577 11:55:28.456378 == TX Byte 1 ==
4578 11:55:28.459367 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 11:55:28.462808 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 11:55:28.463326
4581 11:55:28.463658 [DATLAT]
4582 11:55:28.465697 Freq=600, CH1 RK0
4583 11:55:28.466118
4584 11:55:28.470631 DATLAT Default: 0x9
4585 11:55:28.471154 0, 0xFFFF, sum = 0
4586 11:55:28.472443 1, 0xFFFF, sum = 0
4587 11:55:28.472824 2, 0xFFFF, sum = 0
4588 11:55:28.475912 3, 0xFFFF, sum = 0
4589 11:55:28.476337 4, 0xFFFF, sum = 0
4590 11:55:28.479295 5, 0xFFFF, sum = 0
4591 11:55:28.479738 6, 0xFFFF, sum = 0
4592 11:55:28.482504 7, 0xFFFF, sum = 0
4593 11:55:28.483035 8, 0x0, sum = 1
4594 11:55:28.485711 9, 0x0, sum = 2
4595 11:55:28.486236 10, 0x0, sum = 3
4596 11:55:28.489163 11, 0x0, sum = 4
4597 11:55:28.489685 best_step = 9
4598 11:55:28.490126
4599 11:55:28.490667 ==
4600 11:55:28.492633 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 11:55:28.496009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 11:55:28.496428 ==
4603 11:55:28.499326 RX Vref Scan: 1
4604 11:55:28.499756
4605 11:55:28.502763 RX Vref 0 -> 0, step: 1
4606 11:55:28.503297
4607 11:55:28.503632 RX Delay -195 -> 252, step: 8
4608 11:55:28.503944
4609 11:55:28.505477 Set Vref, RX VrefLevel [Byte0]: 51
4610 11:55:28.509228 [Byte1]: 51
4611 11:55:28.514169
4612 11:55:28.514726 Final RX Vref Byte 0 = 51 to rank0
4613 11:55:28.516962 Final RX Vref Byte 1 = 51 to rank0
4614 11:55:28.520955 Final RX Vref Byte 0 = 51 to rank1
4615 11:55:28.523954 Final RX Vref Byte 1 = 51 to rank1==
4616 11:55:28.526975 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 11:55:28.533212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 11:55:28.533646 ==
4619 11:55:28.534021 DQS Delay:
4620 11:55:28.536238 DQS0 = 0, DQS1 = 0
4621 11:55:28.536653 DQM Delay:
4622 11:55:28.536979 DQM0 = 42, DQM1 = 34
4623 11:55:28.539766 DQ Delay:
4624 11:55:28.542993 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =44
4625 11:55:28.546179 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4626 11:55:28.549551 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4627 11:55:28.552526 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4628 11:55:28.552947
4629 11:55:28.553278
4630 11:55:28.559419 [DQSOSCAuto] RK0, (LSB)MR18= 0x334d, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4631 11:55:28.562753 CH1 RK0: MR19=808, MR18=334D
4632 11:55:28.569944 CH1_RK0: MR19=0x808, MR18=0x334D, DQSOSC=395, MR23=63, INC=168, DEC=112
4633 11:55:28.570517
4634 11:55:28.573029 ----->DramcWriteLeveling(PI) begin...
4635 11:55:28.573559 ==
4636 11:55:28.576275 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 11:55:28.579734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 11:55:28.580261 ==
4639 11:55:28.583133 Write leveling (Byte 0): 28 => 28
4640 11:55:28.586054 Write leveling (Byte 1): 28 => 28
4641 11:55:28.589053 DramcWriteLeveling(PI) end<-----
4642 11:55:28.589475
4643 11:55:28.589802 ==
4644 11:55:28.592237 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:55:28.599033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:55:28.599552 ==
4647 11:55:28.599887 [Gating] SW mode calibration
4648 11:55:28.608834 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 11:55:28.612375 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 11:55:28.615754 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 11:55:28.622318 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 11:55:28.625316 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4653 11:55:28.628673 0 9 12 | B1->B0 | 3333 2d2d | 1 0 | (1 0) (0 0)
4654 11:55:28.635116 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 11:55:28.638847 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 11:55:28.642510 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 11:55:28.648373 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 11:55:28.651778 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 11:55:28.658531 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:55:28.662074 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4661 11:55:28.664905 0 10 12 | B1->B0 | 3333 3c3c | 0 1 | (1 1) (0 0)
4662 11:55:28.668480 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4663 11:55:28.674681 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:55:28.678368 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 11:55:28.684655 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 11:55:28.688003 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 11:55:28.691673 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:55:28.698655 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:55:28.701505 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 11:55:28.704692 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:55:28.707645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:55:28.714387 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:55:28.717597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:55:28.721362 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:55:28.727548 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:55:28.730649 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:55:28.734505 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:55:28.740976 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:55:28.744191 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:55:28.747448 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:55:28.754036 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:55:28.757010 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:55:28.760717 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:55:28.767111 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:55:28.769980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4686 11:55:28.773429 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 11:55:28.776541 Total UI for P1: 0, mck2ui 16
4688 11:55:28.780665 best dqsien dly found for B0: ( 0, 13, 12)
4689 11:55:28.783434 Total UI for P1: 0, mck2ui 16
4690 11:55:28.786593 best dqsien dly found for B1: ( 0, 13, 12)
4691 11:55:28.793101 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4692 11:55:28.796521 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4693 11:55:28.796937
4694 11:55:28.799973 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4695 11:55:28.803710 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4696 11:55:28.806314 [Gating] SW calibration Done
4697 11:55:28.806737 ==
4698 11:55:28.809726 Dram Type= 6, Freq= 0, CH_1, rank 1
4699 11:55:28.813269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4700 11:55:28.813790 ==
4701 11:55:28.816616 RX Vref Scan: 0
4702 11:55:28.817143
4703 11:55:28.817540 RX Vref 0 -> 0, step: 1
4704 11:55:28.817856
4705 11:55:28.819675 RX Delay -230 -> 252, step: 16
4706 11:55:28.826477 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4707 11:55:28.829890 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4708 11:55:28.832672 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4709 11:55:28.836118 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4710 11:55:28.839383 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4711 11:55:28.846435 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4712 11:55:28.849635 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4713 11:55:28.853038 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4714 11:55:28.855699 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4715 11:55:28.862774 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4716 11:55:28.865846 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4717 11:55:28.869025 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4718 11:55:28.872662 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4719 11:55:28.878876 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4720 11:55:28.882069 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4721 11:55:28.885490 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4722 11:55:28.886010 ==
4723 11:55:28.889538 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:55:28.892505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:55:28.895673 ==
4726 11:55:28.896192 DQS Delay:
4727 11:55:28.896525 DQS0 = 0, DQS1 = 0
4728 11:55:28.898693 DQM Delay:
4729 11:55:28.899224 DQM0 = 40, DQM1 = 38
4730 11:55:28.902188 DQ Delay:
4731 11:55:28.905436 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4732 11:55:28.905958 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4733 11:55:28.908543 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4734 11:55:28.915447 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4735 11:55:28.915966
4736 11:55:28.916299
4737 11:55:28.916678 ==
4738 11:55:28.918303 Dram Type= 6, Freq= 0, CH_1, rank 1
4739 11:55:28.921593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4740 11:55:28.922117 ==
4741 11:55:28.922491
4742 11:55:28.922803
4743 11:55:28.924595 TX Vref Scan disable
4744 11:55:28.925011 == TX Byte 0 ==
4745 11:55:28.931621 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4746 11:55:28.934773 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4747 11:55:28.935197 == TX Byte 1 ==
4748 11:55:28.941313 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4749 11:55:28.945541 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4750 11:55:28.946063 ==
4751 11:55:28.948042 Dram Type= 6, Freq= 0, CH_1, rank 1
4752 11:55:28.951808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4753 11:55:28.952234 ==
4754 11:55:28.954841
4755 11:55:28.955263
4756 11:55:28.955598 TX Vref Scan disable
4757 11:55:28.958350 == TX Byte 0 ==
4758 11:55:28.962104 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4759 11:55:28.964800 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4760 11:55:28.968196 == TX Byte 1 ==
4761 11:55:28.971136 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4762 11:55:28.978305 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4763 11:55:28.978825
4764 11:55:28.979193 [DATLAT]
4765 11:55:28.979531 Freq=600, CH1 RK1
4766 11:55:28.979854
4767 11:55:28.981637 DATLAT Default: 0x9
4768 11:55:28.982178 0, 0xFFFF, sum = 0
4769 11:55:28.984431 1, 0xFFFF, sum = 0
4770 11:55:28.987686 2, 0xFFFF, sum = 0
4771 11:55:28.988238 3, 0xFFFF, sum = 0
4772 11:55:28.991124 4, 0xFFFF, sum = 0
4773 11:55:28.991683 5, 0xFFFF, sum = 0
4774 11:55:28.994133 6, 0xFFFF, sum = 0
4775 11:55:28.994635 7, 0xFFFF, sum = 0
4776 11:55:28.997726 8, 0x0, sum = 1
4777 11:55:28.998243 9, 0x0, sum = 2
4778 11:55:29.001407 10, 0x0, sum = 3
4779 11:55:29.001879 11, 0x0, sum = 4
4780 11:55:29.002247 best_step = 9
4781 11:55:29.002591
4782 11:55:29.003939 ==
4783 11:55:29.007364 Dram Type= 6, Freq= 0, CH_1, rank 1
4784 11:55:29.011365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4785 11:55:29.011817 ==
4786 11:55:29.012152 RX Vref Scan: 0
4787 11:55:29.012467
4788 11:55:29.014275 RX Vref 0 -> 0, step: 1
4789 11:55:29.014707
4790 11:55:29.017327 RX Delay -179 -> 252, step: 8
4791 11:55:29.024505 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4792 11:55:29.027125 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4793 11:55:29.030616 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4794 11:55:29.034413 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4795 11:55:29.037533 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4796 11:55:29.043628 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4797 11:55:29.046830 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4798 11:55:29.050855 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4799 11:55:29.053531 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4800 11:55:29.059965 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4801 11:55:29.063136 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4802 11:55:29.066831 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4803 11:55:29.070034 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4804 11:55:29.076835 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4805 11:55:29.079846 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4806 11:55:29.083538 iDelay=205, Bit 15, Center 48 (-107 ~ 204) 312
4807 11:55:29.084102 ==
4808 11:55:29.086921 Dram Type= 6, Freq= 0, CH_1, rank 1
4809 11:55:29.090191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4810 11:55:29.092651 ==
4811 11:55:29.093113 DQS Delay:
4812 11:55:29.093477 DQS0 = 0, DQS1 = 0
4813 11:55:29.096606 DQM Delay:
4814 11:55:29.097069 DQM0 = 37, DQM1 = 35
4815 11:55:29.099624 DQ Delay:
4816 11:55:29.102882 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4817 11:55:29.103345 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4818 11:55:29.107047 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =24
4819 11:55:29.112934 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =48
4820 11:55:29.113353
4821 11:55:29.113678
4822 11:55:29.119665 [DQSOSCAuto] RK1, (LSB)MR18= 0x375b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4823 11:55:29.122769 CH1 RK1: MR19=808, MR18=375B
4824 11:55:29.129212 CH1_RK1: MR19=0x808, MR18=0x375B, DQSOSC=392, MR23=63, INC=170, DEC=113
4825 11:55:29.132667 [RxdqsGatingPostProcess] freq 600
4826 11:55:29.135880 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4827 11:55:29.138896 Pre-setting of DQS Precalculation
4828 11:55:29.145307 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4829 11:55:29.151826 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4830 11:55:29.158156 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4831 11:55:29.158244
4832 11:55:29.158317
4833 11:55:29.162586 [Calibration Summary] 1200 Mbps
4834 11:55:29.162669 CH 0, Rank 0
4835 11:55:29.165719 SW Impedance : PASS
4836 11:55:29.168174 DUTY Scan : NO K
4837 11:55:29.168261 ZQ Calibration : PASS
4838 11:55:29.171829 Jitter Meter : NO K
4839 11:55:29.175544 CBT Training : PASS
4840 11:55:29.175626 Write leveling : PASS
4841 11:55:29.178134 RX DQS gating : PASS
4842 11:55:29.182402 RX DQ/DQS(RDDQC) : PASS
4843 11:55:29.182484 TX DQ/DQS : PASS
4844 11:55:29.184688 RX DATLAT : PASS
4845 11:55:29.188195 RX DQ/DQS(Engine): PASS
4846 11:55:29.188277 TX OE : NO K
4847 11:55:29.191794 All Pass.
4848 11:55:29.191876
4849 11:55:29.191940 CH 0, Rank 1
4850 11:55:29.194513 SW Impedance : PASS
4851 11:55:29.194595 DUTY Scan : NO K
4852 11:55:29.198507 ZQ Calibration : PASS
4853 11:55:29.201195 Jitter Meter : NO K
4854 11:55:29.201276 CBT Training : PASS
4855 11:55:29.204410 Write leveling : PASS
4856 11:55:29.207973 RX DQS gating : PASS
4857 11:55:29.208055 RX DQ/DQS(RDDQC) : PASS
4858 11:55:29.211007 TX DQ/DQS : PASS
4859 11:55:29.214377 RX DATLAT : PASS
4860 11:55:29.214457 RX DQ/DQS(Engine): PASS
4861 11:55:29.217518 TX OE : NO K
4862 11:55:29.217600 All Pass.
4863 11:55:29.217663
4864 11:55:29.221237 CH 1, Rank 0
4865 11:55:29.221318 SW Impedance : PASS
4866 11:55:29.224614 DUTY Scan : NO K
4867 11:55:29.227195 ZQ Calibration : PASS
4868 11:55:29.227277 Jitter Meter : NO K
4869 11:55:29.230861 CBT Training : PASS
4870 11:55:29.234096 Write leveling : PASS
4871 11:55:29.234177 RX DQS gating : PASS
4872 11:55:29.238202 RX DQ/DQS(RDDQC) : PASS
4873 11:55:29.238320 TX DQ/DQS : PASS
4874 11:55:29.240756 RX DATLAT : PASS
4875 11:55:29.243791 RX DQ/DQS(Engine): PASS
4876 11:55:29.243872 TX OE : NO K
4877 11:55:29.247499 All Pass.
4878 11:55:29.247580
4879 11:55:29.247644 CH 1, Rank 1
4880 11:55:29.250557 SW Impedance : PASS
4881 11:55:29.250638 DUTY Scan : NO K
4882 11:55:29.254144 ZQ Calibration : PASS
4883 11:55:29.257438 Jitter Meter : NO K
4884 11:55:29.257523 CBT Training : PASS
4885 11:55:29.260324 Write leveling : PASS
4886 11:55:29.263723 RX DQS gating : PASS
4887 11:55:29.263830 RX DQ/DQS(RDDQC) : PASS
4888 11:55:29.267539 TX DQ/DQS : PASS
4889 11:55:29.270204 RX DATLAT : PASS
4890 11:55:29.270313 RX DQ/DQS(Engine): PASS
4891 11:55:29.274451 TX OE : NO K
4892 11:55:29.274533 All Pass.
4893 11:55:29.274597
4894 11:55:29.277083 DramC Write-DBI off
4895 11:55:29.280215 PER_BANK_REFRESH: Hybrid Mode
4896 11:55:29.280296 TX_TRACKING: ON
4897 11:55:29.290121 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4898 11:55:29.293768 [FAST_K] Save calibration result to emmc
4899 11:55:29.296767 dramc_set_vcore_voltage set vcore to 662500
4900 11:55:29.300071 Read voltage for 933, 3
4901 11:55:29.300153 Vio18 = 0
4902 11:55:29.300217 Vcore = 662500
4903 11:55:29.303665 Vdram = 0
4904 11:55:29.303746 Vddq = 0
4905 11:55:29.303810 Vmddr = 0
4906 11:55:29.310041 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4907 11:55:29.313895 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4908 11:55:29.317049 MEM_TYPE=3, freq_sel=17
4909 11:55:29.320074 sv_algorithm_assistance_LP4_1600
4910 11:55:29.323162 ============ PULL DRAM RESETB DOWN ============
4911 11:55:29.326717 ========== PULL DRAM RESETB DOWN end =========
4912 11:55:29.333145 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4913 11:55:29.336558 ===================================
4914 11:55:29.339851 LPDDR4 DRAM CONFIGURATION
4915 11:55:29.343335 ===================================
4916 11:55:29.343417 EX_ROW_EN[0] = 0x0
4917 11:55:29.346398 EX_ROW_EN[1] = 0x0
4918 11:55:29.346480 LP4Y_EN = 0x0
4919 11:55:29.349576 WORK_FSP = 0x0
4920 11:55:29.349657 WL = 0x3
4921 11:55:29.352958 RL = 0x3
4922 11:55:29.353041 BL = 0x2
4923 11:55:29.356194 RPST = 0x0
4924 11:55:29.356275 RD_PRE = 0x0
4925 11:55:29.359699 WR_PRE = 0x1
4926 11:55:29.359780 WR_PST = 0x0
4927 11:55:29.362791 DBI_WR = 0x0
4928 11:55:29.365934 DBI_RD = 0x0
4929 11:55:29.366016 OTF = 0x1
4930 11:55:29.369941 ===================================
4931 11:55:29.373099 ===================================
4932 11:55:29.373181 ANA top config
4933 11:55:29.376551 ===================================
4934 11:55:29.379660 DLL_ASYNC_EN = 0
4935 11:55:29.382528 ALL_SLAVE_EN = 1
4936 11:55:29.386407 NEW_RANK_MODE = 1
4937 11:55:29.389435 DLL_IDLE_MODE = 1
4938 11:55:29.389517 LP45_APHY_COMB_EN = 1
4939 11:55:29.392640 TX_ODT_DIS = 1
4940 11:55:29.395917 NEW_8X_MODE = 1
4941 11:55:29.398940 ===================================
4942 11:55:29.402227 ===================================
4943 11:55:29.406052 data_rate = 1866
4944 11:55:29.408727 CKR = 1
4945 11:55:29.412207 DQ_P2S_RATIO = 8
4946 11:55:29.415983 ===================================
4947 11:55:29.416065 CA_P2S_RATIO = 8
4948 11:55:29.418728 DQ_CA_OPEN = 0
4949 11:55:29.422315 DQ_SEMI_OPEN = 0
4950 11:55:29.425867 CA_SEMI_OPEN = 0
4951 11:55:29.428492 CA_FULL_RATE = 0
4952 11:55:29.432221 DQ_CKDIV4_EN = 1
4953 11:55:29.432303 CA_CKDIV4_EN = 1
4954 11:55:29.435352 CA_PREDIV_EN = 0
4955 11:55:29.438316 PH8_DLY = 0
4956 11:55:29.441994 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4957 11:55:29.445239 DQ_AAMCK_DIV = 4
4958 11:55:29.448342 CA_AAMCK_DIV = 4
4959 11:55:29.448424 CA_ADMCK_DIV = 4
4960 11:55:29.451556 DQ_TRACK_CA_EN = 0
4961 11:55:29.455551 CA_PICK = 933
4962 11:55:29.458208 CA_MCKIO = 933
4963 11:55:29.461935 MCKIO_SEMI = 0
4964 11:55:29.465107 PLL_FREQ = 3732
4965 11:55:29.468023 DQ_UI_PI_RATIO = 32
4966 11:55:29.468105 CA_UI_PI_RATIO = 0
4967 11:55:29.471356 ===================================
4968 11:55:29.474743 ===================================
4969 11:55:29.478504 memory_type:LPDDR4
4970 11:55:29.482181 GP_NUM : 10
4971 11:55:29.482286 SRAM_EN : 1
4972 11:55:29.484893 MD32_EN : 0
4973 11:55:29.488058 ===================================
4974 11:55:29.491288 [ANA_INIT] >>>>>>>>>>>>>>
4975 11:55:29.495801 <<<<<< [CONFIGURE PHASE]: ANA_TX
4976 11:55:29.498085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4977 11:55:29.501314 ===================================
4978 11:55:29.501396 data_rate = 1866,PCW = 0X8f00
4979 11:55:29.504731 ===================================
4980 11:55:29.511143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4981 11:55:29.514414 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 11:55:29.521018 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4983 11:55:29.524542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4984 11:55:29.527340 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4985 11:55:29.530801 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4986 11:55:29.533821 [ANA_INIT] flow start
4987 11:55:29.537096 [ANA_INIT] PLL >>>>>>>>
4988 11:55:29.537187 [ANA_INIT] PLL <<<<<<<<
4989 11:55:29.540690 [ANA_INIT] MIDPI >>>>>>>>
4990 11:55:29.544111 [ANA_INIT] MIDPI <<<<<<<<
4991 11:55:29.547553 [ANA_INIT] DLL >>>>>>>>
4992 11:55:29.547636 [ANA_INIT] flow end
4993 11:55:29.550386 ============ LP4 DIFF to SE enter ============
4994 11:55:29.557362 ============ LP4 DIFF to SE exit ============
4995 11:55:29.557452 [ANA_INIT] <<<<<<<<<<<<<
4996 11:55:29.560819 [Flow] Enable top DCM control >>>>>
4997 11:55:29.563686 [Flow] Enable top DCM control <<<<<
4998 11:55:29.567023 Enable DLL master slave shuffle
4999 11:55:29.574093 ==============================================================
5000 11:55:29.574202 Gating Mode config
5001 11:55:29.580163 ==============================================================
5002 11:55:29.583478 Config description:
5003 11:55:29.593312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5004 11:55:29.600375 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5005 11:55:29.603449 SELPH_MODE 0: By rank 1: By Phase
5006 11:55:29.609730 ==============================================================
5007 11:55:29.613001 GAT_TRACK_EN = 1
5008 11:55:29.616569 RX_GATING_MODE = 2
5009 11:55:29.616652 RX_GATING_TRACK_MODE = 2
5010 11:55:29.619745 SELPH_MODE = 1
5011 11:55:29.623131 PICG_EARLY_EN = 1
5012 11:55:29.626277 VALID_LAT_VALUE = 1
5013 11:55:29.632985 ==============================================================
5014 11:55:29.636249 Enter into Gating configuration >>>>
5015 11:55:29.639675 Exit from Gating configuration <<<<
5016 11:55:29.642881 Enter into DVFS_PRE_config >>>>>
5017 11:55:29.652651 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5018 11:55:29.655993 Exit from DVFS_PRE_config <<<<<
5019 11:55:29.659573 Enter into PICG configuration >>>>
5020 11:55:29.662765 Exit from PICG configuration <<<<
5021 11:55:29.666115 [RX_INPUT] configuration >>>>>
5022 11:55:29.668985 [RX_INPUT] configuration <<<<<
5023 11:55:29.672498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5024 11:55:29.678933 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5025 11:55:29.686326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5026 11:55:29.692630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5027 11:55:29.699257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5028 11:55:29.702465 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5029 11:55:29.708505 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5030 11:55:29.712258 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5031 11:55:29.715214 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5032 11:55:29.718904 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5033 11:55:29.725068 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5034 11:55:29.728467 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5035 11:55:29.732227 ===================================
5036 11:55:29.735301 LPDDR4 DRAM CONFIGURATION
5037 11:55:29.738723 ===================================
5038 11:55:29.738808 EX_ROW_EN[0] = 0x0
5039 11:55:29.742521 EX_ROW_EN[1] = 0x0
5040 11:55:29.742603 LP4Y_EN = 0x0
5041 11:55:29.745307 WORK_FSP = 0x0
5042 11:55:29.745390 WL = 0x3
5043 11:55:29.748582 RL = 0x3
5044 11:55:29.752155 BL = 0x2
5045 11:55:29.752237 RPST = 0x0
5046 11:55:29.755189 RD_PRE = 0x0
5047 11:55:29.755271 WR_PRE = 0x1
5048 11:55:29.758200 WR_PST = 0x0
5049 11:55:29.758323 DBI_WR = 0x0
5050 11:55:29.761767 DBI_RD = 0x0
5051 11:55:29.761849 OTF = 0x1
5052 11:55:29.765046 ===================================
5053 11:55:29.768294 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5054 11:55:29.774904 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5055 11:55:29.778793 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5056 11:55:29.781066 ===================================
5057 11:55:29.784665 LPDDR4 DRAM CONFIGURATION
5058 11:55:29.787833 ===================================
5059 11:55:29.787916 EX_ROW_EN[0] = 0x10
5060 11:55:29.791289 EX_ROW_EN[1] = 0x0
5061 11:55:29.794578 LP4Y_EN = 0x0
5062 11:55:29.794660 WORK_FSP = 0x0
5063 11:55:29.797592 WL = 0x3
5064 11:55:29.797674 RL = 0x3
5065 11:55:29.801056 BL = 0x2
5066 11:55:29.801138 RPST = 0x0
5067 11:55:29.804064 RD_PRE = 0x0
5068 11:55:29.804145 WR_PRE = 0x1
5069 11:55:29.807683 WR_PST = 0x0
5070 11:55:29.807765 DBI_WR = 0x0
5071 11:55:29.810980 DBI_RD = 0x0
5072 11:55:29.811062 OTF = 0x1
5073 11:55:29.814636 ===================================
5074 11:55:29.820653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5075 11:55:29.824960 nWR fixed to 30
5076 11:55:29.828158 [ModeRegInit_LP4] CH0 RK0
5077 11:55:29.828244 [ModeRegInit_LP4] CH0 RK1
5078 11:55:29.831549 [ModeRegInit_LP4] CH1 RK0
5079 11:55:29.835025 [ModeRegInit_LP4] CH1 RK1
5080 11:55:29.835110 match AC timing 9
5081 11:55:29.841639 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5082 11:55:29.844840 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5083 11:55:29.848238 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5084 11:55:29.854877 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5085 11:55:29.858209 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5086 11:55:29.858351 ==
5087 11:55:29.861449 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:55:29.864445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:55:29.864530 ==
5090 11:55:29.871554 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 11:55:29.877628 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 11:55:29.881103 [CA 0] Center 37 (7~68) winsize 62
5093 11:55:29.884175 [CA 1] Center 37 (7~68) winsize 62
5094 11:55:29.887676 [CA 2] Center 34 (4~64) winsize 61
5095 11:55:29.890988 [CA 3] Center 34 (4~64) winsize 61
5096 11:55:29.894559 [CA 4] Center 32 (2~63) winsize 62
5097 11:55:29.898013 [CA 5] Center 32 (2~63) winsize 62
5098 11:55:29.898096
5099 11:55:29.901373 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 11:55:29.901457
5101 11:55:29.904495 [CATrainingPosCal] consider 1 rank data
5102 11:55:29.907890 u2DelayCellTimex100 = 270/100 ps
5103 11:55:29.910627 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 11:55:29.914370 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5105 11:55:29.917495 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5106 11:55:29.923790 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5107 11:55:29.927062 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5108 11:55:29.930552 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5109 11:55:29.930636
5110 11:55:29.933940 CA PerBit enable=1, Macro0, CA PI delay=32
5111 11:55:29.934024
5112 11:55:29.937216 [CBTSetCACLKResult] CA Dly = 32
5113 11:55:29.937301 CS Dly: 5 (0~36)
5114 11:55:29.937388 ==
5115 11:55:29.940309 Dram Type= 6, Freq= 0, CH_0, rank 1
5116 11:55:29.947128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 11:55:29.947215 ==
5118 11:55:29.950640 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5119 11:55:29.956758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5120 11:55:29.960227 [CA 0] Center 38 (8~68) winsize 61
5121 11:55:29.963555 [CA 1] Center 37 (7~68) winsize 62
5122 11:55:29.966688 [CA 2] Center 34 (4~65) winsize 62
5123 11:55:29.969985 [CA 3] Center 34 (4~65) winsize 62
5124 11:55:29.973898 [CA 4] Center 33 (3~64) winsize 62
5125 11:55:29.976668 [CA 5] Center 32 (2~63) winsize 62
5126 11:55:29.976751
5127 11:55:29.980364 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5128 11:55:29.980447
5129 11:55:29.983309 [CATrainingPosCal] consider 2 rank data
5130 11:55:29.986591 u2DelayCellTimex100 = 270/100 ps
5131 11:55:29.989982 CA0 delay=38 (8~68),Diff = 6 PI (37 cell)
5132 11:55:29.996398 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5133 11:55:29.999879 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5134 11:55:30.003351 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5135 11:55:30.006182 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5136 11:55:30.009865 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5137 11:55:30.009949
5138 11:55:30.012832 CA PerBit enable=1, Macro0, CA PI delay=32
5139 11:55:30.012915
5140 11:55:30.016376 [CBTSetCACLKResult] CA Dly = 32
5141 11:55:30.019696 CS Dly: 6 (0~39)
5142 11:55:30.019780
5143 11:55:30.022946 ----->DramcWriteLeveling(PI) begin...
5144 11:55:30.023031 ==
5145 11:55:30.025944 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 11:55:30.029442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:55:30.029527 ==
5148 11:55:30.032964 Write leveling (Byte 0): 32 => 32
5149 11:55:30.036084 Write leveling (Byte 1): 26 => 26
5150 11:55:30.039434 DramcWriteLeveling(PI) end<-----
5151 11:55:30.039520
5152 11:55:30.039604 ==
5153 11:55:30.042535 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 11:55:30.046049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 11:55:30.046158 ==
5156 11:55:30.049764 [Gating] SW mode calibration
5157 11:55:30.055798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5158 11:55:30.062962 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5159 11:55:30.065890 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5160 11:55:30.072112 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5161 11:55:30.075278 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 11:55:30.079676 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 11:55:30.085491 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 11:55:30.088879 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 11:55:30.092410 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5166 11:55:30.098918 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
5167 11:55:30.102326 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)
5168 11:55:30.105625 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5169 11:55:30.111800 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 11:55:30.114949 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 11:55:30.118231 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 11:55:30.124719 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 11:55:30.128385 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5174 11:55:30.131820 0 15 28 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
5175 11:55:30.138382 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5176 11:55:30.141694 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 11:55:30.144511 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 11:55:30.151585 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 11:55:30.154388 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 11:55:30.157745 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:55:30.164544 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:55:30.167622 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5183 11:55:30.170970 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5184 11:55:30.177485 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5185 11:55:30.180513 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:55:30.184315 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:55:30.190803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:55:30.194013 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:55:30.197358 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:55:30.204106 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:55:30.207771 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:55:30.210563 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:55:30.216852 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:55:30.220527 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:55:30.223965 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:55:30.230082 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:55:30.233329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:55:30.236508 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5199 11:55:30.243483 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5200 11:55:30.243592 Total UI for P1: 0, mck2ui 16
5201 11:55:30.249895 best dqsien dly found for B0: ( 1, 2, 28)
5202 11:55:30.253561 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5203 11:55:30.256488 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 11:55:30.259689 Total UI for P1: 0, mck2ui 16
5205 11:55:30.263171 best dqsien dly found for B1: ( 1, 3, 2)
5206 11:55:30.266275 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5207 11:55:30.269740 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5208 11:55:30.269822
5209 11:55:30.275888 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5210 11:55:30.279515 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5211 11:55:30.279623 [Gating] SW calibration Done
5212 11:55:30.282496 ==
5213 11:55:30.285662 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 11:55:30.289010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 11:55:30.289093 ==
5216 11:55:30.289175 RX Vref Scan: 0
5217 11:55:30.289271
5218 11:55:30.292731 RX Vref 0 -> 0, step: 1
5219 11:55:30.292813
5220 11:55:30.295909 RX Delay -80 -> 252, step: 8
5221 11:55:30.299246 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5222 11:55:30.302445 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5223 11:55:30.306092 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5224 11:55:30.312728 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5225 11:55:30.315789 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5226 11:55:30.318964 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5227 11:55:30.322201 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5228 11:55:30.325598 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5229 11:55:30.332395 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5230 11:55:30.335372 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5231 11:55:30.338661 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5232 11:55:30.341980 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5233 11:55:30.345333 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5234 11:55:30.348382 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5235 11:55:30.354861 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5236 11:55:30.358574 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5237 11:55:30.358656 ==
5238 11:55:30.362476 Dram Type= 6, Freq= 0, CH_0, rank 0
5239 11:55:30.365057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5240 11:55:30.365139 ==
5241 11:55:30.368397 DQS Delay:
5242 11:55:30.368479 DQS0 = 0, DQS1 = 0
5243 11:55:30.368544 DQM Delay:
5244 11:55:30.371884 DQM0 = 100, DQM1 = 89
5245 11:55:30.371967 DQ Delay:
5246 11:55:30.374779 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5247 11:55:30.378087 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5248 11:55:30.381224 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5249 11:55:30.384928 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5250 11:55:30.385009
5251 11:55:30.385074
5252 11:55:30.388284 ==
5253 11:55:30.391191 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 11:55:30.394446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 11:55:30.394529 ==
5256 11:55:30.394593
5257 11:55:30.394652
5258 11:55:30.397683 TX Vref Scan disable
5259 11:55:30.397768 == TX Byte 0 ==
5260 11:55:30.401389 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5261 11:55:30.408179 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5262 11:55:30.408261 == TX Byte 1 ==
5263 11:55:30.414620 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5264 11:55:30.417677 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5265 11:55:30.417759 ==
5266 11:55:30.421331 Dram Type= 6, Freq= 0, CH_0, rank 0
5267 11:55:30.424209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5268 11:55:30.424292 ==
5269 11:55:30.424356
5270 11:55:30.424415
5271 11:55:30.427449 TX Vref Scan disable
5272 11:55:30.430976 == TX Byte 0 ==
5273 11:55:30.434061 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5274 11:55:30.437780 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5275 11:55:30.441135 == TX Byte 1 ==
5276 11:55:30.444028 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5277 11:55:30.447295 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5278 11:55:30.447379
5279 11:55:30.450908 [DATLAT]
5280 11:55:30.450992 Freq=933, CH0 RK0
5281 11:55:30.451076
5282 11:55:30.454220 DATLAT Default: 0xd
5283 11:55:30.454351 0, 0xFFFF, sum = 0
5284 11:55:30.457536 1, 0xFFFF, sum = 0
5285 11:55:30.457621 2, 0xFFFF, sum = 0
5286 11:55:30.460584 3, 0xFFFF, sum = 0
5287 11:55:30.460669 4, 0xFFFF, sum = 0
5288 11:55:30.463767 5, 0xFFFF, sum = 0
5289 11:55:30.463852 6, 0xFFFF, sum = 0
5290 11:55:30.466899 7, 0xFFFF, sum = 0
5291 11:55:30.466984 8, 0xFFFF, sum = 0
5292 11:55:30.471567 9, 0xFFFF, sum = 0
5293 11:55:30.471653 10, 0x0, sum = 1
5294 11:55:30.473581 11, 0x0, sum = 2
5295 11:55:30.473666 12, 0x0, sum = 3
5296 11:55:30.476777 13, 0x0, sum = 4
5297 11:55:30.476861 best_step = 11
5298 11:55:30.476946
5299 11:55:30.477043 ==
5300 11:55:30.479947 Dram Type= 6, Freq= 0, CH_0, rank 0
5301 11:55:30.486424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5302 11:55:30.486508 ==
5303 11:55:30.486592 RX Vref Scan: 1
5304 11:55:30.486671
5305 11:55:30.489688 RX Vref 0 -> 0, step: 1
5306 11:55:30.489800
5307 11:55:30.493131 RX Delay -61 -> 252, step: 4
5308 11:55:30.493212
5309 11:55:30.496393 Set Vref, RX VrefLevel [Byte0]: 53
5310 11:55:30.499954 [Byte1]: 59
5311 11:55:30.500046
5312 11:55:30.503349 Final RX Vref Byte 0 = 53 to rank0
5313 11:55:30.506681 Final RX Vref Byte 1 = 59 to rank0
5314 11:55:30.510436 Final RX Vref Byte 0 = 53 to rank1
5315 11:55:30.513311 Final RX Vref Byte 1 = 59 to rank1==
5316 11:55:30.516246 Dram Type= 6, Freq= 0, CH_0, rank 0
5317 11:55:30.519410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5318 11:55:30.523003 ==
5319 11:55:30.523083 DQS Delay:
5320 11:55:30.523145 DQS0 = 0, DQS1 = 0
5321 11:55:30.526218 DQM Delay:
5322 11:55:30.526365 DQM0 = 98, DQM1 = 88
5323 11:55:30.529514 DQ Delay:
5324 11:55:30.532709 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5325 11:55:30.536052 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5326 11:55:30.539293 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =84
5327 11:55:30.542392 DQ12 =96, DQ13 =94, DQ14 =98, DQ15 =94
5328 11:55:30.542472
5329 11:55:30.542535
5330 11:55:30.549525 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5331 11:55:30.552457 CH0 RK0: MR19=505, MR18=1D17
5332 11:55:30.559347 CH0_RK0: MR19=0x505, MR18=0x1D17, DQSOSC=412, MR23=63, INC=63, DEC=42
5333 11:55:30.559467
5334 11:55:30.562187 ----->DramcWriteLeveling(PI) begin...
5335 11:55:30.562343 ==
5336 11:55:30.565683 Dram Type= 6, Freq= 0, CH_0, rank 1
5337 11:55:30.568811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5338 11:55:30.568892 ==
5339 11:55:30.572161 Write leveling (Byte 0): 33 => 33
5340 11:55:30.575620 Write leveling (Byte 1): 27 => 27
5341 11:55:30.579086 DramcWriteLeveling(PI) end<-----
5342 11:55:30.579166
5343 11:55:30.579228 ==
5344 11:55:30.582377 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 11:55:30.585469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 11:55:30.588636 ==
5347 11:55:30.588714 [Gating] SW mode calibration
5348 11:55:30.598397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5349 11:55:30.601669 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5350 11:55:30.605062 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5351 11:55:30.611969 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 11:55:30.615113 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 11:55:30.619042 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 11:55:30.625168 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:55:30.628189 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:55:30.631845 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
5357 11:55:30.638435 0 14 28 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (1 0)
5358 11:55:30.641322 0 15 0 | B1->B0 | 2d2d 2424 | 0 0 | (0 0) (0 0)
5359 11:55:30.645168 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 11:55:30.651531 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 11:55:30.654692 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:55:30.658067 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:55:30.664731 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:55:30.668317 0 15 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
5365 11:55:30.671677 0 15 28 | B1->B0 | 2828 3f3f | 0 0 | (0 0) (0 0)
5366 11:55:30.677809 1 0 0 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5367 11:55:30.681024 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 11:55:30.684489 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 11:55:30.691081 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:55:30.694409 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:55:30.697682 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:55:30.704370 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5373 11:55:30.707548 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5374 11:55:30.710140 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5375 11:55:30.717140 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:55:30.720226 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:55:30.723401 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:55:30.730186 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:55:30.733707 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:55:30.736647 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:55:30.743598 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:55:30.746522 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:55:30.752953 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:55:30.756780 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:55:30.759727 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:55:30.766159 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:55:30.769996 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:55:30.772693 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5389 11:55:30.779634 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5390 11:55:30.779720 Total UI for P1: 0, mck2ui 16
5391 11:55:30.783007 best dqsien dly found for B0: ( 1, 2, 24)
5392 11:55:30.789419 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5393 11:55:30.792638 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 11:55:30.796045 Total UI for P1: 0, mck2ui 16
5395 11:55:30.800009 best dqsien dly found for B1: ( 1, 2, 30)
5396 11:55:30.802568 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5397 11:55:30.806085 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5398 11:55:30.806167
5399 11:55:30.809521 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5400 11:55:30.815658 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5401 11:55:30.815738 [Gating] SW calibration Done
5402 11:55:30.815803 ==
5403 11:55:30.818956 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 11:55:30.825774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 11:55:30.825856 ==
5406 11:55:30.825919 RX Vref Scan: 0
5407 11:55:30.825979
5408 11:55:30.829421 RX Vref 0 -> 0, step: 1
5409 11:55:30.829502
5410 11:55:30.832401 RX Delay -80 -> 252, step: 8
5411 11:55:30.835602 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5412 11:55:30.838607 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5413 11:55:30.842022 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5414 11:55:30.848866 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5415 11:55:30.852164 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5416 11:55:30.855069 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5417 11:55:30.858216 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5418 11:55:30.861668 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5419 11:55:30.865037 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5420 11:55:30.871526 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5421 11:55:30.874855 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5422 11:55:30.878262 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5423 11:55:30.881490 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5424 11:55:30.884639 iDelay=200, Bit 13, Center 99 (8 ~ 191) 184
5425 11:55:30.891339 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5426 11:55:30.894751 iDelay=200, Bit 15, Center 95 (8 ~ 183) 176
5427 11:55:30.894837 ==
5428 11:55:30.897831 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 11:55:30.900964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 11:55:30.901073 ==
5431 11:55:30.901174 DQS Delay:
5432 11:55:30.904177 DQS0 = 0, DQS1 = 0
5433 11:55:30.904274 DQM Delay:
5434 11:55:30.907440 DQM0 = 97, DQM1 = 91
5435 11:55:30.907526 DQ Delay:
5436 11:55:30.911046 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5437 11:55:30.914029 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =103
5438 11:55:30.917447 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5439 11:55:30.920683 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =95
5440 11:55:30.920770
5441 11:55:30.920855
5442 11:55:30.920956 ==
5443 11:55:30.924554 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 11:55:30.930700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 11:55:30.930788 ==
5446 11:55:30.930873
5447 11:55:30.930953
5448 11:55:30.931030 TX Vref Scan disable
5449 11:55:30.934409 == TX Byte 0 ==
5450 11:55:30.937661 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5451 11:55:30.944219 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5452 11:55:30.944324 == TX Byte 1 ==
5453 11:55:30.947525 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5454 11:55:30.953993 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5455 11:55:30.954113 ==
5456 11:55:30.957169 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 11:55:30.960619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 11:55:30.960704 ==
5459 11:55:30.960769
5460 11:55:30.960828
5461 11:55:30.964083 TX Vref Scan disable
5462 11:55:30.967328 == TX Byte 0 ==
5463 11:55:30.970721 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5464 11:55:30.973662 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5465 11:55:30.976750 == TX Byte 1 ==
5466 11:55:30.980228 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5467 11:55:30.983292 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5468 11:55:30.983375
5469 11:55:30.983439 [DATLAT]
5470 11:55:30.987085 Freq=933, CH0 RK1
5471 11:55:30.987167
5472 11:55:30.990038 DATLAT Default: 0xb
5473 11:55:30.990119 0, 0xFFFF, sum = 0
5474 11:55:30.993529 1, 0xFFFF, sum = 0
5475 11:55:30.993612 2, 0xFFFF, sum = 0
5476 11:55:30.996505 3, 0xFFFF, sum = 0
5477 11:55:30.996589 4, 0xFFFF, sum = 0
5478 11:55:31.000076 5, 0xFFFF, sum = 0
5479 11:55:31.000160 6, 0xFFFF, sum = 0
5480 11:55:31.002970 7, 0xFFFF, sum = 0
5481 11:55:31.003052 8, 0xFFFF, sum = 0
5482 11:55:31.006603 9, 0xFFFF, sum = 0
5483 11:55:31.006687 10, 0x0, sum = 1
5484 11:55:31.010293 11, 0x0, sum = 2
5485 11:55:31.010377 12, 0x0, sum = 3
5486 11:55:31.013129 13, 0x0, sum = 4
5487 11:55:31.013212 best_step = 11
5488 11:55:31.013276
5489 11:55:31.013335 ==
5490 11:55:31.016906 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 11:55:31.019729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 11:55:31.023175 ==
5493 11:55:31.023257 RX Vref Scan: 0
5494 11:55:31.023321
5495 11:55:31.026535 RX Vref 0 -> 0, step: 1
5496 11:55:31.026616
5497 11:55:31.029820 RX Delay -53 -> 252, step: 4
5498 11:55:31.032812 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5499 11:55:31.035973 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5500 11:55:31.042447 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5501 11:55:31.045793 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5502 11:55:31.049700 iDelay=195, Bit 4, Center 100 (11 ~ 190) 180
5503 11:55:31.052512 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5504 11:55:31.055968 iDelay=195, Bit 6, Center 104 (15 ~ 194) 180
5505 11:55:31.059040 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5506 11:55:31.065637 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5507 11:55:31.069109 iDelay=195, Bit 9, Center 78 (-5 ~ 162) 168
5508 11:55:31.072459 iDelay=195, Bit 10, Center 92 (3 ~ 182) 180
5509 11:55:31.075848 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5510 11:55:31.079192 iDelay=195, Bit 12, Center 96 (11 ~ 182) 172
5511 11:55:31.085423 iDelay=195, Bit 13, Center 96 (7 ~ 186) 180
5512 11:55:31.088977 iDelay=195, Bit 14, Center 100 (11 ~ 190) 180
5513 11:55:31.092538 iDelay=195, Bit 15, Center 96 (11 ~ 182) 172
5514 11:55:31.092620 ==
5515 11:55:31.095712 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 11:55:31.099243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 11:55:31.099325 ==
5518 11:55:31.101889 DQS Delay:
5519 11:55:31.101970 DQS0 = 0, DQS1 = 0
5520 11:55:31.106070 DQM Delay:
5521 11:55:31.106152 DQM0 = 97, DQM1 = 90
5522 11:55:31.106217 DQ Delay:
5523 11:55:31.108574 DQ0 =94, DQ1 =100, DQ2 =92, DQ3 =94
5524 11:55:31.111990 DQ4 =100, DQ5 =88, DQ6 =104, DQ7 =104
5525 11:55:31.114990 DQ8 =80, DQ9 =78, DQ10 =92, DQ11 =84
5526 11:55:31.118238 DQ12 =96, DQ13 =96, DQ14 =100, DQ15 =96
5527 11:55:31.121884
5528 11:55:31.121965
5529 11:55:31.129112 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5530 11:55:31.132275 CH0 RK1: MR19=505, MR18=1411
5531 11:55:31.138365 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5532 11:55:31.141734 [RxdqsGatingPostProcess] freq 933
5533 11:55:31.144601 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5534 11:55:31.148128 best DQS0 dly(2T, 0.5T) = (0, 10)
5535 11:55:31.151472 best DQS1 dly(2T, 0.5T) = (0, 11)
5536 11:55:31.154856 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5537 11:55:31.157865 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5538 11:55:31.161604 best DQS0 dly(2T, 0.5T) = (0, 10)
5539 11:55:31.164437 best DQS1 dly(2T, 0.5T) = (0, 10)
5540 11:55:31.168078 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5541 11:55:31.170849 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5542 11:55:31.175256 Pre-setting of DQS Precalculation
5543 11:55:31.177484 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5544 11:55:31.180924 ==
5545 11:55:31.181016 Dram Type= 6, Freq= 0, CH_1, rank 0
5546 11:55:31.188003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5547 11:55:31.188088 ==
5548 11:55:31.190548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5549 11:55:31.197186 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5550 11:55:31.201037 [CA 0] Center 36 (6~67) winsize 62
5551 11:55:31.204270 [CA 1] Center 36 (6~67) winsize 62
5552 11:55:31.207921 [CA 2] Center 34 (4~64) winsize 61
5553 11:55:31.210880 [CA 3] Center 33 (3~64) winsize 62
5554 11:55:31.214274 [CA 4] Center 34 (4~64) winsize 61
5555 11:55:31.217356 [CA 5] Center 33 (3~64) winsize 62
5556 11:55:31.217439
5557 11:55:31.220525 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5558 11:55:31.220609
5559 11:55:31.223900 [CATrainingPosCal] consider 1 rank data
5560 11:55:31.227233 u2DelayCellTimex100 = 270/100 ps
5561 11:55:31.233429 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5562 11:55:31.237196 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5563 11:55:31.240081 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5564 11:55:31.243715 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 11:55:31.247051 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5566 11:55:31.249802 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5567 11:55:31.249885
5568 11:55:31.253633 CA PerBit enable=1, Macro0, CA PI delay=33
5569 11:55:31.253717
5570 11:55:31.256584 [CBTSetCACLKResult] CA Dly = 33
5571 11:55:31.259930 CS Dly: 5 (0~36)
5572 11:55:31.260039 ==
5573 11:55:31.263064 Dram Type= 6, Freq= 0, CH_1, rank 1
5574 11:55:31.266227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5575 11:55:31.266351 ==
5576 11:55:31.273042 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5577 11:55:31.279232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5578 11:55:31.282918 [CA 0] Center 36 (6~67) winsize 62
5579 11:55:31.285926 [CA 1] Center 36 (6~67) winsize 62
5580 11:55:31.289390 [CA 2] Center 34 (4~65) winsize 62
5581 11:55:31.292974 [CA 3] Center 33 (3~64) winsize 62
5582 11:55:31.295955 [CA 4] Center 33 (3~64) winsize 62
5583 11:55:31.299310 [CA 5] Center 33 (3~64) winsize 62
5584 11:55:31.299392
5585 11:55:31.302561 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5586 11:55:31.302643
5587 11:55:31.305788 [CATrainingPosCal] consider 2 rank data
5588 11:55:31.309117 u2DelayCellTimex100 = 270/100 ps
5589 11:55:31.312531 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5590 11:55:31.316082 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5591 11:55:31.319045 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5592 11:55:31.322234 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5593 11:55:31.326231 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5594 11:55:31.328951 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5595 11:55:31.329032
5596 11:55:31.335521 CA PerBit enable=1, Macro0, CA PI delay=33
5597 11:55:31.335601
5598 11:55:31.335664 [CBTSetCACLKResult] CA Dly = 33
5599 11:55:31.338966 CS Dly: 6 (0~38)
5600 11:55:31.339046
5601 11:55:31.342143 ----->DramcWriteLeveling(PI) begin...
5602 11:55:31.342257 ==
5603 11:55:31.345502 Dram Type= 6, Freq= 0, CH_1, rank 0
5604 11:55:31.348576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 11:55:31.348658 ==
5606 11:55:31.351795 Write leveling (Byte 0): 23 => 23
5607 11:55:31.355453 Write leveling (Byte 1): 29 => 29
5608 11:55:31.358739 DramcWriteLeveling(PI) end<-----
5609 11:55:31.358819
5610 11:55:31.358882 ==
5611 11:55:31.362122 Dram Type= 6, Freq= 0, CH_1, rank 0
5612 11:55:31.368592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5613 11:55:31.368673 ==
5614 11:55:31.368738 [Gating] SW mode calibration
5615 11:55:31.378607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5616 11:55:31.381939 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5617 11:55:31.387991 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 11:55:31.391174 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 11:55:31.394593 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 11:55:31.401351 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 11:55:31.404949 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 11:55:31.407714 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 11:55:31.414698 0 14 24 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
5624 11:55:31.418833 0 14 28 | B1->B0 | 2828 2626 | 1 0 | (1 0) (0 0)
5625 11:55:31.421001 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 11:55:31.427518 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 11:55:31.430939 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 11:55:31.434082 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 11:55:31.440962 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 11:55:31.444518 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 11:55:31.447797 0 15 24 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
5632 11:55:31.454101 0 15 28 | B1->B0 | 3a3a 4141 | 0 0 | (0 0) (0 0)
5633 11:55:31.457490 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 11:55:31.460817 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 11:55:31.466948 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 11:55:31.470442 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 11:55:31.474209 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:55:31.480247 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:55:31.483430 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5640 11:55:31.486894 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5641 11:55:31.493638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:55:31.497563 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:55:31.500010 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:55:31.506303 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:55:31.509582 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:55:31.513177 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:55:31.519772 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:55:31.522864 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:55:31.526798 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:55:31.532962 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:55:31.535850 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:55:31.539547 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:55:31.545713 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:55:31.549560 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:55:31.553009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:55:31.559347 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5657 11:55:31.562683 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5658 11:55:31.566197 Total UI for P1: 0, mck2ui 16
5659 11:55:31.569312 best dqsien dly found for B0: ( 1, 2, 28)
5660 11:55:31.572406 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5661 11:55:31.575555 Total UI for P1: 0, mck2ui 16
5662 11:55:31.579265 best dqsien dly found for B1: ( 1, 2, 30)
5663 11:55:31.582887 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5664 11:55:31.585778 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5665 11:55:31.586111
5666 11:55:31.592467 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5667 11:55:31.595931 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5668 11:55:31.599053 [Gating] SW calibration Done
5669 11:55:31.599382 ==
5670 11:55:31.602634 Dram Type= 6, Freq= 0, CH_1, rank 0
5671 11:55:31.605589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5672 11:55:31.605926 ==
5673 11:55:31.606235 RX Vref Scan: 0
5674 11:55:31.606499
5675 11:55:31.608814 RX Vref 0 -> 0, step: 1
5676 11:55:31.609057
5677 11:55:31.612508 RX Delay -80 -> 252, step: 8
5678 11:55:31.615627 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5679 11:55:31.618989 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5680 11:55:31.625131 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5681 11:55:31.628777 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5682 11:55:31.631768 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5683 11:55:31.634672 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5684 11:55:31.638998 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5685 11:55:31.641802 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5686 11:55:31.648136 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5687 11:55:31.651648 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5688 11:55:31.654779 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5689 11:55:31.658011 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5690 11:55:31.661544 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5691 11:55:31.668305 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5692 11:55:31.671313 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5693 11:55:31.674821 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5694 11:55:31.674902 ==
5695 11:55:31.677606 Dram Type= 6, Freq= 0, CH_1, rank 0
5696 11:55:31.681068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5697 11:55:31.681150 ==
5698 11:55:31.684744 DQS Delay:
5699 11:55:31.684825 DQS0 = 0, DQS1 = 0
5700 11:55:31.687669 DQM Delay:
5701 11:55:31.687750 DQM0 = 99, DQM1 = 95
5702 11:55:31.687814 DQ Delay:
5703 11:55:31.690981 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5704 11:55:31.694204 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5705 11:55:31.697467 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5706 11:55:31.704090 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5707 11:55:31.704171
5708 11:55:31.704234
5709 11:55:31.704292 ==
5710 11:55:31.707212 Dram Type= 6, Freq= 0, CH_1, rank 0
5711 11:55:31.710219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5712 11:55:31.710349 ==
5713 11:55:31.710413
5714 11:55:31.710472
5715 11:55:31.713930 TX Vref Scan disable
5716 11:55:31.714010 == TX Byte 0 ==
5717 11:55:31.720563 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5718 11:55:31.723735 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5719 11:55:31.723816 == TX Byte 1 ==
5720 11:55:31.730209 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5721 11:55:31.733323 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5722 11:55:31.733403 ==
5723 11:55:31.736597 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 11:55:31.740402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 11:55:31.740483 ==
5726 11:55:31.743461
5727 11:55:31.743541
5728 11:55:31.743604 TX Vref Scan disable
5729 11:55:31.746930 == TX Byte 0 ==
5730 11:55:31.750180 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5731 11:55:31.753339 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5732 11:55:31.756651 == TX Byte 1 ==
5733 11:55:31.759959 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5734 11:55:31.766609 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5735 11:55:31.766690
5736 11:55:31.766753 [DATLAT]
5737 11:55:31.766812 Freq=933, CH1 RK0
5738 11:55:31.766869
5739 11:55:31.769977 DATLAT Default: 0xd
5740 11:55:31.770056 0, 0xFFFF, sum = 0
5741 11:55:31.773725 1, 0xFFFF, sum = 0
5742 11:55:31.776881 2, 0xFFFF, sum = 0
5743 11:55:31.776962 3, 0xFFFF, sum = 0
5744 11:55:31.779926 4, 0xFFFF, sum = 0
5745 11:55:31.780007 5, 0xFFFF, sum = 0
5746 11:55:31.783679 6, 0xFFFF, sum = 0
5747 11:55:31.783759 7, 0xFFFF, sum = 0
5748 11:55:31.786361 8, 0xFFFF, sum = 0
5749 11:55:31.786442 9, 0xFFFF, sum = 0
5750 11:55:31.789582 10, 0x0, sum = 1
5751 11:55:31.789662 11, 0x0, sum = 2
5752 11:55:31.793532 12, 0x0, sum = 3
5753 11:55:31.793613 13, 0x0, sum = 4
5754 11:55:31.793678 best_step = 11
5755 11:55:31.796670
5756 11:55:31.796749 ==
5757 11:55:31.799640 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 11:55:31.803362 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 11:55:31.803442 ==
5760 11:55:31.803506 RX Vref Scan: 1
5761 11:55:31.803564
5762 11:55:31.806133 RX Vref 0 -> 0, step: 1
5763 11:55:31.806254
5764 11:55:31.809545 RX Delay -53 -> 252, step: 4
5765 11:55:31.809626
5766 11:55:31.812638 Set Vref, RX VrefLevel [Byte0]: 51
5767 11:55:31.816486 [Byte1]: 51
5768 11:55:31.819613
5769 11:55:31.819694 Final RX Vref Byte 0 = 51 to rank0
5770 11:55:31.822661 Final RX Vref Byte 1 = 51 to rank0
5771 11:55:31.826412 Final RX Vref Byte 0 = 51 to rank1
5772 11:55:31.829523 Final RX Vref Byte 1 = 51 to rank1==
5773 11:55:31.832566 Dram Type= 6, Freq= 0, CH_1, rank 0
5774 11:55:31.839188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5775 11:55:31.839268 ==
5776 11:55:31.839331 DQS Delay:
5777 11:55:31.839390 DQS0 = 0, DQS1 = 0
5778 11:55:31.842669 DQM Delay:
5779 11:55:31.842749 DQM0 = 98, DQM1 = 94
5780 11:55:31.845535 DQ Delay:
5781 11:55:31.849155 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =98
5782 11:55:31.852280 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5783 11:55:31.855512 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5784 11:55:31.859008 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5785 11:55:31.859089
5786 11:55:31.859152
5787 11:55:31.865904 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5788 11:55:31.869246 CH1 RK0: MR19=505, MR18=C1C
5789 11:55:31.875452 CH1_RK0: MR19=0x505, MR18=0xC1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5790 11:55:31.875532
5791 11:55:31.878634 ----->DramcWriteLeveling(PI) begin...
5792 11:55:31.878727 ==
5793 11:55:31.882005 Dram Type= 6, Freq= 0, CH_1, rank 1
5794 11:55:31.885690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 11:55:31.885771 ==
5796 11:55:31.888604 Write leveling (Byte 0): 26 => 26
5797 11:55:31.891636 Write leveling (Byte 1): 29 => 29
5798 11:55:31.895444 DramcWriteLeveling(PI) end<-----
5799 11:55:31.895524
5800 11:55:31.895587 ==
5801 11:55:31.898729 Dram Type= 6, Freq= 0, CH_1, rank 1
5802 11:55:31.905435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5803 11:55:31.905515 ==
5804 11:55:31.905578 [Gating] SW mode calibration
5805 11:55:31.915139 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5806 11:55:31.918192 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5807 11:55:31.924460 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 11:55:31.928081 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 11:55:31.931664 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5810 11:55:31.937878 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 11:55:31.941063 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 11:55:31.944584 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 11:55:31.951055 0 14 24 | B1->B0 | 3131 2d2d | 1 0 | (1 1) (0 0)
5814 11:55:31.954092 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5815 11:55:31.958199 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 11:55:31.964806 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 11:55:31.967347 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5818 11:55:31.970707 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 11:55:31.977699 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 11:55:31.981131 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 11:55:31.984389 0 15 24 | B1->B0 | 2525 2f2e | 0 1 | (0 0) (0 0)
5822 11:55:31.990595 0 15 28 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5823 11:55:31.993517 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 11:55:31.996887 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 11:55:32.003367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 11:55:32.007500 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 11:55:32.009953 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 11:55:32.017077 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:55:32.020246 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 11:55:32.023223 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5831 11:55:32.030060 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:55:32.033472 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:55:32.036529 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:55:32.043141 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:55:32.046741 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:55:32.049752 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:55:32.056822 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:55:32.060375 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:55:32.063131 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:55:32.070019 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:55:32.073531 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:55:32.076166 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:55:32.083263 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:55:32.085857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:55:32.089508 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5846 11:55:32.096139 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5847 11:55:32.096221 Total UI for P1: 0, mck2ui 16
5848 11:55:32.103015 best dqsien dly found for B0: ( 1, 2, 24)
5849 11:55:32.106124 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 11:55:32.109364 Total UI for P1: 0, mck2ui 16
5851 11:55:32.112394 best dqsien dly found for B1: ( 1, 2, 28)
5852 11:55:32.116146 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5853 11:55:32.119463 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5854 11:55:32.119544
5855 11:55:32.122494 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5856 11:55:32.125464 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5857 11:55:32.129429 [Gating] SW calibration Done
5858 11:55:32.129523 ==
5859 11:55:32.132855 Dram Type= 6, Freq= 0, CH_1, rank 1
5860 11:55:32.135538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5861 11:55:32.139552 ==
5862 11:55:32.139636 RX Vref Scan: 0
5863 11:55:32.139700
5864 11:55:32.142092 RX Vref 0 -> 0, step: 1
5865 11:55:32.142198
5866 11:55:32.142342 RX Delay -80 -> 252, step: 8
5867 11:55:32.148853 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5868 11:55:32.152068 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5869 11:55:32.156099 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5870 11:55:32.158994 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5871 11:55:32.162521 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5872 11:55:32.165718 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5873 11:55:32.172204 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5874 11:55:32.175382 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5875 11:55:32.178414 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5876 11:55:32.181729 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5877 11:55:32.185076 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5878 11:55:32.192553 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5879 11:55:32.194798 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5880 11:55:32.198363 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5881 11:55:32.202218 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5882 11:55:32.204603 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5883 11:55:32.208235 ==
5884 11:55:32.208316 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:55:32.214819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:55:32.214900 ==
5887 11:55:32.214963 DQS Delay:
5888 11:55:32.218213 DQS0 = 0, DQS1 = 0
5889 11:55:32.218333 DQM Delay:
5890 11:55:32.221398 DQM0 = 97, DQM1 = 94
5891 11:55:32.221478 DQ Delay:
5892 11:55:32.224397 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5893 11:55:32.227712 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5894 11:55:32.231050 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5895 11:55:32.234657 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5896 11:55:32.234737
5897 11:55:32.234799
5898 11:55:32.234863 ==
5899 11:55:32.237727 Dram Type= 6, Freq= 0, CH_1, rank 1
5900 11:55:32.241143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5901 11:55:32.244094 ==
5902 11:55:32.244174
5903 11:55:32.244236
5904 11:55:32.244294 TX Vref Scan disable
5905 11:55:32.247348 == TX Byte 0 ==
5906 11:55:32.251050 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5907 11:55:32.254546 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5908 11:55:32.257535 == TX Byte 1 ==
5909 11:55:32.260668 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5910 11:55:32.264657 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5911 11:55:32.267298 ==
5912 11:55:32.270763 Dram Type= 6, Freq= 0, CH_1, rank 1
5913 11:55:32.273943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5914 11:55:32.274023 ==
5915 11:55:32.274087
5916 11:55:32.274144
5917 11:55:32.277441 TX Vref Scan disable
5918 11:55:32.277521 == TX Byte 0 ==
5919 11:55:32.283954 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5920 11:55:32.286953 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5921 11:55:32.287034 == TX Byte 1 ==
5922 11:55:32.293207 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5923 11:55:32.296474 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5924 11:55:32.296553
5925 11:55:32.296617 [DATLAT]
5926 11:55:32.300092 Freq=933, CH1 RK1
5927 11:55:32.300172
5928 11:55:32.300236 DATLAT Default: 0xb
5929 11:55:32.303480 0, 0xFFFF, sum = 0
5930 11:55:32.303561 1, 0xFFFF, sum = 0
5931 11:55:32.306948 2, 0xFFFF, sum = 0
5932 11:55:32.309927 3, 0xFFFF, sum = 0
5933 11:55:32.310008 4, 0xFFFF, sum = 0
5934 11:55:32.313054 5, 0xFFFF, sum = 0
5935 11:55:32.313135 6, 0xFFFF, sum = 0
5936 11:55:32.316395 7, 0xFFFF, sum = 0
5937 11:55:32.316476 8, 0xFFFF, sum = 0
5938 11:55:32.319584 9, 0xFFFF, sum = 0
5939 11:55:32.319666 10, 0x0, sum = 1
5940 11:55:32.323046 11, 0x0, sum = 2
5941 11:55:32.323127 12, 0x0, sum = 3
5942 11:55:32.326175 13, 0x0, sum = 4
5943 11:55:32.326262 best_step = 11
5944 11:55:32.326328
5945 11:55:32.326386 ==
5946 11:55:32.329722 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 11:55:32.332705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 11:55:32.332785 ==
5949 11:55:32.335984 RX Vref Scan: 0
5950 11:55:32.336064
5951 11:55:32.339547 RX Vref 0 -> 0, step: 1
5952 11:55:32.339627
5953 11:55:32.339691 RX Delay -53 -> 252, step: 4
5954 11:55:32.347579 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5955 11:55:32.350558 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5956 11:55:32.354551 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5957 11:55:32.357019 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5958 11:55:32.361139 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
5959 11:55:32.366884 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5960 11:55:32.370418 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5961 11:55:32.373877 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5962 11:55:32.377103 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5963 11:55:32.380514 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5964 11:55:32.386995 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5965 11:55:32.390652 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
5966 11:55:32.393610 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5967 11:55:32.397201 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5968 11:55:32.400438 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5969 11:55:32.406865 iDelay=199, Bit 15, Center 100 (7 ~ 194) 188
5970 11:55:32.406946 ==
5971 11:55:32.409874 Dram Type= 6, Freq= 0, CH_1, rank 1
5972 11:55:32.413621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5973 11:55:32.413703 ==
5974 11:55:32.413768 DQS Delay:
5975 11:55:32.417034 DQS0 = 0, DQS1 = 0
5976 11:55:32.417115 DQM Delay:
5977 11:55:32.420125 DQM0 = 96, DQM1 = 92
5978 11:55:32.420206 DQ Delay:
5979 11:55:32.423706 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =92
5980 11:55:32.426642 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
5981 11:55:32.430136 DQ8 =78, DQ9 =84, DQ10 =92, DQ11 =86
5982 11:55:32.432937 DQ12 =100, DQ13 =100, DQ14 =98, DQ15 =100
5983 11:55:32.433018
5984 11:55:32.433081
5985 11:55:32.443242 [DQSOSCAuto] RK1, (LSB)MR18= 0xd23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5986 11:55:32.443325 CH1 RK1: MR19=505, MR18=D23
5987 11:55:32.449725 CH1_RK1: MR19=0x505, MR18=0xD23, DQSOSC=410, MR23=63, INC=64, DEC=42
5988 11:55:32.453191 [RxdqsGatingPostProcess] freq 933
5989 11:55:32.459921 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5990 11:55:32.462770 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 11:55:32.466280 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 11:55:32.469106 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 11:55:32.472798 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 11:55:32.476290 best DQS0 dly(2T, 0.5T) = (0, 10)
5995 11:55:32.478938 best DQS1 dly(2T, 0.5T) = (0, 10)
5996 11:55:32.482915 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5997 11:55:32.486108 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5998 11:55:32.486189 Pre-setting of DQS Precalculation
5999 11:55:32.492301 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6000 11:55:32.499258 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6001 11:55:32.506257 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6002 11:55:32.506338
6003 11:55:32.506402
6004 11:55:32.508977 [Calibration Summary] 1866 Mbps
6005 11:55:32.512642 CH 0, Rank 0
6006 11:55:32.512722 SW Impedance : PASS
6007 11:55:32.515545 DUTY Scan : NO K
6008 11:55:32.519176 ZQ Calibration : PASS
6009 11:55:32.519256 Jitter Meter : NO K
6010 11:55:32.522131 CBT Training : PASS
6011 11:55:32.522212 Write leveling : PASS
6012 11:55:32.525946 RX DQS gating : PASS
6013 11:55:32.528845 RX DQ/DQS(RDDQC) : PASS
6014 11:55:32.528930 TX DQ/DQS : PASS
6015 11:55:32.532123 RX DATLAT : PASS
6016 11:55:32.535684 RX DQ/DQS(Engine): PASS
6017 11:55:32.535764 TX OE : NO K
6018 11:55:32.539155 All Pass.
6019 11:55:32.539236
6020 11:55:32.539299 CH 0, Rank 1
6021 11:55:32.541878 SW Impedance : PASS
6022 11:55:32.541958 DUTY Scan : NO K
6023 11:55:32.545625 ZQ Calibration : PASS
6024 11:55:32.548726 Jitter Meter : NO K
6025 11:55:32.548807 CBT Training : PASS
6026 11:55:32.552297 Write leveling : PASS
6027 11:55:32.555605 RX DQS gating : PASS
6028 11:55:32.555686 RX DQ/DQS(RDDQC) : PASS
6029 11:55:32.558785 TX DQ/DQS : PASS
6030 11:55:32.562434 RX DATLAT : PASS
6031 11:55:32.562515 RX DQ/DQS(Engine): PASS
6032 11:55:32.565377 TX OE : NO K
6033 11:55:32.565459 All Pass.
6034 11:55:32.565522
6035 11:55:32.568754 CH 1, Rank 0
6036 11:55:32.568834 SW Impedance : PASS
6037 11:55:32.572543 DUTY Scan : NO K
6038 11:55:32.575505 ZQ Calibration : PASS
6039 11:55:32.575586 Jitter Meter : NO K
6040 11:55:32.578747 CBT Training : PASS
6041 11:55:32.581672 Write leveling : PASS
6042 11:55:32.581753 RX DQS gating : PASS
6043 11:55:32.584874 RX DQ/DQS(RDDQC) : PASS
6044 11:55:32.588360 TX DQ/DQS : PASS
6045 11:55:32.588441 RX DATLAT : PASS
6046 11:55:32.591773 RX DQ/DQS(Engine): PASS
6047 11:55:32.594660 TX OE : NO K
6048 11:55:32.594741 All Pass.
6049 11:55:32.594805
6050 11:55:32.594863 CH 1, Rank 1
6051 11:55:32.598067 SW Impedance : PASS
6052 11:55:32.601471 DUTY Scan : NO K
6053 11:55:32.601565 ZQ Calibration : PASS
6054 11:55:32.604428 Jitter Meter : NO K
6055 11:55:32.604510 CBT Training : PASS
6056 11:55:32.608018 Write leveling : PASS
6057 11:55:32.611550 RX DQS gating : PASS
6058 11:55:32.611632 RX DQ/DQS(RDDQC) : PASS
6059 11:55:32.614761 TX DQ/DQS : PASS
6060 11:55:32.618182 RX DATLAT : PASS
6061 11:55:32.618292 RX DQ/DQS(Engine): PASS
6062 11:55:32.620983 TX OE : NO K
6063 11:55:32.621064 All Pass.
6064 11:55:32.621127
6065 11:55:32.624285 DramC Write-DBI off
6066 11:55:32.628129 PER_BANK_REFRESH: Hybrid Mode
6067 11:55:32.628209 TX_TRACKING: ON
6068 11:55:32.637983 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6069 11:55:32.640924 [FAST_K] Save calibration result to emmc
6070 11:55:32.644238 dramc_set_vcore_voltage set vcore to 650000
6071 11:55:32.647126 Read voltage for 400, 6
6072 11:55:32.647207 Vio18 = 0
6073 11:55:32.650514 Vcore = 650000
6074 11:55:32.650594 Vdram = 0
6075 11:55:32.650658 Vddq = 0
6076 11:55:32.650716 Vmddr = 0
6077 11:55:32.656921 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6078 11:55:32.663787 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6079 11:55:32.663870 MEM_TYPE=3, freq_sel=20
6080 11:55:32.667195 sv_algorithm_assistance_LP4_800
6081 11:55:32.670633 ============ PULL DRAM RESETB DOWN ============
6082 11:55:32.676628 ========== PULL DRAM RESETB DOWN end =========
6083 11:55:32.680369 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6084 11:55:32.683421 ===================================
6085 11:55:32.686974 LPDDR4 DRAM CONFIGURATION
6086 11:55:32.689961 ===================================
6087 11:55:32.690042 EX_ROW_EN[0] = 0x0
6088 11:55:32.693398 EX_ROW_EN[1] = 0x0
6089 11:55:32.696520 LP4Y_EN = 0x0
6090 11:55:32.696600 WORK_FSP = 0x0
6091 11:55:32.700025 WL = 0x2
6092 11:55:32.700104 RL = 0x2
6093 11:55:32.703228 BL = 0x2
6094 11:55:32.703307 RPST = 0x0
6095 11:55:32.706169 RD_PRE = 0x0
6096 11:55:32.706255 WR_PRE = 0x1
6097 11:55:32.709918 WR_PST = 0x0
6098 11:55:32.709997 DBI_WR = 0x0
6099 11:55:32.713092 DBI_RD = 0x0
6100 11:55:32.713170 OTF = 0x1
6101 11:55:32.716175 ===================================
6102 11:55:32.719406 ===================================
6103 11:55:32.722541 ANA top config
6104 11:55:32.726737 ===================================
6105 11:55:32.729229 DLL_ASYNC_EN = 0
6106 11:55:32.729325 ALL_SLAVE_EN = 1
6107 11:55:32.732529 NEW_RANK_MODE = 1
6108 11:55:32.735746 DLL_IDLE_MODE = 1
6109 11:55:32.739197 LP45_APHY_COMB_EN = 1
6110 11:55:32.739294 TX_ODT_DIS = 1
6111 11:55:32.742751 NEW_8X_MODE = 1
6112 11:55:32.745787 ===================================
6113 11:55:32.749224 ===================================
6114 11:55:32.752251 data_rate = 800
6115 11:55:32.756359 CKR = 1
6116 11:55:32.759133 DQ_P2S_RATIO = 4
6117 11:55:32.762119 ===================================
6118 11:55:32.765489 CA_P2S_RATIO = 4
6119 11:55:32.765569 DQ_CA_OPEN = 0
6120 11:55:32.768910 DQ_SEMI_OPEN = 1
6121 11:55:32.772291 CA_SEMI_OPEN = 1
6122 11:55:32.775391 CA_FULL_RATE = 0
6123 11:55:32.778651 DQ_CKDIV4_EN = 0
6124 11:55:32.782117 CA_CKDIV4_EN = 1
6125 11:55:32.785222 CA_PREDIV_EN = 0
6126 11:55:32.785301 PH8_DLY = 0
6127 11:55:32.788853 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6128 11:55:32.792639 DQ_AAMCK_DIV = 0
6129 11:55:32.795165 CA_AAMCK_DIV = 0
6130 11:55:32.798224 CA_ADMCK_DIV = 4
6131 11:55:32.802196 DQ_TRACK_CA_EN = 0
6132 11:55:32.802314 CA_PICK = 800
6133 11:55:32.805310 CA_MCKIO = 400
6134 11:55:32.808253 MCKIO_SEMI = 400
6135 11:55:32.811920 PLL_FREQ = 3016
6136 11:55:32.815274 DQ_UI_PI_RATIO = 32
6137 11:55:32.818346 CA_UI_PI_RATIO = 32
6138 11:55:32.821905 ===================================
6139 11:55:32.824827 ===================================
6140 11:55:32.828138 memory_type:LPDDR4
6141 11:55:32.828218 GP_NUM : 10
6142 11:55:32.831618 SRAM_EN : 1
6143 11:55:32.831698 MD32_EN : 0
6144 11:55:32.834932 ===================================
6145 11:55:32.838883 [ANA_INIT] >>>>>>>>>>>>>>
6146 11:55:32.841780 <<<<<< [CONFIGURE PHASE]: ANA_TX
6147 11:55:32.844688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6148 11:55:32.848099 ===================================
6149 11:55:32.851202 data_rate = 800,PCW = 0X7400
6150 11:55:32.854786 ===================================
6151 11:55:32.857945 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6152 11:55:32.864516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6153 11:55:32.874460 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6154 11:55:32.877899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6155 11:55:32.881512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6156 11:55:32.884005 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6157 11:55:32.887333 [ANA_INIT] flow start
6158 11:55:32.891047 [ANA_INIT] PLL >>>>>>>>
6159 11:55:32.891127 [ANA_INIT] PLL <<<<<<<<
6160 11:55:32.893855 [ANA_INIT] MIDPI >>>>>>>>
6161 11:55:32.897357 [ANA_INIT] MIDPI <<<<<<<<
6162 11:55:32.900465 [ANA_INIT] DLL >>>>>>>>
6163 11:55:32.900543 [ANA_INIT] flow end
6164 11:55:32.903688 ============ LP4 DIFF to SE enter ============
6165 11:55:32.910373 ============ LP4 DIFF to SE exit ============
6166 11:55:32.910453 [ANA_INIT] <<<<<<<<<<<<<
6167 11:55:32.913858 [Flow] Enable top DCM control >>>>>
6168 11:55:32.917556 [Flow] Enable top DCM control <<<<<
6169 11:55:32.920799 Enable DLL master slave shuffle
6170 11:55:32.926922 ==============================================================
6171 11:55:32.930375 Gating Mode config
6172 11:55:32.934133 ==============================================================
6173 11:55:32.936720 Config description:
6174 11:55:32.946759 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6175 11:55:32.954204 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6176 11:55:32.957314 SELPH_MODE 0: By rank 1: By Phase
6177 11:55:32.963469 ==============================================================
6178 11:55:32.966445 GAT_TRACK_EN = 0
6179 11:55:32.969843 RX_GATING_MODE = 2
6180 11:55:32.973090 RX_GATING_TRACK_MODE = 2
6181 11:55:32.973169 SELPH_MODE = 1
6182 11:55:32.977115 PICG_EARLY_EN = 1
6183 11:55:32.979987 VALID_LAT_VALUE = 1
6184 11:55:32.986465 ==============================================================
6185 11:55:32.989658 Enter into Gating configuration >>>>
6186 11:55:32.993088 Exit from Gating configuration <<<<
6187 11:55:32.996397 Enter into DVFS_PRE_config >>>>>
6188 11:55:33.006547 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6189 11:55:33.009923 Exit from DVFS_PRE_config <<<<<
6190 11:55:33.012689 Enter into PICG configuration >>>>
6191 11:55:33.016317 Exit from PICG configuration <<<<
6192 11:55:33.019474 [RX_INPUT] configuration >>>>>
6193 11:55:33.022515 [RX_INPUT] configuration <<<<<
6194 11:55:33.029255 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6195 11:55:33.032875 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6196 11:55:33.038972 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6197 11:55:33.046030 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6198 11:55:33.052199 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 11:55:33.059131 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 11:55:33.062962 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6201 11:55:33.065790 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6202 11:55:33.068747 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6203 11:55:33.075385 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6204 11:55:33.078513 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6205 11:55:33.082243 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6206 11:55:33.085437 ===================================
6207 11:55:33.088424 LPDDR4 DRAM CONFIGURATION
6208 11:55:33.091923 ===================================
6209 11:55:33.092004 EX_ROW_EN[0] = 0x0
6210 11:55:33.095342 EX_ROW_EN[1] = 0x0
6211 11:55:33.098706 LP4Y_EN = 0x0
6212 11:55:33.098786 WORK_FSP = 0x0
6213 11:55:33.101683 WL = 0x2
6214 11:55:33.101799 RL = 0x2
6215 11:55:33.104905 BL = 0x2
6216 11:55:33.104984 RPST = 0x0
6217 11:55:33.107919 RD_PRE = 0x0
6218 11:55:33.107999 WR_PRE = 0x1
6219 11:55:33.111398 WR_PST = 0x0
6220 11:55:33.111478 DBI_WR = 0x0
6221 11:55:33.115044 DBI_RD = 0x0
6222 11:55:33.115124 OTF = 0x1
6223 11:55:33.118212 ===================================
6224 11:55:33.124677 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6225 11:55:33.127918 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6226 11:55:33.131137 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6227 11:55:33.134819 ===================================
6228 11:55:33.137614 LPDDR4 DRAM CONFIGURATION
6229 11:55:33.141791 ===================================
6230 11:55:33.144703 EX_ROW_EN[0] = 0x10
6231 11:55:33.144783 EX_ROW_EN[1] = 0x0
6232 11:55:33.147430 LP4Y_EN = 0x0
6233 11:55:33.147510 WORK_FSP = 0x0
6234 11:55:33.150919 WL = 0x2
6235 11:55:33.150999 RL = 0x2
6236 11:55:33.154101 BL = 0x2
6237 11:55:33.154212 RPST = 0x0
6238 11:55:33.157679 RD_PRE = 0x0
6239 11:55:33.157759 WR_PRE = 0x1
6240 11:55:33.160705 WR_PST = 0x0
6241 11:55:33.160785 DBI_WR = 0x0
6242 11:55:33.164622 DBI_RD = 0x0
6243 11:55:33.164701 OTF = 0x1
6244 11:55:33.167314 ===================================
6245 11:55:33.174077 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6246 11:55:33.178955 nWR fixed to 30
6247 11:55:33.181902 [ModeRegInit_LP4] CH0 RK0
6248 11:55:33.181982 [ModeRegInit_LP4] CH0 RK1
6249 11:55:33.185331 [ModeRegInit_LP4] CH1 RK0
6250 11:55:33.188469 [ModeRegInit_LP4] CH1 RK1
6251 11:55:33.188549 match AC timing 19
6252 11:55:33.195866 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6253 11:55:33.198493 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6254 11:55:33.202403 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6255 11:55:33.208728 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6256 11:55:33.211764 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6257 11:55:33.211912 ==
6258 11:55:33.214817 Dram Type= 6, Freq= 0, CH_0, rank 0
6259 11:55:33.218652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6260 11:55:33.218734 ==
6261 11:55:33.224790 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6262 11:55:33.231576 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6263 11:55:33.234859 [CA 0] Center 36 (8~64) winsize 57
6264 11:55:33.238239 [CA 1] Center 36 (8~64) winsize 57
6265 11:55:33.241267 [CA 2] Center 36 (8~64) winsize 57
6266 11:55:33.244353 [CA 3] Center 36 (8~64) winsize 57
6267 11:55:33.247928 [CA 4] Center 36 (8~64) winsize 57
6268 11:55:33.251454 [CA 5] Center 36 (8~64) winsize 57
6269 11:55:33.251534
6270 11:55:33.254438 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6271 11:55:33.254519
6272 11:55:33.257841 [CATrainingPosCal] consider 1 rank data
6273 11:55:33.261322 u2DelayCellTimex100 = 270/100 ps
6274 11:55:33.264617 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:55:33.268024 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:55:33.271412 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:55:33.274208 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:55:33.277347 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:55:33.280523 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:55:33.280603
6281 11:55:33.287322 CA PerBit enable=1, Macro0, CA PI delay=36
6282 11:55:33.287403
6283 11:55:33.290660 [CBTSetCACLKResult] CA Dly = 36
6284 11:55:33.290741 CS Dly: 1 (0~32)
6285 11:55:33.290805 ==
6286 11:55:33.293905 Dram Type= 6, Freq= 0, CH_0, rank 1
6287 11:55:33.297072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 11:55:33.297158 ==
6289 11:55:33.303885 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6290 11:55:33.310360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6291 11:55:33.313552 [CA 0] Center 36 (8~64) winsize 57
6292 11:55:33.317127 [CA 1] Center 36 (8~64) winsize 57
6293 11:55:33.320192 [CA 2] Center 36 (8~64) winsize 57
6294 11:55:33.323668 [CA 3] Center 36 (8~64) winsize 57
6295 11:55:33.326536 [CA 4] Center 36 (8~64) winsize 57
6296 11:55:33.330242 [CA 5] Center 36 (8~64) winsize 57
6297 11:55:33.330365
6298 11:55:33.333146 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6299 11:55:33.333226
6300 11:55:33.336747 [CATrainingPosCal] consider 2 rank data
6301 11:55:33.339920 u2DelayCellTimex100 = 270/100 ps
6302 11:55:33.343386 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 11:55:33.346621 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 11:55:33.349888 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:55:33.354033 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:55:33.356813 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:55:33.359778 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:55:33.359859
6309 11:55:33.366399 CA PerBit enable=1, Macro0, CA PI delay=36
6310 11:55:33.366480
6311 11:55:33.366544 [CBTSetCACLKResult] CA Dly = 36
6312 11:55:33.369530 CS Dly: 1 (0~32)
6313 11:55:33.369611
6314 11:55:33.373102 ----->DramcWriteLeveling(PI) begin...
6315 11:55:33.373184 ==
6316 11:55:33.375957 Dram Type= 6, Freq= 0, CH_0, rank 0
6317 11:55:33.379384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6318 11:55:33.379466 ==
6319 11:55:33.382831 Write leveling (Byte 0): 40 => 8
6320 11:55:33.386043 Write leveling (Byte 1): 40 => 8
6321 11:55:33.389233 DramcWriteLeveling(PI) end<-----
6322 11:55:33.389313
6323 11:55:33.389375 ==
6324 11:55:33.392594 Dram Type= 6, Freq= 0, CH_0, rank 0
6325 11:55:33.396116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6326 11:55:33.399716 ==
6327 11:55:33.399797 [Gating] SW mode calibration
6328 11:55:33.408995 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6329 11:55:33.412732 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6330 11:55:33.415456 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6331 11:55:33.422477 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6332 11:55:33.425433 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6333 11:55:33.429198 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6334 11:55:33.435569 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6335 11:55:33.439193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6336 11:55:33.442469 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 11:55:33.448626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 11:55:33.452475 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6339 11:55:33.455716 Total UI for P1: 0, mck2ui 16
6340 11:55:33.458698 best dqsien dly found for B0: ( 0, 14, 24)
6341 11:55:33.461881 Total UI for P1: 0, mck2ui 16
6342 11:55:33.465134 best dqsien dly found for B1: ( 0, 14, 24)
6343 11:55:33.468496 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6344 11:55:33.471929 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6345 11:55:33.472010
6346 11:55:33.475099 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6347 11:55:33.481903 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6348 11:55:33.481983 [Gating] SW calibration Done
6349 11:55:33.482047 ==
6350 11:55:33.484760 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 11:55:33.491638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 11:55:33.491718 ==
6353 11:55:33.491781 RX Vref Scan: 0
6354 11:55:33.491839
6355 11:55:33.494602 RX Vref 0 -> 0, step: 1
6356 11:55:33.494681
6357 11:55:33.498420 RX Delay -410 -> 252, step: 16
6358 11:55:33.501384 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6359 11:55:33.504491 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6360 11:55:33.510967 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6361 11:55:33.514353 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6362 11:55:33.518013 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6363 11:55:33.521071 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6364 11:55:33.527797 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6365 11:55:33.531174 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6366 11:55:33.534201 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6367 11:55:33.537743 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6368 11:55:33.544217 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6369 11:55:33.547779 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6370 11:55:33.550725 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6371 11:55:33.557983 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6372 11:55:33.561310 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6373 11:55:33.564109 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6374 11:55:33.564189 ==
6375 11:55:33.567482 Dram Type= 6, Freq= 0, CH_0, rank 0
6376 11:55:33.570956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6377 11:55:33.574096 ==
6378 11:55:33.574176 DQS Delay:
6379 11:55:33.574238 DQS0 = 35, DQS1 = 51
6380 11:55:33.577382 DQM Delay:
6381 11:55:33.577461 DQM0 = 7, DQM1 = 10
6382 11:55:33.581291 DQ Delay:
6383 11:55:33.581370 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6384 11:55:33.583799 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6385 11:55:33.588040 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6386 11:55:33.590418 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6387 11:55:33.590522
6388 11:55:33.590612
6389 11:55:33.590673 ==
6390 11:55:33.594107 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 11:55:33.600747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 11:55:33.600829 ==
6393 11:55:33.600892
6394 11:55:33.600951
6395 11:55:33.604005 TX Vref Scan disable
6396 11:55:33.604085 == TX Byte 0 ==
6397 11:55:33.607302 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6398 11:55:33.610051 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6399 11:55:33.613739 == TX Byte 1 ==
6400 11:55:33.616786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6401 11:55:33.620054 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6402 11:55:33.623320 ==
6403 11:55:33.626594 Dram Type= 6, Freq= 0, CH_0, rank 0
6404 11:55:33.630386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6405 11:55:33.630478 ==
6406 11:55:33.630542
6407 11:55:33.630601
6408 11:55:33.633568 TX Vref Scan disable
6409 11:55:33.633648 == TX Byte 0 ==
6410 11:55:33.636733 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 11:55:33.643078 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 11:55:33.643160 == TX Byte 1 ==
6413 11:55:33.646481 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6414 11:55:33.653287 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6415 11:55:33.653370
6416 11:55:33.653433 [DATLAT]
6417 11:55:33.653493 Freq=400, CH0 RK0
6418 11:55:33.653551
6419 11:55:33.656511 DATLAT Default: 0xf
6420 11:55:33.659518 0, 0xFFFF, sum = 0
6421 11:55:33.659601 1, 0xFFFF, sum = 0
6422 11:55:33.663121 2, 0xFFFF, sum = 0
6423 11:55:33.663203 3, 0xFFFF, sum = 0
6424 11:55:33.666119 4, 0xFFFF, sum = 0
6425 11:55:33.666201 5, 0xFFFF, sum = 0
6426 11:55:33.669896 6, 0xFFFF, sum = 0
6427 11:55:33.669978 7, 0xFFFF, sum = 0
6428 11:55:33.673356 8, 0xFFFF, sum = 0
6429 11:55:33.673439 9, 0xFFFF, sum = 0
6430 11:55:33.676158 10, 0xFFFF, sum = 0
6431 11:55:33.676239 11, 0xFFFF, sum = 0
6432 11:55:33.679343 12, 0xFFFF, sum = 0
6433 11:55:33.679425 13, 0x0, sum = 1
6434 11:55:33.682984 14, 0x0, sum = 2
6435 11:55:33.683066 15, 0x0, sum = 3
6436 11:55:33.686134 16, 0x0, sum = 4
6437 11:55:33.686217 best_step = 14
6438 11:55:33.686300
6439 11:55:33.686362 ==
6440 11:55:33.689283 Dram Type= 6, Freq= 0, CH_0, rank 0
6441 11:55:33.695855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 11:55:33.695936 ==
6443 11:55:33.696000 RX Vref Scan: 1
6444 11:55:33.696061
6445 11:55:33.699418 RX Vref 0 -> 0, step: 1
6446 11:55:33.699501
6447 11:55:33.702378 RX Delay -343 -> 252, step: 8
6448 11:55:33.702459
6449 11:55:33.705730 Set Vref, RX VrefLevel [Byte0]: 53
6450 11:55:33.709060 [Byte1]: 59
6451 11:55:33.709141
6452 11:55:33.712186 Final RX Vref Byte 0 = 53 to rank0
6453 11:55:33.715632 Final RX Vref Byte 1 = 59 to rank0
6454 11:55:33.719580 Final RX Vref Byte 0 = 53 to rank1
6455 11:55:33.722199 Final RX Vref Byte 1 = 59 to rank1==
6456 11:55:33.725633 Dram Type= 6, Freq= 0, CH_0, rank 0
6457 11:55:33.728935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6458 11:55:33.732356 ==
6459 11:55:33.732437 DQS Delay:
6460 11:55:33.732502 DQS0 = 44, DQS1 = 60
6461 11:55:33.735270 DQM Delay:
6462 11:55:33.735351 DQM0 = 10, DQM1 = 15
6463 11:55:33.738992 DQ Delay:
6464 11:55:33.742754 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6465 11:55:33.742836 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6466 11:55:33.745518 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6467 11:55:33.748367 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6468 11:55:33.748466
6469 11:55:33.752067
6470 11:55:33.758509 [DQSOSCAuto] RK0, (LSB)MR18= 0x9286, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6471 11:55:33.761761 CH0 RK0: MR19=C0C, MR18=9286
6472 11:55:33.768166 CH0_RK0: MR19=0xC0C, MR18=0x9286, DQSOSC=391, MR23=63, INC=386, DEC=257
6473 11:55:33.768247 ==
6474 11:55:33.771898 Dram Type= 6, Freq= 0, CH_0, rank 1
6475 11:55:33.774720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 11:55:33.774801 ==
6477 11:55:33.778145 [Gating] SW mode calibration
6478 11:55:33.784455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6479 11:55:33.791124 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6480 11:55:33.794202 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6481 11:55:33.798369 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6482 11:55:33.804603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6483 11:55:33.807759 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6484 11:55:33.811472 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6485 11:55:33.817519 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6486 11:55:33.820908 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 11:55:33.823986 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 11:55:33.830733 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6489 11:55:33.833949 Total UI for P1: 0, mck2ui 16
6490 11:55:33.837216 best dqsien dly found for B0: ( 0, 14, 24)
6491 11:55:33.837325 Total UI for P1: 0, mck2ui 16
6492 11:55:33.844261 best dqsien dly found for B1: ( 0, 14, 24)
6493 11:55:33.847597 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6494 11:55:33.850741 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6495 11:55:33.850822
6496 11:55:33.853755 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6497 11:55:33.857376 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6498 11:55:33.861151 [Gating] SW calibration Done
6499 11:55:33.861257 ==
6500 11:55:33.863744 Dram Type= 6, Freq= 0, CH_0, rank 1
6501 11:55:33.867101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6502 11:55:33.867182 ==
6503 11:55:33.870728 RX Vref Scan: 0
6504 11:55:33.870808
6505 11:55:33.870870 RX Vref 0 -> 0, step: 1
6506 11:55:33.873969
6507 11:55:33.874049 RX Delay -410 -> 252, step: 16
6508 11:55:33.880314 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6509 11:55:33.883516 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6510 11:55:33.887072 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6511 11:55:33.890646 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6512 11:55:33.896683 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6513 11:55:33.900030 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6514 11:55:33.903125 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6515 11:55:33.909985 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6516 11:55:33.913173 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6517 11:55:33.916650 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6518 11:55:33.920344 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6519 11:55:33.926535 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6520 11:55:33.929906 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6521 11:55:33.932671 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6522 11:55:33.936034 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6523 11:55:33.942919 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6524 11:55:33.942999 ==
6525 11:55:33.945943 Dram Type= 6, Freq= 0, CH_0, rank 1
6526 11:55:33.949530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6527 11:55:33.949611 ==
6528 11:55:33.952722 DQS Delay:
6529 11:55:33.952802 DQS0 = 35, DQS1 = 51
6530 11:55:33.952865 DQM Delay:
6531 11:55:33.956262 DQM0 = 8, DQM1 = 9
6532 11:55:33.956342 DQ Delay:
6533 11:55:33.959205 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6534 11:55:33.962394 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6535 11:55:33.965833 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6536 11:55:33.969020 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6537 11:55:33.969101
6538 11:55:33.969164
6539 11:55:33.969222 ==
6540 11:55:33.972963 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 11:55:33.975499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 11:55:33.975580 ==
6543 11:55:33.975643
6544 11:55:33.979383
6545 11:55:33.979463 TX Vref Scan disable
6546 11:55:33.982645 == TX Byte 0 ==
6547 11:55:33.985556 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6548 11:55:33.988821 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6549 11:55:33.992394 == TX Byte 1 ==
6550 11:55:33.995114 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6551 11:55:33.998898 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6552 11:55:33.998979 ==
6553 11:55:34.001935 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:55:34.005466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:55:34.009106 ==
6556 11:55:34.009228
6557 11:55:34.009293
6558 11:55:34.009351 TX Vref Scan disable
6559 11:55:34.011815 == TX Byte 0 ==
6560 11:55:34.015081 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 11:55:34.018588 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 11:55:34.021615 == TX Byte 1 ==
6563 11:55:34.025243 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6564 11:55:34.028579 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6565 11:55:34.028661
6566 11:55:34.028725 [DATLAT]
6567 11:55:34.031863 Freq=400, CH0 RK1
6568 11:55:34.031946
6569 11:55:34.035008 DATLAT Default: 0xe
6570 11:55:34.035089 0, 0xFFFF, sum = 0
6571 11:55:34.038277 1, 0xFFFF, sum = 0
6572 11:55:34.038374 2, 0xFFFF, sum = 0
6573 11:55:34.041954 3, 0xFFFF, sum = 0
6574 11:55:34.042038 4, 0xFFFF, sum = 0
6575 11:55:34.045095 5, 0xFFFF, sum = 0
6576 11:55:34.045178 6, 0xFFFF, sum = 0
6577 11:55:34.048535 7, 0xFFFF, sum = 0
6578 11:55:34.048619 8, 0xFFFF, sum = 0
6579 11:55:34.051377 9, 0xFFFF, sum = 0
6580 11:55:34.051460 10, 0xFFFF, sum = 0
6581 11:55:34.054964 11, 0xFFFF, sum = 0
6582 11:55:34.055070 12, 0xFFFF, sum = 0
6583 11:55:34.057955 13, 0x0, sum = 1
6584 11:55:34.058037 14, 0x0, sum = 2
6585 11:55:34.061845 15, 0x0, sum = 3
6586 11:55:34.061929 16, 0x0, sum = 4
6587 11:55:34.065139 best_step = 14
6588 11:55:34.065221
6589 11:55:34.065286 ==
6590 11:55:34.068084 Dram Type= 6, Freq= 0, CH_0, rank 1
6591 11:55:34.071044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 11:55:34.071127 ==
6593 11:55:34.074877 RX Vref Scan: 0
6594 11:55:34.074959
6595 11:55:34.075023 RX Vref 0 -> 0, step: 1
6596 11:55:34.075082
6597 11:55:34.078582 RX Delay -343 -> 252, step: 8
6598 11:55:34.086087 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6599 11:55:34.089857 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6600 11:55:34.093124 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6601 11:55:34.099415 iDelay=209, Bit 3, Center -40 (-279 ~ 200) 480
6602 11:55:34.102595 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6603 11:55:34.105490 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6604 11:55:34.109132 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6605 11:55:34.115365 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6606 11:55:34.119444 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6607 11:55:34.122144 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6608 11:55:34.125227 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6609 11:55:34.131774 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6610 11:55:34.135213 iDelay=209, Bit 12, Center -36 (-279 ~ 208) 488
6611 11:55:34.138535 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6612 11:55:34.145410 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6613 11:55:34.149196 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6614 11:55:34.149278 ==
6615 11:55:34.151700 Dram Type= 6, Freq= 0, CH_0, rank 1
6616 11:55:34.154970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6617 11:55:34.155053 ==
6618 11:55:34.158274 DQS Delay:
6619 11:55:34.158370 DQS0 = 44, DQS1 = 60
6620 11:55:34.158434 DQM Delay:
6621 11:55:34.161868 DQM0 = 9, DQM1 = 16
6622 11:55:34.161950 DQ Delay:
6623 11:55:34.164660 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6624 11:55:34.168510 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6625 11:55:34.171343 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6626 11:55:34.175133 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6627 11:55:34.175215
6628 11:55:34.175280
6629 11:55:34.184606 [DQSOSCAuto] RK1, (LSB)MR18= 0x847d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6630 11:55:34.184688 CH0 RK1: MR19=C0C, MR18=847D
6631 11:55:34.191201 CH0_RK1: MR19=0xC0C, MR18=0x847D, DQSOSC=393, MR23=63, INC=382, DEC=254
6632 11:55:34.194979 [RxdqsGatingPostProcess] freq 400
6633 11:55:34.201657 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6634 11:55:34.204540 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 11:55:34.207947 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 11:55:34.210996 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 11:55:34.214638 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 11:55:34.217591 best DQS0 dly(2T, 0.5T) = (0, 10)
6639 11:55:34.220912 best DQS1 dly(2T, 0.5T) = (0, 10)
6640 11:55:34.223967 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6641 11:55:34.227405 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6642 11:55:34.227544 Pre-setting of DQS Precalculation
6643 11:55:34.233669 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6644 11:55:34.233751 ==
6645 11:55:34.237043 Dram Type= 6, Freq= 0, CH_1, rank 0
6646 11:55:34.241021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6647 11:55:34.241103 ==
6648 11:55:34.247204 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6649 11:55:34.253664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6650 11:55:34.257170 [CA 0] Center 36 (8~64) winsize 57
6651 11:55:34.260232 [CA 1] Center 36 (8~64) winsize 57
6652 11:55:34.263382 [CA 2] Center 36 (8~64) winsize 57
6653 11:55:34.266542 [CA 3] Center 36 (8~64) winsize 57
6654 11:55:34.270289 [CA 4] Center 36 (8~64) winsize 57
6655 11:55:34.273100 [CA 5] Center 36 (8~64) winsize 57
6656 11:55:34.273182
6657 11:55:34.276641 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6658 11:55:34.276724
6659 11:55:34.279952 [CATrainingPosCal] consider 1 rank data
6660 11:55:34.283678 u2DelayCellTimex100 = 270/100 ps
6661 11:55:34.286733 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:55:34.289947 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:55:34.293195 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:55:34.296175 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:55:34.299671 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:55:34.302993 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:55:34.303075
6668 11:55:34.306312 CA PerBit enable=1, Macro0, CA PI delay=36
6669 11:55:34.309458
6670 11:55:34.309539 [CBTSetCACLKResult] CA Dly = 36
6671 11:55:34.312982 CS Dly: 1 (0~32)
6672 11:55:34.313064 ==
6673 11:55:34.316491 Dram Type= 6, Freq= 0, CH_1, rank 1
6674 11:55:34.319520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 11:55:34.319602 ==
6676 11:55:34.326431 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6677 11:55:34.332640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6678 11:55:34.335740 [CA 0] Center 36 (8~64) winsize 57
6679 11:55:34.339068 [CA 1] Center 36 (8~64) winsize 57
6680 11:55:34.342429 [CA 2] Center 36 (8~64) winsize 57
6681 11:55:34.346013 [CA 3] Center 36 (8~64) winsize 57
6682 11:55:34.346095 [CA 4] Center 36 (8~64) winsize 57
6683 11:55:34.349160 [CA 5] Center 36 (8~64) winsize 57
6684 11:55:34.349242
6685 11:55:34.356232 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6686 11:55:34.356313
6687 11:55:34.359263 [CATrainingPosCal] consider 2 rank data
6688 11:55:34.362188 u2DelayCellTimex100 = 270/100 ps
6689 11:55:34.365912 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 11:55:34.368828 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 11:55:34.372253 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:55:34.375950 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:55:34.379248 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:55:34.382224 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:55:34.382345
6696 11:55:34.385509 CA PerBit enable=1, Macro0, CA PI delay=36
6697 11:55:34.385591
6698 11:55:34.388962 [CBTSetCACLKResult] CA Dly = 36
6699 11:55:34.392292 CS Dly: 1 (0~32)
6700 11:55:34.392374
6701 11:55:34.395417 ----->DramcWriteLeveling(PI) begin...
6702 11:55:34.395500 ==
6703 11:55:34.398851 Dram Type= 6, Freq= 0, CH_1, rank 0
6704 11:55:34.401992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6705 11:55:34.402076 ==
6706 11:55:34.405263 Write leveling (Byte 0): 40 => 8
6707 11:55:34.408413 Write leveling (Byte 1): 40 => 8
6708 11:55:34.411774 DramcWriteLeveling(PI) end<-----
6709 11:55:34.411856
6710 11:55:34.411920 ==
6711 11:55:34.415122 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 11:55:34.418557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 11:55:34.418639 ==
6714 11:55:34.421394 [Gating] SW mode calibration
6715 11:55:34.428301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6716 11:55:34.435133 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6717 11:55:34.438415 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6718 11:55:34.444693 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6719 11:55:34.448356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6720 11:55:34.451121 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6721 11:55:34.458127 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6722 11:55:34.461581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6723 11:55:34.464593 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 11:55:34.471231 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 11:55:34.474625 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6726 11:55:34.477746 Total UI for P1: 0, mck2ui 16
6727 11:55:34.481039 best dqsien dly found for B0: ( 0, 14, 24)
6728 11:55:34.484290 Total UI for P1: 0, mck2ui 16
6729 11:55:34.487572 best dqsien dly found for B1: ( 0, 14, 24)
6730 11:55:34.490676 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6731 11:55:34.493953 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6732 11:55:34.494035
6733 11:55:34.497387 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6734 11:55:34.500486 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6735 11:55:34.504013 [Gating] SW calibration Done
6736 11:55:34.504094 ==
6737 11:55:34.507135 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 11:55:34.513635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 11:55:34.513718 ==
6740 11:55:34.513782 RX Vref Scan: 0
6741 11:55:34.513842
6742 11:55:34.517299 RX Vref 0 -> 0, step: 1
6743 11:55:34.517380
6744 11:55:34.520297 RX Delay -410 -> 252, step: 16
6745 11:55:34.523494 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6746 11:55:34.527396 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6747 11:55:34.533554 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6748 11:55:34.537123 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6749 11:55:34.540268 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6750 11:55:34.543269 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6751 11:55:34.549973 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6752 11:55:34.553536 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6753 11:55:34.557422 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6754 11:55:34.559936 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6755 11:55:34.567144 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6756 11:55:34.569959 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6757 11:55:34.573548 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6758 11:55:34.576740 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6759 11:55:34.583163 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6760 11:55:34.586938 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6761 11:55:34.587021 ==
6762 11:55:34.589779 Dram Type= 6, Freq= 0, CH_1, rank 0
6763 11:55:34.593101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6764 11:55:34.593183 ==
6765 11:55:34.596183 DQS Delay:
6766 11:55:34.596264 DQS0 = 35, DQS1 = 51
6767 11:55:34.599630 DQM Delay:
6768 11:55:34.599710 DQM0 = 6, DQM1 = 15
6769 11:55:34.599774 DQ Delay:
6770 11:55:34.602763 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6771 11:55:34.605908 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6772 11:55:34.609397 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6773 11:55:34.612684 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =16
6774 11:55:34.612764
6775 11:55:34.612828
6776 11:55:34.612886 ==
6777 11:55:34.616115 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 11:55:34.622374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 11:55:34.622455 ==
6780 11:55:34.622518
6781 11:55:34.622575
6782 11:55:34.622631 TX Vref Scan disable
6783 11:55:34.626256 == TX Byte 0 ==
6784 11:55:34.629150 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6785 11:55:34.632733 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6786 11:55:34.635571 == TX Byte 1 ==
6787 11:55:34.639674 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6788 11:55:34.642186 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6789 11:55:34.645626 ==
6790 11:55:34.648852 Dram Type= 6, Freq= 0, CH_1, rank 0
6791 11:55:34.652286 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6792 11:55:34.652367 ==
6793 11:55:34.652431
6794 11:55:34.652489
6795 11:55:34.655279 TX Vref Scan disable
6796 11:55:34.655358 == TX Byte 0 ==
6797 11:55:34.658936 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 11:55:34.665283 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 11:55:34.665363 == TX Byte 1 ==
6800 11:55:34.668571 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6801 11:55:34.675231 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6802 11:55:34.675327
6803 11:55:34.675405 [DATLAT]
6804 11:55:34.675463 Freq=400, CH1 RK0
6805 11:55:34.675520
6806 11:55:34.678526 DATLAT Default: 0xf
6807 11:55:34.681844 0, 0xFFFF, sum = 0
6808 11:55:34.681926 1, 0xFFFF, sum = 0
6809 11:55:34.685047 2, 0xFFFF, sum = 0
6810 11:55:34.685129 3, 0xFFFF, sum = 0
6811 11:55:34.688131 4, 0xFFFF, sum = 0
6812 11:55:34.688213 5, 0xFFFF, sum = 0
6813 11:55:34.691508 6, 0xFFFF, sum = 0
6814 11:55:34.691627 7, 0xFFFF, sum = 0
6815 11:55:34.694937 8, 0xFFFF, sum = 0
6816 11:55:34.695020 9, 0xFFFF, sum = 0
6817 11:55:34.698642 10, 0xFFFF, sum = 0
6818 11:55:34.698725 11, 0xFFFF, sum = 0
6819 11:55:34.701278 12, 0xFFFF, sum = 0
6820 11:55:34.701360 13, 0x0, sum = 1
6821 11:55:34.704423 14, 0x0, sum = 2
6822 11:55:34.704506 15, 0x0, sum = 3
6823 11:55:34.707768 16, 0x0, sum = 4
6824 11:55:34.707851 best_step = 14
6825 11:55:34.707915
6826 11:55:34.707974 ==
6827 11:55:34.711452 Dram Type= 6, Freq= 0, CH_1, rank 0
6828 11:55:34.717803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 11:55:34.717885 ==
6830 11:55:34.717950 RX Vref Scan: 1
6831 11:55:34.718010
6832 11:55:34.721118 RX Vref 0 -> 0, step: 1
6833 11:55:34.721200
6834 11:55:34.724597 RX Delay -343 -> 252, step: 8
6835 11:55:34.724680
6836 11:55:34.727796 Set Vref, RX VrefLevel [Byte0]: 51
6837 11:55:34.730991 [Byte1]: 51
6838 11:55:34.731073
6839 11:55:34.734333 Final RX Vref Byte 0 = 51 to rank0
6840 11:55:34.737601 Final RX Vref Byte 1 = 51 to rank0
6841 11:55:34.740988 Final RX Vref Byte 0 = 51 to rank1
6842 11:55:34.744559 Final RX Vref Byte 1 = 51 to rank1==
6843 11:55:34.747833 Dram Type= 6, Freq= 0, CH_1, rank 0
6844 11:55:34.754283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6845 11:55:34.754380 ==
6846 11:55:34.754445 DQS Delay:
6847 11:55:34.754506 DQS0 = 44, DQS1 = 52
6848 11:55:34.757744 DQM Delay:
6849 11:55:34.757825 DQM0 = 10, DQM1 = 11
6850 11:55:34.760909 DQ Delay:
6851 11:55:34.763848 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6852 11:55:34.763930 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =4
6853 11:55:34.768051 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6854 11:55:34.771150 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6855 11:55:34.771232
6856 11:55:34.773894
6857 11:55:34.780966 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a92, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6858 11:55:34.783452 CH1 RK0: MR19=C0C, MR18=6A92
6859 11:55:34.790487 CH1_RK0: MR19=0xC0C, MR18=0x6A92, DQSOSC=391, MR23=63, INC=386, DEC=257
6860 11:55:34.790570 ==
6861 11:55:34.793630 Dram Type= 6, Freq= 0, CH_1, rank 1
6862 11:55:34.797531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 11:55:34.797613 ==
6864 11:55:34.800445 [Gating] SW mode calibration
6865 11:55:34.807146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6866 11:55:34.813308 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6867 11:55:34.816990 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6868 11:55:34.819973 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6869 11:55:34.826943 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6870 11:55:34.829915 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6871 11:55:34.832974 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6872 11:55:34.839582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6873 11:55:34.842879 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 11:55:34.846247 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 11:55:34.853039 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6876 11:55:34.853121 Total UI for P1: 0, mck2ui 16
6877 11:55:34.859209 best dqsien dly found for B0: ( 0, 14, 24)
6878 11:55:34.859291 Total UI for P1: 0, mck2ui 16
6879 11:55:34.866101 best dqsien dly found for B1: ( 0, 14, 24)
6880 11:55:34.869430 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6881 11:55:34.872702 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6882 11:55:34.872785
6883 11:55:34.875717 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6884 11:55:34.879313 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6885 11:55:34.882363 [Gating] SW calibration Done
6886 11:55:34.882445 ==
6887 11:55:34.886182 Dram Type= 6, Freq= 0, CH_1, rank 1
6888 11:55:34.889251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6889 11:55:34.889331 ==
6890 11:55:34.892077 RX Vref Scan: 0
6891 11:55:34.892157
6892 11:55:34.895692 RX Vref 0 -> 0, step: 1
6893 11:55:34.895772
6894 11:55:34.895834 RX Delay -410 -> 252, step: 16
6895 11:55:34.902701 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6896 11:55:34.906111 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6897 11:55:34.909326 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6898 11:55:34.915521 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6899 11:55:34.918695 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6900 11:55:34.922064 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6901 11:55:34.925312 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6902 11:55:34.931874 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6903 11:55:34.935682 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6904 11:55:34.938573 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6905 11:55:34.941917 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6906 11:55:34.948450 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6907 11:55:34.952032 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6908 11:55:34.955764 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6909 11:55:34.958480 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6910 11:55:34.965008 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6911 11:55:34.965121 ==
6912 11:55:34.968104 Dram Type= 6, Freq= 0, CH_1, rank 1
6913 11:55:34.971724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 11:55:34.971806 ==
6915 11:55:34.971871 DQS Delay:
6916 11:55:34.975689 DQS0 = 43, DQS1 = 51
6917 11:55:34.975771 DQM Delay:
6918 11:55:34.978436 DQM0 = 9, DQM1 = 15
6919 11:55:34.978518 DQ Delay:
6920 11:55:34.981795 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6921 11:55:34.984774 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6922 11:55:34.988214 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6923 11:55:34.991467 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6924 11:55:34.991549
6925 11:55:34.991613
6926 11:55:34.991673 ==
6927 11:55:34.994548 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 11:55:34.998139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 11:55:34.998221 ==
6930 11:55:34.998298
6931 11:55:35.001544
6932 11:55:35.001625 TX Vref Scan disable
6933 11:55:35.004500 == TX Byte 0 ==
6934 11:55:35.008963 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6935 11:55:35.011205 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6936 11:55:35.014271 == TX Byte 1 ==
6937 11:55:35.017744 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6938 11:55:35.020842 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6939 11:55:35.020924 ==
6940 11:55:35.024643 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:55:35.028149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:55:35.030774 ==
6943 11:55:35.030855
6944 11:55:35.030919
6945 11:55:35.030979 TX Vref Scan disable
6946 11:55:35.034752 == TX Byte 0 ==
6947 11:55:35.038290 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 11:55:35.040970 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 11:55:35.044219 == TX Byte 1 ==
6950 11:55:35.048097 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6951 11:55:35.050757 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6952 11:55:35.050839
6953 11:55:35.050904 [DATLAT]
6954 11:55:35.054311 Freq=400, CH1 RK1
6955 11:55:35.054394
6956 11:55:35.057169 DATLAT Default: 0xe
6957 11:55:35.057250 0, 0xFFFF, sum = 0
6958 11:55:35.060495 1, 0xFFFF, sum = 0
6959 11:55:35.060578 2, 0xFFFF, sum = 0
6960 11:55:35.063881 3, 0xFFFF, sum = 0
6961 11:55:35.063964 4, 0xFFFF, sum = 0
6962 11:55:35.067795 5, 0xFFFF, sum = 0
6963 11:55:35.067878 6, 0xFFFF, sum = 0
6964 11:55:35.070679 7, 0xFFFF, sum = 0
6965 11:55:35.070763 8, 0xFFFF, sum = 0
6966 11:55:35.073648 9, 0xFFFF, sum = 0
6967 11:55:35.073731 10, 0xFFFF, sum = 0
6968 11:55:35.077426 11, 0xFFFF, sum = 0
6969 11:55:35.077509 12, 0xFFFF, sum = 0
6970 11:55:35.081096 13, 0x0, sum = 1
6971 11:55:35.081179 14, 0x0, sum = 2
6972 11:55:35.084526 15, 0x0, sum = 3
6973 11:55:35.084609 16, 0x0, sum = 4
6974 11:55:35.088281 best_step = 14
6975 11:55:35.088363
6976 11:55:35.088428 ==
6977 11:55:35.090996 Dram Type= 6, Freq= 0, CH_1, rank 1
6978 11:55:35.094034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 11:55:35.094117 ==
6980 11:55:35.097330 RX Vref Scan: 0
6981 11:55:35.097412
6982 11:55:35.097476 RX Vref 0 -> 0, step: 1
6983 11:55:35.097536
6984 11:55:35.100456 RX Delay -343 -> 252, step: 8
6985 11:55:35.108320 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6986 11:55:35.111763 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6987 11:55:35.114714 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6988 11:55:35.121614 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6989 11:55:35.124489 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6990 11:55:35.128061 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6991 11:55:35.131117 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6992 11:55:35.137870 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6993 11:55:35.141096 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6994 11:55:35.144382 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6995 11:55:35.147429 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6996 11:55:35.154528 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6997 11:55:35.157548 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6998 11:55:35.160625 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6999 11:55:35.167743 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7000 11:55:35.171215 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
7001 11:55:35.171297 ==
7002 11:55:35.174393 Dram Type= 6, Freq= 0, CH_1, rank 1
7003 11:55:35.177895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7004 11:55:35.177977 ==
7005 11:55:35.180356 DQS Delay:
7006 11:55:35.180437 DQS0 = 48, DQS1 = 52
7007 11:55:35.180502 DQM Delay:
7008 11:55:35.183686 DQM0 = 11, DQM1 = 10
7009 11:55:35.183768 DQ Delay:
7010 11:55:35.187032 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
7011 11:55:35.190676 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7012 11:55:35.194206 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7013 11:55:35.197083 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7014 11:55:35.197164
7015 11:55:35.197228
7016 11:55:35.207005 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bb3, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 394 ps
7017 11:55:35.207088 CH1 RK1: MR19=C0C, MR18=7BB3
7018 11:55:35.213654 CH1_RK1: MR19=0xC0C, MR18=0x7BB3, DQSOSC=387, MR23=63, INC=394, DEC=262
7019 11:55:35.216762 [RxdqsGatingPostProcess] freq 400
7020 11:55:35.223296 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7021 11:55:35.226753 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 11:55:35.230473 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 11:55:35.233387 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 11:55:35.237083 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 11:55:35.239854 best DQS0 dly(2T, 0.5T) = (0, 10)
7026 11:55:35.243238 best DQS1 dly(2T, 0.5T) = (0, 10)
7027 11:55:35.246834 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7028 11:55:35.250012 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7029 11:55:35.250095 Pre-setting of DQS Precalculation
7030 11:55:35.256275 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7031 11:55:35.263163 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7032 11:55:35.270124 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7033 11:55:35.270206
7034 11:55:35.270305
7035 11:55:35.272698 [Calibration Summary] 800 Mbps
7036 11:55:35.276300 CH 0, Rank 0
7037 11:55:35.276382 SW Impedance : PASS
7038 11:55:35.279363 DUTY Scan : NO K
7039 11:55:35.283248 ZQ Calibration : PASS
7040 11:55:35.283329 Jitter Meter : NO K
7041 11:55:35.286223 CBT Training : PASS
7042 11:55:35.289183 Write leveling : PASS
7043 11:55:35.289264 RX DQS gating : PASS
7044 11:55:35.293131 RX DQ/DQS(RDDQC) : PASS
7045 11:55:35.296331 TX DQ/DQS : PASS
7046 11:55:35.296426 RX DATLAT : PASS
7047 11:55:35.299276 RX DQ/DQS(Engine): PASS
7048 11:55:35.299358 TX OE : NO K
7049 11:55:35.303069 All Pass.
7050 11:55:35.303151
7051 11:55:35.303215 CH 0, Rank 1
7052 11:55:35.306055 SW Impedance : PASS
7053 11:55:35.306136 DUTY Scan : NO K
7054 11:55:35.309199 ZQ Calibration : PASS
7055 11:55:35.312460 Jitter Meter : NO K
7056 11:55:35.312542 CBT Training : PASS
7057 11:55:35.315909 Write leveling : NO K
7058 11:55:35.318897 RX DQS gating : PASS
7059 11:55:35.318979 RX DQ/DQS(RDDQC) : PASS
7060 11:55:35.322630 TX DQ/DQS : PASS
7061 11:55:35.325989 RX DATLAT : PASS
7062 11:55:35.326126 RX DQ/DQS(Engine): PASS
7063 11:55:35.328876 TX OE : NO K
7064 11:55:35.329003 All Pass.
7065 11:55:35.329100
7066 11:55:35.332143 CH 1, Rank 0
7067 11:55:35.332240 SW Impedance : PASS
7068 11:55:35.335745 DUTY Scan : NO K
7069 11:55:35.338902 ZQ Calibration : PASS
7070 11:55:35.338983 Jitter Meter : NO K
7071 11:55:35.342220 CBT Training : PASS
7072 11:55:35.345774 Write leveling : PASS
7073 11:55:35.345856 RX DQS gating : PASS
7074 11:55:35.348698 RX DQ/DQS(RDDQC) : PASS
7075 11:55:35.351974 TX DQ/DQS : PASS
7076 11:55:35.352082 RX DATLAT : PASS
7077 11:55:35.355069 RX DQ/DQS(Engine): PASS
7078 11:55:35.359189 TX OE : NO K
7079 11:55:35.359271 All Pass.
7080 11:55:35.359335
7081 11:55:35.359394 CH 1, Rank 1
7082 11:55:35.361889 SW Impedance : PASS
7083 11:55:35.365020 DUTY Scan : NO K
7084 11:55:35.365102 ZQ Calibration : PASS
7085 11:55:35.368378 Jitter Meter : NO K
7086 11:55:35.371552 CBT Training : PASS
7087 11:55:35.371660 Write leveling : NO K
7088 11:55:35.375076 RX DQS gating : PASS
7089 11:55:35.378100 RX DQ/DQS(RDDQC) : PASS
7090 11:55:35.378223 TX DQ/DQS : PASS
7091 11:55:35.381489 RX DATLAT : PASS
7092 11:55:35.381570 RX DQ/DQS(Engine): PASS
7093 11:55:35.384827 TX OE : NO K
7094 11:55:35.384909 All Pass.
7095 11:55:35.384974
7096 11:55:35.388345 DramC Write-DBI off
7097 11:55:35.391573 PER_BANK_REFRESH: Hybrid Mode
7098 11:55:35.391655 TX_TRACKING: ON
7099 11:55:35.401881 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7100 11:55:35.405085 [FAST_K] Save calibration result to emmc
7101 11:55:35.407794 dramc_set_vcore_voltage set vcore to 725000
7102 11:55:35.411563 Read voltage for 1600, 0
7103 11:55:35.411645 Vio18 = 0
7104 11:55:35.414465 Vcore = 725000
7105 11:55:35.414547 Vdram = 0
7106 11:55:35.414611 Vddq = 0
7107 11:55:35.414670 Vmddr = 0
7108 11:55:35.420892 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7109 11:55:35.427409 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7110 11:55:35.427492 MEM_TYPE=3, freq_sel=13
7111 11:55:35.430962 sv_algorithm_assistance_LP4_3733
7112 11:55:35.437850 ============ PULL DRAM RESETB DOWN ============
7113 11:55:35.441141 ========== PULL DRAM RESETB DOWN end =========
7114 11:55:35.444157 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7115 11:55:35.448009 ===================================
7116 11:55:35.450668 LPDDR4 DRAM CONFIGURATION
7117 11:55:35.454694 ===================================
7118 11:55:35.457016 EX_ROW_EN[0] = 0x0
7119 11:55:35.457096 EX_ROW_EN[1] = 0x0
7120 11:55:35.460176 LP4Y_EN = 0x0
7121 11:55:35.460256 WORK_FSP = 0x1
7122 11:55:35.463799 WL = 0x5
7123 11:55:35.463879 RL = 0x5
7124 11:55:35.467731 BL = 0x2
7125 11:55:35.467811 RPST = 0x0
7126 11:55:35.470885 RD_PRE = 0x0
7127 11:55:35.470964 WR_PRE = 0x1
7128 11:55:35.473956 WR_PST = 0x1
7129 11:55:35.474035 DBI_WR = 0x0
7130 11:55:35.477746 DBI_RD = 0x0
7131 11:55:35.477826 OTF = 0x1
7132 11:55:35.480410 ===================================
7133 11:55:35.483401 ===================================
7134 11:55:35.486828 ANA top config
7135 11:55:35.490369 ===================================
7136 11:55:35.493554 DLL_ASYNC_EN = 0
7137 11:55:35.493633 ALL_SLAVE_EN = 0
7138 11:55:35.496572 NEW_RANK_MODE = 1
7139 11:55:35.500480 DLL_IDLE_MODE = 1
7140 11:55:35.503531 LP45_APHY_COMB_EN = 1
7141 11:55:35.503611 TX_ODT_DIS = 0
7142 11:55:35.506599 NEW_8X_MODE = 1
7143 11:55:35.510070 ===================================
7144 11:55:35.512945 ===================================
7145 11:55:35.516555 data_rate = 3200
7146 11:55:35.519746 CKR = 1
7147 11:55:35.523067 DQ_P2S_RATIO = 8
7148 11:55:35.526058 ===================================
7149 11:55:35.529701 CA_P2S_RATIO = 8
7150 11:55:35.532958 DQ_CA_OPEN = 0
7151 11:55:35.533039 DQ_SEMI_OPEN = 0
7152 11:55:35.536712 CA_SEMI_OPEN = 0
7153 11:55:35.539488 CA_FULL_RATE = 0
7154 11:55:35.542901 DQ_CKDIV4_EN = 0
7155 11:55:35.546151 CA_CKDIV4_EN = 0
7156 11:55:35.549244 CA_PREDIV_EN = 0
7157 11:55:35.549325 PH8_DLY = 12
7158 11:55:35.552551 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7159 11:55:35.555887 DQ_AAMCK_DIV = 4
7160 11:55:35.559257 CA_AAMCK_DIV = 4
7161 11:55:35.562380 CA_ADMCK_DIV = 4
7162 11:55:35.565990 DQ_TRACK_CA_EN = 0
7163 11:55:35.568729 CA_PICK = 1600
7164 11:55:35.568816 CA_MCKIO = 1600
7165 11:55:35.572652 MCKIO_SEMI = 0
7166 11:55:35.575506 PLL_FREQ = 3068
7167 11:55:35.579131 DQ_UI_PI_RATIO = 32
7168 11:55:35.582844 CA_UI_PI_RATIO = 0
7169 11:55:35.585493 ===================================
7170 11:55:35.589128 ===================================
7171 11:55:35.592179 memory_type:LPDDR4
7172 11:55:35.592259 GP_NUM : 10
7173 11:55:35.595370 SRAM_EN : 1
7174 11:55:35.595451 MD32_EN : 0
7175 11:55:35.598786 ===================================
7176 11:55:35.602014 [ANA_INIT] >>>>>>>>>>>>>>
7177 11:55:35.605783 <<<<<< [CONFIGURE PHASE]: ANA_TX
7178 11:55:35.609024 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7179 11:55:35.612007 ===================================
7180 11:55:35.614976 data_rate = 3200,PCW = 0X7600
7181 11:55:35.618201 ===================================
7182 11:55:35.621848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7183 11:55:35.628185 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7184 11:55:35.631419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7185 11:55:35.638422 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7186 11:55:35.641963 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7187 11:55:35.645060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7188 11:55:35.645143 [ANA_INIT] flow start
7189 11:55:35.647862 [ANA_INIT] PLL >>>>>>>>
7190 11:55:35.651422 [ANA_INIT] PLL <<<<<<<<
7191 11:55:35.654886 [ANA_INIT] MIDPI >>>>>>>>
7192 11:55:35.654973 [ANA_INIT] MIDPI <<<<<<<<
7193 11:55:35.658675 [ANA_INIT] DLL >>>>>>>>
7194 11:55:35.661048 [ANA_INIT] DLL <<<<<<<<
7195 11:55:35.661129 [ANA_INIT] flow end
7196 11:55:35.664410 ============ LP4 DIFF to SE enter ============
7197 11:55:35.671228 ============ LP4 DIFF to SE exit ============
7198 11:55:35.671314 [ANA_INIT] <<<<<<<<<<<<<
7199 11:55:35.674345 [Flow] Enable top DCM control >>>>>
7200 11:55:35.677935 [Flow] Enable top DCM control <<<<<
7201 11:55:35.681197 Enable DLL master slave shuffle
7202 11:55:35.687741 ==============================================================
7203 11:55:35.691185 Gating Mode config
7204 11:55:35.694211 ==============================================================
7205 11:55:35.697899 Config description:
7206 11:55:35.707530 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7207 11:55:35.714131 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7208 11:55:35.717289 SELPH_MODE 0: By rank 1: By Phase
7209 11:55:35.723734 ==============================================================
7210 11:55:35.726915 GAT_TRACK_EN = 1
7211 11:55:35.730530 RX_GATING_MODE = 2
7212 11:55:35.733655 RX_GATING_TRACK_MODE = 2
7213 11:55:35.736743 SELPH_MODE = 1
7214 11:55:35.736828 PICG_EARLY_EN = 1
7215 11:55:35.740349 VALID_LAT_VALUE = 1
7216 11:55:35.746922 ==============================================================
7217 11:55:35.750544 Enter into Gating configuration >>>>
7218 11:55:35.753820 Exit from Gating configuration <<<<
7219 11:55:35.756687 Enter into DVFS_PRE_config >>>>>
7220 11:55:35.767194 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7221 11:55:35.769949 Exit from DVFS_PRE_config <<<<<
7222 11:55:35.773541 Enter into PICG configuration >>>>
7223 11:55:35.776621 Exit from PICG configuration <<<<
7224 11:55:35.779650 [RX_INPUT] configuration >>>>>
7225 11:55:35.783430 [RX_INPUT] configuration <<<<<
7226 11:55:35.789769 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7227 11:55:35.793312 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7228 11:55:35.799549 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7229 11:55:35.806425 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7230 11:55:35.812759 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 11:55:35.819193 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 11:55:35.822536 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7233 11:55:35.826200 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7234 11:55:35.830076 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7235 11:55:35.837325 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7236 11:55:35.839330 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7237 11:55:35.842536 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7238 11:55:35.845573 ===================================
7239 11:55:35.849477 LPDDR4 DRAM CONFIGURATION
7240 11:55:35.852477 ===================================
7241 11:55:35.852565 EX_ROW_EN[0] = 0x0
7242 11:55:35.855516 EX_ROW_EN[1] = 0x0
7243 11:55:35.859125 LP4Y_EN = 0x0
7244 11:55:35.859282 WORK_FSP = 0x1
7245 11:55:35.862048 WL = 0x5
7246 11:55:35.862156 RL = 0x5
7247 11:55:35.865723 BL = 0x2
7248 11:55:35.865808 RPST = 0x0
7249 11:55:35.868630 RD_PRE = 0x0
7250 11:55:35.868723 WR_PRE = 0x1
7251 11:55:35.871955 WR_PST = 0x1
7252 11:55:35.872039 DBI_WR = 0x0
7253 11:55:35.875113 DBI_RD = 0x0
7254 11:55:35.875196 OTF = 0x1
7255 11:55:35.878843 ===================================
7256 11:55:35.885299 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7257 11:55:35.888342 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7258 11:55:35.891799 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7259 11:55:35.895529 ===================================
7260 11:55:35.898390 LPDDR4 DRAM CONFIGURATION
7261 11:55:35.902000 ===================================
7262 11:55:35.904886 EX_ROW_EN[0] = 0x10
7263 11:55:35.904969 EX_ROW_EN[1] = 0x0
7264 11:55:35.907997 LP4Y_EN = 0x0
7265 11:55:35.908080 WORK_FSP = 0x1
7266 11:55:35.911809 WL = 0x5
7267 11:55:35.911894 RL = 0x5
7268 11:55:35.914564 BL = 0x2
7269 11:55:35.914647 RPST = 0x0
7270 11:55:35.918083 RD_PRE = 0x0
7271 11:55:35.918191 WR_PRE = 0x1
7272 11:55:35.921166 WR_PST = 0x1
7273 11:55:35.921248 DBI_WR = 0x0
7274 11:55:35.924782 DBI_RD = 0x0
7275 11:55:35.924864 OTF = 0x1
7276 11:55:35.927910 ===================================
7277 11:55:35.934224 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7278 11:55:35.934323 ==
7279 11:55:35.938072 Dram Type= 6, Freq= 0, CH_0, rank 0
7280 11:55:35.944180 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7281 11:55:35.944272 ==
7282 11:55:35.944339 [Duty_Offset_Calibration]
7283 11:55:35.947798 B0:2 B1:0 CA:5
7284 11:55:35.947882
7285 11:55:35.951337 [DutyScan_Calibration_Flow] k_type=0
7286 11:55:35.959523
7287 11:55:35.959627 ==CLK 0==
7288 11:55:35.962904 Final CLK duty delay cell = -4
7289 11:55:35.966475 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7290 11:55:35.969579 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7291 11:55:35.973242 [-4] AVG Duty = 4922%(X100)
7292 11:55:35.973329
7293 11:55:35.975911 CH0 CLK Duty spec in!! Max-Min= 156%
7294 11:55:35.979371 [DutyScan_Calibration_Flow] ====Done====
7295 11:55:35.979473
7296 11:55:35.982719 [DutyScan_Calibration_Flow] k_type=1
7297 11:55:35.999891
7298 11:55:36.000054 ==DQS 0 ==
7299 11:55:36.003583 Final DQS duty delay cell = 0
7300 11:55:36.006584 [0] MAX Duty = 5218%(X100), DQS PI = 22
7301 11:55:36.009783 [0] MIN Duty = 5093%(X100), DQS PI = 6
7302 11:55:36.013121 [0] AVG Duty = 5155%(X100)
7303 11:55:36.013211
7304 11:55:36.013277 ==DQS 1 ==
7305 11:55:36.016588 Final DQS duty delay cell = 0
7306 11:55:36.019918 [0] MAX Duty = 5156%(X100), DQS PI = 2
7307 11:55:36.023160 [0] MIN Duty = 4969%(X100), DQS PI = 10
7308 11:55:36.026275 [0] AVG Duty = 5062%(X100)
7309 11:55:36.026361
7310 11:55:36.029303 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7311 11:55:36.029386
7312 11:55:36.032717 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7313 11:55:36.036375 [DutyScan_Calibration_Flow] ====Done====
7314 11:55:36.036459
7315 11:55:36.039346 [DutyScan_Calibration_Flow] k_type=3
7316 11:55:36.057149
7317 11:55:36.057297 ==DQM 0 ==
7318 11:55:36.060163 Final DQM duty delay cell = 0
7319 11:55:36.063518 [0] MAX Duty = 5124%(X100), DQS PI = 22
7320 11:55:36.066681 [0] MIN Duty = 4875%(X100), DQS PI = 56
7321 11:55:36.069902 [0] AVG Duty = 4999%(X100)
7322 11:55:36.069990
7323 11:55:36.070055 ==DQM 1 ==
7324 11:55:36.073480 Final DQM duty delay cell = 0
7325 11:55:36.076499 [0] MAX Duty = 4969%(X100), DQS PI = 2
7326 11:55:36.080063 [0] MIN Duty = 4844%(X100), DQS PI = 14
7327 11:55:36.083107 [0] AVG Duty = 4906%(X100)
7328 11:55:36.083198
7329 11:55:36.086533 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7330 11:55:36.086619
7331 11:55:36.089924 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7332 11:55:36.093558 [DutyScan_Calibration_Flow] ====Done====
7333 11:55:36.093642
7334 11:55:36.096610 [DutyScan_Calibration_Flow] k_type=2
7335 11:55:36.114230
7336 11:55:36.114401 ==DQ 0 ==
7337 11:55:36.117811 Final DQ duty delay cell = 0
7338 11:55:36.121075 [0] MAX Duty = 5124%(X100), DQS PI = 20
7339 11:55:36.124152 [0] MIN Duty = 4938%(X100), DQS PI = 12
7340 11:55:36.124237 [0] AVG Duty = 5031%(X100)
7341 11:55:36.127256
7342 11:55:36.127336 ==DQ 1 ==
7343 11:55:36.130935 Final DQ duty delay cell = 0
7344 11:55:36.134503 [0] MAX Duty = 5187%(X100), DQS PI = 2
7345 11:55:36.137625 [0] MIN Duty = 4907%(X100), DQS PI = 14
7346 11:55:36.137708 [0] AVG Duty = 5047%(X100)
7347 11:55:36.140858
7348 11:55:36.143778 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7349 11:55:36.143864
7350 11:55:36.146892 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7351 11:55:36.150445 [DutyScan_Calibration_Flow] ====Done====
7352 11:55:36.150535 ==
7353 11:55:36.153793 Dram Type= 6, Freq= 0, CH_1, rank 0
7354 11:55:36.156800 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 11:55:36.156885 ==
7356 11:55:36.160714 [Duty_Offset_Calibration]
7357 11:55:36.160798 B0:0 B1:-1 CA:3
7358 11:55:36.160862
7359 11:55:36.163800 [DutyScan_Calibration_Flow] k_type=0
7360 11:55:36.173788
7361 11:55:36.173915 ==CLK 0==
7362 11:55:36.176957 Final CLK duty delay cell = -4
7363 11:55:36.179973 [-4] MAX Duty = 5000%(X100), DQS PI = 6
7364 11:55:36.183479 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7365 11:55:36.186662 [-4] AVG Duty = 4922%(X100)
7366 11:55:36.186745
7367 11:55:36.190199 CH1 CLK Duty spec in!! Max-Min= 156%
7368 11:55:36.193841 [DutyScan_Calibration_Flow] ====Done====
7369 11:55:36.193925
7370 11:55:36.196323 [DutyScan_Calibration_Flow] k_type=1
7371 11:55:36.212698
7372 11:55:36.212841 ==DQS 0 ==
7373 11:55:36.216128 Final DQS duty delay cell = 0
7374 11:55:36.219457 [0] MAX Duty = 5250%(X100), DQS PI = 30
7375 11:55:36.222932 [0] MIN Duty = 4938%(X100), DQS PI = 56
7376 11:55:36.225709 [0] AVG Duty = 5094%(X100)
7377 11:55:36.225793
7378 11:55:36.225858 ==DQS 1 ==
7379 11:55:36.229290 Final DQS duty delay cell = -4
7380 11:55:36.232460 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7381 11:55:36.235798 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7382 11:55:36.239121 [-4] AVG Duty = 4922%(X100)
7383 11:55:36.239208
7384 11:55:36.242577 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7385 11:55:36.242668
7386 11:55:36.245540 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7387 11:55:36.249322 [DutyScan_Calibration_Flow] ====Done====
7388 11:55:36.249414
7389 11:55:36.252798 [DutyScan_Calibration_Flow] k_type=3
7390 11:55:36.269886
7391 11:55:36.270032 ==DQM 0 ==
7392 11:55:36.273328 Final DQM duty delay cell = 0
7393 11:55:36.276843 [0] MAX Duty = 5062%(X100), DQS PI = 30
7394 11:55:36.280017 [0] MIN Duty = 4782%(X100), DQS PI = 38
7395 11:55:36.283197 [0] AVG Duty = 4922%(X100)
7396 11:55:36.283282
7397 11:55:36.283348 ==DQM 1 ==
7398 11:55:36.286365 Final DQM duty delay cell = 0
7399 11:55:36.289652 [0] MAX Duty = 5000%(X100), DQS PI = 34
7400 11:55:36.292953 [0] MIN Duty = 4813%(X100), DQS PI = 0
7401 11:55:36.296122 [0] AVG Duty = 4906%(X100)
7402 11:55:36.296206
7403 11:55:36.299981 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7404 11:55:36.300066
7405 11:55:36.303184 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7406 11:55:36.306110 [DutyScan_Calibration_Flow] ====Done====
7407 11:55:36.306195
7408 11:55:36.309260 [DutyScan_Calibration_Flow] k_type=2
7409 11:55:36.325990
7410 11:55:36.326137 ==DQ 0 ==
7411 11:55:36.329874 Final DQ duty delay cell = -4
7412 11:55:36.332538 [-4] MAX Duty = 4938%(X100), DQS PI = 8
7413 11:55:36.335857 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7414 11:55:36.338990 [-4] AVG Duty = 4875%(X100)
7415 11:55:36.339076
7416 11:55:36.339141 ==DQ 1 ==
7417 11:55:36.342448 Final DQ duty delay cell = 0
7418 11:55:36.345696 [0] MAX Duty = 5062%(X100), DQS PI = 30
7419 11:55:36.349047 [0] MIN Duty = 4875%(X100), DQS PI = 0
7420 11:55:36.352810 [0] AVG Duty = 4968%(X100)
7421 11:55:36.352906
7422 11:55:36.358558 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7423 11:55:36.358655
7424 11:55:36.358913 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7425 11:55:36.362551 [DutyScan_Calibration_Flow] ====Done====
7426 11:55:36.365939 nWR fixed to 30
7427 11:55:36.369173 [ModeRegInit_LP4] CH0 RK0
7428 11:55:36.369260 [ModeRegInit_LP4] CH0 RK1
7429 11:55:36.372814 [ModeRegInit_LP4] CH1 RK0
7430 11:55:36.375995 [ModeRegInit_LP4] CH1 RK1
7431 11:55:36.376080 match AC timing 5
7432 11:55:36.382483 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7433 11:55:36.385872 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7434 11:55:36.388689 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7435 11:55:36.394999 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7436 11:55:36.399193 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7437 11:55:36.399291 [MiockJmeterHQA]
7438 11:55:36.402066
7439 11:55:36.402153 [DramcMiockJmeter] u1RxGatingPI = 0
7440 11:55:36.405629 0 : 4365, 4137
7441 11:55:36.405744 4 : 4253, 4027
7442 11:55:36.408061 8 : 4253, 4027
7443 11:55:36.408171 12 : 4253, 4027
7444 11:55:36.411736 16 : 4252, 4027
7445 11:55:36.411834 20 : 4363, 4137
7446 11:55:36.415339 24 : 4363, 4137
7447 11:55:36.415430 28 : 4253, 4026
7448 11:55:36.415495 32 : 4252, 4027
7449 11:55:36.418761 36 : 4252, 4027
7450 11:55:36.418850 40 : 4253, 4027
7451 11:55:36.421453 44 : 4257, 4032
7452 11:55:36.421538 48 : 4366, 4140
7453 11:55:36.424684 52 : 4250, 4027
7454 11:55:36.424770 56 : 4250, 4027
7455 11:55:36.427988 60 : 4250, 4027
7456 11:55:36.428074 64 : 4250, 4026
7457 11:55:36.428141 68 : 4250, 4027
7458 11:55:36.431544 72 : 4361, 4137
7459 11:55:36.431631 76 : 4361, 4138
7460 11:55:36.434524 80 : 4253, 4026
7461 11:55:36.434621 84 : 4250, 4027
7462 11:55:36.437978 88 : 4250, 4027
7463 11:55:36.438064 92 : 4250, 4026
7464 11:55:36.441012 96 : 4250, 2964
7465 11:55:36.441125 100 : 4360, 0
7466 11:55:36.441220 104 : 4361, 0
7467 11:55:36.444363 108 : 4252, 0
7468 11:55:36.444449 112 : 4250, 0
7469 11:55:36.447920 116 : 4363, 0
7470 11:55:36.448011 120 : 4250, 0
7471 11:55:36.448083 124 : 4250, 0
7472 11:55:36.451274 128 : 4250, 0
7473 11:55:36.451365 132 : 4250, 0
7474 11:55:36.451433 136 : 4250, 0
7475 11:55:36.454474 140 : 4250, 0
7476 11:55:36.454563 144 : 4250, 0
7477 11:55:36.458134 148 : 4361, 0
7478 11:55:36.458289 152 : 4360, 0
7479 11:55:36.458359 156 : 4361, 0
7480 11:55:36.461255 160 : 4250, 0
7481 11:55:36.461367 164 : 4250, 0
7482 11:55:36.464351 168 : 4250, 0
7483 11:55:36.464437 172 : 4250, 0
7484 11:55:36.464503 176 : 4250, 0
7485 11:55:36.467328 180 : 4250, 0
7486 11:55:36.467413 184 : 4250, 0
7487 11:55:36.470824 188 : 4250, 0
7488 11:55:36.470914 192 : 4250, 0
7489 11:55:36.470981 196 : 4253, 0
7490 11:55:36.474018 200 : 4361, 0
7491 11:55:36.474129 204 : 4360, 0
7492 11:55:36.477422 208 : 4361, 0
7493 11:55:36.477509 212 : 4250, 0
7494 11:55:36.477575 216 : 4360, 0
7495 11:55:36.480991 220 : 4250, 669
7496 11:55:36.481079 224 : 4250, 3999
7497 11:55:36.484082 228 : 4252, 4030
7498 11:55:36.484169 232 : 4252, 4029
7499 11:55:36.487440 236 : 4250, 4027
7500 11:55:36.487525 240 : 4250, 4026
7501 11:55:36.490480 244 : 4361, 4137
7502 11:55:36.490565 248 : 4250, 4026
7503 11:55:36.493733 252 : 4250, 4027
7504 11:55:36.493818 256 : 4360, 4138
7505 11:55:36.497032 260 : 4250, 4027
7506 11:55:36.497119 264 : 4250, 4027
7507 11:55:36.497186 268 : 4362, 4140
7508 11:55:36.500456 272 : 4250, 4027
7509 11:55:36.500572 276 : 4250, 4027
7510 11:55:36.503879 280 : 4250, 4027
7511 11:55:36.503966 284 : 4250, 4026
7512 11:55:36.507235 288 : 4250, 4027
7513 11:55:36.507321 292 : 4250, 4026
7514 11:55:36.510550 296 : 4361, 4137
7515 11:55:36.510634 300 : 4249, 4027
7516 11:55:36.513561 304 : 4250, 4027
7517 11:55:36.513646 308 : 4360, 4138
7518 11:55:36.516613 312 : 4250, 4026
7519 11:55:36.516699 316 : 4250, 4027
7520 11:55:36.520112 320 : 4361, 4137
7521 11:55:36.520199 324 : 4250, 4027
7522 11:55:36.523367 328 : 4250, 4026
7523 11:55:36.523452 332 : 4250, 4008
7524 11:55:36.523517 336 : 4250, 2137
7525 11:55:36.527301 340 : 4250, 12
7526 11:55:36.527386
7527 11:55:36.530156 MIOCK jitter meter ch=0
7528 11:55:36.530239
7529 11:55:36.533299 1T = (340-100) = 240 dly cells
7530 11:55:36.537065 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7531 11:55:36.537149 ==
7532 11:55:36.540400 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 11:55:36.546720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 11:55:36.546816 ==
7535 11:55:36.549957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7536 11:55:36.556028 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7537 11:55:36.559479 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7538 11:55:36.565948 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7539 11:55:36.574015 [CA 0] Center 43 (13~73) winsize 61
7540 11:55:36.577234 [CA 1] Center 42 (12~73) winsize 62
7541 11:55:36.580408 [CA 2] Center 37 (8~67) winsize 60
7542 11:55:36.584140 [CA 3] Center 37 (8~67) winsize 60
7543 11:55:36.586904 [CA 4] Center 36 (6~66) winsize 61
7544 11:55:36.590521 [CA 5] Center 35 (5~66) winsize 62
7545 11:55:36.590614
7546 11:55:36.593598 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7547 11:55:36.593683
7548 11:55:36.600233 [CATrainingPosCal] consider 1 rank data
7549 11:55:36.600330 u2DelayCellTimex100 = 271/100 ps
7550 11:55:36.606951 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7551 11:55:36.609959 CA1 delay=42 (12~73),Diff = 7 PI (25 cell)
7552 11:55:36.613620 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7553 11:55:36.616929 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7554 11:55:36.620153 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7555 11:55:36.623268 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7556 11:55:36.623356
7557 11:55:36.626563 CA PerBit enable=1, Macro0, CA PI delay=35
7558 11:55:36.626647
7559 11:55:36.630148 [CBTSetCACLKResult] CA Dly = 35
7560 11:55:36.633705 CS Dly: 10 (0~41)
7561 11:55:36.636730 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7562 11:55:36.639691 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7563 11:55:36.639778 ==
7564 11:55:36.643123 Dram Type= 6, Freq= 0, CH_0, rank 1
7565 11:55:36.649886 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7566 11:55:36.650038 ==
7567 11:55:36.652980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7568 11:55:36.659763 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7569 11:55:36.662755 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7570 11:55:36.668982 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7571 11:55:36.677282 [CA 0] Center 44 (14~75) winsize 62
7572 11:55:36.681274 [CA 1] Center 44 (14~74) winsize 61
7573 11:55:36.684104 [CA 2] Center 39 (10~69) winsize 60
7574 11:55:36.687356 [CA 3] Center 39 (10~68) winsize 59
7575 11:55:36.690797 [CA 4] Center 37 (7~67) winsize 61
7576 11:55:36.694059 [CA 5] Center 36 (6~66) winsize 61
7577 11:55:36.694159
7578 11:55:36.697400 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7579 11:55:36.697482
7580 11:55:36.704000 [CATrainingPosCal] consider 2 rank data
7581 11:55:36.704091 u2DelayCellTimex100 = 271/100 ps
7582 11:55:36.710529 CA0 delay=43 (14~73),Diff = 7 PI (25 cell)
7583 11:55:36.713498 CA1 delay=43 (14~73),Diff = 7 PI (25 cell)
7584 11:55:36.717001 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7585 11:55:36.720031 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7586 11:55:36.723404 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7587 11:55:36.726617 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7588 11:55:36.726762
7589 11:55:36.730021 CA PerBit enable=1, Macro0, CA PI delay=36
7590 11:55:36.730104
7591 11:55:36.733951 [CBTSetCACLKResult] CA Dly = 36
7592 11:55:36.736426 CS Dly: 11 (0~44)
7593 11:55:36.739983 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7594 11:55:36.743403 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7595 11:55:36.743488
7596 11:55:36.746994 ----->DramcWriteLeveling(PI) begin...
7597 11:55:36.750210 ==
7598 11:55:36.750381 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 11:55:36.756275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 11:55:36.756371 ==
7601 11:55:36.759571 Write leveling (Byte 0): 35 => 35
7602 11:55:36.763295 Write leveling (Byte 1): 27 => 27
7603 11:55:36.766500 DramcWriteLeveling(PI) end<-----
7604 11:55:36.766591
7605 11:55:36.766656 ==
7606 11:55:36.770042 Dram Type= 6, Freq= 0, CH_0, rank 0
7607 11:55:36.772826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7608 11:55:36.772944 ==
7609 11:55:36.776163 [Gating] SW mode calibration
7610 11:55:36.782764 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7611 11:55:36.789782 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7612 11:55:36.792482 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7613 11:55:36.795701 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7614 11:55:36.802997 1 4 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7615 11:55:36.805674 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7616 11:55:36.809415 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7617 11:55:36.815883 1 4 20 | B1->B0 | 2a2a 3434 | 1 1 | (1 1) (1 1)
7618 11:55:36.819015 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7619 11:55:36.822385 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7620 11:55:36.828961 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7621 11:55:36.832156 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7622 11:55:36.835496 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7623 11:55:36.842374 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7624 11:55:36.845292 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
7625 11:55:36.848670 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
7626 11:55:36.855027 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 11:55:36.859151 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7628 11:55:36.861918 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7629 11:55:36.868986 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:55:36.872250 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7631 11:55:36.874928 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7632 11:55:36.881398 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7633 11:55:36.884925 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7634 11:55:36.888413 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7635 11:55:36.894797 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7636 11:55:36.898274 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7637 11:55:36.901306 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 11:55:36.907899 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7639 11:55:36.911534 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7640 11:55:36.914346 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7641 11:55:36.921482 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7642 11:55:36.924683 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 11:55:36.927633 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:55:36.934752 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 11:55:36.937510 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7646 11:55:36.942046 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 11:55:36.947812 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:55:36.950494 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:55:36.954045 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:55:36.960415 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:55:36.964049 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:55:36.967157 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:55:36.973863 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:55:36.977630 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7655 11:55:36.980296 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7656 11:55:36.986825 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7657 11:55:36.986932 Total UI for P1: 0, mck2ui 16
7658 11:55:36.993428 best dqsien dly found for B0: ( 1, 9, 10)
7659 11:55:36.996767 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 11:55:37.000726 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7661 11:55:37.003369 Total UI for P1: 0, mck2ui 16
7662 11:55:37.006703 best dqsien dly found for B1: ( 1, 9, 20)
7663 11:55:37.010008 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7664 11:55:37.013287 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7665 11:55:37.013377
7666 11:55:37.019762 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7667 11:55:37.023249 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7668 11:55:37.026560 [Gating] SW calibration Done
7669 11:55:37.026649 ==
7670 11:55:37.030196 Dram Type= 6, Freq= 0, CH_0, rank 0
7671 11:55:37.033003 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7672 11:55:37.033089 ==
7673 11:55:37.033154 RX Vref Scan: 0
7674 11:55:37.036282
7675 11:55:37.036367 RX Vref 0 -> 0, step: 1
7676 11:55:37.036433
7677 11:55:37.039477 RX Delay 0 -> 252, step: 8
7678 11:55:37.042939 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7679 11:55:37.046272 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7680 11:55:37.053363 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7681 11:55:37.056050 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7682 11:55:37.059435 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7683 11:55:37.062566 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7684 11:55:37.066150 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7685 11:55:37.072750 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7686 11:55:37.076607 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7687 11:55:37.079330 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7688 11:55:37.082431 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7689 11:55:37.085644 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7690 11:55:37.092416 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7691 11:55:37.095438 iDelay=192, Bit 13, Center 135 (80 ~ 191) 112
7692 11:55:37.098985 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7693 11:55:37.102240 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7694 11:55:37.102342 ==
7695 11:55:37.105252 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 11:55:37.112363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 11:55:37.112461 ==
7698 11:55:37.112528 DQS Delay:
7699 11:55:37.115930 DQS0 = 0, DQS1 = 0
7700 11:55:37.116015 DQM Delay:
7701 11:55:37.118684 DQM0 = 131, DQM1 = 127
7702 11:55:37.118770 DQ Delay:
7703 11:55:37.122039 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7704 11:55:37.125587 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7705 11:55:37.129074 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7706 11:55:37.132328 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
7707 11:55:37.132414
7708 11:55:37.132480
7709 11:55:37.132540 ==
7710 11:55:37.135399 Dram Type= 6, Freq= 0, CH_0, rank 0
7711 11:55:37.142176 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7712 11:55:37.142288 ==
7713 11:55:37.142360
7714 11:55:37.142421
7715 11:55:37.142480 TX Vref Scan disable
7716 11:55:37.145387 == TX Byte 0 ==
7717 11:55:37.148515 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7718 11:55:37.154932 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7719 11:55:37.155039 == TX Byte 1 ==
7720 11:55:37.158757 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7721 11:55:37.165757 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7722 11:55:37.165862 ==
7723 11:55:37.168316 Dram Type= 6, Freq= 0, CH_0, rank 0
7724 11:55:37.171695 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7725 11:55:37.171784 ==
7726 11:55:37.186203
7727 11:55:37.189444 TX Vref early break, caculate TX vref
7728 11:55:37.192730 TX Vref=16, minBit 1, minWin=22, winSum=366
7729 11:55:37.195879 TX Vref=18, minBit 8, minWin=22, winSum=380
7730 11:55:37.199164 TX Vref=20, minBit 7, minWin=23, winSum=389
7731 11:55:37.202501 TX Vref=22, minBit 1, minWin=24, winSum=397
7732 11:55:37.206012 TX Vref=24, minBit 1, minWin=24, winSum=411
7733 11:55:37.213035 TX Vref=26, minBit 1, minWin=25, winSum=418
7734 11:55:37.216179 TX Vref=28, minBit 1, minWin=25, winSum=417
7735 11:55:37.219073 TX Vref=30, minBit 2, minWin=25, winSum=419
7736 11:55:37.222510 TX Vref=32, minBit 1, minWin=24, winSum=407
7737 11:55:37.226230 TX Vref=34, minBit 0, minWin=24, winSum=400
7738 11:55:37.229074 TX Vref=36, minBit 2, minWin=23, winSum=390
7739 11:55:37.236149 [TxChooseVref] Worse bit 2, Min win 25, Win sum 419, Final Vref 30
7740 11:55:37.236268
7741 11:55:37.238811 Final TX Range 0 Vref 30
7742 11:55:37.238894
7743 11:55:37.238957 ==
7744 11:55:37.242177 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 11:55:37.245325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 11:55:37.245409 ==
7747 11:55:37.248422
7748 11:55:37.248504
7749 11:55:37.248568 TX Vref Scan disable
7750 11:55:37.255418 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7751 11:55:37.255553 == TX Byte 0 ==
7752 11:55:37.259144 u2DelayCellOfst[0]=10 cells (3 PI)
7753 11:55:37.261833 u2DelayCellOfst[1]=18 cells (5 PI)
7754 11:55:37.265125 u2DelayCellOfst[2]=10 cells (3 PI)
7755 11:55:37.268430 u2DelayCellOfst[3]=10 cells (3 PI)
7756 11:55:37.271873 u2DelayCellOfst[4]=7 cells (2 PI)
7757 11:55:37.274987 u2DelayCellOfst[5]=0 cells (0 PI)
7758 11:55:37.278703 u2DelayCellOfst[6]=14 cells (4 PI)
7759 11:55:37.281957 u2DelayCellOfst[7]=14 cells (4 PI)
7760 11:55:37.284768 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7761 11:55:37.288323 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7762 11:55:37.291470 == TX Byte 1 ==
7763 11:55:37.294536 u2DelayCellOfst[8]=0 cells (0 PI)
7764 11:55:37.297903 u2DelayCellOfst[9]=0 cells (0 PI)
7765 11:55:37.301611 u2DelayCellOfst[10]=7 cells (2 PI)
7766 11:55:37.304787 u2DelayCellOfst[11]=0 cells (0 PI)
7767 11:55:37.307919 u2DelayCellOfst[12]=10 cells (3 PI)
7768 11:55:37.311147 u2DelayCellOfst[13]=10 cells (3 PI)
7769 11:55:37.314846 u2DelayCellOfst[14]=14 cells (4 PI)
7770 11:55:37.318077 u2DelayCellOfst[15]=10 cells (3 PI)
7771 11:55:37.321204 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7772 11:55:37.324559 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7773 11:55:37.327687 DramC Write-DBI on
7774 11:55:37.327809 ==
7775 11:55:37.330945 Dram Type= 6, Freq= 0, CH_0, rank 0
7776 11:55:37.334175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7777 11:55:37.334288 ==
7778 11:55:37.334369
7779 11:55:37.334430
7780 11:55:37.337268 TX Vref Scan disable
7781 11:55:37.340632 == TX Byte 0 ==
7782 11:55:37.343975 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7783 11:55:37.344087 == TX Byte 1 ==
7784 11:55:37.351392 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7785 11:55:37.351499 DramC Write-DBI off
7786 11:55:37.351568
7787 11:55:37.351629 [DATLAT]
7788 11:55:37.354104 Freq=1600, CH0 RK0
7789 11:55:37.354188
7790 11:55:37.357308 DATLAT Default: 0xf
7791 11:55:37.357393 0, 0xFFFF, sum = 0
7792 11:55:37.360846 1, 0xFFFF, sum = 0
7793 11:55:37.360931 2, 0xFFFF, sum = 0
7794 11:55:37.363681 3, 0xFFFF, sum = 0
7795 11:55:37.363768 4, 0xFFFF, sum = 0
7796 11:55:37.367185 5, 0xFFFF, sum = 0
7797 11:55:37.367272 6, 0xFFFF, sum = 0
7798 11:55:37.370496 7, 0xFFFF, sum = 0
7799 11:55:37.370583 8, 0xFFFF, sum = 0
7800 11:55:37.374161 9, 0xFFFF, sum = 0
7801 11:55:37.374280 10, 0xFFFF, sum = 0
7802 11:55:37.377129 11, 0xFFFF, sum = 0
7803 11:55:37.377214 12, 0xFFFF, sum = 0
7804 11:55:37.380669 13, 0xFFFF, sum = 0
7805 11:55:37.383673 14, 0x0, sum = 1
7806 11:55:37.383759 15, 0x0, sum = 2
7807 11:55:37.383826 16, 0x0, sum = 3
7808 11:55:37.387832 17, 0x0, sum = 4
7809 11:55:37.387920 best_step = 15
7810 11:55:37.387985
7811 11:55:37.388046 ==
7812 11:55:37.389975 Dram Type= 6, Freq= 0, CH_0, rank 0
7813 11:55:37.396784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7814 11:55:37.396879 ==
7815 11:55:37.396945 RX Vref Scan: 1
7816 11:55:37.397005
7817 11:55:37.400408 Set Vref Range= 24 -> 127
7818 11:55:37.400494
7819 11:55:37.403400 RX Vref 24 -> 127, step: 1
7820 11:55:37.403484
7821 11:55:37.406204 RX Delay 11 -> 252, step: 4
7822 11:55:37.406297
7823 11:55:37.410444 Set Vref, RX VrefLevel [Byte0]: 24
7824 11:55:37.413709 [Byte1]: 24
7825 11:55:37.413801
7826 11:55:37.416153 Set Vref, RX VrefLevel [Byte0]: 25
7827 11:55:37.419801 [Byte1]: 25
7828 11:55:37.419887
7829 11:55:37.422799 Set Vref, RX VrefLevel [Byte0]: 26
7830 11:55:37.426069 [Byte1]: 26
7831 11:55:37.429751
7832 11:55:37.429837 Set Vref, RX VrefLevel [Byte0]: 27
7833 11:55:37.433001 [Byte1]: 27
7834 11:55:37.437525
7835 11:55:37.437615 Set Vref, RX VrefLevel [Byte0]: 28
7836 11:55:37.440480 [Byte1]: 28
7837 11:55:37.445129
7838 11:55:37.445219 Set Vref, RX VrefLevel [Byte0]: 29
7839 11:55:37.450226 [Byte1]: 29
7840 11:55:37.452647
7841 11:55:37.452739 Set Vref, RX VrefLevel [Byte0]: 30
7842 11:55:37.455731 [Byte1]: 30
7843 11:55:37.460305
7844 11:55:37.460398 Set Vref, RX VrefLevel [Byte0]: 31
7845 11:55:37.463618 [Byte1]: 31
7846 11:55:37.468480
7847 11:55:37.468577 Set Vref, RX VrefLevel [Byte0]: 32
7848 11:55:37.471220 [Byte1]: 32
7849 11:55:37.475682
7850 11:55:37.475769 Set Vref, RX VrefLevel [Byte0]: 33
7851 11:55:37.479185 [Byte1]: 33
7852 11:55:37.483051
7853 11:55:37.483141 Set Vref, RX VrefLevel [Byte0]: 34
7854 11:55:37.486425 [Byte1]: 34
7855 11:55:37.490627
7856 11:55:37.490761 Set Vref, RX VrefLevel [Byte0]: 35
7857 11:55:37.493656 [Byte1]: 35
7858 11:55:37.498985
7859 11:55:37.499079 Set Vref, RX VrefLevel [Byte0]: 36
7860 11:55:37.501858 [Byte1]: 36
7861 11:55:37.506197
7862 11:55:37.506309 Set Vref, RX VrefLevel [Byte0]: 37
7863 11:55:37.509268 [Byte1]: 37
7864 11:55:37.513656
7865 11:55:37.513756 Set Vref, RX VrefLevel [Byte0]: 38
7866 11:55:37.516963 [Byte1]: 38
7867 11:55:37.521226
7868 11:55:37.521320 Set Vref, RX VrefLevel [Byte0]: 39
7869 11:55:37.524444 [Byte1]: 39
7870 11:55:37.528631
7871 11:55:37.528721 Set Vref, RX VrefLevel [Byte0]: 40
7872 11:55:37.532087 [Byte1]: 40
7873 11:55:37.536408
7874 11:55:37.536500 Set Vref, RX VrefLevel [Byte0]: 41
7875 11:55:37.540431 [Byte1]: 41
7876 11:55:37.544065
7877 11:55:37.544157 Set Vref, RX VrefLevel [Byte0]: 42
7878 11:55:37.547508 [Byte1]: 42
7879 11:55:37.551685
7880 11:55:37.551783 Set Vref, RX VrefLevel [Byte0]: 43
7881 11:55:37.555878 [Byte1]: 43
7882 11:55:37.559071
7883 11:55:37.559164 Set Vref, RX VrefLevel [Byte0]: 44
7884 11:55:37.562730 [Byte1]: 44
7885 11:55:37.567094
7886 11:55:37.567210 Set Vref, RX VrefLevel [Byte0]: 45
7887 11:55:37.570215 [Byte1]: 45
7888 11:55:37.574996
7889 11:55:37.575086 Set Vref, RX VrefLevel [Byte0]: 46
7890 11:55:37.577755 [Byte1]: 46
7891 11:55:37.582066
7892 11:55:37.582181 Set Vref, RX VrefLevel [Byte0]: 47
7893 11:55:37.585463 [Byte1]: 47
7894 11:55:37.589836
7895 11:55:37.589930 Set Vref, RX VrefLevel [Byte0]: 48
7896 11:55:37.592929 [Byte1]: 48
7897 11:55:37.597720
7898 11:55:37.597813 Set Vref, RX VrefLevel [Byte0]: 49
7899 11:55:37.600360 [Byte1]: 49
7900 11:55:37.605395
7901 11:55:37.605486 Set Vref, RX VrefLevel [Byte0]: 50
7902 11:55:37.608233 [Byte1]: 50
7903 11:55:37.612533
7904 11:55:37.612630 Set Vref, RX VrefLevel [Byte0]: 51
7905 11:55:37.616122 [Byte1]: 51
7906 11:55:37.620434
7907 11:55:37.620526 Set Vref, RX VrefLevel [Byte0]: 52
7908 11:55:37.623416 [Byte1]: 52
7909 11:55:37.627882
7910 11:55:37.627972 Set Vref, RX VrefLevel [Byte0]: 53
7911 11:55:37.631204 [Byte1]: 53
7912 11:55:37.635291
7913 11:55:37.635378 Set Vref, RX VrefLevel [Byte0]: 54
7914 11:55:37.638650 [Byte1]: 54
7915 11:55:37.642960
7916 11:55:37.643051 Set Vref, RX VrefLevel [Byte0]: 55
7917 11:55:37.646830 [Byte1]: 55
7918 11:55:37.650659
7919 11:55:37.650776 Set Vref, RX VrefLevel [Byte0]: 56
7920 11:55:37.654214 [Byte1]: 56
7921 11:55:37.658215
7922 11:55:37.658403 Set Vref, RX VrefLevel [Byte0]: 57
7923 11:55:37.661892 [Byte1]: 57
7924 11:55:37.666488
7925 11:55:37.666607 Set Vref, RX VrefLevel [Byte0]: 58
7926 11:55:37.669100 [Byte1]: 58
7927 11:55:37.673685
7928 11:55:37.673774 Set Vref, RX VrefLevel [Byte0]: 59
7929 11:55:37.676734 [Byte1]: 59
7930 11:55:37.681007
7931 11:55:37.681106 Set Vref, RX VrefLevel [Byte0]: 60
7932 11:55:37.684213 [Byte1]: 60
7933 11:55:37.688735
7934 11:55:37.688828 Set Vref, RX VrefLevel [Byte0]: 61
7935 11:55:37.692095 [Byte1]: 61
7936 11:55:37.696304
7937 11:55:37.696399 Set Vref, RX VrefLevel [Byte0]: 62
7938 11:55:37.699417 [Byte1]: 62
7939 11:55:37.703925
7940 11:55:37.704018 Set Vref, RX VrefLevel [Byte0]: 63
7941 11:55:37.707532 [Byte1]: 63
7942 11:55:37.711435
7943 11:55:37.711526 Set Vref, RX VrefLevel [Byte0]: 64
7944 11:55:37.715212 [Byte1]: 64
7945 11:55:37.719175
7946 11:55:37.719271 Set Vref, RX VrefLevel [Byte0]: 65
7947 11:55:37.722233 [Byte1]: 65
7948 11:55:37.726618
7949 11:55:37.726710 Set Vref, RX VrefLevel [Byte0]: 66
7950 11:55:37.730473 [Byte1]: 66
7951 11:55:37.734308
7952 11:55:37.734395 Set Vref, RX VrefLevel [Byte0]: 67
7953 11:55:37.737519 [Byte1]: 67
7954 11:55:37.742222
7955 11:55:37.742347 Set Vref, RX VrefLevel [Byte0]: 68
7956 11:55:37.745251 [Byte1]: 68
7957 11:55:37.749897
7958 11:55:37.749988 Set Vref, RX VrefLevel [Byte0]: 69
7959 11:55:37.753229 [Byte1]: 69
7960 11:55:37.756985
7961 11:55:37.757122 Set Vref, RX VrefLevel [Byte0]: 70
7962 11:55:37.760355 [Byte1]: 70
7963 11:55:37.764833
7964 11:55:37.764921 Set Vref, RX VrefLevel [Byte0]: 71
7965 11:55:37.768165 [Byte1]: 71
7966 11:55:37.772456
7967 11:55:37.772542 Set Vref, RX VrefLevel [Byte0]: 72
7968 11:55:37.776204 [Byte1]: 72
7969 11:55:37.779910
7970 11:55:37.779994 Set Vref, RX VrefLevel [Byte0]: 73
7971 11:55:37.783372 [Byte1]: 73
7972 11:55:37.787777
7973 11:55:37.787863 Final RX Vref Byte 0 = 56 to rank0
7974 11:55:37.791098 Final RX Vref Byte 1 = 62 to rank0
7975 11:55:37.794197 Final RX Vref Byte 0 = 56 to rank1
7976 11:55:37.797547 Final RX Vref Byte 1 = 62 to rank1==
7977 11:55:37.801021 Dram Type= 6, Freq= 0, CH_0, rank 0
7978 11:55:37.807431 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7979 11:55:37.807533 ==
7980 11:55:37.807598 DQS Delay:
7981 11:55:37.807659 DQS0 = 0, DQS1 = 0
7982 11:55:37.811139 DQM Delay:
7983 11:55:37.811223 DQM0 = 128, DQM1 = 124
7984 11:55:37.814723 DQ Delay:
7985 11:55:37.817609 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7986 11:55:37.821061 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7987 11:55:37.824275 DQ8 =114, DQ9 =112, DQ10 =124, DQ11 =120
7988 11:55:37.827974 DQ12 =130, DQ13 =132, DQ14 =132, DQ15 =128
7989 11:55:37.828059
7990 11:55:37.828124
7991 11:55:37.828182
7992 11:55:37.831162 [DramC_TX_OE_Calibration] TA2
7993 11:55:37.834578 Original DQ_B0 (3 6) =30, OEN = 27
7994 11:55:37.837571 Original DQ_B1 (3 6) =30, OEN = 27
7995 11:55:37.840606 24, 0x0, End_B0=24 End_B1=24
7996 11:55:37.840689 25, 0x0, End_B0=25 End_B1=25
7997 11:55:37.843598 26, 0x0, End_B0=26 End_B1=26
7998 11:55:37.847257 27, 0x0, End_B0=27 End_B1=27
7999 11:55:37.850541 28, 0x0, End_B0=28 End_B1=28
8000 11:55:37.853801 29, 0x0, End_B0=29 End_B1=29
8001 11:55:37.853893 30, 0x0, End_B0=30 End_B1=30
8002 11:55:37.857057 31, 0x5151, End_B0=30 End_B1=30
8003 11:55:37.860365 Byte0 end_step=30 best_step=27
8004 11:55:37.863799 Byte1 end_step=30 best_step=27
8005 11:55:37.867033 Byte0 TX OE(2T, 0.5T) = (3, 3)
8006 11:55:37.870486 Byte1 TX OE(2T, 0.5T) = (3, 3)
8007 11:55:37.870574
8008 11:55:37.870641
8009 11:55:37.876735 [DQSOSCAuto] RK0, (LSB)MR18= 0x1513, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8010 11:55:37.879785 CH0 RK0: MR19=303, MR18=1513
8011 11:55:37.886697 CH0_RK0: MR19=0x303, MR18=0x1513, DQSOSC=399, MR23=63, INC=23, DEC=15
8012 11:55:37.886797
8013 11:55:37.889995 ----->DramcWriteLeveling(PI) begin...
8014 11:55:37.890081 ==
8015 11:55:37.893270 Dram Type= 6, Freq= 0, CH_0, rank 1
8016 11:55:37.896316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8017 11:55:37.896403 ==
8018 11:55:37.900354 Write leveling (Byte 0): 35 => 35
8019 11:55:37.902932 Write leveling (Byte 1): 27 => 27
8020 11:55:37.906215 DramcWriteLeveling(PI) end<-----
8021 11:55:37.906336
8022 11:55:37.906401 ==
8023 11:55:37.909430 Dram Type= 6, Freq= 0, CH_0, rank 1
8024 11:55:37.916396 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8025 11:55:37.916504 ==
8026 11:55:37.916570 [Gating] SW mode calibration
8027 11:55:37.926210 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8028 11:55:37.929846 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8029 11:55:37.932329 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8030 11:55:37.939215 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8031 11:55:37.942556 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8032 11:55:37.946049 1 4 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8033 11:55:37.952270 1 4 16 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8034 11:55:37.955616 1 4 20 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8035 11:55:37.962246 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8036 11:55:37.965262 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8037 11:55:37.968886 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8038 11:55:37.972060 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8039 11:55:37.978998 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8040 11:55:37.982268 1 5 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 0)
8041 11:55:37.988587 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8042 11:55:37.991801 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (0 1) (0 0)
8043 11:55:37.995549 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8044 11:55:38.001570 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8045 11:55:38.005323 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8046 11:55:38.008502 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8047 11:55:38.011409 1 6 8 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
8048 11:55:38.018482 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8049 11:55:38.021832 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8050 11:55:38.028167 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8051 11:55:38.031503 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8052 11:55:38.035003 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8053 11:55:38.041383 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 11:55:38.044479 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 11:55:38.047749 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8056 11:55:38.054474 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8057 11:55:38.057843 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8058 11:55:38.060792 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8059 11:55:38.067594 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 11:55:38.070775 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 11:55:38.074712 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 11:55:38.081031 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 11:55:38.083784 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 11:55:38.087750 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 11:55:38.093924 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 11:55:38.097264 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 11:55:38.100617 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 11:55:38.107537 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 11:55:38.110062 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8070 11:55:38.113688 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8071 11:55:38.120215 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8072 11:55:38.123514 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8073 11:55:38.126866 Total UI for P1: 0, mck2ui 16
8074 11:55:38.130378 best dqsien dly found for B0: ( 1, 9, 4)
8075 11:55:38.133383 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 11:55:38.139976 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8077 11:55:38.143997 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:55:38.147104 Total UI for P1: 0, mck2ui 16
8079 11:55:38.149975 best dqsien dly found for B1: ( 1, 9, 18)
8080 11:55:38.153644 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8081 11:55:38.156576 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8082 11:55:38.156670
8083 11:55:38.159647 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8084 11:55:38.163190 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8085 11:55:38.166270 [Gating] SW calibration Done
8086 11:55:38.166360 ==
8087 11:55:38.169630 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 11:55:38.173305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 11:55:38.176332 ==
8090 11:55:38.176421 RX Vref Scan: 0
8091 11:55:38.176508
8092 11:55:38.179464 RX Vref 0 -> 0, step: 1
8093 11:55:38.179550
8094 11:55:38.179636 RX Delay 0 -> 252, step: 8
8095 11:55:38.186226 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8096 11:55:38.189314 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8097 11:55:38.192695 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8098 11:55:38.196158 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8099 11:55:38.199262 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8100 11:55:38.205791 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8101 11:55:38.209364 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8102 11:55:38.212529 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8103 11:55:38.215678 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8104 11:55:38.222189 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8105 11:55:38.225942 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8106 11:55:38.228887 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8107 11:55:38.232004 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8108 11:55:38.235617 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8109 11:55:38.241804 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8110 11:55:38.245147 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8111 11:55:38.245244 ==
8112 11:55:38.249296 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 11:55:38.252000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 11:55:38.252089 ==
8115 11:55:38.255696 DQS Delay:
8116 11:55:38.255789 DQS0 = 0, DQS1 = 0
8117 11:55:38.258614 DQM Delay:
8118 11:55:38.258700 DQM0 = 131, DQM1 = 127
8119 11:55:38.258786 DQ Delay:
8120 11:55:38.261440 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8121 11:55:38.268494 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8122 11:55:38.271464 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8123 11:55:38.274990 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8124 11:55:38.275083
8125 11:55:38.275171
8126 11:55:38.275252 ==
8127 11:55:38.277902 Dram Type= 6, Freq= 0, CH_0, rank 1
8128 11:55:38.281796 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8129 11:55:38.281885 ==
8130 11:55:38.281971
8131 11:55:38.282069
8132 11:55:38.284773 TX Vref Scan disable
8133 11:55:38.287899 == TX Byte 0 ==
8134 11:55:38.291218 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8135 11:55:38.294426 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8136 11:55:38.297738 == TX Byte 1 ==
8137 11:55:38.301252 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8138 11:55:38.304966 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8139 11:55:38.305058 ==
8140 11:55:38.307745 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 11:55:38.314388 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 11:55:38.314485 ==
8143 11:55:38.326600
8144 11:55:38.329826 TX Vref early break, caculate TX vref
8145 11:55:38.333694 TX Vref=16, minBit 9, minWin=22, winSum=381
8146 11:55:38.336756 TX Vref=18, minBit 8, minWin=23, winSum=391
8147 11:55:38.339940 TX Vref=20, minBit 3, minWin=24, winSum=396
8148 11:55:38.343613 TX Vref=22, minBit 10, minWin=24, winSum=403
8149 11:55:38.349466 TX Vref=24, minBit 0, minWin=25, winSum=419
8150 11:55:38.353552 TX Vref=26, minBit 4, minWin=25, winSum=418
8151 11:55:38.356185 TX Vref=28, minBit 3, minWin=25, winSum=418
8152 11:55:38.359783 TX Vref=30, minBit 3, minWin=25, winSum=420
8153 11:55:38.363152 TX Vref=32, minBit 7, minWin=24, winSum=408
8154 11:55:38.366568 TX Vref=34, minBit 0, minWin=24, winSum=396
8155 11:55:38.372963 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 30
8156 11:55:38.373068
8157 11:55:38.376253 Final TX Range 0 Vref 30
8158 11:55:38.376341
8159 11:55:38.376431 ==
8160 11:55:38.379400 Dram Type= 6, Freq= 0, CH_0, rank 1
8161 11:55:38.383083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8162 11:55:38.383179 ==
8163 11:55:38.383265
8164 11:55:38.385632
8165 11:55:38.385717 TX Vref Scan disable
8166 11:55:38.392453 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8167 11:55:38.392555 == TX Byte 0 ==
8168 11:55:38.395574 u2DelayCellOfst[0]=14 cells (4 PI)
8169 11:55:38.398993 u2DelayCellOfst[1]=18 cells (5 PI)
8170 11:55:38.402148 u2DelayCellOfst[2]=14 cells (4 PI)
8171 11:55:38.405813 u2DelayCellOfst[3]=14 cells (4 PI)
8172 11:55:38.408756 u2DelayCellOfst[4]=10 cells (3 PI)
8173 11:55:38.412190 u2DelayCellOfst[5]=0 cells (0 PI)
8174 11:55:38.415256 u2DelayCellOfst[6]=18 cells (5 PI)
8175 11:55:38.418647 u2DelayCellOfst[7]=18 cells (5 PI)
8176 11:55:38.422152 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8177 11:55:38.425036 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8178 11:55:38.428636 == TX Byte 1 ==
8179 11:55:38.432242 u2DelayCellOfst[8]=0 cells (0 PI)
8180 11:55:38.435425 u2DelayCellOfst[9]=0 cells (0 PI)
8181 11:55:38.438161 u2DelayCellOfst[10]=7 cells (2 PI)
8182 11:55:38.442040 u2DelayCellOfst[11]=0 cells (0 PI)
8183 11:55:38.445119 u2DelayCellOfst[12]=10 cells (3 PI)
8184 11:55:38.448703 u2DelayCellOfst[13]=10 cells (3 PI)
8185 11:55:38.452170 u2DelayCellOfst[14]=18 cells (5 PI)
8186 11:55:38.452263 u2DelayCellOfst[15]=10 cells (3 PI)
8187 11:55:38.458079 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8188 11:55:38.461999 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8189 11:55:38.465113 DramC Write-DBI on
8190 11:55:38.465209 ==
8191 11:55:38.467932 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 11:55:38.471370 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 11:55:38.471462 ==
8194 11:55:38.471548
8195 11:55:38.471629
8196 11:55:38.474730 TX Vref Scan disable
8197 11:55:38.474815 == TX Byte 0 ==
8198 11:55:38.481384 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8199 11:55:38.481481 == TX Byte 1 ==
8200 11:55:38.484537 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8201 11:55:38.487670 DramC Write-DBI off
8202 11:55:38.487761
8203 11:55:38.487848 [DATLAT]
8204 11:55:38.491148 Freq=1600, CH0 RK1
8205 11:55:38.491236
8206 11:55:38.491322 DATLAT Default: 0xf
8207 11:55:38.494442 0, 0xFFFF, sum = 0
8208 11:55:38.497978 1, 0xFFFF, sum = 0
8209 11:55:38.498071 2, 0xFFFF, sum = 0
8210 11:55:38.501395 3, 0xFFFF, sum = 0
8211 11:55:38.501482 4, 0xFFFF, sum = 0
8212 11:55:38.504602 5, 0xFFFF, sum = 0
8213 11:55:38.504691 6, 0xFFFF, sum = 0
8214 11:55:38.508073 7, 0xFFFF, sum = 0
8215 11:55:38.508161 8, 0xFFFF, sum = 0
8216 11:55:38.511536 9, 0xFFFF, sum = 0
8217 11:55:38.511625 10, 0xFFFF, sum = 0
8218 11:55:38.514238 11, 0xFFFF, sum = 0
8219 11:55:38.514363 12, 0xFFFF, sum = 0
8220 11:55:38.517566 13, 0xFFFF, sum = 0
8221 11:55:38.517654 14, 0x0, sum = 1
8222 11:55:38.520766 15, 0x0, sum = 2
8223 11:55:38.520854 16, 0x0, sum = 3
8224 11:55:38.524632 17, 0x0, sum = 4
8225 11:55:38.524721 best_step = 15
8226 11:55:38.524807
8227 11:55:38.524887 ==
8228 11:55:38.527493 Dram Type= 6, Freq= 0, CH_0, rank 1
8229 11:55:38.533987 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8230 11:55:38.534109 ==
8231 11:55:38.534220 RX Vref Scan: 0
8232 11:55:38.534304
8233 11:55:38.537893 RX Vref 0 -> 0, step: 1
8234 11:55:38.537976
8235 11:55:38.540487 RX Delay 19 -> 252, step: 4
8236 11:55:38.544086 iDelay=187, Bit 0, Center 126 (75 ~ 178) 104
8237 11:55:38.547036 iDelay=187, Bit 1, Center 132 (79 ~ 186) 108
8238 11:55:38.550691 iDelay=187, Bit 2, Center 126 (75 ~ 178) 104
8239 11:55:38.557069 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8240 11:55:38.560453 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8241 11:55:38.564102 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8242 11:55:38.567489 iDelay=187, Bit 6, Center 138 (91 ~ 186) 96
8243 11:55:38.570139 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8244 11:55:38.576683 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8245 11:55:38.579926 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8246 11:55:38.583679 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8247 11:55:38.586753 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8248 11:55:38.593466 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8249 11:55:38.596629 iDelay=187, Bit 13, Center 130 (79 ~ 182) 104
8250 11:55:38.600145 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8251 11:55:38.603311 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8252 11:55:38.603403 ==
8253 11:55:38.606531 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 11:55:38.612919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 11:55:38.613023 ==
8256 11:55:38.613089 DQS Delay:
8257 11:55:38.616626 DQS0 = 0, DQS1 = 0
8258 11:55:38.616818 DQM Delay:
8259 11:55:38.616923 DQM0 = 129, DQM1 = 123
8260 11:55:38.619957 DQ Delay:
8261 11:55:38.623321 DQ0 =126, DQ1 =132, DQ2 =126, DQ3 =126
8262 11:55:38.626271 DQ4 =132, DQ5 =118, DQ6 =138, DQ7 =134
8263 11:55:38.629553 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8264 11:55:38.632757 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =128
8265 11:55:38.632921
8266 11:55:38.632993
8267 11:55:38.633062
8268 11:55:38.636225 [DramC_TX_OE_Calibration] TA2
8269 11:55:38.639513 Original DQ_B0 (3 6) =30, OEN = 27
8270 11:55:38.642547 Original DQ_B1 (3 6) =30, OEN = 27
8271 11:55:38.645911 24, 0x0, End_B0=24 End_B1=24
8272 11:55:38.649498 25, 0x0, End_B0=25 End_B1=25
8273 11:55:38.649594 26, 0x0, End_B0=26 End_B1=26
8274 11:55:38.653080 27, 0x0, End_B0=27 End_B1=27
8275 11:55:38.656320 28, 0x0, End_B0=28 End_B1=28
8276 11:55:38.659510 29, 0x0, End_B0=29 End_B1=29
8277 11:55:38.659603 30, 0x0, End_B0=30 End_B1=30
8278 11:55:38.662422 31, 0x4141, End_B0=30 End_B1=30
8279 11:55:38.666147 Byte0 end_step=30 best_step=27
8280 11:55:38.669067 Byte1 end_step=30 best_step=27
8281 11:55:38.672092 Byte0 TX OE(2T, 0.5T) = (3, 3)
8282 11:55:38.675622 Byte1 TX OE(2T, 0.5T) = (3, 3)
8283 11:55:38.675727
8284 11:55:38.675793
8285 11:55:38.682505 [DQSOSCAuto] RK1, (LSB)MR18= 0x1614, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8286 11:55:38.685637 CH0 RK1: MR19=303, MR18=1614
8287 11:55:38.692283 CH0_RK1: MR19=0x303, MR18=0x1614, DQSOSC=398, MR23=63, INC=23, DEC=15
8288 11:55:38.695250 [RxdqsGatingPostProcess] freq 1600
8289 11:55:38.701980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8290 11:55:38.702091 best DQS0 dly(2T, 0.5T) = (1, 1)
8291 11:55:38.705518 best DQS1 dly(2T, 0.5T) = (1, 1)
8292 11:55:38.708500 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8293 11:55:38.712010 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8294 11:55:38.715105 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 11:55:38.718761 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 11:55:38.721725 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 11:55:38.725214 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 11:55:38.728345 Pre-setting of DQS Precalculation
8299 11:55:38.731514 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8300 11:55:38.735090 ==
8301 11:55:38.735177 Dram Type= 6, Freq= 0, CH_1, rank 0
8302 11:55:38.741187 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8303 11:55:38.741282 ==
8304 11:55:38.744625 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8305 11:55:38.751167 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8306 11:55:38.754781 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8307 11:55:38.761161 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8308 11:55:38.769191 [CA 0] Center 42 (13~72) winsize 60
8309 11:55:38.772561 [CA 1] Center 42 (13~72) winsize 60
8310 11:55:38.776587 [CA 2] Center 38 (9~68) winsize 60
8311 11:55:38.779372 [CA 3] Center 37 (8~67) winsize 60
8312 11:55:38.782355 [CA 4] Center 38 (8~68) winsize 61
8313 11:55:38.785525 [CA 5] Center 37 (7~67) winsize 61
8314 11:55:38.785613
8315 11:55:38.789191 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8316 11:55:38.789276
8317 11:55:38.792423 [CATrainingPosCal] consider 1 rank data
8318 11:55:38.795643 u2DelayCellTimex100 = 271/100 ps
8319 11:55:38.802371 CA0 delay=42 (13~72),Diff = 5 PI (18 cell)
8320 11:55:38.805706 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8321 11:55:38.808795 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8322 11:55:38.812358 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8323 11:55:38.816299 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8324 11:55:38.819091 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8325 11:55:38.819176
8326 11:55:38.822192 CA PerBit enable=1, Macro0, CA PI delay=37
8327 11:55:38.822322
8328 11:55:38.825536 [CBTSetCACLKResult] CA Dly = 37
8329 11:55:38.828713 CS Dly: 8 (0~39)
8330 11:55:38.832078 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8331 11:55:38.835782 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8332 11:55:38.835867 ==
8333 11:55:38.838632 Dram Type= 6, Freq= 0, CH_1, rank 1
8334 11:55:38.845029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8335 11:55:38.845164 ==
8336 11:55:38.848770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8337 11:55:38.854884 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8338 11:55:38.858530 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8339 11:55:38.864996 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8340 11:55:38.872328 [CA 0] Center 41 (12~71) winsize 60
8341 11:55:38.876088 [CA 1] Center 42 (13~71) winsize 59
8342 11:55:38.879120 [CA 2] Center 37 (8~67) winsize 60
8343 11:55:38.882539 [CA 3] Center 36 (7~66) winsize 60
8344 11:55:38.885542 [CA 4] Center 37 (7~67) winsize 61
8345 11:55:38.888739 [CA 5] Center 36 (7~66) winsize 60
8346 11:55:38.888824
8347 11:55:38.892297 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8348 11:55:38.892380
8349 11:55:38.895781 [CATrainingPosCal] consider 2 rank data
8350 11:55:38.898699 u2DelayCellTimex100 = 271/100 ps
8351 11:55:38.905429 CA0 delay=42 (13~71),Diff = 6 PI (21 cell)
8352 11:55:38.908501 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8353 11:55:38.912190 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8354 11:55:38.915320 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8355 11:55:38.918373 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8356 11:55:38.922306 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8357 11:55:38.922400
8358 11:55:38.925218 CA PerBit enable=1, Macro0, CA PI delay=36
8359 11:55:38.925301
8360 11:55:38.928297 [CBTSetCACLKResult] CA Dly = 36
8361 11:55:38.931786 CS Dly: 9 (0~42)
8362 11:55:38.935140 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8363 11:55:38.938904 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8364 11:55:38.938988
8365 11:55:38.941459 ----->DramcWriteLeveling(PI) begin...
8366 11:55:38.941542 ==
8367 11:55:38.944895 Dram Type= 6, Freq= 0, CH_1, rank 0
8368 11:55:38.951766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8369 11:55:38.951866 ==
8370 11:55:38.954959 Write leveling (Byte 0): 25 => 25
8371 11:55:38.958083 Write leveling (Byte 1): 28 => 28
8372 11:55:38.958193 DramcWriteLeveling(PI) end<-----
8373 11:55:38.958319
8374 11:55:38.961693 ==
8375 11:55:38.964966 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 11:55:38.968476 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 11:55:38.968642 ==
8378 11:55:38.971240 [Gating] SW mode calibration
8379 11:55:38.977919 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8380 11:55:38.981363 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8381 11:55:38.988051 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8382 11:55:38.991585 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 11:55:38.994670 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8384 11:55:39.001496 1 4 12 | B1->B0 | 2525 3333 | 1 0 | (1 1) (0 0)
8385 11:55:39.004684 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 11:55:39.008214 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 11:55:39.014520 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 11:55:39.017616 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 11:55:39.020668 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 11:55:39.027210 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 11:55:39.030243 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8392 11:55:39.033782 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8393 11:55:39.040630 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 11:55:39.043805 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8395 11:55:39.047167 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 11:55:39.053474 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 11:55:39.056742 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 11:55:39.060129 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 11:55:39.066715 1 6 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8400 11:55:39.069877 1 6 12 | B1->B0 | 2828 4545 | 0 0 | (0 0) (0 0)
8401 11:55:39.073912 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 11:55:39.079818 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 11:55:39.083669 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 11:55:39.090654 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 11:55:39.093542 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 11:55:39.096444 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 11:55:39.099668 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8408 11:55:39.106190 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 11:55:39.109726 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8410 11:55:39.113422 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 11:55:39.119486 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 11:55:39.122808 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 11:55:39.126165 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 11:55:39.132777 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 11:55:39.136152 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 11:55:39.139436 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 11:55:39.145713 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 11:55:39.149340 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:55:39.152394 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:55:39.159003 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 11:55:39.162206 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 11:55:39.168762 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 11:55:39.172076 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8424 11:55:39.175220 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 11:55:39.182205 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:55:39.182313 Total UI for P1: 0, mck2ui 16
8427 11:55:39.185490 best dqsien dly found for B0: ( 1, 9, 10)
8428 11:55:39.188628 Total UI for P1: 0, mck2ui 16
8429 11:55:39.192219 best dqsien dly found for B1: ( 1, 9, 12)
8430 11:55:39.195105 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8431 11:55:39.202351 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8432 11:55:39.202460
8433 11:55:39.205247 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8434 11:55:39.208466 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8435 11:55:39.211531 [Gating] SW calibration Done
8436 11:55:39.211619 ==
8437 11:55:39.214925 Dram Type= 6, Freq= 0, CH_1, rank 0
8438 11:55:39.218078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8439 11:55:39.218166 ==
8440 11:55:39.221777 RX Vref Scan: 0
8441 11:55:39.221861
8442 11:55:39.221927 RX Vref 0 -> 0, step: 1
8443 11:55:39.221987
8444 11:55:39.224764 RX Delay 0 -> 252, step: 8
8445 11:55:39.227953 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8446 11:55:39.234875 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8447 11:55:39.238526 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8448 11:55:39.241512 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8449 11:55:39.244743 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8450 11:55:39.247774 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8451 11:55:39.254678 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8452 11:55:39.258005 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8453 11:55:39.261487 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8454 11:55:39.264110 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8455 11:55:39.267751 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8456 11:55:39.274059 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8457 11:55:39.277321 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8458 11:55:39.280713 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8459 11:55:39.284269 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8460 11:55:39.291179 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8461 11:55:39.291289 ==
8462 11:55:39.294141 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 11:55:39.297340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 11:55:39.297428 ==
8465 11:55:39.297494 DQS Delay:
8466 11:55:39.300411 DQS0 = 0, DQS1 = 0
8467 11:55:39.300495 DQM Delay:
8468 11:55:39.303845 DQM0 = 135, DQM1 = 130
8469 11:55:39.303930 DQ Delay:
8470 11:55:39.307415 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8471 11:55:39.310646 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =127
8472 11:55:39.313978 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8473 11:55:39.317476 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8474 11:55:39.317565
8475 11:55:39.317630
8476 11:55:39.320278 ==
8477 11:55:39.323694 Dram Type= 6, Freq= 0, CH_1, rank 0
8478 11:55:39.327146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8479 11:55:39.327233 ==
8480 11:55:39.327298
8481 11:55:39.327357
8482 11:55:39.330409 TX Vref Scan disable
8483 11:55:39.330493 == TX Byte 0 ==
8484 11:55:39.336876 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8485 11:55:39.340247 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8486 11:55:39.340337 == TX Byte 1 ==
8487 11:55:39.347209 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8488 11:55:39.350092 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8489 11:55:39.350184 ==
8490 11:55:39.353287 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 11:55:39.356740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 11:55:39.356834 ==
8493 11:55:39.371936
8494 11:55:39.374660 TX Vref early break, caculate TX vref
8495 11:55:39.377901 TX Vref=16, minBit 8, minWin=22, winSum=370
8496 11:55:39.380954 TX Vref=18, minBit 8, minWin=21, winSum=377
8497 11:55:39.384510 TX Vref=20, minBit 8, minWin=23, winSum=389
8498 11:55:39.387618 TX Vref=22, minBit 8, minWin=23, winSum=397
8499 11:55:39.391427 TX Vref=24, minBit 1, minWin=25, winSum=409
8500 11:55:39.397692 TX Vref=26, minBit 9, minWin=24, winSum=410
8501 11:55:39.401078 TX Vref=28, minBit 3, minWin=25, winSum=416
8502 11:55:39.404021 TX Vref=30, minBit 0, minWin=24, winSum=415
8503 11:55:39.407809 TX Vref=32, minBit 0, minWin=24, winSum=405
8504 11:55:39.410667 TX Vref=34, minBit 15, minWin=23, winSum=396
8505 11:55:39.417801 TX Vref=36, minBit 9, minWin=22, winSum=383
8506 11:55:39.420802 [TxChooseVref] Worse bit 3, Min win 25, Win sum 416, Final Vref 28
8507 11:55:39.420893
8508 11:55:39.423999 Final TX Range 0 Vref 28
8509 11:55:39.424085
8510 11:55:39.424151 ==
8511 11:55:39.427645 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 11:55:39.430511 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 11:55:39.434175 ==
8514 11:55:39.434292
8515 11:55:39.434361
8516 11:55:39.434423 TX Vref Scan disable
8517 11:55:39.440486 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8518 11:55:39.440579 == TX Byte 0 ==
8519 11:55:39.443982 u2DelayCellOfst[0]=14 cells (4 PI)
8520 11:55:39.447286 u2DelayCellOfst[1]=10 cells (3 PI)
8521 11:55:39.450475 u2DelayCellOfst[2]=0 cells (0 PI)
8522 11:55:39.454410 u2DelayCellOfst[3]=7 cells (2 PI)
8523 11:55:39.456814 u2DelayCellOfst[4]=7 cells (2 PI)
8524 11:55:39.460369 u2DelayCellOfst[5]=14 cells (4 PI)
8525 11:55:39.463975 u2DelayCellOfst[6]=14 cells (4 PI)
8526 11:55:39.467106 u2DelayCellOfst[7]=7 cells (2 PI)
8527 11:55:39.470400 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8528 11:55:39.473564 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8529 11:55:39.476658 == TX Byte 1 ==
8530 11:55:39.480433 u2DelayCellOfst[8]=0 cells (0 PI)
8531 11:55:39.483729 u2DelayCellOfst[9]=3 cells (1 PI)
8532 11:55:39.486715 u2DelayCellOfst[10]=10 cells (3 PI)
8533 11:55:39.489970 u2DelayCellOfst[11]=7 cells (2 PI)
8534 11:55:39.493265 u2DelayCellOfst[12]=14 cells (4 PI)
8535 11:55:39.497100 u2DelayCellOfst[13]=14 cells (4 PI)
8536 11:55:39.500139 u2DelayCellOfst[14]=18 cells (5 PI)
8537 11:55:39.500227 u2DelayCellOfst[15]=18 cells (5 PI)
8538 11:55:39.506392 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8539 11:55:39.510041 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8540 11:55:39.513434 DramC Write-DBI on
8541 11:55:39.513523 ==
8542 11:55:39.516468 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 11:55:39.519714 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 11:55:39.519802 ==
8545 11:55:39.519867
8546 11:55:39.519928
8547 11:55:39.523294 TX Vref Scan disable
8548 11:55:39.523379 == TX Byte 0 ==
8549 11:55:39.529696 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8550 11:55:39.529789 == TX Byte 1 ==
8551 11:55:39.533122 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8552 11:55:39.536232 DramC Write-DBI off
8553 11:55:39.536318
8554 11:55:39.536382 [DATLAT]
8555 11:55:39.539335 Freq=1600, CH1 RK0
8556 11:55:39.539452
8557 11:55:39.539524 DATLAT Default: 0xf
8558 11:55:39.542545 0, 0xFFFF, sum = 0
8559 11:55:39.547019 1, 0xFFFF, sum = 0
8560 11:55:39.547105 2, 0xFFFF, sum = 0
8561 11:55:39.549323 3, 0xFFFF, sum = 0
8562 11:55:39.549408 4, 0xFFFF, sum = 0
8563 11:55:39.552774 5, 0xFFFF, sum = 0
8564 11:55:39.552859 6, 0xFFFF, sum = 0
8565 11:55:39.556614 7, 0xFFFF, sum = 0
8566 11:55:39.556706 8, 0xFFFF, sum = 0
8567 11:55:39.559093 9, 0xFFFF, sum = 0
8568 11:55:39.559179 10, 0xFFFF, sum = 0
8569 11:55:39.562714 11, 0xFFFF, sum = 0
8570 11:55:39.562801 12, 0xFFFF, sum = 0
8571 11:55:39.565513 13, 0xFFFF, sum = 0
8572 11:55:39.565597 14, 0x0, sum = 1
8573 11:55:39.569569 15, 0x0, sum = 2
8574 11:55:39.569667 16, 0x0, sum = 3
8575 11:55:39.572395 17, 0x0, sum = 4
8576 11:55:39.572479 best_step = 15
8577 11:55:39.572544
8578 11:55:39.572605 ==
8579 11:55:39.575345 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 11:55:39.582103 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 11:55:39.582206 ==
8582 11:55:39.582314 RX Vref Scan: 1
8583 11:55:39.582377
8584 11:55:39.585374 Set Vref Range= 24 -> 127
8585 11:55:39.585477
8586 11:55:39.589220 RX Vref 24 -> 127, step: 1
8587 11:55:39.589305
8588 11:55:39.589370 RX Delay 19 -> 252, step: 4
8589 11:55:39.592165
8590 11:55:39.592247 Set Vref, RX VrefLevel [Byte0]: 24
8591 11:55:39.595621 [Byte1]: 24
8592 11:55:39.599999
8593 11:55:39.600086 Set Vref, RX VrefLevel [Byte0]: 25
8594 11:55:39.602772 [Byte1]: 25
8595 11:55:39.607525
8596 11:55:39.607613 Set Vref, RX VrefLevel [Byte0]: 26
8597 11:55:39.610655 [Byte1]: 26
8598 11:55:39.615194
8599 11:55:39.615280 Set Vref, RX VrefLevel [Byte0]: 27
8600 11:55:39.618714 [Byte1]: 27
8601 11:55:39.622451
8602 11:55:39.622538 Set Vref, RX VrefLevel [Byte0]: 28
8603 11:55:39.625847 [Byte1]: 28
8604 11:55:39.629714
8605 11:55:39.629801 Set Vref, RX VrefLevel [Byte0]: 29
8606 11:55:39.633202 [Byte1]: 29
8607 11:55:39.637684
8608 11:55:39.637772 Set Vref, RX VrefLevel [Byte0]: 30
8609 11:55:39.640820 [Byte1]: 30
8610 11:55:39.645017
8611 11:55:39.645103 Set Vref, RX VrefLevel [Byte0]: 31
8612 11:55:39.648105 [Byte1]: 31
8613 11:55:39.652797
8614 11:55:39.652888 Set Vref, RX VrefLevel [Byte0]: 32
8615 11:55:39.655730 [Byte1]: 32
8616 11:55:39.660982
8617 11:55:39.661082 Set Vref, RX VrefLevel [Byte0]: 33
8618 11:55:39.663389 [Byte1]: 33
8619 11:55:39.667806
8620 11:55:39.667897 Set Vref, RX VrefLevel [Byte0]: 34
8621 11:55:39.671407 [Byte1]: 34
8622 11:55:39.675596
8623 11:55:39.675690 Set Vref, RX VrefLevel [Byte0]: 35
8624 11:55:39.678620 [Byte1]: 35
8625 11:55:39.683303
8626 11:55:39.683400 Set Vref, RX VrefLevel [Byte0]: 36
8627 11:55:39.685923 [Byte1]: 36
8628 11:55:39.690445
8629 11:55:39.690541 Set Vref, RX VrefLevel [Byte0]: 37
8630 11:55:39.693729 [Byte1]: 37
8631 11:55:39.698467
8632 11:55:39.698561 Set Vref, RX VrefLevel [Byte0]: 38
8633 11:55:39.701270 [Byte1]: 38
8634 11:55:39.705867
8635 11:55:39.705955 Set Vref, RX VrefLevel [Byte0]: 39
8636 11:55:39.708993 [Byte1]: 39
8637 11:55:39.713507
8638 11:55:39.713595 Set Vref, RX VrefLevel [Byte0]: 40
8639 11:55:39.716618 [Byte1]: 40
8640 11:55:39.720685
8641 11:55:39.720774 Set Vref, RX VrefLevel [Byte0]: 41
8642 11:55:39.723994 [Byte1]: 41
8643 11:55:39.728600
8644 11:55:39.728692 Set Vref, RX VrefLevel [Byte0]: 42
8645 11:55:39.731637 [Byte1]: 42
8646 11:55:39.736099
8647 11:55:39.736200 Set Vref, RX VrefLevel [Byte0]: 43
8648 11:55:39.739273 [Byte1]: 43
8649 11:55:39.743341
8650 11:55:39.743429 Set Vref, RX VrefLevel [Byte0]: 44
8651 11:55:39.747448 [Byte1]: 44
8652 11:55:39.751071
8653 11:55:39.751158 Set Vref, RX VrefLevel [Byte0]: 45
8654 11:55:39.754545 [Byte1]: 45
8655 11:55:39.758865
8656 11:55:39.758968 Set Vref, RX VrefLevel [Byte0]: 46
8657 11:55:39.762712 [Byte1]: 46
8658 11:55:39.766243
8659 11:55:39.766353 Set Vref, RX VrefLevel [Byte0]: 47
8660 11:55:39.769789 [Byte1]: 47
8661 11:55:39.773727
8662 11:55:39.773817 Set Vref, RX VrefLevel [Byte0]: 48
8663 11:55:39.777163 [Byte1]: 48
8664 11:55:39.781423
8665 11:55:39.781512 Set Vref, RX VrefLevel [Byte0]: 49
8666 11:55:39.784888 [Byte1]: 49
8667 11:55:39.788734
8668 11:55:39.788822 Set Vref, RX VrefLevel [Byte0]: 50
8669 11:55:39.792564 [Byte1]: 50
8670 11:55:39.796322
8671 11:55:39.796409 Set Vref, RX VrefLevel [Byte0]: 51
8672 11:55:39.800068 [Byte1]: 51
8673 11:55:39.804024
8674 11:55:39.804113 Set Vref, RX VrefLevel [Byte0]: 52
8675 11:55:39.807647 [Byte1]: 52
8676 11:55:39.811686
8677 11:55:39.811773 Set Vref, RX VrefLevel [Byte0]: 53
8678 11:55:39.814948 [Byte1]: 53
8679 11:55:39.819448
8680 11:55:39.819533 Set Vref, RX VrefLevel [Byte0]: 54
8681 11:55:39.822483 [Byte1]: 54
8682 11:55:39.826882
8683 11:55:39.826968 Set Vref, RX VrefLevel [Byte0]: 55
8684 11:55:39.830072 [Byte1]: 55
8685 11:55:39.834173
8686 11:55:39.834270 Set Vref, RX VrefLevel [Byte0]: 56
8687 11:55:39.837666 [Byte1]: 56
8688 11:55:39.842239
8689 11:55:39.842337 Set Vref, RX VrefLevel [Byte0]: 57
8690 11:55:39.845055 [Byte1]: 57
8691 11:55:39.850396
8692 11:55:39.850484 Set Vref, RX VrefLevel [Byte0]: 58
8693 11:55:39.852670 [Byte1]: 58
8694 11:55:39.857837
8695 11:55:39.857932 Set Vref, RX VrefLevel [Byte0]: 59
8696 11:55:39.860720 [Byte1]: 59
8697 11:55:39.864788
8698 11:55:39.864876 Set Vref, RX VrefLevel [Byte0]: 60
8699 11:55:39.867863 [Byte1]: 60
8700 11:55:39.872241
8701 11:55:39.872331 Set Vref, RX VrefLevel [Byte0]: 61
8702 11:55:39.875653 [Byte1]: 61
8703 11:55:39.880041
8704 11:55:39.882888 Set Vref, RX VrefLevel [Byte0]: 62
8705 11:55:39.886361 [Byte1]: 62
8706 11:55:39.886447
8707 11:55:39.889371 Set Vref, RX VrefLevel [Byte0]: 63
8708 11:55:39.893257 [Byte1]: 63
8709 11:55:39.893344
8710 11:55:39.895828 Set Vref, RX VrefLevel [Byte0]: 64
8711 11:55:39.899770 [Byte1]: 64
8712 11:55:39.899859
8713 11:55:39.903196 Set Vref, RX VrefLevel [Byte0]: 65
8714 11:55:39.905818 [Byte1]: 65
8715 11:55:39.909999
8716 11:55:39.910126 Set Vref, RX VrefLevel [Byte0]: 66
8717 11:55:39.913371 [Byte1]: 66
8718 11:55:39.918234
8719 11:55:39.918327 Set Vref, RX VrefLevel [Byte0]: 67
8720 11:55:39.920937 [Byte1]: 67
8721 11:55:39.925479
8722 11:55:39.925565 Set Vref, RX VrefLevel [Byte0]: 68
8723 11:55:39.928555 [Byte1]: 68
8724 11:55:39.933117
8725 11:55:39.933203 Set Vref, RX VrefLevel [Byte0]: 69
8726 11:55:39.936148 [Byte1]: 69
8727 11:55:39.940558
8728 11:55:39.940645 Set Vref, RX VrefLevel [Byte0]: 70
8729 11:55:39.943496 [Byte1]: 70
8730 11:55:39.948114
8731 11:55:39.948203 Final RX Vref Byte 0 = 56 to rank0
8732 11:55:39.951112 Final RX Vref Byte 1 = 61 to rank0
8733 11:55:39.955133 Final RX Vref Byte 0 = 56 to rank1
8734 11:55:39.958180 Final RX Vref Byte 1 = 61 to rank1==
8735 11:55:39.961065 Dram Type= 6, Freq= 0, CH_1, rank 0
8736 11:55:39.967830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8737 11:55:39.967935 ==
8738 11:55:39.968005 DQS Delay:
8739 11:55:39.968066 DQS0 = 0, DQS1 = 0
8740 11:55:39.971466 DQM Delay:
8741 11:55:39.971551 DQM0 = 132, DQM1 = 128
8742 11:55:39.974724 DQ Delay:
8743 11:55:39.978086 DQ0 =140, DQ1 =130, DQ2 =116, DQ3 =132
8744 11:55:39.981020 DQ4 =128, DQ5 =144, DQ6 =144, DQ7 =126
8745 11:55:39.984888 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8746 11:55:39.988354 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8747 11:55:39.988446
8748 11:55:39.988511
8749 11:55:39.988571
8750 11:55:39.990745 [DramC_TX_OE_Calibration] TA2
8751 11:55:39.994197 Original DQ_B0 (3 6) =30, OEN = 27
8752 11:55:39.997231 Original DQ_B1 (3 6) =30, OEN = 27
8753 11:55:40.001043 24, 0x0, End_B0=24 End_B1=24
8754 11:55:40.001133 25, 0x0, End_B0=25 End_B1=25
8755 11:55:40.004550 26, 0x0, End_B0=26 End_B1=26
8756 11:55:40.007091 27, 0x0, End_B0=27 End_B1=27
8757 11:55:40.010719 28, 0x0, End_B0=28 End_B1=28
8758 11:55:40.013724 29, 0x0, End_B0=29 End_B1=29
8759 11:55:40.013812 30, 0x0, End_B0=30 End_B1=30
8760 11:55:40.017192 31, 0x4141, End_B0=30 End_B1=30
8761 11:55:40.020471 Byte0 end_step=30 best_step=27
8762 11:55:40.024005 Byte1 end_step=30 best_step=27
8763 11:55:40.027246 Byte0 TX OE(2T, 0.5T) = (3, 3)
8764 11:55:40.030154 Byte1 TX OE(2T, 0.5T) = (3, 3)
8765 11:55:40.030270
8766 11:55:40.030340
8767 11:55:40.036873 [DQSOSCAuto] RK0, (LSB)MR18= 0xf18, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8768 11:55:40.040376 CH1 RK0: MR19=303, MR18=F18
8769 11:55:40.046954 CH1_RK0: MR19=0x303, MR18=0xF18, DQSOSC=397, MR23=63, INC=23, DEC=15
8770 11:55:40.047056
8771 11:55:40.050367 ----->DramcWriteLeveling(PI) begin...
8772 11:55:40.050454 ==
8773 11:55:40.053857 Dram Type= 6, Freq= 0, CH_1, rank 1
8774 11:55:40.057359 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8775 11:55:40.057457 ==
8776 11:55:40.060985 Write leveling (Byte 0): 25 => 25
8777 11:55:40.063236 Write leveling (Byte 1): 25 => 25
8778 11:55:40.066769 DramcWriteLeveling(PI) end<-----
8779 11:55:40.066857
8780 11:55:40.066921 ==
8781 11:55:40.069990 Dram Type= 6, Freq= 0, CH_1, rank 1
8782 11:55:40.073567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8783 11:55:40.073654 ==
8784 11:55:40.076802 [Gating] SW mode calibration
8785 11:55:40.082911 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8786 11:55:40.089814 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8787 11:55:40.092935 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8788 11:55:40.099511 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8789 11:55:40.102995 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8790 11:55:40.106550 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8791 11:55:40.112782 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8792 11:55:40.116206 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8793 11:55:40.119624 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8794 11:55:40.126081 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8795 11:55:40.128966 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 11:55:40.132642 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8797 11:55:40.139066 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8798 11:55:40.142446 1 5 12 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8799 11:55:40.145669 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8800 11:55:40.152383 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8801 11:55:40.155474 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8802 11:55:40.159107 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8803 11:55:40.165410 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 11:55:40.169151 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8805 11:55:40.172157 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8806 11:55:40.178634 1 6 12 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8807 11:55:40.181900 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8808 11:55:40.185089 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8809 11:55:40.192031 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8810 11:55:40.195660 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8811 11:55:40.198497 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 11:55:40.204811 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:55:40.208400 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8814 11:55:40.211509 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8815 11:55:40.218012 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8816 11:55:40.221265 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:55:40.224651 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:55:40.231308 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:55:40.234749 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8820 11:55:40.238733 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:55:40.244363 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:55:40.247778 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 11:55:40.250868 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:55:40.257406 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:55:40.260791 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:55:40.264069 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:55:40.270495 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:55:40.274187 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8829 11:55:40.277063 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8830 11:55:40.280996 Total UI for P1: 0, mck2ui 16
8831 11:55:40.283688 best dqsien dly found for B0: ( 1, 9, 4)
8832 11:55:40.290758 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8833 11:55:40.293563 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8834 11:55:40.296940 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 11:55:40.300511 Total UI for P1: 0, mck2ui 16
8836 11:55:40.303685 best dqsien dly found for B1: ( 1, 9, 12)
8837 11:55:40.307046 best DQS0 dly(MCK, UI, PI) = (1, 9, 4)
8838 11:55:40.310167 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8839 11:55:40.314166
8840 11:55:40.317168 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 4)
8841 11:55:40.319902 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8842 11:55:40.323235 [Gating] SW calibration Done
8843 11:55:40.323324 ==
8844 11:55:40.326696 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 11:55:40.329909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 11:55:40.329997 ==
8847 11:55:40.332848 RX Vref Scan: 0
8848 11:55:40.332947
8849 11:55:40.333051 RX Vref 0 -> 0, step: 1
8850 11:55:40.333118
8851 11:55:40.336154 RX Delay 0 -> 252, step: 8
8852 11:55:40.340225 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8853 11:55:40.343535 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8854 11:55:40.349805 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8855 11:55:40.352920 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8856 11:55:40.356185 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8857 11:55:40.359865 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8858 11:55:40.363197 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8859 11:55:40.369408 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8860 11:55:40.373079 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8861 11:55:40.376361 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8862 11:55:40.380011 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8863 11:55:40.386181 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8864 11:55:40.389634 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8865 11:55:40.393062 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8866 11:55:40.396255 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8867 11:55:40.399375 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8868 11:55:40.402935 ==
8869 11:55:40.403023 Dram Type= 6, Freq= 0, CH_1, rank 1
8870 11:55:40.408861 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8871 11:55:40.408957 ==
8872 11:55:40.409024 DQS Delay:
8873 11:55:40.412662 DQS0 = 0, DQS1 = 0
8874 11:55:40.412747 DQM Delay:
8875 11:55:40.415731 DQM0 = 134, DQM1 = 131
8876 11:55:40.415814 DQ Delay:
8877 11:55:40.419106 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =131
8878 11:55:40.422032 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8879 11:55:40.425447 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =127
8880 11:55:40.428980 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =143
8881 11:55:40.429069
8882 11:55:40.429135
8883 11:55:40.432221 ==
8884 11:55:40.432305 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 11:55:40.438464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 11:55:40.438559 ==
8887 11:55:40.438626
8888 11:55:40.438687
8889 11:55:40.442632 TX Vref Scan disable
8890 11:55:40.442717 == TX Byte 0 ==
8891 11:55:40.445284 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8892 11:55:40.451588 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8893 11:55:40.451687 == TX Byte 1 ==
8894 11:55:40.455428 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 11:55:40.462028 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8896 11:55:40.462141 ==
8897 11:55:40.464935 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 11:55:40.468129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 11:55:40.468218 ==
8900 11:55:40.483417
8901 11:55:40.486698 TX Vref early break, caculate TX vref
8902 11:55:40.489683 TX Vref=16, minBit 9, minWin=21, winSum=379
8903 11:55:40.493659 TX Vref=18, minBit 9, minWin=22, winSum=386
8904 11:55:40.496568 TX Vref=20, minBit 9, minWin=23, winSum=396
8905 11:55:40.499491 TX Vref=22, minBit 9, minWin=23, winSum=402
8906 11:55:40.503338 TX Vref=24, minBit 9, minWin=24, winSum=411
8907 11:55:40.509720 TX Vref=26, minBit 9, minWin=24, winSum=415
8908 11:55:40.513182 TX Vref=28, minBit 3, minWin=25, winSum=420
8909 11:55:40.516163 TX Vref=30, minBit 0, minWin=26, winSum=421
8910 11:55:40.519816 TX Vref=32, minBit 0, minWin=24, winSum=412
8911 11:55:40.523330 TX Vref=34, minBit 0, minWin=24, winSum=403
8912 11:55:40.529345 TX Vref=36, minBit 0, minWin=24, winSum=399
8913 11:55:40.532748 TX Vref=38, minBit 0, minWin=23, winSum=384
8914 11:55:40.535890 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 30
8915 11:55:40.539638
8916 11:55:40.539728 Final TX Range 0 Vref 30
8917 11:55:40.539794
8918 11:55:40.539854 ==
8919 11:55:40.542768 Dram Type= 6, Freq= 0, CH_1, rank 1
8920 11:55:40.549078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8921 11:55:40.549189 ==
8922 11:55:40.549281
8923 11:55:40.549362
8924 11:55:40.549423 TX Vref Scan disable
8925 11:55:40.556159 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8926 11:55:40.556255 == TX Byte 0 ==
8927 11:55:40.559500 u2DelayCellOfst[0]=14 cells (4 PI)
8928 11:55:40.562680 u2DelayCellOfst[1]=10 cells (3 PI)
8929 11:55:40.566741 u2DelayCellOfst[2]=0 cells (0 PI)
8930 11:55:40.569654 u2DelayCellOfst[3]=7 cells (2 PI)
8931 11:55:40.572983 u2DelayCellOfst[4]=7 cells (2 PI)
8932 11:55:40.575983 u2DelayCellOfst[5]=14 cells (4 PI)
8933 11:55:40.579601 u2DelayCellOfst[6]=14 cells (4 PI)
8934 11:55:40.582863 u2DelayCellOfst[7]=3 cells (1 PI)
8935 11:55:40.586408 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8936 11:55:40.589320 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8937 11:55:40.592447 == TX Byte 1 ==
8938 11:55:40.596135 u2DelayCellOfst[8]=0 cells (0 PI)
8939 11:55:40.599021 u2DelayCellOfst[9]=7 cells (2 PI)
8940 11:55:40.602739 u2DelayCellOfst[10]=14 cells (4 PI)
8941 11:55:40.605420 u2DelayCellOfst[11]=7 cells (2 PI)
8942 11:55:40.608803 u2DelayCellOfst[12]=18 cells (5 PI)
8943 11:55:40.612350 u2DelayCellOfst[13]=18 cells (5 PI)
8944 11:55:40.615508 u2DelayCellOfst[14]=21 cells (6 PI)
8945 11:55:40.615595 u2DelayCellOfst[15]=21 cells (6 PI)
8946 11:55:40.622516 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8947 11:55:40.625310 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8948 11:55:40.628745 DramC Write-DBI on
8949 11:55:40.628834 ==
8950 11:55:40.632196 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 11:55:40.635719 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 11:55:40.635809 ==
8953 11:55:40.635875
8954 11:55:40.635935
8955 11:55:40.638695 TX Vref Scan disable
8956 11:55:40.638778 == TX Byte 0 ==
8957 11:55:40.645873 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8958 11:55:40.645973 == TX Byte 1 ==
8959 11:55:40.651921 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8960 11:55:40.652015 DramC Write-DBI off
8961 11:55:40.652082
8962 11:55:40.652142 [DATLAT]
8963 11:55:40.655066 Freq=1600, CH1 RK1
8964 11:55:40.655152
8965 11:55:40.658398 DATLAT Default: 0xf
8966 11:55:40.658489 0, 0xFFFF, sum = 0
8967 11:55:40.661336 1, 0xFFFF, sum = 0
8968 11:55:40.661423 2, 0xFFFF, sum = 0
8969 11:55:40.665160 3, 0xFFFF, sum = 0
8970 11:55:40.665246 4, 0xFFFF, sum = 0
8971 11:55:40.668381 5, 0xFFFF, sum = 0
8972 11:55:40.668467 6, 0xFFFF, sum = 0
8973 11:55:40.671300 7, 0xFFFF, sum = 0
8974 11:55:40.671386 8, 0xFFFF, sum = 0
8975 11:55:40.674452 9, 0xFFFF, sum = 0
8976 11:55:40.674539 10, 0xFFFF, sum = 0
8977 11:55:40.678242 11, 0xFFFF, sum = 0
8978 11:55:40.678334 12, 0xFFFF, sum = 0
8979 11:55:40.681179 13, 0xFFFF, sum = 0
8980 11:55:40.681264 14, 0x0, sum = 1
8981 11:55:40.684929 15, 0x0, sum = 2
8982 11:55:40.685014 16, 0x0, sum = 3
8983 11:55:40.687987 17, 0x0, sum = 4
8984 11:55:40.688072 best_step = 15
8985 11:55:40.688137
8986 11:55:40.688197 ==
8987 11:55:40.691482 Dram Type= 6, Freq= 0, CH_1, rank 1
8988 11:55:40.698045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8989 11:55:40.698139 ==
8990 11:55:40.698205 RX Vref Scan: 0
8991 11:55:40.698293
8992 11:55:40.700823 RX Vref 0 -> 0, step: 1
8993 11:55:40.700905
8994 11:55:40.704165 RX Delay 19 -> 252, step: 4
8995 11:55:40.707251 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8996 11:55:40.710898 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8997 11:55:40.717772 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8998 11:55:40.720965 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8999 11:55:40.723690 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9000 11:55:40.727179 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9001 11:55:40.730310 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9002 11:55:40.736914 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9003 11:55:40.740517 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9004 11:55:40.743272 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9005 11:55:40.747174 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
9006 11:55:40.753455 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9007 11:55:40.756491 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9008 11:55:40.760355 iDelay=195, Bit 13, Center 134 (79 ~ 190) 112
9009 11:55:40.763067 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9010 11:55:40.766580 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9011 11:55:40.770075 ==
9012 11:55:40.773096 Dram Type= 6, Freq= 0, CH_1, rank 1
9013 11:55:40.776702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9014 11:55:40.776798 ==
9015 11:55:40.776864 DQS Delay:
9016 11:55:40.780065 DQS0 = 0, DQS1 = 0
9017 11:55:40.780151 DQM Delay:
9018 11:55:40.783335 DQM0 = 131, DQM1 = 127
9019 11:55:40.783421 DQ Delay:
9020 11:55:40.786958 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9021 11:55:40.789631 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
9022 11:55:40.792942 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
9023 11:55:40.796506 DQ12 =136, DQ13 =134, DQ14 =132, DQ15 =138
9024 11:55:40.796595
9025 11:55:40.796661
9026 11:55:40.796721
9027 11:55:40.799704 [DramC_TX_OE_Calibration] TA2
9028 11:55:40.803034 Original DQ_B0 (3 6) =30, OEN = 27
9029 11:55:40.805815 Original DQ_B1 (3 6) =30, OEN = 27
9030 11:55:40.809513 24, 0x0, End_B0=24 End_B1=24
9031 11:55:40.812404 25, 0x0, End_B0=25 End_B1=25
9032 11:55:40.816800 26, 0x0, End_B0=26 End_B1=26
9033 11:55:40.816892 27, 0x0, End_B0=27 End_B1=27
9034 11:55:40.820067 28, 0x0, End_B0=28 End_B1=28
9035 11:55:40.822371 29, 0x0, End_B0=29 End_B1=29
9036 11:55:40.826143 30, 0x0, End_B0=30 End_B1=30
9037 11:55:40.826269 31, 0x4141, End_B0=30 End_B1=30
9038 11:55:40.829035 Byte0 end_step=30 best_step=27
9039 11:55:40.832660 Byte1 end_step=30 best_step=27
9040 11:55:40.835749 Byte0 TX OE(2T, 0.5T) = (3, 3)
9041 11:55:40.838958 Byte1 TX OE(2T, 0.5T) = (3, 3)
9042 11:55:40.839047
9043 11:55:40.839112
9044 11:55:40.845941 [DQSOSCAuto] RK1, (LSB)MR18= 0x1220, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
9045 11:55:40.848727 CH1 RK1: MR19=303, MR18=1220
9046 11:55:40.855627 CH1_RK1: MR19=0x303, MR18=0x1220, DQSOSC=393, MR23=63, INC=23, DEC=15
9047 11:55:40.858709 [RxdqsGatingPostProcess] freq 1600
9048 11:55:40.865332 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9049 11:55:40.868872 best DQS0 dly(2T, 0.5T) = (1, 1)
9050 11:55:40.868971 best DQS1 dly(2T, 0.5T) = (1, 1)
9051 11:55:40.872312 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9052 11:55:40.875307 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9053 11:55:40.878623 best DQS0 dly(2T, 0.5T) = (1, 1)
9054 11:55:40.881912 best DQS1 dly(2T, 0.5T) = (1, 1)
9055 11:55:40.885307 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9056 11:55:40.888661 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9057 11:55:40.891867 Pre-setting of DQS Precalculation
9058 11:55:40.898216 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9059 11:55:40.905069 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9060 11:55:40.911410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9061 11:55:40.911518
9062 11:55:40.911582
9063 11:55:40.915486 [Calibration Summary] 3200 Mbps
9064 11:55:40.915569 CH 0, Rank 0
9065 11:55:40.918370 SW Impedance : PASS
9066 11:55:40.921961 DUTY Scan : NO K
9067 11:55:40.922046 ZQ Calibration : PASS
9068 11:55:40.925095 Jitter Meter : NO K
9069 11:55:40.927762 CBT Training : PASS
9070 11:55:40.927845 Write leveling : PASS
9071 11:55:40.931628 RX DQS gating : PASS
9072 11:55:40.934544 RX DQ/DQS(RDDQC) : PASS
9073 11:55:40.934630 TX DQ/DQS : PASS
9074 11:55:40.938133 RX DATLAT : PASS
9075 11:55:40.941091 RX DQ/DQS(Engine): PASS
9076 11:55:40.941177 TX OE : PASS
9077 11:55:40.941243 All Pass.
9078 11:55:40.944342
9079 11:55:40.944426 CH 0, Rank 1
9080 11:55:40.948302 SW Impedance : PASS
9081 11:55:40.948389 DUTY Scan : NO K
9082 11:55:40.951169 ZQ Calibration : PASS
9083 11:55:40.951253 Jitter Meter : NO K
9084 11:55:40.954702 CBT Training : PASS
9085 11:55:40.958093 Write leveling : PASS
9086 11:55:40.958181 RX DQS gating : PASS
9087 11:55:40.961737 RX DQ/DQS(RDDQC) : PASS
9088 11:55:40.964271 TX DQ/DQS : PASS
9089 11:55:40.964358 RX DATLAT : PASS
9090 11:55:40.967833 RX DQ/DQS(Engine): PASS
9091 11:55:40.971119 TX OE : PASS
9092 11:55:40.971208 All Pass.
9093 11:55:40.971274
9094 11:55:40.971337 CH 1, Rank 0
9095 11:55:40.974194 SW Impedance : PASS
9096 11:55:40.977522 DUTY Scan : NO K
9097 11:55:40.977608 ZQ Calibration : PASS
9098 11:55:40.981280 Jitter Meter : NO K
9099 11:55:40.984283 CBT Training : PASS
9100 11:55:40.984369 Write leveling : PASS
9101 11:55:40.987552 RX DQS gating : PASS
9102 11:55:40.990777 RX DQ/DQS(RDDQC) : PASS
9103 11:55:40.990865 TX DQ/DQS : PASS
9104 11:55:40.994173 RX DATLAT : PASS
9105 11:55:40.997388 RX DQ/DQS(Engine): PASS
9106 11:55:40.997478 TX OE : PASS
9107 11:55:41.000396 All Pass.
9108 11:55:41.000480
9109 11:55:41.000545 CH 1, Rank 1
9110 11:55:41.003985 SW Impedance : PASS
9111 11:55:41.004068 DUTY Scan : NO K
9112 11:55:41.007122 ZQ Calibration : PASS
9113 11:55:41.010239 Jitter Meter : NO K
9114 11:55:41.010331 CBT Training : PASS
9115 11:55:41.013526 Write leveling : PASS
9116 11:55:41.017017 RX DQS gating : PASS
9117 11:55:41.017108 RX DQ/DQS(RDDQC) : PASS
9118 11:55:41.020595 TX DQ/DQS : PASS
9119 11:55:41.023431 RX DATLAT : PASS
9120 11:55:41.023516 RX DQ/DQS(Engine): PASS
9121 11:55:41.027161 TX OE : PASS
9122 11:55:41.027245 All Pass.
9123 11:55:41.027310
9124 11:55:41.030226 DramC Write-DBI on
9125 11:55:41.030347 PER_BANK_REFRESH: Hybrid Mode
9126 11:55:41.033295 TX_TRACKING: ON
9127 11:55:41.043261 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9128 11:55:41.050079 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9129 11:55:41.057512 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9130 11:55:41.059929 [FAST_K] Save calibration result to emmc
9131 11:55:41.062971 sync common calibartion params.
9132 11:55:41.066467 sync cbt_mode0:1, 1:1
9133 11:55:41.069586 dram_init: ddr_geometry: 2
9134 11:55:41.069676 dram_init: ddr_geometry: 2
9135 11:55:41.073203 dram_init: ddr_geometry: 2
9136 11:55:41.076154 0:dram_rank_size:100000000
9137 11:55:41.079853 1:dram_rank_size:100000000
9138 11:55:41.082795 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9139 11:55:41.085861 DFS_SHUFFLE_HW_MODE: ON
9140 11:55:41.089230 dramc_set_vcore_voltage set vcore to 725000
9141 11:55:41.093220 Read voltage for 1600, 0
9142 11:55:41.093311 Vio18 = 0
9143 11:55:41.093377 Vcore = 725000
9144 11:55:41.096009 Vdram = 0
9145 11:55:41.096092 Vddq = 0
9146 11:55:41.096157 Vmddr = 0
9147 11:55:41.099007 switch to 3200 Mbps bootup
9148 11:55:41.103117 [DramcRunTimeConfig]
9149 11:55:41.103206 PHYPLL
9150 11:55:41.103273 DPM_CONTROL_AFTERK: ON
9151 11:55:41.105753 PER_BANK_REFRESH: ON
9152 11:55:41.109301 REFRESH_OVERHEAD_REDUCTION: ON
9153 11:55:41.109387 CMD_PICG_NEW_MODE: OFF
9154 11:55:41.113021 XRTWTW_NEW_MODE: ON
9155 11:55:41.115655 XRTRTR_NEW_MODE: ON
9156 11:55:41.115738 TX_TRACKING: ON
9157 11:55:41.119515 RDSEL_TRACKING: OFF
9158 11:55:41.119600 DQS Precalculation for DVFS: ON
9159 11:55:41.122752 RX_TRACKING: OFF
9160 11:55:41.122835 HW_GATING DBG: ON
9161 11:55:41.125921 ZQCS_ENABLE_LP4: ON
9162 11:55:41.126028 RX_PICG_NEW_MODE: ON
9163 11:55:41.129294 TX_PICG_NEW_MODE: ON
9164 11:55:41.132182 ENABLE_RX_DCM_DPHY: ON
9165 11:55:41.135352 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9166 11:55:41.135437 DUMMY_READ_FOR_TRACKING: OFF
9167 11:55:41.139063 !!! SPM_CONTROL_AFTERK: OFF
9168 11:55:41.141804 !!! SPM could not control APHY
9169 11:55:41.145447 IMPEDANCE_TRACKING: ON
9170 11:55:41.145534 TEMP_SENSOR: ON
9171 11:55:41.148751 HW_SAVE_FOR_SR: OFF
9172 11:55:41.152207 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9173 11:55:41.154928 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9174 11:55:41.155014 Read ODT Tracking: ON
9175 11:55:41.158507 Refresh Rate DeBounce: ON
9176 11:55:41.161905 DFS_NO_QUEUE_FLUSH: ON
9177 11:55:41.165257 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9178 11:55:41.165347 ENABLE_DFS_RUNTIME_MRW: OFF
9179 11:55:41.168376 DDR_RESERVE_NEW_MODE: ON
9180 11:55:41.171524 MR_CBT_SWITCH_FREQ: ON
9181 11:55:41.171611 =========================
9182 11:55:41.191937 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9183 11:55:41.195308 dram_init: ddr_geometry: 2
9184 11:55:41.213077 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9185 11:55:41.216417 dram_init: dram init end (result: 0)
9186 11:55:41.223074 DRAM-K: Full calibration passed in 24432 msecs
9187 11:55:41.226439 MRC: failed to locate region type 0.
9188 11:55:41.226532 DRAM rank0 size:0x100000000,
9189 11:55:41.229511 DRAM rank1 size=0x100000000
9190 11:55:41.239965 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9191 11:55:41.246341 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9192 11:55:41.252579 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9193 11:55:41.262481 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9194 11:55:41.262624 DRAM rank0 size:0x100000000,
9195 11:55:41.266472 DRAM rank1 size=0x100000000
9196 11:55:41.266561 CBMEM:
9197 11:55:41.269158 IMD: root @ 0xfffff000 254 entries.
9198 11:55:41.272656 IMD: root @ 0xffffec00 62 entries.
9199 11:55:41.278939 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9200 11:55:41.282125 WARNING: RO_VPD is uninitialized or empty.
9201 11:55:41.286010 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9202 11:55:41.293706 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9203 11:55:41.305968 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9204 11:55:41.317412 BS: romstage times (exec / console): total (unknown) / 23961 ms
9205 11:55:41.317555
9206 11:55:41.317621
9207 11:55:41.327314 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9208 11:55:41.331474 ARM64: Exception handlers installed.
9209 11:55:41.334091 ARM64: Testing exception
9210 11:55:41.337095 ARM64: Done test exception
9211 11:55:41.337185 Enumerating buses...
9212 11:55:41.340193 Show all devs... Before device enumeration.
9213 11:55:41.343858 Root Device: enabled 1
9214 11:55:41.346825 CPU_CLUSTER: 0: enabled 1
9215 11:55:41.346911 CPU: 00: enabled 1
9216 11:55:41.350318 Compare with tree...
9217 11:55:41.350403 Root Device: enabled 1
9218 11:55:41.353872 CPU_CLUSTER: 0: enabled 1
9219 11:55:41.357067 CPU: 00: enabled 1
9220 11:55:41.357154 Root Device scanning...
9221 11:55:41.360027 scan_static_bus for Root Device
9222 11:55:41.363112 CPU_CLUSTER: 0 enabled
9223 11:55:41.366416 scan_static_bus for Root Device done
9224 11:55:41.370115 scan_bus: bus Root Device finished in 8 msecs
9225 11:55:41.370229 done
9226 11:55:41.377324 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9227 11:55:41.379756 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9228 11:55:41.386453 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9229 11:55:41.392933 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9230 11:55:41.393042 Allocating resources...
9231 11:55:41.396167 Reading resources...
9232 11:55:41.399429 Root Device read_resources bus 0 link: 0
9233 11:55:41.402968 DRAM rank0 size:0x100000000,
9234 11:55:41.403057 DRAM rank1 size=0x100000000
9235 11:55:41.409813 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9236 11:55:41.412510 CPU: 00 missing read_resources
9237 11:55:41.416105 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9238 11:55:41.418932 Root Device read_resources bus 0 link: 0 done
9239 11:55:41.422452 Done reading resources.
9240 11:55:41.425788 Show resources in subtree (Root Device)...After reading.
9241 11:55:41.429181 Root Device child on link 0 CPU_CLUSTER: 0
9242 11:55:41.435460 CPU_CLUSTER: 0 child on link 0 CPU: 00
9243 11:55:41.442151 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9244 11:55:41.442339 CPU: 00
9245 11:55:41.448549 Root Device assign_resources, bus 0 link: 0
9246 11:55:41.452297 CPU_CLUSTER: 0 missing set_resources
9247 11:55:41.455269 Root Device assign_resources, bus 0 link: 0 done
9248 11:55:41.458544 Done setting resources.
9249 11:55:41.462073 Show resources in subtree (Root Device)...After assigning values.
9250 11:55:41.469221 Root Device child on link 0 CPU_CLUSTER: 0
9251 11:55:41.471665 CPU_CLUSTER: 0 child on link 0 CPU: 00
9252 11:55:41.478161 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9253 11:55:41.482152 CPU: 00
9254 11:55:41.482257 Done allocating resources.
9255 11:55:41.488066 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9256 11:55:41.491310 Enabling resources...
9257 11:55:41.491404 done.
9258 11:55:41.495054 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9259 11:55:41.498192 Initializing devices...
9260 11:55:41.498304 Root Device init
9261 11:55:41.501574 init hardware done!
9262 11:55:41.504437 0x00000018: ctrlr->caps
9263 11:55:41.504526 52.000 MHz: ctrlr->f_max
9264 11:55:41.508063 0.400 MHz: ctrlr->f_min
9265 11:55:41.511208 0x40ff8080: ctrlr->voltages
9266 11:55:41.511297 sclk: 390625
9267 11:55:41.511363 Bus Width = 1
9268 11:55:41.515396 sclk: 390625
9269 11:55:41.515480 Bus Width = 1
9270 11:55:41.518104 Early init status = 3
9271 11:55:41.521429 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9272 11:55:41.525284 in-header: 03 fc 00 00 01 00 00 00
9273 11:55:41.529265 in-data: 00
9274 11:55:41.531735 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9275 11:55:41.538060 in-header: 03 fd 00 00 00 00 00 00
9276 11:55:41.540316 in-data:
9277 11:55:41.543767 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 11:55:41.548048 in-header: 03 fc 00 00 01 00 00 00
9279 11:55:41.551440 in-data: 00
9280 11:55:41.554914 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9281 11:55:41.560313 in-header: 03 fd 00 00 00 00 00 00
9282 11:55:41.564400 in-data:
9283 11:55:41.567208 [SSUSB] Setting up USB HOST controller...
9284 11:55:41.570374 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9285 11:55:41.573576 [SSUSB] phy power-on done.
9286 11:55:41.577449 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9287 11:55:41.583892 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9288 11:55:41.587090 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9289 11:55:41.593901 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9290 11:55:41.600058 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9291 11:55:41.606693 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9292 11:55:41.613068 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9293 11:55:41.620006 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9294 11:55:41.623085 SPM: binary array size = 0x9dc
9295 11:55:41.626213 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9296 11:55:41.633032 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9297 11:55:41.639596 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9298 11:55:41.647171 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9299 11:55:41.649592 configure_display: Starting display init
9300 11:55:41.683886 anx7625_power_on_init: Init interface.
9301 11:55:41.687204 anx7625_disable_pd_protocol: Disabled PD feature.
9302 11:55:41.690707 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9303 11:55:41.718194 anx7625_start_dp_work: Secure OCM version=00
9304 11:55:41.721290 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9305 11:55:41.736632 sp_tx_get_edid_block: EDID Block = 1
9306 11:55:41.839377 Extracted contents:
9307 11:55:41.841924 header: 00 ff ff ff ff ff ff 00
9308 11:55:41.845566 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9309 11:55:41.848858 version: 01 04
9310 11:55:41.852438 basic params: 95 1f 11 78 0a
9311 11:55:41.855338 chroma info: 76 90 94 55 54 90 27 21 50 54
9312 11:55:41.858654 established: 00 00 00
9313 11:55:41.865194 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9314 11:55:41.871791 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9315 11:55:41.875013 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9316 11:55:41.881244 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9317 11:55:41.888923 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9318 11:55:41.891795 extensions: 00
9319 11:55:41.891894 checksum: fb
9320 11:55:41.891958
9321 11:55:41.897981 Manufacturer: IVO Model 57d Serial Number 0
9322 11:55:41.898082 Made week 0 of 2020
9323 11:55:41.901373 EDID version: 1.4
9324 11:55:41.901490 Digital display
9325 11:55:41.904770 6 bits per primary color channel
9326 11:55:41.908050 DisplayPort interface
9327 11:55:41.908138 Maximum image size: 31 cm x 17 cm
9328 11:55:41.912264 Gamma: 220%
9329 11:55:41.912352 Check DPMS levels
9330 11:55:41.917868 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9331 11:55:41.921005 First detailed timing is preferred timing
9332 11:55:41.924657 Established timings supported:
9333 11:55:41.924748 Standard timings supported:
9334 11:55:41.927419 Detailed timings
9335 11:55:41.931544 Hex of detail: 383680a07038204018303c0035ae10000019
9336 11:55:41.937615 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9337 11:55:41.940764 0780 0798 07c8 0820 hborder 0
9338 11:55:41.944418 0438 043b 0447 0458 vborder 0
9339 11:55:41.947253 -hsync -vsync
9340 11:55:41.947337 Did detailed timing
9341 11:55:41.954544 Hex of detail: 000000000000000000000000000000000000
9342 11:55:41.957446 Manufacturer-specified data, tag 0
9343 11:55:41.960322 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9344 11:55:41.963746 ASCII string: InfoVision
9345 11:55:41.966960 Hex of detail: 000000fe00523134304e574635205248200a
9346 11:55:41.970372 ASCII string: R140NWF5 RH
9347 11:55:41.970462 Checksum
9348 11:55:41.974070 Checksum: 0xfb (valid)
9349 11:55:41.977304 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9350 11:55:41.980672 DSI data_rate: 832800000 bps
9351 11:55:41.986858 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9352 11:55:41.990622 anx7625_parse_edid: pixelclock(138800).
9353 11:55:41.993469 hactive(1920), hsync(48), hfp(24), hbp(88)
9354 11:55:41.997363 vactive(1080), vsync(12), vfp(3), vbp(17)
9355 11:55:42.000350 anx7625_dsi_config: config dsi.
9356 11:55:42.006631 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9357 11:55:42.020733 anx7625_dsi_config: success to config DSI
9358 11:55:42.023852 anx7625_dp_start: MIPI phy setup OK.
9359 11:55:42.027452 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9360 11:55:42.030394 mtk_ddp_mode_set invalid vrefresh 60
9361 11:55:42.033840 main_disp_path_setup
9362 11:55:42.033954 ovl_layer_smi_id_en
9363 11:55:42.037152 ovl_layer_smi_id_en
9364 11:55:42.037235 ccorr_config
9365 11:55:42.037300 aal_config
9366 11:55:42.040658 gamma_config
9367 11:55:42.040742 postmask_config
9368 11:55:42.043799 dither_config
9369 11:55:42.046918 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9370 11:55:42.053461 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9371 11:55:42.057002 Root Device init finished in 554 msecs
9372 11:55:42.060166 CPU_CLUSTER: 0 init
9373 11:55:42.066892 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9374 11:55:42.073496 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9375 11:55:42.073607 APU_MBOX 0x190000b0 = 0x10001
9376 11:55:42.076661 APU_MBOX 0x190001b0 = 0x10001
9377 11:55:42.080041 APU_MBOX 0x190005b0 = 0x10001
9378 11:55:42.083762 APU_MBOX 0x190006b0 = 0x10001
9379 11:55:42.089905 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9380 11:55:42.099840 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9381 11:55:42.112056 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9382 11:55:42.118744 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9383 11:55:42.130485 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9384 11:55:42.140129 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9385 11:55:42.143032 CPU_CLUSTER: 0 init finished in 81 msecs
9386 11:55:42.146125 Devices initialized
9387 11:55:42.149578 Show all devs... After init.
9388 11:55:42.149668 Root Device: enabled 1
9389 11:55:42.152742 CPU_CLUSTER: 0: enabled 1
9390 11:55:42.155953 CPU: 00: enabled 1
9391 11:55:42.159825 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9392 11:55:42.163233 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9393 11:55:42.166726 ELOG: NV offset 0x57f000 size 0x1000
9394 11:55:42.172809 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9395 11:55:42.179714 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9396 11:55:42.182868 ELOG: Event(17) added with size 13 at 2023-11-23 11:55:42 UTC
9397 11:55:42.189475 out: cmd=0x121: 03 db 21 01 00 00 00 00
9398 11:55:42.192721 in-header: 03 2a 00 00 2c 00 00 00
9399 11:55:42.202162 in-data: 35 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9400 11:55:42.208896 ELOG: Event(A1) added with size 10 at 2023-11-23 11:55:42 UTC
9401 11:55:42.215424 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9402 11:55:42.222467 ELOG: Event(A0) added with size 9 at 2023-11-23 11:55:42 UTC
9403 11:55:42.225691 elog_add_boot_reason: Logged dev mode boot
9404 11:55:42.231970 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9405 11:55:42.232081 Finalize devices...
9406 11:55:42.235400 Devices finalized
9407 11:55:42.238725 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9408 11:55:42.242009 Writing coreboot table at 0xffe64000
9409 11:55:42.245285 0. 000000000010a000-0000000000113fff: RAMSTAGE
9410 11:55:42.251728 1. 0000000040000000-00000000400fffff: RAM
9411 11:55:42.255331 2. 0000000040100000-000000004032afff: RAMSTAGE
9412 11:55:42.258604 3. 000000004032b000-00000000545fffff: RAM
9413 11:55:42.261777 4. 0000000054600000-000000005465ffff: BL31
9414 11:55:42.265282 5. 0000000054660000-00000000ffe63fff: RAM
9415 11:55:42.271865 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9416 11:55:42.275242 7. 0000000100000000-000000023fffffff: RAM
9417 11:55:42.278439 Passing 5 GPIOs to payload:
9418 11:55:42.281590 NAME | PORT | POLARITY | VALUE
9419 11:55:42.288366 EC in RW | 0x000000aa | low | undefined
9420 11:55:42.291240 EC interrupt | 0x00000005 | low | undefined
9421 11:55:42.294695 TPM interrupt | 0x000000ab | high | undefined
9422 11:55:42.301675 SD card detect | 0x00000011 | high | undefined
9423 11:55:42.304943 speaker enable | 0x00000093 | high | undefined
9424 11:55:42.308092 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9425 11:55:42.312079 in-header: 03 f9 00 00 02 00 00 00
9426 11:55:42.315105 in-data: 02 00
9427 11:55:42.318534 ADC[4]: Raw value=902586 ID=7
9428 11:55:42.321947 ADC[3]: Raw value=213916 ID=1
9429 11:55:42.322029 RAM Code: 0x71
9430 11:55:42.324955 ADC[6]: Raw value=74630 ID=0
9431 11:55:42.328999 ADC[5]: Raw value=213546 ID=1
9432 11:55:42.329081 SKU Code: 0x1
9433 11:55:42.335245 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8d32
9434 11:55:42.335354 coreboot table: 964 bytes.
9435 11:55:42.338145 IMD ROOT 0. 0xfffff000 0x00001000
9436 11:55:42.341306 IMD SMALL 1. 0xffffe000 0x00001000
9437 11:55:42.344751 RO MCACHE 2. 0xffffc000 0x00001104
9438 11:55:42.348094 CONSOLE 3. 0xfff7c000 0x00080000
9439 11:55:42.351658 FMAP 4. 0xfff7b000 0x00000452
9440 11:55:42.354797 TIME STAMP 5. 0xfff7a000 0x00000910
9441 11:55:42.358791 VBOOT WORK 6. 0xfff66000 0x00014000
9442 11:55:42.361216 RAMOOPS 7. 0xffe66000 0x00100000
9443 11:55:42.365049 COREBOOT 8. 0xffe64000 0x00002000
9444 11:55:42.368020 IMD small region:
9445 11:55:42.371322 IMD ROOT 0. 0xffffec00 0x00000400
9446 11:55:42.374274 VPD 1. 0xffffeb80 0x0000006c
9447 11:55:42.378370 MMC STATUS 2. 0xffffeb60 0x00000004
9448 11:55:42.384900 BS: BS_WRITE_TABLES run times (exec / console): 2 / 137 ms
9449 11:55:42.384987 Probing TPM: done!
9450 11:55:42.391398 Connected to device vid:did:rid of 1ae0:0028:00
9451 11:55:42.398448 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9452 11:55:42.401436 Initialized TPM device CR50 revision 0
9453 11:55:42.404455 Checking cr50 for pending updates
9454 11:55:42.409863 Reading cr50 TPM mode
9455 11:55:42.419061 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9456 11:55:42.425208 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9457 11:55:42.465745 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9458 11:55:42.468824 Checking segment from ROM address 0x40100000
9459 11:55:42.472233 Checking segment from ROM address 0x4010001c
9460 11:55:42.478830 Loading segment from ROM address 0x40100000
9461 11:55:42.478913 code (compression=0)
9462 11:55:42.488711 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9463 11:55:42.495567 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9464 11:55:42.495654 it's not compressed!
9465 11:55:42.502241 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9466 11:55:42.509292 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9467 11:55:42.526023 Loading segment from ROM address 0x4010001c
9468 11:55:42.526118 Entry Point 0x80000000
9469 11:55:42.529167 Loaded segments
9470 11:55:42.532394 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9471 11:55:42.539218 Jumping to boot code at 0x80000000(0xffe64000)
9472 11:55:42.545699 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9473 11:55:42.552476 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9474 11:55:42.560360 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9475 11:55:42.563742 Checking segment from ROM address 0x40100000
9476 11:55:42.567029 Checking segment from ROM address 0x4010001c
9477 11:55:42.573599 Loading segment from ROM address 0x40100000
9478 11:55:42.573728 code (compression=1)
9479 11:55:42.580947 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9480 11:55:42.589863 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9481 11:55:42.589945 using LZMA
9482 11:55:42.598710 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9483 11:55:42.605670 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9484 11:55:42.608873 Loading segment from ROM address 0x4010001c
9485 11:55:42.608952 Entry Point 0x54601000
9486 11:55:42.611956 Loaded segments
9487 11:55:42.615573 NOTICE: MT8192 bl31_setup
9488 11:55:42.622736 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9489 11:55:42.625454 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9490 11:55:42.628946 WARNING: region 0:
9491 11:55:42.632258 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9492 11:55:42.632337 WARNING: region 1:
9493 11:55:42.638555 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9494 11:55:42.641994 WARNING: region 2:
9495 11:55:42.645661 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9496 11:55:42.648546 WARNING: region 3:
9497 11:55:42.652091 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9498 11:55:42.655513 WARNING: region 4:
9499 11:55:42.662218 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9500 11:55:42.662364 WARNING: region 5:
9501 11:55:42.665622 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9502 11:55:42.668954 WARNING: region 6:
9503 11:55:42.672223 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9504 11:55:42.675589 WARNING: region 7:
9505 11:55:42.678495 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9506 11:55:42.685116 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9507 11:55:42.688396 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9508 11:55:42.691986 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9509 11:55:42.698259 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9510 11:55:42.701716 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9511 11:55:42.708452 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9512 11:55:42.711733 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9513 11:55:42.714924 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9514 11:55:42.721630 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9515 11:55:42.724863 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9516 11:55:42.731712 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9517 11:55:42.735244 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9518 11:55:42.738389 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9519 11:55:42.744540 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9520 11:55:42.748010 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9521 11:55:42.751434 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9522 11:55:42.758532 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9523 11:55:42.761242 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9524 11:55:42.767703 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9525 11:55:42.771702 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9526 11:55:42.774336 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9527 11:55:42.781606 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9528 11:55:42.784282 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9529 11:55:42.787644 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9530 11:55:42.795312 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9531 11:55:42.797580 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9532 11:55:42.804539 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9533 11:55:42.807880 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9534 11:55:42.814054 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9535 11:55:42.817816 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9536 11:55:42.820922 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9537 11:55:42.827512 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9538 11:55:42.831091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9539 11:55:42.834795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9540 11:55:42.837642 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9541 11:55:42.844848 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9542 11:55:42.847676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9543 11:55:42.850900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9544 11:55:42.854525 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9545 11:55:42.860703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9546 11:55:42.864049 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9547 11:55:42.867680 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9548 11:55:42.870571 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9549 11:55:42.877043 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9550 11:55:42.880615 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9551 11:55:42.884185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9552 11:55:42.890460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9553 11:55:42.893732 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9554 11:55:42.897163 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9555 11:55:42.903539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9556 11:55:42.906977 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9557 11:55:42.913963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9558 11:55:42.917506 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9559 11:55:42.920519 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9560 11:55:42.927195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9561 11:55:42.930079 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9562 11:55:42.936998 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9563 11:55:42.940430 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9564 11:55:42.947190 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9565 11:55:42.950108 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9566 11:55:42.953735 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9567 11:55:42.960247 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9568 11:55:42.963474 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9569 11:55:42.970192 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9570 11:55:42.973752 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9571 11:55:42.980075 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9572 11:55:42.983767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9573 11:55:42.990290 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9574 11:55:42.993377 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9575 11:55:42.996797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9576 11:55:43.003241 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9577 11:55:43.006937 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9578 11:55:43.013143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9579 11:55:43.016777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9580 11:55:43.023696 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9581 11:55:43.027084 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9582 11:55:43.030039 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9583 11:55:43.036921 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9584 11:55:43.040388 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9585 11:55:43.046796 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9586 11:55:43.050069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9587 11:55:43.056548 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9588 11:55:43.060325 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9589 11:55:43.066509 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9590 11:55:43.069932 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9591 11:55:43.073410 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9592 11:55:43.079924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9593 11:55:43.083562 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9594 11:55:43.089798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9595 11:55:43.093215 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9596 11:55:43.099755 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9597 11:55:43.102861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9598 11:55:43.106400 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9599 11:55:43.112633 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9600 11:55:43.116066 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9601 11:55:43.123074 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9602 11:55:43.125967 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9603 11:55:43.129175 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9604 11:55:43.136406 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9605 11:55:43.139046 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9606 11:55:43.142532 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9607 11:55:43.149008 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9608 11:55:43.152397 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9609 11:55:43.155633 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9610 11:55:43.162519 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9611 11:55:43.165920 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9612 11:55:43.172731 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9613 11:55:43.177008 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9614 11:55:43.179759 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9615 11:55:43.185863 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9616 11:55:43.188791 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9617 11:55:43.196104 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9618 11:55:43.198887 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9619 11:55:43.205502 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9620 11:55:43.208612 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9621 11:55:43.211901 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9622 11:55:43.215274 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9623 11:55:43.221861 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9624 11:55:43.225665 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9625 11:55:43.228836 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9626 11:55:43.235154 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9627 11:55:43.238859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9628 11:55:43.241710 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9629 11:55:43.244847 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9630 11:55:43.251897 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9631 11:55:43.255096 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9632 11:55:43.262598 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9633 11:55:43.265286 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9634 11:55:43.268710 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9635 11:55:43.275298 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9636 11:55:43.278236 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9637 11:55:43.285237 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9638 11:55:43.288318 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9639 11:55:43.291403 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9640 11:55:43.298002 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9641 11:55:43.301614 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9642 11:55:43.308261 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9643 11:55:43.311611 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9644 11:55:43.314586 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9645 11:55:43.321648 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9646 11:55:43.324956 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9647 11:55:43.328292 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9648 11:55:43.334667 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9649 11:55:43.338107 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9650 11:55:43.344945 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9651 11:55:43.347996 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9652 11:55:43.351274 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9653 11:55:43.357909 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9654 11:55:43.361384 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9655 11:55:43.368181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9656 11:55:43.371728 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9657 11:55:43.374370 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9658 11:55:43.381748 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9659 11:55:43.384722 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9660 11:55:43.391538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9661 11:55:43.394819 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9662 11:55:43.397664 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9663 11:55:43.404590 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9664 11:55:43.407919 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9665 11:55:43.414473 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9666 11:55:43.417608 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9667 11:55:43.421228 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9668 11:55:43.427570 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9669 11:55:43.430956 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9670 11:55:43.437516 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9671 11:55:43.440573 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9672 11:55:43.443867 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9673 11:55:43.451272 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9674 11:55:43.454285 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9675 11:55:43.460610 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9676 11:55:43.464055 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9677 11:55:43.466897 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9678 11:55:43.473474 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9679 11:55:43.476787 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9680 11:55:43.483540 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9681 11:55:43.486740 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9682 11:55:43.490221 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9683 11:55:43.496512 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9684 11:55:43.500411 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9685 11:55:43.506219 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9686 11:55:43.509989 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9687 11:55:43.513388 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9688 11:55:43.519892 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9689 11:55:43.522922 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9690 11:55:43.529342 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9691 11:55:43.533142 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9692 11:55:43.536035 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9693 11:55:43.542908 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9694 11:55:43.545898 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9695 11:55:43.552461 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9696 11:55:43.556119 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9697 11:55:43.562406 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9698 11:55:43.566311 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9699 11:55:43.569209 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9700 11:55:43.575831 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9701 11:55:43.578884 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9702 11:55:43.585642 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9703 11:55:43.588658 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9704 11:55:43.595791 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9705 11:55:43.598883 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9706 11:55:43.601920 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9707 11:55:43.609138 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9708 11:55:43.612086 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9709 11:55:43.619068 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9710 11:55:43.622171 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9711 11:55:43.628947 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9712 11:55:43.631954 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9713 11:55:43.634979 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9714 11:55:43.641975 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9715 11:55:43.645400 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9716 11:55:43.651577 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9717 11:55:43.655194 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9718 11:55:43.658238 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9719 11:55:43.664563 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9720 11:55:43.668478 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9721 11:55:43.674902 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9722 11:55:43.677736 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9723 11:55:43.684537 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9724 11:55:43.687525 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9725 11:55:43.690860 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9726 11:55:43.697697 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9727 11:55:43.700832 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9728 11:55:43.708144 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9729 11:55:43.710965 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9730 11:55:43.717453 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9731 11:55:43.720479 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9732 11:55:43.724271 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9733 11:55:43.730390 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9734 11:55:43.733858 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9735 11:55:43.740612 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9736 11:55:43.744221 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9737 11:55:43.746841 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9738 11:55:43.750151 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9739 11:55:43.753886 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9740 11:55:43.760194 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9741 11:55:43.763669 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9742 11:55:43.770574 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9743 11:55:43.773676 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9744 11:55:43.776490 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9745 11:55:43.783414 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9746 11:55:43.787026 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9747 11:55:43.789928 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9748 11:55:43.796536 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9749 11:55:43.799836 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9750 11:55:43.806750 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9751 11:55:43.809757 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9752 11:55:43.813525 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9753 11:55:43.819382 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9754 11:55:43.822995 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9755 11:55:43.826406 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9756 11:55:43.832708 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9757 11:55:43.836788 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9758 11:55:43.842628 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9759 11:55:43.845895 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9760 11:55:43.850036 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9761 11:55:43.856323 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9762 11:55:43.859110 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9763 11:55:43.865725 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9764 11:55:43.869146 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9765 11:55:43.872291 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9766 11:55:43.878958 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9767 11:55:43.882671 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9768 11:55:43.885869 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9769 11:55:43.892315 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9770 11:55:43.896188 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9771 11:55:43.898803 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9772 11:55:43.905582 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9773 11:55:43.908433 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9774 11:55:43.915609 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9775 11:55:43.918926 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9776 11:55:43.922527 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9777 11:55:43.925286 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9778 11:55:43.928862 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9779 11:55:43.934964 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9780 11:55:43.938423 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9781 11:55:43.942049 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9782 11:55:43.944773 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9783 11:55:43.951547 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9784 11:55:43.954640 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9785 11:55:43.958471 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9786 11:55:43.965165 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9787 11:55:43.967790 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9788 11:55:43.971306 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9789 11:55:43.977698 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9790 11:55:43.981345 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9791 11:55:43.987721 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9792 11:55:43.991349 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9793 11:55:43.994513 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9794 11:55:44.000978 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9795 11:55:44.004319 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9796 11:55:44.011538 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9797 11:55:44.013991 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9798 11:55:44.017374 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9799 11:55:44.024645 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9800 11:55:44.027676 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9801 11:55:44.034135 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9802 11:55:44.037205 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9803 11:55:44.043722 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9804 11:55:44.046837 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9805 11:55:44.050280 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9806 11:55:44.057136 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9807 11:55:44.060269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9808 11:55:44.067107 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9809 11:55:44.069947 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9810 11:55:44.077242 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9811 11:55:44.080285 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9812 11:55:44.083197 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9813 11:55:44.090159 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9814 11:55:44.093339 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9815 11:55:44.099852 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9816 11:55:44.103302 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9817 11:55:44.110134 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9818 11:55:44.112853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9819 11:55:44.116348 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9820 11:55:44.123250 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9821 11:55:44.126472 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9822 11:55:44.133712 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9823 11:55:44.136135 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9824 11:55:44.139269 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9825 11:55:44.146341 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9826 11:55:44.149690 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9827 11:55:44.156096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9828 11:55:44.159691 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9829 11:55:44.162562 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9830 11:55:44.169916 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9831 11:55:44.172488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9832 11:55:44.179080 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9833 11:55:44.182058 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9834 11:55:44.188972 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9835 11:55:44.192398 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9836 11:55:44.195908 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9837 11:55:44.202245 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9838 11:55:44.205485 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9839 11:55:44.212415 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9840 11:55:44.215192 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9841 11:55:44.221728 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9842 11:55:44.225035 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9843 11:55:44.228376 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9844 11:55:44.235216 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9845 11:55:44.238181 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9846 11:55:44.245226 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9847 11:55:44.248214 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9848 11:55:44.254588 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9849 11:55:44.257683 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9850 11:55:44.261498 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9851 11:55:44.267785 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9852 11:55:44.270987 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9853 11:55:44.277919 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9854 11:55:44.280813 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9855 11:55:44.284104 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9856 11:55:44.290953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9857 11:55:44.294262 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9858 11:55:44.300998 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9859 11:55:44.304347 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9860 11:55:44.307608 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9861 11:55:44.314201 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9862 11:55:44.317427 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9863 11:55:44.323792 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9864 11:55:44.326963 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9865 11:55:44.334010 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9866 11:55:44.336928 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9867 11:55:44.344160 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9868 11:55:44.347386 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9869 11:55:44.350290 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9870 11:55:44.357260 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9871 11:55:44.359998 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9872 11:55:44.366943 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9873 11:55:44.370437 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9874 11:55:44.376355 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9875 11:55:44.379994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9876 11:55:44.386628 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9877 11:55:44.389664 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9878 11:55:44.396765 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9879 11:55:44.399649 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9880 11:55:44.402897 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9881 11:55:44.409379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9882 11:55:44.412835 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9883 11:55:44.419049 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9884 11:55:44.422739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9885 11:55:44.429292 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9886 11:55:44.432642 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9887 11:55:44.439075 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9888 11:55:44.442476 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9889 11:55:44.445582 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9890 11:55:44.452316 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9891 11:55:44.455522 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9892 11:55:44.462136 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9893 11:55:44.465223 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9894 11:55:44.471703 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9895 11:55:44.475551 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9896 11:55:44.482089 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9897 11:55:44.485607 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9898 11:55:44.491851 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9899 11:55:44.495280 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9900 11:55:44.498379 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9901 11:55:44.505139 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9902 11:55:44.508147 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9903 11:55:44.515070 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9904 11:55:44.517742 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9905 11:55:44.524538 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9906 11:55:44.527981 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9907 11:55:44.531334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9908 11:55:44.538113 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9909 11:55:44.541158 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9910 11:55:44.547679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9911 11:55:44.550966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9912 11:55:44.557923 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9913 11:55:44.560623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9914 11:55:44.567475 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9915 11:55:44.570544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9916 11:55:44.577120 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9917 11:55:44.580617 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9918 11:55:44.587381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9919 11:55:44.590568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9920 11:55:44.597092 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9921 11:55:44.600325 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9922 11:55:44.607148 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9923 11:55:44.610154 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9924 11:55:44.616934 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9925 11:55:44.620139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9926 11:55:44.626288 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9927 11:55:44.630134 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9928 11:55:44.636840 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9929 11:55:44.640309 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9930 11:55:44.647056 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9931 11:55:44.649742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9932 11:55:44.656577 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9933 11:55:44.659517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9934 11:55:44.666155 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9935 11:55:44.669986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9936 11:55:44.676108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9937 11:55:44.679843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9938 11:55:44.685828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9939 11:55:44.689048 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9940 11:55:44.692260 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9941 11:55:44.695946 INFO: [APUAPC] vio 0
9942 11:55:44.702828 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9943 11:55:44.705779 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9944 11:55:44.709027 INFO: [APUAPC] D0_APC_0: 0x400510
9945 11:55:44.712488 INFO: [APUAPC] D0_APC_1: 0x0
9946 11:55:44.715876 INFO: [APUAPC] D0_APC_2: 0x1540
9947 11:55:44.718703 INFO: [APUAPC] D0_APC_3: 0x0
9948 11:55:44.723019 INFO: [APUAPC] D1_APC_0: 0xffffffff
9949 11:55:44.725448 INFO: [APUAPC] D1_APC_1: 0xffffffff
9950 11:55:44.729185 INFO: [APUAPC] D1_APC_2: 0x3fffff
9951 11:55:44.731889 INFO: [APUAPC] D1_APC_3: 0x0
9952 11:55:44.735095 INFO: [APUAPC] D2_APC_0: 0xffffffff
9953 11:55:44.738523 INFO: [APUAPC] D2_APC_1: 0xffffffff
9954 11:55:44.741577 INFO: [APUAPC] D2_APC_2: 0x3fffff
9955 11:55:44.744953 INFO: [APUAPC] D2_APC_3: 0x0
9956 11:55:44.748735 INFO: [APUAPC] D3_APC_0: 0xffffffff
9957 11:55:44.751954 INFO: [APUAPC] D3_APC_1: 0xffffffff
9958 11:55:44.754944 INFO: [APUAPC] D3_APC_2: 0x3fffff
9959 11:55:44.758319 INFO: [APUAPC] D3_APC_3: 0x0
9960 11:55:44.761430 INFO: [APUAPC] D4_APC_0: 0xffffffff
9961 11:55:44.764630 INFO: [APUAPC] D4_APC_1: 0xffffffff
9962 11:55:44.768141 INFO: [APUAPC] D4_APC_2: 0x3fffff
9963 11:55:44.771433 INFO: [APUAPC] D4_APC_3: 0x0
9964 11:55:44.774857 INFO: [APUAPC] D5_APC_0: 0xffffffff
9965 11:55:44.777684 INFO: [APUAPC] D5_APC_1: 0xffffffff
9966 11:55:44.781235 INFO: [APUAPC] D5_APC_2: 0x3fffff
9967 11:55:44.784912 INFO: [APUAPC] D5_APC_3: 0x0
9968 11:55:44.787721 INFO: [APUAPC] D6_APC_0: 0xffffffff
9969 11:55:44.791367 INFO: [APUAPC] D6_APC_1: 0xffffffff
9970 11:55:44.794574 INFO: [APUAPC] D6_APC_2: 0x3fffff
9971 11:55:44.794660 INFO: [APUAPC] D6_APC_3: 0x0
9972 11:55:44.801192 INFO: [APUAPC] D7_APC_0: 0xffffffff
9973 11:55:44.805005 INFO: [APUAPC] D7_APC_1: 0xffffffff
9974 11:55:44.807765 INFO: [APUAPC] D7_APC_2: 0x3fffff
9975 11:55:44.807853 INFO: [APUAPC] D7_APC_3: 0x0
9976 11:55:44.811159 INFO: [APUAPC] D8_APC_0: 0xffffffff
9977 11:55:44.817277 INFO: [APUAPC] D8_APC_1: 0xffffffff
9978 11:55:44.820838 INFO: [APUAPC] D8_APC_2: 0x3fffff
9979 11:55:44.820927 INFO: [APUAPC] D8_APC_3: 0x0
9980 11:55:44.824050 INFO: [APUAPC] D9_APC_0: 0xffffffff
9981 11:55:44.827843 INFO: [APUAPC] D9_APC_1: 0xffffffff
9982 11:55:44.830663 INFO: [APUAPC] D9_APC_2: 0x3fffff
9983 11:55:44.834091 INFO: [APUAPC] D9_APC_3: 0x0
9984 11:55:44.837423 INFO: [APUAPC] D10_APC_0: 0xffffffff
9985 11:55:44.840676 INFO: [APUAPC] D10_APC_1: 0xffffffff
9986 11:55:44.843866 INFO: [APUAPC] D10_APC_2: 0x3fffff
9987 11:55:44.847100 INFO: [APUAPC] D10_APC_3: 0x0
9988 11:55:44.850720 INFO: [APUAPC] D11_APC_0: 0xffffffff
9989 11:55:44.854379 INFO: [APUAPC] D11_APC_1: 0xffffffff
9990 11:55:44.860299 INFO: [APUAPC] D11_APC_2: 0x3fffff
9991 11:55:44.860385 INFO: [APUAPC] D11_APC_3: 0x0
9992 11:55:44.864161 INFO: [APUAPC] D12_APC_0: 0xffffffff
9993 11:55:44.870481 INFO: [APUAPC] D12_APC_1: 0xffffffff
9994 11:55:44.873338 INFO: [APUAPC] D12_APC_2: 0x3fffff
9995 11:55:44.873423 INFO: [APUAPC] D12_APC_3: 0x0
9996 11:55:44.880146 INFO: [APUAPC] D13_APC_0: 0xffffffff
9997 11:55:44.883584 INFO: [APUAPC] D13_APC_1: 0xffffffff
9998 11:55:44.887074 INFO: [APUAPC] D13_APC_2: 0x3fffff
9999 11:55:44.890463 INFO: [APUAPC] D13_APC_3: 0x0
10000 11:55:44.893872 INFO: [APUAPC] D14_APC_0: 0xffffffff
10001 11:55:44.897164 INFO: [APUAPC] D14_APC_1: 0xffffffff
10002 11:55:44.900090 INFO: [APUAPC] D14_APC_2: 0x3fffff
10003 11:55:44.903480 INFO: [APUAPC] D14_APC_3: 0x0
10004 11:55:44.906540 INFO: [APUAPC] D15_APC_0: 0xffffffff
10005 11:55:44.909946 INFO: [APUAPC] D15_APC_1: 0xffffffff
10006 11:55:44.913175 INFO: [APUAPC] D15_APC_2: 0x3fffff
10007 11:55:44.916505 INFO: [APUAPC] D15_APC_3: 0x0
10008 11:55:44.916587 INFO: [APUAPC] APC_CON: 0x4
10009 11:55:44.920149 INFO: [NOCDAPC] D0_APC_0: 0x0
10010 11:55:44.923330 INFO: [NOCDAPC] D0_APC_1: 0x0
10011 11:55:44.926710 INFO: [NOCDAPC] D1_APC_0: 0x0
10012 11:55:44.930096 INFO: [NOCDAPC] D1_APC_1: 0xfff
10013 11:55:44.933209 INFO: [NOCDAPC] D2_APC_0: 0x0
10014 11:55:44.937137 INFO: [NOCDAPC] D2_APC_1: 0xfff
10015 11:55:44.939622 INFO: [NOCDAPC] D3_APC_0: 0x0
10016 11:55:44.943181 INFO: [NOCDAPC] D3_APC_1: 0xfff
10017 11:55:44.946716 INFO: [NOCDAPC] D4_APC_0: 0x0
10018 11:55:44.946799 INFO: [NOCDAPC] D4_APC_1: 0xfff
10019 11:55:44.949860 INFO: [NOCDAPC] D5_APC_0: 0x0
10020 11:55:44.952796 INFO: [NOCDAPC] D5_APC_1: 0xfff
10021 11:55:44.956313 INFO: [NOCDAPC] D6_APC_0: 0x0
10022 11:55:44.959888 INFO: [NOCDAPC] D6_APC_1: 0xfff
10023 11:55:44.962889 INFO: [NOCDAPC] D7_APC_0: 0x0
10024 11:55:44.966045 INFO: [NOCDAPC] D7_APC_1: 0xfff
10025 11:55:44.969671 INFO: [NOCDAPC] D8_APC_0: 0x0
10026 11:55:44.972505 INFO: [NOCDAPC] D8_APC_1: 0xfff
10027 11:55:44.975740 INFO: [NOCDAPC] D9_APC_0: 0x0
10028 11:55:44.979360 INFO: [NOCDAPC] D9_APC_1: 0xfff
10029 11:55:44.982468 INFO: [NOCDAPC] D10_APC_0: 0x0
10030 11:55:44.985810 INFO: [NOCDAPC] D10_APC_1: 0xfff
10031 11:55:44.985892 INFO: [NOCDAPC] D11_APC_0: 0x0
10032 11:55:44.989337 INFO: [NOCDAPC] D11_APC_1: 0xfff
10033 11:55:44.992627 INFO: [NOCDAPC] D12_APC_0: 0x0
10034 11:55:44.996271 INFO: [NOCDAPC] D12_APC_1: 0xfff
10035 11:55:44.998972 INFO: [NOCDAPC] D13_APC_0: 0x0
10036 11:55:45.002589 INFO: [NOCDAPC] D13_APC_1: 0xfff
10037 11:55:45.005750 INFO: [NOCDAPC] D14_APC_0: 0x0
10038 11:55:45.008714 INFO: [NOCDAPC] D14_APC_1: 0xfff
10039 11:55:45.012647 INFO: [NOCDAPC] D15_APC_0: 0x0
10040 11:55:45.015358 INFO: [NOCDAPC] D15_APC_1: 0xfff
10041 11:55:45.018710 INFO: [NOCDAPC] APC_CON: 0x4
10042 11:55:45.021856 INFO: [APUAPC] set_apusys_apc done
10043 11:55:45.025565 INFO: [DEVAPC] devapc_init done
10044 11:55:45.028721 INFO: GICv3 without legacy support detected.
10045 11:55:45.032254 INFO: ARM GICv3 driver initialized in EL3
10046 11:55:45.035476 INFO: Maximum SPI INTID supported: 639
10047 11:55:45.041926 INFO: BL31: Initializing runtime services
10048 11:55:45.044896 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10049 11:55:45.048359 INFO: SPM: enable CPC mode
10050 11:55:45.055188 INFO: mcdi ready for mcusys-off-idle and system suspend
10051 11:55:45.059384 INFO: BL31: Preparing for EL3 exit to normal world
10052 11:55:45.061525 INFO: Entry point address = 0x80000000
10053 11:55:45.064713 INFO: SPSR = 0x8
10054 11:55:45.070375
10055 11:55:45.070487
10056 11:55:45.070589
10057 11:55:45.073434 Starting depthcharge on Spherion...
10058 11:55:45.073517
10059 11:55:45.073582 Wipe memory regions:
10060 11:55:45.073643
10061 11:55:45.074364 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10062 11:55:45.074486 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10063 11:55:45.074572 Setting prompt string to ['asurada:']
10064 11:55:45.074655 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10065 11:55:45.076757 [0x00000040000000, 0x00000054600000)
10066 11:55:45.199540
10067 11:55:45.199692 [0x00000054660000, 0x00000080000000)
10068 11:55:45.459990
10069 11:55:45.460164 [0x000000821a7280, 0x000000ffe64000)
10070 11:55:46.204819
10071 11:55:46.204977 [0x00000100000000, 0x00000240000000)
10072 11:55:48.094976
10073 11:55:48.098119 Initializing XHCI USB controller at 0x11200000.
10074 11:55:49.136280
10075 11:55:49.139749 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10076 11:55:49.140268
10077 11:55:49.140612
10078 11:55:49.140927
10079 11:55:49.141681 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10081 11:55:49.242943 asurada: tftpboot 192.168.201.1 12066552/tftp-deploy-2cwi2ezc/kernel/image.itb 12066552/tftp-deploy-2cwi2ezc/kernel/cmdline
10082 11:55:49.243558 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10083 11:55:49.244030 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10084 11:55:49.248924 tftpboot 192.168.201.1 12066552/tftp-deploy-2cwi2ezc/kernel/image.itp-deploy-2cwi2ezc/kernel/cmdline
10085 11:55:49.249452
10086 11:55:49.249790 Waiting for link
10087 11:55:49.409524
10088 11:55:49.410034 R8152: Initializing
10089 11:55:49.410434
10090 11:55:49.412885 Version 6 (ocp_data = 5c30)
10091 11:55:49.413414
10092 11:55:49.416265 R8152: Done initializing
10093 11:55:49.416782
10094 11:55:49.417121 Adding net device
10095 11:55:51.283426
10096 11:55:51.284136 done.
10097 11:55:51.284642
10098 11:55:51.285006 MAC: 00:24:32:30:7c:7b
10099 11:55:51.285412
10100 11:55:51.286836 Sending DHCP discover... done.
10101 11:55:51.287264
10102 11:55:51.289720 Waiting for reply... done.
10103 11:55:51.290139
10104 11:55:51.292936 Sending DHCP request... done.
10105 11:55:51.293359
10106 11:55:51.299150 Waiting for reply... done.
10107 11:55:51.299690
10108 11:55:51.300031 My ip is 192.168.201.14
10109 11:55:51.300340
10110 11:55:51.301852 The DHCP server ip is 192.168.201.1
10111 11:55:51.302305
10112 11:55:51.308547 TFTP server IP predefined by user: 192.168.201.1
10113 11:55:51.309066
10114 11:55:51.315315 Bootfile predefined by user: 12066552/tftp-deploy-2cwi2ezc/kernel/image.itb
10115 11:55:51.315888
10116 11:55:51.318351 Sending tftp read request... done.
10117 11:55:51.318772
10118 11:55:51.325380 Waiting for the transfer...
10119 11:55:51.325905
10120 11:55:51.981415 00000000 ################################################################
10121 11:55:51.981932
10122 11:55:52.657235 00080000 ################################################################
10123 11:55:52.657858
10124 11:55:53.337589 00100000 ################################################################
10125 11:55:53.338098
10126 11:55:54.019380 00180000 ################################################################
10127 11:55:54.019876
10128 11:55:54.695774 00200000 ################################################################
10129 11:55:54.696482
10130 11:55:55.372476 00280000 ################################################################
10131 11:55:55.373002
10132 11:55:56.048964 00300000 ################################################################
10133 11:55:56.049466
10134 11:55:56.706897 00380000 ################################################################
10135 11:55:56.707392
10136 11:55:57.336882 00400000 ################################################################
10137 11:55:57.337393
10138 11:55:57.999320 00480000 ################################################################
10139 11:55:57.999880
10140 11:55:58.522538 00500000 ################################################################
10141 11:55:58.522686
10142 11:55:59.042393 00580000 ################################################################
10143 11:55:59.042538
10144 11:55:59.561987 00600000 ################################################################
10145 11:55:59.562128
10146 11:56:00.087991 00680000 ################################################################
10147 11:56:00.088138
10148 11:56:00.618198 00700000 ################################################################
10149 11:56:00.618353
10150 11:56:01.150083 00780000 ################################################################
10151 11:56:01.150231
10152 11:56:01.686311 00800000 ################################################################
10153 11:56:01.686454
10154 11:56:02.208721 00880000 ################################################################
10155 11:56:02.208869
10156 11:56:02.724563 00900000 ################################################################
10157 11:56:02.724714
10158 11:56:03.246949 00980000 ################################################################
10159 11:56:03.247098
10160 11:56:03.770054 00a00000 ################################################################
10161 11:56:03.770196
10162 11:56:04.299897 00a80000 ################################################################
10163 11:56:04.300039
10164 11:56:04.822857 00b00000 ################################################################
10165 11:56:04.822999
10166 11:56:05.356638 00b80000 ################################################################
10167 11:56:05.356781
10168 11:56:05.880063 00c00000 ################################################################
10169 11:56:05.880207
10170 11:56:06.408941 00c80000 ################################################################
10171 11:56:06.409072
10172 11:56:06.935604 00d00000 ################################################################
10173 11:56:06.935739
10174 11:56:07.467662 00d80000 ################################################################
10175 11:56:07.467801
10176 11:56:07.994807 00e00000 ################################################################
10177 11:56:07.994944
10178 11:56:08.521836 00e80000 ################################################################
10179 11:56:08.521975
10180 11:56:09.050176 00f00000 ################################################################
10181 11:56:09.050392
10182 11:56:09.582066 00f80000 ################################################################
10183 11:56:09.582204
10184 11:56:10.109900 01000000 ################################################################
10185 11:56:10.110036
10186 11:56:10.629557 01080000 ################################################################
10187 11:56:10.629706
10188 11:56:11.149572 01100000 ################################################################
10189 11:56:11.149716
10190 11:56:11.672875 01180000 ################################################################
10191 11:56:11.673023
10192 11:56:12.204879 01200000 ################################################################
10193 11:56:12.205026
10194 11:56:12.741150 01280000 ################################################################
10195 11:56:12.741320
10196 11:56:13.269332 01300000 ################################################################
10197 11:56:13.269477
10198 11:56:13.798166 01380000 ################################################################
10199 11:56:13.798346
10200 11:56:14.333209 01400000 ################################################################
10201 11:56:14.333358
10202 11:56:14.855617 01480000 ################################################################
10203 11:56:14.855764
10204 11:56:15.382148 01500000 ################################################################
10205 11:56:15.382328
10206 11:56:15.905222 01580000 ################################################################
10207 11:56:15.905367
10208 11:56:16.432707 01600000 ################################################################
10209 11:56:16.432856
10210 11:56:16.955738 01680000 ################################################################
10211 11:56:16.955883
10212 11:56:17.491000 01700000 ################################################################
10213 11:56:17.491146
10214 11:56:18.024218 01780000 ################################################################
10215 11:56:18.024376
10216 11:56:18.556116 01800000 ################################################################
10217 11:56:18.556259
10218 11:56:19.080031 01880000 ################################################################
10219 11:56:19.080176
10220 11:56:19.598124 01900000 ################################################################
10221 11:56:19.598296
10222 11:56:20.116573 01980000 ################################################################
10223 11:56:20.116717
10224 11:56:20.649089 01a00000 ################################################################
10225 11:56:20.649238
10226 11:56:21.172493 01a80000 ################################################################
10227 11:56:21.172639
10228 11:56:21.701640 01b00000 ################################################################
10229 11:56:21.701784
10230 11:56:21.755951 01b80000 ####### done.
10231 11:56:21.756040
10232 11:56:21.759392 The bootfile was 28889566 bytes long.
10233 11:56:21.759481
10234 11:56:21.762965 Sending tftp read request... done.
10235 11:56:21.763050
10236 11:56:21.763117 Waiting for the transfer...
10237 11:56:21.763179
10238 11:56:21.766059 00000000 # done.
10239 11:56:21.766145
10240 11:56:21.772527 Command line loaded dynamically from TFTP file: 12066552/tftp-deploy-2cwi2ezc/kernel/cmdline
10241 11:56:21.772612
10242 11:56:21.796193 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10243 11:56:21.796280
10244 11:56:21.796345 Loading FIT.
10245 11:56:21.796406
10246 11:56:21.799438 Image ramdisk-1 has 17793070 bytes.
10247 11:56:21.799521
10248 11:56:21.802360 Image fdt-1 has 47278 bytes.
10249 11:56:21.802443
10250 11:56:21.805609 Image kernel-1 has 11047184 bytes.
10251 11:56:21.805692
10252 11:56:21.815537 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10253 11:56:21.815621
10254 11:56:21.831805 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10255 11:56:21.831894
10256 11:56:21.838489 Choosing best match conf-1 for compat google,spherion-rev2.
10257 11:56:21.838572
10258 11:56:21.863530 Connected to device vid:did:rid of 1ae0:0028:00
10259 11:56:21.882382
10260 11:56:21.885477 tpm_get_response: command 0x17b, return code 0x0
10261 11:56:21.885560
10262 11:56:21.889091 ec_init: CrosEC protocol v3 supported (256, 248)
10263 11:56:21.892616
10264 11:56:21.895914 tpm_cleanup: add release locality here.
10265 11:56:21.895997
10266 11:56:21.899220 Shutting down all USB controllers.
10267 11:56:21.899302
10268 11:56:21.902163 Removing current net device
10269 11:56:21.902246
10270 11:56:21.905680 Exiting depthcharge with code 4 at timestamp: 66091253
10271 11:56:21.905763
10272 11:56:21.908696 LZMA decompressing kernel-1 to 0x821a6718
10273 11:56:21.908779
10274 11:56:21.915772 LZMA decompressing kernel-1 to 0x40000000
10275 11:56:23.303080
10276 11:56:23.303595 jumping to kernel
10277 11:56:23.305146 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10278 11:56:23.305640 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10279 11:56:23.306018 Setting prompt string to ['Linux version [0-9]']
10280 11:56:23.306415 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10281 11:56:23.306779 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10282 11:56:23.385873
10283 11:56:23.389365 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10284 11:56:23.393439 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10285 11:56:23.393900 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10286 11:56:23.394294 Setting prompt string to []
10287 11:56:23.394691 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10288 11:56:23.395064 Using line separator: #'\n'#
10289 11:56:23.395369 No login prompt set.
10290 11:56:23.395683 Parsing kernel messages
10291 11:56:23.395969 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10292 11:56:23.396473 [login-action] Waiting for messages, (timeout 00:03:47)
10293 11:56:23.412248 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10294 11:56:23.415429 [ 0.000000] random: crng init done
10295 11:56:23.422322 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10296 11:56:23.425900 [ 0.000000] efi: UEFI not found.
10297 11:56:23.431840 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10298 11:56:23.438575 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10299 11:56:23.448522 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10300 11:56:23.458444 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10301 11:56:23.465181 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10302 11:56:23.471291 [ 0.000000] printk: bootconsole [mtk8250] enabled
10303 11:56:23.478460 [ 0.000000] NUMA: No NUMA configuration found
10304 11:56:23.484458 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10305 11:56:23.487879 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10306 11:56:23.491267 [ 0.000000] Zone ranges:
10307 11:56:23.497793 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10308 11:56:23.501187 [ 0.000000] DMA32 empty
10309 11:56:23.507863 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10310 11:56:23.511230 [ 0.000000] Movable zone start for each node
10311 11:56:23.514543 [ 0.000000] Early memory node ranges
10312 11:56:23.520893 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10313 11:56:23.527602 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10314 11:56:23.533947 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10315 11:56:23.540490 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10316 11:56:23.547182 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10317 11:56:23.553965 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10318 11:56:23.610012 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10319 11:56:23.616682 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10320 11:56:23.623349 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10321 11:56:23.626584 [ 0.000000] psci: probing for conduit method from DT.
10322 11:56:23.633970 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10323 11:56:23.636372 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10324 11:56:23.642864 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10325 11:56:23.646772 [ 0.000000] psci: SMC Calling Convention v1.2
10326 11:56:23.653105 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10327 11:56:23.656269 [ 0.000000] Detected VIPT I-cache on CPU0
10328 11:56:23.663099 [ 0.000000] CPU features: detected: GIC system register CPU interface
10329 11:56:23.669528 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10330 11:56:23.676219 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10331 11:56:23.682680 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10332 11:56:23.692775 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10333 11:56:23.699415 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10334 11:56:23.702803 [ 0.000000] alternatives: applying boot alternatives
10335 11:56:23.708887 [ 0.000000] Fallback order for Node 0: 0
10336 11:56:23.715883 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10337 11:56:23.719415 [ 0.000000] Policy zone: Normal
10338 11:56:23.741877 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10339 11:56:23.751719 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10340 11:56:23.763272 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10341 11:56:23.773147 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10342 11:56:23.779975 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10343 11:56:23.782787 <6>[ 0.000000] software IO TLB: area num 8.
10344 11:56:23.839913 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10345 11:56:23.989098 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10346 11:56:23.995332 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10347 11:56:24.002718 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10348 11:56:24.004973 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10349 11:56:24.011743 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10350 11:56:24.018341 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10351 11:56:24.021619 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10352 11:56:24.031359 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10353 11:56:24.038239 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10354 11:56:24.044990 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10355 11:56:24.051417 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10356 11:56:24.054429 <6>[ 0.000000] GICv3: 608 SPIs implemented
10357 11:56:24.057632 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10358 11:56:24.064834 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10359 11:56:24.067669 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10360 11:56:24.074328 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10361 11:56:24.087645 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10362 11:56:24.100480 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10363 11:56:24.107372 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10364 11:56:24.116103 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10365 11:56:24.128692 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10366 11:56:24.135489 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10367 11:56:24.141755 <6>[ 0.009177] Console: colour dummy device 80x25
10368 11:56:24.152059 <6>[ 0.013934] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10369 11:56:24.158817 <6>[ 0.024441] pid_max: default: 32768 minimum: 301
10370 11:56:24.161893 <6>[ 0.029343] LSM: Security Framework initializing
10371 11:56:24.168111 <6>[ 0.034281] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10372 11:56:24.178066 <6>[ 0.042094] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10373 11:56:24.187999 <6>[ 0.051502] cblist_init_generic: Setting adjustable number of callback queues.
10374 11:56:24.195159 <6>[ 0.058990] cblist_init_generic: Setting shift to 3 and lim to 1.
10375 11:56:24.201039 <6>[ 0.065327] cblist_init_generic: Setting adjustable number of callback queues.
10376 11:56:24.208162 <6>[ 0.072754] cblist_init_generic: Setting shift to 3 and lim to 1.
10377 11:56:24.211132 <6>[ 0.079192] rcu: Hierarchical SRCU implementation.
10378 11:56:24.217995 <6>[ 0.084207] rcu: Max phase no-delay instances is 1000.
10379 11:56:24.224475 <6>[ 0.091263] EFI services will not be available.
10380 11:56:24.227730 <6>[ 0.096213] smp: Bringing up secondary CPUs ...
10381 11:56:24.236224 <6>[ 0.101258] Detected VIPT I-cache on CPU1
10382 11:56:24.243767 <6>[ 0.101328] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10383 11:56:24.249286 <6>[ 0.101362] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10384 11:56:24.252602 <6>[ 0.101697] Detected VIPT I-cache on CPU2
10385 11:56:24.262694 <6>[ 0.101750] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10386 11:56:24.269275 <6>[ 0.101768] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10387 11:56:24.272940 <6>[ 0.102024] Detected VIPT I-cache on CPU3
10388 11:56:24.279395 <6>[ 0.102070] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10389 11:56:24.285611 <6>[ 0.102083] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10390 11:56:24.292396 <6>[ 0.102388] CPU features: detected: Spectre-v4
10391 11:56:24.296081 <6>[ 0.102394] CPU features: detected: Spectre-BHB
10392 11:56:24.299043 <6>[ 0.102399] Detected PIPT I-cache on CPU4
10393 11:56:24.305466 <6>[ 0.102457] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10394 11:56:24.312044 <6>[ 0.102474] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10395 11:56:24.318897 <6>[ 0.102768] Detected PIPT I-cache on CPU5
10396 11:56:24.325189 <6>[ 0.102830] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10397 11:56:24.331808 <6>[ 0.102846] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10398 11:56:24.335365 <6>[ 0.103127] Detected PIPT I-cache on CPU6
10399 11:56:24.345408 <6>[ 0.103191] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10400 11:56:24.352138 <6>[ 0.103207] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10401 11:56:24.355292 <6>[ 0.103505] Detected PIPT I-cache on CPU7
10402 11:56:24.362095 <6>[ 0.103570] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10403 11:56:24.368067 <6>[ 0.103586] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10404 11:56:24.371404 <6>[ 0.103633] smp: Brought up 1 node, 8 CPUs
10405 11:56:24.378089 <6>[ 0.245027] SMP: Total of 8 processors activated.
10406 11:56:24.384718 <6>[ 0.249948] CPU features: detected: 32-bit EL0 Support
10407 11:56:24.391166 <6>[ 0.255311] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10408 11:56:24.397847 <6>[ 0.264111] CPU features: detected: Common not Private translations
10409 11:56:24.404543 <6>[ 0.270586] CPU features: detected: CRC32 instructions
10410 11:56:24.411109 <6>[ 0.275971] CPU features: detected: RCpc load-acquire (LDAPR)
10411 11:56:24.414221 <6>[ 0.281967] CPU features: detected: LSE atomic instructions
10412 11:56:24.420751 <6>[ 0.287748] CPU features: detected: Privileged Access Never
10413 11:56:24.427369 <6>[ 0.293528] CPU features: detected: RAS Extension Support
10414 11:56:24.434235 <6>[ 0.299171] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10415 11:56:24.437165 <6>[ 0.306392] CPU: All CPU(s) started at EL2
10416 11:56:24.444088 <6>[ 0.310735] alternatives: applying system-wide alternatives
10417 11:56:24.454220 <6>[ 0.321443] devtmpfs: initialized
10418 11:56:24.469647 <6>[ 0.330458] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10419 11:56:24.476375 <6>[ 0.340420] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10420 11:56:24.482849 <6>[ 0.348663] pinctrl core: initialized pinctrl subsystem
10421 11:56:24.486666 <6>[ 0.355327] DMI not present or invalid.
10422 11:56:24.492773 <6>[ 0.359745] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10423 11:56:24.503077 <6>[ 0.366520] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10424 11:56:24.509565 <6>[ 0.374105] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10425 11:56:24.519048 <6>[ 0.382329] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10426 11:56:24.522555 <6>[ 0.390569] audit: initializing netlink subsys (disabled)
10427 11:56:24.533557 <5>[ 0.396263] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10428 11:56:24.539532 <6>[ 0.396965] thermal_sys: Registered thermal governor 'step_wise'
10429 11:56:24.545705 <6>[ 0.404232] thermal_sys: Registered thermal governor 'power_allocator'
10430 11:56:24.549618 <6>[ 0.410486] cpuidle: using governor menu
10431 11:56:24.555848 <6>[ 0.421448] NET: Registered PF_QIPCRTR protocol family
10432 11:56:24.563087 <6>[ 0.426946] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10433 11:56:24.568848 <6>[ 0.434046] ASID allocator initialised with 32768 entries
10434 11:56:24.572486 <6>[ 0.440615] Serial: AMBA PL011 UART driver
10435 11:56:24.582150 <4>[ 0.449432] Trying to register duplicate clock ID: 134
10436 11:56:24.639071 <6>[ 0.509088] KASLR enabled
10437 11:56:24.653069 <6>[ 0.516759] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10438 11:56:24.659217 <6>[ 0.523772] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10439 11:56:24.665979 <6>[ 0.530264] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10440 11:56:24.672373 <6>[ 0.537270] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10441 11:56:24.679167 <6>[ 0.543755] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10442 11:56:24.685557 <6>[ 0.550761] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10443 11:56:24.692016 <6>[ 0.557250] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10444 11:56:24.698796 <6>[ 0.564256] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10445 11:56:24.702489 <6>[ 0.571714] ACPI: Interpreter disabled.
10446 11:56:24.711095 <6>[ 0.578131] iommu: Default domain type: Translated
10447 11:56:24.718026 <6>[ 0.583284] iommu: DMA domain TLB invalidation policy: strict mode
10448 11:56:24.721024 <5>[ 0.589945] SCSI subsystem initialized
10449 11:56:24.727197 <6>[ 0.594195] usbcore: registered new interface driver usbfs
10450 11:56:24.734358 <6>[ 0.599926] usbcore: registered new interface driver hub
10451 11:56:24.737455 <6>[ 0.605478] usbcore: registered new device driver usb
10452 11:56:24.744417 <6>[ 0.611598] pps_core: LinuxPPS API ver. 1 registered
10453 11:56:24.754203 <6>[ 0.616793] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10454 11:56:24.758199 <6>[ 0.626136] PTP clock support registered
10455 11:56:24.760867 <6>[ 0.630379] EDAC MC: Ver: 3.0.0
10456 11:56:24.769143 <6>[ 0.635540] FPGA manager framework
10457 11:56:24.774702 <6>[ 0.639215] Advanced Linux Sound Architecture Driver Initialized.
10458 11:56:24.778171 <6>[ 0.645983] vgaarb: loaded
10459 11:56:24.785580 <6>[ 0.649167] clocksource: Switched to clocksource arch_sys_counter
10460 11:56:24.788060 <5>[ 0.655615] VFS: Disk quotas dquot_6.6.0
10461 11:56:24.794784 <6>[ 0.659802] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10462 11:56:24.797922 <6>[ 0.666991] pnp: PnP ACPI: disabled
10463 11:56:24.806198 <6>[ 0.673639] NET: Registered PF_INET protocol family
10464 11:56:24.816229 <6>[ 0.679225] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10465 11:56:24.828062 <6>[ 0.691534] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10466 11:56:24.837808 <6>[ 0.700352] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10467 11:56:24.843969 <6>[ 0.708321] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10468 11:56:24.854083 <6>[ 0.717022] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10469 11:56:24.860714 <6>[ 0.726769] TCP: Hash tables configured (established 65536 bind 65536)
10470 11:56:24.866861 <6>[ 0.733634] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10471 11:56:24.877340 <6>[ 0.740834] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10472 11:56:24.884604 <6>[ 0.748533] NET: Registered PF_UNIX/PF_LOCAL protocol family
10473 11:56:24.890146 <6>[ 0.754700] RPC: Registered named UNIX socket transport module.
10474 11:56:24.893915 <6>[ 0.760851] RPC: Registered udp transport module.
10475 11:56:24.899898 <6>[ 0.765783] RPC: Registered tcp transport module.
10476 11:56:24.906676 <6>[ 0.770717] RPC: Registered tcp NFSv4.1 backchannel transport module.
10477 11:56:24.909854 <6>[ 0.777380] PCI: CLS 0 bytes, default 64
10478 11:56:24.913218 <6>[ 0.781775] Unpacking initramfs...
10479 11:56:24.937705 <6>[ 0.801301] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10480 11:56:24.947506 <6>[ 0.810010] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10481 11:56:24.950817 <6>[ 0.818779] kvm [1]: IPA Size Limit: 40 bits
10482 11:56:24.957584 <6>[ 0.823320] kvm [1]: GICv3: no GICV resource entry
10483 11:56:24.961309 <6>[ 0.828343] kvm [1]: disabling GICv2 emulation
10484 11:56:24.967087 <6>[ 0.833033] kvm [1]: GIC system register CPU interface enabled
10485 11:56:24.970417 <6>[ 0.839198] kvm [1]: vgic interrupt IRQ18
10486 11:56:24.977086 <6>[ 0.843561] kvm [1]: VHE mode initialized successfully
10487 11:56:24.983569 <5>[ 0.850118] Initialise system trusted keyrings
10488 11:56:24.990173 <6>[ 0.854952] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10489 11:56:24.997976 <6>[ 0.865016] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10490 11:56:25.004316 <5>[ 0.871431] NFS: Registering the id_resolver key type
10491 11:56:25.007912 <5>[ 0.876733] Key type id_resolver registered
10492 11:56:25.014879 <5>[ 0.881147] Key type id_legacy registered
10493 11:56:25.020768 <6>[ 0.885421] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10494 11:56:25.027394 <6>[ 0.892343] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10495 11:56:25.034020 <6>[ 0.900069] 9p: Installing v9fs 9p2000 file system support
10496 11:56:25.070696 <5>[ 0.937620] Key type asymmetric registered
10497 11:56:25.074036 <5>[ 0.941951] Asymmetric key parser 'x509' registered
10498 11:56:25.083627 <6>[ 0.947098] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10499 11:56:25.087583 <6>[ 0.954715] io scheduler mq-deadline registered
10500 11:56:25.090332 <6>[ 0.959478] io scheduler kyber registered
10501 11:56:25.109540 <6>[ 0.976637] EINJ: ACPI disabled.
10502 11:56:25.141735 <4>[ 1.002301] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10503 11:56:25.151796 <4>[ 1.012935] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10504 11:56:25.167360 <6>[ 1.033977] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10505 11:56:25.174826 <6>[ 1.041992] printk: console [ttyS0] disabled
10506 11:56:25.202651 <6>[ 1.066655] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10507 11:56:25.209793 <6>[ 1.076146] printk: console [ttyS0] enabled
10508 11:56:25.213141 <6>[ 1.076146] printk: console [ttyS0] enabled
10509 11:56:25.219218 <6>[ 1.085040] printk: bootconsole [mtk8250] disabled
10510 11:56:25.223039 <6>[ 1.085040] printk: bootconsole [mtk8250] disabled
10511 11:56:25.229865 <6>[ 1.096272] SuperH (H)SCI(F) driver initialized
10512 11:56:25.232526 <6>[ 1.101560] msm_serial: driver initialized
10513 11:56:25.246765 <6>[ 1.110548] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10514 11:56:25.256858 <6>[ 1.119095] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10515 11:56:25.263138 <6>[ 1.127641] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10516 11:56:25.272941 <6>[ 1.136270] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10517 11:56:25.283009 <6>[ 1.144978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10518 11:56:25.290469 <6>[ 1.153690] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10519 11:56:25.300020 <6>[ 1.162230] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10520 11:56:25.306812 <6>[ 1.171062] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10521 11:56:25.316249 <6>[ 1.179606] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10522 11:56:25.327789 <6>[ 1.195154] loop: module loaded
10523 11:56:25.334585 <6>[ 1.201231] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10524 11:56:25.357636 <4>[ 1.224600] mtk-pmic-keys: Failed to locate of_node [id: -1]
10525 11:56:25.364199 <6>[ 1.231492] megasas: 07.719.03.00-rc1
10526 11:56:25.373786 <6>[ 1.241100] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10527 11:56:25.385553 <6>[ 1.252557] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10528 11:56:25.402161 <6>[ 1.269369] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10529 11:56:25.458799 <6>[ 1.319337] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10530 11:56:25.676185 <6>[ 1.543261] Freeing initrd memory: 17372K
10531 11:56:25.686454 <6>[ 1.553597] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10532 11:56:25.697265 <6>[ 1.564507] tun: Universal TUN/TAP device driver, 1.6
10533 11:56:25.700966 <6>[ 1.570568] thunder_xcv, ver 1.0
10534 11:56:25.703944 <6>[ 1.574071] thunder_bgx, ver 1.0
10535 11:56:25.707000 <6>[ 1.577570] nicpf, ver 1.0
10536 11:56:25.718112 <6>[ 1.581584] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10537 11:56:25.721324 <6>[ 1.589061] hns3: Copyright (c) 2017 Huawei Corporation.
10538 11:56:25.727516 <6>[ 1.594648] hclge is initializing
10539 11:56:25.731034 <6>[ 1.598228] e1000: Intel(R) PRO/1000 Network Driver
10540 11:56:25.737836 <6>[ 1.603359] e1000: Copyright (c) 1999-2006 Intel Corporation.
10541 11:56:25.741138 <6>[ 1.609375] e1000e: Intel(R) PRO/1000 Network Driver
10542 11:56:25.748243 <6>[ 1.614591] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10543 11:56:25.754248 <6>[ 1.620778] igb: Intel(R) Gigabit Ethernet Network Driver
10544 11:56:25.761189 <6>[ 1.626428] igb: Copyright (c) 2007-2014 Intel Corporation.
10545 11:56:25.767714 <6>[ 1.632264] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10546 11:56:25.774392 <6>[ 1.638781] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10547 11:56:25.777540 <6>[ 1.645254] sky2: driver version 1.30
10548 11:56:25.783890 <6>[ 1.650269] VFIO - User Level meta-driver version: 0.3
10549 11:56:25.791405 <6>[ 1.658499] usbcore: registered new interface driver usb-storage
10550 11:56:25.798010 <6>[ 1.664940] usbcore: registered new device driver onboard-usb-hub
10551 11:56:25.807007 <6>[ 1.674095] mt6397-rtc mt6359-rtc: registered as rtc0
10552 11:56:25.816832 <6>[ 1.679562] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:56:25 UTC (1700740585)
10553 11:56:25.819868 <6>[ 1.689126] i2c_dev: i2c /dev entries driver
10554 11:56:25.836613 <6>[ 1.700823] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10555 11:56:25.856914 <6>[ 1.723748] cpu cpu0: EM: created perf domain
10556 11:56:25.859903 <6>[ 1.728676] cpu cpu4: EM: created perf domain
10557 11:56:25.866978 <6>[ 1.734273] sdhci: Secure Digital Host Controller Interface driver
10558 11:56:25.874022 <6>[ 1.740706] sdhci: Copyright(c) Pierre Ossman
10559 11:56:25.880369 <6>[ 1.745655] Synopsys Designware Multimedia Card Interface Driver
10560 11:56:25.886858 <6>[ 1.752288] sdhci-pltfm: SDHCI platform and OF driver helper
10561 11:56:25.890229 <6>[ 1.752408] mmc0: CQHCI version 5.10
10562 11:56:25.896954 <6>[ 1.762388] ledtrig-cpu: registered to indicate activity on CPUs
10563 11:56:25.903738 <6>[ 1.769427] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10564 11:56:25.910188 <6>[ 1.776478] usbcore: registered new interface driver usbhid
10565 11:56:25.913408 <6>[ 1.782302] usbhid: USB HID core driver
10566 11:56:25.920418 <6>[ 1.786501] spi_master spi0: will run message pump with realtime priority
10567 11:56:25.966153 <6>[ 1.826780] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10568 11:56:25.985637 <6>[ 1.842926] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10569 11:56:25.989417 <6>[ 1.856937] mmc0: Command Queue Engine enabled
10570 11:56:25.995703 <6>[ 1.861685] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10571 11:56:26.002189 <6>[ 1.868584] cros-ec-spi spi0.0: Chrome EC device registered
10572 11:56:26.005689 <6>[ 1.869041] mmcblk0: mmc0:0001 DA4128 116 GiB
10573 11:56:26.017583 <6>[ 1.884966] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10574 11:56:26.024966 <6>[ 1.892411] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10575 11:56:26.031970 <6>[ 1.898348] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10576 11:56:26.038096 <6>[ 1.904448] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10577 11:56:26.053413 <6>[ 1.917040] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10578 11:56:26.060554 <6>[ 1.927425] NET: Registered PF_PACKET protocol family
10579 11:56:26.063446 <6>[ 1.932854] 9pnet: Installing 9P2000 support
10580 11:56:26.070596 <5>[ 1.937431] Key type dns_resolver registered
10581 11:56:26.074470 <6>[ 1.942548] registered taskstats version 1
10582 11:56:26.080351 <5>[ 1.946960] Loading compiled-in X.509 certificates
10583 11:56:26.108942 <4>[ 1.969594] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10584 11:56:26.118822 <4>[ 1.980414] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10585 11:56:26.125941 <3>[ 1.990953] debugfs: File 'uA_load' in directory '/' already present!
10586 11:56:26.131809 <3>[ 1.997654] debugfs: File 'min_uV' in directory '/' already present!
10587 11:56:26.138568 <3>[ 2.004262] debugfs: File 'max_uV' in directory '/' already present!
10588 11:56:26.145203 <3>[ 2.010868] debugfs: File 'constraint_flags' in directory '/' already present!
10589 11:56:26.157014 <3>[ 2.020690] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10590 11:56:26.166863 <6>[ 2.033984] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10591 11:56:26.173683 <6>[ 2.040731] xhci-mtk 11200000.usb: xHCI Host Controller
10592 11:56:26.180206 <6>[ 2.046260] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10593 11:56:26.190133 <6>[ 2.054105] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10594 11:56:26.197458 <6>[ 2.063523] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10595 11:56:26.204199 <6>[ 2.069580] xhci-mtk 11200000.usb: xHCI Host Controller
10596 11:56:26.210527 <6>[ 2.075054] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10597 11:56:26.217060 <6>[ 2.082701] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10598 11:56:26.223686 <6>[ 2.090532] hub 1-0:1.0: USB hub found
10599 11:56:26.226674 <6>[ 2.094568] hub 1-0:1.0: 1 port detected
10600 11:56:26.233009 <6>[ 2.098842] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10601 11:56:26.240050 <6>[ 2.107585] hub 2-0:1.0: USB hub found
10602 11:56:26.243932 <6>[ 2.111604] hub 2-0:1.0: 1 port detected
10603 11:56:26.252665 <6>[ 2.119761] mtk-msdc 11f70000.mmc: Got CD GPIO
10604 11:56:26.262229 <6>[ 2.126150] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10605 11:56:26.268943 <6>[ 2.134171] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10606 11:56:26.279092 <4>[ 2.142069] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10607 11:56:26.285872 <6>[ 2.151602] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10608 11:56:26.296219 <6>[ 2.159679] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10609 11:56:26.302440 <6>[ 2.167776] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10610 11:56:26.312503 <6>[ 2.175721] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10611 11:56:26.319255 <6>[ 2.183538] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10612 11:56:26.328865 <6>[ 2.191356] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10613 11:56:26.338373 <6>[ 2.201941] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10614 11:56:26.345412 <6>[ 2.210320] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10615 11:56:26.355644 <6>[ 2.218662] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10616 11:56:26.361762 <6>[ 2.227001] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10617 11:56:26.371545 <6>[ 2.235339] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10618 11:56:26.378452 <6>[ 2.243679] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10619 11:56:26.387889 <6>[ 2.252029] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10620 11:56:26.394637 <6>[ 2.260367] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10621 11:56:26.405059 <6>[ 2.268706] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10622 11:56:26.414583 <6>[ 2.277045] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10623 11:56:26.421173 <6>[ 2.285388] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10624 11:56:26.431100 <6>[ 2.293728] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10625 11:56:26.438019 <6>[ 2.302066] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10626 11:56:26.448164 <6>[ 2.310404] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10627 11:56:26.454301 <6>[ 2.318743] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10628 11:56:26.460991 <6>[ 2.327479] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10629 11:56:26.467482 <6>[ 2.334649] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10630 11:56:26.474281 <6>[ 2.341411] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10631 11:56:26.483857 <6>[ 2.348161] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10632 11:56:26.490641 <6>[ 2.355103] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10633 11:56:26.497486 <6>[ 2.361951] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10634 11:56:26.507654 <6>[ 2.371077] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10635 11:56:26.517117 <6>[ 2.380196] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10636 11:56:26.527439 <6>[ 2.389490] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10637 11:56:26.536691 <6>[ 2.398962] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10638 11:56:26.547190 <6>[ 2.408430] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10639 11:56:26.553297 <6>[ 2.417549] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10640 11:56:26.563240 <6>[ 2.427019] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10641 11:56:26.573406 <6>[ 2.436139] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10642 11:56:26.582579 <6>[ 2.445432] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10643 11:56:26.592578 <6>[ 2.455592] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10644 11:56:26.603278 <6>[ 2.467195] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10645 11:56:26.610037 <6>[ 2.476918] Trying to probe devices needed for running init ...
10646 11:56:26.634295 <6>[ 2.497796] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10647 11:56:26.662070 <6>[ 2.529031] hub 2-1:1.0: USB hub found
10648 11:56:26.664752 <6>[ 2.533520] hub 2-1:1.0: 3 ports detected
10649 11:56:26.673486 <6>[ 2.540743] hub 2-1:1.0: USB hub found
10650 11:56:26.676836 <6>[ 2.545047] hub 2-1:1.0: 3 ports detected
10651 11:56:26.785135 <6>[ 2.649437] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10652 11:56:26.940018 <6>[ 2.807449] hub 1-1:1.0: USB hub found
10653 11:56:26.943168 <6>[ 2.811943] hub 1-1:1.0: 4 ports detected
10654 11:56:26.953605 <6>[ 2.820664] hub 1-1:1.0: USB hub found
10655 11:56:26.956676 <6>[ 2.825165] hub 1-1:1.0: 4 ports detected
10656 11:56:27.025963 <6>[ 2.889691] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10657 11:56:27.277463 <6>[ 3.141481] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10658 11:56:27.410418 <6>[ 3.277456] hub 1-1.4:1.0: USB hub found
10659 11:56:27.413160 <6>[ 3.282126] hub 1-1.4:1.0: 2 ports detected
10660 11:56:27.423068 <6>[ 3.290722] hub 1-1.4:1.0: USB hub found
10661 11:56:27.426706 <6>[ 3.295325] hub 1-1.4:1.0: 2 ports detected
10662 11:56:27.725353 <6>[ 3.589458] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10663 11:56:27.917265 <6>[ 3.781460] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10664 11:56:38.894617 <6>[ 14.766508] ALSA device list:
10665 11:56:38.901227 <6>[ 14.769802] No soundcards found.
10666 11:56:38.908990 <6>[ 14.777712] Freeing unused kernel memory: 8384K
10667 11:56:38.912437 <6>[ 14.782698] Run /init as init process
10668 11:56:38.923596 Loading, please wait...
10669 11:56:38.945036 Starting version 247.3-7+deb11u2
10670 11:56:39.194002 <6>[ 15.059478] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10671 11:56:39.203250 <6>[ 15.071555] remoteproc remoteproc0: scp is available
10672 11:56:39.209230 <6>[ 15.076960] remoteproc remoteproc0: powering up scp
10673 11:56:39.216011 <6>[ 15.082549] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10674 11:56:39.222492 <6>[ 15.091066] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10675 11:56:39.229180 <6>[ 15.093092] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10676 11:56:39.239313 <3>[ 15.099381] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 11:56:39.245796 <6>[ 15.104408] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10678 11:56:39.256389 <3>[ 15.112394] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 11:56:39.265848 <6>[ 15.121085] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10680 11:56:39.268996 <6>[ 15.121307] mc: Linux media interface: v0.10
10681 11:56:39.275857 <3>[ 15.129366] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 11:56:39.285810 <4>[ 15.143348] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10683 11:56:39.292004 <6>[ 15.152128] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10684 11:56:39.299076 <3>[ 15.152892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 11:56:39.308600 <3>[ 15.152912] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 11:56:39.315176 <3>[ 15.152916] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 11:56:39.325729 <3>[ 15.152924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:56:39.332062 <3>[ 15.152928] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 11:56:39.339825 <3>[ 15.152996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 11:56:39.348919 <3>[ 15.153031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10691 11:56:39.355755 <3>[ 15.153036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10692 11:56:39.366101 <3>[ 15.153039] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 11:56:39.373311 <3>[ 15.153073] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10694 11:56:39.379577 <3>[ 15.153078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10695 11:56:39.390461 <3>[ 15.153082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10696 11:56:39.396424 <3>[ 15.153085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 11:56:39.406087 <3>[ 15.153088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10698 11:56:39.412961 <3>[ 15.153106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 11:56:39.419137 <4>[ 15.158010] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10700 11:56:39.425727 <6>[ 15.190821] videodev: Linux video capture interface: v2.00
10701 11:56:39.435500 <4>[ 15.195838] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10702 11:56:39.439431 <4>[ 15.195838] Fallback method does not support PEC.
10703 11:56:39.445579 <6>[ 15.200160] usbcore: registered new interface driver r8152
10704 11:56:39.455423 <3>[ 15.211260] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10705 11:56:39.462957 <6>[ 15.221925] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10706 11:56:39.468492 <6>[ 15.221933] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10707 11:56:39.478915 <6>[ 15.231540] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10708 11:56:39.485292 <6>[ 15.238519] remoteproc remoteproc0: remote processor scp is now up
10709 11:56:39.495193 <6>[ 15.241694] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10710 11:56:39.505180 <6>[ 15.242039] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10711 11:56:39.512184 <3>[ 15.244007] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10712 11:56:39.521860 <6>[ 15.249537] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10713 11:56:39.528222 <6>[ 15.262578] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10714 11:56:39.538032 <6>[ 15.318982] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10715 11:56:39.541237 <6>[ 15.319424] pci_bus 0000:00: root bus resource [bus 00-ff]
10716 11:56:39.548058 <6>[ 15.358915] usbcore: registered new interface driver cdc_ether
10717 11:56:39.554479 <6>[ 15.368706] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10718 11:56:39.561185 <6>[ 15.378255] Bluetooth: Core ver 2.22
10719 11:56:39.572032 <6>[ 15.386385] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10720 11:56:39.577297 <6>[ 15.386393] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10721 11:56:39.584277 <6>[ 15.386553] usbcore: registered new interface driver r8153_ecm
10722 11:56:39.587367 <6>[ 15.394669] NET: Registered PF_BLUETOOTH protocol family
10723 11:56:39.594050 <6>[ 15.401648] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10724 11:56:39.600464 <6>[ 15.402482] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10725 11:56:39.613972 <6>[ 15.403951] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10726 11:56:39.620502 <6>[ 15.404045] usbcore: registered new interface driver uvcvideo
10727 11:56:39.627328 <6>[ 15.410783] Bluetooth: HCI device and connection manager initialized
10728 11:56:39.630973 <6>[ 15.410816] Bluetooth: HCI socket layer initialized
10729 11:56:39.637749 <6>[ 15.410821] Bluetooth: L2CAP socket layer initialized
10730 11:56:39.643627 <6>[ 15.416611] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10731 11:56:39.650848 <6>[ 15.422638] Bluetooth: SCO socket layer initialized
10732 11:56:39.656572 <6>[ 15.423159] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10733 11:56:39.660010 <6>[ 15.429927] pci 0000:00:00.0: supports D1 D2
10734 11:56:39.670371 <4>[ 15.433445] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10735 11:56:39.676693 <4>[ 15.433452] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10736 11:56:39.683911 <6>[ 15.477320] r8152 2-1.3:1.0 eth0: v1.12.13
10737 11:56:39.690030 <6>[ 15.487956] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10738 11:56:39.696879 <6>[ 15.488811] usbcore: registered new interface driver btusb
10739 11:56:39.703223 <6>[ 15.489133] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10740 11:56:39.710097 <6>[ 15.489251] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10741 11:56:39.716276 <6>[ 15.489278] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10742 11:56:39.722977 <6>[ 15.489295] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10743 11:56:39.732598 <6>[ 15.489310] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10744 11:56:39.736040 <6>[ 15.489415] pci 0000:01:00.0: supports D1 D2
10745 11:56:39.742855 <6>[ 15.489416] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10746 11:56:39.752907 <4>[ 15.489776] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10747 11:56:39.758917 <3>[ 15.489790] Bluetooth: hci0: Failed to load firmware file (-2)
10748 11:56:39.765609 <3>[ 15.489795] Bluetooth: hci0: Failed to set up firmware (-2)
10749 11:56:39.775872 <4>[ 15.489800] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10750 11:56:39.782470 <6>[ 15.501313] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10751 11:56:39.788656 <6>[ 15.501845] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10752 11:56:39.795876 <6>[ 15.662783] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10753 11:56:39.805499 <6>[ 15.670864] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10754 11:56:39.812561 <6>[ 15.678874] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10755 11:56:39.822807 <6>[ 15.686874] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10756 11:56:39.829016 <6>[ 15.694875] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10757 11:56:39.835725 <6>[ 15.702875] pci 0000:00:00.0: PCI bridge to [bus 01]
10758 11:56:39.841811 <6>[ 15.708091] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10759 11:56:39.848344 <6>[ 15.716217] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10760 11:56:39.855523 <6>[ 15.723044] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10761 11:56:39.861375 <6>[ 15.730313] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10762 11:56:39.878432 <5>[ 15.744084] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10763 11:56:39.901352 <5>[ 15.765701] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10764 11:56:39.906822 <4>[ 15.772598] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10765 11:56:39.913450 <6>[ 15.781491] cfg80211: failed to load regulatory.db
10766 11:56:39.956797 <6>[ 15.821537] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10767 11:56:39.963029 <6>[ 15.829037] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10768 11:56:39.987035 <6>[ 15.855674] mt7921e 0000:01:00.0: ASIC revision: 79610010
10769 11:56:40.094629 <4>[ 15.957209] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10770 11:56:40.114580 Begin: Loading essential drivers ... done.
10771 11:56:40.118214 Begin: Running /scripts/init-premount ... done.
10772 11:56:40.124722 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10773 11:56:40.134611 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10774 11:56:40.137803 Device /sys/class/net/enx002432307c7b found
10775 11:56:40.138401 done.
10776 11:56:40.163836 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10777 11:56:40.214126 <4>[ 16.076487] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 11:56:40.330335 <4>[ 16.192501] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 11:56:40.451030 <4>[ 16.312989] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 11:56:40.566432 <4>[ 16.428941] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 11:56:40.682682 <4>[ 16.544938] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 11:56:40.798947 <4>[ 16.660966] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 11:56:40.918454 <4>[ 16.780753] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10784 11:56:41.038821 <4>[ 16.900905] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10785 11:56:41.158691 <4>[ 17.020752] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10786 11:56:41.269943 <3>[ 17.138771] mt7921e 0000:01:00.0: hardware init failed
10787 11:56:41.314134 IP-Config: no response after 2 s<6>[ 17.181523] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10788 11:56:41.314782 ecs - giving up
10789 11:56:41.347843 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10790 11:56:42.455149 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10791 11:56:42.460883 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10792 11:56:42.467616 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10793 11:56:42.474204 host : mt8192-asurada-spherion-r0-cbg-2
10794 11:56:42.481540 domain : lava-rack
10795 11:56:42.484147 rootserver: 192.168.201.1 rootpath:
10796 11:56:42.487462 filename :
10797 11:56:42.548768 done.
10798 11:56:42.557030 Begin: Running /scripts/nfs-bottom ... done.
10799 11:56:42.574853 Begin: Running /scripts/init-bottom ... done.
10800 11:56:43.850423 <6>[ 19.719570] NET: Registered PF_INET6 protocol family
10801 11:56:43.858592 <6>[ 19.726929] Segment Routing with IPv6
10802 11:56:43.860860 <6>[ 19.730957] In-situ OAM (IOAM) with IPv6
10803 11:56:43.991960 <30>[ 19.844563] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10804 11:56:43.999453 <30>[ 19.868951] systemd[1]: Detected architecture arm64.
10805 11:56:44.022781
10806 11:56:44.026665 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10807 11:56:44.027091
10808 11:56:44.043617 <30>[ 19.912754] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10809 11:56:45.029399 <30>[ 20.895516] systemd[1]: Queued start job for default target Graphical Interface.
10810 11:56:45.070794 <30>[ 20.939892] systemd[1]: Created slice system-getty.slice.
10811 11:56:45.077155 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10812 11:56:45.093017 <30>[ 20.962594] systemd[1]: Created slice system-modprobe.slice.
10813 11:56:45.100085 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10814 11:56:45.118630 <30>[ 20.987574] systemd[1]: Created slice system-serial\x2dgetty.slice.
10815 11:56:45.128565 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10816 11:56:45.141001 <30>[ 21.010527] systemd[1]: Created slice User and Session Slice.
10817 11:56:45.147819 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10818 11:56:45.168449 <30>[ 21.034298] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10819 11:56:45.178069 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10820 11:56:45.196120 <30>[ 21.062220] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10821 11:56:45.202507 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10822 11:56:45.226857 <30>[ 21.089616] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10823 11:56:45.233643 <30>[ 21.101767] systemd[1]: Reached target Local Encrypted Volumes.
10824 11:56:45.240336 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10825 11:56:45.256335 <30>[ 21.125662] systemd[1]: Reached target Paths.
10826 11:56:45.259671 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10827 11:56:45.276272 <30>[ 21.145448] systemd[1]: Reached target Remote File Systems.
10828 11:56:45.282325 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10829 11:56:45.300282 <30>[ 21.169432] systemd[1]: Reached target Slices.
10830 11:56:45.303661 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10831 11:56:45.320038 <30>[ 21.189462] systemd[1]: Reached target Swap.
10832 11:56:45.323181 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10833 11:56:45.344094 <30>[ 21.209875] systemd[1]: Listening on initctl Compatibility Named Pipe.
10834 11:56:45.350538 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10835 11:56:45.356965 <30>[ 21.226084] systemd[1]: Listening on Journal Audit Socket.
10836 11:56:45.363826 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10837 11:56:45.381222 <30>[ 21.250953] systemd[1]: Listening on Journal Socket (/dev/log).
10838 11:56:45.387880 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10839 11:56:45.404366 <30>[ 21.274004] systemd[1]: Listening on Journal Socket.
10840 11:56:45.410833 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10841 11:56:45.428695 <30>[ 21.295173] systemd[1]: Listening on Network Service Netlink Socket.
10842 11:56:45.435406 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10843 11:56:45.451644 <30>[ 21.320706] systemd[1]: Listening on udev Control Socket.
10844 11:56:45.458119 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10845 11:56:45.472079 <30>[ 21.341894] systemd[1]: Listening on udev Kernel Socket.
10846 11:56:45.479264 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10847 11:56:45.528754 <30>[ 21.397971] systemd[1]: Mounting Huge Pages File System...
10848 11:56:45.535230 Mounting [0;1;39mHuge Pages File System[0m...
10849 11:56:45.550091 <30>[ 21.419746] systemd[1]: Mounting POSIX Message Queue File System...
10850 11:56:45.556681 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10851 11:56:45.574815 <30>[ 21.444622] systemd[1]: Mounting Kernel Debug File System...
10852 11:56:45.581826 Mounting [0;1;39mKernel Debug File System[0m...
10853 11:56:45.599902 <30>[ 21.465824] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10854 11:56:45.626102 <30>[ 21.492681] systemd[1]: Starting Create list of static device nodes for the current kernel...
10855 11:56:45.636150 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10856 11:56:45.651230 <30>[ 21.521017] systemd[1]: Starting Load Kernel Module configfs...
10857 11:56:45.657995 Starting [0;1;39mLoad Kernel Module configfs[0m...
10858 11:56:45.676995 <30>[ 21.546519] systemd[1]: Starting Load Kernel Module drm...
10859 11:56:45.683501 Starting [0;1;39mLoad Kernel Module drm[0m...
10860 11:56:45.700351 <30>[ 21.570096] systemd[1]: Starting Load Kernel Module fuse...
10861 11:56:45.706861 Starting [0;1;39mLoad Kernel Module fuse[0m...
10862 11:56:45.731090 <30>[ 21.597566] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10863 11:56:45.746650 <30>[ 21.616139] systemd[1]: Starting Journal Service...
10864 11:56:45.750209 <6>[ 21.616700] fuse: init (API version 7.37)
10865 11:56:45.756542 Starting [0;1;39mJournal Service[0m...
10866 11:56:45.790642 <30>[ 21.660410] systemd[1]: Starting Load Kernel Modules...
10867 11:56:45.797301 Starting [0;1;39mLoad Kernel Modules[0m...
10868 11:56:45.839915 <30>[ 21.706442] systemd[1]: Starting Remount Root and Kernel File Systems...
10869 11:56:45.847041 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10870 11:56:45.862417 <30>[ 21.732178] systemd[1]: Starting Coldplug All udev Devices...
10871 11:56:45.868918 Starting [0;1;39mColdplug All udev Devices[0m...
10872 11:56:45.886983 <30>[ 21.756344] systemd[1]: Mounted Huge Pages File System.
10873 11:56:45.897392 [[0;32m OK [<3>[ 21.763321] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10874 11:56:45.900614 0m] Mounted [0;1;39mHuge Pages File System[0m.
10875 11:56:45.916939 <30>[ 21.786098] systemd[1]: Mounted POSIX Message Queue File System.
10876 11:56:45.930369 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Messa<3>[ 21.796288] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 11:56:45.933514 ge Queue File System[0m.
10878 11:56:45.948449 <30>[ 21.817702] systemd[1]: Mounted Kernel Debug File System.
10879 11:56:45.954751 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10880 11:56:45.976659 <30>[ 21.842597] systemd[1]: Finished Create list of static device nodes for the current kernel.
10881 11:56:45.990218 [[0;32m OK [0m] Finished [0<3>[ 21.854364] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10882 11:56:45.993395 ;1;39mCreate list of st… nodes for the current kernel[0m.
10883 11:56:46.009530 <30>[ 21.879078] systemd[1]: modprobe@configfs.service: Succeeded.
10884 11:56:46.017005 <30>[ 21.886805] systemd[1]: Finished Load Kernel Module configfs.
10885 11:56:46.027616 <3>[ 21.890123] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10886 11:56:46.033334 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10887 11:56:46.049684 <30>[ 21.918634] systemd[1]: modprobe@drm.service: Succeeded.
10888 11:56:46.056677 <30>[ 21.925130] systemd[1]: Finished Load Kernel Module drm.
10889 11:56:46.065982 <3>[ 21.928532] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 11:56:46.069749 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10891 11:56:46.089378 <30>[ 21.959013] systemd[1]: modprobe@fuse.service: Succeeded.
10892 11:56:46.099257 <3>[ 21.962531] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10893 11:56:46.108176 <30>[ 21.966257] systemd[1]: Finished Load Kernel Module fuse.
10894 11:56:46.109369 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10895 11:56:46.125307 <30>[ 21.995302] systemd[1]: Finished Load Kernel Modules.
10896 11:56:46.135079 <3>[ 21.996652] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:56:46.141943 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10898 11:56:46.158211 <30>[ 22.027762] systemd[1]: Finished Remount Root and Kernel File Systems.
10899 11:56:46.169325 <3>[ 22.032722] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:56:46.174986 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10901 11:56:46.201042 <3>[ 22.067207] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10902 11:56:46.220573 <30>[ 22.090313] systemd[1]: Mounting FUSE Control File System...
10903 11:56:46.227915 Mounting [0;1;39mFUSE Control File System[0m...
10904 11:56:46.238022 <3>[ 22.103187] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10905 11:56:46.249593 <30>[ 22.115825] systemd[1]: Mounting Kernel Configuration File System...
10906 11:56:46.253135 Mounting [0;1;39mKernel Configuration File System[0m...
10907 11:56:46.277520 <30>[ 22.143612] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10908 11:56:46.287113 <30>[ 22.152654] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10909 11:56:46.329420 <30>[ 22.198494] systemd[1]: Starting Load/Save Random Seed...
10910 11:56:46.335447 Starting [0;1;39mLoad/Save Random Seed[0m...
10911 11:56:46.359523 <4>[ 22.219196] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10912 11:56:46.365557 <30>[ 22.220027] systemd[1]: Starting Apply Kernel Variables...
10913 11:56:46.373037 <3>[ 22.235057] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10914 11:56:46.379089 Starting [0;1;39mApply Kernel Variables[0m...
10915 11:56:46.432668 <30>[ 22.302435] systemd[1]: Starting Create System Users...
10916 11:56:46.439317 Starting [0;1;39mCreate System Users[0m...
10917 11:56:46.454721 <30>[ 22.324098] systemd[1]: Started Journal Service.
10918 11:56:46.461008 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10919 11:56:46.484141 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10920 11:56:46.495695 See 'systemctl status systemd-udev-trigger.service' for details.
10921 11:56:46.513097 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10922 11:56:46.527862 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10923 11:56:46.544894 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10924 11:56:46.560417 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10925 11:56:46.604945 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10926 11:56:46.625173 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10927 11:56:46.647739 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10928 11:56:46.671983 <46>[ 22.538341] systemd-journald[297]: Received client request to flush runtime journal.
10929 11:56:47.799428 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10930 11:56:47.815780 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10931 11:56:47.831073 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10932 11:56:47.884056 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10933 11:56:48.099795 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10934 11:56:48.137700 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10935 11:56:48.254150 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10936 11:56:48.313635 Starting [0;1;39mNetwork Service[0m...
10937 11:56:48.574548 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10938 11:56:48.597078 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10939 11:56:48.651862 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10940 11:56:48.954987 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10941 11:56:48.974658 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10942 11:56:49.020586 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10943 11:56:49.041302 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10944 11:56:49.062955 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10945 11:56:49.120431 Starting [0;1;39mNetwork Time Synchronization[0m...
10946 11:56:49.138563 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10947 11:56:49.155790 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10948 11:56:49.172007 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10949 11:56:49.249564 Starting [0;1;39mNetwork Name Resolution[0m...
10950 11:56:49.284710 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10951 11:56:49.327376 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10952 11:56:49.344034 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10953 11:56:49.363192 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10954 11:56:49.379687 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10955 11:56:49.395549 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10956 11:56:49.422162 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10957 11:56:49.446239 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10958 11:56:49.473079 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10959 11:56:49.497517 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10960 11:56:49.511336 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10961 11:56:49.532502 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10962 11:56:49.543637 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10963 11:56:49.559236 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10964 11:56:49.608499 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10965 11:56:49.775934 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10966 11:56:49.898363 Starting [0;1;39mUser Login Management[0m...
10967 11:56:50.181740 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10968 11:56:50.199793 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10969 11:56:50.227385 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10970 11:56:50.276111 Starting [0;1;39mPermit User Sessions[0m...
10971 11:56:50.298527 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10972 11:56:50.315264 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10973 11:56:50.366565 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10974 11:56:50.412940 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10975 11:56:50.427708 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10976 11:56:50.443840 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10977 11:56:50.461162 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10978 11:56:50.478679 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10979 11:56:50.528407 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10980 11:56:50.594344 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10981 11:56:50.675189
10982 11:56:50.675746
10983 11:56:50.678058 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10984 11:56:50.678546
10985 11:56:50.681242 debian-bullseye-arm64 login: root (automatic login)
10986 11:56:50.681734
10987 11:56:50.682132
10988 11:56:51.101347 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
10989 11:56:51.101856
10990 11:56:51.107821 The programs included with the Debian GNU/Linux system are free software;
10991 11:56:51.114291 the exact distribution terms for each program are described in the
10992 11:56:51.117418 individual files in /usr/share/doc/*/copyright.
10993 11:56:51.117887
10994 11:56:51.124390 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10995 11:56:51.127726 permitted by applicable law.
10996 11:56:52.201050 Matched prompt #10: / #
10998 11:56:52.202206 Setting prompt string to ['/ #']
10999 11:56:52.202669 end: 2.2.5.1 login-action (duration 00:00:29) [common]
11001 11:56:52.203653 end: 2.2.5 auto-login-action (duration 00:00:29) [common]
11002 11:56:52.204088 start: 2.2.6 expect-shell-connection (timeout 00:03:18) [common]
11003 11:56:52.204438 Setting prompt string to ['/ #']
11004 11:56:52.204747 Forcing a shell prompt, looking for ['/ #']
11006 11:56:52.255598 / #
11007 11:56:52.256257 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11008 11:56:52.256681 Waiting using forced prompt support (timeout 00:02:30)
11009 11:56:52.262275
11010 11:56:52.263224 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11011 11:56:52.263773 start: 2.2.7 export-device-env (timeout 00:03:18) [common]
11013 11:56:52.364986 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl'
11014 11:56:52.371010 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066552/extract-nfsrootfs-a7kvxpfl'
11016 11:56:52.472620 / # export NFS_SERVER_IP='192.168.201.1'
11017 11:56:52.479159 export NFS_SERVER_IP='192.168.201.1'
11018 11:56:52.480285 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11019 11:56:52.480883 end: 2.2 depthcharge-retry (duration 00:01:42) [common]
11020 11:56:52.481494 end: 2 depthcharge-action (duration 00:01:42) [common]
11021 11:56:52.482035 start: 3 lava-test-retry (timeout 00:07:37) [common]
11022 11:56:52.482506 start: 3.1 lava-test-shell (timeout 00:07:37) [common]
11023 11:56:52.482907 Using namespace: common
11025 11:56:52.584172 / # #
11026 11:56:52.584825 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11027 11:56:52.590968 #
11028 11:56:52.591894 Using /lava-12066552
11030 11:56:52.693078 / # export SHELL=/bin/bash
11031 11:56:52.699919 export SHELL=/bin/bash
11033 11:56:52.801854 / # . /lava-12066552/environment
11034 11:56:52.808977 . /lava-12066552/environment
11036 11:56:52.917348 / # /lava-12066552/bin/lava-test-runner /lava-12066552/0
11037 11:56:52.917993 Test shell timeout: 10s (minimum of the action and connection timeout)
11038 11:56:52.924368 /lava-12066552/bin/lava-test-runner /lava-12066552/0
11039 11:56:53.279319 + export TESTRUN_ID=0_timesync-off
11040 11:56:53.282799 + TESTRUN_ID=0_timesync-off
11041 11:56:53.285836 + cd /lava-12066552/0/tests/0_timesync-off
11042 11:56:53.289140 ++ cat uuid
11043 11:56:53.297798 + UUID=12066552_1.6.2.3.1
11044 11:56:53.298320 + set +x
11045 11:56:53.304228 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12066552_1.6.2.3.1>
11046 11:56:53.304950 Received signal: <STARTRUN> 0_timesync-off 12066552_1.6.2.3.1
11047 11:56:53.305417 Starting test lava.0_timesync-off (12066552_1.6.2.3.1)
11048 11:56:53.306016 Skipping test definition patterns.
11049 11:56:53.307489 + systemctl stop systemd-timesyncd
11050 11:56:53.363441 + set +x
11051 11:56:53.367014 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12066552_1.6.2.3.1>
11052 11:56:53.367697 Received signal: <ENDRUN> 0_timesync-off 12066552_1.6.2.3.1
11053 11:56:53.368137 Ending use of test pattern.
11054 11:56:53.368487 Ending test lava.0_timesync-off (12066552_1.6.2.3.1), duration 0.06
11056 11:56:53.473015 + export TESTRUN_ID=1_kselftest-rtc
11057 11:56:53.476314 + TESTRUN_ID=1_kselftest-rtc
11058 11:56:53.479543 + cd /lava-12066552/0/tests/1_kselftest-rtc
11059 11:56:53.482737 ++ cat uuid
11060 11:56:53.492639 + UUID=12066552_1.6.2.3.5
11061 11:56:53.493068 + set +x
11062 11:56:53.499503 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 12066552_1.6.2.3.5>
11063 11:56:53.500185 Received signal: <STARTRUN> 1_kselftest-rtc 12066552_1.6.2.3.5
11064 11:56:53.500548 Starting test lava.1_kselftest-rtc (12066552_1.6.2.3.5)
11065 11:56:53.500945 Skipping test definition patterns.
11066 11:56:53.502354 + cd ./automated/linux/kselftest/
11067 11:56:53.528407 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11068 11:56:53.592214 INFO: install_deps skipped
11069 11:56:53.728460 --2023-11-23 11:56:53-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11070 11:56:53.753104 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11071 11:56:53.887234 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11072 11:56:54.020314 HTTP request sent, awaiting response... 200 OK
11073 11:56:54.023601 Length: 2962844 (2.8M) [application/octet-stream]
11074 11:56:54.026804 Saving to: 'kselftest.tar.xz'
11075 11:56:54.027284
11076 11:56:54.027608
11077 11:56:54.287776 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11078 11:56:54.555499 kselftest.tar.xz 1%[ ] 47.81K 176KB/s
11079 11:56:54.870724 kselftest.tar.xz 7%[> ] 219.84K 403KB/s
11080 11:56:55.148527 kselftest.tar.xz 27%[====> ] 793.02K 913KB/s
11081 11:56:55.359247 kselftest.tar.xz 63%[===========> ] 1.80M 1.57MB/s
11082 11:56:55.380583 kselftest.tar.xz 95%[==================> ] 2.71M 1.98MB/s
11083 11:56:55.386723 kselftest.tar.xz 100%[===================>] 2.83M 2.03MB/s in 1.4s
11084 11:56:55.387305
11085 11:56:55.645832 2023-11-23 11:56:55 (2.03 MB/s) - 'kselftest.tar.xz' saved [2962844/2962844]
11086 11:56:55.646378
11087 11:57:03.167857 skiplist:
11088 11:57:03.170755 ========================================
11089 11:57:03.174133 ========================================
11090 11:57:03.242991 rtc:rtctest
11091 11:57:03.269281 ============== Tests to run ===============
11092 11:57:03.272649 rtc:rtctest
11093 11:57:03.276048 ===========End Tests to run ===============
11094 11:57:03.281137 shardfile-rtc pass
11095 11:57:03.405044 <12>[ 39.276804] kselftest: Running tests in rtc
11096 11:57:03.418979 TAP version 13
11097 11:57:03.434835 1..1
11098 11:57:03.473654 # selftests: rtc: rtctest
11099 11:57:03.958748 # TAP version 13
11100 11:57:03.959263 # 1..8
11101 11:57:03.961897 # # Starting 8 tests from 2 test cases.
11102 11:57:03.965339 # # RUN rtc.date_read ...
11103 11:57:03.972259 # # rtctest.c:49:date_read:Current RTC date/time is 23/11/2023 11:57:03.
11104 11:57:03.974872 # # OK rtc.date_read
11105 11:57:03.978922 # ok 1 rtc.date_read
11106 11:57:03.981738 # # RUN rtc.date_read_loop ...
11107 11:57:03.992072 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11108 11:57:10.006332 <6>[ 45.882220] vpu: disabling
11109 11:57:10.009701 <6>[ 45.885322] vproc2: disabling
11110 11:57:10.013564 <6>[ 45.889265] vproc1: disabling
11111 11:57:10.017722 <6>[ 45.893600] vaud18: disabling
11112 11:57:10.025405 <6>[ 45.897342] vsram_others: disabling
11113 11:57:10.028366 <6>[ 45.901564] va09: disabling
11114 11:57:10.031703 <6>[ 45.904966] vsram_md: disabling
11115 11:57:10.034372 <6>[ 45.908762] Vgpu: disabling
11116 11:57:34.283676 # # rtctest.c:115:date_read_loop:Performed 2685 RTC time reads.
11117 11:57:34.286686 # # OK rtc.date_read_loop
11118 11:57:34.290084 # ok 2 rtc.date_read_loop
11119 11:57:34.293285 # # RUN rtc.uie_read ...
11120 11:57:37.262424 # # OK rtc.uie_read
11121 11:57:37.265337 # ok 3 rtc.uie_read
11122 11:57:37.268488 # # RUN rtc.uie_select ...
11123 11:57:40.261849 # # OK rtc.uie_select
11124 11:57:40.264788 # ok 4 rtc.uie_select
11125 11:57:40.268732 # # RUN rtc.alarm_alm_set ...
11126 11:57:40.275148 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 11:57:43.
11127 11:57:40.278343 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11128 11:57:40.285018 # # alarm_alm_set: Test terminated by assertion
11129 11:57:40.288176 # # FAIL rtc.alarm_alm_set
11130 11:57:40.291533 # not ok 5 rtc.alarm_alm_set
11131 11:57:40.294577 # # RUN rtc.alarm_wkalm_set ...
11132 11:57:40.301950 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 23/11/2023 11:57:43.
11133 11:57:43.264586 # # OK rtc.alarm_wkalm_set
11134 11:57:43.265147 # ok 6 rtc.alarm_wkalm_set
11135 11:57:43.271794 # # RUN rtc.alarm_alm_set_minute ...
11136 11:57:43.274391 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 11:58:00.
11137 11:57:43.281344 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11138 11:57:43.287820 # # alarm_alm_set_minute: Test terminated by assertion
11139 11:57:43.291479 # # FAIL rtc.alarm_alm_set_minute
11140 11:57:43.294944 # not ok 7 rtc.alarm_alm_set_minute
11141 11:57:43.297661 # # RUN rtc.alarm_wkalm_set_minute ...
11142 11:57:43.304229 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 23/11/2023 11:58:00.
11143 11:58:00.263330 # # OK rtc.alarm_wkalm_set_minute
11144 11:58:00.265753 # ok 8 rtc.alarm_wkalm_set_minute
11145 11:58:00.269325 # # FAILED: 6 / 8 tests passed.
11146 11:58:00.272354 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11147 11:58:00.275779 not ok 1 selftests: rtc: rtctest # exit=1
11148 11:58:00.949013 rtc_rtctest_rtc_date_read pass
11149 11:58:00.952066 rtc_rtctest_rtc_date_read_loop pass
11150 11:58:00.955174 rtc_rtctest_rtc_uie_read pass
11151 11:58:00.958780 rtc_rtctest_rtc_uie_select pass
11152 11:58:00.961777 rtc_rtctest_rtc_alarm_alm_set fail
11153 11:58:00.965152 rtc_rtctest_rtc_alarm_wkalm_set pass
11154 11:58:00.968419 rtc_rtctest_rtc_alarm_alm_set_minute fail
11155 11:58:00.971556 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11156 11:58:00.974672 rtc_rtctest fail
11157 11:58:00.982777 + ../../utils/send-to-lava.sh ./output/result.txt
11158 11:58:01.087560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-rtc RESULT=pass>
11159 11:58:01.088398 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-rtc RESULT=pass
11161 11:58:01.165019 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11162 11:58:01.165784 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11164 11:58:01.247338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11165 11:58:01.248214 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11167 11:58:01.318091 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11168 11:58:01.318988 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11170 11:58:01.397844 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11171 11:58:01.398640 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11173 11:58:01.476022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11174 11:58:01.476811 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11176 11:58:01.554044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11177 11:58:01.554982 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11179 11:58:01.632286 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11180 11:58:01.633075 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11182 11:58:01.708998 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11183 11:58:01.709772 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11185 11:58:01.782575 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11186 11:58:01.783098 + set +x
11187 11:58:01.783702 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11189 11:58:01.788760 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 12066552_1.6.2.3.5>
11190 11:58:01.789554 Received signal: <ENDRUN> 1_kselftest-rtc 12066552_1.6.2.3.5
11191 11:58:01.789940 Ending use of test pattern.
11192 11:58:01.790294 Ending test lava.1_kselftest-rtc (12066552_1.6.2.3.5), duration 68.29
11194 11:58:01.791409 ok: lava_test_shell seems to have completed
11195 11:58:01.792087 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
shardfile-rtc: pass
11196 11:58:01.792516 end: 3.1 lava-test-shell (duration 00:01:09) [common]
11197 11:58:01.792937 end: 3 lava-test-retry (duration 00:01:09) [common]
11198 11:58:01.793362 start: 4 finalize (timeout 00:06:28) [common]
11199 11:58:01.793818 start: 4.1 power-off (timeout 00:00:30) [common]
11200 11:58:01.794617 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11201 11:58:01.874227 >> Command sent successfully.
11202 11:58:01.878038 Returned 0 in 0 seconds
11203 11:58:01.978980 end: 4.1 power-off (duration 00:00:00) [common]
11205 11:58:01.980553 start: 4.2 read-feedback (timeout 00:06:27) [common]
11207 11:58:01.982861 Listened to connection for namespace 'common' for up to 1s
11208 11:58:02.982472 Finalising connection for namespace 'common'
11209 11:58:02.983164 Disconnecting from shell: Finalise
11210 11:58:02.983582 / #
11211 11:58:03.084609 end: 4.2 read-feedback (duration 00:00:01) [common]
11212 11:58:03.085345 end: 4 finalize (duration 00:00:01) [common]
11213 11:58:03.085949 Cleaning after the job
11214 11:58:03.086551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/ramdisk
11215 11:58:03.101149 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/kernel
11216 11:58:03.135278 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/dtb
11217 11:58:03.135556 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/nfsrootfs
11218 11:58:03.227533 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066552/tftp-deploy-2cwi2ezc/modules
11219 11:58:03.234868 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066552
11220 11:58:03.866984 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066552
11221 11:58:03.867170 Job finished correctly