Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 38
- Kernel Warnings: 27
- Boot result: PASS
- Errors: 0
1 11:50:28.034113 lava-dispatcher, installed at version: 2023.10
2 11:50:28.034379 start: 0 validate
3 11:50:28.034511 Start time: 2023-11-23 11:50:28.034503+00:00 (UTC)
4 11:50:28.034630 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:50:28.034758 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:50:28.305103 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:50:28.305776 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:51:05.310962 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:51:05.311170 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:51:05.576892 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:51:05.577089 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:51:05.843287 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:51:05.843464 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:51:07.848933 validate duration: 39.81
16 11:51:07.849215 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:51:07.849326 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:51:07.849429 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:51:07.849565 Not decompressing ramdisk as can be used compressed.
20 11:51:07.849661 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 11:51:07.849734 saving as /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/ramdisk/initrd.cpio.gz
22 11:51:07.849809 total size: 4665395 (4 MB)
23 11:51:08.118726 progress 0 % (0 MB)
24 11:51:08.120168 progress 5 % (0 MB)
25 11:51:08.121441 progress 10 % (0 MB)
26 11:51:08.122854 progress 15 % (0 MB)
27 11:51:08.124096 progress 20 % (0 MB)
28 11:51:08.125370 progress 25 % (1 MB)
29 11:51:08.126698 progress 30 % (1 MB)
30 11:51:08.128271 progress 35 % (1 MB)
31 11:51:08.129539 progress 40 % (1 MB)
32 11:51:08.131225 progress 45 % (2 MB)
33 11:51:08.132501 progress 50 % (2 MB)
34 11:51:08.133773 progress 55 % (2 MB)
35 11:51:08.135041 progress 60 % (2 MB)
36 11:51:08.136269 progress 65 % (2 MB)
37 11:51:08.137492 progress 70 % (3 MB)
38 11:51:08.138753 progress 75 % (3 MB)
39 11:51:08.139978 progress 80 % (3 MB)
40 11:51:08.141371 progress 85 % (3 MB)
41 11:51:08.142639 progress 90 % (4 MB)
42 11:51:08.143867 progress 95 % (4 MB)
43 11:51:08.145111 progress 100 % (4 MB)
44 11:51:08.145297 4 MB downloaded in 0.30 s (15.06 MB/s)
45 11:51:08.145450 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:51:08.145722 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:51:08.145810 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:51:08.145894 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:51:08.146033 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:51:08.146106 saving as /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/kernel/Image
52 11:51:08.146168 total size: 49107456 (46 MB)
53 11:51:08.146229 No compression specified
54 11:51:08.147387 progress 0 % (0 MB)
55 11:51:08.160244 progress 5 % (2 MB)
56 11:51:08.173447 progress 10 % (4 MB)
57 11:51:08.187645 progress 15 % (7 MB)
58 11:51:08.201339 progress 20 % (9 MB)
59 11:51:08.214452 progress 25 % (11 MB)
60 11:51:08.227422 progress 30 % (14 MB)
61 11:51:08.240443 progress 35 % (16 MB)
62 11:51:08.253381 progress 40 % (18 MB)
63 11:51:08.266585 progress 45 % (21 MB)
64 11:51:08.280346 progress 50 % (23 MB)
65 11:51:08.294028 progress 55 % (25 MB)
66 11:51:08.307935 progress 60 % (28 MB)
67 11:51:08.321734 progress 65 % (30 MB)
68 11:51:08.335658 progress 70 % (32 MB)
69 11:51:08.349400 progress 75 % (35 MB)
70 11:51:08.363488 progress 80 % (37 MB)
71 11:51:08.377436 progress 85 % (39 MB)
72 11:51:08.391369 progress 90 % (42 MB)
73 11:51:08.405184 progress 95 % (44 MB)
74 11:51:08.418535 progress 100 % (46 MB)
75 11:51:08.418806 46 MB downloaded in 0.27 s (171.78 MB/s)
76 11:51:08.418968 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:51:08.419211 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:51:08.419301 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:51:08.419392 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:51:08.419537 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:51:08.419609 saving as /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/dtb/mt8192-asurada-spherion-r0.dtb
83 11:51:08.419673 total size: 47278 (0 MB)
84 11:51:08.419737 No compression specified
85 11:51:08.420910 progress 69 % (0 MB)
86 11:51:08.421195 progress 100 % (0 MB)
87 11:51:08.421356 0 MB downloaded in 0.00 s (26.83 MB/s)
88 11:51:08.421484 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:51:08.421715 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:51:08.421806 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:51:08.421894 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:51:08.422013 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 11:51:08.422083 saving as /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/nfsrootfs/full.rootfs.tar
95 11:51:08.422149 total size: 200813988 (191 MB)
96 11:51:08.422213 Using unxz to decompress xz
97 11:51:08.426407 progress 0 % (0 MB)
98 11:51:08.986155 progress 5 % (9 MB)
99 11:51:09.531948 progress 10 % (19 MB)
100 11:51:10.148584 progress 15 % (28 MB)
101 11:51:10.544617 progress 20 % (38 MB)
102 11:51:10.879583 progress 25 % (47 MB)
103 11:51:11.493673 progress 30 % (57 MB)
104 11:51:12.074489 progress 35 % (67 MB)
105 11:51:12.708431 progress 40 % (76 MB)
106 11:51:13.304024 progress 45 % (86 MB)
107 11:51:13.906855 progress 50 % (95 MB)
108 11:51:14.553342 progress 55 % (105 MB)
109 11:51:15.253063 progress 60 % (114 MB)
110 11:51:15.399944 progress 65 % (124 MB)
111 11:51:15.561020 progress 70 % (134 MB)
112 11:51:15.684336 progress 75 % (143 MB)
113 11:51:15.769855 progress 80 % (153 MB)
114 11:51:15.869556 progress 85 % (162 MB)
115 11:51:15.992521 progress 90 % (172 MB)
116 11:51:16.288597 progress 95 % (181 MB)
117 11:51:16.907876 progress 100 % (191 MB)
118 11:51:16.913137 191 MB downloaded in 8.49 s (22.55 MB/s)
119 11:51:16.913561 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:51:16.913967 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:51:16.914096 start: 1.5 download-retry (timeout 00:09:51) [common]
123 11:51:16.914222 start: 1.5.1 http-download (timeout 00:09:51) [common]
124 11:51:16.914457 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:51:16.914566 saving as /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/modules/modules.tar
126 11:51:16.914662 total size: 8621364 (8 MB)
127 11:51:16.914760 Using unxz to decompress xz
128 11:51:17.185169 progress 0 % (0 MB)
129 11:51:17.215246 progress 5 % (0 MB)
130 11:51:17.244397 progress 10 % (0 MB)
131 11:51:17.271134 progress 15 % (1 MB)
132 11:51:17.296883 progress 20 % (1 MB)
133 11:51:17.321731 progress 25 % (2 MB)
134 11:51:17.348466 progress 30 % (2 MB)
135 11:51:17.375967 progress 35 % (2 MB)
136 11:51:17.401444 progress 40 % (3 MB)
137 11:51:17.428187 progress 45 % (3 MB)
138 11:51:17.455868 progress 50 % (4 MB)
139 11:51:17.482522 progress 55 % (4 MB)
140 11:51:17.510007 progress 60 % (4 MB)
141 11:51:17.540158 progress 65 % (5 MB)
142 11:51:17.567466 progress 70 % (5 MB)
143 11:51:17.592907 progress 75 % (6 MB)
144 11:51:17.620797 progress 80 % (6 MB)
145 11:51:17.647673 progress 85 % (7 MB)
146 11:51:17.673849 progress 90 % (7 MB)
147 11:51:17.704808 progress 95 % (7 MB)
148 11:51:17.737104 progress 100 % (8 MB)
149 11:51:17.742075 8 MB downloaded in 0.83 s (9.94 MB/s)
150 11:51:17.742430 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:51:17.742719 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:51:17.742820 start: 1.6 prepare-tftp-overlay (timeout 00:09:50) [common]
154 11:51:17.742919 start: 1.6.1 extract-nfsrootfs (timeout 00:09:50) [common]
155 11:51:21.389862 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn
156 11:51:21.390089 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 11:51:21.390199 start: 1.6.2 lava-overlay (timeout 00:09:46) [common]
158 11:51:21.390780 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj
159 11:51:21.390923 makedir: /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin
160 11:51:21.391035 makedir: /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/tests
161 11:51:21.391156 makedir: /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/results
162 11:51:21.391292 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-add-keys
163 11:51:21.391509 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-add-sources
164 11:51:21.391650 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-background-process-start
165 11:51:21.391784 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-background-process-stop
166 11:51:21.391914 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-common-functions
167 11:51:21.392050 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-echo-ipv4
168 11:51:21.392180 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-install-packages
169 11:51:21.392308 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-installed-packages
170 11:51:21.392436 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-os-build
171 11:51:21.392565 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-probe-channel
172 11:51:21.392695 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-probe-ip
173 11:51:21.392822 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-target-ip
174 11:51:21.392950 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-target-mac
175 11:51:21.393077 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-target-storage
176 11:51:21.393206 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-case
177 11:51:21.393336 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-event
178 11:51:21.393461 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-feedback
179 11:51:21.393587 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-raise
180 11:51:21.393714 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-reference
181 11:51:21.393847 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-runner
182 11:51:21.393974 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-set
183 11:51:21.394109 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-test-shell
184 11:51:21.394238 Updating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-add-keys (debian)
185 11:51:21.394447 Updating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-add-sources (debian)
186 11:51:21.394604 Updating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-install-packages (debian)
187 11:51:21.394805 Updating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-installed-packages (debian)
188 11:51:21.394955 Updating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/bin/lava-os-build (debian)
189 11:51:21.395080 Creating /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/environment
190 11:51:21.395185 LAVA metadata
191 11:51:21.395258 - LAVA_JOB_ID=12066519
192 11:51:21.395324 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:51:21.395443 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:46) [common]
194 11:51:21.395512 skipped lava-vland-overlay
195 11:51:21.395591 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:51:21.395674 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:46) [common]
197 11:51:21.395737 skipped lava-multinode-overlay
198 11:51:21.395810 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:51:21.395889 start: 1.6.2.3 test-definition (timeout 00:09:46) [common]
200 11:51:21.395967 Loading test definitions
201 11:51:21.396061 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:46) [common]
202 11:51:21.396133 Using /lava-12066519 at stage 0
203 11:51:21.396431 uuid=12066519_1.6.2.3.1 testdef=None
204 11:51:21.396522 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:51:21.396609 start: 1.6.2.3.2 test-overlay (timeout 00:09:46) [common]
206 11:51:21.397073 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:51:21.397298 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:46) [common]
209 11:51:21.397933 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:51:21.398168 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:46) [common]
212 11:51:21.398941 runner path: /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/0/tests/0_timesync-off test_uuid 12066519_1.6.2.3.1
213 11:51:21.399104 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:51:21.399334 start: 1.6.2.3.5 git-repo-action (timeout 00:09:46) [common]
216 11:51:21.399410 Using /lava-12066519 at stage 0
217 11:51:21.399512 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:51:21.399594 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/0/tests/1_kselftest-tpm2'
219 11:51:30.514886 Running '/usr/bin/git checkout kernelci.org
220 11:51:30.665859 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:51:30.666647 uuid=12066519_1.6.2.3.5 testdef=None
222 11:51:30.666816 end: 1.6.2.3.5 git-repo-action (duration 00:00:09) [common]
224 11:51:30.667074 start: 1.6.2.3.6 test-overlay (timeout 00:09:37) [common]
225 11:51:30.667843 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:51:30.668082 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:37) [common]
228 11:51:30.669061 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:51:30.669300 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:37) [common]
231 11:51:30.670241 runner path: /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/0/tests/1_kselftest-tpm2 test_uuid 12066519_1.6.2.3.5
232 11:51:30.670382 BOARD='mt8192-asurada-spherion-r0'
233 11:51:30.670449 BRANCH='cip-gitlab'
234 11:51:30.670511 SKIPFILE='/dev/null'
235 11:51:30.670626 SKIP_INSTALL='True'
236 11:51:30.670696 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:51:30.670756 TST_CASENAME=''
238 11:51:30.670811 TST_CMDFILES='tpm2'
239 11:51:30.670956 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:51:30.671166 Creating lava-test-runner.conf files
242 11:51:30.671231 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066519/lava-overlay-snzdubgj/lava-12066519/0 for stage 0
243 11:51:30.671329 - 0_timesync-off
244 11:51:30.671398 - 1_kselftest-tpm2
245 11:51:30.671495 end: 1.6.2.3 test-definition (duration 00:00:09) [common]
246 11:51:30.671588 start: 1.6.2.4 compress-overlay (timeout 00:09:37) [common]
247 11:51:38.245856 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:51:38.246058 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:30) [common]
249 11:51:38.246153 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:51:38.246337 end: 1.6.2 lava-overlay (duration 00:00:17) [common]
251 11:51:38.246439 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:30) [common]
252 11:51:38.366589 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:51:38.366979 start: 1.6.4 extract-modules (timeout 00:09:29) [common]
254 11:51:38.367100 extracting modules file /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn
255 11:51:38.589195 extracting modules file /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066519/extract-overlay-ramdisk-_6hb5nju/ramdisk
256 11:51:38.817545 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:51:38.817715 start: 1.6.5 apply-overlay-tftp (timeout 00:09:29) [common]
258 11:51:38.817812 [common] Applying overlay to NFS
259 11:51:38.817886 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066519/compress-overlay-regg8ylz/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn
260 11:51:39.834356 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:51:39.834548 start: 1.6.6 configure-preseed-file (timeout 00:09:28) [common]
262 11:51:39.834668 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:51:39.834786 start: 1.6.7 compress-ramdisk (timeout 00:09:28) [common]
264 11:51:39.834884 Building ramdisk /var/lib/lava/dispatcher/tmp/12066519/extract-overlay-ramdisk-_6hb5nju/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066519/extract-overlay-ramdisk-_6hb5nju/ramdisk
265 11:51:40.208214 >> 119398 blocks
266 11:51:42.200917 rename /var/lib/lava/dispatcher/tmp/12066519/extract-overlay-ramdisk-_6hb5nju/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/ramdisk/ramdisk.cpio.gz
267 11:51:42.201359 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:51:42.201489 start: 1.6.8 prepare-kernel (timeout 00:09:26) [common]
269 11:51:42.201597 start: 1.6.8.1 prepare-fit (timeout 00:09:26) [common]
270 11:51:42.201719 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/kernel/Image'
271 11:51:55.949520 Returned 0 in 13 seconds
272 11:51:56.050190 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/kernel/image.itb
273 11:51:56.439305 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:51:56.439699 output: Created: Thu Nov 23 11:51:56 2023
275 11:51:56.439806 output: Image 0 (kernel-1)
276 11:51:56.439900 output: Description:
277 11:51:56.439994 output: Created: Thu Nov 23 11:51:56 2023
278 11:51:56.440081 output: Type: Kernel Image
279 11:51:56.440168 output: Compression: lzma compressed
280 11:51:56.440259 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
281 11:51:56.440364 output: Architecture: AArch64
282 11:51:56.440479 output: OS: Linux
283 11:51:56.440580 output: Load Address: 0x00000000
284 11:51:56.440685 output: Entry Point: 0x00000000
285 11:51:56.440792 output: Hash algo: crc32
286 11:51:56.440892 output: Hash value: e6d7c86f
287 11:51:56.441001 output: Image 1 (fdt-1)
288 11:51:56.441102 output: Description: mt8192-asurada-spherion-r0
289 11:51:56.441206 output: Created: Thu Nov 23 11:51:56 2023
290 11:51:56.441307 output: Type: Flat Device Tree
291 11:51:56.441404 output: Compression: uncompressed
292 11:51:56.441510 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 11:51:56.441609 output: Architecture: AArch64
294 11:51:56.441711 output: Hash algo: crc32
295 11:51:56.441810 output: Hash value: cc4352de
296 11:51:56.441906 output: Image 2 (ramdisk-1)
297 11:51:56.442008 output: Description: unavailable
298 11:51:56.442109 output: Created: Thu Nov 23 11:51:56 2023
299 11:51:56.442221 output: Type: RAMDisk Image
300 11:51:56.442322 output: Compression: Unknown Compression
301 11:51:56.442403 output: Data Size: 17793381 Bytes = 17376.35 KiB = 16.97 MiB
302 11:51:56.442507 output: Architecture: AArch64
303 11:51:56.442589 output: OS: Linux
304 11:51:56.442693 output: Load Address: unavailable
305 11:51:56.442791 output: Entry Point: unavailable
306 11:51:56.442890 output: Hash algo: crc32
307 11:51:56.442993 output: Hash value: cbc157a1
308 11:51:56.443089 output: Default Configuration: 'conf-1'
309 11:51:56.443190 output: Configuration 0 (conf-1)
310 11:51:56.443294 output: Description: mt8192-asurada-spherion-r0
311 11:51:56.443390 output: Kernel: kernel-1
312 11:51:56.443495 output: Init Ramdisk: ramdisk-1
313 11:51:56.443591 output: FDT: fdt-1
314 11:51:56.443687 output: Loadables: kernel-1
315 11:51:56.443793 output:
316 11:51:56.444066 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
317 11:51:56.444223 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
318 11:51:56.444387 end: 1.6 prepare-tftp-overlay (duration 00:00:39) [common]
319 11:51:56.444540 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:11) [common]
320 11:51:56.444672 No LXC device requested
321 11:51:56.444807 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:51:56.444958 start: 1.8 deploy-device-env (timeout 00:09:11) [common]
323 11:51:56.445086 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:51:56.445213 Checking files for TFTP limit of 4294967296 bytes.
325 11:51:56.445924 end: 1 tftp-deploy (duration 00:00:49) [common]
326 11:51:56.446081 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:51:56.446248 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:51:56.446415 substitutions:
329 11:51:56.446530 - {DTB}: 12066519/tftp-deploy-6030xfpe/dtb/mt8192-asurada-spherion-r0.dtb
330 11:51:56.446638 - {INITRD}: 12066519/tftp-deploy-6030xfpe/ramdisk/ramdisk.cpio.gz
331 11:51:56.446750 - {KERNEL}: 12066519/tftp-deploy-6030xfpe/kernel/Image
332 11:51:56.446855 - {LAVA_MAC}: None
333 11:51:56.446962 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn
334 11:51:56.447067 - {NFS_SERVER_IP}: 192.168.201.1
335 11:51:56.447166 - {PRESEED_CONFIG}: None
336 11:51:56.447275 - {PRESEED_LOCAL}: None
337 11:51:56.447374 - {RAMDISK}: 12066519/tftp-deploy-6030xfpe/ramdisk/ramdisk.cpio.gz
338 11:51:56.447480 - {ROOT_PART}: None
339 11:51:56.447583 - {ROOT}: None
340 11:51:56.447682 - {SERVER_IP}: 192.168.201.1
341 11:51:56.447789 - {TEE}: None
342 11:51:56.447887 Parsed boot commands:
343 11:51:56.447989 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:51:56.448253 Parsed boot commands: tftpboot 192.168.201.1 12066519/tftp-deploy-6030xfpe/kernel/image.itb 12066519/tftp-deploy-6030xfpe/kernel/cmdline
345 11:51:56.448387 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:51:56.448531 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:51:56.448678 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:51:56.448824 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:51:56.448944 Not connected, no need to disconnect.
350 11:51:56.449069 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:51:56.449214 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:51:56.449325 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-2'
353 11:51:56.453894 Setting prompt string to ['lava-test: # ']
354 11:51:56.454355 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:51:56.454498 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:51:56.454622 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:51:56.454738 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:51:56.455078 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
359 11:52:01.589600 >> Command sent successfully.
360 11:52:01.592085 Returned 0 in 5 seconds
361 11:52:01.692451 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:52:01.692773 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:52:01.692881 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:52:01.692977 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:52:01.693048 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:52:01.693119 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:52:01.693387 [Enter `^Ec?' for help]
369 11:52:01.867117
370 11:52:01.867264
371 11:52:01.867360 F0: 102B 0000
372 11:52:01.867450
373 11:52:01.867511 F3: 1001 0000 [0200]
374 11:52:01.870320
375 11:52:01.870431 F3: 1001 0000
376 11:52:01.870529
377 11:52:01.870626 F7: 102D 0000
378 11:52:01.870716
379 11:52:01.873062 F1: 0000 0000
380 11:52:01.873161
381 11:52:01.873261 V0: 0000 0000 [0001]
382 11:52:01.873359
383 11:52:01.876569 00: 0007 8000
384 11:52:01.876662
385 11:52:01.876732 01: 0000 0000
386 11:52:01.876800
387 11:52:01.879973 BP: 0C00 0209 [0000]
388 11:52:01.880085
389 11:52:01.880189 G0: 1182 0000
390 11:52:01.880287
391 11:52:01.883825 EC: 0000 0021 [4000]
392 11:52:01.883910
393 11:52:01.883982 S7: 0000 0000 [0000]
394 11:52:01.884045
395 11:52:01.887275 CC: 0000 0000 [0001]
396 11:52:01.887355
397 11:52:01.887420 T0: 0000 0040 [010F]
398 11:52:01.887485
399 11:52:01.887546 Jump to BL
400 11:52:01.887606
401 11:52:01.914311
402 11:52:01.914414
403 11:52:01.914484
404 11:52:01.921592 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:52:01.925364 ARM64: Exception handlers installed.
406 11:52:01.929002 ARM64: Testing exception
407 11:52:01.931757 ARM64: Done test exception
408 11:52:01.938851 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:52:01.948686 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:52:01.955780 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:52:01.965480 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:52:01.972392 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:52:01.978775 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:52:01.990369 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:52:01.997092 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:52:02.016409 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:52:02.019949 WDT: Last reset was cold boot
418 11:52:02.023388 SPI1(PAD0) initialized at 2873684 Hz
419 11:52:02.026353 SPI5(PAD0) initialized at 992727 Hz
420 11:52:02.029963 VBOOT: Loading verstage.
421 11:52:02.036925 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:52:02.039855 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:52:02.043414 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:52:02.046165 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:52:02.054606 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:52:02.060554 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:52:02.071410 read SPI 0x96554 0xa1eb: 4593 us, 9024 KB/s, 72.192 Mbps
428 11:52:02.071510
429 11:52:02.071600
430 11:52:02.081284 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:52:02.084735 ARM64: Exception handlers installed.
432 11:52:02.088297 ARM64: Testing exception
433 11:52:02.088384 ARM64: Done test exception
434 11:52:02.095421 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:52:02.098923 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:52:02.112398 Probing TPM: . done!
437 11:52:02.112547 TPM ready after 0 ms
438 11:52:02.121373 Connected to device vid:did:rid of 1ae0:0028:00
439 11:52:02.127903 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 11:52:02.184240 Initialized TPM device CR50 revision 0
441 11:52:02.195676 tlcl_send_startup: Startup return code is 0
442 11:52:02.195798 TPM: setup succeeded
443 11:52:02.206952 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:52:02.216357 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:52:02.227474 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:52:02.236562 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:52:02.240050 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:52:02.247683 in-header: 03 07 00 00 08 00 00 00
449 11:52:02.251145 in-data: aa e4 47 04 13 02 00 00
450 11:52:02.255111 Chrome EC: UHEPI supported
451 11:52:02.262161 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:52:02.265303 in-header: 03 95 00 00 08 00 00 00
453 11:52:02.269168 in-data: 18 20 20 08 00 00 00 00
454 11:52:02.269252 Phase 1
455 11:52:02.272883 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:52:02.280384 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:52:02.284624 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:52:02.287820 Recovery requested (1009000e)
459 11:52:02.296111 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:52:02.301901 tlcl_extend: response is 0
461 11:52:02.310832 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:52:02.316678 tlcl_extend: response is 0
463 11:52:02.323887 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:52:02.343735 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
465 11:52:02.350219 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:52:02.350360
467 11:52:02.350429
468 11:52:02.359943 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:52:02.363710 ARM64: Exception handlers installed.
470 11:52:02.366189 ARM64: Testing exception
471 11:52:02.366336 ARM64: Done test exception
472 11:52:02.388768 pmic_efuse_setting: Set efuses in 11 msecs
473 11:52:02.392049 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:52:02.398547 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:52:02.402509 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:52:02.409100 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:52:02.412497 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:52:02.416469 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:52:02.423195 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:52:02.427214 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:52:02.431191 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:52:02.434766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:52:02.442422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:52:02.445980 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:52:02.449464 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:52:02.456548 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:52:02.460196 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:52:02.467724 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:52:02.471143 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:52:02.478565 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:52:02.485970 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:52:02.489407 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:52:02.496682 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:52:02.500200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:52:02.508037 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:52:02.511437 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:52:02.518966 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:52:02.522764 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:52:02.530870 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:52:02.533622 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:52:02.537084 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:52:02.544821 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:52:02.548390 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:52:02.552379 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:52:02.559182 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:52:02.562575 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:52:02.566670 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:52:02.573699 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:52:02.577166 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:52:02.581556 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:52:02.588792 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:52:02.592651 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:52:02.596152 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:52:02.599690 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:52:02.607079 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:52:02.610632 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:52:02.615068 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:52:02.617974 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:52:02.621635 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:52:02.625467 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:52:02.632568 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:52:02.636354 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:52:02.640052 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:52:02.643293 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:52:02.650990 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:52:02.661940 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:52:02.665611 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:52:02.672748 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:52:02.679680 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:52:02.687337 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:52:02.691069 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:52:02.694549 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:52:02.701845 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
534 11:52:02.709295 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:52:02.712718 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
536 11:52:02.716043 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:52:02.726173 [RTC]rtc_get_frequency_meter,154: input=15, output=853
538 11:52:02.736015 [RTC]rtc_get_frequency_meter,154: input=7, output=725
539 11:52:02.745366 [RTC]rtc_get_frequency_meter,154: input=11, output=789
540 11:52:02.754460 [RTC]rtc_get_frequency_meter,154: input=13, output=821
541 11:52:02.763893 [RTC]rtc_get_frequency_meter,154: input=12, output=805
542 11:52:02.773652 [RTC]rtc_get_frequency_meter,154: input=11, output=789
543 11:52:02.783686 [RTC]rtc_get_frequency_meter,154: input=12, output=805
544 11:52:02.786994 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
545 11:52:02.794046 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
546 11:52:02.797805 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:52:02.801956 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:52:02.805435 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:52:02.808423 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:52:02.812142 ADC[4]: Raw value=904433 ID=7
551 11:52:02.815696 ADC[3]: Raw value=213916 ID=1
552 11:52:02.815773 RAM Code: 0x71
553 11:52:02.819569 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:52:02.826975 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:52:02.834772 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:52:02.841946 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:52:02.845486 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:52:02.848959 in-header: 03 07 00 00 08 00 00 00
559 11:52:02.852307 in-data: aa e4 47 04 13 02 00 00
560 11:52:02.852393 Chrome EC: UHEPI supported
561 11:52:02.859810 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:52:02.863164 in-header: 03 95 00 00 08 00 00 00
563 11:52:02.867119 in-data: 18 20 20 08 00 00 00 00
564 11:52:02.870076 MRC: failed to locate region type 0.
565 11:52:02.877993 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:52:02.878084 DRAM-K: Running full calibration
567 11:52:02.885450 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:52:02.888867 header.status = 0x0
569 11:52:02.892793 header.version = 0x6 (expected: 0x6)
570 11:52:02.896043 header.size = 0xd00 (expected: 0xd00)
571 11:52:02.896129 header.flags = 0x0
572 11:52:02.902862 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:52:02.920089 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 11:52:02.927135 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:52:02.930817 dram_init: ddr_geometry: 2
576 11:52:02.930921 [EMI] MDL number = 2
577 11:52:02.934672 [EMI] Get MDL freq = 0
578 11:52:02.934757 dram_init: ddr_type: 0
579 11:52:02.938718 is_discrete_lpddr4: 1
580 11:52:02.941906 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:52:02.941990
582 11:52:02.942086
583 11:52:02.946307 [Bian_co] ETT version 0.0.0.1
584 11:52:02.949541 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:52:02.949625
586 11:52:02.953474 dramc_set_vcore_voltage set vcore to 650000
587 11:52:02.953558 Read voltage for 800, 4
588 11:52:02.957009 Vio18 = 0
589 11:52:02.957093 Vcore = 650000
590 11:52:02.957160 Vdram = 0
591 11:52:02.961193 Vddq = 0
592 11:52:02.961276 Vmddr = 0
593 11:52:02.961344 dram_init: config_dvfs: 1
594 11:52:02.967425 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:52:02.974393 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:52:02.977361 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
597 11:52:02.980816 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
598 11:52:02.984249 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
599 11:52:02.988168 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
600 11:52:02.991647 MEM_TYPE=3, freq_sel=18
601 11:52:02.991734 sv_algorithm_assistance_LP4_1600
602 11:52:02.995664 ============ PULL DRAM RESETB DOWN ============
603 11:52:03.002771 ========== PULL DRAM RESETB DOWN end =========
604 11:52:03.006943 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:52:03.010014 ===================================
606 11:52:03.010125 LPDDR4 DRAM CONFIGURATION
607 11:52:03.013451 ===================================
608 11:52:03.016517 EX_ROW_EN[0] = 0x0
609 11:52:03.020115 EX_ROW_EN[1] = 0x0
610 11:52:03.020196 LP4Y_EN = 0x0
611 11:52:03.023110 WORK_FSP = 0x0
612 11:52:03.023194 WL = 0x2
613 11:52:03.026651 RL = 0x2
614 11:52:03.026753 BL = 0x2
615 11:52:03.030163 RPST = 0x0
616 11:52:03.030247 RD_PRE = 0x0
617 11:52:03.033318 WR_PRE = 0x1
618 11:52:03.033411 WR_PST = 0x0
619 11:52:03.036436 DBI_WR = 0x0
620 11:52:03.036521 DBI_RD = 0x0
621 11:52:03.040002 OTF = 0x1
622 11:52:03.043300 ===================================
623 11:52:03.046390 ===================================
624 11:52:03.046475 ANA top config
625 11:52:03.049929 ===================================
626 11:52:03.053134 DLL_ASYNC_EN = 0
627 11:52:03.056382 ALL_SLAVE_EN = 1
628 11:52:03.060265 NEW_RANK_MODE = 1
629 11:52:03.060351 DLL_IDLE_MODE = 1
630 11:52:03.063124 LP45_APHY_COMB_EN = 1
631 11:52:03.066387 TX_ODT_DIS = 1
632 11:52:03.069860 NEW_8X_MODE = 1
633 11:52:03.072857 ===================================
634 11:52:03.076140 ===================================
635 11:52:03.079543 data_rate = 1600
636 11:52:03.079629 CKR = 1
637 11:52:03.083183 DQ_P2S_RATIO = 8
638 11:52:03.086100 ===================================
639 11:52:03.090158 CA_P2S_RATIO = 8
640 11:52:03.093790 DQ_CA_OPEN = 0
641 11:52:03.097140 DQ_SEMI_OPEN = 0
642 11:52:03.097225 CA_SEMI_OPEN = 0
643 11:52:03.100331 CA_FULL_RATE = 0
644 11:52:03.103320 DQ_CKDIV4_EN = 1
645 11:52:03.106721 CA_CKDIV4_EN = 1
646 11:52:03.110186 CA_PREDIV_EN = 0
647 11:52:03.110311 PH8_DLY = 0
648 11:52:03.113632 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:52:03.117092 DQ_AAMCK_DIV = 4
650 11:52:03.120264 CA_AAMCK_DIV = 4
651 11:52:03.123346 CA_ADMCK_DIV = 4
652 11:52:03.127319 DQ_TRACK_CA_EN = 0
653 11:52:03.130013 CA_PICK = 800
654 11:52:03.130125 CA_MCKIO = 800
655 11:52:03.133499 MCKIO_SEMI = 0
656 11:52:03.137581 PLL_FREQ = 3068
657 11:52:03.141059 DQ_UI_PI_RATIO = 32
658 11:52:03.144563 CA_UI_PI_RATIO = 0
659 11:52:03.144648 ===================================
660 11:52:03.148626 ===================================
661 11:52:03.152067 memory_type:LPDDR4
662 11:52:03.155760 GP_NUM : 10
663 11:52:03.155848 SRAM_EN : 1
664 11:52:03.159250 MD32_EN : 0
665 11:52:03.163352 ===================================
666 11:52:03.163439 [ANA_INIT] >>>>>>>>>>>>>>
667 11:52:03.167109 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:52:03.170679 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:52:03.173861 ===================================
670 11:52:03.177546 data_rate = 1600,PCW = 0X7600
671 11:52:03.180398 ===================================
672 11:52:03.183731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:52:03.186990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:52:03.194139 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:52:03.197423 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:52:03.200525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:52:03.203858 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:52:03.207086 [ANA_INIT] flow start
679 11:52:03.210298 [ANA_INIT] PLL >>>>>>>>
680 11:52:03.210386 [ANA_INIT] PLL <<<<<<<<
681 11:52:03.213836 [ANA_INIT] MIDPI >>>>>>>>
682 11:52:03.217613 [ANA_INIT] MIDPI <<<<<<<<
683 11:52:03.220533 [ANA_INIT] DLL >>>>>>>>
684 11:52:03.220619 [ANA_INIT] flow end
685 11:52:03.223483 ============ LP4 DIFF to SE enter ============
686 11:52:03.230336 ============ LP4 DIFF to SE exit ============
687 11:52:03.230421 [ANA_INIT] <<<<<<<<<<<<<
688 11:52:03.233504 [Flow] Enable top DCM control >>>>>
689 11:52:03.237071 [Flow] Enable top DCM control <<<<<
690 11:52:03.240528 Enable DLL master slave shuffle
691 11:52:03.247258 ==============================================================
692 11:52:03.247357 Gating Mode config
693 11:52:03.253484 ==============================================================
694 11:52:03.256749 Config description:
695 11:52:03.263844 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:52:03.273604 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:52:03.277182 SELPH_MODE 0: By rank 1: By Phase
698 11:52:03.283430 ==============================================================
699 11:52:03.287350 GAT_TRACK_EN = 1
700 11:52:03.287428 RX_GATING_MODE = 2
701 11:52:03.290666 RX_GATING_TRACK_MODE = 2
702 11:52:03.293766 SELPH_MODE = 1
703 11:52:03.296790 PICG_EARLY_EN = 1
704 11:52:03.299805 VALID_LAT_VALUE = 1
705 11:52:03.307292 ==============================================================
706 11:52:03.309893 Enter into Gating configuration >>>>
707 11:52:03.313304 Exit from Gating configuration <<<<
708 11:52:03.316549 Enter into DVFS_PRE_config >>>>>
709 11:52:03.326557 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:52:03.329548 Exit from DVFS_PRE_config <<<<<
711 11:52:03.333141 Enter into PICG configuration >>>>
712 11:52:03.336275 Exit from PICG configuration <<<<
713 11:52:03.340173 [RX_INPUT] configuration >>>>>
714 11:52:03.343161 [RX_INPUT] configuration <<<<<
715 11:52:03.346741 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:52:03.353131 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:52:03.359524 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:52:03.363032 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:52:03.369700 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:52:03.376324 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:52:03.379779 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:52:03.386587 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:52:03.389369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:52:03.392848 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:52:03.396243 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:52:03.402714 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:52:03.406524 ===================================
728 11:52:03.406609 LPDDR4 DRAM CONFIGURATION
729 11:52:03.409191 ===================================
730 11:52:03.412607 EX_ROW_EN[0] = 0x0
731 11:52:03.416021 EX_ROW_EN[1] = 0x0
732 11:52:03.416105 LP4Y_EN = 0x0
733 11:52:03.419296 WORK_FSP = 0x0
734 11:52:03.419380 WL = 0x2
735 11:52:03.423024 RL = 0x2
736 11:52:03.423108 BL = 0x2
737 11:52:03.425770 RPST = 0x0
738 11:52:03.425854 RD_PRE = 0x0
739 11:52:03.428951 WR_PRE = 0x1
740 11:52:03.429035 WR_PST = 0x0
741 11:52:03.432365 DBI_WR = 0x0
742 11:52:03.432449 DBI_RD = 0x0
743 11:52:03.435700 OTF = 0x1
744 11:52:03.439448 ===================================
745 11:52:03.442221 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:52:03.445720 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:52:03.452756 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:52:03.455596 ===================================
749 11:52:03.455681 LPDDR4 DRAM CONFIGURATION
750 11:52:03.459156 ===================================
751 11:52:03.462557 EX_ROW_EN[0] = 0x10
752 11:52:03.465979 EX_ROW_EN[1] = 0x0
753 11:52:03.466063 LP4Y_EN = 0x0
754 11:52:03.469457 WORK_FSP = 0x0
755 11:52:03.469542 WL = 0x2
756 11:52:03.472458 RL = 0x2
757 11:52:03.472543 BL = 0x2
758 11:52:03.475975 RPST = 0x0
759 11:52:03.476059 RD_PRE = 0x0
760 11:52:03.479571 WR_PRE = 0x1
761 11:52:03.479655 WR_PST = 0x0
762 11:52:03.482721 DBI_WR = 0x0
763 11:52:03.482805 DBI_RD = 0x0
764 11:52:03.485739 OTF = 0x1
765 11:52:03.489181 ===================================
766 11:52:03.495885 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:52:03.499203 nWR fixed to 40
768 11:52:03.499289 [ModeRegInit_LP4] CH0 RK0
769 11:52:03.502800 [ModeRegInit_LP4] CH0 RK1
770 11:52:03.505747 [ModeRegInit_LP4] CH1 RK0
771 11:52:03.505830 [ModeRegInit_LP4] CH1 RK1
772 11:52:03.509013 match AC timing 13
773 11:52:03.512646 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:52:03.519087 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:52:03.522118 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:52:03.525767 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:52:03.532599 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:52:03.532685 [EMI DOE] emi_dcm 0
779 11:52:03.539676 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:52:03.539763 ==
781 11:52:03.542636 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:52:03.545449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:52:03.545611 ==
784 11:52:03.552445 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:52:03.555656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:52:03.566034 [CA 0] Center 38 (7~69) winsize 63
787 11:52:03.569084 [CA 1] Center 37 (7~68) winsize 62
788 11:52:03.572430 [CA 2] Center 34 (4~65) winsize 62
789 11:52:03.575739 [CA 3] Center 34 (4~65) winsize 62
790 11:52:03.579230 [CA 4] Center 33 (3~64) winsize 62
791 11:52:03.582620 [CA 5] Center 33 (3~64) winsize 62
792 11:52:03.582721
793 11:52:03.585671 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:52:03.585754
795 11:52:03.589145 [CATrainingPosCal] consider 1 rank data
796 11:52:03.592314 u2DelayCellTimex100 = 270/100 ps
797 11:52:03.595506 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
798 11:52:03.598794 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
799 11:52:03.605339 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:52:03.608701 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:52:03.612468 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:52:03.615778 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:52:03.615863
804 11:52:03.619016 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:52:03.619101
806 11:52:03.621975 [CBTSetCACLKResult] CA Dly = 33
807 11:52:03.622061 CS Dly: 5 (0~36)
808 11:52:03.625807 ==
809 11:52:03.625892 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:52:03.632547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:52:03.632631 ==
812 11:52:03.635499 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:52:03.641989 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:52:03.652108 [CA 0] Center 38 (7~69) winsize 63
815 11:52:03.655510 [CA 1] Center 37 (7~68) winsize 62
816 11:52:03.658258 [CA 2] Center 35 (4~66) winsize 63
817 11:52:03.661828 [CA 3] Center 35 (4~66) winsize 63
818 11:52:03.665368 [CA 4] Center 34 (3~65) winsize 63
819 11:52:03.668267 [CA 5] Center 33 (3~64) winsize 62
820 11:52:03.668350
821 11:52:03.671818 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:52:03.671903
823 11:52:03.675478 [CATrainingPosCal] consider 2 rank data
824 11:52:03.678241 u2DelayCellTimex100 = 270/100 ps
825 11:52:03.681760 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
826 11:52:03.688683 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:52:03.691509 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:52:03.694954 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:52:03.698511 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:52:03.701822 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:52:03.701907
832 11:52:03.704660 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:52:03.704745
834 11:52:03.708251 [CBTSetCACLKResult] CA Dly = 33
835 11:52:03.708336 CS Dly: 6 (0~38)
836 11:52:03.711767
837 11:52:03.715147 ----->DramcWriteLeveling(PI) begin...
838 11:52:03.715233 ==
839 11:52:03.718592 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:52:03.722370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:52:03.722456 ==
842 11:52:03.725633 Write leveling (Byte 0): 29 => 29
843 11:52:03.725718 Write leveling (Byte 1): 26 => 26
844 11:52:03.729666 DramcWriteLeveling(PI) end<-----
845 11:52:03.729751
846 11:52:03.729818 ==
847 11:52:03.733318 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:52:03.739703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:52:03.739788 ==
850 11:52:03.739856 [Gating] SW mode calibration
851 11:52:03.746817 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:52:03.753600 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:52:03.757015 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:52:03.764159 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:52:03.766862 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:52:03.770297 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 11:52:03.776665 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:52:03.780133 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:52:03.783338 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:52:03.789983 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:52:03.793743 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:52:03.797067 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:52:03.799828 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:52:03.806628 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:52:03.810216 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:52:03.813992 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:52:03.820075 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:52:03.823460 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:52:03.826459 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:52:03.833306 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:52:03.836877 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
872 11:52:03.839941 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:52:03.846660 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:52:03.850141 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:52:03.853030 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:52:03.859825 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:52:03.863258 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:52:03.866748 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:52:03.873129 0 9 8 | B1->B0 | 2323 2f2e | 0 1 | (1 1) (0 0)
880 11:52:03.876303 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
881 11:52:03.879651 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:52:03.886182 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:52:03.889606 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:52:03.892915 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:52:03.899705 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:52:03.902869 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
887 11:52:03.906277 0 10 8 | B1->B0 | 3333 2626 | 1 0 | (1 0) (0 0)
888 11:52:03.913052 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 11:52:03.915956 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:52:03.919614 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:52:03.926288 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:52:03.929201 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:52:03.932599 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:52:03.939356 0 11 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
895 11:52:03.942818 0 11 8 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
896 11:52:03.946057 0 11 12 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
897 11:52:03.952596 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:52:03.956025 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:52:03.959355 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:52:03.965688 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:52:03.969143 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:52:03.972165 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
903 11:52:03.979416 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:52:03.982686 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:52:03.985866 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:52:03.989241 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:52:03.996068 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:52:03.999520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:52:04.002372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:52:04.009213 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:52:04.012360 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:52:04.016074 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:52:04.022399 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:52:04.026013 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:52:04.029164 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:52:04.036103 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:52:04.039025 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:52:04.042107 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
919 11:52:04.049284 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:52:04.049368 Total UI for P1: 0, mck2ui 16
921 11:52:04.055510 best dqsien dly found for B0: ( 0, 14, 4)
922 11:52:04.059003 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 11:52:04.061967 Total UI for P1: 0, mck2ui 16
924 11:52:04.065855 best dqsien dly found for B1: ( 0, 14, 6)
925 11:52:04.069036 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 11:52:04.071966 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
927 11:52:04.072050
928 11:52:04.075330 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 11:52:04.078924 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 11:52:04.082652 [Gating] SW calibration Done
931 11:52:04.082736 ==
932 11:52:04.085565 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:52:04.089344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:52:04.089429 ==
935 11:52:04.093077 RX Vref Scan: 0
936 11:52:04.093162
937 11:52:04.093228 RX Vref 0 -> 0, step: 1
938 11:52:04.093290
939 11:52:04.096294 RX Delay -130 -> 252, step: 16
940 11:52:04.099832 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 11:52:04.106094 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 11:52:04.109588 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 11:52:04.112838 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 11:52:04.116532 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 11:52:04.119896 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 11:52:04.126142 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 11:52:04.129685 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
948 11:52:04.133109 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
949 11:52:04.136253 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
950 11:52:04.139751 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
951 11:52:04.146220 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:52:04.149535 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:52:04.152553 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
954 11:52:04.156376 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:52:04.162645 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
956 11:52:04.162730 ==
957 11:52:04.166167 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:52:04.169954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:52:04.170038 ==
960 11:52:04.170105 DQS Delay:
961 11:52:04.172595 DQS0 = 0, DQS1 = 0
962 11:52:04.172685 DQM Delay:
963 11:52:04.176047 DQM0 = 92, DQM1 = 76
964 11:52:04.176130 DQ Delay:
965 11:52:04.179579 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 11:52:04.182809 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
967 11:52:04.185647 DQ8 =69, DQ9 =53, DQ10 =77, DQ11 =69
968 11:52:04.189022 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
969 11:52:04.189105
970 11:52:04.189171
971 11:52:04.189232 ==
972 11:52:04.192796 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:52:04.195757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:52:04.195841 ==
975 11:52:04.195908
976 11:52:04.195970
977 11:52:04.199562 TX Vref Scan disable
978 11:52:04.202650 == TX Byte 0 ==
979 11:52:04.206050 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
980 11:52:04.209224 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
981 11:52:04.212671 == TX Byte 1 ==
982 11:52:04.216002 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
983 11:52:04.219452 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
984 11:52:04.219536 ==
985 11:52:04.222173 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:52:04.228707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:52:04.228791 ==
988 11:52:04.240625 TX Vref=22, minBit 7, minWin=26, winSum=438
989 11:52:04.244009 TX Vref=24, minBit 0, minWin=27, winSum=441
990 11:52:04.247646 TX Vref=26, minBit 3, minWin=27, winSum=447
991 11:52:04.250646 TX Vref=28, minBit 3, minWin=27, winSum=449
992 11:52:04.254030 TX Vref=30, minBit 8, minWin=27, winSum=452
993 11:52:04.260735 TX Vref=32, minBit 1, minWin=28, winSum=453
994 11:52:04.263813 [TxChooseVref] Worse bit 1, Min win 28, Win sum 453, Final Vref 32
995 11:52:04.263899
996 11:52:04.267166 Final TX Range 1 Vref 32
997 11:52:04.267251
998 11:52:04.267318 ==
999 11:52:04.270676 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:52:04.273929 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:52:04.274014 ==
1002 11:52:04.277244
1003 11:52:04.277328
1004 11:52:04.277395 TX Vref Scan disable
1005 11:52:04.280764 == TX Byte 0 ==
1006 11:52:04.284198 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1007 11:52:04.290613 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1008 11:52:04.290712 == TX Byte 1 ==
1009 11:52:04.294134 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1010 11:52:04.301351 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1011 11:52:04.301437
1012 11:52:04.301505 [DATLAT]
1013 11:52:04.301567 Freq=800, CH0 RK0
1014 11:52:04.301627
1015 11:52:04.303957 DATLAT Default: 0xa
1016 11:52:04.304041 0, 0xFFFF, sum = 0
1017 11:52:04.307416 1, 0xFFFF, sum = 0
1018 11:52:04.307500 2, 0xFFFF, sum = 0
1019 11:52:04.310599 3, 0xFFFF, sum = 0
1020 11:52:04.310684 4, 0xFFFF, sum = 0
1021 11:52:04.313949 5, 0xFFFF, sum = 0
1022 11:52:04.317485 6, 0xFFFF, sum = 0
1023 11:52:04.317570 7, 0xFFFF, sum = 0
1024 11:52:04.320813 8, 0xFFFF, sum = 0
1025 11:52:04.320918 9, 0x0, sum = 1
1026 11:52:04.321020 10, 0x0, sum = 2
1027 11:52:04.323845 11, 0x0, sum = 3
1028 11:52:04.323929 12, 0x0, sum = 4
1029 11:52:04.327350 best_step = 10
1030 11:52:04.327432
1031 11:52:04.327497 ==
1032 11:52:04.330527 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:52:04.334063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:52:04.334146 ==
1035 11:52:04.337633 RX Vref Scan: 1
1036 11:52:04.337715
1037 11:52:04.340450 Set Vref Range= 32 -> 127
1038 11:52:04.340533
1039 11:52:04.340598 RX Vref 32 -> 127, step: 1
1040 11:52:04.340670
1041 11:52:04.343825 RX Delay -111 -> 252, step: 8
1042 11:52:04.343907
1043 11:52:04.347238 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:52:04.350647 [Byte1]: 32
1045 11:52:04.350730
1046 11:52:04.354246 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:52:04.357369 [Byte1]: 33
1048 11:52:04.361363
1049 11:52:04.361445 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:52:04.364498 [Byte1]: 34
1051 11:52:04.369216
1052 11:52:04.369302 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:52:04.372291 [Byte1]: 35
1054 11:52:04.376467
1055 11:52:04.376550 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:52:04.379783 [Byte1]: 36
1057 11:52:04.384220
1058 11:52:04.384302 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:52:04.387800 [Byte1]: 37
1060 11:52:04.392218
1061 11:52:04.392300 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:52:04.395612 [Byte1]: 38
1063 11:52:04.400023
1064 11:52:04.400107 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:52:04.403490 [Byte1]: 39
1066 11:52:04.407504
1067 11:52:04.407588 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:52:04.411183 [Byte1]: 40
1069 11:52:04.415144
1070 11:52:04.415242 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:52:04.419012 [Byte1]: 41
1072 11:52:04.422788
1073 11:52:04.422871 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:52:04.425741 [Byte1]: 42
1075 11:52:04.429910
1076 11:52:04.429993 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:52:04.433075 [Byte1]: 43
1078 11:52:04.437846
1079 11:52:04.437952 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:52:04.440945 [Byte1]: 44
1081 11:52:04.445579
1082 11:52:04.445661 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:52:04.449195 [Byte1]: 45
1084 11:52:04.453037
1085 11:52:04.453119 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:52:04.456411 [Byte1]: 46
1087 11:52:04.460201
1088 11:52:04.463725 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:52:04.467097 [Byte1]: 47
1090 11:52:04.467179
1091 11:52:04.470567 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:52:04.473703 [Byte1]: 48
1093 11:52:04.473786
1094 11:52:04.477048 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:52:04.480174 [Byte1]: 49
1096 11:52:04.483705
1097 11:52:04.483787 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:52:04.486895 [Byte1]: 50
1099 11:52:04.491293
1100 11:52:04.491375 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:52:04.494911 [Byte1]: 51
1102 11:52:04.499144
1103 11:52:04.499250 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:52:04.502135 [Byte1]: 52
1105 11:52:04.506547
1106 11:52:04.506628 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:52:04.510169 [Byte1]: 53
1108 11:52:04.514195
1109 11:52:04.514313 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:52:04.517640 [Byte1]: 54
1111 11:52:04.521525
1112 11:52:04.521635 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:52:04.524837 [Byte1]: 55
1114 11:52:04.529402
1115 11:52:04.529485 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:52:04.532732 [Byte1]: 56
1117 11:52:04.537295
1118 11:52:04.537397 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:52:04.540245 [Byte1]: 57
1120 11:52:04.545312
1121 11:52:04.545394 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:52:04.548396 [Byte1]: 58
1123 11:52:04.552889
1124 11:52:04.552971 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:52:04.555395 [Byte1]: 59
1126 11:52:04.560014
1127 11:52:04.560096 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:52:04.563598 [Byte1]: 60
1129 11:52:04.567589
1130 11:52:04.567671 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:52:04.570833 [Byte1]: 61
1132 11:52:04.575392
1133 11:52:04.575474 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:52:04.578292 [Byte1]: 62
1135 11:52:04.582684
1136 11:52:04.582766 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:52:04.585948 [Byte1]: 63
1138 11:52:04.590674
1139 11:52:04.590755 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:52:04.593972 [Byte1]: 64
1141 11:52:04.598134
1142 11:52:04.598216 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:52:04.601714 [Byte1]: 65
1144 11:52:04.605893
1145 11:52:04.605975 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:52:04.608977 [Byte1]: 66
1147 11:52:04.613754
1148 11:52:04.613836 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:52:04.616862 [Byte1]: 67
1150 11:52:04.621414
1151 11:52:04.621496 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:52:04.624589 [Byte1]: 68
1153 11:52:04.629058
1154 11:52:04.629141 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:52:04.632017 [Byte1]: 69
1156 11:52:04.636281
1157 11:52:04.636363 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:52:04.639709 [Byte1]: 70
1159 11:52:04.644313
1160 11:52:04.644396 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:52:04.647732 [Byte1]: 71
1162 11:52:04.651712
1163 11:52:04.651794 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:52:04.655080 [Byte1]: 72
1165 11:52:04.659215
1166 11:52:04.659297 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:52:04.662527 [Byte1]: 73
1168 11:52:04.667280
1169 11:52:04.667362 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:52:04.670603 [Byte1]: 74
1171 11:52:04.674512
1172 11:52:04.674595 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:52:04.677852 [Byte1]: 75
1174 11:52:04.682524
1175 11:52:04.682607 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:52:04.685506 [Byte1]: 76
1177 11:52:04.689770
1178 11:52:04.689852 Final RX Vref Byte 0 = 55 to rank0
1179 11:52:04.693358 Final RX Vref Byte 1 = 60 to rank0
1180 11:52:04.696510 Final RX Vref Byte 0 = 55 to rank1
1181 11:52:04.699751 Final RX Vref Byte 1 = 60 to rank1==
1182 11:52:04.703216 Dram Type= 6, Freq= 0, CH_0, rank 0
1183 11:52:04.709688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1184 11:52:04.709770 ==
1185 11:52:04.709836 DQS Delay:
1186 11:52:04.709898 DQS0 = 0, DQS1 = 0
1187 11:52:04.713450 DQM Delay:
1188 11:52:04.713539 DQM0 = 88, DQM1 = 76
1189 11:52:04.716524 DQ Delay:
1190 11:52:04.719794 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1191 11:52:04.723506 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1192 11:52:04.723588 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =72
1193 11:52:04.729754 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1194 11:52:04.729837
1195 11:52:04.729902
1196 11:52:04.736562 [DQSOSCAuto] RK0, (LSB)MR18= 0x342d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1197 11:52:04.739726 CH0 RK0: MR19=606, MR18=342D
1198 11:52:04.746827 CH0_RK0: MR19=0x606, MR18=0x342D, DQSOSC=396, MR23=63, INC=94, DEC=62
1199 11:52:04.746909
1200 11:52:04.749654 ----->DramcWriteLeveling(PI) begin...
1201 11:52:04.749729 ==
1202 11:52:04.752999 Dram Type= 6, Freq= 0, CH_0, rank 1
1203 11:52:04.756159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1204 11:52:04.756261 ==
1205 11:52:04.759452 Write leveling (Byte 0): 32 => 32
1206 11:52:04.763151 Write leveling (Byte 1): 27 => 27
1207 11:52:04.766383 DramcWriteLeveling(PI) end<-----
1208 11:52:04.766461
1209 11:52:04.766525 ==
1210 11:52:04.769687 Dram Type= 6, Freq= 0, CH_0, rank 1
1211 11:52:04.772601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1212 11:52:04.772681 ==
1213 11:52:04.776050 [Gating] SW mode calibration
1214 11:52:04.823374 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1215 11:52:04.823662 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1216 11:52:04.823776 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1217 11:52:04.824156 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1218 11:52:04.824251 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 11:52:04.824524 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 11:52:04.825053 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 11:52:04.825810 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 11:52:04.825882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 11:52:04.826127 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:52:04.828551 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:52:04.831914 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:52:04.838566 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:52:04.841999 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:52:04.845436 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:52:04.851833 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:52:04.855342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:52:04.858186 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:52:04.865153 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:52:04.868196 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1234 11:52:04.871892 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1235 11:52:04.878024 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:52:04.881452 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 11:52:04.884777 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 11:52:04.891875 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:52:04.894659 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:52:04.898158 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:52:04.905146 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1242 11:52:04.908197 0 9 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
1243 11:52:04.911543 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1244 11:52:04.914874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1245 11:52:04.921271 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1246 11:52:04.924569 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:52:04.928280 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:52:04.934418 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:52:04.937657 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
1250 11:52:04.941386 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1251 11:52:04.948058 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1252 11:52:04.951248 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:52:04.954255 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:52:04.961398 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:52:04.964755 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:52:04.968412 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:52:04.971857 0 11 4 | B1->B0 | 2323 3332 | 0 1 | (0 0) (0 0)
1258 11:52:04.979148 0 11 8 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
1259 11:52:04.982750 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
1260 11:52:04.986203 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1261 11:52:04.989513 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1262 11:52:04.996438 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:52:05.000192 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:52:05.002928 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:52:05.009645 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:52:05.013190 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1267 11:52:05.016361 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 11:52:05.023276 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 11:52:05.026588 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 11:52:05.029558 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:52:05.036345 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:52:05.039696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:52:05.042662 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:52:05.049637 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:52:05.052729 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:52:05.056070 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:52:05.062580 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:52:05.066176 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:52:05.069179 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:52:05.075774 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:52:05.079253 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1282 11:52:05.082718 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1283 11:52:05.086151 Total UI for P1: 0, mck2ui 16
1284 11:52:05.089543 best dqsien dly found for B0: ( 0, 14, 4)
1285 11:52:05.092840 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 11:52:05.096287 Total UI for P1: 0, mck2ui 16
1287 11:52:05.099667 best dqsien dly found for B1: ( 0, 14, 8)
1288 11:52:05.102511 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1289 11:52:05.109355 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1290 11:52:05.109451
1291 11:52:05.112530 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1292 11:52:05.116063 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1293 11:52:05.119639 [Gating] SW calibration Done
1294 11:52:05.119713 ==
1295 11:52:05.122630 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:52:05.126103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:52:05.126178 ==
1298 11:52:05.126240 RX Vref Scan: 0
1299 11:52:05.126346
1300 11:52:05.129413 RX Vref 0 -> 0, step: 1
1301 11:52:05.129494
1302 11:52:05.132299 RX Delay -130 -> 252, step: 16
1303 11:52:05.135578 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1304 11:52:05.139104 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1305 11:52:05.145581 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1306 11:52:05.149081 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1307 11:52:05.152018 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1308 11:52:05.155571 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1309 11:52:05.159065 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1310 11:52:05.165414 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1311 11:52:05.168693 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1312 11:52:05.172102 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1313 11:52:05.175470 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1314 11:52:05.182045 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1315 11:52:05.185375 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1316 11:52:05.188976 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1317 11:52:05.191800 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1318 11:52:05.194964 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1319 11:52:05.198713 ==
1320 11:52:05.201715 Dram Type= 6, Freq= 0, CH_0, rank 1
1321 11:52:05.205044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1322 11:52:05.205148 ==
1323 11:52:05.205241 DQS Delay:
1324 11:52:05.208447 DQS0 = 0, DQS1 = 0
1325 11:52:05.208544 DQM Delay:
1326 11:52:05.211644 DQM0 = 89, DQM1 = 78
1327 11:52:05.211741 DQ Delay:
1328 11:52:05.214852 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =93
1329 11:52:05.218214 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1330 11:52:05.221703 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1331 11:52:05.225094 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1332 11:52:05.225194
1333 11:52:05.225259
1334 11:52:05.225318 ==
1335 11:52:05.228485 Dram Type= 6, Freq= 0, CH_0, rank 1
1336 11:52:05.231900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1337 11:52:05.231974 ==
1338 11:52:05.232034
1339 11:52:05.232091
1340 11:52:05.235108 TX Vref Scan disable
1341 11:52:05.238660 == TX Byte 0 ==
1342 11:52:05.242033 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1343 11:52:05.244892 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1344 11:52:05.248300 == TX Byte 1 ==
1345 11:52:05.251809 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1346 11:52:05.254760 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1347 11:52:05.254831 ==
1348 11:52:05.258132 Dram Type= 6, Freq= 0, CH_0, rank 1
1349 11:52:05.261777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1350 11:52:05.264625 ==
1351 11:52:05.276409 TX Vref=22, minBit 0, minWin=27, winSum=441
1352 11:52:05.279897 TX Vref=24, minBit 1, minWin=27, winSum=445
1353 11:52:05.283356 TX Vref=26, minBit 2, minWin=27, winSum=450
1354 11:52:05.286693 TX Vref=28, minBit 2, minWin=27, winSum=450
1355 11:52:05.289912 TX Vref=30, minBit 1, minWin=27, winSum=450
1356 11:52:05.296619 TX Vref=32, minBit 1, minWin=27, winSum=448
1357 11:52:05.299856 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 26
1358 11:52:05.299938
1359 11:52:05.303318 Final TX Range 1 Vref 26
1360 11:52:05.303432
1361 11:52:05.303500 ==
1362 11:52:05.306670 Dram Type= 6, Freq= 0, CH_0, rank 1
1363 11:52:05.309941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1364 11:52:05.310023 ==
1365 11:52:05.313138
1366 11:52:05.313218
1367 11:52:05.313281 TX Vref Scan disable
1368 11:52:05.317347 == TX Byte 0 ==
1369 11:52:05.320298 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1370 11:52:05.323179 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1371 11:52:05.326497 == TX Byte 1 ==
1372 11:52:05.329789 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1373 11:52:05.336619 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1374 11:52:05.336699
1375 11:52:05.336763 [DATLAT]
1376 11:52:05.336823 Freq=800, CH0 RK1
1377 11:52:05.336881
1378 11:52:05.339859 DATLAT Default: 0xa
1379 11:52:05.339940 0, 0xFFFF, sum = 0
1380 11:52:05.343301 1, 0xFFFF, sum = 0
1381 11:52:05.343384 2, 0xFFFF, sum = 0
1382 11:52:05.346767 3, 0xFFFF, sum = 0
1383 11:52:05.349598 4, 0xFFFF, sum = 0
1384 11:52:05.349680 5, 0xFFFF, sum = 0
1385 11:52:05.352983 6, 0xFFFF, sum = 0
1386 11:52:05.353065 7, 0xFFFF, sum = 0
1387 11:52:05.356496 8, 0xFFFF, sum = 0
1388 11:52:05.356577 9, 0x0, sum = 1
1389 11:52:05.359984 10, 0x0, sum = 2
1390 11:52:05.360066 11, 0x0, sum = 3
1391 11:52:05.360131 12, 0x0, sum = 4
1392 11:52:05.362844 best_step = 10
1393 11:52:05.362924
1394 11:52:05.362988 ==
1395 11:52:05.366389 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 11:52:05.369981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 11:52:05.370062 ==
1398 11:52:05.372831 RX Vref Scan: 0
1399 11:52:05.372935
1400 11:52:05.373029 RX Vref 0 -> 0, step: 1
1401 11:52:05.376349
1402 11:52:05.376429 RX Delay -95 -> 252, step: 8
1403 11:52:05.383629 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1404 11:52:05.386778 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1405 11:52:05.389756 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1406 11:52:05.392935 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1407 11:52:05.396354 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1408 11:52:05.402723 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1409 11:52:05.406754 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1410 11:52:05.409567 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1411 11:52:05.412797 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1412 11:52:05.416590 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1413 11:52:05.423191 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1414 11:52:05.426046 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1415 11:52:05.429848 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1416 11:52:05.433138 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1417 11:52:05.439545 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1418 11:52:05.442831 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1419 11:52:05.442912 ==
1420 11:52:05.446006 Dram Type= 6, Freq= 0, CH_0, rank 1
1421 11:52:05.449525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1422 11:52:05.449606 ==
1423 11:52:05.449670 DQS Delay:
1424 11:52:05.452620 DQS0 = 0, DQS1 = 0
1425 11:52:05.452700 DQM Delay:
1426 11:52:05.456009 DQM0 = 86, DQM1 = 77
1427 11:52:05.456089 DQ Delay:
1428 11:52:05.459316 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1429 11:52:05.462729 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1430 11:52:05.466598 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1431 11:52:05.469420 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1432 11:52:05.469515
1433 11:52:05.469580
1434 11:52:05.479631 [DQSOSCAuto] RK1, (LSB)MR18= 0x2724, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1435 11:52:05.479713 CH0 RK1: MR19=606, MR18=2724
1436 11:52:05.486655 CH0_RK1: MR19=0x606, MR18=0x2724, DQSOSC=400, MR23=63, INC=92, DEC=61
1437 11:52:05.489650 [RxdqsGatingPostProcess] freq 800
1438 11:52:05.496329 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1439 11:52:05.499766 Pre-setting of DQS Precalculation
1440 11:52:05.502831 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1441 11:52:05.502913 ==
1442 11:52:05.506270 Dram Type= 6, Freq= 0, CH_1, rank 0
1443 11:52:05.509668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:52:05.513103 ==
1445 11:52:05.516136 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1446 11:52:05.522473 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1447 11:52:05.531562 [CA 0] Center 36 (6~67) winsize 62
1448 11:52:05.534763 [CA 1] Center 37 (6~68) winsize 63
1449 11:52:05.538067 [CA 2] Center 35 (5~65) winsize 61
1450 11:52:05.541723 [CA 3] Center 34 (3~65) winsize 63
1451 11:52:05.544621 [CA 4] Center 34 (4~65) winsize 62
1452 11:52:05.548207 [CA 5] Center 34 (3~65) winsize 63
1453 11:52:05.548289
1454 11:52:05.551156 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1455 11:52:05.551237
1456 11:52:05.554962 [CATrainingPosCal] consider 1 rank data
1457 11:52:05.558473 u2DelayCellTimex100 = 270/100 ps
1458 11:52:05.561318 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1459 11:52:05.568299 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1460 11:52:05.571410 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1461 11:52:05.574455 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1462 11:52:05.577869 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1463 11:52:05.581521 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1464 11:52:05.581602
1465 11:52:05.584939 CA PerBit enable=1, Macro0, CA PI delay=34
1466 11:52:05.585019
1467 11:52:05.587951 [CBTSetCACLKResult] CA Dly = 34
1468 11:52:05.588032 CS Dly: 4 (0~35)
1469 11:52:05.591290 ==
1470 11:52:05.594642 Dram Type= 6, Freq= 0, CH_1, rank 1
1471 11:52:05.598058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1472 11:52:05.598140 ==
1473 11:52:05.600961 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1474 11:52:05.607979 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1475 11:52:05.617922 [CA 0] Center 36 (6~67) winsize 62
1476 11:52:05.620853 [CA 1] Center 36 (6~67) winsize 62
1477 11:52:05.624624 [CA 2] Center 34 (4~65) winsize 62
1478 11:52:05.627895 [CA 3] Center 34 (3~65) winsize 63
1479 11:52:05.631889 [CA 4] Center 34 (3~65) winsize 63
1480 11:52:05.635237 [CA 5] Center 34 (3~65) winsize 63
1481 11:52:05.635314
1482 11:52:05.638705 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1483 11:52:05.638779
1484 11:52:05.642160 [CATrainingPosCal] consider 2 rank data
1485 11:52:05.646384 u2DelayCellTimex100 = 270/100 ps
1486 11:52:05.650387 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1487 11:52:05.653202 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1488 11:52:05.657343 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1489 11:52:05.661057 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1490 11:52:05.664771 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1491 11:52:05.668033 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1492 11:52:05.668133
1493 11:52:05.670927 CA PerBit enable=1, Macro0, CA PI delay=34
1494 11:52:05.671023
1495 11:52:05.674496 [CBTSetCACLKResult] CA Dly = 34
1496 11:52:05.674568 CS Dly: 5 (0~37)
1497 11:52:05.674628
1498 11:52:05.677770 ----->DramcWriteLeveling(PI) begin...
1499 11:52:05.677840 ==
1500 11:52:05.680898 Dram Type= 6, Freq= 0, CH_1, rank 0
1501 11:52:05.687713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1502 11:52:05.687814 ==
1503 11:52:05.691269 Write leveling (Byte 0): 27 => 27
1504 11:52:05.694196 Write leveling (Byte 1): 26 => 26
1505 11:52:05.697679 DramcWriteLeveling(PI) end<-----
1506 11:52:05.697779
1507 11:52:05.697871 ==
1508 11:52:05.700914 Dram Type= 6, Freq= 0, CH_1, rank 0
1509 11:52:05.704274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1510 11:52:05.704375 ==
1511 11:52:05.707868 [Gating] SW mode calibration
1512 11:52:05.713976 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1513 11:52:05.718005 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1514 11:52:05.724112 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1515 11:52:05.727987 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1516 11:52:05.730835 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1517 11:52:05.737668 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 11:52:05.740594 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 11:52:05.744085 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 11:52:05.750535 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:52:05.754013 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:52:05.757366 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:52:05.764016 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:52:05.767324 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:52:05.770882 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:52:05.777336 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:52:05.780634 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:52:05.784373 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:52:05.790580 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:52:05.794190 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:52:05.797236 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1532 11:52:05.803704 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1533 11:52:05.808244 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:52:05.810387 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:52:05.816980 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:52:05.820605 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:52:05.823625 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:52:05.830121 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:52:05.833811 0 9 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1540 11:52:05.837344 0 9 8 | B1->B0 | 2e2e 3434 | 0 0 | (0 0) (0 0)
1541 11:52:05.843572 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1542 11:52:05.847128 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1543 11:52:05.850473 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1544 11:52:05.856901 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1545 11:52:05.860395 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:52:05.863540 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:52:05.867096 0 10 4 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
1548 11:52:05.873742 0 10 8 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
1549 11:52:05.877071 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:52:05.880023 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:52:05.886775 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:52:05.890174 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:52:05.893478 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:52:05.900338 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:52:05.903333 0 11 4 | B1->B0 | 2626 2c2c | 0 0 | (0 0) (0 0)
1556 11:52:05.906890 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
1557 11:52:05.913445 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1558 11:52:05.916924 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:52:05.920033 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1560 11:52:05.926838 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1561 11:52:05.930279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:52:05.933676 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:52:05.939946 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1564 11:52:05.943418 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1565 11:52:05.946919 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 11:52:05.953771 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 11:52:05.956706 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 11:52:05.960031 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:52:05.966526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:52:05.970097 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:52:05.973285 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:52:05.979949 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:52:05.983373 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:52:05.987163 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:52:05.990157 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:52:05.996904 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:52:06.000005 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:52:06.003171 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:52:06.010049 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:52:06.013117 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1581 11:52:06.016646 Total UI for P1: 0, mck2ui 16
1582 11:52:06.019971 best dqsien dly found for B0: ( 0, 14, 6)
1583 11:52:06.023267 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 11:52:06.026852 Total UI for P1: 0, mck2ui 16
1585 11:52:06.030123 best dqsien dly found for B1: ( 0, 14, 8)
1586 11:52:06.033102 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1587 11:52:06.036526 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1588 11:52:06.036622
1589 11:52:06.043410 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1590 11:52:06.046440 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1591 11:52:06.049687 [Gating] SW calibration Done
1592 11:52:06.049781 ==
1593 11:52:06.052833 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:52:06.056319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:52:06.056413 ==
1596 11:52:06.056505 RX Vref Scan: 0
1597 11:52:06.056591
1598 11:52:06.059719 RX Vref 0 -> 0, step: 1
1599 11:52:06.059810
1600 11:52:06.063515 RX Delay -130 -> 252, step: 16
1601 11:52:06.066347 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1602 11:52:06.069296 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1603 11:52:06.076305 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1604 11:52:06.079553 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1605 11:52:06.082861 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1606 11:52:06.086671 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1607 11:52:06.089537 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1608 11:52:06.096180 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1609 11:52:06.099647 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1610 11:52:06.103298 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1611 11:52:06.106330 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1612 11:52:06.109387 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1613 11:52:06.116123 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1614 11:52:06.119675 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1615 11:52:06.122553 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1616 11:52:06.126329 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1617 11:52:06.126399 ==
1618 11:52:06.129312 Dram Type= 6, Freq= 0, CH_1, rank 0
1619 11:52:06.136265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1620 11:52:06.136363 ==
1621 11:52:06.136455 DQS Delay:
1622 11:52:06.136542 DQS0 = 0, DQS1 = 0
1623 11:52:06.139595 DQM Delay:
1624 11:52:06.139663 DQM0 = 87, DQM1 = 80
1625 11:52:06.142617 DQ Delay:
1626 11:52:06.146514 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1627 11:52:06.149314 DQ4 =85, DQ5 =93, DQ6 =101, DQ7 =85
1628 11:52:06.152428 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1629 11:52:06.155607 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1630 11:52:06.155690
1631 11:52:06.155774
1632 11:52:06.155853 ==
1633 11:52:06.159525 Dram Type= 6, Freq= 0, CH_1, rank 0
1634 11:52:06.162893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1635 11:52:06.162977 ==
1636 11:52:06.163062
1637 11:52:06.163142
1638 11:52:06.165972 TX Vref Scan disable
1639 11:52:06.166056 == TX Byte 0 ==
1640 11:52:06.172622 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1641 11:52:06.176213 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1642 11:52:06.176297 == TX Byte 1 ==
1643 11:52:06.182438 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1644 11:52:06.186025 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1645 11:52:06.186134 ==
1646 11:52:06.189065 Dram Type= 6, Freq= 0, CH_1, rank 0
1647 11:52:06.192424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1648 11:52:06.192500 ==
1649 11:52:06.206738 TX Vref=22, minBit 0, minWin=27, winSum=442
1650 11:52:06.209718 TX Vref=24, minBit 0, minWin=27, winSum=448
1651 11:52:06.214003 TX Vref=26, minBit 0, minWin=27, winSum=449
1652 11:52:06.217204 TX Vref=28, minBit 1, minWin=27, winSum=454
1653 11:52:06.220624 TX Vref=30, minBit 5, minWin=27, winSum=453
1654 11:52:06.224007 TX Vref=32, minBit 1, minWin=27, winSum=456
1655 11:52:06.230259 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 32
1656 11:52:06.230362
1657 11:52:06.233536 Final TX Range 1 Vref 32
1658 11:52:06.233635
1659 11:52:06.233733 ==
1660 11:52:06.237193 Dram Type= 6, Freq= 0, CH_1, rank 0
1661 11:52:06.240596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1662 11:52:06.240680 ==
1663 11:52:06.240765
1664 11:52:06.240845
1665 11:52:06.243533 TX Vref Scan disable
1666 11:52:06.247009 == TX Byte 0 ==
1667 11:52:06.250535 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1668 11:52:06.254094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1669 11:52:06.256731 == TX Byte 1 ==
1670 11:52:06.260158 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1671 11:52:06.263630 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1672 11:52:06.263713
1673 11:52:06.267152 [DATLAT]
1674 11:52:06.267235 Freq=800, CH1 RK0
1675 11:52:06.267321
1676 11:52:06.270058 DATLAT Default: 0xa
1677 11:52:06.270141 0, 0xFFFF, sum = 0
1678 11:52:06.273353 1, 0xFFFF, sum = 0
1679 11:52:06.273462 2, 0xFFFF, sum = 0
1680 11:52:06.276722 3, 0xFFFF, sum = 0
1681 11:52:06.276807 4, 0xFFFF, sum = 0
1682 11:52:06.279848 5, 0xFFFF, sum = 0
1683 11:52:06.279933 6, 0xFFFF, sum = 0
1684 11:52:06.283366 7, 0xFFFF, sum = 0
1685 11:52:06.283451 8, 0xFFFF, sum = 0
1686 11:52:06.287166 9, 0x0, sum = 1
1687 11:52:06.287250 10, 0x0, sum = 2
1688 11:52:06.289936 11, 0x0, sum = 3
1689 11:52:06.290020 12, 0x0, sum = 4
1690 11:52:06.293131 best_step = 10
1691 11:52:06.293214
1692 11:52:06.293299 ==
1693 11:52:06.296755 Dram Type= 6, Freq= 0, CH_1, rank 0
1694 11:52:06.300371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1695 11:52:06.300455 ==
1696 11:52:06.303318 RX Vref Scan: 1
1697 11:52:06.303400
1698 11:52:06.303484 Set Vref Range= 32 -> 127
1699 11:52:06.303564
1700 11:52:06.306460 RX Vref 32 -> 127, step: 1
1701 11:52:06.306544
1702 11:52:06.309919 RX Delay -95 -> 252, step: 8
1703 11:52:06.310002
1704 11:52:06.313209 Set Vref, RX VrefLevel [Byte0]: 32
1705 11:52:06.316724 [Byte1]: 32
1706 11:52:06.316807
1707 11:52:06.320351 Set Vref, RX VrefLevel [Byte0]: 33
1708 11:52:06.323271 [Byte1]: 33
1709 11:52:06.326468
1710 11:52:06.326551 Set Vref, RX VrefLevel [Byte0]: 34
1711 11:52:06.329999 [Byte1]: 34
1712 11:52:06.333980
1713 11:52:06.334083 Set Vref, RX VrefLevel [Byte0]: 35
1714 11:52:06.338189 [Byte1]: 35
1715 11:52:06.342555
1716 11:52:06.342627 Set Vref, RX VrefLevel [Byte0]: 36
1717 11:52:06.345030 [Byte1]: 36
1718 11:52:06.349249
1719 11:52:06.349349 Set Vref, RX VrefLevel [Byte0]: 37
1720 11:52:06.352612 [Byte1]: 37
1721 11:52:06.357116
1722 11:52:06.357214 Set Vref, RX VrefLevel [Byte0]: 38
1723 11:52:06.360670 [Byte1]: 38
1724 11:52:06.364612
1725 11:52:06.364684 Set Vref, RX VrefLevel [Byte0]: 39
1726 11:52:06.367849 [Byte1]: 39
1727 11:52:06.372135
1728 11:52:06.372231 Set Vref, RX VrefLevel [Byte0]: 40
1729 11:52:06.378841 [Byte1]: 40
1730 11:52:06.378914
1731 11:52:06.381909 Set Vref, RX VrefLevel [Byte0]: 41
1732 11:52:06.385406 [Byte1]: 41
1733 11:52:06.385501
1734 11:52:06.388371 Set Vref, RX VrefLevel [Byte0]: 42
1735 11:52:06.392220 [Byte1]: 42
1736 11:52:06.395394
1737 11:52:06.395469 Set Vref, RX VrefLevel [Byte0]: 43
1738 11:52:06.398587 [Byte1]: 43
1739 11:52:06.402758
1740 11:52:06.402828 Set Vref, RX VrefLevel [Byte0]: 44
1741 11:52:06.406407 [Byte1]: 44
1742 11:52:06.410204
1743 11:52:06.410339 Set Vref, RX VrefLevel [Byte0]: 45
1744 11:52:06.413737 [Byte1]: 45
1745 11:52:06.417702
1746 11:52:06.417774 Set Vref, RX VrefLevel [Byte0]: 46
1747 11:52:06.421307 [Byte1]: 46
1748 11:52:06.425378
1749 11:52:06.425473 Set Vref, RX VrefLevel [Byte0]: 47
1750 11:52:06.428782 [Byte1]: 47
1751 11:52:06.432900
1752 11:52:06.432970 Set Vref, RX VrefLevel [Byte0]: 48
1753 11:52:06.436600 [Byte1]: 48
1754 11:52:06.440724
1755 11:52:06.440795 Set Vref, RX VrefLevel [Byte0]: 49
1756 11:52:06.443831 [Byte1]: 49
1757 11:52:06.448370
1758 11:52:06.448466 Set Vref, RX VrefLevel [Byte0]: 50
1759 11:52:06.451435 [Byte1]: 50
1760 11:52:06.456067
1761 11:52:06.456135 Set Vref, RX VrefLevel [Byte0]: 51
1762 11:52:06.459192 [Byte1]: 51
1763 11:52:06.463542
1764 11:52:06.463620 Set Vref, RX VrefLevel [Byte0]: 52
1765 11:52:06.466437 [Byte1]: 52
1766 11:52:06.471064
1767 11:52:06.471180 Set Vref, RX VrefLevel [Byte0]: 53
1768 11:52:06.474147 [Byte1]: 53
1769 11:52:06.478656
1770 11:52:06.478727 Set Vref, RX VrefLevel [Byte0]: 54
1771 11:52:06.481992 [Byte1]: 54
1772 11:52:06.485984
1773 11:52:06.486080 Set Vref, RX VrefLevel [Byte0]: 55
1774 11:52:06.489391 [Byte1]: 55
1775 11:52:06.494054
1776 11:52:06.494156 Set Vref, RX VrefLevel [Byte0]: 56
1777 11:52:06.496905 [Byte1]: 56
1778 11:52:06.501371
1779 11:52:06.501461 Set Vref, RX VrefLevel [Byte0]: 57
1780 11:52:06.504665 [Byte1]: 57
1781 11:52:06.509247
1782 11:52:06.509320 Set Vref, RX VrefLevel [Byte0]: 58
1783 11:52:06.512473 [Byte1]: 58
1784 11:52:06.516554
1785 11:52:06.516660 Set Vref, RX VrefLevel [Byte0]: 59
1786 11:52:06.520272 [Byte1]: 59
1787 11:52:06.524104
1788 11:52:06.524201 Set Vref, RX VrefLevel [Byte0]: 60
1789 11:52:06.527359 [Byte1]: 60
1790 11:52:06.531767
1791 11:52:06.531837 Set Vref, RX VrefLevel [Byte0]: 61
1792 11:52:06.535286 [Byte1]: 61
1793 11:52:06.539579
1794 11:52:06.539675 Set Vref, RX VrefLevel [Byte0]: 62
1795 11:52:06.542421 [Byte1]: 62
1796 11:52:06.546916
1797 11:52:06.546985 Set Vref, RX VrefLevel [Byte0]: 63
1798 11:52:06.550507 [Byte1]: 63
1799 11:52:06.554502
1800 11:52:06.554571 Set Vref, RX VrefLevel [Byte0]: 64
1801 11:52:06.557869 [Byte1]: 64
1802 11:52:06.562452
1803 11:52:06.562548 Set Vref, RX VrefLevel [Byte0]: 65
1804 11:52:06.565607 [Byte1]: 65
1805 11:52:06.569838
1806 11:52:06.569944 Set Vref, RX VrefLevel [Byte0]: 66
1807 11:52:06.573223 [Byte1]: 66
1808 11:52:06.577283
1809 11:52:06.577360 Set Vref, RX VrefLevel [Byte0]: 67
1810 11:52:06.580652 [Byte1]: 67
1811 11:52:06.584791
1812 11:52:06.584886 Set Vref, RX VrefLevel [Byte0]: 68
1813 11:52:06.588250 [Byte1]: 68
1814 11:52:06.592577
1815 11:52:06.592673 Set Vref, RX VrefLevel [Byte0]: 69
1816 11:52:06.596160 [Byte1]: 69
1817 11:52:06.600501
1818 11:52:06.600575 Set Vref, RX VrefLevel [Byte0]: 70
1819 11:52:06.603752 [Byte1]: 70
1820 11:52:06.607660
1821 11:52:06.607761 Set Vref, RX VrefLevel [Byte0]: 71
1822 11:52:06.611100 [Byte1]: 71
1823 11:52:06.615472
1824 11:52:06.615547 Set Vref, RX VrefLevel [Byte0]: 72
1825 11:52:06.618742 [Byte1]: 72
1826 11:52:06.622770
1827 11:52:06.622867 Set Vref, RX VrefLevel [Byte0]: 73
1828 11:52:06.626660 [Byte1]: 73
1829 11:52:06.630704
1830 11:52:06.630800 Final RX Vref Byte 0 = 61 to rank0
1831 11:52:06.633654 Final RX Vref Byte 1 = 54 to rank0
1832 11:52:06.637190 Final RX Vref Byte 0 = 61 to rank1
1833 11:52:06.640754 Final RX Vref Byte 1 = 54 to rank1==
1834 11:52:06.644002 Dram Type= 6, Freq= 0, CH_1, rank 0
1835 11:52:06.650238 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1836 11:52:06.650380 ==
1837 11:52:06.650470 DQS Delay:
1838 11:52:06.653660 DQS0 = 0, DQS1 = 0
1839 11:52:06.653761 DQM Delay:
1840 11:52:06.653848 DQM0 = 86, DQM1 = 80
1841 11:52:06.656752 DQ Delay:
1842 11:52:06.660503 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1843 11:52:06.663571 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =80
1844 11:52:06.666880 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1845 11:52:06.670425 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =88
1846 11:52:06.670498
1847 11:52:06.670567
1848 11:52:06.677111 [DQSOSCAuto] RK0, (LSB)MR18= 0x1f33, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
1849 11:52:06.680097 CH1 RK0: MR19=606, MR18=1F33
1850 11:52:06.686830 CH1_RK0: MR19=0x606, MR18=0x1F33, DQSOSC=396, MR23=63, INC=94, DEC=62
1851 11:52:06.686908
1852 11:52:06.690470 ----->DramcWriteLeveling(PI) begin...
1853 11:52:06.690544 ==
1854 11:52:06.693731 Dram Type= 6, Freq= 0, CH_1, rank 1
1855 11:52:06.696587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1856 11:52:06.696668 ==
1857 11:52:06.699892 Write leveling (Byte 0): 27 => 27
1858 11:52:06.703574 Write leveling (Byte 1): 28 => 28
1859 11:52:06.707052 DramcWriteLeveling(PI) end<-----
1860 11:52:06.707125
1861 11:52:06.707189 ==
1862 11:52:06.709876 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 11:52:06.713392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 11:52:06.713472 ==
1865 11:52:06.716748 [Gating] SW mode calibration
1866 11:52:06.723393 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1867 11:52:06.729909 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1868 11:52:06.733334 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1869 11:52:06.736828 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1870 11:52:06.743703 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1871 11:52:06.746776 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:52:06.749895 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:52:06.756809 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:52:06.759956 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:52:06.763670 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:52:06.769836 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:52:06.773653 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:52:06.776556 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:52:06.782968 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:52:06.786466 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:52:06.790063 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:52:06.796529 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:52:06.799884 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1884 11:52:06.802857 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1885 11:52:06.809550 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1886 11:52:06.812996 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:52:06.816196 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:52:06.822797 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:52:06.825984 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:52:06.829560 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 11:52:06.835907 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:52:06.839331 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:52:06.842382 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1894 11:52:06.849141 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1895 11:52:06.852933 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:52:06.855573 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:52:06.862743 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1898 11:52:06.865497 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 11:52:06.868931 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 11:52:06.875543 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
1901 11:52:06.878461 0 10 4 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (1 1)
1902 11:52:06.882069 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
1903 11:52:06.888657 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:52:06.891849 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:52:06.895148 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:52:06.901765 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 11:52:06.904982 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 11:52:06.908611 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:52:06.915000 0 11 4 | B1->B0 | 2a2a 4040 | 0 0 | (1 1) (0 0)
1910 11:52:06.918425 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (1 1) (0 0)
1911 11:52:06.921459 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:52:06.928199 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:52:06.931563 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:52:06.935007 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:52:06.941485 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 11:52:06.945239 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1917 11:52:06.947883 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1918 11:52:06.954964 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:52:06.958087 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:52:06.961683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:52:06.968001 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:52:06.970922 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:52:06.974384 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:52:06.981092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:52:06.984738 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:52:06.987358 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:52:06.994413 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:52:06.997641 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:52:07.000705 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:52:07.007398 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 11:52:07.010574 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 11:52:07.014062 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 11:52:07.020501 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1934 11:52:07.023922 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:52:07.027261 Total UI for P1: 0, mck2ui 16
1936 11:52:07.030720 best dqsien dly found for B0: ( 0, 14, 4)
1937 11:52:07.033697 Total UI for P1: 0, mck2ui 16
1938 11:52:07.037005 best dqsien dly found for B1: ( 0, 14, 6)
1939 11:52:07.040560 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1940 11:52:07.043618 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1941 11:52:07.043696
1942 11:52:07.046793 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1943 11:52:07.050088 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1944 11:52:07.053418 [Gating] SW calibration Done
1945 11:52:07.053489 ==
1946 11:52:07.057003 Dram Type= 6, Freq= 0, CH_1, rank 1
1947 11:52:07.060402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1948 11:52:07.063199 ==
1949 11:52:07.063277 RX Vref Scan: 0
1950 11:52:07.063339
1951 11:52:07.066933 RX Vref 0 -> 0, step: 1
1952 11:52:07.067002
1953 11:52:07.070155 RX Delay -130 -> 252, step: 16
1954 11:52:07.073181 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1955 11:52:07.076755 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1956 11:52:07.080204 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1957 11:52:07.083205 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1958 11:52:07.089526 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1959 11:52:07.093027 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1960 11:52:07.096255 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1961 11:52:07.099796 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1962 11:52:07.102910 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1963 11:52:07.110049 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1964 11:52:07.112913 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1965 11:52:07.116171 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1966 11:52:07.119862 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1967 11:52:07.126062 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1968 11:52:07.129767 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1969 11:52:07.132961 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1970 11:52:07.133042 ==
1971 11:52:07.136737 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 11:52:07.139275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 11:52:07.139345 ==
1974 11:52:07.142844 DQS Delay:
1975 11:52:07.142924 DQS0 = 0, DQS1 = 0
1976 11:52:07.143003 DQM Delay:
1977 11:52:07.146070 DQM0 = 83, DQM1 = 79
1978 11:52:07.146144 DQ Delay:
1979 11:52:07.149303 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =77
1980 11:52:07.152934 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =85
1981 11:52:07.155936 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1982 11:52:07.159190 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1983 11:52:07.159266
1984 11:52:07.159328
1985 11:52:07.159386 ==
1986 11:52:07.162768 Dram Type= 6, Freq= 0, CH_1, rank 1
1987 11:52:07.169526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1988 11:52:07.169599 ==
1989 11:52:07.169661
1990 11:52:07.169718
1991 11:52:07.169779 TX Vref Scan disable
1992 11:52:07.172914 == TX Byte 0 ==
1993 11:52:07.176526 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1994 11:52:07.179966 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1995 11:52:07.183538 == TX Byte 1 ==
1996 11:52:07.186656 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1997 11:52:07.192974 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1998 11:52:07.193051 ==
1999 11:52:07.196652 Dram Type= 6, Freq= 0, CH_1, rank 1
2000 11:52:07.199522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2001 11:52:07.199604 ==
2002 11:52:07.212041 TX Vref=22, minBit 1, minWin=27, winSum=447
2003 11:52:07.215667 TX Vref=24, minBit 0, minWin=28, winSum=453
2004 11:52:07.219075 TX Vref=26, minBit 0, minWin=28, winSum=453
2005 11:52:07.222099 TX Vref=28, minBit 0, minWin=28, winSum=454
2006 11:52:07.225441 TX Vref=30, minBit 5, minWin=27, winSum=454
2007 11:52:07.232408 TX Vref=32, minBit 1, minWin=27, winSum=453
2008 11:52:07.235463 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 28
2009 11:52:07.235545
2010 11:52:07.239437 Final TX Range 1 Vref 28
2011 11:52:07.239514
2012 11:52:07.239596 ==
2013 11:52:07.242723 Dram Type= 6, Freq= 0, CH_1, rank 1
2014 11:52:07.245134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2015 11:52:07.245235 ==
2016 11:52:07.248487
2017 11:52:07.248565
2018 11:52:07.248648 TX Vref Scan disable
2019 11:52:07.251977 == TX Byte 0 ==
2020 11:52:07.255207 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2021 11:52:07.269051 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2022 11:52:07.269134 == TX Byte 1 ==
2023 11:52:07.269403 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2024 11:52:07.272067 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2025 11:52:07.272145
2026 11:52:07.272234 [DATLAT]
2027 11:52:07.272311 Freq=800, CH1 RK1
2028 11:52:07.272406
2029 11:52:07.275365 DATLAT Default: 0xa
2030 11:52:07.275451 0, 0xFFFF, sum = 0
2031 11:52:07.279079 1, 0xFFFF, sum = 0
2032 11:52:07.279185 2, 0xFFFF, sum = 0
2033 11:52:07.282446 3, 0xFFFF, sum = 0
2034 11:52:07.282524 4, 0xFFFF, sum = 0
2035 11:52:07.285269 5, 0xFFFF, sum = 0
2036 11:52:07.288668 6, 0xFFFF, sum = 0
2037 11:52:07.288745 7, 0xFFFF, sum = 0
2038 11:52:07.292233 8, 0xFFFF, sum = 0
2039 11:52:07.292315 9, 0x0, sum = 1
2040 11:52:07.292397 10, 0x0, sum = 2
2041 11:52:07.295292 11, 0x0, sum = 3
2042 11:52:07.295368 12, 0x0, sum = 4
2043 11:52:07.298621 best_step = 10
2044 11:52:07.298699
2045 11:52:07.298780 ==
2046 11:52:07.301970 Dram Type= 6, Freq= 0, CH_1, rank 1
2047 11:52:07.305526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2048 11:52:07.305607 ==
2049 11:52:07.308986 RX Vref Scan: 0
2050 11:52:07.309092
2051 11:52:07.309170 RX Vref 0 -> 0, step: 1
2052 11:52:07.309254
2053 11:52:07.311769 RX Delay -95 -> 252, step: 8
2054 11:52:07.318725 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2055 11:52:07.321747 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2056 11:52:07.325656 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2057 11:52:07.328935 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2058 11:52:07.331813 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2059 11:52:07.338432 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2060 11:52:07.342150 iDelay=209, Bit 6, Center 92 (-23 ~ 208) 232
2061 11:52:07.345108 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2062 11:52:07.348772 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2063 11:52:07.351566 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2064 11:52:07.358379 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2065 11:52:07.361717 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2066 11:52:07.365290 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2067 11:52:07.368487 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2068 11:52:07.374874 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2069 11:52:07.378441 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2070 11:52:07.378523 ==
2071 11:52:07.382058 Dram Type= 6, Freq= 0, CH_1, rank 1
2072 11:52:07.385278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2073 11:52:07.385362 ==
2074 11:52:07.388222 DQS Delay:
2075 11:52:07.388305 DQS0 = 0, DQS1 = 0
2076 11:52:07.388391 DQM Delay:
2077 11:52:07.391565 DQM0 = 85, DQM1 = 81
2078 11:52:07.391642 DQ Delay:
2079 11:52:07.395006 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2080 11:52:07.398045 DQ4 =84, DQ5 =96, DQ6 =92, DQ7 =84
2081 11:52:07.401491 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =76
2082 11:52:07.405077 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2083 11:52:07.405159
2084 11:52:07.405240
2085 11:52:07.415401 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2086 11:52:07.415490 CH1 RK1: MR19=606, MR18=1D38
2087 11:52:07.421466 CH1_RK1: MR19=0x606, MR18=0x1D38, DQSOSC=395, MR23=63, INC=94, DEC=63
2088 11:52:07.424736 [RxdqsGatingPostProcess] freq 800
2089 11:52:07.431705 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2090 11:52:07.434629 Pre-setting of DQS Precalculation
2091 11:52:07.438181 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2092 11:52:07.444702 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2093 11:52:07.454718 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2094 11:52:07.454801
2095 11:52:07.454893
2096 11:52:07.457875 [Calibration Summary] 1600 Mbps
2097 11:52:07.457954 CH 0, Rank 0
2098 11:52:07.461656 SW Impedance : PASS
2099 11:52:07.461762 DUTY Scan : NO K
2100 11:52:07.464496 ZQ Calibration : PASS
2101 11:52:07.468289 Jitter Meter : NO K
2102 11:52:07.468376 CBT Training : PASS
2103 11:52:07.471362 Write leveling : PASS
2104 11:52:07.471441 RX DQS gating : PASS
2105 11:52:07.474669 RX DQ/DQS(RDDQC) : PASS
2106 11:52:07.477543 TX DQ/DQS : PASS
2107 11:52:07.477630 RX DATLAT : PASS
2108 11:52:07.481086 RX DQ/DQS(Engine): PASS
2109 11:52:07.484231 TX OE : NO K
2110 11:52:07.484315 All Pass.
2111 11:52:07.484414
2112 11:52:07.484492 CH 0, Rank 1
2113 11:52:07.487647 SW Impedance : PASS
2114 11:52:07.491233 DUTY Scan : NO K
2115 11:52:07.491347 ZQ Calibration : PASS
2116 11:52:07.494735 Jitter Meter : NO K
2117 11:52:07.497532 CBT Training : PASS
2118 11:52:07.497617 Write leveling : PASS
2119 11:52:07.500951 RX DQS gating : PASS
2120 11:52:07.503989 RX DQ/DQS(RDDQC) : PASS
2121 11:52:07.504065 TX DQ/DQS : PASS
2122 11:52:07.507609 RX DATLAT : PASS
2123 11:52:07.511054 RX DQ/DQS(Engine): PASS
2124 11:52:07.511142 TX OE : NO K
2125 11:52:07.514028 All Pass.
2126 11:52:07.514103
2127 11:52:07.514212 CH 1, Rank 0
2128 11:52:07.517431 SW Impedance : PASS
2129 11:52:07.517504 DUTY Scan : NO K
2130 11:52:07.520989 ZQ Calibration : PASS
2131 11:52:07.523876 Jitter Meter : NO K
2132 11:52:07.523959 CBT Training : PASS
2133 11:52:07.527351 Write leveling : PASS
2134 11:52:07.527427 RX DQS gating : PASS
2135 11:52:07.530590 RX DQ/DQS(RDDQC) : PASS
2136 11:52:07.534127 TX DQ/DQS : PASS
2137 11:52:07.534234 RX DATLAT : PASS
2138 11:52:07.537907 RX DQ/DQS(Engine): PASS
2139 11:52:07.540927 TX OE : NO K
2140 11:52:07.541003 All Pass.
2141 11:52:07.541084
2142 11:52:07.541165 CH 1, Rank 1
2143 11:52:07.544314 SW Impedance : PASS
2144 11:52:07.547533 DUTY Scan : NO K
2145 11:52:07.547626 ZQ Calibration : PASS
2146 11:52:07.550665 Jitter Meter : NO K
2147 11:52:07.554211 CBT Training : PASS
2148 11:52:07.554347 Write leveling : PASS
2149 11:52:07.557221 RX DQS gating : PASS
2150 11:52:07.560884 RX DQ/DQS(RDDQC) : PASS
2151 11:52:07.560965 TX DQ/DQS : PASS
2152 11:52:07.563895 RX DATLAT : PASS
2153 11:52:07.567578 RX DQ/DQS(Engine): PASS
2154 11:52:07.567664 TX OE : NO K
2155 11:52:07.567743 All Pass.
2156 11:52:07.570698
2157 11:52:07.570774 DramC Write-DBI off
2158 11:52:07.574480 PER_BANK_REFRESH: Hybrid Mode
2159 11:52:07.574589 TX_TRACKING: ON
2160 11:52:07.577233 [GetDramInforAfterCalByMRR] Vendor 6.
2161 11:52:07.580894 [GetDramInforAfterCalByMRR] Revision 606.
2162 11:52:07.587214 [GetDramInforAfterCalByMRR] Revision 2 0.
2163 11:52:07.587291 MR0 0x3b3b
2164 11:52:07.587360 MR8 0x5151
2165 11:52:07.590633 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2166 11:52:07.590707
2167 11:52:07.593904 MR0 0x3b3b
2168 11:52:07.593981 MR8 0x5151
2169 11:52:07.597078 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2170 11:52:07.597157
2171 11:52:07.606911 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2172 11:52:07.610577 [FAST_K] Save calibration result to emmc
2173 11:52:07.613774 [FAST_K] Save calibration result to emmc
2174 11:52:07.617242 dram_init: config_dvfs: 1
2175 11:52:07.620269 dramc_set_vcore_voltage set vcore to 662500
2176 11:52:07.624024 Read voltage for 1200, 2
2177 11:52:07.624099 Vio18 = 0
2178 11:52:07.624163 Vcore = 662500
2179 11:52:07.627047 Vdram = 0
2180 11:52:07.627140 Vddq = 0
2181 11:52:07.627207 Vmddr = 0
2182 11:52:07.633977 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2183 11:52:07.637207 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2184 11:52:07.640664 MEM_TYPE=3, freq_sel=15
2185 11:52:07.644233 sv_algorithm_assistance_LP4_1600
2186 11:52:07.646956 ============ PULL DRAM RESETB DOWN ============
2187 11:52:07.650481 ========== PULL DRAM RESETB DOWN end =========
2188 11:52:07.657314 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2189 11:52:07.660572 ===================================
2190 11:52:07.660649 LPDDR4 DRAM CONFIGURATION
2191 11:52:07.663923 ===================================
2192 11:52:07.667119 EX_ROW_EN[0] = 0x0
2193 11:52:07.670608 EX_ROW_EN[1] = 0x0
2194 11:52:07.670685 LP4Y_EN = 0x0
2195 11:52:07.673768 WORK_FSP = 0x0
2196 11:52:07.673838 WL = 0x4
2197 11:52:07.676931 RL = 0x4
2198 11:52:07.677021 BL = 0x2
2199 11:52:07.680145 RPST = 0x0
2200 11:52:07.680219 RD_PRE = 0x0
2201 11:52:07.683549 WR_PRE = 0x1
2202 11:52:07.683618 WR_PST = 0x0
2203 11:52:07.686806 DBI_WR = 0x0
2204 11:52:07.686877 DBI_RD = 0x0
2205 11:52:07.690670 OTF = 0x1
2206 11:52:07.693804 ===================================
2207 11:52:07.696549 ===================================
2208 11:52:07.696626 ANA top config
2209 11:52:07.699933 ===================================
2210 11:52:07.703365 DLL_ASYNC_EN = 0
2211 11:52:07.706689 ALL_SLAVE_EN = 0
2212 11:52:07.710646 NEW_RANK_MODE = 1
2213 11:52:07.710719 DLL_IDLE_MODE = 1
2214 11:52:07.713441 LP45_APHY_COMB_EN = 1
2215 11:52:07.716768 TX_ODT_DIS = 1
2216 11:52:07.720275 NEW_8X_MODE = 1
2217 11:52:07.723208 ===================================
2218 11:52:07.726658 ===================================
2219 11:52:07.729990 data_rate = 2400
2220 11:52:07.730061 CKR = 1
2221 11:52:07.733544 DQ_P2S_RATIO = 8
2222 11:52:07.736529 ===================================
2223 11:52:07.740136 CA_P2S_RATIO = 8
2224 11:52:07.743822 DQ_CA_OPEN = 0
2225 11:52:07.746671 DQ_SEMI_OPEN = 0
2226 11:52:07.746745 CA_SEMI_OPEN = 0
2227 11:52:07.749952 CA_FULL_RATE = 0
2228 11:52:07.753326 DQ_CKDIV4_EN = 0
2229 11:52:07.756679 CA_CKDIV4_EN = 0
2230 11:52:07.760074 CA_PREDIV_EN = 0
2231 11:52:07.762908 PH8_DLY = 17
2232 11:52:07.763022 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2233 11:52:07.766284 DQ_AAMCK_DIV = 4
2234 11:52:07.769826 CA_AAMCK_DIV = 4
2235 11:52:07.773313 CA_ADMCK_DIV = 4
2236 11:52:07.776413 DQ_TRACK_CA_EN = 0
2237 11:52:07.779785 CA_PICK = 1200
2238 11:52:07.783454 CA_MCKIO = 1200
2239 11:52:07.783542 MCKIO_SEMI = 0
2240 11:52:07.786737 PLL_FREQ = 2366
2241 11:52:07.790368 DQ_UI_PI_RATIO = 32
2242 11:52:07.793185 CA_UI_PI_RATIO = 0
2243 11:52:07.796793 ===================================
2244 11:52:07.800252 ===================================
2245 11:52:07.803233 memory_type:LPDDR4
2246 11:52:07.803315 GP_NUM : 10
2247 11:52:07.806857 SRAM_EN : 1
2248 11:52:07.809677 MD32_EN : 0
2249 11:52:07.813434 ===================================
2250 11:52:07.813534 [ANA_INIT] >>>>>>>>>>>>>>
2251 11:52:07.816612 <<<<<< [CONFIGURE PHASE]: ANA_TX
2252 11:52:07.819601 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2253 11:52:07.823191 ===================================
2254 11:52:07.826220 data_rate = 2400,PCW = 0X5b00
2255 11:52:07.829539 ===================================
2256 11:52:07.832903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2257 11:52:07.839955 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2258 11:52:07.842731 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2259 11:52:07.849584 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2260 11:52:07.853408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2261 11:52:07.856033 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2262 11:52:07.856118 [ANA_INIT] flow start
2263 11:52:07.859386 [ANA_INIT] PLL >>>>>>>>
2264 11:52:07.862937 [ANA_INIT] PLL <<<<<<<<
2265 11:52:07.866298 [ANA_INIT] MIDPI >>>>>>>>
2266 11:52:07.866375 [ANA_INIT] MIDPI <<<<<<<<
2267 11:52:07.869322 [ANA_INIT] DLL >>>>>>>>
2268 11:52:07.872593 [ANA_INIT] DLL <<<<<<<<
2269 11:52:07.872668 [ANA_INIT] flow end
2270 11:52:07.876095 ============ LP4 DIFF to SE enter ============
2271 11:52:07.882667 ============ LP4 DIFF to SE exit ============
2272 11:52:07.882749 [ANA_INIT] <<<<<<<<<<<<<
2273 11:52:07.885956 [Flow] Enable top DCM control >>>>>
2274 11:52:07.889281 [Flow] Enable top DCM control <<<<<
2275 11:52:07.892517 Enable DLL master slave shuffle
2276 11:52:07.899777 ==============================================================
2277 11:52:07.899865 Gating Mode config
2278 11:52:07.906224 ==============================================================
2279 11:52:07.909689 Config description:
2280 11:52:07.919564 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2281 11:52:07.925968 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2282 11:52:07.929616 SELPH_MODE 0: By rank 1: By Phase
2283 11:52:07.936297 ==============================================================
2284 11:52:07.939203 GAT_TRACK_EN = 1
2285 11:52:07.939284 RX_GATING_MODE = 2
2286 11:52:07.942832 RX_GATING_TRACK_MODE = 2
2287 11:52:07.946132 SELPH_MODE = 1
2288 11:52:07.949094 PICG_EARLY_EN = 1
2289 11:52:07.952615 VALID_LAT_VALUE = 1
2290 11:52:07.958822 ==============================================================
2291 11:52:07.962747 Enter into Gating configuration >>>>
2292 11:52:07.965840 Exit from Gating configuration <<<<
2293 11:52:07.969183 Enter into DVFS_PRE_config >>>>>
2294 11:52:07.978946 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2295 11:52:07.982369 Exit from DVFS_PRE_config <<<<<
2296 11:52:07.985584 Enter into PICG configuration >>>>
2297 11:52:07.988979 Exit from PICG configuration <<<<
2298 11:52:07.992337 [RX_INPUT] configuration >>>>>
2299 11:52:07.995558 [RX_INPUT] configuration <<<<<
2300 11:52:07.999287 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2301 11:52:08.005987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2302 11:52:08.012309 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2303 11:52:08.015754 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2304 11:52:08.022340 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2305 11:52:08.029345 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2306 11:52:08.032573 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2307 11:52:08.035529 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2308 11:52:08.041903 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2309 11:52:08.045322 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2310 11:52:08.049168 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2311 11:52:08.055928 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2312 11:52:08.058676 ===================================
2313 11:52:08.058751 LPDDR4 DRAM CONFIGURATION
2314 11:52:08.062061 ===================================
2315 11:52:08.065668 EX_ROW_EN[0] = 0x0
2316 11:52:08.068727 EX_ROW_EN[1] = 0x0
2317 11:52:08.068797 LP4Y_EN = 0x0
2318 11:52:08.072159 WORK_FSP = 0x0
2319 11:52:08.072241 WL = 0x4
2320 11:52:08.075369 RL = 0x4
2321 11:52:08.075444 BL = 0x2
2322 11:52:08.078320 RPST = 0x0
2323 11:52:08.078433 RD_PRE = 0x0
2324 11:52:08.081841 WR_PRE = 0x1
2325 11:52:08.081915 WR_PST = 0x0
2326 11:52:08.085051 DBI_WR = 0x0
2327 11:52:08.085121 DBI_RD = 0x0
2328 11:52:08.088240 OTF = 0x1
2329 11:52:08.091692 ===================================
2330 11:52:08.095165 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2331 11:52:08.098285 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2332 11:52:08.105185 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 11:52:08.108247 ===================================
2334 11:52:08.108319 LPDDR4 DRAM CONFIGURATION
2335 11:52:08.111857 ===================================
2336 11:52:08.115130 EX_ROW_EN[0] = 0x10
2337 11:52:08.118369 EX_ROW_EN[1] = 0x0
2338 11:52:08.118444 LP4Y_EN = 0x0
2339 11:52:08.121290 WORK_FSP = 0x0
2340 11:52:08.121373 WL = 0x4
2341 11:52:08.124909 RL = 0x4
2342 11:52:08.125010 BL = 0x2
2343 11:52:08.128204 RPST = 0x0
2344 11:52:08.128280 RD_PRE = 0x0
2345 11:52:08.131382 WR_PRE = 0x1
2346 11:52:08.131465 WR_PST = 0x0
2347 11:52:08.134831 DBI_WR = 0x0
2348 11:52:08.134937 DBI_RD = 0x0
2349 11:52:08.138059 OTF = 0x1
2350 11:52:08.141609 ===================================
2351 11:52:08.147962 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2352 11:52:08.148044 ==
2353 11:52:08.151186 Dram Type= 6, Freq= 0, CH_0, rank 0
2354 11:52:08.154563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2355 11:52:08.154648 ==
2356 11:52:08.157994 [Duty_Offset_Calibration]
2357 11:52:08.158076 B0:2 B1:0 CA:4
2358 11:52:08.158142
2359 11:52:08.161508 [DutyScan_Calibration_Flow] k_type=0
2360 11:52:08.171433
2361 11:52:08.171521 ==CLK 0==
2362 11:52:08.175016 Final CLK duty delay cell = 0
2363 11:52:08.178324 [0] MAX Duty = 5156%(X100), DQS PI = 14
2364 11:52:08.181233 [0] MIN Duty = 5000%(X100), DQS PI = 8
2365 11:52:08.181313 [0] AVG Duty = 5078%(X100)
2366 11:52:08.184608
2367 11:52:08.187838 CH0 CLK Duty spec in!! Max-Min= 156%
2368 11:52:08.191398 [DutyScan_Calibration_Flow] ====Done====
2369 11:52:08.191479
2370 11:52:08.194595 [DutyScan_Calibration_Flow] k_type=1
2371 11:52:08.210960
2372 11:52:08.211042 ==DQS 0 ==
2373 11:52:08.213735 Final DQS duty delay cell = 0
2374 11:52:08.217672 [0] MAX Duty = 5156%(X100), DQS PI = 20
2375 11:52:08.220638 [0] MIN Duty = 5093%(X100), DQS PI = 2
2376 11:52:08.224275 [0] AVG Duty = 5124%(X100)
2377 11:52:08.224354
2378 11:52:08.224414 ==DQS 1 ==
2379 11:52:08.227160 Final DQS duty delay cell = 0
2380 11:52:08.230564 [0] MAX Duty = 5125%(X100), DQS PI = 52
2381 11:52:08.233758 [0] MIN Duty = 5000%(X100), DQS PI = 0
2382 11:52:08.233830 [0] AVG Duty = 5062%(X100)
2383 11:52:08.237265
2384 11:52:08.240671 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2385 11:52:08.240742
2386 11:52:08.243770 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2387 11:52:08.247218 [DutyScan_Calibration_Flow] ====Done====
2388 11:52:08.247288
2389 11:52:08.250569 [DutyScan_Calibration_Flow] k_type=3
2390 11:52:08.267202
2391 11:52:08.267278 ==DQM 0 ==
2392 11:52:08.270556 Final DQM duty delay cell = 0
2393 11:52:08.273478 [0] MAX Duty = 5125%(X100), DQS PI = 20
2394 11:52:08.277164 [0] MIN Duty = 4876%(X100), DQS PI = 54
2395 11:52:08.280103 [0] AVG Duty = 5000%(X100)
2396 11:52:08.280179
2397 11:52:08.280242 ==DQM 1 ==
2398 11:52:08.284126 Final DQM duty delay cell = 0
2399 11:52:08.286870 [0] MAX Duty = 4969%(X100), DQS PI = 2
2400 11:52:08.289984 [0] MIN Duty = 4875%(X100), DQS PI = 18
2401 11:52:08.293768 [0] AVG Duty = 4922%(X100)
2402 11:52:08.293848
2403 11:52:08.296649 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2404 11:52:08.296727
2405 11:52:08.300325 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2406 11:52:08.303813 [DutyScan_Calibration_Flow] ====Done====
2407 11:52:08.303885
2408 11:52:08.306521 [DutyScan_Calibration_Flow] k_type=2
2409 11:52:08.323716
2410 11:52:08.323797 ==DQ 0 ==
2411 11:52:08.326790 Final DQ duty delay cell = 0
2412 11:52:08.329900 [0] MAX Duty = 5125%(X100), DQS PI = 18
2413 11:52:08.333297 [0] MIN Duty = 4969%(X100), DQS PI = 38
2414 11:52:08.333376 [0] AVG Duty = 5047%(X100)
2415 11:52:08.336737
2416 11:52:08.336820 ==DQ 1 ==
2417 11:52:08.340162 Final DQ duty delay cell = 0
2418 11:52:08.343654 [0] MAX Duty = 5156%(X100), DQS PI = 6
2419 11:52:08.346693 [0] MIN Duty = 4938%(X100), DQS PI = 16
2420 11:52:08.346766 [0] AVG Duty = 5047%(X100)
2421 11:52:08.346829
2422 11:52:08.349954 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2423 11:52:08.350031
2424 11:52:08.356924 CH0 DQ 1 Duty spec in!! Max-Min= 218%
2425 11:52:08.360168 [DutyScan_Calibration_Flow] ====Done====
2426 11:52:08.360250 ==
2427 11:52:08.363857 Dram Type= 6, Freq= 0, CH_1, rank 0
2428 11:52:08.366850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2429 11:52:08.366926 ==
2430 11:52:08.370327 [Duty_Offset_Calibration]
2431 11:52:08.370413 B0:0 B1:-1 CA:3
2432 11:52:08.370477
2433 11:52:08.373753 [DutyScan_Calibration_Flow] k_type=0
2434 11:52:08.382751
2435 11:52:08.382834 ==CLK 0==
2436 11:52:08.386082 Final CLK duty delay cell = -4
2437 11:52:08.389390 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2438 11:52:08.392406 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2439 11:52:08.395955 [-4] AVG Duty = 4938%(X100)
2440 11:52:08.396069
2441 11:52:08.399399 CH1 CLK Duty spec in!! Max-Min= 124%
2442 11:52:08.402336 [DutyScan_Calibration_Flow] ====Done====
2443 11:52:08.402423
2444 11:52:08.406409 [DutyScan_Calibration_Flow] k_type=1
2445 11:52:08.422322
2446 11:52:08.422399 ==DQS 0 ==
2447 11:52:08.425651 Final DQS duty delay cell = 0
2448 11:52:08.429151 [0] MAX Duty = 5187%(X100), DQS PI = 18
2449 11:52:08.432021 [0] MIN Duty = 4907%(X100), DQS PI = 38
2450 11:52:08.435479 [0] AVG Duty = 5047%(X100)
2451 11:52:08.435590
2452 11:52:08.435681 ==DQS 1 ==
2453 11:52:08.439211 Final DQS duty delay cell = 0
2454 11:52:08.442161 [0] MAX Duty = 5156%(X100), DQS PI = 8
2455 11:52:08.445428 [0] MIN Duty = 5031%(X100), DQS PI = 18
2456 11:52:08.448697 [0] AVG Duty = 5093%(X100)
2457 11:52:08.448776
2458 11:52:08.452030 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2459 11:52:08.452108
2460 11:52:08.455616 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2461 11:52:08.458623 [DutyScan_Calibration_Flow] ====Done====
2462 11:52:08.458694
2463 11:52:08.462080 [DutyScan_Calibration_Flow] k_type=3
2464 11:52:08.478766
2465 11:52:08.478874 ==DQM 0 ==
2466 11:52:08.482174 Final DQM duty delay cell = 0
2467 11:52:08.485922 [0] MAX Duty = 5031%(X100), DQS PI = 26
2468 11:52:08.488469 [0] MIN Duty = 4813%(X100), DQS PI = 38
2469 11:52:08.491919 [0] AVG Duty = 4922%(X100)
2470 11:52:08.492006
2471 11:52:08.492107 ==DQM 1 ==
2472 11:52:08.495616 Final DQM duty delay cell = 0
2473 11:52:08.499076 [0] MAX Duty = 5000%(X100), DQS PI = 34
2474 11:52:08.502318 [0] MIN Duty = 4844%(X100), DQS PI = 0
2475 11:52:08.505332 [0] AVG Duty = 4922%(X100)
2476 11:52:08.505439
2477 11:52:08.509077 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2478 11:52:08.509160
2479 11:52:08.512291 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2480 11:52:08.515438 [DutyScan_Calibration_Flow] ====Done====
2481 11:52:08.515516
2482 11:52:08.518432 [DutyScan_Calibration_Flow] k_type=2
2483 11:52:08.534545
2484 11:52:08.534644 ==DQ 0 ==
2485 11:52:08.538255 Final DQ duty delay cell = -4
2486 11:52:08.540982 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2487 11:52:08.544471 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2488 11:52:08.547932 [-4] AVG Duty = 4922%(X100)
2489 11:52:08.548046
2490 11:52:08.548141 ==DQ 1 ==
2491 11:52:08.551003 Final DQ duty delay cell = 0
2492 11:52:08.554468 [0] MAX Duty = 5031%(X100), DQS PI = 34
2493 11:52:08.558029 [0] MIN Duty = 4844%(X100), DQS PI = 62
2494 11:52:08.560924 [0] AVG Duty = 4937%(X100)
2495 11:52:08.561029
2496 11:52:08.564531 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2497 11:52:08.564614
2498 11:52:08.567971 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2499 11:52:08.570720 [DutyScan_Calibration_Flow] ====Done====
2500 11:52:08.574290 nWR fixed to 30
2501 11:52:08.577744 [ModeRegInit_LP4] CH0 RK0
2502 11:52:08.577826 [ModeRegInit_LP4] CH0 RK1
2503 11:52:08.580921 [ModeRegInit_LP4] CH1 RK0
2504 11:52:08.584311 [ModeRegInit_LP4] CH1 RK1
2505 11:52:08.584393 match AC timing 7
2506 11:52:08.591245 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2507 11:52:08.594273 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2508 11:52:08.597894 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2509 11:52:08.604443 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2510 11:52:08.608246 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2511 11:52:08.608332 ==
2512 11:52:08.610780 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:52:08.614240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:52:08.614363 ==
2515 11:52:08.620974 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2516 11:52:08.627656 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2517 11:52:08.634763 [CA 0] Center 39 (9~70) winsize 62
2518 11:52:08.638461 [CA 1] Center 39 (9~70) winsize 62
2519 11:52:08.641992 [CA 2] Center 35 (5~66) winsize 62
2520 11:52:08.645428 [CA 3] Center 35 (5~66) winsize 62
2521 11:52:08.648864 [CA 4] Center 33 (3~64) winsize 62
2522 11:52:08.652241 [CA 5] Center 33 (3~63) winsize 61
2523 11:52:08.652666
2524 11:52:08.655253 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2525 11:52:08.655678
2526 11:52:08.658814 [CATrainingPosCal] consider 1 rank data
2527 11:52:08.661668 u2DelayCellTimex100 = 270/100 ps
2528 11:52:08.664987 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2529 11:52:08.668659 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2530 11:52:08.675087 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2531 11:52:08.678552 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2532 11:52:08.681682 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2533 11:52:08.684883 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2534 11:52:08.685417
2535 11:52:08.688214 CA PerBit enable=1, Macro0, CA PI delay=33
2536 11:52:08.688639
2537 11:52:08.691380 [CBTSetCACLKResult] CA Dly = 33
2538 11:52:08.691806 CS Dly: 7 (0~38)
2539 11:52:08.694973 ==
2540 11:52:08.697908 Dram Type= 6, Freq= 0, CH_0, rank 1
2541 11:52:08.701478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2542 11:52:08.701905 ==
2543 11:52:08.704603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2544 11:52:08.711626 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2545 11:52:08.721058 [CA 0] Center 39 (9~70) winsize 62
2546 11:52:08.724300 [CA 1] Center 39 (9~70) winsize 62
2547 11:52:08.727579 [CA 2] Center 35 (5~66) winsize 62
2548 11:52:08.731104 [CA 3] Center 35 (5~66) winsize 62
2549 11:52:08.733946 [CA 4] Center 34 (3~65) winsize 63
2550 11:52:08.737515 [CA 5] Center 33 (3~63) winsize 61
2551 11:52:08.737937
2552 11:52:08.740987 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2553 11:52:08.741410
2554 11:52:08.744678 [CATrainingPosCal] consider 2 rank data
2555 11:52:08.747587 u2DelayCellTimex100 = 270/100 ps
2556 11:52:08.750885 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2557 11:52:08.757452 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2558 11:52:08.760808 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2559 11:52:08.763823 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2560 11:52:08.767324 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2561 11:52:08.770560 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2562 11:52:08.770984
2563 11:52:08.774201 CA PerBit enable=1, Macro0, CA PI delay=33
2564 11:52:08.774688
2565 11:52:08.777383 [CBTSetCACLKResult] CA Dly = 33
2566 11:52:08.777811 CS Dly: 8 (0~41)
2567 11:52:08.778150
2568 11:52:08.781088 ----->DramcWriteLeveling(PI) begin...
2569 11:52:08.784393 ==
2570 11:52:08.787423 Dram Type= 6, Freq= 0, CH_0, rank 0
2571 11:52:08.790715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2572 11:52:08.791136 ==
2573 11:52:08.793841 Write leveling (Byte 0): 33 => 33
2574 11:52:08.797329 Write leveling (Byte 1): 26 => 26
2575 11:52:08.800908 DramcWriteLeveling(PI) end<-----
2576 11:52:08.801362
2577 11:52:08.801700 ==
2578 11:52:08.803995 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 11:52:08.807593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 11:52:08.808022 ==
2581 11:52:08.810429 [Gating] SW mode calibration
2582 11:52:08.817204 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2583 11:52:08.823804 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2584 11:52:08.826983 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2585 11:52:08.830673 0 15 4 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
2586 11:52:08.836968 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:52:08.840444 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2588 11:52:08.843567 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2589 11:52:08.850394 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 11:52:08.853700 0 15 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
2591 11:52:08.856572 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2592 11:52:08.863202 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
2593 11:52:08.866816 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2594 11:52:08.870295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:52:08.873596 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2596 11:52:08.880557 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 11:52:08.883573 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 11:52:08.887023 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 1)
2599 11:52:08.893422 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2600 11:52:08.896641 1 1 0 | B1->B0 | 2e2d 4646 | 1 0 | (0 0) (0 0)
2601 11:52:08.900244 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 11:52:08.906563 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:52:08.910793 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:52:08.913315 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 11:52:08.919915 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 11:52:08.923185 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:52:08.926352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2608 11:52:08.933316 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2609 11:52:08.936734 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:52:08.939969 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:52:08.946666 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:52:08.950122 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:52:08.953091 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:52:08.960202 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:52:08.963376 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:52:08.966089 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:52:08.973309 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:52:08.976322 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:52:08.979836 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 11:52:08.986275 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 11:52:08.989810 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 11:52:08.993318 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2623 11:52:08.999447 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2624 11:52:08.999882 Total UI for P1: 0, mck2ui 16
2625 11:52:09.006435 best dqsien dly found for B0: ( 1, 3, 24)
2626 11:52:09.009512 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2627 11:52:09.012906 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 11:52:09.016531 Total UI for P1: 0, mck2ui 16
2629 11:52:09.019332 best dqsien dly found for B1: ( 1, 4, 0)
2630 11:52:09.022791 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2631 11:52:09.026313 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2632 11:52:09.026732
2633 11:52:09.029255 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2634 11:52:09.036099 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2635 11:52:09.036516 [Gating] SW calibration Done
2636 11:52:09.036886 ==
2637 11:52:09.039661 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 11:52:09.045850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 11:52:09.046303 ==
2640 11:52:09.046648 RX Vref Scan: 0
2641 11:52:09.046962
2642 11:52:09.049056 RX Vref 0 -> 0, step: 1
2643 11:52:09.049471
2644 11:52:09.052795 RX Delay -40 -> 252, step: 8
2645 11:52:09.056062 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2646 11:52:09.059428 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2647 11:52:09.062846 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2648 11:52:09.068998 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2649 11:52:09.072595 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2650 11:52:09.075983 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2651 11:52:09.079361 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2652 11:52:09.082300 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
2653 11:52:09.088947 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2654 11:52:09.092269 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2655 11:52:09.095791 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2656 11:52:09.099185 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2657 11:52:09.102029 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2658 11:52:09.109130 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2659 11:52:09.112276 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2660 11:52:09.115465 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2661 11:52:09.115942 ==
2662 11:52:09.118645 Dram Type= 6, Freq= 0, CH_0, rank 0
2663 11:52:09.122177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2664 11:52:09.122659 ==
2665 11:52:09.125869 DQS Delay:
2666 11:52:09.126367 DQS0 = 0, DQS1 = 0
2667 11:52:09.129063 DQM Delay:
2668 11:52:09.129479 DQM0 = 119, DQM1 = 107
2669 11:52:09.129841 DQ Delay:
2670 11:52:09.135374 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2671 11:52:09.139029 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2672 11:52:09.142530 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2673 11:52:09.145690 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2674 11:52:09.146145
2675 11:52:09.146561
2676 11:52:09.146878 ==
2677 11:52:09.149105 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 11:52:09.152190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 11:52:09.152607 ==
2680 11:52:09.152981
2681 11:52:09.153287
2682 11:52:09.155584 TX Vref Scan disable
2683 11:52:09.158679 == TX Byte 0 ==
2684 11:52:09.162325 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2685 11:52:09.165459 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2686 11:52:09.168595 == TX Byte 1 ==
2687 11:52:09.172440 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2688 11:52:09.175510 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2689 11:52:09.175971 ==
2690 11:52:09.178906 Dram Type= 6, Freq= 0, CH_0, rank 0
2691 11:52:09.182490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2692 11:52:09.182935 ==
2693 11:52:09.196114 TX Vref=22, minBit 4, minWin=25, winSum=414
2694 11:52:09.198937 TX Vref=24, minBit 10, minWin=25, winSum=421
2695 11:52:09.202318 TX Vref=26, minBit 1, minWin=26, winSum=421
2696 11:52:09.205674 TX Vref=28, minBit 1, minWin=26, winSum=431
2697 11:52:09.208917 TX Vref=30, minBit 5, minWin=26, winSum=431
2698 11:52:09.215610 TX Vref=32, minBit 8, minWin=26, winSum=433
2699 11:52:09.218998 [TxChooseVref] Worse bit 8, Min win 26, Win sum 433, Final Vref 32
2700 11:52:09.219459
2701 11:52:09.222297 Final TX Range 1 Vref 32
2702 11:52:09.222737
2703 11:52:09.223174 ==
2704 11:52:09.225275 Dram Type= 6, Freq= 0, CH_0, rank 0
2705 11:52:09.228660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2706 11:52:09.231913 ==
2707 11:52:09.232349
2708 11:52:09.232724
2709 11:52:09.233375 TX Vref Scan disable
2710 11:52:09.235296 == TX Byte 0 ==
2711 11:52:09.238643 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2712 11:52:09.245772 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2713 11:52:09.246379 == TX Byte 1 ==
2714 11:52:09.248865 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2715 11:52:09.255320 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2716 11:52:09.255743
2717 11:52:09.256081 [DATLAT]
2718 11:52:09.256398 Freq=1200, CH0 RK0
2719 11:52:09.256701
2720 11:52:09.258779 DATLAT Default: 0xd
2721 11:52:09.259201 0, 0xFFFF, sum = 0
2722 11:52:09.262205 1, 0xFFFF, sum = 0
2723 11:52:09.262678 2, 0xFFFF, sum = 0
2724 11:52:09.265869 3, 0xFFFF, sum = 0
2725 11:52:09.268820 4, 0xFFFF, sum = 0
2726 11:52:09.269250 5, 0xFFFF, sum = 0
2727 11:52:09.272001 6, 0xFFFF, sum = 0
2728 11:52:09.272433 7, 0xFFFF, sum = 0
2729 11:52:09.275461 8, 0xFFFF, sum = 0
2730 11:52:09.275894 9, 0xFFFF, sum = 0
2731 11:52:09.278819 10, 0xFFFF, sum = 0
2732 11:52:09.279250 11, 0xFFFF, sum = 0
2733 11:52:09.281981 12, 0x0, sum = 1
2734 11:52:09.282652 13, 0x0, sum = 2
2735 11:52:09.285576 14, 0x0, sum = 3
2736 11:52:09.286006 15, 0x0, sum = 4
2737 11:52:09.288815 best_step = 13
2738 11:52:09.289235
2739 11:52:09.289569 ==
2740 11:52:09.291985 Dram Type= 6, Freq= 0, CH_0, rank 0
2741 11:52:09.295347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2742 11:52:09.295774 ==
2743 11:52:09.296116 RX Vref Scan: 1
2744 11:52:09.296433
2745 11:52:09.298600 Set Vref Range= 32 -> 127
2746 11:52:09.299030
2747 11:52:09.301780 RX Vref 32 -> 127, step: 1
2748 11:52:09.302468
2749 11:52:09.305286 RX Delay -21 -> 252, step: 4
2750 11:52:09.305804
2751 11:52:09.308383 Set Vref, RX VrefLevel [Byte0]: 32
2752 11:52:09.311794 [Byte1]: 32
2753 11:52:09.312217
2754 11:52:09.315397 Set Vref, RX VrefLevel [Byte0]: 33
2755 11:52:09.318618 [Byte1]: 33
2756 11:52:09.322099
2757 11:52:09.322582 Set Vref, RX VrefLevel [Byte0]: 34
2758 11:52:09.325345 [Byte1]: 34
2759 11:52:09.329999
2760 11:52:09.330461 Set Vref, RX VrefLevel [Byte0]: 35
2761 11:52:09.333202 [Byte1]: 35
2762 11:52:09.338045
2763 11:52:09.338532 Set Vref, RX VrefLevel [Byte0]: 36
2764 11:52:09.341104 [Byte1]: 36
2765 11:52:09.345650
2766 11:52:09.346085 Set Vref, RX VrefLevel [Byte0]: 37
2767 11:52:09.349426 [Byte1]: 37
2768 11:52:09.353721
2769 11:52:09.354144 Set Vref, RX VrefLevel [Byte0]: 38
2770 11:52:09.357070 [Byte1]: 38
2771 11:52:09.361871
2772 11:52:09.362312 Set Vref, RX VrefLevel [Byte0]: 39
2773 11:52:09.365270 [Byte1]: 39
2774 11:52:09.369737
2775 11:52:09.370157 Set Vref, RX VrefLevel [Byte0]: 40
2776 11:52:09.373239 [Byte1]: 40
2777 11:52:09.377661
2778 11:52:09.378080 Set Vref, RX VrefLevel [Byte0]: 41
2779 11:52:09.381058 [Byte1]: 41
2780 11:52:09.385288
2781 11:52:09.385704 Set Vref, RX VrefLevel [Byte0]: 42
2782 11:52:09.388697 [Byte1]: 42
2783 11:52:09.393175
2784 11:52:09.393591 Set Vref, RX VrefLevel [Byte0]: 43
2785 11:52:09.396659 [Byte1]: 43
2786 11:52:09.401072
2787 11:52:09.401490 Set Vref, RX VrefLevel [Byte0]: 44
2788 11:52:09.405119 [Byte1]: 44
2789 11:52:09.409196
2790 11:52:09.409612 Set Vref, RX VrefLevel [Byte0]: 45
2791 11:52:09.412263 [Byte1]: 45
2792 11:52:09.416989
2793 11:52:09.417406 Set Vref, RX VrefLevel [Byte0]: 46
2794 11:52:09.420487 [Byte1]: 46
2795 11:52:09.425329
2796 11:52:09.425748 Set Vref, RX VrefLevel [Byte0]: 47
2797 11:52:09.428363 [Byte1]: 47
2798 11:52:09.432744
2799 11:52:09.433179 Set Vref, RX VrefLevel [Byte0]: 48
2800 11:52:09.436294 [Byte1]: 48
2801 11:52:09.440908
2802 11:52:09.441396 Set Vref, RX VrefLevel [Byte0]: 49
2803 11:52:09.444207 [Byte1]: 49
2804 11:52:09.449113
2805 11:52:09.449531 Set Vref, RX VrefLevel [Byte0]: 50
2806 11:52:09.452494 [Byte1]: 50
2807 11:52:09.456830
2808 11:52:09.457251 Set Vref, RX VrefLevel [Byte0]: 51
2809 11:52:09.459959 [Byte1]: 51
2810 11:52:09.465047
2811 11:52:09.465468 Set Vref, RX VrefLevel [Byte0]: 52
2812 11:52:09.468271 [Byte1]: 52
2813 11:52:09.472949
2814 11:52:09.473366 Set Vref, RX VrefLevel [Byte0]: 53
2815 11:52:09.475740 [Byte1]: 53
2816 11:52:09.480853
2817 11:52:09.481270 Set Vref, RX VrefLevel [Byte0]: 54
2818 11:52:09.483671 [Byte1]: 54
2819 11:52:09.488357
2820 11:52:09.488836 Set Vref, RX VrefLevel [Byte0]: 55
2821 11:52:09.491803 [Byte1]: 55
2822 11:52:09.496807
2823 11:52:09.497224 Set Vref, RX VrefLevel [Byte0]: 56
2824 11:52:09.499915 [Byte1]: 56
2825 11:52:09.504197
2826 11:52:09.504614 Set Vref, RX VrefLevel [Byte0]: 57
2827 11:52:09.507513 [Byte1]: 57
2828 11:52:09.512203
2829 11:52:09.512649 Set Vref, RX VrefLevel [Byte0]: 58
2830 11:52:09.515481 [Byte1]: 58
2831 11:52:09.520259
2832 11:52:09.520689 Set Vref, RX VrefLevel [Byte0]: 59
2833 11:52:09.523591 [Byte1]: 59
2834 11:52:09.528010
2835 11:52:09.528441 Set Vref, RX VrefLevel [Byte0]: 60
2836 11:52:09.531434 [Byte1]: 60
2837 11:52:09.535806
2838 11:52:09.536241 Set Vref, RX VrefLevel [Byte0]: 61
2839 11:52:09.539433 [Byte1]: 61
2840 11:52:09.544177
2841 11:52:09.544609 Set Vref, RX VrefLevel [Byte0]: 62
2842 11:52:09.547007 [Byte1]: 62
2843 11:52:09.552054
2844 11:52:09.552483 Set Vref, RX VrefLevel [Byte0]: 63
2845 11:52:09.555239 [Byte1]: 63
2846 11:52:09.559905
2847 11:52:09.560336 Set Vref, RX VrefLevel [Byte0]: 64
2848 11:52:09.563543 [Byte1]: 64
2849 11:52:09.567867
2850 11:52:09.568322 Set Vref, RX VrefLevel [Byte0]: 65
2851 11:52:09.570818 [Byte1]: 65
2852 11:52:09.575613
2853 11:52:09.576044 Set Vref, RX VrefLevel [Byte0]: 66
2854 11:52:09.579303 [Byte1]: 66
2855 11:52:09.583821
2856 11:52:09.584251 Set Vref, RX VrefLevel [Byte0]: 67
2857 11:52:09.586685 [Byte1]: 67
2858 11:52:09.591243
2859 11:52:09.591676 Set Vref, RX VrefLevel [Byte0]: 68
2860 11:52:09.594741 [Byte1]: 68
2861 11:52:09.599546
2862 11:52:09.599975 Final RX Vref Byte 0 = 58 to rank0
2863 11:52:09.603009 Final RX Vref Byte 1 = 49 to rank0
2864 11:52:09.606102 Final RX Vref Byte 0 = 58 to rank1
2865 11:52:09.609840 Final RX Vref Byte 1 = 49 to rank1==
2866 11:52:09.612419 Dram Type= 6, Freq= 0, CH_0, rank 0
2867 11:52:09.619641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 11:52:09.620076 ==
2869 11:52:09.620519 DQS Delay:
2870 11:52:09.622381 DQS0 = 0, DQS1 = 0
2871 11:52:09.622816 DQM Delay:
2872 11:52:09.623255 DQM0 = 119, DQM1 = 106
2873 11:52:09.625903 DQ Delay:
2874 11:52:09.629090 DQ0 =118, DQ1 =118, DQ2 =116, DQ3 =116
2875 11:52:09.632671 DQ4 =122, DQ5 =114, DQ6 =128, DQ7 =122
2876 11:52:09.636095 DQ8 =96, DQ9 =92, DQ10 =106, DQ11 =100
2877 11:52:09.639302 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =114
2878 11:52:09.639735
2879 11:52:09.640176
2880 11:52:09.646001 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2881 11:52:09.648971 CH0 RK0: MR19=403, MR18=3FE
2882 11:52:09.655987 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2883 11:52:09.656418
2884 11:52:09.658875 ----->DramcWriteLeveling(PI) begin...
2885 11:52:09.659314 ==
2886 11:52:09.662473 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 11:52:09.665572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 11:52:09.668930 ==
2889 11:52:09.669353 Write leveling (Byte 0): 31 => 31
2890 11:52:09.672302 Write leveling (Byte 1): 26 => 26
2891 11:52:09.675685 DramcWriteLeveling(PI) end<-----
2892 11:52:09.676343
2893 11:52:09.676716 ==
2894 11:52:09.679300 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:52:09.685518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:52:09.685947 ==
2897 11:52:09.686442 [Gating] SW mode calibration
2898 11:52:09.695549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2899 11:52:09.699033 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2900 11:52:09.705437 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2901 11:52:09.708826 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2902 11:52:09.712254 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 11:52:09.715510 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 11:52:09.721891 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:52:09.725740 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2906 11:52:09.728978 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2907 11:52:09.735858 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2908 11:52:09.739156 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
2909 11:52:09.742096 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 11:52:09.748879 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 11:52:09.752619 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:52:09.755629 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:52:09.762395 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:52:09.765685 1 0 24 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
2915 11:52:09.768866 1 0 28 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2916 11:52:09.775702 1 1 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2917 11:52:09.778651 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 11:52:09.781926 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 11:52:09.788874 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:52:09.792123 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:52:09.795200 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:52:09.801514 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2923 11:52:09.805024 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2924 11:52:09.808633 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:52:09.815153 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:52:09.818080 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:52:09.821646 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:52:09.827871 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:52:09.831556 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:52:09.834957 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:52:09.841368 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:52:09.844845 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:52:09.848268 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:52:09.854753 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:52:09.858360 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:52:09.861679 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:52:09.867860 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2938 11:52:09.872043 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2939 11:52:09.874676 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2940 11:52:09.878125 Total UI for P1: 0, mck2ui 16
2941 11:52:09.881767 best dqsien dly found for B0: ( 1, 3, 22)
2942 11:52:09.884467 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2943 11:52:09.891351 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:52:09.894709 Total UI for P1: 0, mck2ui 16
2945 11:52:09.898205 best dqsien dly found for B1: ( 1, 3, 30)
2946 11:52:09.901083 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
2947 11:52:09.904767 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2948 11:52:09.905201
2949 11:52:09.907793 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
2950 11:52:09.911186 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2951 11:52:09.914552 [Gating] SW calibration Done
2952 11:52:09.914967 ==
2953 11:52:09.918414 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 11:52:09.921043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 11:52:09.921586 ==
2956 11:52:09.924598 RX Vref Scan: 0
2957 11:52:09.925026
2958 11:52:09.927972 RX Vref 0 -> 0, step: 1
2959 11:52:09.928404
2960 11:52:09.928771 RX Delay -40 -> 252, step: 8
2961 11:52:09.934210 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
2962 11:52:09.937712 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2963 11:52:09.941160 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2964 11:52:09.944654 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2965 11:52:09.947827 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2966 11:52:09.954287 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2967 11:52:09.957760 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2968 11:52:09.961414 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2969 11:52:09.964066 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2970 11:52:09.967536 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2971 11:52:09.974448 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2972 11:52:09.977505 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2973 11:52:09.980992 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2974 11:52:09.984071 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2975 11:52:09.987765 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2976 11:52:09.994145 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2977 11:52:09.994623 ==
2978 11:52:09.997287 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:52:10.000955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:52:10.001409 ==
2981 11:52:10.001751 DQS Delay:
2982 11:52:10.004352 DQS0 = 0, DQS1 = 0
2983 11:52:10.004776 DQM Delay:
2984 11:52:10.007587 DQM0 = 118, DQM1 = 106
2985 11:52:10.008169 DQ Delay:
2986 11:52:10.010629 DQ0 =115, DQ1 =119, DQ2 =115, DQ3 =115
2987 11:52:10.013942 DQ4 =123, DQ5 =107, DQ6 =127, DQ7 =127
2988 11:52:10.017227 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2989 11:52:10.020909 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2990 11:52:10.021333
2991 11:52:10.021668
2992 11:52:10.024206 ==
2993 11:52:10.027531 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 11:52:10.030457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 11:52:10.031038 ==
2996 11:52:10.031395
2997 11:52:10.031717
2998 11:52:10.033661 TX Vref Scan disable
2999 11:52:10.034016 == TX Byte 0 ==
3000 11:52:10.037416 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3001 11:52:10.044080 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3002 11:52:10.044582 == TX Byte 1 ==
3003 11:52:10.047520 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3004 11:52:10.053755 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3005 11:52:10.054182 ==
3006 11:52:10.057480 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 11:52:10.060866 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 11:52:10.061393 ==
3009 11:52:10.072865 TX Vref=22, minBit 1, minWin=25, winSum=413
3010 11:52:10.076379 TX Vref=24, minBit 2, minWin=25, winSum=415
3011 11:52:10.079539 TX Vref=26, minBit 5, minWin=25, winSum=424
3012 11:52:10.082819 TX Vref=28, minBit 0, minWin=26, winSum=423
3013 11:52:10.086145 TX Vref=30, minBit 4, minWin=26, winSum=427
3014 11:52:10.092546 TX Vref=32, minBit 5, minWin=25, winSum=425
3015 11:52:10.096269 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 30
3016 11:52:10.096694
3017 11:52:10.099577 Final TX Range 1 Vref 30
3018 11:52:10.100004
3019 11:52:10.100345 ==
3020 11:52:10.103110 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 11:52:10.105861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 11:52:10.106443 ==
3023 11:52:10.109263
3024 11:52:10.109733
3025 11:52:10.110081 TX Vref Scan disable
3026 11:52:10.112636 == TX Byte 0 ==
3027 11:52:10.116125 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3028 11:52:10.119809 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3029 11:52:10.122550 == TX Byte 1 ==
3030 11:52:10.125906 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3031 11:52:10.132963 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3032 11:52:10.133538
3033 11:52:10.133906 [DATLAT]
3034 11:52:10.134224 Freq=1200, CH0 RK1
3035 11:52:10.134731
3036 11:52:10.136436 DATLAT Default: 0xd
3037 11:52:10.136875 0, 0xFFFF, sum = 0
3038 11:52:10.139167 1, 0xFFFF, sum = 0
3039 11:52:10.142612 2, 0xFFFF, sum = 0
3040 11:52:10.143031 3, 0xFFFF, sum = 0
3041 11:52:10.145772 4, 0xFFFF, sum = 0
3042 11:52:10.146340 5, 0xFFFF, sum = 0
3043 11:52:10.148993 6, 0xFFFF, sum = 0
3044 11:52:10.149420 7, 0xFFFF, sum = 0
3045 11:52:10.152720 8, 0xFFFF, sum = 0
3046 11:52:10.153170 9, 0xFFFF, sum = 0
3047 11:52:10.156177 10, 0xFFFF, sum = 0
3048 11:52:10.156711 11, 0xFFFF, sum = 0
3049 11:52:10.159086 12, 0x0, sum = 1
3050 11:52:10.159612 13, 0x0, sum = 2
3051 11:52:10.162707 14, 0x0, sum = 3
3052 11:52:10.163233 15, 0x0, sum = 4
3053 11:52:10.166324 best_step = 13
3054 11:52:10.166748
3055 11:52:10.167129 ==
3056 11:52:10.169012 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 11:52:10.172773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 11:52:10.173294 ==
3059 11:52:10.173640 RX Vref Scan: 0
3060 11:52:10.175687
3061 11:52:10.176108 RX Vref 0 -> 0, step: 1
3062 11:52:10.176450
3063 11:52:10.179085 RX Delay -21 -> 252, step: 4
3064 11:52:10.185702 iDelay=195, Bit 0, Center 116 (51 ~ 182) 132
3065 11:52:10.189461 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3066 11:52:10.192050 iDelay=195, Bit 2, Center 114 (51 ~ 178) 128
3067 11:52:10.195445 iDelay=195, Bit 3, Center 114 (51 ~ 178) 128
3068 11:52:10.198969 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3069 11:52:10.202153 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3070 11:52:10.208818 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3071 11:52:10.212229 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3072 11:52:10.215427 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3073 11:52:10.218828 iDelay=195, Bit 9, Center 94 (27 ~ 162) 136
3074 11:52:10.222073 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3075 11:52:10.228882 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3076 11:52:10.231923 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3077 11:52:10.235629 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3078 11:52:10.238245 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3079 11:52:10.245259 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3080 11:52:10.245907 ==
3081 11:52:10.248669 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:52:10.251738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:52:10.252155 ==
3084 11:52:10.252508 DQS Delay:
3085 11:52:10.255356 DQS0 = 0, DQS1 = 0
3086 11:52:10.256008 DQM Delay:
3087 11:52:10.258307 DQM0 = 118, DQM1 = 106
3088 11:52:10.258784 DQ Delay:
3089 11:52:10.261573 DQ0 =116, DQ1 =120, DQ2 =114, DQ3 =114
3090 11:52:10.265004 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =122
3091 11:52:10.268041 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =98
3092 11:52:10.271678 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3093 11:52:10.272124
3094 11:52:10.272461
3095 11:52:10.281366 [DQSOSCAuto] RK1, (LSB)MR18= 0xfefb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
3096 11:52:10.285246 CH0 RK1: MR19=303, MR18=FEFB
3097 11:52:10.288913 CH0_RK1: MR19=0x303, MR18=0xFEFB, DQSOSC=410, MR23=63, INC=39, DEC=26
3098 11:52:10.291517 [RxdqsGatingPostProcess] freq 1200
3099 11:52:10.298635 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3100 11:52:10.301716 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 11:52:10.305334 best DQS1 dly(2T, 0.5T) = (0, 12)
3102 11:52:10.308295 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 11:52:10.311688 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3104 11:52:10.315039 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 11:52:10.318286 best DQS1 dly(2T, 0.5T) = (0, 11)
3106 11:52:10.321249 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 11:52:10.324888 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3108 11:52:10.325476 Pre-setting of DQS Precalculation
3109 11:52:10.331689 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3110 11:52:10.332114 ==
3111 11:52:10.334814 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 11:52:10.338431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:52:10.338861 ==
3114 11:52:10.344825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 11:52:10.351123 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3116 11:52:10.358927 [CA 0] Center 38 (8~68) winsize 61
3117 11:52:10.362732 [CA 1] Center 37 (7~68) winsize 62
3118 11:52:10.365345 [CA 2] Center 35 (5~65) winsize 61
3119 11:52:10.368649 [CA 3] Center 34 (4~64) winsize 61
3120 11:52:10.372120 [CA 4] Center 34 (4~65) winsize 62
3121 11:52:10.375665 [CA 5] Center 33 (3~63) winsize 61
3122 11:52:10.376130
3123 11:52:10.378928 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3124 11:52:10.379482
3125 11:52:10.382040 [CATrainingPosCal] consider 1 rank data
3126 11:52:10.385692 u2DelayCellTimex100 = 270/100 ps
3127 11:52:10.388890 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3128 11:52:10.395483 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 11:52:10.398935 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3130 11:52:10.402293 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 11:52:10.405619 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3132 11:52:10.408623 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3133 11:52:10.409049
3134 11:52:10.412301 CA PerBit enable=1, Macro0, CA PI delay=33
3135 11:52:10.412723
3136 11:52:10.415601 [CBTSetCACLKResult] CA Dly = 33
3137 11:52:10.416259 CS Dly: 4 (0~35)
3138 11:52:10.418934 ==
3139 11:52:10.421967 Dram Type= 6, Freq= 0, CH_1, rank 1
3140 11:52:10.425235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 11:52:10.425662 ==
3142 11:52:10.428608 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 11:52:10.434909 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3144 11:52:10.444785 [CA 0] Center 37 (7~68) winsize 62
3145 11:52:10.448289 [CA 1] Center 38 (7~69) winsize 63
3146 11:52:10.451407 [CA 2] Center 34 (4~65) winsize 62
3147 11:52:10.454426 [CA 3] Center 33 (3~64) winsize 62
3148 11:52:10.457800 [CA 4] Center 34 (4~64) winsize 61
3149 11:52:10.461306 [CA 5] Center 33 (3~64) winsize 62
3150 11:52:10.461823
3151 11:52:10.464436 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3152 11:52:10.464860
3153 11:52:10.467505 [CATrainingPosCal] consider 2 rank data
3154 11:52:10.471028 u2DelayCellTimex100 = 270/100 ps
3155 11:52:10.474368 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3156 11:52:10.480735 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 11:52:10.484493 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3158 11:52:10.487616 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 11:52:10.491024 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3160 11:52:10.494581 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3161 11:52:10.495019
3162 11:52:10.497756 CA PerBit enable=1, Macro0, CA PI delay=33
3163 11:52:10.498169
3164 11:52:10.500687 [CBTSetCACLKResult] CA Dly = 33
3165 11:52:10.501295 CS Dly: 6 (0~39)
3166 11:52:10.501667
3167 11:52:10.507514 ----->DramcWriteLeveling(PI) begin...
3168 11:52:10.507938 ==
3169 11:52:10.511166 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 11:52:10.513986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 11:52:10.514439 ==
3172 11:52:10.517775 Write leveling (Byte 0): 25 => 25
3173 11:52:10.520720 Write leveling (Byte 1): 26 => 26
3174 11:52:10.524488 DramcWriteLeveling(PI) end<-----
3175 11:52:10.525028
3176 11:52:10.525369 ==
3177 11:52:10.527714 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:52:10.530829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:52:10.531262 ==
3180 11:52:10.534566 [Gating] SW mode calibration
3181 11:52:10.540790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3182 11:52:10.547703 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3183 11:52:10.551627 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3184 11:52:10.554066 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 11:52:10.560797 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 11:52:10.564176 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:52:10.567588 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:52:10.570581 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:52:10.577292 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
3190 11:52:10.580709 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
3191 11:52:10.583852 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 11:52:10.590871 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 11:52:10.593928 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:52:10.597234 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:52:10.604016 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:52:10.607464 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:52:10.610479 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3198 11:52:10.617310 1 0 28 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
3199 11:52:10.620710 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 11:52:10.623839 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 11:52:10.630492 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:52:10.633786 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:52:10.637588 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:52:10.644216 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:52:10.646862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 11:52:10.650968 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3207 11:52:10.657473 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:52:10.660553 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:52:10.663946 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:52:10.670699 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:52:10.674024 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:52:10.676857 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:52:10.684093 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:52:10.686784 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:52:10.690200 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:52:10.696846 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:52:10.700390 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:52:10.703218 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:52:10.706685 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:52:10.713291 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 11:52:10.716644 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3222 11:52:10.720191 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 11:52:10.726621 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:52:10.730279 Total UI for P1: 0, mck2ui 16
3225 11:52:10.733228 best dqsien dly found for B0: ( 1, 3, 26)
3226 11:52:10.736727 Total UI for P1: 0, mck2ui 16
3227 11:52:10.740179 best dqsien dly found for B1: ( 1, 3, 28)
3228 11:52:10.743042 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3229 11:52:10.746711 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3230 11:52:10.747130
3231 11:52:10.749646 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3232 11:52:10.753320 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3233 11:52:10.756748 [Gating] SW calibration Done
3234 11:52:10.757117 ==
3235 11:52:10.759714 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 11:52:10.762925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 11:52:10.763324 ==
3238 11:52:10.766606 RX Vref Scan: 0
3239 11:52:10.766967
3240 11:52:10.767343 RX Vref 0 -> 0, step: 1
3241 11:52:10.769562
3242 11:52:10.769961 RX Delay -40 -> 252, step: 8
3243 11:52:10.776356 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3244 11:52:10.779725 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3245 11:52:10.783202 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3246 11:52:10.786484 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3247 11:52:10.789452 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3248 11:52:10.796248 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3249 11:52:10.799649 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3250 11:52:10.802898 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3251 11:52:10.806335 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3252 11:52:10.809345 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3253 11:52:10.813270 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3254 11:52:10.819603 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3255 11:52:10.823153 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3256 11:52:10.826054 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3257 11:52:10.829617 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3258 11:52:10.836059 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3259 11:52:10.836170 ==
3260 11:52:10.840087 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 11:52:10.842455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 11:52:10.842569 ==
3263 11:52:10.842665 DQS Delay:
3264 11:52:10.846779 DQS0 = 0, DQS1 = 0
3265 11:52:10.846885 DQM Delay:
3266 11:52:10.849214 DQM0 = 115, DQM1 = 112
3267 11:52:10.849295 DQ Delay:
3268 11:52:10.852675 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3269 11:52:10.856304 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3270 11:52:10.859525 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3271 11:52:10.862807 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3272 11:52:10.862889
3273 11:52:10.862954
3274 11:52:10.865686 ==
3275 11:52:10.869204 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 11:52:10.872259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 11:52:10.872368 ==
3278 11:52:10.872467
3279 11:52:10.872565
3280 11:52:10.875854 TX Vref Scan disable
3281 11:52:10.875936 == TX Byte 0 ==
3282 11:52:10.879276 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3283 11:52:10.885505 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3284 11:52:10.885588 == TX Byte 1 ==
3285 11:52:10.892180 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3286 11:52:10.895570 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3287 11:52:10.895665 ==
3288 11:52:10.899078 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 11:52:10.902513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 11:52:10.902616 ==
3291 11:52:10.914228 TX Vref=22, minBit 9, minWin=23, winSum=409
3292 11:52:10.917546 TX Vref=24, minBit 9, minWin=24, winSum=416
3293 11:52:10.921116 TX Vref=26, minBit 9, minWin=24, winSum=419
3294 11:52:10.924214 TX Vref=28, minBit 8, minWin=25, winSum=422
3295 11:52:10.927400 TX Vref=30, minBit 9, minWin=25, winSum=426
3296 11:52:10.934351 TX Vref=32, minBit 9, minWin=25, winSum=423
3297 11:52:10.937347 [TxChooseVref] Worse bit 9, Min win 25, Win sum 426, Final Vref 30
3298 11:52:10.937597
3299 11:52:10.941199 Final TX Range 1 Vref 30
3300 11:52:10.941505
3301 11:52:10.941746 ==
3302 11:52:10.944046 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 11:52:10.947776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 11:52:10.948086 ==
3305 11:52:10.948341
3306 11:52:10.951166
3307 11:52:10.951467 TX Vref Scan disable
3308 11:52:10.954055 == TX Byte 0 ==
3309 11:52:10.957439 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3310 11:52:10.960729 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3311 11:52:10.963792 == TX Byte 1 ==
3312 11:52:10.967091 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3313 11:52:10.970486 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3314 11:52:10.970568
3315 11:52:10.973845 [DATLAT]
3316 11:52:10.973926 Freq=1200, CH1 RK0
3317 11:52:10.973992
3318 11:52:10.977535 DATLAT Default: 0xd
3319 11:52:10.977616 0, 0xFFFF, sum = 0
3320 11:52:10.980483 1, 0xFFFF, sum = 0
3321 11:52:10.980567 2, 0xFFFF, sum = 0
3322 11:52:10.983632 3, 0xFFFF, sum = 0
3323 11:52:10.987036 4, 0xFFFF, sum = 0
3324 11:52:10.987120 5, 0xFFFF, sum = 0
3325 11:52:10.990648 6, 0xFFFF, sum = 0
3326 11:52:10.990732 7, 0xFFFF, sum = 0
3327 11:52:10.994051 8, 0xFFFF, sum = 0
3328 11:52:10.994138 9, 0xFFFF, sum = 0
3329 11:52:10.996815 10, 0xFFFF, sum = 0
3330 11:52:10.996936 11, 0xFFFF, sum = 0
3331 11:52:11.000419 12, 0x0, sum = 1
3332 11:52:11.000533 13, 0x0, sum = 2
3333 11:52:11.003428 14, 0x0, sum = 3
3334 11:52:11.003515 15, 0x0, sum = 4
3335 11:52:11.003582 best_step = 13
3336 11:52:11.007048
3337 11:52:11.007129 ==
3338 11:52:11.010638 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 11:52:11.013751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 11:52:11.013834 ==
3341 11:52:11.013899 RX Vref Scan: 1
3342 11:52:11.013960
3343 11:52:11.017065 Set Vref Range= 32 -> 127
3344 11:52:11.017152
3345 11:52:11.020928 RX Vref 32 -> 127, step: 1
3346 11:52:11.021022
3347 11:52:11.023976 RX Delay -13 -> 252, step: 4
3348 11:52:11.024071
3349 11:52:11.026860 Set Vref, RX VrefLevel [Byte0]: 32
3350 11:52:11.030870 [Byte1]: 32
3351 11:52:11.030982
3352 11:52:11.034042 Set Vref, RX VrefLevel [Byte0]: 33
3353 11:52:11.036579 [Byte1]: 33
3354 11:52:11.040380
3355 11:52:11.040515 Set Vref, RX VrefLevel [Byte0]: 34
3356 11:52:11.043458 [Byte1]: 34
3357 11:52:11.048072
3358 11:52:11.048224 Set Vref, RX VrefLevel [Byte0]: 35
3359 11:52:11.051486 [Byte1]: 35
3360 11:52:11.056341
3361 11:52:11.056540 Set Vref, RX VrefLevel [Byte0]: 36
3362 11:52:11.059276 [Byte1]: 36
3363 11:52:11.064044
3364 11:52:11.064245 Set Vref, RX VrefLevel [Byte0]: 37
3365 11:52:11.067333 [Byte1]: 37
3366 11:52:11.071836
3367 11:52:11.072075 Set Vref, RX VrefLevel [Byte0]: 38
3368 11:52:11.075452 [Byte1]: 38
3369 11:52:11.079867
3370 11:52:11.080106 Set Vref, RX VrefLevel [Byte0]: 39
3371 11:52:11.082869 [Byte1]: 39
3372 11:52:11.087378
3373 11:52:11.087462 Set Vref, RX VrefLevel [Byte0]: 40
3374 11:52:11.091203 [Byte1]: 40
3375 11:52:11.095306
3376 11:52:11.095387 Set Vref, RX VrefLevel [Byte0]: 41
3377 11:52:11.098862 [Byte1]: 41
3378 11:52:11.103601
3379 11:52:11.103710 Set Vref, RX VrefLevel [Byte0]: 42
3380 11:52:11.106405 [Byte1]: 42
3381 11:52:11.111112
3382 11:52:11.111194 Set Vref, RX VrefLevel [Byte0]: 43
3383 11:52:11.114461 [Byte1]: 43
3384 11:52:11.119040
3385 11:52:11.119121 Set Vref, RX VrefLevel [Byte0]: 44
3386 11:52:11.122216 [Byte1]: 44
3387 11:52:11.126805
3388 11:52:11.126886 Set Vref, RX VrefLevel [Byte0]: 45
3389 11:52:11.130220 [Byte1]: 45
3390 11:52:11.134803
3391 11:52:11.134883 Set Vref, RX VrefLevel [Byte0]: 46
3392 11:52:11.138220 [Byte1]: 46
3393 11:52:11.142762
3394 11:52:11.142877 Set Vref, RX VrefLevel [Byte0]: 47
3395 11:52:11.146084 [Byte1]: 47
3396 11:52:11.150155
3397 11:52:11.150239 Set Vref, RX VrefLevel [Byte0]: 48
3398 11:52:11.153777 [Byte1]: 48
3399 11:52:11.158370
3400 11:52:11.158452 Set Vref, RX VrefLevel [Byte0]: 49
3401 11:52:11.161669 [Byte1]: 49
3402 11:52:11.166655
3403 11:52:11.166756 Set Vref, RX VrefLevel [Byte0]: 50
3404 11:52:11.169657 [Byte1]: 50
3405 11:52:11.174232
3406 11:52:11.174351 Set Vref, RX VrefLevel [Byte0]: 51
3407 11:52:11.177459 [Byte1]: 51
3408 11:52:11.182465
3409 11:52:11.182550 Set Vref, RX VrefLevel [Byte0]: 52
3410 11:52:11.185411 [Byte1]: 52
3411 11:52:11.189821
3412 11:52:11.189906 Set Vref, RX VrefLevel [Byte0]: 53
3413 11:52:11.193425 [Byte1]: 53
3414 11:52:11.198488
3415 11:52:11.198570 Set Vref, RX VrefLevel [Byte0]: 54
3416 11:52:11.200975 [Byte1]: 54
3417 11:52:11.205522
3418 11:52:11.205600 Set Vref, RX VrefLevel [Byte0]: 55
3419 11:52:11.209123 [Byte1]: 55
3420 11:52:11.214227
3421 11:52:11.214328 Set Vref, RX VrefLevel [Byte0]: 56
3422 11:52:11.216766 [Byte1]: 56
3423 11:52:11.221674
3424 11:52:11.221786 Set Vref, RX VrefLevel [Byte0]: 57
3425 11:52:11.225011 [Byte1]: 57
3426 11:52:11.229312
3427 11:52:11.229413 Set Vref, RX VrefLevel [Byte0]: 58
3428 11:52:11.232950 [Byte1]: 58
3429 11:52:11.236978
3430 11:52:11.237086 Set Vref, RX VrefLevel [Byte0]: 59
3431 11:52:11.240226 [Byte1]: 59
3432 11:52:11.245056
3433 11:52:11.245131 Set Vref, RX VrefLevel [Byte0]: 60
3434 11:52:11.248090 [Byte1]: 60
3435 11:52:11.253053
3436 11:52:11.253129 Set Vref, RX VrefLevel [Byte0]: 61
3437 11:52:11.256629 [Byte1]: 61
3438 11:52:11.261379
3439 11:52:11.261451 Set Vref, RX VrefLevel [Byte0]: 62
3440 11:52:11.264145 [Byte1]: 62
3441 11:52:11.268770
3442 11:52:11.268874 Set Vref, RX VrefLevel [Byte0]: 63
3443 11:52:11.272000 [Byte1]: 63
3444 11:52:11.276427
3445 11:52:11.276505 Set Vref, RX VrefLevel [Byte0]: 64
3446 11:52:11.280073 [Byte1]: 64
3447 11:52:11.284271
3448 11:52:11.284375 Set Vref, RX VrefLevel [Byte0]: 65
3449 11:52:11.287501 [Byte1]: 65
3450 11:52:11.292542
3451 11:52:11.292654 Final RX Vref Byte 0 = 53 to rank0
3452 11:52:11.295879 Final RX Vref Byte 1 = 52 to rank0
3453 11:52:11.298914 Final RX Vref Byte 0 = 53 to rank1
3454 11:52:11.303280 Final RX Vref Byte 1 = 52 to rank1==
3455 11:52:11.305333 Dram Type= 6, Freq= 0, CH_1, rank 0
3456 11:52:11.312726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3457 11:52:11.312805 ==
3458 11:52:11.312869 DQS Delay:
3459 11:52:11.312929 DQS0 = 0, DQS1 = 0
3460 11:52:11.315686 DQM Delay:
3461 11:52:11.315773 DQM0 = 115, DQM1 = 112
3462 11:52:11.319042 DQ Delay:
3463 11:52:11.322545 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3464 11:52:11.325562 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3465 11:52:11.329068 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
3466 11:52:11.332407 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3467 11:52:11.332580
3468 11:52:11.332713
3469 11:52:11.342569 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3470 11:52:11.342767 CH1 RK0: MR19=304, MR18=F804
3471 11:52:11.349157 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3472 11:52:11.349430
3473 11:52:11.352111 ----->DramcWriteLeveling(PI) begin...
3474 11:52:11.352338 ==
3475 11:52:11.355373 Dram Type= 6, Freq= 0, CH_1, rank 1
3476 11:52:11.362042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3477 11:52:11.362332 ==
3478 11:52:11.365348 Write leveling (Byte 0): 26 => 26
3479 11:52:11.365514 Write leveling (Byte 1): 26 => 26
3480 11:52:11.368878 DramcWriteLeveling(PI) end<-----
3481 11:52:11.369126
3482 11:52:11.372391 ==
3483 11:52:11.372577 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 11:52:11.378939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 11:52:11.379132 ==
3486 11:52:11.381659 [Gating] SW mode calibration
3487 11:52:11.388484 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3488 11:52:11.391704 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3489 11:52:11.398721 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3490 11:52:11.401951 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3491 11:52:11.405070 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3492 11:52:11.411656 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 11:52:11.415555 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 11:52:11.418522 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3495 11:52:11.425103 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
3496 11:52:11.428727 0 15 28 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3497 11:52:11.431423 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3498 11:52:11.438220 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3499 11:52:11.441599 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3500 11:52:11.445291 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 11:52:11.451307 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 11:52:11.455119 1 0 20 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
3503 11:52:11.458136 1 0 24 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
3504 11:52:11.464766 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
3505 11:52:11.468157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3506 11:52:11.471620 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3507 11:52:11.477821 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 11:52:11.481395 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 11:52:11.484679 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 11:52:11.491362 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 11:52:11.494449 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3512 11:52:11.497872 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3513 11:52:11.504096 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3514 11:52:11.507939 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3515 11:52:11.510682 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 11:52:11.517362 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 11:52:11.520670 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 11:52:11.524382 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 11:52:11.530987 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 11:52:11.534228 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:52:11.537420 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:52:11.543675 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:52:11.547369 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:52:11.550588 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:52:11.556926 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:52:11.560501 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3527 11:52:11.563583 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3528 11:52:11.570198 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3529 11:52:11.570331 Total UI for P1: 0, mck2ui 16
3530 11:52:11.573563 best dqsien dly found for B0: ( 1, 3, 22)
3531 11:52:11.580041 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 11:52:11.583516 Total UI for P1: 0, mck2ui 16
3533 11:52:11.586635 best dqsien dly found for B1: ( 1, 3, 28)
3534 11:52:11.590298 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3535 11:52:11.593236 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3536 11:52:11.593358
3537 11:52:11.596914 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3538 11:52:11.600026 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3539 11:52:11.603407 [Gating] SW calibration Done
3540 11:52:11.603506 ==
3541 11:52:11.606923 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 11:52:11.609947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 11:52:11.610050 ==
3544 11:52:11.613500 RX Vref Scan: 0
3545 11:52:11.613601
3546 11:52:11.616429 RX Vref 0 -> 0, step: 1
3547 11:52:11.616524
3548 11:52:11.616612 RX Delay -40 -> 252, step: 8
3549 11:52:11.622936 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3550 11:52:11.626625 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3551 11:52:11.630005 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3552 11:52:11.632797 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3553 11:52:11.639311 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3554 11:52:11.642876 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3555 11:52:11.645866 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3556 11:52:11.649122 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3557 11:52:11.652703 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3558 11:52:11.659441 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3559 11:52:11.662381 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3560 11:52:11.665727 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3561 11:52:11.669076 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3562 11:52:11.672222 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3563 11:52:11.678768 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3564 11:52:11.682507 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3565 11:52:11.682583 ==
3566 11:52:11.685423 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 11:52:11.688975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 11:52:11.689079 ==
3569 11:52:11.692479 DQS Delay:
3570 11:52:11.692581 DQS0 = 0, DQS1 = 0
3571 11:52:11.692672 DQM Delay:
3572 11:52:11.695548 DQM0 = 115, DQM1 = 111
3573 11:52:11.695653 DQ Delay:
3574 11:52:11.699004 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3575 11:52:11.701981 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =119
3576 11:52:11.708950 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3577 11:52:11.711972 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3578 11:52:11.712045
3579 11:52:11.712116
3580 11:52:11.712181 ==
3581 11:52:11.715602 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 11:52:11.718531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 11:52:11.718605 ==
3584 11:52:11.718666
3585 11:52:11.718732
3586 11:52:11.721918 TX Vref Scan disable
3587 11:52:11.725282 == TX Byte 0 ==
3588 11:52:11.728795 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3589 11:52:11.731720 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3590 11:52:11.735383 == TX Byte 1 ==
3591 11:52:11.738324 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3592 11:52:11.741914 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3593 11:52:11.742009 ==
3594 11:52:11.744833 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 11:52:11.748160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 11:52:11.751663 ==
3597 11:52:11.761745 TX Vref=22, minBit 9, minWin=24, winSum=416
3598 11:52:11.765041 TX Vref=24, minBit 9, minWin=23, winSum=415
3599 11:52:11.768283 TX Vref=26, minBit 9, minWin=25, winSum=421
3600 11:52:11.771399 TX Vref=28, minBit 9, minWin=25, winSum=426
3601 11:52:11.774455 TX Vref=30, minBit 9, minWin=25, winSum=430
3602 11:52:11.781442 TX Vref=32, minBit 9, minWin=25, winSum=427
3603 11:52:11.784535 [TxChooseVref] Worse bit 9, Min win 25, Win sum 430, Final Vref 30
3604 11:52:11.784635
3605 11:52:11.787981 Final TX Range 1 Vref 30
3606 11:52:11.788084
3607 11:52:11.788177 ==
3608 11:52:11.790793 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 11:52:11.794352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 11:52:11.797906 ==
3611 11:52:11.798011
3612 11:52:11.798105
3613 11:52:11.798199 TX Vref Scan disable
3614 11:52:11.801265 == TX Byte 0 ==
3615 11:52:11.804054 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3616 11:52:11.811057 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3617 11:52:11.811136 == TX Byte 1 ==
3618 11:52:11.814484 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3619 11:52:11.821078 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3620 11:52:11.821176
3621 11:52:11.821266 [DATLAT]
3622 11:52:11.821352 Freq=1200, CH1 RK1
3623 11:52:11.821438
3624 11:52:11.824223 DATLAT Default: 0xd
3625 11:52:11.827437 0, 0xFFFF, sum = 0
3626 11:52:11.827543 1, 0xFFFF, sum = 0
3627 11:52:11.831048 2, 0xFFFF, sum = 0
3628 11:52:11.831119 3, 0xFFFF, sum = 0
3629 11:52:11.833874 4, 0xFFFF, sum = 0
3630 11:52:11.833945 5, 0xFFFF, sum = 0
3631 11:52:11.837149 6, 0xFFFF, sum = 0
3632 11:52:11.837257 7, 0xFFFF, sum = 0
3633 11:52:11.840784 8, 0xFFFF, sum = 0
3634 11:52:11.840886 9, 0xFFFF, sum = 0
3635 11:52:11.844089 10, 0xFFFF, sum = 0
3636 11:52:11.844169 11, 0xFFFF, sum = 0
3637 11:52:11.847024 12, 0x0, sum = 1
3638 11:52:11.847101 13, 0x0, sum = 2
3639 11:52:11.850350 14, 0x0, sum = 3
3640 11:52:11.850449 15, 0x0, sum = 4
3641 11:52:11.853808 best_step = 13
3642 11:52:11.853902
3643 11:52:11.853973 ==
3644 11:52:11.857504 Dram Type= 6, Freq= 0, CH_1, rank 1
3645 11:52:11.860189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3646 11:52:11.860262 ==
3647 11:52:11.863873 RX Vref Scan: 0
3648 11:52:11.863953
3649 11:52:11.864017 RX Vref 0 -> 0, step: 1
3650 11:52:11.864076
3651 11:52:11.866711 RX Delay -13 -> 252, step: 4
3652 11:52:11.873862 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3653 11:52:11.876836 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3654 11:52:11.880542 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3655 11:52:11.883682 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3656 11:52:11.887154 iDelay=195, Bit 4, Center 116 (47 ~ 186) 140
3657 11:52:11.893518 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3658 11:52:11.896761 iDelay=195, Bit 6, Center 120 (51 ~ 190) 140
3659 11:52:11.899819 iDelay=195, Bit 7, Center 114 (47 ~ 182) 136
3660 11:52:11.903585 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3661 11:52:11.906871 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3662 11:52:11.913359 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3663 11:52:11.916389 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3664 11:52:11.919912 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3665 11:52:11.922853 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3666 11:52:11.929533 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3667 11:52:11.933061 iDelay=195, Bit 15, Center 122 (59 ~ 186) 128
3668 11:52:11.933215 ==
3669 11:52:11.936336 Dram Type= 6, Freq= 0, CH_1, rank 1
3670 11:52:11.939180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3671 11:52:11.939378 ==
3672 11:52:11.942795 DQS Delay:
3673 11:52:11.942966 DQS0 = 0, DQS1 = 0
3674 11:52:11.943174 DQM Delay:
3675 11:52:11.946190 DQM0 = 115, DQM1 = 112
3676 11:52:11.946431 DQ Delay:
3677 11:52:11.949630 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =112
3678 11:52:11.952587 DQ4 =116, DQ5 =124, DQ6 =120, DQ7 =114
3679 11:52:11.959601 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3680 11:52:11.962866 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =122
3681 11:52:11.963352
3682 11:52:11.963680
3683 11:52:11.969662 [DQSOSCAuto] RK1, (LSB)MR18= 0xf90b, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 412 ps
3684 11:52:11.972912 CH1 RK1: MR19=304, MR18=F90B
3685 11:52:11.979283 CH1_RK1: MR19=0x304, MR18=0xF90B, DQSOSC=405, MR23=63, INC=39, DEC=26
3686 11:52:11.982826 [RxdqsGatingPostProcess] freq 1200
3687 11:52:11.989185 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3688 11:52:11.989768 best DQS0 dly(2T, 0.5T) = (0, 11)
3689 11:52:11.992848 best DQS1 dly(2T, 0.5T) = (0, 11)
3690 11:52:11.995817 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3691 11:52:11.999167 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3692 11:52:12.002625 best DQS0 dly(2T, 0.5T) = (0, 11)
3693 11:52:12.006123 best DQS1 dly(2T, 0.5T) = (0, 11)
3694 11:52:12.009337 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3695 11:52:12.012692 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3696 11:52:12.015620 Pre-setting of DQS Precalculation
3697 11:52:12.022227 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3698 11:52:12.029115 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3699 11:52:12.035284 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3700 11:52:12.035838
3701 11:52:12.036268
3702 11:52:12.038671 [Calibration Summary] 2400 Mbps
3703 11:52:12.039126 CH 0, Rank 0
3704 11:52:12.041993 SW Impedance : PASS
3705 11:52:12.045199 DUTY Scan : NO K
3706 11:52:12.045865 ZQ Calibration : PASS
3707 11:52:12.048877 Jitter Meter : NO K
3708 11:52:12.051421 CBT Training : PASS
3709 11:52:12.051786 Write leveling : PASS
3710 11:52:12.054964 RX DQS gating : PASS
3711 11:52:12.058517 RX DQ/DQS(RDDQC) : PASS
3712 11:52:12.058808 TX DQ/DQS : PASS
3713 11:52:12.061433 RX DATLAT : PASS
3714 11:52:12.061818 RX DQ/DQS(Engine): PASS
3715 11:52:12.064958 TX OE : NO K
3716 11:52:12.065368 All Pass.
3717 11:52:12.065705
3718 11:52:12.068309 CH 0, Rank 1
3719 11:52:12.071415 SW Impedance : PASS
3720 11:52:12.071850 DUTY Scan : NO K
3721 11:52:12.074576 ZQ Calibration : PASS
3722 11:52:12.074871 Jitter Meter : NO K
3723 11:52:12.078294 CBT Training : PASS
3724 11:52:12.081210 Write leveling : PASS
3725 11:52:12.081542 RX DQS gating : PASS
3726 11:52:12.085116 RX DQ/DQS(RDDQC) : PASS
3727 11:52:12.087859 TX DQ/DQS : PASS
3728 11:52:12.088197 RX DATLAT : PASS
3729 11:52:12.091174 RX DQ/DQS(Engine): PASS
3730 11:52:12.094191 TX OE : NO K
3731 11:52:12.094589 All Pass.
3732 11:52:12.094923
3733 11:52:12.095189 CH 1, Rank 0
3734 11:52:12.097740 SW Impedance : PASS
3735 11:52:12.101214 DUTY Scan : NO K
3736 11:52:12.101438 ZQ Calibration : PASS
3737 11:52:12.104047 Jitter Meter : NO K
3738 11:52:12.107657 CBT Training : PASS
3739 11:52:12.107908 Write leveling : PASS
3740 11:52:12.110742 RX DQS gating : PASS
3741 11:52:12.114301 RX DQ/DQS(RDDQC) : PASS
3742 11:52:12.114566 TX DQ/DQS : PASS
3743 11:52:12.117691 RX DATLAT : PASS
3744 11:52:12.121191 RX DQ/DQS(Engine): PASS
3745 11:52:12.121439 TX OE : NO K
3746 11:52:12.124169 All Pass.
3747 11:52:12.124392
3748 11:52:12.124611 CH 1, Rank 1
3749 11:52:12.127194 SW Impedance : PASS
3750 11:52:12.127490 DUTY Scan : NO K
3751 11:52:12.130655 ZQ Calibration : PASS
3752 11:52:12.133910 Jitter Meter : NO K
3753 11:52:12.134133 CBT Training : PASS
3754 11:52:12.137509 Write leveling : PASS
3755 11:52:12.140722 RX DQS gating : PASS
3756 11:52:12.140971 RX DQ/DQS(RDDQC) : PASS
3757 11:52:12.143997 TX DQ/DQS : PASS
3758 11:52:12.144238 RX DATLAT : PASS
3759 11:52:12.147454 RX DQ/DQS(Engine): PASS
3760 11:52:12.150880 TX OE : NO K
3761 11:52:12.151103 All Pass.
3762 11:52:12.151280
3763 11:52:12.153717 DramC Write-DBI off
3764 11:52:12.157203 PER_BANK_REFRESH: Hybrid Mode
3765 11:52:12.157539 TX_TRACKING: ON
3766 11:52:12.167396 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3767 11:52:12.170503 [FAST_K] Save calibration result to emmc
3768 11:52:12.173423 dramc_set_vcore_voltage set vcore to 650000
3769 11:52:12.177051 Read voltage for 600, 5
3770 11:52:12.177434 Vio18 = 0
3771 11:52:12.177737 Vcore = 650000
3772 11:52:12.180227 Vdram = 0
3773 11:52:12.180619 Vddq = 0
3774 11:52:12.181076 Vmddr = 0
3775 11:52:12.187068 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3776 11:52:12.190378 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3777 11:52:12.193731 MEM_TYPE=3, freq_sel=19
3778 11:52:12.197018 sv_algorithm_assistance_LP4_1600
3779 11:52:12.199988 ============ PULL DRAM RESETB DOWN ============
3780 11:52:12.203499 ========== PULL DRAM RESETB DOWN end =========
3781 11:52:12.209931 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3782 11:52:12.213325 ===================================
3783 11:52:12.213718 LPDDR4 DRAM CONFIGURATION
3784 11:52:12.216937 ===================================
3785 11:52:12.219807 EX_ROW_EN[0] = 0x0
3786 11:52:12.223182 EX_ROW_EN[1] = 0x0
3787 11:52:12.223534 LP4Y_EN = 0x0
3788 11:52:12.226756 WORK_FSP = 0x0
3789 11:52:12.227124 WL = 0x2
3790 11:52:12.229685 RL = 0x2
3791 11:52:12.230059 BL = 0x2
3792 11:52:12.233250 RPST = 0x0
3793 11:52:12.233616 RD_PRE = 0x0
3794 11:52:12.236475 WR_PRE = 0x1
3795 11:52:12.236853 WR_PST = 0x0
3796 11:52:12.240008 DBI_WR = 0x0
3797 11:52:12.240381 DBI_RD = 0x0
3798 11:52:12.243443 OTF = 0x1
3799 11:52:12.246760 ===================================
3800 11:52:12.249773 ===================================
3801 11:52:12.250157 ANA top config
3802 11:52:12.253399 ===================================
3803 11:52:12.256749 DLL_ASYNC_EN = 0
3804 11:52:12.259818 ALL_SLAVE_EN = 1
3805 11:52:12.263391 NEW_RANK_MODE = 1
3806 11:52:12.263876 DLL_IDLE_MODE = 1
3807 11:52:12.266221 LP45_APHY_COMB_EN = 1
3808 11:52:12.269486 TX_ODT_DIS = 1
3809 11:52:12.272863 NEW_8X_MODE = 1
3810 11:52:12.276432 ===================================
3811 11:52:12.279817 ===================================
3812 11:52:12.282622 data_rate = 1200
3813 11:52:12.286849 CKR = 1
3814 11:52:12.287303 DQ_P2S_RATIO = 8
3815 11:52:12.289485 ===================================
3816 11:52:12.292813 CA_P2S_RATIO = 8
3817 11:52:12.296082 DQ_CA_OPEN = 0
3818 11:52:12.299551 DQ_SEMI_OPEN = 0
3819 11:52:12.302458 CA_SEMI_OPEN = 0
3820 11:52:12.306002 CA_FULL_RATE = 0
3821 11:52:12.306507 DQ_CKDIV4_EN = 1
3822 11:52:12.309315 CA_CKDIV4_EN = 1
3823 11:52:12.312561 CA_PREDIV_EN = 0
3824 11:52:12.315691 PH8_DLY = 0
3825 11:52:12.319127 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3826 11:52:12.322072 DQ_AAMCK_DIV = 4
3827 11:52:12.322587 CA_AAMCK_DIV = 4
3828 11:52:12.325494 CA_ADMCK_DIV = 4
3829 11:52:12.328741 DQ_TRACK_CA_EN = 0
3830 11:52:12.331871 CA_PICK = 600
3831 11:52:12.335464 CA_MCKIO = 600
3832 11:52:12.338313 MCKIO_SEMI = 0
3833 11:52:12.342210 PLL_FREQ = 2288
3834 11:52:12.345184 DQ_UI_PI_RATIO = 32
3835 11:52:12.345610 CA_UI_PI_RATIO = 0
3836 11:52:12.348645 ===================================
3837 11:52:12.351896 ===================================
3838 11:52:12.355605 memory_type:LPDDR4
3839 11:52:12.358580 GP_NUM : 10
3840 11:52:12.359006 SRAM_EN : 1
3841 11:52:12.361628 MD32_EN : 0
3842 11:52:12.365507 ===================================
3843 11:52:12.368184 [ANA_INIT] >>>>>>>>>>>>>>
3844 11:52:12.371319 <<<<<< [CONFIGURE PHASE]: ANA_TX
3845 11:52:12.374561 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3846 11:52:12.378062 ===================================
3847 11:52:12.378310 data_rate = 1200,PCW = 0X5800
3848 11:52:12.380939 ===================================
3849 11:52:12.384256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3850 11:52:12.390870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3851 11:52:12.397362 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3852 11:52:12.401466 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3853 11:52:12.404570 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3854 11:52:12.407204 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3855 11:52:12.410617 [ANA_INIT] flow start
3856 11:52:12.414073 [ANA_INIT] PLL >>>>>>>>
3857 11:52:12.414418 [ANA_INIT] PLL <<<<<<<<
3858 11:52:12.417297 [ANA_INIT] MIDPI >>>>>>>>
3859 11:52:12.420731 [ANA_INIT] MIDPI <<<<<<<<
3860 11:52:12.420960 [ANA_INIT] DLL >>>>>>>>
3861 11:52:12.423741 [ANA_INIT] flow end
3862 11:52:12.427189 ============ LP4 DIFF to SE enter ============
3863 11:52:12.434215 ============ LP4 DIFF to SE exit ============
3864 11:52:12.434489 [ANA_INIT] <<<<<<<<<<<<<
3865 11:52:12.437091 [Flow] Enable top DCM control >>>>>
3866 11:52:12.440756 [Flow] Enable top DCM control <<<<<
3867 11:52:12.443475 Enable DLL master slave shuffle
3868 11:52:12.450327 ==============================================================
3869 11:52:12.450560 Gating Mode config
3870 11:52:12.457159 ==============================================================
3871 11:52:12.460119 Config description:
3872 11:52:12.466909 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3873 11:52:12.473524 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3874 11:52:12.480021 SELPH_MODE 0: By rank 1: By Phase
3875 11:52:12.487060 ==============================================================
3876 11:52:12.489642 GAT_TRACK_EN = 1
3877 11:52:12.489870 RX_GATING_MODE = 2
3878 11:52:12.493301 RX_GATING_TRACK_MODE = 2
3879 11:52:12.496480 SELPH_MODE = 1
3880 11:52:12.499745 PICG_EARLY_EN = 1
3881 11:52:12.503506 VALID_LAT_VALUE = 1
3882 11:52:12.509835 ==============================================================
3883 11:52:12.512964 Enter into Gating configuration >>>>
3884 11:52:12.517129 Exit from Gating configuration <<<<
3885 11:52:12.519310 Enter into DVFS_PRE_config >>>>>
3886 11:52:12.529003 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3887 11:52:12.532487 Exit from DVFS_PRE_config <<<<<
3888 11:52:12.535688 Enter into PICG configuration >>>>
3889 11:52:12.539394 Exit from PICG configuration <<<<
3890 11:52:12.542489 [RX_INPUT] configuration >>>>>
3891 11:52:12.546026 [RX_INPUT] configuration <<<<<
3892 11:52:12.549207 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3893 11:52:12.555568 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3894 11:52:12.562767 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3895 11:52:12.569118 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3896 11:52:12.575588 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3897 11:52:12.578401 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3898 11:52:12.585619 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3899 11:52:12.589104 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3900 11:52:12.591913 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3901 11:52:12.595432 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3902 11:52:12.602154 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3903 11:52:12.605080 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3904 11:52:12.608804 ===================================
3905 11:52:12.611750 LPDDR4 DRAM CONFIGURATION
3906 11:52:12.615301 ===================================
3907 11:52:12.615728 EX_ROW_EN[0] = 0x0
3908 11:52:12.618705 EX_ROW_EN[1] = 0x0
3909 11:52:12.619128 LP4Y_EN = 0x0
3910 11:52:12.621789 WORK_FSP = 0x0
3911 11:52:12.622301 WL = 0x2
3912 11:52:12.625176 RL = 0x2
3913 11:52:12.625596 BL = 0x2
3914 11:52:12.628399 RPST = 0x0
3915 11:52:12.632055 RD_PRE = 0x0
3916 11:52:12.632515 WR_PRE = 0x1
3917 11:52:12.634766 WR_PST = 0x0
3918 11:52:12.635065 DBI_WR = 0x0
3919 11:52:12.638481 DBI_RD = 0x0
3920 11:52:12.638783 OTF = 0x1
3921 11:52:12.641661 ===================================
3922 11:52:12.644735 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3923 11:52:12.651127 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3924 11:52:12.654712 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3925 11:52:12.657922 ===================================
3926 11:52:12.661277 LPDDR4 DRAM CONFIGURATION
3927 11:52:12.664180 ===================================
3928 11:52:12.664297 EX_ROW_EN[0] = 0x10
3929 11:52:12.667606 EX_ROW_EN[1] = 0x0
3930 11:52:12.667691 LP4Y_EN = 0x0
3931 11:52:12.670818 WORK_FSP = 0x0
3932 11:52:12.670935 WL = 0x2
3933 11:52:12.674277 RL = 0x2
3934 11:52:12.674378 BL = 0x2
3935 11:52:12.678011 RPST = 0x0
3936 11:52:12.680941 RD_PRE = 0x0
3937 11:52:12.681024 WR_PRE = 0x1
3938 11:52:12.684806 WR_PST = 0x0
3939 11:52:12.685134 DBI_WR = 0x0
3940 11:52:12.688066 DBI_RD = 0x0
3941 11:52:12.688394 OTF = 0x1
3942 11:52:12.691055 ===================================
3943 11:52:12.697668 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3944 11:52:12.701542 nWR fixed to 30
3945 11:52:12.704419 [ModeRegInit_LP4] CH0 RK0
3946 11:52:12.704662 [ModeRegInit_LP4] CH0 RK1
3947 11:52:12.707908 [ModeRegInit_LP4] CH1 RK0
3948 11:52:12.711319 [ModeRegInit_LP4] CH1 RK1
3949 11:52:12.711562 match AC timing 17
3950 11:52:12.717844 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3951 11:52:12.721277 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3952 11:52:12.724875 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3953 11:52:12.731081 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3954 11:52:12.734094 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3955 11:52:12.734363 ==
3956 11:52:12.737568 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 11:52:12.740616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 11:52:12.740778 ==
3959 11:52:12.747126 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3960 11:52:12.753957 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3961 11:52:12.757042 [CA 0] Center 36 (6~67) winsize 62
3962 11:52:12.760773 [CA 1] Center 36 (6~66) winsize 61
3963 11:52:12.764330 [CA 2] Center 34 (4~65) winsize 62
3964 11:52:12.767053 [CA 3] Center 34 (4~65) winsize 62
3965 11:52:12.770173 [CA 4] Center 33 (3~64) winsize 62
3966 11:52:12.773660 [CA 5] Center 33 (3~64) winsize 62
3967 11:52:12.773765
3968 11:52:12.777431 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3969 11:52:12.777537
3970 11:52:12.780303 [CATrainingPosCal] consider 1 rank data
3971 11:52:12.783908 u2DelayCellTimex100 = 270/100 ps
3972 11:52:12.786741 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3973 11:52:12.789825 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 11:52:12.793386 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3975 11:52:12.799959 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 11:52:12.803393 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3977 11:52:12.806908 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 11:52:12.807048
3979 11:52:12.809870 CA PerBit enable=1, Macro0, CA PI delay=33
3980 11:52:12.810028
3981 11:52:12.813395 [CBTSetCACLKResult] CA Dly = 33
3982 11:52:12.813553 CS Dly: 5 (0~36)
3983 11:52:12.813686 ==
3984 11:52:12.816697 Dram Type= 6, Freq= 0, CH_0, rank 1
3985 11:52:12.823082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3986 11:52:12.823295 ==
3987 11:52:12.826573 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3988 11:52:12.832974 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3989 11:52:12.836999 [CA 0] Center 36 (6~67) winsize 62
3990 11:52:12.840528 [CA 1] Center 36 (6~67) winsize 62
3991 11:52:12.843643 [CA 2] Center 34 (4~65) winsize 62
3992 11:52:12.847040 [CA 3] Center 34 (4~65) winsize 62
3993 11:52:12.850377 [CA 4] Center 34 (3~65) winsize 63
3994 11:52:12.853550 [CA 5] Center 33 (3~64) winsize 62
3995 11:52:12.853972
3996 11:52:12.857119 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3997 11:52:12.857541
3998 11:52:12.859981 [CATrainingPosCal] consider 2 rank data
3999 11:52:12.863387 u2DelayCellTimex100 = 270/100 ps
4000 11:52:12.866550 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4001 11:52:12.873573 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4002 11:52:12.876413 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4003 11:52:12.879911 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4004 11:52:12.883569 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4005 11:52:12.886324 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4006 11:52:12.886749
4007 11:52:12.889518 CA PerBit enable=1, Macro0, CA PI delay=33
4008 11:52:12.889939
4009 11:52:12.893189 [CBTSetCACLKResult] CA Dly = 33
4010 11:52:12.896013 CS Dly: 5 (0~37)
4011 11:52:12.896431
4012 11:52:12.899356 ----->DramcWriteLeveling(PI) begin...
4013 11:52:12.899828 ==
4014 11:52:12.903130 Dram Type= 6, Freq= 0, CH_0, rank 0
4015 11:52:12.906112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4016 11:52:12.906644 ==
4017 11:52:12.909446 Write leveling (Byte 0): 35 => 35
4018 11:52:12.912976 Write leveling (Byte 1): 28 => 28
4019 11:52:12.915862 DramcWriteLeveling(PI) end<-----
4020 11:52:12.916283
4021 11:52:12.916615 ==
4022 11:52:12.919349 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 11:52:12.922810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 11:52:12.923228 ==
4025 11:52:12.925773 [Gating] SW mode calibration
4026 11:52:12.932851 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4027 11:52:12.939115 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4028 11:52:12.942332 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4029 11:52:12.945658 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4030 11:52:12.952036 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4031 11:52:12.955793 0 9 12 | B1->B0 | 3434 3131 | 0 1 | (0 1) (0 0)
4032 11:52:12.958875 0 9 16 | B1->B0 | 2c2c 2828 | 0 0 | (1 1) (1 1)
4033 11:52:12.965576 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4034 11:52:12.968639 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4035 11:52:12.972275 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4036 11:52:12.978701 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 11:52:12.981612 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 11:52:12.985069 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 11:52:12.991656 0 10 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
4040 11:52:12.995011 0 10 16 | B1->B0 | 3c3c 4242 | 0 0 | (0 0) (0 0)
4041 11:52:12.998626 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4042 11:52:13.005266 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4043 11:52:13.007843 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4044 11:52:13.011615 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 11:52:13.018149 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 11:52:13.021348 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 11:52:13.024980 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4048 11:52:13.031342 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4049 11:52:13.034550 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4050 11:52:13.037951 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4051 11:52:13.044850 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4052 11:52:13.047450 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 11:52:13.054208 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 11:52:13.057541 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 11:52:13.060764 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:52:13.067648 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:52:13.070447 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:52:13.073978 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:52:13.080675 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:52:13.083823 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:52:13.087199 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:52:13.094055 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4063 11:52:13.097086 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:52:13.100407 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4065 11:52:13.103701 Total UI for P1: 0, mck2ui 16
4066 11:52:13.107035 best dqsien dly found for B0: ( 0, 13, 14)
4067 11:52:13.110513 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4068 11:52:13.113527 Total UI for P1: 0, mck2ui 16
4069 11:52:13.117024 best dqsien dly found for B1: ( 0, 13, 16)
4070 11:52:13.123566 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4071 11:52:13.126585 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4072 11:52:13.127008
4073 11:52:13.130138 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4074 11:52:13.133039 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4075 11:52:13.136560 [Gating] SW calibration Done
4076 11:52:13.136984 ==
4077 11:52:13.139954 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 11:52:13.143158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 11:52:13.143585 ==
4080 11:52:13.146209 RX Vref Scan: 0
4081 11:52:13.146829
4082 11:52:13.147213 RX Vref 0 -> 0, step: 1
4083 11:52:13.147535
4084 11:52:13.150611 RX Delay -230 -> 252, step: 16
4085 11:52:13.156209 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4086 11:52:13.159680 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4087 11:52:13.163161 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4088 11:52:13.166560 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4089 11:52:13.169654 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4090 11:52:13.176128 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4091 11:52:13.179184 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4092 11:52:13.182660 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4093 11:52:13.186001 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4094 11:52:13.193160 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4095 11:52:13.195741 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4096 11:52:13.199552 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4097 11:52:13.202656 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4098 11:52:13.209001 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4099 11:52:13.212501 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4100 11:52:13.216270 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4101 11:52:13.216707 ==
4102 11:52:13.218844 Dram Type= 6, Freq= 0, CH_0, rank 0
4103 11:52:13.222361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4104 11:52:13.226099 ==
4105 11:52:13.226574 DQS Delay:
4106 11:52:13.227016 DQS0 = 0, DQS1 = 0
4107 11:52:13.228684 DQM Delay:
4108 11:52:13.229116 DQM0 = 45, DQM1 = 35
4109 11:52:13.232134 DQ Delay:
4110 11:52:13.235896 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4111 11:52:13.236326 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4112 11:52:13.238926 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4113 11:52:13.241940 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4114 11:52:13.245227
4115 11:52:13.245645
4116 11:52:13.245982 ==
4117 11:52:13.248745 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 11:52:13.251622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 11:52:13.252069 ==
4120 11:52:13.252606
4121 11:52:13.253165
4122 11:52:13.254973 TX Vref Scan disable
4123 11:52:13.255396 == TX Byte 0 ==
4124 11:52:13.262072 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4125 11:52:13.264937 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4126 11:52:13.265360 == TX Byte 1 ==
4127 11:52:13.271730 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4128 11:52:13.275330 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4129 11:52:13.275769 ==
4130 11:52:13.278048 Dram Type= 6, Freq= 0, CH_0, rank 0
4131 11:52:13.281641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4132 11:52:13.282194 ==
4133 11:52:13.282595
4134 11:52:13.284710
4135 11:52:13.285131 TX Vref Scan disable
4136 11:52:13.288455 == TX Byte 0 ==
4137 11:52:13.291828 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4138 11:52:13.298530 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4139 11:52:13.298955 == TX Byte 1 ==
4140 11:52:13.301986 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4141 11:52:13.308470 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4142 11:52:13.308940
4143 11:52:13.309302 [DATLAT]
4144 11:52:13.309617 Freq=600, CH0 RK0
4145 11:52:13.309921
4146 11:52:13.311558 DATLAT Default: 0x9
4147 11:52:13.311980 0, 0xFFFF, sum = 0
4148 11:52:13.314930 1, 0xFFFF, sum = 0
4149 11:52:13.318094 2, 0xFFFF, sum = 0
4150 11:52:13.318566 3, 0xFFFF, sum = 0
4151 11:52:13.321766 4, 0xFFFF, sum = 0
4152 11:52:13.322194 5, 0xFFFF, sum = 0
4153 11:52:13.324732 6, 0xFFFF, sum = 0
4154 11:52:13.325157 7, 0xFFFF, sum = 0
4155 11:52:13.328276 8, 0x0, sum = 1
4156 11:52:13.328703 9, 0x0, sum = 2
4157 11:52:13.329045 10, 0x0, sum = 3
4158 11:52:13.331112 11, 0x0, sum = 4
4159 11:52:13.331414 best_step = 9
4160 11:52:13.331655
4161 11:52:13.334482 ==
4162 11:52:13.334754 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 11:52:13.341065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 11:52:13.341163 ==
4165 11:52:13.341244 RX Vref Scan: 1
4166 11:52:13.341335
4167 11:52:13.344007 RX Vref 0 -> 0, step: 1
4168 11:52:13.344089
4169 11:52:13.347276 RX Delay -179 -> 252, step: 8
4170 11:52:13.347390
4171 11:52:13.350721 Set Vref, RX VrefLevel [Byte0]: 58
4172 11:52:13.354474 [Byte1]: 49
4173 11:52:13.354556
4174 11:52:13.357292 Final RX Vref Byte 0 = 58 to rank0
4175 11:52:13.360458 Final RX Vref Byte 1 = 49 to rank0
4176 11:52:13.363937 Final RX Vref Byte 0 = 58 to rank1
4177 11:52:13.367131 Final RX Vref Byte 1 = 49 to rank1==
4178 11:52:13.371112 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 11:52:13.373599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 11:52:13.376822 ==
4181 11:52:13.376909 DQS Delay:
4182 11:52:13.376975 DQS0 = 0, DQS1 = 0
4183 11:52:13.380445 DQM Delay:
4184 11:52:13.380530 DQM0 = 45, DQM1 = 36
4185 11:52:13.383672 DQ Delay:
4186 11:52:13.386683 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4187 11:52:13.386766 DQ4 =48, DQ5 =36, DQ6 =56, DQ7 =48
4188 11:52:13.390387 DQ8 =28, DQ9 =24, DQ10 =36, DQ11 =28
4189 11:52:13.397091 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4190 11:52:13.397189
4191 11:52:13.397254
4192 11:52:13.403614 [DQSOSCAuto] RK0, (LSB)MR18= 0x5149, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 394 ps
4193 11:52:13.407125 CH0 RK0: MR19=808, MR18=5149
4194 11:52:13.413477 CH0_RK0: MR19=0x808, MR18=0x5149, DQSOSC=394, MR23=63, INC=168, DEC=112
4195 11:52:13.413559
4196 11:52:13.416631 ----->DramcWriteLeveling(PI) begin...
4197 11:52:13.416714 ==
4198 11:52:13.420264 Dram Type= 6, Freq= 0, CH_0, rank 1
4199 11:52:13.423215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4200 11:52:13.423298 ==
4201 11:52:13.426591 Write leveling (Byte 0): 33 => 33
4202 11:52:13.430152 Write leveling (Byte 1): 30 => 30
4203 11:52:13.432890 DramcWriteLeveling(PI) end<-----
4204 11:52:13.432972
4205 11:52:13.433036 ==
4206 11:52:13.436418 Dram Type= 6, Freq= 0, CH_0, rank 1
4207 11:52:13.439877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 11:52:13.439965 ==
4209 11:52:13.442909 [Gating] SW mode calibration
4210 11:52:13.449397 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4211 11:52:13.456343 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4212 11:52:13.459233 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4213 11:52:13.466149 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4214 11:52:13.469476 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4215 11:52:13.472497 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4216 11:52:13.479583 0 9 16 | B1->B0 | 3030 2626 | 1 0 | (0 0) (0 0)
4217 11:52:13.482312 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4218 11:52:13.485970 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4219 11:52:13.492607 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4220 11:52:13.495824 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 11:52:13.499514 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 11:52:13.505970 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4223 11:52:13.509278 0 10 12 | B1->B0 | 2b2b 3635 | 0 1 | (1 1) (0 0)
4224 11:52:13.512875 0 10 16 | B1->B0 | 3b3b 4343 | 0 0 | (1 1) (0 0)
4225 11:52:13.519072 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4226 11:52:13.522030 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4227 11:52:13.525227 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4228 11:52:13.532101 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 11:52:13.535191 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 11:52:13.538650 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 11:52:13.545069 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4232 11:52:13.548077 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4233 11:52:13.551689 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4234 11:52:13.558070 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4235 11:52:13.561374 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 11:52:13.564700 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 11:52:13.571745 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 11:52:13.574628 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 11:52:13.577952 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:52:13.584406 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:52:13.587793 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:52:13.591276 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:52:13.597603 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:52:13.600748 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:52:13.603909 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:52:13.610686 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:52:13.614099 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:52:13.617167 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 11:52:13.620695 Total UI for P1: 0, mck2ui 16
4250 11:52:13.623843 best dqsien dly found for B0: ( 0, 13, 14)
4251 11:52:13.627490 Total UI for P1: 0, mck2ui 16
4252 11:52:13.630564 best dqsien dly found for B1: ( 0, 13, 14)
4253 11:52:13.633786 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4254 11:52:13.636940 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4255 11:52:13.640567
4256 11:52:13.643718 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4257 11:52:13.647068 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4258 11:52:13.650484 [Gating] SW calibration Done
4259 11:52:13.650567 ==
4260 11:52:13.653508 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 11:52:13.656881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 11:52:13.656963 ==
4263 11:52:13.657029 RX Vref Scan: 0
4264 11:52:13.660271
4265 11:52:13.660353 RX Vref 0 -> 0, step: 1
4266 11:52:13.660418
4267 11:52:13.663725 RX Delay -230 -> 252, step: 16
4268 11:52:13.666816 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4269 11:52:13.673386 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4270 11:52:13.677321 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4271 11:52:13.680627 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4272 11:52:13.683691 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4273 11:52:13.690180 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4274 11:52:13.693336 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4275 11:52:13.696813 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4276 11:52:13.699625 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4277 11:52:13.703261 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4278 11:52:13.709884 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4279 11:52:13.713111 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4280 11:52:13.716296 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4281 11:52:13.719902 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4282 11:52:13.726640 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4283 11:52:13.729647 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4284 11:52:13.729728 ==
4285 11:52:13.733164 Dram Type= 6, Freq= 0, CH_0, rank 1
4286 11:52:13.736921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4287 11:52:13.737004 ==
4288 11:52:13.739651 DQS Delay:
4289 11:52:13.739733 DQS0 = 0, DQS1 = 0
4290 11:52:13.742436 DQM Delay:
4291 11:52:13.742520 DQM0 = 46, DQM1 = 35
4292 11:52:13.742586 DQ Delay:
4293 11:52:13.745841 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4294 11:52:13.749642 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4295 11:52:13.752857 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4296 11:52:13.756307 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4297 11:52:13.756388
4298 11:52:13.756453
4299 11:52:13.756513 ==
4300 11:52:13.759156 Dram Type= 6, Freq= 0, CH_0, rank 1
4301 11:52:13.766309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4302 11:52:13.766391 ==
4303 11:52:13.766456
4304 11:52:13.766516
4305 11:52:13.769030 TX Vref Scan disable
4306 11:52:13.769111 == TX Byte 0 ==
4307 11:52:13.775690 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4308 11:52:13.778710 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4309 11:52:13.778792 == TX Byte 1 ==
4310 11:52:13.785775 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4311 11:52:13.789259 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4312 11:52:13.789341 ==
4313 11:52:13.791972 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 11:52:13.796065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 11:52:13.796147 ==
4316 11:52:13.796212
4317 11:52:13.796272
4318 11:52:13.798824 TX Vref Scan disable
4319 11:52:13.801862 == TX Byte 0 ==
4320 11:52:13.805386 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4321 11:52:13.808567 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4322 11:52:13.812032 == TX Byte 1 ==
4323 11:52:13.815212 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4324 11:52:13.818701 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4325 11:52:13.821888
4326 11:52:13.822039 [DATLAT]
4327 11:52:13.822151 Freq=600, CH0 RK1
4328 11:52:13.822241
4329 11:52:13.825287 DATLAT Default: 0x9
4330 11:52:13.825393 0, 0xFFFF, sum = 0
4331 11:52:13.828186 1, 0xFFFF, sum = 0
4332 11:52:13.828271 2, 0xFFFF, sum = 0
4333 11:52:13.831713 3, 0xFFFF, sum = 0
4334 11:52:13.831797 4, 0xFFFF, sum = 0
4335 11:52:13.835045 5, 0xFFFF, sum = 0
4336 11:52:13.838169 6, 0xFFFF, sum = 0
4337 11:52:13.838310 7, 0xFFFF, sum = 0
4338 11:52:13.841588 8, 0x0, sum = 1
4339 11:52:13.841671 9, 0x0, sum = 2
4340 11:52:13.841738 10, 0x0, sum = 3
4341 11:52:13.845033 11, 0x0, sum = 4
4342 11:52:13.845116 best_step = 9
4343 11:52:13.845182
4344 11:52:13.845243 ==
4345 11:52:13.848391 Dram Type= 6, Freq= 0, CH_0, rank 1
4346 11:52:13.854950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4347 11:52:13.855034 ==
4348 11:52:13.855100 RX Vref Scan: 0
4349 11:52:13.855162
4350 11:52:13.858083 RX Vref 0 -> 0, step: 1
4351 11:52:13.858207
4352 11:52:13.861688 RX Delay -179 -> 252, step: 8
4353 11:52:13.864670 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4354 11:52:13.871301 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4355 11:52:13.874540 iDelay=205, Bit 2, Center 40 (-107 ~ 188) 296
4356 11:52:13.878379 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4357 11:52:13.881136 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4358 11:52:13.887493 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4359 11:52:13.890788 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4360 11:52:13.894141 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4361 11:52:13.897308 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4362 11:52:13.900735 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4363 11:52:13.907440 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4364 11:52:13.911018 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4365 11:52:13.913793 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4366 11:52:13.917555 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4367 11:52:13.923789 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4368 11:52:13.927031 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4369 11:52:13.927165 ==
4370 11:52:13.930518 Dram Type= 6, Freq= 0, CH_0, rank 1
4371 11:52:13.934110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4372 11:52:13.934577 ==
4373 11:52:13.937534 DQS Delay:
4374 11:52:13.937949 DQS0 = 0, DQS1 = 0
4375 11:52:13.940609 DQM Delay:
4376 11:52:13.941027 DQM0 = 44, DQM1 = 37
4377 11:52:13.941361 DQ Delay:
4378 11:52:13.944019 DQ0 =40, DQ1 =48, DQ2 =40, DQ3 =40
4379 11:52:13.947480 DQ4 =48, DQ5 =32, DQ6 =56, DQ7 =52
4380 11:52:13.950814 DQ8 =28, DQ9 =24, DQ10 =40, DQ11 =32
4381 11:52:13.953541 DQ12 =40, DQ13 =44, DQ14 =48, DQ15 =44
4382 11:52:13.953958
4383 11:52:13.954319
4384 11:52:13.963466 [DQSOSCAuto] RK1, (LSB)MR18= 0x433f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4385 11:52:13.967085 CH0 RK1: MR19=808, MR18=433F
4386 11:52:13.973454 CH0_RK1: MR19=0x808, MR18=0x433F, DQSOSC=397, MR23=63, INC=166, DEC=110
4387 11:52:13.977027 [RxdqsGatingPostProcess] freq 600
4388 11:52:13.980602 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4389 11:52:13.983439 Pre-setting of DQS Precalculation
4390 11:52:13.989742 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4391 11:52:13.990162 ==
4392 11:52:13.993477 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 11:52:13.996289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 11:52:13.996712 ==
4395 11:52:14.003418 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4396 11:52:14.006246 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4397 11:52:14.010952 [CA 0] Center 36 (6~66) winsize 61
4398 11:52:14.014016 [CA 1] Center 35 (5~66) winsize 62
4399 11:52:14.017586 [CA 2] Center 34 (4~65) winsize 62
4400 11:52:14.020416 [CA 3] Center 34 (3~65) winsize 63
4401 11:52:14.024045 [CA 4] Center 34 (4~65) winsize 62
4402 11:52:14.027459 [CA 5] Center 34 (3~65) winsize 63
4403 11:52:14.027875
4404 11:52:14.030342 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4405 11:52:14.030761
4406 11:52:14.033722 [CATrainingPosCal] consider 1 rank data
4407 11:52:14.037058 u2DelayCellTimex100 = 270/100 ps
4408 11:52:14.040136 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4409 11:52:14.047009 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4410 11:52:14.050001 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4411 11:52:14.053524 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
4412 11:52:14.056553 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4413 11:52:14.060046 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4414 11:52:14.060461
4415 11:52:14.063346 CA PerBit enable=1, Macro0, CA PI delay=34
4416 11:52:14.063762
4417 11:52:14.066653 [CBTSetCACLKResult] CA Dly = 34
4418 11:52:14.069971 CS Dly: 4 (0~35)
4419 11:52:14.070406 ==
4420 11:52:14.072976 Dram Type= 6, Freq= 0, CH_1, rank 1
4421 11:52:14.076539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4422 11:52:14.076959 ==
4423 11:52:14.083287 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4424 11:52:14.086366 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4425 11:52:14.090957 [CA 0] Center 36 (6~66) winsize 61
4426 11:52:14.094206 [CA 1] Center 35 (5~66) winsize 62
4427 11:52:14.097411 [CA 2] Center 34 (4~65) winsize 62
4428 11:52:14.100404 [CA 3] Center 34 (3~65) winsize 63
4429 11:52:14.104027 [CA 4] Center 34 (4~65) winsize 62
4430 11:52:14.107129 [CA 5] Center 33 (3~64) winsize 62
4431 11:52:14.107563
4432 11:52:14.110604 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4433 11:52:14.111024
4434 11:52:14.113939 [CATrainingPosCal] consider 2 rank data
4435 11:52:14.117529 u2DelayCellTimex100 = 270/100 ps
4436 11:52:14.120215 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4437 11:52:14.127047 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4438 11:52:14.130719 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 11:52:14.133332 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4440 11:52:14.136892 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4441 11:52:14.140392 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4442 11:52:14.140811
4443 11:52:14.143275 CA PerBit enable=1, Macro0, CA PI delay=33
4444 11:52:14.143698
4445 11:52:14.146908 [CBTSetCACLKResult] CA Dly = 33
4446 11:52:14.149996 CS Dly: 4 (0~36)
4447 11:52:14.150453
4448 11:52:14.153605 ----->DramcWriteLeveling(PI) begin...
4449 11:52:14.154029 ==
4450 11:52:14.156349 Dram Type= 6, Freq= 0, CH_1, rank 0
4451 11:52:14.159922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4452 11:52:14.160348 ==
4453 11:52:14.163276 Write leveling (Byte 0): 30 => 30
4454 11:52:14.166149 Write leveling (Byte 1): 29 => 29
4455 11:52:14.169507 DramcWriteLeveling(PI) end<-----
4456 11:52:14.170074
4457 11:52:14.170800 ==
4458 11:52:14.173332 Dram Type= 6, Freq= 0, CH_1, rank 0
4459 11:52:14.176333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4460 11:52:14.176978 ==
4461 11:52:14.179709 [Gating] SW mode calibration
4462 11:52:14.186151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4463 11:52:14.192735 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4464 11:52:14.196101 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4465 11:52:14.199523 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4466 11:52:14.206149 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4467 11:52:14.209157 0 9 12 | B1->B0 | 2f2f 3131 | 1 0 | (1 0) (1 1)
4468 11:52:14.212503 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4469 11:52:14.218896 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4470 11:52:14.222802 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4471 11:52:14.225737 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 11:52:14.232456 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 11:52:14.236002 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 11:52:14.239354 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 11:52:14.245652 0 10 12 | B1->B0 | 2d2d 3636 | 1 0 | (0 0) (0 0)
4476 11:52:14.248600 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4477 11:52:14.252298 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4478 11:52:14.258460 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4479 11:52:14.261902 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 11:52:14.265315 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 11:52:14.271536 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 11:52:14.274947 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 11:52:14.278608 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 11:52:14.284913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4485 11:52:14.287800 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4486 11:52:14.291487 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4487 11:52:14.297522 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4488 11:52:14.300896 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 11:52:14.304524 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 11:52:14.311002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 11:52:14.314306 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:52:14.317442 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:52:14.324165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:52:14.327196 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:52:14.330903 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:52:14.337409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:52:14.340966 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:52:14.344377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:52:14.350890 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:52:14.354144 Total UI for P1: 0, mck2ui 16
4501 11:52:14.357580 best dqsien dly found for B0: ( 0, 13, 10)
4502 11:52:14.360756 Total UI for P1: 0, mck2ui 16
4503 11:52:14.363567 best dqsien dly found for B1: ( 0, 13, 10)
4504 11:52:14.366811 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4505 11:52:14.370118 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4506 11:52:14.370224
4507 11:52:14.373626 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4508 11:52:14.377218 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4509 11:52:14.380560 [Gating] SW calibration Done
4510 11:52:14.380658 ==
4511 11:52:14.383328 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 11:52:14.386961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 11:52:14.387040 ==
4514 11:52:14.389885 RX Vref Scan: 0
4515 11:52:14.389957
4516 11:52:14.393555 RX Vref 0 -> 0, step: 1
4517 11:52:14.393639
4518 11:52:14.393709 RX Delay -230 -> 252, step: 16
4519 11:52:14.400094 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4520 11:52:14.403422 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4521 11:52:14.406687 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4522 11:52:14.410236 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4523 11:52:14.416840 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4524 11:52:14.419957 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4525 11:52:14.423125 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4526 11:52:14.426758 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4527 11:52:14.433075 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4528 11:52:14.436535 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4529 11:52:14.439920 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4530 11:52:14.442953 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4531 11:52:14.449371 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4532 11:52:14.452778 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4533 11:52:14.456630 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4534 11:52:14.459432 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4535 11:52:14.459508 ==
4536 11:52:14.462854 Dram Type= 6, Freq= 0, CH_1, rank 0
4537 11:52:14.469355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4538 11:52:14.469434 ==
4539 11:52:14.469498 DQS Delay:
4540 11:52:14.472887 DQS0 = 0, DQS1 = 0
4541 11:52:14.472959 DQM Delay:
4542 11:52:14.473021 DQM0 = 42, DQM1 = 39
4543 11:52:14.475713 DQ Delay:
4544 11:52:14.479266 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4545 11:52:14.482786 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4546 11:52:14.485716 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4547 11:52:14.489193 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4548 11:52:14.489275
4549 11:52:14.489340
4550 11:52:14.489401 ==
4551 11:52:14.492592 Dram Type= 6, Freq= 0, CH_1, rank 0
4552 11:52:14.495716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4553 11:52:14.495805 ==
4554 11:52:14.495875
4555 11:52:14.495940
4556 11:52:14.499210 TX Vref Scan disable
4557 11:52:14.502237 == TX Byte 0 ==
4558 11:52:14.505726 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4559 11:52:14.509201 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4560 11:52:14.512229 == TX Byte 1 ==
4561 11:52:14.515892 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4562 11:52:14.519087 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4563 11:52:14.519211 ==
4564 11:52:14.522384 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 11:52:14.525909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 11:52:14.528756 ==
4567 11:52:14.528907
4568 11:52:14.529028
4569 11:52:14.529140 TX Vref Scan disable
4570 11:52:14.533122 == TX Byte 0 ==
4571 11:52:14.536002 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4572 11:52:14.539757 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4573 11:52:14.542775 == TX Byte 1 ==
4574 11:52:14.546507 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4575 11:52:14.552391 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4576 11:52:14.552474
4577 11:52:14.552540 [DATLAT]
4578 11:52:14.552601 Freq=600, CH1 RK0
4579 11:52:14.552661
4580 11:52:14.556023 DATLAT Default: 0x9
4581 11:52:14.556106 0, 0xFFFF, sum = 0
4582 11:52:14.559063 1, 0xFFFF, sum = 0
4583 11:52:14.562516 2, 0xFFFF, sum = 0
4584 11:52:14.562632 3, 0xFFFF, sum = 0
4585 11:52:14.565869 4, 0xFFFF, sum = 0
4586 11:52:14.565983 5, 0xFFFF, sum = 0
4587 11:52:14.568785 6, 0xFFFF, sum = 0
4588 11:52:14.568868 7, 0xFFFF, sum = 0
4589 11:52:14.572131 8, 0x0, sum = 1
4590 11:52:14.572229 9, 0x0, sum = 2
4591 11:52:14.575765 10, 0x0, sum = 3
4592 11:52:14.575849 11, 0x0, sum = 4
4593 11:52:14.575950 best_step = 9
4594 11:52:14.576032
4595 11:52:14.579183 ==
4596 11:52:14.582322 Dram Type= 6, Freq= 0, CH_1, rank 0
4597 11:52:14.585231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4598 11:52:14.585320 ==
4599 11:52:14.585388 RX Vref Scan: 1
4600 11:52:14.585451
4601 11:52:14.588760 RX Vref 0 -> 0, step: 1
4602 11:52:14.588871
4603 11:52:14.592216 RX Delay -179 -> 252, step: 8
4604 11:52:14.592298
4605 11:52:14.595145 Set Vref, RX VrefLevel [Byte0]: 53
4606 11:52:14.598891 [Byte1]: 52
4607 11:52:14.598974
4608 11:52:14.601805 Final RX Vref Byte 0 = 53 to rank0
4609 11:52:14.605280 Final RX Vref Byte 1 = 52 to rank0
4610 11:52:14.608254 Final RX Vref Byte 0 = 53 to rank1
4611 11:52:14.611917 Final RX Vref Byte 1 = 52 to rank1==
4612 11:52:14.614850 Dram Type= 6, Freq= 0, CH_1, rank 0
4613 11:52:14.618531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4614 11:52:14.621481 ==
4615 11:52:14.621563 DQS Delay:
4616 11:52:14.621629 DQS0 = 0, DQS1 = 0
4617 11:52:14.625189 DQM Delay:
4618 11:52:14.625271 DQM0 = 42, DQM1 = 34
4619 11:52:14.628456 DQ Delay:
4620 11:52:14.631387 DQ0 =48, DQ1 =36, DQ2 =32, DQ3 =40
4621 11:52:14.631469 DQ4 =36, DQ5 =52, DQ6 =56, DQ7 =36
4622 11:52:14.634766 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4623 11:52:14.637967 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =40
4624 11:52:14.641548
4625 11:52:14.641647
4626 11:52:14.648007 [DQSOSCAuto] RK0, (LSB)MR18= 0x354f, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 399 ps
4627 11:52:14.651319 CH1 RK0: MR19=808, MR18=354F
4628 11:52:14.657600 CH1_RK0: MR19=0x808, MR18=0x354F, DQSOSC=394, MR23=63, INC=168, DEC=112
4629 11:52:14.657709
4630 11:52:14.661099 ----->DramcWriteLeveling(PI) begin...
4631 11:52:14.661183 ==
4632 11:52:14.665046 Dram Type= 6, Freq= 0, CH_1, rank 1
4633 11:52:14.668005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4634 11:52:14.668087 ==
4635 11:52:14.671267 Write leveling (Byte 0): 29 => 29
4636 11:52:14.674246 Write leveling (Byte 1): 31 => 31
4637 11:52:14.677753 DramcWriteLeveling(PI) end<-----
4638 11:52:14.677834
4639 11:52:14.677927 ==
4640 11:52:14.681333 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:52:14.684639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:52:14.684725 ==
4643 11:52:14.687915 [Gating] SW mode calibration
4644 11:52:14.694067 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4645 11:52:14.700553 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4646 11:52:14.704167 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4647 11:52:14.710415 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4648 11:52:14.713880 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4649 11:52:14.717607 0 9 12 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (0 1)
4650 11:52:14.724226 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4651 11:52:14.727087 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4652 11:52:14.730691 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4653 11:52:14.737020 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4654 11:52:14.740515 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 11:52:14.743734 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 11:52:14.750163 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4657 11:52:14.753582 0 10 12 | B1->B0 | 3333 3f3f | 0 0 | (0 0) (0 0)
4658 11:52:14.756990 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 11:52:14.763660 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4660 11:52:14.766858 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 11:52:14.769771 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4662 11:52:14.776649 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4663 11:52:14.779843 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 11:52:14.783289 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 11:52:14.789998 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4666 11:52:14.793437 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4667 11:52:14.796597 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4668 11:52:14.802835 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4669 11:52:14.806312 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 11:52:14.809867 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 11:52:14.816023 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 11:52:14.819626 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 11:52:14.823172 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 11:52:14.829382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 11:52:14.832838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:52:14.835620 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:52:14.842412 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:52:14.846015 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:52:14.848974 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:52:14.855732 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4681 11:52:14.858765 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4682 11:52:14.862453 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:52:14.865732 Total UI for P1: 0, mck2ui 16
4684 11:52:14.869265 best dqsien dly found for B0: ( 0, 13, 10)
4685 11:52:14.872241 Total UI for P1: 0, mck2ui 16
4686 11:52:14.875359 best dqsien dly found for B1: ( 0, 13, 14)
4687 11:52:14.878604 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4688 11:52:14.881901 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4689 11:52:14.881983
4690 11:52:14.888954 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4691 11:52:14.891816 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4692 11:52:14.895278 [Gating] SW calibration Done
4693 11:52:14.895361 ==
4694 11:52:14.898966 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 11:52:14.901553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 11:52:14.901635 ==
4697 11:52:14.901701 RX Vref Scan: 0
4698 11:52:14.901762
4699 11:52:14.905342 RX Vref 0 -> 0, step: 1
4700 11:52:14.905424
4701 11:52:14.908588 RX Delay -230 -> 252, step: 16
4702 11:52:14.911424 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4703 11:52:14.918707 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4704 11:52:14.921331 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4705 11:52:14.924870 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4706 11:52:14.928554 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4707 11:52:14.931354 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4708 11:52:14.937791 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4709 11:52:14.941054 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4710 11:52:14.944361 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4711 11:52:14.947738 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4712 11:52:14.954195 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4713 11:52:14.957643 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4714 11:52:14.961238 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4715 11:52:14.964573 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4716 11:52:14.971200 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4717 11:52:14.974769 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4718 11:52:14.975160 ==
4719 11:52:14.977789 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 11:52:14.981242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 11:52:14.981666 ==
4722 11:52:14.984600 DQS Delay:
4723 11:52:14.985022 DQS0 = 0, DQS1 = 0
4724 11:52:14.987756 DQM Delay:
4725 11:52:14.988177 DQM0 = 42, DQM1 = 39
4726 11:52:14.988514 DQ Delay:
4727 11:52:14.991029 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4728 11:52:14.994020 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4729 11:52:14.997404 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4730 11:52:15.000603 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4731 11:52:15.001158
4732 11:52:15.001581
4733 11:52:15.004034 ==
4734 11:52:15.007467 Dram Type= 6, Freq= 0, CH_1, rank 1
4735 11:52:15.011130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4736 11:52:15.011556 ==
4737 11:52:15.011898
4738 11:52:15.012214
4739 11:52:15.014339 TX Vref Scan disable
4740 11:52:15.014822 == TX Byte 0 ==
4741 11:52:15.020761 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4742 11:52:15.023815 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4743 11:52:15.024240 == TX Byte 1 ==
4744 11:52:15.030634 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4745 11:52:15.033673 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4746 11:52:15.034094 ==
4747 11:52:15.036982 Dram Type= 6, Freq= 0, CH_1, rank 1
4748 11:52:15.040325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4749 11:52:15.040752 ==
4750 11:52:15.041093
4751 11:52:15.041405
4752 11:52:15.043755 TX Vref Scan disable
4753 11:52:15.047019 == TX Byte 0 ==
4754 11:52:15.050473 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4755 11:52:15.053784 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4756 11:52:15.057256 == TX Byte 1 ==
4757 11:52:15.060169 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4758 11:52:15.064117 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4759 11:52:15.064539
4760 11:52:15.066737 [DATLAT]
4761 11:52:15.067163 Freq=600, CH1 RK1
4762 11:52:15.067508
4763 11:52:15.070365 DATLAT Default: 0x9
4764 11:52:15.070788 0, 0xFFFF, sum = 0
4765 11:52:15.073245 1, 0xFFFF, sum = 0
4766 11:52:15.073733 2, 0xFFFF, sum = 0
4767 11:52:15.076528 3, 0xFFFF, sum = 0
4768 11:52:15.076958 4, 0xFFFF, sum = 0
4769 11:52:15.080004 5, 0xFFFF, sum = 0
4770 11:52:15.083440 6, 0xFFFF, sum = 0
4771 11:52:15.083896 7, 0xFFFF, sum = 0
4772 11:52:15.084246 8, 0x0, sum = 1
4773 11:52:15.087236 9, 0x0, sum = 2
4774 11:52:15.087695 10, 0x0, sum = 3
4775 11:52:15.090308 11, 0x0, sum = 4
4776 11:52:15.090853 best_step = 9
4777 11:52:15.091210
4778 11:52:15.091534 ==
4779 11:52:15.092792 Dram Type= 6, Freq= 0, CH_1, rank 1
4780 11:52:15.099276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4781 11:52:15.099706 ==
4782 11:52:15.100047 RX Vref Scan: 0
4783 11:52:15.100360
4784 11:52:15.103102 RX Vref 0 -> 0, step: 1
4785 11:52:15.103527
4786 11:52:15.105966 RX Delay -179 -> 252, step: 8
4787 11:52:15.109358 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4788 11:52:15.116130 iDelay=205, Bit 1, Center 32 (-131 ~ 196) 328
4789 11:52:15.119517 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4790 11:52:15.122687 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4791 11:52:15.125975 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4792 11:52:15.132240 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4793 11:52:15.135675 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4794 11:52:15.139180 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4795 11:52:15.142094 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4796 11:52:15.148708 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4797 11:52:15.152336 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4798 11:52:15.155707 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4799 11:52:15.158511 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4800 11:52:15.165764 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4801 11:52:15.168648 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4802 11:52:15.171948 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4803 11:52:15.172375 ==
4804 11:52:15.175513 Dram Type= 6, Freq= 0, CH_1, rank 1
4805 11:52:15.178926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4806 11:52:15.181852 ==
4807 11:52:15.182312 DQS Delay:
4808 11:52:15.182662 DQS0 = 0, DQS1 = 0
4809 11:52:15.185289 DQM Delay:
4810 11:52:15.185710 DQM0 = 36, DQM1 = 35
4811 11:52:15.188548 DQ Delay:
4812 11:52:15.188971 DQ0 =40, DQ1 =32, DQ2 =28, DQ3 =32
4813 11:52:15.191595 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4814 11:52:15.195071 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =24
4815 11:52:15.198379 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4816 11:52:15.201445
4817 11:52:15.202094
4818 11:52:15.208073 [DQSOSCAuto] RK1, (LSB)MR18= 0x3a5f, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
4819 11:52:15.211686 CH1 RK1: MR19=808, MR18=3A5F
4820 11:52:15.217841 CH1_RK1: MR19=0x808, MR18=0x3A5F, DQSOSC=391, MR23=63, INC=171, DEC=114
4821 11:52:15.221208 [RxdqsGatingPostProcess] freq 600
4822 11:52:15.224497 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4823 11:52:15.227880 Pre-setting of DQS Precalculation
4824 11:52:15.234641 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4825 11:52:15.240958 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4826 11:52:15.247618 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4827 11:52:15.248043
4828 11:52:15.248377
4829 11:52:15.251130 [Calibration Summary] 1200 Mbps
4830 11:52:15.251551 CH 0, Rank 0
4831 11:52:15.254411 SW Impedance : PASS
4832 11:52:15.257845 DUTY Scan : NO K
4833 11:52:15.258297 ZQ Calibration : PASS
4834 11:52:15.261024 Jitter Meter : NO K
4835 11:52:15.264420 CBT Training : PASS
4836 11:52:15.264841 Write leveling : PASS
4837 11:52:15.267378 RX DQS gating : PASS
4838 11:52:15.270902 RX DQ/DQS(RDDQC) : PASS
4839 11:52:15.271325 TX DQ/DQS : PASS
4840 11:52:15.273851 RX DATLAT : PASS
4841 11:52:15.277366 RX DQ/DQS(Engine): PASS
4842 11:52:15.277787 TX OE : NO K
4843 11:52:15.280608 All Pass.
4844 11:52:15.281028
4845 11:52:15.281365 CH 0, Rank 1
4846 11:52:15.283722 SW Impedance : PASS
4847 11:52:15.284147 DUTY Scan : NO K
4848 11:52:15.286913 ZQ Calibration : PASS
4849 11:52:15.290721 Jitter Meter : NO K
4850 11:52:15.291159 CBT Training : PASS
4851 11:52:15.293794 Write leveling : PASS
4852 11:52:15.294215 RX DQS gating : PASS
4853 11:52:15.297646 RX DQ/DQS(RDDQC) : PASS
4854 11:52:15.300750 TX DQ/DQS : PASS
4855 11:52:15.301174 RX DATLAT : PASS
4856 11:52:15.303772 RX DQ/DQS(Engine): PASS
4857 11:52:15.306971 TX OE : NO K
4858 11:52:15.307395 All Pass.
4859 11:52:15.307729
4860 11:52:15.308044 CH 1, Rank 0
4861 11:52:15.310695 SW Impedance : PASS
4862 11:52:15.313610 DUTY Scan : NO K
4863 11:52:15.314045 ZQ Calibration : PASS
4864 11:52:15.317068 Jitter Meter : NO K
4865 11:52:15.320604 CBT Training : PASS
4866 11:52:15.321035 Write leveling : PASS
4867 11:52:15.323705 RX DQS gating : PASS
4868 11:52:15.326612 RX DQ/DQS(RDDQC) : PASS
4869 11:52:15.327026 TX DQ/DQS : PASS
4870 11:52:15.329836 RX DATLAT : PASS
4871 11:52:15.333622 RX DQ/DQS(Engine): PASS
4872 11:52:15.334057 TX OE : NO K
4873 11:52:15.336559 All Pass.
4874 11:52:15.336993
4875 11:52:15.337343 CH 1, Rank 1
4876 11:52:15.340229 SW Impedance : PASS
4877 11:52:15.340671 DUTY Scan : NO K
4878 11:52:15.343315 ZQ Calibration : PASS
4879 11:52:15.346683 Jitter Meter : NO K
4880 11:52:15.347253 CBT Training : PASS
4881 11:52:15.349747 Write leveling : PASS
4882 11:52:15.353076 RX DQS gating : PASS
4883 11:52:15.353489 RX DQ/DQS(RDDQC) : PASS
4884 11:52:15.356419 TX DQ/DQS : PASS
4885 11:52:15.359809 RX DATLAT : PASS
4886 11:52:15.360286 RX DQ/DQS(Engine): PASS
4887 11:52:15.363276 TX OE : NO K
4888 11:52:15.363710 All Pass.
4889 11:52:15.364042
4890 11:52:15.366808 DramC Write-DBI off
4891 11:52:15.369576 PER_BANK_REFRESH: Hybrid Mode
4892 11:52:15.370073 TX_TRACKING: ON
4893 11:52:15.379245 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4894 11:52:15.382818 [FAST_K] Save calibration result to emmc
4895 11:52:15.386106 dramc_set_vcore_voltage set vcore to 662500
4896 11:52:15.389552 Read voltage for 933, 3
4897 11:52:15.389967 Vio18 = 0
4898 11:52:15.390360 Vcore = 662500
4899 11:52:15.392818 Vdram = 0
4900 11:52:15.393240 Vddq = 0
4901 11:52:15.393588 Vmddr = 0
4902 11:52:15.399284 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4903 11:52:15.402966 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4904 11:52:15.405672 MEM_TYPE=3, freq_sel=17
4905 11:52:15.409122 sv_algorithm_assistance_LP4_1600
4906 11:52:15.412037 ============ PULL DRAM RESETB DOWN ============
4907 11:52:15.415955 ========== PULL DRAM RESETB DOWN end =========
4908 11:52:15.421822 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4909 11:52:15.425664 ===================================
4910 11:52:15.428877 LPDDR4 DRAM CONFIGURATION
4911 11:52:15.432270 ===================================
4912 11:52:15.432695 EX_ROW_EN[0] = 0x0
4913 11:52:15.435439 EX_ROW_EN[1] = 0x0
4914 11:52:15.435865 LP4Y_EN = 0x0
4915 11:52:15.438749 WORK_FSP = 0x0
4916 11:52:15.439171 WL = 0x3
4917 11:52:15.441549 RL = 0x3
4918 11:52:15.441983 BL = 0x2
4919 11:52:15.445070 RPST = 0x0
4920 11:52:15.445489 RD_PRE = 0x0
4921 11:52:15.448514 WR_PRE = 0x1
4922 11:52:15.448935 WR_PST = 0x0
4923 11:52:15.452338 DBI_WR = 0x0
4924 11:52:15.454804 DBI_RD = 0x0
4925 11:52:15.455227 OTF = 0x1
4926 11:52:15.458526 ===================================
4927 11:52:15.461876 ===================================
4928 11:52:15.462333 ANA top config
4929 11:52:15.464778 ===================================
4930 11:52:15.468187 DLL_ASYNC_EN = 0
4931 11:52:15.471275 ALL_SLAVE_EN = 1
4932 11:52:15.474793 NEW_RANK_MODE = 1
4933 11:52:15.478203 DLL_IDLE_MODE = 1
4934 11:52:15.478657 LP45_APHY_COMB_EN = 1
4935 11:52:15.481247 TX_ODT_DIS = 1
4936 11:52:15.484677 NEW_8X_MODE = 1
4937 11:52:15.487796 ===================================
4938 11:52:15.491039 ===================================
4939 11:52:15.494624 data_rate = 1866
4940 11:52:15.497906 CKR = 1
4941 11:52:15.501063 DQ_P2S_RATIO = 8
4942 11:52:15.504223 ===================================
4943 11:52:15.504654 CA_P2S_RATIO = 8
4944 11:52:15.507418 DQ_CA_OPEN = 0
4945 11:52:15.510556 DQ_SEMI_OPEN = 0
4946 11:52:15.514201 CA_SEMI_OPEN = 0
4947 11:52:15.517764 CA_FULL_RATE = 0
4948 11:52:15.521188 DQ_CKDIV4_EN = 1
4949 11:52:15.521612 CA_CKDIV4_EN = 1
4950 11:52:15.523937 CA_PREDIV_EN = 0
4951 11:52:15.527465 PH8_DLY = 0
4952 11:52:15.530710 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4953 11:52:15.534159 DQ_AAMCK_DIV = 4
4954 11:52:15.537674 CA_AAMCK_DIV = 4
4955 11:52:15.538097 CA_ADMCK_DIV = 4
4956 11:52:15.540926 DQ_TRACK_CA_EN = 0
4957 11:52:15.543999 CA_PICK = 933
4958 11:52:15.547429 CA_MCKIO = 933
4959 11:52:15.550754 MCKIO_SEMI = 0
4960 11:52:15.553927 PLL_FREQ = 3732
4961 11:52:15.557425 DQ_UI_PI_RATIO = 32
4962 11:52:15.560346 CA_UI_PI_RATIO = 0
4963 11:52:15.560772 ===================================
4964 11:52:15.563331 ===================================
4965 11:52:15.566952 memory_type:LPDDR4
4966 11:52:15.570116 GP_NUM : 10
4967 11:52:15.570568 SRAM_EN : 1
4968 11:52:15.573259 MD32_EN : 0
4969 11:52:15.576627 ===================================
4970 11:52:15.580062 [ANA_INIT] >>>>>>>>>>>>>>
4971 11:52:15.583702 <<<<<< [CONFIGURE PHASE]: ANA_TX
4972 11:52:15.586421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4973 11:52:15.590289 ===================================
4974 11:52:15.593096 data_rate = 1866,PCW = 0X8f00
4975 11:52:15.596639 ===================================
4976 11:52:15.599994 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4977 11:52:15.602884 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4978 11:52:15.609883 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4979 11:52:15.612956 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4980 11:52:15.616940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4981 11:52:15.619556 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4982 11:52:15.622780 [ANA_INIT] flow start
4983 11:52:15.625936 [ANA_INIT] PLL >>>>>>>>
4984 11:52:15.626391 [ANA_INIT] PLL <<<<<<<<
4985 11:52:15.629391 [ANA_INIT] MIDPI >>>>>>>>
4986 11:52:15.633037 [ANA_INIT] MIDPI <<<<<<<<
4987 11:52:15.636252 [ANA_INIT] DLL >>>>>>>>
4988 11:52:15.636679 [ANA_INIT] flow end
4989 11:52:15.639517 ============ LP4 DIFF to SE enter ============
4990 11:52:15.645853 ============ LP4 DIFF to SE exit ============
4991 11:52:15.646322 [ANA_INIT] <<<<<<<<<<<<<
4992 11:52:15.649379 [Flow] Enable top DCM control >>>>>
4993 11:52:15.652669 [Flow] Enable top DCM control <<<<<
4994 11:52:15.656230 Enable DLL master slave shuffle
4995 11:52:15.662672 ==============================================================
4996 11:52:15.663097 Gating Mode config
4997 11:52:15.669088 ==============================================================
4998 11:52:15.672871 Config description:
4999 11:52:15.681977 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5000 11:52:15.688617 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5001 11:52:15.692290 SELPH_MODE 0: By rank 1: By Phase
5002 11:52:15.698880 ==============================================================
5003 11:52:15.701706 GAT_TRACK_EN = 1
5004 11:52:15.705299 RX_GATING_MODE = 2
5005 11:52:15.708329 RX_GATING_TRACK_MODE = 2
5006 11:52:15.708750 SELPH_MODE = 1
5007 11:52:15.711888 PICG_EARLY_EN = 1
5008 11:52:15.715542 VALID_LAT_VALUE = 1
5009 11:52:15.721518 ==============================================================
5010 11:52:15.724869 Enter into Gating configuration >>>>
5011 11:52:15.728207 Exit from Gating configuration <<<<
5012 11:52:15.731502 Enter into DVFS_PRE_config >>>>>
5013 11:52:15.741435 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5014 11:52:15.744926 Exit from DVFS_PRE_config <<<<<
5015 11:52:15.747999 Enter into PICG configuration >>>>
5016 11:52:15.750990 Exit from PICG configuration <<<<
5017 11:52:15.754925 [RX_INPUT] configuration >>>>>
5018 11:52:15.757657 [RX_INPUT] configuration <<<<<
5019 11:52:15.761482 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5020 11:52:15.767627 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5021 11:52:15.774077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5022 11:52:15.780717 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5023 11:52:15.787631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5024 11:52:15.793816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5025 11:52:15.797166 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5026 11:52:15.800691 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5027 11:52:15.803851 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5028 11:52:15.810125 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5029 11:52:15.813613 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5030 11:52:15.816621 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5031 11:52:15.820276 ===================================
5032 11:52:15.823578 LPDDR4 DRAM CONFIGURATION
5033 11:52:15.826541 ===================================
5034 11:52:15.830184 EX_ROW_EN[0] = 0x0
5035 11:52:15.830632 EX_ROW_EN[1] = 0x0
5036 11:52:15.833358 LP4Y_EN = 0x0
5037 11:52:15.833778 WORK_FSP = 0x0
5038 11:52:15.836417 WL = 0x3
5039 11:52:15.836853 RL = 0x3
5040 11:52:15.839717 BL = 0x2
5041 11:52:15.840139 RPST = 0x0
5042 11:52:15.843154 RD_PRE = 0x0
5043 11:52:15.843580 WR_PRE = 0x1
5044 11:52:15.846565 WR_PST = 0x0
5045 11:52:15.846989 DBI_WR = 0x0
5046 11:52:15.849760 DBI_RD = 0x0
5047 11:52:15.850207 OTF = 0x1
5048 11:52:15.853409 ===================================
5049 11:52:15.859622 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5050 11:52:15.863159 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5051 11:52:15.866121 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5052 11:52:15.869373 ===================================
5053 11:52:15.873258 LPDDR4 DRAM CONFIGURATION
5054 11:52:15.875900 ===================================
5055 11:52:15.879674 EX_ROW_EN[0] = 0x10
5056 11:52:15.880097 EX_ROW_EN[1] = 0x0
5057 11:52:15.882888 LP4Y_EN = 0x0
5058 11:52:15.883310 WORK_FSP = 0x0
5059 11:52:15.886191 WL = 0x3
5060 11:52:15.886643 RL = 0x3
5061 11:52:15.889323 BL = 0x2
5062 11:52:15.889744 RPST = 0x0
5063 11:52:15.892625 RD_PRE = 0x0
5064 11:52:15.893047 WR_PRE = 0x1
5065 11:52:15.895533 WR_PST = 0x0
5066 11:52:15.895955 DBI_WR = 0x0
5067 11:52:15.899101 DBI_RD = 0x0
5068 11:52:15.899525 OTF = 0x1
5069 11:52:15.902444 ===================================
5070 11:52:15.908935 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5071 11:52:15.913849 nWR fixed to 30
5072 11:52:15.917002 [ModeRegInit_LP4] CH0 RK0
5073 11:52:15.917084 [ModeRegInit_LP4] CH0 RK1
5074 11:52:15.919928 [ModeRegInit_LP4] CH1 RK0
5075 11:52:15.923254 [ModeRegInit_LP4] CH1 RK1
5076 11:52:15.923340 match AC timing 9
5077 11:52:15.930202 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5078 11:52:15.933534 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5079 11:52:15.936429 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5080 11:52:15.943258 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5081 11:52:15.946223 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5082 11:52:15.946315 ==
5083 11:52:15.949713 Dram Type= 6, Freq= 0, CH_0, rank 0
5084 11:52:15.952773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5085 11:52:15.956463 ==
5086 11:52:15.959903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5087 11:52:15.966131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5088 11:52:15.969189 [CA 0] Center 38 (7~69) winsize 63
5089 11:52:15.972970 [CA 1] Center 37 (7~68) winsize 62
5090 11:52:15.976477 [CA 2] Center 34 (4~65) winsize 62
5091 11:52:15.979676 [CA 3] Center 34 (4~65) winsize 62
5092 11:52:15.982590 [CA 4] Center 33 (3~64) winsize 62
5093 11:52:15.986243 [CA 5] Center 33 (3~63) winsize 61
5094 11:52:15.986391
5095 11:52:15.989455 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5096 11:52:15.989608
5097 11:52:15.992671 [CATrainingPosCal] consider 1 rank data
5098 11:52:15.995848 u2DelayCellTimex100 = 270/100 ps
5099 11:52:15.998845 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5100 11:52:16.002517 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5101 11:52:16.005884 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5102 11:52:16.012002 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5103 11:52:16.015445 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5104 11:52:16.019023 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5105 11:52:16.019105
5106 11:52:16.021860 CA PerBit enable=1, Macro0, CA PI delay=33
5107 11:52:16.021947
5108 11:52:16.025642 [CBTSetCACLKResult] CA Dly = 33
5109 11:52:16.025737 CS Dly: 6 (0~37)
5110 11:52:16.025812 ==
5111 11:52:16.028778 Dram Type= 6, Freq= 0, CH_0, rank 1
5112 11:52:16.035747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5113 11:52:16.036172 ==
5114 11:52:16.039119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5115 11:52:16.045635 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5116 11:52:16.048998 [CA 0] Center 38 (8~69) winsize 62
5117 11:52:16.052359 [CA 1] Center 38 (7~69) winsize 63
5118 11:52:16.055404 [CA 2] Center 34 (4~65) winsize 62
5119 11:52:16.059028 [CA 3] Center 34 (4~65) winsize 62
5120 11:52:16.062313 [CA 4] Center 33 (3~64) winsize 62
5121 11:52:16.065868 [CA 5] Center 32 (2~63) winsize 62
5122 11:52:16.066331
5123 11:52:16.068807 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5124 11:52:16.069235
5125 11:52:16.072328 [CATrainingPosCal] consider 2 rank data
5126 11:52:16.075556 u2DelayCellTimex100 = 270/100 ps
5127 11:52:16.078608 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5128 11:52:16.085388 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5129 11:52:16.088718 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5130 11:52:16.091972 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5131 11:52:16.095619 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5132 11:52:16.098421 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5133 11:52:16.098848
5134 11:52:16.101773 CA PerBit enable=1, Macro0, CA PI delay=33
5135 11:52:16.102196
5136 11:52:16.105426 [CBTSetCACLKResult] CA Dly = 33
5137 11:52:16.105898 CS Dly: 7 (0~39)
5138 11:52:16.108927
5139 11:52:16.111683 ----->DramcWriteLeveling(PI) begin...
5140 11:52:16.112109 ==
5141 11:52:16.115174 Dram Type= 6, Freq= 0, CH_0, rank 0
5142 11:52:16.118402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5143 11:52:16.118829 ==
5144 11:52:16.121880 Write leveling (Byte 0): 33 => 33
5145 11:52:16.125417 Write leveling (Byte 1): 28 => 28
5146 11:52:16.128322 DramcWriteLeveling(PI) end<-----
5147 11:52:16.128744
5148 11:52:16.129080 ==
5149 11:52:16.131819 Dram Type= 6, Freq= 0, CH_0, rank 0
5150 11:52:16.135347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5151 11:52:16.135771 ==
5152 11:52:16.138543 [Gating] SW mode calibration
5153 11:52:16.145151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5154 11:52:16.151711 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5155 11:52:16.154885 0 14 0 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
5156 11:52:16.157726 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5157 11:52:16.164389 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5158 11:52:16.167797 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5159 11:52:16.171534 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 11:52:16.177670 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 11:52:16.180872 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5162 11:52:16.184141 0 14 28 | B1->B0 | 3434 2c2c | 1 0 | (1 0) (1 0)
5163 11:52:16.190620 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
5164 11:52:16.193908 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5165 11:52:16.197821 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5166 11:52:16.203982 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5167 11:52:16.207426 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 11:52:16.210660 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 11:52:16.217516 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5170 11:52:16.220418 0 15 28 | B1->B0 | 2525 3535 | 0 0 | (0 0) (0 0)
5171 11:52:16.223771 1 0 0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
5172 11:52:16.230594 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 11:52:16.233884 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5174 11:52:16.237127 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5175 11:52:16.243769 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 11:52:16.246730 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 11:52:16.250169 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5178 11:52:16.256682 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5179 11:52:16.260402 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5180 11:52:16.263461 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5181 11:52:16.269844 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5182 11:52:16.273114 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5183 11:52:16.276439 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 11:52:16.283452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 11:52:16.286294 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 11:52:16.289863 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 11:52:16.296689 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 11:52:16.299630 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:52:16.302850 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:52:16.309837 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:52:16.312685 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:52:16.316237 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:52:16.322531 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:52:16.326010 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5195 11:52:16.329081 Total UI for P1: 0, mck2ui 16
5196 11:52:16.332586 best dqsien dly found for B0: ( 1, 2, 26)
5197 11:52:16.336007 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5198 11:52:16.339469 Total UI for P1: 0, mck2ui 16
5199 11:52:16.342527 best dqsien dly found for B1: ( 1, 2, 30)
5200 11:52:16.345842 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5201 11:52:16.349398 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5202 11:52:16.352670
5203 11:52:16.355683 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5204 11:52:16.359051 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5205 11:52:16.362586 [Gating] SW calibration Done
5206 11:52:16.363050 ==
5207 11:52:16.365756 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:52:16.368980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:52:16.369408 ==
5210 11:52:16.369746 RX Vref Scan: 0
5211 11:52:16.372081
5212 11:52:16.372501 RX Vref 0 -> 0, step: 1
5213 11:52:16.372838
5214 11:52:16.375377 RX Delay -80 -> 252, step: 8
5215 11:52:16.378636 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5216 11:52:16.382770 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5217 11:52:16.388981 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5218 11:52:16.391979 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5219 11:52:16.395204 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5220 11:52:16.398531 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5221 11:52:16.401747 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5222 11:52:16.408612 iDelay=208, Bit 7, Center 107 (16 ~ 199) 184
5223 11:52:16.412042 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5224 11:52:16.415567 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5225 11:52:16.418574 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5226 11:52:16.421965 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5227 11:52:16.428279 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5228 11:52:16.431479 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5229 11:52:16.435035 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5230 11:52:16.438187 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5231 11:52:16.438657 ==
5232 11:52:16.441727 Dram Type= 6, Freq= 0, CH_0, rank 0
5233 11:52:16.444599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5234 11:52:16.445024 ==
5235 11:52:16.448170 DQS Delay:
5236 11:52:16.448592 DQS0 = 0, DQS1 = 0
5237 11:52:16.451674 DQM Delay:
5238 11:52:16.452097 DQM0 = 103, DQM1 = 87
5239 11:52:16.454574 DQ Delay:
5240 11:52:16.454995 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5241 11:52:16.461409 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =107
5242 11:52:16.464908 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5243 11:52:16.468148 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5244 11:52:16.468574
5245 11:52:16.468909
5246 11:52:16.469224 ==
5247 11:52:16.471017 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 11:52:16.474331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 11:52:16.474761 ==
5250 11:52:16.475099
5251 11:52:16.475418
5252 11:52:16.477887 TX Vref Scan disable
5253 11:52:16.478393 == TX Byte 0 ==
5254 11:52:16.484135 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5255 11:52:16.487776 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5256 11:52:16.488203 == TX Byte 1 ==
5257 11:52:16.494121 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5258 11:52:16.497343 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5259 11:52:16.497768 ==
5260 11:52:16.500581 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 11:52:16.503907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 11:52:16.504508 ==
5263 11:52:16.507377
5264 11:52:16.507798
5265 11:52:16.508297 TX Vref Scan disable
5266 11:52:16.510842 == TX Byte 0 ==
5267 11:52:16.513938 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5268 11:52:16.520791 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5269 11:52:16.521216 == TX Byte 1 ==
5270 11:52:16.523835 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5271 11:52:16.530912 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5272 11:52:16.531338
5273 11:52:16.531676 [DATLAT]
5274 11:52:16.531993 Freq=933, CH0 RK0
5275 11:52:16.532299
5276 11:52:16.533827 DATLAT Default: 0xd
5277 11:52:16.537345 0, 0xFFFF, sum = 0
5278 11:52:16.537775 1, 0xFFFF, sum = 0
5279 11:52:16.540517 2, 0xFFFF, sum = 0
5280 11:52:16.540945 3, 0xFFFF, sum = 0
5281 11:52:16.543739 4, 0xFFFF, sum = 0
5282 11:52:16.544169 5, 0xFFFF, sum = 0
5283 11:52:16.546765 6, 0xFFFF, sum = 0
5284 11:52:16.547218 7, 0xFFFF, sum = 0
5285 11:52:16.550664 8, 0xFFFF, sum = 0
5286 11:52:16.551093 9, 0xFFFF, sum = 0
5287 11:52:16.553445 10, 0x0, sum = 1
5288 11:52:16.553870 11, 0x0, sum = 2
5289 11:52:16.556900 12, 0x0, sum = 3
5290 11:52:16.557332 13, 0x0, sum = 4
5291 11:52:16.560270 best_step = 11
5292 11:52:16.560694
5293 11:52:16.561030 ==
5294 11:52:16.563673 Dram Type= 6, Freq= 0, CH_0, rank 0
5295 11:52:16.566921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5296 11:52:16.567471 ==
5297 11:52:16.567820 RX Vref Scan: 1
5298 11:52:16.569994
5299 11:52:16.570444 RX Vref 0 -> 0, step: 1
5300 11:52:16.570788
5301 11:52:16.573432 RX Delay -61 -> 252, step: 4
5302 11:52:16.573851
5303 11:52:16.576761 Set Vref, RX VrefLevel [Byte0]: 58
5304 11:52:16.579757 [Byte1]: 49
5305 11:52:16.583482
5306 11:52:16.583903 Final RX Vref Byte 0 = 58 to rank0
5307 11:52:16.586459 Final RX Vref Byte 1 = 49 to rank0
5308 11:52:16.590242 Final RX Vref Byte 0 = 58 to rank1
5309 11:52:16.593249 Final RX Vref Byte 1 = 49 to rank1==
5310 11:52:16.596982 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 11:52:16.603219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 11:52:16.603643 ==
5313 11:52:16.603982 DQS Delay:
5314 11:52:16.604301 DQS0 = 0, DQS1 = 0
5315 11:52:16.606185 DQM Delay:
5316 11:52:16.606668 DQM0 = 102, DQM1 = 89
5317 11:52:16.609716 DQ Delay:
5318 11:52:16.613259 DQ0 =102, DQ1 =102, DQ2 =98, DQ3 =100
5319 11:52:16.616356 DQ4 =104, DQ5 =96, DQ6 =110, DQ7 =108
5320 11:52:16.619647 DQ8 =82, DQ9 =76, DQ10 =90, DQ11 =84
5321 11:52:16.623066 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =96
5322 11:52:16.623488
5323 11:52:16.623823
5324 11:52:16.629353 [DQSOSCAuto] RK0, (LSB)MR18= 0x1913, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5325 11:52:16.632826 CH0 RK0: MR19=505, MR18=1913
5326 11:52:16.639193 CH0_RK0: MR19=0x505, MR18=0x1913, DQSOSC=413, MR23=63, INC=63, DEC=42
5327 11:52:16.639620
5328 11:52:16.642812 ----->DramcWriteLeveling(PI) begin...
5329 11:52:16.643265 ==
5330 11:52:16.646305 Dram Type= 6, Freq= 0, CH_0, rank 1
5331 11:52:16.649281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5332 11:52:16.649708 ==
5333 11:52:16.652762 Write leveling (Byte 0): 31 => 31
5334 11:52:16.656215 Write leveling (Byte 1): 29 => 29
5335 11:52:16.659302 DramcWriteLeveling(PI) end<-----
5336 11:52:16.659742
5337 11:52:16.660082 ==
5338 11:52:16.663145 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 11:52:16.668997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 11:52:16.669424 ==
5341 11:52:16.669801 [Gating] SW mode calibration
5342 11:52:16.678907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5343 11:52:16.682362 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5344 11:52:16.689143 0 14 0 | B1->B0 | 2b2b 3434 | 1 1 | (1 1) (0 0)
5345 11:52:16.692614 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5346 11:52:16.695647 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5347 11:52:16.702032 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5348 11:52:16.704997 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5349 11:52:16.708540 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 11:52:16.715465 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 11:52:16.718739 0 14 28 | B1->B0 | 3232 2626 | 1 0 | (1 1) (0 0)
5352 11:52:16.721952 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
5353 11:52:16.728470 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5354 11:52:16.731939 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5355 11:52:16.734768 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5356 11:52:16.741765 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5357 11:52:16.745356 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 11:52:16.748519 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5359 11:52:16.754910 0 15 28 | B1->B0 | 2727 3f3f | 0 0 | (1 1) (0 0)
5360 11:52:16.758123 1 0 0 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5361 11:52:16.761338 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5362 11:52:16.768120 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5363 11:52:16.771224 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5364 11:52:16.774316 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 11:52:16.780782 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 11:52:16.784170 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5367 11:52:16.787598 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5368 11:52:16.793997 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5369 11:52:16.797678 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5370 11:52:16.800725 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5371 11:52:16.807545 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5372 11:52:16.810493 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 11:52:16.814090 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 11:52:16.820873 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 11:52:16.823668 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 11:52:16.827242 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 11:52:16.834063 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:52:16.836922 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:52:16.840402 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:52:16.847200 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:52:16.850832 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:52:16.853534 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5383 11:52:16.860102 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5384 11:52:16.860524 Total UI for P1: 0, mck2ui 16
5385 11:52:16.863395 best dqsien dly found for B0: ( 1, 2, 24)
5386 11:52:16.870313 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5387 11:52:16.873702 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 11:52:16.876896 Total UI for P1: 0, mck2ui 16
5389 11:52:16.879753 best dqsien dly found for B1: ( 1, 3, 0)
5390 11:52:16.883324 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5391 11:52:16.887095 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5392 11:52:16.887517
5393 11:52:16.890036 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5394 11:52:16.896404 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5395 11:52:16.896834 [Gating] SW calibration Done
5396 11:52:16.897274 ==
5397 11:52:16.899911 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 11:52:16.906335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 11:52:16.906765 ==
5400 11:52:16.907194 RX Vref Scan: 0
5401 11:52:16.907518
5402 11:52:16.909950 RX Vref 0 -> 0, step: 1
5403 11:52:16.910421
5404 11:52:16.913201 RX Delay -80 -> 252, step: 8
5405 11:52:16.916118 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5406 11:52:16.919533 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5407 11:52:16.922987 iDelay=200, Bit 2, Center 95 (8 ~ 183) 176
5408 11:52:16.926223 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5409 11:52:16.932778 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5410 11:52:16.936246 iDelay=200, Bit 5, Center 91 (0 ~ 183) 184
5411 11:52:16.939524 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5412 11:52:16.942373 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5413 11:52:16.945867 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5414 11:52:16.952471 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5415 11:52:16.955913 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5416 11:52:16.958871 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5417 11:52:16.962197 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5418 11:52:16.965733 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5419 11:52:16.971915 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5420 11:52:16.975122 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5421 11:52:16.975551 ==
5422 11:52:16.978959 Dram Type= 6, Freq= 0, CH_0, rank 1
5423 11:52:16.982126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5424 11:52:16.982576 ==
5425 11:52:16.985169 DQS Delay:
5426 11:52:16.985590 DQS0 = 0, DQS1 = 0
5427 11:52:16.985927 DQM Delay:
5428 11:52:16.988375 DQM0 = 100, DQM1 = 88
5429 11:52:16.988800 DQ Delay:
5430 11:52:16.992217 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =99
5431 11:52:16.995114 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5432 11:52:16.998516 DQ8 =79, DQ9 =75, DQ10 =91, DQ11 =83
5433 11:52:17.002217 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5434 11:52:17.002773
5435 11:52:17.003146
5436 11:52:17.003508 ==
5437 11:52:17.004887 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 11:52:17.011762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 11:52:17.012268 ==
5440 11:52:17.012615
5441 11:52:17.013010
5442 11:52:17.013347 TX Vref Scan disable
5443 11:52:17.015797 == TX Byte 0 ==
5444 11:52:17.018597 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5445 11:52:17.025678 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5446 11:52:17.026166 == TX Byte 1 ==
5447 11:52:17.028870 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5448 11:52:17.035122 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5449 11:52:17.035630 ==
5450 11:52:17.038537 Dram Type= 6, Freq= 0, CH_0, rank 1
5451 11:52:17.042004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5452 11:52:17.042556 ==
5453 11:52:17.042925
5454 11:52:17.043293
5455 11:52:17.045408 TX Vref Scan disable
5456 11:52:17.045922 == TX Byte 0 ==
5457 11:52:17.051556 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5458 11:52:17.055082 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5459 11:52:17.058237 == TX Byte 1 ==
5460 11:52:17.061805 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5461 11:52:17.065219 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5462 11:52:17.065650
5463 11:52:17.066078 [DATLAT]
5464 11:52:17.068568 Freq=933, CH0 RK1
5465 11:52:17.069000
5466 11:52:17.069423 DATLAT Default: 0xb
5467 11:52:17.071440 0, 0xFFFF, sum = 0
5468 11:52:17.074839 1, 0xFFFF, sum = 0
5469 11:52:17.075278 2, 0xFFFF, sum = 0
5470 11:52:17.078155 3, 0xFFFF, sum = 0
5471 11:52:17.078797 4, 0xFFFF, sum = 0
5472 11:52:17.081714 5, 0xFFFF, sum = 0
5473 11:52:17.082148 6, 0xFFFF, sum = 0
5474 11:52:17.084747 7, 0xFFFF, sum = 0
5475 11:52:17.085294 8, 0xFFFF, sum = 0
5476 11:52:17.087700 9, 0xFFFF, sum = 0
5477 11:52:17.088139 10, 0x0, sum = 1
5478 11:52:17.091080 11, 0x0, sum = 2
5479 11:52:17.091561 12, 0x0, sum = 3
5480 11:52:17.094867 13, 0x0, sum = 4
5481 11:52:17.095322 best_step = 11
5482 11:52:17.095766
5483 11:52:17.096095 ==
5484 11:52:17.097521 Dram Type= 6, Freq= 0, CH_0, rank 1
5485 11:52:17.101166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5486 11:52:17.104484 ==
5487 11:52:17.104902 RX Vref Scan: 0
5488 11:52:17.105234
5489 11:52:17.107446 RX Vref 0 -> 0, step: 1
5490 11:52:17.107865
5491 11:52:17.110791 RX Delay -61 -> 252, step: 4
5492 11:52:17.114449 iDelay=199, Bit 0, Center 100 (15 ~ 186) 172
5493 11:52:17.117420 iDelay=199, Bit 1, Center 102 (15 ~ 190) 176
5494 11:52:17.124389 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5495 11:52:17.127509 iDelay=199, Bit 3, Center 98 (11 ~ 186) 176
5496 11:52:17.130842 iDelay=199, Bit 4, Center 102 (15 ~ 190) 176
5497 11:52:17.134204 iDelay=199, Bit 5, Center 92 (7 ~ 178) 172
5498 11:52:17.136962 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5499 11:52:17.143934 iDelay=199, Bit 7, Center 108 (23 ~ 194) 172
5500 11:52:17.147313 iDelay=199, Bit 8, Center 82 (-1 ~ 166) 168
5501 11:52:17.150729 iDelay=199, Bit 9, Center 78 (-9 ~ 166) 176
5502 11:52:17.153486 iDelay=199, Bit 10, Center 92 (7 ~ 178) 172
5503 11:52:17.156833 iDelay=199, Bit 11, Center 84 (-1 ~ 170) 172
5504 11:52:17.160387 iDelay=199, Bit 12, Center 94 (11 ~ 178) 168
5505 11:52:17.167074 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5506 11:52:17.170005 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5507 11:52:17.173390 iDelay=199, Bit 15, Center 96 (11 ~ 182) 172
5508 11:52:17.173813 ==
5509 11:52:17.176820 Dram Type= 6, Freq= 0, CH_0, rank 1
5510 11:52:17.180180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5511 11:52:17.183574 ==
5512 11:52:17.184113 DQS Delay:
5513 11:52:17.184470 DQS0 = 0, DQS1 = 0
5514 11:52:17.186935 DQM Delay:
5515 11:52:17.187437 DQM0 = 100, DQM1 = 90
5516 11:52:17.189740 DQ Delay:
5517 11:52:17.193168 DQ0 =100, DQ1 =102, DQ2 =94, DQ3 =98
5518 11:52:17.196496 DQ4 =102, DQ5 =92, DQ6 =110, DQ7 =108
5519 11:52:17.199955 DQ8 =82, DQ9 =78, DQ10 =92, DQ11 =84
5520 11:52:17.203136 DQ12 =94, DQ13 =94, DQ14 =100, DQ15 =96
5521 11:52:17.203554
5522 11:52:17.203887
5523 11:52:17.209685 [DQSOSCAuto] RK1, (LSB)MR18= 0x1714, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5524 11:52:17.213287 CH0 RK1: MR19=505, MR18=1714
5525 11:52:17.219541 CH0_RK1: MR19=0x505, MR18=0x1714, DQSOSC=414, MR23=63, INC=63, DEC=42
5526 11:52:17.222858 [RxdqsGatingPostProcess] freq 933
5527 11:52:17.226559 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5528 11:52:17.229332 best DQS0 dly(2T, 0.5T) = (0, 10)
5529 11:52:17.232674 best DQS1 dly(2T, 0.5T) = (0, 10)
5530 11:52:17.236059 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5531 11:52:17.239618 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5532 11:52:17.242945 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 11:52:17.245842 best DQS1 dly(2T, 0.5T) = (0, 11)
5534 11:52:17.249318 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 11:52:17.252179 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5536 11:52:17.255599 Pre-setting of DQS Precalculation
5537 11:52:17.262284 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5538 11:52:17.262843 ==
5539 11:52:17.265860 Dram Type= 6, Freq= 0, CH_1, rank 0
5540 11:52:17.269168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5541 11:52:17.269588 ==
5542 11:52:17.275313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5543 11:52:17.278952 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5544 11:52:17.282727 [CA 0] Center 36 (6~67) winsize 62
5545 11:52:17.286110 [CA 1] Center 36 (6~67) winsize 62
5546 11:52:17.289526 [CA 2] Center 34 (4~65) winsize 62
5547 11:52:17.293059 [CA 3] Center 34 (4~65) winsize 62
5548 11:52:17.296133 [CA 4] Center 34 (4~65) winsize 62
5549 11:52:17.299392 [CA 5] Center 33 (3~64) winsize 62
5550 11:52:17.299873
5551 11:52:17.302394 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5552 11:52:17.302828
5553 11:52:17.305643 [CATrainingPosCal] consider 1 rank data
5554 11:52:17.309148 u2DelayCellTimex100 = 270/100 ps
5555 11:52:17.312652 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5556 11:52:17.319302 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5557 11:52:17.322181 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5558 11:52:17.325873 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5559 11:52:17.329101 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5560 11:52:17.332629 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5561 11:52:17.333049
5562 11:52:17.335569 CA PerBit enable=1, Macro0, CA PI delay=33
5563 11:52:17.336025
5564 11:52:17.338730 [CBTSetCACLKResult] CA Dly = 33
5565 11:52:17.342344 CS Dly: 5 (0~36)
5566 11:52:17.342769 ==
5567 11:52:17.345356 Dram Type= 6, Freq= 0, CH_1, rank 1
5568 11:52:17.348739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5569 11:52:17.349175 ==
5570 11:52:17.355249 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5571 11:52:17.358435 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5572 11:52:17.362886 [CA 0] Center 36 (6~66) winsize 61
5573 11:52:17.366227 [CA 1] Center 36 (6~67) winsize 62
5574 11:52:17.369594 [CA 2] Center 34 (4~65) winsize 62
5575 11:52:17.373014 [CA 3] Center 33 (3~64) winsize 62
5576 11:52:17.375918 [CA 4] Center 33 (3~64) winsize 62
5577 11:52:17.379302 [CA 5] Center 33 (3~64) winsize 62
5578 11:52:17.379722
5579 11:52:17.382825 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5580 11:52:17.383311
5581 11:52:17.385805 [CATrainingPosCal] consider 2 rank data
5582 11:52:17.389130 u2DelayCellTimex100 = 270/100 ps
5583 11:52:17.392319 CA0 delay=36 (6~66),Diff = 3 PI (18 cell)
5584 11:52:17.398820 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5585 11:52:17.402280 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 11:52:17.405903 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5587 11:52:17.408720 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5588 11:52:17.412124 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5589 11:52:17.412608
5590 11:52:17.415667 CA PerBit enable=1, Macro0, CA PI delay=33
5591 11:52:17.416084
5592 11:52:17.419162 [CBTSetCACLKResult] CA Dly = 33
5593 11:52:17.422106 CS Dly: 6 (0~38)
5594 11:52:17.422555
5595 11:52:17.425488 ----->DramcWriteLeveling(PI) begin...
5596 11:52:17.425928 ==
5597 11:52:17.429198 Dram Type= 6, Freq= 0, CH_1, rank 0
5598 11:52:17.432276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5599 11:52:17.432700 ==
5600 11:52:17.435204 Write leveling (Byte 0): 26 => 26
5601 11:52:17.438685 Write leveling (Byte 1): 26 => 26
5602 11:52:17.441635 DramcWriteLeveling(PI) end<-----
5603 11:52:17.442053
5604 11:52:17.442469 ==
5605 11:52:17.444859 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 11:52:17.448405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 11:52:17.448828 ==
5608 11:52:17.451869 [Gating] SW mode calibration
5609 11:52:17.458411 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5610 11:52:17.464914 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5611 11:52:17.468322 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5612 11:52:17.471574 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5613 11:52:17.478017 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5614 11:52:17.481225 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5615 11:52:17.487987 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 11:52:17.490969 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 11:52:17.494395 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
5618 11:52:17.498097 0 14 28 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (1 0)
5619 11:52:17.504123 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5620 11:52:17.507685 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5621 11:52:17.511115 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5622 11:52:17.517491 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5623 11:52:17.520655 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 11:52:17.527056 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 11:52:17.530588 0 15 24 | B1->B0 | 2626 2626 | 0 0 | (0 0) (0 0)
5626 11:52:17.533995 0 15 28 | B1->B0 | 3737 3f3f | 0 0 | (1 1) (0 0)
5627 11:52:17.540212 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5628 11:52:17.544515 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5629 11:52:17.547009 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5630 11:52:17.553632 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5631 11:52:17.556807 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 11:52:17.560099 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 11:52:17.566801 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5634 11:52:17.570293 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5635 11:52:17.573179 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5636 11:52:17.579907 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5637 11:52:17.582992 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5638 11:52:17.586515 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5639 11:52:17.593250 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 11:52:17.596267 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 11:52:17.599792 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 11:52:17.606456 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 11:52:17.609433 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 11:52:17.613216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:52:17.619653 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:52:17.622547 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:52:17.626033 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:52:17.632550 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:52:17.635934 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:52:17.639544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5651 11:52:17.646240 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 11:52:17.646929 Total UI for P1: 0, mck2ui 16
5653 11:52:17.652265 best dqsien dly found for B0: ( 1, 2, 28)
5654 11:52:17.652855 Total UI for P1: 0, mck2ui 16
5655 11:52:17.655548 best dqsien dly found for B1: ( 1, 2, 28)
5656 11:52:17.662105 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5657 11:52:17.665122 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5658 11:52:17.665541
5659 11:52:17.668919 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5660 11:52:17.672210 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5661 11:52:17.675471 [Gating] SW calibration Done
5662 11:52:17.675914 ==
5663 11:52:17.678781 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 11:52:17.681977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 11:52:17.682437 ==
5666 11:52:17.685124 RX Vref Scan: 0
5667 11:52:17.685540
5668 11:52:17.685871 RX Vref 0 -> 0, step: 1
5669 11:52:17.686421
5670 11:52:17.688868 RX Delay -80 -> 252, step: 8
5671 11:52:17.692286 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5672 11:52:17.698805 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5673 11:52:17.701498 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5674 11:52:17.705055 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5675 11:52:17.708512 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5676 11:52:17.711843 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5677 11:52:17.714685 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5678 11:52:17.721596 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5679 11:52:17.724896 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5680 11:52:17.727807 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5681 11:52:17.731311 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5682 11:52:17.734799 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5683 11:52:17.741265 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5684 11:52:17.744689 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5685 11:52:17.747682 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5686 11:52:17.751268 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5687 11:52:17.751692 ==
5688 11:52:17.754216 Dram Type= 6, Freq= 0, CH_1, rank 0
5689 11:52:17.757558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5690 11:52:17.760730 ==
5691 11:52:17.761155 DQS Delay:
5692 11:52:17.761498 DQS0 = 0, DQS1 = 0
5693 11:52:17.764116 DQM Delay:
5694 11:52:17.764537 DQM0 = 99, DQM1 = 96
5695 11:52:17.767530 DQ Delay:
5696 11:52:17.771224 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5697 11:52:17.773913 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5698 11:52:17.777293 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5699 11:52:17.780888 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5700 11:52:17.781315
5701 11:52:17.781650
5702 11:52:17.781962 ==
5703 11:52:17.784361 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 11:52:17.787646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 11:52:17.788076 ==
5706 11:52:17.788419
5707 11:52:17.788729
5708 11:52:17.790720 TX Vref Scan disable
5709 11:52:17.793825 == TX Byte 0 ==
5710 11:52:17.797154 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5711 11:52:17.800633 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5712 11:52:17.803828 == TX Byte 1 ==
5713 11:52:17.806832 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 11:52:17.810070 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 11:52:17.810568 ==
5716 11:52:17.813614 Dram Type= 6, Freq= 0, CH_1, rank 0
5717 11:52:17.820085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5718 11:52:17.820664 ==
5719 11:52:17.821253
5720 11:52:17.821602
5721 11:52:17.821908 TX Vref Scan disable
5722 11:52:17.824108 == TX Byte 0 ==
5723 11:52:17.827324 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5724 11:52:17.833521 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5725 11:52:17.833947 == TX Byte 1 ==
5726 11:52:17.836940 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 11:52:17.843436 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 11:52:17.843901
5729 11:52:17.844309 [DATLAT]
5730 11:52:17.844638 Freq=933, CH1 RK0
5731 11:52:17.845022
5732 11:52:17.846790 DATLAT Default: 0xd
5733 11:52:17.850359 0, 0xFFFF, sum = 0
5734 11:52:17.850784 1, 0xFFFF, sum = 0
5735 11:52:17.853680 2, 0xFFFF, sum = 0
5736 11:52:17.854105 3, 0xFFFF, sum = 0
5737 11:52:17.856976 4, 0xFFFF, sum = 0
5738 11:52:17.857432 5, 0xFFFF, sum = 0
5739 11:52:17.859807 6, 0xFFFF, sum = 0
5740 11:52:17.860233 7, 0xFFFF, sum = 0
5741 11:52:17.863470 8, 0xFFFF, sum = 0
5742 11:52:17.863896 9, 0xFFFF, sum = 0
5743 11:52:17.866553 10, 0x0, sum = 1
5744 11:52:17.866976 11, 0x0, sum = 2
5745 11:52:17.869870 12, 0x0, sum = 3
5746 11:52:17.870351 13, 0x0, sum = 4
5747 11:52:17.873332 best_step = 11
5748 11:52:17.873748
5749 11:52:17.874078 ==
5750 11:52:17.876327 Dram Type= 6, Freq= 0, CH_1, rank 0
5751 11:52:17.879977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5752 11:52:17.880397 ==
5753 11:52:17.880730 RX Vref Scan: 1
5754 11:52:17.883072
5755 11:52:17.883486 RX Vref 0 -> 0, step: 1
5756 11:52:17.883828
5757 11:52:17.886747 RX Delay -53 -> 252, step: 4
5758 11:52:17.887165
5759 11:52:17.889913 Set Vref, RX VrefLevel [Byte0]: 53
5760 11:52:17.892721 [Byte1]: 52
5761 11:52:17.896532
5762 11:52:17.896998 Final RX Vref Byte 0 = 53 to rank0
5763 11:52:17.899836 Final RX Vref Byte 1 = 52 to rank0
5764 11:52:17.902909 Final RX Vref Byte 0 = 53 to rank1
5765 11:52:17.905904 Final RX Vref Byte 1 = 52 to rank1==
5766 11:52:17.909492 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 11:52:17.916082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 11:52:17.916567 ==
5769 11:52:17.916945 DQS Delay:
5770 11:52:17.919441 DQS0 = 0, DQS1 = 0
5771 11:52:17.919856 DQM Delay:
5772 11:52:17.920220 DQM0 = 98, DQM1 = 94
5773 11:52:17.922368 DQ Delay:
5774 11:52:17.925751 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5775 11:52:17.929276 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
5776 11:52:17.932738 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5777 11:52:17.935885 DQ12 =104, DQ13 =102, DQ14 =102, DQ15 =104
5778 11:52:17.936326
5779 11:52:17.936663
5780 11:52:17.942680 [DQSOSCAuto] RK0, (LSB)MR18= 0xc1c, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5781 11:52:17.945726 CH1 RK0: MR19=505, MR18=C1C
5782 11:52:17.952250 CH1_RK0: MR19=0x505, MR18=0xC1C, DQSOSC=412, MR23=63, INC=63, DEC=42
5783 11:52:17.952675
5784 11:52:17.955404 ----->DramcWriteLeveling(PI) begin...
5785 11:52:17.955833 ==
5786 11:52:17.958601 Dram Type= 6, Freq= 0, CH_1, rank 1
5787 11:52:17.961918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5788 11:52:17.965576 ==
5789 11:52:17.965995 Write leveling (Byte 0): 27 => 27
5790 11:52:17.968545 Write leveling (Byte 1): 29 => 29
5791 11:52:17.971779 DramcWriteLeveling(PI) end<-----
5792 11:52:17.972232
5793 11:52:17.972568 ==
5794 11:52:17.975324 Dram Type= 6, Freq= 0, CH_1, rank 1
5795 11:52:17.982030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 11:52:17.982596 ==
5797 11:52:17.984992 [Gating] SW mode calibration
5798 11:52:17.991849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5799 11:52:17.995346 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5800 11:52:18.001584 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5801 11:52:18.005152 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 11:52:18.008163 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5803 11:52:18.014688 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 11:52:18.018313 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 11:52:18.021335 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 11:52:18.027883 0 14 24 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
5807 11:52:18.031095 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
5808 11:52:18.034466 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 11:52:18.041178 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 11:52:18.044473 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 11:52:18.047707 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 11:52:18.054595 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 11:52:18.057750 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 11:52:18.060713 0 15 24 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
5815 11:52:18.067320 0 15 28 | B1->B0 | 3a3a 4545 | 1 0 | (0 0) (0 0)
5816 11:52:18.070879 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 11:52:18.074280 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 11:52:18.080837 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 11:52:18.083749 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 11:52:18.087240 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 11:52:18.094205 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 11:52:18.097143 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 11:52:18.100390 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5824 11:52:18.107131 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5825 11:52:18.110071 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 11:52:18.113825 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 11:52:18.119980 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 11:52:18.123280 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 11:52:18.126607 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 11:52:18.133150 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 11:52:18.136684 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 11:52:18.140132 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 11:52:18.146322 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:52:18.149650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:52:18.153058 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:52:18.159632 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:52:18.163033 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:52:18.166565 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5839 11:52:18.172676 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5840 11:52:18.173109 Total UI for P1: 0, mck2ui 16
5841 11:52:18.179275 best dqsien dly found for B0: ( 1, 2, 24)
5842 11:52:18.182525 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 11:52:18.185934 Total UI for P1: 0, mck2ui 16
5844 11:52:18.189097 best dqsien dly found for B1: ( 1, 2, 26)
5845 11:52:18.192116 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5846 11:52:18.195581 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5847 11:52:18.196025
5848 11:52:18.199284 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5849 11:52:18.202538 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5850 11:52:18.205778 [Gating] SW calibration Done
5851 11:52:18.206195 ==
5852 11:52:18.208768 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 11:52:18.215420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 11:52:18.215869 ==
5855 11:52:18.216418 RX Vref Scan: 0
5856 11:52:18.216777
5857 11:52:18.218297 RX Vref 0 -> 0, step: 1
5858 11:52:18.218718
5859 11:52:18.221607 RX Delay -80 -> 252, step: 8
5860 11:52:18.225570 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5861 11:52:18.228541 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5862 11:52:18.231665 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5863 11:52:18.235317 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5864 11:52:18.241620 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5865 11:52:18.245088 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5866 11:52:18.247992 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5867 11:52:18.251497 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5868 11:52:18.254902 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5869 11:52:18.257808 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5870 11:52:18.264504 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5871 11:52:18.268060 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5872 11:52:18.271385 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5873 11:52:18.274728 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5874 11:52:18.277689 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5875 11:52:18.284450 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5876 11:52:18.284869 ==
5877 11:52:18.287623 Dram Type= 6, Freq= 0, CH_1, rank 1
5878 11:52:18.290888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5879 11:52:18.291309 ==
5880 11:52:18.291645 DQS Delay:
5881 11:52:18.294183 DQS0 = 0, DQS1 = 0
5882 11:52:18.294645 DQM Delay:
5883 11:52:18.297556 DQM0 = 97, DQM1 = 94
5884 11:52:18.297978 DQ Delay:
5885 11:52:18.300701 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5886 11:52:18.304300 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5887 11:52:18.307672 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5888 11:52:18.310425 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5889 11:52:18.310850
5890 11:52:18.311188
5891 11:52:18.311505 ==
5892 11:52:18.313978 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 11:52:18.320632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 11:52:18.321190 ==
5895 11:52:18.321545
5896 11:52:18.321861
5897 11:52:18.322163 TX Vref Scan disable
5898 11:52:18.323914 == TX Byte 0 ==
5899 11:52:18.327671 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5900 11:52:18.334221 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5901 11:52:18.334746 == TX Byte 1 ==
5902 11:52:18.337611 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5903 11:52:18.343849 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5904 11:52:18.344274 ==
5905 11:52:18.347128 Dram Type= 6, Freq= 0, CH_1, rank 1
5906 11:52:18.350682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5907 11:52:18.351110 ==
5908 11:52:18.351528
5909 11:52:18.351894
5910 11:52:18.353909 TX Vref Scan disable
5911 11:52:18.354367 == TX Byte 0 ==
5912 11:52:18.361036 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5913 11:52:18.363797 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5914 11:52:18.364232 == TX Byte 1 ==
5915 11:52:18.370651 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5916 11:52:18.373699 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5917 11:52:18.374199
5918 11:52:18.374597 [DATLAT]
5919 11:52:18.377090 Freq=933, CH1 RK1
5920 11:52:18.377603
5921 11:52:18.377955 DATLAT Default: 0xb
5922 11:52:18.380446 0, 0xFFFF, sum = 0
5923 11:52:18.380960 1, 0xFFFF, sum = 0
5924 11:52:18.383996 2, 0xFFFF, sum = 0
5925 11:52:18.387493 3, 0xFFFF, sum = 0
5926 11:52:18.388100 4, 0xFFFF, sum = 0
5927 11:52:18.390415 5, 0xFFFF, sum = 0
5928 11:52:18.391009 6, 0xFFFF, sum = 0
5929 11:52:18.393768 7, 0xFFFF, sum = 0
5930 11:52:18.394321 8, 0xFFFF, sum = 0
5931 11:52:18.397017 9, 0xFFFF, sum = 0
5932 11:52:18.397495 10, 0x0, sum = 1
5933 11:52:18.400020 11, 0x0, sum = 2
5934 11:52:18.400548 12, 0x0, sum = 3
5935 11:52:18.403468 13, 0x0, sum = 4
5936 11:52:18.403896 best_step = 11
5937 11:52:18.404319
5938 11:52:18.404650 ==
5939 11:52:18.406847 Dram Type= 6, Freq= 0, CH_1, rank 1
5940 11:52:18.410154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 11:52:18.410651 ==
5942 11:52:18.413392 RX Vref Scan: 0
5943 11:52:18.413896
5944 11:52:18.416533 RX Vref 0 -> 0, step: 1
5945 11:52:18.417082
5946 11:52:18.417579 RX Delay -53 -> 252, step: 4
5947 11:52:18.424306 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5948 11:52:18.427756 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5949 11:52:18.431095 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5950 11:52:18.434804 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5951 11:52:18.437680 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5952 11:52:18.444651 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5953 11:52:18.447303 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5954 11:52:18.450572 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
5955 11:52:18.453831 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5956 11:52:18.457040 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
5957 11:52:18.463708 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5958 11:52:18.467197 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5959 11:52:18.470230 iDelay=199, Bit 12, Center 100 (11 ~ 190) 180
5960 11:52:18.473610 iDelay=199, Bit 13, Center 102 (11 ~ 194) 184
5961 11:52:18.477512 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5962 11:52:18.484430 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5963 11:52:18.485035 ==
5964 11:52:18.486603 Dram Type= 6, Freq= 0, CH_1, rank 1
5965 11:52:18.490484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5966 11:52:18.491002 ==
5967 11:52:18.491345 DQS Delay:
5968 11:52:18.493779 DQS0 = 0, DQS1 = 0
5969 11:52:18.494200 DQM Delay:
5970 11:52:18.496612 DQM0 = 97, DQM1 = 92
5971 11:52:18.497153 DQ Delay:
5972 11:52:18.500158 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =92
5973 11:52:18.503424 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5974 11:52:18.507005 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5975 11:52:18.509849 DQ12 =100, DQ13 =102, DQ14 =98, DQ15 =102
5976 11:52:18.510298
5977 11:52:18.510646
5978 11:52:18.519482 [DQSOSCAuto] RK1, (LSB)MR18= 0xd24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5979 11:52:18.522811 CH1 RK1: MR19=505, MR18=D24
5980 11:52:18.526427 CH1_RK1: MR19=0x505, MR18=0xD24, DQSOSC=410, MR23=63, INC=64, DEC=42
5981 11:52:18.529467 [RxdqsGatingPostProcess] freq 933
5982 11:52:18.536230 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5983 11:52:18.539557 best DQS0 dly(2T, 0.5T) = (0, 10)
5984 11:52:18.542890 best DQS1 dly(2T, 0.5T) = (0, 10)
5985 11:52:18.546184 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5986 11:52:18.549434 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5987 11:52:18.553451 best DQS0 dly(2T, 0.5T) = (0, 10)
5988 11:52:18.556440 best DQS1 dly(2T, 0.5T) = (0, 10)
5989 11:52:18.558894 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5990 11:52:18.562518 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5991 11:52:18.565793 Pre-setting of DQS Precalculation
5992 11:52:18.568960 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5993 11:52:18.575886 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5994 11:52:18.582956 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5995 11:52:18.583387
5996 11:52:18.585392
5997 11:52:18.585816 [Calibration Summary] 1866 Mbps
5998 11:52:18.588991 CH 0, Rank 0
5999 11:52:18.589523 SW Impedance : PASS
6000 11:52:18.592248 DUTY Scan : NO K
6001 11:52:18.595154 ZQ Calibration : PASS
6002 11:52:18.595580 Jitter Meter : NO K
6003 11:52:18.598617 CBT Training : PASS
6004 11:52:18.601947 Write leveling : PASS
6005 11:52:18.602416 RX DQS gating : PASS
6006 11:52:18.605471 RX DQ/DQS(RDDQC) : PASS
6007 11:52:18.608750 TX DQ/DQS : PASS
6008 11:52:18.609175 RX DATLAT : PASS
6009 11:52:18.611589 RX DQ/DQS(Engine): PASS
6010 11:52:18.615163 TX OE : NO K
6011 11:52:18.615590 All Pass.
6012 11:52:18.615928
6013 11:52:18.616241 CH 0, Rank 1
6014 11:52:18.618647 SW Impedance : PASS
6015 11:52:18.621698 DUTY Scan : NO K
6016 11:52:18.622123 ZQ Calibration : PASS
6017 11:52:18.625107 Jitter Meter : NO K
6018 11:52:18.628068 CBT Training : PASS
6019 11:52:18.628502 Write leveling : PASS
6020 11:52:18.631421 RX DQS gating : PASS
6021 11:52:18.634982 RX DQ/DQS(RDDQC) : PASS
6022 11:52:18.635405 TX DQ/DQS : PASS
6023 11:52:18.638644 RX DATLAT : PASS
6024 11:52:18.641547 RX DQ/DQS(Engine): PASS
6025 11:52:18.641986 TX OE : NO K
6026 11:52:18.642373 All Pass.
6027 11:52:18.644701
6028 11:52:18.645122 CH 1, Rank 0
6029 11:52:18.647713 SW Impedance : PASS
6030 11:52:18.648176 DUTY Scan : NO K
6031 11:52:18.651104 ZQ Calibration : PASS
6032 11:52:18.654370 Jitter Meter : NO K
6033 11:52:18.654795 CBT Training : PASS
6034 11:52:18.657511 Write leveling : PASS
6035 11:52:18.661234 RX DQS gating : PASS
6036 11:52:18.661682 RX DQ/DQS(RDDQC) : PASS
6037 11:52:18.664728 TX DQ/DQS : PASS
6038 11:52:18.665151 RX DATLAT : PASS
6039 11:52:18.667820 RX DQ/DQS(Engine): PASS
6040 11:52:18.671041 TX OE : NO K
6041 11:52:18.671562 All Pass.
6042 11:52:18.671906
6043 11:52:18.672219 CH 1, Rank 1
6044 11:52:18.674519 SW Impedance : PASS
6045 11:52:18.677509 DUTY Scan : NO K
6046 11:52:18.677932 ZQ Calibration : PASS
6047 11:52:18.681073 Jitter Meter : NO K
6048 11:52:18.684488 CBT Training : PASS
6049 11:52:18.684983 Write leveling : PASS
6050 11:52:18.687581 RX DQS gating : PASS
6051 11:52:18.690842 RX DQ/DQS(RDDQC) : PASS
6052 11:52:18.691333 TX DQ/DQS : PASS
6053 11:52:18.694174 RX DATLAT : PASS
6054 11:52:18.697702 RX DQ/DQS(Engine): PASS
6055 11:52:18.698127 TX OE : NO K
6056 11:52:18.700641 All Pass.
6057 11:52:18.701130
6058 11:52:18.701473 DramC Write-DBI off
6059 11:52:18.704112 PER_BANK_REFRESH: Hybrid Mode
6060 11:52:18.704537 TX_TRACKING: ON
6061 11:52:18.713914 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6062 11:52:18.717086 [FAST_K] Save calibration result to emmc
6063 11:52:18.720611 dramc_set_vcore_voltage set vcore to 650000
6064 11:52:18.723698 Read voltage for 400, 6
6065 11:52:18.724119 Vio18 = 0
6066 11:52:18.727142 Vcore = 650000
6067 11:52:18.727584 Vdram = 0
6068 11:52:18.728121 Vddq = 0
6069 11:52:18.730140 Vmddr = 0
6070 11:52:18.733585 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6071 11:52:18.740097 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6072 11:52:18.740603 MEM_TYPE=3, freq_sel=20
6073 11:52:18.743728 sv_algorithm_assistance_LP4_800
6074 11:52:18.749774 ============ PULL DRAM RESETB DOWN ============
6075 11:52:18.753310 ========== PULL DRAM RESETB DOWN end =========
6076 11:52:18.756593 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6077 11:52:18.760076 ===================================
6078 11:52:18.763494 LPDDR4 DRAM CONFIGURATION
6079 11:52:18.766329 ===================================
6080 11:52:18.769881 EX_ROW_EN[0] = 0x0
6081 11:52:18.770391 EX_ROW_EN[1] = 0x0
6082 11:52:18.773419 LP4Y_EN = 0x0
6083 11:52:18.773840 WORK_FSP = 0x0
6084 11:52:18.776568 WL = 0x2
6085 11:52:18.776999 RL = 0x2
6086 11:52:18.779395 BL = 0x2
6087 11:52:18.779837 RPST = 0x0
6088 11:52:18.782786 RD_PRE = 0x0
6089 11:52:18.783216 WR_PRE = 0x1
6090 11:52:18.786153 WR_PST = 0x0
6091 11:52:18.786648 DBI_WR = 0x0
6092 11:52:18.789823 DBI_RD = 0x0
6093 11:52:18.790284 OTF = 0x1
6094 11:52:18.792685 ===================================
6095 11:52:18.796351 ===================================
6096 11:52:18.799325 ANA top config
6097 11:52:18.802535 ===================================
6098 11:52:18.806641 DLL_ASYNC_EN = 0
6099 11:52:18.807078 ALL_SLAVE_EN = 1
6100 11:52:18.809331 NEW_RANK_MODE = 1
6101 11:52:18.812548 DLL_IDLE_MODE = 1
6102 11:52:18.815939 LP45_APHY_COMB_EN = 1
6103 11:52:18.819631 TX_ODT_DIS = 1
6104 11:52:18.820074 NEW_8X_MODE = 1
6105 11:52:18.822712 ===================================
6106 11:52:18.825803 ===================================
6107 11:52:18.829268 data_rate = 800
6108 11:52:18.832640 CKR = 1
6109 11:52:18.835952 DQ_P2S_RATIO = 4
6110 11:52:18.839101 ===================================
6111 11:52:18.842083 CA_P2S_RATIO = 4
6112 11:52:18.845819 DQ_CA_OPEN = 0
6113 11:52:18.846408 DQ_SEMI_OPEN = 1
6114 11:52:18.848807 CA_SEMI_OPEN = 1
6115 11:52:18.852377 CA_FULL_RATE = 0
6116 11:52:18.855241 DQ_CKDIV4_EN = 0
6117 11:52:18.858925 CA_CKDIV4_EN = 1
6118 11:52:18.862391 CA_PREDIV_EN = 0
6119 11:52:18.862850 PH8_DLY = 0
6120 11:52:18.865558 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6121 11:52:18.868503 DQ_AAMCK_DIV = 0
6122 11:52:18.871990 CA_AAMCK_DIV = 0
6123 11:52:18.875239 CA_ADMCK_DIV = 4
6124 11:52:18.878611 DQ_TRACK_CA_EN = 0
6125 11:52:18.882041 CA_PICK = 800
6126 11:52:18.882536 CA_MCKIO = 400
6127 11:52:18.885302 MCKIO_SEMI = 400
6128 11:52:18.888327 PLL_FREQ = 3016
6129 11:52:18.891687 DQ_UI_PI_RATIO = 32
6130 11:52:18.895125 CA_UI_PI_RATIO = 32
6131 11:52:18.898377 ===================================
6132 11:52:18.901729 ===================================
6133 11:52:18.904831 memory_type:LPDDR4
6134 11:52:18.905327 GP_NUM : 10
6135 11:52:18.908442 SRAM_EN : 1
6136 11:52:18.911194 MD32_EN : 0
6137 11:52:18.914371 ===================================
6138 11:52:18.914845 [ANA_INIT] >>>>>>>>>>>>>>
6139 11:52:18.917799 <<<<<< [CONFIGURE PHASE]: ANA_TX
6140 11:52:18.921176 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6141 11:52:18.924381 ===================================
6142 11:52:18.927669 data_rate = 800,PCW = 0X7400
6143 11:52:18.931296 ===================================
6144 11:52:18.934367 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6145 11:52:18.940842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6146 11:52:18.950636 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6147 11:52:18.957475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6148 11:52:18.960551 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6149 11:52:18.963846 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6150 11:52:18.964268 [ANA_INIT] flow start
6151 11:52:18.967256 [ANA_INIT] PLL >>>>>>>>
6152 11:52:18.970612 [ANA_INIT] PLL <<<<<<<<
6153 11:52:18.971029 [ANA_INIT] MIDPI >>>>>>>>
6154 11:52:18.974083 [ANA_INIT] MIDPI <<<<<<<<
6155 11:52:18.977481 [ANA_INIT] DLL >>>>>>>>
6156 11:52:18.977902 [ANA_INIT] flow end
6157 11:52:18.984063 ============ LP4 DIFF to SE enter ============
6158 11:52:18.987700 ============ LP4 DIFF to SE exit ============
6159 11:52:18.990484 [ANA_INIT] <<<<<<<<<<<<<
6160 11:52:18.993535 [Flow] Enable top DCM control >>>>>
6161 11:52:18.997301 [Flow] Enable top DCM control <<<<<
6162 11:52:18.999970 Enable DLL master slave shuffle
6163 11:52:19.003445 ==============================================================
6164 11:52:19.006580 Gating Mode config
6165 11:52:19.010166 ==============================================================
6166 11:52:19.013079 Config description:
6167 11:52:19.023262 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6168 11:52:19.029557 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6169 11:52:19.033165 SELPH_MODE 0: By rank 1: By Phase
6170 11:52:19.039449 ==============================================================
6171 11:52:19.042830 GAT_TRACK_EN = 0
6172 11:52:19.046547 RX_GATING_MODE = 2
6173 11:52:19.049706 RX_GATING_TRACK_MODE = 2
6174 11:52:19.052911 SELPH_MODE = 1
6175 11:52:19.056101 PICG_EARLY_EN = 1
6176 11:52:19.059707 VALID_LAT_VALUE = 1
6177 11:52:19.062583 ==============================================================
6178 11:52:19.066103 Enter into Gating configuration >>>>
6179 11:52:19.069545 Exit from Gating configuration <<<<
6180 11:52:19.072577 Enter into DVFS_PRE_config >>>>>
6181 11:52:19.086012 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6182 11:52:19.089187 Exit from DVFS_PRE_config <<<<<
6183 11:52:19.089613 Enter into PICG configuration >>>>
6184 11:52:19.092379 Exit from PICG configuration <<<<
6185 11:52:19.095787 [RX_INPUT] configuration >>>>>
6186 11:52:19.098787 [RX_INPUT] configuration <<<<<
6187 11:52:19.105297 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6188 11:52:19.108847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6189 11:52:19.115279 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6190 11:52:19.121727 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6191 11:52:19.128208 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6192 11:52:19.134806 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6193 11:52:19.138230 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6194 11:52:19.141274 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6195 11:52:19.148020 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6196 11:52:19.151247 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6197 11:52:19.154747 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6198 11:52:19.158128 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6199 11:52:19.161542 ===================================
6200 11:52:19.164835 LPDDR4 DRAM CONFIGURATION
6201 11:52:19.168081 ===================================
6202 11:52:19.171065 EX_ROW_EN[0] = 0x0
6203 11:52:19.171485 EX_ROW_EN[1] = 0x0
6204 11:52:19.174669 LP4Y_EN = 0x0
6205 11:52:19.175088 WORK_FSP = 0x0
6206 11:52:19.177457 WL = 0x2
6207 11:52:19.180702 RL = 0x2
6208 11:52:19.181121 BL = 0x2
6209 11:52:19.184051 RPST = 0x0
6210 11:52:19.184485 RD_PRE = 0x0
6211 11:52:19.187594 WR_PRE = 0x1
6212 11:52:19.188010 WR_PST = 0x0
6213 11:52:19.190941 DBI_WR = 0x0
6214 11:52:19.191490 DBI_RD = 0x0
6215 11:52:19.194344 OTF = 0x1
6216 11:52:19.197578 ===================================
6217 11:52:19.201090 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6218 11:52:19.204079 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6219 11:52:19.207788 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 11:52:19.210905 ===================================
6221 11:52:19.214323 LPDDR4 DRAM CONFIGURATION
6222 11:52:19.217341 ===================================
6223 11:52:19.220912 EX_ROW_EN[0] = 0x10
6224 11:52:19.221333 EX_ROW_EN[1] = 0x0
6225 11:52:19.223687 LP4Y_EN = 0x0
6226 11:52:19.224110 WORK_FSP = 0x0
6227 11:52:19.227080 WL = 0x2
6228 11:52:19.230679 RL = 0x2
6229 11:52:19.231106 BL = 0x2
6230 11:52:19.233666 RPST = 0x0
6231 11:52:19.234087 RD_PRE = 0x0
6232 11:52:19.237360 WR_PRE = 0x1
6233 11:52:19.237899 WR_PST = 0x0
6234 11:52:19.240461 DBI_WR = 0x0
6235 11:52:19.240885 DBI_RD = 0x0
6236 11:52:19.243872 OTF = 0x1
6237 11:52:19.246991 ===================================
6238 11:52:19.253653 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6239 11:52:19.256869 nWR fixed to 30
6240 11:52:19.257358 [ModeRegInit_LP4] CH0 RK0
6241 11:52:19.259900 [ModeRegInit_LP4] CH0 RK1
6242 11:52:19.263614 [ModeRegInit_LP4] CH1 RK0
6243 11:52:19.266581 [ModeRegInit_LP4] CH1 RK1
6244 11:52:19.266995 match AC timing 19
6245 11:52:19.269876 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6246 11:52:19.276467 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6247 11:52:19.279760 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6248 11:52:19.287058 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6249 11:52:19.289799 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6250 11:52:19.290223 ==
6251 11:52:19.293062 Dram Type= 6, Freq= 0, CH_0, rank 0
6252 11:52:19.295963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6253 11:52:19.296388 ==
6254 11:52:19.302576 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6255 11:52:19.309777 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6256 11:52:19.312859 [CA 0] Center 36 (8~64) winsize 57
6257 11:52:19.316352 [CA 1] Center 36 (8~64) winsize 57
6258 11:52:19.316781 [CA 2] Center 36 (8~64) winsize 57
6259 11:52:19.319177 [CA 3] Center 36 (8~64) winsize 57
6260 11:52:19.322623 [CA 4] Center 36 (8~64) winsize 57
6261 11:52:19.325668 [CA 5] Center 36 (8~64) winsize 57
6262 11:52:19.326088
6263 11:52:19.329169 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6264 11:52:19.332619
6265 11:52:19.335782 [CATrainingPosCal] consider 1 rank data
6266 11:52:19.339273 u2DelayCellTimex100 = 270/100 ps
6267 11:52:19.342213 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6268 11:52:19.345628 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6269 11:52:19.348973 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6270 11:52:19.352414 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 11:52:19.355221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 11:52:19.358794 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 11:52:19.359217
6274 11:52:19.362378 CA PerBit enable=1, Macro0, CA PI delay=36
6275 11:52:19.362808
6276 11:52:19.365275 [CBTSetCACLKResult] CA Dly = 36
6277 11:52:19.368358 CS Dly: 1 (0~32)
6278 11:52:19.368780 ==
6279 11:52:19.371754 Dram Type= 6, Freq= 0, CH_0, rank 1
6280 11:52:19.375230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6281 11:52:19.375653 ==
6282 11:52:19.382042 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6283 11:52:19.388305 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6284 11:52:19.388729 [CA 0] Center 36 (8~64) winsize 57
6285 11:52:19.392160 [CA 1] Center 36 (8~64) winsize 57
6286 11:52:19.395344 [CA 2] Center 36 (8~64) winsize 57
6287 11:52:19.398110 [CA 3] Center 36 (8~64) winsize 57
6288 11:52:19.401429 [CA 4] Center 36 (8~64) winsize 57
6289 11:52:19.404931 [CA 5] Center 36 (8~64) winsize 57
6290 11:52:19.405436
6291 11:52:19.408270 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6292 11:52:19.408694
6293 11:52:19.414829 [CATrainingPosCal] consider 2 rank data
6294 11:52:19.415256 u2DelayCellTimex100 = 270/100 ps
6295 11:52:19.418203 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 11:52:19.424600 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 11:52:19.428244 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 11:52:19.431109 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 11:52:19.434488 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 11:52:19.437745 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 11:52:19.438167
6302 11:52:19.441038 CA PerBit enable=1, Macro0, CA PI delay=36
6303 11:52:19.441461
6304 11:52:19.444665 [CBTSetCACLKResult] CA Dly = 36
6305 11:52:19.447570 CS Dly: 1 (0~32)
6306 11:52:19.447993
6307 11:52:19.450975 ----->DramcWriteLeveling(PI) begin...
6308 11:52:19.451406 ==
6309 11:52:19.454352 Dram Type= 6, Freq= 0, CH_0, rank 0
6310 11:52:19.458014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6311 11:52:19.458503 ==
6312 11:52:19.461191 Write leveling (Byte 0): 40 => 8
6313 11:52:19.464103 Write leveling (Byte 1): 40 => 8
6314 11:52:19.467418 DramcWriteLeveling(PI) end<-----
6315 11:52:19.467843
6316 11:52:19.468179 ==
6317 11:52:19.470759 Dram Type= 6, Freq= 0, CH_0, rank 0
6318 11:52:19.473887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6319 11:52:19.474401 ==
6320 11:52:19.477365 [Gating] SW mode calibration
6321 11:52:19.483865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6322 11:52:19.490523 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6323 11:52:19.493603 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6324 11:52:19.496857 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6325 11:52:19.503421 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6326 11:52:19.507128 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6327 11:52:19.510181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6328 11:52:19.516771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6329 11:52:19.520236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6330 11:52:19.523307 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 11:52:19.530108 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6332 11:52:19.533047 Total UI for P1: 0, mck2ui 16
6333 11:52:19.536527 best dqsien dly found for B0: ( 0, 14, 24)
6334 11:52:19.539760 Total UI for P1: 0, mck2ui 16
6335 11:52:19.543031 best dqsien dly found for B1: ( 0, 14, 24)
6336 11:52:19.546742 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6337 11:52:19.549548 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6338 11:52:19.549972
6339 11:52:19.553235 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6340 11:52:19.556186 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6341 11:52:19.559429 [Gating] SW calibration Done
6342 11:52:19.559850 ==
6343 11:52:19.562968 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 11:52:19.566379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 11:52:19.566863 ==
6346 11:52:19.569377 RX Vref Scan: 0
6347 11:52:19.569797
6348 11:52:19.572764 RX Vref 0 -> 0, step: 1
6349 11:52:19.573187
6350 11:52:19.576153 RX Delay -410 -> 252, step: 16
6351 11:52:19.579672 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6352 11:52:19.582662 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6353 11:52:19.586513 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6354 11:52:19.592444 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6355 11:52:19.595528 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6356 11:52:19.599474 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6357 11:52:19.602599 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6358 11:52:19.608892 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6359 11:52:19.612573 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6360 11:52:19.615321 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6361 11:52:19.618913 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6362 11:52:19.625401 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6363 11:52:19.628542 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6364 11:52:19.632353 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6365 11:52:19.638234 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6366 11:52:19.641588 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6367 11:52:19.641813 ==
6368 11:52:19.644650 Dram Type= 6, Freq= 0, CH_0, rank 0
6369 11:52:19.648336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6370 11:52:19.648563 ==
6371 11:52:19.651458 DQS Delay:
6372 11:52:19.651682 DQS0 = 35, DQS1 = 51
6373 11:52:19.654758 DQM Delay:
6374 11:52:19.654983 DQM0 = 5, DQM1 = 11
6375 11:52:19.655164 DQ Delay:
6376 11:52:19.658295 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6377 11:52:19.662170 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6378 11:52:19.664675 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6379 11:52:19.668121 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6380 11:52:19.668690
6381 11:52:19.669231
6382 11:52:19.669609 ==
6383 11:52:19.671636 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 11:52:19.674924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 11:52:19.678035 ==
6386 11:52:19.678496
6387 11:52:19.678828
6388 11:52:19.679134 TX Vref Scan disable
6389 11:52:19.681480 == TX Byte 0 ==
6390 11:52:19.684941 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6391 11:52:19.688176 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6392 11:52:19.691038 == TX Byte 1 ==
6393 11:52:19.694431 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 11:52:19.698063 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 11:52:19.698533 ==
6396 11:52:19.701426 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 11:52:19.708114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 11:52:19.708535 ==
6399 11:52:19.708870
6400 11:52:19.709177
6401 11:52:19.709475 TX Vref Scan disable
6402 11:52:19.711729 == TX Byte 0 ==
6403 11:52:19.714723 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6404 11:52:19.717941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6405 11:52:19.720798 == TX Byte 1 ==
6406 11:52:19.724089 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 11:52:19.727698 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 11:52:19.728119
6409 11:52:19.730977 [DATLAT]
6410 11:52:19.731393 Freq=400, CH0 RK0
6411 11:52:19.731727
6412 11:52:19.734380 DATLAT Default: 0xf
6413 11:52:19.734799 0, 0xFFFF, sum = 0
6414 11:52:19.737712 1, 0xFFFF, sum = 0
6415 11:52:19.738138 2, 0xFFFF, sum = 0
6416 11:52:19.741064 3, 0xFFFF, sum = 0
6417 11:52:19.741486 4, 0xFFFF, sum = 0
6418 11:52:19.744314 5, 0xFFFF, sum = 0
6419 11:52:19.744742 6, 0xFFFF, sum = 0
6420 11:52:19.747732 7, 0xFFFF, sum = 0
6421 11:52:19.748159 8, 0xFFFF, sum = 0
6422 11:52:19.750719 9, 0xFFFF, sum = 0
6423 11:52:19.754064 10, 0xFFFF, sum = 0
6424 11:52:19.754561 11, 0xFFFF, sum = 0
6425 11:52:19.757620 12, 0xFFFF, sum = 0
6426 11:52:19.758043 13, 0x0, sum = 1
6427 11:52:19.760817 14, 0x0, sum = 2
6428 11:52:19.761239 15, 0x0, sum = 3
6429 11:52:19.763840 16, 0x0, sum = 4
6430 11:52:19.764262 best_step = 14
6431 11:52:19.764595
6432 11:52:19.764905 ==
6433 11:52:19.767154 Dram Type= 6, Freq= 0, CH_0, rank 0
6434 11:52:19.770445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6435 11:52:19.770873 ==
6436 11:52:19.774088 RX Vref Scan: 1
6437 11:52:19.774551
6438 11:52:19.777128 RX Vref 0 -> 0, step: 1
6439 11:52:19.777546
6440 11:52:19.777876 RX Delay -343 -> 252, step: 8
6441 11:52:19.778187
6442 11:52:19.780589 Set Vref, RX VrefLevel [Byte0]: 58
6443 11:52:19.783749 [Byte1]: 49
6444 11:52:19.789453
6445 11:52:19.789868 Final RX Vref Byte 0 = 58 to rank0
6446 11:52:19.792257 Final RX Vref Byte 1 = 49 to rank0
6447 11:52:19.795747 Final RX Vref Byte 0 = 58 to rank1
6448 11:52:19.799031 Final RX Vref Byte 1 = 49 to rank1==
6449 11:52:19.802288 Dram Type= 6, Freq= 0, CH_0, rank 0
6450 11:52:19.808864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6451 11:52:19.809288 ==
6452 11:52:19.809626 DQS Delay:
6453 11:52:19.812125 DQS0 = 44, DQS1 = 60
6454 11:52:19.812656 DQM Delay:
6455 11:52:19.815776 DQM0 = 10, DQM1 = 17
6456 11:52:19.816228 DQ Delay:
6457 11:52:19.818717 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =4
6458 11:52:19.822147 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =20
6459 11:52:19.825589 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6460 11:52:19.829031 DQ12 =24, DQ13 =20, DQ14 =28, DQ15 =28
6461 11:52:19.829542
6462 11:52:19.829916
6463 11:52:19.835523 [DQSOSCAuto] RK0, (LSB)MR18= 0x9589, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6464 11:52:19.838419 CH0 RK0: MR19=C0C, MR18=9589
6465 11:52:19.845477 CH0_RK0: MR19=0xC0C, MR18=0x9589, DQSOSC=391, MR23=63, INC=386, DEC=257
6466 11:52:19.845991 ==
6467 11:52:19.848972 Dram Type= 6, Freq= 0, CH_0, rank 1
6468 11:52:19.851844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6469 11:52:19.852298 ==
6470 11:52:19.855217 [Gating] SW mode calibration
6471 11:52:19.861642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6472 11:52:19.867936 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6473 11:52:19.871575 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6474 11:52:19.874787 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6475 11:52:19.881246 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6476 11:52:19.884843 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6477 11:52:19.887728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6478 11:52:19.894298 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6479 11:52:19.897759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6480 11:52:19.904594 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 11:52:19.907942 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6482 11:52:19.910823 Total UI for P1: 0, mck2ui 16
6483 11:52:19.914194 best dqsien dly found for B0: ( 0, 14, 24)
6484 11:52:19.917513 Total UI for P1: 0, mck2ui 16
6485 11:52:19.920605 best dqsien dly found for B1: ( 0, 14, 24)
6486 11:52:19.924393 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6487 11:52:19.927675 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6488 11:52:19.928108
6489 11:52:19.930534 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6490 11:52:19.934299 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6491 11:52:19.937376 [Gating] SW calibration Done
6492 11:52:19.937968 ==
6493 11:52:19.940305 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 11:52:19.944153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 11:52:19.947169 ==
6496 11:52:19.947582 RX Vref Scan: 0
6497 11:52:19.948052
6498 11:52:19.950192 RX Vref 0 -> 0, step: 1
6499 11:52:19.950663
6500 11:52:19.953622 RX Delay -410 -> 252, step: 16
6501 11:52:19.957158 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6502 11:52:19.960480 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6503 11:52:19.963529 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6504 11:52:19.970195 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6505 11:52:19.973721 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6506 11:52:19.976553 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6507 11:52:19.979871 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6508 11:52:19.986700 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6509 11:52:19.989813 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6510 11:52:19.993243 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6511 11:52:19.996569 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6512 11:52:20.002873 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6513 11:52:20.006185 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6514 11:52:20.009777 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6515 11:52:20.015885 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6516 11:52:20.019342 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6517 11:52:20.019543 ==
6518 11:52:20.022576 Dram Type= 6, Freq= 0, CH_0, rank 1
6519 11:52:20.025921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6520 11:52:20.026110 ==
6521 11:52:20.029298 DQS Delay:
6522 11:52:20.029459 DQS0 = 35, DQS1 = 51
6523 11:52:20.032802 DQM Delay:
6524 11:52:20.032962 DQM0 = 7, DQM1 = 10
6525 11:52:20.033107 DQ Delay:
6526 11:52:20.035911 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6527 11:52:20.039239 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6528 11:52:20.042667 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6529 11:52:20.046180 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6530 11:52:20.046384
6531 11:52:20.046530
6532 11:52:20.046670 ==
6533 11:52:20.048749 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 11:52:20.052242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 11:52:20.055546 ==
6536 11:52:20.055646
6537 11:52:20.055734
6538 11:52:20.055808 TX Vref Scan disable
6539 11:52:20.058977 == TX Byte 0 ==
6540 11:52:20.062055 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6541 11:52:20.065642 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6542 11:52:20.068775 == TX Byte 1 ==
6543 11:52:20.071820 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6544 11:52:20.075330 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6545 11:52:20.075412 ==
6546 11:52:20.078810 Dram Type= 6, Freq= 0, CH_0, rank 1
6547 11:52:20.085093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6548 11:52:20.085176 ==
6549 11:52:20.085242
6550 11:52:20.085302
6551 11:52:20.085360 TX Vref Scan disable
6552 11:52:20.088370 == TX Byte 0 ==
6553 11:52:20.091776 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6554 11:52:20.095355 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6555 11:52:20.098317 == TX Byte 1 ==
6556 11:52:20.101560 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6557 11:52:20.105114 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6558 11:52:20.105197
6559 11:52:20.108344 [DATLAT]
6560 11:52:20.108444 Freq=400, CH0 RK1
6561 11:52:20.108536
6562 11:52:20.111865 DATLAT Default: 0xe
6563 11:52:20.111950 0, 0xFFFF, sum = 0
6564 11:52:20.114830 1, 0xFFFF, sum = 0
6565 11:52:20.114932 2, 0xFFFF, sum = 0
6566 11:52:20.118095 3, 0xFFFF, sum = 0
6567 11:52:20.118178 4, 0xFFFF, sum = 0
6568 11:52:20.121612 5, 0xFFFF, sum = 0
6569 11:52:20.121696 6, 0xFFFF, sum = 0
6570 11:52:20.124577 7, 0xFFFF, sum = 0
6571 11:52:20.124660 8, 0xFFFF, sum = 0
6572 11:52:20.128113 9, 0xFFFF, sum = 0
6573 11:52:20.131790 10, 0xFFFF, sum = 0
6574 11:52:20.131879 11, 0xFFFF, sum = 0
6575 11:52:20.134584 12, 0xFFFF, sum = 0
6576 11:52:20.134681 13, 0x0, sum = 1
6577 11:52:20.137915 14, 0x0, sum = 2
6578 11:52:20.138011 15, 0x0, sum = 3
6579 11:52:20.141452 16, 0x0, sum = 4
6580 11:52:20.141554 best_step = 14
6581 11:52:20.141636
6582 11:52:20.141712 ==
6583 11:52:20.144776 Dram Type= 6, Freq= 0, CH_0, rank 1
6584 11:52:20.148004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:52:20.148116 ==
6586 11:52:20.151274 RX Vref Scan: 0
6587 11:52:20.151394
6588 11:52:20.154474 RX Vref 0 -> 0, step: 1
6589 11:52:20.154608
6590 11:52:20.154716 RX Delay -343 -> 252, step: 8
6591 11:52:20.163245 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6592 11:52:20.166319 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6593 11:52:20.170270 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6594 11:52:20.176417 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6595 11:52:20.179784 iDelay=217, Bit 4, Center -28 (-263 ~ 208) 472
6596 11:52:20.183029 iDelay=217, Bit 5, Center -40 (-279 ~ 200) 480
6597 11:52:20.186584 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6598 11:52:20.192765 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6599 11:52:20.196312 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6600 11:52:20.199688 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6601 11:52:20.203061 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6602 11:52:20.209313 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6603 11:52:20.212894 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6604 11:52:20.215763 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6605 11:52:20.222739 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6606 11:52:20.225747 iDelay=217, Bit 15, Center -40 (-279 ~ 200) 480
6607 11:52:20.226219 ==
6608 11:52:20.229290 Dram Type= 6, Freq= 0, CH_0, rank 1
6609 11:52:20.232222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6610 11:52:20.232677 ==
6611 11:52:20.235478 DQS Delay:
6612 11:52:20.235898 DQS0 = 40, DQS1 = 60
6613 11:52:20.236235 DQM Delay:
6614 11:52:20.238900 DQM0 = 6, DQM1 = 14
6615 11:52:20.239327 DQ Delay:
6616 11:52:20.242487 DQ0 =4, DQ1 =8, DQ2 =0, DQ3 =0
6617 11:52:20.245420 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =12
6618 11:52:20.248399 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6619 11:52:20.252288 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6620 11:52:20.252741
6621 11:52:20.253125
6622 11:52:20.262018 [DQSOSCAuto] RK1, (LSB)MR18= 0x847c, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6623 11:52:20.262519 CH0 RK1: MR19=C0C, MR18=847C
6624 11:52:20.268619 CH0_RK1: MR19=0xC0C, MR18=0x847C, DQSOSC=393, MR23=63, INC=382, DEC=254
6625 11:52:20.272327 [RxdqsGatingPostProcess] freq 400
6626 11:52:20.278027 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6627 11:52:20.281632 best DQS0 dly(2T, 0.5T) = (0, 10)
6628 11:52:20.284758 best DQS1 dly(2T, 0.5T) = (0, 10)
6629 11:52:20.288099 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6630 11:52:20.291792 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6631 11:52:20.294761 best DQS0 dly(2T, 0.5T) = (0, 10)
6632 11:52:20.297831 best DQS1 dly(2T, 0.5T) = (0, 10)
6633 11:52:20.301179 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6634 11:52:20.304765 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6635 11:52:20.305336 Pre-setting of DQS Precalculation
6636 11:52:20.311360 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6637 11:52:20.311959 ==
6638 11:52:20.314495 Dram Type= 6, Freq= 0, CH_1, rank 0
6639 11:52:20.317911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6640 11:52:20.318515 ==
6641 11:52:20.324737 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6642 11:52:20.331176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6643 11:52:20.334140 [CA 0] Center 36 (8~64) winsize 57
6644 11:52:20.337339 [CA 1] Center 36 (8~64) winsize 57
6645 11:52:20.340837 [CA 2] Center 36 (8~64) winsize 57
6646 11:52:20.344184 [CA 3] Center 36 (8~64) winsize 57
6647 11:52:20.347257 [CA 4] Center 36 (8~64) winsize 57
6648 11:52:20.350806 [CA 5] Center 36 (8~64) winsize 57
6649 11:52:20.351244
6650 11:52:20.354295 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6651 11:52:20.354732
6652 11:52:20.357178 [CATrainingPosCal] consider 1 rank data
6653 11:52:20.360312 u2DelayCellTimex100 = 270/100 ps
6654 11:52:20.364090 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6655 11:52:20.367011 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6656 11:52:20.370439 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6657 11:52:20.373662 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 11:52:20.377335 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 11:52:20.380402 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 11:52:20.380826
6661 11:52:20.386990 CA PerBit enable=1, Macro0, CA PI delay=36
6662 11:52:20.387429
6663 11:52:20.387762 [CBTSetCACLKResult] CA Dly = 36
6664 11:52:20.390623 CS Dly: 1 (0~32)
6665 11:52:20.391067 ==
6666 11:52:20.393610 Dram Type= 6, Freq= 0, CH_1, rank 1
6667 11:52:20.396935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6668 11:52:20.397367 ==
6669 11:52:20.403126 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6670 11:52:20.410130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6671 11:52:20.413396 [CA 0] Center 36 (8~64) winsize 57
6672 11:52:20.416745 [CA 1] Center 36 (8~64) winsize 57
6673 11:52:20.419780 [CA 2] Center 36 (8~64) winsize 57
6674 11:52:20.422947 [CA 3] Center 36 (8~64) winsize 57
6675 11:52:20.423363 [CA 4] Center 36 (8~64) winsize 57
6676 11:52:20.426978 [CA 5] Center 36 (8~64) winsize 57
6677 11:52:20.427458
6678 11:52:20.433091 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6679 11:52:20.433660
6680 11:52:20.435938 [CATrainingPosCal] consider 2 rank data
6681 11:52:20.439500 u2DelayCellTimex100 = 270/100 ps
6682 11:52:20.442894 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 11:52:20.446342 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 11:52:20.449512 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 11:52:20.452972 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 11:52:20.455946 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 11:52:20.459763 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 11:52:20.460189
6689 11:52:20.462554 CA PerBit enable=1, Macro0, CA PI delay=36
6690 11:52:20.462992
6691 11:52:20.465952 [CBTSetCACLKResult] CA Dly = 36
6692 11:52:20.469481 CS Dly: 1 (0~32)
6693 11:52:20.469909
6694 11:52:20.472916 ----->DramcWriteLeveling(PI) begin...
6695 11:52:20.473340 ==
6696 11:52:20.475953 Dram Type= 6, Freq= 0, CH_1, rank 0
6697 11:52:20.479179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6698 11:52:20.479617 ==
6699 11:52:20.482510 Write leveling (Byte 0): 40 => 8
6700 11:52:20.485970 Write leveling (Byte 1): 40 => 8
6701 11:52:20.489139 DramcWriteLeveling(PI) end<-----
6702 11:52:20.489559
6703 11:52:20.489891 ==
6704 11:52:20.492654 Dram Type= 6, Freq= 0, CH_1, rank 0
6705 11:52:20.495830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6706 11:52:20.496384 ==
6707 11:52:20.499181 [Gating] SW mode calibration
6708 11:52:20.505438 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6709 11:52:20.511793 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6710 11:52:20.515211 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6711 11:52:20.521857 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6712 11:52:20.525031 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6713 11:52:20.528328 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6714 11:52:20.535080 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6715 11:52:20.538537 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6716 11:52:20.542012 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6717 11:52:20.548601 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 11:52:20.551515 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6719 11:52:20.554863 Total UI for P1: 0, mck2ui 16
6720 11:52:20.558354 best dqsien dly found for B0: ( 0, 14, 24)
6721 11:52:20.561256 Total UI for P1: 0, mck2ui 16
6722 11:52:20.564729 best dqsien dly found for B1: ( 0, 14, 24)
6723 11:52:20.568423 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6724 11:52:20.571324 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6725 11:52:20.571758
6726 11:52:20.574725 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6727 11:52:20.578222 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6728 11:52:20.581119 [Gating] SW calibration Done
6729 11:52:20.581556 ==
6730 11:52:20.584575 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 11:52:20.591113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 11:52:20.591543 ==
6733 11:52:20.591880 RX Vref Scan: 0
6734 11:52:20.592210
6735 11:52:20.594543 RX Vref 0 -> 0, step: 1
6736 11:52:20.594993
6737 11:52:20.597828 RX Delay -410 -> 252, step: 16
6738 11:52:20.601006 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6739 11:52:20.604153 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6740 11:52:20.610959 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6741 11:52:20.614319 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6742 11:52:20.617374 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6743 11:52:20.620594 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6744 11:52:20.627122 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6745 11:52:20.630556 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6746 11:52:20.633905 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6747 11:52:20.637232 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6748 11:52:20.643664 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6749 11:52:20.647159 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6750 11:52:20.650622 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6751 11:52:20.656770 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6752 11:52:20.660084 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6753 11:52:20.663637 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6754 11:52:20.664061 ==
6755 11:52:20.666610 Dram Type= 6, Freq= 0, CH_1, rank 0
6756 11:52:20.670089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6757 11:52:20.673539 ==
6758 11:52:20.673951 DQS Delay:
6759 11:52:20.674352 DQS0 = 35, DQS1 = 51
6760 11:52:20.676417 DQM Delay:
6761 11:52:20.676828 DQM0 = 6, DQM1 = 13
6762 11:52:20.680056 DQ Delay:
6763 11:52:20.680470 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6764 11:52:20.682965 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6765 11:52:20.686466 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6766 11:52:20.689886 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6767 11:52:20.690385
6768 11:52:20.690726
6769 11:52:20.692773 ==
6770 11:52:20.693202 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 11:52:20.699584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 11:52:20.700003 ==
6773 11:52:20.700370
6774 11:52:20.700678
6775 11:52:20.703029 TX Vref Scan disable
6776 11:52:20.703446 == TX Byte 0 ==
6777 11:52:20.706511 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6778 11:52:20.713079 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6779 11:52:20.713522 == TX Byte 1 ==
6780 11:52:20.716000 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 11:52:20.722752 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 11:52:20.723301 ==
6783 11:52:20.725771 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 11:52:20.729105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 11:52:20.729625 ==
6786 11:52:20.730179
6787 11:52:20.730677
6788 11:52:20.732473 TX Vref Scan disable
6789 11:52:20.733017 == TX Byte 0 ==
6790 11:52:20.735649 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6791 11:52:20.742979 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6792 11:52:20.743574 == TX Byte 1 ==
6793 11:52:20.745929 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 11:52:20.752302 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 11:52:20.752897
6796 11:52:20.753438 [DATLAT]
6797 11:52:20.753901 Freq=400, CH1 RK0
6798 11:52:20.755519
6799 11:52:20.756156 DATLAT Default: 0xf
6800 11:52:20.758889 0, 0xFFFF, sum = 0
6801 11:52:20.759489 1, 0xFFFF, sum = 0
6802 11:52:20.762315 2, 0xFFFF, sum = 0
6803 11:52:20.762793 3, 0xFFFF, sum = 0
6804 11:52:20.765203 4, 0xFFFF, sum = 0
6805 11:52:20.765746 5, 0xFFFF, sum = 0
6806 11:52:20.768815 6, 0xFFFF, sum = 0
6807 11:52:20.769406 7, 0xFFFF, sum = 0
6808 11:52:20.771780 8, 0xFFFF, sum = 0
6809 11:52:20.772328 9, 0xFFFF, sum = 0
6810 11:52:20.775204 10, 0xFFFF, sum = 0
6811 11:52:20.775717 11, 0xFFFF, sum = 0
6812 11:52:20.778579 12, 0xFFFF, sum = 0
6813 11:52:20.779055 13, 0x0, sum = 1
6814 11:52:20.781648 14, 0x0, sum = 2
6815 11:52:20.782204 15, 0x0, sum = 3
6816 11:52:20.785073 16, 0x0, sum = 4
6817 11:52:20.785671 best_step = 14
6818 11:52:20.786178
6819 11:52:20.786621 ==
6820 11:52:20.788339 Dram Type= 6, Freq= 0, CH_1, rank 0
6821 11:52:20.795259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6822 11:52:20.795842 ==
6823 11:52:20.796379 RX Vref Scan: 1
6824 11:52:20.796874
6825 11:52:20.798356 RX Vref 0 -> 0, step: 1
6826 11:52:20.798845
6827 11:52:20.801391 RX Delay -343 -> 252, step: 8
6828 11:52:20.801872
6829 11:52:20.804886 Set Vref, RX VrefLevel [Byte0]: 53
6830 11:52:20.807921 [Byte1]: 52
6831 11:52:20.811767
6832 11:52:20.812345 Final RX Vref Byte 0 = 53 to rank0
6833 11:52:20.814802 Final RX Vref Byte 1 = 52 to rank0
6834 11:52:20.817876 Final RX Vref Byte 0 = 53 to rank1
6835 11:52:20.821362 Final RX Vref Byte 1 = 52 to rank1==
6836 11:52:20.824687 Dram Type= 6, Freq= 0, CH_1, rank 0
6837 11:52:20.831242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6838 11:52:20.831843 ==
6839 11:52:20.832383 DQS Delay:
6840 11:52:20.834483 DQS0 = 44, DQS1 = 52
6841 11:52:20.835067 DQM Delay:
6842 11:52:20.837372 DQM0 = 10, DQM1 = 10
6843 11:52:20.837888 DQ Delay:
6844 11:52:20.840797 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6845 11:52:20.844112 DQ4 =4, DQ5 =20, DQ6 =20, DQ7 =4
6846 11:52:20.844658 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6847 11:52:20.850378 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6848 11:52:20.850918
6849 11:52:20.851260
6850 11:52:20.857260 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f96, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 395 ps
6851 11:52:20.861254 CH1 RK0: MR19=C0C, MR18=6F96
6852 11:52:20.867217 CH1_RK0: MR19=0xC0C, MR18=0x6F96, DQSOSC=391, MR23=63, INC=386, DEC=257
6853 11:52:20.867645 ==
6854 11:52:20.870545 Dram Type= 6, Freq= 0, CH_1, rank 1
6855 11:52:20.874103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6856 11:52:20.874746 ==
6857 11:52:20.877335 [Gating] SW mode calibration
6858 11:52:20.883882 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6859 11:52:20.890194 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6860 11:52:20.893685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6861 11:52:20.896739 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6862 11:52:20.903684 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6863 11:52:20.906709 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6864 11:52:20.910162 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6865 11:52:20.916611 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6866 11:52:20.919707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6867 11:52:20.923660 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 11:52:20.930094 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6869 11:52:20.932931 Total UI for P1: 0, mck2ui 16
6870 11:52:20.936630 best dqsien dly found for B0: ( 0, 14, 24)
6871 11:52:20.939461 Total UI for P1: 0, mck2ui 16
6872 11:52:20.943258 best dqsien dly found for B1: ( 0, 14, 24)
6873 11:52:20.946358 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6874 11:52:20.949611 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6875 11:52:20.950307
6876 11:52:20.952837 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6877 11:52:20.956077 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6878 11:52:20.959663 [Gating] SW calibration Done
6879 11:52:20.960261 ==
6880 11:52:20.962800 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 11:52:20.966139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 11:52:20.966704 ==
6883 11:52:20.969282 RX Vref Scan: 0
6884 11:52:20.969761
6885 11:52:20.972587 RX Vref 0 -> 0, step: 1
6886 11:52:20.973187
6887 11:52:20.975558 RX Delay -410 -> 252, step: 16
6888 11:52:20.979367 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6889 11:52:20.982406 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6890 11:52:20.985266 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6891 11:52:20.992477 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6892 11:52:20.995227 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6893 11:52:20.999006 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6894 11:52:21.002566 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6895 11:52:21.008755 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6896 11:52:21.011930 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6897 11:52:21.015264 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6898 11:52:21.018501 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6899 11:52:21.025258 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6900 11:52:21.028520 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6901 11:52:21.031674 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6902 11:52:21.038537 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6903 11:52:21.041295 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6904 11:52:21.042015 ==
6905 11:52:21.044905 Dram Type= 6, Freq= 0, CH_1, rank 1
6906 11:52:21.048237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6907 11:52:21.048806 ==
6908 11:52:21.051849 DQS Delay:
6909 11:52:21.052279 DQS0 = 43, DQS1 = 51
6910 11:52:21.054624 DQM Delay:
6911 11:52:21.055182 DQM0 = 10, DQM1 = 15
6912 11:52:21.055605 DQ Delay:
6913 11:52:21.058028 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6914 11:52:21.061385 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6915 11:52:21.064728 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6916 11:52:21.067931 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6917 11:52:21.068476
6918 11:52:21.068975
6919 11:52:21.069419 ==
6920 11:52:21.071110 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 11:52:21.077843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 11:52:21.078712 ==
6923 11:52:21.079245
6924 11:52:21.079602
6925 11:52:21.079917 TX Vref Scan disable
6926 11:52:21.081316 == TX Byte 0 ==
6927 11:52:21.084146 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6928 11:52:21.087515 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6929 11:52:21.091023 == TX Byte 1 ==
6930 11:52:21.094156 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6931 11:52:21.098152 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6932 11:52:21.098795 ==
6933 11:52:21.101073 Dram Type= 6, Freq= 0, CH_1, rank 1
6934 11:52:21.107408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6935 11:52:21.108005 ==
6936 11:52:21.108539
6937 11:52:21.109028
6938 11:52:21.110374 TX Vref Scan disable
6939 11:52:21.110781 == TX Byte 0 ==
6940 11:52:21.114577 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6941 11:52:21.120788 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6942 11:52:21.121376 == TX Byte 1 ==
6943 11:52:21.123781 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6944 11:52:21.130409 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6945 11:52:21.130964
6946 11:52:21.131346 [DATLAT]
6947 11:52:21.131721 Freq=400, CH1 RK1
6948 11:52:21.132217
6949 11:52:21.133865 DATLAT Default: 0xe
6950 11:52:21.134504 0, 0xFFFF, sum = 0
6951 11:52:21.137257 1, 0xFFFF, sum = 0
6952 11:52:21.137879 2, 0xFFFF, sum = 0
6953 11:52:21.140232 3, 0xFFFF, sum = 0
6954 11:52:21.143598 4, 0xFFFF, sum = 0
6955 11:52:21.144069 5, 0xFFFF, sum = 0
6956 11:52:21.147113 6, 0xFFFF, sum = 0
6957 11:52:21.147653 7, 0xFFFF, sum = 0
6958 11:52:21.150068 8, 0xFFFF, sum = 0
6959 11:52:21.150659 9, 0xFFFF, sum = 0
6960 11:52:21.153571 10, 0xFFFF, sum = 0
6961 11:52:21.154122 11, 0xFFFF, sum = 0
6962 11:52:21.156807 12, 0xFFFF, sum = 0
6963 11:52:21.157400 13, 0x0, sum = 1
6964 11:52:21.160246 14, 0x0, sum = 2
6965 11:52:21.160835 15, 0x0, sum = 3
6966 11:52:21.163234 16, 0x0, sum = 4
6967 11:52:21.163772 best_step = 14
6968 11:52:21.164118
6969 11:52:21.164475 ==
6970 11:52:21.166746 Dram Type= 6, Freq= 0, CH_1, rank 1
6971 11:52:21.173038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6972 11:52:21.173633 ==
6973 11:52:21.174176 RX Vref Scan: 0
6974 11:52:21.174684
6975 11:52:21.176445 RX Vref 0 -> 0, step: 1
6976 11:52:21.176970
6977 11:52:21.179686 RX Delay -343 -> 252, step: 8
6978 11:52:21.186131 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6979 11:52:21.189607 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6980 11:52:21.192867 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6981 11:52:21.196116 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6982 11:52:21.202743 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6983 11:52:21.206010 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6984 11:52:21.209217 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6985 11:52:21.212687 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6986 11:52:21.219061 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6987 11:52:21.222746 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6988 11:52:21.225739 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6989 11:52:21.228947 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6990 11:52:21.236017 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6991 11:52:21.238994 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6992 11:52:21.242435 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6993 11:52:21.248888 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6994 11:52:21.249444 ==
6995 11:52:21.252327 Dram Type= 6, Freq= 0, CH_1, rank 1
6996 11:52:21.255782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6997 11:52:21.256275 ==
6998 11:52:21.256700 DQS Delay:
6999 11:52:21.258675 DQS0 = 48, DQS1 = 52
7000 11:52:21.259286 DQM Delay:
7001 11:52:21.262032 DQM0 = 11, DQM1 = 10
7002 11:52:21.262595 DQ Delay:
7003 11:52:21.265499 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =12
7004 11:52:21.268953 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
7005 11:52:21.272008 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7006 11:52:21.275670 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =20
7007 11:52:21.276246
7008 11:52:21.276743
7009 11:52:21.282542 [DQSOSCAuto] RK1, (LSB)MR18= 0x70a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
7010 11:52:21.285029 CH1 RK1: MR19=C0C, MR18=70A8
7011 11:52:21.291528 CH1_RK1: MR19=0xC0C, MR18=0x70A8, DQSOSC=388, MR23=63, INC=392, DEC=261
7012 11:52:21.294881 [RxdqsGatingPostProcess] freq 400
7013 11:52:21.301655 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7014 11:52:21.304610 best DQS0 dly(2T, 0.5T) = (0, 10)
7015 11:52:21.308299 best DQS1 dly(2T, 0.5T) = (0, 10)
7016 11:52:21.311775 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7017 11:52:21.314924 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7018 11:52:21.315348 best DQS0 dly(2T, 0.5T) = (0, 10)
7019 11:52:21.318321 best DQS1 dly(2T, 0.5T) = (0, 10)
7020 11:52:21.321277 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7021 11:52:21.324672 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7022 11:52:21.328310 Pre-setting of DQS Precalculation
7023 11:52:21.334527 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7024 11:52:21.341302 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7025 11:52:21.347780 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7026 11:52:21.348212
7027 11:52:21.348550
7028 11:52:21.350806 [Calibration Summary] 800 Mbps
7029 11:52:21.351371 CH 0, Rank 0
7030 11:52:21.354197 SW Impedance : PASS
7031 11:52:21.357544 DUTY Scan : NO K
7032 11:52:21.358073 ZQ Calibration : PASS
7033 11:52:21.360834 Jitter Meter : NO K
7034 11:52:21.364209 CBT Training : PASS
7035 11:52:21.364627 Write leveling : PASS
7036 11:52:21.367492 RX DQS gating : PASS
7037 11:52:21.370879 RX DQ/DQS(RDDQC) : PASS
7038 11:52:21.371314 TX DQ/DQS : PASS
7039 11:52:21.374214 RX DATLAT : PASS
7040 11:52:21.377834 RX DQ/DQS(Engine): PASS
7041 11:52:21.378359 TX OE : NO K
7042 11:52:21.380627 All Pass.
7043 11:52:21.381202
7044 11:52:21.381747 CH 0, Rank 1
7045 11:52:21.383925 SW Impedance : PASS
7046 11:52:21.384590 DUTY Scan : NO K
7047 11:52:21.387034 ZQ Calibration : PASS
7048 11:52:21.390422 Jitter Meter : NO K
7049 11:52:21.391074 CBT Training : PASS
7050 11:52:21.393598 Write leveling : NO K
7051 11:52:21.396635 RX DQS gating : PASS
7052 11:52:21.397285 RX DQ/DQS(RDDQC) : PASS
7053 11:52:21.400502 TX DQ/DQS : PASS
7054 11:52:21.403794 RX DATLAT : PASS
7055 11:52:21.404264 RX DQ/DQS(Engine): PASS
7056 11:52:21.406367 TX OE : NO K
7057 11:52:21.406716 All Pass.
7058 11:52:21.407035
7059 11:52:21.409865 CH 1, Rank 0
7060 11:52:21.410142 SW Impedance : PASS
7061 11:52:21.413036 DUTY Scan : NO K
7062 11:52:21.416123 ZQ Calibration : PASS
7063 11:52:21.416355 Jitter Meter : NO K
7064 11:52:21.419698 CBT Training : PASS
7065 11:52:21.422935 Write leveling : PASS
7066 11:52:21.423139 RX DQS gating : PASS
7067 11:52:21.425937 RX DQ/DQS(RDDQC) : PASS
7068 11:52:21.426116 TX DQ/DQS : PASS
7069 11:52:21.429456 RX DATLAT : PASS
7070 11:52:21.433087 RX DQ/DQS(Engine): PASS
7071 11:52:21.433249 TX OE : NO K
7072 11:52:21.436017 All Pass.
7073 11:52:21.436163
7074 11:52:21.436299 CH 1, Rank 1
7075 11:52:21.439413 SW Impedance : PASS
7076 11:52:21.439550 DUTY Scan : NO K
7077 11:52:21.442662 ZQ Calibration : PASS
7078 11:52:21.446240 Jitter Meter : NO K
7079 11:52:21.446409 CBT Training : PASS
7080 11:52:21.448885 Write leveling : NO K
7081 11:52:21.452737 RX DQS gating : PASS
7082 11:52:21.452870 RX DQ/DQS(RDDQC) : PASS
7083 11:52:21.455692 TX DQ/DQS : PASS
7084 11:52:21.458923 RX DATLAT : PASS
7085 11:52:21.459053 RX DQ/DQS(Engine): PASS
7086 11:52:21.462382 TX OE : NO K
7087 11:52:21.462514 All Pass.
7088 11:52:21.462637
7089 11:52:21.465461 DramC Write-DBI off
7090 11:52:21.469272 PER_BANK_REFRESH: Hybrid Mode
7091 11:52:21.469407 TX_TRACKING: ON
7092 11:52:21.479379 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7093 11:52:21.482168 [FAST_K] Save calibration result to emmc
7094 11:52:21.485435 dramc_set_vcore_voltage set vcore to 725000
7095 11:52:21.489119 Read voltage for 1600, 0
7096 11:52:21.489225 Vio18 = 0
7097 11:52:21.492399 Vcore = 725000
7098 11:52:21.492480 Vdram = 0
7099 11:52:21.492545 Vddq = 0
7100 11:52:21.492605 Vmddr = 0
7101 11:52:21.498383 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7102 11:52:21.505837 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7103 11:52:21.505942 MEM_TYPE=3, freq_sel=13
7104 11:52:21.508357 sv_algorithm_assistance_LP4_3733
7105 11:52:21.511566 ============ PULL DRAM RESETB DOWN ============
7106 11:52:21.518507 ========== PULL DRAM RESETB DOWN end =========
7107 11:52:21.521983 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7108 11:52:21.525326 ===================================
7109 11:52:21.528378 LPDDR4 DRAM CONFIGURATION
7110 11:52:21.531569 ===================================
7111 11:52:21.531654 EX_ROW_EN[0] = 0x0
7112 11:52:21.534677 EX_ROW_EN[1] = 0x0
7113 11:52:21.537960 LP4Y_EN = 0x0
7114 11:52:21.538060 WORK_FSP = 0x1
7115 11:52:21.541071 WL = 0x5
7116 11:52:21.541168 RL = 0x5
7117 11:52:21.544488 BL = 0x2
7118 11:52:21.544590 RPST = 0x0
7119 11:52:21.547974 RD_PRE = 0x0
7120 11:52:21.548074 WR_PRE = 0x1
7121 11:52:21.551281 WR_PST = 0x1
7122 11:52:21.551414 DBI_WR = 0x0
7123 11:52:21.554691 DBI_RD = 0x0
7124 11:52:21.554828 OTF = 0x1
7125 11:52:21.557867 ===================================
7126 11:52:21.561115 ===================================
7127 11:52:21.564068 ANA top config
7128 11:52:21.567841 ===================================
7129 11:52:21.568019 DLL_ASYNC_EN = 0
7130 11:52:21.570640 ALL_SLAVE_EN = 0
7131 11:52:21.574441 NEW_RANK_MODE = 1
7132 11:52:21.577555 DLL_IDLE_MODE = 1
7133 11:52:21.581063 LP45_APHY_COMB_EN = 1
7134 11:52:21.581406 TX_ODT_DIS = 0
7135 11:52:21.584098 NEW_8X_MODE = 1
7136 11:52:21.587482 ===================================
7137 11:52:21.590881 ===================================
7138 11:52:21.593975 data_rate = 3200
7139 11:52:21.597500 CKR = 1
7140 11:52:21.600924 DQ_P2S_RATIO = 8
7141 11:52:21.603974 ===================================
7142 11:52:21.607991 CA_P2S_RATIO = 8
7143 11:52:21.608417 DQ_CA_OPEN = 0
7144 11:52:21.610726 DQ_SEMI_OPEN = 0
7145 11:52:21.613911 CA_SEMI_OPEN = 0
7146 11:52:21.617387 CA_FULL_RATE = 0
7147 11:52:21.620475 DQ_CKDIV4_EN = 0
7148 11:52:21.623685 CA_CKDIV4_EN = 0
7149 11:52:21.624154 CA_PREDIV_EN = 0
7150 11:52:21.626721 PH8_DLY = 12
7151 11:52:21.630363 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7152 11:52:21.633297 DQ_AAMCK_DIV = 4
7153 11:52:21.637020 CA_AAMCK_DIV = 4
7154 11:52:21.640277 CA_ADMCK_DIV = 4
7155 11:52:21.643443 DQ_TRACK_CA_EN = 0
7156 11:52:21.644026 CA_PICK = 1600
7157 11:52:21.646984 CA_MCKIO = 1600
7158 11:52:21.650245 MCKIO_SEMI = 0
7159 11:52:21.653373 PLL_FREQ = 3068
7160 11:52:21.656655 DQ_UI_PI_RATIO = 32
7161 11:52:21.659899 CA_UI_PI_RATIO = 0
7162 11:52:21.662997 ===================================
7163 11:52:21.666676 ===================================
7164 11:52:21.669686 memory_type:LPDDR4
7165 11:52:21.670054 GP_NUM : 10
7166 11:52:21.673349 SRAM_EN : 1
7167 11:52:21.673803 MD32_EN : 0
7168 11:52:21.676311 ===================================
7169 11:52:21.679795 [ANA_INIT] >>>>>>>>>>>>>>
7170 11:52:21.683186 <<<<<< [CONFIGURE PHASE]: ANA_TX
7171 11:52:21.686294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7172 11:52:21.689532 ===================================
7173 11:52:21.692780 data_rate = 3200,PCW = 0X7600
7174 11:52:21.696074 ===================================
7175 11:52:21.699474 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7176 11:52:21.705687 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7177 11:52:21.709296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7178 11:52:21.715618 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7179 11:52:21.719303 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7180 11:52:21.722615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7181 11:52:21.722694 [ANA_INIT] flow start
7182 11:52:21.725637 [ANA_INIT] PLL >>>>>>>>
7183 11:52:21.729089 [ANA_INIT] PLL <<<<<<<<
7184 11:52:21.729189 [ANA_INIT] MIDPI >>>>>>>>
7185 11:52:21.732198 [ANA_INIT] MIDPI <<<<<<<<
7186 11:52:21.735414 [ANA_INIT] DLL >>>>>>>>
7187 11:52:21.738823 [ANA_INIT] DLL <<<<<<<<
7188 11:52:21.738931 [ANA_INIT] flow end
7189 11:52:21.742143 ============ LP4 DIFF to SE enter ============
7190 11:52:21.748732 ============ LP4 DIFF to SE exit ============
7191 11:52:21.748849 [ANA_INIT] <<<<<<<<<<<<<
7192 11:52:21.752258 [Flow] Enable top DCM control >>>>>
7193 11:52:21.755498 [Flow] Enable top DCM control <<<<<
7194 11:52:21.758448 Enable DLL master slave shuffle
7195 11:52:21.765164 ==============================================================
7196 11:52:21.765328 Gating Mode config
7197 11:52:21.771859 ==============================================================
7198 11:52:21.774822 Config description:
7199 11:52:21.785030 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7200 11:52:21.791675 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7201 11:52:21.794959 SELPH_MODE 0: By rank 1: By Phase
7202 11:52:21.801608 ==============================================================
7203 11:52:21.805051 GAT_TRACK_EN = 1
7204 11:52:21.808040 RX_GATING_MODE = 2
7205 11:52:21.811763 RX_GATING_TRACK_MODE = 2
7206 11:52:21.812316 SELPH_MODE = 1
7207 11:52:21.815161 PICG_EARLY_EN = 1
7208 11:52:21.818048 VALID_LAT_VALUE = 1
7209 11:52:21.825053 ==============================================================
7210 11:52:21.828164 Enter into Gating configuration >>>>
7211 11:52:21.831095 Exit from Gating configuration <<<<
7212 11:52:21.834664 Enter into DVFS_PRE_config >>>>>
7213 11:52:21.844478 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7214 11:52:21.847840 Exit from DVFS_PRE_config <<<<<
7215 11:52:21.851329 Enter into PICG configuration >>>>
7216 11:52:21.854344 Exit from PICG configuration <<<<
7217 11:52:21.857901 [RX_INPUT] configuration >>>>>
7218 11:52:21.860926 [RX_INPUT] configuration <<<<<
7219 11:52:21.863917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7220 11:52:21.870917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7221 11:52:21.877146 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7222 11:52:21.884069 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7223 11:52:21.890631 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7224 11:52:21.896704 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7225 11:52:21.900328 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7226 11:52:21.903366 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7227 11:52:21.906730 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7228 11:52:21.913508 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7229 11:52:21.916732 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7230 11:52:21.920264 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7231 11:52:21.923057 ===================================
7232 11:52:21.926773 LPDDR4 DRAM CONFIGURATION
7233 11:52:21.929864 ===================================
7234 11:52:21.930323 EX_ROW_EN[0] = 0x0
7235 11:52:21.933381 EX_ROW_EN[1] = 0x0
7236 11:52:21.936573 LP4Y_EN = 0x0
7237 11:52:21.936994 WORK_FSP = 0x1
7238 11:52:21.939893 WL = 0x5
7239 11:52:21.940319 RL = 0x5
7240 11:52:21.942990 BL = 0x2
7241 11:52:21.943438 RPST = 0x0
7242 11:52:21.946682 RD_PRE = 0x0
7243 11:52:21.947274 WR_PRE = 0x1
7244 11:52:21.951199 WR_PST = 0x1
7245 11:52:21.951626 DBI_WR = 0x0
7246 11:52:21.953441 DBI_RD = 0x0
7247 11:52:21.953860 OTF = 0x1
7248 11:52:21.956507 ===================================
7249 11:52:21.959804 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7250 11:52:21.965997 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7251 11:52:21.969778 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 11:52:21.972996 ===================================
7253 11:52:21.976587 LPDDR4 DRAM CONFIGURATION
7254 11:52:21.979210 ===================================
7255 11:52:21.979663 EX_ROW_EN[0] = 0x10
7256 11:52:21.982524 EX_ROW_EN[1] = 0x0
7257 11:52:21.986124 LP4Y_EN = 0x0
7258 11:52:21.986729 WORK_FSP = 0x1
7259 11:52:21.989422 WL = 0x5
7260 11:52:21.989885 RL = 0x5
7261 11:52:21.992473 BL = 0x2
7262 11:52:21.992921 RPST = 0x0
7263 11:52:21.996128 RD_PRE = 0x0
7264 11:52:21.996597 WR_PRE = 0x1
7265 11:52:21.998870 WR_PST = 0x1
7266 11:52:21.999441 DBI_WR = 0x0
7267 11:52:22.002124 DBI_RD = 0x0
7268 11:52:22.002605 OTF = 0x1
7269 11:52:22.005514 ===================================
7270 11:52:22.012215 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7271 11:52:22.012669 ==
7272 11:52:22.015464 Dram Type= 6, Freq= 0, CH_0, rank 0
7273 11:52:22.022075 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7274 11:52:22.022655 ==
7275 11:52:22.023012 [Duty_Offset_Calibration]
7276 11:52:22.025764 B0:2 B1:0 CA:4
7277 11:52:22.026412
7278 11:52:22.028319 [DutyScan_Calibration_Flow] k_type=0
7279 11:52:22.037125
7280 11:52:22.037546 ==CLK 0==
7281 11:52:22.040758 Final CLK duty delay cell = -4
7282 11:52:22.044118 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7283 11:52:22.047121 [-4] MIN Duty = 4844%(X100), DQS PI = 2
7284 11:52:22.050069 [-4] AVG Duty = 4937%(X100)
7285 11:52:22.050656
7286 11:52:22.053497 CH0 CLK Duty spec in!! Max-Min= 187%
7287 11:52:22.057014 [DutyScan_Calibration_Flow] ====Done====
7288 11:52:22.057480
7289 11:52:22.059998 [DutyScan_Calibration_Flow] k_type=1
7290 11:52:22.077361
7291 11:52:22.077815 ==DQS 0 ==
7292 11:52:22.080564 Final DQS duty delay cell = 0
7293 11:52:22.084074 [0] MAX Duty = 5218%(X100), DQS PI = 22
7294 11:52:22.087266 [0] MIN Duty = 5093%(X100), DQS PI = 12
7295 11:52:22.091192 [0] AVG Duty = 5155%(X100)
7296 11:52:22.091618
7297 11:52:22.091960 ==DQS 1 ==
7298 11:52:22.094203 Final DQS duty delay cell = 0
7299 11:52:22.097669 [0] MAX Duty = 5187%(X100), DQS PI = 2
7300 11:52:22.101092 [0] MIN Duty = 4969%(X100), DQS PI = 12
7301 11:52:22.101521 [0] AVG Duty = 5078%(X100)
7302 11:52:22.104257
7303 11:52:22.107528 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7304 11:52:22.108096
7305 11:52:22.110556 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7306 11:52:22.114060 [DutyScan_Calibration_Flow] ====Done====
7307 11:52:22.114575
7308 11:52:22.117776 [DutyScan_Calibration_Flow] k_type=3
7309 11:52:22.134465
7310 11:52:22.134897 ==DQM 0 ==
7311 11:52:22.137663 Final DQM duty delay cell = 0
7312 11:52:22.141095 [0] MAX Duty = 5124%(X100), DQS PI = 22
7313 11:52:22.144910 [0] MIN Duty = 4875%(X100), DQS PI = 56
7314 11:52:22.147864 [0] AVG Duty = 4999%(X100)
7315 11:52:22.148287
7316 11:52:22.148628 ==DQM 1 ==
7317 11:52:22.151090 Final DQM duty delay cell = 0
7318 11:52:22.154722 [0] MAX Duty = 5000%(X100), DQS PI = 2
7319 11:52:22.157444 [0] MIN Duty = 4844%(X100), DQS PI = 16
7320 11:52:22.160825 [0] AVG Duty = 4922%(X100)
7321 11:52:22.161306
7322 11:52:22.164520 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7323 11:52:22.164943
7324 11:52:22.167586 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7325 11:52:22.171239 [DutyScan_Calibration_Flow] ====Done====
7326 11:52:22.171773
7327 11:52:22.174073 [DutyScan_Calibration_Flow] k_type=2
7328 11:52:22.191660
7329 11:52:22.192177 ==DQ 0 ==
7330 11:52:22.194936 Final DQ duty delay cell = 0
7331 11:52:22.198560 [0] MAX Duty = 5156%(X100), DQS PI = 22
7332 11:52:22.201424 [0] MIN Duty = 4938%(X100), DQS PI = 14
7333 11:52:22.204705 [0] AVG Duty = 5047%(X100)
7334 11:52:22.205128
7335 11:52:22.205469 ==DQ 1 ==
7336 11:52:22.207998 Final DQ duty delay cell = 0
7337 11:52:22.211540 [0] MAX Duty = 5187%(X100), DQS PI = 4
7338 11:52:22.214877 [0] MIN Duty = 4907%(X100), DQS PI = 34
7339 11:52:22.215335 [0] AVG Duty = 5047%(X100)
7340 11:52:22.217713
7341 11:52:22.221272 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7342 11:52:22.221691
7343 11:52:22.224509 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7344 11:52:22.227865 [DutyScan_Calibration_Flow] ====Done====
7345 11:52:22.228354 ==
7346 11:52:22.230965 Dram Type= 6, Freq= 0, CH_1, rank 0
7347 11:52:22.234679 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7348 11:52:22.235312 ==
7349 11:52:22.237565 [Duty_Offset_Calibration]
7350 11:52:22.237993 B0:0 B1:-1 CA:3
7351 11:52:22.238374
7352 11:52:22.241291 [DutyScan_Calibration_Flow] k_type=0
7353 11:52:22.251345
7354 11:52:22.251757 ==CLK 0==
7355 11:52:22.254310 Final CLK duty delay cell = -4
7356 11:52:22.257830 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7357 11:52:22.260921 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7358 11:52:22.264889 [-4] AVG Duty = 4937%(X100)
7359 11:52:22.265438
7360 11:52:22.267334 CH1 CLK Duty spec in!! Max-Min= 187%
7361 11:52:22.270712 [DutyScan_Calibration_Flow] ====Done====
7362 11:52:22.271127
7363 11:52:22.274407 [DutyScan_Calibration_Flow] k_type=1
7364 11:52:22.290668
7365 11:52:22.291102 ==DQS 0 ==
7366 11:52:22.293767 Final DQS duty delay cell = 0
7367 11:52:22.297087 [0] MAX Duty = 5218%(X100), DQS PI = 28
7368 11:52:22.300197 [0] MIN Duty = 4907%(X100), DQS PI = 58
7369 11:52:22.303415 [0] AVG Duty = 5062%(X100)
7370 11:52:22.303824
7371 11:52:22.304177 ==DQS 1 ==
7372 11:52:22.306823 Final DQS duty delay cell = -4
7373 11:52:22.309941 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7374 11:52:22.313169 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7375 11:52:22.316639 [-4] AVG Duty = 4922%(X100)
7376 11:52:22.317072
7377 11:52:22.320468 CH1 DQS 0 Duty spec in!! Max-Min= 311%
7378 11:52:22.320910
7379 11:52:22.323473 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7380 11:52:22.327055 [DutyScan_Calibration_Flow] ====Done====
7381 11:52:22.327467
7382 11:52:22.329526 [DutyScan_Calibration_Flow] k_type=3
7383 11:52:22.347758
7384 11:52:22.348344 ==DQM 0 ==
7385 11:52:22.350725 Final DQM duty delay cell = 0
7386 11:52:22.354348 [0] MAX Duty = 5062%(X100), DQS PI = 30
7387 11:52:22.357633 [0] MIN Duty = 4782%(X100), DQS PI = 38
7388 11:52:22.361019 [0] AVG Duty = 4922%(X100)
7389 11:52:22.361588
7390 11:52:22.361962 ==DQM 1 ==
7391 11:52:22.364129 Final DQM duty delay cell = 0
7392 11:52:22.367441 [0] MAX Duty = 5000%(X100), DQS PI = 30
7393 11:52:22.370776 [0] MIN Duty = 4813%(X100), DQS PI = 12
7394 11:52:22.373974 [0] AVG Duty = 4906%(X100)
7395 11:52:22.374426
7396 11:52:22.377533 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7397 11:52:22.377949
7398 11:52:22.380548 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7399 11:52:22.383692 [DutyScan_Calibration_Flow] ====Done====
7400 11:52:22.384106
7401 11:52:22.387088 [DutyScan_Calibration_Flow] k_type=2
7402 11:52:22.403928
7403 11:52:22.404413 ==DQ 0 ==
7404 11:52:22.407047 Final DQ duty delay cell = -4
7405 11:52:22.410640 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7406 11:52:22.413820 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7407 11:52:22.417283 [-4] AVG Duty = 4875%(X100)
7408 11:52:22.417699
7409 11:52:22.418032 ==DQ 1 ==
7410 11:52:22.419914 Final DQ duty delay cell = 0
7411 11:52:22.423380 [0] MAX Duty = 5062%(X100), DQS PI = 32
7412 11:52:22.426574 [0] MIN Duty = 4875%(X100), DQS PI = 54
7413 11:52:22.430044 [0] AVG Duty = 4968%(X100)
7414 11:52:22.430509
7415 11:52:22.433293 CH1 DQ 0 Duty spec in!! Max-Min= 125%
7416 11:52:22.433714
7417 11:52:22.436438 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7418 11:52:22.439737 [DutyScan_Calibration_Flow] ====Done====
7419 11:52:22.443627 nWR fixed to 30
7420 11:52:22.446743 [ModeRegInit_LP4] CH0 RK0
7421 11:52:22.447159 [ModeRegInit_LP4] CH0 RK1
7422 11:52:22.449827 [ModeRegInit_LP4] CH1 RK0
7423 11:52:22.453637 [ModeRegInit_LP4] CH1 RK1
7424 11:52:22.454051 match AC timing 5
7425 11:52:22.459487 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7426 11:52:22.462931 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7427 11:52:22.466377 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7428 11:52:22.472845 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7429 11:52:22.475876 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7430 11:52:22.479502 [MiockJmeterHQA]
7431 11:52:22.479916
7432 11:52:22.482180 [DramcMiockJmeter] u1RxGatingPI = 0
7433 11:52:22.482630 0 : 4255, 4030
7434 11:52:22.482974 4 : 4252, 4027
7435 11:52:22.485873 8 : 4257, 4029
7436 11:52:22.486334 12 : 4258, 4029
7437 11:52:22.489001 16 : 4257, 4029
7438 11:52:22.489424 20 : 4365, 4137
7439 11:52:22.492321 24 : 4368, 4140
7440 11:52:22.492750 28 : 4371, 4142
7441 11:52:22.495885 32 : 4255, 4027
7442 11:52:22.496312 36 : 4255, 4027
7443 11:52:22.496661 40 : 4255, 4027
7444 11:52:22.498924 44 : 4365, 4138
7445 11:52:22.499454 48 : 4366, 4137
7446 11:52:22.502242 52 : 4368, 4140
7447 11:52:22.502699 56 : 4254, 4029
7448 11:52:22.505510 60 : 4253, 4029
7449 11:52:22.505936 64 : 4365, 4140
7450 11:52:22.508497 68 : 4250, 4027
7451 11:52:22.508925 72 : 4253, 4029
7452 11:52:22.509267 76 : 4252, 4027
7453 11:52:22.512390 80 : 4250, 4027
7454 11:52:22.512818 84 : 4249, 4027
7455 11:52:22.515321 88 : 4250, 4026
7456 11:52:22.515783 92 : 4250, 4027
7457 11:52:22.518949 96 : 4360, 3174
7458 11:52:22.519373 100 : 4250, 0
7459 11:52:22.519714 104 : 4250, 0
7460 11:52:22.521709 108 : 4360, 0
7461 11:52:22.522339 112 : 4361, 0
7462 11:52:22.525139 116 : 4250, 0
7463 11:52:22.525747 120 : 4250, 0
7464 11:52:22.526380 124 : 4250, 0
7465 11:52:22.528270 128 : 4253, 0
7466 11:52:22.528873 132 : 4250, 0
7467 11:52:22.531674 136 : 4250, 0
7468 11:52:22.532114 140 : 4255, 0
7469 11:52:22.532564 144 : 4360, 0
7470 11:52:22.534909 148 : 4361, 0
7471 11:52:22.535345 152 : 4250, 0
7472 11:52:22.538200 156 : 4247, 0
7473 11:52:22.538696 160 : 4250, 0
7474 11:52:22.539145 164 : 4363, 0
7475 11:52:22.541326 168 : 4255, 0
7476 11:52:22.541765 172 : 4249, 0
7477 11:52:22.544740 176 : 4250, 0
7478 11:52:22.545179 180 : 4253, 0
7479 11:52:22.545627 184 : 4250, 0
7480 11:52:22.548447 188 : 4250, 0
7481 11:52:22.548882 192 : 4253, 0
7482 11:52:22.551458 196 : 4360, 0
7483 11:52:22.551896 200 : 4361, 0
7484 11:52:22.552346 204 : 4250, 0
7485 11:52:22.554778 208 : 4255, 0
7486 11:52:22.555220 212 : 4360, 0
7487 11:52:22.555668 216 : 4250, 0
7488 11:52:22.557795 220 : 4255, 514
7489 11:52:22.558245 224 : 4255, 3992
7490 11:52:22.561260 228 : 4360, 4138
7491 11:52:22.561691 232 : 4360, 4138
7492 11:52:22.564727 236 : 4250, 4027
7493 11:52:22.565230 240 : 4255, 4029
7494 11:52:22.567621 244 : 4360, 4138
7495 11:52:22.568142 248 : 4363, 4138
7496 11:52:22.571067 252 : 4250, 4027
7497 11:52:22.571494 256 : 4363, 4140
7498 11:52:22.574747 260 : 4253, 4029
7499 11:52:22.575178 264 : 4250, 4026
7500 11:52:22.578315 268 : 4252, 4029
7501 11:52:22.578748 272 : 4252, 4029
7502 11:52:22.581020 276 : 4253, 4029
7503 11:52:22.581449 280 : 4363, 4140
7504 11:52:22.581797 284 : 4254, 4029
7505 11:52:22.584305 288 : 4250, 4027
7506 11:52:22.584733 292 : 4250, 4027
7507 11:52:22.587474 296 : 4363, 4140
7508 11:52:22.587919 300 : 4363, 4138
7509 11:52:22.590738 304 : 4250, 4027
7510 11:52:22.591165 308 : 4366, 4140
7511 11:52:22.594872 312 : 4253, 4029
7512 11:52:22.595299 316 : 4250, 4026
7513 11:52:22.597480 320 : 4252, 4029
7514 11:52:22.597902 324 : 4252, 4029
7515 11:52:22.600808 328 : 4252, 4029
7516 11:52:22.601232 332 : 4360, 4121
7517 11:52:22.604523 336 : 4254, 1998
7518 11:52:22.605086
7519 11:52:22.605432 MIOCK jitter meter ch=0
7520 11:52:22.605745
7521 11:52:22.607787 1T = (336-100) = 236 dly cells
7522 11:52:22.614071 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7523 11:52:22.614587 ==
7524 11:52:22.617705 Dram Type= 6, Freq= 0, CH_0, rank 0
7525 11:52:22.620401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7526 11:52:22.620861 ==
7527 11:52:22.627124 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7528 11:52:22.630633 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7529 11:52:22.637183 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7530 11:52:22.640013 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7531 11:52:22.650379 [CA 0] Center 43 (13~73) winsize 61
7532 11:52:22.653644 [CA 1] Center 42 (12~73) winsize 62
7533 11:52:22.656886 [CA 2] Center 37 (8~67) winsize 60
7534 11:52:22.660357 [CA 3] Center 37 (7~67) winsize 61
7535 11:52:22.663888 [CA 4] Center 36 (6~66) winsize 61
7536 11:52:22.666608 [CA 5] Center 35 (5~66) winsize 62
7537 11:52:22.667029
7538 11:52:22.669825 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7539 11:52:22.670245
7540 11:52:22.676317 [CATrainingPosCal] consider 1 rank data
7541 11:52:22.676736 u2DelayCellTimex100 = 275/100 ps
7542 11:52:22.683320 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7543 11:52:22.686568 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7544 11:52:22.689660 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7545 11:52:22.692936 CA3 delay=37 (7~67),Diff = 2 PI (7 cell)
7546 11:52:22.696041 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7547 11:52:22.699413 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7548 11:52:22.699835
7549 11:52:22.702581 CA PerBit enable=1, Macro0, CA PI delay=35
7550 11:52:22.702999
7551 11:52:22.706209 [CBTSetCACLKResult] CA Dly = 35
7552 11:52:22.709492 CS Dly: 11 (0~42)
7553 11:52:22.712350 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7554 11:52:22.715793 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7555 11:52:22.716215 ==
7556 11:52:22.719676 Dram Type= 6, Freq= 0, CH_0, rank 1
7557 11:52:22.726138 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 11:52:22.726609 ==
7559 11:52:22.729014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7560 11:52:22.735594 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7561 11:52:22.739242 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7562 11:52:22.745794 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7563 11:52:22.753801 [CA 0] Center 44 (14~74) winsize 61
7564 11:52:22.757221 [CA 1] Center 44 (14~74) winsize 61
7565 11:52:22.760417 [CA 2] Center 39 (10~69) winsize 60
7566 11:52:22.763474 [CA 3] Center 39 (10~68) winsize 59
7567 11:52:22.767438 [CA 4] Center 37 (7~67) winsize 61
7568 11:52:22.770272 [CA 5] Center 36 (6~66) winsize 61
7569 11:52:22.770703
7570 11:52:22.773453 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7571 11:52:22.773890
7572 11:52:22.779810 [CATrainingPosCal] consider 2 rank data
7573 11:52:22.780247 u2DelayCellTimex100 = 275/100 ps
7574 11:52:22.786693 CA0 delay=43 (14~73),Diff = 7 PI (24 cell)
7575 11:52:22.789980 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7576 11:52:22.792986 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7577 11:52:22.796489 CA3 delay=38 (10~67),Diff = 2 PI (7 cell)
7578 11:52:22.799886 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7579 11:52:22.802982 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7580 11:52:22.803503
7581 11:52:22.806309 CA PerBit enable=1, Macro0, CA PI delay=36
7582 11:52:22.806734
7583 11:52:22.809536 [CBTSetCACLKResult] CA Dly = 36
7584 11:52:22.812693 CS Dly: 12 (0~44)
7585 11:52:22.816328 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7586 11:52:22.819475 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7587 11:52:22.819944
7588 11:52:22.822723 ----->DramcWriteLeveling(PI) begin...
7589 11:52:22.826090 ==
7590 11:52:22.829616 Dram Type= 6, Freq= 0, CH_0, rank 0
7591 11:52:22.832856 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7592 11:52:22.833277 ==
7593 11:52:22.836028 Write leveling (Byte 0): 35 => 35
7594 11:52:22.839486 Write leveling (Byte 1): 26 => 26
7595 11:52:22.842239 DramcWriteLeveling(PI) end<-----
7596 11:52:22.842693
7597 11:52:22.843027 ==
7598 11:52:22.845970 Dram Type= 6, Freq= 0, CH_0, rank 0
7599 11:52:22.848816 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7600 11:52:22.849235 ==
7601 11:52:22.852391 [Gating] SW mode calibration
7602 11:52:22.859173 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7603 11:52:22.865559 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7604 11:52:22.868913 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7605 11:52:22.872424 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7606 11:52:22.878753 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7607 11:52:22.881906 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
7608 11:52:22.885464 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7609 11:52:22.891618 1 4 20 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7610 11:52:22.894897 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7611 11:52:22.898385 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7612 11:52:22.905119 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7613 11:52:22.908816 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7614 11:52:22.911715 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
7615 11:52:22.918034 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 1)
7616 11:52:22.921493 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7617 11:52:22.924209 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7618 11:52:22.931268 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7619 11:52:22.934580 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 11:52:22.937659 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 11:52:22.944471 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 11:52:22.947459 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
7623 11:52:22.950909 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
7624 11:52:22.957484 1 6 16 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
7625 11:52:22.961109 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7626 11:52:22.964349 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 11:52:22.971039 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 11:52:22.973893 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 11:52:22.977243 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7630 11:52:22.983921 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7631 11:52:22.987390 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7632 11:52:22.991182 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7633 11:52:22.997089 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7634 11:52:23.000229 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7635 11:52:23.003697 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 11:52:23.011095 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 11:52:23.013630 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 11:52:23.016854 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 11:52:23.023815 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 11:52:23.026807 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 11:52:23.030285 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 11:52:23.036818 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 11:52:23.040527 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 11:52:23.043276 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7645 11:52:23.049664 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7646 11:52:23.053048 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7647 11:52:23.056229 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7648 11:52:23.063989 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7649 11:52:23.067186 Total UI for P1: 0, mck2ui 16
7650 11:52:23.071254 best dqsien dly found for B0: ( 1, 9, 8)
7651 11:52:23.073159 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7652 11:52:23.076792 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7653 11:52:23.082880 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7654 11:52:23.083353 Total UI for P1: 0, mck2ui 16
7655 11:52:23.089396 best dqsien dly found for B1: ( 1, 9, 20)
7656 11:52:23.092645 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7657 11:52:23.096604 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7658 11:52:23.097158
7659 11:52:23.099333 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7660 11:52:23.102318 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7661 11:52:23.105649 [Gating] SW calibration Done
7662 11:52:23.106224 ==
7663 11:52:23.108823 Dram Type= 6, Freq= 0, CH_0, rank 0
7664 11:52:23.112032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7665 11:52:23.112501 ==
7666 11:52:23.115695 RX Vref Scan: 0
7667 11:52:23.116114
7668 11:52:23.118530 RX Vref 0 -> 0, step: 1
7669 11:52:23.118953
7670 11:52:23.119365 RX Delay 0 -> 252, step: 8
7671 11:52:23.125473 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7672 11:52:23.128488 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7673 11:52:23.132429 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7674 11:52:23.135289 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7675 11:52:23.138770 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7676 11:52:23.144723 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7677 11:52:23.148199 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7678 11:52:23.151649 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7679 11:52:23.154987 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7680 11:52:23.158048 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7681 11:52:23.165124 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7682 11:52:23.168377 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7683 11:52:23.171467 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7684 11:52:23.174710 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7685 11:52:23.181791 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7686 11:52:23.184903 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7687 11:52:23.185326 ==
7688 11:52:23.187720 Dram Type= 6, Freq= 0, CH_0, rank 0
7689 11:52:23.191506 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7690 11:52:23.191933 ==
7691 11:52:23.194463 DQS Delay:
7692 11:52:23.194884 DQS0 = 0, DQS1 = 0
7693 11:52:23.195224 DQM Delay:
7694 11:52:23.197666 DQM0 = 131, DQM1 = 126
7695 11:52:23.198089 DQ Delay:
7696 11:52:23.200937 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7697 11:52:23.204216 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7698 11:52:23.208201 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7699 11:52:23.214446 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7700 11:52:23.214903
7701 11:52:23.215237
7702 11:52:23.215547 ==
7703 11:52:23.217443 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 11:52:23.220673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 11:52:23.221261 ==
7706 11:52:23.221776
7707 11:52:23.222236
7708 11:52:23.224492 TX Vref Scan disable
7709 11:52:23.224912 == TX Byte 0 ==
7710 11:52:23.230669 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7711 11:52:23.234204 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7712 11:52:23.234676 == TX Byte 1 ==
7713 11:52:23.240462 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7714 11:52:23.243801 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7715 11:52:23.244285 ==
7716 11:52:23.247583 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 11:52:23.250754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 11:52:23.251181 ==
7719 11:52:23.265748
7720 11:52:23.269157 TX Vref early break, caculate TX vref
7721 11:52:23.272226 TX Vref=16, minBit 1, minWin=22, winSum=368
7722 11:52:23.275377 TX Vref=18, minBit 0, minWin=23, winSum=381
7723 11:52:23.278594 TX Vref=20, minBit 7, minWin=23, winSum=390
7724 11:52:23.281908 TX Vref=22, minBit 4, minWin=24, winSum=400
7725 11:52:23.285411 TX Vref=24, minBit 1, minWin=24, winSum=406
7726 11:52:23.291979 TX Vref=26, minBit 1, minWin=25, winSum=417
7727 11:52:23.295263 TX Vref=28, minBit 2, minWin=25, winSum=423
7728 11:52:23.298794 TX Vref=30, minBit 2, minWin=25, winSum=419
7729 11:52:23.302004 TX Vref=32, minBit 0, minWin=24, winSum=407
7730 11:52:23.305262 TX Vref=34, minBit 2, minWin=23, winSum=397
7731 11:52:23.312309 [TxChooseVref] Worse bit 2, Min win 25, Win sum 423, Final Vref 28
7732 11:52:23.312734
7733 11:52:23.315234 Final TX Range 0 Vref 28
7734 11:52:23.315812
7735 11:52:23.316330 ==
7736 11:52:23.318721 Dram Type= 6, Freq= 0, CH_0, rank 0
7737 11:52:23.321998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7738 11:52:23.322455 ==
7739 11:52:23.322827
7740 11:52:23.323178
7741 11:52:23.325106 TX Vref Scan disable
7742 11:52:23.331778 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7743 11:52:23.332201 == TX Byte 0 ==
7744 11:52:23.334959 u2DelayCellOfst[0]=10 cells (3 PI)
7745 11:52:23.338239 u2DelayCellOfst[1]=14 cells (4 PI)
7746 11:52:23.341660 u2DelayCellOfst[2]=10 cells (3 PI)
7747 11:52:23.345103 u2DelayCellOfst[3]=10 cells (3 PI)
7748 11:52:23.347793 u2DelayCellOfst[4]=7 cells (2 PI)
7749 11:52:23.351164 u2DelayCellOfst[5]=0 cells (0 PI)
7750 11:52:23.354594 u2DelayCellOfst[6]=14 cells (4 PI)
7751 11:52:23.358078 u2DelayCellOfst[7]=14 cells (4 PI)
7752 11:52:23.361243 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7753 11:52:23.364219 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7754 11:52:23.368303 == TX Byte 1 ==
7755 11:52:23.371071 u2DelayCellOfst[8]=0 cells (0 PI)
7756 11:52:23.374430 u2DelayCellOfst[9]=0 cells (0 PI)
7757 11:52:23.377615 u2DelayCellOfst[10]=3 cells (1 PI)
7758 11:52:23.380810 u2DelayCellOfst[11]=0 cells (0 PI)
7759 11:52:23.381383 u2DelayCellOfst[12]=7 cells (2 PI)
7760 11:52:23.383967 u2DelayCellOfst[13]=7 cells (2 PI)
7761 11:52:23.387212 u2DelayCellOfst[14]=14 cells (4 PI)
7762 11:52:23.390536 u2DelayCellOfst[15]=10 cells (3 PI)
7763 11:52:23.396975 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7764 11:52:23.400234 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7765 11:52:23.400656 DramC Write-DBI on
7766 11:52:23.403675 ==
7767 11:52:23.406956 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 11:52:23.410389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 11:52:23.410891 ==
7770 11:52:23.411233
7771 11:52:23.411543
7772 11:52:23.413490 TX Vref Scan disable
7773 11:52:23.414043 == TX Byte 0 ==
7774 11:52:23.420018 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7775 11:52:23.420526 == TX Byte 1 ==
7776 11:52:23.423376 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7777 11:52:23.426651 DramC Write-DBI off
7778 11:52:23.427067
7779 11:52:23.427434 [DATLAT]
7780 11:52:23.430471 Freq=1600, CH0 RK0
7781 11:52:23.430973
7782 11:52:23.431349 DATLAT Default: 0xf
7783 11:52:23.433598 0, 0xFFFF, sum = 0
7784 11:52:23.434012 1, 0xFFFF, sum = 0
7785 11:52:23.437610 2, 0xFFFF, sum = 0
7786 11:52:23.439904 3, 0xFFFF, sum = 0
7787 11:52:23.440588 4, 0xFFFF, sum = 0
7788 11:52:23.443573 5, 0xFFFF, sum = 0
7789 11:52:23.444031 6, 0xFFFF, sum = 0
7790 11:52:23.447006 7, 0xFFFF, sum = 0
7791 11:52:23.447508 8, 0xFFFF, sum = 0
7792 11:52:23.449680 9, 0xFFFF, sum = 0
7793 11:52:23.450142 10, 0xFFFF, sum = 0
7794 11:52:23.453021 11, 0xFFFF, sum = 0
7795 11:52:23.453516 12, 0xFFFF, sum = 0
7796 11:52:23.456367 13, 0xFFFF, sum = 0
7797 11:52:23.456830 14, 0x0, sum = 1
7798 11:52:23.459704 15, 0x0, sum = 2
7799 11:52:23.460255 16, 0x0, sum = 3
7800 11:52:23.463419 17, 0x0, sum = 4
7801 11:52:23.463883 best_step = 15
7802 11:52:23.464336
7803 11:52:23.464659 ==
7804 11:52:23.466360 Dram Type= 6, Freq= 0, CH_0, rank 0
7805 11:52:23.472602 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7806 11:52:23.473010 ==
7807 11:52:23.473339 RX Vref Scan: 1
7808 11:52:23.473648
7809 11:52:23.475998 Set Vref Range= 24 -> 127
7810 11:52:23.476417
7811 11:52:23.479208 RX Vref 24 -> 127, step: 1
7812 11:52:23.479604
7813 11:52:23.479928 RX Delay 11 -> 252, step: 4
7814 11:52:23.482914
7815 11:52:23.483331 Set Vref, RX VrefLevel [Byte0]: 24
7816 11:52:23.485785 [Byte1]: 24
7817 11:52:23.490455
7818 11:52:23.490873 Set Vref, RX VrefLevel [Byte0]: 25
7819 11:52:23.493273 [Byte1]: 25
7820 11:52:23.497647
7821 11:52:23.498153 Set Vref, RX VrefLevel [Byte0]: 26
7822 11:52:23.500999 [Byte1]: 26
7823 11:52:23.505673
7824 11:52:23.506090 Set Vref, RX VrefLevel [Byte0]: 27
7825 11:52:23.508546 [Byte1]: 27
7826 11:52:23.513718
7827 11:52:23.514135 Set Vref, RX VrefLevel [Byte0]: 28
7828 11:52:23.515892 [Byte1]: 28
7829 11:52:23.520585
7830 11:52:23.521002 Set Vref, RX VrefLevel [Byte0]: 29
7831 11:52:23.523848 [Byte1]: 29
7832 11:52:23.528292
7833 11:52:23.528778 Set Vref, RX VrefLevel [Byte0]: 30
7834 11:52:23.531341 [Byte1]: 30
7835 11:52:23.535631
7836 11:52:23.536133 Set Vref, RX VrefLevel [Byte0]: 31
7837 11:52:23.539669 [Byte1]: 31
7838 11:52:23.543565
7839 11:52:23.543981 Set Vref, RX VrefLevel [Byte0]: 32
7840 11:52:23.546689 [Byte1]: 32
7841 11:52:23.551628
7842 11:52:23.552045 Set Vref, RX VrefLevel [Byte0]: 33
7843 11:52:23.554226 [Byte1]: 33
7844 11:52:23.558890
7845 11:52:23.559464 Set Vref, RX VrefLevel [Byte0]: 34
7846 11:52:23.561819 [Byte1]: 34
7847 11:52:23.566357
7848 11:52:23.566807 Set Vref, RX VrefLevel [Byte0]: 35
7849 11:52:23.569576 [Byte1]: 35
7850 11:52:23.573762
7851 11:52:23.574231 Set Vref, RX VrefLevel [Byte0]: 36
7852 11:52:23.577132 [Byte1]: 36
7853 11:52:23.581251
7854 11:52:23.584766 Set Vref, RX VrefLevel [Byte0]: 37
7855 11:52:23.588090 [Byte1]: 37
7856 11:52:23.588566
7857 11:52:23.591222 Set Vref, RX VrefLevel [Byte0]: 38
7858 11:52:23.595101 [Byte1]: 38
7859 11:52:23.595557
7860 11:52:23.598458 Set Vref, RX VrefLevel [Byte0]: 39
7861 11:52:23.600987 [Byte1]: 39
7862 11:52:23.601404
7863 11:52:23.604267 Set Vref, RX VrefLevel [Byte0]: 40
7864 11:52:23.607771 [Byte1]: 40
7865 11:52:23.612164
7866 11:52:23.612591 Set Vref, RX VrefLevel [Byte0]: 41
7867 11:52:23.614990 [Byte1]: 41
7868 11:52:23.619491
7869 11:52:23.619942 Set Vref, RX VrefLevel [Byte0]: 42
7870 11:52:23.623250 [Byte1]: 42
7871 11:52:23.627498
7872 11:52:23.627911 Set Vref, RX VrefLevel [Byte0]: 43
7873 11:52:23.630984 [Byte1]: 43
7874 11:52:23.635157
7875 11:52:23.635607 Set Vref, RX VrefLevel [Byte0]: 44
7876 11:52:23.637982 [Byte1]: 44
7877 11:52:23.642330
7878 11:52:23.642824 Set Vref, RX VrefLevel [Byte0]: 45
7879 11:52:23.645529 [Byte1]: 45
7880 11:52:23.650066
7881 11:52:23.650579 Set Vref, RX VrefLevel [Byte0]: 46
7882 11:52:23.653242 [Byte1]: 46
7883 11:52:23.657604
7884 11:52:23.658019 Set Vref, RX VrefLevel [Byte0]: 47
7885 11:52:23.660765 [Byte1]: 47
7886 11:52:23.665316
7887 11:52:23.665726 Set Vref, RX VrefLevel [Byte0]: 48
7888 11:52:23.668364 [Byte1]: 48
7889 11:52:23.673338
7890 11:52:23.673835 Set Vref, RX VrefLevel [Byte0]: 49
7891 11:52:23.676917 [Byte1]: 49
7892 11:52:23.680445
7893 11:52:23.680858 Set Vref, RX VrefLevel [Byte0]: 50
7894 11:52:23.683855 [Byte1]: 50
7895 11:52:23.688368
7896 11:52:23.688782 Set Vref, RX VrefLevel [Byte0]: 51
7897 11:52:23.691937 [Byte1]: 51
7898 11:52:23.695702
7899 11:52:23.696129 Set Vref, RX VrefLevel [Byte0]: 52
7900 11:52:23.698728 [Byte1]: 52
7901 11:52:23.703316
7902 11:52:23.703733 Set Vref, RX VrefLevel [Byte0]: 53
7903 11:52:23.706353 [Byte1]: 53
7904 11:52:23.710707
7905 11:52:23.711172 Set Vref, RX VrefLevel [Byte0]: 54
7906 11:52:23.714769 [Byte1]: 54
7907 11:52:23.718475
7908 11:52:23.718894 Set Vref, RX VrefLevel [Byte0]: 55
7909 11:52:23.721899 [Byte1]: 55
7910 11:52:23.726016
7911 11:52:23.726482 Set Vref, RX VrefLevel [Byte0]: 56
7912 11:52:23.729570 [Byte1]: 56
7913 11:52:23.733552
7914 11:52:23.733970 Set Vref, RX VrefLevel [Byte0]: 57
7915 11:52:23.736845 [Byte1]: 57
7916 11:52:23.741678
7917 11:52:23.742348 Set Vref, RX VrefLevel [Byte0]: 58
7918 11:52:23.744927 [Byte1]: 58
7919 11:52:23.748845
7920 11:52:23.749277 Set Vref, RX VrefLevel [Byte0]: 59
7921 11:52:23.752287 [Byte1]: 59
7922 11:52:23.756589
7923 11:52:23.757008 Set Vref, RX VrefLevel [Byte0]: 60
7924 11:52:23.759834 [Byte1]: 60
7925 11:52:23.764246
7926 11:52:23.764745 Set Vref, RX VrefLevel [Byte0]: 61
7927 11:52:23.767577 [Byte1]: 61
7928 11:52:23.771723
7929 11:52:23.772188 Set Vref, RX VrefLevel [Byte0]: 62
7930 11:52:23.775473 [Byte1]: 62
7931 11:52:23.779574
7932 11:52:23.780062 Set Vref, RX VrefLevel [Byte0]: 63
7933 11:52:23.782681 [Byte1]: 63
7934 11:52:23.787106
7935 11:52:23.787731 Set Vref, RX VrefLevel [Byte0]: 64
7936 11:52:23.790531 [Byte1]: 64
7937 11:52:23.795190
7938 11:52:23.795651 Set Vref, RX VrefLevel [Byte0]: 65
7939 11:52:23.798550 [Byte1]: 65
7940 11:52:23.802067
7941 11:52:23.802578 Set Vref, RX VrefLevel [Byte0]: 66
7942 11:52:23.805330 [Byte1]: 66
7943 11:52:23.809825
7944 11:52:23.810432 Set Vref, RX VrefLevel [Byte0]: 67
7945 11:52:23.812919 [Byte1]: 67
7946 11:52:23.817256
7947 11:52:23.817660 Set Vref, RX VrefLevel [Byte0]: 68
7948 11:52:23.820585 [Byte1]: 68
7949 11:52:23.825275
7950 11:52:23.825421 Set Vref, RX VrefLevel [Byte0]: 69
7951 11:52:23.828148 [Byte1]: 69
7952 11:52:23.832210
7953 11:52:23.832313 Set Vref, RX VrefLevel [Byte0]: 70
7954 11:52:23.835520 [Byte1]: 70
7955 11:52:23.839944
7956 11:52:23.840015 Set Vref, RX VrefLevel [Byte0]: 71
7957 11:52:23.843575 [Byte1]: 71
7958 11:52:23.847888
7959 11:52:23.847968 Set Vref, RX VrefLevel [Byte0]: 72
7960 11:52:23.850906 [Byte1]: 72
7961 11:52:23.855563
7962 11:52:23.855639 Set Vref, RX VrefLevel [Byte0]: 73
7963 11:52:23.858429 [Byte1]: 73
7964 11:52:23.863035
7965 11:52:23.863111 Set Vref, RX VrefLevel [Byte0]: 74
7966 11:52:23.865939 [Byte1]: 74
7967 11:52:23.870098
7968 11:52:23.870194 Final RX Vref Byte 0 = 54 to rank0
7969 11:52:23.873718 Final RX Vref Byte 1 = 59 to rank0
7970 11:52:23.877216 Final RX Vref Byte 0 = 54 to rank1
7971 11:52:23.880300 Final RX Vref Byte 1 = 59 to rank1==
7972 11:52:23.883450 Dram Type= 6, Freq= 0, CH_0, rank 0
7973 11:52:23.890105 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7974 11:52:23.890205 ==
7975 11:52:23.890323 DQS Delay:
7976 11:52:23.893472 DQS0 = 0, DQS1 = 0
7977 11:52:23.893541 DQM Delay:
7978 11:52:23.893601 DQM0 = 128, DQM1 = 124
7979 11:52:23.897251 DQ Delay:
7980 11:52:23.899871 DQ0 =130, DQ1 =130, DQ2 =124, DQ3 =124
7981 11:52:23.903281 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7982 11:52:23.906353 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
7983 11:52:23.909464 DQ12 =132, DQ13 =130, DQ14 =132, DQ15 =130
7984 11:52:23.909534
7985 11:52:23.909594
7986 11:52:23.909651
7987 11:52:23.912955 [DramC_TX_OE_Calibration] TA2
7988 11:52:23.916503 Original DQ_B0 (3 6) =30, OEN = 27
7989 11:52:23.920018 Original DQ_B1 (3 6) =30, OEN = 27
7990 11:52:23.922685 24, 0x0, End_B0=24 End_B1=24
7991 11:52:23.926442 25, 0x0, End_B0=25 End_B1=25
7992 11:52:23.926515 26, 0x0, End_B0=26 End_B1=26
7993 11:52:23.929583 27, 0x0, End_B0=27 End_B1=27
7994 11:52:23.932959 28, 0x0, End_B0=28 End_B1=28
7995 11:52:23.936224 29, 0x0, End_B0=29 End_B1=29
7996 11:52:23.936301 30, 0x0, End_B0=30 End_B1=30
7997 11:52:23.940359 31, 0x4141, End_B0=30 End_B1=30
7998 11:52:23.942392 Byte0 end_step=30 best_step=27
7999 11:52:23.945790 Byte1 end_step=30 best_step=27
8000 11:52:23.949264 Byte0 TX OE(2T, 0.5T) = (3, 3)
8001 11:52:23.952491 Byte1 TX OE(2T, 0.5T) = (3, 3)
8002 11:52:23.952567
8003 11:52:23.952631
8004 11:52:23.959361 [DQSOSCAuto] RK0, (LSB)MR18= 0x1916, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
8005 11:52:23.962565 CH0 RK0: MR19=303, MR18=1916
8006 11:52:23.969161 CH0_RK0: MR19=0x303, MR18=0x1916, DQSOSC=397, MR23=63, INC=23, DEC=15
8007 11:52:23.969238
8008 11:52:23.972464 ----->DramcWriteLeveling(PI) begin...
8009 11:52:23.972536 ==
8010 11:52:23.975852 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 11:52:23.979029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 11:52:23.979097 ==
8013 11:52:23.982417 Write leveling (Byte 0): 35 => 35
8014 11:52:23.985881 Write leveling (Byte 1): 26 => 26
8015 11:52:23.989190 DramcWriteLeveling(PI) end<-----
8016 11:52:23.989260
8017 11:52:23.989320 ==
8018 11:52:23.992230 Dram Type= 6, Freq= 0, CH_0, rank 1
8019 11:52:23.998980 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8020 11:52:23.999054 ==
8021 11:52:23.999117 [Gating] SW mode calibration
8022 11:52:24.009115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8023 11:52:24.012168 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8024 11:52:24.015452 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 11:52:24.022000 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 11:52:24.025104 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
8027 11:52:24.028883 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8028 11:52:24.035270 1 4 16 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
8029 11:52:24.038475 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8030 11:52:24.041744 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8031 11:52:24.048635 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8032 11:52:24.051644 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8033 11:52:24.055191 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8034 11:52:24.061452 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
8035 11:52:24.064689 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 1)
8036 11:52:24.067855 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8037 11:52:24.074940 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
8038 11:52:24.077764 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8039 11:52:24.081266 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8040 11:52:24.087851 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8041 11:52:24.091418 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8042 11:52:24.094117 1 6 8 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8043 11:52:24.101266 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8044 11:52:24.104571 1 6 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)
8045 11:52:24.107538 1 6 20 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8046 11:52:24.114260 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8047 11:52:24.118142 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8048 11:52:24.120721 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8049 11:52:24.127657 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8050 11:52:24.130769 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8051 11:52:24.134205 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8052 11:52:24.140695 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8053 11:52:24.144062 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8054 11:52:24.147056 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8055 11:52:24.154015 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8056 11:52:24.157346 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8057 11:52:24.160122 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8058 11:52:24.166780 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8059 11:52:24.170191 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 11:52:24.176835 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8061 11:52:24.180240 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 11:52:24.183384 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 11:52:24.189613 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 11:52:24.193895 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 11:52:24.196454 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8066 11:52:24.199651 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8067 11:52:24.206171 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8068 11:52:24.209999 Total UI for P1: 0, mck2ui 16
8069 11:52:24.212842 best dqsien dly found for B0: ( 1, 9, 6)
8070 11:52:24.216177 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8071 11:52:24.219488 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8072 11:52:24.226045 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8073 11:52:24.229808 Total UI for P1: 0, mck2ui 16
8074 11:52:24.232776 best dqsien dly found for B1: ( 1, 9, 18)
8075 11:52:24.235971 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8076 11:52:24.239970 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8077 11:52:24.240042
8078 11:52:24.242443 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8079 11:52:24.246050 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8080 11:52:24.249090 [Gating] SW calibration Done
8081 11:52:24.249171 ==
8082 11:52:24.253068 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 11:52:24.255862 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 11:52:24.255943 ==
8085 11:52:24.259470 RX Vref Scan: 0
8086 11:52:24.259551
8087 11:52:24.262892 RX Vref 0 -> 0, step: 1
8088 11:52:24.262973
8089 11:52:24.263073 RX Delay 0 -> 252, step: 8
8090 11:52:24.268976 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8091 11:52:24.272284 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8092 11:52:24.275538 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8093 11:52:24.278987 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8094 11:52:24.282946 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8095 11:52:24.289314 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8096 11:52:24.292705 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8097 11:52:24.295390 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8098 11:52:24.299164 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8099 11:52:24.302142 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8100 11:52:24.308970 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8101 11:52:24.311956 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8102 11:52:24.315184 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8103 11:52:24.318939 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8104 11:52:24.325443 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8105 11:52:24.328333 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8106 11:52:24.328413 ==
8107 11:52:24.331591 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 11:52:24.335049 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 11:52:24.335120 ==
8110 11:52:24.338631 DQS Delay:
8111 11:52:24.338702 DQS0 = 0, DQS1 = 0
8112 11:52:24.338762 DQM Delay:
8113 11:52:24.341790 DQM0 = 132, DQM1 = 123
8114 11:52:24.341863 DQ Delay:
8115 11:52:24.345127 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8116 11:52:24.348598 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8117 11:52:24.352095 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
8118 11:52:24.358078 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8119 11:52:24.358155
8120 11:52:24.358218
8121 11:52:24.358315 ==
8122 11:52:24.361967 Dram Type= 6, Freq= 0, CH_0, rank 1
8123 11:52:24.365243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8124 11:52:24.365316 ==
8125 11:52:24.365376
8126 11:52:24.365437
8127 11:52:24.367936 TX Vref Scan disable
8128 11:52:24.368002 == TX Byte 0 ==
8129 11:52:24.374920 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8130 11:52:24.378176 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8131 11:52:24.378244 == TX Byte 1 ==
8132 11:52:24.384602 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8133 11:52:24.388045 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8134 11:52:24.388114 ==
8135 11:52:24.391139 Dram Type= 6, Freq= 0, CH_0, rank 1
8136 11:52:24.394352 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8137 11:52:24.394422 ==
8138 11:52:24.409481
8139 11:52:24.412651 TX Vref early break, caculate TX vref
8140 11:52:24.416573 TX Vref=16, minBit 9, minWin=22, winSum=381
8141 11:52:24.419412 TX Vref=18, minBit 11, minWin=23, winSum=389
8142 11:52:24.423032 TX Vref=20, minBit 3, minWin=24, winSum=399
8143 11:52:24.426889 TX Vref=22, minBit 2, minWin=24, winSum=403
8144 11:52:24.429340 TX Vref=24, minBit 1, minWin=25, winSum=415
8145 11:52:24.435745 TX Vref=26, minBit 4, minWin=25, winSum=417
8146 11:52:24.439583 TX Vref=28, minBit 0, minWin=26, winSum=424
8147 11:52:24.442405 TX Vref=30, minBit 1, minWin=25, winSum=412
8148 11:52:24.445408 TX Vref=32, minBit 1, minWin=24, winSum=404
8149 11:52:24.449492 TX Vref=34, minBit 0, minWin=24, winSum=394
8150 11:52:24.455465 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
8151 11:52:24.455541
8152 11:52:24.458828 Final TX Range 0 Vref 28
8153 11:52:24.458902
8154 11:52:24.458964 ==
8155 11:52:24.462137 Dram Type= 6, Freq= 0, CH_0, rank 1
8156 11:52:24.465488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8157 11:52:24.465560 ==
8158 11:52:24.465621
8159 11:52:24.468654
8160 11:52:24.468721 TX Vref Scan disable
8161 11:52:24.475454 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8162 11:52:24.475525 == TX Byte 0 ==
8163 11:52:24.478698 u2DelayCellOfst[0]=10 cells (3 PI)
8164 11:52:24.482079 u2DelayCellOfst[1]=14 cells (4 PI)
8165 11:52:24.485350 u2DelayCellOfst[2]=7 cells (2 PI)
8166 11:52:24.488800 u2DelayCellOfst[3]=10 cells (3 PI)
8167 11:52:24.491889 u2DelayCellOfst[4]=7 cells (2 PI)
8168 11:52:24.494886 u2DelayCellOfst[5]=0 cells (0 PI)
8169 11:52:24.498614 u2DelayCellOfst[6]=14 cells (4 PI)
8170 11:52:24.501792 u2DelayCellOfst[7]=14 cells (4 PI)
8171 11:52:24.505096 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8172 11:52:24.508581 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8173 11:52:24.511857 == TX Byte 1 ==
8174 11:52:24.515195 u2DelayCellOfst[8]=0 cells (0 PI)
8175 11:52:24.518322 u2DelayCellOfst[9]=0 cells (0 PI)
8176 11:52:24.521616 u2DelayCellOfst[10]=3 cells (1 PI)
8177 11:52:24.521686 u2DelayCellOfst[11]=0 cells (0 PI)
8178 11:52:24.525066 u2DelayCellOfst[12]=10 cells (3 PI)
8179 11:52:24.528503 u2DelayCellOfst[13]=10 cells (3 PI)
8180 11:52:24.531915 u2DelayCellOfst[14]=14 cells (4 PI)
8181 11:52:24.534869 u2DelayCellOfst[15]=10 cells (3 PI)
8182 11:52:24.541568 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8183 11:52:24.545114 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8184 11:52:24.545192 DramC Write-DBI on
8185 11:52:24.548243 ==
8186 11:52:24.548313 Dram Type= 6, Freq= 0, CH_0, rank 1
8187 11:52:24.554490 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8188 11:52:24.554568 ==
8189 11:52:24.554630
8190 11:52:24.554688
8191 11:52:24.558311 TX Vref Scan disable
8192 11:52:24.558400 == TX Byte 0 ==
8193 11:52:24.564227 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8194 11:52:24.564304 == TX Byte 1 ==
8195 11:52:24.567653 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8196 11:52:24.570956 DramC Write-DBI off
8197 11:52:24.571028
8198 11:52:24.571088 [DATLAT]
8199 11:52:24.574216 Freq=1600, CH0 RK1
8200 11:52:24.574332
8201 11:52:24.574392 DATLAT Default: 0xf
8202 11:52:24.577403 0, 0xFFFF, sum = 0
8203 11:52:24.577474 1, 0xFFFF, sum = 0
8204 11:52:24.581280 2, 0xFFFF, sum = 0
8205 11:52:24.581348 3, 0xFFFF, sum = 0
8206 11:52:24.584226 4, 0xFFFF, sum = 0
8207 11:52:24.587399 5, 0xFFFF, sum = 0
8208 11:52:24.587471 6, 0xFFFF, sum = 0
8209 11:52:24.591013 7, 0xFFFF, sum = 0
8210 11:52:24.591094 8, 0xFFFF, sum = 0
8211 11:52:24.594031 9, 0xFFFF, sum = 0
8212 11:52:24.594135 10, 0xFFFF, sum = 0
8213 11:52:24.597756 11, 0xFFFF, sum = 0
8214 11:52:24.597849 12, 0xFFFF, sum = 0
8215 11:52:24.600854 13, 0xFFFF, sum = 0
8216 11:52:24.600954 14, 0x0, sum = 1
8217 11:52:24.604128 15, 0x0, sum = 2
8218 11:52:24.604236 16, 0x0, sum = 3
8219 11:52:24.606973 17, 0x0, sum = 4
8220 11:52:24.607096 best_step = 15
8221 11:52:24.607191
8222 11:52:24.607277 ==
8223 11:52:24.610263 Dram Type= 6, Freq= 0, CH_0, rank 1
8224 11:52:24.616823 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8225 11:52:24.616900 ==
8226 11:52:24.616972 RX Vref Scan: 0
8227 11:52:24.617031
8228 11:52:24.620412 RX Vref 0 -> 0, step: 1
8229 11:52:24.620497
8230 11:52:24.623300 RX Delay 11 -> 252, step: 4
8231 11:52:24.626998 iDelay=191, Bit 0, Center 126 (79 ~ 174) 96
8232 11:52:24.630394 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8233 11:52:24.633321 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8234 11:52:24.639867 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8235 11:52:24.642965 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8236 11:52:24.646566 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8237 11:52:24.650149 iDelay=191, Bit 6, Center 138 (91 ~ 186) 96
8238 11:52:24.653363 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8239 11:52:24.659815 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8240 11:52:24.663193 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8241 11:52:24.666234 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8242 11:52:24.669787 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8243 11:52:24.676123 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8244 11:52:24.679193 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8245 11:52:24.682658 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8246 11:52:24.685721 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8247 11:52:24.685804 ==
8248 11:52:24.689197 Dram Type= 6, Freq= 0, CH_0, rank 1
8249 11:52:24.695723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 11:52:24.695805 ==
8251 11:52:24.695871 DQS Delay:
8252 11:52:24.699544 DQS0 = 0, DQS1 = 0
8253 11:52:24.699626 DQM Delay:
8254 11:52:24.699691 DQM0 = 128, DQM1 = 124
8255 11:52:24.702555 DQ Delay:
8256 11:52:24.705703 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =126
8257 11:52:24.709091 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8258 11:52:24.712176 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8259 11:52:24.715628 DQ12 =128, DQ13 =130, DQ14 =136, DQ15 =132
8260 11:52:24.715709
8261 11:52:24.715774
8262 11:52:24.715834
8263 11:52:24.719030 [DramC_TX_OE_Calibration] TA2
8264 11:52:24.722399 Original DQ_B0 (3 6) =30, OEN = 27
8265 11:52:24.725040 Original DQ_B1 (3 6) =30, OEN = 27
8266 11:52:24.728373 24, 0x0, End_B0=24 End_B1=24
8267 11:52:24.731654 25, 0x0, End_B0=25 End_B1=25
8268 11:52:24.731737 26, 0x0, End_B0=26 End_B1=26
8269 11:52:24.735442 27, 0x0, End_B0=27 End_B1=27
8270 11:52:24.738330 28, 0x0, End_B0=28 End_B1=28
8271 11:52:24.741574 29, 0x0, End_B0=29 End_B1=29
8272 11:52:24.741656 30, 0x0, End_B0=30 End_B1=30
8273 11:52:24.745262 31, 0x4141, End_B0=30 End_B1=30
8274 11:52:24.748678 Byte0 end_step=30 best_step=27
8275 11:52:24.751510 Byte1 end_step=30 best_step=27
8276 11:52:24.755619 Byte0 TX OE(2T, 0.5T) = (3, 3)
8277 11:52:24.758243 Byte1 TX OE(2T, 0.5T) = (3, 3)
8278 11:52:24.758364
8279 11:52:24.758429
8280 11:52:24.764589 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8281 11:52:24.768186 CH0 RK1: MR19=303, MR18=1210
8282 11:52:24.774887 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8283 11:52:24.778378 [RxdqsGatingPostProcess] freq 1600
8284 11:52:24.784585 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8285 11:52:24.788002 best DQS0 dly(2T, 0.5T) = (1, 1)
8286 11:52:24.788083 best DQS1 dly(2T, 0.5T) = (1, 1)
8287 11:52:24.791470 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8288 11:52:24.794143 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8289 11:52:24.798073 best DQS0 dly(2T, 0.5T) = (1, 1)
8290 11:52:24.801412 best DQS1 dly(2T, 0.5T) = (1, 1)
8291 11:52:24.804513 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8292 11:52:24.807866 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8293 11:52:24.810631 Pre-setting of DQS Precalculation
8294 11:52:24.814270 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8295 11:52:24.817561 ==
8296 11:52:24.820559 Dram Type= 6, Freq= 0, CH_1, rank 0
8297 11:52:24.824247 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8298 11:52:24.824330 ==
8299 11:52:24.827584 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8300 11:52:24.834269 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8301 11:52:24.837213 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8302 11:52:24.843777 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8303 11:52:24.851852 [CA 0] Center 42 (12~72) winsize 61
8304 11:52:24.855076 [CA 1] Center 42 (12~72) winsize 61
8305 11:52:24.858535 [CA 2] Center 38 (9~67) winsize 59
8306 11:52:24.861691 [CA 3] Center 36 (7~66) winsize 60
8307 11:52:24.865400 [CA 4] Center 37 (8~67) winsize 60
8308 11:52:24.868536 [CA 5] Center 36 (7~66) winsize 60
8309 11:52:24.868611
8310 11:52:24.871923 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8311 11:52:24.872006
8312 11:52:24.878543 [CATrainingPosCal] consider 1 rank data
8313 11:52:24.878625 u2DelayCellTimex100 = 275/100 ps
8314 11:52:24.884961 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8315 11:52:24.888302 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8316 11:52:24.891232 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8317 11:52:24.894911 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8318 11:52:24.898279 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8319 11:52:24.901491 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8320 11:52:24.901572
8321 11:52:24.904966 CA PerBit enable=1, Macro0, CA PI delay=36
8322 11:52:24.905047
8323 11:52:24.908562 [CBTSetCACLKResult] CA Dly = 36
8324 11:52:24.911691 CS Dly: 8 (0~39)
8325 11:52:24.914283 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8326 11:52:24.918025 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8327 11:52:24.918106 ==
8328 11:52:24.921347 Dram Type= 6, Freq= 0, CH_1, rank 1
8329 11:52:24.927875 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 11:52:24.927957 ==
8331 11:52:24.931111 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8332 11:52:24.937551 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8333 11:52:24.940753 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8334 11:52:24.947321 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8335 11:52:24.955250 [CA 0] Center 41 (11~71) winsize 61
8336 11:52:24.958784 [CA 1] Center 41 (12~71) winsize 60
8337 11:52:24.961978 [CA 2] Center 37 (8~67) winsize 60
8338 11:52:24.965234 [CA 3] Center 36 (6~66) winsize 61
8339 11:52:24.968302 [CA 4] Center 37 (7~67) winsize 61
8340 11:52:24.971588 [CA 5] Center 36 (7~66) winsize 60
8341 11:52:24.971670
8342 11:52:24.975536 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8343 11:52:24.975608
8344 11:52:24.978417 [CATrainingPosCal] consider 2 rank data
8345 11:52:24.981738 u2DelayCellTimex100 = 275/100 ps
8346 11:52:24.988700 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8347 11:52:24.991842 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8348 11:52:24.994713 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8349 11:52:24.998101 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8350 11:52:25.001442 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8351 11:52:25.004424 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8352 11:52:25.004495
8353 11:52:25.008163 CA PerBit enable=1, Macro0, CA PI delay=36
8354 11:52:25.008234
8355 11:52:25.011865 [CBTSetCACLKResult] CA Dly = 36
8356 11:52:25.014946 CS Dly: 9 (0~42)
8357 11:52:25.017997 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8358 11:52:25.021110 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8359 11:52:25.021181
8360 11:52:25.025002 ----->DramcWriteLeveling(PI) begin...
8361 11:52:25.025078 ==
8362 11:52:25.027764 Dram Type= 6, Freq= 0, CH_1, rank 0
8363 11:52:25.034567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8364 11:52:25.034648 ==
8365 11:52:25.037895 Write leveling (Byte 0): 27 => 27
8366 11:52:25.041169 Write leveling (Byte 1): 27 => 27
8367 11:52:25.041250 DramcWriteLeveling(PI) end<-----
8368 11:52:25.043987
8369 11:52:25.044093 ==
8370 11:52:25.047500 Dram Type= 6, Freq= 0, CH_1, rank 0
8371 11:52:25.050970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8372 11:52:25.051051 ==
8373 11:52:25.053959 [Gating] SW mode calibration
8374 11:52:25.060406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8375 11:52:25.064354 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8376 11:52:25.070717 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 11:52:25.073651 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 11:52:25.077053 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:52:25.083838 1 4 12 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
8380 11:52:25.087085 1 4 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8381 11:52:25.090135 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8382 11:52:25.097153 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8383 11:52:25.100150 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8384 11:52:25.103893 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8385 11:52:25.109999 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8386 11:52:25.113208 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8387 11:52:25.116733 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 0) (1 0)
8388 11:52:25.123056 1 5 16 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8389 11:52:25.126466 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8390 11:52:25.129838 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8391 11:52:25.136208 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8392 11:52:25.139963 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8393 11:52:25.146089 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8394 11:52:25.149498 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8395 11:52:25.152934 1 6 12 | B1->B0 | 2b2b 4545 | 0 0 | (0 0) (0 0)
8396 11:52:25.159772 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8397 11:52:25.162410 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8398 11:52:25.166093 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8399 11:52:25.172498 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8400 11:52:25.175544 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8401 11:52:25.178729 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8402 11:52:25.185594 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8403 11:52:25.188899 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8404 11:52:25.192159 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8405 11:52:25.198734 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8406 11:52:25.201736 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8407 11:52:25.205062 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8408 11:52:25.212277 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8409 11:52:25.215122 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8410 11:52:25.218303 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 11:52:25.224860 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 11:52:25.227837 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 11:52:25.231669 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 11:52:25.238155 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 11:52:25.241523 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 11:52:25.244272 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 11:52:25.250962 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 11:52:25.254509 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:52:25.257551 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8420 11:52:25.264182 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8421 11:52:25.264265 Total UI for P1: 0, mck2ui 16
8422 11:52:25.270923 best dqsien dly found for B0: ( 1, 9, 12)
8423 11:52:25.274568 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 11:52:25.277110 Total UI for P1: 0, mck2ui 16
8425 11:52:25.281124 best dqsien dly found for B1: ( 1, 9, 16)
8426 11:52:25.284089 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8427 11:52:25.287657 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8428 11:52:25.287739
8429 11:52:25.291170 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8430 11:52:25.293871 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8431 11:52:25.297387 [Gating] SW calibration Done
8432 11:52:25.297468 ==
8433 11:52:25.300612 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 11:52:25.307284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 11:52:25.307378 ==
8436 11:52:25.307448 RX Vref Scan: 0
8437 11:52:25.307513
8438 11:52:25.310269 RX Vref 0 -> 0, step: 1
8439 11:52:25.310371
8440 11:52:25.314365 RX Delay 0 -> 252, step: 8
8441 11:52:25.317131 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8442 11:52:25.320191 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8443 11:52:25.323458 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8444 11:52:25.327434 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8445 11:52:25.333293 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8446 11:52:25.336576 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8447 11:52:25.340211 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8448 11:52:25.343358 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8449 11:52:25.346830 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8450 11:52:25.353631 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8451 11:52:25.356608 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8452 11:52:25.360244 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8453 11:52:25.363135 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8454 11:52:25.369759 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8455 11:52:25.373060 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8456 11:52:25.376073 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8457 11:52:25.376155 ==
8458 11:52:25.379385 Dram Type= 6, Freq= 0, CH_1, rank 0
8459 11:52:25.382717 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8460 11:52:25.385872 ==
8461 11:52:25.385976 DQS Delay:
8462 11:52:25.386067 DQS0 = 0, DQS1 = 0
8463 11:52:25.389271 DQM Delay:
8464 11:52:25.389347 DQM0 = 135, DQM1 = 129
8465 11:52:25.393077 DQ Delay:
8466 11:52:25.396371 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8467 11:52:25.399519 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8468 11:52:25.402698 DQ8 =115, DQ9 =119, DQ10 =127, DQ11 =123
8469 11:52:25.406124 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8470 11:52:25.406242
8471 11:52:25.406326
8472 11:52:25.406395 ==
8473 11:52:25.409252 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 11:52:25.412646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 11:52:25.412738 ==
8476 11:52:25.416608
8477 11:52:25.416711
8478 11:52:25.416793 TX Vref Scan disable
8479 11:52:25.419013 == TX Byte 0 ==
8480 11:52:25.422520 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8481 11:52:25.426242 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8482 11:52:25.429763 == TX Byte 1 ==
8483 11:52:25.432444 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8484 11:52:25.436591 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8485 11:52:25.437115 ==
8486 11:52:25.439413 Dram Type= 6, Freq= 0, CH_1, rank 0
8487 11:52:25.446045 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8488 11:52:25.446634 ==
8489 11:52:25.457895
8490 11:52:25.461066 TX Vref early break, caculate TX vref
8491 11:52:25.464231 TX Vref=16, minBit 8, minWin=21, winSum=369
8492 11:52:25.467687 TX Vref=18, minBit 8, minWin=22, winSum=377
8493 11:52:25.470830 TX Vref=20, minBit 6, minWin=23, winSum=387
8494 11:52:25.474758 TX Vref=22, minBit 8, minWin=23, winSum=397
8495 11:52:25.477444 TX Vref=24, minBit 8, minWin=24, winSum=406
8496 11:52:25.484145 TX Vref=26, minBit 5, minWin=25, winSum=417
8497 11:52:25.486990 TX Vref=28, minBit 11, minWin=25, winSum=419
8498 11:52:25.490378 TX Vref=30, minBit 10, minWin=24, winSum=415
8499 11:52:25.493725 TX Vref=32, minBit 9, minWin=24, winSum=406
8500 11:52:25.496809 TX Vref=34, minBit 0, minWin=24, winSum=397
8501 11:52:25.503625 [TxChooseVref] Worse bit 11, Min win 25, Win sum 419, Final Vref 28
8502 11:52:25.504109
8503 11:52:25.507153 Final TX Range 0 Vref 28
8504 11:52:25.507608
8505 11:52:25.507950 ==
8506 11:52:25.510193 Dram Type= 6, Freq= 0, CH_1, rank 0
8507 11:52:25.513986 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8508 11:52:25.514475 ==
8509 11:52:25.514828
8510 11:52:25.516738
8511 11:52:25.517211 TX Vref Scan disable
8512 11:52:25.523588 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8513 11:52:25.524060 == TX Byte 0 ==
8514 11:52:25.527136 u2DelayCellOfst[0]=14 cells (4 PI)
8515 11:52:25.529828 u2DelayCellOfst[1]=10 cells (3 PI)
8516 11:52:25.533080 u2DelayCellOfst[2]=0 cells (0 PI)
8517 11:52:25.536447 u2DelayCellOfst[3]=7 cells (2 PI)
8518 11:52:25.540094 u2DelayCellOfst[4]=10 cells (3 PI)
8519 11:52:25.543326 u2DelayCellOfst[5]=17 cells (5 PI)
8520 11:52:25.546696 u2DelayCellOfst[6]=17 cells (5 PI)
8521 11:52:25.549890 u2DelayCellOfst[7]=7 cells (2 PI)
8522 11:52:25.553706 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8523 11:52:25.556076 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8524 11:52:25.559419 == TX Byte 1 ==
8525 11:52:25.562885 u2DelayCellOfst[8]=0 cells (0 PI)
8526 11:52:25.566185 u2DelayCellOfst[9]=3 cells (1 PI)
8527 11:52:25.569201 u2DelayCellOfst[10]=10 cells (3 PI)
8528 11:52:25.573011 u2DelayCellOfst[11]=7 cells (2 PI)
8529 11:52:25.573426 u2DelayCellOfst[12]=14 cells (4 PI)
8530 11:52:25.576412 u2DelayCellOfst[13]=17 cells (5 PI)
8531 11:52:25.579314 u2DelayCellOfst[14]=17 cells (5 PI)
8532 11:52:25.583351 u2DelayCellOfst[15]=17 cells (5 PI)
8533 11:52:25.589285 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8534 11:52:25.592221 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8535 11:52:25.595860 DramC Write-DBI on
8536 11:52:25.596298 ==
8537 11:52:25.599271 Dram Type= 6, Freq= 0, CH_1, rank 0
8538 11:52:25.602354 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8539 11:52:25.602802 ==
8540 11:52:25.603163
8541 11:52:25.603475
8542 11:52:25.605807 TX Vref Scan disable
8543 11:52:25.606220 == TX Byte 0 ==
8544 11:52:25.612252 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8545 11:52:25.612768 == TX Byte 1 ==
8546 11:52:25.615300 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8547 11:52:25.619185 DramC Write-DBI off
8548 11:52:25.619624
8549 11:52:25.619959 [DATLAT]
8550 11:52:25.622042 Freq=1600, CH1 RK0
8551 11:52:25.622515
8552 11:52:25.622871 DATLAT Default: 0xf
8553 11:52:25.625323 0, 0xFFFF, sum = 0
8554 11:52:25.625777 1, 0xFFFF, sum = 0
8555 11:52:25.628721 2, 0xFFFF, sum = 0
8556 11:52:25.629165 3, 0xFFFF, sum = 0
8557 11:52:25.632213 4, 0xFFFF, sum = 0
8558 11:52:25.635509 5, 0xFFFF, sum = 0
8559 11:52:25.635964 6, 0xFFFF, sum = 0
8560 11:52:25.639084 7, 0xFFFF, sum = 0
8561 11:52:25.639524 8, 0xFFFF, sum = 0
8562 11:52:25.641738 9, 0xFFFF, sum = 0
8563 11:52:25.642183 10, 0xFFFF, sum = 0
8564 11:52:25.644975 11, 0xFFFF, sum = 0
8565 11:52:25.645421 12, 0xFFFF, sum = 0
8566 11:52:25.648995 13, 0xFFFF, sum = 0
8567 11:52:25.649434 14, 0x0, sum = 1
8568 11:52:25.651704 15, 0x0, sum = 2
8569 11:52:25.652158 16, 0x0, sum = 3
8570 11:52:25.655200 17, 0x0, sum = 4
8571 11:52:25.655650 best_step = 15
8572 11:52:25.656017
8573 11:52:25.656344 ==
8574 11:52:25.658350 Dram Type= 6, Freq= 0, CH_1, rank 0
8575 11:52:25.665249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8576 11:52:25.665668 ==
8577 11:52:25.666029 RX Vref Scan: 1
8578 11:52:25.666420
8579 11:52:25.668122 Set Vref Range= 24 -> 127
8580 11:52:25.668566
8581 11:52:25.671805 RX Vref 24 -> 127, step: 1
8582 11:52:25.672250
8583 11:52:25.672595 RX Delay 19 -> 252, step: 4
8584 11:52:25.672906
8585 11:52:25.674931 Set Vref, RX VrefLevel [Byte0]: 24
8586 11:52:25.677881 [Byte1]: 24
8587 11:52:25.682221
8588 11:52:25.682680 Set Vref, RX VrefLevel [Byte0]: 25
8589 11:52:25.686092 [Byte1]: 25
8590 11:52:25.689747
8591 11:52:25.690157 Set Vref, RX VrefLevel [Byte0]: 26
8592 11:52:25.692959 [Byte1]: 26
8593 11:52:25.697124
8594 11:52:25.697556 Set Vref, RX VrefLevel [Byte0]: 27
8595 11:52:25.700309 [Byte1]: 27
8596 11:52:25.704616
8597 11:52:25.705026 Set Vref, RX VrefLevel [Byte0]: 28
8598 11:52:25.707709 [Byte1]: 28
8599 11:52:25.711961
8600 11:52:25.712041 Set Vref, RX VrefLevel [Byte0]: 29
8601 11:52:25.715204 [Byte1]: 29
8602 11:52:25.719783
8603 11:52:25.719863 Set Vref, RX VrefLevel [Byte0]: 30
8604 11:52:25.723029 [Byte1]: 30
8605 11:52:25.727425
8606 11:52:25.727496 Set Vref, RX VrefLevel [Byte0]: 31
8607 11:52:25.730467 [Byte1]: 31
8608 11:52:25.735065
8609 11:52:25.735136 Set Vref, RX VrefLevel [Byte0]: 32
8610 11:52:25.738526 [Byte1]: 32
8611 11:52:25.742413
8612 11:52:25.742484 Set Vref, RX VrefLevel [Byte0]: 33
8613 11:52:25.745479 [Byte1]: 33
8614 11:52:25.749935
8615 11:52:25.750062 Set Vref, RX VrefLevel [Byte0]: 34
8616 11:52:25.753250 [Byte1]: 34
8617 11:52:25.757565
8618 11:52:25.757650 Set Vref, RX VrefLevel [Byte0]: 35
8619 11:52:25.760452 [Byte1]: 35
8620 11:52:25.764771
8621 11:52:25.764839 Set Vref, RX VrefLevel [Byte0]: 36
8622 11:52:25.768542 [Byte1]: 36
8623 11:52:25.772513
8624 11:52:25.772582 Set Vref, RX VrefLevel [Byte0]: 37
8625 11:52:25.775928 [Byte1]: 37
8626 11:52:25.780200
8627 11:52:25.780273 Set Vref, RX VrefLevel [Byte0]: 38
8628 11:52:25.783844 [Byte1]: 38
8629 11:52:25.788101
8630 11:52:25.788170 Set Vref, RX VrefLevel [Byte0]: 39
8631 11:52:25.791470 [Byte1]: 39
8632 11:52:25.795328
8633 11:52:25.795404 Set Vref, RX VrefLevel [Byte0]: 40
8634 11:52:25.798785 [Byte1]: 40
8635 11:52:25.802729
8636 11:52:25.802798 Set Vref, RX VrefLevel [Byte0]: 41
8637 11:52:25.805976 [Byte1]: 41
8638 11:52:25.810377
8639 11:52:25.810444 Set Vref, RX VrefLevel [Byte0]: 42
8640 11:52:25.813886 [Byte1]: 42
8641 11:52:25.817911
8642 11:52:25.817979 Set Vref, RX VrefLevel [Byte0]: 43
8643 11:52:25.821457 [Byte1]: 43
8644 11:52:25.825797
8645 11:52:25.825866 Set Vref, RX VrefLevel [Byte0]: 44
8646 11:52:25.828867 [Byte1]: 44
8647 11:52:25.833538
8648 11:52:25.833613 Set Vref, RX VrefLevel [Byte0]: 45
8649 11:52:25.836839 [Byte1]: 45
8650 11:52:25.840956
8651 11:52:25.841025 Set Vref, RX VrefLevel [Byte0]: 46
8652 11:52:25.844220 [Byte1]: 46
8653 11:52:25.848329
8654 11:52:25.848406 Set Vref, RX VrefLevel [Byte0]: 47
8655 11:52:25.851451 [Byte1]: 47
8656 11:52:25.855791
8657 11:52:25.855865 Set Vref, RX VrefLevel [Byte0]: 48
8658 11:52:25.859239 [Byte1]: 48
8659 11:52:25.863713
8660 11:52:25.863785 Set Vref, RX VrefLevel [Byte0]: 49
8661 11:52:25.866742 [Byte1]: 49
8662 11:52:25.871155
8663 11:52:25.871255 Set Vref, RX VrefLevel [Byte0]: 50
8664 11:52:25.874479 [Byte1]: 50
8665 11:52:25.878709
8666 11:52:25.878778 Set Vref, RX VrefLevel [Byte0]: 51
8667 11:52:25.882011 [Byte1]: 51
8668 11:52:25.885916
8669 11:52:25.885987 Set Vref, RX VrefLevel [Byte0]: 52
8670 11:52:25.889529 [Byte1]: 52
8671 11:52:25.893488
8672 11:52:25.893557 Set Vref, RX VrefLevel [Byte0]: 53
8673 11:52:25.897177 [Byte1]: 53
8674 11:52:25.901687
8675 11:52:25.901755 Set Vref, RX VrefLevel [Byte0]: 54
8676 11:52:25.904443 [Byte1]: 54
8677 11:52:25.908994
8678 11:52:25.909064 Set Vref, RX VrefLevel [Byte0]: 55
8679 11:52:25.912272 [Byte1]: 55
8680 11:52:25.916495
8681 11:52:25.916564 Set Vref, RX VrefLevel [Byte0]: 56
8682 11:52:25.919841 [Byte1]: 56
8683 11:52:25.924225
8684 11:52:25.924293 Set Vref, RX VrefLevel [Byte0]: 57
8685 11:52:25.927173 [Byte1]: 57
8686 11:52:25.931604
8687 11:52:25.931685 Set Vref, RX VrefLevel [Byte0]: 58
8688 11:52:25.934772 [Byte1]: 58
8689 11:52:25.939153
8690 11:52:25.939233 Set Vref, RX VrefLevel [Byte0]: 59
8691 11:52:25.942432 [Byte1]: 59
8692 11:52:25.946992
8693 11:52:25.947073 Set Vref, RX VrefLevel [Byte0]: 60
8694 11:52:25.950189 [Byte1]: 60
8695 11:52:25.954461
8696 11:52:25.954542 Set Vref, RX VrefLevel [Byte0]: 61
8697 11:52:25.958078 [Byte1]: 61
8698 11:52:25.962018
8699 11:52:25.962099 Set Vref, RX VrefLevel [Byte0]: 62
8700 11:52:25.965434 [Byte1]: 62
8701 11:52:25.969336
8702 11:52:25.969417 Set Vref, RX VrefLevel [Byte0]: 63
8703 11:52:25.972857 [Byte1]: 63
8704 11:52:25.977510
8705 11:52:25.977590 Set Vref, RX VrefLevel [Byte0]: 64
8706 11:52:25.980634 [Byte1]: 64
8707 11:52:25.984474
8708 11:52:25.984555 Set Vref, RX VrefLevel [Byte0]: 65
8709 11:52:25.987728 [Byte1]: 65
8710 11:52:25.992460
8711 11:52:25.992540 Set Vref, RX VrefLevel [Byte0]: 66
8712 11:52:25.995618 [Byte1]: 66
8713 11:52:25.999696
8714 11:52:25.999777 Set Vref, RX VrefLevel [Byte0]: 67
8715 11:52:26.002952 [Byte1]: 67
8716 11:52:26.007298
8717 11:52:26.007379 Set Vref, RX VrefLevel [Byte0]: 68
8718 11:52:26.010571 [Byte1]: 68
8719 11:52:26.014842
8720 11:52:26.014923 Set Vref, RX VrefLevel [Byte0]: 69
8721 11:52:26.018369 [Byte1]: 69
8722 11:52:26.023347
8723 11:52:26.023428 Set Vref, RX VrefLevel [Byte0]: 70
8724 11:52:26.026392 [Byte1]: 70
8725 11:52:26.030151
8726 11:52:26.030232 Set Vref, RX VrefLevel [Byte0]: 71
8727 11:52:26.033599 [Byte1]: 71
8728 11:52:26.037676
8729 11:52:26.037757 Set Vref, RX VrefLevel [Byte0]: 72
8730 11:52:26.040933 [Byte1]: 72
8731 11:52:26.045491
8732 11:52:26.045572 Set Vref, RX VrefLevel [Byte0]: 73
8733 11:52:26.048631 [Byte1]: 73
8734 11:52:26.052642
8735 11:52:26.052723 Final RX Vref Byte 0 = 56 to rank0
8736 11:52:26.056080 Final RX Vref Byte 1 = 55 to rank0
8737 11:52:26.059530 Final RX Vref Byte 0 = 56 to rank1
8738 11:52:26.063044 Final RX Vref Byte 1 = 55 to rank1==
8739 11:52:26.066119 Dram Type= 6, Freq= 0, CH_1, rank 0
8740 11:52:26.073011 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8741 11:52:26.073094 ==
8742 11:52:26.073161 DQS Delay:
8743 11:52:26.076343 DQS0 = 0, DQS1 = 0
8744 11:52:26.076425 DQM Delay:
8745 11:52:26.076490 DQM0 = 133, DQM1 = 128
8746 11:52:26.078948 DQ Delay:
8747 11:52:26.082777 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =130
8748 11:52:26.085737 DQ4 =128, DQ5 =144, DQ6 =146, DQ7 =126
8749 11:52:26.088839 DQ8 =112, DQ9 =116, DQ10 =130, DQ11 =122
8750 11:52:26.092601 DQ12 =138, DQ13 =136, DQ14 =136, DQ15 =138
8751 11:52:26.092682
8752 11:52:26.092746
8753 11:52:26.092807
8754 11:52:26.095776 [DramC_TX_OE_Calibration] TA2
8755 11:52:26.098900 Original DQ_B0 (3 6) =30, OEN = 27
8756 11:52:26.102543 Original DQ_B1 (3 6) =30, OEN = 27
8757 11:52:26.105392 24, 0x0, End_B0=24 End_B1=24
8758 11:52:26.105505 25, 0x0, End_B0=25 End_B1=25
8759 11:52:26.109277 26, 0x0, End_B0=26 End_B1=26
8760 11:52:26.111935 27, 0x0, End_B0=27 End_B1=27
8761 11:52:26.115670 28, 0x0, End_B0=28 End_B1=28
8762 11:52:26.118667 29, 0x0, End_B0=29 End_B1=29
8763 11:52:26.118746 30, 0x0, End_B0=30 End_B1=30
8764 11:52:26.122113 31, 0x4545, End_B0=30 End_B1=30
8765 11:52:26.125426 Byte0 end_step=30 best_step=27
8766 11:52:26.128750 Byte1 end_step=30 best_step=27
8767 11:52:26.132170 Byte0 TX OE(2T, 0.5T) = (3, 3)
8768 11:52:26.135675 Byte1 TX OE(2T, 0.5T) = (3, 3)
8769 11:52:26.135746
8770 11:52:26.135806
8771 11:52:26.141612 [DQSOSCAuto] RK0, (LSB)MR18= 0xf19, (MSB)MR19= 0x303, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
8772 11:52:26.145364 CH1 RK0: MR19=303, MR18=F19
8773 11:52:26.151376 CH1_RK0: MR19=0x303, MR18=0xF19, DQSOSC=397, MR23=63, INC=23, DEC=15
8774 11:52:26.151454
8775 11:52:26.155030 ----->DramcWriteLeveling(PI) begin...
8776 11:52:26.155101 ==
8777 11:52:26.158111 Dram Type= 6, Freq= 0, CH_1, rank 1
8778 11:52:26.161309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8779 11:52:26.161383 ==
8780 11:52:26.164646 Write leveling (Byte 0): 25 => 25
8781 11:52:26.168052 Write leveling (Byte 1): 25 => 25
8782 11:52:26.171276 DramcWriteLeveling(PI) end<-----
8783 11:52:26.171345
8784 11:52:26.171404 ==
8785 11:52:26.174993 Dram Type= 6, Freq= 0, CH_1, rank 1
8786 11:52:26.178304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 11:52:26.181715 ==
8788 11:52:26.181785 [Gating] SW mode calibration
8789 11:52:26.191191 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8790 11:52:26.195224 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8791 11:52:26.197776 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 11:52:26.204303 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 11:52:26.207903 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8794 11:52:26.210746 1 4 12 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
8795 11:52:26.217887 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8796 11:52:26.221610 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8797 11:52:26.224363 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8798 11:52:26.230628 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8799 11:52:26.234278 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8800 11:52:26.237603 1 5 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8801 11:52:26.243888 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8802 11:52:26.247545 1 5 12 | B1->B0 | 2e2e 2323 | 0 0 | (0 1) (1 0)
8803 11:52:26.250502 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8804 11:52:26.256887 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8805 11:52:26.260818 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8806 11:52:26.264066 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8807 11:52:26.270187 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8808 11:52:26.273781 1 6 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8809 11:52:26.276656 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8810 11:52:26.283433 1 6 12 | B1->B0 | 2e2e 4646 | 0 0 | (0 0) (0 0)
8811 11:52:26.286775 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8812 11:52:26.290008 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8813 11:52:26.296635 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8814 11:52:26.299806 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8815 11:52:26.303144 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8816 11:52:26.310053 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8817 11:52:26.312931 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8818 11:52:26.316501 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8819 11:52:26.324028 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8820 11:52:26.326179 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8821 11:52:26.329827 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8822 11:52:26.336097 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8823 11:52:26.339113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8824 11:52:26.342431 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8825 11:52:26.348793 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8826 11:52:26.352215 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8827 11:52:26.355615 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8828 11:52:26.362133 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8829 11:52:26.365696 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8830 11:52:26.372715 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8831 11:52:26.375520 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8832 11:52:26.378578 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8833 11:52:26.385166 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8834 11:52:26.388512 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8835 11:52:26.392039 Total UI for P1: 0, mck2ui 16
8836 11:52:26.394897 best dqsien dly found for B0: ( 1, 9, 8)
8837 11:52:26.398463 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8838 11:52:26.401682 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8839 11:52:26.404712 Total UI for P1: 0, mck2ui 16
8840 11:52:26.408409 best dqsien dly found for B1: ( 1, 9, 14)
8841 11:52:26.415309 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8842 11:52:26.418194 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8843 11:52:26.418316
8844 11:52:26.421331 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8845 11:52:26.425008 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8846 11:52:26.427758 [Gating] SW calibration Done
8847 11:52:26.427869 ==
8848 11:52:26.431346 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 11:52:26.434957 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 11:52:26.435093 ==
8851 11:52:26.437745 RX Vref Scan: 0
8852 11:52:26.437882
8853 11:52:26.438004 RX Vref 0 -> 0, step: 1
8854 11:52:26.438266
8855 11:52:26.441025 RX Delay 0 -> 252, step: 8
8856 11:52:26.444405 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8857 11:52:26.451145 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8858 11:52:26.454765 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8859 11:52:26.458051 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8860 11:52:26.461184 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8861 11:52:26.464426 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8862 11:52:26.471150 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8863 11:52:26.473833 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8864 11:52:26.477483 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8865 11:52:26.480536 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8866 11:52:26.483774 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8867 11:52:26.491002 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8868 11:52:26.493739 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8869 11:52:26.497258 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8870 11:52:26.500649 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8871 11:52:26.507809 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8872 11:52:26.508231 ==
8873 11:52:26.510477 Dram Type= 6, Freq= 0, CH_1, rank 1
8874 11:52:26.514029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8875 11:52:26.514423 ==
8876 11:52:26.514758 DQS Delay:
8877 11:52:26.517052 DQS0 = 0, DQS1 = 0
8878 11:52:26.517485 DQM Delay:
8879 11:52:26.520437 DQM0 = 133, DQM1 = 130
8880 11:52:26.520877 DQ Delay:
8881 11:52:26.523603 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8882 11:52:26.526946 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8883 11:52:26.530529 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8884 11:52:26.533650 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8885 11:52:26.534139
8886 11:52:26.536743
8887 11:52:26.537179 ==
8888 11:52:26.540207 Dram Type= 6, Freq= 0, CH_1, rank 1
8889 11:52:26.543360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8890 11:52:26.543782 ==
8891 11:52:26.544144
8892 11:52:26.544451
8893 11:52:26.546831 TX Vref Scan disable
8894 11:52:26.547248 == TX Byte 0 ==
8895 11:52:26.553497 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8896 11:52:26.556605 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8897 11:52:26.557101 == TX Byte 1 ==
8898 11:52:26.563651 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8899 11:52:26.566910 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8900 11:52:26.567328 ==
8901 11:52:26.570054 Dram Type= 6, Freq= 0, CH_1, rank 1
8902 11:52:26.573545 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8903 11:52:26.573990 ==
8904 11:52:26.587469
8905 11:52:26.590740 TX Vref early break, caculate TX vref
8906 11:52:26.594232 TX Vref=16, minBit 9, minWin=22, winSum=377
8907 11:52:26.597474 TX Vref=18, minBit 9, minWin=21, winSum=386
8908 11:52:26.600770 TX Vref=20, minBit 1, minWin=24, winSum=395
8909 11:52:26.604151 TX Vref=22, minBit 9, minWin=24, winSum=405
8910 11:52:26.607582 TX Vref=24, minBit 1, minWin=25, winSum=411
8911 11:52:26.613807 TX Vref=26, minBit 9, minWin=24, winSum=418
8912 11:52:26.616959 TX Vref=28, minBit 9, minWin=25, winSum=424
8913 11:52:26.620439 TX Vref=30, minBit 0, minWin=26, winSum=423
8914 11:52:26.623556 TX Vref=32, minBit 9, minWin=24, winSum=418
8915 11:52:26.627161 TX Vref=34, minBit 9, minWin=24, winSum=408
8916 11:52:26.633300 TX Vref=36, minBit 9, minWin=22, winSum=396
8917 11:52:26.636766 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
8918 11:52:26.637193
8919 11:52:26.639948 Final TX Range 0 Vref 30
8920 11:52:26.640370
8921 11:52:26.640757 ==
8922 11:52:26.643321 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 11:52:26.646972 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 11:52:26.649792 ==
8925 11:52:26.650213
8926 11:52:26.650605
8927 11:52:26.650921 TX Vref Scan disable
8928 11:52:26.656539 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8929 11:52:26.656959 == TX Byte 0 ==
8930 11:52:26.659934 u2DelayCellOfst[0]=17 cells (5 PI)
8931 11:52:26.663726 u2DelayCellOfst[1]=10 cells (3 PI)
8932 11:52:26.666731 u2DelayCellOfst[2]=0 cells (0 PI)
8933 11:52:26.669894 u2DelayCellOfst[3]=7 cells (2 PI)
8934 11:52:26.673124 u2DelayCellOfst[4]=7 cells (2 PI)
8935 11:52:26.676378 u2DelayCellOfst[5]=14 cells (4 PI)
8936 11:52:26.679765 u2DelayCellOfst[6]=14 cells (4 PI)
8937 11:52:26.683209 u2DelayCellOfst[7]=7 cells (2 PI)
8938 11:52:26.686127 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8939 11:52:26.689579 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8940 11:52:26.693012 == TX Byte 1 ==
8941 11:52:26.696328 u2DelayCellOfst[8]=0 cells (0 PI)
8942 11:52:26.699675 u2DelayCellOfst[9]=0 cells (0 PI)
8943 11:52:26.702747 u2DelayCellOfst[10]=10 cells (3 PI)
8944 11:52:26.706101 u2DelayCellOfst[11]=7 cells (2 PI)
8945 11:52:26.709248 u2DelayCellOfst[12]=14 cells (4 PI)
8946 11:52:26.712916 u2DelayCellOfst[13]=14 cells (4 PI)
8947 11:52:26.715860 u2DelayCellOfst[14]=17 cells (5 PI)
8948 11:52:26.716279 u2DelayCellOfst[15]=17 cells (5 PI)
8949 11:52:26.722381 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8950 11:52:26.725682 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8951 11:52:26.729115 DramC Write-DBI on
8952 11:52:26.729533 ==
8953 11:52:26.732453 Dram Type= 6, Freq= 0, CH_1, rank 1
8954 11:52:26.735778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8955 11:52:26.736215 ==
8956 11:52:26.736555
8957 11:52:26.736868
8958 11:52:26.738621 TX Vref Scan disable
8959 11:52:26.739102 == TX Byte 0 ==
8960 11:52:26.745711 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8961 11:52:26.746134 == TX Byte 1 ==
8962 11:52:26.752091 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8963 11:52:26.752547 DramC Write-DBI off
8964 11:52:26.752906
8965 11:52:26.753221 [DATLAT]
8966 11:52:26.755270 Freq=1600, CH1 RK1
8967 11:52:26.755641
8968 11:52:26.755951 DATLAT Default: 0xf
8969 11:52:26.758736 0, 0xFFFF, sum = 0
8970 11:52:26.762499 1, 0xFFFF, sum = 0
8971 11:52:26.762941 2, 0xFFFF, sum = 0
8972 11:52:26.765634 3, 0xFFFF, sum = 0
8973 11:52:26.766063 4, 0xFFFF, sum = 0
8974 11:52:26.768684 5, 0xFFFF, sum = 0
8975 11:52:26.769123 6, 0xFFFF, sum = 0
8976 11:52:26.771955 7, 0xFFFF, sum = 0
8977 11:52:26.772379 8, 0xFFFF, sum = 0
8978 11:52:26.775272 9, 0xFFFF, sum = 0
8979 11:52:26.775698 10, 0xFFFF, sum = 0
8980 11:52:26.778663 11, 0xFFFF, sum = 0
8981 11:52:26.779106 12, 0xFFFF, sum = 0
8982 11:52:26.781909 13, 0xFFFF, sum = 0
8983 11:52:26.782399 14, 0x0, sum = 1
8984 11:52:26.785194 15, 0x0, sum = 2
8985 11:52:26.785617 16, 0x0, sum = 3
8986 11:52:26.788489 17, 0x0, sum = 4
8987 11:52:26.788915 best_step = 15
8988 11:52:26.789256
8989 11:52:26.789567 ==
8990 11:52:26.791624 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 11:52:26.798349 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 11:52:26.798775 ==
8993 11:52:26.799111 RX Vref Scan: 0
8994 11:52:26.799427
8995 11:52:26.801650 RX Vref 0 -> 0, step: 1
8996 11:52:26.802067
8997 11:52:26.804802 RX Delay 19 -> 252, step: 4
8998 11:52:26.808187 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8999 11:52:26.811592 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9000 11:52:26.818308 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
9001 11:52:26.820927 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
9002 11:52:26.824352 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
9003 11:52:26.827776 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
9004 11:52:26.831307 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9005 11:52:26.837822 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
9006 11:52:26.840783 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
9007 11:52:26.844105 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9008 11:52:26.847544 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9009 11:52:26.851311 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9010 11:52:26.857291 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
9011 11:52:26.860780 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
9012 11:52:26.863995 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
9013 11:52:26.867332 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9014 11:52:26.867775 ==
9015 11:52:26.870538 Dram Type= 6, Freq= 0, CH_1, rank 1
9016 11:52:26.877134 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9017 11:52:26.877556 ==
9018 11:52:26.878089 DQS Delay:
9019 11:52:26.881119 DQS0 = 0, DQS1 = 0
9020 11:52:26.881541 DQM Delay:
9021 11:52:26.883994 DQM0 = 131, DQM1 = 128
9022 11:52:26.884411 DQ Delay:
9023 11:52:26.886992 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
9024 11:52:26.890178 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =128
9025 11:52:26.893761 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
9026 11:52:26.896827 DQ12 =138, DQ13 =134, DQ14 =134, DQ15 =138
9027 11:52:26.897248
9028 11:52:26.897583
9029 11:52:26.897894
9030 11:52:26.900303 [DramC_TX_OE_Calibration] TA2
9031 11:52:26.903571 Original DQ_B0 (3 6) =30, OEN = 27
9032 11:52:26.906718 Original DQ_B1 (3 6) =30, OEN = 27
9033 11:52:26.909882 24, 0x0, End_B0=24 End_B1=24
9034 11:52:26.913166 25, 0x0, End_B0=25 End_B1=25
9035 11:52:26.913639 26, 0x0, End_B0=26 End_B1=26
9036 11:52:26.916502 27, 0x0, End_B0=27 End_B1=27
9037 11:52:26.919735 28, 0x0, End_B0=28 End_B1=28
9038 11:52:26.923146 29, 0x0, End_B0=29 End_B1=29
9039 11:52:26.926447 30, 0x0, End_B0=30 End_B1=30
9040 11:52:26.926876 31, 0x4545, End_B0=30 End_B1=30
9041 11:52:26.929663 Byte0 end_step=30 best_step=27
9042 11:52:26.933045 Byte1 end_step=30 best_step=27
9043 11:52:26.935880 Byte0 TX OE(2T, 0.5T) = (3, 3)
9044 11:52:26.940352 Byte1 TX OE(2T, 0.5T) = (3, 3)
9045 11:52:26.940776
9046 11:52:26.941111
9047 11:52:26.946346 [DQSOSCAuto] RK1, (LSB)MR18= 0x101e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
9048 11:52:26.949310 CH1 RK1: MR19=303, MR18=101E
9049 11:52:26.955884 CH1_RK1: MR19=0x303, MR18=0x101E, DQSOSC=394, MR23=63, INC=23, DEC=15
9050 11:52:26.958824 [RxdqsGatingPostProcess] freq 1600
9051 11:52:26.965917 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9052 11:52:26.968843 best DQS0 dly(2T, 0.5T) = (1, 1)
9053 11:52:26.972685 best DQS1 dly(2T, 0.5T) = (1, 1)
9054 11:52:26.973109 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9055 11:52:26.975625 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9056 11:52:26.978678 best DQS0 dly(2T, 0.5T) = (1, 1)
9057 11:52:26.982389 best DQS1 dly(2T, 0.5T) = (1, 1)
9058 11:52:26.985412 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9059 11:52:26.989119 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9060 11:52:26.992002 Pre-setting of DQS Precalculation
9061 11:52:26.999053 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9062 11:52:27.005348 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9063 11:52:27.011940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9064 11:52:27.012366
9065 11:52:27.012704
9066 11:52:27.015244 [Calibration Summary] 3200 Mbps
9067 11:52:27.015662 CH 0, Rank 0
9068 11:52:27.018715 SW Impedance : PASS
9069 11:52:27.021950 DUTY Scan : NO K
9070 11:52:27.022583 ZQ Calibration : PASS
9071 11:52:27.025199 Jitter Meter : NO K
9072 11:52:27.028270 CBT Training : PASS
9073 11:52:27.028692 Write leveling : PASS
9074 11:52:27.031678 RX DQS gating : PASS
9075 11:52:27.035053 RX DQ/DQS(RDDQC) : PASS
9076 11:52:27.035477 TX DQ/DQS : PASS
9077 11:52:27.038371 RX DATLAT : PASS
9078 11:52:27.041666 RX DQ/DQS(Engine): PASS
9079 11:52:27.042090 TX OE : PASS
9080 11:52:27.044380 All Pass.
9081 11:52:27.044821
9082 11:52:27.045162 CH 0, Rank 1
9083 11:52:27.047878 SW Impedance : PASS
9084 11:52:27.048300 DUTY Scan : NO K
9085 11:52:27.051269 ZQ Calibration : PASS
9086 11:52:27.054751 Jitter Meter : NO K
9087 11:52:27.055198 CBT Training : PASS
9088 11:52:27.057992 Write leveling : PASS
9089 11:52:27.058466 RX DQS gating : PASS
9090 11:52:27.061216 RX DQ/DQS(RDDQC) : PASS
9091 11:52:27.064428 TX DQ/DQS : PASS
9092 11:52:27.064865 RX DATLAT : PASS
9093 11:52:27.067974 RX DQ/DQS(Engine): PASS
9094 11:52:27.070938 TX OE : PASS
9095 11:52:27.071362 All Pass.
9096 11:52:27.071709
9097 11:52:27.072023 CH 1, Rank 0
9098 11:52:27.074544 SW Impedance : PASS
9099 11:52:27.077652 DUTY Scan : NO K
9100 11:52:27.078076 ZQ Calibration : PASS
9101 11:52:27.080788 Jitter Meter : NO K
9102 11:52:27.084215 CBT Training : PASS
9103 11:52:27.084635 Write leveling : PASS
9104 11:52:27.087488 RX DQS gating : PASS
9105 11:52:27.090676 RX DQ/DQS(RDDQC) : PASS
9106 11:52:27.091102 TX DQ/DQS : PASS
9107 11:52:27.093926 RX DATLAT : PASS
9108 11:52:27.097874 RX DQ/DQS(Engine): PASS
9109 11:52:27.098425 TX OE : PASS
9110 11:52:27.100715 All Pass.
9111 11:52:27.101136
9112 11:52:27.101473 CH 1, Rank 1
9113 11:52:27.103851 SW Impedance : PASS
9114 11:52:27.104274 DUTY Scan : NO K
9115 11:52:27.107128 ZQ Calibration : PASS
9116 11:52:27.110039 Jitter Meter : NO K
9117 11:52:27.110120 CBT Training : PASS
9118 11:52:27.113536 Write leveling : PASS
9119 11:52:27.116700 RX DQS gating : PASS
9120 11:52:27.116782 RX DQ/DQS(RDDQC) : PASS
9121 11:52:27.120417 TX DQ/DQS : PASS
9122 11:52:27.123638 RX DATLAT : PASS
9123 11:52:27.123720 RX DQ/DQS(Engine): PASS
9124 11:52:27.126492 TX OE : PASS
9125 11:52:27.126574 All Pass.
9126 11:52:27.126640
9127 11:52:27.130011 DramC Write-DBI on
9128 11:52:27.133304 PER_BANK_REFRESH: Hybrid Mode
9129 11:52:27.133386 TX_TRACKING: ON
9130 11:52:27.142994 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9131 11:52:27.149480 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9132 11:52:27.156098 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9133 11:52:27.159301 [FAST_K] Save calibration result to emmc
9134 11:52:27.162614 sync common calibartion params.
9135 11:52:27.166119 sync cbt_mode0:1, 1:1
9136 11:52:27.169309 dram_init: ddr_geometry: 2
9137 11:52:27.169380 dram_init: ddr_geometry: 2
9138 11:52:27.172377 dram_init: ddr_geometry: 2
9139 11:52:27.175861 0:dram_rank_size:100000000
9140 11:52:27.179265 1:dram_rank_size:100000000
9141 11:52:27.182444 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9142 11:52:27.185681 DFS_SHUFFLE_HW_MODE: ON
9143 11:52:27.189243 dramc_set_vcore_voltage set vcore to 725000
9144 11:52:27.192784 Read voltage for 1600, 0
9145 11:52:27.192852 Vio18 = 0
9146 11:52:27.196000 Vcore = 725000
9147 11:52:27.196068 Vdram = 0
9148 11:52:27.196131 Vddq = 0
9149 11:52:27.196187 Vmddr = 0
9150 11:52:27.198744 switch to 3200 Mbps bootup
9151 11:52:27.202393 [DramcRunTimeConfig]
9152 11:52:27.202458 PHYPLL
9153 11:52:27.205588 DPM_CONTROL_AFTERK: ON
9154 11:52:27.205655 PER_BANK_REFRESH: ON
9155 11:52:27.208629 REFRESH_OVERHEAD_REDUCTION: ON
9156 11:52:27.211964 CMD_PICG_NEW_MODE: OFF
9157 11:52:27.212032 XRTWTW_NEW_MODE: ON
9158 11:52:27.215271 XRTRTR_NEW_MODE: ON
9159 11:52:27.215338 TX_TRACKING: ON
9160 11:52:27.218684 RDSEL_TRACKING: OFF
9161 11:52:27.221846 DQS Precalculation for DVFS: ON
9162 11:52:27.221917 RX_TRACKING: OFF
9163 11:52:27.225294 HW_GATING DBG: ON
9164 11:52:27.225362 ZQCS_ENABLE_LP4: ON
9165 11:52:27.228496 RX_PICG_NEW_MODE: ON
9166 11:52:27.228565 TX_PICG_NEW_MODE: ON
9167 11:52:27.232126 ENABLE_RX_DCM_DPHY: ON
9168 11:52:27.234973 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9169 11:52:27.238560 DUMMY_READ_FOR_TRACKING: OFF
9170 11:52:27.238632 !!! SPM_CONTROL_AFTERK: OFF
9171 11:52:27.241623 !!! SPM could not control APHY
9172 11:52:27.244962 IMPEDANCE_TRACKING: ON
9173 11:52:27.245035 TEMP_SENSOR: ON
9174 11:52:27.248507 HW_SAVE_FOR_SR: OFF
9175 11:52:27.251627 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9176 11:52:27.255007 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9177 11:52:27.255081 Read ODT Tracking: ON
9178 11:52:27.258200 Refresh Rate DeBounce: ON
9179 11:52:27.261501 DFS_NO_QUEUE_FLUSH: ON
9180 11:52:27.265294 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9181 11:52:27.265693 ENABLE_DFS_RUNTIME_MRW: OFF
9182 11:52:27.268334 DDR_RESERVE_NEW_MODE: ON
9183 11:52:27.271493 MR_CBT_SWITCH_FREQ: ON
9184 11:52:27.275360 =========================
9185 11:52:27.292108 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9186 11:52:27.295536 dram_init: ddr_geometry: 2
9187 11:52:27.313933 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9188 11:52:27.317089 dram_init: dram init end (result: 0)
9189 11:52:27.323736 DRAM-K: Full calibration passed in 24431 msecs
9190 11:52:27.326909 MRC: failed to locate region type 0.
9191 11:52:27.327348 DRAM rank0 size:0x100000000,
9192 11:52:27.330014 DRAM rank1 size=0x100000000
9193 11:52:27.339973 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9194 11:52:27.346498 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9195 11:52:27.353124 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9196 11:52:27.362975 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9197 11:52:27.363393 DRAM rank0 size:0x100000000,
9198 11:52:27.366589 DRAM rank1 size=0x100000000
9199 11:52:27.367005 CBMEM:
9200 11:52:27.369606 IMD: root @ 0xfffff000 254 entries.
9201 11:52:27.372817 IMD: root @ 0xffffec00 62 entries.
9202 11:52:27.376052 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9203 11:52:27.382477 WARNING: RO_VPD is uninitialized or empty.
9204 11:52:27.385966 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9205 11:52:27.393536 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9206 11:52:27.406640 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9207 11:52:27.418073 BS: romstage times (exec / console): total (unknown) / 23959 ms
9208 11:52:27.418526
9209 11:52:27.418863
9210 11:52:27.427662 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9211 11:52:27.430956 ARM64: Exception handlers installed.
9212 11:52:27.434388 ARM64: Testing exception
9213 11:52:27.438066 ARM64: Done test exception
9214 11:52:27.438537 Enumerating buses...
9215 11:52:27.440823 Show all devs... Before device enumeration.
9216 11:52:27.444643 Root Device: enabled 1
9217 11:52:27.447473 CPU_CLUSTER: 0: enabled 1
9218 11:52:27.447898 CPU: 00: enabled 1
9219 11:52:27.450668 Compare with tree...
9220 11:52:27.451092 Root Device: enabled 1
9221 11:52:27.454330 CPU_CLUSTER: 0: enabled 1
9222 11:52:27.457866 CPU: 00: enabled 1
9223 11:52:27.458346 Root Device scanning...
9224 11:52:27.460814 scan_static_bus for Root Device
9225 11:52:27.464432 CPU_CLUSTER: 0 enabled
9226 11:52:27.467343 scan_static_bus for Root Device done
9227 11:52:27.470729 scan_bus: bus Root Device finished in 8 msecs
9228 11:52:27.471156 done
9229 11:52:27.477541 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9230 11:52:27.480881 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9231 11:52:27.487207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9232 11:52:27.490518 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9233 11:52:27.493648 Allocating resources...
9234 11:52:27.497109 Reading resources...
9235 11:52:27.500010 Root Device read_resources bus 0 link: 0
9236 11:52:27.503661 DRAM rank0 size:0x100000000,
9237 11:52:27.504087 DRAM rank1 size=0x100000000
9238 11:52:27.510040 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9239 11:52:27.510525 CPU: 00 missing read_resources
9240 11:52:27.517291 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9241 11:52:27.519951 Root Device read_resources bus 0 link: 0 done
9242 11:52:27.523242 Done reading resources.
9243 11:52:27.526975 Show resources in subtree (Root Device)...After reading.
9244 11:52:27.530347 Root Device child on link 0 CPU_CLUSTER: 0
9245 11:52:27.533400 CPU_CLUSTER: 0 child on link 0 CPU: 00
9246 11:52:27.542997 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9247 11:52:27.543645 CPU: 00
9248 11:52:27.546608 Root Device assign_resources, bus 0 link: 0
9249 11:52:27.549742 CPU_CLUSTER: 0 missing set_resources
9250 11:52:27.556490 Root Device assign_resources, bus 0 link: 0 done
9251 11:52:27.557092 Done setting resources.
9252 11:52:27.563186 Show resources in subtree (Root Device)...After assigning values.
9253 11:52:27.567007 Root Device child on link 0 CPU_CLUSTER: 0
9254 11:52:27.569574 CPU_CLUSTER: 0 child on link 0 CPU: 00
9255 11:52:27.579806 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9256 11:52:27.580230 CPU: 00
9257 11:52:27.582704 Done allocating resources.
9258 11:52:27.589326 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9259 11:52:27.589752 Enabling resources...
9260 11:52:27.592625 done.
9261 11:52:27.595943 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9262 11:52:27.599078 Initializing devices...
9263 11:52:27.599496 Root Device init
9264 11:52:27.602426 init hardware done!
9265 11:52:27.602849 0x00000018: ctrlr->caps
9266 11:52:27.605984 52.000 MHz: ctrlr->f_max
9267 11:52:27.609223 0.400 MHz: ctrlr->f_min
9268 11:52:27.609840 0x40ff8080: ctrlr->voltages
9269 11:52:27.612547 sclk: 390625
9270 11:52:27.613066 Bus Width = 1
9271 11:52:27.615934 sclk: 390625
9272 11:52:27.616379 Bus Width = 1
9273 11:52:27.618850 Early init status = 3
9274 11:52:27.622301 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9275 11:52:27.626825 in-header: 03 fb 00 00 01 00 00 00
9276 11:52:27.629619 in-data: 01
9277 11:52:27.633059 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9278 11:52:27.637542 in-header: 03 fb 00 00 01 00 00 00
9279 11:52:27.641230 in-data: 01
9280 11:52:27.644273 [SSUSB] Setting up USB HOST controller...
9281 11:52:27.647593 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9282 11:52:27.650801 [SSUSB] phy power-on done.
9283 11:52:27.654294 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9284 11:52:27.661077 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9285 11:52:27.663758 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9286 11:52:27.670558 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9287 11:52:27.677099 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9288 11:52:27.683412 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9289 11:52:27.690205 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9290 11:52:27.696808 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9291 11:52:27.700201 SPM: binary array size = 0x9dc
9292 11:52:27.706486 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9293 11:52:27.709999 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9294 11:52:27.720073 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9295 11:52:27.723072 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9296 11:52:27.726349 configure_display: Starting display init
9297 11:52:27.760891 anx7625_power_on_init: Init interface.
9298 11:52:27.764654 anx7625_disable_pd_protocol: Disabled PD feature.
9299 11:52:27.767344 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9300 11:52:27.795121 anx7625_start_dp_work: Secure OCM version=00
9301 11:52:27.798402 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9302 11:52:27.813502 sp_tx_get_edid_block: EDID Block = 1
9303 11:52:27.916386 Extracted contents:
9304 11:52:27.919476 header: 00 ff ff ff ff ff ff 00
9305 11:52:27.922743 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9306 11:52:27.926079 version: 01 04
9307 11:52:27.929161 basic params: 95 1f 11 78 0a
9308 11:52:27.932491 chroma info: 76 90 94 55 54 90 27 21 50 54
9309 11:52:27.935835 established: 00 00 00
9310 11:52:27.942388 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9311 11:52:27.948880 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9312 11:52:27.952332 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9313 11:52:27.958835 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9314 11:52:27.965536 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9315 11:52:27.968871 extensions: 00
9316 11:52:27.969287 checksum: fb
9317 11:52:27.969657
9318 11:52:27.972750 Manufacturer: IVO Model 57d Serial Number 0
9319 11:52:27.975465 Made week 0 of 2020
9320 11:52:27.979050 EDID version: 1.4
9321 11:52:27.979524 Digital display
9322 11:52:27.982167 6 bits per primary color channel
9323 11:52:27.982653 DisplayPort interface
9324 11:52:27.985681 Maximum image size: 31 cm x 17 cm
9325 11:52:27.988532 Gamma: 220%
9326 11:52:27.989067 Check DPMS levels
9327 11:52:27.994815 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9328 11:52:27.998767 First detailed timing is preferred timing
9329 11:52:28.001519 Established timings supported:
9330 11:52:28.001980 Standard timings supported:
9331 11:52:28.005363 Detailed timings
9332 11:52:28.008342 Hex of detail: 383680a07038204018303c0035ae10000019
9333 11:52:28.015325 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9334 11:52:28.018102 0780 0798 07c8 0820 hborder 0
9335 11:52:28.021190 0438 043b 0447 0458 vborder 0
9336 11:52:28.025054 -hsync -vsync
9337 11:52:28.025474 Did detailed timing
9338 11:52:28.031292 Hex of detail: 000000000000000000000000000000000000
9339 11:52:28.034939 Manufacturer-specified data, tag 0
9340 11:52:28.037954 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9341 11:52:28.041026 ASCII string: InfoVision
9342 11:52:28.044589 Hex of detail: 000000fe00523134304e574635205248200a
9343 11:52:28.048295 ASCII string: R140NWF5 RH
9344 11:52:28.048913 Checksum
9345 11:52:28.051434 Checksum: 0xfb (valid)
9346 11:52:28.054191 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9347 11:52:28.057623 DSI data_rate: 832800000 bps
9348 11:52:28.064718 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9349 11:52:28.067694 anx7625_parse_edid: pixelclock(138800).
9350 11:52:28.071003 hactive(1920), hsync(48), hfp(24), hbp(88)
9351 11:52:28.074511 vactive(1080), vsync(12), vfp(3), vbp(17)
9352 11:52:28.077713 anx7625_dsi_config: config dsi.
9353 11:52:28.084082 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9354 11:52:28.098013 anx7625_dsi_config: success to config DSI
9355 11:52:28.101377 anx7625_dp_start: MIPI phy setup OK.
9356 11:52:28.104725 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9357 11:52:28.108210 mtk_ddp_mode_set invalid vrefresh 60
9358 11:52:28.111578 main_disp_path_setup
9359 11:52:28.112022 ovl_layer_smi_id_en
9360 11:52:28.114749 ovl_layer_smi_id_en
9361 11:52:28.115322 ccorr_config
9362 11:52:28.115812 aal_config
9363 11:52:28.117762 gamma_config
9364 11:52:28.118246 postmask_config
9365 11:52:28.121040 dither_config
9366 11:52:28.124525 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9367 11:52:28.131093 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9368 11:52:28.134000 Root Device init finished in 531 msecs
9369 11:52:28.137388 CPU_CLUSTER: 0 init
9370 11:52:28.144012 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9371 11:52:28.150531 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9372 11:52:28.150737 APU_MBOX 0x190000b0 = 0x10001
9373 11:52:28.153614 APU_MBOX 0x190001b0 = 0x10001
9374 11:52:28.157078 APU_MBOX 0x190005b0 = 0x10001
9375 11:52:28.160115 APU_MBOX 0x190006b0 = 0x10001
9376 11:52:28.166503 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9377 11:52:28.177053 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9378 11:52:28.189011 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9379 11:52:28.195736 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9380 11:52:28.207728 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9381 11:52:28.216801 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9382 11:52:28.219871 CPU_CLUSTER: 0 init finished in 81 msecs
9383 11:52:28.223518 Devices initialized
9384 11:52:28.226777 Show all devs... After init.
9385 11:52:28.227271 Root Device: enabled 1
9386 11:52:28.229931 CPU_CLUSTER: 0: enabled 1
9387 11:52:28.233323 CPU: 00: enabled 1
9388 11:52:28.236628 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9389 11:52:28.240196 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9390 11:52:28.243311 ELOG: NV offset 0x57f000 size 0x1000
9391 11:52:28.250017 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9392 11:52:28.256541 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9393 11:52:28.259655 ELOG: Event(17) added with size 13 at 2023-11-23 11:52:29 UTC
9394 11:52:28.266156 out: cmd=0x121: 03 db 21 01 00 00 00 00
9395 11:52:28.269582 in-header: 03 41 00 00 2c 00 00 00
9396 11:52:28.279564 in-data: 1e 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9397 11:52:28.286644 ELOG: Event(A1) added with size 10 at 2023-11-23 11:52:29 UTC
9398 11:52:28.292370 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9399 11:52:28.299543 ELOG: Event(A0) added with size 9 at 2023-11-23 11:52:29 UTC
9400 11:52:28.302978 elog_add_boot_reason: Logged dev mode boot
9401 11:52:28.309240 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9402 11:52:28.309323 Finalize devices...
9403 11:52:28.312669 Devices finalized
9404 11:52:28.315426 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9405 11:52:28.318812 Writing coreboot table at 0xffe64000
9406 11:52:28.322587 0. 000000000010a000-0000000000113fff: RAMSTAGE
9407 11:52:28.325882 1. 0000000040000000-00000000400fffff: RAM
9408 11:52:28.332324 2. 0000000040100000-000000004032afff: RAMSTAGE
9409 11:52:28.335946 3. 000000004032b000-00000000545fffff: RAM
9410 11:52:28.338764 4. 0000000054600000-000000005465ffff: BL31
9411 11:52:28.342315 5. 0000000054660000-00000000ffe63fff: RAM
9412 11:52:28.348833 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9413 11:52:28.352328 7. 0000000100000000-000000023fffffff: RAM
9414 11:52:28.355131 Passing 5 GPIOs to payload:
9415 11:52:28.358523 NAME | PORT | POLARITY | VALUE
9416 11:52:28.365330 EC in RW | 0x000000aa | low | undefined
9417 11:52:28.368428 EC interrupt | 0x00000005 | low | undefined
9418 11:52:28.371714 TPM interrupt | 0x000000ab | high | undefined
9419 11:52:28.378645 SD card detect | 0x00000011 | high | undefined
9420 11:52:28.381550 speaker enable | 0x00000093 | high | undefined
9421 11:52:28.384842 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9422 11:52:28.388512 in-header: 03 f9 00 00 02 00 00 00
9423 11:52:28.391981 in-data: 02 00
9424 11:52:28.395253 ADC[4]: Raw value=902955 ID=7
9425 11:52:28.395366 ADC[3]: Raw value=213546 ID=1
9426 11:52:28.398325 RAM Code: 0x71
9427 11:52:28.401739 ADC[6]: Raw value=74630 ID=0
9428 11:52:28.401935 ADC[5]: Raw value=213546 ID=1
9429 11:52:28.405125 SKU Code: 0x1
9430 11:52:28.411199 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 8d32
9431 11:52:28.411359 coreboot table: 964 bytes.
9432 11:52:28.414682 IMD ROOT 0. 0xfffff000 0x00001000
9433 11:52:28.418306 IMD SMALL 1. 0xffffe000 0x00001000
9434 11:52:28.421248 RO MCACHE 2. 0xffffc000 0x00001104
9435 11:52:28.424868 CONSOLE 3. 0xfff7c000 0x00080000
9436 11:52:28.428300 FMAP 4. 0xfff7b000 0x00000452
9437 11:52:28.431679 TIME STAMP 5. 0xfff7a000 0x00000910
9438 11:52:28.434925 VBOOT WORK 6. 0xfff66000 0x00014000
9439 11:52:28.438152 RAMOOPS 7. 0xffe66000 0x00100000
9440 11:52:28.441513 COREBOOT 8. 0xffe64000 0x00002000
9441 11:52:28.444989 IMD small region:
9442 11:52:28.447773 IMD ROOT 0. 0xffffec00 0x00000400
9443 11:52:28.451801 VPD 1. 0xffffeb80 0x0000006c
9444 11:52:28.454875 MMC STATUS 2. 0xffffeb60 0x00000004
9445 11:52:28.460976 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9446 11:52:28.461418 Probing TPM: done!
9447 11:52:28.465018 Connected to device vid:did:rid of 1ae0:0028:00
9448 11:52:28.475677 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9449 11:52:28.479337 Initialized TPM device CR50 revision 0
9450 11:52:28.482551 Checking cr50 for pending updates
9451 11:52:28.486621 Reading cr50 TPM mode
9452 11:52:28.495705 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9453 11:52:28.501909 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9454 11:52:28.542183 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9455 11:52:28.545672 Checking segment from ROM address 0x40100000
9456 11:52:28.548814 Checking segment from ROM address 0x4010001c
9457 11:52:28.555340 Loading segment from ROM address 0x40100000
9458 11:52:28.555783 code (compression=0)
9459 11:52:28.564990 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9460 11:52:28.572462 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9461 11:52:28.572906 it's not compressed!
9462 11:52:28.578808 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9463 11:52:28.581741 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9464 11:52:28.602124 Loading segment from ROM address 0x4010001c
9465 11:52:28.602684 Entry Point 0x80000000
9466 11:52:28.606284 Loaded segments
9467 11:52:28.608823 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9468 11:52:28.615742 Jumping to boot code at 0x80000000(0xffe64000)
9469 11:52:28.622453 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9470 11:52:28.629076 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9471 11:52:28.636857 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9472 11:52:28.640164 Checking segment from ROM address 0x40100000
9473 11:52:28.643432 Checking segment from ROM address 0x4010001c
9474 11:52:28.649984 Loading segment from ROM address 0x40100000
9475 11:52:28.650442 code (compression=1)
9476 11:52:28.656619 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9477 11:52:28.666661 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9478 11:52:28.667095 using LZMA
9479 11:52:28.675178 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9480 11:52:28.682171 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9481 11:52:28.685515 Loading segment from ROM address 0x4010001c
9482 11:52:28.685937 Entry Point 0x54601000
9483 11:52:28.688682 Loaded segments
9484 11:52:28.691918 NOTICE: MT8192 bl31_setup
9485 11:52:28.699293 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9486 11:52:28.702041 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9487 11:52:28.705260 WARNING: region 0:
9488 11:52:28.708932 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9489 11:52:28.709355 WARNING: region 1:
9490 11:52:28.715702 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9491 11:52:28.719093 WARNING: region 2:
9492 11:52:28.722666 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9493 11:52:28.725632 WARNING: region 3:
9494 11:52:28.729016 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9495 11:52:28.732295 WARNING: region 4:
9496 11:52:28.738946 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9497 11:52:28.739411 WARNING: region 5:
9498 11:52:28.741969 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9499 11:52:28.745555 WARNING: region 6:
9500 11:52:28.748461 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9501 11:52:28.752169 WARNING: region 7:
9502 11:52:28.755381 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9503 11:52:28.762541 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9504 11:52:28.764970 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9505 11:52:28.768373 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9506 11:52:28.775093 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9507 11:52:28.778356 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9508 11:52:28.784990 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9509 11:52:28.788556 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9510 11:52:28.791702 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9511 11:52:28.798580 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9512 11:52:28.801619 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9513 11:52:28.805693 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9514 11:52:28.811800 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9515 11:52:28.815229 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9516 11:52:28.821565 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9517 11:52:28.825347 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9518 11:52:28.828193 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9519 11:52:28.834985 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9520 11:52:28.837960 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9521 11:52:28.841496 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9522 11:52:28.847838 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9523 11:52:28.851090 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9524 11:52:28.857686 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9525 11:52:28.861481 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9526 11:52:28.864888 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9527 11:52:28.870908 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9528 11:52:28.874537 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9529 11:52:28.880867 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9530 11:52:28.884201 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9531 11:52:28.890978 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9532 11:52:28.894248 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9533 11:52:28.897484 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9534 11:52:28.904241 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9535 11:52:28.907218 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9536 11:52:28.910858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9537 11:52:28.913818 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9538 11:52:28.921335 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9539 11:52:28.923792 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9540 11:52:28.927468 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9541 11:52:28.930604 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9542 11:52:28.937113 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9543 11:52:28.940550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9544 11:52:28.943734 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9545 11:52:28.947605 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9546 11:52:28.954087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9547 11:52:28.957362 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9548 11:52:28.960206 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9549 11:52:28.967325 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9550 11:52:28.970489 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9551 11:52:28.973664 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9552 11:52:28.980533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9553 11:52:28.983547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9554 11:52:28.990419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9555 11:52:28.993693 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9556 11:52:28.996905 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9557 11:52:29.003728 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9558 11:52:29.006981 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9559 11:52:29.014136 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9560 11:52:29.016902 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9561 11:52:29.023617 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9562 11:52:29.026766 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9563 11:52:29.033365 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9564 11:52:29.036722 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9565 11:52:29.039900 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9566 11:52:29.046392 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9567 11:52:29.049993 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9568 11:52:29.056817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9569 11:52:29.059704 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9570 11:52:29.066866 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9571 11:52:29.069830 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9572 11:52:29.073300 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9573 11:52:29.079514 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9574 11:52:29.083298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9575 11:52:29.089614 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9576 11:52:29.093278 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9577 11:52:29.099977 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9578 11:52:29.103298 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9579 11:52:29.109832 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9580 11:52:29.112849 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9581 11:52:29.116581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9582 11:52:29.122594 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9583 11:52:29.126319 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9584 11:52:29.132742 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9585 11:52:29.136131 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9586 11:52:29.142714 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9587 11:52:29.146088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9588 11:52:29.149319 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9589 11:52:29.156177 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9590 11:52:29.159388 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9591 11:52:29.166117 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9592 11:52:29.169255 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9593 11:52:29.175860 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9594 11:52:29.179232 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9595 11:52:29.186245 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9596 11:52:29.189543 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9597 11:52:29.192577 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9598 11:52:29.199741 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9599 11:52:29.202627 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9600 11:52:29.205687 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9601 11:52:29.212730 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9602 11:52:29.215818 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9603 11:52:29.218773 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9604 11:52:29.225758 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9605 11:52:29.229065 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9606 11:52:29.232408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9607 11:52:29.239185 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9608 11:52:29.242244 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9609 11:52:29.248612 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9610 11:52:29.252093 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9611 11:52:29.255136 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9612 11:52:29.261758 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9613 11:52:29.265023 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9614 11:52:29.271890 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9615 11:52:29.275525 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9616 11:52:29.278222 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9617 11:52:29.285401 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9618 11:52:29.288780 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9619 11:52:29.292239 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9620 11:52:29.298507 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9621 11:52:29.302292 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9622 11:52:29.305116 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9623 11:52:29.311911 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9624 11:52:29.315359 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9625 11:52:29.318549 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9626 11:52:29.321655 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9627 11:52:29.328313 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9628 11:52:29.331998 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9629 11:52:29.338322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9630 11:52:29.341833 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9631 11:52:29.345017 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9632 11:52:29.351570 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9633 11:52:29.354961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9634 11:52:29.361290 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9635 11:52:29.364652 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9636 11:52:29.368331 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9637 11:52:29.375027 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9638 11:52:29.378313 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9639 11:52:29.385066 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9640 11:52:29.388031 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9641 11:52:29.391543 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9642 11:52:29.398365 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9643 11:52:29.401893 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9644 11:52:29.404605 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9645 11:52:29.411528 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9646 11:52:29.414179 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9647 11:52:29.421101 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9648 11:52:29.424111 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9649 11:52:29.427403 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9650 11:52:29.434551 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9651 11:52:29.437500 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9652 11:52:29.444004 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9653 11:52:29.447489 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9654 11:52:29.450892 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9655 11:52:29.458540 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9656 11:52:29.461316 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9657 11:52:29.467792 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9658 11:52:29.470786 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9659 11:52:29.474321 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9660 11:52:29.481312 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9661 11:52:29.484157 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9662 11:52:29.490532 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9663 11:52:29.494030 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9664 11:52:29.497068 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9665 11:52:29.503734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9666 11:52:29.506893 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9667 11:52:29.513271 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9668 11:52:29.517399 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9669 11:52:29.519905 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9670 11:52:29.526407 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9671 11:52:29.529756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9672 11:52:29.536654 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9673 11:52:29.539891 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9674 11:52:29.543309 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9675 11:52:29.549999 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9676 11:52:29.553185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9677 11:52:29.559507 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9678 11:52:29.563024 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9679 11:52:29.566270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9680 11:52:29.572715 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9681 11:52:29.576243 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9682 11:52:29.583217 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9683 11:52:29.585983 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9684 11:52:29.589953 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9685 11:52:29.595890 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9686 11:52:29.599460 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9687 11:52:29.606036 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9688 11:52:29.609503 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9689 11:52:29.612693 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9690 11:52:29.619974 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9691 11:52:29.623058 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9692 11:52:29.629359 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9693 11:52:29.632728 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9694 11:52:29.638887 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9695 11:52:29.642084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9696 11:52:29.646059 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9697 11:52:29.652161 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9698 11:52:29.655575 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9699 11:52:29.662196 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9700 11:52:29.665213 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9701 11:52:29.671703 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9702 11:52:29.674965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9703 11:52:29.678385 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9704 11:52:29.684919 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9705 11:52:29.688505 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9706 11:52:29.694856 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9707 11:52:29.698514 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9708 11:52:29.704896 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9709 11:52:29.708097 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9710 11:52:29.711616 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9711 11:52:29.718094 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9712 11:52:29.721607 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9713 11:52:29.728363 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9714 11:52:29.731689 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9715 11:52:29.735132 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9716 11:52:29.741095 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9717 11:52:29.744382 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9718 11:52:29.751963 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9719 11:52:29.754336 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9720 11:52:29.761628 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9721 11:52:29.764377 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9722 11:52:29.768370 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9723 11:52:29.774699 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9724 11:52:29.777452 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9725 11:52:29.784445 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9726 11:52:29.787615 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9727 11:52:29.793912 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9728 11:52:29.797148 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9729 11:52:29.801580 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9730 11:52:29.807581 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9731 11:52:29.810805 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9732 11:52:29.814089 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9733 11:52:29.820681 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9734 11:52:29.823994 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9735 11:52:29.827105 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9736 11:52:29.830393 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9737 11:52:29.836907 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9738 11:52:29.840093 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9739 11:52:29.846506 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9740 11:52:29.850532 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9741 11:52:29.853701 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9742 11:52:29.859892 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9743 11:52:29.863528 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9744 11:52:29.870095 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9745 11:52:29.873122 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9746 11:52:29.876183 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9747 11:52:29.883331 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9748 11:52:29.886324 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9749 11:52:29.889579 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9750 11:52:29.896928 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9751 11:52:29.899299 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9752 11:52:29.902663 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9753 11:52:29.909202 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9754 11:52:29.912758 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9755 11:52:29.919603 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9756 11:52:29.922917 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9757 11:52:29.925954 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9758 11:52:29.932350 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9759 11:52:29.936264 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9760 11:52:29.942438 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9761 11:52:29.945704 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9762 11:52:29.948756 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9763 11:52:29.955681 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9764 11:52:29.958474 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9765 11:52:29.962361 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9766 11:52:29.968830 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9767 11:52:29.972075 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9768 11:52:29.978064 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9769 11:52:29.982106 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9770 11:52:29.984791 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9771 11:52:29.991942 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9772 11:52:29.994969 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9773 11:52:29.998078 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9774 11:52:30.001381 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9775 11:52:30.004727 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9776 11:52:30.011408 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9777 11:52:30.014727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9778 11:52:30.017763 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9779 11:52:30.024359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9780 11:52:30.027992 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9781 11:52:30.031288 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9782 11:52:30.034683 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9783 11:52:30.040915 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9784 11:52:30.044281 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9785 11:52:30.047622 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9786 11:52:30.054175 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9787 11:52:30.057282 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9788 11:52:30.063980 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9789 11:52:30.067340 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9790 11:52:30.073946 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9791 11:52:30.076970 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9792 11:52:30.080687 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9793 11:52:30.086996 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9794 11:52:30.090544 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9795 11:52:30.097067 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9796 11:52:30.100057 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9797 11:52:30.106761 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9798 11:52:30.110228 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9799 11:52:30.113252 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9800 11:52:30.119706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9801 11:52:30.122981 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9802 11:52:30.129628 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9803 11:52:30.133297 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9804 11:52:30.136569 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9805 11:52:30.143292 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9806 11:52:30.146579 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9807 11:52:30.152734 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9808 11:52:30.156579 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9809 11:52:30.159476 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9810 11:52:30.165608 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9811 11:52:30.169500 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9812 11:52:30.175651 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9813 11:52:30.179027 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9814 11:52:30.185609 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9815 11:52:30.188648 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9816 11:52:30.192196 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9817 11:52:30.198710 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9818 11:52:30.202513 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9819 11:52:30.209142 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9820 11:52:30.212490 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9821 11:52:30.218987 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9822 11:52:30.222354 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9823 11:52:30.226146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9824 11:52:30.232001 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9825 11:52:30.235190 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9826 11:52:30.241672 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9827 11:52:30.245557 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9828 11:52:30.248490 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9829 11:52:30.255084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9830 11:52:30.258940 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9831 11:52:30.265488 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9832 11:52:30.268302 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9833 11:52:30.271591 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9834 11:52:30.278225 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9835 11:52:30.281919 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9836 11:52:30.288612 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9837 11:52:30.291590 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9838 11:52:30.298456 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9839 11:52:30.301623 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9840 11:52:30.304761 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9841 11:52:30.311440 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9842 11:52:30.314572 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9843 11:52:30.321299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9844 11:52:30.324317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9845 11:52:30.330883 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9846 11:52:30.334352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9847 11:52:30.337774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9848 11:52:30.344397 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9849 11:52:30.347748 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9850 11:52:30.353827 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9851 11:52:30.357449 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9852 11:52:30.361120 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9853 11:52:30.367424 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9854 11:52:30.370876 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9855 11:52:30.377231 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9856 11:52:30.380284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9857 11:52:30.383850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9858 11:52:30.390580 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9859 11:52:30.393805 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9860 11:52:30.400382 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9861 11:52:30.403665 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9862 11:52:30.410008 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9863 11:52:30.413134 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9864 11:52:30.419766 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9865 11:52:30.422865 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9866 11:52:30.429994 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9867 11:52:30.433181 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9868 11:52:30.440007 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9869 11:52:30.442670 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9870 11:52:30.446154 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9871 11:52:30.452974 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9872 11:52:30.456887 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9873 11:52:30.462344 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9874 11:52:30.465966 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9875 11:52:30.472496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9876 11:52:30.475860 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9877 11:52:30.482117 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9878 11:52:30.485508 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9879 11:52:30.489570 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9880 11:52:30.496061 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9881 11:52:30.498975 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9882 11:52:30.505278 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9883 11:52:30.508525 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9884 11:52:30.515407 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9885 11:52:30.518347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9886 11:52:30.524970 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9887 11:52:30.528003 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9888 11:52:30.531465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9889 11:52:30.538466 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9890 11:52:30.541573 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9891 11:52:30.548197 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9892 11:52:30.551843 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9893 11:52:30.558028 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9894 11:52:30.561411 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9895 11:52:30.568496 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9896 11:52:30.571346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9897 11:52:30.574759 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9898 11:52:30.581178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9899 11:52:30.584460 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9900 11:52:30.591202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9901 11:52:30.594816 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9902 11:52:30.601056 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9903 11:52:30.604403 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9904 11:52:30.608334 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9905 11:52:30.614195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9906 11:52:30.617958 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9907 11:52:30.624428 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9908 11:52:30.628013 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9909 11:52:30.634066 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9910 11:52:30.637321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9911 11:52:30.643720 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9912 11:52:30.646939 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9913 11:52:30.653690 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9914 11:52:30.656762 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9915 11:52:30.663419 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9916 11:52:30.666512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9917 11:52:30.673370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9918 11:52:30.676517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9919 11:52:30.683324 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9920 11:52:30.686219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9921 11:52:30.693381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9922 11:52:30.696350 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9923 11:52:30.703317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9924 11:52:30.706385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9925 11:52:30.712974 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9926 11:52:30.715960 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9927 11:52:30.722945 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9928 11:52:30.726065 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9929 11:52:30.732843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9930 11:52:30.736326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9931 11:52:30.742826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9932 11:52:30.746382 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9933 11:52:30.752663 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9934 11:52:30.757125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9935 11:52:30.763163 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9936 11:52:30.766012 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9937 11:52:30.769413 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9938 11:52:30.772877 INFO: [APUAPC] vio 0
9939 11:52:30.779889 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9940 11:52:30.783025 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9941 11:52:30.786314 INFO: [APUAPC] D0_APC_0: 0x400510
9942 11:52:30.789092 INFO: [APUAPC] D0_APC_1: 0x0
9943 11:52:30.792589 INFO: [APUAPC] D0_APC_2: 0x1540
9944 11:52:30.795971 INFO: [APUAPC] D0_APC_3: 0x0
9945 11:52:30.800004 INFO: [APUAPC] D1_APC_0: 0xffffffff
9946 11:52:30.802840 INFO: [APUAPC] D1_APC_1: 0xffffffff
9947 11:52:30.806004 INFO: [APUAPC] D1_APC_2: 0x3fffff
9948 11:52:30.806535 INFO: [APUAPC] D1_APC_3: 0x0
9949 11:52:30.812550 INFO: [APUAPC] D2_APC_0: 0xffffffff
9950 11:52:30.816210 INFO: [APUAPC] D2_APC_1: 0xffffffff
9951 11:52:30.819127 INFO: [APUAPC] D2_APC_2: 0x3fffff
9952 11:52:30.819569 INFO: [APUAPC] D2_APC_3: 0x0
9953 11:52:30.822605 INFO: [APUAPC] D3_APC_0: 0xffffffff
9954 11:52:30.829241 INFO: [APUAPC] D3_APC_1: 0xffffffff
9955 11:52:30.832600 INFO: [APUAPC] D3_APC_2: 0x3fffff
9956 11:52:30.833022 INFO: [APUAPC] D3_APC_3: 0x0
9957 11:52:30.835504 INFO: [APUAPC] D4_APC_0: 0xffffffff
9958 11:52:30.838962 INFO: [APUAPC] D4_APC_1: 0xffffffff
9959 11:52:30.842159 INFO: [APUAPC] D4_APC_2: 0x3fffff
9960 11:52:30.845286 INFO: [APUAPC] D4_APC_3: 0x0
9961 11:52:30.849064 INFO: [APUAPC] D5_APC_0: 0xffffffff
9962 11:52:30.852032 INFO: [APUAPC] D5_APC_1: 0xffffffff
9963 11:52:30.855603 INFO: [APUAPC] D5_APC_2: 0x3fffff
9964 11:52:30.858607 INFO: [APUAPC] D5_APC_3: 0x0
9965 11:52:30.862108 INFO: [APUAPC] D6_APC_0: 0xffffffff
9966 11:52:30.865769 INFO: [APUAPC] D6_APC_1: 0xffffffff
9967 11:52:30.868704 INFO: [APUAPC] D6_APC_2: 0x3fffff
9968 11:52:30.872234 INFO: [APUAPC] D6_APC_3: 0x0
9969 11:52:30.875353 INFO: [APUAPC] D7_APC_0: 0xffffffff
9970 11:52:30.878319 INFO: [APUAPC] D7_APC_1: 0xffffffff
9971 11:52:30.882069 INFO: [APUAPC] D7_APC_2: 0x3fffff
9972 11:52:30.885141 INFO: [APUAPC] D7_APC_3: 0x0
9973 11:52:30.888089 INFO: [APUAPC] D8_APC_0: 0xffffffff
9974 11:52:30.891679 INFO: [APUAPC] D8_APC_1: 0xffffffff
9975 11:52:30.894781 INFO: [APUAPC] D8_APC_2: 0x3fffff
9976 11:52:30.898351 INFO: [APUAPC] D8_APC_3: 0x0
9977 11:52:30.901287 INFO: [APUAPC] D9_APC_0: 0xffffffff
9978 11:52:30.904965 INFO: [APUAPC] D9_APC_1: 0xffffffff
9979 11:52:30.908331 INFO: [APUAPC] D9_APC_2: 0x3fffff
9980 11:52:30.911522 INFO: [APUAPC] D9_APC_3: 0x0
9981 11:52:30.915057 INFO: [APUAPC] D10_APC_0: 0xffffffff
9982 11:52:30.917879 INFO: [APUAPC] D10_APC_1: 0xffffffff
9983 11:52:30.921095 INFO: [APUAPC] D10_APC_2: 0x3fffff
9984 11:52:30.924641 INFO: [APUAPC] D10_APC_3: 0x0
9985 11:52:30.928129 INFO: [APUAPC] D11_APC_0: 0xffffffff
9986 11:52:30.931443 INFO: [APUAPC] D11_APC_1: 0xffffffff
9987 11:52:30.934625 INFO: [APUAPC] D11_APC_2: 0x3fffff
9988 11:52:30.938416 INFO: [APUAPC] D11_APC_3: 0x0
9989 11:52:30.941603 INFO: [APUAPC] D12_APC_0: 0xffffffff
9990 11:52:30.944670 INFO: [APUAPC] D12_APC_1: 0xffffffff
9991 11:52:30.947848 INFO: [APUAPC] D12_APC_2: 0x3fffff
9992 11:52:30.951260 INFO: [APUAPC] D12_APC_3: 0x0
9993 11:52:30.954339 INFO: [APUAPC] D13_APC_0: 0xffffffff
9994 11:52:30.957840 INFO: [APUAPC] D13_APC_1: 0xffffffff
9995 11:52:30.960994 INFO: [APUAPC] D13_APC_2: 0x3fffff
9996 11:52:30.964312 INFO: [APUAPC] D13_APC_3: 0x0
9997 11:52:30.967860 INFO: [APUAPC] D14_APC_0: 0xffffffff
9998 11:52:30.970771 INFO: [APUAPC] D14_APC_1: 0xffffffff
9999 11:52:30.974109 INFO: [APUAPC] D14_APC_2: 0x3fffff
10000 11:52:30.977647 INFO: [APUAPC] D14_APC_3: 0x0
10001 11:52:30.980383 INFO: [APUAPC] D15_APC_0: 0xffffffff
10002 11:52:30.984412 INFO: [APUAPC] D15_APC_1: 0xffffffff
10003 11:52:30.987052 INFO: [APUAPC] D15_APC_2: 0x3fffff
10004 11:52:30.990302 INFO: [APUAPC] D15_APC_3: 0x0
10005 11:52:30.994214 INFO: [APUAPC] APC_CON: 0x4
10006 11:52:30.996928 INFO: [NOCDAPC] D0_APC_0: 0x0
10007 11:52:31.000889 INFO: [NOCDAPC] D0_APC_1: 0x0
10008 11:52:31.003377 INFO: [NOCDAPC] D1_APC_0: 0x0
10009 11:52:31.007173 INFO: [NOCDAPC] D1_APC_1: 0xfff
10010 11:52:31.010373 INFO: [NOCDAPC] D2_APC_0: 0x0
10011 11:52:31.013423 INFO: [NOCDAPC] D2_APC_1: 0xfff
10012 11:52:31.016633 INFO: [NOCDAPC] D3_APC_0: 0x0
10013 11:52:31.019838 INFO: [NOCDAPC] D3_APC_1: 0xfff
10014 11:52:31.020262 INFO: [NOCDAPC] D4_APC_0: 0x0
10015 11:52:31.023010 INFO: [NOCDAPC] D4_APC_1: 0xfff
10016 11:52:31.026395 INFO: [NOCDAPC] D5_APC_0: 0x0
10017 11:52:31.029847 INFO: [NOCDAPC] D5_APC_1: 0xfff
10018 11:52:31.032661 INFO: [NOCDAPC] D6_APC_0: 0x0
10019 11:52:31.036141 INFO: [NOCDAPC] D6_APC_1: 0xfff
10020 11:52:31.039395 INFO: [NOCDAPC] D7_APC_0: 0x0
10021 11:52:31.042718 INFO: [NOCDAPC] D7_APC_1: 0xfff
10022 11:52:31.045976 INFO: [NOCDAPC] D8_APC_0: 0x0
10023 11:52:31.049271 INFO: [NOCDAPC] D8_APC_1: 0xfff
10024 11:52:31.052524 INFO: [NOCDAPC] D9_APC_0: 0x0
10025 11:52:31.055687 INFO: [NOCDAPC] D9_APC_1: 0xfff
10026 11:52:31.055772 INFO: [NOCDAPC] D10_APC_0: 0x0
10027 11:52:31.059218 INFO: [NOCDAPC] D10_APC_1: 0xfff
10028 11:52:31.062319 INFO: [NOCDAPC] D11_APC_0: 0x0
10029 11:52:31.065941 INFO: [NOCDAPC] D11_APC_1: 0xfff
10030 11:52:31.068993 INFO: [NOCDAPC] D12_APC_0: 0x0
10031 11:52:31.072604 INFO: [NOCDAPC] D12_APC_1: 0xfff
10032 11:52:31.075937 INFO: [NOCDAPC] D13_APC_0: 0x0
10033 11:52:31.079037 INFO: [NOCDAPC] D13_APC_1: 0xfff
10034 11:52:31.082242 INFO: [NOCDAPC] D14_APC_0: 0x0
10035 11:52:31.085734 INFO: [NOCDAPC] D14_APC_1: 0xfff
10036 11:52:31.089255 INFO: [NOCDAPC] D15_APC_0: 0x0
10037 11:52:31.092426 INFO: [NOCDAPC] D15_APC_1: 0xfff
10038 11:52:31.095543 INFO: [NOCDAPC] APC_CON: 0x4
10039 11:52:31.098657 INFO: [APUAPC] set_apusys_apc done
10040 11:52:31.102191 INFO: [DEVAPC] devapc_init done
10041 11:52:31.105487 INFO: GICv3 without legacy support detected.
10042 11:52:31.108953 INFO: ARM GICv3 driver initialized in EL3
10043 11:52:31.111987 INFO: Maximum SPI INTID supported: 639
10044 11:52:31.115288 INFO: BL31: Initializing runtime services
10045 11:52:31.121901 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10046 11:52:31.125010 INFO: SPM: enable CPC mode
10047 11:52:31.131694 INFO: mcdi ready for mcusys-off-idle and system suspend
10048 11:52:31.135024 INFO: BL31: Preparing for EL3 exit to normal world
10049 11:52:31.138300 INFO: Entry point address = 0x80000000
10050 11:52:31.141494 INFO: SPSR = 0x8
10051 11:52:31.147084
10052 11:52:31.147286
10053 11:52:31.147449
10054 11:52:31.150055 Starting depthcharge on Spherion...
10055 11:52:31.150553
10056 11:52:31.150955 Wipe memory regions:
10057 11:52:31.151319
10058 11:52:31.154368 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10059 11:52:31.154950 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 11:52:31.155422 Setting prompt string to ['asurada:']
10061 11:52:31.155879 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 11:52:31.156680 [0x00000040000000, 0x00000054600000)
10063 11:52:31.275714
10064 11:52:31.275979 [0x00000054660000, 0x00000080000000)
10065 11:52:31.535814
10066 11:52:31.535946 [0x000000821a7280, 0x000000ffe64000)
10067 11:52:32.281059
10068 11:52:32.281586 [0x00000100000000, 0x00000240000000)
10069 11:52:34.171766
10070 11:52:34.174948 Initializing XHCI USB controller at 0x11200000.
10071 11:52:35.212773
10072 11:52:35.215948 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10073 11:52:35.216495
10074 11:52:35.216836
10075 11:52:35.217163
10076 11:52:35.217948 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 11:52:35.319040 asurada: tftpboot 192.168.201.1 12066519/tftp-deploy-6030xfpe/kernel/image.itb 12066519/tftp-deploy-6030xfpe/kernel/cmdline
10079 11:52:35.319188 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 11:52:35.319280 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 11:52:35.323721 tftpboot 192.168.201.1 12066519/tftp-deploy-6030xfpe/kernel/image.itp-deploy-6030xfpe/kernel/cmdline
10082 11:52:35.323809
10083 11:52:35.323874 Waiting for link
10084 11:52:35.484371
10085 11:52:35.484522 R8152: Initializing
10086 11:52:35.484595
10087 11:52:35.487791 Version 6 (ocp_data = 5c30)
10088 11:52:35.487871
10089 11:52:35.490816 R8152: Done initializing
10090 11:52:35.490893
10091 11:52:35.490958 Adding net device
10092 11:52:37.344051
10093 11:52:37.344593 done.
10094 11:52:37.345020
10095 11:52:37.345326 MAC: 00:24:32:30:7c:7b
10096 11:52:37.345707
10097 11:52:37.347271 Sending DHCP discover... done.
10098 11:52:37.347619
10099 11:52:37.350354 Waiting for reply... done.
10100 11:52:37.350694
10101 11:52:37.354459 Sending DHCP request... done.
10102 11:52:37.354916
10103 11:52:37.363869 Waiting for reply... done.
10104 11:52:37.363960
10105 11:52:37.364026 My ip is 192.168.201.14
10106 11:52:37.364087
10107 11:52:37.367745 The DHCP server ip is 192.168.201.1
10108 11:52:37.367817
10109 11:52:37.373648 TFTP server IP predefined by user: 192.168.201.1
10110 11:52:37.373726
10111 11:52:37.380787 Bootfile predefined by user: 12066519/tftp-deploy-6030xfpe/kernel/image.itb
10112 11:52:37.381260
10113 11:52:37.383947 Sending tftp read request... done.
10114 11:52:37.384336
10115 11:52:37.390361 Waiting for the transfer...
10116 11:52:37.390766
10117 11:52:38.015185 00000000 ################################################################
10118 11:52:38.015322
10119 11:52:38.681756 00080000 ################################################################
10120 11:52:38.682383
10121 11:52:39.363012 00100000 ################################################################
10122 11:52:39.363560
10123 11:52:40.039242 00180000 ################################################################
10124 11:52:40.039763
10125 11:52:40.701818 00200000 ################################################################
10126 11:52:40.702381
10127 11:52:41.401942 00280000 ################################################################
10128 11:52:41.402474
10129 11:52:42.096615 00300000 ################################################################
10130 11:52:42.097139
10131 11:52:42.752732 00380000 ################################################################
10132 11:52:42.752869
10133 11:52:43.327172 00400000 ################################################################
10134 11:52:43.327313
10135 11:52:43.999939 00480000 ################################################################
10136 11:52:44.000452
10137 11:52:44.726782 00500000 ################################################################
10138 11:52:44.727286
10139 11:52:45.339027 00580000 ################################################################
10140 11:52:45.339280
10141 11:52:46.039955 00600000 ################################################################
10142 11:52:46.040494
10143 11:52:46.740718 00680000 ################################################################
10144 11:52:46.741214
10145 11:52:47.435438 00700000 ################################################################
10146 11:52:47.435966
10147 11:52:48.087163 00780000 ################################################################
10148 11:52:48.087689
10149 11:52:48.804941 00800000 ################################################################
10150 11:52:48.805519
10151 11:52:49.504102 00880000 ################################################################
10152 11:52:49.504238
10153 11:52:50.092454 00900000 ################################################################
10154 11:52:50.092599
10155 11:52:50.662810 00980000 ################################################################
10156 11:52:50.662958
10157 11:52:51.228196 00a00000 ################################################################
10158 11:52:51.228348
10159 11:52:51.796587 00a80000 ################################################################
10160 11:52:51.796732
10161 11:52:52.362871 00b00000 ################################################################
10162 11:52:52.363019
10163 11:52:52.897336 00b80000 ################################################################
10164 11:52:52.897483
10165 11:52:53.435707 00c00000 ################################################################
10166 11:52:53.435884
10167 11:52:53.985841 00c80000 ################################################################
10168 11:52:53.985989
10169 11:52:54.556109 00d00000 ################################################################
10170 11:52:54.556256
10171 11:52:55.115902 00d80000 ################################################################
10172 11:52:55.116054
10173 11:52:55.667360 00e00000 ################################################################
10174 11:52:55.667511
10175 11:52:56.208103 00e80000 ################################################################
10176 11:52:56.208253
10177 11:52:56.752835 00f00000 ################################################################
10178 11:52:56.752976
10179 11:52:57.302112 00f80000 ################################################################
10180 11:52:57.302291
10181 11:52:57.858353 01000000 ################################################################
10182 11:52:57.858496
10183 11:52:58.413201 01080000 ################################################################
10184 11:52:58.413352
10185 11:52:59.003247 01100000 ################################################################
10186 11:52:59.003412
10187 11:52:59.569527 01180000 ################################################################
10188 11:52:59.569675
10189 11:53:00.161404 01200000 ################################################################
10190 11:53:00.161559
10191 11:53:00.738085 01280000 ################################################################
10192 11:53:00.738246
10193 11:53:01.320880 01300000 ################################################################
10194 11:53:01.321027
10195 11:53:01.911375 01380000 ################################################################
10196 11:53:01.911795
10197 11:53:02.581064 01400000 ################################################################
10198 11:53:02.581262
10199 11:53:03.241143 01480000 ################################################################
10200 11:53:03.241678
10201 11:53:03.932268 01500000 ################################################################
10202 11:53:03.932805
10203 11:53:04.615687 01580000 ################################################################
10204 11:53:04.616060
10205 11:53:05.251736 01600000 ################################################################
10206 11:53:05.251884
10207 11:53:05.811308 01680000 ################################################################
10208 11:53:05.811457
10209 11:53:06.441449 01700000 ################################################################
10210 11:53:06.441979
10211 11:53:07.083663 01780000 ################################################################
10212 11:53:07.084068
10213 11:53:07.744893 01800000 ################################################################
10214 11:53:07.745419
10215 11:53:08.323005 01880000 ################################################################
10216 11:53:08.323149
10217 11:53:08.981276 01900000 ################################################################
10218 11:53:08.981772
10219 11:53:09.560693 01980000 ################################################################
10220 11:53:09.560868
10221 11:53:10.104267 01a00000 ################################################################
10222 11:53:10.104444
10223 11:53:10.654651 01a80000 ################################################################
10224 11:53:10.654809
10225 11:53:11.206927 01b00000 ################################################################
10226 11:53:11.207147
10227 11:53:11.265152 01b80000 ####### done.
10228 11:53:11.265293
10229 11:53:11.268698 The bootfile was 28889878 bytes long.
10230 11:53:11.268783
10231 11:53:11.271464 Sending tftp read request... done.
10232 11:53:11.271547
10233 11:53:11.271611 Waiting for the transfer...
10234 11:53:11.271671
10235 11:53:11.275075 00000000 # done.
10236 11:53:11.275155
10237 11:53:11.281870 Command line loaded dynamically from TFTP file: 12066519/tftp-deploy-6030xfpe/kernel/cmdline
10238 11:53:11.281988
10239 11:53:11.304525 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10240 11:53:11.304649
10241 11:53:11.304727 Loading FIT.
10242 11:53:11.304789
10243 11:53:11.307899 Image ramdisk-1 has 17793381 bytes.
10244 11:53:11.307986
10245 11:53:11.310858 Image fdt-1 has 47278 bytes.
10246 11:53:11.310960
10247 11:53:11.314579 Image kernel-1 has 11047184 bytes.
10248 11:53:11.314656
10249 11:53:11.324794 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10250 11:53:11.324886
10251 11:53:11.340963 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10252 11:53:11.341078
10253 11:53:11.347409 Choosing best match conf-1 for compat google,spherion-rev2.
10254 11:53:11.347493
10255 11:53:11.355403 Connected to device vid:did:rid of 1ae0:0028:00
10256 11:53:11.362154
10257 11:53:11.365333 tpm_get_response: command 0x17b, return code 0x0
10258 11:53:11.365412
10259 11:53:11.368666 ec_init: CrosEC protocol v3 supported (256, 248)
10260 11:53:11.372777
10261 11:53:11.376059 tpm_cleanup: add release locality here.
10262 11:53:11.376135
10263 11:53:11.376213 Shutting down all USB controllers.
10264 11:53:11.379626
10265 11:53:11.379701 Removing current net device
10266 11:53:11.379771
10267 11:53:11.385701 Exiting depthcharge with code 4 at timestamp: 69468734
10268 11:53:11.385786
10269 11:53:11.390522 LZMA decompressing kernel-1 to 0x821a6718
10270 11:53:11.390602
10271 11:53:11.392505 LZMA decompressing kernel-1 to 0x40000000
10272 11:53:12.781136
10273 11:53:12.781317 jumping to kernel
10274 11:53:12.781803 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10275 11:53:12.781914 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10276 11:53:12.781993 Setting prompt string to ['Linux version [0-9]']
10277 11:53:12.782072 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 11:53:12.782139 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 11:53:12.863642
10280 11:53:12.866791 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10281 11:53:12.870405 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10282 11:53:12.870497 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 11:53:12.870577 Setting prompt string to []
10284 11:53:12.870655 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 11:53:12.870735 Using line separator: #'\n'#
10286 11:53:12.870795 No login prompt set.
10287 11:53:12.870858 Parsing kernel messages
10288 11:53:12.870920 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 11:53:12.871027 [login-action] Waiting for messages, (timeout 00:03:44)
10290 11:53:12.889762 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10291 11:53:12.892875 [ 0.000000] random: crng init done
10292 11:53:12.899739 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10293 11:53:12.902721 [ 0.000000] efi: UEFI not found.
10294 11:53:12.909159 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10295 11:53:12.916150 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10296 11:53:12.925892 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10297 11:53:12.935953 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10298 11:53:12.942083 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10299 11:53:12.948634 [ 0.000000] printk: bootconsole [mtk8250] enabled
10300 11:53:12.955383 [ 0.000000] NUMA: No NUMA configuration found
10301 11:53:12.962107 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10302 11:53:12.965134 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10303 11:53:12.968899 [ 0.000000] Zone ranges:
10304 11:53:12.975278 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10305 11:53:12.978809 [ 0.000000] DMA32 empty
10306 11:53:12.985090 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10307 11:53:12.988287 [ 0.000000] Movable zone start for each node
10308 11:53:12.991642 [ 0.000000] Early memory node ranges
10309 11:53:12.998547 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10310 11:53:13.004543 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10311 11:53:13.011172 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10312 11:53:13.017892 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10313 11:53:13.024719 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10314 11:53:13.031159 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10315 11:53:13.087672 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10316 11:53:13.094366 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10317 11:53:13.100399 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10318 11:53:13.104313 [ 0.000000] psci: probing for conduit method from DT.
10319 11:53:13.110678 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10320 11:53:13.113936 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10321 11:53:13.120386 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10322 11:53:13.123572 [ 0.000000] psci: SMC Calling Convention v1.2
10323 11:53:13.130492 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10324 11:53:13.133729 [ 0.000000] Detected VIPT I-cache on CPU0
10325 11:53:13.140104 [ 0.000000] CPU features: detected: GIC system register CPU interface
10326 11:53:13.146805 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10327 11:53:13.153252 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10328 11:53:13.159979 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10329 11:53:13.170222 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10330 11:53:13.177235 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10331 11:53:13.179897 [ 0.000000] alternatives: applying boot alternatives
10332 11:53:13.186821 [ 0.000000] Fallback order for Node 0: 0
10333 11:53:13.193104 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10334 11:53:13.196102 [ 0.000000] Policy zone: Normal
10335 11:53:13.219148 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10336 11:53:13.229023 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10337 11:53:13.240685 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10338 11:53:13.250050 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10339 11:53:13.256849 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10340 11:53:13.259928 <6>[ 0.000000] software IO TLB: area num 8.
10341 11:53:13.317274 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10342 11:53:13.466610 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10343 11:53:13.473430 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10344 11:53:13.480048 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10345 11:53:13.483750 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10346 11:53:13.489427 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10347 11:53:13.496838 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10348 11:53:13.499714 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10349 11:53:13.509409 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10350 11:53:13.516193 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10351 11:53:13.522646 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10352 11:53:13.529640 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10353 11:53:13.532954 <6>[ 0.000000] GICv3: 608 SPIs implemented
10354 11:53:13.535907 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10355 11:53:13.542570 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10356 11:53:13.545503 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10357 11:53:13.552467 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10358 11:53:13.565238 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10359 11:53:13.578744 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10360 11:53:13.584969 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10361 11:53:13.593234 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10362 11:53:13.606607 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10363 11:53:13.613586 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10364 11:53:13.619899 <6>[ 0.009182] Console: colour dummy device 80x25
10365 11:53:13.629702 <6>[ 0.013908] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10366 11:53:13.636201 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10367 11:53:13.639469 <6>[ 0.029251] LSM: Security Framework initializing
10368 11:53:13.646055 <6>[ 0.034218] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10369 11:53:13.656581 <6>[ 0.042030] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10370 11:53:13.665700 <6>[ 0.051443] cblist_init_generic: Setting adjustable number of callback queues.
10371 11:53:13.669107 <6>[ 0.058886] cblist_init_generic: Setting shift to 3 and lim to 1.
10372 11:53:13.679204 <6>[ 0.065224] cblist_init_generic: Setting adjustable number of callback queues.
10373 11:53:13.685896 <6>[ 0.072651] cblist_init_generic: Setting shift to 3 and lim to 1.
10374 11:53:13.689047 <6>[ 0.079050] rcu: Hierarchical SRCU implementation.
10375 11:53:13.695901 <6>[ 0.084096] rcu: Max phase no-delay instances is 1000.
10376 11:53:13.702134 <6>[ 0.091156] EFI services will not be available.
10377 11:53:13.705484 <6>[ 0.096104] smp: Bringing up secondary CPUs ...
10378 11:53:13.713845 <6>[ 0.101149] Detected VIPT I-cache on CPU1
10379 11:53:13.720841 <6>[ 0.101218] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10380 11:53:13.727365 <6>[ 0.101249] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10381 11:53:13.730469 <6>[ 0.101591] Detected VIPT I-cache on CPU2
10382 11:53:13.740336 <6>[ 0.101644] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10383 11:53:13.746910 <6>[ 0.101662] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10384 11:53:13.750295 <6>[ 0.101927] Detected VIPT I-cache on CPU3
10385 11:53:13.757366 <6>[ 0.101974] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10386 11:53:13.764155 <6>[ 0.101989] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10387 11:53:13.767232 <6>[ 0.102290] CPU features: detected: Spectre-v4
10388 11:53:13.773874 <6>[ 0.102297] CPU features: detected: Spectre-BHB
10389 11:53:13.776860 <6>[ 0.102302] Detected PIPT I-cache on CPU4
10390 11:53:13.783903 <6>[ 0.102359] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10391 11:53:13.790234 <6>[ 0.102375] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10392 11:53:13.796578 <6>[ 0.102673] Detected PIPT I-cache on CPU5
10393 11:53:13.803322 <6>[ 0.102736] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10394 11:53:13.809930 <6>[ 0.102752] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10395 11:53:13.813048 <6>[ 0.103034] Detected PIPT I-cache on CPU6
10396 11:53:13.820156 <6>[ 0.103097] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10397 11:53:13.826793 <6>[ 0.103114] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10398 11:53:13.833143 <6>[ 0.103410] Detected PIPT I-cache on CPU7
10399 11:53:13.839935 <6>[ 0.103474] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10400 11:53:13.846149 <6>[ 0.103490] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10401 11:53:13.849295 <6>[ 0.103537] smp: Brought up 1 node, 8 CPUs
10402 11:53:13.856006 <6>[ 0.244930] SMP: Total of 8 processors activated.
10403 11:53:13.859244 <6>[ 0.249850] CPU features: detected: 32-bit EL0 Support
10404 11:53:13.869496 <6>[ 0.255246] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10405 11:53:13.876065 <6>[ 0.264046] CPU features: detected: Common not Private translations
10406 11:53:13.882182 <6>[ 0.270522] CPU features: detected: CRC32 instructions
10407 11:53:13.888913 <6>[ 0.275906] CPU features: detected: RCpc load-acquire (LDAPR)
10408 11:53:13.892316 <6>[ 0.281903] CPU features: detected: LSE atomic instructions
10409 11:53:13.898927 <6>[ 0.287684] CPU features: detected: Privileged Access Never
10410 11:53:13.905667 <6>[ 0.293499] CPU features: detected: RAS Extension Support
10411 11:53:13.912061 <6>[ 0.299108] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10412 11:53:13.915467 <6>[ 0.306325] CPU: All CPU(s) started at EL2
10413 11:53:13.922011 <6>[ 0.310642] alternatives: applying system-wide alternatives
10414 11:53:13.932150 <6>[ 0.321327] devtmpfs: initialized
10415 11:53:13.947427 <6>[ 0.330194] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10416 11:53:13.953635 <6>[ 0.340156] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10417 11:53:13.960394 <6>[ 0.348352] pinctrl core: initialized pinctrl subsystem
10418 11:53:13.963610 <6>[ 0.355021] DMI not present or invalid.
10419 11:53:13.970130 <6>[ 0.359431] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10420 11:53:13.980297 <6>[ 0.366314] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10421 11:53:13.987000 <6>[ 0.373894] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10422 11:53:13.996776 <6>[ 0.382119] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10423 11:53:13.999992 <6>[ 0.390361] audit: initializing netlink subsys (disabled)
10424 11:53:14.010154 <5>[ 0.396053] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10425 11:53:14.016919 <6>[ 0.396748] thermal_sys: Registered thermal governor 'step_wise'
10426 11:53:14.023017 <6>[ 0.404021] thermal_sys: Registered thermal governor 'power_allocator'
10427 11:53:14.026290 <6>[ 0.410274] cpuidle: using governor menu
10428 11:53:14.032856 <6>[ 0.421235] NET: Registered PF_QIPCRTR protocol family
10429 11:53:14.039451 <6>[ 0.426734] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10430 11:53:14.046350 <6>[ 0.433837] ASID allocator initialised with 32768 entries
10431 11:53:14.049359 <6>[ 0.440395] Serial: AMBA PL011 UART driver
10432 11:53:14.059551 <4>[ 0.449179] Trying to register duplicate clock ID: 134
10433 11:53:14.113992 <6>[ 0.506761] KASLR enabled
10434 11:53:14.128007 <6>[ 0.514441] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10435 11:53:14.135081 <6>[ 0.521455] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10436 11:53:14.141677 <6>[ 0.527943] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10437 11:53:14.148670 <6>[ 0.534948] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10438 11:53:14.155028 <6>[ 0.541437] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10439 11:53:14.161206 <6>[ 0.548445] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10440 11:53:14.167648 <6>[ 0.554933] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10441 11:53:14.175637 <6>[ 0.561939] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10442 11:53:14.178039 <6>[ 0.569426] ACPI: Interpreter disabled.
10443 11:53:14.187119 <6>[ 0.575809] iommu: Default domain type: Translated
10444 11:53:14.193384 <6>[ 0.580921] iommu: DMA domain TLB invalidation policy: strict mode
10445 11:53:14.196419 <5>[ 0.587575] SCSI subsystem initialized
10446 11:53:14.203460 <6>[ 0.591736] usbcore: registered new interface driver usbfs
10447 11:53:14.209102 <6>[ 0.597467] usbcore: registered new interface driver hub
10448 11:53:14.212462 <6>[ 0.603020] usbcore: registered new device driver usb
10449 11:53:14.220132 <6>[ 0.609119] pps_core: LinuxPPS API ver. 1 registered
10450 11:53:14.229308 <6>[ 0.614314] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10451 11:53:14.233249 <6>[ 0.623666] PTP clock support registered
10452 11:53:14.236160 <6>[ 0.627908] EDAC MC: Ver: 3.0.0
10453 11:53:14.243414 <6>[ 0.633055] FPGA manager framework
10454 11:53:14.250128 <6>[ 0.636733] Advanced Linux Sound Architecture Driver Initialized.
10455 11:53:14.253352 <6>[ 0.643498] vgaarb: loaded
10456 11:53:14.259947 <6>[ 0.646680] clocksource: Switched to clocksource arch_sys_counter
10457 11:53:14.263707 <5>[ 0.653108] VFS: Disk quotas dquot_6.6.0
10458 11:53:14.269919 <6>[ 0.657293] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10459 11:53:14.273407 <6>[ 0.664479] pnp: PnP ACPI: disabled
10460 11:53:14.281729 <6>[ 0.671075] NET: Registered PF_INET protocol family
10461 11:53:14.291508 <6>[ 0.676658] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10462 11:53:14.302674 <6>[ 0.688956] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10463 11:53:14.312546 <6>[ 0.697770] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10464 11:53:14.319375 <6>[ 0.705738] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10465 11:53:14.329519 <6>[ 0.714439] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10466 11:53:14.335931 <6>[ 0.724185] TCP: Hash tables configured (established 65536 bind 65536)
10467 11:53:14.342582 <6>[ 0.731043] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10468 11:53:14.352312 <6>[ 0.738243] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10469 11:53:14.358788 <6>[ 0.745937] NET: Registered PF_UNIX/PF_LOCAL protocol family
10470 11:53:14.365589 <6>[ 0.752035] RPC: Registered named UNIX socket transport module.
10471 11:53:14.368647 <6>[ 0.758187] RPC: Registered udp transport module.
10472 11:53:14.375204 <6>[ 0.763121] RPC: Registered tcp transport module.
10473 11:53:14.381762 <6>[ 0.768050] RPC: Registered tcp NFSv4.1 backchannel transport module.
10474 11:53:14.385181 <6>[ 0.774719] PCI: CLS 0 bytes, default 64
10475 11:53:14.388297 <6>[ 0.779107] Unpacking initramfs...
10476 11:53:14.405000 <6>[ 0.791274] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10477 11:53:14.414773 <6>[ 0.799940] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10478 11:53:14.418654 <6>[ 0.808799] kvm [1]: IPA Size Limit: 40 bits
10479 11:53:14.425021 <6>[ 0.813332] kvm [1]: GICv3: no GICV resource entry
10480 11:53:14.428253 <6>[ 0.818358] kvm [1]: disabling GICv2 emulation
10481 11:53:14.434920 <6>[ 0.823047] kvm [1]: GIC system register CPU interface enabled
10482 11:53:14.438413 <6>[ 0.829212] kvm [1]: vgic interrupt IRQ18
10483 11:53:14.444892 <6>[ 0.833572] kvm [1]: VHE mode initialized successfully
10484 11:53:14.450985 <5>[ 0.840110] Initialise system trusted keyrings
10485 11:53:14.457663 <6>[ 0.844932] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10486 11:53:14.465716 <6>[ 0.854885] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10487 11:53:14.472095 <5>[ 0.861274] NFS: Registering the id_resolver key type
10488 11:53:14.475413 <5>[ 0.866576] Key type id_resolver registered
10489 11:53:14.481844 <5>[ 0.870990] Key type id_legacy registered
10490 11:53:14.488943 <6>[ 0.875267] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10491 11:53:14.494962 <6>[ 0.882186] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10492 11:53:14.501553 <6>[ 0.889908] 9p: Installing v9fs 9p2000 file system support
10493 11:53:14.538668 <5>[ 0.927849] Key type asymmetric registered
10494 11:53:14.541616 <5>[ 0.932180] Asymmetric key parser 'x509' registered
10495 11:53:14.551912 <6>[ 0.937322] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10496 11:53:14.554815 <6>[ 0.944935] io scheduler mq-deadline registered
10497 11:53:14.558477 <6>[ 0.949714] io scheduler kyber registered
10498 11:53:14.577215 <6>[ 0.966844] EINJ: ACPI disabled.
10499 11:53:14.609982 <4>[ 0.992754] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10500 11:53:14.619585 <4>[ 1.003364] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10501 11:53:14.634661 <6>[ 1.024276] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10502 11:53:14.642538 <6>[ 1.032263] printk: console [ttyS0] disabled
10503 11:53:14.670663 <6>[ 1.056899] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10504 11:53:14.677317 <6>[ 1.066383] printk: console [ttyS0] enabled
10505 11:53:14.680290 <6>[ 1.066383] printk: console [ttyS0] enabled
10506 11:53:14.686999 <6>[ 1.075277] printk: bootconsole [mtk8250] disabled
10507 11:53:14.690147 <6>[ 1.075277] printk: bootconsole [mtk8250] disabled
10508 11:53:14.697151 <6>[ 1.086508] SuperH (H)SCI(F) driver initialized
10509 11:53:14.700658 <6>[ 1.091770] msm_serial: driver initialized
10510 11:53:14.714396 <6>[ 1.100761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10511 11:53:14.724516 <6>[ 1.109311] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10512 11:53:14.731354 <6>[ 1.117853] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10513 11:53:14.741002 <6>[ 1.126483] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10514 11:53:14.750830 <6>[ 1.135196] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10515 11:53:14.757586 <6>[ 1.143910] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10516 11:53:14.767691 <6>[ 1.152451] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10517 11:53:14.773752 <6>[ 1.161253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10518 11:53:14.784104 <6>[ 1.169800] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10519 11:53:14.796317 <6>[ 1.185297] loop: module loaded
10520 11:53:14.802769 <6>[ 1.191373] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10521 11:53:14.825838 <4>[ 1.214688] mtk-pmic-keys: Failed to locate of_node [id: -1]
10522 11:53:14.832011 <6>[ 1.221469] megasas: 07.719.03.00-rc1
10523 11:53:14.841213 <6>[ 1.231049] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10524 11:53:14.848953 <6>[ 1.238049] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10525 11:53:14.865302 <6>[ 1.254751] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10526 11:53:14.922437 <6>[ 1.304724] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10527 11:53:15.135998 <6>[ 1.525839] Freeing initrd memory: 17372K
10528 11:53:15.146686 <6>[ 1.536348] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10529 11:53:15.157840 <6>[ 1.547228] tun: Universal TUN/TAP device driver, 1.6
10530 11:53:15.161049 <6>[ 1.553288] thunder_xcv, ver 1.0
10531 11:53:15.164443 <6>[ 1.556793] thunder_bgx, ver 1.0
10532 11:53:15.167936 <6>[ 1.560289] nicpf, ver 1.0
10533 11:53:15.177763 <6>[ 1.564297] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10534 11:53:15.181395 <6>[ 1.571772] hns3: Copyright (c) 2017 Huawei Corporation.
10535 11:53:15.188290 <6>[ 1.577359] hclge is initializing
10536 11:53:15.191122 <6>[ 1.580939] e1000: Intel(R) PRO/1000 Network Driver
10537 11:53:15.197829 <6>[ 1.586068] e1000: Copyright (c) 1999-2006 Intel Corporation.
10538 11:53:15.201172 <6>[ 1.592083] e1000e: Intel(R) PRO/1000 Network Driver
10539 11:53:15.208005 <6>[ 1.597299] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10540 11:53:15.215093 <6>[ 1.603483] igb: Intel(R) Gigabit Ethernet Network Driver
10541 11:53:15.221493 <6>[ 1.609132] igb: Copyright (c) 2007-2014 Intel Corporation.
10542 11:53:15.227457 <6>[ 1.614967] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10543 11:53:15.234347 <6>[ 1.621484] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10544 11:53:15.237606 <6>[ 1.627948] sky2: driver version 1.30
10545 11:53:15.244327 <6>[ 1.632941] VFIO - User Level meta-driver version: 0.3
10546 11:53:15.252032 <6>[ 1.641158] usbcore: registered new interface driver usb-storage
10547 11:53:15.258028 <6>[ 1.647598] usbcore: registered new device driver onboard-usb-hub
10548 11:53:15.267456 <6>[ 1.656771] mt6397-rtc mt6359-rtc: registered as rtc0
10549 11:53:15.276919 <6>[ 1.662239] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:53:16 UTC (1700740396)
10550 11:53:15.280921 <6>[ 1.671806] i2c_dev: i2c /dev entries driver
10551 11:53:15.296890 <6>[ 1.683487] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10552 11:53:15.316717 <6>[ 1.706467] cpu cpu0: EM: created perf domain
10553 11:53:15.320260 <6>[ 1.711386] cpu cpu4: EM: created perf domain
10554 11:53:15.327472 <6>[ 1.716951] sdhci: Secure Digital Host Controller Interface driver
10555 11:53:15.334117 <6>[ 1.723384] sdhci: Copyright(c) Pierre Ossman
10556 11:53:15.340515 <6>[ 1.728346] Synopsys Designware Multimedia Card Interface Driver
10557 11:53:15.347304 <6>[ 1.734986] sdhci-pltfm: SDHCI platform and OF driver helper
10558 11:53:15.350509 <6>[ 1.735030] mmc0: CQHCI version 5.10
10559 11:53:15.357403 <6>[ 1.745226] ledtrig-cpu: registered to indicate activity on CPUs
10560 11:53:15.363820 <6>[ 1.752270] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10561 11:53:15.370724 <6>[ 1.759329] usbcore: registered new interface driver usbhid
10562 11:53:15.374094 <6>[ 1.765153] usbhid: USB HID core driver
10563 11:53:15.380478 <6>[ 1.769347] spi_master spi0: will run message pump with realtime priority
10564 11:53:15.430555 <6>[ 1.813773] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10565 11:53:15.450734 <6>[ 1.830120] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10566 11:53:15.454487 <6>[ 1.843703] mmc0: Command Queue Engine enabled
10567 11:53:15.460972 <6>[ 1.846096] cros-ec-spi spi0.0: Chrome EC device registered
10568 11:53:15.468110 <6>[ 1.848439] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10569 11:53:15.471238 <6>[ 1.861470] mmcblk0: mmc0:0001 DA4128 116 GiB
10570 11:53:15.482442 <6>[ 1.868527] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10571 11:53:15.488697 <6>[ 1.871625] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10572 11:53:15.495960 <6>[ 1.878994] NET: Registered PF_PACKET protocol family
10573 11:53:15.499013 <6>[ 1.885246] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10574 11:53:15.505222 <6>[ 1.889170] 9pnet: Installing 9P2000 support
10575 11:53:15.508613 <6>[ 1.894950] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10576 11:53:15.515288 <5>[ 1.898842] Key type dns_resolver registered
10577 11:53:15.522205 <6>[ 1.904724] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10578 11:53:15.525509 <6>[ 1.908964] registered taskstats version 1
10579 11:53:15.528856 <5>[ 1.919445] Loading compiled-in X.509 certificates
10580 11:53:15.560649 <4>[ 1.943525] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10581 11:53:15.570688 <4>[ 1.954270] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10582 11:53:15.577234 <3>[ 1.964802] debugfs: File 'uA_load' in directory '/' already present!
10583 11:53:15.583842 <3>[ 1.971503] debugfs: File 'min_uV' in directory '/' already present!
10584 11:53:15.590552 <3>[ 1.978169] debugfs: File 'max_uV' in directory '/' already present!
10585 11:53:15.596852 <3>[ 1.984780] debugfs: File 'constraint_flags' in directory '/' already present!
10586 11:53:15.610238 <3>[ 1.996772] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10587 11:53:15.623105 <6>[ 2.012511] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10588 11:53:15.629948 <6>[ 2.019425] xhci-mtk 11200000.usb: xHCI Host Controller
10589 11:53:15.637120 <6>[ 2.024939] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10590 11:53:15.646969 <6>[ 2.032779] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10591 11:53:15.652727 <6>[ 2.042189] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10592 11:53:15.659584 <6>[ 2.048256] xhci-mtk 11200000.usb: xHCI Host Controller
10593 11:53:15.666678 <6>[ 2.053733] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10594 11:53:15.673708 <6>[ 2.061381] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10595 11:53:15.679393 <6>[ 2.068997] hub 1-0:1.0: USB hub found
10596 11:53:15.682747 <6>[ 2.073008] hub 1-0:1.0: 1 port detected
10597 11:53:15.689401 <6>[ 2.077308] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10598 11:53:15.696134 <6>[ 2.085817] hub 2-0:1.0: USB hub found
10599 11:53:15.699654 <6>[ 2.089822] hub 2-0:1.0: 1 port detected
10600 11:53:15.707437 <6>[ 2.096940] mtk-msdc 11f70000.mmc: Got CD GPIO
10601 11:53:15.719572 <6>[ 2.105670] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10602 11:53:15.726034 <6>[ 2.113698] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10603 11:53:15.736104 <4>[ 2.121627] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10604 11:53:15.745896 <6>[ 2.131169] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10605 11:53:15.752568 <6>[ 2.139268] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10606 11:53:15.758866 <6>[ 2.147402] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10607 11:53:15.769359 <6>[ 2.155357] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10608 11:53:15.776298 <6>[ 2.163176] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10609 11:53:15.785614 <6>[ 2.170994] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10610 11:53:15.795615 <6>[ 2.181416] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10611 11:53:15.802109 <6>[ 2.189777] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10612 11:53:15.812541 <6>[ 2.198117] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10613 11:53:15.818710 <6>[ 2.206455] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10614 11:53:15.829145 <6>[ 2.214794] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10615 11:53:15.835372 <6>[ 2.223132] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10616 11:53:15.845066 <6>[ 2.231471] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10617 11:53:15.855431 <6>[ 2.239811] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10618 11:53:15.862095 <6>[ 2.248150] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10619 11:53:15.871905 <6>[ 2.256494] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10620 11:53:15.878688 <6>[ 2.264847] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10621 11:53:15.888075 <6>[ 2.273186] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10622 11:53:15.895441 <6>[ 2.281527] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10623 11:53:15.905270 <6>[ 2.289867] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10624 11:53:15.911162 <6>[ 2.298206] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10625 11:53:15.918348 <6>[ 2.306942] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10626 11:53:15.924734 <6>[ 2.314107] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10627 11:53:15.932007 <6>[ 2.320866] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10628 11:53:15.940914 <6>[ 2.327613] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10629 11:53:15.947653 <6>[ 2.334553] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10630 11:53:15.954311 <6>[ 2.341394] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10631 11:53:15.964778 <6>[ 2.350520] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10632 11:53:15.974559 <6>[ 2.359639] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10633 11:53:15.984445 <6>[ 2.368933] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10634 11:53:15.993887 <6>[ 2.378404] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10635 11:53:16.004246 <6>[ 2.387875] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10636 11:53:16.010712 <6>[ 2.396998] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10637 11:53:16.020774 <6>[ 2.406465] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10638 11:53:16.030292 <6>[ 2.415582] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10639 11:53:16.040526 <6>[ 2.424875] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10640 11:53:16.050264 <6>[ 2.435036] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10641 11:53:16.060016 <6>[ 2.446626] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10642 11:53:16.066670 <6>[ 2.456333] Trying to probe devices needed for running init ...
10643 11:53:16.088854 <6>[ 2.475192] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10644 11:53:16.117226 <6>[ 2.506809] hub 2-1:1.0: USB hub found
10645 11:53:16.120517 <6>[ 2.511293] hub 2-1:1.0: 3 ports detected
10646 11:53:16.128567 <6>[ 2.518222] hub 2-1:1.0: USB hub found
10647 11:53:16.131889 <6>[ 2.522550] hub 2-1:1.0: 3 ports detected
10648 11:53:16.241000 <6>[ 2.626962] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10649 11:53:16.395049 <6>[ 2.784618] hub 1-1:1.0: USB hub found
10650 11:53:16.397951 <6>[ 2.789049] hub 1-1:1.0: 4 ports detected
10651 11:53:16.407919 <6>[ 2.797145] hub 1-1:1.0: USB hub found
10652 11:53:16.410698 <6>[ 2.801541] hub 1-1:1.0: 4 ports detected
10653 11:53:16.480635 <6>[ 2.867205] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10654 11:53:16.732213 <6>[ 3.118934] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10655 11:53:16.864979 <6>[ 3.254988] hub 1-1.4:1.0: USB hub found
10656 11:53:16.868773 <6>[ 3.259658] hub 1-1.4:1.0: 2 ports detected
10657 11:53:16.878116 <6>[ 3.267977] hub 1-1.4:1.0: USB hub found
10658 11:53:16.881459 <6>[ 3.272569] hub 1-1.4:1.0: 2 ports detected
10659 11:53:17.180443 <6>[ 3.566997] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10660 11:53:17.372304 <6>[ 3.758964] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10661 11:53:28.341892 <6>[ 14.735953] ALSA device list:
10662 11:53:28.347996 <6>[ 14.739248] No soundcards found.
10663 11:53:28.356425 <6>[ 14.747159] Freeing unused kernel memory: 8384K
10664 11:53:28.359164 <6>[ 14.752143] Run /init as init process
10665 11:53:28.370694 Loading, please wait...
10666 11:53:28.391217 Starting version 247.3-7+deb11u2
10667 11:53:28.583953 <6>[ 14.971808] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10668 11:53:28.596171 <3>[ 14.982902] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10669 11:53:28.601548 <6>[ 14.985174] remoteproc remoteproc0: scp is available
10670 11:53:28.608816 <3>[ 14.991241] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10671 11:53:28.618052 <3>[ 14.991273] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10672 11:53:28.624739 <3>[ 14.991639] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10673 11:53:28.631358 <6>[ 14.999769] remoteproc remoteproc0: powering up scp
10674 11:53:28.638158 <6>[ 15.014636] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10675 11:53:28.644671 <3>[ 15.020260] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10676 11:53:28.654977 <3>[ 15.020276] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10677 11:53:28.661353 <3>[ 15.020377] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 11:53:28.670947 <3>[ 15.020389] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 11:53:28.677755 <6>[ 15.021801] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10680 11:53:28.687546 <3>[ 15.023579] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10681 11:53:28.694146 <3>[ 15.023801] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10682 11:53:28.704138 <3>[ 15.023815] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10683 11:53:28.710991 <3>[ 15.023829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10684 11:53:28.720655 <3>[ 15.024015] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10685 11:53:28.728301 <3>[ 15.024025] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10686 11:53:28.737066 <3>[ 15.024036] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10687 11:53:28.743662 <3>[ 15.024055] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10688 11:53:28.750124 <3>[ 15.024066] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10689 11:53:28.760747 <3>[ 15.024135] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10690 11:53:28.767241 <6>[ 15.027277] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10691 11:53:28.774121 <6>[ 15.034244] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10692 11:53:28.780950 <6>[ 15.034731] usbcore: registered new interface driver r8152
10693 11:53:28.790723 <6>[ 15.042338] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10694 11:53:28.797436 <6>[ 15.055128] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10695 11:53:28.800438 <6>[ 15.075452] mc: Linux media interface: v0.10
10696 11:53:28.807508 <6>[ 15.083826] usbcore: registered new interface driver cdc_ether
10697 11:53:28.817392 <4>[ 15.123793] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10698 11:53:28.820887 <4>[ 15.123793] Fallback method does not support PEC.
10699 11:53:28.827950 <6>[ 15.137835] videodev: Linux video capture interface: v2.00
10700 11:53:28.831069 <6>[ 15.137851] Bluetooth: Core ver 2.22
10701 11:53:28.837758 <6>[ 15.138069] NET: Registered PF_BLUETOOTH protocol family
10702 11:53:28.844572 <6>[ 15.138073] Bluetooth: HCI device and connection manager initialized
10703 11:53:28.847516 <6>[ 15.138107] Bluetooth: HCI socket layer initialized
10704 11:53:28.853752 <6>[ 15.138111] Bluetooth: L2CAP socket layer initialized
10705 11:53:28.857578 <6>[ 15.138125] Bluetooth: SCO socket layer initialized
10706 11:53:28.867415 <4>[ 15.138124] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10707 11:53:28.873830 <4>[ 15.138636] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10708 11:53:28.880453 <6>[ 15.143680] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10709 11:53:28.890793 <3>[ 15.159128] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10710 11:53:28.897146 <6>[ 15.175876] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10711 11:53:28.903441 <6>[ 15.175888] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10712 11:53:28.913566 <6>[ 15.180892] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10713 11:53:28.916649 <6>[ 15.185718] remoteproc remoteproc0: remote processor scp is now up
10714 11:53:28.926548 <4>[ 15.186239] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10715 11:53:28.936558 <4>[ 15.186257] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10716 11:53:28.944246 <6>[ 15.186554] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10717 11:53:28.953774 <6>[ 15.187768] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10718 11:53:28.956103 <6>[ 15.193171] pci_bus 0000:00: root bus resource [bus 00-ff]
10719 11:53:28.966587 <3>[ 15.217521] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 11:53:28.972789 <6>[ 15.223155] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10721 11:53:28.979414 <6>[ 15.231109] r8152 2-1.3:1.0 eth0: v1.12.13
10722 11:53:28.989156 <6>[ 15.232715] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10723 11:53:28.996227 <6>[ 15.246414] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10724 11:53:29.002576 <6>[ 15.249821] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10725 11:53:29.012616 <6>[ 15.263917] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10726 11:53:29.022181 <6>[ 15.269544] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10727 11:53:29.025913 <6>[ 15.269610] pci 0000:00:00.0: supports D1 D2
10728 11:53:29.035144 <6>[ 15.277160] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10729 11:53:29.042096 <6>[ 15.285579] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10730 11:53:29.048853 <6>[ 15.308369] usbcore: registered new interface driver r8153_ecm
10731 11:53:29.055104 <6>[ 15.315703] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10732 11:53:29.062015 <6>[ 15.337705] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10733 11:53:29.068677 <6>[ 15.339884] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10734 11:53:29.075023 <6>[ 15.354941] usbcore: registered new interface driver btusb
10735 11:53:29.081576 <6>[ 15.355390] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10736 11:53:29.091216 <4>[ 15.355953] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10737 11:53:29.098379 <3>[ 15.355961] Bluetooth: hci0: Failed to load firmware file (-2)
10738 11:53:29.101464 <3>[ 15.355962] Bluetooth: hci0: Failed to set up firmware (-2)
10739 11:53:29.114427 <4>[ 15.355964] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10740 11:53:29.124443 <6>[ 15.357166] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10741 11:53:29.131101 <6>[ 15.357374] usbcore: registered new interface driver uvcvideo
10742 11:53:29.138269 <6>[ 15.362511] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10743 11:53:29.144630 <6>[ 15.393596] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10744 11:53:29.154169 <6>[ 15.399421] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10745 11:53:29.161234 <6>[ 15.549460] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10746 11:53:29.164262 <6>[ 15.557039] pci 0000:01:00.0: supports D1 D2
10747 11:53:29.170880 <6>[ 15.561558] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10748 11:53:29.191339 <6>[ 15.578892] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10749 11:53:29.197467 <6>[ 15.585783] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10750 11:53:29.204222 <6>[ 15.593863] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10751 11:53:29.214143 <6>[ 15.601864] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10752 11:53:29.221400 <6>[ 15.609865] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10753 11:53:29.230863 <6>[ 15.617865] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10754 11:53:29.234178 <6>[ 15.625864] pci 0000:00:00.0: PCI bridge to [bus 01]
10755 11:53:29.244604 <6>[ 15.631080] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 11:53:29.250654 <6>[ 15.639189] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 11:53:29.257449 <6>[ 15.646031] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10758 11:53:29.263595 <6>[ 15.652736] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10759 11:53:29.285624 <5>[ 15.673342] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10760 11:53:29.305404 <5>[ 15.693355] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10761 11:53:29.312124 <4>[ 15.700315] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 11:53:29.318644 <6>[ 15.709217] cfg80211: failed to load regulatory.db
10763 11:53:29.379792 <6>[ 15.767375] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 11:53:29.386170 <6>[ 15.774934] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 11:53:29.410693 <6>[ 15.801678] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 11:53:29.518212 <4>[ 15.902921] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 11:53:29.526082 Begin: Loading essential drivers ... done.
10768 11:53:29.529822 Begin: Running /scripts/init-premount ... done.
10769 11:53:29.536329 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10770 11:53:29.546611 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10771 11:53:29.549480 Device /sys/class/net/enx002432307c7b found
10772 11:53:29.549588 done.
10773 11:53:29.606971 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10774 11:53:29.639167 <4>[ 16.023598] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 11:53:29.757981 <4>[ 16.142635] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 11:53:29.877642 <4>[ 16.262443] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:53:29.997793 <4>[ 16.382649] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 11:53:30.118231 <4>[ 16.502570] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 11:53:30.238410 <4>[ 16.622625] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 11:53:30.357537 <4>[ 16.742264] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 11:53:30.477790 <4>[ 16.862271] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 11:53:30.597515 <4>[ 16.982193] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 11:53:30.617952 <6>[ 17.009404] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10784 11:53:30.708925 <3>[ 17.100110] mt7921e 0000:01:00.0: hardware init failed
10785 11:53:30.771384 IP-Config: no response after 2 secs - giving up
10786 11:53:30.814651 IP-Config: enx002432307c7b hardware address 00:24:32:30:7c:7b mtu 1500 DHCP
10787 11:53:30.821263 IP-Config: enx002432307c7b complete (dhcp from 192.168.201.1):
10788 11:53:30.827814 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10789 11:53:30.834672 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10790 11:53:30.841358 host : mt8192-asurada-spherion-r0-cbg-2
10791 11:53:30.847755 domain : lava-rack
10792 11:53:30.854527 rootserver: 192.168.201.1 rootpath:
10793 11:53:30.854740 filename :
10794 11:53:30.909946 done.
10795 11:53:30.919450 Begin: Running /scripts/nfs-bottom ... done.
10796 11:53:30.939237 Begin: Running /scripts/init-bottom ... done.
10797 11:53:32.162707 <6>[ 18.553711] NET: Registered PF_INET6 protocol family
10798 11:53:32.169578 <6>[ 18.560928] Segment Routing with IPv6
10799 11:53:32.172714 <6>[ 18.564961] In-situ OAM (IOAM) with IPv6
10800 11:53:32.303654 <30>[ 18.675460] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10801 11:53:32.306994 <30>[ 18.699847] systemd[1]: Detected architecture arm64.
10802 11:53:32.329474
10803 11:53:32.333463 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10804 11:53:32.333561
10805 11:53:32.350038 <30>[ 18.741664] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10806 11:53:33.249883 <30>[ 19.637597] systemd[1]: Queued start job for default target Graphical Interface.
10807 11:53:33.289882 <30>[ 19.681344] systemd[1]: Created slice system-getty.slice.
10808 11:53:33.296297 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10809 11:53:33.312594 <30>[ 19.704303] systemd[1]: Created slice system-modprobe.slice.
10810 11:53:33.319745 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10811 11:53:33.338009 <30>[ 19.729064] systemd[1]: Created slice system-serial\x2dgetty.slice.
10812 11:53:33.348008 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10813 11:53:33.360346 <30>[ 19.752021] systemd[1]: Created slice User and Session Slice.
10814 11:53:33.367263 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10815 11:53:33.387445 <30>[ 19.775818] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10816 11:53:33.397255 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10817 11:53:33.415183 <30>[ 19.803630] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10818 11:53:33.421983 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10819 11:53:33.446397 <30>[ 19.831565] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10820 11:53:33.454495 <30>[ 19.843791] systemd[1]: Reached target Local Encrypted Volumes.
10821 11:53:33.459855 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10822 11:53:33.475588 <30>[ 19.867420] systemd[1]: Reached target Paths.
10823 11:53:33.478952 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10824 11:53:33.495258 <30>[ 19.886976] systemd[1]: Reached target Remote File Systems.
10825 11:53:33.501506 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10826 11:53:33.515505 <30>[ 19.906941] systemd[1]: Reached target Slices.
10827 11:53:33.521917 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10828 11:53:33.535522 <30>[ 19.926975] systemd[1]: Reached target Swap.
10829 11:53:33.538839 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10830 11:53:33.559205 <30>[ 19.947438] systemd[1]: Listening on initctl Compatibility Named Pipe.
10831 11:53:33.565690 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10832 11:53:33.573000 <30>[ 19.963560] systemd[1]: Listening on Journal Audit Socket.
10833 11:53:33.579317 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10834 11:53:33.596630 <30>[ 19.988350] systemd[1]: Listening on Journal Socket (/dev/log).
10835 11:53:33.603129 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10836 11:53:33.619621 <30>[ 20.011512] systemd[1]: Listening on Journal Socket.
10837 11:53:33.626453 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10838 11:53:33.645037 <30>[ 20.032829] systemd[1]: Listening on Network Service Netlink Socket.
10839 11:53:33.650716 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10840 11:53:33.666153 <30>[ 20.057891] systemd[1]: Listening on udev Control Socket.
10841 11:53:33.672679 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10842 11:53:33.687943 <30>[ 20.079411] systemd[1]: Listening on udev Kernel Socket.
10843 11:53:33.694122 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10844 11:53:33.747668 <30>[ 20.139046] systemd[1]: Mounting Huge Pages File System...
10845 11:53:33.753831 Mounting [0;1;39mHuge Pages File System[0m...
10846 11:53:33.771192 <30>[ 20.163135] systemd[1]: Mounting POSIX Message Queue File System...
10847 11:53:33.777991 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10848 11:53:33.828866 <30>[ 20.219377] systemd[1]: Mounting Kernel Debug File System...
10849 11:53:33.834073 Mounting [0;1;39mKernel Debug File System[0m...
10850 11:53:33.851086 <30>[ 20.239428] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10851 11:53:33.863840 <30>[ 20.252209] systemd[1]: Starting Create list of static device nodes for the current kernel...
10852 11:53:33.870778 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10853 11:53:33.892392 <30>[ 20.284001] systemd[1]: Starting Load Kernel Module configfs...
10854 11:53:33.898867 Starting [0;1;39mLoad Kernel Module configfs[0m...
10855 11:53:33.919785 <30>[ 20.311613] systemd[1]: Starting Load Kernel Module drm...
10856 11:53:33.926799 Starting [0;1;39mLoad Kernel Module drm[0m...
10857 11:53:33.944664 <30>[ 20.335576] systemd[1]: Starting Load Kernel Module fuse...
10858 11:53:33.950308 Starting [0;1;39mLoad Kernel Module fuse[0m...
10859 11:53:33.973605 <30>[ 20.361869] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10860 11:53:33.989207 <30>[ 20.380642] systemd[1]: Starting Journal Service...
10861 11:53:33.992495 <6>[ 20.380893] fuse: init (API version 7.37)
10862 11:53:33.999826 Starting [0;1;39mJournal Service[0m...
10863 11:53:34.052724 <30>[ 20.444115] systemd[1]: Starting Load Kernel Modules...
10864 11:53:34.059506 Starting [0;1;39mLoad Kernel Modules[0m...
10865 11:53:34.079629 <30>[ 20.468083] systemd[1]: Starting Remount Root and Kernel File Systems...
10866 11:53:34.086416 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10867 11:53:34.103687 <30>[ 20.495323] systemd[1]: Starting Coldplug All udev Devices...
10868 11:53:34.110352 Starting [0;1;39mColdplug All udev Devices[0m...
10869 11:53:34.121399 <3>[ 20.510089] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10870 11:53:34.134702 <30>[ 20.526069] systemd[1]: Mounted Huge Pages File System.
10871 11:53:34.141184 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10872 11:53:34.152512 <3>[ 20.540533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 11:53:34.158816 <30>[ 20.550107] systemd[1]: Mounted POSIX Message Queue File System.
10874 11:53:34.166161 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10875 11:53:34.180819 <30>[ 20.571489] systemd[1]: Mounted Kernel Debug File System.
10876 11:53:34.193991 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<3>[ 20.580826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10877 11:53:34.194113 g File System[0m.
10878 11:53:34.219743 <30>[ 20.608050] systemd[1]: Finished Create list of static device nodes for the current kernel.
10879 11:53:34.229482 <3>[ 20.613699] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 11:53:34.236526 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10881 11:53:34.252762 <30>[ 20.644249] systemd[1]: modprobe@configfs.service: Succeeded.
10882 11:53:34.263115 <3>[ 20.651472] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 11:53:34.269819 <30>[ 20.658010] systemd[1]: Finished Load Kernel Module configfs.
10884 11:53:34.276196 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10885 11:53:34.292510 <30>[ 20.683890] systemd[1]: modprobe@drm.service: Succeeded.
10886 11:53:34.302137 <3>[ 20.684310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 11:53:34.308736 <30>[ 20.690173] systemd[1]: Finished Load Kernel Module drm.
10888 11:53:34.312001 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10889 11:53:34.329126 <30>[ 20.720517] systemd[1]: modprobe@fuse.service: Succeeded.
10890 11:53:34.339509 <3>[ 20.723413] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 11:53:34.345452 <30>[ 20.728293] systemd[1]: Finished Load Kernel Module fuse.
10892 11:53:34.348834 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10893 11:53:34.369974 <30>[ 20.761734] systemd[1]: Finished Load Kernel Modules.
10894 11:53:34.379971 <3>[ 20.762288] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 11:53:34.386686 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10896 11:53:34.401750 <30>[ 20.793391] systemd[1]: Finished Remount Root and Kernel File Systems.
10897 11:53:34.411997 <3>[ 20.798328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 11:53:34.418447 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10899 11:53:34.445303 <3>[ 20.834056] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 11:53:34.484230 <30>[ 20.875508] systemd[1]: Mounting FUSE Control File System...
10901 11:53:34.490584 Mounting [0;1;39mFUSE Control File System[0m...
10902 11:53:34.509073 <30>[ 20.897587] systemd[1]: Mounting Kernel Configuration File System...
10903 11:53:34.512593 Mounting [0;1;39mKernel Configuration File System[0m...
10904 11:53:34.536105 <30>[ 20.924327] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10905 11:53:34.546022 <30>[ 20.933369] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10906 11:53:34.585055 <30>[ 20.976126] systemd[1]: Starting Load/Save Random Seed...
10907 11:53:34.591208 Starting [0;1;39mLoad/Save Random Seed[0m...
10908 11:53:34.608183 <30>[ 20.999781] systemd[1]: Starting Apply Kernel Variables...
10909 11:53:34.614546 Starting [0;1;39mApply Kernel Variables[0m...
10910 11:53:34.641446 <4>[ 21.023273] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10911 11:53:34.648838 <30>[ 21.023644] systemd[1]: Starting Create System Users...
10912 11:53:34.654720 <3>[ 21.039033] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10913 11:53:34.661383 Starting [0;1;39mCreate System Users[0m...
10914 11:53:34.677478 <30>[ 21.069245] systemd[1]: Started Journal Service.
10915 11:53:34.683825 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10916 11:53:34.704925 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10917 11:53:34.719824 See 'systemctl status systemd-udev-trigger.service' for details.
10918 11:53:34.735859 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10919 11:53:34.752199 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10920 11:53:34.773305 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10921 11:53:34.793013 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10922 11:53:34.808975 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10923 11:53:34.864245 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10924 11:53:34.881825 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10925 11:53:34.922774 <46>[ 21.311193] systemd-journald[305]: Received client request to flush runtime journal.
10926 11:53:34.963098 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10927 11:53:34.977391 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10928 11:53:34.991630 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10929 11:53:35.036694 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10930 11:53:36.327368 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10931 11:53:36.364079 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10932 11:53:36.422590 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10933 11:53:36.480727 Starting [0;1;39mNetwork Service[0m...
10934 11:53:36.795589 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10935 11:53:36.820669 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10936 11:53:36.875525 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10937 11:53:37.157656 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10938 11:53:37.174697 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10939 11:53:37.220096 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10940 11:53:37.240550 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10941 11:53:37.271646 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10942 11:53:37.302241 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10943 11:53:37.359999 Starting [0;1;39mNetwork Name Resolution[0m...
10944 11:53:37.389454 Starting [0;1;39mNetwork Time Synchronization[0m...
10945 11:53:37.408318 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10946 11:53:37.424446 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10947 11:53:37.468582 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10948 11:53:37.647484 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10949 11:53:37.663723 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10950 11:53:37.682524 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10951 11:53:37.695166 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10952 11:53:37.711312 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10953 11:53:37.836721 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10954 11:53:37.870818 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10955 11:53:37.910889 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10956 11:53:38.121512 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10957 11:53:38.135103 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10958 11:53:38.388615 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10959 11:53:38.403550 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10960 11:53:38.419300 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10961 11:53:38.475835 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10962 11:53:39.003486 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10963 11:53:39.092192 Starting [0;1;39mUser Login Management[0m...
10964 11:53:39.113399 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10965 11:53:39.142728 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10966 11:53:39.167079 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10967 11:53:39.208884 Starting [0;1;39mPermit User Sessions[0m...
10968 11:53:39.342298 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10969 11:53:39.380378 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10970 11:53:39.439384 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10971 11:53:39.461722 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10972 11:53:39.468526 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10973 11:53:39.484339 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10974 11:53:39.504657 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10975 11:53:39.519110 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10976 11:53:39.575712 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10977 11:53:39.622936 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10978 11:53:39.706522
10979 11:53:39.706679
10980 11:53:39.709454 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10981 11:53:39.709538
10982 11:53:39.713028 debian-bullseye-arm64 login: root (automatic login)
10983 11:53:39.713112
10984 11:53:39.713178
10985 11:53:40.105879 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
10986 11:53:40.106029
10987 11:53:40.112320 The programs included with the Debian GNU/Linux system are free software;
10988 11:53:40.119270 the exact distribution terms for each program are described in the
10989 11:53:40.122311 individual files in /usr/share/doc/*/copyright.
10990 11:53:40.122393
10991 11:53:40.129244 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10992 11:53:40.132650 permitted by applicable law.
10993 11:53:41.097971 Matched prompt #10: / #
10995 11:53:41.098281 Setting prompt string to ['/ #']
10996 11:53:41.098407 end: 2.2.5.1 login-action (duration 00:00:28) [common]
10998 11:53:41.098735 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
10999 11:53:41.098874 start: 2.2.6 expect-shell-connection (timeout 00:03:15) [common]
11000 11:53:41.098962 Setting prompt string to ['/ #']
11001 11:53:41.099055 Forcing a shell prompt, looking for ['/ #']
11003 11:53:41.149353 / #
11004 11:53:41.149545 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11005 11:53:41.149650 Waiting using forced prompt support (timeout 00:02:30)
11006 11:53:41.154604
11007 11:53:41.154926 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11008 11:53:41.155033 start: 2.2.7 export-device-env (timeout 00:03:15) [common]
11010 11:53:41.255385 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn'
11011 11:53:41.260906 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066519/extract-nfsrootfs-zty8zotn'
11013 11:53:41.361450 / # export NFS_SERVER_IP='192.168.201.1'
11014 11:53:41.366713 export NFS_SERVER_IP='192.168.201.1'
11015 11:53:41.367012 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11016 11:53:41.367116 end: 2.2 depthcharge-retry (duration 00:01:45) [common]
11017 11:53:41.367208 end: 2 depthcharge-action (duration 00:01:45) [common]
11018 11:53:41.367304 start: 3 lava-test-retry (timeout 00:07:26) [common]
11019 11:53:41.367392 start: 3.1 lava-test-shell (timeout 00:07:26) [common]
11020 11:53:41.367469 Using namespace: common
11022 11:53:41.467830 / # #
11023 11:53:41.468002 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11024 11:53:41.472807 #
11025 11:53:41.473075 Using /lava-12066519
11027 11:53:41.573423 / # export SHELL=/bin/bash
11028 11:53:41.578718 export SHELL=/bin/bash
11030 11:53:41.679290 / # . /lava-12066519/environment
11031 11:53:41.684371 . /lava-12066519/environment
11033 11:53:41.791386 / # /lava-12066519/bin/lava-test-runner /lava-12066519/0
11034 11:53:41.791542 Test shell timeout: 10s (minimum of the action and connection timeout)
11035 11:53:41.796622 /lava-12066519/bin/lava-test-runner /lava-12066519/0
11036 11:53:42.127217 + export TESTRUN_ID=0_timesync-off
11037 11:53:42.130383 + TESTRUN_ID=0_timesync-off
11038 11:53:42.134403 + cd /lava-12066519/0/tests/0_timesync-off
11039 11:53:42.137264 ++ cat uuid
11040 11:53:42.144994 + UUID=12066519_1.6.2.3.1
11041 11:53:42.145109 + set +x
11042 11:53:42.152221 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12066519_1.6.2.3.1>
11043 11:53:42.152504 Received signal: <STARTRUN> 0_timesync-off 12066519_1.6.2.3.1
11044 11:53:42.152590 Starting test lava.0_timesync-off (12066519_1.6.2.3.1)
11045 11:53:42.152680 Skipping test definition patterns.
11046 11:53:42.155259 + systemctl stop systemd-timesyncd
11047 11:53:42.217657 + set +x
11048 11:53:42.221366 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12066519_1.6.2.3.1>
11049 11:53:42.221645 Received signal: <ENDRUN> 0_timesync-off 12066519_1.6.2.3.1
11050 11:53:42.221737 Ending use of test pattern.
11051 11:53:42.221802 Ending test lava.0_timesync-off (12066519_1.6.2.3.1), duration 0.07
11053 11:53:42.315899 + export TESTRUN_ID=1_kselftest-tpm2
11054 11:53:42.319466 + TESTRUN_ID=1_kselftest-tpm2
11055 11:53:42.322668 + cd /lava-12066519/0/tests/1_kselftest-tpm2
11056 11:53:42.325409 ++ cat uuid
11057 11:53:42.333864 + UUID=12066519_1.6.2.3.5
11058 11:53:42.333985 + set +x
11059 11:53:42.340319 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12066519_1.6.2.3.5>
11060 11:53:42.340601 Received signal: <STARTRUN> 1_kselftest-tpm2 12066519_1.6.2.3.5
11061 11:53:42.340678 Starting test lava.1_kselftest-tpm2 (12066519_1.6.2.3.5)
11062 11:53:42.340763 Skipping test definition patterns.
11063 11:53:42.343613 + cd ./automated/linux/kselftest/
11064 11:53:42.370107 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11065 11:53:42.422757 INFO: install_deps skipped
11066 11:53:42.551771 --2023-11-23 11:53:42-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11067 11:53:42.582526 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11068 11:53:42.715646 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11069 11:53:42.848562 HTTP request sent, awaiting response... 200 OK
11070 11:53:42.852044 Length: 2962844 (2.8M) [application/octet-stream]
11071 11:53:42.855261 Saving to: 'kselftest.tar.xz'
11072 11:53:42.855358
11073 11:53:42.855425
11074 11:53:43.114868 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11075 11:53:43.398416 kselftest.tar.xz 1%[ ] 47.81K 181KB/s
11076 11:53:43.655464 kselftest.tar.xz 6%[> ] 193.46K 353KB/s
11077 11:53:43.923221 kselftest.tar.xz 19%[==> ] 552.63K 687KB/s
11078 11:53:44.189785 kselftest.tar.xz 29%[====> ] 860.89K 802KB/s
11079 11:53:44.456353 kselftest.tar.xz 41%[=======> ] 1.16M 886KB/s
11080 11:53:44.724358 kselftest.tar.xz 52%[=========> ] 1.49M 952KB/s
11081 11:53:44.960123 kselftest.tar.xz 65%[============> ] 1.84M 1006KB/s
11082 11:53:45.258270 kselftest.tar.xz 77%[==============> ] 2.20M 1.04MB/s
11083 11:53:45.524516 kselftest.tar.xz 89%[================> ] 2.54M 1.05MB/s
11084 11:53:45.531576 kselftest.tar.xz 99%[==================> ] 2.80M 1.05MB/s
11085 11:53:45.537429 kselftest.tar.xz 100%[===================>] 2.83M 1.05MB/s in 2.7s
11086 11:53:45.537633
11087 11:53:45.798944 2023-11-23 11:53:45 (1.05 MB/s) - 'kselftest.tar.xz' saved [2962844/2962844]
11088 11:53:45.799100
11089 11:53:52.524503 skiplist:
11090 11:53:52.527722 ========================================
11091 11:53:52.531302 ========================================
11092 11:53:52.588360 tpm2:test_smoke.sh
11093 11:53:52.591511 tpm2:test_space.sh
11094 11:53:52.609531 ============== Tests to run ===============
11095 11:53:52.612600 tpm2:test_smoke.sh
11096 11:53:52.612688 tpm2:test_space.sh
11097 11:53:52.616240 ===========End Tests to run ===============
11098 11:53:52.619294 shardfile-tpm2 pass
11099 11:53:52.740913 <12>[ 39.134948] kselftest: Running tests in tpm2
11100 11:53:52.752987 TAP version 13
11101 11:53:52.767666 1..2
11102 11:53:52.807930 # selftests: tpm2: test_smoke.sh
11103 11:53:54.269152 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11104 11:53:54.272395 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11105 11:53:54.279170 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11106 11:53:54.282477 # Traceback (most recent call last):
11107 11:53:54.292307 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11108 11:53:54.292780 # if self.tpm:
11109 11:53:54.299608 # AttributeError: 'Client' object has no attribute 'tpm'
11110 11:53:54.302247 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11111 11:53:54.309219 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11112 11:53:54.312177 # Traceback (most recent call last):
11113 11:53:54.321856 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11114 11:53:54.325560 # if self.tpm:
11115 11:53:54.328974 # AttributeError: 'Client' object has no attribute 'tpm'
11116 11:53:54.335407 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11117 11:53:54.342099 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11118 11:53:54.345206 # Traceback (most recent call last):
11119 11:53:54.354754 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11120 11:53:54.355147 # if self.tpm:
11121 11:53:54.362151 # AttributeError: 'Client' object has no attribute 'tpm'
11122 11:53:54.365257 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11123 11:53:54.371796 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11124 11:53:54.374803 # Traceback (most recent call last):
11125 11:53:54.384937 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11126 11:53:54.388255 # if self.tpm:
11127 11:53:54.391519 # AttributeError: 'Client' object has no attribute 'tpm'
11128 11:53:54.398336 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11129 11:53:54.402514 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11130 11:53:54.404621 # Traceback (most recent call last):
11131 11:53:54.414887 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11132 11:53:54.418065 # if self.tpm:
11133 11:53:54.421312 # AttributeError: 'Client' object has no attribute 'tpm'
11134 11:53:54.427764 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11135 11:53:54.434802 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11136 11:53:54.437898 # Traceback (most recent call last):
11137 11:53:54.448020 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11138 11:53:54.448513 # if self.tpm:
11139 11:53:54.454844 # AttributeError: 'Client' object has no attribute 'tpm'
11140 11:53:54.457802 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11141 11:53:54.464626 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11142 11:53:54.468098 # Traceback (most recent call last):
11143 11:53:54.477563 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11144 11:53:54.481310 # if self.tpm:
11145 11:53:54.484552 # AttributeError: 'Client' object has no attribute 'tpm'
11146 11:53:54.491068 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11147 11:53:54.497577 # Exception ignored in: <function Client.__del__ at 0xffff9be88d30>
11148 11:53:54.500745 # Traceback (most recent call last):
11149 11:53:54.511029 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11150 11:53:54.511545 # if self.tpm:
11151 11:53:54.517452 # AttributeError: 'Client' object has no attribute 'tpm'
11152 11:53:54.517880 #
11153 11:53:54.523995 # ======================================================================
11154 11:53:54.527476 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11155 11:53:54.533850 # ----------------------------------------------------------------------
11156 11:53:54.537210 # Traceback (most recent call last):
11157 11:53:54.547479 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11158 11:53:54.553792 # self.root_key = self.client.create_root_key()
11159 11:53:54.563939 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11160 11:53:54.570836 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11161 11:53:54.580201 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11162 11:53:54.583429 # raise ProtocolError(cc, rc)
11163 11:53:54.587630 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11164 11:53:54.588191 #
11165 11:53:54.593871 # ======================================================================
11166 11:53:54.603630 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11167 11:53:54.607913 # ----------------------------------------------------------------------
11168 11:53:54.610864 # Traceback (most recent call last):
11169 11:53:54.620517 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11170 11:53:54.623973 # self.client = tpm2.Client()
11171 11:53:54.633763 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11172 11:53:54.637220 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11173 11:53:54.643390 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11174 11:53:54.643899 #
11175 11:53:54.650009 # ======================================================================
11176 11:53:54.653645 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11177 11:53:54.660019 # ----------------------------------------------------------------------
11178 11:53:54.663211 # Traceback (most recent call last):
11179 11:53:54.673702 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11180 11:53:54.676849 # self.client = tpm2.Client()
11181 11:53:54.686632 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11182 11:53:54.693365 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11183 11:53:54.696614 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11184 11:53:54.697192 #
11185 11:53:54.703147 # ======================================================================
11186 11:53:54.709653 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11187 11:53:54.716153 # ----------------------------------------------------------------------
11188 11:53:54.719219 # Traceback (most recent call last):
11189 11:53:54.729271 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11190 11:53:54.729864 # self.client = tpm2.Client()
11191 11:53:54.739271 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11192 11:53:54.746239 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11193 11:53:54.752496 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11194 11:53:54.752921 #
11195 11:53:54.758944 # ======================================================================
11196 11:53:54.762600 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11197 11:53:54.769441 # ----------------------------------------------------------------------
11198 11:53:54.772374 # Traceback (most recent call last):
11199 11:53:54.782364 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11200 11:53:54.785530 # self.client = tpm2.Client()
11201 11:53:54.795904 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11202 11:53:54.802500 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11203 11:53:54.805219 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11204 11:53:54.805632 #
11205 11:53:54.811917 # ======================================================================
11206 11:53:54.818930 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11207 11:53:54.821921 # ----------------------------------------------------------------------
11208 11:53:54.825175 # Traceback (most recent call last):
11209 11:53:54.838885 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11210 11:53:54.839307 # self.client = tpm2.Client()
11211 11:53:54.848305 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11212 11:53:54.855297 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11213 11:53:54.858355 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11214 11:53:54.861584 #
11215 11:53:54.868178 # ======================================================================
11216 11:53:54.871661 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11217 11:53:54.878711 # ----------------------------------------------------------------------
11218 11:53:54.881615 # Traceback (most recent call last):
11219 11:53:54.891981 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11220 11:53:54.894735 # self.client = tpm2.Client()
11221 11:53:54.905193 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11222 11:53:54.908085 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11223 11:53:54.914495 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11224 11:53:54.914928 #
11225 11:53:54.921050 # ======================================================================
11226 11:53:54.924859 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11227 11:53:54.931285 # ----------------------------------------------------------------------
11228 11:53:54.934731 # Traceback (most recent call last):
11229 11:53:54.944764 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11230 11:53:54.948358 # self.client = tpm2.Client()
11231 11:53:54.959009 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11232 11:53:54.965080 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11233 11:53:54.967910 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11234 11:53:54.968506 #
11235 11:53:54.974414 # ======================================================================
11236 11:53:54.981024 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11237 11:53:54.987753 # ----------------------------------------------------------------------
11238 11:53:54.991113 # Traceback (most recent call last):
11239 11:53:55.000039 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11240 11:53:55.002717 # self.client = tpm2.Client()
11241 11:53:55.014430 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11242 11:53:55.019837 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11243 11:53:55.023011 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11244 11:53:55.023401 #
11245 11:53:55.030660 # ----------------------------------------------------------------------
11246 11:53:55.035861 # Ran 9 tests in 0.035s
11247 11:53:55.036247 #
11248 11:53:55.036556 # FAILED (errors=9)
11249 11:53:55.039497 # test_async (tpm2_tests.AsyncTest) ... ok
11250 11:53:55.043086 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11251 11:53:55.043474 #
11252 11:53:55.052492 # ----------------------------------------------------------------------
11253 11:53:55.052883 # Ran 2 tests in 0.032s
11254 11:53:55.053191 #
11255 11:53:55.055742 # OK
11256 11:53:55.056122 ok 1 selftests: tpm2: test_smoke.sh
11257 11:53:55.059061 # selftests: tpm2: test_space.sh
11258 11:53:55.066012 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11259 11:53:55.069028 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11260 11:53:55.072229 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11261 11:53:55.078852 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11262 11:53:55.079292 #
11263 11:53:55.085878 # ======================================================================
11264 11:53:55.088701 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11265 11:53:55.095618 # ----------------------------------------------------------------------
11266 11:53:55.099247 # Traceback (most recent call last):
11267 11:53:55.112396 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11268 11:53:55.115688 # root1 = space1.create_root_key()
11269 11:53:55.125656 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11270 11:53:55.129039 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11271 11:53:55.138522 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11272 11:53:55.142108 # raise ProtocolError(cc, rc)
11273 11:53:55.148828 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11274 11:53:55.149424 #
11275 11:53:55.155504 # ======================================================================
11276 11:53:55.162060 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11277 11:53:55.165216 # ----------------------------------------------------------------------
11278 11:53:55.169158 # Traceback (most recent call last):
11279 11:53:55.181963 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11280 11:53:55.185124 # space1.create_root_key()
11281 11:53:55.194837 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11282 11:53:55.201731 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11283 11:53:55.208529 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11284 11:53:55.211629 # raise ProtocolError(cc, rc)
11285 11:53:55.218968 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11286 11:53:55.219352 #
11287 11:53:55.225091 # ======================================================================
11288 11:53:55.232194 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11289 11:53:55.238004 # ----------------------------------------------------------------------
11290 11:53:55.241521 # Traceback (most recent call last):
11291 11:53:55.251522 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11292 11:53:55.254712 # root1 = space1.create_root_key()
11293 11:53:55.264530 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11294 11:53:55.271214 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11295 11:53:55.281377 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11296 11:53:55.284566 # raise ProtocolError(cc, rc)
11297 11:53:55.291167 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11298 11:53:55.291667 #
11299 11:53:55.297584 # ======================================================================
11300 11:53:55.301596 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11301 11:53:55.307856 # ----------------------------------------------------------------------
11302 11:53:55.311249 # Traceback (most recent call last):
11303 11:53:55.320950 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11304 11:53:55.324321 # root1 = space1.create_root_key()
11305 11:53:55.337489 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11306 11:53:55.340549 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11307 11:53:55.350492 # File "/lava-12066519/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11308 11:53:55.354179 # raise ProtocolError(cc, rc)
11309 11:53:55.360632 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11310 11:53:55.360848 #
11311 11:53:55.366635 # ----------------------------------------------------------------------
11312 11:53:55.369994 # Ran 4 tests in 0.070s
11313 11:53:55.370069 #
11314 11:53:55.370132 # FAILED (errors=4)
11315 11:53:55.376602 not ok 2 selftests: tpm2: test_space.sh # exit=1
11316 11:53:55.376679 tpm2_test_smoke_sh pass
11317 11:53:55.379831 tpm2_test_space_sh fail
11318 11:53:55.383298 + ../../utils/send-to-lava.sh ./output/result.txt
11319 11:53:55.390458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11320 11:53:55.390731 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11322 11:53:55.414714 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11323 11:53:55.414974 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11325 11:53:55.472794 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11326 11:53:55.473066 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11328 11:53:55.476239 + set +x
11329 11:53:55.479539 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12066519_1.6.2.3.5>
11330 11:53:55.479794 Received signal: <ENDRUN> 1_kselftest-tpm2 12066519_1.6.2.3.5
11331 11:53:55.479873 Ending use of test pattern.
11332 11:53:55.479936 Ending test lava.1_kselftest-tpm2 (12066519_1.6.2.3.5), duration 13.14
11334 11:53:55.482933 <LAVA_TEST_RUNNER EXIT>
11335 11:53:55.483184 ok: lava_test_shell seems to have completed
11336 11:53:55.483293 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11337 11:53:55.483382 end: 3.1 lava-test-shell (duration 00:00:14) [common]
11338 11:53:55.483466 end: 3 lava-test-retry (duration 00:00:14) [common]
11339 11:53:55.483550 start: 4 finalize (timeout 00:07:12) [common]
11340 11:53:55.483653 start: 4.1 power-off (timeout 00:00:30) [common]
11341 11:53:55.483815 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11342 11:53:55.563838 >> Command sent successfully.
11343 11:53:55.566649 Returned 0 in 0 seconds
11344 11:53:55.667017 end: 4.1 power-off (duration 00:00:00) [common]
11346 11:53:55.667335 start: 4.2 read-feedback (timeout 00:07:12) [common]
11347 11:53:55.667602 Listened to connection for namespace 'common' for up to 1s
11348 11:53:56.668520 Finalising connection for namespace 'common'
11349 11:53:56.668692 Disconnecting from shell: Finalise
11350 11:53:56.668776 / #
11351 11:53:56.769104 end: 4.2 read-feedback (duration 00:00:01) [common]
11352 11:53:56.769272 end: 4 finalize (duration 00:00:01) [common]
11353 11:53:56.769393 Cleaning after the job
11354 11:53:56.769491 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/ramdisk
11355 11:53:56.772166 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/kernel
11356 11:53:56.784509 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/dtb
11357 11:53:56.784687 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/nfsrootfs
11358 11:53:56.874177 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066519/tftp-deploy-6030xfpe/modules
11359 11:53:56.881479 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066519
11360 11:53:57.518133 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066519
11361 11:53:57.518385 Job finished correctly