Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 37
- Kernel Warnings: 26
- Boot result: PASS
- Errors: 0
1 11:50:27.934479 lava-dispatcher, installed at version: 2023.10
2 11:50:27.934690 start: 0 validate
3 11:50:27.934816 Start time: 2023-11-23 11:50:27.934807+00:00 (UTC)
4 11:50:27.934931 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:50:27.935057 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 11:50:28.210668 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:50:28.210842 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:51:06.720083 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:51:06.720899 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:51:06.991773 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:51:06.992530 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-libcamera%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:51:07.522412 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:51:07.522651 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:51:12.527801 validate duration: 44.59
16 11:51:12.528052 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:51:12.528147 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:51:12.528279 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:51:12.528406 Not decompressing ramdisk as can be used compressed.
20 11:51:12.528492 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/initrd.cpio.gz
21 11:51:12.528556 saving as /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/ramdisk/initrd.cpio.gz
22 11:51:12.528623 total size: 4665398 (4 MB)
23 11:51:12.794955 progress 0 % (0 MB)
24 11:51:12.796535 progress 5 % (0 MB)
25 11:51:12.797904 progress 10 % (0 MB)
26 11:51:12.799199 progress 15 % (0 MB)
27 11:51:12.800501 progress 20 % (0 MB)
28 11:51:12.801791 progress 25 % (1 MB)
29 11:51:12.803138 progress 30 % (1 MB)
30 11:51:12.804466 progress 35 % (1 MB)
31 11:51:12.805716 progress 40 % (1 MB)
32 11:51:12.807128 progress 45 % (2 MB)
33 11:51:12.808427 progress 50 % (2 MB)
34 11:51:12.809819 progress 55 % (2 MB)
35 11:51:12.811098 progress 60 % (2 MB)
36 11:51:12.812421 progress 65 % (2 MB)
37 11:51:12.813668 progress 70 % (3 MB)
38 11:51:12.814984 progress 75 % (3 MB)
39 11:51:12.816307 progress 80 % (3 MB)
40 11:51:12.817849 progress 85 % (3 MB)
41 11:51:12.819106 progress 90 % (4 MB)
42 11:51:12.820433 progress 95 % (4 MB)
43 11:51:12.821760 progress 100 % (4 MB)
44 11:51:12.821931 4 MB downloaded in 0.29 s (15.17 MB/s)
45 11:51:12.822097 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:51:12.822370 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:51:12.822478 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:51:12.822578 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:51:12.822720 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:51:12.822855 saving as /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/kernel/Image
52 11:51:12.822955 total size: 49107456 (46 MB)
53 11:51:12.823056 No compression specified
54 11:51:12.824672 progress 0 % (0 MB)
55 11:51:12.837484 progress 5 % (2 MB)
56 11:51:12.850522 progress 10 % (4 MB)
57 11:51:12.863456 progress 15 % (7 MB)
58 11:51:12.877034 progress 20 % (9 MB)
59 11:51:12.890477 progress 25 % (11 MB)
60 11:51:12.904324 progress 30 % (14 MB)
61 11:51:12.917727 progress 35 % (16 MB)
62 11:51:12.931106 progress 40 % (18 MB)
63 11:51:12.944276 progress 45 % (21 MB)
64 11:51:12.957434 progress 50 % (23 MB)
65 11:51:12.970550 progress 55 % (25 MB)
66 11:51:12.983723 progress 60 % (28 MB)
67 11:51:12.996785 progress 65 % (30 MB)
68 11:51:13.009924 progress 70 % (32 MB)
69 11:51:13.022881 progress 75 % (35 MB)
70 11:51:13.036134 progress 80 % (37 MB)
71 11:51:13.049316 progress 85 % (39 MB)
72 11:51:13.062435 progress 90 % (42 MB)
73 11:51:13.075439 progress 95 % (44 MB)
74 11:51:13.088262 progress 100 % (46 MB)
75 11:51:13.088541 46 MB downloaded in 0.27 s (176.34 MB/s)
76 11:51:13.088720 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:51:13.088994 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:51:13.089106 start: 1.3 download-retry (timeout 00:09:59) [common]
80 11:51:13.089211 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 11:51:13.089397 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:51:13.089501 saving as /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/dtb/mt8192-asurada-spherion-r0.dtb
83 11:51:13.089607 total size: 47278 (0 MB)
84 11:51:13.089711 No compression specified
85 11:51:13.091482 progress 69 % (0 MB)
86 11:51:13.091792 progress 100 % (0 MB)
87 11:51:13.091969 0 MB downloaded in 0.00 s (19.11 MB/s)
88 11:51:13.092148 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:51:13.092442 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:51:13.092551 start: 1.4 download-retry (timeout 00:09:59) [common]
92 11:51:13.092655 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 11:51:13.092790 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-libcamera/20230623.0/arm64/full.rootfs.tar.xz
94 11:51:13.092866 saving as /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/nfsrootfs/full.rootfs.tar
95 11:51:13.092967 total size: 89451516 (85 MB)
96 11:51:13.093071 Using unxz to decompress xz
97 11:51:13.097693 progress 0 % (0 MB)
98 11:51:13.321231 progress 5 % (4 MB)
99 11:51:13.554123 progress 10 % (8 MB)
100 11:51:13.823313 progress 15 % (12 MB)
101 11:51:14.031132 progress 20 % (17 MB)
102 11:51:14.130740 progress 25 % (21 MB)
103 11:51:14.384252 progress 30 % (25 MB)
104 11:51:14.680354 progress 35 % (29 MB)
105 11:51:14.982968 progress 40 % (34 MB)
106 11:51:15.254754 progress 45 % (38 MB)
107 11:51:15.509040 progress 50 % (42 MB)
108 11:51:15.787854 progress 55 % (46 MB)
109 11:51:16.053107 progress 60 % (51 MB)
110 11:51:16.324778 progress 65 % (55 MB)
111 11:51:16.622091 progress 70 % (59 MB)
112 11:51:16.932116 progress 75 % (64 MB)
113 11:51:17.243332 progress 80 % (68 MB)
114 11:51:17.507629 progress 85 % (72 MB)
115 11:51:17.742325 progress 90 % (76 MB)
116 11:51:18.013290 progress 95 % (81 MB)
117 11:51:18.286703 progress 100 % (85 MB)
118 11:51:18.293271 85 MB downloaded in 5.20 s (16.40 MB/s)
119 11:51:18.293635 end: 1.4.1 http-download (duration 00:00:05) [common]
121 11:51:18.294053 end: 1.4 download-retry (duration 00:00:05) [common]
122 11:51:18.294189 start: 1.5 download-retry (timeout 00:09:54) [common]
123 11:51:18.294323 start: 1.5.1 http-download (timeout 00:09:54) [common]
124 11:51:18.294555 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:51:18.294671 saving as /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/modules/modules.tar
126 11:51:18.294771 total size: 8621364 (8 MB)
127 11:51:18.294869 Using unxz to decompress xz
128 11:51:18.565412 progress 0 % (0 MB)
129 11:51:18.587289 progress 5 % (0 MB)
130 11:51:18.611507 progress 10 % (0 MB)
131 11:51:18.636430 progress 15 % (1 MB)
132 11:51:18.660782 progress 20 % (1 MB)
133 11:51:18.685816 progress 25 % (2 MB)
134 11:51:18.713110 progress 30 % (2 MB)
135 11:51:18.741054 progress 35 % (2 MB)
136 11:51:18.765860 progress 40 % (3 MB)
137 11:51:18.791697 progress 45 % (3 MB)
138 11:51:18.818700 progress 50 % (4 MB)
139 11:51:18.846487 progress 55 % (4 MB)
140 11:51:18.874034 progress 60 % (4 MB)
141 11:51:18.904358 progress 65 % (5 MB)
142 11:51:18.931711 progress 70 % (5 MB)
143 11:51:18.956797 progress 75 % (6 MB)
144 11:51:18.984527 progress 80 % (6 MB)
145 11:51:19.011052 progress 85 % (7 MB)
146 11:51:19.036851 progress 90 % (7 MB)
147 11:51:19.067489 progress 95 % (7 MB)
148 11:51:19.098000 progress 100 % (8 MB)
149 11:51:19.102837 8 MB downloaded in 0.81 s (10.17 MB/s)
150 11:51:19.103119 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:51:19.103397 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:51:19.103501 start: 1.6 prepare-tftp-overlay (timeout 00:09:53) [common]
154 11:51:19.103599 start: 1.6.1 extract-nfsrootfs (timeout 00:09:53) [common]
155 11:51:20.920091 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7
156 11:51:20.920326 end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
157 11:51:20.920453 start: 1.6.2 lava-overlay (timeout 00:09:52) [common]
158 11:51:20.920639 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc
159 11:51:20.920773 makedir: /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin
160 11:51:20.920876 makedir: /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/tests
161 11:51:20.921012 makedir: /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/results
162 11:51:20.921114 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-add-keys
163 11:51:20.921259 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-add-sources
164 11:51:20.921388 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-background-process-start
165 11:51:20.921531 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-background-process-stop
166 11:51:20.921670 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-common-functions
167 11:51:20.921793 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-echo-ipv4
168 11:51:20.921916 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-install-packages
169 11:51:20.922038 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-installed-packages
170 11:51:20.922161 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-os-build
171 11:51:20.922283 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-probe-channel
172 11:51:20.922423 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-probe-ip
173 11:51:20.922559 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-target-ip
174 11:51:20.922682 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-target-mac
175 11:51:20.922805 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-target-storage
176 11:51:20.922960 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-case
177 11:51:20.923084 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-event
178 11:51:20.923207 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-feedback
179 11:51:20.923330 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-raise
180 11:51:20.923489 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-reference
181 11:51:20.923627 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-runner
182 11:51:20.923763 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-set
183 11:51:20.923884 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-test-shell
184 11:51:20.924039 Updating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-install-packages (oe)
185 11:51:20.924190 Updating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/bin/lava-installed-packages (oe)
186 11:51:20.924345 Creating /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/environment
187 11:51:20.924439 LAVA metadata
188 11:51:20.924524 - LAVA_JOB_ID=12066517
189 11:51:20.924601 - LAVA_DISPATCHER_IP=192.168.201.1
190 11:51:20.924698 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:52) [common]
191 11:51:20.924764 skipped lava-vland-overlay
192 11:51:20.924836 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 11:51:20.924913 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:52) [common]
194 11:51:20.924972 skipped lava-multinode-overlay
195 11:51:20.925072 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 11:51:20.925147 start: 1.6.2.3 test-definition (timeout 00:09:52) [common]
197 11:51:20.925217 Loading test definitions
198 11:51:20.925303 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:52) [common]
199 11:51:20.925375 Using /lava-12066517 at stage 0
200 11:51:20.925701 uuid=12066517_1.6.2.3.1 testdef=None
201 11:51:20.925802 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 11:51:20.925883 start: 1.6.2.3.2 test-overlay (timeout 00:09:52) [common]
203 11:51:20.926395 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 11:51:20.926641 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:52) [common]
206 11:51:20.927360 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 11:51:20.927583 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:52) [common]
209 11:51:20.928227 runner path: /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/0/tests/0_lc-compliance test_uuid 12066517_1.6.2.3.1
210 11:51:20.928393 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 11:51:20.928594 Creating lava-test-runner.conf files
213 11:51:20.928671 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066517/lava-overlay-bnnvmapc/lava-12066517/0 for stage 0
214 11:51:20.928772 - 0_lc-compliance
215 11:51:20.928867 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
216 11:51:20.928967 start: 1.6.2.4 compress-overlay (timeout 00:09:52) [common]
217 11:51:20.935242 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
218 11:51:20.935348 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:52) [common]
219 11:51:20.935430 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
220 11:51:20.935514 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
221 11:51:20.935597 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:52) [common]
222 11:51:21.057103 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
223 11:51:21.057499 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
224 11:51:21.057620 extracting modules file /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7
225 11:51:21.283258 extracting modules file /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066517/extract-overlay-ramdisk-4rtwa5x3/ramdisk
226 11:51:21.515368 end: 1.6.4 extract-modules (duration 00:00:00) [common]
227 11:51:21.515540 start: 1.6.5 apply-overlay-tftp (timeout 00:09:51) [common]
228 11:51:21.515638 [common] Applying overlay to NFS
229 11:51:21.515708 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066517/compress-overlay-t3re_3_9/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7
230 11:51:21.522433 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
231 11:51:21.522555 start: 1.6.6 configure-preseed-file (timeout 00:09:51) [common]
232 11:51:21.522672 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
233 11:51:21.522759 start: 1.6.7 compress-ramdisk (timeout 00:09:51) [common]
234 11:51:21.522839 Building ramdisk /var/lib/lava/dispatcher/tmp/12066517/extract-overlay-ramdisk-4rtwa5x3/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066517/extract-overlay-ramdisk-4rtwa5x3/ramdisk
235 11:51:21.855493 >> 119398 blocks
236 11:51:23.987894 rename /var/lib/lava/dispatcher/tmp/12066517/extract-overlay-ramdisk-4rtwa5x3/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/ramdisk/ramdisk.cpio.gz
237 11:51:23.988397 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
238 11:51:23.988517 start: 1.6.8 prepare-kernel (timeout 00:09:49) [common]
239 11:51:23.988620 start: 1.6.8.1 prepare-fit (timeout 00:09:49) [common]
240 11:51:23.988730 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/kernel/Image'
241 11:51:37.169971 Returned 0 in 13 seconds
242 11:51:37.270726 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/kernel/image.itb
243 11:51:37.630052 output: FIT description: Kernel Image image with one or more FDT blobs
244 11:51:37.630528 output: Created: Thu Nov 23 11:51:37 2023
245 11:51:37.630647 output: Image 0 (kernel-1)
246 11:51:37.630745 output: Description:
247 11:51:37.630836 output: Created: Thu Nov 23 11:51:37 2023
248 11:51:37.630930 output: Type: Kernel Image
249 11:51:37.631073 output: Compression: lzma compressed
250 11:51:37.631183 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
251 11:51:37.631279 output: Architecture: AArch64
252 11:51:37.631372 output: OS: Linux
253 11:51:37.631467 output: Load Address: 0x00000000
254 11:51:37.631558 output: Entry Point: 0x00000000
255 11:51:37.631653 output: Hash algo: crc32
256 11:51:37.631742 output: Hash value: e6d7c86f
257 11:51:37.631834 output: Image 1 (fdt-1)
258 11:51:37.631920 output: Description: mt8192-asurada-spherion-r0
259 11:51:37.632008 output: Created: Thu Nov 23 11:51:37 2023
260 11:51:37.632095 output: Type: Flat Device Tree
261 11:51:37.632182 output: Compression: uncompressed
262 11:51:37.632313 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
263 11:51:37.632401 output: Architecture: AArch64
264 11:51:37.632488 output: Hash algo: crc32
265 11:51:37.632575 output: Hash value: cc4352de
266 11:51:37.632663 output: Image 2 (ramdisk-1)
267 11:51:37.632751 output: Description: unavailable
268 11:51:37.632838 output: Created: Thu Nov 23 11:51:37 2023
269 11:51:37.632924 output: Type: RAMDisk Image
270 11:51:37.633012 output: Compression: Unknown Compression
271 11:51:37.633099 output: Data Size: 17792555 Bytes = 17375.54 KiB = 16.97 MiB
272 11:51:37.633187 output: Architecture: AArch64
273 11:51:37.633274 output: OS: Linux
274 11:51:37.633361 output: Load Address: unavailable
275 11:51:37.633448 output: Entry Point: unavailable
276 11:51:37.633535 output: Hash algo: crc32
277 11:51:37.633620 output: Hash value: c74ed7b8
278 11:51:37.633706 output: Default Configuration: 'conf-1'
279 11:51:37.633787 output: Configuration 0 (conf-1)
280 11:51:37.633867 output: Description: mt8192-asurada-spherion-r0
281 11:51:37.633955 output: Kernel: kernel-1
282 11:51:37.634042 output: Init Ramdisk: ramdisk-1
283 11:51:37.634128 output: FDT: fdt-1
284 11:51:37.634216 output: Loadables: kernel-1
285 11:51:37.634304 output:
286 11:51:37.634584 end: 1.6.8.1 prepare-fit (duration 00:00:14) [common]
287 11:51:37.634735 end: 1.6.8 prepare-kernel (duration 00:00:14) [common]
288 11:51:37.634890 end: 1.6 prepare-tftp-overlay (duration 00:00:19) [common]
289 11:51:37.635032 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:35) [common]
290 11:51:37.635154 No LXC device requested
291 11:51:37.635279 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
292 11:51:37.635412 start: 1.8 deploy-device-env (timeout 00:09:35) [common]
293 11:51:37.635531 end: 1.8 deploy-device-env (duration 00:00:00) [common]
294 11:51:37.635642 Checking files for TFTP limit of 4294967296 bytes.
295 11:51:37.636389 end: 1 tftp-deploy (duration 00:00:25) [common]
296 11:51:37.636535 start: 2 depthcharge-action (timeout 00:05:00) [common]
297 11:51:37.636676 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
298 11:51:37.636865 substitutions:
299 11:51:37.636967 - {DTB}: 12066517/tftp-deploy-xw34pi1y/dtb/mt8192-asurada-spherion-r0.dtb
300 11:51:37.637068 - {INITRD}: 12066517/tftp-deploy-xw34pi1y/ramdisk/ramdisk.cpio.gz
301 11:51:37.637162 - {KERNEL}: 12066517/tftp-deploy-xw34pi1y/kernel/Image
302 11:51:37.637254 - {LAVA_MAC}: None
303 11:51:37.637345 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7
304 11:51:37.637436 - {NFS_SERVER_IP}: 192.168.201.1
305 11:51:37.637527 - {PRESEED_CONFIG}: None
306 11:51:37.637617 - {PRESEED_LOCAL}: None
307 11:51:37.637706 - {RAMDISK}: 12066517/tftp-deploy-xw34pi1y/ramdisk/ramdisk.cpio.gz
308 11:51:37.637796 - {ROOT_PART}: None
309 11:51:37.637884 - {ROOT}: None
310 11:51:37.637971 - {SERVER_IP}: 192.168.201.1
311 11:51:37.638061 - {TEE}: None
312 11:51:37.638150 Parsed boot commands:
313 11:51:37.638239 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
314 11:51:37.638496 Parsed boot commands: tftpboot 192.168.201.1 12066517/tftp-deploy-xw34pi1y/kernel/image.itb 12066517/tftp-deploy-xw34pi1y/kernel/cmdline
315 11:51:37.638634 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
316 11:51:37.638762 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
317 11:51:37.638899 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
318 11:51:37.639027 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
319 11:51:37.639137 Not connected, no need to disconnect.
320 11:51:37.639250 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
321 11:51:37.639375 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
322 11:51:37.639484 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-8'
323 11:51:37.644266 Setting prompt string to ['lava-test: # ']
324 11:51:37.644747 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
325 11:51:37.644914 end: 2.2.1 reset-connection (duration 00:00:00) [common]
326 11:51:37.645093 start: 2.2.2 reset-device (timeout 00:05:00) [common]
327 11:51:37.645255 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
328 11:51:37.645628 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
329 11:51:42.781847 >> Command sent successfully.
330 11:51:42.784566 Returned 0 in 5 seconds
331 11:51:42.885000 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
333 11:51:42.885342 end: 2.2.2 reset-device (duration 00:00:05) [common]
334 11:51:42.885451 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
335 11:51:42.885538 Setting prompt string to 'Starting depthcharge on Spherion...'
336 11:51:42.885608 Changing prompt to 'Starting depthcharge on Spherion...'
337 11:51:42.885677 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
338 11:51:42.885944 [Enter `^Ec?' for help]
339 11:51:43.057002
340 11:51:43.057165
341 11:51:43.057244 F0: 102B 0000
342 11:51:43.057311
343 11:51:43.057371 F3: 1001 0000 [0200]
344 11:51:43.057430
345 11:51:43.060475 F3: 1001 0000
346 11:51:43.060559
347 11:51:43.060625 F7: 102D 0000
348 11:51:43.060688
349 11:51:43.060748 F1: 0000 0000
350 11:51:43.064245
351 11:51:43.064328 V0: 0000 0000 [0001]
352 11:51:43.064397
353 11:51:43.064457 00: 0007 8000
354 11:51:43.064520
355 11:51:43.067951 01: 0000 0000
356 11:51:43.068036
357 11:51:43.068101 BP: 0C00 0209 [0000]
358 11:51:43.068163
359 11:51:43.071858 G0: 1182 0000
360 11:51:43.071941
361 11:51:43.072007 EC: 0000 0021 [4000]
362 11:51:43.072068
363 11:51:43.075385 S7: 0000 0000 [0000]
364 11:51:43.075468
365 11:51:43.075533 CC: 0000 0000 [0001]
366 11:51:43.075594
367 11:51:43.078802 T0: 0000 0040 [010F]
368 11:51:43.078887
369 11:51:43.078952 Jump to BL
370 11:51:43.079013
371 11:51:43.103748
372 11:51:43.103894
373 11:51:43.103965
374 11:51:43.111277 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
375 11:51:43.114788 ARM64: Exception handlers installed.
376 11:51:43.118449 ARM64: Testing exception
377 11:51:43.121912 ARM64: Done test exception
378 11:51:43.129368 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
379 11:51:43.139661 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
380 11:51:43.146292 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
381 11:51:43.156413 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
382 11:51:43.163071 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
383 11:51:43.169889 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
384 11:51:43.180430 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
385 11:51:43.187640 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
386 11:51:43.206546 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
387 11:51:43.209787 WDT: Last reset was cold boot
388 11:51:43.213241 SPI1(PAD0) initialized at 2873684 Hz
389 11:51:43.216818 SPI5(PAD0) initialized at 992727 Hz
390 11:51:43.219831 VBOOT: Loading verstage.
391 11:51:43.226836 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
392 11:51:43.230176 FMAP: Found "FLASH" version 1.1 at 0x20000.
393 11:51:43.233402 FMAP: base = 0x0 size = 0x800000 #areas = 25
394 11:51:43.236406 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
395 11:51:43.243871 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
396 11:51:43.250610 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
397 11:51:43.261355 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
398 11:51:43.261445
399 11:51:43.261532
400 11:51:43.271445 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
401 11:51:43.274865 ARM64: Exception handlers installed.
402 11:51:43.278312 ARM64: Testing exception
403 11:51:43.278398 ARM64: Done test exception
404 11:51:43.284818 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
405 11:51:43.288648 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
406 11:51:43.302562 Probing TPM: . done!
407 11:51:43.302654 TPM ready after 0 ms
408 11:51:43.309133 Connected to device vid:did:rid of 1ae0:0028:00
409 11:51:43.357077 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
410 11:51:43.357220 Initialized TPM device CR50 revision 0
411 11:51:43.369020 tlcl_send_startup: Startup return code is 0
412 11:51:43.369116 TPM: setup succeeded
413 11:51:43.380823 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
414 11:51:43.389462 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
415 11:51:43.400917 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
416 11:51:43.411629 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
417 11:51:43.415222 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
418 11:51:43.418790 in-header: 03 07 00 00 08 00 00 00
419 11:51:43.422471 in-data: aa e4 47 04 13 02 00 00
420 11:51:43.426030 Chrome EC: UHEPI supported
421 11:51:43.432806 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
422 11:51:43.436221 in-header: 03 9d 00 00 08 00 00 00
423 11:51:43.440101 in-data: 10 20 20 08 00 00 00 00
424 11:51:43.440191 Phase 1
425 11:51:43.447533 FMAP: area GBB found @ 3f5000 (12032 bytes)
426 11:51:43.451014 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
427 11:51:43.458268 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
428 11:51:43.458355 Recovery requested (1009000e)
429 11:51:43.467475 TPM: Extending digest for VBOOT: boot mode into PCR 0
430 11:51:43.472633 tlcl_extend: response is 0
431 11:51:43.480610 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
432 11:51:43.486506 tlcl_extend: response is 0
433 11:51:43.493277 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
434 11:51:43.513899 read SPI 0x210d4 0x2173b: 15147 us, 9045 KB/s, 72.360 Mbps
435 11:51:43.521911 BS: bootblock times (exec / console): total (unknown) / 148 ms
436 11:51:43.522013
437 11:51:43.522079
438 11:51:43.529491 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
439 11:51:43.532970 ARM64: Exception handlers installed.
440 11:51:43.536718 ARM64: Testing exception
441 11:51:43.536803 ARM64: Done test exception
442 11:51:43.556393 pmic_efuse_setting: Set efuses in 11 msecs
443 11:51:43.565846 pmwrap_interface_init: Select PMIF_VLD_RDY
444 11:51:43.569322 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
445 11:51:43.572709 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
446 11:51:43.576558 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
447 11:51:43.583812 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
448 11:51:43.587367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
449 11:51:43.591691 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
450 11:51:43.598422 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
451 11:51:43.602590 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
452 11:51:43.605262 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
453 11:51:43.612079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
454 11:51:43.615734 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
455 11:51:43.621896 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
456 11:51:43.625354 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
457 11:51:43.632366 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
458 11:51:43.635579 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
459 11:51:43.642144 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
460 11:51:43.648958 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
461 11:51:43.655226 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
462 11:51:43.658978 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
463 11:51:43.666154 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
464 11:51:43.670107 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
465 11:51:43.677286 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
466 11:51:43.680892 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
467 11:51:43.687583 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
468 11:51:43.691595 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
469 11:51:43.697891 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
470 11:51:43.704441 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
471 11:51:43.708146 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
472 11:51:43.716605 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
473 11:51:43.719001 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
474 11:51:43.723063 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
475 11:51:43.726568 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
476 11:51:43.733937 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
477 11:51:43.738071 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
478 11:51:43.741662 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
479 11:51:43.749247 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
480 11:51:43.752111 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
481 11:51:43.759273 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
482 11:51:43.762411 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
483 11:51:43.765304 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
484 11:51:43.772279 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
485 11:51:43.775725 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
486 11:51:43.778910 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
487 11:51:43.785573 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
488 11:51:43.788624 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
489 11:51:43.792275 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
490 11:51:43.795293 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
491 11:51:43.802107 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
492 11:51:43.806041 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
493 11:51:43.809106 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
494 11:51:43.811986 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
495 11:51:43.822406 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
496 11:51:43.829043 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
497 11:51:43.835284 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
498 11:51:43.842453 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
499 11:51:43.852035 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
500 11:51:43.855212 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
501 11:51:43.861963 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
502 11:51:43.865215 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
503 11:51:43.872524 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x35
504 11:51:43.878792 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
505 11:51:43.882172 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
506 11:51:43.885437 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
507 11:51:43.896421 [RTC]rtc_get_frequency_meter,154: input=15, output=794
508 11:51:43.899462 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
509 11:51:43.906551 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
510 11:51:43.909799 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
511 11:51:43.912925 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
512 11:51:43.916870 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
513 11:51:43.920021 ADC[4]: Raw value=898520 ID=7
514 11:51:43.923000 ADC[3]: Raw value=212700 ID=1
515 11:51:43.923086 RAM Code: 0x71
516 11:51:43.929604 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
517 11:51:43.933410 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
518 11:51:43.943621 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
519 11:51:43.950408 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
520 11:51:43.953647 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
521 11:51:43.956825 in-header: 03 07 00 00 08 00 00 00
522 11:51:43.960374 in-data: aa e4 47 04 13 02 00 00
523 11:51:43.960456 Chrome EC: UHEPI supported
524 11:51:43.966966 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
525 11:51:43.971229 in-header: 03 d5 00 00 08 00 00 00
526 11:51:43.974069 in-data: 98 20 60 08 00 00 00 00
527 11:51:43.977664 MRC: failed to locate region type 0.
528 11:51:43.988372 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
529 11:51:43.988911 DRAM-K: Running full calibration
530 11:51:43.995718 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
531 11:51:43.995804 header.status = 0x0
532 11:51:43.999358 header.version = 0x6 (expected: 0x6)
533 11:51:44.003145 header.size = 0xd00 (expected: 0xd00)
534 11:51:44.006309 header.flags = 0x0
535 11:51:44.009633 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
536 11:51:44.028450 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
537 11:51:44.035354 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
538 11:51:44.038455 dram_init: ddr_geometry: 2
539 11:51:44.042410 [EMI] MDL number = 2
540 11:51:44.042495 [EMI] Get MDL freq = 0
541 11:51:44.045621 dram_init: ddr_type: 0
542 11:51:44.045705 is_discrete_lpddr4: 1
543 11:51:44.048560 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
544 11:51:44.048644
545 11:51:44.048711
546 11:51:44.051758 [Bian_co] ETT version 0.0.0.1
547 11:51:44.058734 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
548 11:51:44.058818
549 11:51:44.061919 dramc_set_vcore_voltage set vcore to 650000
550 11:51:44.062003 Read voltage for 800, 4
551 11:51:44.065412 Vio18 = 0
552 11:51:44.065499 Vcore = 650000
553 11:51:44.065565 Vdram = 0
554 11:51:44.068656 Vddq = 0
555 11:51:44.068740 Vmddr = 0
556 11:51:44.071749 dram_init: config_dvfs: 1
557 11:51:44.075250 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
558 11:51:44.081692 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
559 11:51:44.085514 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
560 11:51:44.088978 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
561 11:51:44.092699 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
562 11:51:44.096965 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
563 11:51:44.100326 MEM_TYPE=3, freq_sel=18
564 11:51:44.100411 sv_algorithm_assistance_LP4_1600
565 11:51:44.106968 ============ PULL DRAM RESETB DOWN ============
566 11:51:44.110977 ========== PULL DRAM RESETB DOWN end =========
567 11:51:44.114346 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
568 11:51:44.118301 ===================================
569 11:51:44.122320 LPDDR4 DRAM CONFIGURATION
570 11:51:44.122406 ===================================
571 11:51:44.125913 EX_ROW_EN[0] = 0x0
572 11:51:44.129256 EX_ROW_EN[1] = 0x0
573 11:51:44.129342 LP4Y_EN = 0x0
574 11:51:44.129428 WORK_FSP = 0x0
575 11:51:44.132880 WL = 0x2
576 11:51:44.132965 RL = 0x2
577 11:51:44.136513 BL = 0x2
578 11:51:44.136599 RPST = 0x0
579 11:51:44.140609 RD_PRE = 0x0
580 11:51:44.140694 WR_PRE = 0x1
581 11:51:44.144011 WR_PST = 0x0
582 11:51:44.144097 DBI_WR = 0x0
583 11:51:44.148061 DBI_RD = 0x0
584 11:51:44.148147 OTF = 0x1
585 11:51:44.151828 ===================================
586 11:51:44.156047 ===================================
587 11:51:44.156133 ANA top config
588 11:51:44.159452 ===================================
589 11:51:44.163143 DLL_ASYNC_EN = 0
590 11:51:44.163227 ALL_SLAVE_EN = 1
591 11:51:44.166885 NEW_RANK_MODE = 1
592 11:51:44.170180 DLL_IDLE_MODE = 1
593 11:51:44.174084 LP45_APHY_COMB_EN = 1
594 11:51:44.174169 TX_ODT_DIS = 1
595 11:51:44.177360 NEW_8X_MODE = 1
596 11:51:44.180591 ===================================
597 11:51:44.183938 ===================================
598 11:51:44.187497 data_rate = 1600
599 11:51:44.190449 CKR = 1
600 11:51:44.193838 DQ_P2S_RATIO = 8
601 11:51:44.197166 ===================================
602 11:51:44.197253 CA_P2S_RATIO = 8
603 11:51:44.200464 DQ_CA_OPEN = 0
604 11:51:44.204114 DQ_SEMI_OPEN = 0
605 11:51:44.207465 CA_SEMI_OPEN = 0
606 11:51:44.210741 CA_FULL_RATE = 0
607 11:51:44.213893 DQ_CKDIV4_EN = 1
608 11:51:44.213979 CA_CKDIV4_EN = 1
609 11:51:44.216984 CA_PREDIV_EN = 0
610 11:51:44.220651 PH8_DLY = 0
611 11:51:44.223866 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
612 11:51:44.227118 DQ_AAMCK_DIV = 4
613 11:51:44.227206 CA_AAMCK_DIV = 4
614 11:51:44.230448 CA_ADMCK_DIV = 4
615 11:51:44.233753 DQ_TRACK_CA_EN = 0
616 11:51:44.237199 CA_PICK = 800
617 11:51:44.240565 CA_MCKIO = 800
618 11:51:44.243853 MCKIO_SEMI = 0
619 11:51:44.247257 PLL_FREQ = 3068
620 11:51:44.247343 DQ_UI_PI_RATIO = 32
621 11:51:44.251076 CA_UI_PI_RATIO = 0
622 11:51:44.254351 ===================================
623 11:51:44.257455 ===================================
624 11:51:44.260597 memory_type:LPDDR4
625 11:51:44.263966 GP_NUM : 10
626 11:51:44.264054 SRAM_EN : 1
627 11:51:44.267052 MD32_EN : 0
628 11:51:44.270618 ===================================
629 11:51:44.274256 [ANA_INIT] >>>>>>>>>>>>>>
630 11:51:44.274342 <<<<<< [CONFIGURE PHASE]: ANA_TX
631 11:51:44.277938 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
632 11:51:44.280521 ===================================
633 11:51:44.284043 data_rate = 1600,PCW = 0X7600
634 11:51:44.287389 ===================================
635 11:51:44.290602 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
636 11:51:44.297498 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
637 11:51:44.303860 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
638 11:51:44.307226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
639 11:51:44.310566 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
640 11:51:44.314187 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
641 11:51:44.317747 [ANA_INIT] flow start
642 11:51:44.317842 [ANA_INIT] PLL >>>>>>>>
643 11:51:44.321228 [ANA_INIT] PLL <<<<<<<<
644 11:51:44.321321 [ANA_INIT] MIDPI >>>>>>>>
645 11:51:44.325321 [ANA_INIT] MIDPI <<<<<<<<
646 11:51:44.328908 [ANA_INIT] DLL >>>>>>>>
647 11:51:44.329002 [ANA_INIT] flow end
648 11:51:44.332763 ============ LP4 DIFF to SE enter ============
649 11:51:44.336401 ============ LP4 DIFF to SE exit ============
650 11:51:44.340095 [ANA_INIT] <<<<<<<<<<<<<
651 11:51:44.344046 [Flow] Enable top DCM control >>>>>
652 11:51:44.347307 [Flow] Enable top DCM control <<<<<
653 11:51:44.351466 Enable DLL master slave shuffle
654 11:51:44.355115 ==============================================================
655 11:51:44.358337 Gating Mode config
656 11:51:44.361900 ==============================================================
657 11:51:44.365041 Config description:
658 11:51:44.374886 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
659 11:51:44.381567 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
660 11:51:44.384828 SELPH_MODE 0: By rank 1: By Phase
661 11:51:44.391692 ==============================================================
662 11:51:44.395056 GAT_TRACK_EN = 1
663 11:51:44.398206 RX_GATING_MODE = 2
664 11:51:44.401296 RX_GATING_TRACK_MODE = 2
665 11:51:44.401387 SELPH_MODE = 1
666 11:51:44.404718 PICG_EARLY_EN = 1
667 11:51:44.407930 VALID_LAT_VALUE = 1
668 11:51:44.415121 ==============================================================
669 11:51:44.418095 Enter into Gating configuration >>>>
670 11:51:44.421724 Exit from Gating configuration <<<<
671 11:51:44.424767 Enter into DVFS_PRE_config >>>>>
672 11:51:44.434754 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
673 11:51:44.438150 Exit from DVFS_PRE_config <<<<<
674 11:51:44.441290 Enter into PICG configuration >>>>
675 11:51:44.444561 Exit from PICG configuration <<<<
676 11:51:44.448328 [RX_INPUT] configuration >>>>>
677 11:51:44.451475 [RX_INPUT] configuration <<<<<
678 11:51:44.454680 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
679 11:51:44.461158 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
680 11:51:44.467677 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
681 11:51:44.474633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
682 11:51:44.477997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
683 11:51:44.484528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
684 11:51:44.487782 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
685 11:51:44.494453 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
686 11:51:44.498222 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
687 11:51:44.501573 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
688 11:51:44.504354 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
689 11:51:44.511991 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
690 11:51:44.516010 ===================================
691 11:51:44.516111 LPDDR4 DRAM CONFIGURATION
692 11:51:44.519517 ===================================
693 11:51:44.523037 EX_ROW_EN[0] = 0x0
694 11:51:44.523132 EX_ROW_EN[1] = 0x0
695 11:51:44.526447 LP4Y_EN = 0x0
696 11:51:44.526539 WORK_FSP = 0x0
697 11:51:44.530250 WL = 0x2
698 11:51:44.530359 RL = 0x2
699 11:51:44.530441 BL = 0x2
700 11:51:44.534038 RPST = 0x0
701 11:51:44.534159 RD_PRE = 0x0
702 11:51:44.537689 WR_PRE = 0x1
703 11:51:44.537777 WR_PST = 0x0
704 11:51:44.541295 DBI_WR = 0x0
705 11:51:44.541384 DBI_RD = 0x0
706 11:51:44.545382 OTF = 0x1
707 11:51:44.548720 ===================================
708 11:51:44.552478 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
709 11:51:44.555940 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
710 11:51:44.560068 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
711 11:51:44.563310 ===================================
712 11:51:44.567032 LPDDR4 DRAM CONFIGURATION
713 11:51:44.571042 ===================================
714 11:51:44.571194 EX_ROW_EN[0] = 0x10
715 11:51:44.574450 EX_ROW_EN[1] = 0x0
716 11:51:44.574658 LP4Y_EN = 0x0
717 11:51:44.577939 WORK_FSP = 0x0
718 11:51:44.578051 WL = 0x2
719 11:51:44.581706 RL = 0x2
720 11:51:44.581797 BL = 0x2
721 11:51:44.581867 RPST = 0x0
722 11:51:44.585113 RD_PRE = 0x0
723 11:51:44.588729 WR_PRE = 0x1
724 11:51:44.588819 WR_PST = 0x0
725 11:51:44.588885 DBI_WR = 0x0
726 11:51:44.592658 DBI_RD = 0x0
727 11:51:44.592743 OTF = 0x1
728 11:51:44.596519 ===================================
729 11:51:44.603142 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
730 11:51:44.606870 nWR fixed to 40
731 11:51:44.610535 [ModeRegInit_LP4] CH0 RK0
732 11:51:44.610626 [ModeRegInit_LP4] CH0 RK1
733 11:51:44.614139 [ModeRegInit_LP4] CH1 RK0
734 11:51:44.614230 [ModeRegInit_LP4] CH1 RK1
735 11:51:44.617776 match AC timing 13
736 11:51:44.621991 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
737 11:51:44.625205 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
738 11:51:44.628936 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
739 11:51:44.636480 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
740 11:51:44.639951 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
741 11:51:44.643812 [EMI DOE] emi_dcm 0
742 11:51:44.647472 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
743 11:51:44.647565 ==
744 11:51:44.650723 Dram Type= 6, Freq= 0, CH_0, rank 0
745 11:51:44.654792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
746 11:51:44.654884 ==
747 11:51:44.658401 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
748 11:51:44.665802 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
749 11:51:44.674929 [CA 0] Center 38 (7~69) winsize 63
750 11:51:44.678646 [CA 1] Center 37 (7~68) winsize 62
751 11:51:44.682244 [CA 2] Center 35 (5~66) winsize 62
752 11:51:44.686396 [CA 3] Center 35 (5~66) winsize 62
753 11:51:44.689929 [CA 4] Center 34 (4~65) winsize 62
754 11:51:44.690030 [CA 5] Center 34 (4~64) winsize 61
755 11:51:44.690098
756 11:51:44.693459 [CmdBusTrainingLP45] Vref(ca) range 1: 30
757 11:51:44.697287
758 11:51:44.697377 [CATrainingPosCal] consider 1 rank data
759 11:51:44.700982 u2DelayCellTimex100 = 270/100 ps
760 11:51:44.704914 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
761 11:51:44.707968 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
762 11:51:44.711957 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
763 11:51:44.715701 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
764 11:51:44.719520 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
765 11:51:44.723323 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
766 11:51:44.723485
767 11:51:44.727032 CA PerBit enable=1, Macro0, CA PI delay=34
768 11:51:44.727124
769 11:51:44.730814 [CBTSetCACLKResult] CA Dly = 34
770 11:51:44.730923 CS Dly: 6 (0~37)
771 11:51:44.734058 ==
772 11:51:44.734149 Dram Type= 6, Freq= 0, CH_0, rank 1
773 11:51:44.741492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:51:44.741603 ==
775 11:51:44.745003 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
776 11:51:44.752134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
777 11:51:44.761182 [CA 0] Center 38 (7~69) winsize 63
778 11:51:44.764999 [CA 1] Center 37 (7~68) winsize 62
779 11:51:44.768436 [CA 2] Center 35 (5~66) winsize 62
780 11:51:44.772533 [CA 3] Center 35 (5~66) winsize 62
781 11:51:44.776113 [CA 4] Center 34 (4~65) winsize 62
782 11:51:44.776239 [CA 5] Center 34 (3~65) winsize 63
783 11:51:44.779951
784 11:51:44.783680 [CmdBusTrainingLP45] Vref(ca) range 1: 32
785 11:51:44.783780
786 11:51:44.783851 [CATrainingPosCal] consider 2 rank data
787 11:51:44.787634 u2DelayCellTimex100 = 270/100 ps
788 11:51:44.791476 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
789 11:51:44.795576 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
790 11:51:44.799339 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
791 11:51:44.802802 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
792 11:51:44.805649 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
793 11:51:44.808967 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
794 11:51:44.809059
795 11:51:44.812460 CA PerBit enable=1, Macro0, CA PI delay=34
796 11:51:44.815669
797 11:51:44.815758 [CBTSetCACLKResult] CA Dly = 34
798 11:51:44.818867 CS Dly: 6 (0~38)
799 11:51:44.818982
800 11:51:44.822390 ----->DramcWriteLeveling(PI) begin...
801 11:51:44.822479 ==
802 11:51:44.826004 Dram Type= 6, Freq= 0, CH_0, rank 0
803 11:51:44.828926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 11:51:44.829043 ==
805 11:51:44.832330 Write leveling (Byte 0): 31 => 31
806 11:51:44.835557 Write leveling (Byte 1): 30 => 30
807 11:51:44.839197 DramcWriteLeveling(PI) end<-----
808 11:51:44.839317
809 11:51:44.839417 ==
810 11:51:44.842644 Dram Type= 6, Freq= 0, CH_0, rank 0
811 11:51:44.845820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
812 11:51:44.845912 ==
813 11:51:44.849389 [Gating] SW mode calibration
814 11:51:44.855924 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
815 11:51:44.862606 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
816 11:51:44.865680 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
817 11:51:44.872683 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
818 11:51:44.875789 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
819 11:51:44.879055 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
820 11:51:44.882711 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:51:44.889003 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:51:44.892480 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:51:44.895863 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:51:44.903589 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:51:44.907180 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:51:44.911449 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:51:44.914791 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:51:44.918410 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
829 11:51:44.924821 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
830 11:51:44.929149 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
831 11:51:44.931909 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
832 11:51:44.935234 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
833 11:51:44.941842 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
834 11:51:44.945433 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
835 11:51:44.949060 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
836 11:51:44.955288 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 11:51:44.958588 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 11:51:44.962345 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:51:44.968741 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:51:44.972098 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 11:51:44.975400 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:51:44.981959 0 9 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
843 11:51:44.985229 0 9 12 | B1->B0 | 2626 3333 | 1 0 | (1 1) (0 0)
844 11:51:44.988522 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
845 11:51:44.995483 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
846 11:51:44.998579 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
847 11:51:45.002277 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
848 11:51:45.008785 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
849 11:51:45.012159 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
850 11:51:45.016099 0 10 8 | B1->B0 | 3434 3030 | 0 0 | (0 1) (0 1)
851 11:51:45.019117 0 10 12 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
852 11:51:45.025419 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 11:51:45.028417 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 11:51:45.032104 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 11:51:45.038761 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 11:51:45.042091 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:51:45.045482 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:51:45.051722 0 11 8 | B1->B0 | 2828 3131 | 0 0 | (0 0) (0 0)
859 11:51:45.055175 0 11 12 | B1->B0 | 3737 3e3e | 0 0 | (0 0) (0 0)
860 11:51:45.058706 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
861 11:51:45.065390 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
862 11:51:45.068449 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
863 11:51:45.071843 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
864 11:51:45.078303 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
865 11:51:45.081655 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
866 11:51:45.084958 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
867 11:51:45.091814 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
868 11:51:45.095595 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
869 11:51:45.098577 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
870 11:51:45.105039 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
871 11:51:45.108664 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
872 11:51:45.112154 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
873 11:51:45.115144 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
874 11:51:45.122328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
875 11:51:45.125209 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
876 11:51:45.128990 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
877 11:51:45.135396 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
878 11:51:45.139169 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
879 11:51:45.142128 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
880 11:51:45.148693 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
881 11:51:45.151823 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
882 11:51:45.155363 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
883 11:51:45.162249 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
884 11:51:45.162399 Total UI for P1: 0, mck2ui 16
885 11:51:45.169244 best dqsien dly found for B0: ( 0, 14, 8)
886 11:51:45.169349 Total UI for P1: 0, mck2ui 16
887 11:51:45.172411 best dqsien dly found for B1: ( 0, 14, 10)
888 11:51:45.178973 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
889 11:51:45.182055 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
890 11:51:45.182146
891 11:51:45.185967 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
892 11:51:45.188885 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
893 11:51:45.192409 [Gating] SW calibration Done
894 11:51:45.192500 ==
895 11:51:45.195345 Dram Type= 6, Freq= 0, CH_0, rank 0
896 11:51:45.198642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
897 11:51:45.198732 ==
898 11:51:45.202028 RX Vref Scan: 0
899 11:51:45.202116
900 11:51:45.202184 RX Vref 0 -> 0, step: 1
901 11:51:45.202247
902 11:51:45.205223 RX Delay -130 -> 252, step: 16
903 11:51:45.208592 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
904 11:51:45.215440 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
905 11:51:45.218798 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
906 11:51:45.221847 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
907 11:51:45.225482 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
908 11:51:45.228676 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
909 11:51:45.235290 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
910 11:51:45.238480 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
911 11:51:45.242188 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
912 11:51:45.245529 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
913 11:51:45.248496 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
914 11:51:45.255334 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
915 11:51:45.258820 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
916 11:51:45.262100 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
917 11:51:45.265283 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
918 11:51:45.268481 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
919 11:51:45.271908 ==
920 11:51:45.272058 Dram Type= 6, Freq= 0, CH_0, rank 0
921 11:51:45.278383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 11:51:45.278481 ==
923 11:51:45.278567 DQS Delay:
924 11:51:45.281841 DQS0 = 0, DQS1 = 0
925 11:51:45.281927 DQM Delay:
926 11:51:45.285430 DQM0 = 81, DQM1 = 70
927 11:51:45.285519 DQ Delay:
928 11:51:45.288681 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
929 11:51:45.292114 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
930 11:51:45.295421 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =61
931 11:51:45.298514 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
932 11:51:45.298603
933 11:51:45.298670
934 11:51:45.298731 ==
935 11:51:45.301852 Dram Type= 6, Freq= 0, CH_0, rank 0
936 11:51:45.305742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 11:51:45.305831 ==
938 11:51:45.305898
939 11:51:45.305959
940 11:51:45.308809 TX Vref Scan disable
941 11:51:45.308922 == TX Byte 0 ==
942 11:51:45.315333 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 11:51:45.318647 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 11:51:45.318780 == TX Byte 1 ==
945 11:51:45.325381 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
946 11:51:45.328988 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
947 11:51:45.329094 ==
948 11:51:45.332197 Dram Type= 6, Freq= 0, CH_0, rank 0
949 11:51:45.335756 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 11:51:45.335845 ==
951 11:51:45.349512 TX Vref=22, minBit 5, minWin=26, winSum=434
952 11:51:45.352880 TX Vref=24, minBit 10, minWin=26, winSum=437
953 11:51:45.355967 TX Vref=26, minBit 14, minWin=26, winSum=441
954 11:51:45.359392 TX Vref=28, minBit 4, minWin=27, winSum=442
955 11:51:45.362726 TX Vref=30, minBit 9, minWin=27, winSum=441
956 11:51:45.369411 TX Vref=32, minBit 10, minWin=26, winSum=437
957 11:51:45.372890 [TxChooseVref] Worse bit 4, Min win 27, Win sum 442, Final Vref 28
958 11:51:45.372991
959 11:51:45.376121 Final TX Range 1 Vref 28
960 11:51:45.376275
961 11:51:45.376344 ==
962 11:51:45.379286 Dram Type= 6, Freq= 0, CH_0, rank 0
963 11:51:45.382528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 11:51:45.385854 ==
965 11:51:45.385948
966 11:51:45.386016
967 11:51:45.386077 TX Vref Scan disable
968 11:51:45.389515 == TX Byte 0 ==
969 11:51:45.392745 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
970 11:51:45.399499 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
971 11:51:45.399629 == TX Byte 1 ==
972 11:51:45.402989 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
973 11:51:45.406081 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
974 11:51:45.409269
975 11:51:45.409362 [DATLAT]
976 11:51:45.409459 Freq=800, CH0 RK0
977 11:51:45.409583
978 11:51:45.412840 DATLAT Default: 0xa
979 11:51:45.412944 0, 0xFFFF, sum = 0
980 11:51:45.416594 1, 0xFFFF, sum = 0
981 11:51:45.416687 2, 0xFFFF, sum = 0
982 11:51:45.419693 3, 0xFFFF, sum = 0
983 11:51:45.419782 4, 0xFFFF, sum = 0
984 11:51:45.422737 5, 0xFFFF, sum = 0
985 11:51:45.426207 6, 0xFFFF, sum = 0
986 11:51:45.426309 7, 0xFFFF, sum = 0
987 11:51:45.429662 8, 0xFFFF, sum = 0
988 11:51:45.429759 9, 0x0, sum = 1
989 11:51:45.429828 10, 0x0, sum = 2
990 11:51:45.432681 11, 0x0, sum = 3
991 11:51:45.432766 12, 0x0, sum = 4
992 11:51:45.436148 best_step = 10
993 11:51:45.436271
994 11:51:45.436338 ==
995 11:51:45.439512 Dram Type= 6, Freq= 0, CH_0, rank 0
996 11:51:45.442725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
997 11:51:45.442808 ==
998 11:51:45.445947 RX Vref Scan: 1
999 11:51:45.446022
1000 11:51:45.446083 Set Vref Range= 32 -> 127
1001 11:51:45.446142
1002 11:51:45.449698 RX Vref 32 -> 127, step: 1
1003 11:51:45.449783
1004 11:51:45.453126 RX Delay -111 -> 252, step: 8
1005 11:51:45.453211
1006 11:51:45.456385 Set Vref, RX VrefLevel [Byte0]: 32
1007 11:51:45.459391 [Byte1]: 32
1008 11:51:45.459479
1009 11:51:45.463110 Set Vref, RX VrefLevel [Byte0]: 33
1010 11:51:45.466005 [Byte1]: 33
1011 11:51:45.469957
1012 11:51:45.470053 Set Vref, RX VrefLevel [Byte0]: 34
1013 11:51:45.473573 [Byte1]: 34
1014 11:51:45.477844
1015 11:51:45.477938 Set Vref, RX VrefLevel [Byte0]: 35
1016 11:51:45.481135 [Byte1]: 35
1017 11:51:45.485334
1018 11:51:45.485428 Set Vref, RX VrefLevel [Byte0]: 36
1019 11:51:45.488954 [Byte1]: 36
1020 11:51:45.493009
1021 11:51:45.493098 Set Vref, RX VrefLevel [Byte0]: 37
1022 11:51:45.496067 [Byte1]: 37
1023 11:51:45.500475
1024 11:51:45.500566 Set Vref, RX VrefLevel [Byte0]: 38
1025 11:51:45.504071 [Byte1]: 38
1026 11:51:45.508430
1027 11:51:45.508546 Set Vref, RX VrefLevel [Byte0]: 39
1028 11:51:45.511418 [Byte1]: 39
1029 11:51:45.515744
1030 11:51:45.515836 Set Vref, RX VrefLevel [Byte0]: 40
1031 11:51:45.519168 [Byte1]: 40
1032 11:51:45.523500
1033 11:51:45.523590 Set Vref, RX VrefLevel [Byte0]: 41
1034 11:51:45.527163 [Byte1]: 41
1035 11:51:45.531300
1036 11:51:45.531424 Set Vref, RX VrefLevel [Byte0]: 42
1037 11:51:45.534265 [Byte1]: 42
1038 11:51:45.538713
1039 11:51:45.538804 Set Vref, RX VrefLevel [Byte0]: 43
1040 11:51:45.542148 [Byte1]: 43
1041 11:51:45.546407
1042 11:51:45.546496 Set Vref, RX VrefLevel [Byte0]: 44
1043 11:51:45.549644 [Byte1]: 44
1044 11:51:45.553961
1045 11:51:45.554052 Set Vref, RX VrefLevel [Byte0]: 45
1046 11:51:45.557428 [Byte1]: 45
1047 11:51:45.562928
1048 11:51:45.563068 Set Vref, RX VrefLevel [Byte0]: 46
1049 11:51:45.565711 [Byte1]: 46
1050 11:51:45.569935
1051 11:51:45.570031 Set Vref, RX VrefLevel [Byte0]: 47
1052 11:51:45.573161 [Byte1]: 47
1053 11:51:45.577705
1054 11:51:45.577827 Set Vref, RX VrefLevel [Byte0]: 48
1055 11:51:45.580531 [Byte1]: 48
1056 11:51:45.584888
1057 11:51:45.585000 Set Vref, RX VrefLevel [Byte0]: 49
1058 11:51:45.588352 [Byte1]: 49
1059 11:51:45.592441
1060 11:51:45.592625 Set Vref, RX VrefLevel [Byte0]: 50
1061 11:51:45.595881 [Byte1]: 50
1062 11:51:45.599859
1063 11:51:45.600047 Set Vref, RX VrefLevel [Byte0]: 51
1064 11:51:45.603510 [Byte1]: 51
1065 11:51:45.608003
1066 11:51:45.608129 Set Vref, RX VrefLevel [Byte0]: 52
1067 11:51:45.614055 [Byte1]: 52
1068 11:51:45.614165
1069 11:51:45.617927 Set Vref, RX VrefLevel [Byte0]: 53
1070 11:51:45.620853 [Byte1]: 53
1071 11:51:45.620961
1072 11:51:45.624344 Set Vref, RX VrefLevel [Byte0]: 54
1073 11:51:45.628014 [Byte1]: 54
1074 11:51:45.628122
1075 11:51:45.630948 Set Vref, RX VrefLevel [Byte0]: 55
1076 11:51:45.634364 [Byte1]: 55
1077 11:51:45.638033
1078 11:51:45.638134 Set Vref, RX VrefLevel [Byte0]: 56
1079 11:51:45.641742 [Byte1]: 56
1080 11:51:45.645777
1081 11:51:45.645873 Set Vref, RX VrefLevel [Byte0]: 57
1082 11:51:45.649282 [Byte1]: 57
1083 11:51:45.653736
1084 11:51:45.653843 Set Vref, RX VrefLevel [Byte0]: 58
1085 11:51:45.657000 [Byte1]: 58
1086 11:51:45.661266
1087 11:51:45.661388 Set Vref, RX VrefLevel [Byte0]: 59
1088 11:51:45.664159 [Byte1]: 59
1089 11:51:45.668798
1090 11:51:45.668893 Set Vref, RX VrefLevel [Byte0]: 60
1091 11:51:45.672182 [Byte1]: 60
1092 11:51:45.676765
1093 11:51:45.676903 Set Vref, RX VrefLevel [Byte0]: 61
1094 11:51:45.680002 [Byte1]: 61
1095 11:51:45.684384
1096 11:51:45.684529 Set Vref, RX VrefLevel [Byte0]: 62
1097 11:51:45.687208 [Byte1]: 62
1098 11:51:45.692103
1099 11:51:45.692266 Set Vref, RX VrefLevel [Byte0]: 63
1100 11:51:45.695075 [Byte1]: 63
1101 11:51:45.699572
1102 11:51:45.699702 Set Vref, RX VrefLevel [Byte0]: 64
1103 11:51:45.702690 [Byte1]: 64
1104 11:51:45.707385
1105 11:51:45.707508 Set Vref, RX VrefLevel [Byte0]: 65
1106 11:51:45.710464 [Byte1]: 65
1107 11:51:45.714783
1108 11:51:45.714873 Set Vref, RX VrefLevel [Byte0]: 66
1109 11:51:45.717968 [Byte1]: 66
1110 11:51:45.722359
1111 11:51:45.722481 Set Vref, RX VrefLevel [Byte0]: 67
1112 11:51:45.725487 [Byte1]: 67
1113 11:51:45.730058
1114 11:51:45.730182 Set Vref, RX VrefLevel [Byte0]: 68
1115 11:51:45.733099 [Byte1]: 68
1116 11:51:45.737321
1117 11:51:45.737446 Set Vref, RX VrefLevel [Byte0]: 69
1118 11:51:45.740866 [Byte1]: 69
1119 11:51:45.745508
1120 11:51:45.745604 Set Vref, RX VrefLevel [Byte0]: 70
1121 11:51:45.748496 [Byte1]: 70
1122 11:51:45.752612
1123 11:51:45.752782 Set Vref, RX VrefLevel [Byte0]: 71
1124 11:51:45.756260 [Byte1]: 71
1125 11:51:45.760333
1126 11:51:45.760474 Set Vref, RX VrefLevel [Byte0]: 72
1127 11:51:45.764541 [Byte1]: 72
1128 11:51:45.768330
1129 11:51:45.768473 Set Vref, RX VrefLevel [Byte0]: 73
1130 11:51:45.771723 [Byte1]: 73
1131 11:51:45.775995
1132 11:51:45.776137 Set Vref, RX VrefLevel [Byte0]: 74
1133 11:51:45.778907 [Byte1]: 74
1134 11:51:45.783900
1135 11:51:45.784029 Set Vref, RX VrefLevel [Byte0]: 75
1136 11:51:45.786968 [Byte1]: 75
1137 11:51:45.791258
1138 11:51:45.791355 Set Vref, RX VrefLevel [Byte0]: 76
1139 11:51:45.794176 [Byte1]: 76
1140 11:51:45.798757
1141 11:51:45.798852 Set Vref, RX VrefLevel [Byte0]: 77
1142 11:51:45.802240 [Byte1]: 77
1143 11:51:45.806256
1144 11:51:45.806371 Set Vref, RX VrefLevel [Byte0]: 78
1145 11:51:45.809519 [Byte1]: 78
1146 11:51:45.813900
1147 11:51:45.814003 Set Vref, RX VrefLevel [Byte0]: 79
1148 11:51:45.817384 [Byte1]: 79
1149 11:51:45.822013
1150 11:51:45.822123 Set Vref, RX VrefLevel [Byte0]: 80
1151 11:51:45.824768 [Byte1]: 80
1152 11:51:45.829252
1153 11:51:45.829369 Final RX Vref Byte 0 = 60 to rank0
1154 11:51:45.833136 Final RX Vref Byte 1 = 56 to rank0
1155 11:51:45.836108 Final RX Vref Byte 0 = 60 to rank1
1156 11:51:45.839153 Final RX Vref Byte 1 = 56 to rank1==
1157 11:51:45.843041 Dram Type= 6, Freq= 0, CH_0, rank 0
1158 11:51:45.849204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1159 11:51:45.849338 ==
1160 11:51:45.849409 DQS Delay:
1161 11:51:45.849471 DQS0 = 0, DQS1 = 0
1162 11:51:45.852829 DQM Delay:
1163 11:51:45.852922 DQM0 = 82, DQM1 = 67
1164 11:51:45.855855 DQ Delay:
1165 11:51:45.859406 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1166 11:51:45.859566 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1167 11:51:45.862849 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1168 11:51:45.866153 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1169 11:51:45.869184
1170 11:51:45.869326
1171 11:51:45.875843 [DQSOSCAuto] RK0, (LSB)MR18= 0x2928, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
1172 11:51:45.879630 CH0 RK0: MR19=606, MR18=2928
1173 11:51:45.886082 CH0_RK0: MR19=0x606, MR18=0x2928, DQSOSC=399, MR23=63, INC=92, DEC=61
1174 11:51:45.886213
1175 11:51:45.889754 ----->DramcWriteLeveling(PI) begin...
1176 11:51:45.889856 ==
1177 11:51:45.892508 Dram Type= 6, Freq= 0, CH_0, rank 1
1178 11:51:45.896039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1179 11:51:45.896147 ==
1180 11:51:45.899260 Write leveling (Byte 0): 31 => 31
1181 11:51:45.902641 Write leveling (Byte 1): 30 => 30
1182 11:51:45.906131 DramcWriteLeveling(PI) end<-----
1183 11:51:45.906236
1184 11:51:45.906306 ==
1185 11:51:45.909344 Dram Type= 6, Freq= 0, CH_0, rank 1
1186 11:51:45.912519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 11:51:45.912620 ==
1188 11:51:45.915900 [Gating] SW mode calibration
1189 11:51:45.923001 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1190 11:51:45.929554 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1191 11:51:45.932988 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1192 11:51:45.936102 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1193 11:51:45.943006 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1194 11:51:45.946028 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1195 11:51:45.949213 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:51:45.956029 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 11:51:45.959460 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 11:51:45.962470 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:51:45.969626 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:51:45.972768 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:51:45.975944 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:51:45.979634 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:51:46.026726 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 11:51:46.026863 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 11:51:46.027209 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 11:51:46.027323 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 11:51:46.027595 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 11:51:46.027683 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1209 11:51:46.027757 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1210 11:51:46.028028 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1211 11:51:46.028416 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1212 11:51:46.028517 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1213 11:51:46.071097 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 11:51:46.071291 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 11:51:46.071363 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 11:51:46.071639 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 11:51:46.071722 0 9 8 | B1->B0 | 2322 3232 | 1 0 | (0 0) (1 1)
1218 11:51:46.071984 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1219 11:51:46.072068 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1220 11:51:46.072140 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1221 11:51:46.072533 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1222 11:51:46.072832 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1223 11:51:46.075650 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1224 11:51:46.079266 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1225 11:51:46.082451 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 1) (1 0)
1226 11:51:46.085867 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:51:46.092282 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:51:46.095643 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:51:46.099384 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:51:46.102778 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:51:46.109358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:51:46.112379 0 11 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1233 11:51:46.115898 0 11 8 | B1->B0 | 2c2c 3d3d | 0 1 | (0 0) (0 0)
1234 11:51:46.122759 0 11 12 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
1235 11:51:46.125982 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 11:51:46.129771 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1237 11:51:46.136011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1238 11:51:46.139895 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1239 11:51:46.143423 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1240 11:51:46.147090 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1241 11:51:46.154022 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1242 11:51:46.157401 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1243 11:51:46.161172 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1244 11:51:46.164761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1245 11:51:46.171586 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1246 11:51:46.174679 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1247 11:51:46.178456 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1248 11:51:46.181692 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1249 11:51:46.188547 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1250 11:51:46.191474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1251 11:51:46.194890 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1252 11:51:46.201890 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1253 11:51:46.204823 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1254 11:51:46.208323 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1255 11:51:46.215179 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1256 11:51:46.218076 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1257 11:51:46.221826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1258 11:51:46.228189 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 11:51:46.228399 Total UI for P1: 0, mck2ui 16
1260 11:51:46.234956 best dqsien dly found for B0: ( 0, 14, 8)
1261 11:51:46.235084 Total UI for P1: 0, mck2ui 16
1262 11:51:46.241362 best dqsien dly found for B1: ( 0, 14, 10)
1263 11:51:46.244574 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1264 11:51:46.247928 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1265 11:51:46.248072
1266 11:51:46.251517 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1267 11:51:46.255018 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1268 11:51:46.258176 [Gating] SW calibration Done
1269 11:51:46.258319 ==
1270 11:51:46.261447 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 11:51:46.264914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 11:51:46.265050 ==
1273 11:51:46.268004 RX Vref Scan: 0
1274 11:51:46.268100
1275 11:51:46.268191 RX Vref 0 -> 0, step: 1
1276 11:51:46.268318
1277 11:51:46.271319 RX Delay -130 -> 252, step: 16
1278 11:51:46.274626 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1279 11:51:46.281596 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1280 11:51:46.284935 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1281 11:51:46.288021 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1282 11:51:46.291653 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1283 11:51:46.294920 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1284 11:51:46.301986 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1285 11:51:46.304503 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1286 11:51:46.308119 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1287 11:51:46.311481 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1288 11:51:46.315018 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1289 11:51:46.321216 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1290 11:51:46.325039 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1291 11:51:46.328596 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1292 11:51:46.331692 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1293 11:51:46.335232 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1294 11:51:46.338374 ==
1295 11:51:46.338484 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:51:46.345380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:51:46.345554 ==
1298 11:51:46.345658 DQS Delay:
1299 11:51:46.348165 DQS0 = 0, DQS1 = 0
1300 11:51:46.348307 DQM Delay:
1301 11:51:46.351402 DQM0 = 77, DQM1 = 69
1302 11:51:46.351503 DQ Delay:
1303 11:51:46.355182 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1304 11:51:46.358224 DQ4 =77, DQ5 =61, DQ6 =93, DQ7 =93
1305 11:51:46.361733 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1306 11:51:46.364871 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1307 11:51:46.365025
1308 11:51:46.365138
1309 11:51:46.365299 ==
1310 11:51:46.368455 Dram Type= 6, Freq= 0, CH_0, rank 1
1311 11:51:46.371642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1312 11:51:46.371835 ==
1313 11:51:46.371943
1314 11:51:46.372042
1315 11:51:46.375041 TX Vref Scan disable
1316 11:51:46.375166 == TX Byte 0 ==
1317 11:51:46.381848 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1318 11:51:46.384863 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1319 11:51:46.385012 == TX Byte 1 ==
1320 11:51:46.391367 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1321 11:51:46.394685 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1322 11:51:46.394797 ==
1323 11:51:46.398346 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 11:51:46.401916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 11:51:46.402040 ==
1326 11:51:46.415979 TX Vref=22, minBit 13, minWin=26, winSum=432
1327 11:51:46.418871 TX Vref=24, minBit 1, minWin=27, winSum=438
1328 11:51:46.422187 TX Vref=26, minBit 11, minWin=26, winSum=436
1329 11:51:46.425663 TX Vref=28, minBit 1, minWin=27, winSum=444
1330 11:51:46.429003 TX Vref=30, minBit 9, minWin=27, winSum=447
1331 11:51:46.435911 TX Vref=32, minBit 1, minWin=27, winSum=442
1332 11:51:46.438811 [TxChooseVref] Worse bit 9, Min win 27, Win sum 447, Final Vref 30
1333 11:51:46.438926
1334 11:51:46.442414 Final TX Range 1 Vref 30
1335 11:51:46.442520
1336 11:51:46.442587 ==
1337 11:51:46.445423 Dram Type= 6, Freq= 0, CH_0, rank 1
1338 11:51:46.448792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1339 11:51:46.448899 ==
1340 11:51:46.452230
1341 11:51:46.452344
1342 11:51:46.452412 TX Vref Scan disable
1343 11:51:46.455583 == TX Byte 0 ==
1344 11:51:46.459323 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1345 11:51:46.462626 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1346 11:51:46.465577 == TX Byte 1 ==
1347 11:51:46.469123 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1348 11:51:46.472573 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1349 11:51:46.472690
1350 11:51:46.475783 [DATLAT]
1351 11:51:46.475881 Freq=800, CH0 RK1
1352 11:51:46.475948
1353 11:51:46.479174 DATLAT Default: 0xa
1354 11:51:46.479275 0, 0xFFFF, sum = 0
1355 11:51:46.482511 1, 0xFFFF, sum = 0
1356 11:51:46.482608 2, 0xFFFF, sum = 0
1357 11:51:46.485908 3, 0xFFFF, sum = 0
1358 11:51:46.486011 4, 0xFFFF, sum = 0
1359 11:51:46.489196 5, 0xFFFF, sum = 0
1360 11:51:46.489297 6, 0xFFFF, sum = 0
1361 11:51:46.492759 7, 0xFFFF, sum = 0
1362 11:51:46.492900 8, 0xFFFF, sum = 0
1363 11:51:46.495992 9, 0x0, sum = 1
1364 11:51:46.496117 10, 0x0, sum = 2
1365 11:51:46.499527 11, 0x0, sum = 3
1366 11:51:46.499627 12, 0x0, sum = 4
1367 11:51:46.502321 best_step = 10
1368 11:51:46.502420
1369 11:51:46.502487 ==
1370 11:51:46.505873 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 11:51:46.508995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 11:51:46.509100 ==
1373 11:51:46.512483 RX Vref Scan: 0
1374 11:51:46.512585
1375 11:51:46.512653 RX Vref 0 -> 0, step: 1
1376 11:51:46.512713
1377 11:51:46.515823 RX Delay -111 -> 252, step: 8
1378 11:51:46.522547 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1379 11:51:46.526334 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1380 11:51:46.529107 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1381 11:51:46.532545 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1382 11:51:46.535505 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1383 11:51:46.542431 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1384 11:51:46.545721 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1385 11:51:46.549334 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1386 11:51:46.552486 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1387 11:51:46.555765 iDelay=209, Bit 9, Center 52 (-63 ~ 168) 232
1388 11:51:46.562532 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1389 11:51:46.565563 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1390 11:51:46.568920 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1391 11:51:46.572351 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1392 11:51:46.578841 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1393 11:51:46.582427 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1394 11:51:46.582549 ==
1395 11:51:46.585500 Dram Type= 6, Freq= 0, CH_0, rank 1
1396 11:51:46.588846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1397 11:51:46.588960 ==
1398 11:51:46.589032 DQS Delay:
1399 11:51:46.592477 DQS0 = 0, DQS1 = 0
1400 11:51:46.592584 DQM Delay:
1401 11:51:46.595305 DQM0 = 78, DQM1 = 69
1402 11:51:46.595397 DQ Delay:
1403 11:51:46.599272 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1404 11:51:46.602425 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1405 11:51:46.605593 DQ8 =60, DQ9 =52, DQ10 =72, DQ11 =60
1406 11:51:46.608959 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1407 11:51:46.609069
1408 11:51:46.609154
1409 11:51:46.618997 [DQSOSCAuto] RK1, (LSB)MR18= 0x4822, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 391 ps
1410 11:51:46.619152 CH0 RK1: MR19=606, MR18=4822
1411 11:51:46.625462 CH0_RK1: MR19=0x606, MR18=0x4822, DQSOSC=391, MR23=63, INC=96, DEC=64
1412 11:51:46.628962 [RxdqsGatingPostProcess] freq 800
1413 11:51:46.635817 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1414 11:51:46.638824 Pre-setting of DQS Precalculation
1415 11:51:46.642188 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1416 11:51:46.642322 ==
1417 11:51:46.645495 Dram Type= 6, Freq= 0, CH_1, rank 0
1418 11:51:46.648748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 11:51:46.652050 ==
1420 11:51:46.655745 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 11:51:46.662064 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 11:51:46.671136 [CA 0] Center 36 (6~66) winsize 61
1423 11:51:46.674095 [CA 1] Center 37 (7~67) winsize 61
1424 11:51:46.677591 [CA 2] Center 34 (4~64) winsize 61
1425 11:51:46.681433 [CA 3] Center 34 (4~64) winsize 61
1426 11:51:46.684375 [CA 4] Center 34 (4~65) winsize 62
1427 11:51:46.687686 [CA 5] Center 34 (4~64) winsize 61
1428 11:51:46.687806
1429 11:51:46.691331 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1430 11:51:46.691438
1431 11:51:46.694261 [CATrainingPosCal] consider 1 rank data
1432 11:51:46.697896 u2DelayCellTimex100 = 270/100 ps
1433 11:51:46.700896 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1434 11:51:46.704688 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1435 11:51:46.707654 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1436 11:51:46.714272 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1437 11:51:46.718181 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1438 11:51:46.721195 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1439 11:51:46.721304
1440 11:51:46.724607 CA PerBit enable=1, Macro0, CA PI delay=34
1441 11:51:46.724704
1442 11:51:46.727698 [CBTSetCACLKResult] CA Dly = 34
1443 11:51:46.727792 CS Dly: 5 (0~36)
1444 11:51:46.727860 ==
1445 11:51:46.730979 Dram Type= 6, Freq= 0, CH_1, rank 1
1446 11:51:46.737507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 11:51:46.737644 ==
1448 11:51:46.741115 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1449 11:51:46.747821 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1450 11:51:46.756916 [CA 0] Center 37 (7~67) winsize 61
1451 11:51:46.760236 [CA 1] Center 36 (6~67) winsize 62
1452 11:51:46.763720 [CA 2] Center 34 (4~65) winsize 62
1453 11:51:46.766701 [CA 3] Center 33 (3~64) winsize 62
1454 11:51:46.770365 [CA 4] Center 34 (4~65) winsize 62
1455 11:51:46.773930 [CA 5] Center 33 (3~64) winsize 62
1456 11:51:46.774048
1457 11:51:46.777060 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1458 11:51:46.777158
1459 11:51:46.780093 [CATrainingPosCal] consider 2 rank data
1460 11:51:46.783635 u2DelayCellTimex100 = 270/100 ps
1461 11:51:46.787358 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1462 11:51:46.790392 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1463 11:51:46.794144 CA2 delay=34 (4~64),Diff = 0 PI (0 cell)
1464 11:51:46.800437 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1465 11:51:46.805024 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 11:51:46.808038 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1467 11:51:46.808158
1468 11:51:46.811959 CA PerBit enable=1, Macro0, CA PI delay=34
1469 11:51:46.812073
1470 11:51:46.812142 [CBTSetCACLKResult] CA Dly = 34
1471 11:51:46.815582 CS Dly: 5 (0~37)
1472 11:51:46.815683
1473 11:51:46.819252 ----->DramcWriteLeveling(PI) begin...
1474 11:51:46.819363 ==
1475 11:51:46.822841 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 11:51:46.826257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 11:51:46.826389 ==
1478 11:51:46.830060 Write leveling (Byte 0): 26 => 26
1479 11:51:46.833516 Write leveling (Byte 1): 30 => 30
1480 11:51:46.837232 DramcWriteLeveling(PI) end<-----
1481 11:51:46.837366
1482 11:51:46.837469 ==
1483 11:51:46.840165 Dram Type= 6, Freq= 0, CH_1, rank 0
1484 11:51:46.843842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1485 11:51:46.843947 ==
1486 11:51:46.847200 [Gating] SW mode calibration
1487 11:51:46.853636 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1488 11:51:46.857073 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1489 11:51:46.863791 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1490 11:51:46.866917 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1491 11:51:46.870377 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1492 11:51:46.876973 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:51:46.880480 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:51:46.883329 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 11:51:46.890532 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 11:51:46.893515 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:51:46.897248 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:51:46.903657 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:51:46.907426 0 7 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1500 11:51:46.910433 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:51:46.913888 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:51:46.920789 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 11:51:46.923970 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 11:51:46.927208 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 11:51:46.934018 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 11:51:46.936895 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1507 11:51:46.940419 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1508 11:51:46.947285 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 11:51:46.950313 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 11:51:46.953610 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 11:51:46.960051 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 11:51:46.963366 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 11:51:46.966859 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 11:51:46.973795 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 11:51:46.976851 0 9 8 | B1->B0 | 2a2a 2928 | 0 1 | (0 0) (1 1)
1516 11:51:46.980511 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1517 11:51:46.986845 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1518 11:51:46.990037 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1519 11:51:46.993582 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1520 11:51:47.000148 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1521 11:51:47.003648 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1522 11:51:47.006731 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1523 11:51:47.013187 0 10 8 | B1->B0 | 2b2b 2b2b | 0 0 | (0 0) (0 0)
1524 11:51:47.016641 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:51:47.020229 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:51:47.026980 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:51:47.030216 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:51:47.033685 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:51:47.040037 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:51:47.043257 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1531 11:51:47.046622 0 11 8 | B1->B0 | 3838 3b3b | 1 0 | (0 0) (1 1)
1532 11:51:47.050229 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1533 11:51:47.056635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1534 11:51:47.059997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 11:51:47.063152 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1536 11:51:47.070369 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1537 11:51:47.073207 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1538 11:51:47.076689 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1539 11:51:47.083546 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1540 11:51:47.086785 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1541 11:51:47.090042 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1542 11:51:47.096557 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1543 11:51:47.100109 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1544 11:51:47.103221 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1545 11:51:47.110480 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1546 11:51:47.113343 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1547 11:51:47.117000 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1548 11:51:47.123240 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1549 11:51:47.127087 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1550 11:51:47.130073 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1551 11:51:47.136981 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1552 11:51:47.140021 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1553 11:51:47.143307 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1554 11:51:47.146850 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1555 11:51:47.153381 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1556 11:51:47.157185 Total UI for P1: 0, mck2ui 16
1557 11:51:47.160324 best dqsien dly found for B1: ( 0, 14, 6)
1558 11:51:47.164036 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1559 11:51:47.166900 Total UI for P1: 0, mck2ui 16
1560 11:51:47.170170 best dqsien dly found for B0: ( 0, 14, 8)
1561 11:51:47.173427 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1562 11:51:47.177354 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1563 11:51:47.177473
1564 11:51:47.180472 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1565 11:51:47.183310 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1566 11:51:47.187020 [Gating] SW calibration Done
1567 11:51:47.187155 ==
1568 11:51:47.190414 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 11:51:47.193335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 11:51:47.197218 ==
1571 11:51:47.197332 RX Vref Scan: 0
1572 11:51:47.197401
1573 11:51:47.200240 RX Vref 0 -> 0, step: 1
1574 11:51:47.200343
1575 11:51:47.200409 RX Delay -130 -> 252, step: 16
1576 11:51:47.207542 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1577 11:51:47.210378 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1578 11:51:47.213754 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1579 11:51:47.217114 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1580 11:51:47.220587 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1581 11:51:47.227434 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1582 11:51:47.230339 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1583 11:51:47.233659 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1584 11:51:47.237562 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1585 11:51:47.240461 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1586 11:51:47.247214 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1587 11:51:47.250262 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1588 11:51:47.253578 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1589 11:51:47.257007 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1590 11:51:47.260225 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1591 11:51:47.267212 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1592 11:51:47.267361 ==
1593 11:51:47.270487 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:51:47.273427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:51:47.273533 ==
1596 11:51:47.273604 DQS Delay:
1597 11:51:47.277200 DQS0 = 0, DQS1 = 0
1598 11:51:47.277296 DQM Delay:
1599 11:51:47.280407 DQM0 = 82, DQM1 = 73
1600 11:51:47.280505 DQ Delay:
1601 11:51:47.283847 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1602 11:51:47.286796 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1603 11:51:47.290335 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1604 11:51:47.293548 DQ12 =85, DQ13 =85, DQ14 =77, DQ15 =77
1605 11:51:47.293654
1606 11:51:47.293720
1607 11:51:47.293780 ==
1608 11:51:47.296732 Dram Type= 6, Freq= 0, CH_1, rank 0
1609 11:51:47.300521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1610 11:51:47.300634 ==
1611 11:51:47.303588
1612 11:51:47.303681
1613 11:51:47.303748 TX Vref Scan disable
1614 11:51:47.307105 == TX Byte 0 ==
1615 11:51:47.310271 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1616 11:51:47.313920 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1617 11:51:47.316995 == TX Byte 1 ==
1618 11:51:47.320243 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1619 11:51:47.323921 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1620 11:51:47.324038 ==
1621 11:51:47.326918 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:51:47.333905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:51:47.334047 ==
1624 11:51:47.345746 TX Vref=22, minBit 5, minWin=27, winSum=445
1625 11:51:47.349187 TX Vref=24, minBit 1, minWin=27, winSum=447
1626 11:51:47.352463 TX Vref=26, minBit 8, minWin=27, winSum=449
1627 11:51:47.355995 TX Vref=28, minBit 1, minWin=27, winSum=450
1628 11:51:47.359314 TX Vref=30, minBit 0, minWin=28, winSum=453
1629 11:51:47.365565 TX Vref=32, minBit 0, minWin=27, winSum=449
1630 11:51:47.369481 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 30
1631 11:51:47.369613
1632 11:51:47.372492 Final TX Range 1 Vref 30
1633 11:51:47.372590
1634 11:51:47.372657 ==
1635 11:51:47.375630 Dram Type= 6, Freq= 0, CH_1, rank 0
1636 11:51:47.379749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1637 11:51:47.379877 ==
1638 11:51:47.379948
1639 11:51:47.380026
1640 11:51:47.383061 TX Vref Scan disable
1641 11:51:47.386286 == TX Byte 0 ==
1642 11:51:47.389612 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1643 11:51:47.393057 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1644 11:51:47.396411 == TX Byte 1 ==
1645 11:51:47.399805 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1646 11:51:47.402913 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1647 11:51:47.403027
1648 11:51:47.406281 [DATLAT]
1649 11:51:47.406378 Freq=800, CH1 RK0
1650 11:51:47.406445
1651 11:51:47.409729 DATLAT Default: 0xa
1652 11:51:47.409821 0, 0xFFFF, sum = 0
1653 11:51:47.413034 1, 0xFFFF, sum = 0
1654 11:51:47.413131 2, 0xFFFF, sum = 0
1655 11:51:47.416635 3, 0xFFFF, sum = 0
1656 11:51:47.416732 4, 0xFFFF, sum = 0
1657 11:51:47.419676 5, 0xFFFF, sum = 0
1658 11:51:47.419771 6, 0xFFFF, sum = 0
1659 11:51:47.423719 7, 0xFFFF, sum = 0
1660 11:51:47.423848 8, 0xFFFF, sum = 0
1661 11:51:47.426333 9, 0x0, sum = 1
1662 11:51:47.426424 10, 0x0, sum = 2
1663 11:51:47.430010 11, 0x0, sum = 3
1664 11:51:47.430114 12, 0x0, sum = 4
1665 11:51:47.432942 best_step = 10
1666 11:51:47.433035
1667 11:51:47.433101 ==
1668 11:51:47.436284 Dram Type= 6, Freq= 0, CH_1, rank 0
1669 11:51:47.439646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1670 11:51:47.439752 ==
1671 11:51:47.439820 RX Vref Scan: 1
1672 11:51:47.442805
1673 11:51:47.442916 Set Vref Range= 32 -> 127
1674 11:51:47.443021
1675 11:51:47.446338 RX Vref 32 -> 127, step: 1
1676 11:51:47.446432
1677 11:51:47.449965 RX Delay -111 -> 252, step: 8
1678 11:51:47.450065
1679 11:51:47.452803 Set Vref, RX VrefLevel [Byte0]: 32
1680 11:51:47.456800 [Byte1]: 32
1681 11:51:47.456927
1682 11:51:47.459799 Set Vref, RX VrefLevel [Byte0]: 33
1683 11:51:47.463089 [Byte1]: 33
1684 11:51:47.463196
1685 11:51:47.466441 Set Vref, RX VrefLevel [Byte0]: 34
1686 11:51:47.469701 [Byte1]: 34
1687 11:51:47.473711
1688 11:51:47.473837 Set Vref, RX VrefLevel [Byte0]: 35
1689 11:51:47.477344 [Byte1]: 35
1690 11:51:47.481750
1691 11:51:47.481874 Set Vref, RX VrefLevel [Byte0]: 36
1692 11:51:47.484754 [Byte1]: 36
1693 11:51:47.489260
1694 11:51:47.489382 Set Vref, RX VrefLevel [Byte0]: 37
1695 11:51:47.492405 [Byte1]: 37
1696 11:51:47.496842
1697 11:51:47.496963 Set Vref, RX VrefLevel [Byte0]: 38
1698 11:51:47.500637 [Byte1]: 38
1699 11:51:47.504601
1700 11:51:47.504723 Set Vref, RX VrefLevel [Byte0]: 39
1701 11:51:47.507868 [Byte1]: 39
1702 11:51:47.511990
1703 11:51:47.512103 Set Vref, RX VrefLevel [Byte0]: 40
1704 11:51:47.515493 [Byte1]: 40
1705 11:51:47.519972
1706 11:51:47.520102 Set Vref, RX VrefLevel [Byte0]: 41
1707 11:51:47.522829 [Byte1]: 41
1708 11:51:47.527464
1709 11:51:47.527590 Set Vref, RX VrefLevel [Byte0]: 42
1710 11:51:47.530795 [Byte1]: 42
1711 11:51:47.534965
1712 11:51:47.535081 Set Vref, RX VrefLevel [Byte0]: 43
1713 11:51:47.538116 [Byte1]: 43
1714 11:51:47.542580
1715 11:51:47.542706 Set Vref, RX VrefLevel [Byte0]: 44
1716 11:51:47.545930 [Byte1]: 44
1717 11:51:47.550345
1718 11:51:47.550466 Set Vref, RX VrefLevel [Byte0]: 45
1719 11:51:47.553395 [Byte1]: 45
1720 11:51:47.557866
1721 11:51:47.557988 Set Vref, RX VrefLevel [Byte0]: 46
1722 11:51:47.561386 [Byte1]: 46
1723 11:51:47.565607
1724 11:51:47.565729 Set Vref, RX VrefLevel [Byte0]: 47
1725 11:51:47.569106 [Byte1]: 47
1726 11:51:47.573183
1727 11:51:47.573298 Set Vref, RX VrefLevel [Byte0]: 48
1728 11:51:47.576527 [Byte1]: 48
1729 11:51:47.580851
1730 11:51:47.580970 Set Vref, RX VrefLevel [Byte0]: 49
1731 11:51:47.584078 [Byte1]: 49
1732 11:51:47.588506
1733 11:51:47.588628 Set Vref, RX VrefLevel [Byte0]: 50
1734 11:51:47.591653 [Byte1]: 50
1735 11:51:47.596401
1736 11:51:47.596527 Set Vref, RX VrefLevel [Byte0]: 51
1737 11:51:47.599240 [Byte1]: 51
1738 11:51:47.603962
1739 11:51:47.604087 Set Vref, RX VrefLevel [Byte0]: 52
1740 11:51:47.607229 [Byte1]: 52
1741 11:51:47.611320
1742 11:51:47.611439 Set Vref, RX VrefLevel [Byte0]: 53
1743 11:51:47.614612 [Byte1]: 53
1744 11:51:47.619563
1745 11:51:47.619689 Set Vref, RX VrefLevel [Byte0]: 54
1746 11:51:47.622542 [Byte1]: 54
1747 11:51:47.626648
1748 11:51:47.626781 Set Vref, RX VrefLevel [Byte0]: 55
1749 11:51:47.629915 [Byte1]: 55
1750 11:51:47.634663
1751 11:51:47.634781 Set Vref, RX VrefLevel [Byte0]: 56
1752 11:51:47.637675 [Byte1]: 56
1753 11:51:47.641899
1754 11:51:47.642014 Set Vref, RX VrefLevel [Byte0]: 57
1755 11:51:47.645455 [Byte1]: 57
1756 11:51:47.649651
1757 11:51:47.649757 Set Vref, RX VrefLevel [Byte0]: 58
1758 11:51:47.653254 [Byte1]: 58
1759 11:51:47.657178
1760 11:51:47.657286 Set Vref, RX VrefLevel [Byte0]: 59
1761 11:51:47.660455 [Byte1]: 59
1762 11:51:47.664943
1763 11:51:47.665068 Set Vref, RX VrefLevel [Byte0]: 60
1764 11:51:47.668130 [Byte1]: 60
1765 11:51:47.673011
1766 11:51:47.673135 Set Vref, RX VrefLevel [Byte0]: 61
1767 11:51:47.676135 [Byte1]: 61
1768 11:51:47.680176
1769 11:51:47.680331 Set Vref, RX VrefLevel [Byte0]: 62
1770 11:51:47.683782 [Byte1]: 62
1771 11:51:47.688168
1772 11:51:47.688313 Set Vref, RX VrefLevel [Byte0]: 63
1773 11:51:47.691258 [Byte1]: 63
1774 11:51:47.695488
1775 11:51:47.695601 Set Vref, RX VrefLevel [Byte0]: 64
1776 11:51:47.699060 [Byte1]: 64
1777 11:51:47.703299
1778 11:51:47.703421 Set Vref, RX VrefLevel [Byte0]: 65
1779 11:51:47.707339 [Byte1]: 65
1780 11:51:47.710980
1781 11:51:47.711097 Set Vref, RX VrefLevel [Byte0]: 66
1782 11:51:47.714333 [Byte1]: 66
1783 11:51:47.718480
1784 11:51:47.718614 Set Vref, RX VrefLevel [Byte0]: 67
1785 11:51:47.721933 [Byte1]: 67
1786 11:51:47.726315
1787 11:51:47.729227 Set Vref, RX VrefLevel [Byte0]: 68
1788 11:51:47.729427 [Byte1]: 68
1789 11:51:47.733890
1790 11:51:47.734006 Set Vref, RX VrefLevel [Byte0]: 69
1791 11:51:47.737459 [Byte1]: 69
1792 11:51:47.741714
1793 11:51:47.741834 Set Vref, RX VrefLevel [Byte0]: 70
1794 11:51:47.744978 [Byte1]: 70
1795 11:51:47.749189
1796 11:51:47.749308 Set Vref, RX VrefLevel [Byte0]: 71
1797 11:51:47.752287 [Byte1]: 71
1798 11:51:47.757146
1799 11:51:47.757269 Set Vref, RX VrefLevel [Byte0]: 72
1800 11:51:47.760345 [Byte1]: 72
1801 11:51:47.764438
1802 11:51:47.764558 Set Vref, RX VrefLevel [Byte0]: 73
1803 11:51:47.767650 [Byte1]: 73
1804 11:51:47.772185
1805 11:51:47.772350 Set Vref, RX VrefLevel [Byte0]: 74
1806 11:51:47.775230 [Byte1]: 74
1807 11:51:47.779736
1808 11:51:47.779862 Final RX Vref Byte 0 = 60 to rank0
1809 11:51:47.783041 Final RX Vref Byte 1 = 53 to rank0
1810 11:51:47.786848 Final RX Vref Byte 0 = 60 to rank1
1811 11:51:47.789959 Final RX Vref Byte 1 = 53 to rank1==
1812 11:51:47.793358 Dram Type= 6, Freq= 0, CH_1, rank 0
1813 11:51:47.799980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1814 11:51:47.800127 ==
1815 11:51:47.800214 DQS Delay:
1816 11:51:47.800318 DQS0 = 0, DQS1 = 0
1817 11:51:47.803076 DQM Delay:
1818 11:51:47.803166 DQM0 = 81, DQM1 = 72
1819 11:51:47.806687 DQ Delay:
1820 11:51:47.809975 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1821 11:51:47.810080 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1822 11:51:47.813217 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1823 11:51:47.816545 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =80
1824 11:51:47.819813
1825 11:51:47.819926
1826 11:51:47.826527 [DQSOSCAuto] RK0, (LSB)MR18= 0x151f, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
1827 11:51:47.829750 CH1 RK0: MR19=606, MR18=151F
1828 11:51:47.836521 CH1_RK0: MR19=0x606, MR18=0x151F, DQSOSC=402, MR23=63, INC=91, DEC=60
1829 11:51:47.836666
1830 11:51:47.839833 ----->DramcWriteLeveling(PI) begin...
1831 11:51:47.839932 ==
1832 11:51:47.843434 Dram Type= 6, Freq= 0, CH_1, rank 1
1833 11:51:47.846462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1834 11:51:47.846572 ==
1835 11:51:47.850029 Write leveling (Byte 0): 29 => 29
1836 11:51:47.853406 Write leveling (Byte 1): 29 => 29
1837 11:51:47.856778 DramcWriteLeveling(PI) end<-----
1838 11:51:47.856890
1839 11:51:47.856961 ==
1840 11:51:47.860006 Dram Type= 6, Freq= 0, CH_1, rank 1
1841 11:51:47.863198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1842 11:51:47.863299 ==
1843 11:51:47.866607 [Gating] SW mode calibration
1844 11:51:47.873500 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1845 11:51:47.880269 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1846 11:51:47.883455 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1847 11:51:47.886956 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1848 11:51:47.893516 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1849 11:51:47.896718 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:51:47.899878 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:51:47.903755 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:51:47.910266 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:51:47.913861 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:51:47.917082 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1855 11:51:47.923752 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 11:51:47.926961 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:51:47.930123 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:51:47.936882 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 11:51:47.940008 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:51:47.943896 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:51:47.950457 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:51:47.953415 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:51:47.956545 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1864 11:51:47.963231 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 11:51:47.966918 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 11:51:47.970061 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 11:51:47.977089 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:51:47.980131 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:51:47.983723 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:51:47.989883 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:51:47.993101 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
1872 11:51:47.996617 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1873 11:51:48.003270 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1874 11:51:48.006482 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1875 11:51:48.010046 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1876 11:51:48.016728 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1877 11:51:48.019935 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1878 11:51:48.023181 0 10 0 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1879 11:51:48.026390 0 10 4 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
1880 11:51:48.033326 0 10 8 | B1->B0 | 2828 2323 | 1 0 | (1 0) (0 0)
1881 11:51:48.036392 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 11:51:48.040029 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 11:51:48.046361 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:51:48.049878 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:51:48.053185 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:51:48.060097 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:51:48.063332 0 11 4 | B1->B0 | 2c2c 3a3a | 1 0 | (0 0) (0 0)
1888 11:51:48.066414 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
1889 11:51:48.073519 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1890 11:51:48.076484 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1891 11:51:48.079788 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1892 11:51:48.086731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1893 11:51:48.089776 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1894 11:51:48.093409 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1895 11:51:48.099636 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 11:51:48.103092 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 11:51:48.106410 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 11:51:48.113119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 11:51:48.116831 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 11:51:48.119966 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 11:51:48.122987 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1902 11:51:48.130375 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1903 11:51:48.133614 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1904 11:51:48.136870 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1905 11:51:48.143653 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1906 11:51:48.146776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1907 11:51:48.150059 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1908 11:51:48.156483 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 11:51:48.160027 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 11:51:48.163722 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 11:51:48.169984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1912 11:51:48.170134 Total UI for P1: 0, mck2ui 16
1913 11:51:48.176670 best dqsien dly found for B0: ( 0, 14, 2)
1914 11:51:48.180284 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 11:51:48.183243 Total UI for P1: 0, mck2ui 16
1916 11:51:48.186392 best dqsien dly found for B1: ( 0, 14, 6)
1917 11:51:48.189791 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1918 11:51:48.193019 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1919 11:51:48.193135
1920 11:51:48.196342 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1921 11:51:48.199722 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1922 11:51:48.203280 [Gating] SW calibration Done
1923 11:51:48.203405 ==
1924 11:51:48.206635 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 11:51:48.209748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 11:51:48.209858 ==
1927 11:51:48.213393 RX Vref Scan: 0
1928 11:51:48.213500
1929 11:51:48.216577 RX Vref 0 -> 0, step: 1
1930 11:51:48.216676
1931 11:51:48.216745 RX Delay -130 -> 252, step: 16
1932 11:51:48.223170 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1933 11:51:48.226368 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1934 11:51:48.230040 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1935 11:51:48.233712 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1936 11:51:48.236393 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1937 11:51:48.243279 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1938 11:51:48.246757 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1939 11:51:48.249846 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1940 11:51:48.253226 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1941 11:51:48.256860 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1942 11:51:48.263859 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1943 11:51:48.267373 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1944 11:51:48.269939 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1945 11:51:48.273180 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1946 11:51:48.276701 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1947 11:51:48.283398 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1948 11:51:48.283536 ==
1949 11:51:48.286469 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 11:51:48.290105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 11:51:48.290232 ==
1952 11:51:48.290303 DQS Delay:
1953 11:51:48.293481 DQS0 = 0, DQS1 = 0
1954 11:51:48.293584 DQM Delay:
1955 11:51:48.297242 DQM0 = 78, DQM1 = 76
1956 11:51:48.297345 DQ Delay:
1957 11:51:48.300358 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1958 11:51:48.303351 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1959 11:51:48.306688 DQ8 =61, DQ9 =69, DQ10 =77, DQ11 =69
1960 11:51:48.309827 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
1961 11:51:48.309939
1962 11:51:48.310008
1963 11:51:48.310069 ==
1964 11:51:48.313200 Dram Type= 6, Freq= 0, CH_1, rank 1
1965 11:51:48.316530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1966 11:51:48.316640 ==
1967 11:51:48.316709
1968 11:51:48.316771
1969 11:51:48.319990 TX Vref Scan disable
1970 11:51:48.323515 == TX Byte 0 ==
1971 11:51:48.326697 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1972 11:51:48.330195 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1973 11:51:48.333356 == TX Byte 1 ==
1974 11:51:48.336630 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1975 11:51:48.340279 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1976 11:51:48.340393 ==
1977 11:51:48.343934 Dram Type= 6, Freq= 0, CH_1, rank 1
1978 11:51:48.346839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1979 11:51:48.350248 ==
1980 11:51:48.361126 TX Vref=22, minBit 1, minWin=27, winSum=447
1981 11:51:48.364726 TX Vref=24, minBit 5, minWin=27, winSum=451
1982 11:51:48.368444 TX Vref=26, minBit 5, minWin=27, winSum=456
1983 11:51:48.371200 TX Vref=28, minBit 0, minWin=28, winSum=458
1984 11:51:48.374685 TX Vref=30, minBit 1, minWin=27, winSum=455
1985 11:51:48.378413 TX Vref=32, minBit 1, minWin=27, winSum=454
1986 11:51:48.384907 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 28
1987 11:51:48.385071
1988 11:51:48.388572 Final TX Range 1 Vref 28
1989 11:51:48.388677
1990 11:51:48.388743 ==
1991 11:51:48.391527 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 11:51:48.395024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 11:51:48.395162 ==
1994 11:51:48.395261
1995 11:51:48.397973
1996 11:51:48.398056 TX Vref Scan disable
1997 11:51:48.402038 == TX Byte 0 ==
1998 11:51:48.405213 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1999 11:51:48.408469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2000 11:51:48.411437 == TX Byte 1 ==
2001 11:51:48.415226 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2002 11:51:48.418279 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2003 11:51:48.418410
2004 11:51:48.421298 [DATLAT]
2005 11:51:48.421415 Freq=800, CH1 RK1
2006 11:51:48.421514
2007 11:51:48.424648 DATLAT Default: 0xa
2008 11:51:48.424735 0, 0xFFFF, sum = 0
2009 11:51:48.428137 1, 0xFFFF, sum = 0
2010 11:51:48.428247 2, 0xFFFF, sum = 0
2011 11:51:48.431379 3, 0xFFFF, sum = 0
2012 11:51:48.431467 4, 0xFFFF, sum = 0
2013 11:51:48.434634 5, 0xFFFF, sum = 0
2014 11:51:48.434760 6, 0xFFFF, sum = 0
2015 11:51:48.438063 7, 0xFFFF, sum = 0
2016 11:51:48.438176 8, 0xFFFF, sum = 0
2017 11:51:48.441283 9, 0x0, sum = 1
2018 11:51:48.441382 10, 0x0, sum = 2
2019 11:51:48.444635 11, 0x0, sum = 3
2020 11:51:48.444774 12, 0x0, sum = 4
2021 11:51:48.448360 best_step = 10
2022 11:51:48.448459
2023 11:51:48.448523 ==
2024 11:51:48.451325 Dram Type= 6, Freq= 0, CH_1, rank 1
2025 11:51:48.454942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2026 11:51:48.455052 ==
2027 11:51:48.458053 RX Vref Scan: 0
2028 11:51:48.458145
2029 11:51:48.458207 RX Vref 0 -> 0, step: 1
2030 11:51:48.458266
2031 11:51:48.461243 RX Delay -111 -> 252, step: 8
2032 11:51:48.468171 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2033 11:51:48.471373 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2034 11:51:48.474960 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2035 11:51:48.478196 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
2036 11:51:48.481870 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2037 11:51:48.488234 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2038 11:51:48.492071 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2039 11:51:48.495101 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2040 11:51:48.498353 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
2041 11:51:48.502012 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2042 11:51:48.508468 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
2043 11:51:48.511722 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2044 11:51:48.515466 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
2045 11:51:48.518435 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
2046 11:51:48.521733 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2047 11:51:48.528460 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2048 11:51:48.528624 ==
2049 11:51:48.531576 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 11:51:48.534907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 11:51:48.535013 ==
2052 11:51:48.535081 DQS Delay:
2053 11:51:48.538619 DQS0 = 0, DQS1 = 0
2054 11:51:48.538744 DQM Delay:
2055 11:51:48.541567 DQM0 = 78, DQM1 = 75
2056 11:51:48.541652 DQ Delay:
2057 11:51:48.545038 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =72
2058 11:51:48.548565 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2059 11:51:48.551785 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =68
2060 11:51:48.554756 DQ12 =84, DQ13 =84, DQ14 =80, DQ15 =80
2061 11:51:48.554871
2062 11:51:48.554990
2063 11:51:48.561491 [DQSOSCAuto] RK1, (LSB)MR18= 0x2841, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
2064 11:51:48.565048 CH1 RK1: MR19=606, MR18=2841
2065 11:51:48.571409 CH1_RK1: MR19=0x606, MR18=0x2841, DQSOSC=393, MR23=63, INC=95, DEC=63
2066 11:51:48.574736 [RxdqsGatingPostProcess] freq 800
2067 11:51:48.581491 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2068 11:51:48.581638 Pre-setting of DQS Precalculation
2069 11:51:48.588143 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2070 11:51:48.594595 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2071 11:51:48.601657 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2072 11:51:48.601823
2073 11:51:48.601920
2074 11:51:48.605215 [Calibration Summary] 1600 Mbps
2075 11:51:48.608477 CH 0, Rank 0
2076 11:51:48.608579 SW Impedance : PASS
2077 11:51:48.611336 DUTY Scan : NO K
2078 11:51:48.614496 ZQ Calibration : PASS
2079 11:51:48.614597 Jitter Meter : NO K
2080 11:51:48.618168 CBT Training : PASS
2081 11:51:48.621356 Write leveling : PASS
2082 11:51:48.621486 RX DQS gating : PASS
2083 11:51:48.625235 RX DQ/DQS(RDDQC) : PASS
2084 11:51:48.628014 TX DQ/DQS : PASS
2085 11:51:48.628142 RX DATLAT : PASS
2086 11:51:48.631376 RX DQ/DQS(Engine): PASS
2087 11:51:48.631481 TX OE : NO K
2088 11:51:48.634631 All Pass.
2089 11:51:48.634719
2090 11:51:48.634783 CH 0, Rank 1
2091 11:51:48.638217 SW Impedance : PASS
2092 11:51:48.638339 DUTY Scan : NO K
2093 11:51:48.641309 ZQ Calibration : PASS
2094 11:51:48.644702 Jitter Meter : NO K
2095 11:51:48.644804 CBT Training : PASS
2096 11:51:48.648251 Write leveling : PASS
2097 11:51:48.651590 RX DQS gating : PASS
2098 11:51:48.651691 RX DQ/DQS(RDDQC) : PASS
2099 11:51:48.654746 TX DQ/DQS : PASS
2100 11:51:48.658217 RX DATLAT : PASS
2101 11:51:48.658323 RX DQ/DQS(Engine): PASS
2102 11:51:48.661469 TX OE : NO K
2103 11:51:48.661565 All Pass.
2104 11:51:48.661630
2105 11:51:48.665254 CH 1, Rank 0
2106 11:51:48.665368 SW Impedance : PASS
2107 11:51:48.667951 DUTY Scan : NO K
2108 11:51:48.668040 ZQ Calibration : PASS
2109 11:51:48.671577 Jitter Meter : NO K
2110 11:51:48.674609 CBT Training : PASS
2111 11:51:48.674712 Write leveling : PASS
2112 11:51:48.678151 RX DQS gating : PASS
2113 11:51:48.681492 RX DQ/DQS(RDDQC) : PASS
2114 11:51:48.681614 TX DQ/DQS : PASS
2115 11:51:48.684699 RX DATLAT : PASS
2116 11:51:48.688151 RX DQ/DQS(Engine): PASS
2117 11:51:48.688320 TX OE : NO K
2118 11:51:48.691878 All Pass.
2119 11:51:48.691986
2120 11:51:48.692056 CH 1, Rank 1
2121 11:51:48.694847 SW Impedance : PASS
2122 11:51:48.694957 DUTY Scan : NO K
2123 11:51:48.698281 ZQ Calibration : PASS
2124 11:51:48.701534 Jitter Meter : NO K
2125 11:51:48.701641 CBT Training : PASS
2126 11:51:48.704648 Write leveling : PASS
2127 11:51:48.708248 RX DQS gating : PASS
2128 11:51:48.708358 RX DQ/DQS(RDDQC) : PASS
2129 11:51:48.711388 TX DQ/DQS : PASS
2130 11:51:48.711483 RX DATLAT : PASS
2131 11:51:48.714973 RX DQ/DQS(Engine): PASS
2132 11:51:48.718174 TX OE : NO K
2133 11:51:48.718281 All Pass.
2134 11:51:48.718350
2135 11:51:48.721744 DramC Write-DBI off
2136 11:51:48.721845 PER_BANK_REFRESH: Hybrid Mode
2137 11:51:48.725062 TX_TRACKING: ON
2138 11:51:48.728246 [GetDramInforAfterCalByMRR] Vendor 6.
2139 11:51:48.731411 [GetDramInforAfterCalByMRR] Revision 606.
2140 11:51:48.734930 [GetDramInforAfterCalByMRR] Revision 2 0.
2141 11:51:48.735042 MR0 0x3b3b
2142 11:51:48.738215 MR8 0x5151
2143 11:51:48.741326 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2144 11:51:48.741438
2145 11:51:48.741508 MR0 0x3b3b
2146 11:51:48.745143 MR8 0x5151
2147 11:51:48.747926 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2148 11:51:48.748027
2149 11:51:48.754910 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2150 11:51:48.758205 [FAST_K] Save calibration result to emmc
2151 11:51:48.764727 [FAST_K] Save calibration result to emmc
2152 11:51:48.764873 dram_init: config_dvfs: 1
2153 11:51:48.768029 dramc_set_vcore_voltage set vcore to 662500
2154 11:51:48.771143 Read voltage for 1200, 2
2155 11:51:48.771249 Vio18 = 0
2156 11:51:48.774887 Vcore = 662500
2157 11:51:48.774989 Vdram = 0
2158 11:51:48.775059 Vddq = 0
2159 11:51:48.777859 Vmddr = 0
2160 11:51:48.781460 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2161 11:51:48.787857 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2162 11:51:48.788002 MEM_TYPE=3, freq_sel=15
2163 11:51:48.791223 sv_algorithm_assistance_LP4_1600
2164 11:51:48.798277 ============ PULL DRAM RESETB DOWN ============
2165 11:51:48.801595 ========== PULL DRAM RESETB DOWN end =========
2166 11:51:48.804973 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2167 11:51:48.808232 ===================================
2168 11:51:48.811216 LPDDR4 DRAM CONFIGURATION
2169 11:51:48.814412 ===================================
2170 11:51:48.814529 EX_ROW_EN[0] = 0x0
2171 11:51:48.818182 EX_ROW_EN[1] = 0x0
2172 11:51:48.821242 LP4Y_EN = 0x0
2173 11:51:48.821432 WORK_FSP = 0x0
2174 11:51:48.824819 WL = 0x4
2175 11:51:48.824933 RL = 0x4
2176 11:51:48.827921 BL = 0x2
2177 11:51:48.828036 RPST = 0x0
2178 11:51:48.831392 RD_PRE = 0x0
2179 11:51:48.831493 WR_PRE = 0x1
2180 11:51:48.834750 WR_PST = 0x0
2181 11:51:48.834849 DBI_WR = 0x0
2182 11:51:48.837985 DBI_RD = 0x0
2183 11:51:48.838119 OTF = 0x1
2184 11:51:48.841693 ===================================
2185 11:51:48.845278 ===================================
2186 11:51:48.848193 ANA top config
2187 11:51:48.851587 ===================================
2188 11:51:48.851714 DLL_ASYNC_EN = 0
2189 11:51:48.854576 ALL_SLAVE_EN = 0
2190 11:51:48.858515 NEW_RANK_MODE = 1
2191 11:51:48.861580 DLL_IDLE_MODE = 1
2192 11:51:48.861692 LP45_APHY_COMB_EN = 1
2193 11:51:48.865051 TX_ODT_DIS = 1
2194 11:51:48.868580 NEW_8X_MODE = 1
2195 11:51:48.871757 ===================================
2196 11:51:48.875063 ===================================
2197 11:51:48.878224 data_rate = 2400
2198 11:51:48.881776 CKR = 1
2199 11:51:48.881894 DQ_P2S_RATIO = 8
2200 11:51:48.884832 ===================================
2201 11:51:48.888119 CA_P2S_RATIO = 8
2202 11:51:48.891769 DQ_CA_OPEN = 0
2203 11:51:48.895070 DQ_SEMI_OPEN = 0
2204 11:51:48.898668 CA_SEMI_OPEN = 0
2205 11:51:48.901601 CA_FULL_RATE = 0
2206 11:51:48.901716 DQ_CKDIV4_EN = 0
2207 11:51:48.905367 CA_CKDIV4_EN = 0
2208 11:51:48.908599 CA_PREDIV_EN = 0
2209 11:51:48.911487 PH8_DLY = 17
2210 11:51:48.914845 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2211 11:51:48.918548 DQ_AAMCK_DIV = 4
2212 11:51:48.918664 CA_AAMCK_DIV = 4
2213 11:51:48.921476 CA_ADMCK_DIV = 4
2214 11:51:48.924956 DQ_TRACK_CA_EN = 0
2215 11:51:48.928024 CA_PICK = 1200
2216 11:51:48.931578 CA_MCKIO = 1200
2217 11:51:48.934882 MCKIO_SEMI = 0
2218 11:51:48.938269 PLL_FREQ = 2366
2219 11:51:48.938382 DQ_UI_PI_RATIO = 32
2220 11:51:48.941469 CA_UI_PI_RATIO = 0
2221 11:51:48.944633 ===================================
2222 11:51:48.948112 ===================================
2223 11:51:48.951248 memory_type:LPDDR4
2224 11:51:48.954803 GP_NUM : 10
2225 11:51:48.954921 SRAM_EN : 1
2226 11:51:48.958181 MD32_EN : 0
2227 11:51:48.961565 ===================================
2228 11:51:48.964641 [ANA_INIT] >>>>>>>>>>>>>>
2229 11:51:48.964757 <<<<<< [CONFIGURE PHASE]: ANA_TX
2230 11:51:48.968226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2231 11:51:48.971295 ===================================
2232 11:51:48.974964 data_rate = 2400,PCW = 0X5b00
2233 11:51:48.977838 ===================================
2234 11:51:48.981677 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2235 11:51:48.987789 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2236 11:51:48.994437 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2237 11:51:48.997885 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2238 11:51:49.001213 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2239 11:51:49.004787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2240 11:51:49.007886 [ANA_INIT] flow start
2241 11:51:49.007997 [ANA_INIT] PLL >>>>>>>>
2242 11:51:49.011334 [ANA_INIT] PLL <<<<<<<<
2243 11:51:49.014655 [ANA_INIT] MIDPI >>>>>>>>
2244 11:51:49.017796 [ANA_INIT] MIDPI <<<<<<<<
2245 11:51:49.017905 [ANA_INIT] DLL >>>>>>>>
2246 11:51:49.021382 [ANA_INIT] DLL <<<<<<<<
2247 11:51:49.021485 [ANA_INIT] flow end
2248 11:51:49.027635 ============ LP4 DIFF to SE enter ============
2249 11:51:49.031476 ============ LP4 DIFF to SE exit ============
2250 11:51:49.034633 [ANA_INIT] <<<<<<<<<<<<<
2251 11:51:49.037640 [Flow] Enable top DCM control >>>>>
2252 11:51:49.041229 [Flow] Enable top DCM control <<<<<
2253 11:51:49.041348 Enable DLL master slave shuffle
2254 11:51:49.047838 ==============================================================
2255 11:51:49.050986 Gating Mode config
2256 11:51:49.054675 ==============================================================
2257 11:51:49.057825 Config description:
2258 11:51:49.068096 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2259 11:51:49.074335 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2260 11:51:49.078182 SELPH_MODE 0: By rank 1: By Phase
2261 11:51:49.084162 ==============================================================
2262 11:51:49.088034 GAT_TRACK_EN = 1
2263 11:51:49.091107 RX_GATING_MODE = 2
2264 11:51:49.094662 RX_GATING_TRACK_MODE = 2
2265 11:51:49.094790 SELPH_MODE = 1
2266 11:51:49.097711 PICG_EARLY_EN = 1
2267 11:51:49.101219 VALID_LAT_VALUE = 1
2268 11:51:49.107671 ==============================================================
2269 11:51:49.111282 Enter into Gating configuration >>>>
2270 11:51:49.114417 Exit from Gating configuration <<<<
2271 11:51:49.117994 Enter into DVFS_PRE_config >>>>>
2272 11:51:49.128123 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2273 11:51:49.131367 Exit from DVFS_PRE_config <<<<<
2274 11:51:49.134428 Enter into PICG configuration >>>>
2275 11:51:49.138147 Exit from PICG configuration <<<<
2276 11:51:49.141376 [RX_INPUT] configuration >>>>>
2277 11:51:49.144872 [RX_INPUT] configuration <<<<<
2278 11:51:49.147851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2279 11:51:49.154437 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2280 11:51:49.161568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2281 11:51:49.167750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2282 11:51:49.171064 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2283 11:51:49.178488 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2284 11:51:49.181406 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2285 11:51:49.188008 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2286 11:51:49.191177 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2287 11:51:49.194494 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2288 11:51:49.197992 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2289 11:51:49.204472 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2290 11:51:49.208160 ===================================
2291 11:51:49.208317 LPDDR4 DRAM CONFIGURATION
2292 11:51:49.211255 ===================================
2293 11:51:49.214537 EX_ROW_EN[0] = 0x0
2294 11:51:49.218161 EX_ROW_EN[1] = 0x0
2295 11:51:49.218277 LP4Y_EN = 0x0
2296 11:51:49.221119 WORK_FSP = 0x0
2297 11:51:49.221212 WL = 0x4
2298 11:51:49.224557 RL = 0x4
2299 11:51:49.224656 BL = 0x2
2300 11:51:49.228186 RPST = 0x0
2301 11:51:49.228325 RD_PRE = 0x0
2302 11:51:49.231283 WR_PRE = 0x1
2303 11:51:49.231375 WR_PST = 0x0
2304 11:51:49.234576 DBI_WR = 0x0
2305 11:51:49.234675 DBI_RD = 0x0
2306 11:51:49.237774 OTF = 0x1
2307 11:51:49.241095 ===================================
2308 11:51:49.244611 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2309 11:51:49.248391 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2310 11:51:49.254662 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2311 11:51:49.257855 ===================================
2312 11:51:49.257972 LPDDR4 DRAM CONFIGURATION
2313 11:51:49.261533 ===================================
2314 11:51:49.264526 EX_ROW_EN[0] = 0x10
2315 11:51:49.264636 EX_ROW_EN[1] = 0x0
2316 11:51:49.267960 LP4Y_EN = 0x0
2317 11:51:49.268067 WORK_FSP = 0x0
2318 11:51:49.271453 WL = 0x4
2319 11:51:49.271558 RL = 0x4
2320 11:51:49.275004 BL = 0x2
2321 11:51:49.275106 RPST = 0x0
2322 11:51:49.278010 RD_PRE = 0x0
2323 11:51:49.278106 WR_PRE = 0x1
2324 11:51:49.281853 WR_PST = 0x0
2325 11:51:49.284659 DBI_WR = 0x0
2326 11:51:49.284766 DBI_RD = 0x0
2327 11:51:49.288140 OTF = 0x1
2328 11:51:49.291903 ===================================
2329 11:51:49.294760 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2330 11:51:49.294892 ==
2331 11:51:49.298128 Dram Type= 6, Freq= 0, CH_0, rank 0
2332 11:51:49.304685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2333 11:51:49.304837 ==
2334 11:51:49.304907 [Duty_Offset_Calibration]
2335 11:51:49.308060 B0:2 B1:0 CA:3
2336 11:51:49.308156
2337 11:51:49.311492 [DutyScan_Calibration_Flow] k_type=0
2338 11:51:49.320559
2339 11:51:49.320711 ==CLK 0==
2340 11:51:49.323851 Final CLK duty delay cell = 0
2341 11:51:49.327094 [0] MAX Duty = 5062%(X100), DQS PI = 20
2342 11:51:49.330823 [0] MIN Duty = 4906%(X100), DQS PI = 54
2343 11:51:49.330943 [0] AVG Duty = 4984%(X100)
2344 11:51:49.334046
2345 11:51:49.337072 CH0 CLK Duty spec in!! Max-Min= 156%
2346 11:51:49.340800 [DutyScan_Calibration_Flow] ====Done====
2347 11:51:49.340913
2348 11:51:49.343917 [DutyScan_Calibration_Flow] k_type=1
2349 11:51:49.359888
2350 11:51:49.360042 ==DQS 0 ==
2351 11:51:49.363158 Final DQS duty delay cell = 0
2352 11:51:49.366531 [0] MAX Duty = 5062%(X100), DQS PI = 12
2353 11:51:49.369969 [0] MIN Duty = 4907%(X100), DQS PI = 46
2354 11:51:49.373231 [0] AVG Duty = 4984%(X100)
2355 11:51:49.373343
2356 11:51:49.373410 ==DQS 1 ==
2357 11:51:49.376391 Final DQS duty delay cell = 0
2358 11:51:49.379979 [0] MAX Duty = 5125%(X100), DQS PI = 24
2359 11:51:49.383083 [0] MIN Duty = 5062%(X100), DQS PI = 0
2360 11:51:49.386857 [0] AVG Duty = 5093%(X100)
2361 11:51:49.386975
2362 11:51:49.390554 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2363 11:51:49.390663
2364 11:51:49.393410 CH0 DQS 1 Duty spec in!! Max-Min= 63%
2365 11:51:49.396896 [DutyScan_Calibration_Flow] ====Done====
2366 11:51:49.397009
2367 11:51:49.400155 [DutyScan_Calibration_Flow] k_type=3
2368 11:51:49.417357
2369 11:51:49.417506 ==DQM 0 ==
2370 11:51:49.420472 Final DQM duty delay cell = 0
2371 11:51:49.423712 [0] MAX Duty = 5124%(X100), DQS PI = 28
2372 11:51:49.427210 [0] MIN Duty = 4907%(X100), DQS PI = 0
2373 11:51:49.427333 [0] AVG Duty = 5015%(X100)
2374 11:51:49.430357
2375 11:51:49.430451 ==DQM 1 ==
2376 11:51:49.433696 Final DQM duty delay cell = 4
2377 11:51:49.437429 [4] MAX Duty = 5124%(X100), DQS PI = 0
2378 11:51:49.440735 [4] MIN Duty = 5031%(X100), DQS PI = 12
2379 11:51:49.440880 [4] AVG Duty = 5077%(X100)
2380 11:51:49.440985
2381 11:51:49.447263 CH0 DQM 0 Duty spec in!! Max-Min= 217%
2382 11:51:49.447415
2383 11:51:49.450321 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2384 11:51:49.454090 [DutyScan_Calibration_Flow] ====Done====
2385 11:51:49.454212
2386 11:51:49.457115 [DutyScan_Calibration_Flow] k_type=2
2387 11:51:49.472021
2388 11:51:49.472175 ==DQ 0 ==
2389 11:51:49.475154 Final DQ duty delay cell = -4
2390 11:51:49.478491 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2391 11:51:49.481995 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2392 11:51:49.485515 [-4] AVG Duty = 4969%(X100)
2393 11:51:49.485638
2394 11:51:49.485705 ==DQ 1 ==
2395 11:51:49.488681 Final DQ duty delay cell = -4
2396 11:51:49.491786 [-4] MAX Duty = 5000%(X100), DQS PI = 48
2397 11:51:49.495435 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2398 11:51:49.498472 [-4] AVG Duty = 4938%(X100)
2399 11:51:49.498613
2400 11:51:49.502144 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2401 11:51:49.502275
2402 11:51:49.505298 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2403 11:51:49.508759 [DutyScan_Calibration_Flow] ====Done====
2404 11:51:49.508897 ==
2405 11:51:49.511845 Dram Type= 6, Freq= 0, CH_1, rank 0
2406 11:51:49.515154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2407 11:51:49.515293 ==
2408 11:51:49.518371 [Duty_Offset_Calibration]
2409 11:51:49.518499 B0:1 B1:-2 CA:0
2410 11:51:49.518615
2411 11:51:49.522122 [DutyScan_Calibration_Flow] k_type=0
2412 11:51:49.532847
2413 11:51:49.533054 ==CLK 0==
2414 11:51:49.535980 Final CLK duty delay cell = 0
2415 11:51:49.539610 [0] MAX Duty = 5031%(X100), DQS PI = 16
2416 11:51:49.542862 [0] MIN Duty = 4907%(X100), DQS PI = 0
2417 11:51:49.543003 [0] AVG Duty = 4969%(X100)
2418 11:51:49.543102
2419 11:51:49.545970 CH1 CLK Duty spec in!! Max-Min= 124%
2420 11:51:49.552405 [DutyScan_Calibration_Flow] ====Done====
2421 11:51:49.552662
2422 11:51:49.555699 [DutyScan_Calibration_Flow] k_type=1
2423 11:51:49.571017
2424 11:51:49.571212 ==DQS 0 ==
2425 11:51:49.574132 Final DQS duty delay cell = -4
2426 11:51:49.577834 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2427 11:51:49.580861 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2428 11:51:49.584114 [-4] AVG Duty = 4969%(X100)
2429 11:51:49.584288
2430 11:51:49.584402 ==DQS 1 ==
2431 11:51:49.587626 Final DQS duty delay cell = 0
2432 11:51:49.591207 [0] MAX Duty = 5093%(X100), DQS PI = 0
2433 11:51:49.594080 [0] MIN Duty = 4875%(X100), DQS PI = 26
2434 11:51:49.597271 [0] AVG Duty = 4984%(X100)
2435 11:51:49.597411
2436 11:51:49.600672 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2437 11:51:49.600798
2438 11:51:49.604133 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2439 11:51:49.607887 [DutyScan_Calibration_Flow] ====Done====
2440 11:51:49.608010
2441 11:51:49.611268 [DutyScan_Calibration_Flow] k_type=3
2442 11:51:49.627690
2443 11:51:49.627845 ==DQM 0 ==
2444 11:51:49.631002 Final DQM duty delay cell = 0
2445 11:51:49.634571 [0] MAX Duty = 5000%(X100), DQS PI = 22
2446 11:51:49.637489 [0] MIN Duty = 4844%(X100), DQS PI = 52
2447 11:51:49.641012 [0] AVG Duty = 4922%(X100)
2448 11:51:49.641130
2449 11:51:49.641202 ==DQM 1 ==
2450 11:51:49.644198 Final DQM duty delay cell = 0
2451 11:51:49.647480 [0] MAX Duty = 5062%(X100), DQS PI = 38
2452 11:51:49.650900 [0] MIN Duty = 4907%(X100), DQS PI = 2
2453 11:51:49.654152 [0] AVG Duty = 4984%(X100)
2454 11:51:49.654268
2455 11:51:49.657450 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2456 11:51:49.657549
2457 11:51:49.660714 CH1 DQM 1 Duty spec in!! Max-Min= 155%
2458 11:51:49.664391 [DutyScan_Calibration_Flow] ====Done====
2459 11:51:49.664502
2460 11:51:49.667709 [DutyScan_Calibration_Flow] k_type=2
2461 11:51:49.684147
2462 11:51:49.684346 ==DQ 0 ==
2463 11:51:49.687253 Final DQ duty delay cell = 0
2464 11:51:49.690747 [0] MAX Duty = 5062%(X100), DQS PI = 18
2465 11:51:49.693998 [0] MIN Duty = 4907%(X100), DQS PI = 56
2466 11:51:49.694118 [0] AVG Duty = 4984%(X100)
2467 11:51:49.694189
2468 11:51:49.697728 ==DQ 1 ==
2469 11:51:49.700719 Final DQ duty delay cell = 0
2470 11:51:49.704553 [0] MAX Duty = 5125%(X100), DQS PI = 36
2471 11:51:49.707589 [0] MIN Duty = 4969%(X100), DQS PI = 26
2472 11:51:49.707701 [0] AVG Duty = 5047%(X100)
2473 11:51:49.707769
2474 11:51:49.710491 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2475 11:51:49.714203
2476 11:51:49.717218 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2477 11:51:49.720431 [DutyScan_Calibration_Flow] ====Done====
2478 11:51:49.723975 nWR fixed to 30
2479 11:51:49.724144 [ModeRegInit_LP4] CH0 RK0
2480 11:51:49.727217 [ModeRegInit_LP4] CH0 RK1
2481 11:51:49.730996 [ModeRegInit_LP4] CH1 RK0
2482 11:51:49.731109 [ModeRegInit_LP4] CH1 RK1
2483 11:51:49.734119 match AC timing 7
2484 11:51:49.737194 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2485 11:51:49.743562 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2486 11:51:49.747258 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2487 11:51:49.753725 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2488 11:51:49.757203 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2489 11:51:49.757324 ==
2490 11:51:49.760794 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 11:51:49.763853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 11:51:49.763957 ==
2493 11:51:49.770370 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 11:51:49.777165 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2495 11:51:49.784160 [CA 0] Center 40 (10~71) winsize 62
2496 11:51:49.787474 [CA 1] Center 39 (9~70) winsize 62
2497 11:51:49.790732 [CA 2] Center 36 (6~66) winsize 61
2498 11:51:49.794273 [CA 3] Center 35 (5~66) winsize 62
2499 11:51:49.797253 [CA 4] Center 34 (4~65) winsize 62
2500 11:51:49.800781 [CA 5] Center 33 (3~63) winsize 61
2501 11:51:49.800903
2502 11:51:49.804191 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2503 11:51:49.804322
2504 11:51:49.807382 [CATrainingPosCal] consider 1 rank data
2505 11:51:49.810521 u2DelayCellTimex100 = 270/100 ps
2506 11:51:49.814266 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2507 11:51:49.820763 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2508 11:51:49.823731 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2509 11:51:49.827472 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 11:51:49.830559 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2511 11:51:49.834412 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2512 11:51:49.834569
2513 11:51:49.837663 CA PerBit enable=1, Macro0, CA PI delay=33
2514 11:51:49.837786
2515 11:51:49.840714 [CBTSetCACLKResult] CA Dly = 33
2516 11:51:49.840833 CS Dly: 7 (0~38)
2517 11:51:49.844125 ==
2518 11:51:49.847433 Dram Type= 6, Freq= 0, CH_0, rank 1
2519 11:51:49.850678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 11:51:49.850793 ==
2521 11:51:49.854100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 11:51:49.860331 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2523 11:51:49.870186 [CA 0] Center 40 (10~70) winsize 61
2524 11:51:49.873294 [CA 1] Center 39 (9~70) winsize 62
2525 11:51:49.876973 [CA 2] Center 35 (5~66) winsize 62
2526 11:51:49.880134 [CA 3] Center 35 (5~66) winsize 62
2527 11:51:49.883375 [CA 4] Center 34 (3~65) winsize 63
2528 11:51:49.886825 [CA 5] Center 33 (3~64) winsize 62
2529 11:51:49.886946
2530 11:51:49.890028 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2531 11:51:49.890127
2532 11:51:49.893470 [CATrainingPosCal] consider 2 rank data
2533 11:51:49.896488 u2DelayCellTimex100 = 270/100 ps
2534 11:51:49.899993 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2535 11:51:49.903797 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2536 11:51:49.910019 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2537 11:51:49.913790 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 11:51:49.916995 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2539 11:51:49.920399 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2540 11:51:49.920546
2541 11:51:49.923340 CA PerBit enable=1, Macro0, CA PI delay=33
2542 11:51:49.923438
2543 11:51:49.926728 [CBTSetCACLKResult] CA Dly = 33
2544 11:51:49.926835 CS Dly: 8 (0~40)
2545 11:51:49.930032
2546 11:51:49.933414 ----->DramcWriteLeveling(PI) begin...
2547 11:51:49.933531 ==
2548 11:51:49.937118 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 11:51:49.940012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 11:51:49.940119 ==
2551 11:51:49.943840 Write leveling (Byte 0): 34 => 34
2552 11:51:49.946801 Write leveling (Byte 1): 27 => 27
2553 11:51:49.950040 DramcWriteLeveling(PI) end<-----
2554 11:51:49.950152
2555 11:51:49.950221 ==
2556 11:51:49.953260 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 11:51:49.956721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 11:51:49.956833 ==
2559 11:51:49.960116 [Gating] SW mode calibration
2560 11:51:49.966765 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2561 11:51:49.973404 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2562 11:51:49.976822 0 15 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
2563 11:51:49.980046 0 15 4 | B1->B0 | 2c2c 3434 | 1 0 | (0 0) (0 0)
2564 11:51:49.983281 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 11:51:49.990119 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 11:51:49.993513 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 11:51:49.997014 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 11:51:50.003355 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 11:51:50.006533 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2570 11:51:50.009950 1 0 0 | B1->B0 | 3333 2b2b | 1 0 | (1 0) (0 0)
2571 11:51:50.016598 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2572 11:51:50.020349 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 11:51:50.023506 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 11:51:50.030374 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 11:51:50.033549 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 11:51:50.036815 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2577 11:51:50.043300 1 0 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2578 11:51:50.046854 1 1 0 | B1->B0 | 2727 3535 | 0 1 | (0 0) (0 0)
2579 11:51:50.050106 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2580 11:51:50.056791 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 11:51:50.060269 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 11:51:50.063211 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 11:51:50.070001 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 11:51:50.073369 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 11:51:50.077232 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 11:51:50.080312 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2587 11:51:50.086727 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 11:51:50.090079 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 11:51:50.093746 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 11:51:50.100396 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 11:51:50.103411 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 11:51:50.106833 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 11:51:50.113664 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 11:51:50.117200 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 11:51:50.120402 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 11:51:50.126783 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 11:51:50.130033 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 11:51:50.133348 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 11:51:50.140086 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 11:51:50.143370 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 11:51:50.146707 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 11:51:50.153668 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2603 11:51:50.156932 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2604 11:51:50.160668 Total UI for P1: 0, mck2ui 16
2605 11:51:50.163795 best dqsien dly found for B0: ( 1, 4, 0)
2606 11:51:50.167165 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 11:51:50.169976 Total UI for P1: 0, mck2ui 16
2608 11:51:50.173494 best dqsien dly found for B1: ( 1, 4, 2)
2609 11:51:50.176924 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2610 11:51:50.180138 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2611 11:51:50.180289
2612 11:51:50.183358 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2613 11:51:50.187070 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2614 11:51:50.189942 [Gating] SW calibration Done
2615 11:51:50.190054 ==
2616 11:51:50.193820 Dram Type= 6, Freq= 0, CH_0, rank 0
2617 11:51:50.196733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2618 11:51:50.200021 ==
2619 11:51:50.200130 RX Vref Scan: 0
2620 11:51:50.200199
2621 11:51:50.203487 RX Vref 0 -> 0, step: 1
2622 11:51:50.203585
2623 11:51:50.206899 RX Delay -40 -> 252, step: 8
2624 11:51:50.209953 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2625 11:51:50.213188 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2626 11:51:50.216874 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2627 11:51:50.219846 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2628 11:51:50.226750 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2629 11:51:50.230220 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2630 11:51:50.233179 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2631 11:51:50.236600 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2632 11:51:50.240411 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2633 11:51:50.243825 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2634 11:51:50.250256 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2635 11:51:50.253365 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
2636 11:51:50.257177 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2637 11:51:50.260696 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2638 11:51:50.263548 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2639 11:51:50.269996 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2640 11:51:50.270159 ==
2641 11:51:50.273508 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 11:51:50.277322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 11:51:50.277444 ==
2644 11:51:50.277516 DQS Delay:
2645 11:51:50.280386 DQS0 = 0, DQS1 = 0
2646 11:51:50.280476 DQM Delay:
2647 11:51:50.283615 DQM0 = 113, DQM1 = 102
2648 11:51:50.283708 DQ Delay:
2649 11:51:50.287177 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2650 11:51:50.290469 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2651 11:51:50.293615 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =99
2652 11:51:50.296692 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2653 11:51:50.296806
2654 11:51:50.296876
2655 11:51:50.296936 ==
2656 11:51:50.300284 Dram Type= 6, Freq= 0, CH_0, rank 0
2657 11:51:50.306761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2658 11:51:50.306899 ==
2659 11:51:50.306970
2660 11:51:50.307031
2661 11:51:50.307089 TX Vref Scan disable
2662 11:51:50.310755 == TX Byte 0 ==
2663 11:51:50.314309 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2664 11:51:50.317282 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2665 11:51:50.320400 == TX Byte 1 ==
2666 11:51:50.324141 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2667 11:51:50.327511 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2668 11:51:50.331026 ==
2669 11:51:50.334223 Dram Type= 6, Freq= 0, CH_0, rank 0
2670 11:51:50.337014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2671 11:51:50.337115 ==
2672 11:51:50.348992 TX Vref=22, minBit 4, minWin=25, winSum=413
2673 11:51:50.352248 TX Vref=24, minBit 6, minWin=25, winSum=419
2674 11:51:50.355953 TX Vref=26, minBit 8, minWin=25, winSum=421
2675 11:51:50.358992 TX Vref=28, minBit 4, minWin=26, winSum=429
2676 11:51:50.362226 TX Vref=30, minBit 8, minWin=25, winSum=426
2677 11:51:50.366058 TX Vref=32, minBit 8, minWin=25, winSum=426
2678 11:51:50.372501 [TxChooseVref] Worse bit 4, Min win 26, Win sum 429, Final Vref 28
2679 11:51:50.372648
2680 11:51:50.375644 Final TX Range 1 Vref 28
2681 11:51:50.375741
2682 11:51:50.375808 ==
2683 11:51:50.378993 Dram Type= 6, Freq= 0, CH_0, rank 0
2684 11:51:50.382806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2685 11:51:50.382926 ==
2686 11:51:50.382996
2687 11:51:50.383056
2688 11:51:50.386036 TX Vref Scan disable
2689 11:51:50.389016 == TX Byte 0 ==
2690 11:51:50.392558 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2691 11:51:50.395693 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2692 11:51:50.399073 == TX Byte 1 ==
2693 11:51:50.402712 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2694 11:51:50.405690 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2695 11:51:50.405838
2696 11:51:50.409293 [DATLAT]
2697 11:51:50.409397 Freq=1200, CH0 RK0
2698 11:51:50.409465
2699 11:51:50.412553 DATLAT Default: 0xd
2700 11:51:50.412648 0, 0xFFFF, sum = 0
2701 11:51:50.415748 1, 0xFFFF, sum = 0
2702 11:51:50.415845 2, 0xFFFF, sum = 0
2703 11:51:50.419127 3, 0xFFFF, sum = 0
2704 11:51:50.419230 4, 0xFFFF, sum = 0
2705 11:51:50.422305 5, 0xFFFF, sum = 0
2706 11:51:50.422403 6, 0xFFFF, sum = 0
2707 11:51:50.425949 7, 0xFFFF, sum = 0
2708 11:51:50.426051 8, 0xFFFF, sum = 0
2709 11:51:50.429451 9, 0xFFFF, sum = 0
2710 11:51:50.432489 10, 0xFFFF, sum = 0
2711 11:51:50.432594 11, 0xFFFF, sum = 0
2712 11:51:50.436290 12, 0x0, sum = 1
2713 11:51:50.436393 13, 0x0, sum = 2
2714 11:51:50.436461 14, 0x0, sum = 3
2715 11:51:50.439262 15, 0x0, sum = 4
2716 11:51:50.439353 best_step = 13
2717 11:51:50.439420
2718 11:51:50.442416 ==
2719 11:51:50.442507 Dram Type= 6, Freq= 0, CH_0, rank 0
2720 11:51:50.449122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2721 11:51:50.449255 ==
2722 11:51:50.449326 RX Vref Scan: 1
2723 11:51:50.449388
2724 11:51:50.452469 Set Vref Range= 32 -> 127
2725 11:51:50.452570
2726 11:51:50.455721 RX Vref 32 -> 127, step: 1
2727 11:51:50.455819
2728 11:51:50.458978 RX Delay -37 -> 252, step: 4
2729 11:51:50.459078
2730 11:51:50.462234 Set Vref, RX VrefLevel [Byte0]: 32
2731 11:51:50.465619 [Byte1]: 32
2732 11:51:50.465728
2733 11:51:50.469142 Set Vref, RX VrefLevel [Byte0]: 33
2734 11:51:50.472375 [Byte1]: 33
2735 11:51:50.472485
2736 11:51:50.475726 Set Vref, RX VrefLevel [Byte0]: 34
2737 11:51:50.479082 [Byte1]: 34
2738 11:51:50.483698
2739 11:51:50.483826 Set Vref, RX VrefLevel [Byte0]: 35
2740 11:51:50.486856 [Byte1]: 35
2741 11:51:50.491504
2742 11:51:50.491664 Set Vref, RX VrefLevel [Byte0]: 36
2743 11:51:50.495165 [Byte1]: 36
2744 11:51:50.499708
2745 11:51:50.499833 Set Vref, RX VrefLevel [Byte0]: 37
2746 11:51:50.503203 [Byte1]: 37
2747 11:51:50.507354
2748 11:51:50.507478 Set Vref, RX VrefLevel [Byte0]: 38
2749 11:51:50.510956 [Byte1]: 38
2750 11:51:50.515507
2751 11:51:50.515667 Set Vref, RX VrefLevel [Byte0]: 39
2752 11:51:50.518655 [Byte1]: 39
2753 11:51:50.523414
2754 11:51:50.523546 Set Vref, RX VrefLevel [Byte0]: 40
2755 11:51:50.527062 [Byte1]: 40
2756 11:51:50.531451
2757 11:51:50.531571 Set Vref, RX VrefLevel [Byte0]: 41
2758 11:51:50.534954 [Byte1]: 41
2759 11:51:50.539408
2760 11:51:50.539562 Set Vref, RX VrefLevel [Byte0]: 42
2761 11:51:50.542658 [Byte1]: 42
2762 11:51:50.547443
2763 11:51:50.547591 Set Vref, RX VrefLevel [Byte0]: 43
2764 11:51:50.550851 [Byte1]: 43
2765 11:51:50.555847
2766 11:51:50.555975 Set Vref, RX VrefLevel [Byte0]: 44
2767 11:51:50.558638 [Byte1]: 44
2768 11:51:50.563329
2769 11:51:50.563448 Set Vref, RX VrefLevel [Byte0]: 45
2770 11:51:50.566636 [Byte1]: 45
2771 11:51:50.571554
2772 11:51:50.571690 Set Vref, RX VrefLevel [Byte0]: 46
2773 11:51:50.575067 [Byte1]: 46
2774 11:51:50.579267
2775 11:51:50.579390 Set Vref, RX VrefLevel [Byte0]: 47
2776 11:51:50.583109 [Byte1]: 47
2777 11:51:50.587721
2778 11:51:50.587846 Set Vref, RX VrefLevel [Byte0]: 48
2779 11:51:50.590892 [Byte1]: 48
2780 11:51:50.595418
2781 11:51:50.595551 Set Vref, RX VrefLevel [Byte0]: 49
2782 11:51:50.598860 [Byte1]: 49
2783 11:51:50.603698
2784 11:51:50.603826 Set Vref, RX VrefLevel [Byte0]: 50
2785 11:51:50.607324 [Byte1]: 50
2786 11:51:50.611405
2787 11:51:50.611527 Set Vref, RX VrefLevel [Byte0]: 51
2788 11:51:50.614924 [Byte1]: 51
2789 11:51:50.619666
2790 11:51:50.619796 Set Vref, RX VrefLevel [Byte0]: 52
2791 11:51:50.622730 [Byte1]: 52
2792 11:51:50.627547
2793 11:51:50.627676 Set Vref, RX VrefLevel [Byte0]: 53
2794 11:51:50.630759 [Byte1]: 53
2795 11:51:50.635677
2796 11:51:50.635814 Set Vref, RX VrefLevel [Byte0]: 54
2797 11:51:50.638834 [Byte1]: 54
2798 11:51:50.643347
2799 11:51:50.643473 Set Vref, RX VrefLevel [Byte0]: 55
2800 11:51:50.646574 [Byte1]: 55
2801 11:51:50.651436
2802 11:51:50.651560 Set Vref, RX VrefLevel [Byte0]: 56
2803 11:51:50.654564 [Byte1]: 56
2804 11:51:50.659745
2805 11:51:50.659872 Set Vref, RX VrefLevel [Byte0]: 57
2806 11:51:50.662882 [Byte1]: 57
2807 11:51:50.667509
2808 11:51:50.667639 Set Vref, RX VrefLevel [Byte0]: 58
2809 11:51:50.670697 [Byte1]: 58
2810 11:51:50.675455
2811 11:51:50.675580 Set Vref, RX VrefLevel [Byte0]: 59
2812 11:51:50.678857 [Byte1]: 59
2813 11:51:50.683684
2814 11:51:50.683814 Set Vref, RX VrefLevel [Byte0]: 60
2815 11:51:50.686710 [Byte1]: 60
2816 11:51:50.691483
2817 11:51:50.691601 Set Vref, RX VrefLevel [Byte0]: 61
2818 11:51:50.694575 [Byte1]: 61
2819 11:51:50.699530
2820 11:51:50.699653 Set Vref, RX VrefLevel [Byte0]: 62
2821 11:51:50.703130 [Byte1]: 62
2822 11:51:50.707454
2823 11:51:50.707572 Set Vref, RX VrefLevel [Byte0]: 63
2824 11:51:50.710996 [Byte1]: 63
2825 11:51:50.715491
2826 11:51:50.715616 Set Vref, RX VrefLevel [Byte0]: 64
2827 11:51:50.718852 [Byte1]: 64
2828 11:51:50.723398
2829 11:51:50.723559 Set Vref, RX VrefLevel [Byte0]: 65
2830 11:51:50.726843 [Byte1]: 65
2831 11:51:50.731349
2832 11:51:50.731477 Set Vref, RX VrefLevel [Byte0]: 66
2833 11:51:50.734765 [Byte1]: 66
2834 11:51:50.739436
2835 11:51:50.739570 Set Vref, RX VrefLevel [Byte0]: 67
2836 11:51:50.742565 [Byte1]: 67
2837 11:51:50.747742
2838 11:51:50.747873 Set Vref, RX VrefLevel [Byte0]: 68
2839 11:51:50.750830 [Byte1]: 68
2840 11:51:50.755548
2841 11:51:50.755674 Set Vref, RX VrefLevel [Byte0]: 69
2842 11:51:50.758766 [Byte1]: 69
2843 11:51:50.763374
2844 11:51:50.763499 Set Vref, RX VrefLevel [Byte0]: 70
2845 11:51:50.766915 [Byte1]: 70
2846 11:51:50.771606
2847 11:51:50.771743 Set Vref, RX VrefLevel [Byte0]: 71
2848 11:51:50.774941 [Byte1]: 71
2849 11:51:50.779633
2850 11:51:50.779764 Set Vref, RX VrefLevel [Byte0]: 72
2851 11:51:50.782666 [Byte1]: 72
2852 11:51:50.787531
2853 11:51:50.787662 Set Vref, RX VrefLevel [Byte0]: 73
2854 11:51:50.790860 [Byte1]: 73
2855 11:51:50.795546
2856 11:51:50.795682 Final RX Vref Byte 0 = 61 to rank0
2857 11:51:50.798973 Final RX Vref Byte 1 = 49 to rank0
2858 11:51:50.802145 Final RX Vref Byte 0 = 61 to rank1
2859 11:51:50.805752 Final RX Vref Byte 1 = 49 to rank1==
2860 11:51:50.808776 Dram Type= 6, Freq= 0, CH_0, rank 0
2861 11:51:50.812432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2862 11:51:50.815995 ==
2863 11:51:50.816126 DQS Delay:
2864 11:51:50.816225 DQS0 = 0, DQS1 = 0
2865 11:51:50.819091 DQM Delay:
2866 11:51:50.819207 DQM0 = 112, DQM1 = 100
2867 11:51:50.822127 DQ Delay:
2868 11:51:50.825510 DQ0 =110, DQ1 =112, DQ2 =112, DQ3 =108
2869 11:51:50.829455 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2870 11:51:50.832438 DQ8 =90, DQ9 =84, DQ10 =100, DQ11 =94
2871 11:51:50.835617 DQ12 =106, DQ13 =106, DQ14 =114, DQ15 =110
2872 11:51:50.835732
2873 11:51:50.835818
2874 11:51:50.842006 [DQSOSCAuto] RK0, (LSB)MR18= 0xfffe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 410 ps
2875 11:51:50.845556 CH0 RK0: MR19=303, MR18=FFFE
2876 11:51:50.851922 CH0_RK0: MR19=0x303, MR18=0xFFFE, DQSOSC=410, MR23=63, INC=39, DEC=26
2877 11:51:50.852067
2878 11:51:50.855602 ----->DramcWriteLeveling(PI) begin...
2879 11:51:50.855712 ==
2880 11:51:50.858847 Dram Type= 6, Freq= 0, CH_0, rank 1
2881 11:51:50.861973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2882 11:51:50.862081 ==
2883 11:51:50.865618 Write leveling (Byte 0): 31 => 31
2884 11:51:50.868587 Write leveling (Byte 1): 31 => 31
2885 11:51:50.872083 DramcWriteLeveling(PI) end<-----
2886 11:51:50.872216
2887 11:51:50.872286 ==
2888 11:51:50.875463 Dram Type= 6, Freq= 0, CH_0, rank 1
2889 11:51:50.882215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2890 11:51:50.882354 ==
2891 11:51:50.882444 [Gating] SW mode calibration
2892 11:51:50.892131 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2893 11:51:50.895299 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2894 11:51:50.898931 0 15 0 | B1->B0 | 2727 3434 | 1 0 | (1 1) (0 0)
2895 11:51:50.905522 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 11:51:50.909221 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 11:51:50.912481 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 11:51:50.918812 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2899 11:51:50.922296 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2900 11:51:50.925841 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2901 11:51:50.932510 0 15 28 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
2902 11:51:50.935697 1 0 0 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
2903 11:51:50.939240 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 11:51:50.945464 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 11:51:50.948817 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2906 11:51:50.952164 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2907 11:51:50.958830 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2908 11:51:50.962208 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2909 11:51:50.965794 1 0 28 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
2910 11:51:50.969049 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2911 11:51:50.975606 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 11:51:50.979025 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 11:51:50.982150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 11:51:50.988793 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2915 11:51:50.992674 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2916 11:51:50.995870 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 11:51:51.002703 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2918 11:51:51.006037 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2919 11:51:51.009293 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 11:51:51.015683 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 11:51:51.018942 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 11:51:51.022452 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 11:51:51.029087 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 11:51:51.032210 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 11:51:51.035940 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:51:51.042487 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:51:51.045984 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:51:51.049323 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:51:51.052314 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:51:51.059105 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:51:51.062337 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:51:51.065984 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:51:51.072589 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2934 11:51:51.075918 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2935 11:51:51.078936 Total UI for P1: 0, mck2ui 16
2936 11:51:51.082221 best dqsien dly found for B0: ( 1, 3, 28)
2937 11:51:51.085521 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 11:51:51.089438 Total UI for P1: 0, mck2ui 16
2939 11:51:51.092320 best dqsien dly found for B1: ( 1, 4, 0)
2940 11:51:51.095694 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2941 11:51:51.099319 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2942 11:51:51.099441
2943 11:51:51.105720 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2944 11:51:51.109296 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2945 11:51:51.109423 [Gating] SW calibration Done
2946 11:51:51.112467 ==
2947 11:51:51.112564 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 11:51:51.119094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 11:51:51.119226 ==
2950 11:51:51.119322 RX Vref Scan: 0
2951 11:51:51.119410
2952 11:51:51.122255 RX Vref 0 -> 0, step: 1
2953 11:51:51.122354
2954 11:51:51.125682 RX Delay -40 -> 252, step: 8
2955 11:51:51.128959 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2956 11:51:51.132376 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
2957 11:51:51.135807 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2958 11:51:51.142711 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2959 11:51:51.145811 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2960 11:51:51.149031 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2961 11:51:51.152420 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2962 11:51:51.155687 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2963 11:51:51.159111 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2964 11:51:51.165689 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2965 11:51:51.169007 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2966 11:51:51.172427 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2967 11:51:51.175942 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2968 11:51:51.179478 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2969 11:51:51.185957 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2970 11:51:51.189057 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2971 11:51:51.189192 ==
2972 11:51:51.192776 Dram Type= 6, Freq= 0, CH_0, rank 1
2973 11:51:51.195753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2974 11:51:51.195871 ==
2975 11:51:51.199441 DQS Delay:
2976 11:51:51.199547 DQS0 = 0, DQS1 = 0
2977 11:51:51.199639 DQM Delay:
2978 11:51:51.202842 DQM0 = 111, DQM1 = 101
2979 11:51:51.202946 DQ Delay:
2980 11:51:51.206173 DQ0 =111, DQ1 =107, DQ2 =111, DQ3 =107
2981 11:51:51.209420 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2982 11:51:51.212518 DQ8 =91, DQ9 =83, DQ10 =103, DQ11 =95
2983 11:51:51.215820 DQ12 =107, DQ13 =107, DQ14 =111, DQ15 =111
2984 11:51:51.219713
2985 11:51:51.219825
2986 11:51:51.219925 ==
2987 11:51:51.222821 Dram Type= 6, Freq= 0, CH_0, rank 1
2988 11:51:51.226042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2989 11:51:51.226141 ==
2990 11:51:51.226230
2991 11:51:51.226317
2992 11:51:51.229751 TX Vref Scan disable
2993 11:51:51.229843 == TX Byte 0 ==
2994 11:51:51.235867 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2995 11:51:51.239325 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2996 11:51:51.239443 == TX Byte 1 ==
2997 11:51:51.243039 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2998 11:51:51.249500 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2999 11:51:51.249643 ==
3000 11:51:51.252571 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 11:51:51.256436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 11:51:51.256559 ==
3003 11:51:51.268166 TX Vref=22, minBit 0, minWin=26, winSum=427
3004 11:51:51.271340 TX Vref=24, minBit 5, minWin=26, winSum=433
3005 11:51:51.274701 TX Vref=26, minBit 1, minWin=26, winSum=437
3006 11:51:51.278229 TX Vref=28, minBit 1, minWin=27, winSum=444
3007 11:51:51.281951 TX Vref=30, minBit 1, minWin=27, winSum=445
3008 11:51:51.284806 TX Vref=32, minBit 13, minWin=26, winSum=441
3009 11:51:51.291859 [TxChooseVref] Worse bit 1, Min win 27, Win sum 445, Final Vref 30
3010 11:51:51.292004
3011 11:51:51.294736 Final TX Range 1 Vref 30
3012 11:51:51.294848
3013 11:51:51.294916 ==
3014 11:51:51.298032 Dram Type= 6, Freq= 0, CH_0, rank 1
3015 11:51:51.301640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3016 11:51:51.301754 ==
3017 11:51:51.301823
3018 11:51:51.305033
3019 11:51:51.305129 TX Vref Scan disable
3020 11:51:51.308532 == TX Byte 0 ==
3021 11:51:51.311881 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3022 11:51:51.315176 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3023 11:51:51.318179 == TX Byte 1 ==
3024 11:51:51.321556 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3025 11:51:51.325360 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3026 11:51:51.325478
3027 11:51:51.328351 [DATLAT]
3028 11:51:51.328444 Freq=1200, CH0 RK1
3029 11:51:51.328537
3030 11:51:51.331345 DATLAT Default: 0xd
3031 11:51:51.331427 0, 0xFFFF, sum = 0
3032 11:51:51.334758 1, 0xFFFF, sum = 0
3033 11:51:51.334857 2, 0xFFFF, sum = 0
3034 11:51:51.338199 3, 0xFFFF, sum = 0
3035 11:51:51.338291 4, 0xFFFF, sum = 0
3036 11:51:51.341692 5, 0xFFFF, sum = 0
3037 11:51:51.341789 6, 0xFFFF, sum = 0
3038 11:51:51.344763 7, 0xFFFF, sum = 0
3039 11:51:51.344854 8, 0xFFFF, sum = 0
3040 11:51:51.347991 9, 0xFFFF, sum = 0
3041 11:51:51.351599 10, 0xFFFF, sum = 0
3042 11:51:51.351709 11, 0xFFFF, sum = 0
3043 11:51:51.354850 12, 0x0, sum = 1
3044 11:51:51.354956 13, 0x0, sum = 2
3045 11:51:51.355063 14, 0x0, sum = 3
3046 11:51:51.358275 15, 0x0, sum = 4
3047 11:51:51.358373 best_step = 13
3048 11:51:51.358438
3049 11:51:51.361504 ==
3050 11:51:51.361593 Dram Type= 6, Freq= 0, CH_0, rank 1
3051 11:51:51.368601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3052 11:51:51.368742 ==
3053 11:51:51.368811 RX Vref Scan: 0
3054 11:51:51.368872
3055 11:51:51.371395 RX Vref 0 -> 0, step: 1
3056 11:51:51.371499
3057 11:51:51.374861 RX Delay -37 -> 252, step: 4
3058 11:51:51.378145 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3059 11:51:51.381461 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3060 11:51:51.388735 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3061 11:51:51.391880 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3062 11:51:51.394736 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3063 11:51:51.398412 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3064 11:51:51.401499 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3065 11:51:51.408028 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3066 11:51:51.411681 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3067 11:51:51.415088 iDelay=195, Bit 9, Center 82 (11 ~ 154) 144
3068 11:51:51.418310 iDelay=195, Bit 10, Center 102 (31 ~ 174) 144
3069 11:51:51.421516 iDelay=195, Bit 11, Center 92 (23 ~ 162) 140
3070 11:51:51.428197 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3071 11:51:51.431823 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3072 11:51:51.434855 iDelay=195, Bit 14, Center 112 (47 ~ 178) 132
3073 11:51:51.438086 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3074 11:51:51.438191 ==
3075 11:51:51.441619 Dram Type= 6, Freq= 0, CH_0, rank 1
3076 11:51:51.444849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3077 11:51:51.448744 ==
3078 11:51:51.448860 DQS Delay:
3079 11:51:51.448937 DQS0 = 0, DQS1 = 0
3080 11:51:51.451829 DQM Delay:
3081 11:51:51.451911 DQM0 = 111, DQM1 = 100
3082 11:51:51.454796 DQ Delay:
3083 11:51:51.458620 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3084 11:51:51.461530 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3085 11:51:51.465054 DQ8 =90, DQ9 =82, DQ10 =102, DQ11 =92
3086 11:51:51.468418 DQ12 =108, DQ13 =108, DQ14 =112, DQ15 =110
3087 11:51:51.468522
3088 11:51:51.468588
3089 11:51:51.475374 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fb, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 402 ps
3090 11:51:51.479119 CH0 RK1: MR19=403, MR18=14FB
3091 11:51:51.485111 CH0_RK1: MR19=0x403, MR18=0x14FB, DQSOSC=402, MR23=63, INC=40, DEC=27
3092 11:51:51.488423 [RxdqsGatingPostProcess] freq 1200
3093 11:51:51.495238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3094 11:51:51.495385 best DQS0 dly(2T, 0.5T) = (0, 12)
3095 11:51:51.498247 best DQS1 dly(2T, 0.5T) = (0, 12)
3096 11:51:51.501812 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3097 11:51:51.504851 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3098 11:51:51.508597 best DQS0 dly(2T, 0.5T) = (0, 11)
3099 11:51:51.511625 best DQS1 dly(2T, 0.5T) = (0, 12)
3100 11:51:51.515304 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3101 11:51:51.518213 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3102 11:51:51.521449 Pre-setting of DQS Precalculation
3103 11:51:51.525078 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3104 11:51:51.528426 ==
3105 11:51:51.532084 Dram Type= 6, Freq= 0, CH_1, rank 0
3106 11:51:51.535393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3107 11:51:51.535513 ==
3108 11:51:51.538332 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3109 11:51:51.545127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3110 11:51:51.553843 [CA 0] Center 37 (7~67) winsize 61
3111 11:51:51.557637 [CA 1] Center 37 (7~68) winsize 62
3112 11:51:51.560725 [CA 2] Center 34 (5~64) winsize 60
3113 11:51:51.564000 [CA 3] Center 33 (3~64) winsize 62
3114 11:51:51.567276 [CA 4] Center 34 (4~64) winsize 61
3115 11:51:51.570696 [CA 5] Center 33 (3~63) winsize 61
3116 11:51:51.570791
3117 11:51:51.573777 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3118 11:51:51.573868
3119 11:51:51.577453 [CATrainingPosCal] consider 1 rank data
3120 11:51:51.580579 u2DelayCellTimex100 = 270/100 ps
3121 11:51:51.584241 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3122 11:51:51.587464 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3123 11:51:51.593616 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3124 11:51:51.597165 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3125 11:51:51.600221 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3126 11:51:51.603691 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3127 11:51:51.603790
3128 11:51:51.606948 CA PerBit enable=1, Macro0, CA PI delay=33
3129 11:51:51.607064
3130 11:51:51.610350 [CBTSetCACLKResult] CA Dly = 33
3131 11:51:51.610439 CS Dly: 5 (0~36)
3132 11:51:51.613977 ==
3133 11:51:51.614070 Dram Type= 6, Freq= 0, CH_1, rank 1
3134 11:51:51.620579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 11:51:51.620693 ==
3136 11:51:51.623694 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3137 11:51:51.630322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3138 11:51:51.639589 [CA 0] Center 37 (7~67) winsize 61
3139 11:51:51.642858 [CA 1] Center 37 (7~68) winsize 62
3140 11:51:51.646728 [CA 2] Center 34 (4~65) winsize 62
3141 11:51:51.649738 [CA 3] Center 33 (3~64) winsize 62
3142 11:51:51.652958 [CA 4] Center 34 (4~65) winsize 62
3143 11:51:51.656570 [CA 5] Center 32 (2~63) winsize 62
3144 11:51:51.656664
3145 11:51:51.659586 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3146 11:51:51.659671
3147 11:51:51.662840 [CATrainingPosCal] consider 2 rank data
3148 11:51:51.666191 u2DelayCellTimex100 = 270/100 ps
3149 11:51:51.669748 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3150 11:51:51.673331 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3151 11:51:51.679634 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3152 11:51:51.683337 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3153 11:51:51.686231 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3154 11:51:51.689763 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3155 11:51:51.689860
3156 11:51:51.693283 CA PerBit enable=1, Macro0, CA PI delay=33
3157 11:51:51.693426
3158 11:51:51.696116 [CBTSetCACLKResult] CA Dly = 33
3159 11:51:51.696240 CS Dly: 6 (0~39)
3160 11:51:51.696354
3161 11:51:51.699706 ----->DramcWriteLeveling(PI) begin...
3162 11:51:51.699795 ==
3163 11:51:51.702836 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 11:51:51.709671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 11:51:51.709790 ==
3166 11:51:51.713397 Write leveling (Byte 0): 26 => 26
3167 11:51:51.716644 Write leveling (Byte 1): 28 => 28
3168 11:51:51.716748 DramcWriteLeveling(PI) end<-----
3169 11:51:51.719721
3170 11:51:51.719808 ==
3171 11:51:51.723357 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:51:51.726489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:51:51.726603 ==
3174 11:51:51.729709 [Gating] SW mode calibration
3175 11:51:51.736694 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3176 11:51:51.739711 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3177 11:51:51.746626 0 15 0 | B1->B0 | 2a2a 2424 | 1 1 | (1 1) (0 0)
3178 11:51:51.749966 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 11:51:51.753096 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 11:51:51.759781 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 11:51:51.763112 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3182 11:51:51.766892 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3183 11:51:51.773076 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3184 11:51:51.776931 0 15 28 | B1->B0 | 2929 3232 | 0 1 | (0 0) (1 0)
3185 11:51:51.779863 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3186 11:51:51.786703 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 11:51:51.789717 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 11:51:51.793190 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 11:51:51.796630 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3190 11:51:51.803250 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3191 11:51:51.806526 1 0 24 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)
3192 11:51:51.809965 1 0 28 | B1->B0 | 4343 3c3b | 0 1 | (0 0) (0 0)
3193 11:51:51.816722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 11:51:51.820118 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 11:51:51.823468 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 11:51:51.829841 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3197 11:51:51.833562 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 11:51:51.836709 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 11:51:51.843135 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 11:51:51.846351 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3201 11:51:51.849736 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 11:51:51.856501 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 11:51:51.859912 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 11:51:51.863318 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 11:51:51.870098 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 11:51:51.873186 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 11:51:51.876976 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:51:51.883136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:51:51.886345 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:51:51.889850 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:51:51.893057 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:51:51.899818 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:51:51.903311 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:51:51.906467 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:51:51.913121 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:51:51.916673 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3217 11:51:51.920172 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3218 11:51:51.923450 Total UI for P1: 0, mck2ui 16
3219 11:51:51.926968 best dqsien dly found for B1: ( 1, 3, 28)
3220 11:51:51.933559 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3221 11:51:51.933709 Total UI for P1: 0, mck2ui 16
3222 11:51:51.939919 best dqsien dly found for B0: ( 1, 3, 30)
3223 11:51:51.943593 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3224 11:51:51.946475 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3225 11:51:51.946557
3226 11:51:51.949869 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3227 11:51:51.953449 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3228 11:51:51.956743 [Gating] SW calibration Done
3229 11:51:51.956842 ==
3230 11:51:51.960157 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 11:51:51.963641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 11:51:51.963733 ==
3233 11:51:51.966872 RX Vref Scan: 0
3234 11:51:51.966959
3235 11:51:51.967025 RX Vref 0 -> 0, step: 1
3236 11:51:51.967085
3237 11:51:51.969845 RX Delay -40 -> 252, step: 8
3238 11:51:51.973359 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3239 11:51:51.980185 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3240 11:51:51.983685 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3241 11:51:51.986730 iDelay=200, Bit 3, Center 111 (32 ~ 191) 160
3242 11:51:51.990080 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3243 11:51:51.993372 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3244 11:51:51.996653 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3245 11:51:52.003397 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3246 11:51:52.006933 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3247 11:51:52.010001 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3248 11:51:52.013273 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3249 11:51:52.016752 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3250 11:51:52.023437 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3251 11:51:52.026608 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3252 11:51:52.029855 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3253 11:51:52.033051 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3254 11:51:52.033150 ==
3255 11:51:52.036687 Dram Type= 6, Freq= 0, CH_1, rank 0
3256 11:51:52.043079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3257 11:51:52.043194 ==
3258 11:51:52.043266 DQS Delay:
3259 11:51:52.046518 DQS0 = 0, DQS1 = 0
3260 11:51:52.046606 DQM Delay:
3261 11:51:52.046673 DQM0 = 113, DQM1 = 105
3262 11:51:52.049923 DQ Delay:
3263 11:51:52.053055 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3264 11:51:52.056520 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3265 11:51:52.059627 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =103
3266 11:51:52.063047 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3267 11:51:52.063146
3268 11:51:52.063213
3269 11:51:52.063274 ==
3270 11:51:52.066860 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 11:51:52.069874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 11:51:52.073246 ==
3273 11:51:52.073336
3274 11:51:52.073403
3275 11:51:52.073463 TX Vref Scan disable
3276 11:51:52.076495 == TX Byte 0 ==
3277 11:51:52.079729 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3278 11:51:52.083203 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3279 11:51:52.086578 == TX Byte 1 ==
3280 11:51:52.089948 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3281 11:51:52.093138 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3282 11:51:52.093272 ==
3283 11:51:52.096373 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 11:51:52.103071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 11:51:52.103225 ==
3286 11:51:52.113765 TX Vref=22, minBit 11, minWin=24, winSum=407
3287 11:51:52.117380 TX Vref=24, minBit 10, minWin=24, winSum=412
3288 11:51:52.120533 TX Vref=26, minBit 10, minWin=24, winSum=417
3289 11:51:52.123982 TX Vref=28, minBit 9, minWin=24, winSum=423
3290 11:51:52.127121 TX Vref=30, minBit 9, minWin=25, winSum=424
3291 11:51:52.134085 TX Vref=32, minBit 8, minWin=25, winSum=421
3292 11:51:52.136984 [TxChooseVref] Worse bit 9, Min win 25, Win sum 424, Final Vref 30
3293 11:51:52.137101
3294 11:51:52.140523 Final TX Range 1 Vref 30
3295 11:51:52.140608
3296 11:51:52.140671 ==
3297 11:51:52.143647 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 11:51:52.147045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 11:51:52.147170 ==
3300 11:51:52.150579
3301 11:51:52.150663
3302 11:51:52.150763 TX Vref Scan disable
3303 11:51:52.154061 == TX Byte 0 ==
3304 11:51:52.157344 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3305 11:51:52.160473 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3306 11:51:52.163736 == TX Byte 1 ==
3307 11:51:52.167332 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3308 11:51:52.173744 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3309 11:51:52.173866
3310 11:51:52.173950 [DATLAT]
3311 11:51:52.174025 Freq=1200, CH1 RK0
3312 11:51:52.174084
3313 11:51:52.177022 DATLAT Default: 0xd
3314 11:51:52.177122 0, 0xFFFF, sum = 0
3315 11:51:52.180625 1, 0xFFFF, sum = 0
3316 11:51:52.180704 2, 0xFFFF, sum = 0
3317 11:51:52.183750 3, 0xFFFF, sum = 0
3318 11:51:52.186990 4, 0xFFFF, sum = 0
3319 11:51:52.187110 5, 0xFFFF, sum = 0
3320 11:51:52.190644 6, 0xFFFF, sum = 0
3321 11:51:52.190732 7, 0xFFFF, sum = 0
3322 11:51:52.193790 8, 0xFFFF, sum = 0
3323 11:51:52.193880 9, 0xFFFF, sum = 0
3324 11:51:52.197192 10, 0xFFFF, sum = 0
3325 11:51:52.197287 11, 0xFFFF, sum = 0
3326 11:51:52.200522 12, 0x0, sum = 1
3327 11:51:52.200612 13, 0x0, sum = 2
3328 11:51:52.203510 14, 0x0, sum = 3
3329 11:51:52.203595 15, 0x0, sum = 4
3330 11:51:52.203692 best_step = 13
3331 11:51:52.207170
3332 11:51:52.207258 ==
3333 11:51:52.210495 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 11:51:52.213564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 11:51:52.213658 ==
3336 11:51:52.213724 RX Vref Scan: 1
3337 11:51:52.213785
3338 11:51:52.217183 Set Vref Range= 32 -> 127
3339 11:51:52.217271
3340 11:51:52.220402 RX Vref 32 -> 127, step: 1
3341 11:51:52.220489
3342 11:51:52.223647 RX Delay -21 -> 252, step: 4
3343 11:51:52.223735
3344 11:51:52.227036 Set Vref, RX VrefLevel [Byte0]: 32
3345 11:51:52.230700 [Byte1]: 32
3346 11:51:52.230824
3347 11:51:52.233624 Set Vref, RX VrefLevel [Byte0]: 33
3348 11:51:52.236968 [Byte1]: 33
3349 11:51:52.240075
3350 11:51:52.240195 Set Vref, RX VrefLevel [Byte0]: 34
3351 11:51:52.243730 [Byte1]: 34
3352 11:51:52.248354
3353 11:51:52.248468 Set Vref, RX VrefLevel [Byte0]: 35
3354 11:51:52.251215 [Byte1]: 35
3355 11:51:52.256373
3356 11:51:52.256484 Set Vref, RX VrefLevel [Byte0]: 36
3357 11:51:52.259507 [Byte1]: 36
3358 11:51:52.264103
3359 11:51:52.264271 Set Vref, RX VrefLevel [Byte0]: 37
3360 11:51:52.267434 [Byte1]: 37
3361 11:51:52.272020
3362 11:51:52.272131 Set Vref, RX VrefLevel [Byte0]: 38
3363 11:51:52.275309 [Byte1]: 38
3364 11:51:52.279685
3365 11:51:52.279791 Set Vref, RX VrefLevel [Byte0]: 39
3366 11:51:52.283633 [Byte1]: 39
3367 11:51:52.287866
3368 11:51:52.287973 Set Vref, RX VrefLevel [Byte0]: 40
3369 11:51:52.290981 [Byte1]: 40
3370 11:51:52.295605
3371 11:51:52.295717 Set Vref, RX VrefLevel [Byte0]: 41
3372 11:51:52.298875 [Byte1]: 41
3373 11:51:52.303837
3374 11:51:52.303960 Set Vref, RX VrefLevel [Byte0]: 42
3375 11:51:52.307070 [Byte1]: 42
3376 11:51:52.311928
3377 11:51:52.312044 Set Vref, RX VrefLevel [Byte0]: 43
3378 11:51:52.314840 [Byte1]: 43
3379 11:51:52.319686
3380 11:51:52.319795 Set Vref, RX VrefLevel [Byte0]: 44
3381 11:51:52.323026 [Byte1]: 44
3382 11:51:52.327195
3383 11:51:52.327344 Set Vref, RX VrefLevel [Byte0]: 45
3384 11:51:52.330647 [Byte1]: 45
3385 11:51:52.335236
3386 11:51:52.335348 Set Vref, RX VrefLevel [Byte0]: 46
3387 11:51:52.338521 [Byte1]: 46
3388 11:51:52.344011
3389 11:51:52.344130 Set Vref, RX VrefLevel [Byte0]: 47
3390 11:51:52.346318 [Byte1]: 47
3391 11:51:52.351328
3392 11:51:52.351447 Set Vref, RX VrefLevel [Byte0]: 48
3393 11:51:52.354426 [Byte1]: 48
3394 11:51:52.359198
3395 11:51:52.359309 Set Vref, RX VrefLevel [Byte0]: 49
3396 11:51:52.362131 [Byte1]: 49
3397 11:51:52.367206
3398 11:51:52.367316 Set Vref, RX VrefLevel [Byte0]: 50
3399 11:51:52.370410 [Byte1]: 50
3400 11:51:52.374878
3401 11:51:52.374990 Set Vref, RX VrefLevel [Byte0]: 51
3402 11:51:52.378305 [Byte1]: 51
3403 11:51:52.382909
3404 11:51:52.383019 Set Vref, RX VrefLevel [Byte0]: 52
3405 11:51:52.386068 [Byte1]: 52
3406 11:51:52.390807
3407 11:51:52.390914 Set Vref, RX VrefLevel [Byte0]: 53
3408 11:51:52.393988 [Byte1]: 53
3409 11:51:52.398949
3410 11:51:52.399062 Set Vref, RX VrefLevel [Byte0]: 54
3411 11:51:52.401886 [Byte1]: 54
3412 11:51:52.406885
3413 11:51:52.406999 Set Vref, RX VrefLevel [Byte0]: 55
3414 11:51:52.409688 [Byte1]: 55
3415 11:51:52.414457
3416 11:51:52.414586 Set Vref, RX VrefLevel [Byte0]: 56
3417 11:51:52.417814 [Byte1]: 56
3418 11:51:52.422777
3419 11:51:52.422896 Set Vref, RX VrefLevel [Byte0]: 57
3420 11:51:52.425663 [Byte1]: 57
3421 11:51:52.430227
3422 11:51:52.430343 Set Vref, RX VrefLevel [Byte0]: 58
3423 11:51:52.433626 [Byte1]: 58
3424 11:51:52.438264
3425 11:51:52.438384 Set Vref, RX VrefLevel [Byte0]: 59
3426 11:51:52.441664 [Byte1]: 59
3427 11:51:52.446227
3428 11:51:52.446356 Set Vref, RX VrefLevel [Byte0]: 60
3429 11:51:52.452736 [Byte1]: 60
3430 11:51:52.452860
3431 11:51:52.455944 Set Vref, RX VrefLevel [Byte0]: 61
3432 11:51:52.459377 [Byte1]: 61
3433 11:51:52.459488
3434 11:51:52.462713 Set Vref, RX VrefLevel [Byte0]: 62
3435 11:51:52.465776 [Byte1]: 62
3436 11:51:52.470188
3437 11:51:52.470323 Set Vref, RX VrefLevel [Byte0]: 63
3438 11:51:52.473057 [Byte1]: 63
3439 11:51:52.477960
3440 11:51:52.478101 Set Vref, RX VrefLevel [Byte0]: 64
3441 11:51:52.481105 [Byte1]: 64
3442 11:51:52.485586
3443 11:51:52.485723 Set Vref, RX VrefLevel [Byte0]: 65
3444 11:51:52.489172 [Byte1]: 65
3445 11:51:52.493679
3446 11:51:52.493813 Set Vref, RX VrefLevel [Byte0]: 66
3447 11:51:52.497184 [Byte1]: 66
3448 11:51:52.501560
3449 11:51:52.501707 Set Vref, RX VrefLevel [Byte0]: 67
3450 11:51:52.505251 [Byte1]: 67
3451 11:51:52.509357
3452 11:51:52.509488 Set Vref, RX VrefLevel [Byte0]: 68
3453 11:51:52.512870 [Byte1]: 68
3454 11:51:52.517375
3455 11:51:52.517513 Set Vref, RX VrefLevel [Byte0]: 69
3456 11:51:52.521185 [Byte1]: 69
3457 11:51:52.525465
3458 11:51:52.525599 Final RX Vref Byte 0 = 54 to rank0
3459 11:51:52.528955 Final RX Vref Byte 1 = 55 to rank0
3460 11:51:52.532121 Final RX Vref Byte 0 = 54 to rank1
3461 11:51:52.535632 Final RX Vref Byte 1 = 55 to rank1==
3462 11:51:52.538689 Dram Type= 6, Freq= 0, CH_1, rank 0
3463 11:51:52.545257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3464 11:51:52.545405 ==
3465 11:51:52.545475 DQS Delay:
3466 11:51:52.545536 DQS0 = 0, DQS1 = 0
3467 11:51:52.548956 DQM Delay:
3468 11:51:52.549076 DQM0 = 112, DQM1 = 107
3469 11:51:52.551922 DQ Delay:
3470 11:51:52.555617 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =110
3471 11:51:52.558606 DQ4 =108, DQ5 =120, DQ6 =124, DQ7 =110
3472 11:51:52.562035 DQ8 =94, DQ9 =98, DQ10 =104, DQ11 =102
3473 11:51:52.565650 DQ12 =114, DQ13 =114, DQ14 =116, DQ15 =114
3474 11:51:52.565766
3475 11:51:52.565830
3476 11:51:52.572138 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 416 ps
3477 11:51:52.575657 CH1 RK0: MR19=303, MR18=F1F8
3478 11:51:52.581856 CH1_RK0: MR19=0x303, MR18=0xF1F8, DQSOSC=413, MR23=63, INC=38, DEC=25
3479 11:51:52.581976
3480 11:51:52.585721 ----->DramcWriteLeveling(PI) begin...
3481 11:51:52.585822 ==
3482 11:51:52.588771 Dram Type= 6, Freq= 0, CH_1, rank 1
3483 11:51:52.591923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 11:51:52.595121 ==
3485 11:51:52.595225 Write leveling (Byte 0): 25 => 25
3486 11:51:52.598639 Write leveling (Byte 1): 27 => 27
3487 11:51:52.602009 DramcWriteLeveling(PI) end<-----
3488 11:51:52.602108
3489 11:51:52.602175 ==
3490 11:51:52.605410 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 11:51:52.611991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 11:51:52.612120 ==
3493 11:51:52.612190 [Gating] SW mode calibration
3494 11:51:52.622376 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3495 11:51:52.625484 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3496 11:51:52.628991 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3497 11:51:52.635610 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3498 11:51:52.638730 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3499 11:51:52.642289 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3500 11:51:52.648664 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3501 11:51:52.652306 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3502 11:51:52.655240 0 15 24 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
3503 11:51:52.661921 0 15 28 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
3504 11:51:52.665380 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 11:51:52.668938 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3506 11:51:52.675467 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3507 11:51:52.678722 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3508 11:51:52.681835 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3509 11:51:52.688789 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3510 11:51:52.692031 1 0 24 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
3511 11:51:52.695272 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3512 11:51:52.702032 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 11:51:52.705292 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3514 11:51:52.708515 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3515 11:51:52.711923 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3516 11:51:52.718854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3517 11:51:52.722468 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3518 11:51:52.725610 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3519 11:51:52.731837 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3520 11:51:52.735542 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 11:51:52.738424 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 11:51:52.745306 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 11:51:52.748468 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 11:51:52.751984 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 11:51:52.758698 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 11:51:52.761779 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 11:51:52.765075 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 11:51:52.771774 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 11:51:52.775127 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 11:51:52.778182 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 11:51:52.785178 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:51:52.788479 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:51:52.791720 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3534 11:51:52.798068 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3535 11:51:52.801606 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 11:51:52.804754 Total UI for P1: 0, mck2ui 16
3537 11:51:52.808374 best dqsien dly found for B0: ( 1, 3, 22)
3538 11:51:52.811772 Total UI for P1: 0, mck2ui 16
3539 11:51:52.814665 best dqsien dly found for B1: ( 1, 3, 26)
3540 11:51:52.818272 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3541 11:51:52.821218 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3542 11:51:52.821319
3543 11:51:52.825015 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3544 11:51:52.827881 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3545 11:51:52.831660 [Gating] SW calibration Done
3546 11:51:52.831762 ==
3547 11:51:52.835005 Dram Type= 6, Freq= 0, CH_1, rank 1
3548 11:51:52.838314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3549 11:51:52.841730 ==
3550 11:51:52.841825 RX Vref Scan: 0
3551 11:51:52.841892
3552 11:51:52.844446 RX Vref 0 -> 0, step: 1
3553 11:51:52.844531
3554 11:51:52.847757 RX Delay -40 -> 252, step: 8
3555 11:51:52.851266 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3556 11:51:52.854830 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3557 11:51:52.857974 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3558 11:51:52.861170 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3559 11:51:52.868021 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3560 11:51:52.871275 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3561 11:51:52.875024 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3562 11:51:52.878147 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3563 11:51:52.881339 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3564 11:51:52.884896 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3565 11:51:52.890963 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3566 11:51:52.894629 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3567 11:51:52.898048 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3568 11:51:52.901081 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3569 11:51:52.904643 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3570 11:51:52.911285 iDelay=200, Bit 15, Center 115 (40 ~ 191) 152
3571 11:51:52.911405 ==
3572 11:51:52.914906 Dram Type= 6, Freq= 0, CH_1, rank 1
3573 11:51:52.918127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3574 11:51:52.918222 ==
3575 11:51:52.918325 DQS Delay:
3576 11:51:52.921401 DQS0 = 0, DQS1 = 0
3577 11:51:52.921486 DQM Delay:
3578 11:51:52.924582 DQM0 = 112, DQM1 = 109
3579 11:51:52.924667 DQ Delay:
3580 11:51:52.927663 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =111
3581 11:51:52.931277 DQ4 =111, DQ5 =119, DQ6 =119, DQ7 =111
3582 11:51:52.934545 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3583 11:51:52.937711 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =115
3584 11:51:52.937800
3585 11:51:52.937867
3586 11:51:52.941171 ==
3587 11:51:52.944653 Dram Type= 6, Freq= 0, CH_1, rank 1
3588 11:51:52.947812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3589 11:51:52.947917 ==
3590 11:51:52.947985
3591 11:51:52.948045
3592 11:51:52.950835 TX Vref Scan disable
3593 11:51:52.950921 == TX Byte 0 ==
3594 11:51:52.957464 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3595 11:51:52.961283 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3596 11:51:52.961410 == TX Byte 1 ==
3597 11:51:52.967816 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3598 11:51:52.970973 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3599 11:51:52.971061 ==
3600 11:51:52.973990 Dram Type= 6, Freq= 0, CH_1, rank 1
3601 11:51:52.977412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3602 11:51:52.977509 ==
3603 11:51:52.989639 TX Vref=22, minBit 11, minWin=25, winSum=423
3604 11:51:52.992988 TX Vref=24, minBit 1, minWin=26, winSum=424
3605 11:51:52.996582 TX Vref=26, minBit 8, minWin=26, winSum=430
3606 11:51:52.999984 TX Vref=28, minBit 1, minWin=26, winSum=432
3607 11:51:53.003147 TX Vref=30, minBit 9, minWin=26, winSum=434
3608 11:51:53.009729 TX Vref=32, minBit 1, minWin=26, winSum=427
3609 11:51:53.013125 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3610 11:51:53.013231
3611 11:51:53.016412 Final TX Range 1 Vref 30
3612 11:51:53.016498
3613 11:51:53.016561 ==
3614 11:51:53.019631 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:51:53.022939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:51:53.023053 ==
3617 11:51:53.026059
3618 11:51:53.026142
3619 11:51:53.026206 TX Vref Scan disable
3620 11:51:53.029749 == TX Byte 0 ==
3621 11:51:53.032878 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3622 11:51:53.039581 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3623 11:51:53.039705 == TX Byte 1 ==
3624 11:51:53.043009 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3625 11:51:53.049268 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3626 11:51:53.049405
3627 11:51:53.049486 [DATLAT]
3628 11:51:53.049547 Freq=1200, CH1 RK1
3629 11:51:53.049605
3630 11:51:53.052607 DATLAT Default: 0xd
3631 11:51:53.055896 0, 0xFFFF, sum = 0
3632 11:51:53.055997 1, 0xFFFF, sum = 0
3633 11:51:53.059142 2, 0xFFFF, sum = 0
3634 11:51:53.059234 3, 0xFFFF, sum = 0
3635 11:51:53.062734 4, 0xFFFF, sum = 0
3636 11:51:53.062821 5, 0xFFFF, sum = 0
3637 11:51:53.065842 6, 0xFFFF, sum = 0
3638 11:51:53.065935 7, 0xFFFF, sum = 0
3639 11:51:53.069118 8, 0xFFFF, sum = 0
3640 11:51:53.069208 9, 0xFFFF, sum = 0
3641 11:51:53.072687 10, 0xFFFF, sum = 0
3642 11:51:53.072777 11, 0xFFFF, sum = 0
3643 11:51:53.076003 12, 0x0, sum = 1
3644 11:51:53.076103 13, 0x0, sum = 2
3645 11:51:53.080036 14, 0x0, sum = 3
3646 11:51:53.080134 15, 0x0, sum = 4
3647 11:51:53.082695 best_step = 13
3648 11:51:53.082797
3649 11:51:53.082892 ==
3650 11:51:53.085959 Dram Type= 6, Freq= 0, CH_1, rank 1
3651 11:51:53.089215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3652 11:51:53.089312 ==
3653 11:51:53.089378 RX Vref Scan: 0
3654 11:51:53.089438
3655 11:51:53.092804 RX Vref 0 -> 0, step: 1
3656 11:51:53.092892
3657 11:51:53.095829 RX Delay -21 -> 252, step: 4
3658 11:51:53.099424 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3659 11:51:53.105911 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3660 11:51:53.109412 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3661 11:51:53.112460 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3662 11:51:53.115939 iDelay=195, Bit 4, Center 110 (39 ~ 182) 144
3663 11:51:53.119022 iDelay=195, Bit 5, Center 122 (51 ~ 194) 144
3664 11:51:53.125561 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3665 11:51:53.128926 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3666 11:51:53.132608 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3667 11:51:53.135825 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3668 11:51:53.139068 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3669 11:51:53.145745 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3670 11:51:53.149271 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3671 11:51:53.152412 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3672 11:51:53.155723 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3673 11:51:53.162212 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3674 11:51:53.162312 ==
3675 11:51:53.165576 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 11:51:53.169104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 11:51:53.169192 ==
3678 11:51:53.169258 DQS Delay:
3679 11:51:53.172158 DQS0 = 0, DQS1 = 0
3680 11:51:53.172286 DQM Delay:
3681 11:51:53.175809 DQM0 = 111, DQM1 = 110
3682 11:51:53.175895 DQ Delay:
3683 11:51:53.178852 DQ0 =114, DQ1 =108, DQ2 =100, DQ3 =108
3684 11:51:53.181955 DQ4 =110, DQ5 =122, DQ6 =122, DQ7 =110
3685 11:51:53.185561 DQ8 =96, DQ9 =102, DQ10 =110, DQ11 =104
3686 11:51:53.188442 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3687 11:51:53.188590
3688 11:51:53.188659
3689 11:51:53.198753 [DQSOSCAuto] RK1, (LSB)MR18= 0xf909, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3690 11:51:53.202236 CH1 RK1: MR19=304, MR18=F909
3691 11:51:53.205262 CH1_RK1: MR19=0x304, MR18=0xF909, DQSOSC=406, MR23=63, INC=39, DEC=26
3692 11:51:53.208575 [RxdqsGatingPostProcess] freq 1200
3693 11:51:53.215362 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3694 11:51:53.218401 best DQS0 dly(2T, 0.5T) = (0, 11)
3695 11:51:53.222080 best DQS1 dly(2T, 0.5T) = (0, 11)
3696 11:51:53.224853 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3697 11:51:53.228037 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3698 11:51:53.231688 best DQS0 dly(2T, 0.5T) = (0, 11)
3699 11:51:53.234796 best DQS1 dly(2T, 0.5T) = (0, 11)
3700 11:51:53.238135 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3701 11:51:53.241740 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3702 11:51:53.245019 Pre-setting of DQS Precalculation
3703 11:51:53.248326 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3704 11:51:53.254632 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3705 11:51:53.264456 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3706 11:51:53.264571
3707 11:51:53.264639
3708 11:51:53.268135 [Calibration Summary] 2400 Mbps
3709 11:51:53.268241 CH 0, Rank 0
3710 11:51:53.271205 SW Impedance : PASS
3711 11:51:53.271286 DUTY Scan : NO K
3712 11:51:53.274699 ZQ Calibration : PASS
3713 11:51:53.274781 Jitter Meter : NO K
3714 11:51:53.277726 CBT Training : PASS
3715 11:51:53.281578 Write leveling : PASS
3716 11:51:53.281669 RX DQS gating : PASS
3717 11:51:53.284722 RX DQ/DQS(RDDQC) : PASS
3718 11:51:53.288311 TX DQ/DQS : PASS
3719 11:51:53.288401 RX DATLAT : PASS
3720 11:51:53.291581 RX DQ/DQS(Engine): PASS
3721 11:51:53.294622 TX OE : NO K
3722 11:51:53.294706 All Pass.
3723 11:51:53.294771
3724 11:51:53.294830 CH 0, Rank 1
3725 11:51:53.297653 SW Impedance : PASS
3726 11:51:53.301572 DUTY Scan : NO K
3727 11:51:53.301666 ZQ Calibration : PASS
3728 11:51:53.304427 Jitter Meter : NO K
3729 11:51:53.307621 CBT Training : PASS
3730 11:51:53.307706 Write leveling : PASS
3731 11:51:53.310961 RX DQS gating : PASS
3732 11:51:53.314259 RX DQ/DQS(RDDQC) : PASS
3733 11:51:53.314344 TX DQ/DQS : PASS
3734 11:51:53.318000 RX DATLAT : PASS
3735 11:51:53.318101 RX DQ/DQS(Engine): PASS
3736 11:51:53.321417 TX OE : NO K
3737 11:51:53.321502 All Pass.
3738 11:51:53.321567
3739 11:51:53.324480 CH 1, Rank 0
3740 11:51:53.324590 SW Impedance : PASS
3741 11:51:53.327798 DUTY Scan : NO K
3742 11:51:53.331433 ZQ Calibration : PASS
3743 11:51:53.331518 Jitter Meter : NO K
3744 11:51:53.334288 CBT Training : PASS
3745 11:51:53.337721 Write leveling : PASS
3746 11:51:53.337805 RX DQS gating : PASS
3747 11:51:53.341350 RX DQ/DQS(RDDQC) : PASS
3748 11:51:53.344540 TX DQ/DQS : PASS
3749 11:51:53.344623 RX DATLAT : PASS
3750 11:51:53.348369 RX DQ/DQS(Engine): PASS
3751 11:51:53.351049 TX OE : NO K
3752 11:51:53.351133 All Pass.
3753 11:51:53.351198
3754 11:51:53.351258 CH 1, Rank 1
3755 11:51:53.354706 SW Impedance : PASS
3756 11:51:53.357663 DUTY Scan : NO K
3757 11:51:53.357749 ZQ Calibration : PASS
3758 11:51:53.361266 Jitter Meter : NO K
3759 11:51:53.364455 CBT Training : PASS
3760 11:51:53.364540 Write leveling : PASS
3761 11:51:53.367640 RX DQS gating : PASS
3762 11:51:53.367724 RX DQ/DQS(RDDQC) : PASS
3763 11:51:53.371305 TX DQ/DQS : PASS
3764 11:51:53.374395 RX DATLAT : PASS
3765 11:51:53.374482 RX DQ/DQS(Engine): PASS
3766 11:51:53.377688 TX OE : NO K
3767 11:51:53.377773 All Pass.
3768 11:51:53.377839
3769 11:51:53.381300 DramC Write-DBI off
3770 11:51:53.384213 PER_BANK_REFRESH: Hybrid Mode
3771 11:51:53.384313 TX_TRACKING: ON
3772 11:51:53.394042 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3773 11:51:53.397760 [FAST_K] Save calibration result to emmc
3774 11:51:53.400693 dramc_set_vcore_voltage set vcore to 650000
3775 11:51:53.404165 Read voltage for 600, 5
3776 11:51:53.404297 Vio18 = 0
3777 11:51:53.407608 Vcore = 650000
3778 11:51:53.407696 Vdram = 0
3779 11:51:53.407764 Vddq = 0
3780 11:51:53.407833 Vmddr = 0
3781 11:51:53.414309 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3782 11:51:53.417677 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3783 11:51:53.420653 MEM_TYPE=3, freq_sel=19
3784 11:51:53.424070 sv_algorithm_assistance_LP4_1600
3785 11:51:53.427348 ============ PULL DRAM RESETB DOWN ============
3786 11:51:53.434172 ========== PULL DRAM RESETB DOWN end =========
3787 11:51:53.437670 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3788 11:51:53.440557 ===================================
3789 11:51:53.443836 LPDDR4 DRAM CONFIGURATION
3790 11:51:53.447307 ===================================
3791 11:51:53.447400 EX_ROW_EN[0] = 0x0
3792 11:51:53.450682 EX_ROW_EN[1] = 0x0
3793 11:51:53.450767 LP4Y_EN = 0x0
3794 11:51:53.453713 WORK_FSP = 0x0
3795 11:51:53.453795 WL = 0x2
3796 11:51:53.457618 RL = 0x2
3797 11:51:53.457704 BL = 0x2
3798 11:51:53.460561 RPST = 0x0
3799 11:51:53.460671 RD_PRE = 0x0
3800 11:51:53.463928 WR_PRE = 0x1
3801 11:51:53.467206 WR_PST = 0x0
3802 11:51:53.467289 DBI_WR = 0x0
3803 11:51:53.470890 DBI_RD = 0x0
3804 11:51:53.470973 OTF = 0x1
3805 11:51:53.473834 ===================================
3806 11:51:53.477094 ===================================
3807 11:51:53.477181 ANA top config
3808 11:51:53.480321 ===================================
3809 11:51:53.483731 DLL_ASYNC_EN = 0
3810 11:51:53.487364 ALL_SLAVE_EN = 1
3811 11:51:53.490312 NEW_RANK_MODE = 1
3812 11:51:53.493839 DLL_IDLE_MODE = 1
3813 11:51:53.493923 LP45_APHY_COMB_EN = 1
3814 11:51:53.497011 TX_ODT_DIS = 1
3815 11:51:53.500458 NEW_8X_MODE = 1
3816 11:51:53.503790 ===================================
3817 11:51:53.507002 ===================================
3818 11:51:53.510487 data_rate = 1200
3819 11:51:53.513743 CKR = 1
3820 11:51:53.513829 DQ_P2S_RATIO = 8
3821 11:51:53.516833 ===================================
3822 11:51:53.520458 CA_P2S_RATIO = 8
3823 11:51:53.523368 DQ_CA_OPEN = 0
3824 11:51:53.526907 DQ_SEMI_OPEN = 0
3825 11:51:53.529967 CA_SEMI_OPEN = 0
3826 11:51:53.533696 CA_FULL_RATE = 0
3827 11:51:53.533785 DQ_CKDIV4_EN = 1
3828 11:51:53.536739 CA_CKDIV4_EN = 1
3829 11:51:53.540030 CA_PREDIV_EN = 0
3830 11:51:53.543215 PH8_DLY = 0
3831 11:51:53.546792 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3832 11:51:53.550070 DQ_AAMCK_DIV = 4
3833 11:51:53.550155 CA_AAMCK_DIV = 4
3834 11:51:53.553505 CA_ADMCK_DIV = 4
3835 11:51:53.556511 DQ_TRACK_CA_EN = 0
3836 11:51:53.560348 CA_PICK = 600
3837 11:51:53.563526 CA_MCKIO = 600
3838 11:51:53.566552 MCKIO_SEMI = 0
3839 11:51:53.570265 PLL_FREQ = 2288
3840 11:51:53.570349 DQ_UI_PI_RATIO = 32
3841 11:51:53.573194 CA_UI_PI_RATIO = 0
3842 11:51:53.576534 ===================================
3843 11:51:53.579910 ===================================
3844 11:51:53.583096 memory_type:LPDDR4
3845 11:51:53.586498 GP_NUM : 10
3846 11:51:53.586582 SRAM_EN : 1
3847 11:51:53.590130 MD32_EN : 0
3848 11:51:53.593200 ===================================
3849 11:51:53.596441 [ANA_INIT] >>>>>>>>>>>>>>
3850 11:51:53.596525 <<<<<< [CONFIGURE PHASE]: ANA_TX
3851 11:51:53.599965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3852 11:51:53.603358 ===================================
3853 11:51:53.606405 data_rate = 1200,PCW = 0X5800
3854 11:51:53.609831 ===================================
3855 11:51:53.613091 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3856 11:51:53.619980 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3857 11:51:53.626322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3858 11:51:53.629449 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3859 11:51:53.632727 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3860 11:51:53.636346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3861 11:51:53.639347 [ANA_INIT] flow start
3862 11:51:53.639432 [ANA_INIT] PLL >>>>>>>>
3863 11:51:53.642706 [ANA_INIT] PLL <<<<<<<<
3864 11:51:53.646124 [ANA_INIT] MIDPI >>>>>>>>
3865 11:51:53.649343 [ANA_INIT] MIDPI <<<<<<<<
3866 11:51:53.649428 [ANA_INIT] DLL >>>>>>>>
3867 11:51:53.652645 [ANA_INIT] flow end
3868 11:51:53.656066 ============ LP4 DIFF to SE enter ============
3869 11:51:53.659382 ============ LP4 DIFF to SE exit ============
3870 11:51:53.662702 [ANA_INIT] <<<<<<<<<<<<<
3871 11:51:53.665810 [Flow] Enable top DCM control >>>>>
3872 11:51:53.669112 [Flow] Enable top DCM control <<<<<
3873 11:51:53.672717 Enable DLL master slave shuffle
3874 11:51:53.679112 ==============================================================
3875 11:51:53.679219 Gating Mode config
3876 11:51:53.686205 ==============================================================
3877 11:51:53.686300 Config description:
3878 11:51:53.695818 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3879 11:51:53.702379 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3880 11:51:53.709308 SELPH_MODE 0: By rank 1: By Phase
3881 11:51:53.712867 ==============================================================
3882 11:51:53.715851 GAT_TRACK_EN = 1
3883 11:51:53.719134 RX_GATING_MODE = 2
3884 11:51:53.722259 RX_GATING_TRACK_MODE = 2
3885 11:51:53.725812 SELPH_MODE = 1
3886 11:51:53.728810 PICG_EARLY_EN = 1
3887 11:51:53.732767 VALID_LAT_VALUE = 1
3888 11:51:53.735809 ==============================================================
3889 11:51:53.738944 Enter into Gating configuration >>>>
3890 11:51:53.742153 Exit from Gating configuration <<<<
3891 11:51:53.745917 Enter into DVFS_PRE_config >>>>>
3892 11:51:53.758972 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3893 11:51:53.762386 Exit from DVFS_PRE_config <<<<<
3894 11:51:53.765565 Enter into PICG configuration >>>>
3895 11:51:53.765649 Exit from PICG configuration <<<<
3896 11:51:53.768904 [RX_INPUT] configuration >>>>>
3897 11:51:53.772420 [RX_INPUT] configuration <<<<<
3898 11:51:53.778729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3899 11:51:53.782655 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3900 11:51:53.788842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3901 11:51:53.795302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3902 11:51:53.801855 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3903 11:51:53.808453 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3904 11:51:53.812229 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3905 11:51:53.815312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3906 11:51:53.821831 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3907 11:51:53.825100 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3908 11:51:53.828397 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3909 11:51:53.832025 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3910 11:51:53.835226 ===================================
3911 11:51:53.838308 LPDDR4 DRAM CONFIGURATION
3912 11:51:53.841960 ===================================
3913 11:51:53.845065 EX_ROW_EN[0] = 0x0
3914 11:51:53.845152 EX_ROW_EN[1] = 0x0
3915 11:51:53.848637 LP4Y_EN = 0x0
3916 11:51:53.848724 WORK_FSP = 0x0
3917 11:51:53.851654 WL = 0x2
3918 11:51:53.851736 RL = 0x2
3919 11:51:53.855220 BL = 0x2
3920 11:51:53.855341 RPST = 0x0
3921 11:51:53.858288 RD_PRE = 0x0
3922 11:51:53.858372 WR_PRE = 0x1
3923 11:51:53.861682 WR_PST = 0x0
3924 11:51:53.861767 DBI_WR = 0x0
3925 11:51:53.865329 DBI_RD = 0x0
3926 11:51:53.865415 OTF = 0x1
3927 11:51:53.868562 ===================================
3928 11:51:53.874931 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3929 11:51:53.878059 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3930 11:51:53.881703 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 11:51:53.884871 ===================================
3932 11:51:53.888216 LPDDR4 DRAM CONFIGURATION
3933 11:51:53.891358 ===================================
3934 11:51:53.894883 EX_ROW_EN[0] = 0x10
3935 11:51:53.894980 EX_ROW_EN[1] = 0x0
3936 11:51:53.897908 LP4Y_EN = 0x0
3937 11:51:53.897996 WORK_FSP = 0x0
3938 11:51:53.901772 WL = 0x2
3939 11:51:53.901871 RL = 0x2
3940 11:51:53.904880 BL = 0x2
3941 11:51:53.904969 RPST = 0x0
3942 11:51:53.908399 RD_PRE = 0x0
3943 11:51:53.908490 WR_PRE = 0x1
3944 11:51:53.911814 WR_PST = 0x0
3945 11:51:53.911902 DBI_WR = 0x0
3946 11:51:53.914778 DBI_RD = 0x0
3947 11:51:53.914865 OTF = 0x1
3948 11:51:53.918515 ===================================
3949 11:51:53.924479 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3950 11:51:53.929207 nWR fixed to 30
3951 11:51:53.932842 [ModeRegInit_LP4] CH0 RK0
3952 11:51:53.932949 [ModeRegInit_LP4] CH0 RK1
3953 11:51:53.936331 [ModeRegInit_LP4] CH1 RK0
3954 11:51:53.939337 [ModeRegInit_LP4] CH1 RK1
3955 11:51:53.939428 match AC timing 17
3956 11:51:53.946289 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3957 11:51:53.949153 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3958 11:51:53.952518 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3959 11:51:53.959427 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3960 11:51:53.962431 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3961 11:51:53.962540 ==
3962 11:51:53.966370 Dram Type= 6, Freq= 0, CH_0, rank 0
3963 11:51:53.969072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3964 11:51:53.969168 ==
3965 11:51:53.975908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3966 11:51:53.982734 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3967 11:51:53.985979 [CA 0] Center 37 (7~67) winsize 61
3968 11:51:53.989006 [CA 1] Center 37 (7~67) winsize 61
3969 11:51:53.992427 [CA 2] Center 35 (5~65) winsize 61
3970 11:51:53.995892 [CA 3] Center 35 (5~65) winsize 61
3971 11:51:53.998907 [CA 4] Center 34 (4~65) winsize 62
3972 11:51:54.002359 [CA 5] Center 34 (4~64) winsize 61
3973 11:51:54.002469
3974 11:51:54.005496 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3975 11:51:54.005593
3976 11:51:54.009306 [CATrainingPosCal] consider 1 rank data
3977 11:51:54.012139 u2DelayCellTimex100 = 270/100 ps
3978 11:51:54.015762 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3979 11:51:54.019043 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3980 11:51:54.022360 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3981 11:51:54.025858 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3982 11:51:54.029285 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3983 11:51:54.035565 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3984 11:51:54.035684
3985 11:51:54.039047 CA PerBit enable=1, Macro0, CA PI delay=34
3986 11:51:54.039145
3987 11:51:54.042229 [CBTSetCACLKResult] CA Dly = 34
3988 11:51:54.042319 CS Dly: 6 (0~37)
3989 11:51:54.042385 ==
3990 11:51:54.045602 Dram Type= 6, Freq= 0, CH_0, rank 1
3991 11:51:54.048669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3992 11:51:54.052338 ==
3993 11:51:54.055526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3994 11:51:54.061966 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3995 11:51:54.065689 [CA 0] Center 37 (7~67) winsize 61
3996 11:51:54.068657 [CA 1] Center 36 (6~67) winsize 62
3997 11:51:54.071822 [CA 2] Center 35 (5~65) winsize 61
3998 11:51:54.075594 [CA 3] Center 35 (5~65) winsize 61
3999 11:51:54.078615 [CA 4] Center 34 (4~65) winsize 62
4000 11:51:54.082047 [CA 5] Center 33 (3~64) winsize 62
4001 11:51:54.082170
4002 11:51:54.085221 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4003 11:51:54.085326
4004 11:51:54.088491 [CATrainingPosCal] consider 2 rank data
4005 11:51:54.092052 u2DelayCellTimex100 = 270/100 ps
4006 11:51:54.095254 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4007 11:51:54.098901 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4008 11:51:54.101964 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4009 11:51:54.108434 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4010 11:51:54.112284 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4011 11:51:54.115170 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4012 11:51:54.115280
4013 11:51:54.118369 CA PerBit enable=1, Macro0, CA PI delay=34
4014 11:51:54.118473
4015 11:51:54.121574 [CBTSetCACLKResult] CA Dly = 34
4016 11:51:54.121713 CS Dly: 6 (0~38)
4017 11:51:54.121794
4018 11:51:54.125121 ----->DramcWriteLeveling(PI) begin...
4019 11:51:54.125235 ==
4020 11:51:54.128187 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 11:51:54.135109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 11:51:54.135254 ==
4023 11:51:54.138315 Write leveling (Byte 0): 33 => 33
4024 11:51:54.141556 Write leveling (Byte 1): 32 => 32
4025 11:51:54.145123 DramcWriteLeveling(PI) end<-----
4026 11:51:54.145251
4027 11:51:54.145318 ==
4028 11:51:54.148333 Dram Type= 6, Freq= 0, CH_0, rank 0
4029 11:51:54.151388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4030 11:51:54.151486 ==
4031 11:51:54.154852 [Gating] SW mode calibration
4032 11:51:54.161881 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4033 11:51:54.164752 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4034 11:51:54.171568 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4035 11:51:54.174707 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4036 11:51:54.177804 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4037 11:51:54.184432 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
4038 11:51:54.188038 0 9 16 | B1->B0 | 3232 2d2d | 1 1 | (1 1) (1 0)
4039 11:51:54.191716 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 11:51:54.197987 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 11:51:54.201050 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4042 11:51:54.204388 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4043 11:51:54.210930 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4044 11:51:54.214478 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4045 11:51:54.218102 0 10 12 | B1->B0 | 2929 2d2d | 0 0 | (0 0) (0 0)
4046 11:51:54.224689 0 10 16 | B1->B0 | 3535 3838 | 0 0 | (0 0) (0 0)
4047 11:51:54.227526 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 11:51:54.230977 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 11:51:54.237648 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 11:51:54.241125 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4051 11:51:54.244521 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4052 11:51:54.251049 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4053 11:51:54.254108 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4054 11:51:54.257368 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4055 11:51:54.264110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 11:51:54.267711 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 11:51:54.271001 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 11:51:54.277408 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 11:51:54.280414 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 11:51:54.283748 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 11:51:54.290648 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 11:51:54.293904 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 11:51:54.297135 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 11:51:54.303810 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 11:51:54.307517 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 11:51:54.310901 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4067 11:51:54.317315 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:51:54.320470 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:51:54.323773 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4070 11:51:54.330267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4071 11:51:54.333396 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 11:51:54.337178 Total UI for P1: 0, mck2ui 16
4073 11:51:54.340177 best dqsien dly found for B0: ( 0, 13, 14)
4074 11:51:54.343415 Total UI for P1: 0, mck2ui 16
4075 11:51:54.346818 best dqsien dly found for B1: ( 0, 13, 18)
4076 11:51:54.350212 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4077 11:51:54.353549 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4078 11:51:54.353656
4079 11:51:54.356768 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4080 11:51:54.360269 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4081 11:51:54.363572 [Gating] SW calibration Done
4082 11:51:54.363661 ==
4083 11:51:54.366771 Dram Type= 6, Freq= 0, CH_0, rank 0
4084 11:51:54.370085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4085 11:51:54.370170 ==
4086 11:51:54.373492 RX Vref Scan: 0
4087 11:51:54.373580
4088 11:51:54.376657 RX Vref 0 -> 0, step: 1
4089 11:51:54.376748
4090 11:51:54.376834 RX Delay -230 -> 252, step: 16
4091 11:51:54.384173 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4092 11:51:54.387167 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4093 11:51:54.390291 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4094 11:51:54.393466 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4095 11:51:54.400109 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4096 11:51:54.403872 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4097 11:51:54.407118 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4098 11:51:54.410063 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4099 11:51:54.413459 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4100 11:51:54.420144 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4101 11:51:54.423508 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4102 11:51:54.427142 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4103 11:51:54.430186 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4104 11:51:54.436525 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4105 11:51:54.439767 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4106 11:51:54.443292 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4107 11:51:54.443383 ==
4108 11:51:54.446457 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 11:51:54.453525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 11:51:54.453625 ==
4111 11:51:54.453692 DQS Delay:
4112 11:51:54.453752 DQS0 = 0, DQS1 = 0
4113 11:51:54.456140 DQM Delay:
4114 11:51:54.456247 DQM0 = 38, DQM1 = 30
4115 11:51:54.459567 DQ Delay:
4116 11:51:54.462856 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4117 11:51:54.466413 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4118 11:51:54.469770 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4119 11:51:54.472978 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4120 11:51:54.473065
4121 11:51:54.473130
4122 11:51:54.473190 ==
4123 11:51:54.476386 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 11:51:54.479635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 11:51:54.479719 ==
4126 11:51:54.479784
4127 11:51:54.479844
4128 11:51:54.483092 TX Vref Scan disable
4129 11:51:54.483202 == TX Byte 0 ==
4130 11:51:54.489964 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4131 11:51:54.492836 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4132 11:51:54.492923 == TX Byte 1 ==
4133 11:51:54.499784 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4134 11:51:54.503406 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4135 11:51:54.503546 ==
4136 11:51:54.506692 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 11:51:54.509488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 11:51:54.509593 ==
4139 11:51:54.509689
4140 11:51:54.509799
4141 11:51:54.513079 TX Vref Scan disable
4142 11:51:54.516465 == TX Byte 0 ==
4143 11:51:54.519808 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4144 11:51:54.523142 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4145 11:51:54.526398 == TX Byte 1 ==
4146 11:51:54.529957 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4147 11:51:54.533020 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4148 11:51:54.536017
4149 11:51:54.536102 [DATLAT]
4150 11:51:54.536189 Freq=600, CH0 RK0
4151 11:51:54.536276
4152 11:51:54.539432 DATLAT Default: 0x9
4153 11:51:54.539540 0, 0xFFFF, sum = 0
4154 11:51:54.542692 1, 0xFFFF, sum = 0
4155 11:51:54.542776 2, 0xFFFF, sum = 0
4156 11:51:54.546038 3, 0xFFFF, sum = 0
4157 11:51:54.546139 4, 0xFFFF, sum = 0
4158 11:51:54.549448 5, 0xFFFF, sum = 0
4159 11:51:54.552780 6, 0xFFFF, sum = 0
4160 11:51:54.552866 7, 0xFFFF, sum = 0
4161 11:51:54.552932 8, 0x0, sum = 1
4162 11:51:54.555955 9, 0x0, sum = 2
4163 11:51:54.556040 10, 0x0, sum = 3
4164 11:51:54.559760 11, 0x0, sum = 4
4165 11:51:54.559844 best_step = 9
4166 11:51:54.559910
4167 11:51:54.559970 ==
4168 11:51:54.562627 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 11:51:54.569132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 11:51:54.569221 ==
4171 11:51:54.569286 RX Vref Scan: 1
4172 11:51:54.569346
4173 11:51:54.572661 RX Vref 0 -> 0, step: 1
4174 11:51:54.572749
4175 11:51:54.575976 RX Delay -195 -> 252, step: 8
4176 11:51:54.576059
4177 11:51:54.579233 Set Vref, RX VrefLevel [Byte0]: 61
4178 11:51:54.582424 [Byte1]: 49
4179 11:51:54.582525
4180 11:51:54.585642 Final RX Vref Byte 0 = 61 to rank0
4181 11:51:54.589272 Final RX Vref Byte 1 = 49 to rank0
4182 11:51:54.592371 Final RX Vref Byte 0 = 61 to rank1
4183 11:51:54.595942 Final RX Vref Byte 1 = 49 to rank1==
4184 11:51:54.599122 Dram Type= 6, Freq= 0, CH_0, rank 0
4185 11:51:54.602249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4186 11:51:54.602365 ==
4187 11:51:54.605437 DQS Delay:
4188 11:51:54.605539 DQS0 = 0, DQS1 = 0
4189 11:51:54.608774 DQM Delay:
4190 11:51:54.608869 DQM0 = 35, DQM1 = 29
4191 11:51:54.608979 DQ Delay:
4192 11:51:54.612766 DQ0 =32, DQ1 =40, DQ2 =36, DQ3 =32
4193 11:51:54.616805 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4194 11:51:54.618797 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4195 11:51:54.622100 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4196 11:51:54.622207
4197 11:51:54.622302
4198 11:51:54.631764 [DQSOSCAuto] RK0, (LSB)MR18= 0x403f, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4199 11:51:54.635426 CH0 RK0: MR19=808, MR18=403F
4200 11:51:54.641926 CH0_RK0: MR19=0x808, MR18=0x403F, DQSOSC=397, MR23=63, INC=166, DEC=110
4201 11:51:54.642100
4202 11:51:54.645593 ----->DramcWriteLeveling(PI) begin...
4203 11:51:54.645682 ==
4204 11:51:54.648729 Dram Type= 6, Freq= 0, CH_0, rank 1
4205 11:51:54.651818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 11:51:54.651903 ==
4207 11:51:54.654994 Write leveling (Byte 0): 33 => 33
4208 11:51:54.658782 Write leveling (Byte 1): 32 => 32
4209 11:51:54.661642 DramcWriteLeveling(PI) end<-----
4210 11:51:54.661744
4211 11:51:54.661823 ==
4212 11:51:54.665134 Dram Type= 6, Freq= 0, CH_0, rank 1
4213 11:51:54.668639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4214 11:51:54.668723 ==
4215 11:51:54.671823 [Gating] SW mode calibration
4216 11:51:54.678186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4217 11:51:54.684881 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4218 11:51:54.688057 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4219 11:51:54.691938 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4220 11:51:54.698361 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4221 11:51:54.701363 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 1)
4222 11:51:54.704981 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4223 11:51:54.711613 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 11:51:54.714874 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 11:51:54.718017 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 11:51:54.724985 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4227 11:51:54.728166 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4228 11:51:54.731837 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4229 11:51:54.738309 0 10 12 | B1->B0 | 2c2c 3030 | 0 0 | (0 0) (0 0)
4230 11:51:54.741641 0 10 16 | B1->B0 | 3535 4545 | 1 0 | (0 0) (0 0)
4231 11:51:54.744335 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 11:51:54.751488 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 11:51:54.754422 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 11:51:54.758096 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 11:51:54.764470 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4236 11:51:54.767542 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4237 11:51:54.771129 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4238 11:51:54.777735 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4239 11:51:54.780839 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 11:51:54.784409 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 11:51:54.791268 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 11:51:54.794020 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 11:51:54.797826 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 11:51:54.803962 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 11:51:54.807474 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 11:51:54.811032 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 11:51:54.817156 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 11:51:54.820663 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 11:51:54.823763 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:51:54.830972 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:51:54.833836 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:51:54.837397 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:51:54.843722 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4254 11:51:54.843828 Total UI for P1: 0, mck2ui 16
4255 11:51:54.847158 best dqsien dly found for B0: ( 0, 13, 10)
4256 11:51:54.853937 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4257 11:51:54.857511 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4258 11:51:54.860656 Total UI for P1: 0, mck2ui 16
4259 11:51:54.863936 best dqsien dly found for B1: ( 0, 13, 18)
4260 11:51:54.867254 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4261 11:51:54.870310 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4262 11:51:54.870408
4263 11:51:54.873674 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4264 11:51:54.880113 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4265 11:51:54.880264 [Gating] SW calibration Done
4266 11:51:54.880337 ==
4267 11:51:54.883492 Dram Type= 6, Freq= 0, CH_0, rank 1
4268 11:51:54.890321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 11:51:54.890439 ==
4270 11:51:54.890506 RX Vref Scan: 0
4271 11:51:54.890566
4272 11:51:54.893523 RX Vref 0 -> 0, step: 1
4273 11:51:54.893608
4274 11:51:54.896994 RX Delay -230 -> 252, step: 16
4275 11:51:54.900274 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4276 11:51:54.903454 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4277 11:51:54.910177 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4278 11:51:54.913645 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4279 11:51:54.916750 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4280 11:51:54.920181 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4281 11:51:54.923712 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4282 11:51:54.929844 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4283 11:51:54.933380 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4284 11:51:54.936579 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4285 11:51:54.940212 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4286 11:51:54.946778 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4287 11:51:54.949719 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4288 11:51:54.953427 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4289 11:51:54.956590 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4290 11:51:54.963284 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4291 11:51:54.963429 ==
4292 11:51:54.966982 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 11:51:54.969778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 11:51:54.969884 ==
4295 11:51:54.969952 DQS Delay:
4296 11:51:54.973053 DQS0 = 0, DQS1 = 0
4297 11:51:54.973162 DQM Delay:
4298 11:51:54.976800 DQM0 = 36, DQM1 = 29
4299 11:51:54.976957 DQ Delay:
4300 11:51:54.980018 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4301 11:51:54.983203 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4302 11:51:54.986252 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4303 11:51:54.990059 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4304 11:51:54.990176
4305 11:51:54.990242
4306 11:51:54.990302 ==
4307 11:51:54.993277 Dram Type= 6, Freq= 0, CH_0, rank 1
4308 11:51:54.996355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4309 11:51:54.996470 ==
4310 11:51:54.996580
4311 11:51:54.996668
4312 11:51:54.999754 TX Vref Scan disable
4313 11:51:55.002842 == TX Byte 0 ==
4314 11:51:55.006418 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4315 11:51:55.009543 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4316 11:51:55.013141 == TX Byte 1 ==
4317 11:51:55.016338 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4318 11:51:55.019966 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4319 11:51:55.020055 ==
4320 11:51:55.023038 Dram Type= 6, Freq= 0, CH_0, rank 1
4321 11:51:55.029377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4322 11:51:55.029540 ==
4323 11:51:55.029654
4324 11:51:55.029757
4325 11:51:55.029848 TX Vref Scan disable
4326 11:51:55.033973 == TX Byte 0 ==
4327 11:51:55.037264 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4328 11:51:55.040747 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4329 11:51:55.044176 == TX Byte 1 ==
4330 11:51:55.047280 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4331 11:51:55.054214 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4332 11:51:55.054362
4333 11:51:55.054437 [DATLAT]
4334 11:51:55.054500 Freq=600, CH0 RK1
4335 11:51:55.054561
4336 11:51:55.057626 DATLAT Default: 0x9
4337 11:51:55.057710 0, 0xFFFF, sum = 0
4338 11:51:55.060419 1, 0xFFFF, sum = 0
4339 11:51:55.060501 2, 0xFFFF, sum = 0
4340 11:51:55.063725 3, 0xFFFF, sum = 0
4341 11:51:55.066991 4, 0xFFFF, sum = 0
4342 11:51:55.067080 5, 0xFFFF, sum = 0
4343 11:51:55.070661 6, 0xFFFF, sum = 0
4344 11:51:55.070742 7, 0xFFFF, sum = 0
4345 11:51:55.073683 8, 0x0, sum = 1
4346 11:51:55.073765 9, 0x0, sum = 2
4347 11:51:55.073845 10, 0x0, sum = 3
4348 11:51:55.077169 11, 0x0, sum = 4
4349 11:51:55.077251 best_step = 9
4350 11:51:55.077316
4351 11:51:55.077415 ==
4352 11:51:55.080179 Dram Type= 6, Freq= 0, CH_0, rank 1
4353 11:51:55.087111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 11:51:55.087265 ==
4355 11:51:55.087388 RX Vref Scan: 0
4356 11:51:55.087493
4357 11:51:55.090312 RX Vref 0 -> 0, step: 1
4358 11:51:55.090409
4359 11:51:55.093307 RX Delay -195 -> 252, step: 8
4360 11:51:55.097001 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4361 11:51:55.103420 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4362 11:51:55.106674 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4363 11:51:55.110014 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4364 11:51:55.113663 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4365 11:51:55.119893 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4366 11:51:55.123162 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4367 11:51:55.126432 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4368 11:51:55.130178 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4369 11:51:55.133159 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4370 11:51:55.139873 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4371 11:51:55.143345 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4372 11:51:55.146619 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4373 11:51:55.153015 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4374 11:51:55.156602 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4375 11:51:55.159637 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4376 11:51:55.159732 ==
4377 11:51:55.163256 Dram Type= 6, Freq= 0, CH_0, rank 1
4378 11:51:55.166373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4379 11:51:55.166490 ==
4380 11:51:55.169738 DQS Delay:
4381 11:51:55.169813 DQS0 = 0, DQS1 = 0
4382 11:51:55.173363 DQM Delay:
4383 11:51:55.173437 DQM0 = 33, DQM1 = 28
4384 11:51:55.173505 DQ Delay:
4385 11:51:55.176398 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4386 11:51:55.179759 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4387 11:51:55.182954 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4388 11:51:55.186421 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4389 11:51:55.186531
4390 11:51:55.186632
4391 11:51:55.196801 [DQSOSCAuto] RK1, (LSB)MR18= 0x7442, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 388 ps
4392 11:51:55.199877 CH0 RK1: MR19=808, MR18=7442
4393 11:51:55.203140 CH0_RK1: MR19=0x808, MR18=0x7442, DQSOSC=388, MR23=63, INC=174, DEC=116
4394 11:51:55.206398 [RxdqsGatingPostProcess] freq 600
4395 11:51:55.212940 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4396 11:51:55.216558 Pre-setting of DQS Precalculation
4397 11:51:55.219675 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4398 11:51:55.219758 ==
4399 11:51:55.223105 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 11:51:55.229494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 11:51:55.229610 ==
4402 11:51:55.232829 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4403 11:51:55.239745 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4404 11:51:55.243003 [CA 0] Center 35 (5~66) winsize 62
4405 11:51:55.246425 [CA 1] Center 36 (6~66) winsize 61
4406 11:51:55.249849 [CA 2] Center 34 (4~65) winsize 62
4407 11:51:55.253004 [CA 3] Center 34 (3~65) winsize 63
4408 11:51:55.256612 [CA 4] Center 34 (3~65) winsize 63
4409 11:51:55.259479 [CA 5] Center 33 (3~64) winsize 62
4410 11:51:55.259598
4411 11:51:55.263423 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4412 11:51:55.263513
4413 11:51:55.266391 [CATrainingPosCal] consider 1 rank data
4414 11:51:55.269637 u2DelayCellTimex100 = 270/100 ps
4415 11:51:55.272810 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4416 11:51:55.276768 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4417 11:51:55.283085 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4418 11:51:55.286195 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4419 11:51:55.289333 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4420 11:51:55.292868 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4421 11:51:55.292959
4422 11:51:55.296351 CA PerBit enable=1, Macro0, CA PI delay=33
4423 11:51:55.296428
4424 11:51:55.299778 [CBTSetCACLKResult] CA Dly = 33
4425 11:51:55.299852 CS Dly: 5 (0~36)
4426 11:51:55.302750 ==
4427 11:51:55.302870 Dram Type= 6, Freq= 0, CH_1, rank 1
4428 11:51:55.309563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4429 11:51:55.309677 ==
4430 11:51:55.312630 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4431 11:51:55.319679 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4432 11:51:55.323122 [CA 0] Center 36 (6~66) winsize 61
4433 11:51:55.326241 [CA 1] Center 35 (5~66) winsize 62
4434 11:51:55.329951 [CA 2] Center 34 (4~65) winsize 62
4435 11:51:55.333039 [CA 3] Center 34 (3~65) winsize 63
4436 11:51:55.336195 [CA 4] Center 34 (3~65) winsize 63
4437 11:51:55.339845 [CA 5] Center 34 (3~65) winsize 63
4438 11:51:55.339948
4439 11:51:55.343361 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4440 11:51:55.343481
4441 11:51:55.346345 [CATrainingPosCal] consider 2 rank data
4442 11:51:55.349421 u2DelayCellTimex100 = 270/100 ps
4443 11:51:55.353434 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4444 11:51:55.359591 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4445 11:51:55.363093 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4446 11:51:55.366106 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4447 11:51:55.369523 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4448 11:51:55.372752 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4449 11:51:55.372890
4450 11:51:55.375872 CA PerBit enable=1, Macro0, CA PI delay=33
4451 11:51:55.375991
4452 11:51:55.379238 [CBTSetCACLKResult] CA Dly = 33
4453 11:51:55.379349 CS Dly: 5 (0~37)
4454 11:51:55.382724
4455 11:51:55.386474 ----->DramcWriteLeveling(PI) begin...
4456 11:51:55.386575 ==
4457 11:51:55.389275 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 11:51:55.392944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 11:51:55.393042 ==
4460 11:51:55.395972 Write leveling (Byte 0): 30 => 30
4461 11:51:55.399241 Write leveling (Byte 1): 30 => 30
4462 11:51:55.402882 DramcWriteLeveling(PI) end<-----
4463 11:51:55.402965
4464 11:51:55.403032 ==
4465 11:51:55.406326 Dram Type= 6, Freq= 0, CH_1, rank 0
4466 11:51:55.409195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4467 11:51:55.409283 ==
4468 11:51:55.412878 [Gating] SW mode calibration
4469 11:51:55.419240 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4470 11:51:55.425764 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4471 11:51:55.429147 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4472 11:51:55.432397 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4473 11:51:55.439369 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4474 11:51:55.442481 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4475 11:51:55.446296 0 9 16 | B1->B0 | 2727 2525 | 0 0 | (1 1) (1 1)
4476 11:51:55.449402 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 11:51:55.456052 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4478 11:51:55.459304 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4479 11:51:55.462717 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4480 11:51:55.469723 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4481 11:51:55.472567 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4482 11:51:55.475991 0 10 12 | B1->B0 | 3030 3030 | 0 1 | (0 0) (0 0)
4483 11:51:55.482462 0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
4484 11:51:55.486189 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 11:51:55.489193 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 11:51:55.496349 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4487 11:51:55.499243 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4488 11:51:55.502458 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4489 11:51:55.509108 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4490 11:51:55.512233 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4491 11:51:55.515883 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 11:51:55.522571 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 11:51:55.525989 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 11:51:55.528908 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 11:51:55.535615 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 11:51:55.538806 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 11:51:55.542083 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 11:51:55.549207 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 11:51:55.552484 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 11:51:55.555433 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 11:51:55.562196 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:51:55.565491 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:51:55.568778 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:51:55.575279 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:51:55.578792 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:51:55.582148 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4507 11:51:55.585451 Total UI for P1: 0, mck2ui 16
4508 11:51:55.588877 best dqsien dly found for B0: ( 0, 13, 10)
4509 11:51:55.592216 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4510 11:51:55.595101 Total UI for P1: 0, mck2ui 16
4511 11:51:55.598527 best dqsien dly found for B1: ( 0, 13, 12)
4512 11:51:55.601967 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4513 11:51:55.608579 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4514 11:51:55.608739
4515 11:51:55.611713 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4516 11:51:55.615310 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4517 11:51:55.618773 [Gating] SW calibration Done
4518 11:51:55.618910 ==
4519 11:51:55.622078 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:51:55.625298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:51:55.625428 ==
4522 11:51:55.628828 RX Vref Scan: 0
4523 11:51:55.628950
4524 11:51:55.629048 RX Vref 0 -> 0, step: 1
4525 11:51:55.629140
4526 11:51:55.631778 RX Delay -230 -> 252, step: 16
4527 11:51:55.635235 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4528 11:51:55.642155 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4529 11:51:55.645447 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4530 11:51:55.648615 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4531 11:51:55.651912 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4532 11:51:55.658448 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4533 11:51:55.661489 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4534 11:51:55.665145 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4535 11:51:55.668341 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4536 11:51:55.671697 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4537 11:51:55.678091 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4538 11:51:55.681585 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4539 11:51:55.684917 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4540 11:51:55.688311 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4541 11:51:55.694642 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4542 11:51:55.698473 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4543 11:51:55.698653 ==
4544 11:51:55.701320 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 11:51:55.704949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 11:51:55.705112 ==
4547 11:51:55.707992 DQS Delay:
4548 11:51:55.708100 DQS0 = 0, DQS1 = 0
4549 11:51:55.708192 DQM Delay:
4550 11:51:55.711270 DQM0 = 39, DQM1 = 31
4551 11:51:55.711383 DQ Delay:
4552 11:51:55.714635 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4553 11:51:55.718009 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4554 11:51:55.721162 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4555 11:51:55.724927 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4556 11:51:55.725066
4557 11:51:55.725163
4558 11:51:55.725254 ==
4559 11:51:55.727701 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 11:51:55.734380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 11:51:55.734574 ==
4562 11:51:55.734687
4563 11:51:55.734784
4564 11:51:55.734876 TX Vref Scan disable
4565 11:51:55.738276 == TX Byte 0 ==
4566 11:51:55.742020 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4567 11:51:55.748183 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4568 11:51:55.748379 == TX Byte 1 ==
4569 11:51:55.751655 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4570 11:51:55.758087 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4571 11:51:55.758276 ==
4572 11:51:55.761829 Dram Type= 6, Freq= 0, CH_1, rank 0
4573 11:51:55.764956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4574 11:51:55.765111 ==
4575 11:51:55.765217
4576 11:51:55.765310
4577 11:51:55.768263 TX Vref Scan disable
4578 11:51:55.771541 == TX Byte 0 ==
4579 11:51:55.774521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4580 11:51:55.778034 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4581 11:51:55.781254 == TX Byte 1 ==
4582 11:51:55.784431 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4583 11:51:55.787810 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4584 11:51:55.787940
4585 11:51:55.788038 [DATLAT]
4586 11:51:55.791144 Freq=600, CH1 RK0
4587 11:51:55.791266
4588 11:51:55.794630 DATLAT Default: 0x9
4589 11:51:55.794749 0, 0xFFFF, sum = 0
4590 11:51:55.798012 1, 0xFFFF, sum = 0
4591 11:51:55.798128 2, 0xFFFF, sum = 0
4592 11:51:55.801384 3, 0xFFFF, sum = 0
4593 11:51:55.801505 4, 0xFFFF, sum = 0
4594 11:51:55.804956 5, 0xFFFF, sum = 0
4595 11:51:55.805086 6, 0xFFFF, sum = 0
4596 11:51:55.808047 7, 0xFFFF, sum = 0
4597 11:51:55.808165 8, 0x0, sum = 1
4598 11:51:55.811184 9, 0x0, sum = 2
4599 11:51:55.811302 10, 0x0, sum = 3
4600 11:51:55.811399 11, 0x0, sum = 4
4601 11:51:55.814847 best_step = 9
4602 11:51:55.814959
4603 11:51:55.815058 ==
4604 11:51:55.817847 Dram Type= 6, Freq= 0, CH_1, rank 0
4605 11:51:55.821686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4606 11:51:55.821786 ==
4607 11:51:55.824531 RX Vref Scan: 1
4608 11:51:55.824638
4609 11:51:55.824713 RX Vref 0 -> 0, step: 1
4610 11:51:55.824797
4611 11:51:55.828218 RX Delay -179 -> 252, step: 8
4612 11:51:55.828354
4613 11:51:55.831289 Set Vref, RX VrefLevel [Byte0]: 54
4614 11:51:55.835430 [Byte1]: 55
4615 11:51:55.838735
4616 11:51:55.838828 Final RX Vref Byte 0 = 54 to rank0
4617 11:51:55.842052 Final RX Vref Byte 1 = 55 to rank0
4618 11:51:55.845305 Final RX Vref Byte 0 = 54 to rank1
4619 11:51:55.848621 Final RX Vref Byte 1 = 55 to rank1==
4620 11:51:55.851987 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 11:51:55.858970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 11:51:55.859133 ==
4623 11:51:55.859238 DQS Delay:
4624 11:51:55.861879 DQS0 = 0, DQS1 = 0
4625 11:51:55.861994 DQM Delay:
4626 11:51:55.862091 DQM0 = 38, DQM1 = 27
4627 11:51:55.865645 DQ Delay:
4628 11:51:55.868678 DQ0 =44, DQ1 =36, DQ2 =24, DQ3 =36
4629 11:51:55.871767 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4630 11:51:55.875526 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4631 11:51:55.878872 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4632 11:51:55.879013
4633 11:51:55.879113
4634 11:51:55.884907 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b38, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 401 ps
4635 11:51:55.888634 CH1 RK0: MR19=808, MR18=2B38
4636 11:51:55.895204 CH1_RK0: MR19=0x808, MR18=0x2B38, DQSOSC=399, MR23=63, INC=164, DEC=109
4637 11:51:55.895407
4638 11:51:55.898449 ----->DramcWriteLeveling(PI) begin...
4639 11:51:55.898609 ==
4640 11:51:55.901931 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:51:55.905453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:51:55.905647 ==
4643 11:51:55.908326 Write leveling (Byte 0): 29 => 29
4644 11:51:55.911605 Write leveling (Byte 1): 33 => 33
4645 11:51:55.915168 DramcWriteLeveling(PI) end<-----
4646 11:51:55.915315
4647 11:51:55.915425 ==
4648 11:51:55.918361 Dram Type= 6, Freq= 0, CH_1, rank 1
4649 11:51:55.921919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4650 11:51:55.922046 ==
4651 11:51:55.925062 [Gating] SW mode calibration
4652 11:51:55.931669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4653 11:51:55.938002 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4654 11:51:55.941138 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4655 11:51:55.948035 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4656 11:51:55.951539 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4657 11:51:55.954519 0 9 12 | B1->B0 | 3131 2d2d | 0 0 | (1 1) (1 1)
4658 11:51:55.961788 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4659 11:51:55.964544 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 11:51:55.968254 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4661 11:51:55.974827 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4662 11:51:55.978238 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4663 11:51:55.981582 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4664 11:51:55.984663 0 10 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4665 11:51:55.991155 0 10 12 | B1->B0 | 2d2d 3d3d | 0 0 | (0 0) (0 0)
4666 11:51:55.994757 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4667 11:51:55.997753 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 11:51:56.004960 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 11:51:56.007851 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4670 11:51:56.011355 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4671 11:51:56.017884 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4672 11:51:56.021003 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4673 11:51:56.024365 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4674 11:51:56.031279 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4675 11:51:56.034644 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 11:51:56.038058 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 11:51:56.044257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 11:51:56.047775 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 11:51:56.050870 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 11:51:56.057527 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 11:51:56.061304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 11:51:56.064210 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 11:51:56.071032 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:51:56.074417 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 11:51:56.077690 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:51:56.084100 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:51:56.087330 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:51:56.091222 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:51:56.097305 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 11:51:56.097412 Total UI for P1: 0, mck2ui 16
4691 11:51:56.103932 best dqsien dly found for B0: ( 0, 13, 10)
4692 11:51:56.104056 Total UI for P1: 0, mck2ui 16
4693 11:51:56.110600 best dqsien dly found for B1: ( 0, 13, 10)
4694 11:51:56.114007 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4695 11:51:56.117528 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4696 11:51:56.117651
4697 11:51:56.120505 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4698 11:51:56.123746 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4699 11:51:56.127367 [Gating] SW calibration Done
4700 11:51:56.127480 ==
4701 11:51:56.130559 Dram Type= 6, Freq= 0, CH_1, rank 1
4702 11:51:56.133709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4703 11:51:56.133813 ==
4704 11:51:56.137461 RX Vref Scan: 0
4705 11:51:56.137556
4706 11:51:56.137624 RX Vref 0 -> 0, step: 1
4707 11:51:56.137686
4708 11:51:56.140373 RX Delay -230 -> 252, step: 16
4709 11:51:56.143901 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4710 11:51:56.150676 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4711 11:51:56.154062 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4712 11:51:56.157434 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4713 11:51:56.160906 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4714 11:51:56.166808 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4715 11:51:56.170555 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4716 11:51:56.173906 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4717 11:51:56.176780 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4718 11:51:56.183577 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4719 11:51:56.187108 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4720 11:51:56.190462 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4721 11:51:56.193833 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4722 11:51:56.196771 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4723 11:51:56.203701 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4724 11:51:56.206839 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4725 11:51:56.206971 ==
4726 11:51:56.210173 Dram Type= 6, Freq= 0, CH_1, rank 1
4727 11:51:56.213434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4728 11:51:56.213547 ==
4729 11:51:56.217237 DQS Delay:
4730 11:51:56.217355 DQS0 = 0, DQS1 = 0
4731 11:51:56.220170 DQM Delay:
4732 11:51:56.220291 DQM0 = 35, DQM1 = 29
4733 11:51:56.220390 DQ Delay:
4734 11:51:56.223279 DQ0 =33, DQ1 =33, DQ2 =17, DQ3 =33
4735 11:51:56.226999 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4736 11:51:56.230020 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4737 11:51:56.233370 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4738 11:51:56.233499
4739 11:51:56.233596
4740 11:51:56.233686 ==
4741 11:51:56.236867 Dram Type= 6, Freq= 0, CH_1, rank 1
4742 11:51:56.243463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4743 11:51:56.243643 ==
4744 11:51:56.243751
4745 11:51:56.243841
4746 11:51:56.246445 TX Vref Scan disable
4747 11:51:56.246555 == TX Byte 0 ==
4748 11:51:56.250058 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4749 11:51:56.256931 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4750 11:51:56.257083 == TX Byte 1 ==
4751 11:51:56.263145 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4752 11:51:56.266632 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4753 11:51:56.266752 ==
4754 11:51:56.270122 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 11:51:56.272811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 11:51:56.272926 ==
4757 11:51:56.273020
4758 11:51:56.273111
4759 11:51:56.276411 TX Vref Scan disable
4760 11:51:56.279531 == TX Byte 0 ==
4761 11:51:56.283095 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4762 11:51:56.286130 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4763 11:51:56.289448 == TX Byte 1 ==
4764 11:51:56.292648 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4765 11:51:56.296443 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4766 11:51:56.296555
4767 11:51:56.299554 [DATLAT]
4768 11:51:56.299662 Freq=600, CH1 RK1
4769 11:51:56.299759
4770 11:51:56.302719 DATLAT Default: 0x9
4771 11:51:56.302829 0, 0xFFFF, sum = 0
4772 11:51:56.306069 1, 0xFFFF, sum = 0
4773 11:51:56.306177 2, 0xFFFF, sum = 0
4774 11:51:56.309200 3, 0xFFFF, sum = 0
4775 11:51:56.309305 4, 0xFFFF, sum = 0
4776 11:51:56.312647 5, 0xFFFF, sum = 0
4777 11:51:56.312755 6, 0xFFFF, sum = 0
4778 11:51:56.315934 7, 0xFFFF, sum = 0
4779 11:51:56.316046 8, 0x0, sum = 1
4780 11:51:56.319380 9, 0x0, sum = 2
4781 11:51:56.319490 10, 0x0, sum = 3
4782 11:51:56.322471 11, 0x0, sum = 4
4783 11:51:56.322579 best_step = 9
4784 11:51:56.322669
4785 11:51:56.322762 ==
4786 11:51:56.326080 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 11:51:56.332397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 11:51:56.332514 ==
4789 11:51:56.332608 RX Vref Scan: 0
4790 11:51:56.332697
4791 11:51:56.335839 RX Vref 0 -> 0, step: 1
4792 11:51:56.335950
4793 11:51:56.339460 RX Delay -195 -> 252, step: 8
4794 11:51:56.342474 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4795 11:51:56.349278 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4796 11:51:56.352479 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4797 11:51:56.355529 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4798 11:51:56.358850 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4799 11:51:56.362217 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4800 11:51:56.369125 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4801 11:51:56.372256 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4802 11:51:56.375519 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4803 11:51:56.378747 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4804 11:51:56.385497 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4805 11:51:56.389033 iDelay=205, Bit 11, Center 24 (-139 ~ 188) 328
4806 11:51:56.392361 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4807 11:51:56.395387 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4808 11:51:56.401991 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4809 11:51:56.405591 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4810 11:51:56.405727 ==
4811 11:51:56.408818 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 11:51:56.412325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 11:51:56.412442 ==
4814 11:51:56.415482 DQS Delay:
4815 11:51:56.415593 DQS0 = 0, DQS1 = 0
4816 11:51:56.415686 DQM Delay:
4817 11:51:56.418662 DQM0 = 36, DQM1 = 30
4818 11:51:56.418778 DQ Delay:
4819 11:51:56.422296 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4820 11:51:56.425307 DQ4 =32, DQ5 =48, DQ6 =48, DQ7 =32
4821 11:51:56.428580 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4822 11:51:56.432008 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4823 11:51:56.432139
4824 11:51:56.432276
4825 11:51:56.442148 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d5c, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 398 ps
4826 11:51:56.442263 CH1 RK1: MR19=808, MR18=3D5C
4827 11:51:56.448986 CH1_RK1: MR19=0x808, MR18=0x3D5C, DQSOSC=392, MR23=63, INC=170, DEC=113
4828 11:51:56.451951 [RxdqsGatingPostProcess] freq 600
4829 11:51:56.458919 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4830 11:51:56.462410 Pre-setting of DQS Precalculation
4831 11:51:56.465526 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4832 11:51:56.472178 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4833 11:51:56.482030 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4834 11:51:56.482170
4835 11:51:56.482269
4836 11:51:56.482364 [Calibration Summary] 1200 Mbps
4837 11:51:56.484975 CH 0, Rank 0
4838 11:51:56.488945 SW Impedance : PASS
4839 11:51:56.489056 DUTY Scan : NO K
4840 11:51:56.491805 ZQ Calibration : PASS
4841 11:51:56.491912 Jitter Meter : NO K
4842 11:51:56.495247 CBT Training : PASS
4843 11:51:56.498413 Write leveling : PASS
4844 11:51:56.498528 RX DQS gating : PASS
4845 11:51:56.501871 RX DQ/DQS(RDDQC) : PASS
4846 11:51:56.505704 TX DQ/DQS : PASS
4847 11:51:56.505817 RX DATLAT : PASS
4848 11:51:56.508333 RX DQ/DQS(Engine): PASS
4849 11:51:56.511825 TX OE : NO K
4850 11:51:56.511941 All Pass.
4851 11:51:56.512034
4852 11:51:56.512123 CH 0, Rank 1
4853 11:51:56.514810 SW Impedance : PASS
4854 11:51:56.518647 DUTY Scan : NO K
4855 11:51:56.518760 ZQ Calibration : PASS
4856 11:51:56.521855 Jitter Meter : NO K
4857 11:51:56.524971 CBT Training : PASS
4858 11:51:56.525083 Write leveling : PASS
4859 11:51:56.528390 RX DQS gating : PASS
4860 11:51:56.531816 RX DQ/DQS(RDDQC) : PASS
4861 11:51:56.531924 TX DQ/DQS : PASS
4862 11:51:56.534996 RX DATLAT : PASS
4863 11:51:56.538183 RX DQ/DQS(Engine): PASS
4864 11:51:56.538291 TX OE : NO K
4865 11:51:56.538385 All Pass.
4866 11:51:56.541470
4867 11:51:56.541575 CH 1, Rank 0
4868 11:51:56.544943 SW Impedance : PASS
4869 11:51:56.545053 DUTY Scan : NO K
4870 11:51:56.548085 ZQ Calibration : PASS
4871 11:51:56.548215 Jitter Meter : NO K
4872 11:51:56.551736 CBT Training : PASS
4873 11:51:56.554557 Write leveling : PASS
4874 11:51:56.554667 RX DQS gating : PASS
4875 11:51:56.558084 RX DQ/DQS(RDDQC) : PASS
4876 11:51:56.561291 TX DQ/DQS : PASS
4877 11:51:56.561403 RX DATLAT : PASS
4878 11:51:56.564654 RX DQ/DQS(Engine): PASS
4879 11:51:56.567878 TX OE : NO K
4880 11:51:56.567985 All Pass.
4881 11:51:56.568076
4882 11:51:56.568164 CH 1, Rank 1
4883 11:51:56.571501 SW Impedance : PASS
4884 11:51:56.574895 DUTY Scan : NO K
4885 11:51:56.575003 ZQ Calibration : PASS
4886 11:51:56.577987 Jitter Meter : NO K
4887 11:51:56.580982 CBT Training : PASS
4888 11:51:56.581094 Write leveling : PASS
4889 11:51:56.584626 RX DQS gating : PASS
4890 11:51:56.588151 RX DQ/DQS(RDDQC) : PASS
4891 11:51:56.588309 TX DQ/DQS : PASS
4892 11:51:56.591139 RX DATLAT : PASS
4893 11:51:56.594388 RX DQ/DQS(Engine): PASS
4894 11:51:56.594496 TX OE : NO K
4895 11:51:56.594595 All Pass.
4896 11:51:56.597945
4897 11:51:56.598051 DramC Write-DBI off
4898 11:51:56.600913 PER_BANK_REFRESH: Hybrid Mode
4899 11:51:56.601020 TX_TRACKING: ON
4900 11:51:56.611105 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4901 11:51:56.614519 [FAST_K] Save calibration result to emmc
4902 11:51:56.617614 dramc_set_vcore_voltage set vcore to 662500
4903 11:51:56.620790 Read voltage for 933, 3
4904 11:51:56.620898 Vio18 = 0
4905 11:51:56.624720 Vcore = 662500
4906 11:51:56.624836 Vdram = 0
4907 11:51:56.624929 Vddq = 0
4908 11:51:56.625019 Vmddr = 0
4909 11:51:56.630669 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4910 11:51:56.637526 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4911 11:51:56.637653 MEM_TYPE=3, freq_sel=17
4912 11:51:56.641347 sv_algorithm_assistance_LP4_1600
4913 11:51:56.644452 ============ PULL DRAM RESETB DOWN ============
4914 11:51:56.650436 ========== PULL DRAM RESETB DOWN end =========
4915 11:51:56.654058 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4916 11:51:56.657259 ===================================
4917 11:51:56.661010 LPDDR4 DRAM CONFIGURATION
4918 11:51:56.663800 ===================================
4919 11:51:56.663913 EX_ROW_EN[0] = 0x0
4920 11:51:56.667701 EX_ROW_EN[1] = 0x0
4921 11:51:56.670475 LP4Y_EN = 0x0
4922 11:51:56.670583 WORK_FSP = 0x0
4923 11:51:56.674193 WL = 0x3
4924 11:51:56.674299 RL = 0x3
4925 11:51:56.677338 BL = 0x2
4926 11:51:56.677449 RPST = 0x0
4927 11:51:56.680576 RD_PRE = 0x0
4928 11:51:56.680682 WR_PRE = 0x1
4929 11:51:56.684257 WR_PST = 0x0
4930 11:51:56.684364 DBI_WR = 0x0
4931 11:51:56.687150 DBI_RD = 0x0
4932 11:51:56.687236 OTF = 0x1
4933 11:51:56.690620 ===================================
4934 11:51:56.694156 ===================================
4935 11:51:56.697107 ANA top config
4936 11:51:56.700843 ===================================
4937 11:51:56.700955 DLL_ASYNC_EN = 0
4938 11:51:56.703898 ALL_SLAVE_EN = 1
4939 11:51:56.707262 NEW_RANK_MODE = 1
4940 11:51:56.710344 DLL_IDLE_MODE = 1
4941 11:51:56.710453 LP45_APHY_COMB_EN = 1
4942 11:51:56.713975 TX_ODT_DIS = 1
4943 11:51:56.717091 NEW_8X_MODE = 1
4944 11:51:56.720488 ===================================
4945 11:51:56.723830 ===================================
4946 11:51:56.726994 data_rate = 1866
4947 11:51:56.730357 CKR = 1
4948 11:51:56.735136 DQ_P2S_RATIO = 8
4949 11:51:56.736986 ===================================
4950 11:51:56.737099 CA_P2S_RATIO = 8
4951 11:51:56.740642 DQ_CA_OPEN = 0
4952 11:51:56.743660 DQ_SEMI_OPEN = 0
4953 11:51:56.747273 CA_SEMI_OPEN = 0
4954 11:51:56.750466 CA_FULL_RATE = 0
4955 11:51:56.753971 DQ_CKDIV4_EN = 1
4956 11:51:56.754081 CA_CKDIV4_EN = 1
4957 11:51:56.757265 CA_PREDIV_EN = 0
4958 11:51:56.760625 PH8_DLY = 0
4959 11:51:56.763623 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4960 11:51:56.767201 DQ_AAMCK_DIV = 4
4961 11:51:56.767315 CA_AAMCK_DIV = 4
4962 11:51:56.770344 CA_ADMCK_DIV = 4
4963 11:51:56.773501 DQ_TRACK_CA_EN = 0
4964 11:51:56.776912 CA_PICK = 933
4965 11:51:56.780216 CA_MCKIO = 933
4966 11:51:56.783424 MCKIO_SEMI = 0
4967 11:51:56.787130 PLL_FREQ = 3732
4968 11:51:56.790372 DQ_UI_PI_RATIO = 32
4969 11:51:56.790482 CA_UI_PI_RATIO = 0
4970 11:51:56.793354 ===================================
4971 11:51:56.797027 ===================================
4972 11:51:56.800397 memory_type:LPDDR4
4973 11:51:56.803771 GP_NUM : 10
4974 11:51:56.803885 SRAM_EN : 1
4975 11:51:56.806703 MD32_EN : 0
4976 11:51:56.810231 ===================================
4977 11:51:56.813638 [ANA_INIT] >>>>>>>>>>>>>>
4978 11:51:56.813754 <<<<<< [CONFIGURE PHASE]: ANA_TX
4979 11:51:56.816735 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4980 11:51:56.820408 ===================================
4981 11:51:56.823617 data_rate = 1866,PCW = 0X8f00
4982 11:51:56.826753 ===================================
4983 11:51:56.829840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4984 11:51:56.836670 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4985 11:51:56.843416 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4986 11:51:56.846842 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4987 11:51:56.850635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4988 11:51:56.853126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4989 11:51:56.857036 [ANA_INIT] flow start
4990 11:51:56.857152 [ANA_INIT] PLL >>>>>>>>
4991 11:51:56.859921 [ANA_INIT] PLL <<<<<<<<
4992 11:51:56.863400 [ANA_INIT] MIDPI >>>>>>>>
4993 11:51:56.867038 [ANA_INIT] MIDPI <<<<<<<<
4994 11:51:56.867153 [ANA_INIT] DLL >>>>>>>>
4995 11:51:56.869923 [ANA_INIT] flow end
4996 11:51:56.873231 ============ LP4 DIFF to SE enter ============
4997 11:51:56.876939 ============ LP4 DIFF to SE exit ============
4998 11:51:56.880051 [ANA_INIT] <<<<<<<<<<<<<
4999 11:51:56.883013 [Flow] Enable top DCM control >>>>>
5000 11:51:56.886595 [Flow] Enable top DCM control <<<<<
5001 11:51:56.890026 Enable DLL master slave shuffle
5002 11:51:56.893185 ==============================================================
5003 11:51:56.896487 Gating Mode config
5004 11:51:56.903167 ==============================================================
5005 11:51:56.903287 Config description:
5006 11:51:56.913126 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5007 11:51:56.919904 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5008 11:51:56.926268 SELPH_MODE 0: By rank 1: By Phase
5009 11:51:56.929957 ==============================================================
5010 11:51:56.933292 GAT_TRACK_EN = 1
5011 11:51:56.936292 RX_GATING_MODE = 2
5012 11:51:56.939634 RX_GATING_TRACK_MODE = 2
5013 11:51:56.943272 SELPH_MODE = 1
5014 11:51:56.946339 PICG_EARLY_EN = 1
5015 11:51:56.950320 VALID_LAT_VALUE = 1
5016 11:51:56.952952 ==============================================================
5017 11:51:56.956087 Enter into Gating configuration >>>>
5018 11:51:56.959634 Exit from Gating configuration <<<<
5019 11:51:56.962930 Enter into DVFS_PRE_config >>>>>
5020 11:51:56.976168 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5021 11:51:56.979651 Exit from DVFS_PRE_config <<<<<
5022 11:51:56.983063 Enter into PICG configuration >>>>
5023 11:51:56.983176 Exit from PICG configuration <<<<
5024 11:51:56.986217 [RX_INPUT] configuration >>>>>
5025 11:51:56.989434 [RX_INPUT] configuration <<<<<
5026 11:51:56.995981 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5027 11:51:56.999239 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5028 11:51:57.006074 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5029 11:51:57.012874 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5030 11:51:57.019220 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5031 11:51:57.025752 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5032 11:51:57.029263 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5033 11:51:57.032366 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5034 11:51:57.035866 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5035 11:51:57.042597 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5036 11:51:57.045799 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5037 11:51:57.049024 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5038 11:51:57.052947 ===================================
5039 11:51:57.055707 LPDDR4 DRAM CONFIGURATION
5040 11:51:57.058980 ===================================
5041 11:51:57.062171 EX_ROW_EN[0] = 0x0
5042 11:51:57.062250 EX_ROW_EN[1] = 0x0
5043 11:51:57.065828 LP4Y_EN = 0x0
5044 11:51:57.065906 WORK_FSP = 0x0
5045 11:51:57.069010 WL = 0x3
5046 11:51:57.069083 RL = 0x3
5047 11:51:57.072115 BL = 0x2
5048 11:51:57.072256 RPST = 0x0
5049 11:51:57.075836 RD_PRE = 0x0
5050 11:51:57.075907 WR_PRE = 0x1
5051 11:51:57.079109 WR_PST = 0x0
5052 11:51:57.079187 DBI_WR = 0x0
5053 11:51:57.082144 DBI_RD = 0x0
5054 11:51:57.082227 OTF = 0x1
5055 11:51:57.085430 ===================================
5056 11:51:57.092000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5057 11:51:57.095802 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5058 11:51:57.098905 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5059 11:51:57.102195 ===================================
5060 11:51:57.105362 LPDDR4 DRAM CONFIGURATION
5061 11:51:57.108628 ===================================
5062 11:51:57.112241 EX_ROW_EN[0] = 0x10
5063 11:51:57.112327 EX_ROW_EN[1] = 0x0
5064 11:51:57.115581 LP4Y_EN = 0x0
5065 11:51:57.115665 WORK_FSP = 0x0
5066 11:51:57.118684 WL = 0x3
5067 11:51:57.118767 RL = 0x3
5068 11:51:57.122358 BL = 0x2
5069 11:51:57.122442 RPST = 0x0
5070 11:51:57.125621 RD_PRE = 0x0
5071 11:51:57.125705 WR_PRE = 0x1
5072 11:51:57.128879 WR_PST = 0x0
5073 11:51:57.128963 DBI_WR = 0x0
5074 11:51:57.132365 DBI_RD = 0x0
5075 11:51:57.132449 OTF = 0x1
5076 11:51:57.135316 ===================================
5077 11:51:57.142076 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5078 11:51:57.146422 nWR fixed to 30
5079 11:51:57.149839 [ModeRegInit_LP4] CH0 RK0
5080 11:51:57.149916 [ModeRegInit_LP4] CH0 RK1
5081 11:51:57.153176 [ModeRegInit_LP4] CH1 RK0
5082 11:51:57.156842 [ModeRegInit_LP4] CH1 RK1
5083 11:51:57.156923 match AC timing 9
5084 11:51:57.162960 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5085 11:51:57.166596 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5086 11:51:57.169790 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5087 11:51:57.176184 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5088 11:51:57.179991 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5089 11:51:57.180069 ==
5090 11:51:57.183298 Dram Type= 6, Freq= 0, CH_0, rank 0
5091 11:51:57.186358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5092 11:51:57.186459 ==
5093 11:51:57.193286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5094 11:51:57.199918 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5095 11:51:57.202821 [CA 0] Center 38 (8~69) winsize 62
5096 11:51:57.206121 [CA 1] Center 38 (7~69) winsize 63
5097 11:51:57.209704 [CA 2] Center 35 (5~66) winsize 62
5098 11:51:57.213202 [CA 3] Center 35 (4~66) winsize 63
5099 11:51:57.216211 [CA 4] Center 34 (4~65) winsize 62
5100 11:51:57.219359 [CA 5] Center 33 (3~64) winsize 62
5101 11:51:57.219461
5102 11:51:57.222877 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5103 11:51:57.222959
5104 11:51:57.226011 [CATrainingPosCal] consider 1 rank data
5105 11:51:57.229875 u2DelayCellTimex100 = 270/100 ps
5106 11:51:57.233150 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5107 11:51:57.235899 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5108 11:51:57.239900 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5109 11:51:57.242975 CA3 delay=35 (4~66),Diff = 2 PI (12 cell)
5110 11:51:57.249465 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5111 11:51:57.252816 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5112 11:51:57.252896
5113 11:51:57.255904 CA PerBit enable=1, Macro0, CA PI delay=33
5114 11:51:57.255982
5115 11:51:57.259448 [CBTSetCACLKResult] CA Dly = 33
5116 11:51:57.259525 CS Dly: 7 (0~38)
5117 11:51:57.259589 ==
5118 11:51:57.262548 Dram Type= 6, Freq= 0, CH_0, rank 1
5119 11:51:57.266037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5120 11:51:57.269077 ==
5121 11:51:57.272987 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5122 11:51:57.279161 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5123 11:51:57.282818 [CA 0] Center 38 (8~69) winsize 62
5124 11:51:57.286205 [CA 1] Center 38 (8~69) winsize 62
5125 11:51:57.289284 [CA 2] Center 35 (5~66) winsize 62
5126 11:51:57.292596 [CA 3] Center 35 (5~66) winsize 62
5127 11:51:57.295625 [CA 4] Center 34 (4~65) winsize 62
5128 11:51:57.299198 [CA 5] Center 34 (4~64) winsize 61
5129 11:51:57.299277
5130 11:51:57.302345 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5131 11:51:57.302423
5132 11:51:57.305729 [CATrainingPosCal] consider 2 rank data
5133 11:51:57.308869 u2DelayCellTimex100 = 270/100 ps
5134 11:51:57.312185 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5135 11:51:57.315794 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5136 11:51:57.319110 CA2 delay=35 (5~66),Diff = 1 PI (6 cell)
5137 11:51:57.322297 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5138 11:51:57.328924 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5139 11:51:57.332147 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5140 11:51:57.332259
5141 11:51:57.335663 CA PerBit enable=1, Macro0, CA PI delay=34
5142 11:51:57.335745
5143 11:51:57.338806 [CBTSetCACLKResult] CA Dly = 34
5144 11:51:57.338888 CS Dly: 7 (0~39)
5145 11:51:57.338952
5146 11:51:57.342629 ----->DramcWriteLeveling(PI) begin...
5147 11:51:57.342713 ==
5148 11:51:57.345348 Dram Type= 6, Freq= 0, CH_0, rank 0
5149 11:51:57.352554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5150 11:51:57.352641 ==
5151 11:51:57.355630 Write leveling (Byte 0): 30 => 30
5152 11:51:57.358724 Write leveling (Byte 1): 27 => 27
5153 11:51:57.358805 DramcWriteLeveling(PI) end<-----
5154 11:51:57.358870
5155 11:51:57.362403 ==
5156 11:51:57.365247 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 11:51:57.368525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 11:51:57.368612 ==
5159 11:51:57.372169 [Gating] SW mode calibration
5160 11:51:57.378534 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5161 11:51:57.382549 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5162 11:51:57.388703 0 14 0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
5163 11:51:57.391821 0 14 4 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
5164 11:51:57.395090 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5165 11:51:57.401843 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5166 11:51:57.405270 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5167 11:51:57.408549 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5168 11:51:57.415372 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5169 11:51:57.418296 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5170 11:51:57.422036 0 15 0 | B1->B0 | 3333 2c2c | 1 1 | (1 1) (1 0)
5171 11:51:57.428466 0 15 4 | B1->B0 | 2727 2323 | 1 0 | (1 0) (0 0)
5172 11:51:57.431756 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5173 11:51:57.434912 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5174 11:51:57.441782 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5175 11:51:57.444787 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5176 11:51:57.448419 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5177 11:51:57.454923 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5178 11:51:57.458052 1 0 0 | B1->B0 | 2929 3d3d | 0 0 | (0 0) (0 0)
5179 11:51:57.461439 1 0 4 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5180 11:51:57.467998 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5181 11:51:57.471266 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5182 11:51:57.474894 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5183 11:51:57.481228 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5184 11:51:57.484677 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5185 11:51:57.487918 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5186 11:51:57.494771 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5187 11:51:57.497957 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5188 11:51:57.501537 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 11:51:57.508325 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 11:51:57.511305 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 11:51:57.514777 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 11:51:57.521221 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 11:51:57.524580 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 11:51:57.528007 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 11:51:57.534690 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 11:51:57.537736 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5197 11:51:57.540812 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5198 11:51:57.544520 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:51:57.550996 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:51:57.554022 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:51:57.557302 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5202 11:51:57.564440 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5203 11:51:57.567334 Total UI for P1: 0, mck2ui 16
5204 11:51:57.570465 best dqsien dly found for B0: ( 1, 2, 28)
5205 11:51:57.573835 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 11:51:57.577459 Total UI for P1: 0, mck2ui 16
5207 11:51:57.580876 best dqsien dly found for B1: ( 1, 3, 0)
5208 11:51:57.584311 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5209 11:51:57.587275 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5210 11:51:57.587362
5211 11:51:57.590744 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5212 11:51:57.594042 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5213 11:51:57.597333 [Gating] SW calibration Done
5214 11:51:57.597411 ==
5215 11:51:57.600639 Dram Type= 6, Freq= 0, CH_0, rank 0
5216 11:51:57.607672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5217 11:51:57.607765 ==
5218 11:51:57.607840 RX Vref Scan: 0
5219 11:51:57.607901
5220 11:51:57.610660 RX Vref 0 -> 0, step: 1
5221 11:51:57.610734
5222 11:51:57.613925 RX Delay -80 -> 252, step: 8
5223 11:51:57.617462 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5224 11:51:57.620416 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5225 11:51:57.623763 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5226 11:51:57.627206 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5227 11:51:57.630567 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5228 11:51:57.637367 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5229 11:51:57.640472 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5230 11:51:57.643712 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5231 11:51:57.647020 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5232 11:51:57.650266 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5233 11:51:57.657191 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5234 11:51:57.661319 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5235 11:51:57.663784 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5236 11:51:57.667159 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5237 11:51:57.670252 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5238 11:51:57.676968 iDelay=208, Bit 15, Center 87 (-16 ~ 191) 208
5239 11:51:57.677061 ==
5240 11:51:57.680659 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 11:51:57.683674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 11:51:57.683750 ==
5243 11:51:57.683814 DQS Delay:
5244 11:51:57.687217 DQS0 = 0, DQS1 = 0
5245 11:51:57.687295 DQM Delay:
5246 11:51:57.690271 DQM0 = 94, DQM1 = 82
5247 11:51:57.690346 DQ Delay:
5248 11:51:57.693598 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5249 11:51:57.697310 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5250 11:51:57.700325 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5251 11:51:57.704034 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =87
5252 11:51:57.704110
5253 11:51:57.704173
5254 11:51:57.704271 ==
5255 11:51:57.706899 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 11:51:57.710500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 11:51:57.710587 ==
5258 11:51:57.713729
5259 11:51:57.713813
5260 11:51:57.713876 TX Vref Scan disable
5261 11:51:57.717115 == TX Byte 0 ==
5262 11:51:57.720422 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5263 11:51:57.723869 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5264 11:51:57.726976 == TX Byte 1 ==
5265 11:51:57.730581 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5266 11:51:57.733627 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5267 11:51:57.733715 ==
5268 11:51:57.736723 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 11:51:57.743400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 11:51:57.743485 ==
5271 11:51:57.743556
5272 11:51:57.743616
5273 11:51:57.746989 TX Vref Scan disable
5274 11:51:57.747060 == TX Byte 0 ==
5275 11:51:57.753273 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5276 11:51:57.757026 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5277 11:51:57.757112 == TX Byte 1 ==
5278 11:51:57.763458 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5279 11:51:57.766559 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5280 11:51:57.766642
5281 11:51:57.766706 [DATLAT]
5282 11:51:57.770224 Freq=933, CH0 RK0
5283 11:51:57.770306
5284 11:51:57.770370 DATLAT Default: 0xd
5285 11:51:57.773396 0, 0xFFFF, sum = 0
5286 11:51:57.773478 1, 0xFFFF, sum = 0
5287 11:51:57.776352 2, 0xFFFF, sum = 0
5288 11:51:57.776435 3, 0xFFFF, sum = 0
5289 11:51:57.780153 4, 0xFFFF, sum = 0
5290 11:51:57.780289 5, 0xFFFF, sum = 0
5291 11:51:57.783079 6, 0xFFFF, sum = 0
5292 11:51:57.783164 7, 0xFFFF, sum = 0
5293 11:51:57.786568 8, 0xFFFF, sum = 0
5294 11:51:57.786642 9, 0xFFFF, sum = 0
5295 11:51:57.789732 10, 0x0, sum = 1
5296 11:51:57.789817 11, 0x0, sum = 2
5297 11:51:57.793477 12, 0x0, sum = 3
5298 11:51:57.793562 13, 0x0, sum = 4
5299 11:51:57.796453 best_step = 11
5300 11:51:57.796536
5301 11:51:57.796599 ==
5302 11:51:57.799602 Dram Type= 6, Freq= 0, CH_0, rank 0
5303 11:51:57.802928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5304 11:51:57.803012 ==
5305 11:51:57.806347 RX Vref Scan: 1
5306 11:51:57.806428
5307 11:51:57.806492 RX Vref 0 -> 0, step: 1
5308 11:51:57.806552
5309 11:51:57.809806 RX Delay -69 -> 252, step: 4
5310 11:51:57.809888
5311 11:51:57.812994 Set Vref, RX VrefLevel [Byte0]: 61
5312 11:51:57.816610 [Byte1]: 49
5313 11:51:57.820580
5314 11:51:57.820675 Final RX Vref Byte 0 = 61 to rank0
5315 11:51:57.823874 Final RX Vref Byte 1 = 49 to rank0
5316 11:51:57.827245 Final RX Vref Byte 0 = 61 to rank1
5317 11:51:57.830421 Final RX Vref Byte 1 = 49 to rank1==
5318 11:51:57.833632 Dram Type= 6, Freq= 0, CH_0, rank 0
5319 11:51:57.840185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5320 11:51:57.840315 ==
5321 11:51:57.840381 DQS Delay:
5322 11:51:57.840441 DQS0 = 0, DQS1 = 0
5323 11:51:57.843521 DQM Delay:
5324 11:51:57.843603 DQM0 = 95, DQM1 = 83
5325 11:51:57.847034 DQ Delay:
5326 11:51:57.850276 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5327 11:51:57.853746 DQ4 =96, DQ5 =84, DQ6 =102, DQ7 =106
5328 11:51:57.857228 DQ8 =76, DQ9 =68, DQ10 =84, DQ11 =76
5329 11:51:57.860575 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5330 11:51:57.860666
5331 11:51:57.860731
5332 11:51:57.866917 [DQSOSCAuto] RK0, (LSB)MR18= 0x1211, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5333 11:51:57.870386 CH0 RK0: MR19=505, MR18=1211
5334 11:51:57.876813 CH0_RK0: MR19=0x505, MR18=0x1211, DQSOSC=416, MR23=63, INC=62, DEC=41
5335 11:51:57.876927
5336 11:51:57.880039 ----->DramcWriteLeveling(PI) begin...
5337 11:51:57.880122 ==
5338 11:51:57.883445 Dram Type= 6, Freq= 0, CH_0, rank 1
5339 11:51:57.886668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 11:51:57.886810 ==
5341 11:51:57.890039 Write leveling (Byte 0): 30 => 30
5342 11:51:57.893300 Write leveling (Byte 1): 31 => 31
5343 11:51:57.896858 DramcWriteLeveling(PI) end<-----
5344 11:51:57.896960
5345 11:51:57.897072 ==
5346 11:51:57.900375 Dram Type= 6, Freq= 0, CH_0, rank 1
5347 11:51:57.903604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5348 11:51:57.903688 ==
5349 11:51:57.906991 [Gating] SW mode calibration
5350 11:51:57.913172 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5351 11:51:57.919921 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5352 11:51:57.923541 0 14 0 | B1->B0 | 2727 3434 | 1 0 | (1 1) (0 0)
5353 11:51:57.929908 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
5354 11:51:57.933250 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5355 11:51:57.936458 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5356 11:51:57.943367 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5357 11:51:57.946670 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5358 11:51:57.949897 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5359 11:51:57.953316 0 14 28 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 1)
5360 11:51:57.959660 0 15 0 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
5361 11:51:57.963233 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 11:51:57.966927 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5363 11:51:57.973219 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5364 11:51:57.976801 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5365 11:51:57.979715 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5366 11:51:57.986363 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5367 11:51:57.989618 0 15 28 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5368 11:51:57.993174 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5369 11:51:57.999607 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 11:51:58.002777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 11:51:58.006330 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5372 11:51:58.012755 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5373 11:51:58.016354 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5374 11:51:58.019353 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5375 11:51:58.025962 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5376 11:51:58.029491 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5377 11:51:58.032650 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 11:51:58.039341 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 11:51:58.043079 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 11:51:58.045864 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 11:51:58.052913 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 11:51:58.055940 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 11:51:58.059330 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 11:51:58.065629 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 11:51:58.069074 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 11:51:58.072525 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:51:58.079210 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:51:58.082259 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:51:58.085659 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:51:58.092358 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5391 11:51:58.095659 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5392 11:51:58.099158 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5393 11:51:58.102321 Total UI for P1: 0, mck2ui 16
5394 11:51:58.105821 best dqsien dly found for B0: ( 1, 2, 26)
5395 11:51:58.112330 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5396 11:51:58.112414 Total UI for P1: 0, mck2ui 16
5397 11:51:58.115660 best dqsien dly found for B1: ( 1, 3, 0)
5398 11:51:58.122336 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5399 11:51:58.125777 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5400 11:51:58.125860
5401 11:51:58.128652 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5402 11:51:58.132278 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5403 11:51:58.135729 [Gating] SW calibration Done
5404 11:51:58.135811 ==
5405 11:51:58.138582 Dram Type= 6, Freq= 0, CH_0, rank 1
5406 11:51:58.142165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5407 11:51:58.142247 ==
5408 11:51:58.145396 RX Vref Scan: 0
5409 11:51:58.145476
5410 11:51:58.145540 RX Vref 0 -> 0, step: 1
5411 11:51:58.145600
5412 11:51:58.149157 RX Delay -80 -> 252, step: 8
5413 11:51:58.152247 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5414 11:51:58.155311 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5415 11:51:58.161862 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5416 11:51:58.165403 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5417 11:51:58.168773 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5418 11:51:58.171803 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5419 11:51:58.175651 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5420 11:51:58.182160 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5421 11:51:58.185413 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5422 11:51:58.188481 iDelay=208, Bit 9, Center 63 (-32 ~ 159) 192
5423 11:51:58.192179 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5424 11:51:58.195438 iDelay=208, Bit 11, Center 71 (-24 ~ 167) 192
5425 11:51:58.202231 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5426 11:51:58.205428 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5427 11:51:58.208439 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5428 11:51:58.212196 iDelay=208, Bit 15, Center 87 (-8 ~ 183) 192
5429 11:51:58.212323 ==
5430 11:51:58.215399 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:51:58.218470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:51:58.221731 ==
5433 11:51:58.221806 DQS Delay:
5434 11:51:58.221868 DQS0 = 0, DQS1 = 0
5435 11:51:58.225328 DQM Delay:
5436 11:51:58.225405 DQM0 = 91, DQM1 = 81
5437 11:51:58.228266 DQ Delay:
5438 11:51:58.228339 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5439 11:51:58.231927 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =103
5440 11:51:58.235001 DQ8 =75, DQ9 =63, DQ10 =87, DQ11 =71
5441 11:51:58.238252 DQ12 =87, DQ13 =91, DQ14 =91, DQ15 =87
5442 11:51:58.241727
5443 11:51:58.241809
5444 11:51:58.241873 ==
5445 11:51:58.245272 Dram Type= 6, Freq= 0, CH_0, rank 1
5446 11:51:58.248194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5447 11:51:58.248311 ==
5448 11:51:58.248375
5449 11:51:58.248434
5450 11:51:58.251768 TX Vref Scan disable
5451 11:51:58.251848 == TX Byte 0 ==
5452 11:51:58.258505 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5453 11:51:58.261698 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5454 11:51:58.261780 == TX Byte 1 ==
5455 11:51:58.268185 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5456 11:51:58.272057 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5457 11:51:58.272139 ==
5458 11:51:58.275144 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 11:51:58.278344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 11:51:58.278426 ==
5461 11:51:58.278490
5462 11:51:58.278549
5463 11:51:58.281769 TX Vref Scan disable
5464 11:51:58.284882 == TX Byte 0 ==
5465 11:51:58.288239 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5466 11:51:58.291670 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5467 11:51:58.294743 == TX Byte 1 ==
5468 11:51:58.298160 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5469 11:51:58.301555 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5470 11:51:58.301660
5471 11:51:58.304935 [DATLAT]
5472 11:51:58.305009 Freq=933, CH0 RK1
5473 11:51:58.305072
5474 11:51:58.308187 DATLAT Default: 0xb
5475 11:51:58.308280 0, 0xFFFF, sum = 0
5476 11:51:58.311194 1, 0xFFFF, sum = 0
5477 11:51:58.311278 2, 0xFFFF, sum = 0
5478 11:51:58.314514 3, 0xFFFF, sum = 0
5479 11:51:58.314596 4, 0xFFFF, sum = 0
5480 11:51:58.317881 5, 0xFFFF, sum = 0
5481 11:51:58.317963 6, 0xFFFF, sum = 0
5482 11:51:58.321649 7, 0xFFFF, sum = 0
5483 11:51:58.321762 8, 0xFFFF, sum = 0
5484 11:51:58.324748 9, 0xFFFF, sum = 0
5485 11:51:58.324830 10, 0x0, sum = 1
5486 11:51:58.327932 11, 0x0, sum = 2
5487 11:51:58.328014 12, 0x0, sum = 3
5488 11:51:58.331372 13, 0x0, sum = 4
5489 11:51:58.331454 best_step = 11
5490 11:51:58.331518
5491 11:51:58.331577 ==
5492 11:51:58.334448 Dram Type= 6, Freq= 0, CH_0, rank 1
5493 11:51:58.341425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 11:51:58.341510 ==
5495 11:51:58.341586 RX Vref Scan: 0
5496 11:51:58.341647
5497 11:51:58.344400 RX Vref 0 -> 0, step: 1
5498 11:51:58.344481
5499 11:51:58.348111 RX Delay -77 -> 252, step: 4
5500 11:51:58.351365 iDelay=199, Bit 0, Center 92 (-1 ~ 186) 188
5501 11:51:58.354560 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5502 11:51:58.361031 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5503 11:51:58.364255 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5504 11:51:58.367779 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5505 11:51:58.371241 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5506 11:51:58.374657 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5507 11:51:58.380905 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5508 11:51:58.384431 iDelay=199, Bit 8, Center 76 (-13 ~ 166) 180
5509 11:51:58.387813 iDelay=199, Bit 9, Center 70 (-17 ~ 158) 176
5510 11:51:58.390981 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5511 11:51:58.394278 iDelay=199, Bit 11, Center 76 (-13 ~ 166) 180
5512 11:51:58.400870 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5513 11:51:58.404118 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5514 11:51:58.407287 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5515 11:51:58.410807 iDelay=199, Bit 15, Center 90 (-1 ~ 182) 184
5516 11:51:58.410885 ==
5517 11:51:58.414053 Dram Type= 6, Freq= 0, CH_0, rank 1
5518 11:51:58.417263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 11:51:58.420707 ==
5520 11:51:58.420793 DQS Delay:
5521 11:51:58.420877 DQS0 = 0, DQS1 = 0
5522 11:51:58.424096 DQM Delay:
5523 11:51:58.424186 DQM0 = 93, DQM1 = 84
5524 11:51:58.427410 DQ Delay:
5525 11:51:58.427509 DQ0 =92, DQ1 =94, DQ2 =90, DQ3 =88
5526 11:51:58.430396 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
5527 11:51:58.434534 DQ8 =76, DQ9 =70, DQ10 =86, DQ11 =76
5528 11:51:58.440366 DQ12 =92, DQ13 =90, DQ14 =96, DQ15 =90
5529 11:51:58.440452
5530 11:51:58.440516
5531 11:51:58.447119 [DQSOSCAuto] RK1, (LSB)MR18= 0x3011, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 406 ps
5532 11:51:58.450267 CH0 RK1: MR19=505, MR18=3011
5533 11:51:58.457307 CH0_RK1: MR19=0x505, MR18=0x3011, DQSOSC=406, MR23=63, INC=65, DEC=43
5534 11:51:58.460429 [RxdqsGatingPostProcess] freq 933
5535 11:51:58.463728 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5536 11:51:58.466979 best DQS0 dly(2T, 0.5T) = (0, 10)
5537 11:51:58.470169 best DQS1 dly(2T, 0.5T) = (0, 11)
5538 11:51:58.473891 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5539 11:51:58.476830 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5540 11:51:58.480375 best DQS0 dly(2T, 0.5T) = (0, 10)
5541 11:51:58.483788 best DQS1 dly(2T, 0.5T) = (0, 11)
5542 11:51:58.487188 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5543 11:51:58.490345 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5544 11:51:58.493507 Pre-setting of DQS Precalculation
5545 11:51:58.496749 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5546 11:51:58.496833 ==
5547 11:51:58.500088 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 11:51:58.506590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 11:51:58.506676 ==
5550 11:51:58.510272 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5551 11:51:58.516591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5552 11:51:58.519864 [CA 0] Center 37 (8~67) winsize 60
5553 11:51:58.523606 [CA 1] Center 37 (7~68) winsize 62
5554 11:51:58.526545 [CA 2] Center 35 (6~64) winsize 59
5555 11:51:58.529801 [CA 3] Center 34 (4~64) winsize 61
5556 11:51:58.533370 [CA 4] Center 34 (5~64) winsize 60
5557 11:51:58.536837 [CA 5] Center 34 (4~64) winsize 61
5558 11:51:58.536926
5559 11:51:58.539975 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5560 11:51:58.540059
5561 11:51:58.543054 [CATrainingPosCal] consider 1 rank data
5562 11:51:58.546416 u2DelayCellTimex100 = 270/100 ps
5563 11:51:58.550054 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5564 11:51:58.553433 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5565 11:51:58.559915 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5566 11:51:58.563017 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5567 11:51:58.566214 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5568 11:51:58.569770 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5569 11:51:58.569854
5570 11:51:58.572958 CA PerBit enable=1, Macro0, CA PI delay=34
5571 11:51:58.573040
5572 11:51:58.576517 [CBTSetCACLKResult] CA Dly = 34
5573 11:51:58.576599 CS Dly: 6 (0~37)
5574 11:51:58.576664 ==
5575 11:51:58.579694 Dram Type= 6, Freq= 0, CH_1, rank 1
5576 11:51:58.586157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5577 11:51:58.586241 ==
5578 11:51:58.589804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5579 11:51:58.596384 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5580 11:51:58.599827 [CA 0] Center 38 (8~68) winsize 61
5581 11:51:58.603460 [CA 1] Center 37 (7~68) winsize 62
5582 11:51:58.606283 [CA 2] Center 35 (5~65) winsize 61
5583 11:51:58.609893 [CA 3] Center 34 (4~64) winsize 61
5584 11:51:58.613382 [CA 4] Center 35 (5~65) winsize 61
5585 11:51:58.616323 [CA 5] Center 34 (4~64) winsize 61
5586 11:51:58.616407
5587 11:51:58.620077 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5588 11:51:58.620161
5589 11:51:58.623266 [CATrainingPosCal] consider 2 rank data
5590 11:51:58.626391 u2DelayCellTimex100 = 270/100 ps
5591 11:51:58.629612 CA0 delay=37 (8~67),Diff = 3 PI (18 cell)
5592 11:51:58.636193 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5593 11:51:58.639704 CA2 delay=35 (6~64),Diff = 1 PI (6 cell)
5594 11:51:58.642893 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5595 11:51:58.646117 CA4 delay=34 (5~64),Diff = 0 PI (0 cell)
5596 11:51:58.649202 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5597 11:51:58.649310
5598 11:51:58.652979 CA PerBit enable=1, Macro0, CA PI delay=34
5599 11:51:58.653062
5600 11:51:58.655902 [CBTSetCACLKResult] CA Dly = 34
5601 11:51:58.655986 CS Dly: 7 (0~39)
5602 11:51:58.659308
5603 11:51:58.662854 ----->DramcWriteLeveling(PI) begin...
5604 11:51:58.662939 ==
5605 11:51:58.666053 Dram Type= 6, Freq= 0, CH_1, rank 0
5606 11:51:58.669450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5607 11:51:58.669534 ==
5608 11:51:58.672511 Write leveling (Byte 0): 27 => 27
5609 11:51:58.675838 Write leveling (Byte 1): 28 => 28
5610 11:51:58.678851 DramcWriteLeveling(PI) end<-----
5611 11:51:58.678935
5612 11:51:58.679020 ==
5613 11:51:58.682553 Dram Type= 6, Freq= 0, CH_1, rank 0
5614 11:51:58.685846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5615 11:51:58.685930 ==
5616 11:51:58.689119 [Gating] SW mode calibration
5617 11:51:58.695607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5618 11:51:58.702525 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5619 11:51:58.705587 0 14 0 | B1->B0 | 3333 3333 | 0 0 | (0 0) (0 0)
5620 11:51:58.708935 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 11:51:58.715225 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5622 11:51:58.719184 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5623 11:51:58.722457 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5624 11:51:58.728724 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5625 11:51:58.731863 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5626 11:51:58.735274 0 14 28 | B1->B0 | 2f2f 2f2f | 1 1 | (1 0) (1 1)
5627 11:51:58.742017 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 11:51:58.745351 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 11:51:58.749008 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5630 11:51:58.755567 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5631 11:51:58.758834 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5632 11:51:58.762048 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5633 11:51:58.768462 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5634 11:51:58.771694 0 15 28 | B1->B0 | 2929 2e2e | 0 0 | (0 0) (0 0)
5635 11:51:58.775151 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (1 1)
5636 11:51:58.781739 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 11:51:58.785207 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 11:51:58.788832 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5639 11:51:58.795105 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5640 11:51:58.798265 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5641 11:51:58.801758 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5642 11:51:58.804875 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5643 11:51:58.811586 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5644 11:51:58.815197 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 11:51:58.818411 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 11:51:58.824897 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 11:51:58.828671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 11:51:58.831819 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 11:51:58.838673 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 11:51:58.841536 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 11:51:58.845179 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:51:58.851859 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:51:58.854931 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:51:58.858210 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:51:58.864702 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:51:58.868215 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:51:58.871493 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:51:58.878185 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5659 11:51:58.881354 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5660 11:51:58.884549 Total UI for P1: 0, mck2ui 16
5661 11:51:58.887877 best dqsien dly found for B1: ( 1, 2, 28)
5662 11:51:58.891240 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5663 11:51:58.894529 Total UI for P1: 0, mck2ui 16
5664 11:51:58.898009 best dqsien dly found for B0: ( 1, 2, 30)
5665 11:51:58.901119 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5666 11:51:58.904701 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5667 11:51:58.904783
5668 11:51:58.911268 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5669 11:51:58.914636 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5670 11:51:58.914719 [Gating] SW calibration Done
5671 11:51:58.917728 ==
5672 11:51:58.921220 Dram Type= 6, Freq= 0, CH_1, rank 0
5673 11:51:58.924624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5674 11:51:58.924707 ==
5675 11:51:58.924772 RX Vref Scan: 0
5676 11:51:58.924833
5677 11:51:58.927875 RX Vref 0 -> 0, step: 1
5678 11:51:58.927957
5679 11:51:58.930970 RX Delay -80 -> 252, step: 8
5680 11:51:58.934839 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5681 11:51:58.937887 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5682 11:51:58.941100 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5683 11:51:58.947717 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5684 11:51:58.950901 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5685 11:51:58.954489 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5686 11:51:58.957778 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5687 11:51:58.960950 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5688 11:51:58.964191 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5689 11:51:58.970797 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5690 11:51:58.974390 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5691 11:51:58.977510 iDelay=208, Bit 11, Center 79 (-24 ~ 183) 208
5692 11:51:58.980759 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5693 11:51:58.984018 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5694 11:51:58.990810 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5695 11:51:58.994337 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5696 11:51:58.994422 ==
5697 11:51:58.997654 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 11:51:59.000908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 11:51:59.000992 ==
5700 11:51:59.004186 DQS Delay:
5701 11:51:59.004307 DQS0 = 0, DQS1 = 0
5702 11:51:59.004373 DQM Delay:
5703 11:51:59.007398 DQM0 = 94, DQM1 = 86
5704 11:51:59.007479 DQ Delay:
5705 11:51:59.011055 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =91
5706 11:51:59.014465 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5707 11:51:59.017631 DQ8 =75, DQ9 =75, DQ10 =87, DQ11 =79
5708 11:51:59.020863 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5709 11:51:59.020944
5710 11:51:59.021008
5711 11:51:59.021067 ==
5712 11:51:59.024017 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:51:59.030737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:51:59.030819 ==
5715 11:51:59.030884
5716 11:51:59.030945
5717 11:51:59.031004 TX Vref Scan disable
5718 11:51:59.034420 == TX Byte 0 ==
5719 11:51:59.037637 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5720 11:51:59.040841 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5721 11:51:59.044208 == TX Byte 1 ==
5722 11:51:59.047782 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5723 11:51:59.050846 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5724 11:51:59.054194 ==
5725 11:51:59.057379 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 11:51:59.060632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 11:51:59.060720 ==
5728 11:51:59.060793
5729 11:51:59.060861
5730 11:51:59.064283 TX Vref Scan disable
5731 11:51:59.064415 == TX Byte 0 ==
5732 11:51:59.070683 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5733 11:51:59.073815 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5734 11:51:59.073925 == TX Byte 1 ==
5735 11:51:59.080440 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5736 11:51:59.083931 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5737 11:51:59.084085
5738 11:51:59.084268 [DATLAT]
5739 11:51:59.087661 Freq=933, CH1 RK0
5740 11:51:59.087831
5741 11:51:59.087967 DATLAT Default: 0xd
5742 11:51:59.090703 0, 0xFFFF, sum = 0
5743 11:51:59.090915 1, 0xFFFF, sum = 0
5744 11:51:59.094002 2, 0xFFFF, sum = 0
5745 11:51:59.094195 3, 0xFFFF, sum = 0
5746 11:51:59.097986 4, 0xFFFF, sum = 0
5747 11:51:59.098214 5, 0xFFFF, sum = 0
5748 11:51:59.100900 6, 0xFFFF, sum = 0
5749 11:51:59.101130 7, 0xFFFF, sum = 0
5750 11:51:59.104482 8, 0xFFFF, sum = 0
5751 11:51:59.107448 9, 0xFFFF, sum = 0
5752 11:51:59.107743 10, 0x0, sum = 1
5753 11:51:59.108010 11, 0x0, sum = 2
5754 11:51:59.110597 12, 0x0, sum = 3
5755 11:51:59.110969 13, 0x0, sum = 4
5756 11:51:59.113965 best_step = 11
5757 11:51:59.114364
5758 11:51:59.114647 ==
5759 11:51:59.117315 Dram Type= 6, Freq= 0, CH_1, rank 0
5760 11:51:59.120859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5761 11:51:59.121220 ==
5762 11:51:59.124162 RX Vref Scan: 1
5763 11:51:59.124557
5764 11:51:59.124841 RX Vref 0 -> 0, step: 1
5765 11:51:59.125105
5766 11:51:59.127415 RX Delay -69 -> 252, step: 4
5767 11:51:59.127774
5768 11:51:59.130843 Set Vref, RX VrefLevel [Byte0]: 54
5769 11:51:59.134505 [Byte1]: 55
5770 11:51:59.138145
5771 11:51:59.138606 Final RX Vref Byte 0 = 54 to rank0
5772 11:51:59.141663 Final RX Vref Byte 1 = 55 to rank0
5773 11:51:59.144968 Final RX Vref Byte 0 = 54 to rank1
5774 11:51:59.148387 Final RX Vref Byte 1 = 55 to rank1==
5775 11:51:59.151281 Dram Type= 6, Freq= 0, CH_1, rank 0
5776 11:51:59.158197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5777 11:51:59.158385 ==
5778 11:51:59.158519 DQS Delay:
5779 11:51:59.158642 DQS0 = 0, DQS1 = 0
5780 11:51:59.161437 DQM Delay:
5781 11:51:59.161604 DQM0 = 96, DQM1 = 88
5782 11:51:59.164835 DQ Delay:
5783 11:51:59.168025 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =92
5784 11:51:59.171174 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =92
5785 11:51:59.174411 DQ8 =78, DQ9 =82, DQ10 =86, DQ11 =82
5786 11:51:59.178156 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5787 11:51:59.178261
5788 11:51:59.178342
5789 11:51:59.184672 [DQSOSCAuto] RK0, (LSB)MR18= 0x60e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 420 ps
5790 11:51:59.187948 CH1 RK0: MR19=505, MR18=60E
5791 11:51:59.194473 CH1_RK0: MR19=0x505, MR18=0x60E, DQSOSC=417, MR23=63, INC=62, DEC=41
5792 11:51:59.194585
5793 11:51:59.197579 ----->DramcWriteLeveling(PI) begin...
5794 11:51:59.197680 ==
5795 11:51:59.200811 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 11:51:59.204129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 11:51:59.204290 ==
5798 11:51:59.207873 Write leveling (Byte 0): 25 => 25
5799 11:51:59.211085 Write leveling (Byte 1): 27 => 27
5800 11:51:59.214509 DramcWriteLeveling(PI) end<-----
5801 11:51:59.214584
5802 11:51:59.214645 ==
5803 11:51:59.217364 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 11:51:59.220909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 11:51:59.220986 ==
5806 11:51:59.223976 [Gating] SW mode calibration
5807 11:51:59.230555 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5808 11:51:59.237218 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5809 11:51:59.240431 0 14 0 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
5810 11:51:59.247546 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5811 11:51:59.250581 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5812 11:51:59.254085 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5813 11:51:59.260726 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5814 11:51:59.263860 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5815 11:51:59.267170 0 14 24 | B1->B0 | 3333 2d2d | 1 1 | (1 0) (1 0)
5816 11:51:59.273758 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
5817 11:51:59.277233 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5818 11:51:59.280419 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5819 11:51:59.286853 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5820 11:51:59.290141 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5821 11:51:59.293461 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5822 11:51:59.296858 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5823 11:51:59.303638 0 15 24 | B1->B0 | 2a2a 3535 | 0 0 | (0 0) (0 0)
5824 11:51:59.307079 0 15 28 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
5825 11:51:59.310137 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5826 11:51:59.317075 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5827 11:51:59.320408 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5828 11:51:59.323345 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5829 11:51:59.330562 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5830 11:51:59.333590 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5831 11:51:59.336977 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5832 11:51:59.343167 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5833 11:51:59.346885 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 11:51:59.350163 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 11:51:59.356489 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 11:51:59.360364 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 11:51:59.363357 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 11:51:59.369710 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 11:51:59.373390 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 11:51:59.376711 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 11:51:59.383227 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 11:51:59.386747 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:51:59.389918 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:51:59.396834 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:51:59.399697 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:51:59.403667 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5847 11:51:59.409924 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5848 11:51:59.410029 Total UI for P1: 0, mck2ui 16
5849 11:51:59.416473 best dqsien dly found for B0: ( 1, 2, 20)
5850 11:51:59.419969 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5851 11:51:59.422990 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5852 11:51:59.426134 Total UI for P1: 0, mck2ui 16
5853 11:51:59.429790 best dqsien dly found for B1: ( 1, 2, 26)
5854 11:51:59.433214 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5855 11:51:59.436059 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5856 11:51:59.436160
5857 11:51:59.439752 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5858 11:51:59.446089 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5859 11:51:59.446165 [Gating] SW calibration Done
5860 11:51:59.446228 ==
5861 11:51:59.449931 Dram Type= 6, Freq= 0, CH_1, rank 1
5862 11:51:59.456301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5863 11:51:59.456379 ==
5864 11:51:59.456445 RX Vref Scan: 0
5865 11:51:59.456503
5866 11:51:59.459643 RX Vref 0 -> 0, step: 1
5867 11:51:59.459720
5868 11:51:59.462555 RX Delay -80 -> 252, step: 8
5869 11:51:59.466487 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5870 11:51:59.469204 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5871 11:51:59.472642 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5872 11:51:59.479506 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5873 11:51:59.482482 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5874 11:51:59.485855 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5875 11:51:59.489248 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5876 11:51:59.492622 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5877 11:51:59.495892 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5878 11:51:59.502856 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5879 11:51:59.505719 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5880 11:51:59.509261 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5881 11:51:59.512711 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5882 11:51:59.515785 iDelay=208, Bit 13, Center 95 (-8 ~ 199) 208
5883 11:51:59.522428 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5884 11:51:59.525678 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5885 11:51:59.525772 ==
5886 11:51:59.530075 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 11:51:59.532240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 11:51:59.532330 ==
5889 11:51:59.532393 DQS Delay:
5890 11:51:59.535605 DQS0 = 0, DQS1 = 0
5891 11:51:59.535681 DQM Delay:
5892 11:51:59.539152 DQM0 = 93, DQM1 = 89
5893 11:51:59.539244 DQ Delay:
5894 11:51:59.542304 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5895 11:51:59.545566 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5896 11:51:59.548943 DQ8 =75, DQ9 =75, DQ10 =91, DQ11 =83
5897 11:51:59.552370 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =99
5898 11:51:59.552444
5899 11:51:59.552504
5900 11:51:59.552562 ==
5901 11:51:59.555619 Dram Type= 6, Freq= 0, CH_1, rank 1
5902 11:51:59.562277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5903 11:51:59.562358 ==
5904 11:51:59.562423
5905 11:51:59.562484
5906 11:51:59.562543 TX Vref Scan disable
5907 11:51:59.565413 == TX Byte 0 ==
5908 11:51:59.569144 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5909 11:51:59.572280 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5910 11:51:59.575665 == TX Byte 1 ==
5911 11:51:59.578662 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5912 11:51:59.582490 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5913 11:51:59.585575 ==
5914 11:51:59.588881 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 11:51:59.592156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 11:51:59.592330 ==
5917 11:51:59.592452
5918 11:51:59.592562
5919 11:51:59.595466 TX Vref Scan disable
5920 11:51:59.595615 == TX Byte 0 ==
5921 11:51:59.602228 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5922 11:51:59.605441 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5923 11:51:59.605640 == TX Byte 1 ==
5924 11:51:59.612479 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5925 11:51:59.615869 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5926 11:51:59.616309
5927 11:51:59.616772 [DATLAT]
5928 11:51:59.619203 Freq=933, CH1 RK1
5929 11:51:59.619583
5930 11:51:59.619881 DATLAT Default: 0xb
5931 11:51:59.622935 0, 0xFFFF, sum = 0
5932 11:51:59.623321 1, 0xFFFF, sum = 0
5933 11:51:59.625839 2, 0xFFFF, sum = 0
5934 11:51:59.626284 3, 0xFFFF, sum = 0
5935 11:51:59.628929 4, 0xFFFF, sum = 0
5936 11:51:59.629412 5, 0xFFFF, sum = 0
5937 11:51:59.632286 6, 0xFFFF, sum = 0
5938 11:51:59.632802 7, 0xFFFF, sum = 0
5939 11:51:59.635698 8, 0xFFFF, sum = 0
5940 11:51:59.636162 9, 0xFFFF, sum = 0
5941 11:51:59.639255 10, 0x0, sum = 1
5942 11:51:59.639745 11, 0x0, sum = 2
5943 11:51:59.642270 12, 0x0, sum = 3
5944 11:51:59.642665 13, 0x0, sum = 4
5945 11:51:59.645826 best_step = 11
5946 11:51:59.646210
5947 11:51:59.646514 ==
5948 11:51:59.649014 Dram Type= 6, Freq= 0, CH_1, rank 1
5949 11:51:59.652351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5950 11:51:59.652742 ==
5951 11:51:59.655711 RX Vref Scan: 0
5952 11:51:59.656097
5953 11:51:59.656507 RX Vref 0 -> 0, step: 1
5954 11:51:59.656807
5955 11:51:59.658860 RX Delay -69 -> 252, step: 4
5956 11:51:59.666330 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5957 11:51:59.669759 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5958 11:51:59.673111 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5959 11:51:59.676461 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5960 11:51:59.679642 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5961 11:51:59.686536 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5962 11:51:59.689616 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5963 11:51:59.693021 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5964 11:51:59.696241 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5965 11:51:59.699570 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5966 11:51:59.702934 iDelay=203, Bit 10, Center 92 (-5 ~ 190) 196
5967 11:51:59.709555 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5968 11:51:59.713135 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5969 11:51:59.716407 iDelay=203, Bit 13, Center 100 (7 ~ 194) 188
5970 11:51:59.719696 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5971 11:51:59.722975 iDelay=203, Bit 15, Center 100 (7 ~ 194) 188
5972 11:51:59.723391 ==
5973 11:51:59.726277 Dram Type= 6, Freq= 0, CH_1, rank 1
5974 11:51:59.732783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5975 11:51:59.733201 ==
5976 11:51:59.733531 DQS Delay:
5977 11:51:59.736277 DQS0 = 0, DQS1 = 0
5978 11:51:59.736701 DQM Delay:
5979 11:51:59.737032 DQM0 = 92, DQM1 = 91
5980 11:51:59.739610 DQ Delay:
5981 11:51:59.743106 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5982 11:51:59.746097 DQ4 =90, DQ5 =102, DQ6 =104, DQ7 =88
5983 11:51:59.749412 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =84
5984 11:51:59.752835 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =100
5985 11:51:59.753294
5986 11:51:59.753625
5987 11:51:59.759081 [DQSOSCAuto] RK1, (LSB)MR18= 0x1428, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 415 ps
5988 11:51:59.762753 CH1 RK1: MR19=505, MR18=1428
5989 11:51:59.769055 CH1_RK1: MR19=0x505, MR18=0x1428, DQSOSC=409, MR23=63, INC=64, DEC=43
5990 11:51:59.772422 [RxdqsGatingPostProcess] freq 933
5991 11:51:59.779133 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5992 11:51:59.779550 best DQS0 dly(2T, 0.5T) = (0, 10)
5993 11:51:59.782445 best DQS1 dly(2T, 0.5T) = (0, 10)
5994 11:51:59.785802 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5995 11:51:59.789286 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5996 11:51:59.792727 best DQS0 dly(2T, 0.5T) = (0, 10)
5997 11:51:59.795650 best DQS1 dly(2T, 0.5T) = (0, 10)
5998 11:51:59.799002 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5999 11:51:59.802351 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6000 11:51:59.805538 Pre-setting of DQS Precalculation
6001 11:51:59.812650 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6002 11:51:59.819052 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6003 11:51:59.825795 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6004 11:51:59.826212
6005 11:51:59.826538
6006 11:51:59.828966 [Calibration Summary] 1866 Mbps
6007 11:51:59.829385 CH 0, Rank 0
6008 11:51:59.832265 SW Impedance : PASS
6009 11:51:59.832681 DUTY Scan : NO K
6010 11:51:59.835353 ZQ Calibration : PASS
6011 11:51:59.838786 Jitter Meter : NO K
6012 11:51:59.839202 CBT Training : PASS
6013 11:51:59.842154 Write leveling : PASS
6014 11:51:59.845603 RX DQS gating : PASS
6015 11:51:59.846018 RX DQ/DQS(RDDQC) : PASS
6016 11:51:59.849081 TX DQ/DQS : PASS
6017 11:51:59.852452 RX DATLAT : PASS
6018 11:51:59.852868 RX DQ/DQS(Engine): PASS
6019 11:51:59.855438 TX OE : NO K
6020 11:51:59.855851 All Pass.
6021 11:51:59.856179
6022 11:51:59.858775 CH 0, Rank 1
6023 11:51:59.859187 SW Impedance : PASS
6024 11:51:59.862136 DUTY Scan : NO K
6025 11:51:59.865710 ZQ Calibration : PASS
6026 11:51:59.866130 Jitter Meter : NO K
6027 11:51:59.869028 CBT Training : PASS
6028 11:51:59.872148 Write leveling : PASS
6029 11:51:59.872598 RX DQS gating : PASS
6030 11:51:59.875742 RX DQ/DQS(RDDQC) : PASS
6031 11:51:59.876154 TX DQ/DQS : PASS
6032 11:51:59.878624 RX DATLAT : PASS
6033 11:51:59.882065 RX DQ/DQS(Engine): PASS
6034 11:51:59.882480 TX OE : NO K
6035 11:51:59.885370 All Pass.
6036 11:51:59.885787
6037 11:51:59.886115 CH 1, Rank 0
6038 11:51:59.888845 SW Impedance : PASS
6039 11:51:59.889346 DUTY Scan : NO K
6040 11:51:59.892115 ZQ Calibration : PASS
6041 11:51:59.895256 Jitter Meter : NO K
6042 11:51:59.895674 CBT Training : PASS
6043 11:51:59.898144 Write leveling : PASS
6044 11:51:59.901832 RX DQS gating : PASS
6045 11:51:59.901914 RX DQ/DQS(RDDQC) : PASS
6046 11:51:59.905040 TX DQ/DQS : PASS
6047 11:51:59.908427 RX DATLAT : PASS
6048 11:51:59.908508 RX DQ/DQS(Engine): PASS
6049 11:51:59.911638 TX OE : NO K
6050 11:51:59.911719 All Pass.
6051 11:51:59.911783
6052 11:51:59.914936 CH 1, Rank 1
6053 11:51:59.915017 SW Impedance : PASS
6054 11:51:59.918233 DUTY Scan : NO K
6055 11:51:59.921402 ZQ Calibration : PASS
6056 11:51:59.921484 Jitter Meter : NO K
6057 11:51:59.924656 CBT Training : PASS
6058 11:51:59.928483 Write leveling : PASS
6059 11:51:59.928563 RX DQS gating : PASS
6060 11:51:59.931905 RX DQ/DQS(RDDQC) : PASS
6061 11:51:59.931991 TX DQ/DQS : PASS
6062 11:51:59.935094 RX DATLAT : PASS
6063 11:51:59.938522 RX DQ/DQS(Engine): PASS
6064 11:51:59.938603 TX OE : NO K
6065 11:51:59.941653 All Pass.
6066 11:51:59.941734
6067 11:51:59.941798 DramC Write-DBI off
6068 11:51:59.945164 PER_BANK_REFRESH: Hybrid Mode
6069 11:51:59.948079 TX_TRACKING: ON
6070 11:51:59.954824 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6071 11:51:59.958053 [FAST_K] Save calibration result to emmc
6072 11:51:59.961251 dramc_set_vcore_voltage set vcore to 650000
6073 11:51:59.964688 Read voltage for 400, 6
6074 11:51:59.964769 Vio18 = 0
6075 11:51:59.968021 Vcore = 650000
6076 11:51:59.968101 Vdram = 0
6077 11:51:59.968165 Vddq = 0
6078 11:51:59.971520 Vmddr = 0
6079 11:51:59.974506 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6080 11:51:59.981374 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6081 11:51:59.981455 MEM_TYPE=3, freq_sel=20
6082 11:51:59.984554 sv_algorithm_assistance_LP4_800
6083 11:51:59.991198 ============ PULL DRAM RESETB DOWN ============
6084 11:51:59.994559 ========== PULL DRAM RESETB DOWN end =========
6085 11:51:59.998069 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6086 11:52:00.001375 ===================================
6087 11:52:00.004420 LPDDR4 DRAM CONFIGURATION
6088 11:52:00.007765 ===================================
6089 11:52:00.010954 EX_ROW_EN[0] = 0x0
6090 11:52:00.011038 EX_ROW_EN[1] = 0x0
6091 11:52:00.014246 LP4Y_EN = 0x0
6092 11:52:00.014327 WORK_FSP = 0x0
6093 11:52:00.017608 WL = 0x2
6094 11:52:00.017688 RL = 0x2
6095 11:52:00.021087 BL = 0x2
6096 11:52:00.021167 RPST = 0x0
6097 11:52:00.024660 RD_PRE = 0x0
6098 11:52:00.024741 WR_PRE = 0x1
6099 11:52:00.027872 WR_PST = 0x0
6100 11:52:00.027953 DBI_WR = 0x0
6101 11:52:00.031155 DBI_RD = 0x0
6102 11:52:00.031235 OTF = 0x1
6103 11:52:00.034555 ===================================
6104 11:52:00.037803 ===================================
6105 11:52:00.040666 ANA top config
6106 11:52:00.044207 ===================================
6107 11:52:00.047717 DLL_ASYNC_EN = 0
6108 11:52:00.047797 ALL_SLAVE_EN = 1
6109 11:52:00.050978 NEW_RANK_MODE = 1
6110 11:52:00.054081 DLL_IDLE_MODE = 1
6111 11:52:00.057631 LP45_APHY_COMB_EN = 1
6112 11:52:00.057712 TX_ODT_DIS = 1
6113 11:52:00.060963 NEW_8X_MODE = 1
6114 11:52:00.064193 ===================================
6115 11:52:00.067553 ===================================
6116 11:52:00.070883 data_rate = 800
6117 11:52:00.074478 CKR = 1
6118 11:52:00.077451 DQ_P2S_RATIO = 4
6119 11:52:00.080930 ===================================
6120 11:52:00.084032 CA_P2S_RATIO = 4
6121 11:52:00.084112 DQ_CA_OPEN = 0
6122 11:52:00.087988 DQ_SEMI_OPEN = 1
6123 11:52:00.090712 CA_SEMI_OPEN = 1
6124 11:52:00.094508 CA_FULL_RATE = 0
6125 11:52:00.097611 DQ_CKDIV4_EN = 0
6126 11:52:00.097692 CA_CKDIV4_EN = 1
6127 11:52:00.101147 CA_PREDIV_EN = 0
6128 11:52:00.104473 PH8_DLY = 0
6129 11:52:00.107476 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6130 11:52:00.110850 DQ_AAMCK_DIV = 0
6131 11:52:00.114425 CA_AAMCK_DIV = 0
6132 11:52:00.114506 CA_ADMCK_DIV = 4
6133 11:52:00.117634 DQ_TRACK_CA_EN = 0
6134 11:52:00.120725 CA_PICK = 800
6135 11:52:00.124130 CA_MCKIO = 400
6136 11:52:00.127525 MCKIO_SEMI = 400
6137 11:52:00.130623 PLL_FREQ = 3016
6138 11:52:00.134240 DQ_UI_PI_RATIO = 32
6139 11:52:00.137441 CA_UI_PI_RATIO = 32
6140 11:52:00.140532 ===================================
6141 11:52:00.143899 ===================================
6142 11:52:00.143980 memory_type:LPDDR4
6143 11:52:00.147674 GP_NUM : 10
6144 11:52:00.150867 SRAM_EN : 1
6145 11:52:00.150948 MD32_EN : 0
6146 11:52:00.154140 ===================================
6147 11:52:00.157448 [ANA_INIT] >>>>>>>>>>>>>>
6148 11:52:00.160676 <<<<<< [CONFIGURE PHASE]: ANA_TX
6149 11:52:00.164316 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6150 11:52:00.167549 ===================================
6151 11:52:00.170951 data_rate = 800,PCW = 0X7400
6152 11:52:00.171031 ===================================
6153 11:52:00.177519 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6154 11:52:00.180776 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6155 11:52:00.193694 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6156 11:52:00.197000 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6157 11:52:00.200835 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6158 11:52:00.204156 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6159 11:52:00.206938 [ANA_INIT] flow start
6160 11:52:00.207018 [ANA_INIT] PLL >>>>>>>>
6161 11:52:00.210763 [ANA_INIT] PLL <<<<<<<<
6162 11:52:00.213950 [ANA_INIT] MIDPI >>>>>>>>
6163 11:52:00.217397 [ANA_INIT] MIDPI <<<<<<<<
6164 11:52:00.217478 [ANA_INIT] DLL >>>>>>>>
6165 11:52:00.220660 [ANA_INIT] flow end
6166 11:52:00.224045 ============ LP4 DIFF to SE enter ============
6167 11:52:00.227154 ============ LP4 DIFF to SE exit ============
6168 11:52:00.230289 [ANA_INIT] <<<<<<<<<<<<<
6169 11:52:00.233705 [Flow] Enable top DCM control >>>>>
6170 11:52:00.236869 [Flow] Enable top DCM control <<<<<
6171 11:52:00.240253 Enable DLL master slave shuffle
6172 11:52:00.246751 ==============================================================
6173 11:52:00.246833 Gating Mode config
6174 11:52:00.253463 ==============================================================
6175 11:52:00.253544 Config description:
6176 11:52:00.263619 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6177 11:52:00.270201 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6178 11:52:00.276723 SELPH_MODE 0: By rank 1: By Phase
6179 11:52:00.280151 ==============================================================
6180 11:52:00.283453 GAT_TRACK_EN = 0
6181 11:52:00.286651 RX_GATING_MODE = 2
6182 11:52:00.290054 RX_GATING_TRACK_MODE = 2
6183 11:52:00.293136 SELPH_MODE = 1
6184 11:52:00.296625 PICG_EARLY_EN = 1
6185 11:52:00.300055 VALID_LAT_VALUE = 1
6186 11:52:00.303226 ==============================================================
6187 11:52:00.309937 Enter into Gating configuration >>>>
6188 11:52:00.312668 Exit from Gating configuration <<<<
6189 11:52:00.312748 Enter into DVFS_PRE_config >>>>>
6190 11:52:00.326266 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6191 11:52:00.329648 Exit from DVFS_PRE_config <<<<<
6192 11:52:00.332794 Enter into PICG configuration >>>>
6193 11:52:00.336070 Exit from PICG configuration <<<<
6194 11:52:00.336150 [RX_INPUT] configuration >>>>>
6195 11:52:00.339415 [RX_INPUT] configuration <<<<<
6196 11:52:00.346070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6197 11:52:00.352667 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6198 11:52:00.356192 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6199 11:52:00.362399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6200 11:52:00.369198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6201 11:52:00.375817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6202 11:52:00.379076 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6203 11:52:00.382541 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6204 11:52:00.389056 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6205 11:52:00.392370 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6206 11:52:00.395654 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6207 11:52:00.402094 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6208 11:52:00.405378 ===================================
6209 11:52:00.405459 LPDDR4 DRAM CONFIGURATION
6210 11:52:00.409115 ===================================
6211 11:52:00.412252 EX_ROW_EN[0] = 0x0
6212 11:52:00.412336 EX_ROW_EN[1] = 0x0
6213 11:52:00.415405 LP4Y_EN = 0x0
6214 11:52:00.415485 WORK_FSP = 0x0
6215 11:52:00.418812 WL = 0x2
6216 11:52:00.418893 RL = 0x2
6217 11:52:00.422015 BL = 0x2
6218 11:52:00.425700 RPST = 0x0
6219 11:52:00.425781 RD_PRE = 0x0
6220 11:52:00.428955 WR_PRE = 0x1
6221 11:52:00.429036 WR_PST = 0x0
6222 11:52:00.432022 DBI_WR = 0x0
6223 11:52:00.432103 DBI_RD = 0x0
6224 11:52:00.435263 OTF = 0x1
6225 11:52:00.438862 ===================================
6226 11:52:00.442021 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6227 11:52:00.445415 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6228 11:52:00.448709 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6229 11:52:00.451970 ===================================
6230 11:52:00.455332 LPDDR4 DRAM CONFIGURATION
6231 11:52:00.458670 ===================================
6232 11:52:00.461920 EX_ROW_EN[0] = 0x10
6233 11:52:00.462000 EX_ROW_EN[1] = 0x0
6234 11:52:00.465579 LP4Y_EN = 0x0
6235 11:52:00.465658 WORK_FSP = 0x0
6236 11:52:00.468529 WL = 0x2
6237 11:52:00.468610 RL = 0x2
6238 11:52:00.471738 BL = 0x2
6239 11:52:00.471818 RPST = 0x0
6240 11:52:00.475053 RD_PRE = 0x0
6241 11:52:00.478964 WR_PRE = 0x1
6242 11:52:00.479045 WR_PST = 0x0
6243 11:52:00.481864 DBI_WR = 0x0
6244 11:52:00.481944 DBI_RD = 0x0
6245 11:52:00.485208 OTF = 0x1
6246 11:52:00.488228 ===================================
6247 11:52:00.491422 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6248 11:52:00.496982 nWR fixed to 30
6249 11:52:00.500335 [ModeRegInit_LP4] CH0 RK0
6250 11:52:00.500415 [ModeRegInit_LP4] CH0 RK1
6251 11:52:00.503655 [ModeRegInit_LP4] CH1 RK0
6252 11:52:00.506784 [ModeRegInit_LP4] CH1 RK1
6253 11:52:00.506865 match AC timing 19
6254 11:52:00.513787 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6255 11:52:00.517159 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6256 11:52:00.520404 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6257 11:52:00.527123 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6258 11:52:00.530350 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6259 11:52:00.530431 ==
6260 11:52:00.533800 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 11:52:00.536701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 11:52:00.536783 ==
6263 11:52:00.543538 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6264 11:52:00.550234 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6265 11:52:00.553388 [CA 0] Center 36 (8~64) winsize 57
6266 11:52:00.556770 [CA 1] Center 36 (8~64) winsize 57
6267 11:52:00.560002 [CA 2] Center 36 (8~64) winsize 57
6268 11:52:00.563536 [CA 3] Center 36 (8~64) winsize 57
6269 11:52:00.563607 [CA 4] Center 36 (8~64) winsize 57
6270 11:52:00.566650 [CA 5] Center 36 (8~64) winsize 57
6271 11:52:00.566747
6272 11:52:00.573188 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6273 11:52:00.573266
6274 11:52:00.576359 [CATrainingPosCal] consider 1 rank data
6275 11:52:00.579717 u2DelayCellTimex100 = 270/100 ps
6276 11:52:00.583536 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:52:00.586564 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:52:00.589811 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:52:00.593334 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6280 11:52:00.596261 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6281 11:52:00.599679 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6282 11:52:00.599776
6283 11:52:00.603003 CA PerBit enable=1, Macro0, CA PI delay=36
6284 11:52:00.603080
6285 11:52:00.606257 [CBTSetCACLKResult] CA Dly = 36
6286 11:52:00.609471 CS Dly: 1 (0~32)
6287 11:52:00.609544 ==
6288 11:52:00.613025 Dram Type= 6, Freq= 0, CH_0, rank 1
6289 11:52:00.616431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:52:00.616513 ==
6291 11:52:00.622931 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6292 11:52:00.629524 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6293 11:52:00.633273 [CA 0] Center 36 (8~64) winsize 57
6294 11:52:00.633347 [CA 1] Center 36 (8~64) winsize 57
6295 11:52:00.636148 [CA 2] Center 36 (8~64) winsize 57
6296 11:52:00.639593 [CA 3] Center 36 (8~64) winsize 57
6297 11:52:00.643161 [CA 4] Center 36 (8~64) winsize 57
6298 11:52:00.646579 [CA 5] Center 36 (8~64) winsize 57
6299 11:52:00.646676
6300 11:52:00.649544 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6301 11:52:00.649619
6302 11:52:00.653022 [CATrainingPosCal] consider 2 rank data
6303 11:52:00.656163 u2DelayCellTimex100 = 270/100 ps
6304 11:52:00.659505 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6305 11:52:00.662798 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6306 11:52:00.670008 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6307 11:52:00.672609 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6308 11:52:00.676523 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 11:52:00.679274 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 11:52:00.679354
6311 11:52:00.682948 CA PerBit enable=1, Macro0, CA PI delay=36
6312 11:52:00.683031
6313 11:52:00.686025 [CBTSetCACLKResult] CA Dly = 36
6314 11:52:00.686106 CS Dly: 1 (0~32)
6315 11:52:00.686170
6316 11:52:00.689804 ----->DramcWriteLeveling(PI) begin...
6317 11:52:00.692864 ==
6318 11:52:00.696488 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 11:52:00.699426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 11:52:00.699533 ==
6321 11:52:00.702563 Write leveling (Byte 0): 40 => 8
6322 11:52:00.706187 Write leveling (Byte 1): 40 => 8
6323 11:52:00.709519 DramcWriteLeveling(PI) end<-----
6324 11:52:00.709621
6325 11:52:00.709711 ==
6326 11:52:00.712221 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 11:52:00.715851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 11:52:00.715951 ==
6329 11:52:00.719122 [Gating] SW mode calibration
6330 11:52:00.725852 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6331 11:52:00.732405 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6332 11:52:00.735643 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6333 11:52:00.738987 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6334 11:52:00.745492 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 11:52:00.749215 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6336 11:52:00.752620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6337 11:52:00.758918 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6338 11:52:00.762291 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6339 11:52:00.765706 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6340 11:52:00.769120 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6341 11:52:00.772709 Total UI for P1: 0, mck2ui 16
6342 11:52:00.775756 best dqsien dly found for B0: ( 0, 14, 24)
6343 11:52:00.779173 Total UI for P1: 0, mck2ui 16
6344 11:52:00.782497 best dqsien dly found for B1: ( 0, 14, 24)
6345 11:52:00.785782 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6346 11:52:00.792173 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6347 11:52:00.792654
6348 11:52:00.795519 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6349 11:52:00.798897 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6350 11:52:00.802514 [Gating] SW calibration Done
6351 11:52:00.802924 ==
6352 11:52:00.805694 Dram Type= 6, Freq= 0, CH_0, rank 0
6353 11:52:00.808796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6354 11:52:00.809212 ==
6355 11:52:00.812162 RX Vref Scan: 0
6356 11:52:00.812622
6357 11:52:00.812949 RX Vref 0 -> 0, step: 1
6358 11:52:00.813257
6359 11:52:00.815338 RX Delay -410 -> 252, step: 16
6360 11:52:00.818605 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6361 11:52:00.825120 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6362 11:52:00.828495 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6363 11:52:00.831788 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6364 11:52:00.835088 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6365 11:52:00.841867 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6366 11:52:00.845123 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6367 11:52:00.848208 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6368 11:52:00.852001 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6369 11:52:00.858511 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6370 11:52:00.861802 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6371 11:52:00.865035 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6372 11:52:00.868403 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6373 11:52:00.874826 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6374 11:52:00.878474 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6375 11:52:00.881640 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6376 11:52:00.881721 ==
6377 11:52:00.885273 Dram Type= 6, Freq= 0, CH_0, rank 0
6378 11:52:00.892010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6379 11:52:00.892091 ==
6380 11:52:00.892154 DQS Delay:
6381 11:52:00.895237 DQS0 = 59, DQS1 = 59
6382 11:52:00.895317 DQM Delay:
6383 11:52:00.895380 DQM0 = 18, DQM1 = 10
6384 11:52:00.898307 DQ Delay:
6385 11:52:00.901540 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6386 11:52:00.905328 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6387 11:52:00.905414 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6388 11:52:00.911482 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6389 11:52:00.911582
6390 11:52:00.911660
6391 11:52:00.911733 ==
6392 11:52:00.914924 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 11:52:00.918547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 11:52:00.918657 ==
6395 11:52:00.918744
6396 11:52:00.918824
6397 11:52:00.921510 TX Vref Scan disable
6398 11:52:00.921630 == TX Byte 0 ==
6399 11:52:00.924943 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6400 11:52:00.931292 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6401 11:52:00.931426 == TX Byte 1 ==
6402 11:52:00.935165 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6403 11:52:00.941155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6404 11:52:00.941327 ==
6405 11:52:00.944645 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 11:52:00.947913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 11:52:00.948151 ==
6408 11:52:00.948389
6409 11:52:00.948568
6410 11:52:00.951864 TX Vref Scan disable
6411 11:52:00.952157 == TX Byte 0 ==
6412 11:52:00.958295 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6413 11:52:00.961605 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6414 11:52:00.962096 == TX Byte 1 ==
6415 11:52:00.964846 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6416 11:52:00.971512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6417 11:52:00.971991
6418 11:52:00.972481 [DATLAT]
6419 11:52:00.974884 Freq=400, CH0 RK0
6420 11:52:00.975356
6421 11:52:00.975763 DATLAT Default: 0xf
6422 11:52:00.978116 0, 0xFFFF, sum = 0
6423 11:52:00.978590 1, 0xFFFF, sum = 0
6424 11:52:00.981851 2, 0xFFFF, sum = 0
6425 11:52:00.982375 3, 0xFFFF, sum = 0
6426 11:52:00.984795 4, 0xFFFF, sum = 0
6427 11:52:00.985353 5, 0xFFFF, sum = 0
6428 11:52:00.988232 6, 0xFFFF, sum = 0
6429 11:52:00.988757 7, 0xFFFF, sum = 0
6430 11:52:00.991725 8, 0xFFFF, sum = 0
6431 11:52:00.992252 9, 0xFFFF, sum = 0
6432 11:52:00.995077 10, 0xFFFF, sum = 0
6433 11:52:00.995606 11, 0xFFFF, sum = 0
6434 11:52:00.998302 12, 0xFFFF, sum = 0
6435 11:52:00.998855 13, 0x0, sum = 1
6436 11:52:01.001433 14, 0x0, sum = 2
6437 11:52:01.001853 15, 0x0, sum = 3
6438 11:52:01.004914 16, 0x0, sum = 4
6439 11:52:01.005337 best_step = 14
6440 11:52:01.005664
6441 11:52:01.005967 ==
6442 11:52:01.008323 Dram Type= 6, Freq= 0, CH_0, rank 0
6443 11:52:01.014671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6444 11:52:01.015226 ==
6445 11:52:01.015802 RX Vref Scan: 1
6446 11:52:01.016361
6447 11:52:01.018294 RX Vref 0 -> 0, step: 1
6448 11:52:01.018710
6449 11:52:01.021763 RX Delay -359 -> 252, step: 8
6450 11:52:01.022334
6451 11:52:01.024585 Set Vref, RX VrefLevel [Byte0]: 61
6452 11:52:01.028187 [Byte1]: 49
6453 11:52:01.028633
6454 11:52:01.031247 Final RX Vref Byte 0 = 61 to rank0
6455 11:52:01.034674 Final RX Vref Byte 1 = 49 to rank0
6456 11:52:01.038139 Final RX Vref Byte 0 = 61 to rank1
6457 11:52:01.041409 Final RX Vref Byte 1 = 49 to rank1==
6458 11:52:01.044666 Dram Type= 6, Freq= 0, CH_0, rank 0
6459 11:52:01.048075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6460 11:52:01.051304 ==
6461 11:52:01.051744 DQS Delay:
6462 11:52:01.052104 DQS0 = 60, DQS1 = 68
6463 11:52:01.054556 DQM Delay:
6464 11:52:01.054974 DQM0 = 15, DQM1 = 14
6465 11:52:01.058386 DQ Delay:
6466 11:52:01.061141 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6467 11:52:01.061561 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6468 11:52:01.064797 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6469 11:52:01.067907 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6470 11:52:01.068368
6471 11:52:01.071287
6472 11:52:01.077862 [DQSOSCAuto] RK0, (LSB)MR18= 0x8380, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6473 11:52:01.081761 CH0 RK0: MR19=C0C, MR18=8380
6474 11:52:01.088142 CH0_RK0: MR19=0xC0C, MR18=0x8380, DQSOSC=393, MR23=63, INC=382, DEC=254
6475 11:52:01.088618 ==
6476 11:52:01.091224 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 11:52:01.094765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 11:52:01.095185 ==
6479 11:52:01.098085 [Gating] SW mode calibration
6480 11:52:01.104798 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6481 11:52:01.111464 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6482 11:52:01.114742 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6483 11:52:01.117732 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6484 11:52:01.121597 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 11:52:01.128060 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6486 11:52:01.131301 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6487 11:52:01.134683 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6488 11:52:01.141351 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6489 11:52:01.144340 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6490 11:52:01.147659 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6491 11:52:01.151124 Total UI for P1: 0, mck2ui 16
6492 11:52:01.154313 best dqsien dly found for B0: ( 0, 14, 24)
6493 11:52:01.157712 Total UI for P1: 0, mck2ui 16
6494 11:52:01.161062 best dqsien dly found for B1: ( 0, 14, 24)
6495 11:52:01.164325 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6496 11:52:01.167720 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6497 11:52:01.171391
6498 11:52:01.174553 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6499 11:52:01.177862 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6500 11:52:01.181148 [Gating] SW calibration Done
6501 11:52:01.181564 ==
6502 11:52:01.184566 Dram Type= 6, Freq= 0, CH_0, rank 1
6503 11:52:01.187811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6504 11:52:01.188268 ==
6505 11:52:01.188608 RX Vref Scan: 0
6506 11:52:01.188918
6507 11:52:01.190900 RX Vref 0 -> 0, step: 1
6508 11:52:01.191344
6509 11:52:01.194156 RX Delay -410 -> 252, step: 16
6510 11:52:01.197488 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6511 11:52:01.204107 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6512 11:52:01.207368 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6513 11:52:01.210963 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6514 11:52:01.214022 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6515 11:52:01.220796 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6516 11:52:01.224447 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6517 11:52:01.227391 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6518 11:52:01.230747 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6519 11:52:01.237474 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6520 11:52:01.240874 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6521 11:52:01.244195 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6522 11:52:01.247127 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6523 11:52:01.253895 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6524 11:52:01.257346 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6525 11:52:01.260569 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6526 11:52:01.260987 ==
6527 11:52:01.264088 Dram Type= 6, Freq= 0, CH_0, rank 1
6528 11:52:01.270791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 11:52:01.271209 ==
6530 11:52:01.271539 DQS Delay:
6531 11:52:01.271846 DQS0 = 59, DQS1 = 59
6532 11:52:01.274016 DQM Delay:
6533 11:52:01.274427 DQM0 = 17, DQM1 = 10
6534 11:52:01.277115 DQ Delay:
6535 11:52:01.280759 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6536 11:52:01.283554 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =32
6537 11:52:01.283967 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6538 11:52:01.287302 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6539 11:52:01.290574
6540 11:52:01.290988
6541 11:52:01.291318 ==
6542 11:52:01.293813 Dram Type= 6, Freq= 0, CH_0, rank 1
6543 11:52:01.296987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6544 11:52:01.297409 ==
6545 11:52:01.297779
6546 11:52:01.298199
6547 11:52:01.300339 TX Vref Scan disable
6548 11:52:01.300754 == TX Byte 0 ==
6549 11:52:01.303593 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6550 11:52:01.310243 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6551 11:52:01.310659 == TX Byte 1 ==
6552 11:52:01.313624 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6553 11:52:01.320331 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6554 11:52:01.320751 ==
6555 11:52:01.323516 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 11:52:01.327179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 11:52:01.327624 ==
6558 11:52:01.327963
6559 11:52:01.328312
6560 11:52:01.330289 TX Vref Scan disable
6561 11:52:01.330703 == TX Byte 0 ==
6562 11:52:01.333213 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6563 11:52:01.339947 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6564 11:52:01.340437 == TX Byte 1 ==
6565 11:52:01.343266 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6566 11:52:01.349941 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6567 11:52:01.350383
6568 11:52:01.350715 [DATLAT]
6569 11:52:01.353443 Freq=400, CH0 RK1
6570 11:52:01.353860
6571 11:52:01.354222 DATLAT Default: 0xe
6572 11:52:01.356479 0, 0xFFFF, sum = 0
6573 11:52:01.356900 1, 0xFFFF, sum = 0
6574 11:52:01.359775 2, 0xFFFF, sum = 0
6575 11:52:01.360263 3, 0xFFFF, sum = 0
6576 11:52:01.363129 4, 0xFFFF, sum = 0
6577 11:52:01.363550 5, 0xFFFF, sum = 0
6578 11:52:01.366602 6, 0xFFFF, sum = 0
6579 11:52:01.367143 7, 0xFFFF, sum = 0
6580 11:52:01.370283 8, 0xFFFF, sum = 0
6581 11:52:01.370705 9, 0xFFFF, sum = 0
6582 11:52:01.373577 10, 0xFFFF, sum = 0
6583 11:52:01.373998 11, 0xFFFF, sum = 0
6584 11:52:01.376802 12, 0xFFFF, sum = 0
6585 11:52:01.377222 13, 0x0, sum = 1
6586 11:52:01.380168 14, 0x0, sum = 2
6587 11:52:01.380662 15, 0x0, sum = 3
6588 11:52:01.383289 16, 0x0, sum = 4
6589 11:52:01.383727 best_step = 14
6590 11:52:01.384077
6591 11:52:01.384436 ==
6592 11:52:01.386321 Dram Type= 6, Freq= 0, CH_0, rank 1
6593 11:52:01.392970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6594 11:52:01.393388 ==
6595 11:52:01.393716 RX Vref Scan: 0
6596 11:52:01.394022
6597 11:52:01.396313 RX Vref 0 -> 0, step: 1
6598 11:52:01.396729
6599 11:52:01.400014 RX Delay -359 -> 252, step: 8
6600 11:52:01.406499 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6601 11:52:01.409844 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6602 11:52:01.413152 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6603 11:52:01.416410 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6604 11:52:01.423484 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6605 11:52:01.426088 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6606 11:52:01.429596 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6607 11:52:01.432917 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6608 11:52:01.439652 iDelay=217, Bit 8, Center -64 (-311 ~ 184) 496
6609 11:52:01.442839 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6610 11:52:01.446435 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6611 11:52:01.449462 iDelay=217, Bit 11, Center -64 (-311 ~ 184) 496
6612 11:52:01.456064 iDelay=217, Bit 12, Center -52 (-303 ~ 200) 504
6613 11:52:01.459734 iDelay=217, Bit 13, Center -44 (-295 ~ 208) 504
6614 11:52:01.462932 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6615 11:52:01.466395 iDelay=217, Bit 15, Center -48 (-295 ~ 200) 496
6616 11:52:01.469496 ==
6617 11:52:01.472495 Dram Type= 6, Freq= 0, CH_0, rank 1
6618 11:52:01.476198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6619 11:52:01.476316 ==
6620 11:52:01.476381 DQS Delay:
6621 11:52:01.479218 DQS0 = 60, DQS1 = 72
6622 11:52:01.479300 DQM Delay:
6623 11:52:01.482609 DQM0 = 11, DQM1 = 17
6624 11:52:01.482690 DQ Delay:
6625 11:52:01.485975 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6626 11:52:01.489124 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6627 11:52:01.492188 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6628 11:52:01.495586 DQ12 =20, DQ13 =28, DQ14 =28, DQ15 =24
6629 11:52:01.495667
6630 11:52:01.495731
6631 11:52:01.502598 [DQSOSCAuto] RK1, (LSB)MR18= 0xcc81, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6632 11:52:01.505949 CH0 RK1: MR19=C0C, MR18=CC81
6633 11:52:01.512530 CH0_RK1: MR19=0xC0C, MR18=0xCC81, DQSOSC=384, MR23=63, INC=400, DEC=267
6634 11:52:01.515911 [RxdqsGatingPostProcess] freq 400
6635 11:52:01.519323 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6636 11:52:01.522052 best DQS0 dly(2T, 0.5T) = (0, 10)
6637 11:52:01.525812 best DQS1 dly(2T, 0.5T) = (0, 10)
6638 11:52:01.529193 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6639 11:52:01.532384 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6640 11:52:01.535802 best DQS0 dly(2T, 0.5T) = (0, 10)
6641 11:52:01.538998 best DQS1 dly(2T, 0.5T) = (0, 10)
6642 11:52:01.542284 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6643 11:52:01.545407 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6644 11:52:01.548900 Pre-setting of DQS Precalculation
6645 11:52:01.552118 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6646 11:52:01.555450 ==
6647 11:52:01.555621 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 11:52:01.562236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 11:52:01.562475 ==
6650 11:52:01.565453 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6651 11:52:01.572262 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6652 11:52:01.575502 [CA 0] Center 36 (8~64) winsize 57
6653 11:52:01.579042 [CA 1] Center 36 (8~64) winsize 57
6654 11:52:01.582186 [CA 2] Center 36 (8~64) winsize 57
6655 11:52:01.585850 [CA 3] Center 36 (8~64) winsize 57
6656 11:52:01.588816 [CA 4] Center 36 (8~64) winsize 57
6657 11:52:01.592256 [CA 5] Center 36 (8~64) winsize 57
6658 11:52:01.592675
6659 11:52:01.595541 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6660 11:52:01.595953
6661 11:52:01.599003 [CATrainingPosCal] consider 1 rank data
6662 11:52:01.602248 u2DelayCellTimex100 = 270/100 ps
6663 11:52:01.605727 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:52:01.608963 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:52:01.612147 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:52:01.615832 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6667 11:52:01.619193 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6668 11:52:01.625350 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6669 11:52:01.625763
6670 11:52:01.629201 CA PerBit enable=1, Macro0, CA PI delay=36
6671 11:52:01.629616
6672 11:52:01.632423 [CBTSetCACLKResult] CA Dly = 36
6673 11:52:01.632838 CS Dly: 1 (0~32)
6674 11:52:01.633168 ==
6675 11:52:01.635765 Dram Type= 6, Freq= 0, CH_1, rank 1
6676 11:52:01.638935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:52:01.641874 ==
6678 11:52:01.645469 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6679 11:52:01.651936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6680 11:52:01.655484 [CA 0] Center 36 (8~64) winsize 57
6681 11:52:01.658578 [CA 1] Center 36 (8~64) winsize 57
6682 11:52:01.662061 [CA 2] Center 36 (8~64) winsize 57
6683 11:52:01.665330 [CA 3] Center 36 (8~64) winsize 57
6684 11:52:01.668990 [CA 4] Center 36 (8~64) winsize 57
6685 11:52:01.671625 [CA 5] Center 36 (8~64) winsize 57
6686 11:52:01.672045
6687 11:52:01.675441 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6688 11:52:01.675857
6689 11:52:01.678590 [CATrainingPosCal] consider 2 rank data
6690 11:52:01.681792 u2DelayCellTimex100 = 270/100 ps
6691 11:52:01.685318 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6692 11:52:01.688606 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6693 11:52:01.691737 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6694 11:52:01.695156 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6695 11:52:01.698496 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 11:52:01.701854 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 11:52:01.702270
6698 11:52:01.705516 CA PerBit enable=1, Macro0, CA PI delay=36
6699 11:52:01.708711
6700 11:52:01.709123 [CBTSetCACLKResult] CA Dly = 36
6701 11:52:01.711789 CS Dly: 1 (0~32)
6702 11:52:01.712234
6703 11:52:01.715087 ----->DramcWriteLeveling(PI) begin...
6704 11:52:01.715547 ==
6705 11:52:01.718299 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 11:52:01.722082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 11:52:01.722505 ==
6708 11:52:01.725335 Write leveling (Byte 0): 40 => 8
6709 11:52:01.728713 Write leveling (Byte 1): 40 => 8
6710 11:52:01.731951 DramcWriteLeveling(PI) end<-----
6711 11:52:01.732414
6712 11:52:01.732842 ==
6713 11:52:01.735249 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 11:52:01.738754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 11:52:01.739290 ==
6716 11:52:01.741933 [Gating] SW mode calibration
6717 11:52:01.748569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6718 11:52:01.755115 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6719 11:52:01.758269 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6720 11:52:01.764792 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6721 11:52:01.768151 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 11:52:01.771467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6723 11:52:01.778196 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6724 11:52:01.781246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6725 11:52:01.784796 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6726 11:52:01.791248 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6727 11:52:01.794863 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6728 11:52:01.797998 Total UI for P1: 0, mck2ui 16
6729 11:52:01.801392 best dqsien dly found for B0: ( 0, 14, 24)
6730 11:52:01.804936 Total UI for P1: 0, mck2ui 16
6731 11:52:01.808487 best dqsien dly found for B1: ( 0, 14, 24)
6732 11:52:01.811392 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6733 11:52:01.814665 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6734 11:52:01.815088
6735 11:52:01.817934 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6736 11:52:01.821094 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6737 11:52:01.824850 [Gating] SW calibration Done
6738 11:52:01.825270 ==
6739 11:52:01.827798 Dram Type= 6, Freq= 0, CH_1, rank 0
6740 11:52:01.830600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 11:52:01.834278 ==
6742 11:52:01.834359 RX Vref Scan: 0
6743 11:52:01.834423
6744 11:52:01.837544 RX Vref 0 -> 0, step: 1
6745 11:52:01.837625
6746 11:52:01.840830 RX Delay -410 -> 252, step: 16
6747 11:52:01.844072 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6748 11:52:01.847319 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6749 11:52:01.850697 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6750 11:52:01.857075 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6751 11:52:01.860877 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6752 11:52:01.863780 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6753 11:52:01.867292 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6754 11:52:01.873571 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6755 11:52:01.877127 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6756 11:52:01.880508 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6757 11:52:01.883732 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6758 11:52:01.890473 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6759 11:52:01.894139 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6760 11:52:01.896822 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6761 11:52:01.900379 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6762 11:52:01.907063 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6763 11:52:01.907171 ==
6764 11:52:01.910164 Dram Type= 6, Freq= 0, CH_1, rank 0
6765 11:52:01.913491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6766 11:52:01.913574 ==
6767 11:52:01.913639 DQS Delay:
6768 11:52:01.917140 DQS0 = 51, DQS1 = 67
6769 11:52:01.917221 DQM Delay:
6770 11:52:01.920307 DQM0 = 13, DQM1 = 18
6771 11:52:01.920389 DQ Delay:
6772 11:52:01.923574 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6773 11:52:01.926776 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6774 11:52:01.930025 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6775 11:52:01.933417 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6776 11:52:01.933498
6777 11:52:01.933563
6778 11:52:01.933622 ==
6779 11:52:01.936648 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 11:52:01.940421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 11:52:01.940504 ==
6782 11:52:01.940568
6783 11:52:01.943239
6784 11:52:01.943320 TX Vref Scan disable
6785 11:52:01.947043 == TX Byte 0 ==
6786 11:52:01.949886 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6787 11:52:01.953704 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6788 11:52:01.956994 == TX Byte 1 ==
6789 11:52:01.960361 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6790 11:52:01.963544 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6791 11:52:01.963625 ==
6792 11:52:01.967066 Dram Type= 6, Freq= 0, CH_1, rank 0
6793 11:52:01.969704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6794 11:52:01.973153 ==
6795 11:52:01.973234
6796 11:52:01.973298
6797 11:52:01.973358 TX Vref Scan disable
6798 11:52:01.976358 == TX Byte 0 ==
6799 11:52:01.980042 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6800 11:52:01.982930 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6801 11:52:01.986548 == TX Byte 1 ==
6802 11:52:01.989897 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6803 11:52:01.993287 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6804 11:52:01.993368
6805 11:52:01.996537 [DATLAT]
6806 11:52:01.996618 Freq=400, CH1 RK0
6807 11:52:01.996682
6808 11:52:01.999842 DATLAT Default: 0xf
6809 11:52:01.999924 0, 0xFFFF, sum = 0
6810 11:52:02.002993 1, 0xFFFF, sum = 0
6811 11:52:02.003075 2, 0xFFFF, sum = 0
6812 11:52:02.006199 3, 0xFFFF, sum = 0
6813 11:52:02.006282 4, 0xFFFF, sum = 0
6814 11:52:02.009673 5, 0xFFFF, sum = 0
6815 11:52:02.009756 6, 0xFFFF, sum = 0
6816 11:52:02.013130 7, 0xFFFF, sum = 0
6817 11:52:02.013212 8, 0xFFFF, sum = 0
6818 11:52:02.016351 9, 0xFFFF, sum = 0
6819 11:52:02.016434 10, 0xFFFF, sum = 0
6820 11:52:02.019345 11, 0xFFFF, sum = 0
6821 11:52:02.019427 12, 0xFFFF, sum = 0
6822 11:52:02.022698 13, 0x0, sum = 1
6823 11:52:02.022781 14, 0x0, sum = 2
6824 11:52:02.026357 15, 0x0, sum = 3
6825 11:52:02.026439 16, 0x0, sum = 4
6826 11:52:02.029388 best_step = 14
6827 11:52:02.029469
6828 11:52:02.029534 ==
6829 11:52:02.032987 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 11:52:02.036323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 11:52:02.036409 ==
6832 11:52:02.039465 RX Vref Scan: 1
6833 11:52:02.039547
6834 11:52:02.039613 RX Vref 0 -> 0, step: 1
6835 11:52:02.039673
6836 11:52:02.042906 RX Delay -375 -> 252, step: 8
6837 11:52:02.042987
6838 11:52:02.046277 Set Vref, RX VrefLevel [Byte0]: 54
6839 11:52:02.049519 [Byte1]: 55
6840 11:52:02.054561
6841 11:52:02.054657 Final RX Vref Byte 0 = 54 to rank0
6842 11:52:02.057817 Final RX Vref Byte 1 = 55 to rank0
6843 11:52:02.061179 Final RX Vref Byte 0 = 54 to rank1
6844 11:52:02.064397 Final RX Vref Byte 1 = 55 to rank1==
6845 11:52:02.067569 Dram Type= 6, Freq= 0, CH_1, rank 0
6846 11:52:02.074061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6847 11:52:02.074143 ==
6848 11:52:02.074208 DQS Delay:
6849 11:52:02.077182 DQS0 = 52, DQS1 = 68
6850 11:52:02.077263 DQM Delay:
6851 11:52:02.077328 DQM0 = 9, DQM1 = 13
6852 11:52:02.080483 DQ Delay:
6853 11:52:02.084054 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6854 11:52:02.084135 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6855 11:52:02.087282 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =8
6856 11:52:02.090722 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6857 11:52:02.090803
6858 11:52:02.093994
6859 11:52:02.100562 [DQSOSCAuto] RK0, (LSB)MR18= 0x6578, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 397 ps
6860 11:52:02.103795 CH1 RK0: MR19=C0C, MR18=6578
6861 11:52:02.110738 CH1_RK0: MR19=0xC0C, MR18=0x6578, DQSOSC=394, MR23=63, INC=380, DEC=253
6862 11:52:02.110820 ==
6863 11:52:02.113828 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 11:52:02.117186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 11:52:02.117268 ==
6866 11:52:02.120422 [Gating] SW mode calibration
6867 11:52:02.127015 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6868 11:52:02.133707 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6869 11:52:02.137273 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6870 11:52:02.140360 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6871 11:52:02.146803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 11:52:02.150280 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6873 11:52:02.153430 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6874 11:52:02.157026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6875 11:52:02.163643 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6876 11:52:02.166935 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6877 11:52:02.170173 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6878 11:52:02.173691 Total UI for P1: 0, mck2ui 16
6879 11:52:02.176796 best dqsien dly found for B0: ( 0, 14, 24)
6880 11:52:02.180055 Total UI for P1: 0, mck2ui 16
6881 11:52:02.183305 best dqsien dly found for B1: ( 0, 14, 24)
6882 11:52:02.186645 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6883 11:52:02.193163 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6884 11:52:02.193245
6885 11:52:02.196648 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6886 11:52:02.200101 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6887 11:52:02.203403 [Gating] SW calibration Done
6888 11:52:02.203484 ==
6889 11:52:02.206386 Dram Type= 6, Freq= 0, CH_1, rank 1
6890 11:52:02.209910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6891 11:52:02.209991 ==
6892 11:52:02.213328 RX Vref Scan: 0
6893 11:52:02.213409
6894 11:52:02.213474 RX Vref 0 -> 0, step: 1
6895 11:52:02.213534
6896 11:52:02.216491 RX Delay -410 -> 252, step: 16
6897 11:52:02.219511 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6898 11:52:02.226724 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6899 11:52:02.229537 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6900 11:52:02.232782 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6901 11:52:02.236063 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6902 11:52:02.242648 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6903 11:52:02.245991 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6904 11:52:02.249829 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6905 11:52:02.256350 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6906 11:52:02.259307 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6907 11:52:02.262444 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6908 11:52:02.266159 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6909 11:52:02.272570 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6910 11:52:02.275934 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6911 11:52:02.279313 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6912 11:52:02.282507 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6913 11:52:02.286148 ==
6914 11:52:02.286230 Dram Type= 6, Freq= 0, CH_1, rank 1
6915 11:52:02.292684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 11:52:02.292767 ==
6917 11:52:02.292831 DQS Delay:
6918 11:52:02.295918 DQS0 = 59, DQS1 = 67
6919 11:52:02.295999 DQM Delay:
6920 11:52:02.299391 DQM0 = 19, DQM1 = 21
6921 11:52:02.299472 DQ Delay:
6922 11:52:02.302728 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6923 11:52:02.305629 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6924 11:52:02.309355 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
6925 11:52:02.312508 DQ12 =32, DQ13 =32, DQ14 =24, DQ15 =32
6926 11:52:02.312590
6927 11:52:02.312653
6928 11:52:02.312713 ==
6929 11:52:02.315894 Dram Type= 6, Freq= 0, CH_1, rank 1
6930 11:52:02.319045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6931 11:52:02.319131 ==
6932 11:52:02.319195
6933 11:52:02.319254
6934 11:52:02.322747 TX Vref Scan disable
6935 11:52:02.322828 == TX Byte 0 ==
6936 11:52:02.329364 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6937 11:52:02.332647 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6938 11:52:02.332730 == TX Byte 1 ==
6939 11:52:02.339291 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6940 11:52:02.342125 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6941 11:52:02.342207 ==
6942 11:52:02.346028 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 11:52:02.349370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 11:52:02.349452 ==
6945 11:52:02.349517
6946 11:52:02.349577
6947 11:52:02.352542 TX Vref Scan disable
6948 11:52:02.352623 == TX Byte 0 ==
6949 11:52:02.359230 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6950 11:52:02.362392 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6951 11:52:02.362474 == TX Byte 1 ==
6952 11:52:02.368951 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6953 11:52:02.372450 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6954 11:52:02.372531
6955 11:52:02.372595 [DATLAT]
6956 11:52:02.375801 Freq=400, CH1 RK1
6957 11:52:02.375883
6958 11:52:02.375947 DATLAT Default: 0xe
6959 11:52:02.379205 0, 0xFFFF, sum = 0
6960 11:52:02.379288 1, 0xFFFF, sum = 0
6961 11:52:02.382215 2, 0xFFFF, sum = 0
6962 11:52:02.382298 3, 0xFFFF, sum = 0
6963 11:52:02.385417 4, 0xFFFF, sum = 0
6964 11:52:02.385499 5, 0xFFFF, sum = 0
6965 11:52:02.389030 6, 0xFFFF, sum = 0
6966 11:52:02.389114 7, 0xFFFF, sum = 0
6967 11:52:02.392413 8, 0xFFFF, sum = 0
6968 11:52:02.392497 9, 0xFFFF, sum = 0
6969 11:52:02.395658 10, 0xFFFF, sum = 0
6970 11:52:02.398879 11, 0xFFFF, sum = 0
6971 11:52:02.398962 12, 0xFFFF, sum = 0
6972 11:52:02.402155 13, 0x0, sum = 1
6973 11:52:02.402237 14, 0x0, sum = 2
6974 11:52:02.405350 15, 0x0, sum = 3
6975 11:52:02.405432 16, 0x0, sum = 4
6976 11:52:02.405509 best_step = 14
6977 11:52:02.405570
6978 11:52:02.408556 ==
6979 11:52:02.412089 Dram Type= 6, Freq= 0, CH_1, rank 1
6980 11:52:02.415466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6981 11:52:02.415548 ==
6982 11:52:02.415613 RX Vref Scan: 0
6983 11:52:02.415673
6984 11:52:02.418464 RX Vref 0 -> 0, step: 1
6985 11:52:02.418545
6986 11:52:02.422211 RX Delay -375 -> 252, step: 8
6987 11:52:02.429182 iDelay=217, Bit 0, Center -40 (-287 ~ 208) 496
6988 11:52:02.432000 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6989 11:52:02.435891 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6990 11:52:02.441953 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6991 11:52:02.445794 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
6992 11:52:02.449080 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6993 11:52:02.452434 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6994 11:52:02.455242 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6995 11:52:02.462508 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6996 11:52:02.465237 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6997 11:52:02.469053 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6998 11:52:02.475793 iDelay=217, Bit 11, Center -60 (-319 ~ 200) 520
6999 11:52:02.478738 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7000 11:52:02.482316 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7001 11:52:02.485574 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7002 11:52:02.492165 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7003 11:52:02.492318 ==
7004 11:52:02.495571 Dram Type= 6, Freq= 0, CH_1, rank 1
7005 11:52:02.498909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7006 11:52:02.499061 ==
7007 11:52:02.499182 DQS Delay:
7008 11:52:02.502006 DQS0 = 60, DQS1 = 64
7009 11:52:02.502179 DQM Delay:
7010 11:52:02.505903 DQM0 = 13, DQM1 = 10
7011 11:52:02.506077 DQ Delay:
7012 11:52:02.508720 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
7013 11:52:02.512078 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7014 11:52:02.515277 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7015 11:52:02.519050 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7016 11:52:02.519349
7017 11:52:02.519585
7018 11:52:02.525595 [DQSOSCAuto] RK1, (LSB)MR18= 0x84b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 393 ps
7019 11:52:02.528758 CH1 RK1: MR19=C0C, MR18=84B4
7020 11:52:02.535468 CH1_RK1: MR19=0xC0C, MR18=0x84B4, DQSOSC=387, MR23=63, INC=394, DEC=262
7021 11:52:02.538838 [RxdqsGatingPostProcess] freq 400
7022 11:52:02.545469 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7023 11:52:02.548758 best DQS0 dly(2T, 0.5T) = (0, 10)
7024 11:52:02.549177 best DQS1 dly(2T, 0.5T) = (0, 10)
7025 11:52:02.552132 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7026 11:52:02.555347 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7027 11:52:02.558768 best DQS0 dly(2T, 0.5T) = (0, 10)
7028 11:52:02.562025 best DQS1 dly(2T, 0.5T) = (0, 10)
7029 11:52:02.565520 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7030 11:52:02.568273 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7031 11:52:02.572077 Pre-setting of DQS Precalculation
7032 11:52:02.578522 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7033 11:52:02.585273 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7034 11:52:02.591506 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7035 11:52:02.591922
7036 11:52:02.592297
7037 11:52:02.595358 [Calibration Summary] 800 Mbps
7038 11:52:02.595772 CH 0, Rank 0
7039 11:52:02.598147 SW Impedance : PASS
7040 11:52:02.601336 DUTY Scan : NO K
7041 11:52:02.601751 ZQ Calibration : PASS
7042 11:52:02.605281 Jitter Meter : NO K
7043 11:52:02.607935 CBT Training : PASS
7044 11:52:02.608404 Write leveling : PASS
7045 11:52:02.611662 RX DQS gating : PASS
7046 11:52:02.614980 RX DQ/DQS(RDDQC) : PASS
7047 11:52:02.615396 TX DQ/DQS : PASS
7048 11:52:02.618569 RX DATLAT : PASS
7049 11:52:02.619012 RX DQ/DQS(Engine): PASS
7050 11:52:02.621256 TX OE : NO K
7051 11:52:02.621912 All Pass.
7052 11:52:02.622291
7053 11:52:02.624723 CH 0, Rank 1
7054 11:52:02.625139 SW Impedance : PASS
7055 11:52:02.627897 DUTY Scan : NO K
7056 11:52:02.631310 ZQ Calibration : PASS
7057 11:52:02.631725 Jitter Meter : NO K
7058 11:52:02.634372 CBT Training : PASS
7059 11:52:02.637891 Write leveling : NO K
7060 11:52:02.638306 RX DQS gating : PASS
7061 11:52:02.641292 RX DQ/DQS(RDDQC) : PASS
7062 11:52:02.644639 TX DQ/DQS : PASS
7063 11:52:02.645056 RX DATLAT : PASS
7064 11:52:02.648008 RX DQ/DQS(Engine): PASS
7065 11:52:02.650864 TX OE : NO K
7066 11:52:02.651280 All Pass.
7067 11:52:02.651608
7068 11:52:02.651916 CH 1, Rank 0
7069 11:52:02.654583 SW Impedance : PASS
7070 11:52:02.658006 DUTY Scan : NO K
7071 11:52:02.658422 ZQ Calibration : PASS
7072 11:52:02.661357 Jitter Meter : NO K
7073 11:52:02.664153 CBT Training : PASS
7074 11:52:02.664600 Write leveling : PASS
7075 11:52:02.667584 RX DQS gating : PASS
7076 11:52:02.670858 RX DQ/DQS(RDDQC) : PASS
7077 11:52:02.671289 TX DQ/DQS : PASS
7078 11:52:02.674171 RX DATLAT : PASS
7079 11:52:02.677992 RX DQ/DQS(Engine): PASS
7080 11:52:02.678412 TX OE : NO K
7081 11:52:02.678746 All Pass.
7082 11:52:02.679055
7083 11:52:02.680800 CH 1, Rank 1
7084 11:52:02.684045 SW Impedance : PASS
7085 11:52:02.684490 DUTY Scan : NO K
7086 11:52:02.687672 ZQ Calibration : PASS
7087 11:52:02.688090 Jitter Meter : NO K
7088 11:52:02.690765 CBT Training : PASS
7089 11:52:02.694081 Write leveling : NO K
7090 11:52:02.694501 RX DQS gating : PASS
7091 11:52:02.697402 RX DQ/DQS(RDDQC) : PASS
7092 11:52:02.700558 TX DQ/DQS : PASS
7093 11:52:02.700974 RX DATLAT : PASS
7094 11:52:02.704049 RX DQ/DQS(Engine): PASS
7095 11:52:02.707235 TX OE : NO K
7096 11:52:02.707656 All Pass.
7097 11:52:02.707984
7098 11:52:02.711168 DramC Write-DBI off
7099 11:52:02.711585 PER_BANK_REFRESH: Hybrid Mode
7100 11:52:02.714334 TX_TRACKING: ON
7101 11:52:02.724093 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7102 11:52:02.727088 [FAST_K] Save calibration result to emmc
7103 11:52:02.730468 dramc_set_vcore_voltage set vcore to 725000
7104 11:52:02.730888 Read voltage for 1600, 0
7105 11:52:02.733727 Vio18 = 0
7106 11:52:02.734148 Vcore = 725000
7107 11:52:02.734483 Vdram = 0
7108 11:52:02.737699 Vddq = 0
7109 11:52:02.738115 Vmddr = 0
7110 11:52:02.740435 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7111 11:52:02.747524 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7112 11:52:02.751102 MEM_TYPE=3, freq_sel=13
7113 11:52:02.753535 sv_algorithm_assistance_LP4_3733
7114 11:52:02.756806 ============ PULL DRAM RESETB DOWN ============
7115 11:52:02.760137 ========== PULL DRAM RESETB DOWN end =========
7116 11:52:02.767144 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7117 11:52:02.770596 ===================================
7118 11:52:02.771016 LPDDR4 DRAM CONFIGURATION
7119 11:52:02.773543 ===================================
7120 11:52:02.776852 EX_ROW_EN[0] = 0x0
7121 11:52:02.780533 EX_ROW_EN[1] = 0x0
7122 11:52:02.780953 LP4Y_EN = 0x0
7123 11:52:02.783232 WORK_FSP = 0x1
7124 11:52:02.783648 WL = 0x5
7125 11:52:02.787166 RL = 0x5
7126 11:52:02.787584 BL = 0x2
7127 11:52:02.790513 RPST = 0x0
7128 11:52:02.790931 RD_PRE = 0x0
7129 11:52:02.793592 WR_PRE = 0x1
7130 11:52:02.794013 WR_PST = 0x1
7131 11:52:02.796930 DBI_WR = 0x0
7132 11:52:02.797349 DBI_RD = 0x0
7133 11:52:02.799978 OTF = 0x1
7134 11:52:02.803276 ===================================
7135 11:52:02.806930 ===================================
7136 11:52:02.807351 ANA top config
7137 11:52:02.810153 ===================================
7138 11:52:02.813467 DLL_ASYNC_EN = 0
7139 11:52:02.816874 ALL_SLAVE_EN = 0
7140 11:52:02.817290 NEW_RANK_MODE = 1
7141 11:52:02.820012 DLL_IDLE_MODE = 1
7142 11:52:02.823115 LP45_APHY_COMB_EN = 1
7143 11:52:02.826416 TX_ODT_DIS = 0
7144 11:52:02.829777 NEW_8X_MODE = 1
7145 11:52:02.833068 ===================================
7146 11:52:02.836305 ===================================
7147 11:52:02.836733 data_rate = 3200
7148 11:52:02.839956 CKR = 1
7149 11:52:02.843004 DQ_P2S_RATIO = 8
7150 11:52:02.846197 ===================================
7151 11:52:02.849826 CA_P2S_RATIO = 8
7152 11:52:02.852710 DQ_CA_OPEN = 0
7153 11:52:02.856541 DQ_SEMI_OPEN = 0
7154 11:52:02.856961 CA_SEMI_OPEN = 0
7155 11:52:02.859774 CA_FULL_RATE = 0
7156 11:52:02.862928 DQ_CKDIV4_EN = 0
7157 11:52:02.866278 CA_CKDIV4_EN = 0
7158 11:52:02.869404 CA_PREDIV_EN = 0
7159 11:52:02.872726 PH8_DLY = 12
7160 11:52:02.876163 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7161 11:52:02.876634 DQ_AAMCK_DIV = 4
7162 11:52:02.879752 CA_AAMCK_DIV = 4
7163 11:52:02.882621 CA_ADMCK_DIV = 4
7164 11:52:02.886436 DQ_TRACK_CA_EN = 0
7165 11:52:02.889668 CA_PICK = 1600
7166 11:52:02.892884 CA_MCKIO = 1600
7167 11:52:02.893305 MCKIO_SEMI = 0
7168 11:52:02.895996 PLL_FREQ = 3068
7169 11:52:02.899428 DQ_UI_PI_RATIO = 32
7170 11:52:02.902806 CA_UI_PI_RATIO = 0
7171 11:52:02.905985 ===================================
7172 11:52:02.909730 ===================================
7173 11:52:02.912714 memory_type:LPDDR4
7174 11:52:02.913328 GP_NUM : 10
7175 11:52:02.916087 SRAM_EN : 1
7176 11:52:02.919384 MD32_EN : 0
7177 11:52:02.922708 ===================================
7178 11:52:02.923242 [ANA_INIT] >>>>>>>>>>>>>>
7179 11:52:02.925873 <<<<<< [CONFIGURE PHASE]: ANA_TX
7180 11:52:02.929645 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7181 11:52:02.932310 ===================================
7182 11:52:02.936121 data_rate = 3200,PCW = 0X7600
7183 11:52:02.941497 ===================================
7184 11:52:02.942569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7185 11:52:02.949216 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7186 11:52:02.952495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7187 11:52:02.958988 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7188 11:52:02.962112 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7189 11:52:02.965438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7190 11:52:02.968751 [ANA_INIT] flow start
7191 11:52:02.969164 [ANA_INIT] PLL >>>>>>>>
7192 11:52:02.972141 [ANA_INIT] PLL <<<<<<<<
7193 11:52:02.975509 [ANA_INIT] MIDPI >>>>>>>>
7194 11:52:02.975924 [ANA_INIT] MIDPI <<<<<<<<
7195 11:52:02.979023 [ANA_INIT] DLL >>>>>>>>
7196 11:52:02.982190 [ANA_INIT] DLL <<<<<<<<
7197 11:52:02.982606 [ANA_INIT] flow end
7198 11:52:02.988802 ============ LP4 DIFF to SE enter ============
7199 11:52:02.991949 ============ LP4 DIFF to SE exit ============
7200 11:52:02.992589 [ANA_INIT] <<<<<<<<<<<<<
7201 11:52:02.995526 [Flow] Enable top DCM control >>>>>
7202 11:52:02.998491 [Flow] Enable top DCM control <<<<<
7203 11:52:03.001923 Enable DLL master slave shuffle
7204 11:52:03.008318 ==============================================================
7205 11:52:03.012084 Gating Mode config
7206 11:52:03.015173 ==============================================================
7207 11:52:03.018904 Config description:
7208 11:52:03.028625 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7209 11:52:03.034789 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7210 11:52:03.038703 SELPH_MODE 0: By rank 1: By Phase
7211 11:52:03.044734 ==============================================================
7212 11:52:03.048116 GAT_TRACK_EN = 1
7213 11:52:03.051502 RX_GATING_MODE = 2
7214 11:52:03.054694 RX_GATING_TRACK_MODE = 2
7215 11:52:03.055167 SELPH_MODE = 1
7216 11:52:03.058269 PICG_EARLY_EN = 1
7217 11:52:03.061364 VALID_LAT_VALUE = 1
7218 11:52:03.068001 ==============================================================
7219 11:52:03.071373 Enter into Gating configuration >>>>
7220 11:52:03.074743 Exit from Gating configuration <<<<
7221 11:52:03.078041 Enter into DVFS_PRE_config >>>>>
7222 11:52:03.087986 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7223 11:52:03.091361 Exit from DVFS_PRE_config <<<<<
7224 11:52:03.094568 Enter into PICG configuration >>>>
7225 11:52:03.098008 Exit from PICG configuration <<<<
7226 11:52:03.101206 [RX_INPUT] configuration >>>>>
7227 11:52:03.104712 [RX_INPUT] configuration <<<<<
7228 11:52:03.108092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7229 11:52:03.114804 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7230 11:52:03.121224 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7231 11:52:03.127800 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7232 11:52:03.134647 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7233 11:52:03.137980 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7234 11:52:03.144431 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7235 11:52:03.147667 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7236 11:52:03.151140 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7237 11:52:03.154381 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7238 11:52:03.157787 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7239 11:52:03.164407 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7240 11:52:03.168295 ===================================
7241 11:52:03.171293 LPDDR4 DRAM CONFIGURATION
7242 11:52:03.174761 ===================================
7243 11:52:03.175180 EX_ROW_EN[0] = 0x0
7244 11:52:03.178082 EX_ROW_EN[1] = 0x0
7245 11:52:03.178500 LP4Y_EN = 0x0
7246 11:52:03.181401 WORK_FSP = 0x1
7247 11:52:03.181880 WL = 0x5
7248 11:52:03.184672 RL = 0x5
7249 11:52:03.185090 BL = 0x2
7250 11:52:03.187733 RPST = 0x0
7251 11:52:03.188231 RD_PRE = 0x0
7252 11:52:03.190959 WR_PRE = 0x1
7253 11:52:03.191378 WR_PST = 0x1
7254 11:52:03.194710 DBI_WR = 0x0
7255 11:52:03.195129 DBI_RD = 0x0
7256 11:52:03.197777 OTF = 0x1
7257 11:52:03.200994 ===================================
7258 11:52:03.204370 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7259 11:52:03.208129 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7260 11:52:03.214666 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7261 11:52:03.218011 ===================================
7262 11:52:03.218433 LPDDR4 DRAM CONFIGURATION
7263 11:52:03.221283 ===================================
7264 11:52:03.224559 EX_ROW_EN[0] = 0x10
7265 11:52:03.227920 EX_ROW_EN[1] = 0x0
7266 11:52:03.228594 LP4Y_EN = 0x0
7267 11:52:03.230858 WORK_FSP = 0x1
7268 11:52:03.231279 WL = 0x5
7269 11:52:03.234339 RL = 0x5
7270 11:52:03.234759 BL = 0x2
7271 11:52:03.237901 RPST = 0x0
7272 11:52:03.238403 RD_PRE = 0x0
7273 11:52:03.240844 WR_PRE = 0x1
7274 11:52:03.241484 WR_PST = 0x1
7275 11:52:03.244159 DBI_WR = 0x0
7276 11:52:03.244712 DBI_RD = 0x0
7277 11:52:03.247558 OTF = 0x1
7278 11:52:03.250848 ===================================
7279 11:52:03.257957 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7280 11:52:03.258377 ==
7281 11:52:03.260765 Dram Type= 6, Freq= 0, CH_0, rank 0
7282 11:52:03.264433 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7283 11:52:03.264867 ==
7284 11:52:03.267443 [Duty_Offset_Calibration]
7285 11:52:03.267858 B0:2 B1:0 CA:3
7286 11:52:03.268187
7287 11:52:03.270689 [DutyScan_Calibration_Flow] k_type=0
7288 11:52:03.281484
7289 11:52:03.281901 ==CLK 0==
7290 11:52:03.284810 Final CLK duty delay cell = 0
7291 11:52:03.288112 [0] MAX Duty = 5031%(X100), DQS PI = 12
7292 11:52:03.291441 [0] MIN Duty = 4907%(X100), DQS PI = 6
7293 11:52:03.291860 [0] AVG Duty = 4969%(X100)
7294 11:52:03.292190
7295 11:52:03.294655 CH0 CLK Duty spec in!! Max-Min= 124%
7296 11:52:03.301553 [DutyScan_Calibration_Flow] ====Done====
7297 11:52:03.301996
7298 11:52:03.304590 [DutyScan_Calibration_Flow] k_type=1
7299 11:52:03.321348
7300 11:52:03.321766 ==DQS 0 ==
7301 11:52:03.324555 Final DQS duty delay cell = 0
7302 11:52:03.327695 [0] MAX Duty = 5094%(X100), DQS PI = 30
7303 11:52:03.331136 [0] MIN Duty = 4875%(X100), DQS PI = 52
7304 11:52:03.334113 [0] AVG Duty = 4984%(X100)
7305 11:52:03.334531
7306 11:52:03.334862 ==DQS 1 ==
7307 11:52:03.337585 Final DQS duty delay cell = 0
7308 11:52:03.341102 [0] MAX Duty = 5156%(X100), DQS PI = 30
7309 11:52:03.344182 [0] MIN Duty = 5031%(X100), DQS PI = 14
7310 11:52:03.347496 [0] AVG Duty = 5093%(X100)
7311 11:52:03.347950
7312 11:52:03.351077 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7313 11:52:03.351543
7314 11:52:03.353856 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7315 11:52:03.357456 [DutyScan_Calibration_Flow] ====Done====
7316 11:52:03.357907
7317 11:52:03.360833 [DutyScan_Calibration_Flow] k_type=3
7318 11:52:03.378259
7319 11:52:03.378749 ==DQM 0 ==
7320 11:52:03.381690 Final DQM duty delay cell = 0
7321 11:52:03.384862 [0] MAX Duty = 5156%(X100), DQS PI = 12
7322 11:52:03.388092 [0] MIN Duty = 4875%(X100), DQS PI = 48
7323 11:52:03.391417 [0] AVG Duty = 5015%(X100)
7324 11:52:03.391869
7325 11:52:03.392429 ==DQM 1 ==
7326 11:52:03.394639 Final DQM duty delay cell = 0
7327 11:52:03.397895 [0] MAX Duty = 4969%(X100), DQS PI = 62
7328 11:52:03.401333 [0] MIN Duty = 4813%(X100), DQS PI = 20
7329 11:52:03.404751 [0] AVG Duty = 4891%(X100)
7330 11:52:03.405165
7331 11:52:03.408554 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7332 11:52:03.408972
7333 11:52:03.410963 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7334 11:52:03.414688 [DutyScan_Calibration_Flow] ====Done====
7335 11:52:03.415105
7336 11:52:03.417919 [DutyScan_Calibration_Flow] k_type=2
7337 11:52:03.434395
7338 11:52:03.434625 ==DQ 0 ==
7339 11:52:03.437499 Final DQ duty delay cell = -4
7340 11:52:03.440794 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7341 11:52:03.444222 [-4] MIN Duty = 4876%(X100), DQS PI = 44
7342 11:52:03.447625 [-4] AVG Duty = 4938%(X100)
7343 11:52:03.447934
7344 11:52:03.448121 ==DQ 1 ==
7345 11:52:03.451033 Final DQ duty delay cell = 0
7346 11:52:03.454040 [0] MAX Duty = 5156%(X100), DQS PI = 58
7347 11:52:03.457547 [0] MIN Duty = 5000%(X100), DQS PI = 16
7348 11:52:03.461123 [0] AVG Duty = 5078%(X100)
7349 11:52:03.461433
7350 11:52:03.463936 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7351 11:52:03.464274
7352 11:52:03.467544 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7353 11:52:03.470958 [DutyScan_Calibration_Flow] ====Done====
7354 11:52:03.471283 ==
7355 11:52:03.473888 Dram Type= 6, Freq= 0, CH_1, rank 0
7356 11:52:03.477683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7357 11:52:03.477984 ==
7358 11:52:03.480506 [Duty_Offset_Calibration]
7359 11:52:03.480736 B0:1 B1:-2 CA:0
7360 11:52:03.480922
7361 11:52:03.483732 [DutyScan_Calibration_Flow] k_type=0
7362 11:52:03.495009
7363 11:52:03.495297 ==CLK 0==
7364 11:52:03.498485 Final CLK duty delay cell = 0
7365 11:52:03.501649 [0] MAX Duty = 5093%(X100), DQS PI = 22
7366 11:52:03.504540 [0] MIN Duty = 4844%(X100), DQS PI = 60
7367 11:52:03.508240 [0] AVG Duty = 4968%(X100)
7368 11:52:03.508443
7369 11:52:03.511114 CH1 CLK Duty spec in!! Max-Min= 249%
7370 11:52:03.514820 [DutyScan_Calibration_Flow] ====Done====
7371 11:52:03.515069
7372 11:52:03.518039 [DutyScan_Calibration_Flow] k_type=1
7373 11:52:03.533889
7374 11:52:03.534337 ==DQS 0 ==
7375 11:52:03.537238 Final DQS duty delay cell = -4
7376 11:52:03.540567 [-4] MAX Duty = 4969%(X100), DQS PI = 26
7377 11:52:03.543583 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7378 11:52:03.547585 [-4] AVG Duty = 4906%(X100)
7379 11:52:03.547945
7380 11:52:03.548369 ==DQS 1 ==
7381 11:52:03.550269 Final DQS duty delay cell = 0
7382 11:52:03.554089 [0] MAX Duty = 5124%(X100), DQS PI = 62
7383 11:52:03.556963 [0] MIN Duty = 4844%(X100), DQS PI = 24
7384 11:52:03.560273 [0] AVG Duty = 4984%(X100)
7385 11:52:03.560641
7386 11:52:03.563540 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7387 11:52:03.564025
7388 11:52:03.566914 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7389 11:52:03.570537 [DutyScan_Calibration_Flow] ====Done====
7390 11:52:03.571002
7391 11:52:03.573457 [DutyScan_Calibration_Flow] k_type=3
7392 11:52:03.591002
7393 11:52:03.591368 ==DQM 0 ==
7394 11:52:03.594232 Final DQM duty delay cell = 0
7395 11:52:03.597773 [0] MAX Duty = 5031%(X100), DQS PI = 24
7396 11:52:03.600991 [0] MIN Duty = 4813%(X100), DQS PI = 56
7397 11:52:03.604269 [0] AVG Duty = 4922%(X100)
7398 11:52:03.604686
7399 11:52:03.605008 ==DQM 1 ==
7400 11:52:03.607642 Final DQM duty delay cell = 0
7401 11:52:03.610813 [0] MAX Duty = 5062%(X100), DQS PI = 34
7402 11:52:03.614194 [0] MIN Duty = 4875%(X100), DQS PI = 24
7403 11:52:03.617438 [0] AVG Duty = 4968%(X100)
7404 11:52:03.617954
7405 11:52:03.620690 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7406 11:52:03.621207
7407 11:52:03.623864 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7408 11:52:03.627501 [DutyScan_Calibration_Flow] ====Done====
7409 11:52:03.627590
7410 11:52:03.630653 [DutyScan_Calibration_Flow] k_type=2
7411 11:52:03.647292
7412 11:52:03.647380 ==DQ 0 ==
7413 11:52:03.650812 Final DQ duty delay cell = 0
7414 11:52:03.653922 [0] MAX Duty = 5093%(X100), DQS PI = 22
7415 11:52:03.657199 [0] MIN Duty = 4938%(X100), DQS PI = 0
7416 11:52:03.657303 [0] AVG Duty = 5015%(X100)
7417 11:52:03.661112
7418 11:52:03.661226 ==DQ 1 ==
7419 11:52:03.664488 Final DQ duty delay cell = 0
7420 11:52:03.667711 [0] MAX Duty = 5125%(X100), DQS PI = 34
7421 11:52:03.671191 [0] MIN Duty = 4969%(X100), DQS PI = 24
7422 11:52:03.671261 [0] AVG Duty = 5047%(X100)
7423 11:52:03.671327
7424 11:52:03.674471 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7425 11:52:03.677767
7426 11:52:03.680671 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7427 11:52:03.683867 [DutyScan_Calibration_Flow] ====Done====
7428 11:52:03.687475 nWR fixed to 30
7429 11:52:03.687595 [ModeRegInit_LP4] CH0 RK0
7430 11:52:03.690881 [ModeRegInit_LP4] CH0 RK1
7431 11:52:03.693766 [ModeRegInit_LP4] CH1 RK0
7432 11:52:03.697035 [ModeRegInit_LP4] CH1 RK1
7433 11:52:03.697174 match AC timing 5
7434 11:52:03.700697 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7435 11:52:03.707064 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7436 11:52:03.710769 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7437 11:52:03.717025 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7438 11:52:03.720269 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7439 11:52:03.720494 [MiockJmeterHQA]
7440 11:52:03.720675
7441 11:52:03.723672 [DramcMiockJmeter] u1RxGatingPI = 0
7442 11:52:03.727496 0 : 4254, 4029
7443 11:52:03.727885 4 : 4255, 4029
7444 11:52:03.730652 8 : 4260, 4032
7445 11:52:03.731065 12 : 4367, 4140
7446 11:52:03.731377 16 : 4255, 4029
7447 11:52:03.733945 20 : 4365, 4140
7448 11:52:03.734369 24 : 4255, 4029
7449 11:52:03.737326 28 : 4252, 4030
7450 11:52:03.737752 32 : 4255, 4029
7451 11:52:03.740591 36 : 4366, 4140
7452 11:52:03.741030 40 : 4368, 4140
7453 11:52:03.741366 44 : 4253, 4029
7454 11:52:03.744112 48 : 4255, 4030
7455 11:52:03.744684 52 : 4257, 4029
7456 11:52:03.747188 56 : 4252, 4030
7457 11:52:03.747611 60 : 4252, 4030
7458 11:52:03.750478 64 : 4253, 4029
7459 11:52:03.750905 68 : 4252, 4029
7460 11:52:03.753708 72 : 4255, 4029
7461 11:52:03.754130 76 : 4363, 4140
7462 11:52:03.754465 80 : 4363, 4140
7463 11:52:03.757012 84 : 4365, 4140
7464 11:52:03.757431 88 : 4363, 4139
7465 11:52:03.760590 92 : 4255, 4029
7466 11:52:03.761014 96 : 4252, 4030
7467 11:52:03.763920 100 : 4258, 4031
7468 11:52:03.764382 104 : 4255, 3815
7469 11:52:03.767275 108 : 4252, 0
7470 11:52:03.767728 112 : 4368, 0
7471 11:52:03.768071 116 : 4253, 0
7472 11:52:03.770480 120 : 4363, 0
7473 11:52:03.770934 124 : 4363, 0
7474 11:52:03.773817 128 : 4252, 0
7475 11:52:03.774271 132 : 4252, 0
7476 11:52:03.774618 136 : 4253, 0
7477 11:52:03.777099 140 : 4252, 0
7478 11:52:03.777552 144 : 4252, 0
7479 11:52:03.780347 148 : 4363, 0
7480 11:52:03.781009 152 : 4252, 0
7481 11:52:03.781360 156 : 4255, 0
7482 11:52:03.783237 160 : 4365, 0
7483 11:52:03.783884 164 : 4252, 0
7484 11:52:03.784479 168 : 4363, 0
7485 11:52:03.786943 172 : 4361, 0
7486 11:52:03.787366 176 : 4368, 0
7487 11:52:03.790318 180 : 4252, 0
7488 11:52:03.790741 184 : 4252, 0
7489 11:52:03.791078 188 : 4253, 0
7490 11:52:03.793737 192 : 4257, 0
7491 11:52:03.794157 196 : 4253, 0
7492 11:52:03.796671 200 : 4252, 0
7493 11:52:03.797094 204 : 4368, 0
7494 11:52:03.797428 208 : 4254, 0
7495 11:52:03.800051 212 : 4252, 0
7496 11:52:03.800558 216 : 4255, 0
7497 11:52:03.803549 220 : 4253, 0
7498 11:52:03.803972 224 : 4252, 0
7499 11:52:03.804404 228 : 4253, 0
7500 11:52:03.806442 232 : 4252, 0
7501 11:52:03.806863 236 : 4252, 874
7502 11:52:03.809595 240 : 4255, 4029
7503 11:52:03.810016 244 : 4250, 4026
7504 11:52:03.813139 248 : 4252, 4029
7505 11:52:03.813702 252 : 4363, 4140
7506 11:52:03.816623 256 : 4255, 4029
7507 11:52:03.817081 260 : 4255, 4029
7508 11:52:03.817425 264 : 4252, 4029
7509 11:52:03.819684 268 : 4253, 4029
7510 11:52:03.820106 272 : 4252, 4030
7511 11:52:03.823365 276 : 4257, 4032
7512 11:52:03.823784 280 : 4255, 4029
7513 11:52:03.826201 284 : 4363, 4140
7514 11:52:03.826651 288 : 4363, 4140
7515 11:52:03.829720 292 : 4252, 4026
7516 11:52:03.830147 296 : 4255, 4029
7517 11:52:03.833171 300 : 4252, 4029
7518 11:52:03.833645 304 : 4363, 4140
7519 11:52:03.836159 308 : 4250, 4026
7520 11:52:03.836770 312 : 4252, 4030
7521 11:52:03.840066 316 : 4255, 4029
7522 11:52:03.840755 320 : 4253, 4029
7523 11:52:03.841305 324 : 4363, 4139
7524 11:52:03.842782 328 : 4363, 4139
7525 11:52:03.843198 332 : 4255, 4029
7526 11:52:03.846336 336 : 4255, 4030
7527 11:52:03.846768 340 : 4363, 4140
7528 11:52:03.849984 344 : 4255, 4029
7529 11:52:03.850426 348 : 4255, 4029
7530 11:52:03.852993 352 : 4366, 4136
7531 11:52:03.853456 356 : 4363, 2757
7532 11:52:03.856519 360 : 4252, 6
7533 11:52:03.856940
7534 11:52:03.857380 MIOCK jitter meter ch=0
7535 11:52:03.857822
7536 11:52:03.859522 1T = (360-108) = 252 dly cells
7537 11:52:03.866284 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7538 11:52:03.866876 ==
7539 11:52:03.869783 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 11:52:03.872954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 11:52:03.873506 ==
7542 11:52:03.879667 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 11:52:03.882897 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 11:52:03.889446 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 11:52:03.892663 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 11:52:03.902626 [CA 0] Center 43 (13~74) winsize 62
7547 11:52:03.906194 [CA 1] Center 43 (13~74) winsize 62
7548 11:52:03.909404 [CA 2] Center 38 (10~67) winsize 58
7549 11:52:03.912254 [CA 3] Center 38 (9~68) winsize 60
7550 11:52:03.915996 [CA 4] Center 36 (7~66) winsize 60
7551 11:52:03.918761 [CA 5] Center 36 (7~66) winsize 60
7552 11:52:03.918846
7553 11:52:03.922301 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7554 11:52:03.922384
7555 11:52:03.928642 [CATrainingPosCal] consider 1 rank data
7556 11:52:03.928752 u2DelayCellTimex100 = 258/100 ps
7557 11:52:03.935195 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7558 11:52:03.938818 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7559 11:52:03.941828 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7560 11:52:03.945240 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7561 11:52:03.948707 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7562 11:52:03.951921 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7563 11:52:03.952011
7564 11:52:03.955549 CA PerBit enable=1, Macro0, CA PI delay=36
7565 11:52:03.955658
7566 11:52:03.958816 [CBTSetCACLKResult] CA Dly = 36
7567 11:52:03.961956 CS Dly: 11 (0~42)
7568 11:52:03.965042 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 11:52:03.968904 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 11:52:03.968989 ==
7571 11:52:03.971758 Dram Type= 6, Freq= 0, CH_0, rank 1
7572 11:52:03.978409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 11:52:03.978497 ==
7574 11:52:03.981682 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 11:52:03.988357 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 11:52:03.991722 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 11:52:03.998343 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 11:52:04.006093 [CA 0] Center 43 (13~74) winsize 62
7579 11:52:04.009109 [CA 1] Center 43 (13~74) winsize 62
7580 11:52:04.012413 [CA 2] Center 39 (10~68) winsize 59
7581 11:52:04.015865 [CA 3] Center 39 (10~68) winsize 59
7582 11:52:04.019389 [CA 4] Center 36 (6~66) winsize 61
7583 11:52:04.022770 [CA 5] Center 36 (6~66) winsize 61
7584 11:52:04.022854
7585 11:52:04.025695 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 11:52:04.025780
7587 11:52:04.032098 [CATrainingPosCal] consider 2 rank data
7588 11:52:04.032196 u2DelayCellTimex100 = 258/100 ps
7589 11:52:04.039188 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7590 11:52:04.042025 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7591 11:52:04.046004 CA2 delay=38 (10~67),Diff = 2 PI (7 cell)
7592 11:52:04.049070 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7593 11:52:04.052352 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7594 11:52:04.055912 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7595 11:52:04.055993
7596 11:52:04.059111 CA PerBit enable=1, Macro0, CA PI delay=36
7597 11:52:04.059191
7598 11:52:04.062305 [CBTSetCACLKResult] CA Dly = 36
7599 11:52:04.065352 CS Dly: 11 (0~43)
7600 11:52:04.068684 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 11:52:04.072342 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 11:52:04.072428
7603 11:52:04.075385 ----->DramcWriteLeveling(PI) begin...
7604 11:52:04.075471 ==
7605 11:52:04.078979 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 11:52:04.085729 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 11:52:04.085811 ==
7608 11:52:04.088648 Write leveling (Byte 0): 37 => 37
7609 11:52:04.091927 Write leveling (Byte 1): 29 => 29
7610 11:52:04.092008 DramcWriteLeveling(PI) end<-----
7611 11:52:04.092072
7612 11:52:04.095181 ==
7613 11:52:04.098613 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 11:52:04.102007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 11:52:04.102092 ==
7616 11:52:04.105426 [Gating] SW mode calibration
7617 11:52:04.112007 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7618 11:52:04.115092 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7619 11:52:04.122080 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7620 11:52:04.125182 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 11:52:04.128811 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7622 11:52:04.135085 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7623 11:52:04.138312 1 4 16 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7624 11:52:04.141982 1 4 20 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
7625 11:52:04.148332 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7626 11:52:04.151626 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7627 11:52:04.154849 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7628 11:52:04.161993 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7629 11:52:04.165313 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7630 11:52:04.168117 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7631 11:52:04.175324 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
7632 11:52:04.178329 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (1 0)
7633 11:52:04.181592 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7634 11:52:04.188145 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7635 11:52:04.191476 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7636 11:52:04.195155 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7637 11:52:04.201521 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7638 11:52:04.204949 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7639 11:52:04.208111 1 6 16 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
7640 11:52:04.214668 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7641 11:52:04.217867 1 6 24 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
7642 11:52:04.221733 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 11:52:04.228107 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 11:52:04.231088 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 11:52:04.234733 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7646 11:52:04.241434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 11:52:04.244513 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 11:52:04.247781 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7649 11:52:04.254734 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7650 11:52:04.257970 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:52:04.261387 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:52:04.264548 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:52:04.271217 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:52:04.274521 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:52:04.277764 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:52:04.284415 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:52:04.287687 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 11:52:04.290931 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 11:52:04.297628 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 11:52:04.301200 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 11:52:04.304307 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 11:52:04.310982 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 11:52:04.313911 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7664 11:52:04.317384 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7665 11:52:04.320935 Total UI for P1: 0, mck2ui 16
7666 11:52:04.324174 best dqsien dly found for B0: ( 1, 9, 14)
7667 11:52:04.330568 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7668 11:52:04.334213 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7669 11:52:04.337222 Total UI for P1: 0, mck2ui 16
7670 11:52:04.340908 best dqsien dly found for B1: ( 1, 9, 24)
7671 11:52:04.344023 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7672 11:52:04.347878 best DQS1 dly(MCK, UI, PI) = (1, 9, 24)
7673 11:52:04.347959
7674 11:52:04.350902 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7675 11:52:04.354132 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 24)
7676 11:52:04.357321 [Gating] SW calibration Done
7677 11:52:04.357402 ==
7678 11:52:04.360810 Dram Type= 6, Freq= 0, CH_0, rank 0
7679 11:52:04.367033 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7680 11:52:04.367114 ==
7681 11:52:04.367178 RX Vref Scan: 0
7682 11:52:04.367265
7683 11:52:04.370299 RX Vref 0 -> 0, step: 1
7684 11:52:04.370379
7685 11:52:04.373575 RX Delay 0 -> 252, step: 8
7686 11:52:04.377028 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
7687 11:52:04.380262 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7688 11:52:04.383611 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7689 11:52:04.387052 iDelay=200, Bit 3, Center 123 (72 ~ 175) 104
7690 11:52:04.393991 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7691 11:52:04.396894 iDelay=200, Bit 5, Center 115 (64 ~ 167) 104
7692 11:52:04.400176 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
7693 11:52:04.403542 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7694 11:52:04.406901 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7695 11:52:04.413847 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7696 11:52:04.416959 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7697 11:52:04.420011 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7698 11:52:04.423624 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7699 11:52:04.426889 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7700 11:52:04.433495 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7701 11:52:04.436948 iDelay=200, Bit 15, Center 127 (72 ~ 183) 112
7702 11:52:04.437029 ==
7703 11:52:04.440220 Dram Type= 6, Freq= 0, CH_0, rank 0
7704 11:52:04.443405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7705 11:52:04.443502 ==
7706 11:52:04.446848 DQS Delay:
7707 11:52:04.446930 DQS0 = 0, DQS1 = 0
7708 11:52:04.446994 DQM Delay:
7709 11:52:04.449837 DQM0 = 129, DQM1 = 123
7710 11:52:04.449917 DQ Delay:
7711 11:52:04.453681 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =123
7712 11:52:04.456879 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =143
7713 11:52:04.463201 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7714 11:52:04.466602 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7715 11:52:04.466683
7716 11:52:04.466747
7717 11:52:04.466807 ==
7718 11:52:04.469775 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 11:52:04.472931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 11:52:04.473010 ==
7721 11:52:04.473073
7722 11:52:04.473132
7723 11:52:04.476133 TX Vref Scan disable
7724 11:52:04.479496 == TX Byte 0 ==
7725 11:52:04.483321 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7726 11:52:04.486692 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7727 11:52:04.490151 == TX Byte 1 ==
7728 11:52:04.493251 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7729 11:52:04.496338 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7730 11:52:04.496433 ==
7731 11:52:04.499758 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 11:52:04.506459 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 11:52:04.506540 ==
7734 11:52:04.518477
7735 11:52:04.521760 TX Vref early break, caculate TX vref
7736 11:52:04.524980 TX Vref=16, minBit 8, minWin=22, winSum=368
7737 11:52:04.528082 TX Vref=18, minBit 8, minWin=21, winSum=375
7738 11:52:04.531961 TX Vref=20, minBit 8, minWin=23, winSum=388
7739 11:52:04.535493 TX Vref=22, minBit 13, minWin=23, winSum=396
7740 11:52:04.538249 TX Vref=24, minBit 4, minWin=24, winSum=405
7741 11:52:04.545353 TX Vref=26, minBit 8, minWin=25, winSum=415
7742 11:52:04.548388 TX Vref=28, minBit 4, minWin=25, winSum=413
7743 11:52:04.552037 TX Vref=30, minBit 8, minWin=24, winSum=410
7744 11:52:04.555273 TX Vref=32, minBit 5, minWin=24, winSum=398
7745 11:52:04.558242 TX Vref=34, minBit 8, minWin=22, winSum=393
7746 11:52:04.564916 [TxChooseVref] Worse bit 8, Min win 25, Win sum 415, Final Vref 26
7747 11:52:04.565362
7748 11:52:04.568159 Final TX Range 0 Vref 26
7749 11:52:04.568608
7750 11:52:04.568934 ==
7751 11:52:04.571337 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 11:52:04.574680 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 11:52:04.575203 ==
7754 11:52:04.575733
7755 11:52:04.576285
7756 11:52:04.578221 TX Vref Scan disable
7757 11:52:04.584813 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7758 11:52:04.585254 == TX Byte 0 ==
7759 11:52:04.588158 u2DelayCellOfst[0]=11 cells (3 PI)
7760 11:52:04.591454 u2DelayCellOfst[1]=15 cells (4 PI)
7761 11:52:04.594740 u2DelayCellOfst[2]=11 cells (3 PI)
7762 11:52:04.598578 u2DelayCellOfst[3]=11 cells (3 PI)
7763 11:52:04.601779 u2DelayCellOfst[4]=7 cells (2 PI)
7764 11:52:04.604898 u2DelayCellOfst[5]=0 cells (0 PI)
7765 11:52:04.608190 u2DelayCellOfst[6]=15 cells (4 PI)
7766 11:52:04.611602 u2DelayCellOfst[7]=15 cells (4 PI)
7767 11:52:04.614918 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7768 11:52:04.618342 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7769 11:52:04.621566 == TX Byte 1 ==
7770 11:52:04.624823 u2DelayCellOfst[8]=3 cells (1 PI)
7771 11:52:04.625239 u2DelayCellOfst[9]=0 cells (0 PI)
7772 11:52:04.628134 u2DelayCellOfst[10]=7 cells (2 PI)
7773 11:52:04.631505 u2DelayCellOfst[11]=3 cells (1 PI)
7774 11:52:04.634677 u2DelayCellOfst[12]=11 cells (3 PI)
7775 11:52:04.637821 u2DelayCellOfst[13]=11 cells (3 PI)
7776 11:52:04.641224 u2DelayCellOfst[14]=15 cells (4 PI)
7777 11:52:04.644958 u2DelayCellOfst[15]=11 cells (3 PI)
7778 11:52:04.648139 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7779 11:52:04.654395 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7780 11:52:04.654881 DramC Write-DBI on
7781 11:52:04.655360 ==
7782 11:52:04.657808 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 11:52:04.664319 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 11:52:04.664741 ==
7785 11:52:04.665080
7786 11:52:04.665458
7787 11:52:04.665865 TX Vref Scan disable
7788 11:52:04.668067 == TX Byte 0 ==
7789 11:52:04.671472 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7790 11:52:04.674641 == TX Byte 1 ==
7791 11:52:04.677912 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
7792 11:52:04.681242 DramC Write-DBI off
7793 11:52:04.681732
7794 11:52:04.682076 [DATLAT]
7795 11:52:04.682475 Freq=1600, CH0 RK0
7796 11:52:04.682801
7797 11:52:04.684528 DATLAT Default: 0xf
7798 11:52:04.688091 0, 0xFFFF, sum = 0
7799 11:52:04.688627 1, 0xFFFF, sum = 0
7800 11:52:04.691135 2, 0xFFFF, sum = 0
7801 11:52:04.691643 3, 0xFFFF, sum = 0
7802 11:52:04.694760 4, 0xFFFF, sum = 0
7803 11:52:04.695273 5, 0xFFFF, sum = 0
7804 11:52:04.698276 6, 0xFFFF, sum = 0
7805 11:52:04.698782 7, 0xFFFF, sum = 0
7806 11:52:04.701531 8, 0xFFFF, sum = 0
7807 11:52:04.702009 9, 0xFFFF, sum = 0
7808 11:52:04.704590 10, 0xFFFF, sum = 0
7809 11:52:04.705110 11, 0xFFFF, sum = 0
7810 11:52:04.707911 12, 0xFFFF, sum = 0
7811 11:52:04.708541 13, 0xEFFF, sum = 0
7812 11:52:04.711289 14, 0x0, sum = 1
7813 11:52:04.711796 15, 0x0, sum = 2
7814 11:52:04.714497 16, 0x0, sum = 3
7815 11:52:04.715078 17, 0x0, sum = 4
7816 11:52:04.717746 best_step = 15
7817 11:52:04.718160
7818 11:52:04.718489 ==
7819 11:52:04.721097 Dram Type= 6, Freq= 0, CH_0, rank 0
7820 11:52:04.724367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7821 11:52:04.724905 ==
7822 11:52:04.727661 RX Vref Scan: 1
7823 11:52:04.728181
7824 11:52:04.728648 Set Vref Range= 24 -> 127
7825 11:52:04.728974
7826 11:52:04.730880 RX Vref 24 -> 127, step: 1
7827 11:52:04.731474
7828 11:52:04.734580 RX Delay 11 -> 252, step: 4
7829 11:52:04.734993
7830 11:52:04.737612 Set Vref, RX VrefLevel [Byte0]: 24
7831 11:52:04.740722 [Byte1]: 24
7832 11:52:04.741140
7833 11:52:04.744260 Set Vref, RX VrefLevel [Byte0]: 25
7834 11:52:04.747657 [Byte1]: 25
7835 11:52:04.751396
7836 11:52:04.751809 Set Vref, RX VrefLevel [Byte0]: 26
7837 11:52:04.754665 [Byte1]: 26
7838 11:52:04.758975
7839 11:52:04.759390 Set Vref, RX VrefLevel [Byte0]: 27
7840 11:52:04.761581 [Byte1]: 27
7841 11:52:04.766037
7842 11:52:04.766603 Set Vref, RX VrefLevel [Byte0]: 28
7843 11:52:04.769642 [Byte1]: 28
7844 11:52:04.774148
7845 11:52:04.774658 Set Vref, RX VrefLevel [Byte0]: 29
7846 11:52:04.776997 [Byte1]: 29
7847 11:52:04.780790
7848 11:52:04.780873 Set Vref, RX VrefLevel [Byte0]: 30
7849 11:52:04.784495 [Byte1]: 30
7850 11:52:04.788966
7851 11:52:04.789046 Set Vref, RX VrefLevel [Byte0]: 31
7852 11:52:04.792127 [Byte1]: 31
7853 11:52:04.796451
7854 11:52:04.796533 Set Vref, RX VrefLevel [Byte0]: 32
7855 11:52:04.799382 [Byte1]: 32
7856 11:52:04.803720
7857 11:52:04.803825 Set Vref, RX VrefLevel [Byte0]: 33
7858 11:52:04.807131 [Byte1]: 33
7859 11:52:04.811290
7860 11:52:04.811397 Set Vref, RX VrefLevel [Byte0]: 34
7861 11:52:04.814972 [Byte1]: 34
7862 11:52:04.818872
7863 11:52:04.818983 Set Vref, RX VrefLevel [Byte0]: 35
7864 11:52:04.822479 [Byte1]: 35
7865 11:52:04.826906
7866 11:52:04.826987 Set Vref, RX VrefLevel [Byte0]: 36
7867 11:52:04.829779 [Byte1]: 36
7868 11:52:04.834388
7869 11:52:04.834500 Set Vref, RX VrefLevel [Byte0]: 37
7870 11:52:04.837692 [Byte1]: 37
7871 11:52:04.842327
7872 11:52:04.842457 Set Vref, RX VrefLevel [Byte0]: 38
7873 11:52:04.845369 [Byte1]: 38
7874 11:52:04.849671
7875 11:52:04.849753 Set Vref, RX VrefLevel [Byte0]: 39
7876 11:52:04.852782 [Byte1]: 39
7877 11:52:04.857138
7878 11:52:04.857220 Set Vref, RX VrefLevel [Byte0]: 40
7879 11:52:04.860531 [Byte1]: 40
7880 11:52:04.864963
7881 11:52:04.865075 Set Vref, RX VrefLevel [Byte0]: 41
7882 11:52:04.868138 [Byte1]: 41
7883 11:52:04.872361
7884 11:52:04.872458 Set Vref, RX VrefLevel [Byte0]: 42
7885 11:52:04.875671 [Byte1]: 42
7886 11:52:04.879966
7887 11:52:04.880080 Set Vref, RX VrefLevel [Byte0]: 43
7888 11:52:04.883384 [Byte1]: 43
7889 11:52:04.887817
7890 11:52:04.887922 Set Vref, RX VrefLevel [Byte0]: 44
7891 11:52:04.891281 [Byte1]: 44
7892 11:52:04.895415
7893 11:52:04.895494 Set Vref, RX VrefLevel [Byte0]: 45
7894 11:52:04.898705 [Byte1]: 45
7895 11:52:04.903080
7896 11:52:04.903163 Set Vref, RX VrefLevel [Byte0]: 46
7897 11:52:04.906464 [Byte1]: 46
7898 11:52:04.910376
7899 11:52:04.910457 Set Vref, RX VrefLevel [Byte0]: 47
7900 11:52:04.914193 [Byte1]: 47
7901 11:52:04.918013
7902 11:52:04.918094 Set Vref, RX VrefLevel [Byte0]: 48
7903 11:52:04.921432 [Byte1]: 48
7904 11:52:04.926012
7905 11:52:04.926095 Set Vref, RX VrefLevel [Byte0]: 49
7906 11:52:04.929210 [Byte1]: 49
7907 11:52:04.933179
7908 11:52:04.933263 Set Vref, RX VrefLevel [Byte0]: 50
7909 11:52:04.936407 [Byte1]: 50
7910 11:52:04.941216
7911 11:52:04.941300 Set Vref, RX VrefLevel [Byte0]: 51
7912 11:52:04.944066 [Byte1]: 51
7913 11:52:04.948435
7914 11:52:04.948521 Set Vref, RX VrefLevel [Byte0]: 52
7915 11:52:04.951899 [Byte1]: 52
7916 11:52:04.956178
7917 11:52:04.956305 Set Vref, RX VrefLevel [Byte0]: 53
7918 11:52:04.959464 [Byte1]: 53
7919 11:52:04.963577
7920 11:52:04.963661 Set Vref, RX VrefLevel [Byte0]: 54
7921 11:52:04.966960 [Byte1]: 54
7922 11:52:04.971305
7923 11:52:04.971388 Set Vref, RX VrefLevel [Byte0]: 55
7924 11:52:04.974508 [Byte1]: 55
7925 11:52:04.978717
7926 11:52:04.978801 Set Vref, RX VrefLevel [Byte0]: 56
7927 11:52:04.982282 [Byte1]: 56
7928 11:52:04.986492
7929 11:52:04.986578 Set Vref, RX VrefLevel [Byte0]: 57
7930 11:52:04.989797 [Byte1]: 57
7931 11:52:04.994135
7932 11:52:04.994245 Set Vref, RX VrefLevel [Byte0]: 58
7933 11:52:04.997359 [Byte1]: 58
7934 11:52:05.001563
7935 11:52:05.001667 Set Vref, RX VrefLevel [Byte0]: 59
7936 11:52:05.005151 [Byte1]: 59
7937 11:52:05.009598
7938 11:52:05.009685 Set Vref, RX VrefLevel [Byte0]: 60
7939 11:52:05.013015 [Byte1]: 60
7940 11:52:05.016988
7941 11:52:05.017069 Set Vref, RX VrefLevel [Byte0]: 61
7942 11:52:05.020431 [Byte1]: 61
7943 11:52:05.024675
7944 11:52:05.024756 Set Vref, RX VrefLevel [Byte0]: 62
7945 11:52:05.027887 [Byte1]: 62
7946 11:52:05.032343
7947 11:52:05.032423 Set Vref, RX VrefLevel [Byte0]: 63
7948 11:52:05.035682 [Byte1]: 63
7949 11:52:05.039989
7950 11:52:05.040088 Set Vref, RX VrefLevel [Byte0]: 64
7951 11:52:05.043293 [Byte1]: 64
7952 11:52:05.047439
7953 11:52:05.047522 Set Vref, RX VrefLevel [Byte0]: 65
7954 11:52:05.051056 [Byte1]: 65
7955 11:52:05.055049
7956 11:52:05.055133 Set Vref, RX VrefLevel [Byte0]: 66
7957 11:52:05.058322 [Byte1]: 66
7958 11:52:05.062458
7959 11:52:05.062545 Set Vref, RX VrefLevel [Byte0]: 67
7960 11:52:05.065740 [Byte1]: 67
7961 11:52:05.070252
7962 11:52:05.070337 Set Vref, RX VrefLevel [Byte0]: 68
7963 11:52:05.073591 [Byte1]: 68
7964 11:52:05.077727
7965 11:52:05.077877 Set Vref, RX VrefLevel [Byte0]: 69
7966 11:52:05.081174 [Byte1]: 69
7967 11:52:05.085768
7968 11:52:05.085869 Set Vref, RX VrefLevel [Byte0]: 70
7969 11:52:05.089278 [Byte1]: 70
7970 11:52:05.092961
7971 11:52:05.093046 Set Vref, RX VrefLevel [Byte0]: 71
7972 11:52:05.096483 [Byte1]: 71
7973 11:52:05.100722
7974 11:52:05.100830 Set Vref, RX VrefLevel [Byte0]: 72
7975 11:52:05.103873 [Byte1]: 72
7976 11:52:05.108148
7977 11:52:05.108271 Set Vref, RX VrefLevel [Byte0]: 73
7978 11:52:05.111692 [Byte1]: 73
7979 11:52:05.116283
7980 11:52:05.116367 Set Vref, RX VrefLevel [Byte0]: 74
7981 11:52:05.119578 [Byte1]: 74
7982 11:52:05.123346
7983 11:52:05.123429 Set Vref, RX VrefLevel [Byte0]: 75
7984 11:52:05.126897 [Byte1]: 75
7985 11:52:05.131263
7986 11:52:05.131411 Set Vref, RX VrefLevel [Byte0]: 76
7987 11:52:05.134556 [Byte1]: 76
7988 11:52:05.138903
7989 11:52:05.138986 Set Vref, RX VrefLevel [Byte0]: 77
7990 11:52:05.142314 [Byte1]: 77
7991 11:52:05.146840
7992 11:52:05.146924 Set Vref, RX VrefLevel [Byte0]: 78
7993 11:52:05.149997 [Byte1]: 78
7994 11:52:05.153886
7995 11:52:05.153970 Final RX Vref Byte 0 = 64 to rank0
7996 11:52:05.157582 Final RX Vref Byte 1 = 61 to rank0
7997 11:52:05.160716 Final RX Vref Byte 0 = 64 to rank1
7998 11:52:05.163733 Final RX Vref Byte 1 = 61 to rank1==
7999 11:52:05.167225 Dram Type= 6, Freq= 0, CH_0, rank 0
8000 11:52:05.173903 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8001 11:52:05.174027 ==
8002 11:52:05.174151 DQS Delay:
8003 11:52:05.174270 DQS0 = 0, DQS1 = 0
8004 11:52:05.177286 DQM Delay:
8005 11:52:05.177367 DQM0 = 126, DQM1 = 119
8006 11:52:05.180418 DQ Delay:
8007 11:52:05.183811 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
8008 11:52:05.186926 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
8009 11:52:05.190687 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
8010 11:52:05.194067 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
8011 11:52:05.194171
8012 11:52:05.194237
8013 11:52:05.194297
8014 11:52:05.196905 [DramC_TX_OE_Calibration] TA2
8015 11:52:05.200551 Original DQ_B0 (3 6) =30, OEN = 27
8016 11:52:05.203505 Original DQ_B1 (3 6) =30, OEN = 27
8017 11:52:05.206792 24, 0x0, End_B0=24 End_B1=24
8018 11:52:05.206900 25, 0x0, End_B0=25 End_B1=25
8019 11:52:05.210285 26, 0x0, End_B0=26 End_B1=26
8020 11:52:05.213707 27, 0x0, End_B0=27 End_B1=27
8021 11:52:05.216947 28, 0x0, End_B0=28 End_B1=28
8022 11:52:05.220034 29, 0x0, End_B0=29 End_B1=29
8023 11:52:05.220119 30, 0x0, End_B0=30 End_B1=30
8024 11:52:05.223624 31, 0x4141, End_B0=30 End_B1=30
8025 11:52:05.227082 Byte0 end_step=30 best_step=27
8026 11:52:05.230378 Byte1 end_step=30 best_step=27
8027 11:52:05.233349 Byte0 TX OE(2T, 0.5T) = (3, 3)
8028 11:52:05.237082 Byte1 TX OE(2T, 0.5T) = (3, 3)
8029 11:52:05.237192
8030 11:52:05.237299
8031 11:52:05.243331 [DQSOSCAuto] RK0, (LSB)MR18= 0x1615, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
8032 11:52:05.246524 CH0 RK0: MR19=303, MR18=1615
8033 11:52:05.253319 CH0_RK0: MR19=0x303, MR18=0x1615, DQSOSC=398, MR23=63, INC=23, DEC=15
8034 11:52:05.253403
8035 11:52:05.256644 ----->DramcWriteLeveling(PI) begin...
8036 11:52:05.256727 ==
8037 11:52:05.259913 Dram Type= 6, Freq= 0, CH_0, rank 1
8038 11:52:05.263280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8039 11:52:05.263364 ==
8040 11:52:05.266394 Write leveling (Byte 0): 33 => 33
8041 11:52:05.269813 Write leveling (Byte 1): 26 => 26
8042 11:52:05.273347 DramcWriteLeveling(PI) end<-----
8043 11:52:05.273509
8044 11:52:05.273661 ==
8045 11:52:05.276420 Dram Type= 6, Freq= 0, CH_0, rank 1
8046 11:52:05.279932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8047 11:52:05.280029 ==
8048 11:52:05.283046 [Gating] SW mode calibration
8049 11:52:05.289934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8050 11:52:05.296092 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8051 11:52:05.299618 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 11:52:05.306150 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8053 11:52:05.309434 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8054 11:52:05.313080 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8055 11:52:05.319961 1 4 16 | B1->B0 | 2626 3434 | 0 1 | (0 0) (1 1)
8056 11:52:05.323137 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8057 11:52:05.326546 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8058 11:52:05.332809 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8059 11:52:05.336795 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8060 11:52:05.339479 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8061 11:52:05.346111 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
8062 11:52:05.349373 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8063 11:52:05.353191 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 0) (0 0)
8064 11:52:05.355919 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8065 11:52:05.362557 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8066 11:52:05.366021 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8067 11:52:05.369367 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8068 11:52:05.375958 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8069 11:52:05.379236 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8070 11:52:05.382635 1 6 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
8071 11:52:05.389068 1 6 16 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8072 11:52:05.392529 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8073 11:52:05.396097 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8074 11:52:05.402638 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8075 11:52:05.406284 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8076 11:52:05.409343 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 11:52:05.415801 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 11:52:05.419276 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8079 11:52:05.422576 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8080 11:52:05.429137 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8081 11:52:05.432483 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 11:52:05.435908 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 11:52:05.442404 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 11:52:05.445902 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 11:52:05.448995 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 11:52:05.455861 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 11:52:05.459169 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 11:52:05.462522 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 11:52:05.469383 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 11:52:05.472616 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 11:52:05.475918 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 11:52:05.482541 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 11:52:05.485843 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8094 11:52:05.488979 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8095 11:52:05.492333 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8096 11:52:05.496131 Total UI for P1: 0, mck2ui 16
8097 11:52:05.499281 best dqsien dly found for B0: ( 1, 9, 10)
8098 11:52:05.505632 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8099 11:52:05.508794 Total UI for P1: 0, mck2ui 16
8100 11:52:05.512094 best dqsien dly found for B1: ( 1, 9, 16)
8101 11:52:05.515352 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8102 11:52:05.518986 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8103 11:52:05.519067
8104 11:52:05.522602 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8105 11:52:05.525620 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8106 11:52:05.528776 [Gating] SW calibration Done
8107 11:52:05.528856 ==
8108 11:52:05.532171 Dram Type= 6, Freq= 0, CH_0, rank 1
8109 11:52:05.535243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8110 11:52:05.535325 ==
8111 11:52:05.538767 RX Vref Scan: 0
8112 11:52:05.538847
8113 11:52:05.541949 RX Vref 0 -> 0, step: 1
8114 11:52:05.542030
8115 11:52:05.542093 RX Delay 0 -> 252, step: 8
8116 11:52:05.548822 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8117 11:52:05.552121 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8118 11:52:05.555302 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8119 11:52:05.558643 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8120 11:52:05.562187 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8121 11:52:05.568475 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8122 11:52:05.571942 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8123 11:52:05.574958 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8124 11:52:05.578095 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8125 11:52:05.581409 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8126 11:52:05.588117 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8127 11:52:05.591735 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8128 11:52:05.595010 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8129 11:52:05.598282 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8130 11:52:05.601557 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8131 11:52:05.607933 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8132 11:52:05.608018 ==
8133 11:52:05.611363 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 11:52:05.614681 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 11:52:05.614766 ==
8136 11:52:05.614851 DQS Delay:
8137 11:52:05.617932 DQS0 = 0, DQS1 = 0
8138 11:52:05.618016 DQM Delay:
8139 11:52:05.621595 DQM0 = 127, DQM1 = 121
8140 11:52:05.621679 DQ Delay:
8141 11:52:05.624423 DQ0 =127, DQ1 =131, DQ2 =123, DQ3 =123
8142 11:52:05.627924 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8143 11:52:05.631441 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8144 11:52:05.638238 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8145 11:52:05.638323
8146 11:52:05.638409
8147 11:52:05.638490 ==
8148 11:52:05.641527 Dram Type= 6, Freq= 0, CH_0, rank 1
8149 11:52:05.644920 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8150 11:52:05.645005 ==
8151 11:52:05.645092
8152 11:52:05.645176
8153 11:52:05.647892 TX Vref Scan disable
8154 11:52:05.647977 == TX Byte 0 ==
8155 11:52:05.654591 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8156 11:52:05.657644 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8157 11:52:05.657728 == TX Byte 1 ==
8158 11:52:05.664232 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8159 11:52:05.667873 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8160 11:52:05.667955 ==
8161 11:52:05.671145 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 11:52:05.674336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 11:52:05.674418 ==
8164 11:52:05.689139
8165 11:52:05.692452 TX Vref early break, caculate TX vref
8166 11:52:05.695532 TX Vref=16, minBit 8, minWin=21, winSum=364
8167 11:52:05.698906 TX Vref=18, minBit 0, minWin=23, winSum=374
8168 11:52:05.702145 TX Vref=20, minBit 0, minWin=23, winSum=382
8169 11:52:05.705430 TX Vref=22, minBit 1, minWin=23, winSum=391
8170 11:52:05.708630 TX Vref=24, minBit 1, minWin=24, winSum=400
8171 11:52:05.715018 TX Vref=26, minBit 0, minWin=25, winSum=407
8172 11:52:05.718944 TX Vref=28, minBit 0, minWin=25, winSum=410
8173 11:52:05.721700 TX Vref=30, minBit 8, minWin=24, winSum=404
8174 11:52:05.725357 TX Vref=32, minBit 8, minWin=23, winSum=394
8175 11:52:05.728542 TX Vref=34, minBit 8, minWin=23, winSum=384
8176 11:52:05.735368 [TxChooseVref] Worse bit 0, Min win 25, Win sum 410, Final Vref 28
8177 11:52:05.735454
8178 11:52:05.738449 Final TX Range 0 Vref 28
8179 11:52:05.738533
8180 11:52:05.738618 ==
8181 11:52:05.742152 Dram Type= 6, Freq= 0, CH_0, rank 1
8182 11:52:05.745403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8183 11:52:05.745491 ==
8184 11:52:05.745577
8185 11:52:05.745658
8186 11:52:05.748536 TX Vref Scan disable
8187 11:52:05.755296 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8188 11:52:05.755381 == TX Byte 0 ==
8189 11:52:05.758790 u2DelayCellOfst[0]=15 cells (4 PI)
8190 11:52:05.762369 u2DelayCellOfst[1]=18 cells (5 PI)
8191 11:52:05.765176 u2DelayCellOfst[2]=15 cells (4 PI)
8192 11:52:05.768402 u2DelayCellOfst[3]=15 cells (4 PI)
8193 11:52:05.771794 u2DelayCellOfst[4]=11 cells (3 PI)
8194 11:52:05.775134 u2DelayCellOfst[5]=0 cells (0 PI)
8195 11:52:05.778342 u2DelayCellOfst[6]=22 cells (6 PI)
8196 11:52:05.781860 u2DelayCellOfst[7]=18 cells (5 PI)
8197 11:52:05.785063 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8198 11:52:05.788383 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8199 11:52:05.791981 == TX Byte 1 ==
8200 11:52:05.792089 u2DelayCellOfst[8]=0 cells (0 PI)
8201 11:52:05.794991 u2DelayCellOfst[9]=0 cells (0 PI)
8202 11:52:05.798875 u2DelayCellOfst[10]=7 cells (2 PI)
8203 11:52:05.801889 u2DelayCellOfst[11]=3 cells (1 PI)
8204 11:52:05.805105 u2DelayCellOfst[12]=15 cells (4 PI)
8205 11:52:05.808465 u2DelayCellOfst[13]=11 cells (3 PI)
8206 11:52:05.811749 u2DelayCellOfst[14]=15 cells (4 PI)
8207 11:52:05.815259 u2DelayCellOfst[15]=11 cells (3 PI)
8208 11:52:05.818599 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8209 11:52:05.825155 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8210 11:52:05.825230 DramC Write-DBI on
8211 11:52:05.825292 ==
8212 11:52:05.828257 Dram Type= 6, Freq= 0, CH_0, rank 1
8213 11:52:05.831670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8214 11:52:05.834972 ==
8215 11:52:05.835041
8216 11:52:05.835101
8217 11:52:05.835161 TX Vref Scan disable
8218 11:52:05.838142 == TX Byte 0 ==
8219 11:52:05.841897 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
8220 11:52:05.845167 == TX Byte 1 ==
8221 11:52:05.848344 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8222 11:52:05.851820 DramC Write-DBI off
8223 11:52:05.851898
8224 11:52:05.851960 [DATLAT]
8225 11:52:05.852019 Freq=1600, CH0 RK1
8226 11:52:05.852076
8227 11:52:05.855176 DATLAT Default: 0xf
8228 11:52:05.855253 0, 0xFFFF, sum = 0
8229 11:52:05.858625 1, 0xFFFF, sum = 0
8230 11:52:05.858704 2, 0xFFFF, sum = 0
8231 11:52:05.861893 3, 0xFFFF, sum = 0
8232 11:52:05.865260 4, 0xFFFF, sum = 0
8233 11:52:05.865335 5, 0xFFFF, sum = 0
8234 11:52:05.868342 6, 0xFFFF, sum = 0
8235 11:52:05.868420 7, 0xFFFF, sum = 0
8236 11:52:05.871645 8, 0xFFFF, sum = 0
8237 11:52:05.871724 9, 0xFFFF, sum = 0
8238 11:52:05.875027 10, 0xFFFF, sum = 0
8239 11:52:05.875104 11, 0xFFFF, sum = 0
8240 11:52:05.878719 12, 0xFFFF, sum = 0
8241 11:52:05.878795 13, 0xCFFF, sum = 0
8242 11:52:05.881464 14, 0x0, sum = 1
8243 11:52:05.881544 15, 0x0, sum = 2
8244 11:52:05.884690 16, 0x0, sum = 3
8245 11:52:05.884759 17, 0x0, sum = 4
8246 11:52:05.888006 best_step = 15
8247 11:52:05.888116
8248 11:52:05.888240 ==
8249 11:52:05.891319 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 11:52:05.894583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 11:52:05.894683 ==
8252 11:52:05.898077 RX Vref Scan: 0
8253 11:52:05.898159
8254 11:52:05.898222 RX Vref 0 -> 0, step: 1
8255 11:52:05.898282
8256 11:52:05.901440 RX Delay 3 -> 252, step: 4
8257 11:52:05.904573 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8258 11:52:05.911624 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8259 11:52:05.914818 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8260 11:52:05.917942 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8261 11:52:05.921357 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8262 11:52:05.924893 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8263 11:52:05.931374 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8264 11:52:05.934641 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8265 11:52:05.938082 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8266 11:52:05.941084 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8267 11:52:05.944788 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8268 11:52:05.951613 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8269 11:52:05.954506 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8270 11:52:05.957983 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8271 11:52:05.961067 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8272 11:52:05.967818 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8273 11:52:05.967890 ==
8274 11:52:05.971159 Dram Type= 6, Freq= 0, CH_0, rank 1
8275 11:52:05.974386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 11:52:05.974487 ==
8277 11:52:05.974552 DQS Delay:
8278 11:52:05.977888 DQS0 = 0, DQS1 = 0
8279 11:52:05.977953 DQM Delay:
8280 11:52:05.981335 DQM0 = 124, DQM1 = 118
8281 11:52:05.981405 DQ Delay:
8282 11:52:05.984412 DQ0 =124, DQ1 =124, DQ2 =120, DQ3 =122
8283 11:52:05.987380 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8284 11:52:05.991179 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8285 11:52:05.994596 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8286 11:52:05.994667
8287 11:52:05.994727
8288 11:52:05.994784
8289 11:52:05.997792 [DramC_TX_OE_Calibration] TA2
8290 11:52:06.001165 Original DQ_B0 (3 6) =30, OEN = 27
8291 11:52:06.004184 Original DQ_B1 (3 6) =30, OEN = 27
8292 11:52:06.007489 24, 0x0, End_B0=24 End_B1=24
8293 11:52:06.010649 25, 0x0, End_B0=25 End_B1=25
8294 11:52:06.014017 26, 0x0, End_B0=26 End_B1=26
8295 11:52:06.014089 27, 0x0, End_B0=27 End_B1=27
8296 11:52:06.018030 28, 0x0, End_B0=28 End_B1=28
8297 11:52:06.020676 29, 0x0, End_B0=29 End_B1=29
8298 11:52:06.024092 30, 0x0, End_B0=30 End_B1=30
8299 11:52:06.027227 31, 0x4545, End_B0=30 End_B1=30
8300 11:52:06.027301 Byte0 end_step=30 best_step=27
8301 11:52:06.030730 Byte1 end_step=30 best_step=27
8302 11:52:06.033854 Byte0 TX OE(2T, 0.5T) = (3, 3)
8303 11:52:06.037351 Byte1 TX OE(2T, 0.5T) = (3, 3)
8304 11:52:06.037438
8305 11:52:06.037501
8306 11:52:06.043876 [DQSOSCAuto] RK1, (LSB)MR18= 0x2512, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 391 ps
8307 11:52:06.047002 CH0 RK1: MR19=303, MR18=2512
8308 11:52:06.053989 CH0_RK1: MR19=0x303, MR18=0x2512, DQSOSC=391, MR23=63, INC=24, DEC=16
8309 11:52:06.057291 [RxdqsGatingPostProcess] freq 1600
8310 11:52:06.063719 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8311 11:52:06.066929 best DQS0 dly(2T, 0.5T) = (1, 1)
8312 11:52:06.067013 best DQS1 dly(2T, 0.5T) = (1, 1)
8313 11:52:06.070357 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8314 11:52:06.073712 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8315 11:52:06.077006 best DQS0 dly(2T, 0.5T) = (1, 1)
8316 11:52:06.080172 best DQS1 dly(2T, 0.5T) = (1, 1)
8317 11:52:06.084038 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8318 11:52:06.087159 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8319 11:52:06.090260 Pre-setting of DQS Precalculation
8320 11:52:06.093757 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8321 11:52:06.097029 ==
8322 11:52:06.097109 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 11:52:06.103501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 11:52:06.103581 ==
8325 11:52:06.106856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8326 11:52:06.113783 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8327 11:52:06.117013 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8328 11:52:06.123577 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8329 11:52:06.131656 [CA 0] Center 41 (12~70) winsize 59
8330 11:52:06.134790 [CA 1] Center 42 (12~72) winsize 61
8331 11:52:06.138343 [CA 2] Center 37 (8~66) winsize 59
8332 11:52:06.141510 [CA 3] Center 37 (8~66) winsize 59
8333 11:52:06.145022 [CA 4] Center 37 (8~67) winsize 60
8334 11:52:06.148167 [CA 5] Center 35 (6~65) winsize 60
8335 11:52:06.148313
8336 11:52:06.151539 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8337 11:52:06.151615
8338 11:52:06.154878 [CATrainingPosCal] consider 1 rank data
8339 11:52:06.158520 u2DelayCellTimex100 = 258/100 ps
8340 11:52:06.161483 CA0 delay=41 (12~70),Diff = 6 PI (22 cell)
8341 11:52:06.168404 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8342 11:52:06.171797 CA2 delay=37 (8~66),Diff = 2 PI (7 cell)
8343 11:52:06.174563 CA3 delay=37 (8~66),Diff = 2 PI (7 cell)
8344 11:52:06.178367 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8345 11:52:06.181179 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8346 11:52:06.181261
8347 11:52:06.185069 CA PerBit enable=1, Macro0, CA PI delay=35
8348 11:52:06.185138
8349 11:52:06.188150 [CBTSetCACLKResult] CA Dly = 35
8350 11:52:06.191439 CS Dly: 9 (0~40)
8351 11:52:06.194568 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8352 11:52:06.198189 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8353 11:52:06.198261 ==
8354 11:52:06.201390 Dram Type= 6, Freq= 0, CH_1, rank 1
8355 11:52:06.204655 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 11:52:06.204725 ==
8357 11:52:06.211139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 11:52:06.214435 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 11:52:06.221064 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 11:52:06.224463 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 11:52:06.234862 [CA 0] Center 42 (13~71) winsize 59
8362 11:52:06.237794 [CA 1] Center 42 (12~72) winsize 61
8363 11:52:06.241627 [CA 2] Center 38 (9~67) winsize 59
8364 11:52:06.244728 [CA 3] Center 36 (7~66) winsize 60
8365 11:52:06.248042 [CA 4] Center 38 (8~68) winsize 61
8366 11:52:06.251316 [CA 5] Center 36 (6~66) winsize 61
8367 11:52:06.251396
8368 11:52:06.254624 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8369 11:52:06.254706
8370 11:52:06.258241 [CATrainingPosCal] consider 2 rank data
8371 11:52:06.261400 u2DelayCellTimex100 = 258/100 ps
8372 11:52:06.264443 CA0 delay=41 (13~70),Diff = 6 PI (22 cell)
8373 11:52:06.271055 CA1 delay=42 (12~72),Diff = 7 PI (26 cell)
8374 11:52:06.274763 CA2 delay=37 (9~66),Diff = 2 PI (7 cell)
8375 11:52:06.277818 CA3 delay=37 (8~66),Diff = 2 PI (7 cell)
8376 11:52:06.281351 CA4 delay=37 (8~67),Diff = 2 PI (7 cell)
8377 11:52:06.284773 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
8378 11:52:06.284853
8379 11:52:06.288033 CA PerBit enable=1, Macro0, CA PI delay=35
8380 11:52:06.288138
8381 11:52:06.291278 [CBTSetCACLKResult] CA Dly = 35
8382 11:52:06.294377 CS Dly: 10 (0~43)
8383 11:52:06.297534 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 11:52:06.301193 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 11:52:06.301272
8386 11:52:06.304573 ----->DramcWriteLeveling(PI) begin...
8387 11:52:06.304653 ==
8388 11:52:06.307600 Dram Type= 6, Freq= 0, CH_1, rank 0
8389 11:52:06.310970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8390 11:52:06.314342 ==
8391 11:52:06.314422 Write leveling (Byte 0): 27 => 27
8392 11:52:06.317524 Write leveling (Byte 1): 29 => 29
8393 11:52:06.321357 DramcWriteLeveling(PI) end<-----
8394 11:52:06.321434
8395 11:52:06.321495 ==
8396 11:52:06.324172 Dram Type= 6, Freq= 0, CH_1, rank 0
8397 11:52:06.330812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 11:52:06.330893 ==
8399 11:52:06.334236 [Gating] SW mode calibration
8400 11:52:06.340637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8401 11:52:06.344139 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8402 11:52:06.350566 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 11:52:06.354306 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8404 11:52:06.357523 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8405 11:52:06.363956 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8406 11:52:06.367372 1 4 16 | B1->B0 | 3434 3433 | 1 1 | (1 1) (1 1)
8407 11:52:06.370582 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8408 11:52:06.377489 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8409 11:52:06.380349 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8410 11:52:06.383957 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 11:52:06.390526 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 11:52:06.394394 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 11:52:06.396847 1 5 12 | B1->B0 | 3232 3232 | 0 1 | (0 1) (1 0)
8414 11:52:06.403849 1 5 16 | B1->B0 | 2626 2323 | 0 1 | (1 0) (1 0)
8415 11:52:06.407136 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8416 11:52:06.410326 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8417 11:52:06.413828 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8418 11:52:06.420147 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 11:52:06.423701 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 11:52:06.427003 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 11:52:06.433702 1 6 12 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
8422 11:52:06.436987 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8423 11:52:06.440309 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8424 11:52:06.446850 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8425 11:52:06.449986 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8426 11:52:06.453347 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 11:52:06.459614 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 11:52:06.463483 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 11:52:06.466578 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:52:06.473326 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8431 11:52:06.476552 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 11:52:06.479922 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 11:52:06.486333 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 11:52:06.489525 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 11:52:06.493150 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 11:52:06.499748 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 11:52:06.503227 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 11:52:06.505973 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 11:52:06.512943 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 11:52:06.515973 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 11:52:06.519803 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 11:52:06.525701 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 11:52:06.529068 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 11:52:06.532876 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 11:52:06.539140 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8446 11:52:06.542909 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8447 11:52:06.546103 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8448 11:52:06.549457 Total UI for P1: 0, mck2ui 16
8449 11:52:06.552556 best dqsien dly found for B0: ( 1, 9, 14)
8450 11:52:06.555942 Total UI for P1: 0, mck2ui 16
8451 11:52:06.559146 best dqsien dly found for B1: ( 1, 9, 14)
8452 11:52:06.562353 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8453 11:52:06.565591 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8454 11:52:06.565679
8455 11:52:06.572449 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8456 11:52:06.575870 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8457 11:52:06.578624 [Gating] SW calibration Done
8458 11:52:06.578706 ==
8459 11:52:06.581928 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 11:52:06.585863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 11:52:06.585944 ==
8462 11:52:06.586009 RX Vref Scan: 0
8463 11:52:06.588814
8464 11:52:06.588895 RX Vref 0 -> 0, step: 1
8465 11:52:06.588959
8466 11:52:06.592063 RX Delay 0 -> 252, step: 8
8467 11:52:06.595363 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8468 11:52:06.598902 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8469 11:52:06.605387 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8470 11:52:06.608464 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8471 11:52:06.611991 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8472 11:52:06.615218 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8473 11:52:06.618918 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8474 11:52:06.625327 iDelay=208, Bit 7, Center 131 (72 ~ 191) 120
8475 11:52:06.628953 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8476 11:52:06.631933 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8477 11:52:06.634972 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8478 11:52:06.638497 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8479 11:52:06.645050 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8480 11:52:06.648291 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8481 11:52:06.651954 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8482 11:52:06.655325 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8483 11:52:06.655418 ==
8484 11:52:06.658406 Dram Type= 6, Freq= 0, CH_1, rank 0
8485 11:52:06.664954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8486 11:52:06.665067 ==
8487 11:52:06.665154 DQS Delay:
8488 11:52:06.668546 DQS0 = 0, DQS1 = 0
8489 11:52:06.668667 DQM Delay:
8490 11:52:06.671331 DQM0 = 133, DQM1 = 125
8491 11:52:06.671451 DQ Delay:
8492 11:52:06.675006 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8493 11:52:06.678390 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =131
8494 11:52:06.681703 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8495 11:52:06.684478 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8496 11:52:06.684613
8497 11:52:06.684717
8498 11:52:06.684815 ==
8499 11:52:06.688160 Dram Type= 6, Freq= 0, CH_1, rank 0
8500 11:52:06.694495 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8501 11:52:06.694576 ==
8502 11:52:06.694640
8503 11:52:06.694700
8504 11:52:06.694757 TX Vref Scan disable
8505 11:52:06.698241 == TX Byte 0 ==
8506 11:52:06.701416 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8507 11:52:06.708094 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8508 11:52:06.708175 == TX Byte 1 ==
8509 11:52:06.711312 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8510 11:52:06.718153 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8511 11:52:06.718234 ==
8512 11:52:06.720947 Dram Type= 6, Freq= 0, CH_1, rank 0
8513 11:52:06.724367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8514 11:52:06.724449 ==
8515 11:52:06.736853
8516 11:52:06.740193 TX Vref early break, caculate TX vref
8517 11:52:06.743736 TX Vref=16, minBit 11, minWin=20, winSum=361
8518 11:52:06.746925 TX Vref=18, minBit 11, minWin=21, winSum=365
8519 11:52:06.750112 TX Vref=20, minBit 11, minWin=22, winSum=376
8520 11:52:06.753781 TX Vref=22, minBit 8, minWin=23, winSum=389
8521 11:52:06.757167 TX Vref=24, minBit 1, minWin=24, winSum=398
8522 11:52:06.763615 TX Vref=26, minBit 11, minWin=24, winSum=407
8523 11:52:06.766954 TX Vref=28, minBit 8, minWin=25, winSum=413
8524 11:52:06.770122 TX Vref=30, minBit 1, minWin=24, winSum=404
8525 11:52:06.773417 TX Vref=32, minBit 1, minWin=23, winSum=397
8526 11:52:06.776569 TX Vref=34, minBit 8, minWin=23, winSum=391
8527 11:52:06.783600 [TxChooseVref] Worse bit 8, Min win 25, Win sum 413, Final Vref 28
8528 11:52:06.783681
8529 11:52:06.786379 Final TX Range 0 Vref 28
8530 11:52:06.786460
8531 11:52:06.786525 ==
8532 11:52:06.789838 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 11:52:06.793020 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 11:52:06.793103 ==
8535 11:52:06.793167
8536 11:52:06.793227
8537 11:52:06.796824 TX Vref Scan disable
8538 11:52:06.803162 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8539 11:52:06.803243 == TX Byte 0 ==
8540 11:52:06.806413 u2DelayCellOfst[0]=22 cells (6 PI)
8541 11:52:06.810121 u2DelayCellOfst[1]=15 cells (4 PI)
8542 11:52:06.812991 u2DelayCellOfst[2]=0 cells (0 PI)
8543 11:52:06.816126 u2DelayCellOfst[3]=7 cells (2 PI)
8544 11:52:06.819490 u2DelayCellOfst[4]=11 cells (3 PI)
8545 11:52:06.823498 u2DelayCellOfst[5]=22 cells (6 PI)
8546 11:52:06.826373 u2DelayCellOfst[6]=22 cells (6 PI)
8547 11:52:06.829893 u2DelayCellOfst[7]=7 cells (2 PI)
8548 11:52:06.833133 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8549 11:52:06.836504 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8550 11:52:06.839538 == TX Byte 1 ==
8551 11:52:06.842907 u2DelayCellOfst[8]=0 cells (0 PI)
8552 11:52:06.842988 u2DelayCellOfst[9]=7 cells (2 PI)
8553 11:52:06.845999 u2DelayCellOfst[10]=18 cells (5 PI)
8554 11:52:06.849651 u2DelayCellOfst[11]=11 cells (3 PI)
8555 11:52:06.852733 u2DelayCellOfst[12]=22 cells (6 PI)
8556 11:52:06.856048 u2DelayCellOfst[13]=22 cells (6 PI)
8557 11:52:06.859188 u2DelayCellOfst[14]=22 cells (6 PI)
8558 11:52:06.862481 u2DelayCellOfst[15]=22 cells (6 PI)
8559 11:52:06.869199 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8560 11:52:06.872533 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8561 11:52:06.872614 DramC Write-DBI on
8562 11:52:06.872678 ==
8563 11:52:06.875624 Dram Type= 6, Freq= 0, CH_1, rank 0
8564 11:52:06.882544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8565 11:52:06.882625 ==
8566 11:52:06.882688
8567 11:52:06.882747
8568 11:52:06.885790 TX Vref Scan disable
8569 11:52:06.885870 == TX Byte 0 ==
8570 11:52:06.892185 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8571 11:52:06.892275 == TX Byte 1 ==
8572 11:52:06.895606 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8573 11:52:06.898872 DramC Write-DBI off
8574 11:52:06.898952
8575 11:52:06.899015 [DATLAT]
8576 11:52:06.902007 Freq=1600, CH1 RK0
8577 11:52:06.902088
8578 11:52:06.902151 DATLAT Default: 0xf
8579 11:52:06.905743 0, 0xFFFF, sum = 0
8580 11:52:06.905825 1, 0xFFFF, sum = 0
8581 11:52:06.908551 2, 0xFFFF, sum = 0
8582 11:52:06.908632 3, 0xFFFF, sum = 0
8583 11:52:06.912185 4, 0xFFFF, sum = 0
8584 11:52:06.912290 5, 0xFFFF, sum = 0
8585 11:52:06.915382 6, 0xFFFF, sum = 0
8586 11:52:06.915464 7, 0xFFFF, sum = 0
8587 11:52:06.918735 8, 0xFFFF, sum = 0
8588 11:52:06.921956 9, 0xFFFF, sum = 0
8589 11:52:06.922038 10, 0xFFFF, sum = 0
8590 11:52:06.925340 11, 0xFFFF, sum = 0
8591 11:52:06.925422 12, 0xFFFF, sum = 0
8592 11:52:06.928633 13, 0x8FFF, sum = 0
8593 11:52:06.928715 14, 0x0, sum = 1
8594 11:52:06.932217 15, 0x0, sum = 2
8595 11:52:06.932312 16, 0x0, sum = 3
8596 11:52:06.935374 17, 0x0, sum = 4
8597 11:52:06.935456 best_step = 15
8598 11:52:06.935520
8599 11:52:06.935579 ==
8600 11:52:06.939000 Dram Type= 6, Freq= 0, CH_1, rank 0
8601 11:52:06.942239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8602 11:52:06.942320 ==
8603 11:52:06.945228 RX Vref Scan: 1
8604 11:52:06.945309
8605 11:52:06.948541 Set Vref Range= 24 -> 127
8606 11:52:06.948622
8607 11:52:06.948686 RX Vref 24 -> 127, step: 1
8608 11:52:06.948746
8609 11:52:06.951898 RX Delay 11 -> 252, step: 4
8610 11:52:06.951978
8611 11:52:06.955221 Set Vref, RX VrefLevel [Byte0]: 24
8612 11:52:06.958427 [Byte1]: 24
8613 11:52:06.962212
8614 11:52:06.962292 Set Vref, RX VrefLevel [Byte0]: 25
8615 11:52:06.965326 [Byte1]: 25
8616 11:52:06.969638
8617 11:52:06.969733 Set Vref, RX VrefLevel [Byte0]: 26
8618 11:52:06.972754 [Byte1]: 26
8619 11:52:06.977397
8620 11:52:06.977478 Set Vref, RX VrefLevel [Byte0]: 27
8621 11:52:06.980168 [Byte1]: 27
8622 11:52:06.984742
8623 11:52:06.984828 Set Vref, RX VrefLevel [Byte0]: 28
8624 11:52:06.987764 [Byte1]: 28
8625 11:52:06.992103
8626 11:52:06.992216 Set Vref, RX VrefLevel [Byte0]: 29
8627 11:52:06.995468 [Byte1]: 29
8628 11:52:06.999923
8629 11:52:07.000039 Set Vref, RX VrefLevel [Byte0]: 30
8630 11:52:07.003199 [Byte1]: 30
8631 11:52:07.007440
8632 11:52:07.007544 Set Vref, RX VrefLevel [Byte0]: 31
8633 11:52:07.010707 [Byte1]: 31
8634 11:52:07.015219
8635 11:52:07.015381 Set Vref, RX VrefLevel [Byte0]: 32
8636 11:52:07.018462 [Byte1]: 32
8637 11:52:07.022616
8638 11:52:07.022775 Set Vref, RX VrefLevel [Byte0]: 33
8639 11:52:07.025941 [Byte1]: 33
8640 11:52:07.030322
8641 11:52:07.030480 Set Vref, RX VrefLevel [Byte0]: 34
8642 11:52:07.033692 [Byte1]: 34
8643 11:52:07.038126
8644 11:52:07.038437 Set Vref, RX VrefLevel [Byte0]: 35
8645 11:52:07.041162 [Byte1]: 35
8646 11:52:07.045512
8647 11:52:07.045903 Set Vref, RX VrefLevel [Byte0]: 36
8648 11:52:07.049074 [Byte1]: 36
8649 11:52:07.053567
8650 11:52:07.053984 Set Vref, RX VrefLevel [Byte0]: 37
8651 11:52:07.056832 [Byte1]: 37
8652 11:52:07.061260
8653 11:52:07.061638 Set Vref, RX VrefLevel [Byte0]: 38
8654 11:52:07.064256 [Byte1]: 38
8655 11:52:07.068584
8656 11:52:07.068987 Set Vref, RX VrefLevel [Byte0]: 39
8657 11:52:07.071911 [Byte1]: 39
8658 11:52:07.076143
8659 11:52:07.076569 Set Vref, RX VrefLevel [Byte0]: 40
8660 11:52:07.079502 [Byte1]: 40
8661 11:52:07.083946
8662 11:52:07.084361 Set Vref, RX VrefLevel [Byte0]: 41
8663 11:52:07.087177 [Byte1]: 41
8664 11:52:07.092095
8665 11:52:07.092534 Set Vref, RX VrefLevel [Byte0]: 42
8666 11:52:07.094868 [Byte1]: 42
8667 11:52:07.099111
8668 11:52:07.099494 Set Vref, RX VrefLevel [Byte0]: 43
8669 11:52:07.102600 [Byte1]: 43
8670 11:52:07.106741
8671 11:52:07.107121 Set Vref, RX VrefLevel [Byte0]: 44
8672 11:52:07.109558 [Byte1]: 44
8673 11:52:07.113939
8674 11:52:07.114020 Set Vref, RX VrefLevel [Byte0]: 45
8675 11:52:07.117247 [Byte1]: 45
8676 11:52:07.121856
8677 11:52:07.121936 Set Vref, RX VrefLevel [Byte0]: 46
8678 11:52:07.125084 [Byte1]: 46
8679 11:52:07.129154
8680 11:52:07.129234 Set Vref, RX VrefLevel [Byte0]: 47
8681 11:52:07.132442 [Byte1]: 47
8682 11:52:07.136817
8683 11:52:07.136897 Set Vref, RX VrefLevel [Byte0]: 48
8684 11:52:07.140065 [Byte1]: 48
8685 11:52:07.144461
8686 11:52:07.144541 Set Vref, RX VrefLevel [Byte0]: 49
8687 11:52:07.148110 [Byte1]: 49
8688 11:52:07.152135
8689 11:52:07.152274 Set Vref, RX VrefLevel [Byte0]: 50
8690 11:52:07.155555 [Byte1]: 50
8691 11:52:07.159641
8692 11:52:07.159753 Set Vref, RX VrefLevel [Byte0]: 51
8693 11:52:07.163049 [Byte1]: 51
8694 11:52:07.167339
8695 11:52:07.167477 Set Vref, RX VrefLevel [Byte0]: 52
8696 11:52:07.170445 [Byte1]: 52
8697 11:52:07.174773
8698 11:52:07.174875 Set Vref, RX VrefLevel [Byte0]: 53
8699 11:52:07.178247 [Byte1]: 53
8700 11:52:07.182200
8701 11:52:07.182337 Set Vref, RX VrefLevel [Byte0]: 54
8702 11:52:07.185484 [Byte1]: 54
8703 11:52:07.189974
8704 11:52:07.190059 Set Vref, RX VrefLevel [Byte0]: 55
8705 11:52:07.193317 [Byte1]: 55
8706 11:52:07.198130
8707 11:52:07.198209 Set Vref, RX VrefLevel [Byte0]: 56
8708 11:52:07.201280 [Byte1]: 56
8709 11:52:07.205573
8710 11:52:07.205679 Set Vref, RX VrefLevel [Byte0]: 57
8711 11:52:07.208854 [Byte1]: 57
8712 11:52:07.213224
8713 11:52:07.213314 Set Vref, RX VrefLevel [Byte0]: 58
8714 11:52:07.216129 [Byte1]: 58
8715 11:52:07.220640
8716 11:52:07.220719 Set Vref, RX VrefLevel [Byte0]: 59
8717 11:52:07.224121 [Byte1]: 59
8718 11:52:07.228000
8719 11:52:07.228105 Set Vref, RX VrefLevel [Byte0]: 60
8720 11:52:07.231422 [Byte1]: 60
8721 11:52:07.236025
8722 11:52:07.236134 Set Vref, RX VrefLevel [Byte0]: 61
8723 11:52:07.238946 [Byte1]: 61
8724 11:52:07.243260
8725 11:52:07.243365 Set Vref, RX VrefLevel [Byte0]: 62
8726 11:52:07.246913 [Byte1]: 62
8727 11:52:07.251065
8728 11:52:07.251146 Set Vref, RX VrefLevel [Byte0]: 63
8729 11:52:07.254309 [Byte1]: 63
8730 11:52:07.258831
8731 11:52:07.258911 Set Vref, RX VrefLevel [Byte0]: 64
8732 11:52:07.261996 [Byte1]: 64
8733 11:52:07.266593
8734 11:52:07.266665 Set Vref, RX VrefLevel [Byte0]: 65
8735 11:52:07.269844 [Byte1]: 65
8736 11:52:07.274189
8737 11:52:07.274262 Set Vref, RX VrefLevel [Byte0]: 66
8738 11:52:07.277285 [Byte1]: 66
8739 11:52:07.281619
8740 11:52:07.281692 Set Vref, RX VrefLevel [Byte0]: 67
8741 11:52:07.284948 [Byte1]: 67
8742 11:52:07.289440
8743 11:52:07.289511 Set Vref, RX VrefLevel [Byte0]: 68
8744 11:52:07.292743 [Byte1]: 68
8745 11:52:07.296580
8746 11:52:07.296650 Set Vref, RX VrefLevel [Byte0]: 69
8747 11:52:07.300058 [Byte1]: 69
8748 11:52:07.304547
8749 11:52:07.304622 Set Vref, RX VrefLevel [Byte0]: 70
8750 11:52:07.307740 [Byte1]: 70
8751 11:52:07.311802
8752 11:52:07.311909 Final RX Vref Byte 0 = 56 to rank0
8753 11:52:07.315243 Final RX Vref Byte 1 = 54 to rank0
8754 11:52:07.318825 Final RX Vref Byte 0 = 56 to rank1
8755 11:52:07.321707 Final RX Vref Byte 1 = 54 to rank1==
8756 11:52:07.325191 Dram Type= 6, Freq= 0, CH_1, rank 0
8757 11:52:07.331664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 11:52:07.331743 ==
8759 11:52:07.331821 DQS Delay:
8760 11:52:07.331893 DQS0 = 0, DQS1 = 0
8761 11:52:07.334972 DQM Delay:
8762 11:52:07.335072 DQM0 = 131, DQM1 = 123
8763 11:52:07.338401 DQ Delay:
8764 11:52:07.341777 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8765 11:52:07.344953 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8766 11:52:07.348475 DQ8 =108, DQ9 =114, DQ10 =122, DQ11 =116
8767 11:52:07.351537 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8768 11:52:07.351639
8769 11:52:07.351736
8770 11:52:07.351830
8771 11:52:07.355274 [DramC_TX_OE_Calibration] TA2
8772 11:52:07.358646 Original DQ_B0 (3 6) =30, OEN = 27
8773 11:52:07.361496 Original DQ_B1 (3 6) =30, OEN = 27
8774 11:52:07.365425 24, 0x0, End_B0=24 End_B1=24
8775 11:52:07.365500 25, 0x0, End_B0=25 End_B1=25
8776 11:52:07.368143 26, 0x0, End_B0=26 End_B1=26
8777 11:52:07.371468 27, 0x0, End_B0=27 End_B1=27
8778 11:52:07.375121 28, 0x0, End_B0=28 End_B1=28
8779 11:52:07.377971 29, 0x0, End_B0=29 End_B1=29
8780 11:52:07.378047 30, 0x0, End_B0=30 End_B1=30
8781 11:52:07.381724 31, 0x4141, End_B0=30 End_B1=30
8782 11:52:07.384470 Byte0 end_step=30 best_step=27
8783 11:52:07.388053 Byte1 end_step=30 best_step=27
8784 11:52:07.391368 Byte0 TX OE(2T, 0.5T) = (3, 3)
8785 11:52:07.394737 Byte1 TX OE(2T, 0.5T) = (3, 3)
8786 11:52:07.394817
8787 11:52:07.394881
8788 11:52:07.401399 [DQSOSCAuto] RK0, (LSB)MR18= 0x80c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8789 11:52:07.404603 CH1 RK0: MR19=303, MR18=80C
8790 11:52:07.411217 CH1_RK0: MR19=0x303, MR18=0x80C, DQSOSC=403, MR23=63, INC=22, DEC=15
8791 11:52:07.411301
8792 11:52:07.414552 ----->DramcWriteLeveling(PI) begin...
8793 11:52:07.414633 ==
8794 11:52:07.417670 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 11:52:07.421470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 11:52:07.421576 ==
8797 11:52:07.424199 Write leveling (Byte 0): 23 => 23
8798 11:52:07.427947 Write leveling (Byte 1): 24 => 24
8799 11:52:07.431127 DramcWriteLeveling(PI) end<-----
8800 11:52:07.431232
8801 11:52:07.431312 ==
8802 11:52:07.434879 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 11:52:07.437893 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 11:52:07.437966 ==
8805 11:52:07.441298 [Gating] SW mode calibration
8806 11:52:07.447720 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8807 11:52:07.454608 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8808 11:52:07.457930 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 11:52:07.461145 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8810 11:52:07.467778 1 4 8 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
8811 11:52:07.471083 1 4 12 | B1->B0 | 3232 3434 | 0 1 | (1 1) (1 1)
8812 11:52:07.474483 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 11:52:07.480932 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 11:52:07.484179 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 11:52:07.487773 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 11:52:07.494159 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 11:52:07.497298 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 11:52:07.500926 1 5 8 | B1->B0 | 3434 2b2b | 1 0 | (1 0) (0 1)
8819 11:52:07.507568 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8820 11:52:07.510831 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 11:52:07.514088 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 11:52:07.520635 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 11:52:07.524211 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 11:52:07.527646 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 11:52:07.533962 1 6 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
8826 11:52:07.537298 1 6 8 | B1->B0 | 2626 4242 | 0 0 | (0 0) (0 0)
8827 11:52:07.540530 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8828 11:52:07.547229 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 11:52:07.550878 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 11:52:07.554062 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 11:52:07.560733 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 11:52:07.563911 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 11:52:07.567288 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 11:52:07.573954 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8835 11:52:07.577271 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8836 11:52:07.580653 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8837 11:52:07.587052 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 11:52:07.590247 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 11:52:07.594192 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 11:52:07.600668 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 11:52:07.603726 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 11:52:07.607134 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 11:52:07.613373 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 11:52:07.617173 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 11:52:07.620438 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 11:52:07.623763 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 11:52:07.630054 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 11:52:07.633301 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:52:07.637050 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 11:52:07.643253 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8851 11:52:07.646575 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8852 11:52:07.650383 Total UI for P1: 0, mck2ui 16
8853 11:52:07.653323 best dqsien dly found for B0: ( 1, 9, 8)
8854 11:52:07.656929 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:52:07.660064 Total UI for P1: 0, mck2ui 16
8856 11:52:07.663529 best dqsien dly found for B1: ( 1, 9, 10)
8857 11:52:07.666894 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8858 11:52:07.670064 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8859 11:52:07.670163
8860 11:52:07.676544 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8861 11:52:07.679932 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8862 11:52:07.683405 [Gating] SW calibration Done
8863 11:52:07.683504 ==
8864 11:52:07.686743 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 11:52:07.689826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 11:52:07.689912 ==
8867 11:52:07.690008 RX Vref Scan: 0
8868 11:52:07.690128
8869 11:52:07.693053 RX Vref 0 -> 0, step: 1
8870 11:52:07.693132
8871 11:52:07.696261 RX Delay 0 -> 252, step: 8
8872 11:52:07.699962 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8873 11:52:07.703033 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8874 11:52:07.709733 iDelay=200, Bit 2, Center 115 (56 ~ 175) 120
8875 11:52:07.713297 iDelay=200, Bit 3, Center 127 (64 ~ 191) 128
8876 11:52:07.716222 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8877 11:52:07.719647 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8878 11:52:07.722927 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8879 11:52:07.726351 iDelay=200, Bit 7, Center 127 (64 ~ 191) 128
8880 11:52:07.733287 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8881 11:52:07.736648 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8882 11:52:07.739715 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8883 11:52:07.743285 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8884 11:52:07.749507 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8885 11:52:07.753260 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8886 11:52:07.756388 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8887 11:52:07.759846 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8888 11:52:07.759952 ==
8889 11:52:07.762855 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:52:07.766561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:52:07.769884 ==
8892 11:52:07.770008 DQS Delay:
8893 11:52:07.770115 DQS0 = 0, DQS1 = 0
8894 11:52:07.773212 DQM Delay:
8895 11:52:07.773292 DQM0 = 130, DQM1 = 129
8896 11:52:07.776561 DQ Delay:
8897 11:52:07.779804 DQ0 =135, DQ1 =127, DQ2 =115, DQ3 =127
8898 11:52:07.783057 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =127
8899 11:52:07.786286 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8900 11:52:07.789555 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8901 11:52:07.789661
8902 11:52:07.789752
8903 11:52:07.789839 ==
8904 11:52:07.792975 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 11:52:07.796166 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 11:52:07.796314 ==
8907 11:52:07.799650
8908 11:52:07.799731
8909 11:52:07.799795 TX Vref Scan disable
8910 11:52:07.802623 == TX Byte 0 ==
8911 11:52:07.806297 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8912 11:52:07.809299 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8913 11:52:07.812956 == TX Byte 1 ==
8914 11:52:07.816148 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8915 11:52:07.819185 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8916 11:52:07.819270 ==
8917 11:52:07.822738 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 11:52:07.829287 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 11:52:07.829369 ==
8920 11:52:07.842184
8921 11:52:07.845367 TX Vref early break, caculate TX vref
8922 11:52:07.848884 TX Vref=16, minBit 6, minWin=22, winSum=381
8923 11:52:07.852194 TX Vref=18, minBit 0, minWin=22, winSum=392
8924 11:52:07.855342 TX Vref=20, minBit 0, minWin=23, winSum=398
8925 11:52:07.858462 TX Vref=22, minBit 0, minWin=23, winSum=404
8926 11:52:07.862087 TX Vref=24, minBit 0, minWin=25, winSum=418
8927 11:52:07.868736 TX Vref=26, minBit 0, minWin=25, winSum=419
8928 11:52:07.872241 TX Vref=28, minBit 1, minWin=24, winSum=421
8929 11:52:07.874998 TX Vref=30, minBit 0, minWin=24, winSum=419
8930 11:52:07.878385 TX Vref=32, minBit 1, minWin=23, winSum=407
8931 11:52:07.881800 TX Vref=34, minBit 1, minWin=23, winSum=402
8932 11:52:07.885021 TX Vref=36, minBit 0, minWin=22, winSum=393
8933 11:52:07.891945 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 26
8934 11:52:07.892051
8935 11:52:07.895352 Final TX Range 0 Vref 26
8936 11:52:07.895481
8937 11:52:07.895577 ==
8938 11:52:07.898369 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:52:07.901923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:52:07.902004 ==
8941 11:52:07.902068
8942 11:52:07.902127
8943 11:52:07.905658 TX Vref Scan disable
8944 11:52:07.911976 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8945 11:52:07.912100 == TX Byte 0 ==
8946 11:52:07.915072 u2DelayCellOfst[0]=18 cells (5 PI)
8947 11:52:07.918773 u2DelayCellOfst[1]=11 cells (3 PI)
8948 11:52:07.922143 u2DelayCellOfst[2]=0 cells (0 PI)
8949 11:52:07.924917 u2DelayCellOfst[3]=3 cells (1 PI)
8950 11:52:07.928363 u2DelayCellOfst[4]=7 cells (2 PI)
8951 11:52:07.932074 u2DelayCellOfst[5]=22 cells (6 PI)
8952 11:52:07.935292 u2DelayCellOfst[6]=18 cells (5 PI)
8953 11:52:07.938716 u2DelayCellOfst[7]=7 cells (2 PI)
8954 11:52:07.941953 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8955 11:52:07.945118 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8956 11:52:07.948209 == TX Byte 1 ==
8957 11:52:07.948331 u2DelayCellOfst[8]=0 cells (0 PI)
8958 11:52:07.951617 u2DelayCellOfst[9]=7 cells (2 PI)
8959 11:52:07.954957 u2DelayCellOfst[10]=15 cells (4 PI)
8960 11:52:07.958067 u2DelayCellOfst[11]=7 cells (2 PI)
8961 11:52:07.961501 u2DelayCellOfst[12]=15 cells (4 PI)
8962 11:52:07.964896 u2DelayCellOfst[13]=18 cells (5 PI)
8963 11:52:07.968512 u2DelayCellOfst[14]=18 cells (5 PI)
8964 11:52:07.971683 u2DelayCellOfst[15]=18 cells (5 PI)
8965 11:52:07.975286 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8966 11:52:07.981473 Update DQM dly =978 (3 ,6, 18) DQM OEN =(3 ,3)
8967 11:52:07.981557 DramC Write-DBI on
8968 11:52:07.981622 ==
8969 11:52:07.984953 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 11:52:07.988322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 11:52:07.991558 ==
8972 11:52:07.991639
8973 11:52:07.991704
8974 11:52:07.991765 TX Vref Scan disable
8975 11:52:07.994962 == TX Byte 0 ==
8976 11:52:07.998838 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8977 11:52:08.002156 == TX Byte 1 ==
8978 11:52:08.004916 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8979 11:52:08.008380 DramC Write-DBI off
8980 11:52:08.008461
8981 11:52:08.008526 [DATLAT]
8982 11:52:08.008586 Freq=1600, CH1 RK1
8983 11:52:08.008645
8984 11:52:08.011775 DATLAT Default: 0xf
8985 11:52:08.011881 0, 0xFFFF, sum = 0
8986 11:52:08.015466 1, 0xFFFF, sum = 0
8987 11:52:08.018268 2, 0xFFFF, sum = 0
8988 11:52:08.018352 3, 0xFFFF, sum = 0
8989 11:52:08.021920 4, 0xFFFF, sum = 0
8990 11:52:08.022003 5, 0xFFFF, sum = 0
8991 11:52:08.024763 6, 0xFFFF, sum = 0
8992 11:52:08.024847 7, 0xFFFF, sum = 0
8993 11:52:08.028092 8, 0xFFFF, sum = 0
8994 11:52:08.028210 9, 0xFFFF, sum = 0
8995 11:52:08.031649 10, 0xFFFF, sum = 0
8996 11:52:08.031759 11, 0xFFFF, sum = 0
8997 11:52:08.035037 12, 0xFFFF, sum = 0
8998 11:52:08.035181 13, 0x8FFF, sum = 0
8999 11:52:08.038027 14, 0x0, sum = 1
9000 11:52:08.038150 15, 0x0, sum = 2
9001 11:52:08.041495 16, 0x0, sum = 3
9002 11:52:08.041642 17, 0x0, sum = 4
9003 11:52:08.044754 best_step = 15
9004 11:52:08.044836
9005 11:52:08.044900 ==
9006 11:52:08.048541 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 11:52:08.051374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 11:52:08.051482 ==
9009 11:52:08.055144 RX Vref Scan: 0
9010 11:52:08.055225
9011 11:52:08.055290 RX Vref 0 -> 0, step: 1
9012 11:52:08.055350
9013 11:52:08.057999 RX Delay 11 -> 252, step: 4
9014 11:52:08.061751 iDelay=195, Bit 0, Center 132 (79 ~ 186) 108
9015 11:52:08.068160 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
9016 11:52:08.071484 iDelay=195, Bit 2, Center 114 (59 ~ 170) 112
9017 11:52:08.074952 iDelay=195, Bit 3, Center 124 (71 ~ 178) 108
9018 11:52:08.077966 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
9019 11:52:08.081247 iDelay=195, Bit 5, Center 138 (83 ~ 194) 112
9020 11:52:08.088079 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
9021 11:52:08.091262 iDelay=195, Bit 7, Center 122 (67 ~ 178) 112
9022 11:52:08.094520 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
9023 11:52:08.098353 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9024 11:52:08.101397 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9025 11:52:08.108139 iDelay=195, Bit 11, Center 118 (63 ~ 174) 112
9026 11:52:08.111405 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
9027 11:52:08.114771 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
9028 11:52:08.117786 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9029 11:52:08.124558 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9030 11:52:08.124655 ==
9031 11:52:08.127704 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 11:52:08.131244 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 11:52:08.131326 ==
9034 11:52:08.131422 DQS Delay:
9035 11:52:08.134475 DQS0 = 0, DQS1 = 0
9036 11:52:08.134594 DQM Delay:
9037 11:52:08.138027 DQM0 = 127, DQM1 = 124
9038 11:52:08.138109 DQ Delay:
9039 11:52:08.141692 DQ0 =132, DQ1 =126, DQ2 =114, DQ3 =124
9040 11:52:08.144375 DQ4 =124, DQ5 =138, DQ6 =138, DQ7 =122
9041 11:52:08.147680 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =118
9042 11:52:08.150915 DQ12 =130, DQ13 =132, DQ14 =130, DQ15 =134
9043 11:52:08.151022
9044 11:52:08.151115
9045 11:52:08.151202
9046 11:52:08.154394 [DramC_TX_OE_Calibration] TA2
9047 11:52:08.157882 Original DQ_B0 (3 6) =30, OEN = 27
9048 11:52:08.161254 Original DQ_B1 (3 6) =30, OEN = 27
9049 11:52:08.164641 24, 0x0, End_B0=24 End_B1=24
9050 11:52:08.167841 25, 0x0, End_B0=25 End_B1=25
9051 11:52:08.167950 26, 0x0, End_B0=26 End_B1=26
9052 11:52:08.171104 27, 0x0, End_B0=27 End_B1=27
9053 11:52:08.174296 28, 0x0, End_B0=28 End_B1=28
9054 11:52:08.177598 29, 0x0, End_B0=29 End_B1=29
9055 11:52:08.180836 30, 0x0, End_B0=30 End_B1=30
9056 11:52:08.180919 31, 0x4545, End_B0=30 End_B1=30
9057 11:52:08.184085 Byte0 end_step=30 best_step=27
9058 11:52:08.187423 Byte1 end_step=30 best_step=27
9059 11:52:08.190757 Byte0 TX OE(2T, 0.5T) = (3, 3)
9060 11:52:08.194112 Byte1 TX OE(2T, 0.5T) = (3, 3)
9061 11:52:08.194201
9062 11:52:08.194297
9063 11:52:08.200661 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9064 11:52:08.204299 CH1 RK1: MR19=303, MR18=101C
9065 11:52:08.210961 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9066 11:52:08.214285 [RxdqsGatingPostProcess] freq 1600
9067 11:52:08.221076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9068 11:52:08.224184 best DQS0 dly(2T, 0.5T) = (1, 1)
9069 11:52:08.224266 best DQS1 dly(2T, 0.5T) = (1, 1)
9070 11:52:08.227624 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9071 11:52:08.230493 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9072 11:52:08.233808 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 11:52:08.237522 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 11:52:08.240762 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 11:52:08.244033 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 11:52:08.247359 Pre-setting of DQS Precalculation
9077 11:52:08.250990 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9078 11:52:08.260754 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9079 11:52:08.267121 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 11:52:08.267202
9081 11:52:08.267266
9082 11:52:08.270229 [Calibration Summary] 3200 Mbps
9083 11:52:08.270310 CH 0, Rank 0
9084 11:52:08.273671 SW Impedance : PASS
9085 11:52:08.273752 DUTY Scan : NO K
9086 11:52:08.276916 ZQ Calibration : PASS
9087 11:52:08.280800 Jitter Meter : NO K
9088 11:52:08.280903 CBT Training : PASS
9089 11:52:08.284035 Write leveling : PASS
9090 11:52:08.287353 RX DQS gating : PASS
9091 11:52:08.287434 RX DQ/DQS(RDDQC) : PASS
9092 11:52:08.290159 TX DQ/DQS : PASS
9093 11:52:08.293924 RX DATLAT : PASS
9094 11:52:08.294006 RX DQ/DQS(Engine): PASS
9095 11:52:08.297251 TX OE : PASS
9096 11:52:08.297333 All Pass.
9097 11:52:08.297397
9098 11:52:08.300392 CH 0, Rank 1
9099 11:52:08.300473 SW Impedance : PASS
9100 11:52:08.303984 DUTY Scan : NO K
9101 11:52:08.307215 ZQ Calibration : PASS
9102 11:52:08.307296 Jitter Meter : NO K
9103 11:52:08.310569 CBT Training : PASS
9104 11:52:08.313414 Write leveling : PASS
9105 11:52:08.313495 RX DQS gating : PASS
9106 11:52:08.317035 RX DQ/DQS(RDDQC) : PASS
9107 11:52:08.317117 TX DQ/DQS : PASS
9108 11:52:08.320586 RX DATLAT : PASS
9109 11:52:08.323795 RX DQ/DQS(Engine): PASS
9110 11:52:08.323876 TX OE : PASS
9111 11:52:08.327106 All Pass.
9112 11:52:08.327187
9113 11:52:08.327251 CH 1, Rank 0
9114 11:52:08.330366 SW Impedance : PASS
9115 11:52:08.330448 DUTY Scan : NO K
9116 11:52:08.333201 ZQ Calibration : PASS
9117 11:52:08.336510 Jitter Meter : NO K
9118 11:52:08.336592 CBT Training : PASS
9119 11:52:08.339868 Write leveling : PASS
9120 11:52:08.343487 RX DQS gating : PASS
9121 11:52:08.343568 RX DQ/DQS(RDDQC) : PASS
9122 11:52:08.346676 TX DQ/DQS : PASS
9123 11:52:08.349999 RX DATLAT : PASS
9124 11:52:08.350080 RX DQ/DQS(Engine): PASS
9125 11:52:08.353385 TX OE : PASS
9126 11:52:08.353467 All Pass.
9127 11:52:08.353532
9128 11:52:08.356592 CH 1, Rank 1
9129 11:52:08.356674 SW Impedance : PASS
9130 11:52:08.359785 DUTY Scan : NO K
9131 11:52:08.362943 ZQ Calibration : PASS
9132 11:52:08.363024 Jitter Meter : NO K
9133 11:52:08.366219 CBT Training : PASS
9134 11:52:08.369922 Write leveling : PASS
9135 11:52:08.370003 RX DQS gating : PASS
9136 11:52:08.373013 RX DQ/DQS(RDDQC) : PASS
9137 11:52:08.373095 TX DQ/DQS : PASS
9138 11:52:08.376141 RX DATLAT : PASS
9139 11:52:08.379561 RX DQ/DQS(Engine): PASS
9140 11:52:08.379642 TX OE : PASS
9141 11:52:08.382942 All Pass.
9142 11:52:08.383061
9143 11:52:08.383125 DramC Write-DBI on
9144 11:52:08.386079 PER_BANK_REFRESH: Hybrid Mode
9145 11:52:08.389548 TX_TRACKING: ON
9146 11:52:08.396171 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9147 11:52:08.406224 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9148 11:52:08.413014 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9149 11:52:08.416011 [FAST_K] Save calibration result to emmc
9150 11:52:08.419346 sync common calibartion params.
9151 11:52:08.419427 sync cbt_mode0:1, 1:1
9152 11:52:08.422909 dram_init: ddr_geometry: 2
9153 11:52:08.425839 dram_init: ddr_geometry: 2
9154 11:52:08.429607 dram_init: ddr_geometry: 2
9155 11:52:08.429688 0:dram_rank_size:100000000
9156 11:52:08.432791 1:dram_rank_size:100000000
9157 11:52:08.439327 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9158 11:52:08.439409 DFS_SHUFFLE_HW_MODE: ON
9159 11:52:08.445737 dramc_set_vcore_voltage set vcore to 725000
9160 11:52:08.445818 Read voltage for 1600, 0
9161 11:52:08.449118 Vio18 = 0
9162 11:52:08.449200 Vcore = 725000
9163 11:52:08.449265 Vdram = 0
9164 11:52:08.452488 Vddq = 0
9165 11:52:08.452569 Vmddr = 0
9166 11:52:08.455719 switch to 3200 Mbps bootup
9167 11:52:08.455801 [DramcRunTimeConfig]
9168 11:52:08.455866 PHYPLL
9169 11:52:08.459041 DPM_CONTROL_AFTERK: ON
9170 11:52:08.459123 PER_BANK_REFRESH: ON
9171 11:52:08.462388 REFRESH_OVERHEAD_REDUCTION: ON
9172 11:52:08.465932 CMD_PICG_NEW_MODE: OFF
9173 11:52:08.466013 XRTWTW_NEW_MODE: ON
9174 11:52:08.469041 XRTRTR_NEW_MODE: ON
9175 11:52:08.469148 TX_TRACKING: ON
9176 11:52:08.472213 RDSEL_TRACKING: OFF
9177 11:52:08.476138 DQS Precalculation for DVFS: ON
9178 11:52:08.476246 RX_TRACKING: OFF
9179 11:52:08.479239 HW_GATING DBG: ON
9180 11:52:08.479320 ZQCS_ENABLE_LP4: ON
9181 11:52:08.482402 RX_PICG_NEW_MODE: ON
9182 11:52:08.485821 TX_PICG_NEW_MODE: ON
9183 11:52:08.485902 ENABLE_RX_DCM_DPHY: ON
9184 11:52:08.489052 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9185 11:52:08.492191 DUMMY_READ_FOR_TRACKING: OFF
9186 11:52:08.495786 !!! SPM_CONTROL_AFTERK: OFF
9187 11:52:08.495876 !!! SPM could not control APHY
9188 11:52:08.499181 IMPEDANCE_TRACKING: ON
9189 11:52:08.499262 TEMP_SENSOR: ON
9190 11:52:08.502179 HW_SAVE_FOR_SR: OFF
9191 11:52:08.506005 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9192 11:52:08.509027 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9193 11:52:08.512613 Read ODT Tracking: ON
9194 11:52:08.512694 Refresh Rate DeBounce: ON
9195 11:52:08.515658 DFS_NO_QUEUE_FLUSH: ON
9196 11:52:08.519041 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9197 11:52:08.522194 ENABLE_DFS_RUNTIME_MRW: OFF
9198 11:52:08.522275 DDR_RESERVE_NEW_MODE: ON
9199 11:52:08.525659 MR_CBT_SWITCH_FREQ: ON
9200 11:52:08.528726 =========================
9201 11:52:08.546702 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9202 11:52:08.549816 dram_init: ddr_geometry: 2
9203 11:52:08.568357 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9204 11:52:08.571451 dram_init: dram init end (result: 0)
9205 11:52:08.577951 DRAM-K: Full calibration passed in 24578 msecs
9206 11:52:08.581298 MRC: failed to locate region type 0.
9207 11:52:08.581379 DRAM rank0 size:0x100000000,
9208 11:52:08.585073 DRAM rank1 size=0x100000000
9209 11:52:08.594526 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9210 11:52:08.601122 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9211 11:52:08.607826 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9212 11:52:08.618165 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9213 11:52:08.618247 DRAM rank0 size:0x100000000,
9214 11:52:08.621075 DRAM rank1 size=0x100000000
9215 11:52:08.621155 CBMEM:
9216 11:52:08.624144 IMD: root @ 0xfffff000 254 entries.
9217 11:52:08.627966 IMD: root @ 0xffffec00 62 entries.
9218 11:52:08.630994 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9219 11:52:08.637582 WARNING: RO_VPD is uninitialized or empty.
9220 11:52:08.640716 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9221 11:52:08.648356 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9222 11:52:08.660879 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9223 11:52:08.672438 BS: romstage times (exec / console): total (unknown) / 24041 ms
9224 11:52:08.672520
9225 11:52:08.672584
9226 11:52:08.682271 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9227 11:52:08.686013 ARM64: Exception handlers installed.
9228 11:52:08.689492 ARM64: Testing exception
9229 11:52:08.692363 ARM64: Done test exception
9230 11:52:08.692444 Enumerating buses...
9231 11:52:08.695742 Show all devs... Before device enumeration.
9232 11:52:08.698996 Root Device: enabled 1
9233 11:52:08.702348 CPU_CLUSTER: 0: enabled 1
9234 11:52:08.702429 CPU: 00: enabled 1
9235 11:52:08.706146 Compare with tree...
9236 11:52:08.706228 Root Device: enabled 1
9237 11:52:08.709392 CPU_CLUSTER: 0: enabled 1
9238 11:52:08.712346 CPU: 00: enabled 1
9239 11:52:08.712427 Root Device scanning...
9240 11:52:08.715893 scan_static_bus for Root Device
9241 11:52:08.719181 CPU_CLUSTER: 0 enabled
9242 11:52:08.722538 scan_static_bus for Root Device done
9243 11:52:08.725759 scan_bus: bus Root Device finished in 8 msecs
9244 11:52:08.725841 done
9245 11:52:08.732496 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9246 11:52:08.735616 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9247 11:52:08.741968 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9248 11:52:08.745251 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9249 11:52:08.749080 Allocating resources...
9250 11:52:08.751986 Reading resources...
9251 11:52:08.755463 Root Device read_resources bus 0 link: 0
9252 11:52:08.755546 DRAM rank0 size:0x100000000,
9253 11:52:08.758494 DRAM rank1 size=0x100000000
9254 11:52:08.762239 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9255 11:52:08.765599 CPU: 00 missing read_resources
9256 11:52:08.768853 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9257 11:52:08.775389 Root Device read_resources bus 0 link: 0 done
9258 11:52:08.775471 Done reading resources.
9259 11:52:08.781953 Show resources in subtree (Root Device)...After reading.
9260 11:52:08.785352 Root Device child on link 0 CPU_CLUSTER: 0
9261 11:52:08.788726 CPU_CLUSTER: 0 child on link 0 CPU: 00
9262 11:52:08.798618 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9263 11:52:08.798703 CPU: 00
9264 11:52:08.801957 Root Device assign_resources, bus 0 link: 0
9265 11:52:08.805289 CPU_CLUSTER: 0 missing set_resources
9266 11:52:08.811785 Root Device assign_resources, bus 0 link: 0 done
9267 11:52:08.811870 Done setting resources.
9268 11:52:08.818565 Show resources in subtree (Root Device)...After assigning values.
9269 11:52:08.822143 Root Device child on link 0 CPU_CLUSTER: 0
9270 11:52:08.824887 CPU_CLUSTER: 0 child on link 0 CPU: 00
9271 11:52:08.835116 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9272 11:52:08.835201 CPU: 00
9273 11:52:08.838454 Done allocating resources.
9274 11:52:08.841571 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9275 11:52:08.844863 Enabling resources...
9276 11:52:08.844946 done.
9277 11:52:08.851661 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9278 11:52:08.851743 Initializing devices...
9279 11:52:08.854942 Root Device init
9280 11:52:08.855024 init hardware done!
9281 11:52:08.858420 0x00000018: ctrlr->caps
9282 11:52:08.861681 52.000 MHz: ctrlr->f_max
9283 11:52:08.861764 0.400 MHz: ctrlr->f_min
9284 11:52:08.865054 0x40ff8080: ctrlr->voltages
9285 11:52:08.865137 sclk: 390625
9286 11:52:08.868131 Bus Width = 1
9287 11:52:08.868251 sclk: 390625
9288 11:52:08.871831 Bus Width = 1
9289 11:52:08.871912 Early init status = 3
9290 11:52:08.878402 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9291 11:52:08.881573 in-header: 03 fc 00 00 01 00 00 00
9292 11:52:08.881655 in-data: 00
9293 11:52:08.888146 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9294 11:52:08.891362 in-header: 03 fd 00 00 00 00 00 00
9295 11:52:08.894757 in-data:
9296 11:52:08.897993 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9297 11:52:08.901100 in-header: 03 fc 00 00 01 00 00 00
9298 11:52:08.904925 in-data: 00
9299 11:52:08.907681 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9300 11:52:08.912636 in-header: 03 fd 00 00 00 00 00 00
9301 11:52:08.916053 in-data:
9302 11:52:08.918874 [SSUSB] Setting up USB HOST controller...
9303 11:52:08.922635 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9304 11:52:08.925600 [SSUSB] phy power-on done.
9305 11:52:08.929283 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9306 11:52:08.935714 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9307 11:52:08.938906 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9308 11:52:08.945565 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9309 11:52:08.952319 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9310 11:52:08.958912 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9311 11:52:08.965391 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9312 11:52:08.972410 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9313 11:52:08.975734 SPM: binary array size = 0x9dc
9314 11:52:08.978782 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9315 11:52:08.985548 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9316 11:52:08.991903 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9317 11:52:08.998454 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9318 11:52:09.001754 configure_display: Starting display init
9319 11:52:09.035499 anx7625_power_on_init: Init interface.
9320 11:52:09.038861 anx7625_disable_pd_protocol: Disabled PD feature.
9321 11:52:09.042500 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9322 11:52:09.070153 anx7625_start_dp_work: Secure OCM version=00
9323 11:52:09.073374 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9324 11:52:09.088183 sp_tx_get_edid_block: EDID Block = 1
9325 11:52:09.190866 Extracted contents:
9326 11:52:09.194163 header: 00 ff ff ff ff ff ff 00
9327 11:52:09.197267 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9328 11:52:09.200679 version: 01 04
9329 11:52:09.203952 basic params: 95 1f 11 78 0a
9330 11:52:09.207553 chroma info: 76 90 94 55 54 90 27 21 50 54
9331 11:52:09.210501 established: 00 00 00
9332 11:52:09.217315 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9333 11:52:09.220232 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9334 11:52:09.227354 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9335 11:52:09.234075 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9336 11:52:09.240571 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9337 11:52:09.243433 extensions: 00
9338 11:52:09.243547 checksum: fb
9339 11:52:09.243642
9340 11:52:09.247017 Manufacturer: IVO Model 57d Serial Number 0
9341 11:52:09.250091 Made week 0 of 2020
9342 11:52:09.250172 EDID version: 1.4
9343 11:52:09.253936 Digital display
9344 11:52:09.257193 6 bits per primary color channel
9345 11:52:09.257276 DisplayPort interface
9346 11:52:09.260411 Maximum image size: 31 cm x 17 cm
9347 11:52:09.263729 Gamma: 220%
9348 11:52:09.263809 Check DPMS levels
9349 11:52:09.266905 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9350 11:52:09.273438 First detailed timing is preferred timing
9351 11:52:09.273519 Established timings supported:
9352 11:52:09.277177 Standard timings supported:
9353 11:52:09.279816 Detailed timings
9354 11:52:09.283318 Hex of detail: 383680a07038204018303c0035ae10000019
9355 11:52:09.286677 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9356 11:52:09.293410 0780 0798 07c8 0820 hborder 0
9357 11:52:09.296582 0438 043b 0447 0458 vborder 0
9358 11:52:09.299832 -hsync -vsync
9359 11:52:09.299912 Did detailed timing
9360 11:52:09.306802 Hex of detail: 000000000000000000000000000000000000
9361 11:52:09.309975 Manufacturer-specified data, tag 0
9362 11:52:09.313053 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9363 11:52:09.316451 ASCII string: InfoVision
9364 11:52:09.319692 Hex of detail: 000000fe00523134304e574635205248200a
9365 11:52:09.323199 ASCII string: R140NWF5 RH
9366 11:52:09.323280 Checksum
9367 11:52:09.326266 Checksum: 0xfb (valid)
9368 11:52:09.329790 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9369 11:52:09.333140 DSI data_rate: 832800000 bps
9370 11:52:09.339715 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9371 11:52:09.342895 anx7625_parse_edid: pixelclock(138800).
9372 11:52:09.346334 hactive(1920), hsync(48), hfp(24), hbp(88)
9373 11:52:09.349350 vactive(1080), vsync(12), vfp(3), vbp(17)
9374 11:52:09.353033 anx7625_dsi_config: config dsi.
9375 11:52:09.359377 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9376 11:52:09.372592 anx7625_dsi_config: success to config DSI
9377 11:52:09.376339 anx7625_dp_start: MIPI phy setup OK.
9378 11:52:09.379538 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9379 11:52:09.382690 mtk_ddp_mode_set invalid vrefresh 60
9380 11:52:09.385880 main_disp_path_setup
9381 11:52:09.385960 ovl_layer_smi_id_en
9382 11:52:09.389423 ovl_layer_smi_id_en
9383 11:52:09.389503 ccorr_config
9384 11:52:09.389567 aal_config
9385 11:52:09.392429 gamma_config
9386 11:52:09.392510 postmask_config
9387 11:52:09.395755 dither_config
9388 11:52:09.399231 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9389 11:52:09.405706 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9390 11:52:09.409095 Root Device init finished in 551 msecs
9391 11:52:09.412373 CPU_CLUSTER: 0 init
9392 11:52:09.419033 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9393 11:52:09.422435 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9394 11:52:09.425703 APU_MBOX 0x190000b0 = 0x10001
9395 11:52:09.428988 APU_MBOX 0x190001b0 = 0x10001
9396 11:52:09.432583 APU_MBOX 0x190005b0 = 0x10001
9397 11:52:09.435733 APU_MBOX 0x190006b0 = 0x10001
9398 11:52:09.439376 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9399 11:52:09.451876 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9400 11:52:09.464379 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9401 11:52:09.470457 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9402 11:52:09.482302 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9403 11:52:09.491641 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9404 11:52:09.494879 CPU_CLUSTER: 0 init finished in 81 msecs
9405 11:52:09.498252 Devices initialized
9406 11:52:09.501330 Show all devs... After init.
9407 11:52:09.501412 Root Device: enabled 1
9408 11:52:09.504816 CPU_CLUSTER: 0: enabled 1
9409 11:52:09.508087 CPU: 00: enabled 1
9410 11:52:09.511621 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9411 11:52:09.514753 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9412 11:52:09.517989 ELOG: NV offset 0x57f000 size 0x1000
9413 11:52:09.524591 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9414 11:52:09.531197 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9415 11:52:09.534464 ELOG: Event(17) added with size 13 at 2023-11-23 11:52:10 UTC
9416 11:52:09.537818 out: cmd=0x121: 03 db 21 01 00 00 00 00
9417 11:52:09.542028 in-header: 03 5c 00 00 2c 00 00 00
9418 11:52:09.555331 in-data: 02 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9419 11:52:09.561819 ELOG: Event(A1) added with size 10 at 2023-11-23 11:52:10 UTC
9420 11:52:09.568206 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9421 11:52:09.574916 ELOG: Event(A0) added with size 9 at 2023-11-23 11:52:10 UTC
9422 11:52:09.578259 elog_add_boot_reason: Logged dev mode boot
9423 11:52:09.581489 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9424 11:52:09.585327 Finalize devices...
9425 11:52:09.585408 Devices finalized
9426 11:52:09.591571 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9427 11:52:09.594870 Writing coreboot table at 0xffe64000
9428 11:52:09.598197 0. 000000000010a000-0000000000113fff: RAMSTAGE
9429 11:52:09.601590 1. 0000000040000000-00000000400fffff: RAM
9430 11:52:09.608099 2. 0000000040100000-000000004032afff: RAMSTAGE
9431 11:52:09.611815 3. 000000004032b000-00000000545fffff: RAM
9432 11:52:09.614857 4. 0000000054600000-000000005465ffff: BL31
9433 11:52:09.618031 5. 0000000054660000-00000000ffe63fff: RAM
9434 11:52:09.624752 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9435 11:52:09.628106 7. 0000000100000000-000000023fffffff: RAM
9436 11:52:09.628187 Passing 5 GPIOs to payload:
9437 11:52:09.634668 NAME | PORT | POLARITY | VALUE
9438 11:52:09.637920 EC in RW | 0x000000aa | low | undefined
9439 11:52:09.644493 EC interrupt | 0x00000005 | low | undefined
9440 11:52:09.647935 TPM interrupt | 0x000000ab | high | undefined
9441 11:52:09.651289 SD card detect | 0x00000011 | high | undefined
9442 11:52:09.657845 speaker enable | 0x00000093 | high | undefined
9443 11:52:09.661058 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9444 11:52:09.664839 in-header: 03 f9 00 00 02 00 00 00
9445 11:52:09.664919 in-data: 02 00
9446 11:52:09.667857 ADC[4]: Raw value=895191 ID=7
9447 11:52:09.671168 ADC[3]: Raw value=213070 ID=1
9448 11:52:09.671249 RAM Code: 0x71
9449 11:52:09.674803 ADC[6]: Raw value=74352 ID=0
9450 11:52:09.677901 ADC[5]: Raw value=211960 ID=1
9451 11:52:09.677982 SKU Code: 0x1
9452 11:52:09.684563 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum f7f7
9453 11:52:09.687745 coreboot table: 964 bytes.
9454 11:52:09.690958 IMD ROOT 0. 0xfffff000 0x00001000
9455 11:52:09.694611 IMD SMALL 1. 0xffffe000 0x00001000
9456 11:52:09.697945 RO MCACHE 2. 0xffffc000 0x00001104
9457 11:52:09.701214 CONSOLE 3. 0xfff7c000 0x00080000
9458 11:52:09.704089 FMAP 4. 0xfff7b000 0x00000452
9459 11:52:09.707364 TIME STAMP 5. 0xfff7a000 0x00000910
9460 11:52:09.711236 VBOOT WORK 6. 0xfff66000 0x00014000
9461 11:52:09.714482 RAMOOPS 7. 0xffe66000 0x00100000
9462 11:52:09.717587 COREBOOT 8. 0xffe64000 0x00002000
9463 11:52:09.717667 IMD small region:
9464 11:52:09.720910 IMD ROOT 0. 0xffffec00 0x00000400
9465 11:52:09.724131 VPD 1. 0xffffeb80 0x0000006c
9466 11:52:09.727401 MMC STATUS 2. 0xffffeb60 0x00000004
9467 11:52:09.734276 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9468 11:52:09.737508 Probing TPM: done!
9469 11:52:09.741065 Connected to device vid:did:rid of 1ae0:0028:00
9470 11:52:09.750972 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9471 11:52:09.754127 Initialized TPM device CR50 revision 0
9472 11:52:09.758097 Checking cr50 for pending updates
9473 11:52:09.761474 Reading cr50 TPM mode
9474 11:52:09.769903 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9475 11:52:09.776966 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9476 11:52:09.816720 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9477 11:52:09.819966 Checking segment from ROM address 0x40100000
9478 11:52:09.823191 Checking segment from ROM address 0x4010001c
9479 11:52:09.829967 Loading segment from ROM address 0x40100000
9480 11:52:09.830049 code (compression=0)
9481 11:52:09.839794 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9482 11:52:09.846392 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9483 11:52:09.846474 it's not compressed!
9484 11:52:09.853431 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9485 11:52:09.856741 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9486 11:52:09.877129 Loading segment from ROM address 0x4010001c
9487 11:52:09.877211 Entry Point 0x80000000
9488 11:52:09.880196 Loaded segments
9489 11:52:09.883398 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9490 11:52:09.890257 Jumping to boot code at 0x80000000(0xffe64000)
9491 11:52:09.896976 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9492 11:52:09.903713 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9493 11:52:09.911454 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9494 11:52:09.914571 Checking segment from ROM address 0x40100000
9495 11:52:09.918008 Checking segment from ROM address 0x4010001c
9496 11:52:09.924875 Loading segment from ROM address 0x40100000
9497 11:52:09.924959 code (compression=1)
9498 11:52:09.931600 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9499 11:52:09.941633 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9500 11:52:09.941717 using LZMA
9501 11:52:09.949428 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9502 11:52:09.956399 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9503 11:52:09.959424 Loading segment from ROM address 0x4010001c
9504 11:52:09.959508 Entry Point 0x54601000
9505 11:52:09.962726 Loaded segments
9506 11:52:09.966292 NOTICE: MT8192 bl31_setup
9507 11:52:09.973552 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9508 11:52:09.976358 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9509 11:52:09.980158 WARNING: region 0:
9510 11:52:09.983578 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 11:52:09.983660 WARNING: region 1:
9512 11:52:09.990134 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9513 11:52:09.993350 WARNING: region 2:
9514 11:52:09.996600 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9515 11:52:09.999977 WARNING: region 3:
9516 11:52:10.003118 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 11:52:10.006665 WARNING: region 4:
9518 11:52:10.013252 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 11:52:10.013333 WARNING: region 5:
9520 11:52:10.016385 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 11:52:10.020127 WARNING: region 6:
9522 11:52:10.023191 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 11:52:10.026920 WARNING: region 7:
9524 11:52:10.029822 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 11:52:10.036914 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9526 11:52:10.039885 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9527 11:52:10.043397 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9528 11:52:10.049763 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9529 11:52:10.053382 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9530 11:52:10.056402 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9531 11:52:10.063520 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9532 11:52:10.066779 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9533 11:52:10.073631 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9534 11:52:10.076417 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9535 11:52:10.079751 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9536 11:52:10.086455 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9537 11:52:10.089792 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9538 11:52:10.093110 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9539 11:52:10.100048 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9540 11:52:10.103502 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9541 11:52:10.109935 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9542 11:52:10.113027 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9543 11:52:10.116457 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9544 11:52:10.123348 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9545 11:52:10.126519 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9546 11:52:10.129899 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9547 11:52:10.136525 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9548 11:52:10.139793 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9549 11:52:10.146501 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9550 11:52:10.149974 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9551 11:52:10.153152 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9552 11:52:10.159795 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9553 11:52:10.162949 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9554 11:52:10.169880 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9555 11:52:10.173277 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9556 11:52:10.176523 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9557 11:52:10.183497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9558 11:52:10.186834 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9559 11:52:10.190202 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9560 11:52:10.193004 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9561 11:52:10.200077 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9562 11:52:10.203332 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9563 11:52:10.206484 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9564 11:52:10.209802 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9565 11:52:10.216707 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9566 11:52:10.219905 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9567 11:52:10.223267 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9568 11:52:10.226404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9569 11:52:10.233013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9570 11:52:10.236499 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9571 11:52:10.239606 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9572 11:52:10.243128 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9573 11:52:10.249777 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9574 11:52:10.253370 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9575 11:52:10.259935 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9576 11:52:10.263071 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9577 11:52:10.266528 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9578 11:52:10.273425 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9579 11:52:10.276668 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9580 11:52:10.283268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9581 11:52:10.286293 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9582 11:52:10.293019 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9583 11:52:10.296404 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9584 11:52:10.299713 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9585 11:52:10.306462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9586 11:52:10.310082 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9587 11:52:10.316555 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9588 11:52:10.319848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9589 11:52:10.326562 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9590 11:52:10.329750 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9591 11:52:10.336521 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9592 11:52:10.339829 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9593 11:52:10.343150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9594 11:52:10.349885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9595 11:52:10.353476 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9596 11:52:10.359835 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9597 11:52:10.363207 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9598 11:52:10.366369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9599 11:52:10.373225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9600 11:52:10.376817 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9601 11:52:10.383315 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9602 11:52:10.386779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9603 11:52:10.393291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9604 11:52:10.396474 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9605 11:52:10.402955 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9606 11:52:10.406640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9607 11:52:10.409993 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9608 11:52:10.416414 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9609 11:52:10.420031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9610 11:52:10.426409 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9611 11:52:10.429966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9612 11:52:10.436453 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9613 11:52:10.440363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9614 11:52:10.443462 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9615 11:52:10.449902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9616 11:52:10.453451 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9617 11:52:10.460060 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9618 11:52:10.463415 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9619 11:52:10.469899 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9620 11:52:10.473157 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9621 11:52:10.476426 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9622 11:52:10.483207 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9623 11:52:10.486684 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9624 11:52:10.489866 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9625 11:52:10.493329 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9626 11:52:10.500141 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9627 11:52:10.503372 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9628 11:52:10.506795 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9629 11:52:10.513138 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9630 11:52:10.516479 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9631 11:52:10.523131 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9632 11:52:10.526669 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9633 11:52:10.530066 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9634 11:52:10.536881 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9635 11:52:10.540181 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9636 11:52:10.546919 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9637 11:52:10.550263 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9638 11:52:10.553443 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9639 11:52:10.560379 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9640 11:52:10.563276 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9641 11:52:10.566633 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9642 11:52:10.573296 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9643 11:52:10.576734 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9644 11:52:10.580024 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9645 11:52:10.583268 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9646 11:52:10.589975 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9647 11:52:10.593317 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9648 11:52:10.596896 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9649 11:52:10.603207 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9650 11:52:10.606886 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9651 11:52:10.610244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9652 11:52:10.617086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9653 11:52:10.620244 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9654 11:52:10.626938 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9655 11:52:10.630206 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9656 11:52:10.633880 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9657 11:52:10.640182 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9658 11:52:10.643970 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9659 11:52:10.647261 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9660 11:52:10.653689 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9661 11:52:10.656884 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9662 11:52:10.663602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9663 11:52:10.666885 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9664 11:52:10.670247 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9665 11:52:10.676937 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9666 11:52:10.680422 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9667 11:52:10.683787 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9668 11:52:10.690397 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9669 11:52:10.693561 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9670 11:52:10.700186 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9671 11:52:10.704023 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9672 11:52:10.707220 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9673 11:52:10.714068 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9674 11:52:10.717290 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9675 11:52:10.723590 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9676 11:52:10.727215 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9677 11:52:10.730531 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9678 11:52:10.736821 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9679 11:52:10.740440 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9680 11:52:10.743475 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9681 11:52:10.750383 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9682 11:52:10.753532 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9683 11:52:10.760434 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9684 11:52:10.763758 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9685 11:52:10.766994 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9686 11:52:10.773643 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9687 11:52:10.776988 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9688 11:52:10.783890 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9689 11:52:10.787115 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9690 11:52:10.790491 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9691 11:52:10.797369 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9692 11:52:10.800405 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9693 11:52:10.807156 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9694 11:52:10.810538 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9695 11:52:10.813932 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9696 11:52:10.819900 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9697 11:52:10.823315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9698 11:52:10.826775 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9699 11:52:10.833553 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9700 11:52:10.836995 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9701 11:52:10.843356 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9702 11:52:10.846425 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9703 11:52:10.850194 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9704 11:52:10.856814 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9705 11:52:10.860260 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9706 11:52:10.866448 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9707 11:52:10.869729 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9708 11:52:10.873312 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9709 11:52:10.880025 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9710 11:52:10.882947 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9711 11:52:10.889958 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9712 11:52:10.893246 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9713 11:52:10.896586 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9714 11:52:10.902866 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9715 11:52:10.906465 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9716 11:52:10.913019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9717 11:52:10.916196 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9718 11:52:10.919704 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9719 11:52:10.926382 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9720 11:52:10.929599 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9721 11:52:10.936613 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9722 11:52:10.939885 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9723 11:52:10.946344 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9724 11:52:10.949627 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9725 11:52:10.952784 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9726 11:52:10.959469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9727 11:52:10.962818 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9728 11:52:10.969463 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9729 11:52:10.972860 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9730 11:52:10.979190 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9731 11:52:10.982973 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9732 11:52:10.986047 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9733 11:52:10.992526 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9734 11:52:10.996297 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9735 11:52:11.002574 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9736 11:52:11.006377 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9737 11:52:11.009235 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9738 11:52:11.016094 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9739 11:52:11.019689 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9740 11:52:11.025793 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9741 11:52:11.029238 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9742 11:52:11.032643 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9743 11:52:11.039198 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9744 11:52:11.042663 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9745 11:52:11.048815 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9746 11:52:11.052698 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9747 11:52:11.058970 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9748 11:52:11.062507 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9749 11:52:11.065630 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9750 11:52:11.072276 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9751 11:52:11.075417 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9752 11:52:11.081944 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9753 11:52:11.085801 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9754 11:52:11.088621 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9755 11:52:11.095425 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9756 11:52:11.099024 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9757 11:52:11.102172 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9758 11:52:11.105383 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9759 11:52:11.112276 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9760 11:52:11.115627 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9761 11:52:11.118735 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9762 11:52:11.125317 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9763 11:52:11.128771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9764 11:52:11.131881 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9765 11:52:11.138699 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9766 11:52:11.141807 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9767 11:52:11.148295 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9768 11:52:11.151779 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9769 11:52:11.155190 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9770 11:52:11.161693 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9771 11:52:11.165018 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9772 11:52:11.168341 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9773 11:52:11.175084 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9774 11:52:11.178454 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9775 11:52:11.181742 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9776 11:52:11.188440 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9777 11:52:11.191885 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9778 11:52:11.198547 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9779 11:52:11.201362 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9780 11:52:11.205073 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9781 11:52:11.211389 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9782 11:52:11.214566 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9783 11:52:11.217798 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9784 11:52:11.224623 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9785 11:52:11.228305 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9786 11:52:11.234950 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9787 11:52:11.237900 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9788 11:52:11.241278 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9789 11:52:11.247739 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9790 11:52:11.250869 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9791 11:52:11.254248 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9792 11:52:11.261168 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9793 11:52:11.264021 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9794 11:52:11.267700 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9795 11:52:11.274322 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9796 11:52:11.277995 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9797 11:52:11.281189 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9798 11:52:11.284192 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9799 11:52:11.287803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9800 11:52:11.294709 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9801 11:52:11.297473 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9802 11:52:11.301309 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9803 11:52:11.304075 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9804 11:52:11.311359 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9805 11:52:11.314114 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9806 11:52:11.317527 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9807 11:52:11.324023 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9808 11:52:11.327683 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9809 11:52:11.334034 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9810 11:52:11.337497 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9811 11:52:11.341069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9812 11:52:11.347563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9813 11:52:11.350758 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9814 11:52:11.357570 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9815 11:52:11.360884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9816 11:52:11.363898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9817 11:52:11.370549 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9818 11:52:11.373907 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9819 11:52:11.380870 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9820 11:52:11.383784 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9821 11:52:11.390774 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9822 11:52:11.393714 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9823 11:52:11.397334 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9824 11:52:11.403893 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9825 11:52:11.407116 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9826 11:52:11.413795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9827 11:52:11.417237 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9828 11:52:11.420184 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9829 11:52:11.426809 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9830 11:52:11.430126 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9831 11:52:11.436772 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9832 11:52:11.440060 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9833 11:52:11.443487 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9834 11:52:11.450166 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9835 11:52:11.453516 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9836 11:52:11.459860 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9837 11:52:11.463288 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9838 11:52:11.466954 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9839 11:52:11.473441 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9840 11:52:11.476603 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9841 11:52:11.483110 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9842 11:52:11.486640 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9843 11:52:11.493164 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9844 11:52:11.496767 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9845 11:52:11.499760 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9846 11:52:11.506312 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9847 11:52:11.509860 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9848 11:52:11.516631 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9849 11:52:11.520118 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9850 11:52:11.523344 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9851 11:52:11.529970 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9852 11:52:11.533232 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9853 11:52:11.539613 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9854 11:52:11.542694 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9855 11:52:11.546301 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9856 11:52:11.552854 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9857 11:52:11.555909 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9858 11:52:11.562749 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9859 11:52:11.566082 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9860 11:52:11.572967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9861 11:52:11.576190 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9862 11:52:11.579321 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9863 11:52:11.585969 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9864 11:52:11.589185 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9865 11:52:11.595983 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9866 11:52:11.598970 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9867 11:52:11.602341 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9868 11:52:11.608813 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9869 11:52:11.612489 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9870 11:52:11.619002 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9871 11:52:11.622250 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9872 11:52:11.625746 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9873 11:52:11.632517 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9874 11:52:11.635256 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9875 11:52:11.642072 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9876 11:52:11.645573 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9877 11:52:11.652344 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9878 11:52:11.655712 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9879 11:52:11.658844 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9880 11:52:11.665546 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9881 11:52:11.668930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9882 11:52:11.675612 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9883 11:52:11.678673 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9884 11:52:11.685247 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9885 11:52:11.688602 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9886 11:52:11.691919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9887 11:52:11.698468 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9888 11:52:11.701707 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9889 11:52:11.708235 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9890 11:52:11.711665 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9891 11:52:11.718534 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9892 11:52:11.721990 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9893 11:52:11.728135 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9894 11:52:11.731574 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9895 11:52:11.735202 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9896 11:52:11.741807 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9897 11:52:11.745107 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9898 11:52:11.752004 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9899 11:52:11.754802 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9900 11:52:11.761591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9901 11:52:11.765047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9902 11:52:11.768330 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9903 11:52:11.774873 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9904 11:52:11.778396 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9905 11:52:11.784683 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9906 11:52:11.788141 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9907 11:52:11.794898 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9908 11:52:11.798168 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9909 11:52:11.804887 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9910 11:52:11.807929 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9911 11:52:11.811439 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9912 11:52:11.817992 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9913 11:52:11.821713 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9914 11:52:11.828063 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9915 11:52:11.831164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9916 11:52:11.838549 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9917 11:52:11.841589 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9918 11:52:11.845166 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9919 11:52:11.851186 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9920 11:52:11.854479 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9921 11:52:11.861329 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9922 11:52:11.864442 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9923 11:52:11.871440 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9924 11:52:11.874701 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9925 11:52:11.878230 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9926 11:52:11.884299 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9927 11:52:11.887900 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9928 11:52:11.891041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9929 11:52:11.897935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9930 11:52:11.900994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9931 11:52:11.907656 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9932 11:52:11.911209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9933 11:52:11.917284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9934 11:52:11.920621 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9935 11:52:11.927269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9936 11:52:11.930645 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9937 11:52:11.937727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9938 11:52:11.941039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9939 11:52:11.947353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9940 11:52:11.950747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9941 11:52:11.957579 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9942 11:52:11.961330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9943 11:52:11.967284 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9944 11:52:11.970328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9945 11:52:11.977079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9946 11:52:11.980602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9947 11:52:11.987164 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9948 11:52:11.990473 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9949 11:52:11.997318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9950 11:52:12.000413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9951 11:52:12.006638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9952 11:52:12.010515 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9953 11:52:12.017016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9954 11:52:12.020220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9955 11:52:12.026843 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9956 11:52:12.030091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9957 11:52:12.037196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9958 11:52:12.040410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9959 11:52:12.043798 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9960 11:52:12.046905 INFO: [APUAPC] vio 0
9961 11:52:12.053315 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9962 11:52:12.056776 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9963 11:52:12.059935 INFO: [APUAPC] D0_APC_0: 0x400510
9964 11:52:12.063474 INFO: [APUAPC] D0_APC_1: 0x0
9965 11:52:12.066705 INFO: [APUAPC] D0_APC_2: 0x1540
9966 11:52:12.069884 INFO: [APUAPC] D0_APC_3: 0x0
9967 11:52:12.073112 INFO: [APUAPC] D1_APC_0: 0xffffffff
9968 11:52:12.076757 INFO: [APUAPC] D1_APC_1: 0xffffffff
9969 11:52:12.079733 INFO: [APUAPC] D1_APC_2: 0x3fffff
9970 11:52:12.083480 INFO: [APUAPC] D1_APC_3: 0x0
9971 11:52:12.086549 INFO: [APUAPC] D2_APC_0: 0xffffffff
9972 11:52:12.089831 INFO: [APUAPC] D2_APC_1: 0xffffffff
9973 11:52:12.093303 INFO: [APUAPC] D2_APC_2: 0x3fffff
9974 11:52:12.097126 INFO: [APUAPC] D2_APC_3: 0x0
9975 11:52:12.100032 INFO: [APUAPC] D3_APC_0: 0xffffffff
9976 11:52:12.103024 INFO: [APUAPC] D3_APC_1: 0xffffffff
9977 11:52:12.106754 INFO: [APUAPC] D3_APC_2: 0x3fffff
9978 11:52:12.106835 INFO: [APUAPC] D3_APC_3: 0x0
9979 11:52:12.113032 INFO: [APUAPC] D4_APC_0: 0xffffffff
9980 11:52:12.116337 INFO: [APUAPC] D4_APC_1: 0xffffffff
9981 11:52:12.120099 INFO: [APUAPC] D4_APC_2: 0x3fffff
9982 11:52:12.120216 INFO: [APUAPC] D4_APC_3: 0x0
9983 11:52:12.123403 INFO: [APUAPC] D5_APC_0: 0xffffffff
9984 11:52:12.126175 INFO: [APUAPC] D5_APC_1: 0xffffffff
9985 11:52:12.129429 INFO: [APUAPC] D5_APC_2: 0x3fffff
9986 11:52:12.132713 INFO: [APUAPC] D5_APC_3: 0x0
9987 11:52:12.136413 INFO: [APUAPC] D6_APC_0: 0xffffffff
9988 11:52:12.139631 INFO: [APUAPC] D6_APC_1: 0xffffffff
9989 11:52:12.142811 INFO: [APUAPC] D6_APC_2: 0x3fffff
9990 11:52:12.146161 INFO: [APUAPC] D6_APC_3: 0x0
9991 11:52:12.149583 INFO: [APUAPC] D7_APC_0: 0xffffffff
9992 11:52:12.152851 INFO: [APUAPC] D7_APC_1: 0xffffffff
9993 11:52:12.156062 INFO: [APUAPC] D7_APC_2: 0x3fffff
9994 11:52:12.159366 INFO: [APUAPC] D7_APC_3: 0x0
9995 11:52:12.162760 INFO: [APUAPC] D8_APC_0: 0xffffffff
9996 11:52:12.165923 INFO: [APUAPC] D8_APC_1: 0xffffffff
9997 11:52:12.169409 INFO: [APUAPC] D8_APC_2: 0x3fffff
9998 11:52:12.172602 INFO: [APUAPC] D8_APC_3: 0x0
9999 11:52:12.175937 INFO: [APUAPC] D9_APC_0: 0xffffffff
10000 11:52:12.179056 INFO: [APUAPC] D9_APC_1: 0xffffffff
10001 11:52:12.182329 INFO: [APUAPC] D9_APC_2: 0x3fffff
10002 11:52:12.186156 INFO: [APUAPC] D9_APC_3: 0x0
10003 11:52:12.189001 INFO: [APUAPC] D10_APC_0: 0xffffffff
10004 11:52:12.192316 INFO: [APUAPC] D10_APC_1: 0xffffffff
10005 11:52:12.195537 INFO: [APUAPC] D10_APC_2: 0x3fffff
10006 11:52:12.199079 INFO: [APUAPC] D10_APC_3: 0x0
10007 11:52:12.202524 INFO: [APUAPC] D11_APC_0: 0xffffffff
10008 11:52:12.205406 INFO: [APUAPC] D11_APC_1: 0xffffffff
10009 11:52:12.209163 INFO: [APUAPC] D11_APC_2: 0x3fffff
10010 11:52:12.212491 INFO: [APUAPC] D11_APC_3: 0x0
10011 11:52:12.215649 INFO: [APUAPC] D12_APC_0: 0xffffffff
10012 11:52:12.218907 INFO: [APUAPC] D12_APC_1: 0xffffffff
10013 11:52:12.222084 INFO: [APUAPC] D12_APC_2: 0x3fffff
10014 11:52:12.225854 INFO: [APUAPC] D12_APC_3: 0x0
10015 11:52:12.228393 INFO: [APUAPC] D13_APC_0: 0xffffffff
10016 11:52:12.231837 INFO: [APUAPC] D13_APC_1: 0xffffffff
10017 11:52:12.235292 INFO: [APUAPC] D13_APC_2: 0x3fffff
10018 11:52:12.238449 INFO: [APUAPC] D13_APC_3: 0x0
10019 11:52:12.241871 INFO: [APUAPC] D14_APC_0: 0xffffffff
10020 11:52:12.245208 INFO: [APUAPC] D14_APC_1: 0xffffffff
10021 11:52:12.248493 INFO: [APUAPC] D14_APC_2: 0x3fffff
10022 11:52:12.251838 INFO: [APUAPC] D14_APC_3: 0x0
10023 11:52:12.255197 INFO: [APUAPC] D15_APC_0: 0xffffffff
10024 11:52:12.258536 INFO: [APUAPC] D15_APC_1: 0xffffffff
10025 11:52:12.261632 INFO: [APUAPC] D15_APC_2: 0x3fffff
10026 11:52:12.264927 INFO: [APUAPC] D15_APC_3: 0x0
10027 11:52:12.268334 INFO: [APUAPC] APC_CON: 0x4
10028 11:52:12.271633 INFO: [NOCDAPC] D0_APC_0: 0x0
10029 11:52:12.274981 INFO: [NOCDAPC] D0_APC_1: 0x0
10030 11:52:12.278381 INFO: [NOCDAPC] D1_APC_0: 0x0
10031 11:52:12.281659 INFO: [NOCDAPC] D1_APC_1: 0xfff
10032 11:52:12.284710 INFO: [NOCDAPC] D2_APC_0: 0x0
10033 11:52:12.288156 INFO: [NOCDAPC] D2_APC_1: 0xfff
10034 11:52:12.291440 INFO: [NOCDAPC] D3_APC_0: 0x0
10035 11:52:12.291524 INFO: [NOCDAPC] D3_APC_1: 0xfff
10036 11:52:12.294683 INFO: [NOCDAPC] D4_APC_0: 0x0
10037 11:52:12.298311 INFO: [NOCDAPC] D4_APC_1: 0xfff
10038 11:52:12.301340 INFO: [NOCDAPC] D5_APC_0: 0x0
10039 11:52:12.304805 INFO: [NOCDAPC] D5_APC_1: 0xfff
10040 11:52:12.308401 INFO: [NOCDAPC] D6_APC_0: 0x0
10041 11:52:12.311354 INFO: [NOCDAPC] D6_APC_1: 0xfff
10042 11:52:12.314630 INFO: [NOCDAPC] D7_APC_0: 0x0
10043 11:52:12.317684 INFO: [NOCDAPC] D7_APC_1: 0xfff
10044 11:52:12.321299 INFO: [NOCDAPC] D8_APC_0: 0x0
10045 11:52:12.324449 INFO: [NOCDAPC] D8_APC_1: 0xfff
10046 11:52:12.324534 INFO: [NOCDAPC] D9_APC_0: 0x0
10047 11:52:12.327912 INFO: [NOCDAPC] D9_APC_1: 0xfff
10048 11:52:12.331242 INFO: [NOCDAPC] D10_APC_0: 0x0
10049 11:52:12.334460 INFO: [NOCDAPC] D10_APC_1: 0xfff
10050 11:52:12.338353 INFO: [NOCDAPC] D11_APC_0: 0x0
10051 11:52:12.341268 INFO: [NOCDAPC] D11_APC_1: 0xfff
10052 11:52:12.344345 INFO: [NOCDAPC] D12_APC_0: 0x0
10053 11:52:12.347665 INFO: [NOCDAPC] D12_APC_1: 0xfff
10054 11:52:12.351117 INFO: [NOCDAPC] D13_APC_0: 0x0
10055 11:52:12.354303 INFO: [NOCDAPC] D13_APC_1: 0xfff
10056 11:52:12.357545 INFO: [NOCDAPC] D14_APC_0: 0x0
10057 11:52:12.360921 INFO: [NOCDAPC] D14_APC_1: 0xfff
10058 11:52:12.364175 INFO: [NOCDAPC] D15_APC_0: 0x0
10059 11:52:12.367409 INFO: [NOCDAPC] D15_APC_1: 0xfff
10060 11:52:12.370727 INFO: [NOCDAPC] APC_CON: 0x4
10061 11:52:12.374142 INFO: [APUAPC] set_apusys_apc done
10062 11:52:12.374224 INFO: [DEVAPC] devapc_init done
10063 11:52:12.380888 INFO: GICv3 without legacy support detected.
10064 11:52:12.384166 INFO: ARM GICv3 driver initialized in EL3
10065 11:52:12.387276 INFO: Maximum SPI INTID supported: 639
10066 11:52:12.390969 INFO: BL31: Initializing runtime services
10067 11:52:12.397285 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10068 11:52:12.400620 INFO: SPM: enable CPC mode
10069 11:52:12.404100 INFO: mcdi ready for mcusys-off-idle and system suspend
10070 11:52:12.410900 INFO: BL31: Preparing for EL3 exit to normal world
10071 11:52:12.413856 INFO: Entry point address = 0x80000000
10072 11:52:12.416931 INFO: SPSR = 0x8
10073 11:52:12.421305
10074 11:52:12.421385
10075 11:52:12.421450
10076 11:52:12.424610 Starting depthcharge on Spherion...
10077 11:52:12.424692
10078 11:52:12.424757 Wipe memory regions:
10079 11:52:12.424817
10080 11:52:12.425486 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10081 11:52:12.425600 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10082 11:52:12.425689 Setting prompt string to ['asurada:']
10083 11:52:12.425768 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10084 11:52:12.428107 [0x00000040000000, 0x00000054600000)
10085 11:52:12.550302
10086 11:52:12.550432 [0x00000054660000, 0x00000080000000)
10087 11:52:12.810731
10088 11:52:12.810865 [0x000000821a7280, 0x000000ffe64000)
10089 11:52:13.554876
10090 11:52:13.555045 [0x00000100000000, 0x00000240000000)
10091 11:52:15.442756
10092 11:52:15.445457 Initializing XHCI USB controller at 0x11200000.
10093 11:52:16.483403
10094 11:52:16.486787 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10095 11:52:16.486876
10096 11:52:16.486939
10097 11:52:16.486999
10098 11:52:16.487279 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10100 11:52:16.587590 asurada: tftpboot 192.168.201.1 12066517/tftp-deploy-xw34pi1y/kernel/image.itb 12066517/tftp-deploy-xw34pi1y/kernel/cmdline
10101 11:52:16.587720 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 11:52:16.587807 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10103 11:52:16.591874 tftpboot 192.168.201.1 12066517/tftp-deploy-xw34pi1y/kernel/image.itbtp-deploy-xw34pi1y/kernel/cmdline
10104 11:52:16.591965
10105 11:52:16.592063 Waiting for link
10106 11:52:16.752326
10107 11:52:16.752455 R8152: Initializing
10108 11:52:16.752527
10109 11:52:16.755550 Version 6 (ocp_data = 5c30)
10110 11:52:16.755624
10111 11:52:16.758728 R8152: Done initializing
10112 11:52:16.758826
10113 11:52:16.758913 Adding net device
10114 11:52:18.725710
10115 11:52:18.725859 done.
10116 11:52:18.725927
10117 11:52:18.725989 MAC: 00:24:32:30:78:ff
10118 11:52:18.726049
10119 11:52:18.728895 Sending DHCP discover... done.
10120 11:52:18.728978
10121 11:52:22.940898 Waiting for reply... done.
10122 11:52:22.941559
10123 11:52:22.942165 Sending DHCP request... done.
10124 11:52:22.944398
10125 11:52:22.948759 Waiting for reply... done.
10126 11:52:22.949221
10127 11:52:22.949587 My ip is 192.168.201.21
10128 11:52:22.949958
10129 11:52:22.952048 The DHCP server ip is 192.168.201.1
10130 11:52:22.952740
10131 11:52:22.958755 TFTP server IP predefined by user: 192.168.201.1
10132 11:52:22.959223
10133 11:52:22.965765 Bootfile predefined by user: 12066517/tftp-deploy-xw34pi1y/kernel/image.itb
10134 11:52:22.966268
10135 11:52:22.966650 Sending tftp read request... done.
10136 11:52:22.968738
10137 11:52:22.975670 Waiting for the transfer...
10138 11:52:22.976180
10139 11:52:23.615053 00000000 ################################################################
10140 11:52:23.615204
10141 11:52:24.156678 00080000 ################################################################
10142 11:52:24.156815
10143 11:52:24.683313 00100000 ################################################################
10144 11:52:24.683449
10145 11:52:25.211277 00180000 ################################################################
10146 11:52:25.211411
10147 11:52:25.746675 00200000 ################################################################
10148 11:52:25.746814
10149 11:52:26.282990 00280000 ################################################################
10150 11:52:26.283128
10151 11:52:26.829901 00300000 ################################################################
10152 11:52:26.830037
10153 11:52:27.360477 00380000 ################################################################
10154 11:52:27.360614
10155 11:52:27.889991 00400000 ################################################################
10156 11:52:27.890132
10157 11:52:28.475003 00480000 ################################################################
10158 11:52:28.475555
10159 11:52:29.098390 00500000 ################################################################
10160 11:52:29.098528
10161 11:52:29.679124 00580000 ################################################################
10162 11:52:29.679259
10163 11:52:30.248337 00600000 ################################################################
10164 11:52:30.248465
10165 11:52:30.806340 00680000 ################################################################
10166 11:52:30.806484
10167 11:52:31.360824 00700000 ################################################################
10168 11:52:31.360974
10169 11:52:31.955575 00780000 ################################################################
10170 11:52:31.956086
10171 11:52:32.563823 00800000 ################################################################
10172 11:52:32.563972
10173 11:52:33.146741 00880000 ################################################################
10174 11:52:33.146890
10175 11:52:33.722033 00900000 ################################################################
10176 11:52:33.722177
10177 11:52:34.270253 00980000 ################################################################
10178 11:52:34.270440
10179 11:52:34.879736 00a00000 ################################################################
10180 11:52:34.880275
10181 11:52:35.501925 00a80000 ################################################################
10182 11:52:35.502076
10183 11:52:36.087646 00b00000 ################################################################
10184 11:52:36.087793
10185 11:52:36.694167 00b80000 ################################################################
10186 11:52:36.694314
10187 11:52:37.322513 00c00000 ################################################################
10188 11:52:37.322661
10189 11:52:37.911918 00c80000 ################################################################
10190 11:52:37.912065
10191 11:52:38.477278 00d00000 ################################################################
10192 11:52:38.477425
10193 11:52:39.047797 00d80000 ################################################################
10194 11:52:39.047965
10195 11:52:39.603674 00e00000 ################################################################
10196 11:52:39.603813
10197 11:52:40.157237 00e80000 ################################################################
10198 11:52:40.157388
10199 11:52:40.700144 00f00000 ################################################################
10200 11:52:40.700302
10201 11:52:41.236138 00f80000 ################################################################
10202 11:52:41.236336
10203 11:52:41.773535 01000000 ################################################################
10204 11:52:41.773667
10205 11:52:42.349970 01080000 ################################################################
10206 11:52:42.350509
10207 11:52:43.019252 01100000 ################################################################
10208 11:52:43.019773
10209 11:52:43.692729 01180000 ################################################################
10210 11:52:43.693351
10211 11:52:44.317972 01200000 ################################################################
10212 11:52:44.318150
10213 11:52:44.873422 01280000 ################################################################
10214 11:52:44.873596
10215 11:52:45.441350 01300000 ################################################################
10216 11:52:45.441484
10217 11:52:46.003178 01380000 ################################################################
10218 11:52:46.003339
10219 11:52:46.553553 01400000 ################################################################
10220 11:52:46.553683
10221 11:52:47.136847 01480000 ################################################################
10222 11:52:47.137206
10223 11:52:47.733426 01500000 ################################################################
10224 11:52:47.733576
10225 11:52:48.280374 01580000 ################################################################
10226 11:52:48.280523
10227 11:52:48.835443 01600000 ################################################################
10228 11:52:48.835586
10229 11:52:49.399153 01680000 ################################################################
10230 11:52:49.399293
10231 11:52:49.968315 01700000 ################################################################
10232 11:52:49.968476
10233 11:52:50.542284 01780000 ################################################################
10234 11:52:50.543000
10235 11:52:51.187071 01800000 ################################################################
10236 11:52:51.187209
10237 11:52:51.755046 01880000 ################################################################
10238 11:52:51.755186
10239 11:52:52.303286 01900000 ################################################################
10240 11:52:52.303428
10241 11:52:52.889408 01980000 ################################################################
10242 11:52:52.889569
10243 11:52:53.431034 01a00000 ################################################################
10244 11:52:53.431197
10245 11:52:53.968124 01a80000 ################################################################
10246 11:52:53.968307
10247 11:52:54.503436 01b00000 ################################################################
10248 11:52:54.503571
10249 11:52:54.560518 01b80000 ####### done.
10250 11:52:54.560641
10251 11:52:54.564064 The bootfile was 28889050 bytes long.
10252 11:52:54.564172
10253 11:52:54.567376 Sending tftp read request... done.
10254 11:52:54.567514
10255 11:52:54.567607 Waiting for the transfer...
10256 11:52:54.567714
10257 11:52:54.570503 00000000 # done.
10258 11:52:54.570594
10259 11:52:54.577325 Command line loaded dynamically from TFTP file: 12066517/tftp-deploy-xw34pi1y/kernel/cmdline
10260 11:52:54.577407
10261 11:52:54.600737 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10262 11:52:54.600836
10263 11:52:54.600910 Loading FIT.
10264 11:52:54.601008
10265 11:52:54.603884 Image ramdisk-1 has 17792555 bytes.
10266 11:52:54.603984
10267 11:52:54.607282 Image fdt-1 has 47278 bytes.
10268 11:52:54.607393
10269 11:52:54.610432 Image kernel-1 has 11047184 bytes.
10270 11:52:54.610576
10271 11:52:54.620185 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10272 11:52:54.620356
10273 11:52:54.636794 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10274 11:52:54.636883
10275 11:52:54.643350 Choosing best match conf-1 for compat google,spherion-rev2.
10276 11:52:54.643454
10277 11:52:54.651056 Connected to device vid:did:rid of 1ae0:0028:00
10278 11:52:54.658877
10279 11:52:54.662260 tpm_get_response: command 0x17b, return code 0x0
10280 11:52:54.662344
10281 11:52:54.665428 ec_init: CrosEC protocol v3 supported (256, 248)
10282 11:52:54.669243
10283 11:52:54.673123 tpm_cleanup: add release locality here.
10284 11:52:54.673203
10285 11:52:54.673298 Shutting down all USB controllers.
10286 11:52:54.676027
10287 11:52:54.676124 Removing current net device
10288 11:52:54.676236
10289 11:52:54.682622 Exiting depthcharge with code 4 at timestamp: 71575411
10290 11:52:54.682703
10291 11:52:54.686331 LZMA decompressing kernel-1 to 0x821a6718
10292 11:52:54.686412
10293 11:52:54.689469 LZMA decompressing kernel-1 to 0x40000000
10294 11:52:56.077972
10295 11:52:56.078110 jumping to kernel
10296 11:52:56.078561 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10297 11:52:56.078657 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10298 11:52:56.078742 Setting prompt string to ['Linux version [0-9]']
10299 11:52:56.078857 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10300 11:52:56.078964 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10301 11:52:56.160021
10302 11:52:56.163338 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10303 11:52:56.166622 start: 2.2.5.1 login-action (timeout 00:03:41) [common]
10304 11:52:56.166719 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10305 11:52:56.166790 Setting prompt string to []
10306 11:52:56.166923 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10307 11:52:56.166998 Using line separator: #'\n'#
10308 11:52:56.167057 No login prompt set.
10309 11:52:56.167119 Parsing kernel messages
10310 11:52:56.167174 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10311 11:52:56.167279 [login-action] Waiting for messages, (timeout 00:03:41)
10312 11:52:56.186198 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10313 11:52:56.189482 [ 0.000000] random: crng init done
10314 11:52:56.196172 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10315 11:52:56.199492 [ 0.000000] efi: UEFI not found.
10316 11:52:56.206522 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10317 11:52:56.213003 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10318 11:52:56.222677 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10319 11:52:56.232890 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10320 11:52:56.239125 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10321 11:52:56.245952 [ 0.000000] printk: bootconsole [mtk8250] enabled
10322 11:52:56.249609 [ 0.000000] NUMA: No NUMA configuration found
10323 11:52:56.259480 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10324 11:52:56.262271 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10325 11:52:56.265558 [ 0.000000] Zone ranges:
10326 11:52:56.272618 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10327 11:52:56.275746 [ 0.000000] DMA32 empty
10328 11:52:56.282503 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10329 11:52:56.285860 [ 0.000000] Movable zone start for each node
10330 11:52:56.289186 [ 0.000000] Early memory node ranges
10331 11:52:56.295661 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10332 11:52:56.301983 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10333 11:52:56.308550 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10334 11:52:56.315032 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10335 11:52:56.318852 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10336 11:52:56.328356 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10337 11:52:56.384107 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10338 11:52:56.390608 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10339 11:52:56.397114 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10340 11:52:56.400399 [ 0.000000] psci: probing for conduit method from DT.
10341 11:52:56.407370 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10342 11:52:56.410507 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10343 11:52:56.416920 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10344 11:52:56.420519 [ 0.000000] psci: SMC Calling Convention v1.2
10345 11:52:56.427303 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10346 11:52:56.430156 [ 0.000000] Detected VIPT I-cache on CPU0
10347 11:52:56.437107 [ 0.000000] CPU features: detected: GIC system register CPU interface
10348 11:52:56.443594 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10349 11:52:56.450208 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10350 11:52:56.456763 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10351 11:52:56.463520 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10352 11:52:56.473383 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10353 11:52:56.476843 [ 0.000000] alternatives: applying boot alternatives
10354 11:52:56.483373 [ 0.000000] Fallback order for Node 0: 0
10355 11:52:56.489779 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10356 11:52:56.493344 [ 0.000000] Policy zone: Normal
10357 11:52:56.516405 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10358 11:52:56.526347 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10359 11:52:56.536705 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10360 11:52:56.547248 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10361 11:52:56.553263 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10362 11:52:56.556640 <6>[ 0.000000] software IO TLB: area num 8.
10363 11:52:56.612697 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10364 11:52:56.762363 <6>[ 0.000000] Memory: 7952244K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 400524K reserved, 32768K cma-reserved)
10365 11:52:56.768345 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10366 11:52:56.775108 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10367 11:52:56.778299 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10368 11:52:56.784935 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10369 11:52:56.791945 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10370 11:52:56.795277 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10371 11:52:56.805095 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10372 11:52:56.811638 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10373 11:52:56.818546 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10374 11:52:56.824609 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10375 11:52:56.828113 <6>[ 0.000000] GICv3: 608 SPIs implemented
10376 11:52:56.831948 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10377 11:52:56.838647 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10378 11:52:56.841358 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10379 11:52:56.848139 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10380 11:52:56.861022 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10381 11:52:56.874253 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10382 11:52:56.880744 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10383 11:52:56.888777 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10384 11:52:56.901848 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10385 11:52:56.908701 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10386 11:52:56.915170 <6>[ 0.009182] Console: colour dummy device 80x25
10387 11:52:56.924857 <6>[ 0.013938] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10388 11:52:56.931358 <6>[ 0.024446] pid_max: default: 32768 minimum: 301
10389 11:52:56.934791 <6>[ 0.029319] LSM: Security Framework initializing
10390 11:52:56.941409 <6>[ 0.034257] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10391 11:52:56.951649 <6>[ 0.042070] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10392 11:52:56.958234 <6>[ 0.051479] cblist_init_generic: Setting adjustable number of callback queues.
10393 11:52:56.964570 <6>[ 0.058923] cblist_init_generic: Setting shift to 3 and lim to 1.
10394 11:52:56.974486 <6>[ 0.065262] cblist_init_generic: Setting adjustable number of callback queues.
10395 11:52:56.981105 <6>[ 0.072689] cblist_init_generic: Setting shift to 3 and lim to 1.
10396 11:52:56.984775 <6>[ 0.079089] rcu: Hierarchical SRCU implementation.
10397 11:52:56.991136 <6>[ 0.084135] rcu: Max phase no-delay instances is 1000.
10398 11:52:56.997970 <6>[ 0.091160] EFI services will not be available.
10399 11:52:57.001154 <6>[ 0.096112] smp: Bringing up secondary CPUs ...
10400 11:52:57.009229 <6>[ 0.101189] Detected VIPT I-cache on CPU1
10401 11:52:57.015972 <6>[ 0.101260] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10402 11:52:57.022512 <6>[ 0.101293] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10403 11:52:57.026119 <6>[ 0.101629] Detected VIPT I-cache on CPU2
10404 11:52:57.032679 <6>[ 0.101680] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10405 11:52:57.039517 <6>[ 0.101697] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10406 11:52:57.045808 <6>[ 0.101955] Detected VIPT I-cache on CPU3
10407 11:52:57.052532 <6>[ 0.102001] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10408 11:52:57.059359 <6>[ 0.102015] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10409 11:52:57.062280 <6>[ 0.102318] CPU features: detected: Spectre-v4
10410 11:52:57.069047 <6>[ 0.102326] CPU features: detected: Spectre-BHB
10411 11:52:57.072651 <6>[ 0.102331] Detected PIPT I-cache on CPU4
10412 11:52:57.078807 <6>[ 0.102388] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10413 11:52:57.085486 <6>[ 0.102404] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10414 11:52:57.092411 <6>[ 0.102696] Detected PIPT I-cache on CPU5
10415 11:52:57.098761 <6>[ 0.102757] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10416 11:52:57.105223 <6>[ 0.102774] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10417 11:52:57.109105 <6>[ 0.103053] Detected PIPT I-cache on CPU6
10418 11:52:57.115395 <6>[ 0.103116] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10419 11:52:57.122175 <6>[ 0.103132] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10420 11:52:57.128769 <6>[ 0.103427] Detected PIPT I-cache on CPU7
10421 11:52:57.135122 <6>[ 0.103491] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10422 11:52:57.141700 <6>[ 0.103508] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10423 11:52:57.144951 <6>[ 0.103555] smp: Brought up 1 node, 8 CPUs
10424 11:52:57.151402 <6>[ 0.244851] SMP: Total of 8 processors activated.
10425 11:52:57.154898 <6>[ 0.249802] CPU features: detected: 32-bit EL0 Support
10426 11:52:57.164941 <6>[ 0.255186] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10427 11:52:57.171470 <6>[ 0.263987] CPU features: detected: Common not Private translations
10428 11:52:57.177930 <6>[ 0.270462] CPU features: detected: CRC32 instructions
10429 11:52:57.181468 <6>[ 0.275813] CPU features: detected: RCpc load-acquire (LDAPR)
10430 11:52:57.188155 <6>[ 0.281773] CPU features: detected: LSE atomic instructions
10431 11:52:57.194606 <6>[ 0.287555] CPU features: detected: Privileged Access Never
10432 11:52:57.201093 <6>[ 0.293334] CPU features: detected: RAS Extension Support
10433 11:52:57.207904 <6>[ 0.298943] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10434 11:52:57.211196 <6>[ 0.306162] CPU: All CPU(s) started at EL2
10435 11:52:57.217753 <6>[ 0.310505] alternatives: applying system-wide alternatives
10436 11:52:57.227082 <6>[ 0.321241] devtmpfs: initialized
10437 11:52:57.239467 <6>[ 0.330130] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10438 11:52:57.249153 <6>[ 0.340094] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10439 11:52:57.255727 <6>[ 0.348113] pinctrl core: initialized pinctrl subsystem
10440 11:52:57.259281 <6>[ 0.354780] DMI not present or invalid.
10441 11:52:57.265792 <6>[ 0.359190] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10442 11:52:57.275414 <6>[ 0.366054] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10443 11:52:57.282065 <6>[ 0.373637] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10444 11:52:57.291850 <6>[ 0.381851] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10445 11:52:57.295119 <6>[ 0.390095] audit: initializing netlink subsys (disabled)
10446 11:52:57.305330 <5>[ 0.395787] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10447 11:52:57.311730 <6>[ 0.396490] thermal_sys: Registered thermal governor 'step_wise'
10448 11:52:57.318197 <6>[ 0.403756] thermal_sys: Registered thermal governor 'power_allocator'
10449 11:52:57.321569 <6>[ 0.410009] cpuidle: using governor menu
10450 11:52:57.328104 <6>[ 0.420971] NET: Registered PF_QIPCRTR protocol family
10451 11:52:57.334785 <6>[ 0.426467] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10452 11:52:57.341354 <6>[ 0.433571] ASID allocator initialised with 32768 entries
10453 11:52:57.344662 <6>[ 0.440136] Serial: AMBA PL011 UART driver
10454 11:52:57.354518 <4>[ 0.448920] Trying to register duplicate clock ID: 134
10455 11:52:57.408946 <6>[ 0.506758] KASLR enabled
10456 11:52:57.423543 <6>[ 0.514446] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10457 11:52:57.430275 <6>[ 0.521460] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10458 11:52:57.436770 <6>[ 0.527950] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10459 11:52:57.443250 <6>[ 0.534956] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10460 11:52:57.449719 <6>[ 0.541442] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10461 11:52:57.456159 <6>[ 0.548448] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10462 11:52:57.462823 <6>[ 0.554937] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10463 11:52:57.469732 <6>[ 0.561943] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10464 11:52:57.472656 <6>[ 0.569439] ACPI: Interpreter disabled.
10465 11:52:57.481770 <6>[ 0.575793] iommu: Default domain type: Translated
10466 11:52:57.488130 <6>[ 0.580904] iommu: DMA domain TLB invalidation policy: strict mode
10467 11:52:57.491713 <5>[ 0.587555] SCSI subsystem initialized
10468 11:52:57.498133 <6>[ 0.591698] usbcore: registered new interface driver usbfs
10469 11:52:57.504975 <6>[ 0.597429] usbcore: registered new interface driver hub
10470 11:52:57.508176 <6>[ 0.602980] usbcore: registered new device driver usb
10471 11:52:57.514799 <6>[ 0.609064] pps_core: LinuxPPS API ver. 1 registered
10472 11:52:57.524305 <6>[ 0.614258] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10473 11:52:57.527919 <6>[ 0.623604] PTP clock support registered
10474 11:52:57.531115 <6>[ 0.627844] EDAC MC: Ver: 3.0.0
10475 11:52:57.538681 <6>[ 0.633000] FPGA manager framework
10476 11:52:57.545678 <6>[ 0.636679] Advanced Linux Sound Architecture Driver Initialized.
10477 11:52:57.548817 <6>[ 0.643447] vgaarb: loaded
10478 11:52:57.555234 <6>[ 0.646628] clocksource: Switched to clocksource arch_sys_counter
10479 11:52:57.558761 <5>[ 0.653061] VFS: Disk quotas dquot_6.6.0
10480 11:52:57.565099 <6>[ 0.657244] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10481 11:52:57.568713 <6>[ 0.664430] pnp: PnP ACPI: disabled
10482 11:52:57.576996 <6>[ 0.671057] NET: Registered PF_INET protocol family
10483 11:52:57.586898 <6>[ 0.676641] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10484 11:52:57.598003 <6>[ 0.688957] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10485 11:52:57.608073 <6>[ 0.697769] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10486 11:52:57.614524 <6>[ 0.705742] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10487 11:52:57.621474 <6>[ 0.714443] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10488 11:52:57.633104 <6>[ 0.724192] TCP: Hash tables configured (established 65536 bind 65536)
10489 11:52:57.640027 <6>[ 0.731049] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10490 11:52:57.646480 <6>[ 0.738249] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10491 11:52:57.652909 <6>[ 0.745950] NET: Registered PF_UNIX/PF_LOCAL protocol family
10492 11:52:57.659659 <6>[ 0.752123] RPC: Registered named UNIX socket transport module.
10493 11:52:57.663070 <6>[ 0.758276] RPC: Registered udp transport module.
10494 11:52:57.669712 <6>[ 0.763211] RPC: Registered tcp transport module.
10495 11:52:57.675833 <6>[ 0.768145] RPC: Registered tcp NFSv4.1 backchannel transport module.
10496 11:52:57.679260 <6>[ 0.774813] PCI: CLS 0 bytes, default 64
10497 11:52:57.682608 <6>[ 0.779206] Unpacking initramfs...
10498 11:52:57.707583 <6>[ 0.798731] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10499 11:52:57.717581 <6>[ 0.807385] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10500 11:52:57.720823 <6>[ 0.816238] kvm [1]: IPA Size Limit: 40 bits
10501 11:52:57.727538 <6>[ 0.820765] kvm [1]: GICv3: no GICV resource entry
10502 11:52:57.730920 <6>[ 0.825786] kvm [1]: disabling GICv2 emulation
10503 11:52:57.737600 <6>[ 0.830472] kvm [1]: GIC system register CPU interface enabled
10504 11:52:57.740761 <6>[ 0.836636] kvm [1]: vgic interrupt IRQ18
10505 11:52:57.747827 <6>[ 0.840991] kvm [1]: VHE mode initialized successfully
10506 11:52:57.754277 <5>[ 0.847468] Initialise system trusted keyrings
10507 11:52:57.760679 <6>[ 0.852316] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10508 11:52:57.768015 <6>[ 0.862386] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10509 11:52:57.774857 <5>[ 0.868824] NFS: Registering the id_resolver key type
10510 11:52:57.778057 <5>[ 0.874127] Key type id_resolver registered
10511 11:52:57.784814 <5>[ 0.878542] Key type id_legacy registered
10512 11:52:57.791013 <6>[ 0.882819] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10513 11:52:57.798247 <6>[ 0.889741] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10514 11:52:57.804653 <6>[ 0.897458] 9p: Installing v9fs 9p2000 file system support
10515 11:52:57.839979 <5>[ 0.934335] Key type asymmetric registered
10516 11:52:57.843445 <5>[ 0.938669] Asymmetric key parser 'x509' registered
10517 11:52:57.853423 <6>[ 0.943816] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10518 11:52:57.856694 <6>[ 0.951452] io scheduler mq-deadline registered
10519 11:52:57.860031 <6>[ 0.956216] io scheduler kyber registered
10520 11:52:57.878863 <6>[ 0.973174] EINJ: ACPI disabled.
10521 11:52:57.911389 <4>[ 0.999001] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10522 11:52:57.921044 <4>[ 1.009636] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10523 11:52:57.936021 <6>[ 1.030414] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10524 11:52:57.944009 <6>[ 1.038398] printk: console [ttyS0] disabled
10525 11:52:57.972319 <6>[ 1.063047] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10526 11:52:57.978654 <6>[ 1.072521] printk: console [ttyS0] enabled
10527 11:52:57.981706 <6>[ 1.072521] printk: console [ttyS0] enabled
10528 11:52:57.988662 <6>[ 1.081417] printk: bootconsole [mtk8250] disabled
10529 11:52:57.991589 <6>[ 1.081417] printk: bootconsole [mtk8250] disabled
10530 11:52:57.998459 <6>[ 1.092631] SuperH (H)SCI(F) driver initialized
10531 11:52:58.001607 <6>[ 1.097910] msm_serial: driver initialized
10532 11:52:58.016339 <6>[ 1.106938] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10533 11:52:58.026198 <6>[ 1.115489] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10534 11:52:58.032534 <6>[ 1.124033] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10535 11:52:58.042861 <6>[ 1.132665] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10536 11:52:58.049424 <6>[ 1.141372] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10537 11:52:58.059695 <6>[ 1.150094] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10538 11:52:58.069291 <6>[ 1.158640] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10539 11:52:58.075689 <6>[ 1.167447] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10540 11:52:58.085824 <6>[ 1.175994] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10541 11:52:58.097173 <6>[ 1.191677] loop: module loaded
10542 11:52:58.104101 <6>[ 1.197676] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10543 11:52:58.126783 <4>[ 1.221123] mtk-pmic-keys: Failed to locate of_node [id: -1]
10544 11:52:58.133891 <6>[ 1.228078] megasas: 07.719.03.00-rc1
10545 11:52:58.143150 <6>[ 1.237681] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10546 11:52:58.152054 <6>[ 1.246016] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10547 11:52:58.168498 <6>[ 1.262540] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10548 11:52:58.224819 <6>[ 1.312301] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10549 11:52:58.425663 <6>[ 1.520046] Freeing initrd memory: 17372K
10550 11:52:58.436107 <6>[ 1.530414] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10551 11:52:58.446942 <6>[ 1.541285] tun: Universal TUN/TAP device driver, 1.6
10552 11:52:58.450127 <6>[ 1.547343] thunder_xcv, ver 1.0
10553 11:52:58.453932 <6>[ 1.550846] thunder_bgx, ver 1.0
10554 11:52:58.457079 <6>[ 1.554337] nicpf, ver 1.0
10555 11:52:58.467270 <6>[ 1.558350] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10556 11:52:58.470807 <6>[ 1.565826] hns3: Copyright (c) 2017 Huawei Corporation.
10557 11:52:58.477039 <6>[ 1.571431] hclge is initializing
10558 11:52:58.480804 <6>[ 1.575013] e1000: Intel(R) PRO/1000 Network Driver
10559 11:52:58.487197 <6>[ 1.580142] e1000: Copyright (c) 1999-2006 Intel Corporation.
10560 11:52:58.490553 <6>[ 1.586155] e1000e: Intel(R) PRO/1000 Network Driver
10561 11:52:58.497299 <6>[ 1.591371] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10562 11:52:58.503790 <6>[ 1.597556] igb: Intel(R) Gigabit Ethernet Network Driver
10563 11:52:58.510806 <6>[ 1.603206] igb: Copyright (c) 2007-2014 Intel Corporation.
10564 11:52:58.517400 <6>[ 1.609042] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10565 11:52:58.524089 <6>[ 1.615561] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10566 11:52:58.527161 <6>[ 1.622027] sky2: driver version 1.30
10567 11:52:58.533910 <6>[ 1.627027] VFIO - User Level meta-driver version: 0.3
10568 11:52:58.540808 <6>[ 1.635304] usbcore: registered new interface driver usb-storage
10569 11:52:58.547739 <6>[ 1.641743] usbcore: registered new device driver onboard-usb-hub
10570 11:52:58.556885 <6>[ 1.650870] mt6397-rtc mt6359-rtc: registered as rtc0
10571 11:52:58.567047 <6>[ 1.656333] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:52:59 UTC (1700740379)
10572 11:52:58.569652 <6>[ 1.665913] i2c_dev: i2c /dev entries driver
10573 11:52:58.586984 <6>[ 1.677601] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10574 11:52:58.607108 <6>[ 1.701583] cpu cpu0: EM: created perf domain
10575 11:52:58.610805 <6>[ 1.706524] cpu cpu4: EM: created perf domain
10576 11:52:58.618209 <6>[ 1.712127] sdhci: Secure Digital Host Controller Interface driver
10577 11:52:58.624480 <6>[ 1.718562] sdhci: Copyright(c) Pierre Ossman
10578 11:52:58.631148 <6>[ 1.723510] Synopsys Designware Multimedia Card Interface Driver
10579 11:52:58.638381 <6>[ 1.730142] sdhci-pltfm: SDHCI platform and OF driver helper
10580 11:52:58.641805 <6>[ 1.730256] mmc0: CQHCI version 5.10
10581 11:52:58.648388 <6>[ 1.740146] ledtrig-cpu: registered to indicate activity on CPUs
10582 11:52:58.655037 <6>[ 1.747116] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10583 11:52:58.661966 <6>[ 1.754167] usbcore: registered new interface driver usbhid
10584 11:52:58.664792 <6>[ 1.759991] usbhid: USB HID core driver
10585 11:52:58.672167 <6>[ 1.764177] spi_master spi0: will run message pump with realtime priority
10586 11:52:58.714832 <6>[ 1.802279] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10587 11:52:58.730923 <6>[ 1.818347] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10588 11:52:58.738083 <6>[ 1.831913] mmc0: Command Queue Engine enabled
10589 11:52:58.744640 <6>[ 1.836671] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10590 11:52:58.750811 <6>[ 1.843981] mmcblk0: mmc0:0001 DA4128 116 GiB
10591 11:52:58.754390 <6>[ 1.848924] cros-ec-spi spi0.0: Chrome EC device registered
10592 11:52:58.761133 <6>[ 1.852905] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10593 11:52:58.768602 <6>[ 1.862453] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10594 11:52:58.775031 <6>[ 1.868671] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10595 11:52:58.781437 <6>[ 1.874633] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10596 11:52:58.801448 <6>[ 1.892371] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10597 11:52:58.809061 <6>[ 1.903184] NET: Registered PF_PACKET protocol family
10598 11:52:58.812297 <6>[ 1.908576] 9pnet: Installing 9P2000 support
10599 11:52:58.819003 <5>[ 1.913142] Key type dns_resolver registered
10600 11:52:58.822062 <6>[ 1.918135] registered taskstats version 1
10601 11:52:58.828628 <5>[ 1.922517] Loading compiled-in X.509 certificates
10602 11:52:58.860159 <4>[ 1.947641] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 11:52:58.870143 <4>[ 1.958378] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 11:52:58.876921 <3>[ 1.968915] debugfs: File 'uA_load' in directory '/' already present!
10605 11:52:58.883417 <3>[ 1.975617] debugfs: File 'min_uV' in directory '/' already present!
10606 11:52:58.889996 <3>[ 1.982225] debugfs: File 'max_uV' in directory '/' already present!
10607 11:52:58.896353 <3>[ 1.988831] debugfs: File 'constraint_flags' in directory '/' already present!
10608 11:52:58.908764 <3>[ 1.999692] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10609 11:52:58.921464 <6>[ 2.015362] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10610 11:52:58.927938 <6>[ 2.022262] xhci-mtk 11200000.usb: xHCI Host Controller
10611 11:52:58.934751 <6>[ 2.027766] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10612 11:52:58.944662 <6>[ 2.035632] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10613 11:52:58.951328 <6>[ 2.045047] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10614 11:52:58.957894 <6>[ 2.051109] xhci-mtk 11200000.usb: xHCI Host Controller
10615 11:52:58.964248 <6>[ 2.056586] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10616 11:52:58.971103 <6>[ 2.064233] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10617 11:52:58.977560 <6>[ 2.071858] hub 1-0:1.0: USB hub found
10618 11:52:58.981410 <6>[ 2.075872] hub 1-0:1.0: 1 port detected
10619 11:52:58.987438 <6>[ 2.080139] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10620 11:52:58.994313 <6>[ 2.088644] hub 2-0:1.0: USB hub found
10621 11:52:58.997718 <6>[ 2.092654] hub 2-0:1.0: 1 port detected
10622 11:52:59.005141 <6>[ 2.099632] mtk-msdc 11f70000.mmc: Got CD GPIO
10623 11:52:59.016544 <6>[ 2.107365] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10624 11:52:59.022927 <6>[ 2.115386] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10625 11:52:59.032662 <4>[ 2.123290] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10626 11:52:59.042711 <6>[ 2.132813] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10627 11:52:59.050238 <6>[ 2.140894] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10628 11:52:59.056088 <6>[ 2.149047] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10629 11:52:59.066021 <6>[ 2.157004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10630 11:52:59.072885 <6>[ 2.164822] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10631 11:52:59.082500 <6>[ 2.172640] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10632 11:52:59.093119 <6>[ 2.183211] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10633 11:52:59.099811 <6>[ 2.191594] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10634 11:52:59.110097 <6>[ 2.199934] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10635 11:52:59.116434 <6>[ 2.208276] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10636 11:52:59.126484 <6>[ 2.216614] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10637 11:52:59.133142 <6>[ 2.224953] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10638 11:52:59.143238 <6>[ 2.233293] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10639 11:52:59.149594 <6>[ 2.241631] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10640 11:52:59.159574 <6>[ 2.249970] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10641 11:52:59.166389 <6>[ 2.258313] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10642 11:52:59.176534 <6>[ 2.266655] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10643 11:52:59.182969 <6>[ 2.274994] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10644 11:52:59.192323 <6>[ 2.283332] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10645 11:52:59.202661 <6>[ 2.291670] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10646 11:52:59.209394 <6>[ 2.300008] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10647 11:52:59.215933 <6>[ 2.308821] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10648 11:52:59.222705 <6>[ 2.316125] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10649 11:52:59.229294 <6>[ 2.323071] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10650 11:52:59.239687 <6>[ 2.329937] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10651 11:52:59.246272 <6>[ 2.336898] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10652 11:52:59.252759 <6>[ 2.343748] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10653 11:52:59.262438 <6>[ 2.352874] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10654 11:52:59.272480 <6>[ 2.361993] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10655 11:52:59.282482 <6>[ 2.371308] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10656 11:52:59.292055 <6>[ 2.380781] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10657 11:52:59.302039 <6>[ 2.390249] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10658 11:52:59.308507 <6>[ 2.399371] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10659 11:52:59.318444 <6>[ 2.408838] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10660 11:52:59.328771 <6>[ 2.417956] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10661 11:52:59.338754 <6>[ 2.427249] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10662 11:52:59.348435 <6>[ 2.437408] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10663 11:52:59.358782 <6>[ 2.449080] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10664 11:52:59.364952 <6>[ 2.458888] Trying to probe devices needed for running init ...
10665 11:52:59.388070 <6>[ 2.479064] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10666 11:52:59.415484 <6>[ 2.509539] hub 2-1:1.0: USB hub found
10667 11:52:59.419118 <6>[ 2.513962] hub 2-1:1.0: 3 ports detected
10668 11:52:59.426896 <6>[ 2.520782] hub 2-1:1.0: USB hub found
10669 11:52:59.430446 <6>[ 2.525246] hub 2-1:1.0: 3 ports detected
10670 11:52:59.540317 <6>[ 2.630923] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10671 11:52:59.699007 <6>[ 2.792799] hub 1-1:1.0: USB hub found
10672 11:52:59.702021 <6>[ 2.797296] hub 1-1:1.0: 4 ports detected
10673 11:52:59.712019 <6>[ 2.805777] hub 1-1:1.0: USB hub found
10674 11:52:59.714964 <6>[ 2.810314] hub 1-1:1.0: 4 ports detected
10675 11:52:59.784312 <6>[ 2.874981] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10676 11:53:00.036341 <6>[ 3.126881] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10677 11:53:00.168568 <6>[ 3.262643] hub 1-1.4:1.0: USB hub found
10678 11:53:00.171972 <6>[ 3.267274] hub 1-1.4:1.0: 2 ports detected
10679 11:53:00.181714 <6>[ 3.275788] hub 1-1.4:1.0: USB hub found
10680 11:53:00.184771 <6>[ 3.280376] hub 1-1.4:1.0: 2 ports detected
10681 11:53:00.484345 <6>[ 3.574889] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10682 11:53:00.672085 <6>[ 3.762924] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10683 11:53:11.636591 <6>[ 14.735909] ALSA device list:
10684 11:53:11.643663 <6>[ 14.739204] No soundcards found.
10685 11:53:11.651334 <6>[ 14.747156] Freeing unused kernel memory: 8384K
10686 11:53:11.654596 <6>[ 14.752140] Run /init as init process
10687 11:53:11.666082 Loading, please wait...
10688 11:53:11.686711 Starting version 247.3-7+deb11u2
10689 11:53:11.911603 <6>[ 15.004209] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10690 11:53:11.922055 <6>[ 15.017786] remoteproc remoteproc0: scp is available
10691 11:53:11.932127 <3>[ 15.020858] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10692 11:53:11.935135 <6>[ 15.023725] remoteproc remoteproc0: powering up scp
10693 11:53:11.945211 <3>[ 15.031706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10694 11:53:11.951656 <6>[ 15.036738] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10695 11:53:11.961517 <3>[ 15.044887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10696 11:53:11.965265 <6>[ 15.053064] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10697 11:53:11.974923 <6>[ 15.054874] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10698 11:53:11.981439 <3>[ 15.061352] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10699 11:53:11.988167 <6>[ 15.063674] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10700 11:53:11.998119 <6>[ 15.063703] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10701 11:53:12.008163 <6>[ 15.063708] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10702 11:53:12.011443 <6>[ 15.075515] usbcore: registered new interface driver r8152
10703 11:53:12.021073 <3>[ 15.082540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10704 11:53:12.027977 <3>[ 15.082546] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 11:53:12.037716 <3>[ 15.082557] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10706 11:53:12.044358 <3>[ 15.082565] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10707 11:53:12.054467 <3>[ 15.082638] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 11:53:12.060947 <4>[ 15.096016] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10709 11:53:12.068433 <4>[ 15.096016] Fallback method does not support PEC.
10710 11:53:12.074971 <3>[ 15.122088] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10711 11:53:12.081960 <4>[ 15.130502] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10712 11:53:12.091435 <3>[ 15.137501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10713 11:53:12.098374 <3>[ 15.137506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10714 11:53:12.101379 <6>[ 15.139188] mc: Linux media interface: v0.10
10715 11:53:12.112143 <3>[ 15.142064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10716 11:53:12.118645 <3>[ 15.142078] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10717 11:53:12.128797 <3>[ 15.142082] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10718 11:53:12.135245 <3>[ 15.142086] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10719 11:53:12.141735 <3>[ 15.142089] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10720 11:53:12.152129 <3>[ 15.148142] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 11:53:12.158478 <4>[ 15.148229] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10722 11:53:12.168129 <3>[ 15.169783] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10723 11:53:12.175188 <6>[ 15.180458] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10724 11:53:12.182010 <6>[ 15.192155] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10725 11:53:12.188468 <6>[ 15.192162] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10726 11:53:12.195027 <6>[ 15.199148] pci_bus 0000:00: root bus resource [bus 00-ff]
10727 11:53:12.201682 <6>[ 15.203678] remoteproc remoteproc0: remote processor scp is now up
10728 11:53:12.211903 <6>[ 15.204985] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10729 11:53:12.218214 <6>[ 15.211774] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10730 11:53:12.228432 <6>[ 15.211780] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10731 11:53:12.235206 <6>[ 15.211831] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10732 11:53:12.242044 <6>[ 15.219967] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10733 11:53:12.248111 <6>[ 15.222428] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10734 11:53:12.258056 <6>[ 15.227984] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10735 11:53:12.264769 <3>[ 15.239193] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10736 11:53:12.271260 <6>[ 15.244900] pci 0000:00:00.0: supports D1 D2
10737 11:53:12.278136 <4>[ 15.262392] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10738 11:53:12.284563 <6>[ 15.268430] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10739 11:53:12.294307 <4>[ 15.275332] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10740 11:53:12.304920 <6>[ 15.279261] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10741 11:53:12.314334 <6>[ 15.279586] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10742 11:53:12.321356 <6>[ 15.279805] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10743 11:53:12.327906 <6>[ 15.284563] usbcore: registered new interface driver cdc_ether
10744 11:53:12.337360 <6>[ 15.285521] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10745 11:53:12.344035 <6>[ 15.285705] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10746 11:53:12.350872 <6>[ 15.285742] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10747 11:53:12.357128 <6>[ 15.285765] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10748 11:53:12.363984 <6>[ 15.285781] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10749 11:53:12.370375 <6>[ 15.285905] pci 0000:01:00.0: supports D1 D2
10750 11:53:12.377017 <6>[ 15.285909] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10751 11:53:12.383595 <6>[ 15.299034] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10752 11:53:12.390286 <6>[ 15.299893] videodev: Linux video capture interface: v2.00
10753 11:53:12.396956 <6>[ 15.312615] usbcore: registered new interface driver r8153_ecm
10754 11:53:12.400139 <6>[ 15.312713] Bluetooth: Core ver 2.22
10755 11:53:12.403776 <6>[ 15.312852] NET: Registered PF_BLUETOOTH protocol family
10756 11:53:12.409930 <6>[ 15.312857] Bluetooth: HCI device and connection manager initialized
10757 11:53:12.416635 <6>[ 15.312910] Bluetooth: HCI socket layer initialized
10758 11:53:12.423479 <6>[ 15.312926] Bluetooth: L2CAP socket layer initialized
10759 11:53:12.426476 <6>[ 15.312944] Bluetooth: SCO socket layer initialized
10760 11:53:12.436434 <6>[ 15.318879] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10761 11:53:12.443218 <6>[ 15.359522] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10762 11:53:12.449717 <6>[ 15.366636] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10763 11:53:12.459504 <6>[ 15.366647] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10764 11:53:12.463049 <6>[ 15.367497] usbcore: registered new interface driver btusb
10765 11:53:12.469878 <6>[ 15.371345] r8152 2-1.3:1.0 eth0: v1.12.13
10766 11:53:12.479630 <4>[ 15.371588] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10767 11:53:12.485878 <3>[ 15.371596] Bluetooth: hci0: Failed to load firmware file (-2)
10768 11:53:12.489765 <3>[ 15.371598] Bluetooth: hci0: Failed to set up firmware (-2)
10769 11:53:12.502630 <4>[ 15.371601] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10770 11:53:12.512788 <6>[ 15.372870] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10771 11:53:12.519285 <6>[ 15.373037] usbcore: registered new interface driver uvcvideo
10772 11:53:12.529059 <6>[ 15.380210] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10773 11:53:12.535298 <6>[ 15.380223] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10774 11:53:12.542493 <6>[ 15.380789] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10775 11:53:12.549148 <6>[ 15.394513] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10776 11:53:12.552303 <6>[ 15.395160] pci 0000:00:00.0: PCI bridge to [bus 01]
10777 11:53:12.562124 <6>[ 15.654279] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10778 11:53:12.568970 <6>[ 15.662415] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10779 11:53:12.575242 <6>[ 15.669343] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10780 11:53:12.581759 <6>[ 15.675984] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10781 11:53:12.604605 <5>[ 15.697433] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10782 11:53:12.623595 <5>[ 15.716129] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10783 11:53:12.630448 <4>[ 15.723043] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10784 11:53:12.637113 <6>[ 15.731931] cfg80211: failed to load regulatory.db
10785 11:53:12.697079 <6>[ 15.789782] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10786 11:53:12.703893 <6>[ 15.797351] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10787 11:53:12.728044 <6>[ 15.824052] mt7921e 0000:01:00.0: ASIC revision: 79610010
10788 11:53:12.834973 <4>[ 15.924393] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10789 11:53:12.838273 Begin: Loading essential drivers ... done.
10790 11:53:12.841527 Begin: Running /scripts/init-premount ... done.
10791 11:53:12.851670 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10792 11:53:12.858048 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10793 11:53:12.861852 Device /sys/class/net/enx0024323078ff found
10794 11:53:12.864558 done.
10795 11:53:12.901927 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10796 11:53:12.956036 <4>[ 16.044938] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10797 11:53:13.072590 <4>[ 16.161721] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10798 11:53:13.193490 <4>[ 16.282450] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10799 11:53:13.313898 <4>[ 16.402671] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10800 11:53:13.433707 <4>[ 16.522479] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10801 11:53:13.553415 <4>[ 16.642596] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 11:53:13.673770 <4>[ 16.762523] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 11:53:13.793216 <4>[ 16.882375] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 11:53:13.891318 <6>[ 16.987004] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10805 11:53:13.913792 <4>[ 17.002227] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 11:53:14.025138 <3>[ 17.120476] mt7921e 0000:01:00.0: hardware init failed
10807 11:53:14.060485 IP-Config: no response after 2 secs - giving up
10808 11:53:14.098408 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10809 11:53:14.105214 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10810 11:53:14.111570 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10811 11:53:14.118452 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10812 11:53:14.124986 host : mt8192-asurada-spherion-r0-cbg-8
10813 11:53:14.131918 domain : lava-rack
10814 11:53:14.134752 rootserver: 192.168.201.1 rootpath:
10815 11:53:14.138079 filename :
10816 11:53:14.251437 done.
10817 11:53:14.259425 Begin: Running /scripts/nfs-bottom ... done.
10818 11:53:14.277985 Begin: Running /scripts/init-bottom ... done.
10819 11:53:15.495645 <6>[ 18.591903] NET: Registered PF_INET6 protocol family
10820 11:53:15.502622 <6>[ 18.598940] Segment Routing with IPv6
10821 11:53:15.506356 <6>[ 18.602958] In-situ OAM (IOAM) with IPv6
10822 11:53:15.633638 <30>[ 18.709487] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10823 11:53:15.636232 <30>[ 18.733895] systemd[1]: Detected architecture arm64.
10824 11:53:15.658691
10825 11:53:15.661876 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10826 11:53:15.661993
10827 11:53:15.676935 <30>[ 18.773335] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10828 11:53:16.576249 <30>[ 19.668937] systemd[1]: Queued start job for default target Graphical Interface.
10829 11:53:16.621064 <30>[ 19.717254] systemd[1]: Created slice system-getty.slice.
10830 11:53:16.627974 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10831 11:53:16.644024 <30>[ 19.740320] systemd[1]: Created slice system-modprobe.slice.
10832 11:53:16.651305 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10833 11:53:16.668495 <30>[ 19.764134] systemd[1]: Created slice system-serial\x2dgetty.slice.
10834 11:53:16.678017 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10835 11:53:16.692137 <30>[ 19.787961] systemd[1]: Created slice User and Session Slice.
10836 11:53:16.698506 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10837 11:53:16.719625 <30>[ 19.811756] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10838 11:53:16.728972 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10839 11:53:16.746752 <30>[ 19.839665] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10840 11:53:16.753399 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10841 11:53:16.777627 <30>[ 19.867027] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10842 11:53:16.784622 <30>[ 19.879188] systemd[1]: Reached target Local Encrypted Volumes.
10843 11:53:16.790895 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10844 11:53:16.807488 <30>[ 19.903487] systemd[1]: Reached target Paths.
10845 11:53:16.810793 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10846 11:53:16.826793 <30>[ 19.922922] systemd[1]: Reached target Remote File Systems.
10847 11:53:16.833459 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10848 11:53:16.850866 <30>[ 19.947291] systemd[1]: Reached target Slices.
10849 11:53:16.857635 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10850 11:53:16.870740 <30>[ 19.966917] systemd[1]: Reached target Swap.
10851 11:53:16.873948 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10852 11:53:16.894178 <30>[ 19.987460] systemd[1]: Listening on initctl Compatibility Named Pipe.
10853 11:53:16.900716 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10854 11:53:16.907483 <30>[ 20.003722] systemd[1]: Listening on Journal Audit Socket.
10855 11:53:16.914587 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10856 11:53:16.932158 <30>[ 20.028346] systemd[1]: Listening on Journal Socket (/dev/log).
10857 11:53:16.938613 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10858 11:53:16.954879 <30>[ 20.051536] systemd[1]: Listening on Journal Socket.
10859 11:53:16.962043 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10860 11:53:16.979297 <30>[ 20.072453] systemd[1]: Listening on Network Service Netlink Socket.
10861 11:53:16.985800 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10862 11:53:17.001535 <30>[ 20.097958] systemd[1]: Listening on udev Control Socket.
10863 11:53:17.008141 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10864 11:53:17.022800 <30>[ 20.119392] systemd[1]: Listening on udev Kernel Socket.
10865 11:53:17.029493 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10866 11:53:17.074973 <30>[ 20.170969] systemd[1]: Mounting Huge Pages File System...
10867 11:53:17.081327 Mounting [0;1;39mHuge Pages File System[0m...
10868 11:53:17.099239 <30>[ 20.195285] systemd[1]: Mounting POSIX Message Queue File System...
10869 11:53:17.105350 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10870 11:53:17.127463 <30>[ 20.223858] systemd[1]: Mounting Kernel Debug File System...
10871 11:53:17.133981 Mounting [0;1;39mKernel Debug File System[0m...
10872 11:53:17.149980 <30>[ 20.243419] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10873 11:53:17.171604 <30>[ 20.264738] systemd[1]: Starting Create list of static device nodes for the current kernel...
10874 11:53:17.181492 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10875 11:53:17.198836 <30>[ 20.295496] systemd[1]: Starting Load Kernel Module configfs...
10876 11:53:17.205481 Starting [0;1;39mLoad Kernel Module configfs[0m...
10877 11:53:17.222042 <30>[ 20.318363] systemd[1]: Starting Load Kernel Module drm...
10878 11:53:17.228781 Starting [0;1;39mLoad Kernel Module drm[0m...
10879 11:53:17.247474 <30>[ 20.343986] systemd[1]: Starting Load Kernel Module fuse...
10880 11:53:17.254066 Starting [0;1;39mLoad Kernel Module fuse[0m...
10881 11:53:17.275618 <30>[ 20.368867] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10882 11:53:17.291214 <30>[ 20.387817] systemd[1]: Starting Journal Service...
10883 11:53:17.294729 Starting [0;1;39mJournal Service[0m...
10884 11:53:17.304213 <6>[ 20.400729] fuse: init (API version 7.37)
10885 11:53:17.318278 <30>[ 20.414658] systemd[1]: Starting Load Kernel Modules...
10886 11:53:17.324644 Starting [0;1;39mLoad Kernel Modules[0m...
10887 11:53:17.344343 <30>[ 20.437565] systemd[1]: Starting Remount Root and Kernel File Systems...
10888 11:53:17.351105 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10889 11:53:17.368373 <30>[ 20.464799] systemd[1]: Starting Coldplug All udev Devices...
10890 11:53:17.374962 Starting [0;1;39mColdplug All udev Devices[0m...
10891 11:53:17.397514 <30>[ 20.493675] systemd[1]: Mounted Huge Pages File System.
10892 11:53:17.403834 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10893 11:53:17.419052 <30>[ 20.515890] systemd[1]: Mounted POSIX Message Queue File System.
10894 11:53:17.425953 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10895 11:53:17.442829 <30>[ 20.539512] systemd[1]: Mounted Kernel Debug File System.
10896 11:53:17.449608 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10897 11:53:17.471380 <30>[ 20.564644] systemd[1]: Finished Create list of static device nodes for the current kernel.
10898 11:53:17.481260 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10899 11:53:17.495485 <30>[ 20.592063] systemd[1]: modprobe@configfs.service: Succeeded.
10900 11:53:17.502713 <30>[ 20.599157] systemd[1]: Finished Load Kernel Module configfs.
10901 11:53:17.509028 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10902 11:53:17.527509 <30>[ 20.623794] systemd[1]: modprobe@drm.service: Succeeded.
10903 11:53:17.534040 <30>[ 20.630115] systemd[1]: Finished Load Kernel Module drm.
10904 11:53:17.540502 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10905 11:53:17.556046 <30>[ 20.652042] systemd[1]: modprobe@fuse.service: Succeeded.
10906 11:53:17.566348 <3>[ 20.657825] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 11:53:17.569507 <30>[ 20.658540] systemd[1]: Finished Load Kernel Module fuse.
10908 11:53:17.576894 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10909 11:53:17.595961 <30>[ 20.692373] systemd[1]: Finished Load Kernel Modules.
10910 11:53:17.606174 <3>[ 20.692750] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:53:17.612508 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10912 11:53:17.631313 <30>[ 20.724319] systemd[1]: Finished Remount Root and Kernel File Systems.
10913 11:53:17.637705 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10914 11:53:17.657747 <3>[ 20.750584] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 11:53:17.687554 <3>[ 20.780136] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:53:17.704497 <30>[ 20.800443] systemd[1]: Mounting FUSE Control File System...
10917 11:53:17.717710 Mounting [0;1;39mFUSE Control File Sys<3>[ 20.809652] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:53:17.720901 tem[0m...
10919 11:53:17.737435 <30>[ 20.833487] systemd[1]: Mounting Kernel Configuration File System...
10920 11:53:17.747484 <3>[ 20.839813] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:53:17.753747 Mounting [0;1;39mKernel Configuration File System[0m...
10922 11:53:17.776083 <3>[ 20.869088] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 11:53:17.787907 <30>[ 20.880957] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10924 11:53:17.797742 <30>[ 20.889984] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10925 11:53:17.807733 <3>[ 20.899293] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 11:53:17.839116 <30>[ 20.935379] systemd[1]: Starting Load/Save Random Seed...
10927 11:53:17.846740 Starting [0;1;39mLoad/Save Random Seed[0m...
10928 11:53:17.853122 <3>[ 20.946570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:53:17.863187 <3>[ 20.956140] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10930 11:53:17.866481 <30>[ 20.958042] systemd[1]: Starting Apply Kernel Variables...
10931 11:53:17.873508 Starting [0;1;39mApply Kernel Variables[0m...
10932 11:53:17.892120 <30>[ 20.988923] systemd[1]: Starting Create System Users...
10933 11:53:17.898918 Starting [0;1;39mCreate System Users[0m...
10934 11:53:17.916943 <30>[ 21.012894] systemd[1]: Mounted FUSE Control File System.
10935 11:53:17.937371 [[0;32m OK [0m] Mounted [0;<4>[ 21.020493] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10936 11:53:17.944287 1;39mFUSE Contro<3>[ 21.037515] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10937 11:53:17.947302 l File System[0m.
10938 11:53:17.962682 <30>[ 21.059438] systemd[1]: Mounted Kernel Configuration File System.
10939 11:53:17.969597 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10940 11:53:17.986742 <30>[ 21.083297] systemd[1]: Started Journal Service.
10941 11:53:17.993521 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10942 11:53:18.013863 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10943 11:53:18.026534 See 'systemctl status systemd-udev-trigger.service' for details.
10944 11:53:18.044624 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10945 11:53:18.064530 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10946 11:53:18.083757 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10947 11:53:18.139587 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10948 11:53:18.157010 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10949 11:53:18.202612 <46>[ 21.295913] systemd-journald[305]: Received client request to flush runtime journal.
10950 11:53:18.239219 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10951 11:53:18.251333 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10952 11:53:18.266391 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10953 11:53:18.322609 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10954 11:53:19.624428 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10955 11:53:19.666536 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10956 11:53:19.699598 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10957 11:53:19.726271 Starting [0;1;39mNetwork Service[0m...
10958 11:53:20.053691 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10959 11:53:20.077253 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10960 11:53:20.122666 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10961 11:53:20.414353 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10962 11:53:20.433242 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10963 11:53:20.479089 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10964 11:53:20.495604 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10965 11:53:20.516161 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10966 11:53:20.530973 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10967 11:53:20.575428 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10968 11:53:20.631159 Starting [0;1;39mNetwork Name Resolution[0m...
10969 11:53:20.659652 Starting [0;1;39mNetwork Time Synchronization[0m...
10970 11:53:20.679869 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10971 11:53:20.734632 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10972 11:53:20.872570 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10973 11:53:20.891212 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10974 11:53:20.909343 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10975 11:53:20.922478 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10976 11:53:20.937955 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10977 11:53:21.066713 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10978 11:53:21.102916 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10979 11:53:21.145366 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10980 11:53:21.605819 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10981 11:53:21.618354 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10982 11:53:21.872569 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10983 11:53:21.886103 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10984 11:53:21.902320 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10985 11:53:21.975177 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10986 11:53:22.290483 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10987 11:53:22.375089 Starting [0;1;39mUser Login Management[0m...
10988 11:53:22.393050 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10989 11:53:22.414381 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10990 11:53:22.433356 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10991 11:53:22.471079 Starting [0;1;39mPermit User Sessions[0m...
10992 11:53:22.560556 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10993 11:53:22.591226 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10994 11:53:22.610971 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10995 11:53:22.627013 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10996 11:53:22.649028 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10997 11:53:22.703122 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10998 11:53:22.720215 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10999 11:53:22.738644 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11000 11:53:22.784022 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11001 11:53:22.838133 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11002 11:53:22.950747
11003 11:53:22.951437
11004 11:53:22.953749 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11005 11:53:22.954106
11006 11:53:22.956831 debian-bullseye-arm64 login: root (automatic login)
11007 11:53:22.957085
11008 11:53:22.957287
11009 11:53:23.277307 Linux debian-bullseye-arm64 6.1.62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
11010 11:53:23.277457
11011 11:53:23.284297 The programs included with the Debian GNU/Linux system are free software;
11012 11:53:23.290817 the exact distribution terms for each program are described in the
11013 11:53:23.293978 individual files in /usr/share/doc/*/copyright.
11014 11:53:23.294056
11015 11:53:23.300447 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11016 11:53:23.303821 permitted by applicable law.
11017 11:53:23.382792 Matched prompt #10: / #
11019 11:53:23.383067 Setting prompt string to ['/ #']
11020 11:53:23.383162 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11022 11:53:23.383358 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11023 11:53:23.383445 start: 2.2.6 expect-shell-connection (timeout 00:03:14) [common]
11024 11:53:23.383514 Setting prompt string to ['/ #']
11025 11:53:23.383574 Forcing a shell prompt, looking for ['/ #']
11027 11:53:23.433765 / #
11028 11:53:23.433909 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11029 11:53:23.434006 Waiting using forced prompt support (timeout 00:02:30)
11030 11:53:23.438476
11031 11:53:23.438747 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11032 11:53:23.438841 start: 2.2.7 export-device-env (timeout 00:03:14) [common]
11034 11:53:23.539200 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7'
11035 11:53:23.544035 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12066517/extract-nfsrootfs-5nshq7d7'
11037 11:53:23.644576 / # export NFS_SERVER_IP='192.168.201.1'
11038 11:53:23.649893 export NFS_SERVER_IP='192.168.201.1'
11039 11:53:23.650186 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11040 11:53:23.650290 end: 2.2 depthcharge-retry (duration 00:01:46) [common]
11041 11:53:23.650377 end: 2 depthcharge-action (duration 00:01:46) [common]
11042 11:53:23.650465 start: 3 lava-test-retry (timeout 00:30:00) [common]
11043 11:53:23.650557 start: 3.1 lava-test-shell (timeout 00:30:00) [common]
11044 11:53:23.650640 Using namespace: common
11046 11:53:23.750942 / # #
11047 11:53:23.751114 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:30:00)
11048 11:53:23.756673 #
11049 11:53:23.756934 Using /lava-12066517
11051 11:53:23.857241 / # export SHELL=/bin/sh
11052 11:53:23.862025 export SHELL=/bin/sh
11054 11:53:23.962514 / # . /lava-12066517/environment
11055 11:53:23.967495 . /lava-12066517/environment
11057 11:53:24.073352 / # /lava-12066517/bin/lava-test-runner /lava-12066517/0
11058 11:53:24.073499 Test shell timeout: 10s (minimum of the action and connection timeout)
11059 11:53:24.078547 /lava-12066517/bin/lava-test-runner /lava-12066517/0
11060 11:53:24.318661 + export TESTRUN_ID=0_lc-compliance
11061 11:53:24.324886 + cd /lava-12066517/0/tests/0_lc-compliance
11062 11:53:24.324985 + cat uuid
11063 11:53:24.332361 + UUID=12066517_1.6.2.3.1
11064 11:53:24.332440 + set +x
11065 11:53:24.338324 <LAVA_SIGNAL_STARTRUN 0_lc-compliance 12066517_1.6.2.3.1>
11066 11:53:24.338608 Received signal: <STARTRUN> 0_lc-compliance 12066517_1.6.2.3.1
11067 11:53:24.338713 Starting test lava.0_lc-compliance (12066517_1.6.2.3.1)
11068 11:53:24.338827 Skipping test definition patterns.
11069 11:53:24.341408 + /usr/bin/lc-compliance-parser.sh
11070 11:53:25.550914 [0:00:28.526497155] [411] [1;32m INFO [1;37mCamera [1;34mcamera_manager.cpp:297 [0mlibcamera v0.0.0+1-1f607da9
11071 11:53:25.554016 Using camera /base/soc/usb@11200000-1.4.1:1.0-04f2:b741
11072 11:53:25.568094 [0:00:28.544602308] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11073 11:53:25.627891 [0:00:28.604216616] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11074 11:53:25.641454 [==========] Running 120 tests from 1 test suite.
11075 11:53:25.684471 [0:00:28.660124924] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11076 11:53:25.736468 [0:00:28.712484693] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11077 11:53:25.739760 [----------] Global test environment set-up.
11078 11:53:25.826282 [----------] 120 tests from CaptureTests/SingleStream
11079 11:53:25.916653 [ RUN ] CaptureTests/SingleStream.Capture/Raw_1
11080 11:53:25.990633 <LAVA_SIGNAL_TESTSET START CaptureTests/SingleStream>
11081 11:53:25.990959 Received signal: <TESTSET> START CaptureTests/SingleStream
11082 11:53:25.991048 Starting test_set CaptureTests/SingleStream
11083 11:53:25.993705 Camera needs 4 requests, can't test only 1
11084 11:53:26.076156 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11085 11:53:26.154324
11086 11:53:26.196448 [0:00:29.172669924] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11087 11:53:26.243704 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_1 (60 ms)
11088 11:53:26.345895 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_1 RESULT=skip>
11089 11:53:26.346219 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_1 RESULT=skip
11091 11:53:26.362550 [ RUN ] CaptureTests/SingleStream.Capture/Raw_2
11092 11:53:26.417873 Camera needs 4 requests, can't test only 2
11093 11:53:26.497620 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11094 11:53:26.582344
11095 11:53:26.675316 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_2 (54 ms)
11096 11:53:26.758973 [0:00:29.735233462] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11097 11:53:26.778975 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_2 RESULT=skip>
11098 11:53:26.779264 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_2 RESULT=skip
11100 11:53:26.796436 [ RUN ] CaptureTests/SingleStream.Capture/Raw_3
11101 11:53:26.855443 Camera needs 4 requests, can't test only 3
11102 11:53:26.942863 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11103 11:53:27.026336
11104 11:53:27.114489 [ SKIPPED ] CaptureTests/SingleStream.Capture/Raw_3 (55 ms)
11105 11:53:27.217097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_3 RESULT=skip>
11106 11:53:27.217434 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_3 RESULT=skip
11108 11:53:27.235943 [ RUN ] CaptureTests/SingleStream.Capture/Raw_5
11109 11:53:27.298031 [ OK ] CaptureTests/SingleStream.Capture/Raw_5 (460 ms)
11110 11:53:27.403564 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_5 RESULT=pass>
11111 11:53:27.403892 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_5 RESULT=pass
11113 11:53:27.421079 [ RUN ] CaptureTests/SingleStream.Capture/Raw_8
11114 11:53:27.452625 [0:00:30.429092770] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11115 11:53:27.479416 [ OK ] CaptureTests/SingleStream.Capture/Raw_8 (561 ms)
11116 11:53:27.579471 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_8 RESULT=pass>
11117 11:53:27.579812 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_8 RESULT=pass
11119 11:53:27.599184 [ RUN ] CaptureTests/SingleStream.Capture/Raw_13
11120 11:53:27.661908 [ OK ] CaptureTests/SingleStream.Capture/Raw_13 (695 ms)
11121 11:53:27.758912 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_13 RESULT=pass>
11122 11:53:27.759230 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_13 RESULT=pass
11124 11:53:27.776748 [ RUN ] CaptureTests/SingleStream.Capture/Raw_21
11125 11:53:28.340917 [ OK ] CaptureTests/SingleStream.Capture/Raw_21 (896 ms)
11126 11:53:28.350348 [0:00:31.325981693] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11127 11:53:28.444730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_21 RESULT=pass>
11128 11:53:28.445049 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_21 RESULT=pass
11130 11:53:28.462851 [ RUN ] CaptureTests/SingleStream.Capture/Raw_34
11131 11:53:29.673525 [ OK ] CaptureTests/SingleStream.Capture/Raw_34 (1333 ms)
11132 11:53:29.683409 [0:00:32.658948463] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11133 11:53:29.778973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_34 RESULT=pass>
11134 11:53:29.779286 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_34 RESULT=pass
11136 11:53:29.797313 [ RUN ] CaptureTests/SingleStream.Capture/Raw_55
11137 11:53:31.802433 [ OK ] CaptureTests/SingleStream.Capture/Raw_55 (2128 ms)
11138 11:53:31.811895 [0:00:34.787269770] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11139 11:53:31.907001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_55 RESULT=pass>
11140 11:53:31.907353 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_55 RESULT=pass
11142 11:53:31.926188 [ RUN ] CaptureTests/SingleStream.Capture/Raw_89
11143 11:53:35.030113 [ OK ] CaptureTests/SingleStream.Capture/Raw_89 (3229 ms)
11144 11:53:35.039890 [0:00:38.016137617] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11145 11:53:35.092899 [0:00:38.070258848] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11146 11:53:35.137979 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Raw_89 RESULT=pass>
11147 11:53:35.138331 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Raw_89 RESULT=pass
11149 11:53:35.148152 [0:00:38.124665386] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11150 11:53:35.159572 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_1
11151 11:53:35.201723 [0:00:38.178843848] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11152 11:53:35.222909 Camera needs 4 requests, can't test only 1
11153 11:53:35.303713 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11154 11:53:35.390915
11155 11:53:35.482664 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_1 (55 ms)
11156 11:53:35.583947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip>
11157 11:53:35.584302 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_1 RESULT=skip
11159 11:53:35.601501 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_2
11160 11:53:35.660792 [0:00:38.638228848] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11161 11:53:35.664192 Camera needs 4 requests, can't test only 2
11162 11:53:35.752353 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11163 11:53:35.840931
11164 11:53:35.940841 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_2 (53 ms)
11165 11:53:36.049056 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip>
11166 11:53:36.049384 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_2 RESULT=skip
11168 11:53:36.071428 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_3
11169 11:53:36.125803 [0:00:39.102712771] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11170 11:53:36.142896 Camera needs 4 requests, can't test only 3
11171 11:53:36.236714 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11172 11:53:36.321303
11173 11:53:36.419214 [ SKIPPED ] CaptureTests/SingleStream.Capture/StillCapture_3 (56 ms)
11174 11:53:36.525779 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip>
11175 11:53:36.526103 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_3 RESULT=skip
11177 11:53:36.544210 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_5
11178 11:53:36.608613 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_5 (459 ms)
11179 11:53:36.714954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass>
11180 11:53:36.715331 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_5 RESULT=pass
11182 11:53:36.734672 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_8
11183 11:53:36.796561 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_8 (463 ms)
11184 11:53:36.822830 [0:00:39.800376155] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11185 11:53:36.901951 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass>
11186 11:53:36.902271 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_8 RESULT=pass
11188 11:53:36.919966 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_13
11189 11:53:36.977600 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_13 (698 ms)
11190 11:53:37.067540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass>
11191 11:53:37.067862 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_13 RESULT=pass
11193 11:53:37.087408 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_21
11194 11:53:37.747120 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_21 (934 ms)
11195 11:53:37.759960 [0:00:40.733621463] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11196 11:53:37.857936 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass>
11197 11:53:37.858258 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_21 RESULT=pass
11199 11:53:37.877560 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_34
11200 11:53:39.142590 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_34 (1395 ms)
11201 11:53:39.155510 [0:00:42.129454694] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11202 11:53:39.246218 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass>
11203 11:53:39.246543 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_34 RESULT=pass
11205 11:53:39.267255 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_55
11206 11:53:41.270691 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_55 (2129 ms)
11207 11:53:41.283617 [0:00:44.257213771] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11208 11:53:41.368705 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass>
11209 11:53:41.369026 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_55 RESULT=pass
11211 11:53:41.385641 [ RUN ] CaptureTests/SingleStream.Capture/StillCapture_89
11212 11:53:43.056425 <6>[ 46.158951] vpu: disabling
11213 11:53:43.059783 <6>[ 46.162149] vproc2: disabling
11214 11:53:43.062937 <6>[ 46.165614] vproc1: disabling
11215 11:53:43.066369 <6>[ 46.169246] vaud18: disabling
11216 11:53:43.073483 <6>[ 46.173013] vsram_others: disabling
11217 11:53:43.076701 <6>[ 46.177135] va09: disabling
11218 11:53:43.080441 <6>[ 46.180470] vsram_md: disabling
11219 11:53:43.083380 <6>[ 46.184173] Vgpu: disabling
11220 11:53:44.498051 [ OK ] CaptureTests/SingleStream.Capture/StillCapture_89 (3227 ms)
11221 11:53:44.510820 [0:00:47.485655540] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11222 11:53:44.561071 [0:00:47.539438156] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11223 11:53:44.600955 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass>
11224 11:53:44.601247 Received signal: <TESTCASE> TEST_CASE_ID=Capture/StillCapture_89 RESULT=pass
11226 11:53:44.616147 [0:00:47.594277463] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11227 11:53:44.622593 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_1
11228 11:53:44.669477 [0:00:47.647944925] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11229 11:53:44.677311 Camera needs 4 requests, can't test only 1
11230 11:53:44.757990 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11231 11:53:44.838304
11232 11:53:44.930640 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_1 (55 ms)
11233 11:53:45.031095 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip>
11234 11:53:45.031410 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_1 RESULT=skip
11236 11:53:45.049972 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_2
11237 11:53:45.067489 [0:00:48.045919617] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11238 11:53:45.109129 Camera needs 4 requests, can't test only 2
11239 11:53:45.192288 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11240 11:53:45.277225
11241 11:53:45.366815 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_2 (55 ms)
11242 11:53:45.466332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip>
11243 11:53:45.466651 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_2 RESULT=skip
11245 11:53:45.484757 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_3
11246 11:53:45.531518 [0:00:48.510018617] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11247 11:53:45.554626 Camera needs 4 requests, can't test only 3
11248 11:53:45.640806 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11249 11:53:45.727721
11250 11:53:45.820894 [ SKIPPED ] CaptureTests/SingleStream.Capture/VideoRecording_3 (54 ms)
11251 11:53:45.935737 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip>
11252 11:53:45.936064 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_3 RESULT=skip
11254 11:53:45.952385 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_5
11255 11:53:46.006071 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_5 (398 ms)
11256 11:53:46.100925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass>
11257 11:53:46.101256 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_5 RESULT=pass
11259 11:53:46.118338 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_8
11260 11:53:46.175386 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_8 (463 ms)
11261 11:53:46.225076 [0:00:49.203832156] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11262 11:53:46.270523 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass>
11263 11:53:46.270831 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_8 RESULT=pass
11265 11:53:46.288139 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_13
11266 11:53:46.346114 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_13 (695 ms)
11267 11:53:46.454357 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass>
11268 11:53:46.454679 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_13 RESULT=pass
11270 11:53:46.471989 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_21
11271 11:53:47.211350 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_21 (994 ms)
11272 11:53:47.224456 [0:00:50.199974541] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11273 11:53:47.322983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass>
11274 11:53:47.323343 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_21 RESULT=pass
11276 11:53:47.343075 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_34
11277 11:53:48.546096 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_34 (1335 ms)
11278 11:53:48.559192 [0:00:51.534753771] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11279 11:53:48.660591 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass>
11280 11:53:48.660914 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_34 RESULT=pass
11282 11:53:48.680845 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_55
11283 11:53:50.675909 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_55 (2130 ms)
11284 11:53:50.689219 [0:00:53.664677925] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11285 11:53:50.786492 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass>
11286 11:53:50.786855 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_55 RESULT=pass
11288 11:53:50.803079 [ RUN ] CaptureTests/SingleStream.Capture/VideoRecording_89
11289 11:53:53.905635 [ OK ] CaptureTests/SingleStream.Capture/VideoRecording_89 (3230 ms)
11290 11:53:53.918591 [0:00:56.894971464] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11291 11:53:53.971459 [0:00:56.950434618] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11292 11:53:54.018204 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass>
11293 11:53:54.018523 Received signal: <TESTCASE> TEST_CASE_ID=Capture/VideoRecording_89 RESULT=pass
11295 11:53:54.031668 [0:00:57.007276409] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11296 11:53:54.037911 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_1
11297 11:53:54.080952 [0:00:57.060075993] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11298 11:53:54.096985 Camera needs 4 requests, can't test only 1
11299 11:53:54.186005 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11300 11:53:54.273005
11301 11:53:54.370862 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_1 (56 ms)
11302 11:53:54.446653 [0:00:57.426322635] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11303 11:53:54.468158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip>
11304 11:53:54.468534 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_1 RESULT=skip
11306 11:53:54.486679 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_2
11307 11:53:54.542762 Camera needs 4 requests, can't test only 2
11308 11:53:54.627566 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11309 11:53:54.714272
11310 11:53:54.798761 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_2 (56 ms)
11311 11:53:54.889540 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip>
11312 11:53:54.889868 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_2 RESULT=skip
11314 11:53:54.906965 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_3
11315 11:53:54.962877 Camera needs 4 requests, can't test only 3
11316 11:53:54.977264 [0:00:57.956754143] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11317 11:53:55.058372 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11318 11:53:55.140616
11319 11:53:55.234291 [ SKIPPED ] CaptureTests/SingleStream.Capture/Viewfinder_3 (54 ms)
11320 11:53:55.338052 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip>
11321 11:53:55.338423 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_3 RESULT=skip
11323 11:53:55.356343 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_5
11324 11:53:55.415525 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_5 (366 ms)
11325 11:53:55.517633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass>
11326 11:53:55.517956 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_5 RESULT=pass
11328 11:53:55.537404 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_8
11329 11:53:55.598776 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_8 (530 ms)
11330 11:53:55.674678 [0:00:58.654248634] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11331 11:53:55.713036 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass>
11332 11:53:55.713356 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_8 RESULT=pass
11334 11:53:55.733240 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_13
11335 11:53:55.794376 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_13 (697 ms)
11336 11:53:55.895395 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass>
11337 11:53:55.895714 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_13 RESULT=pass
11339 11:53:55.914029 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_21
11340 11:53:56.599225 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_21 (934 ms)
11341 11:53:56.612067 [0:00:59.588456403] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11342 11:53:56.711051 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass>
11343 11:53:56.711391 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_21 RESULT=pass
11345 11:53:56.728783 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_34
11346 11:53:57.996550 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_34 (1397 ms)
11347 11:53:58.010029 [0:01:00.986114878] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11348 11:53:58.114084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass>
11349 11:53:58.114407 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_34 RESULT=pass
11351 11:53:58.133591 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_55
11352 11:54:00.126838 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_55 (2131 ms)
11353 11:54:00.140264 [0:01:03.116611112] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11354 11:54:00.239671 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass>
11355 11:54:00.239995 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_55 RESULT=pass
11357 11:54:00.258544 [ RUN ] CaptureTests/SingleStream.Capture/Viewfinder_89
11358 11:54:03.357132 [ OK ] CaptureTests/SingleStream.Capture/Viewfinder_89 (3230 ms)
11359 11:54:03.369969 [0:01:06.346557685] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11360 11:54:03.423605 [0:01:06.403242125] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11361 11:54:03.467984 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass>
11362 11:54:03.468261 Received signal: <TESTCASE> TEST_CASE_ID=Capture/Viewfinder_89 RESULT=pass
11364 11:54:03.480816 [0:01:06.459964487] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11365 11:54:03.489385 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_1
11366 11:54:03.532962 [0:01:06.513043999] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11367 11:54:03.551268 Camera needs 4 requests, can't test only 1
11368 11:54:03.644165 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11369 11:54:03.728745
11370 11:54:03.821511 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_1 (56 ms)
11371 11:54:03.929815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip>
11372 11:54:03.930137 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_1 RESULT=skip
11374 11:54:03.949909 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_2
11375 11:54:04.006917 Camera needs 4 requests, can't test only 2
11376 11:54:04.090336 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11377 11:54:04.182730
11378 11:54:04.274981 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_2 (57 ms)
11379 11:54:04.377615 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip>
11380 11:54:04.377977 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_2 RESULT=skip
11382 11:54:04.396868 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_3
11383 11:54:04.460274 Camera needs 4 requests, can't test only 3
11384 11:54:04.549319 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11385 11:54:04.642318
11386 11:54:04.685744 [0:01:07.665572447] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11387 11:54:04.746733 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Raw_3 (54 ms)
11388 11:54:04.853135 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip>
11389 11:54:04.853451 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_3 RESULT=skip
11391 11:54:04.872342 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_5
11392 11:54:04.932014 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_5 (1151 ms)
11393 11:54:05.031567 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass>
11394 11:54:05.031894 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_5 RESULT=pass
11396 11:54:05.051761 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_8
11397 11:54:06.096925 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_8 (1421 ms)
11398 11:54:06.110457 [0:01:09.087280601] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11399 11:54:06.207456 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass>
11400 11:54:06.207772 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_8 RESULT=pass
11402 11:54:06.224906 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_13
11403 11:54:08.149364 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_13 (2052 ms)
11404 11:54:08.162459 [0:01:11.139360456] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11405 11:54:08.273434 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass>
11406 11:54:08.273747 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_13 RESULT=pass
11408 11:54:08.291026 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_21
11409 11:54:10.871132 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_21 (2722 ms)
11410 11:54:10.884513 [0:01:13.862026969] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11411 11:54:10.979300 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass>
11412 11:54:10.979614 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_21 RESULT=pass
11414 11:54:10.995700 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_34
11415 11:54:14.989259 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_34 (4118 ms)
11416 11:54:15.002656 [0:01:17.980428302] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11417 11:54:15.099530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass>
11418 11:54:15.099847 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_34 RESULT=pass
11420 11:54:15.117011 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_55
11421 11:54:21.337127 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_55 (6348 ms)
11422 11:54:21.349850 [0:01:24.327944746] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11423 11:54:21.466433 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass>
11424 11:54:21.466738 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_55 RESULT=pass
11426 11:54:21.488148 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Raw_89
11427 11:54:30.985655 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Raw_89 (9650 ms)
11428 11:54:30.998939 [0:01:33.978175474] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11429 11:54:31.050957 [0:01:34.033741784] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11430 11:54:31.109362 [0:01:34.091816315] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11431 11:54:31.112802 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass
11433 11:54:31.115783 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Raw_89 RESULT=pass>
11434 11:54:31.125530 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1
11435 11:54:31.165642 [0:01:34.148260242] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11436 11:54:31.187508 Camera needs 4 requests, can't test only 1
11437 11:54:31.278083 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11438 11:54:31.365839
11439 11:54:31.460193 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_1 (57 ms)
11440 11:54:31.565596 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip>
11441 11:54:31.565914 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_1 RESULT=skip
11443 11:54:31.581811 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2
11444 11:54:31.640730 Camera needs 4 requests, can't test only 2
11445 11:54:31.735247 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11446 11:54:31.830379
11447 11:54:31.929036 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_2 (58 ms)
11448 11:54:32.031073 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip>
11449 11:54:32.031392 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_2 RESULT=skip
11451 11:54:32.045568 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3
11452 11:54:32.098810 Camera needs 4 requests, can't test only 3
11453 11:54:32.179916 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11454 11:54:32.264618
11455 11:54:32.359014 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_3 (58 ms)
11456 11:54:32.387049 [0:01:35.369883240] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11457 11:54:32.465475 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip>
11458 11:54:32.465758 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_3 RESULT=skip
11460 11:54:32.481856 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5
11461 11:54:32.546618 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_5 (1220 ms)
11462 11:54:32.658157 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass>
11463 11:54:32.658450 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_5 RESULT=pass
11465 11:54:32.675223 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8
11466 11:54:33.833057 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_8 (1452 ms)
11467 11:54:33.842880 [0:01:36.822334078] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11468 11:54:33.944118 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass>
11469 11:54:33.944443 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_8 RESULT=pass
11471 11:54:33.958909 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13
11472 11:54:35.883976 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_13 (2050 ms)
11473 11:54:35.893762 [0:01:38.873452308] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11474 11:54:36.013559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass>
11475 11:54:36.014388 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_13 RESULT=pass
11477 11:54:36.034072 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21
11478 11:54:38.667883 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_21 (2784 ms)
11479 11:54:38.677945 [0:01:41.658359751] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11480 11:54:38.776736 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass>
11481 11:54:38.777043 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_21 RESULT=pass
11483 11:54:38.792729 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34
11484 11:54:42.786066 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_34 (4119 ms)
11485 11:54:42.796145 [0:01:45.776735075] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11486 11:54:42.894578 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass>
11487 11:54:42.894874 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_34 RESULT=pass
11489 11:54:42.909185 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55
11490 11:54:49.100809 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_55 (6315 ms)
11491 11:54:49.110500 [0:01:52.091623642] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11492 11:54:49.227355 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass>
11493 11:54:49.227663 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_55 RESULT=pass
11495 11:54:49.244167 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89
11496 11:54:58.719384 [ OK ] CaptureTests/SingleStream.CaptureStartStop/StillCapture_89 (9619 ms)
11497 11:54:58.729190 [0:02:01.711464556] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11498 11:54:58.782133 [0:02:01.767697475] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11499 11:54:58.837374 [0:02:01.822839982] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11500 11:54:58.844100 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass>
11501 11:54:58.844367 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/StillCapture_89 RESULT=pass
11503 11:54:58.855619 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1
11504 11:54:58.890508 [0:02:01.875872801] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11505 11:54:58.911610 Camera needs 4 requests, can't test only 1
11506 11:54:58.997718 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11507 11:54:59.079604
11508 11:54:59.177665 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_1 (56 ms)
11509 11:54:59.280871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip>
11510 11:54:59.281178 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_1 RESULT=skip
11512 11:54:59.294364 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2
11513 11:54:59.367405 Camera needs 4 requests, can't test only 2
11514 11:54:59.460107 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11515 11:54:59.545945
11516 11:54:59.648138 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_2 (55 ms)
11517 11:54:59.752023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip>
11518 11:54:59.752337 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_2 RESULT=skip
11520 11:54:59.767618 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3
11521 11:54:59.825760 Camera needs 4 requests, can't test only 3
11522 11:54:59.902375 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11523 11:54:59.982534
11524 11:55:00.069066 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_3 (53 ms)
11525 11:55:00.078704 [0:02:03.061894311] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11526 11:55:00.169034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip>
11527 11:55:00.169360 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_3 RESULT=skip
11529 11:55:00.182590 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5
11530 11:55:00.241836 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_5 (1186 ms)
11531 11:55:00.352488 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass>
11532 11:55:00.352794 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_5 RESULT=pass
11534 11:55:00.368240 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8
11535 11:55:01.456329 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_8 (1384 ms)
11536 11:55:01.466472 [0:02:04.447992968] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11537 11:55:01.561858 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass>
11538 11:55:01.562151 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_8 RESULT=pass
11540 11:55:01.579625 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13
11541 11:55:03.507392 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_13 (2050 ms)
11542 11:55:03.516582 [0:02:06.497941004] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11543 11:55:03.617511 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass>
11544 11:55:03.617820 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_13 RESULT=pass
11546 11:55:03.632104 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21
11547 11:55:06.228903 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_21 (2722 ms)
11548 11:55:06.238619 [0:02:09.219525428] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11549 11:55:06.338821 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass>
11550 11:55:06.339124 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_21 RESULT=pass
11552 11:55:06.355624 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34
11553 11:55:10.346430 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_34 (4117 ms)
11554 11:55:10.356268 [0:02:13.336904556] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11555 11:55:10.457460 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass>
11556 11:55:10.457787 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_34 RESULT=pass
11558 11:55:10.470696 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55
11559 11:55:16.660369 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_55 (6312 ms)
11560 11:55:16.669412 [0:02:19.650176355] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11561 11:55:16.782190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass>
11562 11:55:16.782520 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_55 RESULT=pass
11564 11:55:16.799400 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89
11565 11:55:26.372597 [ OK ] CaptureTests/SingleStream.CaptureStartStop/VideoRecording_89 (9713 ms)
11566 11:55:26.381971 [0:02:29.362294624] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11567 11:55:26.434760 [0:02:29.418494582] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11568 11:55:26.492730 [0:02:29.476103213] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11569 11:55:26.499283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass>
11570 11:55:26.499550 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/VideoRecording_89 RESULT=pass
11572 11:55:26.509239 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1
11573 11:55:26.548360 [0:02:29.532064431] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11574 11:55:26.576786 Camera needs 4 requests, can't test only 1
11575 11:55:26.674333 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11576 11:55:26.771712
11577 11:55:26.877859 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_1 (56 ms)
11578 11:55:26.990968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip>
11579 11:55:26.991292 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_1 RESULT=skip
11581 11:55:27.006979 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2
11582 11:55:27.066366 Camera needs 4 requests, can't test only 2
11583 11:55:27.162156 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11584 11:55:27.260228
11585 11:55:27.363088 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_2 (58 ms)
11586 11:55:27.479907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip>
11587 11:55:27.480259 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_2 RESULT=skip
11589 11:55:27.496497 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3
11590 11:55:27.562164 Camera needs 4 requests, can't test only 3
11591 11:55:27.637992 [0:02:30.621866543] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11592 11:55:27.662287 ../src/apps/lc-compliance/simple_capture.cpp:91: Skipped
11593 11:55:27.748043
11594 11:55:27.852751 [ SKIPPED ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_3 (57 ms)
11595 11:55:27.967227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip>
11596 11:55:27.967528 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_3 RESULT=skip
11598 11:55:27.982728 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5
11599 11:55:28.046804 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_5 (1089 ms)
11600 11:55:28.156837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass>
11601 11:55:28.157130 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_5 RESULT=pass
11603 11:55:28.173906 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8
11604 11:55:29.022012 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_8 (1388 ms)
11605 11:55:29.031459 [0:02:32.011219244] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11606 11:55:29.142343 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass>
11607 11:55:29.142645 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_8 RESULT=pass
11609 11:55:29.159501 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13
11610 11:55:31.199798 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_13 (2178 ms)
11611 11:55:31.209249 [0:02:34.189587614] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11612 11:55:31.312127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass>
11613 11:55:31.312429 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_13 RESULT=pass
11615 11:55:31.330291 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21
11616 11:55:33.887358 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_21 (2687 ms)
11617 11:55:33.897109 [0:02:36.877375041] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11618 11:55:34.025429 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass>
11619 11:55:34.026316 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_21 RESULT=pass
11621 11:55:34.046730 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34
11622 11:55:38.201994 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_34 (4315 ms)
11623 11:55:38.212048 [0:02:41.191572945] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11624 11:55:38.343070 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass>
11625 11:55:38.343910 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_34 RESULT=pass
11627 11:55:38.364701 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55
11628 11:55:44.577917 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_55 (6376 ms)
11629 11:55:44.587594 [0:02:47.567728479] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11630 11:55:44.712641 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass>
11631 11:55:44.713527 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_55 RESULT=pass
11633 11:55:44.733452 [ RUN ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89
11634 11:55:54.351870 [ OK ] CaptureTests/SingleStream.CaptureStartStop/Viewfinder_89 (9774 ms)
11635 11:55:54.361307 [0:02:57.341531181] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11636 11:55:54.488155 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass>
11637 11:55:54.489042 Received signal: <TESTCASE> TEST_CASE_ID=CaptureStartStop/Viewfinder_89 RESULT=pass
11639 11:55:54.505633 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_1
11640 11:55:54.677216 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_1 (329 ms)
11641 11:55:54.690528 [0:02:57.671344783] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11642 11:55:54.810228 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass>
11643 11:55:54.811237 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_1 RESULT=pass
11645 11:55:54.832450 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_2
11646 11:55:54.945536 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_2 (268 ms)
11647 11:55:54.958553 [0:02:57.939369768] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11648 11:55:55.073143 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass>
11649 11:55:55.074029 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_2 RESULT=pass
11651 11:55:55.092887 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_3
11652 11:55:55.246401 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_3 (301 ms)
11653 11:55:55.259488 [0:02:58.239953937] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11654 11:55:55.377024 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass>
11655 11:55:55.377938 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_3 RESULT=pass
11657 11:55:55.400052 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_5
11658 11:55:55.613896 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_5 (368 ms)
11659 11:55:55.623729 [0:02:58.607805580] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11660 11:55:55.739532 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass>
11661 11:55:55.740472 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_5 RESULT=pass
11663 11:55:55.762966 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_8
11664 11:55:56.082099 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_8 (468 ms)
11665 11:55:56.095435 [0:02:59.075722403] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11666 11:55:56.209788 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass>
11667 11:55:56.210636 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_8 RESULT=pass
11669 11:55:56.234653 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_13
11670 11:55:56.812658 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_13 (731 ms)
11671 11:55:56.825971 [0:02:59.806001363] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11672 11:55:56.939400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass>
11673 11:55:56.940356 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_13 RESULT=pass
11675 11:55:56.959686 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_21
11676 11:55:57.712452 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_21 (900 ms)
11677 11:55:57.725718 [0:03:00.706201496] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11678 11:55:57.841632 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass>
11679 11:55:57.841959 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_21 RESULT=pass
11681 11:55:57.860391 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_34
11682 11:55:59.047178 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_34 (1335 ms)
11683 11:55:59.060594 [0:03:02.041415946] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11684 11:55:59.176023 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass>
11685 11:55:59.176343 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_34 RESULT=pass
11687 11:55:59.192266 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_55
11688 11:56:01.179254 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_55 (2131 ms)
11689 11:56:01.192349 [0:03:04.173020078] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11690 11:56:01.318764 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass>
11691 11:56:01.319724 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_55 RESULT=pass
11693 11:56:01.342746 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Raw_89
11694 11:56:04.378973 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Raw_89 (3200 ms)
11695 11:56:04.391666 [0:03:07.372796808] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11696 11:56:04.519281 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass>
11697 11:56:04.520145 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Raw_89 RESULT=pass
11699 11:56:04.544183 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1
11700 11:56:04.712162 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_1 (330 ms)
11701 11:56:04.721870 [0:03:07.702769559] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11702 11:56:04.856556 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass>
11703 11:56:04.857367 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_1 RESULT=pass
11705 11:56:04.875301 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2
11706 11:56:04.979500 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_2 (268 ms)
11707 11:56:04.989465 [0:03:07.969918258] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11708 11:56:05.105421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass>
11709 11:56:05.106294 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_2 RESULT=pass
11711 11:56:05.122223 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3
11712 11:56:05.279573 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_3 (300 ms)
11713 11:56:05.289558 [0:03:08.270615372] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11714 11:56:05.395904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass>
11715 11:56:05.396264 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_3 RESULT=pass
11717 11:56:05.412644 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5
11718 11:56:05.646995 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_5 (367 ms)
11719 11:56:05.656817 [0:03:08.637463663] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11720 11:56:05.784981 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass>
11721 11:56:05.785804 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_5 RESULT=pass
11723 11:56:05.803937 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8
11724 11:56:06.114344 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_8 (468 ms)
11725 11:56:06.124160 [0:03:09.105780690] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11726 11:56:06.228423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass>
11727 11:56:06.228722 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_8 RESULT=pass
11729 11:56:06.246947 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13
11730 11:56:06.846280 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_13 (732 ms)
11731 11:56:06.856724 [0:03:09.837389318] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11732 11:56:06.981528 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass>
11733 11:56:06.982401 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_13 RESULT=pass
11735 11:56:07.001140 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21
11736 11:56:07.844442 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_21 (998 ms)
11737 11:56:07.854532 [0:03:10.835599368] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11738 11:56:07.982749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass>
11739 11:56:07.983564 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_21 RESULT=pass
11741 11:56:08.002505 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34
11742 11:56:09.309957 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_34 (1465 ms)
11743 11:56:09.319990 [0:03:12.302410995] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11744 11:56:09.449789 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass>
11745 11:56:09.450592 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_34 RESULT=pass
11747 11:56:09.467658 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55
11748 11:56:11.443137 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_55 (2133 ms)
11749 11:56:11.453177 [0:03:14.435791311] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11750 11:56:11.581099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass>
11751 11:56:11.581961 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_55 RESULT=pass
11753 11:56:11.601582 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89
11754 11:56:14.644040 [ OK ] CaptureTests/SingleStream.UnbalancedStop/StillCapture_89 (3201 ms)
11755 11:56:14.653600 [0:03:17.634544413] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11756 11:56:14.782718 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass>
11757 11:56:14.783569 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/StillCapture_89 RESULT=pass
11759 11:56:14.803193 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1
11760 11:56:14.941914 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_1 (299 ms)
11761 11:56:14.951835 [0:03:17.933087231] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11762 11:56:15.073841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass>
11763 11:56:15.074666 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_1 RESULT=pass
11765 11:56:15.092328 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2
11766 11:56:15.242527 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_2 (300 ms)
11767 11:56:15.252099 [0:03:18.233229122] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11768 11:56:15.375677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass>
11769 11:56:15.376537 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_2 RESULT=pass
11771 11:56:15.394083 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3
11772 11:56:15.542820 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_3 (300 ms)
11773 11:56:15.552450 [0:03:18.533505508] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11774 11:56:15.673723 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass>
11775 11:56:15.674610 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_3 RESULT=pass
11777 11:56:15.694160 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5
11778 11:56:16.007670 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_5 (465 ms)
11779 11:56:16.017388 [0:03:18.998301854] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11780 11:56:16.146527 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass>
11781 11:56:16.147473 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_5 RESULT=pass
11783 11:56:16.164998 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8
11784 11:56:16.572391 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_8 (565 ms)
11785 11:56:16.582808 [0:03:19.563185319] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11786 11:56:16.711010 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass>
11787 11:56:16.711988 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_8 RESULT=pass
11789 11:56:16.732900 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13
11790 11:56:17.269909 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_13 (698 ms)
11791 11:56:17.279740 [0:03:20.261074818] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11792 11:56:17.392462 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass>
11793 11:56:17.392766 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_13 RESULT=pass
11795 11:56:17.407016 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21
11796 11:56:18.169844 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_21 (900 ms)
11797 11:56:18.179770 [0:03:21.161016523] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11798 11:56:18.289400 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass>
11799 11:56:18.289725 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_21 RESULT=pass
11801 11:56:18.304787 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34
11802 11:56:19.567778 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_34 (1398 ms)
11803 11:56:19.577493 [0:03:22.559044294] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11804 11:56:19.676098 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass>
11805 11:56:19.676437 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_34 RESULT=pass
11807 11:56:19.692131 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55
11808 11:56:21.697989 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_55 (2130 ms)
11809 11:56:21.707575 [0:03:24.689407030] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11810 11:56:21.822536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass>
11811 11:56:21.823136 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_55 RESULT=pass
11813 11:56:21.839874 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89
11814 11:56:24.927971 [ OK ] CaptureTests/SingleStream.UnbalancedStop/VideoRecording_89 (3230 ms)
11815 11:56:24.937755 [0:03:27.919542358] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11816 11:56:25.045259 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass>
11817 11:56:25.045581 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/VideoRecording_89 RESULT=pass
11819 11:56:25.060546 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1
11820 11:56:25.225508 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_1 (298 ms)
11821 11:56:25.235518 [0:03:28.217759877] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11822 11:56:25.337159 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass
11824 11:56:25.340162 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_1 RESULT=pass>
11825 11:56:25.354751 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2
11826 11:56:25.525936 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_2 (301 ms)
11827 11:56:25.535720 [0:03:28.518248798] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11828 11:56:25.643458 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass
11830 11:56:25.646625 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_2 RESULT=pass>
11831 11:56:25.663252 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3
11832 11:56:25.827226 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_3 (300 ms)
11833 11:56:25.836589 [0:03:28.818831714] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11834 11:56:25.933179 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass
11836 11:56:25.936815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_3 RESULT=pass>
11837 11:56:25.952975 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5
11838 11:56:26.291612 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_5 (464 ms)
11839 11:56:26.301278 [0:03:29.283372167] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11840 11:56:26.404826 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass
11842 11:56:26.407667 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_5 RESULT=pass>
11843 11:56:26.425536 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8
11844 11:56:26.856146 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_8 (564 ms)
11845 11:56:26.865723 [0:03:29.847592921] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11846 11:56:26.970893 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass
11848 11:56:26.974022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_8 RESULT=pass>
11849 11:56:26.990032 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13
11850 11:56:27.553764 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_13 (698 ms)
11851 11:56:27.563612 [0:03:30.545704752] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11852 11:56:27.660170 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass
11854 11:56:27.663188 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_13 RESULT=pass>
11855 11:56:27.678881 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21
11856 11:56:28.452831 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_21 (899 ms)
11857 11:56:28.462868 [0:03:31.444905369] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11858 11:56:28.578307 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass
11860 11:56:28.580993 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_21 RESULT=pass>
11861 11:56:28.598766 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34
11862 11:56:29.851027 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_34 (1398 ms)
11863 11:56:29.860999 [0:03:32.843119020] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11864 11:56:29.970876 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass
11866 11:56:29.973470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_34 RESULT=pass>
11867 11:56:29.990010 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55
11868 11:56:31.949680 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_55 (2098 ms)
11869 11:56:31.958866 [0:03:34.941159749] [411] [1;32m INFO [1;37mCamera [1;34mcamera.cpp:1027 [0mconfiguring streams: (0) 1280x720-MJPEG
11870 11:56:32.085902 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass
11872 11:56:32.088393 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_55 RESULT=pass>
11873 11:56:32.108553 [ RUN ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89
11874 11:56:35.212255 [ OK ] CaptureTests/SingleStream.UnbalancedStop/Viewfinder_89 (3263 ms)
11875 11:56:35.347957 Received signal: <TESTCASE> TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass
11877 11:56:35.350885 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=UnbalancedStop/Viewfinder_89 RESULT=pass>
11878 11:56:35.369228 [----------] 120 tests from CaptureTests/SingleStream (189659 ms total)
11879 11:56:35.472547
11880 11:56:35.580607 [----------] Global test environment tear-down
11881 11:56:35.693673 [==========] 120 tests from 1 test suite ran. (189659 ms total)
11882 11:56:35.806956 <LAVA_SIGNAL_TESTSET STOP>
11883 11:56:35.807861 Received signal: <TESTSET> STOP
11884 11:56:35.808481 Closing test_set CaptureTests/SingleStream
11885 11:56:35.823143 + set +x
11886 11:56:35.826618 <LAVA_SIGNAL_ENDRUN 0_lc-compliance 12066517_1.6.2.3.1>
11887 11:56:35.827461 Received signal: <ENDRUN> 0_lc-compliance 12066517_1.6.2.3.1
11888 11:56:35.827943 Ending use of test pattern.
11889 11:56:35.828492 Ending test lava.0_lc-compliance (12066517_1.6.2.3.1), duration 191.49
11891 11:56:35.830609 <LAVA_TEST_RUNNER EXIT>
11892 11:56:35.831357 ok: lava_test_shell seems to have completed
11893 11:56:35.842886 Capture/Raw_1:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_13:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_2:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_21:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_3:
result: skip
set: CaptureTests/SingleStream
Capture/Raw_34:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_5:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_55:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_8:
result: pass
set: CaptureTests/SingleStream
Capture/Raw_89:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
Capture/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
Capture/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
Capture/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
Capture/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
Capture/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
Capture/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_1:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_2:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_3:
result: skip
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
CaptureStartStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Raw_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/StillCapture_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/VideoRecording_89:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_1:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_13:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_2:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_21:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_3:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_34:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_5:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_55:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_8:
result: pass
set: CaptureTests/SingleStream
UnbalancedStop/Viewfinder_89:
result: pass
set: CaptureTests/SingleStream
11894 11:56:35.843877 end: 3.1 lava-test-shell (duration 00:03:12) [common]
11895 11:56:35.844430 end: 3 lava-test-retry (duration 00:03:12) [common]
11896 11:56:35.844914 start: 4 finalize (timeout 00:10:00) [common]
11897 11:56:35.845398 start: 4.1 power-off (timeout 00:00:30) [common]
11898 11:56:35.846264 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11899 11:56:35.961766 >> Command sent successfully.
11900 11:56:35.966925 Returned 0 in 0 seconds
11901 11:56:36.067990 end: 4.1 power-off (duration 00:00:00) [common]
11903 11:56:36.070002 start: 4.2 read-feedback (timeout 00:10:00) [common]
11904 11:56:36.071489 Listened to connection for namespace 'common' for up to 1s
11905 11:56:36.072358 Listened to connection for namespace 'common' for up to 1s
11906 11:56:37.072096 Finalising connection for namespace 'common'
11907 11:56:37.073167 Disconnecting from shell: Finalise
11908 11:56:37.073833 / #
11909 11:56:37.175045 end: 4.2 read-feedback (duration 00:00:01) [common]
11910 11:56:37.175782 end: 4 finalize (duration 00:00:01) [common]
11911 11:56:37.176431 Cleaning after the job
11912 11:56:37.177045 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/ramdisk
11913 11:56:37.190224 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/kernel
11914 11:56:37.223835 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/dtb
11915 11:56:37.224121 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/nfsrootfs
11916 11:56:37.285742 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066517/tftp-deploy-xw34pi1y/modules
11917 11:56:37.292754 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066517
11918 11:56:37.612458 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066517
11919 11:56:37.612641 Job finished correctly