Boot log: mt8192-asurada-spherion-r0
- Warnings: 1
- Kernel Errors: 30
- Kernel Warnings: 25
- Boot result: PASS
- Errors: 1
1 11:56:05.081723 lava-dispatcher, installed at version: 2023.10
2 11:56:05.081944 start: 0 validate
3 11:56:05.082109 Start time: 2023-11-23 11:56:05.082101+00:00 (UTC)
4 11:56:05.082239 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:56:05.082373 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 11:56:05.349379 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:56:05.349561 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:56:05.616512 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:56:05.616704 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:56:05.882616 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:56:05.882853 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.62-cip9-13-g34c303883a305%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:56:06.150884 validate duration: 1.07
14 11:56:06.151285 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:56:06.151416 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:56:06.151535 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:56:06.151687 Not decompressing ramdisk as can be used compressed.
18 11:56:06.151809 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230623.0/arm64/rootfs.cpio.gz
19 11:56:06.151903 saving as /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/ramdisk/rootfs.cpio.gz
20 11:56:06.151997 total size: 26246609 (25 MB)
21 11:56:06.153643 progress 0 % (0 MB)
22 11:56:06.161168 progress 5 % (1 MB)
23 11:56:06.168781 progress 10 % (2 MB)
24 11:56:06.176215 progress 15 % (3 MB)
25 11:56:06.183731 progress 20 % (5 MB)
26 11:56:06.190845 progress 25 % (6 MB)
27 11:56:06.197935 progress 30 % (7 MB)
28 11:56:06.204887 progress 35 % (8 MB)
29 11:56:06.211921 progress 40 % (10 MB)
30 11:56:06.218973 progress 45 % (11 MB)
31 11:56:06.226054 progress 50 % (12 MB)
32 11:56:06.233294 progress 55 % (13 MB)
33 11:56:06.241426 progress 60 % (15 MB)
34 11:56:06.248966 progress 65 % (16 MB)
35 11:56:06.256286 progress 70 % (17 MB)
36 11:56:06.263613 progress 75 % (18 MB)
37 11:56:06.270806 progress 80 % (20 MB)
38 11:56:06.277821 progress 85 % (21 MB)
39 11:56:06.284707 progress 90 % (22 MB)
40 11:56:06.291596 progress 95 % (23 MB)
41 11:56:06.298552 progress 100 % (25 MB)
42 11:56:06.298831 25 MB downloaded in 0.15 s (170.47 MB/s)
43 11:56:06.298996 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:56:06.299247 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:56:06.299336 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:56:06.299422 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:56:06.299563 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:56:06.299638 saving as /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/kernel/Image
50 11:56:06.299700 total size: 49107456 (46 MB)
51 11:56:06.299764 No compression specified
52 11:56:06.301038 progress 0 % (0 MB)
53 11:56:06.314341 progress 5 % (2 MB)
54 11:56:06.327437 progress 10 % (4 MB)
55 11:56:06.340792 progress 15 % (7 MB)
56 11:56:06.354066 progress 20 % (9 MB)
57 11:56:06.367188 progress 25 % (11 MB)
58 11:56:06.380114 progress 30 % (14 MB)
59 11:56:06.393120 progress 35 % (16 MB)
60 11:56:06.406490 progress 40 % (18 MB)
61 11:56:06.419554 progress 45 % (21 MB)
62 11:56:06.432925 progress 50 % (23 MB)
63 11:56:06.446297 progress 55 % (25 MB)
64 11:56:06.459548 progress 60 % (28 MB)
65 11:56:06.472380 progress 65 % (30 MB)
66 11:56:06.485480 progress 70 % (32 MB)
67 11:56:06.498348 progress 75 % (35 MB)
68 11:56:06.511479 progress 80 % (37 MB)
69 11:56:06.524748 progress 85 % (39 MB)
70 11:56:06.537907 progress 90 % (42 MB)
71 11:56:06.550747 progress 95 % (44 MB)
72 11:56:06.563369 progress 100 % (46 MB)
73 11:56:06.563603 46 MB downloaded in 0.26 s (177.46 MB/s)
74 11:56:06.563757 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:56:06.563994 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:56:06.564081 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:56:06.564173 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:56:06.564311 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:56:06.564380 saving as /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/dtb/mt8192-asurada-spherion-r0.dtb
81 11:56:06.564441 total size: 47278 (0 MB)
82 11:56:06.564502 No compression specified
83 11:56:06.565716 progress 69 % (0 MB)
84 11:56:06.565990 progress 100 % (0 MB)
85 11:56:06.566148 0 MB downloaded in 0.00 s (26.46 MB/s)
86 11:56:06.566273 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:56:06.566495 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:56:06.566578 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:56:06.566659 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:56:06.566779 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.62-cip9-13-g34c303883a305/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:56:06.566849 saving as /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/modules/modules.tar
93 11:56:06.566909 total size: 8621364 (8 MB)
94 11:56:06.566971 Using unxz to decompress xz
95 11:56:06.571320 progress 0 % (0 MB)
96 11:56:06.593207 progress 5 % (0 MB)
97 11:56:06.617710 progress 10 % (0 MB)
98 11:56:06.642158 progress 15 % (1 MB)
99 11:56:06.666558 progress 20 % (1 MB)
100 11:56:06.691794 progress 25 % (2 MB)
101 11:56:06.719300 progress 30 % (2 MB)
102 11:56:06.748520 progress 35 % (2 MB)
103 11:56:06.774860 progress 40 % (3 MB)
104 11:56:06.802073 progress 45 % (3 MB)
105 11:56:06.829831 progress 50 % (4 MB)
106 11:56:06.856074 progress 55 % (4 MB)
107 11:56:06.882904 progress 60 % (4 MB)
108 11:56:06.913403 progress 65 % (5 MB)
109 11:56:06.941052 progress 70 % (5 MB)
110 11:56:06.966624 progress 75 % (6 MB)
111 11:56:06.995387 progress 80 % (6 MB)
112 11:56:07.022728 progress 85 % (7 MB)
113 11:56:07.049613 progress 90 % (7 MB)
114 11:56:07.081171 progress 95 % (7 MB)
115 11:56:07.112640 progress 100 % (8 MB)
116 11:56:07.117612 8 MB downloaded in 0.55 s (14.93 MB/s)
117 11:56:07.117925 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:56:07.118332 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:56:07.118429 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:56:07.118541 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:56:07.118626 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:56:07.118713 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:56:07.118964 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn
125 11:56:07.119121 makedir: /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin
126 11:56:07.119231 makedir: /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/tests
127 11:56:07.119350 makedir: /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/results
128 11:56:07.119475 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-add-keys
129 11:56:07.119661 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-add-sources
130 11:56:07.119810 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-background-process-start
131 11:56:07.119949 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-background-process-stop
132 11:56:07.120093 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-common-functions
133 11:56:07.120225 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-echo-ipv4
134 11:56:07.120372 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-install-packages
135 11:56:07.120505 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-installed-packages
136 11:56:07.120646 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-os-build
137 11:56:07.120788 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-probe-channel
138 11:56:07.120917 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-probe-ip
139 11:56:07.121056 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-target-ip
140 11:56:07.121186 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-target-mac
141 11:56:07.121324 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-target-storage
142 11:56:07.121459 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-case
143 11:56:07.121622 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-event
144 11:56:07.121785 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-feedback
145 11:56:07.121958 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-raise
146 11:56:07.122131 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-reference
147 11:56:07.122300 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-runner
148 11:56:07.122464 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-set
149 11:56:07.122637 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-test-shell
150 11:56:07.122810 Updating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-install-packages (oe)
151 11:56:07.123003 Updating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/bin/lava-installed-packages (oe)
152 11:56:07.123175 Creating /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/environment
153 11:56:07.123324 LAVA metadata
154 11:56:07.123401 - LAVA_JOB_ID=12066541
155 11:56:07.123468 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:56:07.123593 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:56:07.123664 skipped lava-vland-overlay
158 11:56:07.123740 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:56:07.123841 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:56:07.123910 skipped lava-multinode-overlay
161 11:56:07.123988 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:56:07.124092 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:56:07.124172 Loading test definitions
164 11:56:07.124274 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:56:07.124356 Using /lava-12066541 at stage 0
166 11:56:07.124684 uuid=12066541_1.5.2.3.1 testdef=None
167 11:56:07.124783 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:56:07.124875 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:56:07.125490 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:56:07.125869 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:56:07.126806 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:56:07.127088 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:56:07.127720 runner path: /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 12066541_1.5.2.3.1
176 11:56:07.127894 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:56:07.128131 Creating lava-test-runner.conf files
179 11:56:07.128196 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12066541/lava-overlay-6whj77rn/lava-12066541/0 for stage 0
180 11:56:07.128297 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:56:07.128398 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:56:07.128486 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:56:07.136474 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:56:07.136614 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:56:07.136707 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:56:07.136808 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:56:07.136902 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:56:07.879023 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:56:07.879458 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:56:07.879606 extracting modules file /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12066541/extract-overlay-ramdisk-qfd_24bx/ramdisk
191 11:56:08.150302 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:56:08.150495 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:56:08.150628 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066541/compress-overlay-x8_ug82g/overlay-1.5.2.4.tar.gz to ramdisk
194 11:56:08.150732 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12066541/compress-overlay-x8_ug82g/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12066541/extract-overlay-ramdisk-qfd_24bx/ramdisk
195 11:56:08.160856 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:56:08.161010 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:56:08.161133 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:56:08.161260 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:56:08.161371 Building ramdisk /var/lib/lava/dispatcher/tmp/12066541/extract-overlay-ramdisk-qfd_24bx/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12066541/extract-overlay-ramdisk-qfd_24bx/ramdisk
200 11:56:08.807489 >> 228427 blocks
201 11:56:12.885115 rename /var/lib/lava/dispatcher/tmp/12066541/extract-overlay-ramdisk-qfd_24bx/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/ramdisk/ramdisk.cpio.gz
202 11:56:12.885633 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:56:12.885768 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
204 11:56:12.885883 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
205 11:56:12.885991 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/kernel/Image'
206 11:56:26.112615 Returned 0 in 13 seconds
207 11:56:26.213260 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/kernel/image.itb
208 11:56:26.828656 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:56:26.829046 output: Created: Thu Nov 23 11:56:26 2023
210 11:56:26.829126 output: Image 0 (kernel-1)
211 11:56:26.829194 output: Description:
212 11:56:26.829263 output: Created: Thu Nov 23 11:56:26 2023
213 11:56:26.829333 output: Type: Kernel Image
214 11:56:26.829394 output: Compression: lzma compressed
215 11:56:26.829457 output: Data Size: 11047184 Bytes = 10788.27 KiB = 10.54 MiB
216 11:56:26.829519 output: Architecture: AArch64
217 11:56:26.829587 output: OS: Linux
218 11:56:26.829644 output: Load Address: 0x00000000
219 11:56:26.829701 output: Entry Point: 0x00000000
220 11:56:26.829758 output: Hash algo: crc32
221 11:56:26.829818 output: Hash value: e6d7c86f
222 11:56:26.829878 output: Image 1 (fdt-1)
223 11:56:26.829934 output: Description: mt8192-asurada-spherion-r0
224 11:56:26.829988 output: Created: Thu Nov 23 11:56:26 2023
225 11:56:26.830043 output: Type: Flat Device Tree
226 11:56:26.830098 output: Compression: uncompressed
227 11:56:26.830153 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 11:56:26.830208 output: Architecture: AArch64
229 11:56:26.830261 output: Hash algo: crc32
230 11:56:26.830314 output: Hash value: cc4352de
231 11:56:26.830367 output: Image 2 (ramdisk-1)
232 11:56:26.830426 output: Description: unavailable
233 11:56:26.830480 output: Created: Thu Nov 23 11:56:26 2023
234 11:56:26.830534 output: Type: RAMDisk Image
235 11:56:26.830588 output: Compression: Unknown Compression
236 11:56:26.830645 output: Data Size: 39354927 Bytes = 38432.55 KiB = 37.53 MiB
237 11:56:26.830700 output: Architecture: AArch64
238 11:56:26.830753 output: OS: Linux
239 11:56:26.830806 output: Load Address: unavailable
240 11:56:26.830859 output: Entry Point: unavailable
241 11:56:26.830918 output: Hash algo: crc32
242 11:56:26.830972 output: Hash value: 45f561e5
243 11:56:26.831025 output: Default Configuration: 'conf-1'
244 11:56:26.831078 output: Configuration 0 (conf-1)
245 11:56:26.831131 output: Description: mt8192-asurada-spherion-r0
246 11:56:26.831189 output: Kernel: kernel-1
247 11:56:26.831243 output: Init Ramdisk: ramdisk-1
248 11:56:26.831296 output: FDT: fdt-1
249 11:56:26.831348 output: Loadables: kernel-1
250 11:56:26.831406 output:
251 11:56:26.831664 end: 1.5.8.1 prepare-fit (duration 00:00:14) [common]
252 11:56:26.831774 end: 1.5.8 prepare-kernel (duration 00:00:14) [common]
253 11:56:26.831885 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:56:26.831984 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:56:26.832074 No LXC device requested
256 11:56:26.832164 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:56:26.832253 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:56:26.832334 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:56:26.832410 Checking files for TFTP limit of 4294967296 bytes.
260 11:56:26.832930 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:56:26.833036 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:56:26.833129 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:56:26.833259 substitutions:
264 11:56:26.833327 - {DTB}: 12066541/tftp-deploy-wp7f11ac/dtb/mt8192-asurada-spherion-r0.dtb
265 11:56:26.833393 - {INITRD}: 12066541/tftp-deploy-wp7f11ac/ramdisk/ramdisk.cpio.gz
266 11:56:26.833455 - {KERNEL}: 12066541/tftp-deploy-wp7f11ac/kernel/Image
267 11:56:26.833513 - {LAVA_MAC}: None
268 11:56:26.833570 - {PRESEED_CONFIG}: None
269 11:56:26.833660 - {PRESEED_LOCAL}: None
270 11:56:26.833718 - {RAMDISK}: 12066541/tftp-deploy-wp7f11ac/ramdisk/ramdisk.cpio.gz
271 11:56:26.833774 - {ROOT_PART}: None
272 11:56:26.833829 - {ROOT}: None
273 11:56:26.833886 - {SERVER_IP}: 192.168.201.1
274 11:56:26.833943 - {TEE}: None
275 11:56:26.833998 Parsed boot commands:
276 11:56:26.834052 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:56:26.834239 Parsed boot commands: tftpboot 192.168.201.1 12066541/tftp-deploy-wp7f11ac/kernel/image.itb 12066541/tftp-deploy-wp7f11ac/kernel/cmdline
278 11:56:26.834330 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:56:26.834426 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:56:26.834526 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:56:26.834618 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:56:26.834696 Not connected, no need to disconnect.
283 11:56:26.834771 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:56:26.834852 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:56:26.834925 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 11:56:26.839090 Setting prompt string to ['lava-test: # ']
287 11:56:26.839504 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:56:26.839625 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:56:26.839730 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:56:26.839831 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:56:26.840037 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 11:56:31.976490 >> Command sent successfully.
293 11:56:31.979106 Returned 0 in 5 seconds
294 11:56:32.079581 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:56:32.080078 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:56:32.080239 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:56:32.080386 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:56:32.080496 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:56:32.080608 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:56:32.081060 [Enter `^Ec?' for help]
302 11:56:32.253099
303 11:56:32.253603
304 11:56:32.253948 F0: 102B 0000
305 11:56:32.254258
306 11:56:32.254547 F3: 1001 0000 [0200]
307 11:56:32.256401
308 11:56:32.256794 F3: 1001 0000
309 11:56:32.257099
310 11:56:32.257384 F7: 102D 0000
311 11:56:32.257705
312 11:56:32.260171 F1: 0000 0000
313 11:56:32.260570
314 11:56:32.260877 V0: 0000 0000 [0001]
315 11:56:32.261176
316 11:56:32.262992 00: 0007 8000
317 11:56:32.263400
318 11:56:32.263814 01: 0000 0000
319 11:56:32.264138
320 11:56:32.266210 BP: 0C00 0209 [0000]
321 11:56:32.266614
322 11:56:32.266922 G0: 1182 0000
323 11:56:32.267207
324 11:56:32.269800 EC: 0000 0021 [4000]
325 11:56:32.270205
326 11:56:32.270744 S7: 0000 0000 [0000]
327 11:56:32.271098
328 11:56:32.273568 CC: 0000 0000 [0001]
329 11:56:32.274023
330 11:56:32.274334 T0: 0000 0040 [010F]
331 11:56:32.274628
332 11:56:32.274900 Jump to BL
333 11:56:32.276664
334 11:56:32.300780
335 11:56:32.301174
336 11:56:32.301479
337 11:56:32.307794 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:56:32.311196 ARM64: Exception handlers installed.
339 11:56:32.314787 ARM64: Testing exception
340 11:56:32.318157 ARM64: Done test exception
341 11:56:32.324811 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:56:32.335442 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:56:32.341925 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:56:32.351709 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:56:32.358338 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:56:32.365248 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:56:32.376877 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:56:32.383490 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:56:32.403239 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:56:32.406375 WDT: Last reset was cold boot
351 11:56:32.410080 SPI1(PAD0) initialized at 2873684 Hz
352 11:56:32.413414 SPI5(PAD0) initialized at 992727 Hz
353 11:56:32.416186 VBOOT: Loading verstage.
354 11:56:32.423173 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:56:32.427238 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:56:32.430899 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:56:32.434123 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:56:32.441084 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:56:32.447136 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:56:32.458277 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:56:32.458665
362 11:56:32.458972
363 11:56:32.469037 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:56:32.472208 ARM64: Exception handlers installed.
365 11:56:32.472599 ARM64: Testing exception
366 11:56:32.475355 ARM64: Done test exception
367 11:56:32.479002 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:56:32.485897 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:56:32.498999 Probing TPM: . done!
370 11:56:32.499392 TPM ready after 0 ms
371 11:56:32.506275 Connected to device vid:did:rid of 1ae0:0028:00
372 11:56:32.513099 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 11:56:32.572627 Initialized TPM device CR50 revision 0
374 11:56:32.583727 tlcl_send_startup: Startup return code is 0
375 11:56:32.584179 TPM: setup succeeded
376 11:56:32.595429 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:56:32.604044 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:56:32.616181 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:56:32.626344 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:56:32.630669 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:56:32.634217 in-header: 03 07 00 00 08 00 00 00
382 11:56:32.637988 in-data: aa e4 47 04 13 02 00 00
383 11:56:32.638545 Chrome EC: UHEPI supported
384 11:56:32.646004 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:56:32.649235 in-header: 03 95 00 00 08 00 00 00
386 11:56:32.652986 in-data: 18 20 20 08 00 00 00 00
387 11:56:32.653378 Phase 1
388 11:56:32.656783 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:56:32.664073 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:56:32.667959 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:56:32.672023 Recovery requested (1009000e)
392 11:56:32.681056 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:56:32.686722 tlcl_extend: response is 0
394 11:56:32.696004 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:56:32.701645 tlcl_extend: response is 0
396 11:56:32.708969 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:56:32.728216 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
398 11:56:32.734865 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:56:32.735291
400 11:56:32.735615
401 11:56:32.745297 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:56:32.748487 ARM64: Exception handlers installed.
403 11:56:32.751609 ARM64: Testing exception
404 11:56:32.751998 ARM64: Done test exception
405 11:56:32.773917 pmic_efuse_setting: Set efuses in 11 msecs
406 11:56:32.777427 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:56:32.784091 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:56:32.787572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:56:32.791148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:56:32.798595 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:56:32.802576 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:56:32.806352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:56:32.813075 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:56:32.817727 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:56:32.821167 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:56:32.828066 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:56:32.832121 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:56:32.835438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:56:32.839205 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:56:32.845993 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:56:32.853274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:56:32.856954 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:56:32.864541 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:56:32.868293 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:56:32.876012 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:56:32.879602 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:56:32.887138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:56:32.890467 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:56:32.898014 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:56:32.901812 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:56:32.909529 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:56:32.912983 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:56:32.920537 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:56:32.924210 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:56:32.927735 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:56:32.931800 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:56:32.938716 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:56:32.942796 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:56:32.946329 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:56:32.953713 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:56:32.957388 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:56:32.961741 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:56:32.968832 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:56:32.972353 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:56:32.976009 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:56:32.983419 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:56:32.987403 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:56:32.991031 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:56:32.994346 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:56:32.998274 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:56:33.002212 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:56:33.009685 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:56:33.013276 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:56:33.016250 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:56:33.019987 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:56:33.023398 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:56:33.027118 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:56:33.038901 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:56:33.046700 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:56:33.049922 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:56:33.057199 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:56:33.068286 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:56:33.072538 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:56:33.075834 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:56:33.079615 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:56:33.086986 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x18
467 11:56:33.091123 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:56:33.098970 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:56:33.102028 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:56:33.111880 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 11:56:33.121216 [RTC]rtc_get_frequency_meter,154: input=23, output=943
472 11:56:33.131000 [RTC]rtc_get_frequency_meter,154: input=19, output=852
473 11:56:33.140333 [RTC]rtc_get_frequency_meter,154: input=17, output=805
474 11:56:33.149852 [RTC]rtc_get_frequency_meter,154: input=16, output=781
475 11:56:33.159247 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 11:56:33.168528 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 11:56:33.171775 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 11:56:33.179879 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 11:56:33.183025 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:56:33.186671 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:56:33.190396 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:56:33.194564 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:56:33.197887 ADC[4]: Raw value=906203 ID=7
484 11:56:33.202521 ADC[3]: Raw value=213441 ID=1
485 11:56:33.202974 RAM Code: 0x71
486 11:56:33.206173 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:56:33.209994 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:56:33.221348 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:56:33.224898 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:56:33.228019 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:56:33.231988 in-header: 03 07 00 00 08 00 00 00
492 11:56:33.235863 in-data: aa e4 47 04 13 02 00 00
493 11:56:33.239395 Chrome EC: UHEPI supported
494 11:56:33.246904 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:56:33.250807 in-header: 03 95 00 00 08 00 00 00
496 11:56:33.254333 in-data: 18 20 20 08 00 00 00 00
497 11:56:33.257962 MRC: failed to locate region type 0.
498 11:56:33.261655 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:56:33.265891 DRAM-K: Running full calibration
500 11:56:33.272490 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:56:33.276387 header.status = 0x0
502 11:56:33.276805 header.version = 0x6 (expected: 0x6)
503 11:56:33.280330 header.size = 0xd00 (expected: 0xd00)
504 11:56:33.284353 header.flags = 0x0
505 11:56:33.287270 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:56:33.307761 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
507 11:56:33.314888 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:56:33.315344 dram_init: ddr_geometry: 2
509 11:56:33.318836 [EMI] MDL number = 2
510 11:56:33.322403 [EMI] Get MDL freq = 0
511 11:56:33.322883 dram_init: ddr_type: 0
512 11:56:33.326297 is_discrete_lpddr4: 1
513 11:56:33.326720 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:56:33.329677
515 11:56:33.330095
516 11:56:33.330425 [Bian_co] ETT version 0.0.0.1
517 11:56:33.333646 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:56:33.337459
519 11:56:33.341688 dramc_set_vcore_voltage set vcore to 650000
520 11:56:33.342199 Read voltage for 800, 4
521 11:56:33.342544 Vio18 = 0
522 11:56:33.345706 Vcore = 650000
523 11:56:33.346187 Vdram = 0
524 11:56:33.346523 Vddq = 0
525 11:56:33.346834 Vmddr = 0
526 11:56:33.348906 dram_init: config_dvfs: 1
527 11:56:33.353158 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:56:33.360793 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:56:33.364391 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 11:56:33.368332 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 11:56:33.372122 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 11:56:33.375450 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 11:56:33.375872 MEM_TYPE=3, freq_sel=18
534 11:56:33.379023 sv_algorithm_assistance_LP4_1600
535 11:56:33.382574 ============ PULL DRAM RESETB DOWN ============
536 11:56:33.389041 ========== PULL DRAM RESETB DOWN end =========
537 11:56:33.392517 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:56:33.396283 ===================================
539 11:56:33.400114 LPDDR4 DRAM CONFIGURATION
540 11:56:33.400535 ===================================
541 11:56:33.403673 EX_ROW_EN[0] = 0x0
542 11:56:33.407488 EX_ROW_EN[1] = 0x0
543 11:56:33.407933 LP4Y_EN = 0x0
544 11:56:33.410960 WORK_FSP = 0x0
545 11:56:33.411378 WL = 0x2
546 11:56:33.411731 RL = 0x2
547 11:56:33.414556 BL = 0x2
548 11:56:33.414956 RPST = 0x0
549 11:56:33.417727 RD_PRE = 0x0
550 11:56:33.420967 WR_PRE = 0x1
551 11:56:33.421416 WR_PST = 0x0
552 11:56:33.424674 DBI_WR = 0x0
553 11:56:33.425300 DBI_RD = 0x0
554 11:56:33.428173 OTF = 0x1
555 11:56:33.431628 ===================================
556 11:56:33.434566 ===================================
557 11:56:33.435013 ANA top config
558 11:56:33.438178 ===================================
559 11:56:33.441313 DLL_ASYNC_EN = 0
560 11:56:33.441851 ALL_SLAVE_EN = 1
561 11:56:33.444862 NEW_RANK_MODE = 1
562 11:56:33.447664 DLL_IDLE_MODE = 1
563 11:56:33.451300 LP45_APHY_COMB_EN = 1
564 11:56:33.454842 TX_ODT_DIS = 1
565 11:56:33.455295 NEW_8X_MODE = 1
566 11:56:33.458871 ===================================
567 11:56:33.462186 ===================================
568 11:56:33.465341 data_rate = 1600
569 11:56:33.468513 CKR = 1
570 11:56:33.472488 DQ_P2S_RATIO = 8
571 11:56:33.475462 ===================================
572 11:56:33.475882 CA_P2S_RATIO = 8
573 11:56:33.478687 DQ_CA_OPEN = 0
574 11:56:33.482331 DQ_SEMI_OPEN = 0
575 11:56:33.485280 CA_SEMI_OPEN = 0
576 11:56:33.488793 CA_FULL_RATE = 0
577 11:56:33.492364 DQ_CKDIV4_EN = 1
578 11:56:33.492779 CA_CKDIV4_EN = 1
579 11:56:33.495753 CA_PREDIV_EN = 0
580 11:56:33.498791 PH8_DLY = 0
581 11:56:33.502342 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:56:33.505507 DQ_AAMCK_DIV = 4
583 11:56:33.505977 CA_AAMCK_DIV = 4
584 11:56:33.509367 CA_ADMCK_DIV = 4
585 11:56:33.512277 DQ_TRACK_CA_EN = 0
586 11:56:33.515711 CA_PICK = 800
587 11:56:33.518665 CA_MCKIO = 800
588 11:56:33.523228 MCKIO_SEMI = 0
589 11:56:33.523651 PLL_FREQ = 3068
590 11:56:33.526723 DQ_UI_PI_RATIO = 32
591 11:56:33.530278 CA_UI_PI_RATIO = 0
592 11:56:33.534216 ===================================
593 11:56:33.537850 ===================================
594 11:56:33.538305 memory_type:LPDDR4
595 11:56:33.541411 GP_NUM : 10
596 11:56:33.542010 SRAM_EN : 1
597 11:56:33.545851 MD32_EN : 0
598 11:56:33.548752 ===================================
599 11:56:33.553100 [ANA_INIT] >>>>>>>>>>>>>>
600 11:56:33.553539 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:56:33.557347 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:56:33.559926 ===================================
603 11:56:33.563195 data_rate = 1600,PCW = 0X7600
604 11:56:33.566484 ===================================
605 11:56:33.570304 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:56:33.576506 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:56:33.580095 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:56:33.586447 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:56:33.590030 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:56:33.593022 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:56:33.593444 [ANA_INIT] flow start
612 11:56:33.596851 [ANA_INIT] PLL >>>>>>>>
613 11:56:33.600118 [ANA_INIT] PLL <<<<<<<<
614 11:56:33.600541 [ANA_INIT] MIDPI >>>>>>>>
615 11:56:33.603336 [ANA_INIT] MIDPI <<<<<<<<
616 11:56:33.606324 [ANA_INIT] DLL >>>>>>>>
617 11:56:33.606771 [ANA_INIT] flow end
618 11:56:33.613406 ============ LP4 DIFF to SE enter ============
619 11:56:33.616813 ============ LP4 DIFF to SE exit ============
620 11:56:33.620034 [ANA_INIT] <<<<<<<<<<<<<
621 11:56:33.620444 [Flow] Enable top DCM control >>>>>
622 11:56:33.623534 [Flow] Enable top DCM control <<<<<
623 11:56:33.626431 Enable DLL master slave shuffle
624 11:56:33.633606 ==============================================================
625 11:56:33.636825 Gating Mode config
626 11:56:33.640298 ==============================================================
627 11:56:33.643435 Config description:
628 11:56:33.653717 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:56:33.660050 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:56:33.663694 SELPH_MODE 0: By rank 1: By Phase
631 11:56:33.670658 ==============================================================
632 11:56:33.673457 GAT_TRACK_EN = 1
633 11:56:33.673945 RX_GATING_MODE = 2
634 11:56:33.677207 RX_GATING_TRACK_MODE = 2
635 11:56:33.680231 SELPH_MODE = 1
636 11:56:33.683912 PICG_EARLY_EN = 1
637 11:56:33.686947 VALID_LAT_VALUE = 1
638 11:56:33.693819 ==============================================================
639 11:56:33.696726 Enter into Gating configuration >>>>
640 11:56:33.700457 Exit from Gating configuration <<<<
641 11:56:33.703630 Enter into DVFS_PRE_config >>>>>
642 11:56:33.713874 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:56:33.716928 Exit from DVFS_PRE_config <<<<<
644 11:56:33.720728 Enter into PICG configuration >>>>
645 11:56:33.724028 Exit from PICG configuration <<<<
646 11:56:33.727135 [RX_INPUT] configuration >>>>>
647 11:56:33.727620 [RX_INPUT] configuration <<<<<
648 11:56:33.733998 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:56:33.740543 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:56:33.743872 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:56:33.750512 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:56:33.757148 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:56:33.764262 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:56:33.767063 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:56:33.770440 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:56:33.777100 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:56:33.780383 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:56:33.783770 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:56:33.786917 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:56:33.790673 ===================================
661 11:56:33.793874 LPDDR4 DRAM CONFIGURATION
662 11:56:33.797431 ===================================
663 11:56:33.800396 EX_ROW_EN[0] = 0x0
664 11:56:33.800811 EX_ROW_EN[1] = 0x0
665 11:56:33.804127 LP4Y_EN = 0x0
666 11:56:33.804541 WORK_FSP = 0x0
667 11:56:33.807105 WL = 0x2
668 11:56:33.807519 RL = 0x2
669 11:56:33.810827 BL = 0x2
670 11:56:33.811242 RPST = 0x0
671 11:56:33.813882 RD_PRE = 0x0
672 11:56:33.814299 WR_PRE = 0x1
673 11:56:33.816876 WR_PST = 0x0
674 11:56:33.820645 DBI_WR = 0x0
675 11:56:33.821062 DBI_RD = 0x0
676 11:56:33.823641 OTF = 0x1
677 11:56:33.827298 ===================================
678 11:56:33.830605 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:56:33.834338 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:56:33.837397 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:56:33.840510 ===================================
682 11:56:33.844609 LPDDR4 DRAM CONFIGURATION
683 11:56:33.847414 ===================================
684 11:56:33.850976 EX_ROW_EN[0] = 0x10
685 11:56:33.851393 EX_ROW_EN[1] = 0x0
686 11:56:33.853942 LP4Y_EN = 0x0
687 11:56:33.854358 WORK_FSP = 0x0
688 11:56:33.857369 WL = 0x2
689 11:56:33.857819 RL = 0x2
690 11:56:33.860814 BL = 0x2
691 11:56:33.861227 RPST = 0x0
692 11:56:33.863924 RD_PRE = 0x0
693 11:56:33.864387 WR_PRE = 0x1
694 11:56:33.866945 WR_PST = 0x0
695 11:56:33.867504 DBI_WR = 0x0
696 11:56:33.870482 DBI_RD = 0x0
697 11:56:33.870922 OTF = 0x1
698 11:56:33.873710 ===================================
699 11:56:33.880632 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:56:33.885136 nWR fixed to 40
701 11:56:33.888913 [ModeRegInit_LP4] CH0 RK0
702 11:56:33.889403 [ModeRegInit_LP4] CH0 RK1
703 11:56:33.891553 [ModeRegInit_LP4] CH1 RK0
704 11:56:33.895219 [ModeRegInit_LP4] CH1 RK1
705 11:56:33.895673 match AC timing 13
706 11:56:33.902162 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:56:33.904978 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:56:33.908844 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:56:33.915378 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:56:33.918525 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:56:33.918977 [EMI DOE] emi_dcm 0
712 11:56:33.925434 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:56:33.925897 ==
714 11:56:33.928573 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:56:33.931873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:56:33.932293 ==
717 11:56:33.938665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:56:33.945364 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:56:33.952775 [CA 0] Center 36 (6~67) winsize 62
720 11:56:33.955998 [CA 1] Center 36 (6~67) winsize 62
721 11:56:33.959134 [CA 2] Center 34 (4~65) winsize 62
722 11:56:33.962744 [CA 3] Center 33 (3~64) winsize 62
723 11:56:33.966108 [CA 4] Center 33 (3~64) winsize 62
724 11:56:33.969486 [CA 5] Center 32 (2~62) winsize 61
725 11:56:33.970035
726 11:56:33.972596 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:56:33.973088
728 11:56:33.976171 [CATrainingPosCal] consider 1 rank data
729 11:56:33.979386 u2DelayCellTimex100 = 270/100 ps
730 11:56:33.982634 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 11:56:33.986123 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 11:56:33.989404 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 11:56:33.996533 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
734 11:56:33.999364 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
735 11:56:34.002635 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 11:56:34.003134
737 11:56:34.006254 CA PerBit enable=1, Macro0, CA PI delay=32
738 11:56:34.006731
739 11:56:34.009433 [CBTSetCACLKResult] CA Dly = 32
740 11:56:34.010138 CS Dly: 4 (0~35)
741 11:56:34.010613 ==
742 11:56:34.019906 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:56:34.020499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:56:34.020882 ==
745 11:56:34.022825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:56:34.029327 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:56:34.038571 [CA 0] Center 36 (6~67) winsize 62
748 11:56:34.042928 [CA 1] Center 36 (6~67) winsize 62
749 11:56:34.045388 [CA 2] Center 34 (3~65) winsize 63
750 11:56:34.048357 [CA 3] Center 33 (3~64) winsize 62
751 11:56:34.052148 [CA 4] Center 33 (3~64) winsize 62
752 11:56:34.055140 [CA 5] Center 32 (2~63) winsize 62
753 11:56:34.055537
754 11:56:34.058681 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:56:34.059063
756 11:56:34.061984 [CATrainingPosCal] consider 2 rank data
757 11:56:34.065567 u2DelayCellTimex100 = 270/100 ps
758 11:56:34.068850 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 11:56:34.072258 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 11:56:34.078915 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 11:56:34.082133 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
762 11:56:34.085714 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
763 11:56:34.088823 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 11:56:34.089190
765 11:56:34.092474 CA PerBit enable=1, Macro0, CA PI delay=32
766 11:56:34.092991
767 11:56:34.095511 [CBTSetCACLKResult] CA Dly = 32
768 11:56:34.096023 CS Dly: 4 (0~36)
769 11:56:34.096511
770 11:56:34.099000 ----->DramcWriteLeveling(PI) begin...
771 11:56:34.102935 ==
772 11:56:34.103364 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:56:34.106282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:56:34.110682 ==
775 11:56:34.111183 Write leveling (Byte 0): 32 => 32
776 11:56:34.114220 Write leveling (Byte 1): 29 => 29
777 11:56:34.117641 DramcWriteLeveling(PI) end<-----
778 11:56:34.118178
779 11:56:34.118755 ==
780 11:56:34.120794 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:56:34.124126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:56:34.124547 ==
783 11:56:34.128104 [Gating] SW mode calibration
784 11:56:34.135043 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:56:34.141690 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:56:34.144902 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:56:34.148722 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:56:34.151610 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 11:56:34.158618 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:56:34.161507 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:56:34.165243 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:56:34.171143 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:56:34.174892 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:56:34.178016 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:56:34.184967 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:56:34.188116 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:56:34.191315 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:56:34.198026 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:56:34.201555 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:56:34.204776 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:56:34.211477 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:56:34.215097 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 11:56:34.218397 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:56:34.224745 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
805 11:56:34.228183 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
806 11:56:34.232037 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:56:34.235339 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:56:34.241451 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:56:34.244735 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:56:34.248333 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:56:34.254931 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:56:34.258472 0 9 8 | B1->B0 | 2323 2f2f | 0 1 | (1 1) (1 1)
813 11:56:34.261853 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
814 11:56:34.268608 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:56:34.271739 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:56:34.274906 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:56:34.281649 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:56:34.285368 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:56:34.288486 0 10 4 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
820 11:56:34.295713 0 10 8 | B1->B0 | 3030 2525 | 0 0 | (0 0) (1 0)
821 11:56:34.298700 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:56:34.301724 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:56:34.305217 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:56:34.311957 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:56:34.315310 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:56:34.318740 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:56:34.325829 0 11 4 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
828 11:56:34.328507 0 11 8 | B1->B0 | 2929 4444 | 0 0 | (0 0) (0 0)
829 11:56:34.331715 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
830 11:56:34.338454 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:56:34.341454 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:56:34.345196 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:56:34.351738 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:56:34.355275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:56:34.358364 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:56:34.365272 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 11:56:34.368678 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 11:56:34.371586 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:56:34.378757 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:56:34.381720 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:56:34.384966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:56:34.391784 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:56:34.395481 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:56:34.398361 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:56:34.401809 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:56:34.408731 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:56:34.411588 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:56:34.415143 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:56:34.421816 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:56:34.424938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:56:34.428613 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:56:34.434976 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
853 11:56:34.438222 Total UI for P1: 0, mck2ui 16
854 11:56:34.441763 best dqsien dly found for B0: ( 0, 14, 6)
855 11:56:34.445276 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:56:34.448525 Total UI for P1: 0, mck2ui 16
857 11:56:34.452026 best dqsien dly found for B1: ( 0, 14, 10)
858 11:56:34.455550 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
859 11:56:34.459079 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
860 11:56:34.459161
861 11:56:34.462312 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
862 11:56:34.465670 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
863 11:56:34.468941 [Gating] SW calibration Done
864 11:56:34.469022 ==
865 11:56:34.472499 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:56:34.475764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:56:34.475846 ==
868 11:56:34.479355 RX Vref Scan: 0
869 11:56:34.479436
870 11:56:34.479500 RX Vref 0 -> 0, step: 1
871 11:56:34.482398
872 11:56:34.482478 RX Delay -130 -> 252, step: 16
873 11:56:34.489446 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
874 11:56:34.492493 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 11:56:34.496306 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 11:56:34.499327 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 11:56:34.502345 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 11:56:34.505809 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 11:56:34.512769 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 11:56:34.515887 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
881 11:56:34.519396 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
882 11:56:34.522490 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 11:56:34.526375 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 11:56:34.532458 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 11:56:34.535634 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
886 11:56:34.539278 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
887 11:56:34.542510 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 11:56:34.549321 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
889 11:56:34.549403 ==
890 11:56:34.552494 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:56:34.555679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:56:34.555760 ==
893 11:56:34.555824 DQS Delay:
894 11:56:34.559451 DQS0 = 0, DQS1 = 0
895 11:56:34.559532 DQM Delay:
896 11:56:34.562408 DQM0 = 89, DQM1 = 84
897 11:56:34.562488 DQ Delay:
898 11:56:34.566350 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
899 11:56:34.569393 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
900 11:56:34.572667 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
901 11:56:34.576256 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
902 11:56:34.576337
903 11:56:34.576400
904 11:56:34.576459 ==
905 11:56:34.579409 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:56:34.582865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:56:34.582947 ==
908 11:56:34.583010
909 11:56:34.583069
910 11:56:34.586061 TX Vref Scan disable
911 11:56:34.589107 == TX Byte 0 ==
912 11:56:34.592817 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 11:56:34.595899 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 11:56:34.599401 == TX Byte 1 ==
915 11:56:34.602607 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
916 11:56:34.606103 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
917 11:56:34.606185 ==
918 11:56:34.609364 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:56:34.612943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:56:34.615699 ==
921 11:56:34.627288 TX Vref=22, minBit 12, minWin=26, winSum=444
922 11:56:34.630991 TX Vref=24, minBit 10, minWin=27, winSum=451
923 11:56:34.634101 TX Vref=26, minBit 8, minWin=27, winSum=453
924 11:56:34.637330 TX Vref=28, minBit 3, minWin=28, winSum=456
925 11:56:34.641034 TX Vref=30, minBit 8, minWin=28, winSum=461
926 11:56:34.644132 TX Vref=32, minBit 2, minWin=28, winSum=455
927 11:56:34.650855 [TxChooseVref] Worse bit 8, Min win 28, Win sum 461, Final Vref 30
928 11:56:34.650936
929 11:56:34.654662 Final TX Range 1 Vref 30
930 11:56:34.654743
931 11:56:34.654819 ==
932 11:56:34.657774 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:56:34.661489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:56:34.661601 ==
935 11:56:34.661667
936 11:56:34.661725
937 11:56:34.664680 TX Vref Scan disable
938 11:56:34.668059 == TX Byte 0 ==
939 11:56:34.671054 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 11:56:34.674922 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 11:56:34.678036 == TX Byte 1 ==
942 11:56:34.681212 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
943 11:56:34.684561 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
944 11:56:34.684678
945 11:56:34.688209 [DATLAT]
946 11:56:34.688290 Freq=800, CH0 RK0
947 11:56:34.688353
948 11:56:34.691601 DATLAT Default: 0xa
949 11:56:34.691681 0, 0xFFFF, sum = 0
950 11:56:34.694598 1, 0xFFFF, sum = 0
951 11:56:34.694713 2, 0xFFFF, sum = 0
952 11:56:34.698151 3, 0xFFFF, sum = 0
953 11:56:34.698234 4, 0xFFFF, sum = 0
954 11:56:34.701707 5, 0xFFFF, sum = 0
955 11:56:34.701790 6, 0xFFFF, sum = 0
956 11:56:34.704699 7, 0xFFFF, sum = 0
957 11:56:34.704781 8, 0xFFFF, sum = 0
958 11:56:34.708195 9, 0x0, sum = 1
959 11:56:34.708277 10, 0x0, sum = 2
960 11:56:34.711740 11, 0x0, sum = 3
961 11:56:34.711822 12, 0x0, sum = 4
962 11:56:34.715021 best_step = 10
963 11:56:34.715101
964 11:56:34.715165 ==
965 11:56:34.718068 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:56:34.721202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:56:34.721288 ==
968 11:56:34.724599 RX Vref Scan: 1
969 11:56:34.724713
970 11:56:34.724777 Set Vref Range= 32 -> 127
971 11:56:34.724836
972 11:56:34.728096 RX Vref 32 -> 127, step: 1
973 11:56:34.728202
974 11:56:34.731382 RX Delay -95 -> 252, step: 8
975 11:56:34.731464
976 11:56:34.735175 Set Vref, RX VrefLevel [Byte0]: 32
977 11:56:34.738027 [Byte1]: 32
978 11:56:34.738107
979 11:56:34.741659 Set Vref, RX VrefLevel [Byte0]: 33
980 11:56:34.744722 [Byte1]: 33
981 11:56:34.744806
982 11:56:34.747954 Set Vref, RX VrefLevel [Byte0]: 34
983 11:56:34.751699 [Byte1]: 34
984 11:56:34.755363
985 11:56:34.755443 Set Vref, RX VrefLevel [Byte0]: 35
986 11:56:34.758544 [Byte1]: 35
987 11:56:34.762883
988 11:56:34.762963 Set Vref, RX VrefLevel [Byte0]: 36
989 11:56:34.766680 [Byte1]: 36
990 11:56:34.771036
991 11:56:34.771117 Set Vref, RX VrefLevel [Byte0]: 37
992 11:56:34.774752 [Byte1]: 37
993 11:56:34.779187
994 11:56:34.779267 Set Vref, RX VrefLevel [Byte0]: 38
995 11:56:34.782229 [Byte1]: 38
996 11:56:34.786025
997 11:56:34.786106 Set Vref, RX VrefLevel [Byte0]: 39
998 11:56:34.789673 [Byte1]: 39
999 11:56:34.793392
1000 11:56:34.793488 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:56:34.796928 [Byte1]: 40
1002 11:56:34.801482
1003 11:56:34.801564 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:56:34.804587 [Byte1]: 41
1005 11:56:34.808894
1006 11:56:34.808979 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:56:34.812184 [Byte1]: 42
1008 11:56:34.816507
1009 11:56:34.816588 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:56:34.819666 [Byte1]: 43
1011 11:56:34.823975
1012 11:56:34.824056 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:56:34.827726 [Byte1]: 44
1014 11:56:34.831449
1015 11:56:34.831530 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:56:34.834891 [Byte1]: 45
1017 11:56:34.839384
1018 11:56:34.839464 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:56:34.842504 [Byte1]: 46
1020 11:56:34.846785
1021 11:56:34.846866 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:56:34.850010 [Byte1]: 47
1023 11:56:34.854411
1024 11:56:34.854491 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:56:34.857519 [Byte1]: 48
1026 11:56:34.861796
1027 11:56:34.861901 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:56:34.865071 [Byte1]: 49
1029 11:56:34.869459
1030 11:56:34.869589 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:56:34.872598 [Byte1]: 50
1032 11:56:34.876993
1033 11:56:34.877075 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:56:34.880470 [Byte1]: 51
1035 11:56:34.884859
1036 11:56:34.884963 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:56:34.888070 [Byte1]: 52
1038 11:56:34.892447
1039 11:56:34.892526 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:56:34.895588 [Byte1]: 53
1041 11:56:34.899749
1042 11:56:34.899828 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:56:34.903483 [Byte1]: 54
1044 11:56:34.907524
1045 11:56:34.907602 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:56:34.910938 [Byte1]: 55
1047 11:56:34.915486
1048 11:56:34.915565 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:56:34.918273 [Byte1]: 56
1050 11:56:34.922888
1051 11:56:34.922967 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:56:34.925739 [Byte1]: 57
1053 11:56:34.930498
1054 11:56:34.930576 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:56:34.933452 [Byte1]: 58
1056 11:56:34.937822
1057 11:56:34.937901 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:56:34.941472 [Byte1]: 59
1059 11:56:34.945769
1060 11:56:34.945847 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:56:34.948903 [Byte1]: 60
1062 11:56:34.953178
1063 11:56:34.953256 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:56:34.956137 [Byte1]: 61
1065 11:56:34.960590
1066 11:56:34.960668 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:56:34.963758 [Byte1]: 62
1068 11:56:34.968277
1069 11:56:34.968357 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:56:34.971464 [Byte1]: 63
1071 11:56:34.975678
1072 11:56:34.975754 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:56:34.979330 [Byte1]: 64
1074 11:56:34.983455
1075 11:56:34.983553 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:56:34.986658 [Byte1]: 65
1077 11:56:34.991040
1078 11:56:34.991118 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:56:34.994441 [Byte1]: 66
1080 11:56:34.998426
1081 11:56:34.998506 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:56:35.001688 [Byte1]: 67
1083 11:56:35.006550
1084 11:56:35.006629 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:56:35.009711 [Byte1]: 68
1086 11:56:35.013884
1087 11:56:35.013963 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:56:35.017681 [Byte1]: 69
1089 11:56:35.021378
1090 11:56:35.021457 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:56:35.024774 [Byte1]: 70
1092 11:56:35.028983
1093 11:56:35.029062 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:56:35.032045 [Byte1]: 71
1095 11:56:35.036500
1096 11:56:35.036611 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:56:35.039849 [Byte1]: 72
1098 11:56:35.044322
1099 11:56:35.044401 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:56:35.047407 [Byte1]: 73
1101 11:56:35.052198
1102 11:56:35.052277 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:56:35.055277 [Byte1]: 74
1104 11:56:35.059495
1105 11:56:35.059574 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:56:35.062763 [Byte1]: 75
1107 11:56:35.066979
1108 11:56:35.067071 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:56:35.070338 [Byte1]: 76
1110 11:56:35.074869
1111 11:56:35.074951 Set Vref, RX VrefLevel [Byte0]: 77
1112 11:56:35.077646 [Byte1]: 77
1113 11:56:35.082486
1114 11:56:35.082569 Set Vref, RX VrefLevel [Byte0]: 78
1115 11:56:35.085355 [Byte1]: 78
1116 11:56:35.090166
1117 11:56:35.090256 Final RX Vref Byte 0 = 57 to rank0
1118 11:56:35.093239 Final RX Vref Byte 1 = 59 to rank0
1119 11:56:35.096610 Final RX Vref Byte 0 = 57 to rank1
1120 11:56:35.099652 Final RX Vref Byte 1 = 59 to rank1==
1121 11:56:35.103490 Dram Type= 6, Freq= 0, CH_0, rank 0
1122 11:56:35.110228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1123 11:56:35.110361 ==
1124 11:56:35.110465 DQS Delay:
1125 11:56:35.110561 DQS0 = 0, DQS1 = 0
1126 11:56:35.113401 DQM Delay:
1127 11:56:35.113547 DQM0 = 92, DQM1 = 85
1128 11:56:35.116885 DQ Delay:
1129 11:56:35.120308 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1130 11:56:35.120476 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1131 11:56:35.123480 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1132 11:56:35.126794 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1133 11:56:35.130569
1134 11:56:35.130801
1135 11:56:35.136903 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1136 11:56:35.140767 CH0 RK0: MR19=606, MR18=4F45
1137 11:56:35.147234 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1138 11:56:35.147685
1139 11:56:35.150558 ----->DramcWriteLeveling(PI) begin...
1140 11:56:35.150993 ==
1141 11:56:35.153739 Dram Type= 6, Freq= 0, CH_0, rank 1
1142 11:56:35.157250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1143 11:56:35.157721 ==
1144 11:56:35.160686 Write leveling (Byte 0): 34 => 34
1145 11:56:35.163747 Write leveling (Byte 1): 28 => 28
1146 11:56:35.167046 DramcWriteLeveling(PI) end<-----
1147 11:56:35.167452
1148 11:56:35.167766 ==
1149 11:56:35.170637 Dram Type= 6, Freq= 0, CH_0, rank 1
1150 11:56:35.173923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1151 11:56:35.174333 ==
1152 11:56:35.217928 [Gating] SW mode calibration
1153 11:56:35.218757 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1154 11:56:35.219158 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1155 11:56:35.219484 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1156 11:56:35.219785 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1157 11:56:35.220073 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1158 11:56:35.220358 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:56:35.220703 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:56:35.220995 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:56:35.261888 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:56:35.262333 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:56:35.262990 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:56:35.263329 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:56:35.263695 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:56:35.263998 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:56:35.264286 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:56:35.264649 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:56:35.264950 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:56:35.265228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:56:35.301711 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:56:35.302216 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:56:35.303119 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1174 11:56:35.303489 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:56:35.303802 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:56:35.304166 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:56:35.304464 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:56:35.304809 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:56:35.305105 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:56:35.307056 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:56:35.310220 0 9 8 | B1->B0 | 2f2f 2b2b | 0 0 | (0 0) (0 0)
1182 11:56:35.313281 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:56:35.316636 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:56:35.320010 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:56:35.326863 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1186 11:56:35.330045 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1187 11:56:35.333516 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1188 11:56:35.340282 0 10 4 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
1189 11:56:35.343867 0 10 8 | B1->B0 | 2525 2828 | 1 1 | (1 0) (0 1)
1190 11:56:35.347631 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:56:35.350968 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:56:35.355147 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:56:35.362529 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 11:56:35.365982 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1195 11:56:35.369803 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 11:56:35.372480 0 11 4 | B1->B0 | 2727 2626 | 0 0 | (0 0) (0 0)
1197 11:56:35.379944 0 11 8 | B1->B0 | 4242 3737 | 0 0 | (1 1) (0 0)
1198 11:56:35.383249 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:56:35.386378 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:56:35.390070 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:56:35.396788 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 11:56:35.400142 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1203 11:56:35.403382 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1204 11:56:35.410138 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 11:56:35.413315 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1206 11:56:35.416721 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:56:35.423019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:56:35.426929 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:56:35.430090 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:56:35.436794 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:56:35.440192 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:56:35.443291 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:56:35.449827 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:56:35.453265 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:56:35.456660 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:56:35.460237 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:56:35.467069 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:56:35.470334 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:56:35.473318 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:56:35.480289 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:56:35.483215 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1222 11:56:35.486832 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 11:56:35.490200 Total UI for P1: 0, mck2ui 16
1224 11:56:35.493955 best dqsien dly found for B0: ( 0, 14, 8)
1225 11:56:35.496762 Total UI for P1: 0, mck2ui 16
1226 11:56:35.500533 best dqsien dly found for B1: ( 0, 14, 8)
1227 11:56:35.503710 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1228 11:56:35.506869 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1229 11:56:35.507295
1230 11:56:35.513598 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1231 11:56:35.516747 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1232 11:56:35.517158 [Gating] SW calibration Done
1233 11:56:35.519906 ==
1234 11:56:35.523790 Dram Type= 6, Freq= 0, CH_0, rank 1
1235 11:56:35.526525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1236 11:56:35.526939 ==
1237 11:56:35.527267 RX Vref Scan: 0
1238 11:56:35.527570
1239 11:56:35.530104 RX Vref 0 -> 0, step: 1
1240 11:56:35.530516
1241 11:56:35.533245 RX Delay -130 -> 252, step: 16
1242 11:56:35.536419 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1243 11:56:35.540153 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1244 11:56:35.543367 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1245 11:56:35.550255 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1246 11:56:35.553303 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1247 11:56:35.557031 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1248 11:56:35.559909 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1249 11:56:35.563328 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1250 11:56:35.569851 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1251 11:56:35.573447 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1252 11:56:35.576773 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1253 11:56:35.580371 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1254 11:56:35.583447 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1255 11:56:35.590390 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1256 11:56:35.593720 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1257 11:56:35.597515 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1258 11:56:35.597976 ==
1259 11:56:35.600138 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:56:35.603972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:56:35.604410 ==
1262 11:56:35.607342 DQS Delay:
1263 11:56:35.607768 DQS0 = 0, DQS1 = 0
1264 11:56:35.610368 DQM Delay:
1265 11:56:35.610774 DQM0 = 91, DQM1 = 82
1266 11:56:35.611096 DQ Delay:
1267 11:56:35.613569 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1268 11:56:35.617171 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1269 11:56:35.620277 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1270 11:56:35.624173 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
1271 11:56:35.624580
1272 11:56:35.624898
1273 11:56:35.625192 ==
1274 11:56:35.626979 Dram Type= 6, Freq= 0, CH_0, rank 1
1275 11:56:35.634149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1276 11:56:35.634583 ==
1277 11:56:35.634910
1278 11:56:35.635206
1279 11:56:35.635491 TX Vref Scan disable
1280 11:56:35.638062 == TX Byte 0 ==
1281 11:56:35.641078 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1282 11:56:35.644780 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1283 11:56:35.648042 == TX Byte 1 ==
1284 11:56:35.651096 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1285 11:56:35.654264 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1286 11:56:35.657940 ==
1287 11:56:35.661047 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 11:56:35.664321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 11:56:35.664732 ==
1290 11:56:35.677354 TX Vref=22, minBit 8, minWin=27, winSum=446
1291 11:56:35.680759 TX Vref=24, minBit 1, minWin=28, winSum=452
1292 11:56:35.684012 TX Vref=26, minBit 11, minWin=27, winSum=456
1293 11:56:35.687718 TX Vref=28, minBit 7, minWin=28, winSum=457
1294 11:56:35.690933 TX Vref=30, minBit 4, minWin=28, winSum=457
1295 11:56:35.694290 TX Vref=32, minBit 2, minWin=28, winSum=453
1296 11:56:35.701014 [TxChooseVref] Worse bit 7, Min win 28, Win sum 457, Final Vref 28
1297 11:56:35.701423
1298 11:56:35.704040 Final TX Range 1 Vref 28
1299 11:56:35.704446
1300 11:56:35.704830 ==
1301 11:56:35.707315 Dram Type= 6, Freq= 0, CH_0, rank 1
1302 11:56:35.711081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1303 11:56:35.711370 ==
1304 11:56:35.711596
1305 11:56:35.714186
1306 11:56:35.714470 TX Vref Scan disable
1307 11:56:35.717267 == TX Byte 0 ==
1308 11:56:35.720892 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1309 11:56:35.724317 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1310 11:56:35.727513 == TX Byte 1 ==
1311 11:56:35.730663 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1312 11:56:35.737718 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1313 11:56:35.738098
1314 11:56:35.738330 [DATLAT]
1315 11:56:35.738542 Freq=800, CH0 RK1
1316 11:56:35.738786
1317 11:56:35.740546 DATLAT Default: 0xa
1318 11:56:35.740922 0, 0xFFFF, sum = 0
1319 11:56:35.744396 1, 0xFFFF, sum = 0
1320 11:56:35.744707 2, 0xFFFF, sum = 0
1321 11:56:35.747430 3, 0xFFFF, sum = 0
1322 11:56:35.750651 4, 0xFFFF, sum = 0
1323 11:56:35.750943 5, 0xFFFF, sum = 0
1324 11:56:35.754340 6, 0xFFFF, sum = 0
1325 11:56:35.754629 7, 0xFFFF, sum = 0
1326 11:56:35.757416 8, 0xFFFF, sum = 0
1327 11:56:35.757730 9, 0x0, sum = 1
1328 11:56:35.757961 10, 0x0, sum = 2
1329 11:56:35.760765 11, 0x0, sum = 3
1330 11:56:35.761054 12, 0x0, sum = 4
1331 11:56:35.764561 best_step = 10
1332 11:56:35.764845
1333 11:56:35.765070 ==
1334 11:56:35.767733 Dram Type= 6, Freq= 0, CH_0, rank 1
1335 11:56:35.770764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1336 11:56:35.771056 ==
1337 11:56:35.774591 RX Vref Scan: 0
1338 11:56:35.774876
1339 11:56:35.775100 RX Vref 0 -> 0, step: 1
1340 11:56:35.775310
1341 11:56:35.777633 RX Delay -79 -> 252, step: 8
1342 11:56:35.784342 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1343 11:56:35.787265 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1344 11:56:35.791101 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1345 11:56:35.794267 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1346 11:56:35.797414 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1347 11:56:35.804241 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1348 11:56:35.807853 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1349 11:56:35.811250 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1350 11:56:35.814257 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1351 11:56:35.817781 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1352 11:56:35.824448 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1353 11:56:35.827785 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1354 11:56:35.831116 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1355 11:56:35.834233 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1356 11:56:35.837771 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1357 11:56:35.844093 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1358 11:56:35.844418 ==
1359 11:56:35.847667 Dram Type= 6, Freq= 0, CH_0, rank 1
1360 11:56:35.851320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1361 11:56:35.851608 ==
1362 11:56:35.851830 DQS Delay:
1363 11:56:35.854509 DQS0 = 0, DQS1 = 0
1364 11:56:35.854861 DQM Delay:
1365 11:56:35.857980 DQM0 = 93, DQM1 = 83
1366 11:56:35.858264 DQ Delay:
1367 11:56:35.861342 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1368 11:56:35.864274 DQ4 =96, DQ5 =88, DQ6 =100, DQ7 =100
1369 11:56:35.867454 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1370 11:56:35.871348 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =88
1371 11:56:35.871635
1372 11:56:35.871858
1373 11:56:35.877478 [DQSOSCAuto] RK1, (LSB)MR18= 0x4617, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
1374 11:56:35.881309 CH0 RK1: MR19=606, MR18=4617
1375 11:56:35.888233 CH0_RK1: MR19=0x606, MR18=0x4617, DQSOSC=392, MR23=63, INC=96, DEC=64
1376 11:56:35.891003 [RxdqsGatingPostProcess] freq 800
1377 11:56:35.897554 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1378 11:56:35.897950 Pre-setting of DQS Precalculation
1379 11:56:35.904493 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1380 11:56:35.904782 ==
1381 11:56:35.907938 Dram Type= 6, Freq= 0, CH_1, rank 0
1382 11:56:35.911379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1383 11:56:35.911668 ==
1384 11:56:35.918229 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1385 11:56:35.924956 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1386 11:56:35.932445 [CA 0] Center 36 (6~67) winsize 62
1387 11:56:35.935715 [CA 1] Center 36 (6~67) winsize 62
1388 11:56:35.939166 [CA 2] Center 35 (4~66) winsize 63
1389 11:56:35.942772 [CA 3] Center 34 (4~65) winsize 62
1390 11:56:35.945628 [CA 4] Center 34 (4~65) winsize 62
1391 11:56:35.948902 [CA 5] Center 34 (4~64) winsize 61
1392 11:56:35.949191
1393 11:56:35.952432 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1394 11:56:35.952732
1395 11:56:35.956628 [CATrainingPosCal] consider 1 rank data
1396 11:56:35.959432 u2DelayCellTimex100 = 270/100 ps
1397 11:56:35.962835 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1398 11:56:35.966476 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1399 11:56:35.972552 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1400 11:56:35.976061 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 11:56:35.979240 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1402 11:56:35.982352 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1403 11:56:35.982644
1404 11:56:35.985875 CA PerBit enable=1, Macro0, CA PI delay=34
1405 11:56:35.986168
1406 11:56:35.989064 [CBTSetCACLKResult] CA Dly = 34
1407 11:56:35.989403 CS Dly: 6 (0~37)
1408 11:56:35.989742 ==
1409 11:56:35.992726 Dram Type= 6, Freq= 0, CH_1, rank 1
1410 11:56:35.999332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1411 11:56:35.999800 ==
1412 11:56:36.002777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1413 11:56:36.009000 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1414 11:56:36.019317 [CA 0] Center 36 (6~67) winsize 62
1415 11:56:36.023236 [CA 1] Center 37 (6~68) winsize 63
1416 11:56:36.026549 [CA 2] Center 35 (5~66) winsize 62
1417 11:56:36.030076 [CA 3] Center 34 (4~65) winsize 62
1418 11:56:36.033851 [CA 4] Center 34 (4~65) winsize 62
1419 11:56:36.037667 [CA 5] Center 34 (4~65) winsize 62
1420 11:56:36.037960
1421 11:56:36.041341 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1422 11:56:36.041672
1423 11:56:36.044735 [CATrainingPosCal] consider 2 rank data
1424 11:56:36.045030 u2DelayCellTimex100 = 270/100 ps
1425 11:56:36.051703 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1426 11:56:36.054589 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1427 11:56:36.057925 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1428 11:56:36.061847 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 11:56:36.065006 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1430 11:56:36.068186 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1431 11:56:36.068747
1432 11:56:36.071559 CA PerBit enable=1, Macro0, CA PI delay=34
1433 11:56:36.071639
1434 11:56:36.074703 [CBTSetCACLKResult] CA Dly = 34
1435 11:56:36.078233 CS Dly: 7 (0~39)
1436 11:56:36.078340
1437 11:56:36.081933 ----->DramcWriteLeveling(PI) begin...
1438 11:56:36.082014 ==
1439 11:56:36.084695 Dram Type= 6, Freq= 0, CH_1, rank 0
1440 11:56:36.087805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1441 11:56:36.087913 ==
1442 11:56:36.091571 Write leveling (Byte 0): 26 => 26
1443 11:56:36.094653 Write leveling (Byte 1): 27 => 27
1444 11:56:36.098103 DramcWriteLeveling(PI) end<-----
1445 11:56:36.098182
1446 11:56:36.098245 ==
1447 11:56:36.101293 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:56:36.104371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:56:36.104446 ==
1450 11:56:36.108182 [Gating] SW mode calibration
1451 11:56:36.114696 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1452 11:56:36.121534 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1453 11:56:36.124616 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1454 11:56:36.128215 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1455 11:56:36.131260 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:56:36.137994 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:56:36.141621 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:56:36.144887 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:56:36.151752 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:56:36.154979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:56:36.157958 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:56:36.164931 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:56:36.168271 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:56:36.171693 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:56:36.178015 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:56:36.181757 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:56:36.184858 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:56:36.191862 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:56:36.194842 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:56:36.198000 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1471 11:56:36.205163 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:56:36.208206 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:56:36.211634 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:56:36.215125 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:56:36.221484 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:56:36.224813 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:56:36.228093 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:56:36.235143 0 9 4 | B1->B0 | 2424 2929 | 0 0 | (0 0) (0 0)
1479 11:56:36.238143 0 9 8 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1480 11:56:36.241985 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:56:36.248757 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:56:36.251729 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:56:36.254877 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1484 11:56:36.261908 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1485 11:56:36.264927 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1486 11:56:36.268591 0 10 4 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 0)
1487 11:56:36.274969 0 10 8 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
1488 11:56:36.278713 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:56:36.281952 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:56:36.288180 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:56:36.291915 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:56:36.295111 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 11:56:36.298189 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 11:56:36.304910 0 11 4 | B1->B0 | 2a2a 3232 | 0 1 | (0 0) (0 0)
1495 11:56:36.308214 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1496 11:56:36.311394 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:56:36.318690 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:56:36.321635 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:56:36.325074 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:56:36.331720 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1501 11:56:36.335406 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 11:56:36.338406 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1503 11:56:36.344999 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1504 11:56:36.348763 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:56:36.352024 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:56:36.358513 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:56:36.361825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:56:36.365254 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:56:36.371743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:56:36.374903 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:56:36.378538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:56:36.382029 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:56:36.388788 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:56:36.391927 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:56:36.394943 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:56:36.401863 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:56:36.405194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1518 11:56:36.409070 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 11:56:36.412001 Total UI for P1: 0, mck2ui 16
1520 11:56:36.415270 best dqsien dly found for B0: ( 0, 14, 0)
1521 11:56:36.418857 Total UI for P1: 0, mck2ui 16
1522 11:56:36.421903 best dqsien dly found for B1: ( 0, 14, 2)
1523 11:56:36.425068 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1524 11:56:36.428727 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1525 11:56:36.428807
1526 11:56:36.431955 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1527 11:56:36.438860 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1528 11:56:36.438967 [Gating] SW calibration Done
1529 11:56:36.439033 ==
1530 11:56:36.442100 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 11:56:36.448655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 11:56:36.448736 ==
1533 11:56:36.448799 RX Vref Scan: 0
1534 11:56:36.448858
1535 11:56:36.451960 RX Vref 0 -> 0, step: 1
1536 11:56:36.452039
1537 11:56:36.455285 RX Delay -130 -> 252, step: 16
1538 11:56:36.458949 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1539 11:56:36.462641 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 11:56:36.465292 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 11:56:36.472138 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 11:56:36.475447 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 11:56:36.478684 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 11:56:36.481913 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1545 11:56:36.485302 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 11:56:36.491875 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1547 11:56:36.495223 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1548 11:56:36.498823 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 11:56:36.501960 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 11:56:36.505221 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1551 11:56:36.511998 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1552 11:56:36.515100 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1553 11:56:36.518790 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1554 11:56:36.518888 ==
1555 11:56:36.522196 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 11:56:36.525702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 11:56:36.525774 ==
1558 11:56:36.528777 DQS Delay:
1559 11:56:36.528878 DQS0 = 0, DQS1 = 0
1560 11:56:36.531816 DQM Delay:
1561 11:56:36.531913 DQM0 = 95, DQM1 = 91
1562 11:56:36.532019 DQ Delay:
1563 11:56:36.535673 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1564 11:56:36.538896 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1565 11:56:36.542092 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1566 11:56:36.545120 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1567 11:56:36.548834
1568 11:56:36.548936
1569 11:56:36.549022 ==
1570 11:56:36.551779 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 11:56:36.555745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 11:56:36.555817 ==
1573 11:56:36.555876
1574 11:56:36.555932
1575 11:56:36.558453 TX Vref Scan disable
1576 11:56:36.558522 == TX Byte 0 ==
1577 11:56:36.565345 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1578 11:56:36.568596 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1579 11:56:36.568704 == TX Byte 1 ==
1580 11:56:36.575335 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1581 11:56:36.578772 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1582 11:56:36.578853 ==
1583 11:56:36.582075 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 11:56:36.585477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 11:56:36.585558 ==
1586 11:56:36.598835 TX Vref=22, minBit 0, minWin=26, winSum=432
1587 11:56:36.602093 TX Vref=24, minBit 0, minWin=26, winSum=435
1588 11:56:36.605381 TX Vref=26, minBit 4, minWin=26, winSum=440
1589 11:56:36.608885 TX Vref=28, minBit 3, minWin=26, winSum=442
1590 11:56:36.612087 TX Vref=30, minBit 0, minWin=26, winSum=440
1591 11:56:36.615437 TX Vref=32, minBit 3, minWin=26, winSum=443
1592 11:56:36.621984 [TxChooseVref] Worse bit 3, Min win 26, Win sum 443, Final Vref 32
1593 11:56:36.622067
1594 11:56:36.625346 Final TX Range 1 Vref 32
1595 11:56:36.625426
1596 11:56:36.625530 ==
1597 11:56:36.628950 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 11:56:36.631951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 11:56:36.632025 ==
1600 11:56:36.632109
1601 11:56:36.632186
1602 11:56:36.635603 TX Vref Scan disable
1603 11:56:36.638753 == TX Byte 0 ==
1604 11:56:36.642359 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 11:56:36.645778 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 11:56:36.648905 == TX Byte 1 ==
1607 11:56:36.652230 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1608 11:56:36.655660 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1609 11:56:36.655738
1610 11:56:36.659161 [DATLAT]
1611 11:56:36.659234 Freq=800, CH1 RK0
1612 11:56:36.659318
1613 11:56:36.661895 DATLAT Default: 0xa
1614 11:56:36.661969 0, 0xFFFF, sum = 0
1615 11:56:36.665708 1, 0xFFFF, sum = 0
1616 11:56:36.665784 2, 0xFFFF, sum = 0
1617 11:56:36.668659 3, 0xFFFF, sum = 0
1618 11:56:36.668733 4, 0xFFFF, sum = 0
1619 11:56:36.672336 5, 0xFFFF, sum = 0
1620 11:56:36.672409 6, 0xFFFF, sum = 0
1621 11:56:36.675434 7, 0xFFFF, sum = 0
1622 11:56:36.675507 8, 0xFFFF, sum = 0
1623 11:56:36.678621 9, 0x0, sum = 1
1624 11:56:36.678695 10, 0x0, sum = 2
1625 11:56:36.682459 11, 0x0, sum = 3
1626 11:56:36.682532 12, 0x0, sum = 4
1627 11:56:36.685525 best_step = 10
1628 11:56:36.685632
1629 11:56:36.685715 ==
1630 11:56:36.688673 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 11:56:36.692277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 11:56:36.692350 ==
1633 11:56:36.695354 RX Vref Scan: 1
1634 11:56:36.695426
1635 11:56:36.695504 Set Vref Range= 32 -> 127
1636 11:56:36.695580
1637 11:56:36.699081 RX Vref 32 -> 127, step: 1
1638 11:56:36.699157
1639 11:56:36.702171 RX Delay -79 -> 252, step: 8
1640 11:56:36.702250
1641 11:56:36.705293 Set Vref, RX VrefLevel [Byte0]: 32
1642 11:56:36.708985 [Byte1]: 32
1643 11:56:36.709062
1644 11:56:36.712426 Set Vref, RX VrefLevel [Byte0]: 33
1645 11:56:36.715470 [Byte1]: 33
1646 11:56:36.719045
1647 11:56:36.719117 Set Vref, RX VrefLevel [Byte0]: 34
1648 11:56:36.722386 [Byte1]: 34
1649 11:56:36.726476
1650 11:56:36.726554 Set Vref, RX VrefLevel [Byte0]: 35
1651 11:56:36.729454 [Byte1]: 35
1652 11:56:36.733980
1653 11:56:36.734056 Set Vref, RX VrefLevel [Byte0]: 36
1654 11:56:36.737673 [Byte1]: 36
1655 11:56:36.741476
1656 11:56:36.741549 Set Vref, RX VrefLevel [Byte0]: 37
1657 11:56:36.745010 [Byte1]: 37
1658 11:56:36.748993
1659 11:56:36.749065 Set Vref, RX VrefLevel [Byte0]: 38
1660 11:56:36.752281 [Byte1]: 38
1661 11:56:36.756364
1662 11:56:36.756438 Set Vref, RX VrefLevel [Byte0]: 39
1663 11:56:36.759669 [Byte1]: 39
1664 11:56:36.764013
1665 11:56:36.764085 Set Vref, RX VrefLevel [Byte0]: 40
1666 11:56:36.767320 [Byte1]: 40
1667 11:56:36.771753
1668 11:56:36.771837 Set Vref, RX VrefLevel [Byte0]: 41
1669 11:56:36.775106 [Byte1]: 41
1670 11:56:36.779300
1671 11:56:36.779375 Set Vref, RX VrefLevel [Byte0]: 42
1672 11:56:36.782623 [Byte1]: 42
1673 11:56:36.786901
1674 11:56:36.786978 Set Vref, RX VrefLevel [Byte0]: 43
1675 11:56:36.789850 [Byte1]: 43
1676 11:56:36.794123
1677 11:56:36.794195 Set Vref, RX VrefLevel [Byte0]: 44
1678 11:56:36.797850 [Byte1]: 44
1679 11:56:36.802126
1680 11:56:36.802203 Set Vref, RX VrefLevel [Byte0]: 45
1681 11:56:36.805467 [Byte1]: 45
1682 11:56:36.809704
1683 11:56:36.809781 Set Vref, RX VrefLevel [Byte0]: 46
1684 11:56:36.812888 [Byte1]: 46
1685 11:56:36.817247
1686 11:56:36.817314 Set Vref, RX VrefLevel [Byte0]: 47
1687 11:56:36.820494 [Byte1]: 47
1688 11:56:36.824777
1689 11:56:36.824848 Set Vref, RX VrefLevel [Byte0]: 48
1690 11:56:36.827935 [Byte1]: 48
1691 11:56:36.832571
1692 11:56:36.832643 Set Vref, RX VrefLevel [Byte0]: 49
1693 11:56:36.835444 [Byte1]: 49
1694 11:56:36.840022
1695 11:56:36.840087 Set Vref, RX VrefLevel [Byte0]: 50
1696 11:56:36.842760 [Byte1]: 50
1697 11:56:36.847062
1698 11:56:36.850108 Set Vref, RX VrefLevel [Byte0]: 51
1699 11:56:36.850175 [Byte1]: 51
1700 11:56:36.855242
1701 11:56:36.855312 Set Vref, RX VrefLevel [Byte0]: 52
1702 11:56:36.858131 [Byte1]: 52
1703 11:56:36.862588
1704 11:56:36.862654 Set Vref, RX VrefLevel [Byte0]: 53
1705 11:56:36.865488 [Byte1]: 53
1706 11:56:36.869814
1707 11:56:36.869887 Set Vref, RX VrefLevel [Byte0]: 54
1708 11:56:36.873224 [Byte1]: 54
1709 11:56:36.877114
1710 11:56:36.877181 Set Vref, RX VrefLevel [Byte0]: 55
1711 11:56:36.880479 [Byte1]: 55
1712 11:56:36.884997
1713 11:56:36.885075 Set Vref, RX VrefLevel [Byte0]: 56
1714 11:56:36.888083 [Byte1]: 56
1715 11:56:36.892230
1716 11:56:36.892298 Set Vref, RX VrefLevel [Byte0]: 57
1717 11:56:36.895565 [Byte1]: 57
1718 11:56:36.899883
1719 11:56:36.899955 Set Vref, RX VrefLevel [Byte0]: 58
1720 11:56:36.903288 [Byte1]: 58
1721 11:56:36.907210
1722 11:56:36.907283 Set Vref, RX VrefLevel [Byte0]: 59
1723 11:56:36.910805 [Byte1]: 59
1724 11:56:36.915022
1725 11:56:36.915092 Set Vref, RX VrefLevel [Byte0]: 60
1726 11:56:36.918047 [Byte1]: 60
1727 11:56:36.922635
1728 11:56:36.922716 Set Vref, RX VrefLevel [Byte0]: 61
1729 11:56:36.925704 [Byte1]: 61
1730 11:56:36.930026
1731 11:56:36.930111 Set Vref, RX VrefLevel [Byte0]: 62
1732 11:56:36.933105 [Byte1]: 62
1733 11:56:36.937466
1734 11:56:36.937533 Set Vref, RX VrefLevel [Byte0]: 63
1735 11:56:36.940625 [Byte1]: 63
1736 11:56:36.945552
1737 11:56:36.945648 Set Vref, RX VrefLevel [Byte0]: 64
1738 11:56:36.948314 [Byte1]: 64
1739 11:56:36.952498
1740 11:56:36.952580 Set Vref, RX VrefLevel [Byte0]: 65
1741 11:56:36.956287 [Byte1]: 65
1742 11:56:36.960616
1743 11:56:36.960689 Set Vref, RX VrefLevel [Byte0]: 66
1744 11:56:36.963667 [Byte1]: 66
1745 11:56:36.968001
1746 11:56:36.968088 Set Vref, RX VrefLevel [Byte0]: 67
1747 11:56:36.971150 [Byte1]: 67
1748 11:56:36.975618
1749 11:56:36.975699 Set Vref, RX VrefLevel [Byte0]: 68
1750 11:56:36.978754 [Byte1]: 68
1751 11:56:36.983396
1752 11:56:36.983466 Set Vref, RX VrefLevel [Byte0]: 69
1753 11:56:36.986669 [Byte1]: 69
1754 11:56:36.990489
1755 11:56:36.990561 Set Vref, RX VrefLevel [Byte0]: 70
1756 11:56:36.994107 [Byte1]: 70
1757 11:56:36.998140
1758 11:56:36.998205 Set Vref, RX VrefLevel [Byte0]: 71
1759 11:56:37.001728 [Byte1]: 71
1760 11:56:37.005842
1761 11:56:37.005923 Set Vref, RX VrefLevel [Byte0]: 72
1762 11:56:37.009224 [Byte1]: 72
1763 11:56:37.013004
1764 11:56:37.013099 Set Vref, RX VrefLevel [Byte0]: 73
1765 11:56:37.016924 [Byte1]: 73
1766 11:56:37.021039
1767 11:56:37.021119 Set Vref, RX VrefLevel [Byte0]: 74
1768 11:56:37.024019 [Byte1]: 74
1769 11:56:37.028745
1770 11:56:37.028823 Set Vref, RX VrefLevel [Byte0]: 75
1771 11:56:37.031683 [Byte1]: 75
1772 11:56:37.035865
1773 11:56:37.035949 Set Vref, RX VrefLevel [Byte0]: 76
1774 11:56:37.038931 [Byte1]: 76
1775 11:56:37.043461
1776 11:56:37.043566 Final RX Vref Byte 0 = 55 to rank0
1777 11:56:37.046595 Final RX Vref Byte 1 = 58 to rank0
1778 11:56:37.050417 Final RX Vref Byte 0 = 55 to rank1
1779 11:56:37.053119 Final RX Vref Byte 1 = 58 to rank1==
1780 11:56:37.056577 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 11:56:37.063546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 11:56:37.063632 ==
1783 11:56:37.063696 DQS Delay:
1784 11:56:37.063755 DQS0 = 0, DQS1 = 0
1785 11:56:37.066528 DQM Delay:
1786 11:56:37.066641 DQM0 = 95, DQM1 = 90
1787 11:56:37.070316 DQ Delay:
1788 11:56:37.073491 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1789 11:56:37.076770 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1790 11:56:37.076863 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
1791 11:56:37.083758 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1792 11:56:37.083833
1793 11:56:37.083894
1794 11:56:37.089968 [DQSOSCAuto] RK0, (LSB)MR18= 0x2a47, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1795 11:56:37.093150 CH1 RK0: MR19=606, MR18=2A47
1796 11:56:37.100052 CH1_RK0: MR19=0x606, MR18=0x2A47, DQSOSC=392, MR23=63, INC=96, DEC=64
1797 11:56:37.100138
1798 11:56:37.103152 ----->DramcWriteLeveling(PI) begin...
1799 11:56:37.103260 ==
1800 11:56:37.106746 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 11:56:37.110194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 11:56:37.110308 ==
1803 11:56:37.113410 Write leveling (Byte 0): 27 => 27
1804 11:56:37.116684 Write leveling (Byte 1): 28 => 28
1805 11:56:37.119930 DramcWriteLeveling(PI) end<-----
1806 11:56:37.120036
1807 11:56:37.120134 ==
1808 11:56:37.123230 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 11:56:37.126591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 11:56:37.126687 ==
1811 11:56:37.129663 [Gating] SW mode calibration
1812 11:56:37.136538 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 11:56:37.143467 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 11:56:37.146408 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1815 11:56:37.149729 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1816 11:56:37.156765 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:56:37.159790 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:56:37.163340 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:56:37.169877 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:56:37.172890 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:56:37.176093 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:56:37.183357 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:56:37.186308 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:56:37.189510 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:56:37.196066 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:56:37.199676 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:56:37.203253 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:56:37.209972 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:56:37.213230 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:56:37.216390 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1831 11:56:37.223010 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1832 11:56:37.226570 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:56:37.229902 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:56:37.236199 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:56:37.239696 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:56:37.243114 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:56:37.246226 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:56:37.253117 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:56:37.256201 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1840 11:56:37.259435 0 9 8 | B1->B0 | 3333 3131 | 1 1 | (0 0) (1 1)
1841 11:56:37.266241 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:56:37.269516 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:56:37.273221 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 11:56:37.279918 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 11:56:37.282834 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 11:56:37.286727 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1847 11:56:37.292846 0 10 4 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 0)
1848 11:56:37.296188 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1849 11:56:37.299938 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:56:37.306644 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:56:37.309687 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:56:37.312888 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 11:56:37.319756 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 11:56:37.323102 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1855 11:56:37.326787 0 11 4 | B1->B0 | 3535 2d2d | 0 0 | (1 1) (0 0)
1856 11:56:37.332866 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
1857 11:56:37.336737 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:56:37.339806 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:56:37.343205 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 11:56:37.349541 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 11:56:37.353450 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 11:56:37.356294 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1863 11:56:37.363037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:56:37.366448 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:56:37.369437 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:56:37.376126 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:56:37.379372 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:56:37.383317 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:56:37.389550 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:56:37.392721 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:56:37.397008 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:56:37.403025 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:56:37.406409 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:56:37.409384 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:56:37.416989 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:56:37.419438 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:56:37.422739 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:56:37.429890 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:56:37.432992 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1880 11:56:37.436717 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 11:56:37.439695 Total UI for P1: 0, mck2ui 16
1882 11:56:37.442787 best dqsien dly found for B0: ( 0, 14, 4)
1883 11:56:37.446573 Total UI for P1: 0, mck2ui 16
1884 11:56:37.449595 best dqsien dly found for B1: ( 0, 14, 4)
1885 11:56:37.452763 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1886 11:56:37.456554 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 11:56:37.456634
1888 11:56:37.459470 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1889 11:56:37.462884 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 11:56:37.466363 [Gating] SW calibration Done
1891 11:56:37.466443 ==
1892 11:56:37.469962 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 11:56:37.472798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 11:56:37.476695 ==
1895 11:56:37.476774 RX Vref Scan: 0
1896 11:56:37.476838
1897 11:56:37.479767 RX Vref 0 -> 0, step: 1
1898 11:56:37.479846
1899 11:56:37.483643 RX Delay -130 -> 252, step: 16
1900 11:56:37.486559 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1901 11:56:37.489753 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1902 11:56:37.492880 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1903 11:56:37.496074 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1904 11:56:37.502924 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1905 11:56:37.506005 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1906 11:56:37.509773 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1907 11:56:37.512889 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1908 11:56:37.516560 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1909 11:56:37.523268 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1910 11:56:37.526439 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1911 11:56:37.529457 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1912 11:56:37.532798 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1913 11:56:37.536521 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1914 11:56:37.543119 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1915 11:56:37.546315 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1916 11:56:37.546395 ==
1917 11:56:37.549545 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 11:56:37.553219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 11:56:37.553299 ==
1920 11:56:37.556216 DQS Delay:
1921 11:56:37.556296 DQS0 = 0, DQS1 = 0
1922 11:56:37.556359 DQM Delay:
1923 11:56:37.559533 DQM0 = 92, DQM1 = 87
1924 11:56:37.559613 DQ Delay:
1925 11:56:37.562923 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1926 11:56:37.566187 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1927 11:56:37.569530 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1928 11:56:37.572847 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =93
1929 11:56:37.572930
1930 11:56:37.572992
1931 11:56:37.573050 ==
1932 11:56:37.576256 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 11:56:37.583088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 11:56:37.583169 ==
1935 11:56:37.583231
1936 11:56:37.583290
1937 11:56:37.583347 TX Vref Scan disable
1938 11:56:37.586813 == TX Byte 0 ==
1939 11:56:37.589778 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1940 11:56:37.593834 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1941 11:56:37.596798 == TX Byte 1 ==
1942 11:56:37.600022 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1943 11:56:37.606727 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1944 11:56:37.606809 ==
1945 11:56:37.609939 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 11:56:37.613103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 11:56:37.613243 ==
1948 11:56:37.625570 TX Vref=22, minBit 2, minWin=26, winSum=438
1949 11:56:37.628979 TX Vref=24, minBit 2, minWin=26, winSum=444
1950 11:56:37.632119 TX Vref=26, minBit 2, minWin=26, winSum=440
1951 11:56:37.635882 TX Vref=28, minBit 1, minWin=27, winSum=453
1952 11:56:37.638952 TX Vref=30, minBit 3, minWin=27, winSum=451
1953 11:56:37.642071 TX Vref=32, minBit 1, minWin=27, winSum=449
1954 11:56:37.648803 [TxChooseVref] Worse bit 1, Min win 27, Win sum 453, Final Vref 28
1955 11:56:37.648905
1956 11:56:37.652493 Final TX Range 1 Vref 28
1957 11:56:37.652593
1958 11:56:37.652666 ==
1959 11:56:37.655616 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 11:56:37.659452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 11:56:37.659554 ==
1962 11:56:37.659647
1963 11:56:37.662294
1964 11:56:37.662370 TX Vref Scan disable
1965 11:56:37.665329 == TX Byte 0 ==
1966 11:56:37.668964 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 11:56:37.672644 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 11:56:37.675438 == TX Byte 1 ==
1969 11:56:37.679078 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 11:56:37.685398 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 11:56:37.685515
1972 11:56:37.685630 [DATLAT]
1973 11:56:37.685720 Freq=800, CH1 RK1
1974 11:56:37.685805
1975 11:56:37.688613 DATLAT Default: 0xa
1976 11:56:37.688728 0, 0xFFFF, sum = 0
1977 11:56:37.692113 1, 0xFFFF, sum = 0
1978 11:56:37.692197 2, 0xFFFF, sum = 0
1979 11:56:37.695092 3, 0xFFFF, sum = 0
1980 11:56:37.698751 4, 0xFFFF, sum = 0
1981 11:56:37.698888 5, 0xFFFF, sum = 0
1982 11:56:37.701958 6, 0xFFFF, sum = 0
1983 11:56:37.702065 7, 0xFFFF, sum = 0
1984 11:56:37.705620 8, 0xFFFF, sum = 0
1985 11:56:37.705725 9, 0x0, sum = 1
1986 11:56:37.708396 10, 0x0, sum = 2
1987 11:56:37.708516 11, 0x0, sum = 3
1988 11:56:37.708606 12, 0x0, sum = 4
1989 11:56:37.711775 best_step = 10
1990 11:56:37.711872
1991 11:56:37.711965 ==
1992 11:56:37.715532 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 11:56:37.718700 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 11:56:37.718782 ==
1995 11:56:37.721884 RX Vref Scan: 0
1996 11:56:37.721953
1997 11:56:37.722012 RX Vref 0 -> 0, step: 1
1998 11:56:37.722108
1999 11:56:37.725095 RX Delay -79 -> 252, step: 8
2000 11:56:37.732099 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2001 11:56:37.735269 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2002 11:56:37.738395 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2003 11:56:37.742154 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2004 11:56:37.745520 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2005 11:56:37.752507 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2006 11:56:37.755399 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2007 11:56:37.758390 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2008 11:56:37.762007 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2009 11:56:37.765831 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2010 11:56:37.771693 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2011 11:56:37.775345 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2012 11:56:37.778916 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2013 11:56:37.781652 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2014 11:56:37.785247 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2015 11:56:37.789115 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2016 11:56:37.792024 ==
2017 11:56:37.795301 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 11:56:37.798598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 11:56:37.798702 ==
2020 11:56:37.798794 DQS Delay:
2021 11:56:37.802228 DQS0 = 0, DQS1 = 0
2022 11:56:37.802326 DQM Delay:
2023 11:56:37.805209 DQM0 = 97, DQM1 = 90
2024 11:56:37.805313 DQ Delay:
2025 11:56:37.808888 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2026 11:56:37.811994 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2027 11:56:37.815386 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2028 11:56:37.819146 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2029 11:56:37.819246
2030 11:56:37.819338
2031 11:56:37.825116 [DQSOSCAuto] RK1, (LSB)MR18= 0x4914, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2032 11:56:37.828563 CH1 RK1: MR19=606, MR18=4914
2033 11:56:37.835116 CH1_RK1: MR19=0x606, MR18=0x4914, DQSOSC=391, MR23=63, INC=96, DEC=64
2034 11:56:37.838608 [RxdqsGatingPostProcess] freq 800
2035 11:56:37.845485 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 11:56:37.845598 Pre-setting of DQS Precalculation
2037 11:56:37.851877 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 11:56:37.858663 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 11:56:37.865501 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 11:56:37.865608
2041 11:56:37.865674
2042 11:56:37.869188 [Calibration Summary] 1600 Mbps
2043 11:56:37.872394 CH 0, Rank 0
2044 11:56:37.872469 SW Impedance : PASS
2045 11:56:37.875336 DUTY Scan : NO K
2046 11:56:37.878930 ZQ Calibration : PASS
2047 11:56:37.879011 Jitter Meter : NO K
2048 11:56:37.881998 CBT Training : PASS
2049 11:56:37.882073 Write leveling : PASS
2050 11:56:37.885159 RX DQS gating : PASS
2051 11:56:37.888587 RX DQ/DQS(RDDQC) : PASS
2052 11:56:37.888687 TX DQ/DQS : PASS
2053 11:56:37.892079 RX DATLAT : PASS
2054 11:56:37.895229 RX DQ/DQS(Engine): PASS
2055 11:56:37.895299 TX OE : NO K
2056 11:56:37.898929 All Pass.
2057 11:56:37.899004
2058 11:56:37.899065 CH 0, Rank 1
2059 11:56:37.902033 SW Impedance : PASS
2060 11:56:37.902135 DUTY Scan : NO K
2061 11:56:37.905282 ZQ Calibration : PASS
2062 11:56:37.908981 Jitter Meter : NO K
2063 11:56:37.909072 CBT Training : PASS
2064 11:56:37.912079 Write leveling : PASS
2065 11:56:37.915209 RX DQS gating : PASS
2066 11:56:37.915311 RX DQ/DQS(RDDQC) : PASS
2067 11:56:37.918221 TX DQ/DQS : PASS
2068 11:56:37.921668 RX DATLAT : PASS
2069 11:56:37.921776 RX DQ/DQS(Engine): PASS
2070 11:56:37.925173 TX OE : NO K
2071 11:56:37.925282 All Pass.
2072 11:56:37.925372
2073 11:56:37.928193 CH 1, Rank 0
2074 11:56:37.928294 SW Impedance : PASS
2075 11:56:37.931972 DUTY Scan : NO K
2076 11:56:37.935201 ZQ Calibration : PASS
2077 11:56:37.935275 Jitter Meter : NO K
2078 11:56:37.938174 CBT Training : PASS
2079 11:56:37.938270 Write leveling : PASS
2080 11:56:37.941826 RX DQS gating : PASS
2081 11:56:37.945248 RX DQ/DQS(RDDQC) : PASS
2082 11:56:37.945323 TX DQ/DQS : PASS
2083 11:56:37.948195 RX DATLAT : PASS
2084 11:56:37.951867 RX DQ/DQS(Engine): PASS
2085 11:56:37.951971 TX OE : NO K
2086 11:56:37.955228 All Pass.
2087 11:56:37.955303
2088 11:56:37.955371 CH 1, Rank 1
2089 11:56:37.958250 SW Impedance : PASS
2090 11:56:37.958352 DUTY Scan : NO K
2091 11:56:37.961860 ZQ Calibration : PASS
2092 11:56:37.964759 Jitter Meter : NO K
2093 11:56:37.964836 CBT Training : PASS
2094 11:56:37.968727 Write leveling : PASS
2095 11:56:37.971466 RX DQS gating : PASS
2096 11:56:37.971566 RX DQ/DQS(RDDQC) : PASS
2097 11:56:37.975273 TX DQ/DQS : PASS
2098 11:56:37.975347 RX DATLAT : PASS
2099 11:56:37.978560 RX DQ/DQS(Engine): PASS
2100 11:56:37.981612 TX OE : NO K
2101 11:56:37.981690 All Pass.
2102 11:56:37.981752
2103 11:56:37.985043 DramC Write-DBI off
2104 11:56:37.985144 PER_BANK_REFRESH: Hybrid Mode
2105 11:56:37.988198 TX_TRACKING: ON
2106 11:56:37.992049 [GetDramInforAfterCalByMRR] Vendor 6.
2107 11:56:37.994963 [GetDramInforAfterCalByMRR] Revision 606.
2108 11:56:37.998510 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 11:56:37.998610 MR0 0x3b3b
2110 11:56:38.002151 MR8 0x5151
2111 11:56:38.005431 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 11:56:38.005534
2113 11:56:38.005674 MR0 0x3b3b
2114 11:56:38.008474 MR8 0x5151
2115 11:56:38.011467 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 11:56:38.011580
2117 11:56:38.018422 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 11:56:38.021481 [FAST_K] Save calibration result to emmc
2119 11:56:38.028436 [FAST_K] Save calibration result to emmc
2120 11:56:38.028538 dram_init: config_dvfs: 1
2121 11:56:38.031684 dramc_set_vcore_voltage set vcore to 662500
2122 11:56:38.034806 Read voltage for 1200, 2
2123 11:56:38.034895 Vio18 = 0
2124 11:56:38.037964 Vcore = 662500
2125 11:56:38.038035 Vdram = 0
2126 11:56:38.038100 Vddq = 0
2127 11:56:38.041623 Vmddr = 0
2128 11:56:38.044858 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 11:56:38.051618 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 11:56:38.051694 MEM_TYPE=3, freq_sel=15
2131 11:56:38.054679 sv_algorithm_assistance_LP4_1600
2132 11:56:38.061418 ============ PULL DRAM RESETB DOWN ============
2133 11:56:38.065041 ========== PULL DRAM RESETB DOWN end =========
2134 11:56:38.068067 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 11:56:38.071503 ===================================
2136 11:56:38.074823 LPDDR4 DRAM CONFIGURATION
2137 11:56:38.077748 ===================================
2138 11:56:38.081269 EX_ROW_EN[0] = 0x0
2139 11:56:38.081372 EX_ROW_EN[1] = 0x0
2140 11:56:38.084773 LP4Y_EN = 0x0
2141 11:56:38.084878 WORK_FSP = 0x0
2142 11:56:38.087700 WL = 0x4
2143 11:56:38.087814 RL = 0x4
2144 11:56:38.091143 BL = 0x2
2145 11:56:38.091259 RPST = 0x0
2146 11:56:38.094667 RD_PRE = 0x0
2147 11:56:38.094779 WR_PRE = 0x1
2148 11:56:38.097886 WR_PST = 0x0
2149 11:56:38.097965 DBI_WR = 0x0
2150 11:56:38.101672 DBI_RD = 0x0
2151 11:56:38.101747 OTF = 0x1
2152 11:56:38.104514 ===================================
2153 11:56:38.107791 ===================================
2154 11:56:38.111153 ANA top config
2155 11:56:38.114862 ===================================
2156 11:56:38.114945 DLL_ASYNC_EN = 0
2157 11:56:38.118209 ALL_SLAVE_EN = 0
2158 11:56:38.121733 NEW_RANK_MODE = 1
2159 11:56:38.124399 DLL_IDLE_MODE = 1
2160 11:56:38.127903 LP45_APHY_COMB_EN = 1
2161 11:56:38.128002 TX_ODT_DIS = 1
2162 11:56:38.131093 NEW_8X_MODE = 1
2163 11:56:38.134913 ===================================
2164 11:56:38.137858 ===================================
2165 11:56:38.141495 data_rate = 2400
2166 11:56:38.144536 CKR = 1
2167 11:56:38.147601 DQ_P2S_RATIO = 8
2168 11:56:38.151508 ===================================
2169 11:56:38.154625 CA_P2S_RATIO = 8
2170 11:56:38.154694 DQ_CA_OPEN = 0
2171 11:56:38.157787 DQ_SEMI_OPEN = 0
2172 11:56:38.160848 CA_SEMI_OPEN = 0
2173 11:56:38.164507 CA_FULL_RATE = 0
2174 11:56:38.167883 DQ_CKDIV4_EN = 0
2175 11:56:38.171160 CA_CKDIV4_EN = 0
2176 11:56:38.171241 CA_PREDIV_EN = 0
2177 11:56:38.174318 PH8_DLY = 17
2178 11:56:38.177827 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 11:56:38.180962 DQ_AAMCK_DIV = 4
2180 11:56:38.184417 CA_AAMCK_DIV = 4
2181 11:56:38.187907 CA_ADMCK_DIV = 4
2182 11:56:38.187980 DQ_TRACK_CA_EN = 0
2183 11:56:38.191051 CA_PICK = 1200
2184 11:56:38.194272 CA_MCKIO = 1200
2185 11:56:38.197440 MCKIO_SEMI = 0
2186 11:56:38.201065 PLL_FREQ = 2366
2187 11:56:38.204463 DQ_UI_PI_RATIO = 32
2188 11:56:38.207453 CA_UI_PI_RATIO = 0
2189 11:56:38.210664 ===================================
2190 11:56:38.214365 ===================================
2191 11:56:38.214446 memory_type:LPDDR4
2192 11:56:38.217714 GP_NUM : 10
2193 11:56:38.221153 SRAM_EN : 1
2194 11:56:38.221232 MD32_EN : 0
2195 11:56:38.224552 ===================================
2196 11:56:38.227672 [ANA_INIT] >>>>>>>>>>>>>>
2197 11:56:38.231204 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 11:56:38.234408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 11:56:38.237547 ===================================
2200 11:56:38.241053 data_rate = 2400,PCW = 0X5b00
2201 11:56:38.244241 ===================================
2202 11:56:38.247429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 11:56:38.250603 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 11:56:38.257313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 11:56:38.260941 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 11:56:38.264137 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 11:56:38.267270 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 11:56:38.270845 [ANA_INIT] flow start
2209 11:56:38.274010 [ANA_INIT] PLL >>>>>>>>
2210 11:56:38.274099 [ANA_INIT] PLL <<<<<<<<
2211 11:56:38.277763 [ANA_INIT] MIDPI >>>>>>>>
2212 11:56:38.280868 [ANA_INIT] MIDPI <<<<<<<<
2213 11:56:38.280946 [ANA_INIT] DLL >>>>>>>>
2214 11:56:38.284034 [ANA_INIT] DLL <<<<<<<<
2215 11:56:38.287402 [ANA_INIT] flow end
2216 11:56:38.290648 ============ LP4 DIFF to SE enter ============
2217 11:56:38.294446 ============ LP4 DIFF to SE exit ============
2218 11:56:38.297127 [ANA_INIT] <<<<<<<<<<<<<
2219 11:56:38.300883 [Flow] Enable top DCM control >>>>>
2220 11:56:38.304002 [Flow] Enable top DCM control <<<<<
2221 11:56:38.307039 Enable DLL master slave shuffle
2222 11:56:38.310910 ==============================================================
2223 11:56:38.313928 Gating Mode config
2224 11:56:38.320940 ==============================================================
2225 11:56:38.321019 Config description:
2226 11:56:38.330631 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 11:56:38.337635 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 11:56:38.340545 SELPH_MODE 0: By rank 1: By Phase
2229 11:56:38.347490 ==============================================================
2230 11:56:38.350696 GAT_TRACK_EN = 1
2231 11:56:38.353939 RX_GATING_MODE = 2
2232 11:56:38.357230 RX_GATING_TRACK_MODE = 2
2233 11:56:38.360328 SELPH_MODE = 1
2234 11:56:38.363707 PICG_EARLY_EN = 1
2235 11:56:38.367397 VALID_LAT_VALUE = 1
2236 11:56:38.371208 ==============================================================
2237 11:56:38.373742 Enter into Gating configuration >>>>
2238 11:56:38.377115 Exit from Gating configuration <<<<
2239 11:56:38.380301 Enter into DVFS_PRE_config >>>>>
2240 11:56:38.393500 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 11:56:38.393606 Exit from DVFS_PRE_config <<<<<
2242 11:56:38.396778 Enter into PICG configuration >>>>
2243 11:56:38.400334 Exit from PICG configuration <<<<
2244 11:56:38.403405 [RX_INPUT] configuration >>>>>
2245 11:56:38.407450 [RX_INPUT] configuration <<<<<
2246 11:56:38.413386 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 11:56:38.416730 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 11:56:38.423255 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 11:56:38.430103 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 11:56:38.437067 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 11:56:38.443584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 11:56:38.447068 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 11:56:38.450540 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 11:56:38.453493 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 11:56:38.460482 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 11:56:38.463745 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 11:56:38.466919 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 11:56:38.470124 ===================================
2259 11:56:38.473271 LPDDR4 DRAM CONFIGURATION
2260 11:56:38.476452 ===================================
2261 11:56:38.476545 EX_ROW_EN[0] = 0x0
2262 11:56:38.480240 EX_ROW_EN[1] = 0x0
2263 11:56:38.483528 LP4Y_EN = 0x0
2264 11:56:38.483620 WORK_FSP = 0x0
2265 11:56:38.486735 WL = 0x4
2266 11:56:38.486835 RL = 0x4
2267 11:56:38.490196 BL = 0x2
2268 11:56:38.490275 RPST = 0x0
2269 11:56:38.493996 RD_PRE = 0x0
2270 11:56:38.494074 WR_PRE = 0x1
2271 11:56:38.496484 WR_PST = 0x0
2272 11:56:38.496592 DBI_WR = 0x0
2273 11:56:38.500399 DBI_RD = 0x0
2274 11:56:38.500528 OTF = 0x1
2275 11:56:38.503437 ===================================
2276 11:56:38.506593 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 11:56:38.513398 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 11:56:38.516507 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 11:56:38.519830 ===================================
2280 11:56:38.523225 LPDDR4 DRAM CONFIGURATION
2281 11:56:38.527249 ===================================
2282 11:56:38.527331 EX_ROW_EN[0] = 0x10
2283 11:56:38.530270 EX_ROW_EN[1] = 0x0
2284 11:56:38.530379 LP4Y_EN = 0x0
2285 11:56:38.533987 WORK_FSP = 0x0
2286 11:56:38.534081 WL = 0x4
2287 11:56:38.536446 RL = 0x4
2288 11:56:38.540049 BL = 0x2
2289 11:56:38.540149 RPST = 0x0
2290 11:56:38.543118 RD_PRE = 0x0
2291 11:56:38.543215 WR_PRE = 0x1
2292 11:56:38.546483 WR_PST = 0x0
2293 11:56:38.546554 DBI_WR = 0x0
2294 11:56:38.549902 DBI_RD = 0x0
2295 11:56:38.549997 OTF = 0x1
2296 11:56:38.553098 ===================================
2297 11:56:38.560221 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 11:56:38.560333 ==
2299 11:56:38.563706 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 11:56:38.566952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 11:56:38.567047 ==
2302 11:56:38.570230 [Duty_Offset_Calibration]
2303 11:56:38.570303 B0:2 B1:1 CA:1
2304 11:56:38.573113
2305 11:56:38.576511 [DutyScan_Calibration_Flow] k_type=0
2306 11:56:38.584691
2307 11:56:38.584787 ==CLK 0==
2308 11:56:38.588120 Final CLK duty delay cell = 0
2309 11:56:38.591202 [0] MAX Duty = 5187%(X100), DQS PI = 24
2310 11:56:38.594450 [0] MIN Duty = 4875%(X100), DQS PI = 0
2311 11:56:38.594522 [0] AVG Duty = 5031%(X100)
2312 11:56:38.597429
2313 11:56:38.601360 CH0 CLK Duty spec in!! Max-Min= 312%
2314 11:56:38.604474 [DutyScan_Calibration_Flow] ====Done====
2315 11:56:38.604582
2316 11:56:38.607441 [DutyScan_Calibration_Flow] k_type=1
2317 11:56:38.622036
2318 11:56:38.622141 ==DQS 0 ==
2319 11:56:38.625710 Final DQS duty delay cell = -4
2320 11:56:38.628612 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2321 11:56:38.632275 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2322 11:56:38.635461 [-4] AVG Duty = 4937%(X100)
2323 11:56:38.635563
2324 11:56:38.635661 ==DQS 1 ==
2325 11:56:38.638765 Final DQS duty delay cell = -4
2326 11:56:38.642319 [-4] MAX Duty = 5000%(X100), DQS PI = 62
2327 11:56:38.645196 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2328 11:56:38.648655 [-4] AVG Duty = 4922%(X100)
2329 11:56:38.648726
2330 11:56:38.652102 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2331 11:56:38.652197
2332 11:56:38.655424 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2333 11:56:38.658609 [DutyScan_Calibration_Flow] ====Done====
2334 11:56:38.658678
2335 11:56:38.662046 [DutyScan_Calibration_Flow] k_type=3
2336 11:56:38.679673
2337 11:56:38.679793 ==DQM 0 ==
2338 11:56:38.682704 Final DQM duty delay cell = 0
2339 11:56:38.685804 [0] MAX Duty = 5156%(X100), DQS PI = 28
2340 11:56:38.689501 [0] MIN Duty = 4875%(X100), DQS PI = 58
2341 11:56:38.692680 [0] AVG Duty = 5015%(X100)
2342 11:56:38.692750
2343 11:56:38.692810 ==DQM 1 ==
2344 11:56:38.695954 Final DQM duty delay cell = 0
2345 11:56:38.699183 [0] MAX Duty = 5093%(X100), DQS PI = 0
2346 11:56:38.702980 [0] MIN Duty = 5031%(X100), DQS PI = 2
2347 11:56:38.703049 [0] AVG Duty = 5062%(X100)
2348 11:56:38.706537
2349 11:56:38.709568 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2350 11:56:38.709693
2351 11:56:38.712438 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2352 11:56:38.716171 [DutyScan_Calibration_Flow] ====Done====
2353 11:56:38.716261
2354 11:56:38.719171 [DutyScan_Calibration_Flow] k_type=2
2355 11:56:38.735747
2356 11:56:38.735863 ==DQ 0 ==
2357 11:56:38.739241 Final DQ duty delay cell = 0
2358 11:56:38.742386 [0] MAX Duty = 5031%(X100), DQS PI = 24
2359 11:56:38.745989 [0] MIN Duty = 4906%(X100), DQS PI = 0
2360 11:56:38.746069 [0] AVG Duty = 4968%(X100)
2361 11:56:38.746132
2362 11:56:38.749215 ==DQ 1 ==
2363 11:56:38.752626 Final DQ duty delay cell = 0
2364 11:56:38.755811 [0] MAX Duty = 5093%(X100), DQS PI = 10
2365 11:56:38.759223 [0] MIN Duty = 4938%(X100), DQS PI = 36
2366 11:56:38.759303 [0] AVG Duty = 5015%(X100)
2367 11:56:38.759367
2368 11:56:38.762240 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2369 11:56:38.762320
2370 11:56:38.769332 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2371 11:56:38.772348 [DutyScan_Calibration_Flow] ====Done====
2372 11:56:38.772428 ==
2373 11:56:38.775882 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 11:56:38.779490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 11:56:38.779577 ==
2376 11:56:38.782225 [Duty_Offset_Calibration]
2377 11:56:38.782305 B0:1 B1:0 CA:0
2378 11:56:38.782370
2379 11:56:38.785868 [DutyScan_Calibration_Flow] k_type=0
2380 11:56:38.795187
2381 11:56:38.795266 ==CLK 0==
2382 11:56:38.798290 Final CLK duty delay cell = -4
2383 11:56:38.801207 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2384 11:56:38.804948 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2385 11:56:38.807707 [-4] AVG Duty = 4969%(X100)
2386 11:56:38.807788
2387 11:56:38.811275 CH1 CLK Duty spec in!! Max-Min= 124%
2388 11:56:38.814675 [DutyScan_Calibration_Flow] ====Done====
2389 11:56:38.814755
2390 11:56:38.817881 [DutyScan_Calibration_Flow] k_type=1
2391 11:56:38.834781
2392 11:56:38.834861 ==DQS 0 ==
2393 11:56:38.838469 Final DQS duty delay cell = 0
2394 11:56:38.841184 [0] MAX Duty = 5094%(X100), DQS PI = 26
2395 11:56:38.844701 [0] MIN Duty = 4875%(X100), DQS PI = 0
2396 11:56:38.844780 [0] AVG Duty = 4984%(X100)
2397 11:56:38.847798
2398 11:56:38.847877 ==DQS 1 ==
2399 11:56:38.851677 Final DQS duty delay cell = 0
2400 11:56:38.854619 [0] MAX Duty = 5218%(X100), DQS PI = 20
2401 11:56:38.858078 [0] MIN Duty = 4969%(X100), DQS PI = 10
2402 11:56:38.858157 [0] AVG Duty = 5093%(X100)
2403 11:56:38.861110
2404 11:56:38.864564 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2405 11:56:38.864643
2406 11:56:38.867991 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2407 11:56:38.871108 [DutyScan_Calibration_Flow] ====Done====
2408 11:56:38.871186
2409 11:56:38.874308 [DutyScan_Calibration_Flow] k_type=3
2410 11:56:38.891314
2411 11:56:38.891395 ==DQM 0 ==
2412 11:56:38.894277 Final DQM duty delay cell = 0
2413 11:56:38.898169 [0] MAX Duty = 5156%(X100), DQS PI = 6
2414 11:56:38.901073 [0] MIN Duty = 5031%(X100), DQS PI = 0
2415 11:56:38.901164 [0] AVG Duty = 5093%(X100)
2416 11:56:38.901227
2417 11:56:38.904931 ==DQM 1 ==
2418 11:56:38.908075 Final DQM duty delay cell = 0
2419 11:56:38.911210 [0] MAX Duty = 5031%(X100), DQS PI = 16
2420 11:56:38.914547 [0] MIN Duty = 4907%(X100), DQS PI = 36
2421 11:56:38.914627 [0] AVG Duty = 4969%(X100)
2422 11:56:38.914690
2423 11:56:38.921266 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2424 11:56:38.921370
2425 11:56:38.924873 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2426 11:56:38.928189 [DutyScan_Calibration_Flow] ====Done====
2427 11:56:38.928271
2428 11:56:38.931369 [DutyScan_Calibration_Flow] k_type=2
2429 11:56:38.946921
2430 11:56:38.947057 ==DQ 0 ==
2431 11:56:38.950425 Final DQ duty delay cell = -4
2432 11:56:38.953453 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2433 11:56:38.956690 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2434 11:56:38.960334 [-4] AVG Duty = 4984%(X100)
2435 11:56:38.960473
2436 11:56:38.960550 ==DQ 1 ==
2437 11:56:38.963260 Final DQ duty delay cell = 0
2438 11:56:38.966801 [0] MAX Duty = 5125%(X100), DQS PI = 20
2439 11:56:38.970370 [0] MIN Duty = 4969%(X100), DQS PI = 12
2440 11:56:38.973610 [0] AVG Duty = 5047%(X100)
2441 11:56:38.973690
2442 11:56:38.976886 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2443 11:56:38.976969
2444 11:56:38.979937 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2445 11:56:38.983084 [DutyScan_Calibration_Flow] ====Done====
2446 11:56:38.986857 nWR fixed to 30
2447 11:56:38.990295 [ModeRegInit_LP4] CH0 RK0
2448 11:56:38.990375 [ModeRegInit_LP4] CH0 RK1
2449 11:56:38.993908 [ModeRegInit_LP4] CH1 RK0
2450 11:56:38.997003 [ModeRegInit_LP4] CH1 RK1
2451 11:56:38.997084 match AC timing 7
2452 11:56:39.003630 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 11:56:39.006721 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 11:56:39.010390 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 11:56:39.016798 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 11:56:39.020605 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 11:56:39.020713 ==
2458 11:56:39.023214 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 11:56:39.026720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 11:56:39.026800 ==
2461 11:56:39.033703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 11:56:39.040439 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 11:56:39.047593 [CA 0] Center 39 (8~70) winsize 63
2464 11:56:39.051054 [CA 1] Center 39 (8~70) winsize 63
2465 11:56:39.053771 [CA 2] Center 35 (5~66) winsize 62
2466 11:56:39.057627 [CA 3] Center 34 (4~65) winsize 62
2467 11:56:39.060326 [CA 4] Center 33 (3~64) winsize 62
2468 11:56:39.063587 [CA 5] Center 32 (3~62) winsize 60
2469 11:56:39.063670
2470 11:56:39.067151 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2471 11:56:39.067231
2472 11:56:39.070866 [CATrainingPosCal] consider 1 rank data
2473 11:56:39.074066 u2DelayCellTimex100 = 270/100 ps
2474 11:56:39.077447 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2475 11:56:39.080560 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2476 11:56:39.087527 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2477 11:56:39.090415 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2478 11:56:39.093819 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2479 11:56:39.097119 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2480 11:56:39.097236
2481 11:56:39.100826 CA PerBit enable=1, Macro0, CA PI delay=32
2482 11:56:39.100924
2483 11:56:39.103819 [CBTSetCACLKResult] CA Dly = 32
2484 11:56:39.103920 CS Dly: 6 (0~37)
2485 11:56:39.107177 ==
2486 11:56:39.107284 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 11:56:39.113815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 11:56:39.113993 ==
2489 11:56:39.117451 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 11:56:39.123494 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2491 11:56:39.133245 [CA 0] Center 38 (8~69) winsize 62
2492 11:56:39.136320 [CA 1] Center 38 (8~69) winsize 62
2493 11:56:39.139497 [CA 2] Center 35 (4~66) winsize 63
2494 11:56:39.143458 [CA 3] Center 34 (4~65) winsize 62
2495 11:56:39.146242 [CA 4] Center 33 (3~63) winsize 61
2496 11:56:39.149881 [CA 5] Center 32 (3~62) winsize 60
2497 11:56:39.149995
2498 11:56:39.153154 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2499 11:56:39.153223
2500 11:56:39.156099 [CATrainingPosCal] consider 2 rank data
2501 11:56:39.159544 u2DelayCellTimex100 = 270/100 ps
2502 11:56:39.162832 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2503 11:56:39.166658 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2504 11:56:39.172962 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2505 11:56:39.176307 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2506 11:56:39.180068 CA4 delay=33 (3~63),Diff = 1 PI (4 cell)
2507 11:56:39.183459 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2508 11:56:39.183541
2509 11:56:39.186346 CA PerBit enable=1, Macro0, CA PI delay=32
2510 11:56:39.186427
2511 11:56:39.190066 [CBTSetCACLKResult] CA Dly = 32
2512 11:56:39.190148 CS Dly: 6 (0~38)
2513 11:56:39.190212
2514 11:56:39.193468 ----->DramcWriteLeveling(PI) begin...
2515 11:56:39.196368 ==
2516 11:56:39.196452 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 11:56:39.203273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 11:56:39.203378 ==
2519 11:56:39.206567 Write leveling (Byte 0): 33 => 33
2520 11:56:39.209605 Write leveling (Byte 1): 28 => 28
2521 11:56:39.209713 DramcWriteLeveling(PI) end<-----
2522 11:56:39.213463
2523 11:56:39.213573 ==
2524 11:56:39.216539 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 11:56:39.219584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 11:56:39.219668 ==
2527 11:56:39.223229 [Gating] SW mode calibration
2528 11:56:39.229640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 11:56:39.233170 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 11:56:39.239631 0 15 0 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
2531 11:56:39.243559 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2532 11:56:39.246625 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:56:39.253041 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:56:39.256662 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 11:56:39.259650 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 11:56:39.266585 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2537 11:56:39.269694 0 15 28 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
2538 11:56:39.273067 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2539 11:56:39.279969 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:56:39.283290 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:56:39.286343 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:56:39.293518 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 11:56:39.296398 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 11:56:39.299739 1 0 24 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
2545 11:56:39.306527 1 0 28 | B1->B0 | 2e2e 4545 | 0 0 | (0 0) (0 0)
2546 11:56:39.309779 1 1 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
2547 11:56:39.312765 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:56:39.316938 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:56:39.323128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:56:39.326920 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 11:56:39.329852 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 11:56:39.336532 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2553 11:56:39.339792 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 11:56:39.343628 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 11:56:39.350243 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:56:39.353449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:56:39.356774 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:56:39.363504 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:56:39.366819 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:56:39.369830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:56:39.376635 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:56:39.379882 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:56:39.383695 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:56:39.386691 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:56:39.393724 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:56:39.396924 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:56:39.400022 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:56:39.406686 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:56:39.410134 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 11:56:39.413247 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 11:56:39.416557 Total UI for P1: 0, mck2ui 16
2572 11:56:39.419856 best dqsien dly found for B0: ( 1, 3, 28)
2573 11:56:39.426607 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2574 11:56:39.429830 Total UI for P1: 0, mck2ui 16
2575 11:56:39.433431 best dqsien dly found for B1: ( 1, 4, 0)
2576 11:56:39.436701 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2577 11:56:39.439628 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2578 11:56:39.439709
2579 11:56:39.443077 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2580 11:56:39.446656 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2581 11:56:39.449965 [Gating] SW calibration Done
2582 11:56:39.450047 ==
2583 11:56:39.453419 Dram Type= 6, Freq= 0, CH_0, rank 0
2584 11:56:39.456306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 11:56:39.456424 ==
2586 11:56:39.459862 RX Vref Scan: 0
2587 11:56:39.459943
2588 11:56:39.460006 RX Vref 0 -> 0, step: 1
2589 11:56:39.460064
2590 11:56:39.463110 RX Delay -40 -> 252, step: 8
2591 11:56:39.466734 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2592 11:56:39.474074 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2593 11:56:39.476814 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2594 11:56:39.480346 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2595 11:56:39.483705 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2596 11:56:39.486868 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2597 11:56:39.493172 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2598 11:56:39.496877 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2599 11:56:39.499962 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2600 11:56:39.503251 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2601 11:56:39.506380 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2602 11:56:39.513150 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2603 11:56:39.516872 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2604 11:56:39.519774 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2605 11:56:39.523128 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2606 11:56:39.526827 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2607 11:56:39.530006 ==
2608 11:56:39.530113 Dram Type= 6, Freq= 0, CH_0, rank 0
2609 11:56:39.536618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2610 11:56:39.536701 ==
2611 11:56:39.536764 DQS Delay:
2612 11:56:39.539621 DQS0 = 0, DQS1 = 0
2613 11:56:39.539702 DQM Delay:
2614 11:56:39.543352 DQM0 = 121, DQM1 = 113
2615 11:56:39.543433 DQ Delay:
2616 11:56:39.546699 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2617 11:56:39.550116 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2618 11:56:39.553116 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2619 11:56:39.556695 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2620 11:56:39.556776
2621 11:56:39.556840
2622 11:56:39.556898 ==
2623 11:56:39.559712 Dram Type= 6, Freq= 0, CH_0, rank 0
2624 11:56:39.563486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2625 11:56:39.566486 ==
2626 11:56:39.566565
2627 11:56:39.566627
2628 11:56:39.566684 TX Vref Scan disable
2629 11:56:39.570227 == TX Byte 0 ==
2630 11:56:39.573443 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2631 11:56:39.576469 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2632 11:56:39.580623 == TX Byte 1 ==
2633 11:56:39.583344 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2634 11:56:39.586956 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2635 11:56:39.587036 ==
2636 11:56:39.590604 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 11:56:39.596930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 11:56:39.597011 ==
2639 11:56:39.607965 TX Vref=22, minBit 0, minWin=25, winSum=413
2640 11:56:39.611709 TX Vref=24, minBit 0, minWin=25, winSum=416
2641 11:56:39.614687 TX Vref=26, minBit 7, minWin=25, winSum=423
2642 11:56:39.617751 TX Vref=28, minBit 0, minWin=26, winSum=427
2643 11:56:39.621299 TX Vref=30, minBit 0, minWin=26, winSum=428
2644 11:56:39.628123 TX Vref=32, minBit 0, minWin=26, winSum=426
2645 11:56:39.631316 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 30
2646 11:56:39.631397
2647 11:56:39.634331 Final TX Range 1 Vref 30
2648 11:56:39.634410
2649 11:56:39.634473 ==
2650 11:56:39.637525 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 11:56:39.641361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 11:56:39.641472 ==
2653 11:56:39.641580
2654 11:56:39.644825
2655 11:56:39.644895 TX Vref Scan disable
2656 11:56:39.647750 == TX Byte 0 ==
2657 11:56:39.651051 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2658 11:56:39.654365 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2659 11:56:39.657817 == TX Byte 1 ==
2660 11:56:39.660926 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2661 11:56:39.664658 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2662 11:56:39.664737
2663 11:56:39.667914 [DATLAT]
2664 11:56:39.668025 Freq=1200, CH0 RK0
2665 11:56:39.668124
2666 11:56:39.671093 DATLAT Default: 0xd
2667 11:56:39.671173 0, 0xFFFF, sum = 0
2668 11:56:39.674440 1, 0xFFFF, sum = 0
2669 11:56:39.674552 2, 0xFFFF, sum = 0
2670 11:56:39.677735 3, 0xFFFF, sum = 0
2671 11:56:39.677842 4, 0xFFFF, sum = 0
2672 11:56:39.681402 5, 0xFFFF, sum = 0
2673 11:56:39.681483 6, 0xFFFF, sum = 0
2674 11:56:39.684463 7, 0xFFFF, sum = 0
2675 11:56:39.687625 8, 0xFFFF, sum = 0
2676 11:56:39.687706 9, 0xFFFF, sum = 0
2677 11:56:39.691344 10, 0xFFFF, sum = 0
2678 11:56:39.691423 11, 0xFFFF, sum = 0
2679 11:56:39.694825 12, 0x0, sum = 1
2680 11:56:39.694906 13, 0x0, sum = 2
2681 11:56:39.697785 14, 0x0, sum = 3
2682 11:56:39.697865 15, 0x0, sum = 4
2683 11:56:39.697928 best_step = 13
2684 11:56:39.697987
2685 11:56:39.700732 ==
2686 11:56:39.704763 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 11:56:39.707507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 11:56:39.707612 ==
2689 11:56:39.707700 RX Vref Scan: 1
2690 11:56:39.707785
2691 11:56:39.711323 Set Vref Range= 32 -> 127
2692 11:56:39.711431
2693 11:56:39.714401 RX Vref 32 -> 127, step: 1
2694 11:56:39.714480
2695 11:56:39.717705 RX Delay -13 -> 252, step: 4
2696 11:56:39.717785
2697 11:56:39.720902 Set Vref, RX VrefLevel [Byte0]: 32
2698 11:56:39.724521 [Byte1]: 32
2699 11:56:39.724600
2700 11:56:39.727541 Set Vref, RX VrefLevel [Byte0]: 33
2701 11:56:39.730745 [Byte1]: 33
2702 11:56:39.730817
2703 11:56:39.734496 Set Vref, RX VrefLevel [Byte0]: 34
2704 11:56:39.737741 [Byte1]: 34
2705 11:56:39.742012
2706 11:56:39.742091 Set Vref, RX VrefLevel [Byte0]: 35
2707 11:56:39.745006 [Byte1]: 35
2708 11:56:39.749887
2709 11:56:39.749966 Set Vref, RX VrefLevel [Byte0]: 36
2710 11:56:39.752977 [Byte1]: 36
2711 11:56:39.757807
2712 11:56:39.757885 Set Vref, RX VrefLevel [Byte0]: 37
2713 11:56:39.761317 [Byte1]: 37
2714 11:56:39.765709
2715 11:56:39.765787 Set Vref, RX VrefLevel [Byte0]: 38
2716 11:56:39.768846 [Byte1]: 38
2717 11:56:39.773531
2718 11:56:39.773643 Set Vref, RX VrefLevel [Byte0]: 39
2719 11:56:39.776817 [Byte1]: 39
2720 11:56:39.781494
2721 11:56:39.781617 Set Vref, RX VrefLevel [Byte0]: 40
2722 11:56:39.784845 [Byte1]: 40
2723 11:56:39.789323
2724 11:56:39.789401 Set Vref, RX VrefLevel [Byte0]: 41
2725 11:56:39.792638 [Byte1]: 41
2726 11:56:39.797479
2727 11:56:39.797558 Set Vref, RX VrefLevel [Byte0]: 42
2728 11:56:39.800591 [Byte1]: 42
2729 11:56:39.805201
2730 11:56:39.805281 Set Vref, RX VrefLevel [Byte0]: 43
2731 11:56:39.808878 [Byte1]: 43
2732 11:56:39.812860
2733 11:56:39.812939 Set Vref, RX VrefLevel [Byte0]: 44
2734 11:56:39.816518 [Byte1]: 44
2735 11:56:39.821023
2736 11:56:39.821102 Set Vref, RX VrefLevel [Byte0]: 45
2737 11:56:39.824441 [Byte1]: 45
2738 11:56:39.828704
2739 11:56:39.828798 Set Vref, RX VrefLevel [Byte0]: 46
2740 11:56:39.831783 [Byte1]: 46
2741 11:56:39.836809
2742 11:56:39.836887 Set Vref, RX VrefLevel [Byte0]: 47
2743 11:56:39.839924 [Byte1]: 47
2744 11:56:39.844912
2745 11:56:39.844990 Set Vref, RX VrefLevel [Byte0]: 48
2746 11:56:39.848037 [Byte1]: 48
2747 11:56:39.852201
2748 11:56:39.852305 Set Vref, RX VrefLevel [Byte0]: 49
2749 11:56:39.855866 [Byte1]: 49
2750 11:56:39.860178
2751 11:56:39.860289 Set Vref, RX VrefLevel [Byte0]: 50
2752 11:56:39.863322 [Byte1]: 50
2753 11:56:39.868540
2754 11:56:39.868639 Set Vref, RX VrefLevel [Byte0]: 51
2755 11:56:39.871421 [Byte1]: 51
2756 11:56:39.875898
2757 11:56:39.875992 Set Vref, RX VrefLevel [Byte0]: 52
2758 11:56:39.879392 [Byte1]: 52
2759 11:56:39.884286
2760 11:56:39.884381 Set Vref, RX VrefLevel [Byte0]: 53
2761 11:56:39.887263 [Byte1]: 53
2762 11:56:39.892121
2763 11:56:39.892221 Set Vref, RX VrefLevel [Byte0]: 54
2764 11:56:39.894852 [Byte1]: 54
2765 11:56:39.899691
2766 11:56:39.899790 Set Vref, RX VrefLevel [Byte0]: 55
2767 11:56:39.903336 [Byte1]: 55
2768 11:56:39.907582
2769 11:56:39.907662 Set Vref, RX VrefLevel [Byte0]: 56
2770 11:56:39.911355 [Byte1]: 56
2771 11:56:39.915180
2772 11:56:39.915259 Set Vref, RX VrefLevel [Byte0]: 57
2773 11:56:39.918599 [Byte1]: 57
2774 11:56:39.923473
2775 11:56:39.923553 Set Vref, RX VrefLevel [Byte0]: 58
2776 11:56:39.926649 [Byte1]: 58
2777 11:56:39.931529
2778 11:56:39.931608 Set Vref, RX VrefLevel [Byte0]: 59
2779 11:56:39.934356 [Byte1]: 59
2780 11:56:39.939363
2781 11:56:39.939443 Set Vref, RX VrefLevel [Byte0]: 60
2782 11:56:39.942473 [Byte1]: 60
2783 11:56:39.946979
2784 11:56:39.947058 Set Vref, RX VrefLevel [Byte0]: 61
2785 11:56:39.953281 [Byte1]: 61
2786 11:56:39.953361
2787 11:56:39.956806 Set Vref, RX VrefLevel [Byte0]: 62
2788 11:56:39.960080 [Byte1]: 62
2789 11:56:39.960160
2790 11:56:39.963408 Set Vref, RX VrefLevel [Byte0]: 63
2791 11:56:39.966794 [Byte1]: 63
2792 11:56:39.970540
2793 11:56:39.970620 Set Vref, RX VrefLevel [Byte0]: 64
2794 11:56:39.974293 [Byte1]: 64
2795 11:56:39.978453
2796 11:56:39.978533 Set Vref, RX VrefLevel [Byte0]: 65
2797 11:56:39.981934 [Byte1]: 65
2798 11:56:39.986668
2799 11:56:39.986748 Set Vref, RX VrefLevel [Byte0]: 66
2800 11:56:39.990081 [Byte1]: 66
2801 11:56:39.994453
2802 11:56:39.994533 Set Vref, RX VrefLevel [Byte0]: 67
2803 11:56:39.997458 [Byte1]: 67
2804 11:56:40.002239
2805 11:56:40.002319 Set Vref, RX VrefLevel [Byte0]: 68
2806 11:56:40.005867 [Byte1]: 68
2807 11:56:40.010306
2808 11:56:40.010387 Set Vref, RX VrefLevel [Byte0]: 69
2809 11:56:40.013330 [Byte1]: 69
2810 11:56:40.018038
2811 11:56:40.018118 Final RX Vref Byte 0 = 61 to rank0
2812 11:56:40.021091 Final RX Vref Byte 1 = 50 to rank0
2813 11:56:40.024468 Final RX Vref Byte 0 = 61 to rank1
2814 11:56:40.027843 Final RX Vref Byte 1 = 50 to rank1==
2815 11:56:40.031516 Dram Type= 6, Freq= 0, CH_0, rank 0
2816 11:56:40.038469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2817 11:56:40.038551 ==
2818 11:56:40.038614 DQS Delay:
2819 11:56:40.038673 DQS0 = 0, DQS1 = 0
2820 11:56:40.041481 DQM Delay:
2821 11:56:40.041609 DQM0 = 121, DQM1 = 112
2822 11:56:40.044462 DQ Delay:
2823 11:56:40.048269 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =120
2824 11:56:40.051417 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
2825 11:56:40.054628 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2826 11:56:40.058449 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2827 11:56:40.058530
2828 11:56:40.058593
2829 11:56:40.065273 [DQSOSCAuto] RK0, (LSB)MR18= 0x140e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 402 ps
2830 11:56:40.068417 CH0 RK0: MR19=404, MR18=140E
2831 11:56:40.074992 CH0_RK0: MR19=0x404, MR18=0x140E, DQSOSC=402, MR23=63, INC=40, DEC=27
2832 11:56:40.075073
2833 11:56:40.078825 ----->DramcWriteLeveling(PI) begin...
2834 11:56:40.078906 ==
2835 11:56:40.081864 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 11:56:40.085073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 11:56:40.085155 ==
2838 11:56:40.088329 Write leveling (Byte 0): 32 => 32
2839 11:56:40.092206 Write leveling (Byte 1): 30 => 30
2840 11:56:40.095276 DramcWriteLeveling(PI) end<-----
2841 11:56:40.095356
2842 11:56:40.095418 ==
2843 11:56:40.098417 Dram Type= 6, Freq= 0, CH_0, rank 1
2844 11:56:40.101506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2845 11:56:40.105050 ==
2846 11:56:40.105130 [Gating] SW mode calibration
2847 11:56:40.114999 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2848 11:56:40.118614 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2849 11:56:40.121756 0 15 0 | B1->B0 | 3333 2f2f | 1 1 | (1 1) (1 1)
2850 11:56:40.128369 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2851 11:56:40.131548 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2852 11:56:40.135428 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 11:56:40.141495 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:56:40.144967 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:56:40.148433 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:56:40.155411 0 15 28 | B1->B0 | 3131 3030 | 0 0 | (1 0) (1 0)
2857 11:56:40.158431 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2858 11:56:40.161448 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2859 11:56:40.168308 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2860 11:56:40.172164 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 11:56:40.175124 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:56:40.181918 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:56:40.184962 1 0 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
2864 11:56:40.188620 1 0 28 | B1->B0 | 3535 3737 | 1 1 | (0 0) (0 0)
2865 11:56:40.192418 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 11:56:40.198532 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 11:56:40.202125 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2868 11:56:40.205099 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 11:56:40.212174 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:56:40.215205 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:56:40.218330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:56:40.225150 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2873 11:56:40.228976 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:56:40.232037 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:56:40.238731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:56:40.242160 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:56:40.245464 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:56:40.252027 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:56:40.255475 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:56:40.258447 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:56:40.265315 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:56:40.268872 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:56:40.271895 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:56:40.275569 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:56:40.282082 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:56:40.285298 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:56:40.288433 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:56:40.295170 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2889 11:56:40.298858 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2890 11:56:40.302324 Total UI for P1: 0, mck2ui 16
2891 11:56:40.305851 best dqsien dly found for B1: ( 1, 3, 28)
2892 11:56:40.308909 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2893 11:56:40.312518 Total UI for P1: 0, mck2ui 16
2894 11:56:40.315257 best dqsien dly found for B0: ( 1, 3, 30)
2895 11:56:40.319078 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2896 11:56:40.322022 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2897 11:56:40.322103
2898 11:56:40.325627 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2899 11:56:40.332025 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2900 11:56:40.332106 [Gating] SW calibration Done
2901 11:56:40.332169 ==
2902 11:56:40.335933 Dram Type= 6, Freq= 0, CH_0, rank 1
2903 11:56:40.342246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2904 11:56:40.342326 ==
2905 11:56:40.342389 RX Vref Scan: 0
2906 11:56:40.342447
2907 11:56:40.346025 RX Vref 0 -> 0, step: 1
2908 11:56:40.346104
2909 11:56:40.349042 RX Delay -40 -> 252, step: 8
2910 11:56:40.352476 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2911 11:56:40.355545 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2912 11:56:40.359387 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2913 11:56:40.362375 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2914 11:56:40.369295 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
2915 11:56:40.372474 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2916 11:56:40.375921 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2917 11:56:40.379407 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2918 11:56:40.382573 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2919 11:56:40.389131 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2920 11:56:40.392610 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2921 11:56:40.395942 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2922 11:56:40.399178 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2923 11:56:40.402298 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2924 11:56:40.409005 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2925 11:56:40.413051 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2926 11:56:40.413157 ==
2927 11:56:40.416100 Dram Type= 6, Freq= 0, CH_0, rank 1
2928 11:56:40.419623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2929 11:56:40.419702 ==
2930 11:56:40.422377 DQS Delay:
2931 11:56:40.422447 DQS0 = 0, DQS1 = 0
2932 11:56:40.422517 DQM Delay:
2933 11:56:40.426264 DQM0 = 122, DQM1 = 113
2934 11:56:40.426333 DQ Delay:
2935 11:56:40.429247 DQ0 =119, DQ1 =123, DQ2 =123, DQ3 =119
2936 11:56:40.432421 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2937 11:56:40.436217 DQ8 =99, DQ9 =103, DQ10 =115, DQ11 =107
2938 11:56:40.442607 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2939 11:56:40.442706
2940 11:56:40.442801
2941 11:56:40.442888 ==
2942 11:56:40.445723 Dram Type= 6, Freq= 0, CH_0, rank 1
2943 11:56:40.449523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2944 11:56:40.449642 ==
2945 11:56:40.449706
2946 11:56:40.449764
2947 11:56:40.452649 TX Vref Scan disable
2948 11:56:40.452729 == TX Byte 0 ==
2949 11:56:40.459448 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2950 11:56:40.462596 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2951 11:56:40.462676 == TX Byte 1 ==
2952 11:56:40.469187 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2953 11:56:40.472785 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2954 11:56:40.472865 ==
2955 11:56:40.475806 Dram Type= 6, Freq= 0, CH_0, rank 1
2956 11:56:40.479313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2957 11:56:40.479394 ==
2958 11:56:40.492258 TX Vref=22, minBit 1, minWin=25, winSum=416
2959 11:56:40.495514 TX Vref=24, minBit 1, minWin=25, winSum=419
2960 11:56:40.498731 TX Vref=26, minBit 3, minWin=25, winSum=423
2961 11:56:40.502294 TX Vref=28, minBit 3, minWin=25, winSum=427
2962 11:56:40.505293 TX Vref=30, minBit 5, minWin=26, winSum=432
2963 11:56:40.508582 TX Vref=32, minBit 0, minWin=26, winSum=428
2964 11:56:40.515138 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 30
2965 11:56:40.515219
2966 11:56:40.518554 Final TX Range 1 Vref 30
2967 11:56:40.518634
2968 11:56:40.518697 ==
2969 11:56:40.521987 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 11:56:40.525826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 11:56:40.525909 ==
2972 11:56:40.525997
2973 11:56:40.528501
2974 11:56:40.528580 TX Vref Scan disable
2975 11:56:40.531987 == TX Byte 0 ==
2976 11:56:40.535092 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2977 11:56:40.538661 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2978 11:56:40.542375 == TX Byte 1 ==
2979 11:56:40.545404 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2980 11:56:40.548606 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2981 11:56:40.548686
2982 11:56:40.552465 [DATLAT]
2983 11:56:40.552545 Freq=1200, CH0 RK1
2984 11:56:40.552608
2985 11:56:40.555623 DATLAT Default: 0xd
2986 11:56:40.555703 0, 0xFFFF, sum = 0
2987 11:56:40.558742 1, 0xFFFF, sum = 0
2988 11:56:40.558822 2, 0xFFFF, sum = 0
2989 11:56:40.561801 3, 0xFFFF, sum = 0
2990 11:56:40.561883 4, 0xFFFF, sum = 0
2991 11:56:40.565622 5, 0xFFFF, sum = 0
2992 11:56:40.565702 6, 0xFFFF, sum = 0
2993 11:56:40.569056 7, 0xFFFF, sum = 0
2994 11:56:40.569136 8, 0xFFFF, sum = 0
2995 11:56:40.572022 9, 0xFFFF, sum = 0
2996 11:56:40.575514 10, 0xFFFF, sum = 0
2997 11:56:40.575596 11, 0xFFFF, sum = 0
2998 11:56:40.578574 12, 0x0, sum = 1
2999 11:56:40.578654 13, 0x0, sum = 2
3000 11:56:40.578719 14, 0x0, sum = 3
3001 11:56:40.582135 15, 0x0, sum = 4
3002 11:56:40.582206 best_step = 13
3003 11:56:40.582266
3004 11:56:40.582322 ==
3005 11:56:40.585852 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 11:56:40.592267 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 11:56:40.592367 ==
3008 11:56:40.592464 RX Vref Scan: 0
3009 11:56:40.592579
3010 11:56:40.595491 RX Vref 0 -> 0, step: 1
3011 11:56:40.595589
3012 11:56:40.599041 RX Delay -13 -> 252, step: 4
3013 11:56:40.602171 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3014 11:56:40.605380 iDelay=195, Bit 1, Center 122 (59 ~ 186) 128
3015 11:56:40.612173 iDelay=195, Bit 2, Center 116 (51 ~ 182) 132
3016 11:56:40.615499 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3017 11:56:40.618695 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3018 11:56:40.622271 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3019 11:56:40.625434 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3020 11:56:40.632344 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3021 11:56:40.635827 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3022 11:56:40.638763 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3023 11:56:40.642255 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3024 11:56:40.645779 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3025 11:56:40.649231 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3026 11:56:40.655716 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3027 11:56:40.659766 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3028 11:56:40.662474 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3029 11:56:40.662554 ==
3030 11:56:40.665566 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 11:56:40.668797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 11:56:40.672430 ==
3033 11:56:40.672509 DQS Delay:
3034 11:56:40.672578 DQS0 = 0, DQS1 = 0
3035 11:56:40.675403 DQM Delay:
3036 11:56:40.675483 DQM0 = 121, DQM1 = 111
3037 11:56:40.679111 DQ Delay:
3038 11:56:40.682197 DQ0 =120, DQ1 =122, DQ2 =116, DQ3 =118
3039 11:56:40.685496 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3040 11:56:40.688933 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =104
3041 11:56:40.692569 DQ12 =116, DQ13 =118, DQ14 =122, DQ15 =120
3042 11:56:40.692648
3043 11:56:40.692710
3044 11:56:40.698968 [DQSOSCAuto] RK1, (LSB)MR18= 0xdee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps
3045 11:56:40.702570 CH0 RK1: MR19=403, MR18=DEE
3046 11:56:40.709279 CH0_RK1: MR19=0x403, MR18=0xDEE, DQSOSC=405, MR23=63, INC=39, DEC=26
3047 11:56:40.712376 [RxdqsGatingPostProcess] freq 1200
3048 11:56:40.716073 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3049 11:56:40.719031 best DQS0 dly(2T, 0.5T) = (0, 11)
3050 11:56:40.722203 best DQS1 dly(2T, 0.5T) = (0, 12)
3051 11:56:40.725930 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3052 11:56:40.729246 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3053 11:56:40.732977 best DQS0 dly(2T, 0.5T) = (0, 11)
3054 11:56:40.735602 best DQS1 dly(2T, 0.5T) = (0, 11)
3055 11:56:40.739273 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3056 11:56:40.742529 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3057 11:56:40.745788 Pre-setting of DQS Precalculation
3058 11:56:40.749242 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3059 11:56:40.749322 ==
3060 11:56:40.752606 Dram Type= 6, Freq= 0, CH_1, rank 0
3061 11:56:40.759015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3062 11:56:40.759094 ==
3063 11:56:40.762564 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3064 11:56:40.769360 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3065 11:56:40.777996 [CA 0] Center 37 (7~68) winsize 62
3066 11:56:40.781543 [CA 1] Center 37 (7~68) winsize 62
3067 11:56:40.784521 [CA 2] Center 35 (5~65) winsize 61
3068 11:56:40.787739 [CA 3] Center 34 (4~64) winsize 61
3069 11:56:40.791423 [CA 4] Center 34 (4~64) winsize 61
3070 11:56:40.794910 [CA 5] Center 33 (4~63) winsize 60
3071 11:56:40.795000
3072 11:56:40.798366 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3073 11:56:40.798454
3074 11:56:40.801170 [CATrainingPosCal] consider 1 rank data
3075 11:56:40.804732 u2DelayCellTimex100 = 270/100 ps
3076 11:56:40.808228 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3077 11:56:40.811850 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3078 11:56:40.814925 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3079 11:56:40.821353 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3080 11:56:40.825113 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3081 11:56:40.828311 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3082 11:56:40.828392
3083 11:56:40.831395 CA PerBit enable=1, Macro0, CA PI delay=33
3084 11:56:40.831474
3085 11:56:40.834929 [CBTSetCACLKResult] CA Dly = 33
3086 11:56:40.835009 CS Dly: 7 (0~38)
3087 11:56:40.835074 ==
3088 11:56:40.837970 Dram Type= 6, Freq= 0, CH_1, rank 1
3089 11:56:40.844470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3090 11:56:40.844552 ==
3091 11:56:40.848322 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3092 11:56:40.855036 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3093 11:56:40.863485 [CA 0] Center 37 (7~68) winsize 62
3094 11:56:40.866879 [CA 1] Center 38 (8~68) winsize 61
3095 11:56:40.870129 [CA 2] Center 35 (5~65) winsize 61
3096 11:56:40.873908 [CA 3] Center 34 (4~65) winsize 62
3097 11:56:40.877057 [CA 4] Center 34 (4~65) winsize 62
3098 11:56:40.880309 [CA 5] Center 33 (3~63) winsize 61
3099 11:56:40.880388
3100 11:56:40.883791 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3101 11:56:40.883871
3102 11:56:40.886784 [CATrainingPosCal] consider 2 rank data
3103 11:56:40.890672 u2DelayCellTimex100 = 270/100 ps
3104 11:56:40.893568 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3105 11:56:40.896724 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3106 11:56:40.903564 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3107 11:56:40.907007 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3108 11:56:40.910375 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3109 11:56:40.913724 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3110 11:56:40.913825
3111 11:56:40.916698 CA PerBit enable=1, Macro0, CA PI delay=33
3112 11:56:40.916767
3113 11:56:40.920146 [CBTSetCACLKResult] CA Dly = 33
3114 11:56:40.920213 CS Dly: 8 (0~41)
3115 11:56:40.920272
3116 11:56:40.923344 ----->DramcWriteLeveling(PI) begin...
3117 11:56:40.926951 ==
3118 11:56:40.927026 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 11:56:40.933770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 11:56:40.933846 ==
3121 11:56:40.936935 Write leveling (Byte 0): 27 => 27
3122 11:56:40.939991 Write leveling (Byte 1): 27 => 27
3123 11:56:40.943479 DramcWriteLeveling(PI) end<-----
3124 11:56:40.943548
3125 11:56:40.943606 ==
3126 11:56:40.947290 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 11:56:40.950308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 11:56:40.950410 ==
3129 11:56:40.953670 [Gating] SW mode calibration
3130 11:56:40.960228 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3131 11:56:40.963860 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3132 11:56:40.970176 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 11:56:40.973857 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 11:56:40.976732 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 11:56:40.983632 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:56:40.986969 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:56:40.990511 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:56:40.996859 0 15 24 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 0)
3139 11:56:41.000533 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3140 11:56:41.003623 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 11:56:41.010175 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 11:56:41.013745 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 11:56:41.016906 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:56:41.023853 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:56:41.026942 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:56:41.030638 1 0 24 | B1->B0 | 3434 3d3d | 0 0 | (0 0) (0 0)
3147 11:56:41.033892 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 11:56:41.040724 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 11:56:41.043558 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 11:56:41.047407 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 11:56:41.053872 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:56:41.057360 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:56:41.060447 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:56:41.067007 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3155 11:56:41.070181 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3156 11:56:41.073467 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:56:41.080338 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:56:41.083550 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:56:41.087474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:56:41.093495 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:56:41.097129 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:56:41.100462 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:56:41.106967 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:56:41.110412 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:56:41.113434 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:56:41.120513 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:56:41.123446 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:56:41.127191 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:56:41.130456 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:56:41.137146 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3171 11:56:41.140299 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3172 11:56:41.143709 Total UI for P1: 0, mck2ui 16
3173 11:56:41.147031 best dqsien dly found for B0: ( 1, 3, 24)
3174 11:56:41.150209 Total UI for P1: 0, mck2ui 16
3175 11:56:41.153568 best dqsien dly found for B1: ( 1, 3, 24)
3176 11:56:41.157253 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3177 11:56:41.160476 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3178 11:56:41.160557
3179 11:56:41.163797 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3180 11:56:41.166778 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3181 11:56:41.169966 [Gating] SW calibration Done
3182 11:56:41.170081 ==
3183 11:56:41.173560 Dram Type= 6, Freq= 0, CH_1, rank 0
3184 11:56:41.180436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3185 11:56:41.180517 ==
3186 11:56:41.180580 RX Vref Scan: 0
3187 11:56:41.180639
3188 11:56:41.183060 RX Vref 0 -> 0, step: 1
3189 11:56:41.183165
3190 11:56:41.186605 RX Delay -40 -> 252, step: 8
3191 11:56:41.189917 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3192 11:56:41.193653 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3193 11:56:41.196793 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3194 11:56:41.203264 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3195 11:56:41.206747 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3196 11:56:41.210099 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3197 11:56:41.213276 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3198 11:56:41.216723 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3199 11:56:41.219984 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3200 11:56:41.227057 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3201 11:56:41.230412 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3202 11:56:41.233439 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3203 11:56:41.236586 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3204 11:56:41.243627 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3205 11:56:41.246979 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3206 11:56:41.250430 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3207 11:56:41.250510 ==
3208 11:56:41.253255 Dram Type= 6, Freq= 0, CH_1, rank 0
3209 11:56:41.256719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3210 11:56:41.256799 ==
3211 11:56:41.260023 DQS Delay:
3212 11:56:41.260102 DQS0 = 0, DQS1 = 0
3213 11:56:41.260164 DQM Delay:
3214 11:56:41.263341 DQM0 = 120, DQM1 = 116
3215 11:56:41.263420 DQ Delay:
3216 11:56:41.267133 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3217 11:56:41.270007 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3218 11:56:41.276447 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3219 11:56:41.280193 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3220 11:56:41.280272
3221 11:56:41.280334
3222 11:56:41.280391 ==
3223 11:56:41.283173 Dram Type= 6, Freq= 0, CH_1, rank 0
3224 11:56:41.286991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3225 11:56:41.287071 ==
3226 11:56:41.287134
3227 11:56:41.287191
3228 11:56:41.289947 TX Vref Scan disable
3229 11:56:41.290026 == TX Byte 0 ==
3230 11:56:41.296807 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3231 11:56:41.299829 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3232 11:56:41.299908 == TX Byte 1 ==
3233 11:56:41.306817 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3234 11:56:41.309969 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3235 11:56:41.310070 ==
3236 11:56:41.313208 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 11:56:41.316508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 11:56:41.316580 ==
3239 11:56:41.329277 TX Vref=22, minBit 9, minWin=24, winSum=412
3240 11:56:41.332777 TX Vref=24, minBit 10, minWin=25, winSum=420
3241 11:56:41.336150 TX Vref=26, minBit 11, minWin=25, winSum=423
3242 11:56:41.339496 TX Vref=28, minBit 9, minWin=25, winSum=424
3243 11:56:41.343005 TX Vref=30, minBit 1, minWin=26, winSum=430
3244 11:56:41.346448 TX Vref=32, minBit 9, minWin=25, winSum=427
3245 11:56:41.352932 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3246 11:56:41.353013
3247 11:56:41.355976 Final TX Range 1 Vref 30
3248 11:56:41.356055
3249 11:56:41.356117 ==
3250 11:56:41.359471 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 11:56:41.363038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 11:56:41.363118 ==
3253 11:56:41.363180
3254 11:56:41.366432
3255 11:56:41.366510 TX Vref Scan disable
3256 11:56:41.369463 == TX Byte 0 ==
3257 11:56:41.372862 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3258 11:56:41.376015 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3259 11:56:41.379740 == TX Byte 1 ==
3260 11:56:41.382787 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3261 11:56:41.386421 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3262 11:56:41.386500
3263 11:56:41.389880 [DATLAT]
3264 11:56:41.389958 Freq=1200, CH1 RK0
3265 11:56:41.390020
3266 11:56:41.393303 DATLAT Default: 0xd
3267 11:56:41.393382 0, 0xFFFF, sum = 0
3268 11:56:41.396272 1, 0xFFFF, sum = 0
3269 11:56:41.396352 2, 0xFFFF, sum = 0
3270 11:56:41.399504 3, 0xFFFF, sum = 0
3271 11:56:41.399619 4, 0xFFFF, sum = 0
3272 11:56:41.403315 5, 0xFFFF, sum = 0
3273 11:56:41.403421 6, 0xFFFF, sum = 0
3274 11:56:41.406275 7, 0xFFFF, sum = 0
3275 11:56:41.406347 8, 0xFFFF, sum = 0
3276 11:56:41.409468 9, 0xFFFF, sum = 0
3277 11:56:41.409569 10, 0xFFFF, sum = 0
3278 11:56:41.413182 11, 0xFFFF, sum = 0
3279 11:56:41.413253 12, 0x0, sum = 1
3280 11:56:41.416360 13, 0x0, sum = 2
3281 11:56:41.416456 14, 0x0, sum = 3
3282 11:56:41.420122 15, 0x0, sum = 4
3283 11:56:41.420218 best_step = 13
3284 11:56:41.420303
3285 11:56:41.420423 ==
3286 11:56:41.423061 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 11:56:41.430039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 11:56:41.430123 ==
3289 11:56:41.430183 RX Vref Scan: 1
3290 11:56:41.430240
3291 11:56:41.433505 Set Vref Range= 32 -> 127
3292 11:56:41.433571
3293 11:56:41.436847 RX Vref 32 -> 127, step: 1
3294 11:56:41.436946
3295 11:56:41.437033 RX Delay -5 -> 252, step: 4
3296 11:56:41.439832
3297 11:56:41.439929 Set Vref, RX VrefLevel [Byte0]: 32
3298 11:56:41.443100 [Byte1]: 32
3299 11:56:41.447527
3300 11:56:41.447594 Set Vref, RX VrefLevel [Byte0]: 33
3301 11:56:41.450897 [Byte1]: 33
3302 11:56:41.455512
3303 11:56:41.455590 Set Vref, RX VrefLevel [Byte0]: 34
3304 11:56:41.458585 [Byte1]: 34
3305 11:56:41.463532
3306 11:56:41.463610 Set Vref, RX VrefLevel [Byte0]: 35
3307 11:56:41.466909 [Byte1]: 35
3308 11:56:41.471075
3309 11:56:41.471182 Set Vref, RX VrefLevel [Byte0]: 36
3310 11:56:41.474668 [Byte1]: 36
3311 11:56:41.478991
3312 11:56:41.479091 Set Vref, RX VrefLevel [Byte0]: 37
3313 11:56:41.482170 [Byte1]: 37
3314 11:56:41.486622
3315 11:56:41.486726 Set Vref, RX VrefLevel [Byte0]: 38
3316 11:56:41.490164 [Byte1]: 38
3317 11:56:41.494498
3318 11:56:41.494593 Set Vref, RX VrefLevel [Byte0]: 39
3319 11:56:41.498227 [Byte1]: 39
3320 11:56:41.502496
3321 11:56:41.502577 Set Vref, RX VrefLevel [Byte0]: 40
3322 11:56:41.505756 [Byte1]: 40
3323 11:56:41.510172
3324 11:56:41.510275 Set Vref, RX VrefLevel [Byte0]: 41
3325 11:56:41.513886 [Byte1]: 41
3326 11:56:41.518169
3327 11:56:41.518263 Set Vref, RX VrefLevel [Byte0]: 42
3328 11:56:41.521463 [Byte1]: 42
3329 11:56:41.526681
3330 11:56:41.526775 Set Vref, RX VrefLevel [Byte0]: 43
3331 11:56:41.529368 [Byte1]: 43
3332 11:56:41.534497
3333 11:56:41.534575 Set Vref, RX VrefLevel [Byte0]: 44
3334 11:56:41.537114 [Byte1]: 44
3335 11:56:41.541459
3336 11:56:41.541539 Set Vref, RX VrefLevel [Byte0]: 45
3337 11:56:41.545116 [Byte1]: 45
3338 11:56:41.549631
3339 11:56:41.549709 Set Vref, RX VrefLevel [Byte0]: 46
3340 11:56:41.552847 [Byte1]: 46
3341 11:56:41.557616
3342 11:56:41.557707 Set Vref, RX VrefLevel [Byte0]: 47
3343 11:56:41.560602 [Byte1]: 47
3344 11:56:41.565545
3345 11:56:41.565627 Set Vref, RX VrefLevel [Byte0]: 48
3346 11:56:41.568697 [Byte1]: 48
3347 11:56:41.572982
3348 11:56:41.573063 Set Vref, RX VrefLevel [Byte0]: 49
3349 11:56:41.576269 [Byte1]: 49
3350 11:56:41.580940
3351 11:56:41.581018 Set Vref, RX VrefLevel [Byte0]: 50
3352 11:56:41.584349 [Byte1]: 50
3353 11:56:41.588775
3354 11:56:41.588879 Set Vref, RX VrefLevel [Byte0]: 51
3355 11:56:41.591909 [Byte1]: 51
3356 11:56:41.596433
3357 11:56:41.596511 Set Vref, RX VrefLevel [Byte0]: 52
3358 11:56:41.600130 [Byte1]: 52
3359 11:56:41.604348
3360 11:56:41.604426 Set Vref, RX VrefLevel [Byte0]: 53
3361 11:56:41.607988 [Byte1]: 53
3362 11:56:41.612415
3363 11:56:41.612494 Set Vref, RX VrefLevel [Byte0]: 54
3364 11:56:41.615531 [Byte1]: 54
3365 11:56:41.620395
3366 11:56:41.620474 Set Vref, RX VrefLevel [Byte0]: 55
3367 11:56:41.623485 [Byte1]: 55
3368 11:56:41.628422
3369 11:56:41.628499 Set Vref, RX VrefLevel [Byte0]: 56
3370 11:56:41.631209 [Byte1]: 56
3371 11:56:41.635999
3372 11:56:41.636077 Set Vref, RX VrefLevel [Byte0]: 57
3373 11:56:41.639748 [Byte1]: 57
3374 11:56:41.643915
3375 11:56:41.643993 Set Vref, RX VrefLevel [Byte0]: 58
3376 11:56:41.647037 [Byte1]: 58
3377 11:56:41.651973
3378 11:56:41.652053 Set Vref, RX VrefLevel [Byte0]: 59
3379 11:56:41.655066 [Byte1]: 59
3380 11:56:41.659754
3381 11:56:41.659834 Set Vref, RX VrefLevel [Byte0]: 60
3382 11:56:41.662822 [Byte1]: 60
3383 11:56:41.667689
3384 11:56:41.667776 Set Vref, RX VrefLevel [Byte0]: 61
3385 11:56:41.670731 [Byte1]: 61
3386 11:56:41.675091
3387 11:56:41.675166 Set Vref, RX VrefLevel [Byte0]: 62
3388 11:56:41.678746 [Byte1]: 62
3389 11:56:41.683046
3390 11:56:41.683124 Set Vref, RX VrefLevel [Byte0]: 63
3391 11:56:41.686293 [Byte1]: 63
3392 11:56:41.690823
3393 11:56:41.690934 Set Vref, RX VrefLevel [Byte0]: 64
3394 11:56:41.694135 [Byte1]: 64
3395 11:56:41.698775
3396 11:56:41.698854 Set Vref, RX VrefLevel [Byte0]: 65
3397 11:56:41.702315 [Byte1]: 65
3398 11:56:41.706636
3399 11:56:41.706715 Set Vref, RX VrefLevel [Byte0]: 66
3400 11:56:41.710173 [Byte1]: 66
3401 11:56:41.714556
3402 11:56:41.714635 Set Vref, RX VrefLevel [Byte0]: 67
3403 11:56:41.717551 [Byte1]: 67
3404 11:56:41.722502
3405 11:56:41.722592 Set Vref, RX VrefLevel [Byte0]: 68
3406 11:56:41.725612 [Byte1]: 68
3407 11:56:41.730627
3408 11:56:41.730706 Set Vref, RX VrefLevel [Byte0]: 69
3409 11:56:41.733573 [Byte1]: 69
3410 11:56:41.737919
3411 11:56:41.738001 Final RX Vref Byte 0 = 55 to rank0
3412 11:56:41.741511 Final RX Vref Byte 1 = 53 to rank0
3413 11:56:41.744753 Final RX Vref Byte 0 = 55 to rank1
3414 11:56:41.748276 Final RX Vref Byte 1 = 53 to rank1==
3415 11:56:41.751297 Dram Type= 6, Freq= 0, CH_1, rank 0
3416 11:56:41.758566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3417 11:56:41.758640 ==
3418 11:56:41.758710 DQS Delay:
3419 11:56:41.758768 DQS0 = 0, DQS1 = 0
3420 11:56:41.761414 DQM Delay:
3421 11:56:41.761506 DQM0 = 120, DQM1 = 117
3422 11:56:41.764516 DQ Delay:
3423 11:56:41.768636 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3424 11:56:41.771591 DQ4 =122, DQ5 =128, DQ6 =128, DQ7 =120
3425 11:56:41.775290 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3426 11:56:41.777853 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3427 11:56:41.777922
3428 11:56:41.777980
3429 11:56:41.784613 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3430 11:56:41.788173 CH1 RK0: MR19=404, MR18=316
3431 11:56:41.794818 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3432 11:56:41.794894
3433 11:56:41.798406 ----->DramcWriteLeveling(PI) begin...
3434 11:56:41.798477 ==
3435 11:56:41.801190 Dram Type= 6, Freq= 0, CH_1, rank 1
3436 11:56:41.804911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3437 11:56:41.805012 ==
3438 11:56:41.808149 Write leveling (Byte 0): 28 => 28
3439 11:56:41.811644 Write leveling (Byte 1): 28 => 28
3440 11:56:41.814998 DramcWriteLeveling(PI) end<-----
3441 11:56:41.815092
3442 11:56:41.815177 ==
3443 11:56:41.818564 Dram Type= 6, Freq= 0, CH_1, rank 1
3444 11:56:41.821637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3445 11:56:41.824880 ==
3446 11:56:41.824948 [Gating] SW mode calibration
3447 11:56:41.834979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3448 11:56:41.838160 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3449 11:56:41.842036 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 11:56:41.848541 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 11:56:41.851558 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 11:56:41.854671 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3453 11:56:41.861491 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3454 11:56:41.864483 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3455 11:56:41.868166 0 15 24 | B1->B0 | 2727 3333 | 0 0 | (1 0) (0 1)
3456 11:56:41.875155 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
3457 11:56:41.878323 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 11:56:41.881472 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 11:56:41.888342 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 11:56:41.891745 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 11:56:41.895213 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3462 11:56:41.898446 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3463 11:56:41.905451 1 0 24 | B1->B0 | 4646 2929 | 0 0 | (0 0) (1 1)
3464 11:56:41.908148 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 11:56:41.911513 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 11:56:41.918368 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 11:56:41.921506 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 11:56:41.925043 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 11:56:41.931330 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3470 11:56:41.935073 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3471 11:56:41.938180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
3472 11:56:41.944903 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3473 11:56:41.948226 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:56:41.951247 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:56:41.958218 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:56:41.961804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:56:41.964488 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:56:41.971228 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 11:56:41.974478 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 11:56:41.978119 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 11:56:41.984465 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 11:56:41.987642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 11:56:41.991416 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 11:56:41.998095 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3485 11:56:42.001121 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3486 11:56:42.004730 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3487 11:56:42.010875 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3488 11:56:42.014194 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3489 11:56:42.017547 Total UI for P1: 0, mck2ui 16
3490 11:56:42.020843 best dqsien dly found for B1: ( 1, 3, 22)
3491 11:56:42.024716 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3492 11:56:42.027476 Total UI for P1: 0, mck2ui 16
3493 11:56:42.030671 best dqsien dly found for B0: ( 1, 3, 26)
3494 11:56:42.034092 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3495 11:56:42.037311 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3496 11:56:42.037430
3497 11:56:42.044046 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3498 11:56:42.047515 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3499 11:56:42.047588 [Gating] SW calibration Done
3500 11:56:42.050964 ==
3501 11:56:42.054152 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 11:56:42.057314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 11:56:42.057409 ==
3504 11:56:42.057505 RX Vref Scan: 0
3505 11:56:42.057627
3506 11:56:42.060398 RX Vref 0 -> 0, step: 1
3507 11:56:42.060477
3508 11:56:42.064065 RX Delay -40 -> 252, step: 8
3509 11:56:42.067334 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3510 11:56:42.070724 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3511 11:56:42.074148 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3512 11:56:42.080714 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3513 11:56:42.083841 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3514 11:56:42.087198 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3515 11:56:42.090620 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3516 11:56:42.093817 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3517 11:56:42.100726 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3518 11:56:42.103807 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3519 11:56:42.107159 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3520 11:56:42.110192 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3521 11:56:42.114153 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3522 11:56:42.120576 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3523 11:56:42.124194 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3524 11:56:42.127377 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3525 11:56:42.127473 ==
3526 11:56:42.130578 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 11:56:42.133800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 11:56:42.136834 ==
3529 11:56:42.136928 DQS Delay:
3530 11:56:42.137014 DQS0 = 0, DQS1 = 0
3531 11:56:42.140655 DQM Delay:
3532 11:56:42.140748 DQM0 = 120, DQM1 = 117
3533 11:56:42.143956 DQ Delay:
3534 11:56:42.147377 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3535 11:56:42.150728 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3536 11:56:42.153897 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3537 11:56:42.157249 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3538 11:56:42.157328
3539 11:56:42.157390
3540 11:56:42.157448 ==
3541 11:56:42.160495 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 11:56:42.163869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 11:56:42.163950 ==
3544 11:56:42.164013
3545 11:56:42.164099
3546 11:56:42.167699 TX Vref Scan disable
3547 11:56:42.170296 == TX Byte 0 ==
3548 11:56:42.173975 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3549 11:56:42.176814 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3550 11:56:42.180430 == TX Byte 1 ==
3551 11:56:42.183864 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3552 11:56:42.187344 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3553 11:56:42.187431 ==
3554 11:56:42.190228 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 11:56:42.196686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 11:56:42.196790 ==
3557 11:56:42.207030 TX Vref=22, minBit 1, minWin=25, winSum=417
3558 11:56:42.210794 TX Vref=24, minBit 0, minWin=26, winSum=422
3559 11:56:42.214013 TX Vref=26, minBit 4, minWin=26, winSum=428
3560 11:56:42.217021 TX Vref=28, minBit 2, minWin=26, winSum=431
3561 11:56:42.220360 TX Vref=30, minBit 6, minWin=26, winSum=431
3562 11:56:42.227128 TX Vref=32, minBit 6, minWin=26, winSum=430
3563 11:56:42.230409 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
3564 11:56:42.230484
3565 11:56:42.233504 Final TX Range 1 Vref 28
3566 11:56:42.233639
3567 11:56:42.233727 ==
3568 11:56:42.237181 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 11:56:42.240365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 11:56:42.240459 ==
3571 11:56:42.243686
3572 11:56:42.243763
3573 11:56:42.243823 TX Vref Scan disable
3574 11:56:42.246748 == TX Byte 0 ==
3575 11:56:42.250445 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3576 11:56:42.253505 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3577 11:56:42.257261 == TX Byte 1 ==
3578 11:56:42.260369 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3579 11:56:42.264091 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3580 11:56:42.264160
3581 11:56:42.266796 [DATLAT]
3582 11:56:42.266871 Freq=1200, CH1 RK1
3583 11:56:42.266929
3584 11:56:42.270554 DATLAT Default: 0xd
3585 11:56:42.270640 0, 0xFFFF, sum = 0
3586 11:56:42.273348 1, 0xFFFF, sum = 0
3587 11:56:42.273444 2, 0xFFFF, sum = 0
3588 11:56:42.276613 3, 0xFFFF, sum = 0
3589 11:56:42.276710 4, 0xFFFF, sum = 0
3590 11:56:42.280452 5, 0xFFFF, sum = 0
3591 11:56:42.280547 6, 0xFFFF, sum = 0
3592 11:56:42.283770 7, 0xFFFF, sum = 0
3593 11:56:42.287188 8, 0xFFFF, sum = 0
3594 11:56:42.287283 9, 0xFFFF, sum = 0
3595 11:56:42.290078 10, 0xFFFF, sum = 0
3596 11:56:42.290147 11, 0xFFFF, sum = 0
3597 11:56:42.293440 12, 0x0, sum = 1
3598 11:56:42.293550 13, 0x0, sum = 2
3599 11:56:42.297363 14, 0x0, sum = 3
3600 11:56:42.297443 15, 0x0, sum = 4
3601 11:56:42.297507 best_step = 13
3602 11:56:42.297565
3603 11:56:42.300402 ==
3604 11:56:42.303794 Dram Type= 6, Freq= 0, CH_1, rank 1
3605 11:56:42.306855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3606 11:56:42.306937 ==
3607 11:56:42.306999 RX Vref Scan: 0
3608 11:56:42.307057
3609 11:56:42.310327 RX Vref 0 -> 0, step: 1
3610 11:56:42.310404
3611 11:56:42.313431 RX Delay -5 -> 252, step: 4
3612 11:56:42.316919 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3613 11:56:42.323591 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3614 11:56:42.326737 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3615 11:56:42.330564 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3616 11:56:42.333756 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3617 11:56:42.337118 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3618 11:56:42.339998 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3619 11:56:42.346797 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3620 11:56:42.350243 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3621 11:56:42.354021 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3622 11:56:42.357054 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3623 11:56:42.363273 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3624 11:56:42.366834 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3625 11:56:42.370043 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3626 11:56:42.373202 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3627 11:56:42.376655 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3628 11:56:42.376736 ==
3629 11:56:42.379736 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 11:56:42.386225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 11:56:42.386297 ==
3632 11:56:42.386371 DQS Delay:
3633 11:56:42.389913 DQS0 = 0, DQS1 = 0
3634 11:56:42.389981 DQM Delay:
3635 11:56:42.393236 DQM0 = 120, DQM1 = 118
3636 11:56:42.393329 DQ Delay:
3637 11:56:42.396498 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3638 11:56:42.399471 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3639 11:56:42.402982 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3640 11:56:42.406086 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3641 11:56:42.406166
3642 11:56:42.406229
3643 11:56:42.416051 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3644 11:56:42.419171 CH1 RK1: MR19=403, MR18=FEC
3645 11:56:42.422714 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3646 11:56:42.425564 [RxdqsGatingPostProcess] freq 1200
3647 11:56:42.432847 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3648 11:56:42.435734 best DQS0 dly(2T, 0.5T) = (0, 11)
3649 11:56:42.439052 best DQS1 dly(2T, 0.5T) = (0, 11)
3650 11:56:42.442764 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3651 11:56:42.445772 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3652 11:56:42.448937 best DQS0 dly(2T, 0.5T) = (0, 11)
3653 11:56:42.452635 best DQS1 dly(2T, 0.5T) = (0, 11)
3654 11:56:42.455737 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3655 11:56:42.458795 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3656 11:56:42.462447 Pre-setting of DQS Precalculation
3657 11:56:42.465694 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3658 11:56:42.472602 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3659 11:56:42.478666 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3660 11:56:42.478746
3661 11:56:42.482442
3662 11:56:42.482520 [Calibration Summary] 2400 Mbps
3663 11:56:42.485710 CH 0, Rank 0
3664 11:56:42.485789 SW Impedance : PASS
3665 11:56:42.488586 DUTY Scan : NO K
3666 11:56:42.492043 ZQ Calibration : PASS
3667 11:56:42.492137 Jitter Meter : NO K
3668 11:56:42.495545 CBT Training : PASS
3669 11:56:42.498535 Write leveling : PASS
3670 11:56:42.498614 RX DQS gating : PASS
3671 11:56:42.501740 RX DQ/DQS(RDDQC) : PASS
3672 11:56:42.505108 TX DQ/DQS : PASS
3673 11:56:42.505207 RX DATLAT : PASS
3674 11:56:42.508502 RX DQ/DQS(Engine): PASS
3675 11:56:42.512119 TX OE : NO K
3676 11:56:42.512193 All Pass.
3677 11:56:42.512263
3678 11:56:42.512323 CH 0, Rank 1
3679 11:56:42.515261 SW Impedance : PASS
3680 11:56:42.518415 DUTY Scan : NO K
3681 11:56:42.518484 ZQ Calibration : PASS
3682 11:56:42.522269 Jitter Meter : NO K
3683 11:56:42.522349 CBT Training : PASS
3684 11:56:42.525409 Write leveling : PASS
3685 11:56:42.528695 RX DQS gating : PASS
3686 11:56:42.528783 RX DQ/DQS(RDDQC) : PASS
3687 11:56:42.532046 TX DQ/DQS : PASS
3688 11:56:42.535221 RX DATLAT : PASS
3689 11:56:42.535299 RX DQ/DQS(Engine): PASS
3690 11:56:42.538598 TX OE : NO K
3691 11:56:42.538677 All Pass.
3692 11:56:42.538753
3693 11:56:42.542053 CH 1, Rank 0
3694 11:56:42.542145 SW Impedance : PASS
3695 11:56:42.545372 DUTY Scan : NO K
3696 11:56:42.548326 ZQ Calibration : PASS
3697 11:56:42.548425 Jitter Meter : NO K
3698 11:56:42.551881 CBT Training : PASS
3699 11:56:42.555093 Write leveling : PASS
3700 11:56:42.555171 RX DQS gating : PASS
3701 11:56:42.558287 RX DQ/DQS(RDDQC) : PASS
3702 11:56:42.561821 TX DQ/DQS : PASS
3703 11:56:42.561901 RX DATLAT : PASS
3704 11:56:42.565193 RX DQ/DQS(Engine): PASS
3705 11:56:42.568328 TX OE : NO K
3706 11:56:42.568434 All Pass.
3707 11:56:42.568533
3708 11:56:42.568620 CH 1, Rank 1
3709 11:56:42.571473 SW Impedance : PASS
3710 11:56:42.575189 DUTY Scan : NO K
3711 11:56:42.575269 ZQ Calibration : PASS
3712 11:56:42.578397 Jitter Meter : NO K
3713 11:56:42.578468 CBT Training : PASS
3714 11:56:42.581370 Write leveling : PASS
3715 11:56:42.585058 RX DQS gating : PASS
3716 11:56:42.585130 RX DQ/DQS(RDDQC) : PASS
3717 11:56:42.588362 TX DQ/DQS : PASS
3718 11:56:42.591329 RX DATLAT : PASS
3719 11:56:42.591408 RX DQ/DQS(Engine): PASS
3720 11:56:42.595044 TX OE : NO K
3721 11:56:42.595124 All Pass.
3722 11:56:42.595186
3723 11:56:42.597826 DramC Write-DBI off
3724 11:56:42.601476 PER_BANK_REFRESH: Hybrid Mode
3725 11:56:42.601594 TX_TRACKING: ON
3726 11:56:42.611244 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3727 11:56:42.614822 [FAST_K] Save calibration result to emmc
3728 11:56:42.617959 dramc_set_vcore_voltage set vcore to 650000
3729 11:56:42.621426 Read voltage for 600, 5
3730 11:56:42.621531 Vio18 = 0
3731 11:56:42.621665 Vcore = 650000
3732 11:56:42.624674 Vdram = 0
3733 11:56:42.624753 Vddq = 0
3734 11:56:42.624815 Vmddr = 0
3735 11:56:42.630956 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3736 11:56:42.634662 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3737 11:56:42.637690 MEM_TYPE=3, freq_sel=19
3738 11:56:42.641270 sv_algorithm_assistance_LP4_1600
3739 11:56:42.644317 ============ PULL DRAM RESETB DOWN ============
3740 11:56:42.651055 ========== PULL DRAM RESETB DOWN end =========
3741 11:56:42.654621 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3742 11:56:42.658036 ===================================
3743 11:56:42.661119 LPDDR4 DRAM CONFIGURATION
3744 11:56:42.664606 ===================================
3745 11:56:42.664686 EX_ROW_EN[0] = 0x0
3746 11:56:42.667852 EX_ROW_EN[1] = 0x0
3747 11:56:42.667930 LP4Y_EN = 0x0
3748 11:56:42.671268 WORK_FSP = 0x0
3749 11:56:42.671356 WL = 0x2
3750 11:56:42.674565 RL = 0x2
3751 11:56:42.674644 BL = 0x2
3752 11:56:42.677784 RPST = 0x0
3753 11:56:42.677863 RD_PRE = 0x0
3754 11:56:42.681306 WR_PRE = 0x1
3755 11:56:42.681400 WR_PST = 0x0
3756 11:56:42.684492 DBI_WR = 0x0
3757 11:56:42.684568 DBI_RD = 0x0
3758 11:56:42.687995 OTF = 0x1
3759 11:56:42.691244 ===================================
3760 11:56:42.694335 ===================================
3761 11:56:42.694413 ANA top config
3762 11:56:42.698026 ===================================
3763 11:56:42.701173 DLL_ASYNC_EN = 0
3764 11:56:42.704263 ALL_SLAVE_EN = 1
3765 11:56:42.707889 NEW_RANK_MODE = 1
3766 11:56:42.707969 DLL_IDLE_MODE = 1
3767 11:56:42.711021 LP45_APHY_COMB_EN = 1
3768 11:56:42.714613 TX_ODT_DIS = 1
3769 11:56:42.717798 NEW_8X_MODE = 1
3770 11:56:42.720808 ===================================
3771 11:56:42.724239 ===================================
3772 11:56:42.727921 data_rate = 1200
3773 11:56:42.728002 CKR = 1
3774 11:56:42.731109 DQ_P2S_RATIO = 8
3775 11:56:42.734194 ===================================
3776 11:56:42.738305 CA_P2S_RATIO = 8
3777 11:56:42.741048 DQ_CA_OPEN = 0
3778 11:56:42.744357 DQ_SEMI_OPEN = 0
3779 11:56:42.747498 CA_SEMI_OPEN = 0
3780 11:56:42.747577 CA_FULL_RATE = 0
3781 11:56:42.751206 DQ_CKDIV4_EN = 1
3782 11:56:42.754132 CA_CKDIV4_EN = 1
3783 11:56:42.757785 CA_PREDIV_EN = 0
3784 11:56:42.760741 PH8_DLY = 0
3785 11:56:42.764379 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3786 11:56:42.764486 DQ_AAMCK_DIV = 4
3787 11:56:42.767603 CA_AAMCK_DIV = 4
3788 11:56:42.770700 CA_ADMCK_DIV = 4
3789 11:56:42.774171 DQ_TRACK_CA_EN = 0
3790 11:56:42.777599 CA_PICK = 600
3791 11:56:42.781313 CA_MCKIO = 600
3792 11:56:42.781383 MCKIO_SEMI = 0
3793 11:56:42.784645 PLL_FREQ = 2288
3794 11:56:42.787703 DQ_UI_PI_RATIO = 32
3795 11:56:42.790910 CA_UI_PI_RATIO = 0
3796 11:56:42.794052 ===================================
3797 11:56:42.797686 ===================================
3798 11:56:42.801171 memory_type:LPDDR4
3799 11:56:42.801268 GP_NUM : 10
3800 11:56:42.804174 SRAM_EN : 1
3801 11:56:42.807448 MD32_EN : 0
3802 11:56:42.810645 ===================================
3803 11:56:42.810743 [ANA_INIT] >>>>>>>>>>>>>>
3804 11:56:42.814279 <<<<<< [CONFIGURE PHASE]: ANA_TX
3805 11:56:42.817293 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3806 11:56:42.820976 ===================================
3807 11:56:42.824031 data_rate = 1200,PCW = 0X5800
3808 11:56:42.827249 ===================================
3809 11:56:42.831303 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3810 11:56:42.836967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3811 11:56:42.840466 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3812 11:56:42.847010 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3813 11:56:42.850684 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3814 11:56:42.853676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3815 11:56:42.857614 [ANA_INIT] flow start
3816 11:56:42.857707 [ANA_INIT] PLL >>>>>>>>
3817 11:56:42.860372 [ANA_INIT] PLL <<<<<<<<
3818 11:56:42.863903 [ANA_INIT] MIDPI >>>>>>>>
3819 11:56:42.863983 [ANA_INIT] MIDPI <<<<<<<<
3820 11:56:42.867488 [ANA_INIT] DLL >>>>>>>>
3821 11:56:42.870734 [ANA_INIT] flow end
3822 11:56:42.873769 ============ LP4 DIFF to SE enter ============
3823 11:56:42.877089 ============ LP4 DIFF to SE exit ============
3824 11:56:42.880797 [ANA_INIT] <<<<<<<<<<<<<
3825 11:56:42.883968 [Flow] Enable top DCM control >>>>>
3826 11:56:42.887116 [Flow] Enable top DCM control <<<<<
3827 11:56:42.890787 Enable DLL master slave shuffle
3828 11:56:42.893928 ==============================================================
3829 11:56:42.897227 Gating Mode config
3830 11:56:42.900808 ==============================================================
3831 11:56:42.904151 Config description:
3832 11:56:42.914042 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3833 11:56:42.920233 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3834 11:56:42.923455 SELPH_MODE 0: By rank 1: By Phase
3835 11:56:42.930553 ==============================================================
3836 11:56:42.933526 GAT_TRACK_EN = 1
3837 11:56:42.937208 RX_GATING_MODE = 2
3838 11:56:42.940665 RX_GATING_TRACK_MODE = 2
3839 11:56:42.944004 SELPH_MODE = 1
3840 11:56:42.947012 PICG_EARLY_EN = 1
3841 11:56:42.947116 VALID_LAT_VALUE = 1
3842 11:56:42.953721 ==============================================================
3843 11:56:42.956722 Enter into Gating configuration >>>>
3844 11:56:42.960566 Exit from Gating configuration <<<<
3845 11:56:42.963479 Enter into DVFS_PRE_config >>>>>
3846 11:56:42.973503 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3847 11:56:42.976972 Exit from DVFS_PRE_config <<<<<
3848 11:56:42.980309 Enter into PICG configuration >>>>
3849 11:56:42.983462 Exit from PICG configuration <<<<
3850 11:56:42.987179 [RX_INPUT] configuration >>>>>
3851 11:56:42.990187 [RX_INPUT] configuration <<<<<
3852 11:56:42.993473 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3853 11:56:43.000087 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3854 11:56:43.006633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 11:56:43.013373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 11:56:43.020106 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3857 11:56:43.026740 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3858 11:56:43.030436 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3859 11:56:43.033481 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3860 11:56:43.036651 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3861 11:56:43.040379 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3862 11:56:43.046641 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3863 11:56:43.049673 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3864 11:56:43.053537 ===================================
3865 11:56:43.056856 LPDDR4 DRAM CONFIGURATION
3866 11:56:43.059739 ===================================
3867 11:56:43.059810 EX_ROW_EN[0] = 0x0
3868 11:56:43.063492 EX_ROW_EN[1] = 0x0
3869 11:56:43.063561 LP4Y_EN = 0x0
3870 11:56:43.066536 WORK_FSP = 0x0
3871 11:56:43.066608 WL = 0x2
3872 11:56:43.070173 RL = 0x2
3873 11:56:43.070242 BL = 0x2
3874 11:56:43.073343 RPST = 0x0
3875 11:56:43.076337 RD_PRE = 0x0
3876 11:56:43.076435 WR_PRE = 0x1
3877 11:56:43.080179 WR_PST = 0x0
3878 11:56:43.080273 DBI_WR = 0x0
3879 11:56:43.083166 DBI_RD = 0x0
3880 11:56:43.083249 OTF = 0x1
3881 11:56:43.086356 ===================================
3882 11:56:43.089966 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3883 11:56:43.096583 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3884 11:56:43.099465 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3885 11:56:43.103430 ===================================
3886 11:56:43.106383 LPDDR4 DRAM CONFIGURATION
3887 11:56:43.109473 ===================================
3888 11:56:43.109567 EX_ROW_EN[0] = 0x10
3889 11:56:43.113154 EX_ROW_EN[1] = 0x0
3890 11:56:43.113252 LP4Y_EN = 0x0
3891 11:56:43.116219 WORK_FSP = 0x0
3892 11:56:43.116321 WL = 0x2
3893 11:56:43.119956 RL = 0x2
3894 11:56:43.120051 BL = 0x2
3895 11:56:43.123242 RPST = 0x0
3896 11:56:43.123311 RD_PRE = 0x0
3897 11:56:43.126573 WR_PRE = 0x1
3898 11:56:43.126641 WR_PST = 0x0
3899 11:56:43.129391 DBI_WR = 0x0
3900 11:56:43.133019 DBI_RD = 0x0
3901 11:56:43.133107 OTF = 0x1
3902 11:56:43.136152 ===================================
3903 11:56:43.143287 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3904 11:56:43.146427 nWR fixed to 30
3905 11:56:43.149854 [ModeRegInit_LP4] CH0 RK0
3906 11:56:43.149924 [ModeRegInit_LP4] CH0 RK1
3907 11:56:43.153322 [ModeRegInit_LP4] CH1 RK0
3908 11:56:43.156460 [ModeRegInit_LP4] CH1 RK1
3909 11:56:43.156561 match AC timing 17
3910 11:56:43.163311 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3911 11:56:43.166412 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3912 11:56:43.169692 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3913 11:56:43.176304 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3914 11:56:43.179694 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3915 11:56:43.179765 ==
3916 11:56:43.183024 Dram Type= 6, Freq= 0, CH_0, rank 0
3917 11:56:43.186653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3918 11:56:43.186726 ==
3919 11:56:43.192908 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3920 11:56:43.199768 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3921 11:56:43.203076 [CA 0] Center 36 (5~67) winsize 63
3922 11:56:43.206164 [CA 1] Center 36 (5~67) winsize 63
3923 11:56:43.209765 [CA 2] Center 33 (3~64) winsize 62
3924 11:56:43.212849 [CA 3] Center 33 (2~64) winsize 63
3925 11:56:43.216270 [CA 4] Center 33 (2~64) winsize 63
3926 11:56:43.219313 [CA 5] Center 32 (2~63) winsize 62
3927 11:56:43.219561
3928 11:56:43.223179 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3929 11:56:43.223259
3930 11:56:43.226338 [CATrainingPosCal] consider 1 rank data
3931 11:56:43.229364 u2DelayCellTimex100 = 270/100 ps
3932 11:56:43.232925 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3933 11:56:43.236288 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3934 11:56:43.239681 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3935 11:56:43.242727 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3936 11:56:43.246715 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3937 11:56:43.249693 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3938 11:56:43.249771
3939 11:56:43.256027 CA PerBit enable=1, Macro0, CA PI delay=32
3940 11:56:43.256107
3941 11:56:43.259387 [CBTSetCACLKResult] CA Dly = 32
3942 11:56:43.259466 CS Dly: 4 (0~35)
3943 11:56:43.259528 ==
3944 11:56:43.263461 Dram Type= 6, Freq= 0, CH_0, rank 1
3945 11:56:43.266450 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3946 11:56:43.266530 ==
3947 11:56:43.273045 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3948 11:56:43.279931 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3949 11:56:43.282482 [CA 0] Center 36 (5~67) winsize 63
3950 11:56:43.286007 [CA 1] Center 35 (5~66) winsize 62
3951 11:56:43.289088 [CA 2] Center 34 (3~65) winsize 63
3952 11:56:43.292791 [CA 3] Center 33 (3~64) winsize 62
3953 11:56:43.295918 [CA 4] Center 33 (2~64) winsize 63
3954 11:56:43.299095 [CA 5] Center 32 (2~63) winsize 62
3955 11:56:43.299191
3956 11:56:43.302405 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3957 11:56:43.302503
3958 11:56:43.306138 [CATrainingPosCal] consider 2 rank data
3959 11:56:43.309276 u2DelayCellTimex100 = 270/100 ps
3960 11:56:43.312973 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3961 11:56:43.316409 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3962 11:56:43.319366 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3963 11:56:43.322648 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3964 11:56:43.325742 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3965 11:56:43.332693 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3966 11:56:43.332796
3967 11:56:43.335742 CA PerBit enable=1, Macro0, CA PI delay=32
3968 11:56:43.335844
3969 11:56:43.339539 [CBTSetCACLKResult] CA Dly = 32
3970 11:56:43.339633 CS Dly: 4 (0~36)
3971 11:56:43.339717
3972 11:56:43.342625 ----->DramcWriteLeveling(PI) begin...
3973 11:56:43.342727 ==
3974 11:56:43.345996 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 11:56:43.352621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 11:56:43.352699 ==
3977 11:56:43.355678 Write leveling (Byte 0): 34 => 34
3978 11:56:43.355773 Write leveling (Byte 1): 33 => 33
3979 11:56:43.359438 DramcWriteLeveling(PI) end<-----
3980 11:56:43.359532
3981 11:56:43.359625 ==
3982 11:56:43.362541 Dram Type= 6, Freq= 0, CH_0, rank 0
3983 11:56:43.369156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3984 11:56:43.369227 ==
3985 11:56:43.372629 [Gating] SW mode calibration
3986 11:56:43.379421 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3987 11:56:43.382243 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3988 11:56:43.389495 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 11:56:43.392137 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3990 11:56:43.395846 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3991 11:56:43.402408 0 9 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
3992 11:56:43.405529 0 9 16 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
3993 11:56:43.408944 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 11:56:43.415510 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 11:56:43.418823 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 11:56:43.422415 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 11:56:43.428798 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3998 11:56:43.432348 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3999 11:56:43.435571 0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
4000 11:56:43.439226 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)
4001 11:56:43.445340 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 11:56:43.448922 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 11:56:43.451955 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 11:56:43.458690 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 11:56:43.461852 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4006 11:56:43.465597 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4007 11:56:43.471983 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4008 11:56:43.475527 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4009 11:56:43.479006 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:56:43.485806 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:56:43.488896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:56:43.492762 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:56:43.498845 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 11:56:43.502289 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 11:56:43.505471 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 11:56:43.512373 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 11:56:43.515252 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 11:56:43.519199 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 11:56:43.522313 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 11:56:43.529342 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 11:56:43.532489 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4022 11:56:43.535460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:56:43.542373 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4024 11:56:43.545440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4025 11:56:43.548530 Total UI for P1: 0, mck2ui 16
4026 11:56:43.552481 best dqsien dly found for B0: ( 0, 13, 12)
4027 11:56:43.555436 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4028 11:56:43.558679 Total UI for P1: 0, mck2ui 16
4029 11:56:43.561904 best dqsien dly found for B1: ( 0, 13, 14)
4030 11:56:43.565444 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4031 11:56:43.568606 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4032 11:56:43.572499
4033 11:56:43.575718 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4034 11:56:43.578785 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4035 11:56:43.581776 [Gating] SW calibration Done
4036 11:56:43.581856 ==
4037 11:56:43.585173 Dram Type= 6, Freq= 0, CH_0, rank 0
4038 11:56:43.588744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4039 11:56:43.588823 ==
4040 11:56:43.588886 RX Vref Scan: 0
4041 11:56:43.588945
4042 11:56:43.592171 RX Vref 0 -> 0, step: 1
4043 11:56:43.592251
4044 11:56:43.595658 RX Delay -230 -> 252, step: 16
4045 11:56:43.598850 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4046 11:56:43.601823 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4047 11:56:43.608491 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4048 11:56:43.612074 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4049 11:56:43.615180 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4050 11:56:43.618314 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4051 11:56:43.625184 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4052 11:56:43.628910 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4053 11:56:43.632036 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4054 11:56:43.635195 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4055 11:56:43.638356 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4056 11:56:43.645403 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4057 11:56:43.648445 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4058 11:56:43.651898 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4059 11:56:43.655067 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4060 11:56:43.661956 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4061 11:56:43.662048 ==
4062 11:56:43.664940 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 11:56:43.668831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 11:56:43.668901 ==
4065 11:56:43.668960 DQS Delay:
4066 11:56:43.671669 DQS0 = 0, DQS1 = 0
4067 11:56:43.671743 DQM Delay:
4068 11:56:43.675414 DQM0 = 52, DQM1 = 46
4069 11:56:43.675483 DQ Delay:
4070 11:56:43.678203 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4071 11:56:43.681525 DQ4 =49, DQ5 =49, DQ6 =57, DQ7 =57
4072 11:56:43.685338 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4073 11:56:43.688334 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4074 11:56:43.688436
4075 11:56:43.688523
4076 11:56:43.688607 ==
4077 11:56:43.691594 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 11:56:43.695206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 11:56:43.695293 ==
4080 11:56:43.698351
4081 11:56:43.698422
4082 11:56:43.698480 TX Vref Scan disable
4083 11:56:43.702063 == TX Byte 0 ==
4084 11:56:43.705169 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4085 11:56:43.708245 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4086 11:56:43.711942 == TX Byte 1 ==
4087 11:56:43.715312 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4088 11:56:43.718624 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4089 11:56:43.721733 ==
4090 11:56:43.721831 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 11:56:43.728145 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 11:56:43.728249 ==
4093 11:56:43.728339
4094 11:56:43.728433
4095 11:56:43.731712 TX Vref Scan disable
4096 11:56:43.731783 == TX Byte 0 ==
4097 11:56:43.738527 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4098 11:56:43.741522 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4099 11:56:43.741631 == TX Byte 1 ==
4100 11:56:43.748650 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4101 11:56:43.751487 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4102 11:56:43.751557
4103 11:56:43.751616 [DATLAT]
4104 11:56:43.755096 Freq=600, CH0 RK0
4105 11:56:43.755165
4106 11:56:43.755223 DATLAT Default: 0x9
4107 11:56:43.758247 0, 0xFFFF, sum = 0
4108 11:56:43.758316 1, 0xFFFF, sum = 0
4109 11:56:43.761498 2, 0xFFFF, sum = 0
4110 11:56:43.761633 3, 0xFFFF, sum = 0
4111 11:56:43.764528 4, 0xFFFF, sum = 0
4112 11:56:43.764623 5, 0xFFFF, sum = 0
4113 11:56:43.767998 6, 0xFFFF, sum = 0
4114 11:56:43.768068 7, 0xFFFF, sum = 0
4115 11:56:43.771306 8, 0x0, sum = 1
4116 11:56:43.771376 9, 0x0, sum = 2
4117 11:56:43.775460 10, 0x0, sum = 3
4118 11:56:43.775533 11, 0x0, sum = 4
4119 11:56:43.778030 best_step = 9
4120 11:56:43.778099
4121 11:56:43.778157 ==
4122 11:56:43.781560 Dram Type= 6, Freq= 0, CH_0, rank 0
4123 11:56:43.784800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4124 11:56:43.784900 ==
4125 11:56:43.788114 RX Vref Scan: 1
4126 11:56:43.788206
4127 11:56:43.788291 RX Vref 0 -> 0, step: 1
4128 11:56:43.788383
4129 11:56:43.791108 RX Delay -163 -> 252, step: 8
4130 11:56:43.791179
4131 11:56:43.794599 Set Vref, RX VrefLevel [Byte0]: 61
4132 11:56:43.798065 [Byte1]: 50
4133 11:56:43.801583
4134 11:56:43.801699 Final RX Vref Byte 0 = 61 to rank0
4135 11:56:43.805089 Final RX Vref Byte 1 = 50 to rank0
4136 11:56:43.808500 Final RX Vref Byte 0 = 61 to rank1
4137 11:56:43.811593 Final RX Vref Byte 1 = 50 to rank1==
4138 11:56:43.815687 Dram Type= 6, Freq= 0, CH_0, rank 0
4139 11:56:43.821418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4140 11:56:43.821498 ==
4141 11:56:43.821560 DQS Delay:
4142 11:56:43.824697 DQS0 = 0, DQS1 = 0
4143 11:56:43.824776 DQM Delay:
4144 11:56:43.824838 DQM0 = 52, DQM1 = 48
4145 11:56:43.828193 DQ Delay:
4146 11:56:43.831591 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4147 11:56:43.835102 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =60
4148 11:56:43.838202 DQ8 =36, DQ9 =36, DQ10 =52, DQ11 =40
4149 11:56:43.841230 DQ12 =56, DQ13 =56, DQ14 =56, DQ15 =52
4150 11:56:43.841309
4151 11:56:43.841371
4152 11:56:43.848208 [DQSOSCAuto] RK0, (LSB)MR18= 0x6e61, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4153 11:56:43.851618 CH0 RK0: MR19=808, MR18=6E61
4154 11:56:43.858239 CH0_RK0: MR19=0x808, MR18=0x6E61, DQSOSC=389, MR23=63, INC=173, DEC=115
4155 11:56:43.858318
4156 11:56:43.861207 ----->DramcWriteLeveling(PI) begin...
4157 11:56:43.861287 ==
4158 11:56:43.864573 Dram Type= 6, Freq= 0, CH_0, rank 1
4159 11:56:43.867646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4160 11:56:43.867753 ==
4161 11:56:43.871361 Write leveling (Byte 0): 35 => 35
4162 11:56:43.874408 Write leveling (Byte 1): 30 => 30
4163 11:56:43.877521 DramcWriteLeveling(PI) end<-----
4164 11:56:43.877657
4165 11:56:43.877722 ==
4166 11:56:43.881005 Dram Type= 6, Freq= 0, CH_0, rank 1
4167 11:56:43.884496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4168 11:56:43.887865 ==
4169 11:56:43.887935 [Gating] SW mode calibration
4170 11:56:43.894259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4171 11:56:43.900868 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4172 11:56:43.904079 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4173 11:56:43.911367 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4174 11:56:43.914244 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 11:56:43.917518 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 11:56:43.924269 0 9 16 | B1->B0 | 2929 2424 | 0 0 | (1 1) (0 0)
4177 11:56:43.927347 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 11:56:43.931047 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 11:56:43.937464 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 11:56:43.941270 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 11:56:43.943923 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 11:56:43.951371 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4183 11:56:43.954111 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4184 11:56:43.957235 0 10 16 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
4185 11:56:43.964066 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 11:56:43.967059 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 11:56:43.970831 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 11:56:43.973971 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 11:56:43.980870 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4190 11:56:43.983946 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 11:56:43.987376 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 11:56:43.993972 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:56:43.996906 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:56:44.000877 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:56:44.007361 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:56:44.010351 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:56:44.013924 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 11:56:44.020215 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 11:56:44.023801 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 11:56:44.026829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 11:56:44.034106 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 11:56:44.037045 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 11:56:44.040418 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 11:56:44.047284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 11:56:44.050374 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 11:56:44.053739 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:56:44.060460 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4208 11:56:44.063426 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4209 11:56:44.067099 Total UI for P1: 0, mck2ui 16
4210 11:56:44.070225 best dqsien dly found for B0: ( 0, 13, 12)
4211 11:56:44.073950 Total UI for P1: 0, mck2ui 16
4212 11:56:44.077210 best dqsien dly found for B1: ( 0, 13, 12)
4213 11:56:44.080329 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4214 11:56:44.084207 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4215 11:56:44.084287
4216 11:56:44.087312 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4217 11:56:44.090753 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4218 11:56:44.094305 [Gating] SW calibration Done
4219 11:56:44.094385 ==
4220 11:56:44.097154 Dram Type= 6, Freq= 0, CH_0, rank 1
4221 11:56:44.100179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4222 11:56:44.100260 ==
4223 11:56:44.103904 RX Vref Scan: 0
4224 11:56:44.103983
4225 11:56:44.106951 RX Vref 0 -> 0, step: 1
4226 11:56:44.107031
4227 11:56:44.110296 RX Delay -230 -> 252, step: 16
4228 11:56:44.113558 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4229 11:56:44.116880 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4230 11:56:44.120420 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4231 11:56:44.123824 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4232 11:56:44.130380 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4233 11:56:44.133279 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4234 11:56:44.136863 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4235 11:56:44.140142 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4236 11:56:44.146474 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4237 11:56:44.150134 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4238 11:56:44.153243 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4239 11:56:44.156560 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4240 11:56:44.163277 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4241 11:56:44.166193 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4242 11:56:44.169909 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4243 11:56:44.173438 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4244 11:56:44.173543 ==
4245 11:56:44.176357 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 11:56:44.183256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 11:56:44.183336 ==
4248 11:56:44.183399 DQS Delay:
4249 11:56:44.186390 DQS0 = 0, DQS1 = 0
4250 11:56:44.186460 DQM Delay:
4251 11:56:44.186519 DQM0 = 52, DQM1 = 43
4252 11:56:44.189516 DQ Delay:
4253 11:56:44.193466 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4254 11:56:44.196450 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4255 11:56:44.200089 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4256 11:56:44.203113 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4257 11:56:44.203209
4258 11:56:44.203295
4259 11:56:44.203378 ==
4260 11:56:44.206236 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 11:56:44.209930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 11:56:44.210009 ==
4263 11:56:44.210105
4264 11:56:44.210160
4265 11:56:44.213400 TX Vref Scan disable
4266 11:56:44.213500 == TX Byte 0 ==
4267 11:56:44.219889 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4268 11:56:44.223231 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4269 11:56:44.223328 == TX Byte 1 ==
4270 11:56:44.229777 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4271 11:56:44.233448 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4272 11:56:44.233544 ==
4273 11:56:44.236227 Dram Type= 6, Freq= 0, CH_0, rank 1
4274 11:56:44.239569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4275 11:56:44.239646 ==
4276 11:56:44.239705
4277 11:56:44.239760
4278 11:56:44.243346 TX Vref Scan disable
4279 11:56:44.246384 == TX Byte 0 ==
4280 11:56:44.249469 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4281 11:56:44.253271 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4282 11:56:44.256355 == TX Byte 1 ==
4283 11:56:44.259876 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4284 11:56:44.266634 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4285 11:56:44.266738
4286 11:56:44.266841 [DATLAT]
4287 11:56:44.266936 Freq=600, CH0 RK1
4288 11:56:44.267036
4289 11:56:44.269543 DATLAT Default: 0x9
4290 11:56:44.269649 0, 0xFFFF, sum = 0
4291 11:56:44.273018 1, 0xFFFF, sum = 0
4292 11:56:44.273120 2, 0xFFFF, sum = 0
4293 11:56:44.276344 3, 0xFFFF, sum = 0
4294 11:56:44.279745 4, 0xFFFF, sum = 0
4295 11:56:44.279845 5, 0xFFFF, sum = 0
4296 11:56:44.283104 6, 0xFFFF, sum = 0
4297 11:56:44.283200 7, 0xFFFF, sum = 0
4298 11:56:44.283287 8, 0x0, sum = 1
4299 11:56:44.286669 9, 0x0, sum = 2
4300 11:56:44.286740 10, 0x0, sum = 3
4301 11:56:44.289931 11, 0x0, sum = 4
4302 11:56:44.289999 best_step = 9
4303 11:56:44.290059
4304 11:56:44.290130 ==
4305 11:56:44.292720 Dram Type= 6, Freq= 0, CH_0, rank 1
4306 11:56:44.299664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4307 11:56:44.299761 ==
4308 11:56:44.299852 RX Vref Scan: 0
4309 11:56:44.299943
4310 11:56:44.302887 RX Vref 0 -> 0, step: 1
4311 11:56:44.302955
4312 11:56:44.306027 RX Delay -163 -> 252, step: 8
4313 11:56:44.309835 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4314 11:56:44.316390 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4315 11:56:44.319433 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4316 11:56:44.323080 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4317 11:56:44.326260 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4318 11:56:44.329467 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4319 11:56:44.332860 iDelay=205, Bit 6, Center 64 (-75 ~ 204) 280
4320 11:56:44.339498 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4321 11:56:44.343000 iDelay=205, Bit 8, Center 40 (-99 ~ 180) 280
4322 11:56:44.345933 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4323 11:56:44.349546 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4324 11:56:44.352801 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4325 11:56:44.359859 iDelay=205, Bit 12, Center 52 (-83 ~ 188) 272
4326 11:56:44.363348 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4327 11:56:44.366289 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4328 11:56:44.370023 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4329 11:56:44.370113 ==
4330 11:56:44.373036 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 11:56:44.379349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 11:56:44.379474 ==
4333 11:56:44.379569 DQS Delay:
4334 11:56:44.383081 DQS0 = 0, DQS1 = 0
4335 11:56:44.383227 DQM Delay:
4336 11:56:44.383331 DQM0 = 54, DQM1 = 47
4337 11:56:44.386302 DQ Delay:
4338 11:56:44.389591 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4339 11:56:44.392581 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4340 11:56:44.396330 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4341 11:56:44.399463 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4342 11:56:44.399659
4343 11:56:44.399841
4344 11:56:44.405908 [DQSOSCAuto] RK1, (LSB)MR18= 0x6526, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps
4345 11:56:44.409328 CH0 RK1: MR19=808, MR18=6526
4346 11:56:44.416114 CH0_RK1: MR19=0x808, MR18=0x6526, DQSOSC=390, MR23=63, INC=172, DEC=114
4347 11:56:44.419397 [RxdqsGatingPostProcess] freq 600
4348 11:56:44.422904 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4349 11:56:44.426192 Pre-setting of DQS Precalculation
4350 11:56:44.433011 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4351 11:56:44.433640 ==
4352 11:56:44.436400 Dram Type= 6, Freq= 0, CH_1, rank 0
4353 11:56:44.439803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4354 11:56:44.440285 ==
4355 11:56:44.445994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4356 11:56:44.452558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4357 11:56:44.455944 [CA 0] Center 35 (5~66) winsize 62
4358 11:56:44.459308 [CA 1] Center 36 (5~67) winsize 63
4359 11:56:44.463097 [CA 2] Center 34 (4~65) winsize 62
4360 11:56:44.466156 [CA 3] Center 34 (4~65) winsize 62
4361 11:56:44.469535 [CA 4] Center 34 (4~65) winsize 62
4362 11:56:44.472851 [CA 5] Center 34 (3~65) winsize 63
4363 11:56:44.473289
4364 11:56:44.476518 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4365 11:56:44.476930
4366 11:56:44.479799 [CATrainingPosCal] consider 1 rank data
4367 11:56:44.482962 u2DelayCellTimex100 = 270/100 ps
4368 11:56:44.486010 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4369 11:56:44.489902 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4370 11:56:44.492997 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4371 11:56:44.496094 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4372 11:56:44.499173 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4373 11:56:44.502918 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4374 11:56:44.503409
4375 11:56:44.509051 CA PerBit enable=1, Macro0, CA PI delay=34
4376 11:56:44.509536
4377 11:56:44.510006 [CBTSetCACLKResult] CA Dly = 34
4378 11:56:44.512617 CS Dly: 6 (0~37)
4379 11:56:44.513202 ==
4380 11:56:44.515577 Dram Type= 6, Freq= 0, CH_1, rank 1
4381 11:56:44.518993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4382 11:56:44.519404 ==
4383 11:56:44.525614 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4384 11:56:44.532882 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4385 11:56:44.536105 [CA 0] Center 36 (5~67) winsize 63
4386 11:56:44.538795 [CA 1] Center 36 (5~67) winsize 63
4387 11:56:44.542676 [CA 2] Center 34 (4~65) winsize 62
4388 11:56:44.545848 [CA 3] Center 34 (3~65) winsize 63
4389 11:56:44.549384 [CA 4] Center 34 (4~65) winsize 62
4390 11:56:44.552297 [CA 5] Center 34 (3~65) winsize 63
4391 11:56:44.552703
4392 11:56:44.555645 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4393 11:56:44.556060
4394 11:56:44.558715 [CATrainingPosCal] consider 2 rank data
4395 11:56:44.562239 u2DelayCellTimex100 = 270/100 ps
4396 11:56:44.565665 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4397 11:56:44.568986 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4398 11:56:44.572070 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 11:56:44.575288 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4400 11:56:44.579020 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4401 11:56:44.585469 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4402 11:56:44.585899
4403 11:56:44.588554 CA PerBit enable=1, Macro0, CA PI delay=34
4404 11:56:44.588958
4405 11:56:44.591775 [CBTSetCACLKResult] CA Dly = 34
4406 11:56:44.592185 CS Dly: 6 (0~38)
4407 11:56:44.592510
4408 11:56:44.595578 ----->DramcWriteLeveling(PI) begin...
4409 11:56:44.595990 ==
4410 11:56:44.598507 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 11:56:44.605121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 11:56:44.605529 ==
4413 11:56:44.608654 Write leveling (Byte 0): 33 => 33
4414 11:56:44.609060 Write leveling (Byte 1): 31 => 31
4415 11:56:44.612068 DramcWriteLeveling(PI) end<-----
4416 11:56:44.612475
4417 11:56:44.612802 ==
4418 11:56:44.614857 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 11:56:44.621813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 11:56:44.622223 ==
4421 11:56:44.624845 [Gating] SW mode calibration
4422 11:56:44.631379 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4423 11:56:44.634865 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4424 11:56:44.641505 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 11:56:44.644974 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4426 11:56:44.648281 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4427 11:56:44.655176 0 9 12 | B1->B0 | 3232 2f2f | 0 1 | (0 1) (1 0)
4428 11:56:44.658357 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4429 11:56:44.661220 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 11:56:44.664875 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 11:56:44.671511 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 11:56:44.675085 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4433 11:56:44.677874 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4434 11:56:44.684876 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4435 11:56:44.688168 0 10 12 | B1->B0 | 2d2d 3636 | 0 0 | (0 0) (0 0)
4436 11:56:44.691283 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 11:56:44.697980 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 11:56:44.701122 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 11:56:44.704957 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 11:56:44.711091 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 11:56:44.714781 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4442 11:56:44.717904 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4443 11:56:44.724907 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4444 11:56:44.727928 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:56:44.731147 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:56:44.737958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:56:44.740957 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:56:44.744689 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:56:44.751231 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:56:44.754369 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 11:56:44.757500 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 11:56:44.764589 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 11:56:44.767683 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 11:56:44.771209 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 11:56:44.777804 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 11:56:44.780697 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4457 11:56:44.784111 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4458 11:56:44.790818 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4459 11:56:44.794143 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4460 11:56:44.797060 Total UI for P1: 0, mck2ui 16
4461 11:56:44.800446 best dqsien dly found for B0: ( 0, 13, 10)
4462 11:56:44.803711 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4463 11:56:44.807355 Total UI for P1: 0, mck2ui 16
4464 11:56:44.810371 best dqsien dly found for B1: ( 0, 13, 12)
4465 11:56:44.813488 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4466 11:56:44.817150 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4467 11:56:44.817232
4468 11:56:44.820838 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4469 11:56:44.826951 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4470 11:56:44.827031 [Gating] SW calibration Done
4471 11:56:44.830044 ==
4472 11:56:44.834136 Dram Type= 6, Freq= 0, CH_1, rank 0
4473 11:56:44.836977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4474 11:56:44.837056 ==
4475 11:56:44.837118 RX Vref Scan: 0
4476 11:56:44.837176
4477 11:56:44.840207 RX Vref 0 -> 0, step: 1
4478 11:56:44.840286
4479 11:56:44.843816 RX Delay -230 -> 252, step: 16
4480 11:56:44.847011 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4481 11:56:44.850076 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4482 11:56:44.857033 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4483 11:56:44.860482 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4484 11:56:44.863372 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4485 11:56:44.867109 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4486 11:56:44.870085 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4487 11:56:44.877157 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4488 11:56:44.880281 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4489 11:56:44.883805 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4490 11:56:44.886786 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4491 11:56:44.893446 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4492 11:56:44.896901 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4493 11:56:44.899977 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4494 11:56:44.903592 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4495 11:56:44.910391 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4496 11:56:44.910470 ==
4497 11:56:44.913781 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 11:56:44.916995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 11:56:44.917095 ==
4500 11:56:44.917227 DQS Delay:
4501 11:56:44.920520 DQS0 = 0, DQS1 = 0
4502 11:56:44.920625 DQM Delay:
4503 11:56:44.923518 DQM0 = 52, DQM1 = 49
4504 11:56:44.923588 DQ Delay:
4505 11:56:44.926565 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4506 11:56:44.930044 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4507 11:56:44.933204 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4508 11:56:44.936619 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4509 11:56:44.936721
4510 11:56:44.936809
4511 11:56:44.936893 ==
4512 11:56:44.940053 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 11:56:44.943671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 11:56:44.943767 ==
4515 11:56:44.943861
4516 11:56:44.943946
4517 11:56:44.946713 TX Vref Scan disable
4518 11:56:44.950598 == TX Byte 0 ==
4519 11:56:44.953434 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4520 11:56:44.956862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4521 11:56:44.960132 == TX Byte 1 ==
4522 11:56:44.963596 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 11:56:44.966959 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 11:56:44.967030 ==
4525 11:56:44.970150 Dram Type= 6, Freq= 0, CH_1, rank 0
4526 11:56:44.977038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4527 11:56:44.977113 ==
4528 11:56:44.977174
4529 11:56:44.977230
4530 11:56:44.977287 TX Vref Scan disable
4531 11:56:44.980670 == TX Byte 0 ==
4532 11:56:44.984393 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4533 11:56:44.991246 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4534 11:56:44.991322 == TX Byte 1 ==
4535 11:56:44.994372 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4536 11:56:45.001077 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4537 11:56:45.001188
4538 11:56:45.001277 [DATLAT]
4539 11:56:45.001363 Freq=600, CH1 RK0
4540 11:56:45.001454
4541 11:56:45.003918 DATLAT Default: 0x9
4542 11:56:45.003987 0, 0xFFFF, sum = 0
4543 11:56:45.007460 1, 0xFFFF, sum = 0
4544 11:56:45.007560 2, 0xFFFF, sum = 0
4545 11:56:45.010897 3, 0xFFFF, sum = 0
4546 11:56:45.014591 4, 0xFFFF, sum = 0
4547 11:56:45.014692 5, 0xFFFF, sum = 0
4548 11:56:45.017403 6, 0xFFFF, sum = 0
4549 11:56:45.017502 7, 0xFFFF, sum = 0
4550 11:56:45.020521 8, 0x0, sum = 1
4551 11:56:45.020591 9, 0x0, sum = 2
4552 11:56:45.020650 10, 0x0, sum = 3
4553 11:56:45.024362 11, 0x0, sum = 4
4554 11:56:45.024442 best_step = 9
4555 11:56:45.024505
4556 11:56:45.024563 ==
4557 11:56:45.027521 Dram Type= 6, Freq= 0, CH_1, rank 0
4558 11:56:45.034191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4559 11:56:45.034277 ==
4560 11:56:45.034340 RX Vref Scan: 1
4561 11:56:45.034399
4562 11:56:45.037497 RX Vref 0 -> 0, step: 1
4563 11:56:45.037584
4564 11:56:45.040779 RX Delay -147 -> 252, step: 8
4565 11:56:45.040883
4566 11:56:45.044157 Set Vref, RX VrefLevel [Byte0]: 55
4567 11:56:45.047222 [Byte1]: 53
4568 11:56:45.047295
4569 11:56:45.050494 Final RX Vref Byte 0 = 55 to rank0
4570 11:56:45.054337 Final RX Vref Byte 1 = 53 to rank0
4571 11:56:45.057157 Final RX Vref Byte 0 = 55 to rank1
4572 11:56:45.060429 Final RX Vref Byte 1 = 53 to rank1==
4573 11:56:45.064137 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 11:56:45.067254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 11:56:45.067326 ==
4576 11:56:45.070248 DQS Delay:
4577 11:56:45.070343 DQS0 = 0, DQS1 = 0
4578 11:56:45.070436 DQM Delay:
4579 11:56:45.073752 DQM0 = 48, DQM1 = 45
4580 11:56:45.073820 DQ Delay:
4581 11:56:45.077079 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4582 11:56:45.080252 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4583 11:56:45.083910 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4584 11:56:45.087026 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4585 11:56:45.087097
4586 11:56:45.087157
4587 11:56:45.097486 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4588 11:56:45.100754 CH1 RK0: MR19=808, MR18=466C
4589 11:56:45.103808 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4590 11:56:45.106931
4591 11:56:45.110467 ----->DramcWriteLeveling(PI) begin...
4592 11:56:45.110547 ==
4593 11:56:45.113405 Dram Type= 6, Freq= 0, CH_1, rank 1
4594 11:56:45.117225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4595 11:56:45.117327 ==
4596 11:56:45.120568 Write leveling (Byte 0): 32 => 32
4597 11:56:45.123994 Write leveling (Byte 1): 32 => 32
4598 11:56:45.127289 DramcWriteLeveling(PI) end<-----
4599 11:56:45.127368
4600 11:56:45.127430 ==
4601 11:56:45.130602 Dram Type= 6, Freq= 0, CH_1, rank 1
4602 11:56:45.133715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4603 11:56:45.133796 ==
4604 11:56:45.137142 [Gating] SW mode calibration
4605 11:56:45.143659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4606 11:56:45.149819 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4607 11:56:45.153381 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4608 11:56:45.156360 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4609 11:56:45.163178 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4610 11:56:45.166345 0 9 12 | B1->B0 | 2f2f 3131 | 0 0 | (0 1) (0 1)
4611 11:56:45.170175 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4612 11:56:45.176699 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 11:56:45.179939 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 11:56:45.183009 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 11:56:45.186471 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4616 11:56:45.193475 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4617 11:56:45.196635 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4618 11:56:45.199797 0 10 12 | B1->B0 | 3535 3333 | 0 0 | (0 0) (0 0)
4619 11:56:45.206530 0 10 16 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
4620 11:56:45.209807 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 11:56:45.212964 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 11:56:45.219812 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4623 11:56:45.222860 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4624 11:56:45.226442 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4625 11:56:45.232926 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4626 11:56:45.236138 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4627 11:56:45.240017 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4628 11:56:45.246559 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:56:45.249544 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:56:45.253160 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:56:45.259935 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:56:45.262989 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:56:45.266145 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 11:56:45.272770 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 11:56:45.276070 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 11:56:45.279815 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 11:56:45.286428 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 11:56:45.289647 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 11:56:45.293288 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4640 11:56:45.299717 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4641 11:56:45.303006 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4642 11:56:45.306268 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 11:56:45.309395 Total UI for P1: 0, mck2ui 16
4644 11:56:45.313082 best dqsien dly found for B0: ( 0, 13, 10)
4645 11:56:45.316347 Total UI for P1: 0, mck2ui 16
4646 11:56:45.319395 best dqsien dly found for B1: ( 0, 13, 8)
4647 11:56:45.323120 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4648 11:56:45.326497 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4649 11:56:45.326578
4650 11:56:45.329415 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4651 11:56:45.336391 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4652 11:56:45.336497 [Gating] SW calibration Done
4653 11:56:45.336588 ==
4654 11:56:45.339557 Dram Type= 6, Freq= 0, CH_1, rank 1
4655 11:56:45.346408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4656 11:56:45.346484 ==
4657 11:56:45.346557 RX Vref Scan: 0
4658 11:56:45.346617
4659 11:56:45.349569 RX Vref 0 -> 0, step: 1
4660 11:56:45.349678
4661 11:56:45.352806 RX Delay -230 -> 252, step: 16
4662 11:56:45.356137 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4663 11:56:45.359355 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4664 11:56:45.366069 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4665 11:56:45.369472 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4666 11:56:45.372602 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4667 11:56:45.375592 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4668 11:56:45.379512 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4669 11:56:45.386354 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4670 11:56:45.389331 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4671 11:56:45.392433 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4672 11:56:45.395936 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4673 11:56:45.402376 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4674 11:56:45.405735 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4675 11:56:45.409307 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4676 11:56:45.412138 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4677 11:56:45.415574 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4678 11:56:45.418929 ==
4679 11:56:45.422148 Dram Type= 6, Freq= 0, CH_1, rank 1
4680 11:56:45.426057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4681 11:56:45.426137 ==
4682 11:56:45.426200 DQS Delay:
4683 11:56:45.429164 DQS0 = 0, DQS1 = 0
4684 11:56:45.429243 DQM Delay:
4685 11:56:45.432220 DQM0 = 50, DQM1 = 48
4686 11:56:45.432302 DQ Delay:
4687 11:56:45.435969 DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49
4688 11:56:45.438980 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4689 11:56:45.442811 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4690 11:56:45.446105 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4691 11:56:45.446195
4692 11:56:45.446259
4693 11:56:45.446318 ==
4694 11:56:45.449289 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 11:56:45.452515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 11:56:45.452595 ==
4697 11:56:45.452658
4698 11:56:45.452738
4699 11:56:45.455495 TX Vref Scan disable
4700 11:56:45.459080 == TX Byte 0 ==
4701 11:56:45.462782 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4702 11:56:45.465551 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4703 11:56:45.469172 == TX Byte 1 ==
4704 11:56:45.472606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4705 11:56:45.475551 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4706 11:56:45.475648 ==
4707 11:56:45.478660 Dram Type= 6, Freq= 0, CH_1, rank 1
4708 11:56:45.485498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4709 11:56:45.485644 ==
4710 11:56:45.485710
4711 11:56:45.485767
4712 11:56:45.485822 TX Vref Scan disable
4713 11:56:45.489391 == TX Byte 0 ==
4714 11:56:45.493180 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4715 11:56:45.496210 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4716 11:56:45.499815 == TX Byte 1 ==
4717 11:56:45.502966 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4718 11:56:45.509893 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4719 11:56:45.509973
4720 11:56:45.510035 [DATLAT]
4721 11:56:45.510091 Freq=600, CH1 RK1
4722 11:56:45.510146
4723 11:56:45.512891 DATLAT Default: 0x9
4724 11:56:45.512971 0, 0xFFFF, sum = 0
4725 11:56:45.516086 1, 0xFFFF, sum = 0
4726 11:56:45.516179 2, 0xFFFF, sum = 0
4727 11:56:45.519497 3, 0xFFFF, sum = 0
4728 11:56:45.523141 4, 0xFFFF, sum = 0
4729 11:56:45.523216 5, 0xFFFF, sum = 0
4730 11:56:45.525842 6, 0xFFFF, sum = 0
4731 11:56:45.525912 7, 0xFFFF, sum = 0
4732 11:56:45.529238 8, 0x0, sum = 1
4733 11:56:45.529308 9, 0x0, sum = 2
4734 11:56:45.529366 10, 0x0, sum = 3
4735 11:56:45.532659 11, 0x0, sum = 4
4736 11:56:45.532730 best_step = 9
4737 11:56:45.532787
4738 11:56:45.532842 ==
4739 11:56:45.536474 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 11:56:45.543127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 11:56:45.543199 ==
4742 11:56:45.543292 RX Vref Scan: 0
4743 11:56:45.543377
4744 11:56:45.546336 RX Vref 0 -> 0, step: 1
4745 11:56:45.546413
4746 11:56:45.549507 RX Delay -163 -> 252, step: 8
4747 11:56:45.552707 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4748 11:56:45.559419 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4749 11:56:45.562897 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4750 11:56:45.565858 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4751 11:56:45.569709 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4752 11:56:45.572817 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4753 11:56:45.576422 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4754 11:56:45.582726 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4755 11:56:45.586461 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4756 11:56:45.589658 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4757 11:56:45.592801 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4758 11:56:45.599721 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4759 11:56:45.602731 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4760 11:56:45.605940 iDelay=205, Bit 13, Center 48 (-99 ~ 196) 296
4761 11:56:45.609034 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4762 11:56:45.613094 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4763 11:56:45.615866 ==
4764 11:56:45.619322 Dram Type= 6, Freq= 0, CH_1, rank 1
4765 11:56:45.622835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4766 11:56:45.622916 ==
4767 11:56:45.622980 DQS Delay:
4768 11:56:45.626277 DQS0 = 0, DQS1 = 0
4769 11:56:45.626356 DQM Delay:
4770 11:56:45.628959 DQM0 = 49, DQM1 = 44
4771 11:56:45.629038 DQ Delay:
4772 11:56:45.632876 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4773 11:56:45.635739 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4774 11:56:45.639396 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4775 11:56:45.642164 DQ12 =52, DQ13 =48, DQ14 =52, DQ15 =52
4776 11:56:45.642244
4777 11:56:45.642307
4778 11:56:45.649079 [DQSOSCAuto] RK1, (LSB)MR18= 0x661e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4779 11:56:45.652432 CH1 RK1: MR19=808, MR18=661E
4780 11:56:45.659022 CH1_RK1: MR19=0x808, MR18=0x661E, DQSOSC=390, MR23=63, INC=172, DEC=114
4781 11:56:45.662321 [RxdqsGatingPostProcess] freq 600
4782 11:56:45.669298 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4783 11:56:45.669396 Pre-setting of DQS Precalculation
4784 11:56:45.675588 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4785 11:56:45.682216 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4786 11:56:45.688501 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4787 11:56:45.688600
4788 11:56:45.688691
4789 11:56:45.692255 [Calibration Summary] 1200 Mbps
4790 11:56:45.695279 CH 0, Rank 0
4791 11:56:45.695357 SW Impedance : PASS
4792 11:56:45.698481 DUTY Scan : NO K
4793 11:56:45.702351 ZQ Calibration : PASS
4794 11:56:45.702429 Jitter Meter : NO K
4795 11:56:45.705429 CBT Training : PASS
4796 11:56:45.708771 Write leveling : PASS
4797 11:56:45.708857 RX DQS gating : PASS
4798 11:56:45.712015 RX DQ/DQS(RDDQC) : PASS
4799 11:56:45.712117 TX DQ/DQS : PASS
4800 11:56:45.715041 RX DATLAT : PASS
4801 11:56:45.718168 RX DQ/DQS(Engine): PASS
4802 11:56:45.718264 TX OE : NO K
4803 11:56:45.722110 All Pass.
4804 11:56:45.722212
4805 11:56:45.722300 CH 0, Rank 1
4806 11:56:45.725061 SW Impedance : PASS
4807 11:56:45.725131 DUTY Scan : NO K
4808 11:56:45.728456 ZQ Calibration : PASS
4809 11:56:45.731432 Jitter Meter : NO K
4810 11:56:45.731502 CBT Training : PASS
4811 11:56:45.734885 Write leveling : PASS
4812 11:56:45.738241 RX DQS gating : PASS
4813 11:56:45.738321 RX DQ/DQS(RDDQC) : PASS
4814 11:56:45.742200 TX DQ/DQS : PASS
4815 11:56:45.744791 RX DATLAT : PASS
4816 11:56:45.744882 RX DQ/DQS(Engine): PASS
4817 11:56:45.748043 TX OE : NO K
4818 11:56:45.748122 All Pass.
4819 11:56:45.748192
4820 11:56:45.751673 CH 1, Rank 0
4821 11:56:45.751778 SW Impedance : PASS
4822 11:56:45.755211 DUTY Scan : NO K
4823 11:56:45.758520 ZQ Calibration : PASS
4824 11:56:45.758619 Jitter Meter : NO K
4825 11:56:45.761554 CBT Training : PASS
4826 11:56:45.764653 Write leveling : PASS
4827 11:56:45.764750 RX DQS gating : PASS
4828 11:56:45.768751 RX DQ/DQS(RDDQC) : PASS
4829 11:56:45.771352 TX DQ/DQS : PASS
4830 11:56:45.771455 RX DATLAT : PASS
4831 11:56:45.774729 RX DQ/DQS(Engine): PASS
4832 11:56:45.774800 TX OE : NO K
4833 11:56:45.777969 All Pass.
4834 11:56:45.778064
4835 11:56:45.778160 CH 1, Rank 1
4836 11:56:45.781785 SW Impedance : PASS
4837 11:56:45.781884 DUTY Scan : NO K
4838 11:56:45.784846 ZQ Calibration : PASS
4839 11:56:45.788413 Jitter Meter : NO K
4840 11:56:45.788509 CBT Training : PASS
4841 11:56:45.791393 Write leveling : PASS
4842 11:56:45.794731 RX DQS gating : PASS
4843 11:56:45.794828 RX DQ/DQS(RDDQC) : PASS
4844 11:56:45.798699 TX DQ/DQS : PASS
4845 11:56:45.801460 RX DATLAT : PASS
4846 11:56:45.801557 RX DQ/DQS(Engine): PASS
4847 11:56:45.804914 TX OE : NO K
4848 11:56:45.805017 All Pass.
4849 11:56:45.805104
4850 11:56:45.808333 DramC Write-DBI off
4851 11:56:45.811272 PER_BANK_REFRESH: Hybrid Mode
4852 11:56:45.811344 TX_TRACKING: ON
4853 11:56:45.821126 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4854 11:56:45.824966 [FAST_K] Save calibration result to emmc
4855 11:56:45.828065 dramc_set_vcore_voltage set vcore to 662500
4856 11:56:45.831175 Read voltage for 933, 3
4857 11:56:45.831274 Vio18 = 0
4858 11:56:45.831363 Vcore = 662500
4859 11:56:45.834877 Vdram = 0
4860 11:56:45.834948 Vddq = 0
4861 11:56:45.835007 Vmddr = 0
4862 11:56:45.841332 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4863 11:56:45.845137 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4864 11:56:45.848225 MEM_TYPE=3, freq_sel=17
4865 11:56:45.851321 sv_algorithm_assistance_LP4_1600
4866 11:56:45.854965 ============ PULL DRAM RESETB DOWN ============
4867 11:56:45.858045 ========== PULL DRAM RESETB DOWN end =========
4868 11:56:45.864981 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4869 11:56:45.867797 ===================================
4870 11:56:45.867869 LPDDR4 DRAM CONFIGURATION
4871 11:56:45.871230 ===================================
4872 11:56:45.874583 EX_ROW_EN[0] = 0x0
4873 11:56:45.878152 EX_ROW_EN[1] = 0x0
4874 11:56:45.878223 LP4Y_EN = 0x0
4875 11:56:45.881707 WORK_FSP = 0x0
4876 11:56:45.881781 WL = 0x3
4877 11:56:45.884750 RL = 0x3
4878 11:56:45.884819 BL = 0x2
4879 11:56:45.888408 RPST = 0x0
4880 11:56:45.888503 RD_PRE = 0x0
4881 11:56:45.891177 WR_PRE = 0x1
4882 11:56:45.891260 WR_PST = 0x0
4883 11:56:45.895040 DBI_WR = 0x0
4884 11:56:45.895113 DBI_RD = 0x0
4885 11:56:45.898255 OTF = 0x1
4886 11:56:45.901086 ===================================
4887 11:56:45.904683 ===================================
4888 11:56:45.904757 ANA top config
4889 11:56:45.908236 ===================================
4890 11:56:45.911487 DLL_ASYNC_EN = 0
4891 11:56:45.914722 ALL_SLAVE_EN = 1
4892 11:56:45.914793 NEW_RANK_MODE = 1
4893 11:56:45.918164 DLL_IDLE_MODE = 1
4894 11:56:45.921183 LP45_APHY_COMB_EN = 1
4895 11:56:45.924357 TX_ODT_DIS = 1
4896 11:56:45.928148 NEW_8X_MODE = 1
4897 11:56:45.931415 ===================================
4898 11:56:45.934442 ===================================
4899 11:56:45.934512 data_rate = 1866
4900 11:56:45.937588 CKR = 1
4901 11:56:45.941242 DQ_P2S_RATIO = 8
4902 11:56:45.944710 ===================================
4903 11:56:45.947821 CA_P2S_RATIO = 8
4904 11:56:45.950860 DQ_CA_OPEN = 0
4905 11:56:45.954613 DQ_SEMI_OPEN = 0
4906 11:56:45.954693 CA_SEMI_OPEN = 0
4907 11:56:45.957488 CA_FULL_RATE = 0
4908 11:56:45.961047 DQ_CKDIV4_EN = 1
4909 11:56:45.964495 CA_CKDIV4_EN = 1
4910 11:56:45.967803 CA_PREDIV_EN = 0
4911 11:56:45.970931 PH8_DLY = 0
4912 11:56:45.971012 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4913 11:56:45.974520 DQ_AAMCK_DIV = 4
4914 11:56:45.977557 CA_AAMCK_DIV = 4
4915 11:56:45.981053 CA_ADMCK_DIV = 4
4916 11:56:45.984592 DQ_TRACK_CA_EN = 0
4917 11:56:45.987985 CA_PICK = 933
4918 11:56:45.988090 CA_MCKIO = 933
4919 11:56:45.991167 MCKIO_SEMI = 0
4920 11:56:45.994435 PLL_FREQ = 3732
4921 11:56:45.997460 DQ_UI_PI_RATIO = 32
4922 11:56:46.001189 CA_UI_PI_RATIO = 0
4923 11:56:46.004182 ===================================
4924 11:56:46.007395 ===================================
4925 11:56:46.010635 memory_type:LPDDR4
4926 11:56:46.010717 GP_NUM : 10
4927 11:56:46.014126 SRAM_EN : 1
4928 11:56:46.014206 MD32_EN : 0
4929 11:56:46.017863 ===================================
4930 11:56:46.021174 [ANA_INIT] >>>>>>>>>>>>>>
4931 11:56:46.024148 <<<<<< [CONFIGURE PHASE]: ANA_TX
4932 11:56:46.027685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4933 11:56:46.031082 ===================================
4934 11:56:46.034129 data_rate = 1866,PCW = 0X8f00
4935 11:56:46.037905 ===================================
4936 11:56:46.040934 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4937 11:56:46.047665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4938 11:56:46.050786 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4939 11:56:46.057400 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4940 11:56:46.061231 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4941 11:56:46.064198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4942 11:56:46.064280 [ANA_INIT] flow start
4943 11:56:46.067591 [ANA_INIT] PLL >>>>>>>>
4944 11:56:46.070829 [ANA_INIT] PLL <<<<<<<<
4945 11:56:46.070907 [ANA_INIT] MIDPI >>>>>>>>
4946 11:56:46.073950 [ANA_INIT] MIDPI <<<<<<<<
4947 11:56:46.077385 [ANA_INIT] DLL >>>>>>>>
4948 11:56:46.077458 [ANA_INIT] flow end
4949 11:56:46.084016 ============ LP4 DIFF to SE enter ============
4950 11:56:46.087098 ============ LP4 DIFF to SE exit ============
4951 11:56:46.090800 [ANA_INIT] <<<<<<<<<<<<<
4952 11:56:46.093862 [Flow] Enable top DCM control >>>>>
4953 11:56:46.097318 [Flow] Enable top DCM control <<<<<
4954 11:56:46.097395 Enable DLL master slave shuffle
4955 11:56:46.103819 ==============================================================
4956 11:56:46.107787 Gating Mode config
4957 11:56:46.110849 ==============================================================
4958 11:56:46.113933 Config description:
4959 11:56:46.123495 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4960 11:56:46.130463 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4961 11:56:46.133356 SELPH_MODE 0: By rank 1: By Phase
4962 11:56:46.140104 ==============================================================
4963 11:56:46.143636 GAT_TRACK_EN = 1
4964 11:56:46.146786 RX_GATING_MODE = 2
4965 11:56:46.149873 RX_GATING_TRACK_MODE = 2
4966 11:56:46.153773 SELPH_MODE = 1
4967 11:56:46.153873 PICG_EARLY_EN = 1
4968 11:56:46.156788 VALID_LAT_VALUE = 1
4969 11:56:46.163396 ==============================================================
4970 11:56:46.166541 Enter into Gating configuration >>>>
4971 11:56:46.170266 Exit from Gating configuration <<<<
4972 11:56:46.173225 Enter into DVFS_PRE_config >>>>>
4973 11:56:46.183104 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4974 11:56:46.186790 Exit from DVFS_PRE_config <<<<<
4975 11:56:46.189781 Enter into PICG configuration >>>>
4976 11:56:46.193509 Exit from PICG configuration <<<<
4977 11:56:46.196621 [RX_INPUT] configuration >>>>>
4978 11:56:46.199979 [RX_INPUT] configuration <<<<<
4979 11:56:46.202987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4980 11:56:46.209595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4981 11:56:46.216684 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 11:56:46.222892 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 11:56:46.230134 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4984 11:56:46.233437 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4985 11:56:46.239619 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4986 11:56:46.242940 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4987 11:56:46.246290 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4988 11:56:46.249716 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4989 11:56:46.256403 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4990 11:56:46.259660 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4991 11:56:46.263270 ===================================
4992 11:56:46.266529 LPDDR4 DRAM CONFIGURATION
4993 11:56:46.269819 ===================================
4994 11:56:46.269893 EX_ROW_EN[0] = 0x0
4995 11:56:46.272913 EX_ROW_EN[1] = 0x0
4996 11:56:46.272990 LP4Y_EN = 0x0
4997 11:56:46.276571 WORK_FSP = 0x0
4998 11:56:46.276644 WL = 0x3
4999 11:56:46.279923 RL = 0x3
5000 11:56:46.280009 BL = 0x2
5001 11:56:46.283077 RPST = 0x0
5002 11:56:46.283156 RD_PRE = 0x0
5003 11:56:46.286417 WR_PRE = 0x1
5004 11:56:46.286491 WR_PST = 0x0
5005 11:56:46.289464 DBI_WR = 0x0
5006 11:56:46.292993 DBI_RD = 0x0
5007 11:56:46.293063 OTF = 0x1
5008 11:56:46.296645 ===================================
5009 11:56:46.299789 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5010 11:56:46.302855 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5011 11:56:46.309399 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5012 11:56:46.313096 ===================================
5013 11:56:46.313172 LPDDR4 DRAM CONFIGURATION
5014 11:56:46.316570 ===================================
5015 11:56:46.319912 EX_ROW_EN[0] = 0x10
5016 11:56:46.323188 EX_ROW_EN[1] = 0x0
5017 11:56:46.323266 LP4Y_EN = 0x0
5018 11:56:46.326678 WORK_FSP = 0x0
5019 11:56:46.326755 WL = 0x3
5020 11:56:46.329397 RL = 0x3
5021 11:56:46.329473 BL = 0x2
5022 11:56:46.332590 RPST = 0x0
5023 11:56:46.332664 RD_PRE = 0x0
5024 11:56:46.336314 WR_PRE = 0x1
5025 11:56:46.336394 WR_PST = 0x0
5026 11:56:46.339461 DBI_WR = 0x0
5027 11:56:46.339538 DBI_RD = 0x0
5028 11:56:46.342672 OTF = 0x1
5029 11:56:46.346075 ===================================
5030 11:56:46.352567 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5031 11:56:46.355982 nWR fixed to 30
5032 11:56:46.359703 [ModeRegInit_LP4] CH0 RK0
5033 11:56:46.359779 [ModeRegInit_LP4] CH0 RK1
5034 11:56:46.362713 [ModeRegInit_LP4] CH1 RK0
5035 11:56:46.366284 [ModeRegInit_LP4] CH1 RK1
5036 11:56:46.366360 match AC timing 9
5037 11:56:46.372434 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5038 11:56:46.376281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5039 11:56:46.379446 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5040 11:56:46.385998 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5041 11:56:46.389813 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5042 11:56:46.389888 ==
5043 11:56:46.393074 Dram Type= 6, Freq= 0, CH_0, rank 0
5044 11:56:46.395889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5045 11:56:46.395958 ==
5046 11:56:46.403015 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5047 11:56:46.409073 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5048 11:56:46.412665 [CA 0] Center 37 (6~68) winsize 63
5049 11:56:46.416104 [CA 1] Center 37 (6~68) winsize 63
5050 11:56:46.419608 [CA 2] Center 34 (4~65) winsize 62
5051 11:56:46.422684 [CA 3] Center 34 (3~65) winsize 63
5052 11:56:46.426364 [CA 4] Center 33 (3~64) winsize 62
5053 11:56:46.429070 [CA 5] Center 32 (2~63) winsize 62
5054 11:56:46.429144
5055 11:56:46.432676 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5056 11:56:46.432764
5057 11:56:46.436161 [CATrainingPosCal] consider 1 rank data
5058 11:56:46.439168 u2DelayCellTimex100 = 270/100 ps
5059 11:56:46.442741 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5060 11:56:46.445754 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5061 11:56:46.448942 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5062 11:56:46.453016 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5063 11:56:46.455840 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5064 11:56:46.459286 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5065 11:56:46.459392
5066 11:56:46.465769 CA PerBit enable=1, Macro0, CA PI delay=32
5067 11:56:46.465846
5068 11:56:46.465910 [CBTSetCACLKResult] CA Dly = 32
5069 11:56:46.469492 CS Dly: 5 (0~36)
5070 11:56:46.469572 ==
5071 11:56:46.472264 Dram Type= 6, Freq= 0, CH_0, rank 1
5072 11:56:46.475896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5073 11:56:46.476006 ==
5074 11:56:46.482496 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5075 11:56:46.489140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5076 11:56:46.492459 [CA 0] Center 37 (6~68) winsize 63
5077 11:56:46.495764 [CA 1] Center 37 (6~68) winsize 63
5078 11:56:46.499387 [CA 2] Center 34 (4~65) winsize 62
5079 11:56:46.502566 [CA 3] Center 34 (3~65) winsize 63
5080 11:56:46.506008 [CA 4] Center 33 (3~63) winsize 61
5081 11:56:46.509148 [CA 5] Center 32 (2~62) winsize 61
5082 11:56:46.509219
5083 11:56:46.512005 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5084 11:56:46.512080
5085 11:56:46.515756 [CATrainingPosCal] consider 2 rank data
5086 11:56:46.518753 u2DelayCellTimex100 = 270/100 ps
5087 11:56:46.521877 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5088 11:56:46.525570 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5089 11:56:46.528681 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5090 11:56:46.532528 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5091 11:56:46.535602 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5092 11:56:46.542290 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5093 11:56:46.542364
5094 11:56:46.545209 CA PerBit enable=1, Macro0, CA PI delay=32
5095 11:56:46.545283
5096 11:56:46.548969 [CBTSetCACLKResult] CA Dly = 32
5097 11:56:46.549044 CS Dly: 5 (0~37)
5098 11:56:46.549104
5099 11:56:46.552110 ----->DramcWriteLeveling(PI) begin...
5100 11:56:46.552189 ==
5101 11:56:46.555206 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 11:56:46.561729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 11:56:46.561804 ==
5104 11:56:46.565641 Write leveling (Byte 0): 33 => 33
5105 11:56:46.565714 Write leveling (Byte 1): 32 => 32
5106 11:56:46.568634 DramcWriteLeveling(PI) end<-----
5107 11:56:46.568704
5108 11:56:46.568767 ==
5109 11:56:46.571814 Dram Type= 6, Freq= 0, CH_0, rank 0
5110 11:56:46.578737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5111 11:56:46.578814 ==
5112 11:56:46.581794 [Gating] SW mode calibration
5113 11:56:46.588352 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5114 11:56:46.592072 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5115 11:56:46.598298 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5116 11:56:46.601955 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 11:56:46.605262 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 11:56:46.611816 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 11:56:46.615256 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5120 11:56:46.618772 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5121 11:56:46.622072 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5122 11:56:46.628382 0 14 28 | B1->B0 | 3232 2727 | 1 0 | (1 0) (0 0)
5123 11:56:46.631921 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (1 0)
5124 11:56:46.634894 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 11:56:46.641827 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 11:56:46.644872 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 11:56:46.648098 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5128 11:56:46.654980 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5129 11:56:46.658199 0 15 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
5130 11:56:46.661747 0 15 28 | B1->B0 | 2424 3939 | 0 1 | (0 0) (0 0)
5131 11:56:46.668153 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5132 11:56:46.671686 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 11:56:46.675458 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 11:56:46.681402 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 11:56:46.685081 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 11:56:46.688211 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5137 11:56:46.694710 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5138 11:56:46.698083 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5139 11:56:46.701536 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5140 11:56:46.708039 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:56:46.711164 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:56:46.714997 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:56:46.721498 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:56:46.725168 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:56:46.727955 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:56:46.734554 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 11:56:46.738119 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 11:56:46.741471 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 11:56:46.747872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 11:56:46.751231 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 11:56:46.754244 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5152 11:56:46.761400 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5153 11:56:46.764370 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5154 11:56:46.768012 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5155 11:56:46.771026 Total UI for P1: 0, mck2ui 16
5156 11:56:46.774599 best dqsien dly found for B0: ( 1, 2, 26)
5157 11:56:46.777716 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5158 11:56:46.781219 Total UI for P1: 0, mck2ui 16
5159 11:56:46.784276 best dqsien dly found for B1: ( 1, 2, 28)
5160 11:56:46.787983 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5161 11:56:46.794253 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5162 11:56:46.794329
5163 11:56:46.797555 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5164 11:56:46.800952 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5165 11:56:46.804695 [Gating] SW calibration Done
5166 11:56:46.804770 ==
5167 11:56:46.807854 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 11:56:46.811105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 11:56:46.811180 ==
5170 11:56:46.814116 RX Vref Scan: 0
5171 11:56:46.814189
5172 11:56:46.814249 RX Vref 0 -> 0, step: 1
5173 11:56:46.814310
5174 11:56:46.817355 RX Delay -80 -> 252, step: 8
5175 11:56:46.821001 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5176 11:56:46.824598 iDelay=208, Bit 1, Center 103 (8 ~ 199) 192
5177 11:56:46.830977 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5178 11:56:46.834426 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5179 11:56:46.837354 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5180 11:56:46.841436 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5181 11:56:46.844278 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5182 11:56:46.847556 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5183 11:56:46.854466 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5184 11:56:46.857436 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5185 11:56:46.860748 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5186 11:56:46.864365 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5187 11:56:46.867559 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5188 11:56:46.870765 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5189 11:56:46.877235 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5190 11:56:46.880867 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5191 11:56:46.880954 ==
5192 11:56:46.884016 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 11:56:46.887780 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 11:56:46.887861 ==
5195 11:56:46.890557 DQS Delay:
5196 11:56:46.890628 DQS0 = 0, DQS1 = 0
5197 11:56:46.890689 DQM Delay:
5198 11:56:46.894150 DQM0 = 103, DQM1 = 96
5199 11:56:46.894223 DQ Delay:
5200 11:56:46.897374 DQ0 =103, DQ1 =103, DQ2 =99, DQ3 =99
5201 11:56:46.901601 DQ4 =103, DQ5 =95, DQ6 =115, DQ7 =111
5202 11:56:46.904284 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5203 11:56:46.907759 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5204 11:56:46.907840
5205 11:56:46.907908
5206 11:56:46.907967 ==
5207 11:56:46.910750 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:56:46.917401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:56:46.917477 ==
5210 11:56:46.917540
5211 11:56:46.917653
5212 11:56:46.920916 TX Vref Scan disable
5213 11:56:46.921001 == TX Byte 0 ==
5214 11:56:46.923978 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5215 11:56:46.930978 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5216 11:56:46.931063 == TX Byte 1 ==
5217 11:56:46.934094 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5218 11:56:46.940306 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5219 11:56:46.940410 ==
5220 11:56:46.944072 Dram Type= 6, Freq= 0, CH_0, rank 0
5221 11:56:46.947449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5222 11:56:46.947527 ==
5223 11:56:46.947590
5224 11:56:46.947646
5225 11:56:46.950253 TX Vref Scan disable
5226 11:56:46.953657 == TX Byte 0 ==
5227 11:56:46.957021 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5228 11:56:46.960814 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5229 11:56:46.964340 == TX Byte 1 ==
5230 11:56:46.967292 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5231 11:56:46.970279 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5232 11:56:46.970380
5233 11:56:46.970458 [DATLAT]
5234 11:56:46.973819 Freq=933, CH0 RK0
5235 11:56:46.973889
5236 11:56:46.976955 DATLAT Default: 0xd
5237 11:56:46.977036 0, 0xFFFF, sum = 0
5238 11:56:46.980497 1, 0xFFFF, sum = 0
5239 11:56:46.980566 2, 0xFFFF, sum = 0
5240 11:56:46.984139 3, 0xFFFF, sum = 0
5241 11:56:46.984227 4, 0xFFFF, sum = 0
5242 11:56:46.986937 5, 0xFFFF, sum = 0
5243 11:56:46.987024 6, 0xFFFF, sum = 0
5244 11:56:46.990281 7, 0xFFFF, sum = 0
5245 11:56:46.990369 8, 0xFFFF, sum = 0
5246 11:56:46.993753 9, 0xFFFF, sum = 0
5247 11:56:46.993837 10, 0x0, sum = 1
5248 11:56:46.997299 11, 0x0, sum = 2
5249 11:56:46.997373 12, 0x0, sum = 3
5250 11:56:47.000995 13, 0x0, sum = 4
5251 11:56:47.001065 best_step = 11
5252 11:56:47.001124
5253 11:56:47.001182 ==
5254 11:56:47.003685 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 11:56:47.007575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 11:56:47.007649 ==
5257 11:56:47.010379 RX Vref Scan: 1
5258 11:56:47.010448
5259 11:56:47.013763 RX Vref 0 -> 0, step: 1
5260 11:56:47.013850
5261 11:56:47.013909 RX Delay -45 -> 252, step: 4
5262 11:56:47.013965
5263 11:56:47.017516 Set Vref, RX VrefLevel [Byte0]: 61
5264 11:56:47.020187 [Byte1]: 50
5265 11:56:47.024992
5266 11:56:47.025066 Final RX Vref Byte 0 = 61 to rank0
5267 11:56:47.028760 Final RX Vref Byte 1 = 50 to rank0
5268 11:56:47.031933 Final RX Vref Byte 0 = 61 to rank1
5269 11:56:47.035042 Final RX Vref Byte 1 = 50 to rank1==
5270 11:56:47.038206 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:56:47.044933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:56:47.045026 ==
5273 11:56:47.045090 DQS Delay:
5274 11:56:47.048049 DQS0 = 0, DQS1 = 0
5275 11:56:47.048118 DQM Delay:
5276 11:56:47.048177 DQM0 = 105, DQM1 = 96
5277 11:56:47.051279 DQ Delay:
5278 11:56:47.054780 DQ0 =102, DQ1 =106, DQ2 =104, DQ3 =102
5279 11:56:47.058088 DQ4 =106, DQ5 =100, DQ6 =114, DQ7 =112
5280 11:56:47.061368 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5281 11:56:47.065217 DQ12 =102, DQ13 =102, DQ14 =108, DQ15 =104
5282 11:56:47.065290
5283 11:56:47.065350
5284 11:56:47.071528 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5285 11:56:47.074573 CH0 RK0: MR19=505, MR18=332B
5286 11:56:47.081462 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5287 11:56:47.081562
5288 11:56:47.084976 ----->DramcWriteLeveling(PI) begin...
5289 11:56:47.085048 ==
5290 11:56:47.087927 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 11:56:47.091182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 11:56:47.094741 ==
5293 11:56:47.094816 Write leveling (Byte 0): 33 => 33
5294 11:56:47.098172 Write leveling (Byte 1): 31 => 31
5295 11:56:47.101866 DramcWriteLeveling(PI) end<-----
5296 11:56:47.101935
5297 11:56:47.101998 ==
5298 11:56:47.104764 Dram Type= 6, Freq= 0, CH_0, rank 1
5299 11:56:47.111212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 11:56:47.111294 ==
5301 11:56:47.111355 [Gating] SW mode calibration
5302 11:56:47.121232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5303 11:56:47.124801 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5304 11:56:47.127988 0 14 0 | B1->B0 | 3333 3232 | 1 0 | (1 1) (0 0)
5305 11:56:47.135001 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 11:56:47.138094 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 11:56:47.141462 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 11:56:47.148377 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 11:56:47.151298 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5310 11:56:47.154994 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5311 11:56:47.161141 0 14 28 | B1->B0 | 2c2c 2929 | 0 0 | (0 0) (0 0)
5312 11:56:47.164649 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 11:56:47.167748 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 11:56:47.174543 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 11:56:47.177765 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 11:56:47.181157 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5317 11:56:47.187649 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5318 11:56:47.191240 0 15 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
5319 11:56:47.194371 0 15 28 | B1->B0 | 3b3b 3737 | 0 1 | (0 0) (0 0)
5320 11:56:47.201011 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5321 11:56:47.204761 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 11:56:47.207729 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 11:56:47.214550 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 11:56:47.217906 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 11:56:47.221346 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5326 11:56:47.227742 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5327 11:56:47.231060 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5328 11:56:47.234647 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:56:47.238114 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:56:47.244548 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:56:47.247750 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:56:47.251162 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:56:47.257865 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:56:47.261309 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:56:47.264633 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:56:47.271329 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 11:56:47.274698 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 11:56:47.278204 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 11:56:47.284318 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 11:56:47.287505 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 11:56:47.291097 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5342 11:56:47.297793 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5343 11:56:47.300724 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5344 11:56:47.304563 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5345 11:56:47.307656 Total UI for P1: 0, mck2ui 16
5346 11:56:47.311307 best dqsien dly found for B0: ( 1, 2, 28)
5347 11:56:47.314385 Total UI for P1: 0, mck2ui 16
5348 11:56:47.317509 best dqsien dly found for B1: ( 1, 2, 28)
5349 11:56:47.321138 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5350 11:56:47.324312 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5351 11:56:47.324392
5352 11:56:47.327596 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5353 11:56:47.334427 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5354 11:56:47.334507 [Gating] SW calibration Done
5355 11:56:47.337614 ==
5356 11:56:47.337709 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 11:56:47.344276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 11:56:47.344383 ==
5359 11:56:47.344473 RX Vref Scan: 0
5360 11:56:47.344560
5361 11:56:47.347338 RX Vref 0 -> 0, step: 1
5362 11:56:47.347417
5363 11:56:47.351397 RX Delay -80 -> 252, step: 8
5364 11:56:47.353966 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5365 11:56:47.357414 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5366 11:56:47.361065 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5367 11:56:47.367688 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5368 11:56:47.370847 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5369 11:56:47.374217 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5370 11:56:47.377290 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5371 11:56:47.380785 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5372 11:56:47.383961 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5373 11:56:47.390829 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5374 11:56:47.393858 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5375 11:56:47.397704 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5376 11:56:47.400717 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5377 11:56:47.403669 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5378 11:56:47.411034 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5379 11:56:47.413794 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5380 11:56:47.413888 ==
5381 11:56:47.417385 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 11:56:47.420806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 11:56:47.420904 ==
5384 11:56:47.424341 DQS Delay:
5385 11:56:47.424418 DQS0 = 0, DQS1 = 0
5386 11:56:47.424502 DQM Delay:
5387 11:56:47.427225 DQM0 = 106, DQM1 = 93
5388 11:56:47.427313 DQ Delay:
5389 11:56:47.430697 DQ0 =107, DQ1 =111, DQ2 =103, DQ3 =99
5390 11:56:47.433518 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5391 11:56:47.437344 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5392 11:56:47.440391 DQ12 =103, DQ13 =99, DQ14 =103, DQ15 =99
5393 11:56:47.440501
5394 11:56:47.440578
5395 11:56:47.443649 ==
5396 11:56:47.443753 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:56:47.450346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:56:47.450430 ==
5399 11:56:47.450495
5400 11:56:47.450554
5401 11:56:47.453693 TX Vref Scan disable
5402 11:56:47.453771 == TX Byte 0 ==
5403 11:56:47.457115 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5404 11:56:47.463933 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5405 11:56:47.464016 == TX Byte 1 ==
5406 11:56:47.466803 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5407 11:56:47.473334 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5408 11:56:47.473418 ==
5409 11:56:47.477191 Dram Type= 6, Freq= 0, CH_0, rank 1
5410 11:56:47.480097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5411 11:56:47.480207 ==
5412 11:56:47.480282
5413 11:56:47.480343
5414 11:56:47.483659 TX Vref Scan disable
5415 11:56:47.486474 == TX Byte 0 ==
5416 11:56:47.489828 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5417 11:56:47.493130 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5418 11:56:47.496606 == TX Byte 1 ==
5419 11:56:47.499928 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5420 11:56:47.503100 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5421 11:56:47.503187
5422 11:56:47.506319 [DATLAT]
5423 11:56:47.506399 Freq=933, CH0 RK1
5424 11:56:47.506463
5425 11:56:47.510057 DATLAT Default: 0xb
5426 11:56:47.510132 0, 0xFFFF, sum = 0
5427 11:56:47.513371 1, 0xFFFF, sum = 0
5428 11:56:47.513450 2, 0xFFFF, sum = 0
5429 11:56:47.516323 3, 0xFFFF, sum = 0
5430 11:56:47.516431 4, 0xFFFF, sum = 0
5431 11:56:47.519873 5, 0xFFFF, sum = 0
5432 11:56:47.520006 6, 0xFFFF, sum = 0
5433 11:56:47.523543 7, 0xFFFF, sum = 0
5434 11:56:47.523650 8, 0xFFFF, sum = 0
5435 11:56:47.526960 9, 0xFFFF, sum = 0
5436 11:56:47.527039 10, 0x0, sum = 1
5437 11:56:47.529979 11, 0x0, sum = 2
5438 11:56:47.530056 12, 0x0, sum = 3
5439 11:56:47.533670 13, 0x0, sum = 4
5440 11:56:47.533746 best_step = 11
5441 11:56:47.533808
5442 11:56:47.533888 ==
5443 11:56:47.536646 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 11:56:47.539854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 11:56:47.543036 ==
5446 11:56:47.543115 RX Vref Scan: 0
5447 11:56:47.543193
5448 11:56:47.546872 RX Vref 0 -> 0, step: 1
5449 11:56:47.546982
5450 11:56:47.550176 RX Delay -53 -> 252, step: 4
5451 11:56:47.553664 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5452 11:56:47.556571 iDelay=199, Bit 1, Center 106 (23 ~ 190) 168
5453 11:56:47.563343 iDelay=199, Bit 2, Center 104 (19 ~ 190) 172
5454 11:56:47.566862 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5455 11:56:47.569812 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5456 11:56:47.573242 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5457 11:56:47.577096 iDelay=199, Bit 6, Center 112 (27 ~ 198) 172
5458 11:56:47.580140 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5459 11:56:47.586661 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5460 11:56:47.589840 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5461 11:56:47.593567 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5462 11:56:47.596922 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5463 11:56:47.600284 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5464 11:56:47.603384 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5465 11:56:47.609751 iDelay=199, Bit 14, Center 104 (23 ~ 186) 164
5466 11:56:47.613254 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5467 11:56:47.613334 ==
5468 11:56:47.616652 Dram Type= 6, Freq= 0, CH_0, rank 1
5469 11:56:47.619997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5470 11:56:47.620078 ==
5471 11:56:47.623247 DQS Delay:
5472 11:56:47.623343 DQS0 = 0, DQS1 = 0
5473 11:56:47.623406 DQM Delay:
5474 11:56:47.626471 DQM0 = 105, DQM1 = 94
5475 11:56:47.626552 DQ Delay:
5476 11:56:47.630490 DQ0 =104, DQ1 =106, DQ2 =104, DQ3 =102
5477 11:56:47.633564 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5478 11:56:47.636799 DQ8 =86, DQ9 =82, DQ10 =94, DQ11 =88
5479 11:56:47.639966 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5480 11:56:47.643061
5481 11:56:47.643134
5482 11:56:47.649880 [DQSOSCAuto] RK1, (LSB)MR18= 0x26fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5483 11:56:47.653005 CH0 RK1: MR19=504, MR18=26FE
5484 11:56:47.659897 CH0_RK1: MR19=0x504, MR18=0x26FE, DQSOSC=409, MR23=63, INC=64, DEC=43
5485 11:56:47.663517 [RxdqsGatingPostProcess] freq 933
5486 11:56:47.666392 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5487 11:56:47.669690 best DQS0 dly(2T, 0.5T) = (0, 10)
5488 11:56:47.673058 best DQS1 dly(2T, 0.5T) = (0, 10)
5489 11:56:47.676588 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5490 11:56:47.679754 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5491 11:56:47.683478 best DQS0 dly(2T, 0.5T) = (0, 10)
5492 11:56:47.686295 best DQS1 dly(2T, 0.5T) = (0, 10)
5493 11:56:47.689882 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5494 11:56:47.693470 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5495 11:56:47.696367 Pre-setting of DQS Precalculation
5496 11:56:47.699987 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5497 11:56:47.700067 ==
5498 11:56:47.703011 Dram Type= 6, Freq= 0, CH_1, rank 0
5499 11:56:47.706839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5500 11:56:47.709960 ==
5501 11:56:47.713010 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5502 11:56:47.720026 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5503 11:56:47.723022 [CA 0] Center 36 (6~67) winsize 62
5504 11:56:47.726682 [CA 1] Center 37 (6~68) winsize 63
5505 11:56:47.729881 [CA 2] Center 34 (4~65) winsize 62
5506 11:56:47.733009 [CA 3] Center 34 (4~65) winsize 62
5507 11:56:47.736578 [CA 4] Center 34 (4~64) winsize 61
5508 11:56:47.740081 [CA 5] Center 33 (3~64) winsize 62
5509 11:56:47.740161
5510 11:56:47.743071 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5511 11:56:47.743213
5512 11:56:47.746310 [CATrainingPosCal] consider 1 rank data
5513 11:56:47.749506 u2DelayCellTimex100 = 270/100 ps
5514 11:56:47.753268 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5515 11:56:47.756417 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5516 11:56:47.759888 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5517 11:56:47.763134 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5518 11:56:47.769493 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5519 11:56:47.773190 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5520 11:56:47.773295
5521 11:56:47.776162 CA PerBit enable=1, Macro0, CA PI delay=33
5522 11:56:47.776266
5523 11:56:47.780270 [CBTSetCACLKResult] CA Dly = 33
5524 11:56:47.780349 CS Dly: 7 (0~38)
5525 11:56:47.780412 ==
5526 11:56:47.782772 Dram Type= 6, Freq= 0, CH_1, rank 1
5527 11:56:47.789520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 11:56:47.789703 ==
5529 11:56:47.792825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5530 11:56:47.799646 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5531 11:56:47.802623 [CA 0] Center 36 (6~67) winsize 62
5532 11:56:47.806264 [CA 1] Center 37 (7~68) winsize 62
5533 11:56:47.809724 [CA 2] Center 35 (5~65) winsize 61
5534 11:56:47.812890 [CA 3] Center 34 (4~65) winsize 62
5535 11:56:47.816047 [CA 4] Center 34 (4~65) winsize 62
5536 11:56:47.819203 [CA 5] Center 33 (3~64) winsize 62
5537 11:56:47.819282
5538 11:56:47.822703 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5539 11:56:47.822783
5540 11:56:47.825858 [CATrainingPosCal] consider 2 rank data
5541 11:56:47.829402 u2DelayCellTimex100 = 270/100 ps
5542 11:56:47.832605 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5543 11:56:47.836201 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5544 11:56:47.839582 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5545 11:56:47.845756 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5546 11:56:47.848998 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5547 11:56:47.852724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5548 11:56:47.852803
5549 11:56:47.855835 CA PerBit enable=1, Macro0, CA PI delay=33
5550 11:56:47.855927
5551 11:56:47.858924 [CBTSetCACLKResult] CA Dly = 33
5552 11:56:47.859003 CS Dly: 7 (0~39)
5553 11:56:47.859066
5554 11:56:47.862627 ----->DramcWriteLeveling(PI) begin...
5555 11:56:47.865807 ==
5556 11:56:47.869077 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 11:56:47.872082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 11:56:47.872161 ==
5559 11:56:47.875849 Write leveling (Byte 0): 28 => 28
5560 11:56:47.878985 Write leveling (Byte 1): 26 => 26
5561 11:56:47.882530 DramcWriteLeveling(PI) end<-----
5562 11:56:47.882610
5563 11:56:47.882672 ==
5564 11:56:47.885673 Dram Type= 6, Freq= 0, CH_1, rank 0
5565 11:56:47.888846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5566 11:56:47.888926 ==
5567 11:56:47.892493 [Gating] SW mode calibration
5568 11:56:47.899082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5569 11:56:47.905746 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5570 11:56:47.908948 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:56:47.911860 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 11:56:47.915605 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 11:56:47.922074 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 11:56:47.925171 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5575 11:56:47.928804 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5576 11:56:47.935462 0 14 24 | B1->B0 | 3434 2d2d | 0 0 | (1 0) (0 1)
5577 11:56:47.938636 0 14 28 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (1 0)
5578 11:56:47.942484 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:56:47.948987 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 11:56:47.952352 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 11:56:47.955335 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5582 11:56:47.962216 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5583 11:56:47.965795 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5584 11:56:47.969015 0 15 24 | B1->B0 | 2b2b 3131 | 0 0 | (0 0) (0 0)
5585 11:56:47.975685 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
5586 11:56:47.978586 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:56:47.982225 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 11:56:47.989282 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 11:56:47.991876 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 11:56:47.995662 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5591 11:56:48.002285 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5592 11:56:48.005343 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5593 11:56:48.008326 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:56:48.015090 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:56:48.018767 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:56:48.021955 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:56:48.028525 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:56:48.031240 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:56:48.034771 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:56:48.041426 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:56:48.044922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:56:48.048071 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:56:48.054853 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 11:56:48.057856 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 11:56:48.061445 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5606 11:56:48.067771 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5607 11:56:48.071406 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5608 11:56:48.074481 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5609 11:56:48.081117 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5610 11:56:48.081196 Total UI for P1: 0, mck2ui 16
5611 11:56:48.084412 best dqsien dly found for B0: ( 1, 2, 24)
5612 11:56:48.091203 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5613 11:56:48.094337 Total UI for P1: 0, mck2ui 16
5614 11:56:48.098135 best dqsien dly found for B1: ( 1, 2, 26)
5615 11:56:48.101373 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5616 11:56:48.104508 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5617 11:56:48.104635
5618 11:56:48.107558 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5619 11:56:48.110872 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5620 11:56:48.114505 [Gating] SW calibration Done
5621 11:56:48.114585 ==
5622 11:56:48.117833 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 11:56:48.121199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 11:56:48.121313 ==
5625 11:56:48.124739 RX Vref Scan: 0
5626 11:56:48.124818
5627 11:56:48.127704 RX Vref 0 -> 0, step: 1
5628 11:56:48.127784
5629 11:56:48.127846 RX Delay -80 -> 252, step: 8
5630 11:56:48.134369 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5631 11:56:48.138000 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5632 11:56:48.141898 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5633 11:56:48.144823 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5634 11:56:48.147950 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5635 11:56:48.151224 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5636 11:56:48.157759 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5637 11:56:48.161256 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5638 11:56:48.165136 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5639 11:56:48.167760 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5640 11:56:48.171311 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5641 11:56:48.175077 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5642 11:56:48.181519 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5643 11:56:48.184835 iDelay=208, Bit 13, Center 107 (24 ~ 191) 168
5644 11:56:48.187686 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5645 11:56:48.191402 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5646 11:56:48.191482 ==
5647 11:56:48.194617 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 11:56:48.198276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 11:56:48.201462 ==
5650 11:56:48.201541 DQS Delay:
5651 11:56:48.201643 DQS0 = 0, DQS1 = 0
5652 11:56:48.204440 DQM Delay:
5653 11:56:48.204548 DQM0 = 103, DQM1 = 98
5654 11:56:48.207886 DQ Delay:
5655 11:56:48.211378 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5656 11:56:48.214411 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5657 11:56:48.217716 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5658 11:56:48.221444 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =103
5659 11:56:48.221564
5660 11:56:48.221655
5661 11:56:48.221714 ==
5662 11:56:48.224553 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 11:56:48.227629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 11:56:48.227709 ==
5665 11:56:48.227782
5666 11:56:48.227842
5667 11:56:48.231079 TX Vref Scan disable
5668 11:56:48.231158 == TX Byte 0 ==
5669 11:56:48.237748 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5670 11:56:48.241275 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5671 11:56:48.244505 == TX Byte 1 ==
5672 11:56:48.247893 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5673 11:56:48.251001 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5674 11:56:48.251119 ==
5675 11:56:48.254287 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 11:56:48.257891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 11:56:48.257971 ==
5678 11:56:48.261152
5679 11:56:48.261231
5680 11:56:48.261294 TX Vref Scan disable
5681 11:56:48.264432 == TX Byte 0 ==
5682 11:56:48.267510 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5683 11:56:48.274009 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5684 11:56:48.274089 == TX Byte 1 ==
5685 11:56:48.277474 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5686 11:56:48.284093 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5687 11:56:48.284174
5688 11:56:48.284236 [DATLAT]
5689 11:56:48.284295 Freq=933, CH1 RK0
5690 11:56:48.284352
5691 11:56:48.287494 DATLAT Default: 0xd
5692 11:56:48.287572 0, 0xFFFF, sum = 0
5693 11:56:48.290930 1, 0xFFFF, sum = 0
5694 11:56:48.291010 2, 0xFFFF, sum = 0
5695 11:56:48.294705 3, 0xFFFF, sum = 0
5696 11:56:48.294786 4, 0xFFFF, sum = 0
5697 11:56:48.297755 5, 0xFFFF, sum = 0
5698 11:56:48.301207 6, 0xFFFF, sum = 0
5699 11:56:48.301287 7, 0xFFFF, sum = 0
5700 11:56:48.304521 8, 0xFFFF, sum = 0
5701 11:56:48.304627 9, 0xFFFF, sum = 0
5702 11:56:48.307451 10, 0x0, sum = 1
5703 11:56:48.307531 11, 0x0, sum = 2
5704 11:56:48.307595 12, 0x0, sum = 3
5705 11:56:48.311222 13, 0x0, sum = 4
5706 11:56:48.311302 best_step = 11
5707 11:56:48.311376
5708 11:56:48.311439 ==
5709 11:56:48.314667 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 11:56:48.321493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 11:56:48.321627 ==
5712 11:56:48.321731 RX Vref Scan: 1
5713 11:56:48.321795
5714 11:56:48.324402 RX Vref 0 -> 0, step: 1
5715 11:56:48.324481
5716 11:56:48.327523 RX Delay -45 -> 252, step: 4
5717 11:56:48.327603
5718 11:56:48.331175 Set Vref, RX VrefLevel [Byte0]: 55
5719 11:56:48.334668 [Byte1]: 53
5720 11:56:48.334748
5721 11:56:48.337899 Final RX Vref Byte 0 = 55 to rank0
5722 11:56:48.341235 Final RX Vref Byte 1 = 53 to rank0
5723 11:56:48.344139 Final RX Vref Byte 0 = 55 to rank1
5724 11:56:48.347514 Final RX Vref Byte 1 = 53 to rank1==
5725 11:56:48.351489 Dram Type= 6, Freq= 0, CH_1, rank 0
5726 11:56:48.354539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5727 11:56:48.354634 ==
5728 11:56:48.357875 DQS Delay:
5729 11:56:48.357954 DQS0 = 0, DQS1 = 0
5730 11:56:48.361262 DQM Delay:
5731 11:56:48.361342 DQM0 = 103, DQM1 = 99
5732 11:56:48.361404 DQ Delay:
5733 11:56:48.364429 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5734 11:56:48.367961 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5735 11:56:48.371442 DQ8 =90, DQ9 =92, DQ10 =98, DQ11 =92
5736 11:56:48.374189 DQ12 =104, DQ13 =104, DQ14 =106, DQ15 =106
5737 11:56:48.378045
5738 11:56:48.378123
5739 11:56:48.384665 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b33, (MSB)MR19= 0x505, tDQSOscB0 = 405 ps tDQSOscB1 = 413 ps
5740 11:56:48.387348 CH1 RK0: MR19=505, MR18=1B33
5741 11:56:48.394260 CH1_RK0: MR19=0x505, MR18=0x1B33, DQSOSC=405, MR23=63, INC=66, DEC=44
5742 11:56:48.394342
5743 11:56:48.397792 ----->DramcWriteLeveling(PI) begin...
5744 11:56:48.397904 ==
5745 11:56:48.400794 Dram Type= 6, Freq= 0, CH_1, rank 1
5746 11:56:48.404032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5747 11:56:48.404115 ==
5748 11:56:48.407411 Write leveling (Byte 0): 26 => 26
5749 11:56:48.411195 Write leveling (Byte 1): 28 => 28
5750 11:56:48.414148 DramcWriteLeveling(PI) end<-----
5751 11:56:48.414229
5752 11:56:48.414292 ==
5753 11:56:48.417824 Dram Type= 6, Freq= 0, CH_1, rank 1
5754 11:56:48.421051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 11:56:48.421132 ==
5756 11:56:48.424113 [Gating] SW mode calibration
5757 11:56:48.430671 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5758 11:56:48.437431 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5759 11:56:48.440669 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 11:56:48.444139 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 11:56:48.450521 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 11:56:48.453679 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 11:56:48.457464 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5764 11:56:48.463721 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5765 11:56:48.467424 0 14 24 | B1->B0 | 2f2f 3333 | 1 1 | (0 0) (1 0)
5766 11:56:48.470987 0 14 28 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5767 11:56:48.477143 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 11:56:48.480518 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 11:56:48.483565 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 11:56:48.490696 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 11:56:48.494058 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5772 11:56:48.497156 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5773 11:56:48.503987 0 15 24 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
5774 11:56:48.506827 0 15 28 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
5775 11:56:48.510333 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 11:56:48.516877 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 11:56:48.520282 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 11:56:48.523555 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 11:56:48.530166 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5780 11:56:48.533447 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5781 11:56:48.537041 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5782 11:56:48.543684 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5783 11:56:48.546773 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:56:48.550604 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:56:48.557268 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:56:48.560027 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:56:48.563815 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:56:48.566834 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:56:48.573452 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:56:48.576927 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:56:48.579929 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 11:56:48.586908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 11:56:48.589995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 11:56:48.593803 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 11:56:48.600087 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5796 11:56:48.603469 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5797 11:56:48.606652 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5798 11:56:48.613748 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 11:56:48.613833 Total UI for P1: 0, mck2ui 16
5800 11:56:48.620336 best dqsien dly found for B0: ( 1, 2, 24)
5801 11:56:48.620417 Total UI for P1: 0, mck2ui 16
5802 11:56:48.626976 best dqsien dly found for B1: ( 1, 2, 24)
5803 11:56:48.630146 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5804 11:56:48.633308 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5805 11:56:48.633414
5806 11:56:48.636699 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5807 11:56:48.640041 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5808 11:56:48.643840 [Gating] SW calibration Done
5809 11:56:48.643920 ==
5810 11:56:48.647029 Dram Type= 6, Freq= 0, CH_1, rank 1
5811 11:56:48.649911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5812 11:56:48.649992 ==
5813 11:56:48.653422 RX Vref Scan: 0
5814 11:56:48.653527
5815 11:56:48.653648 RX Vref 0 -> 0, step: 1
5816 11:56:48.653710
5817 11:56:48.656703 RX Delay -80 -> 252, step: 8
5818 11:56:48.660319 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5819 11:56:48.666955 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5820 11:56:48.670086 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5821 11:56:48.673480 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5822 11:56:48.676715 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5823 11:56:48.679668 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5824 11:56:48.683504 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5825 11:56:48.690328 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5826 11:56:48.693341 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5827 11:56:48.696439 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5828 11:56:48.699621 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5829 11:56:48.703177 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5830 11:56:48.706661 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5831 11:56:48.712950 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5832 11:56:48.716324 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5833 11:56:48.719708 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5834 11:56:48.719788 ==
5835 11:56:48.722803 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 11:56:48.726282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 11:56:48.726364 ==
5838 11:56:48.729823 DQS Delay:
5839 11:56:48.729904 DQS0 = 0, DQS1 = 0
5840 11:56:48.733384 DQM Delay:
5841 11:56:48.733463 DQM0 = 102, DQM1 = 99
5842 11:56:48.733526 DQ Delay:
5843 11:56:48.736026 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =95
5844 11:56:48.739855 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5845 11:56:48.743071 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5846 11:56:48.749542 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5847 11:56:48.749686
5848 11:56:48.749777
5849 11:56:48.749862 ==
5850 11:56:48.752787 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 11:56:48.756464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 11:56:48.756545 ==
5853 11:56:48.756609
5854 11:56:48.756667
5855 11:56:48.759380 TX Vref Scan disable
5856 11:56:48.759461 == TX Byte 0 ==
5857 11:56:48.766032 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5858 11:56:48.769305 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5859 11:56:48.769410 == TX Byte 1 ==
5860 11:56:48.776371 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5861 11:56:48.779759 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5862 11:56:48.779839 ==
5863 11:56:48.782783 Dram Type= 6, Freq= 0, CH_1, rank 1
5864 11:56:48.785846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5865 11:56:48.785927 ==
5866 11:56:48.785990
5867 11:56:48.786050
5868 11:56:48.789451 TX Vref Scan disable
5869 11:56:48.793107 == TX Byte 0 ==
5870 11:56:48.796255 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5871 11:56:48.799362 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5872 11:56:48.802972 == TX Byte 1 ==
5873 11:56:48.805932 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5874 11:56:48.809449 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5875 11:56:48.809554
5876 11:56:48.812976 [DATLAT]
5877 11:56:48.813057 Freq=933, CH1 RK1
5878 11:56:48.813119
5879 11:56:48.816138 DATLAT Default: 0xb
5880 11:56:48.816217 0, 0xFFFF, sum = 0
5881 11:56:48.820001 1, 0xFFFF, sum = 0
5882 11:56:48.820096 2, 0xFFFF, sum = 0
5883 11:56:48.823187 3, 0xFFFF, sum = 0
5884 11:56:48.823268 4, 0xFFFF, sum = 0
5885 11:56:48.826518 5, 0xFFFF, sum = 0
5886 11:56:48.826601 6, 0xFFFF, sum = 0
5887 11:56:48.829467 7, 0xFFFF, sum = 0
5888 11:56:48.829596 8, 0xFFFF, sum = 0
5889 11:56:48.833237 9, 0xFFFF, sum = 0
5890 11:56:48.833319 10, 0x0, sum = 1
5891 11:56:48.835885 11, 0x0, sum = 2
5892 11:56:48.835993 12, 0x0, sum = 3
5893 11:56:48.839285 13, 0x0, sum = 4
5894 11:56:48.839394 best_step = 11
5895 11:56:48.839485
5896 11:56:48.839571 ==
5897 11:56:48.842997 Dram Type= 6, Freq= 0, CH_1, rank 1
5898 11:56:48.849585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5899 11:56:48.849682 ==
5900 11:56:48.849752 RX Vref Scan: 0
5901 11:56:48.849817
5902 11:56:48.852659 RX Vref 0 -> 0, step: 1
5903 11:56:48.852739
5904 11:56:48.856006 RX Delay -45 -> 252, step: 4
5905 11:56:48.859187 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5906 11:56:48.862700 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5907 11:56:48.869035 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5908 11:56:48.872288 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5909 11:56:48.875680 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5910 11:56:48.878975 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5911 11:56:48.882154 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5912 11:56:48.889052 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5913 11:56:48.892389 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5914 11:56:48.895503 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5915 11:56:48.899207 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5916 11:56:48.902378 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5917 11:56:48.909108 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5918 11:56:48.912317 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5919 11:56:48.915498 iDelay=203, Bit 14, Center 106 (23 ~ 190) 168
5920 11:56:48.919101 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5921 11:56:48.919181 ==
5922 11:56:48.922185 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 11:56:48.929023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 11:56:48.929121 ==
5925 11:56:48.929201 DQS Delay:
5926 11:56:48.929260 DQS0 = 0, DQS1 = 0
5927 11:56:48.932077 DQM Delay:
5928 11:56:48.932157 DQM0 = 105, DQM1 = 100
5929 11:56:48.935587 DQ Delay:
5930 11:56:48.938946 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5931 11:56:48.941932 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5932 11:56:48.945368 DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94
5933 11:56:48.948369 DQ12 =110, DQ13 =106, DQ14 =106, DQ15 =108
5934 11:56:48.948449
5935 11:56:48.948512
5936 11:56:48.955418 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5937 11:56:48.958746 CH1 RK1: MR19=505, MR18=2C00
5938 11:56:48.965161 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5939 11:56:48.968764 [RxdqsGatingPostProcess] freq 933
5940 11:56:48.975530 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5941 11:56:48.978848 best DQS0 dly(2T, 0.5T) = (0, 10)
5942 11:56:48.978929 best DQS1 dly(2T, 0.5T) = (0, 10)
5943 11:56:48.981809 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5944 11:56:48.985023 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5945 11:56:48.988653 best DQS0 dly(2T, 0.5T) = (0, 10)
5946 11:56:48.992236 best DQS1 dly(2T, 0.5T) = (0, 10)
5947 11:56:48.994949 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5948 11:56:48.998720 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5949 11:56:49.001556 Pre-setting of DQS Precalculation
5950 11:56:49.008251 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5951 11:56:49.015362 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5952 11:56:49.021525 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5953 11:56:49.021663
5954 11:56:49.021748
5955 11:56:49.025383 [Calibration Summary] 1866 Mbps
5956 11:56:49.025488 CH 0, Rank 0
5957 11:56:49.028460 SW Impedance : PASS
5958 11:56:49.031582 DUTY Scan : NO K
5959 11:56:49.031681 ZQ Calibration : PASS
5960 11:56:49.035461 Jitter Meter : NO K
5961 11:56:49.038618 CBT Training : PASS
5962 11:56:49.038716 Write leveling : PASS
5963 11:56:49.041501 RX DQS gating : PASS
5964 11:56:49.044772 RX DQ/DQS(RDDQC) : PASS
5965 11:56:49.044847 TX DQ/DQS : PASS
5966 11:56:49.048008 RX DATLAT : PASS
5967 11:56:49.048109 RX DQ/DQS(Engine): PASS
5968 11:56:49.051603 TX OE : NO K
5969 11:56:49.051676 All Pass.
5970 11:56:49.051741
5971 11:56:49.054857 CH 0, Rank 1
5972 11:56:49.054925 SW Impedance : PASS
5973 11:56:49.058286 DUTY Scan : NO K
5974 11:56:49.061552 ZQ Calibration : PASS
5975 11:56:49.061646 Jitter Meter : NO K
5976 11:56:49.064890 CBT Training : PASS
5977 11:56:49.068003 Write leveling : PASS
5978 11:56:49.068078 RX DQS gating : PASS
5979 11:56:49.071301 RX DQ/DQS(RDDQC) : PASS
5980 11:56:49.075098 TX DQ/DQS : PASS
5981 11:56:49.075200 RX DATLAT : PASS
5982 11:56:49.077911 RX DQ/DQS(Engine): PASS
5983 11:56:49.081725 TX OE : NO K
5984 11:56:49.081801 All Pass.
5985 11:56:49.081867
5986 11:56:49.081926 CH 1, Rank 0
5987 11:56:49.084983 SW Impedance : PASS
5988 11:56:49.088368 DUTY Scan : NO K
5989 11:56:49.088466 ZQ Calibration : PASS
5990 11:56:49.091374 Jitter Meter : NO K
5991 11:56:49.095363 CBT Training : PASS
5992 11:56:49.095438 Write leveling : PASS
5993 11:56:49.098008 RX DQS gating : PASS
5994 11:56:49.098086 RX DQ/DQS(RDDQC) : PASS
5995 11:56:49.101711 TX DQ/DQS : PASS
5996 11:56:49.104867 RX DATLAT : PASS
5997 11:56:49.104944 RX DQ/DQS(Engine): PASS
5998 11:56:49.108047 TX OE : NO K
5999 11:56:49.108129 All Pass.
6000 11:56:49.108193
6001 11:56:49.111140 CH 1, Rank 1
6002 11:56:49.111212 SW Impedance : PASS
6003 11:56:49.114707 DUTY Scan : NO K
6004 11:56:49.117803 ZQ Calibration : PASS
6005 11:56:49.117884 Jitter Meter : NO K
6006 11:56:49.121563 CBT Training : PASS
6007 11:56:49.125015 Write leveling : PASS
6008 11:56:49.125096 RX DQS gating : PASS
6009 11:56:49.128044 RX DQ/DQS(RDDQC) : PASS
6010 11:56:49.131174 TX DQ/DQS : PASS
6011 11:56:49.131313 RX DATLAT : PASS
6012 11:56:49.134730 RX DQ/DQS(Engine): PASS
6013 11:56:49.137831 TX OE : NO K
6014 11:56:49.137911 All Pass.
6015 11:56:49.137974
6016 11:56:49.138033 DramC Write-DBI off
6017 11:56:49.141004 PER_BANK_REFRESH: Hybrid Mode
6018 11:56:49.144609 TX_TRACKING: ON
6019 11:56:49.150947 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6020 11:56:49.154617 [FAST_K] Save calibration result to emmc
6021 11:56:49.161298 dramc_set_vcore_voltage set vcore to 650000
6022 11:56:49.161378 Read voltage for 400, 6
6023 11:56:49.164332 Vio18 = 0
6024 11:56:49.164412 Vcore = 650000
6025 11:56:49.164476 Vdram = 0
6026 11:56:49.168320 Vddq = 0
6027 11:56:49.168400 Vmddr = 0
6028 11:56:49.171034 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6029 11:56:49.178086 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6030 11:56:49.181447 MEM_TYPE=3, freq_sel=20
6031 11:56:49.181553 sv_algorithm_assistance_LP4_800
6032 11:56:49.187762 ============ PULL DRAM RESETB DOWN ============
6033 11:56:49.190891 ========== PULL DRAM RESETB DOWN end =========
6034 11:56:49.194464 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6035 11:56:49.197878 ===================================
6036 11:56:49.201067 LPDDR4 DRAM CONFIGURATION
6037 11:56:49.204257 ===================================
6038 11:56:49.207446 EX_ROW_EN[0] = 0x0
6039 11:56:49.207526 EX_ROW_EN[1] = 0x0
6040 11:56:49.211195 LP4Y_EN = 0x0
6041 11:56:49.211277 WORK_FSP = 0x0
6042 11:56:49.214497 WL = 0x2
6043 11:56:49.214577 RL = 0x2
6044 11:56:49.217392 BL = 0x2
6045 11:56:49.217519 RPST = 0x0
6046 11:56:49.220911 RD_PRE = 0x0
6047 11:56:49.221014 WR_PRE = 0x1
6048 11:56:49.224780 WR_PST = 0x0
6049 11:56:49.224862 DBI_WR = 0x0
6050 11:56:49.227637 DBI_RD = 0x0
6051 11:56:49.230685 OTF = 0x1
6052 11:56:49.230759 ===================================
6053 11:56:49.234476 ===================================
6054 11:56:49.237788 ANA top config
6055 11:56:49.240717 ===================================
6056 11:56:49.244137 DLL_ASYNC_EN = 0
6057 11:56:49.244219 ALL_SLAVE_EN = 1
6058 11:56:49.247529 NEW_RANK_MODE = 1
6059 11:56:49.250566 DLL_IDLE_MODE = 1
6060 11:56:49.253826 LP45_APHY_COMB_EN = 1
6061 11:56:49.257503 TX_ODT_DIS = 1
6062 11:56:49.257646 NEW_8X_MODE = 1
6063 11:56:49.260726 ===================================
6064 11:56:49.263737 ===================================
6065 11:56:49.267368 data_rate = 800
6066 11:56:49.270913 CKR = 1
6067 11:56:49.273993 DQ_P2S_RATIO = 4
6068 11:56:49.277453 ===================================
6069 11:56:49.280787 CA_P2S_RATIO = 4
6070 11:56:49.283908 DQ_CA_OPEN = 0
6071 11:56:49.283989 DQ_SEMI_OPEN = 1
6072 11:56:49.287015 CA_SEMI_OPEN = 1
6073 11:56:49.290791 CA_FULL_RATE = 0
6074 11:56:49.293675 DQ_CKDIV4_EN = 0
6075 11:56:49.296856 CA_CKDIV4_EN = 1
6076 11:56:49.300680 CA_PREDIV_EN = 0
6077 11:56:49.300762 PH8_DLY = 0
6078 11:56:49.304270 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6079 11:56:49.306821 DQ_AAMCK_DIV = 0
6080 11:56:49.310739 CA_AAMCK_DIV = 0
6081 11:56:49.313587 CA_ADMCK_DIV = 4
6082 11:56:49.316831 DQ_TRACK_CA_EN = 0
6083 11:56:49.316912 CA_PICK = 800
6084 11:56:49.320272 CA_MCKIO = 400
6085 11:56:49.323907 MCKIO_SEMI = 400
6086 11:56:49.326792 PLL_FREQ = 3016
6087 11:56:49.330364 DQ_UI_PI_RATIO = 32
6088 11:56:49.333281 CA_UI_PI_RATIO = 32
6089 11:56:49.336901 ===================================
6090 11:56:49.340251 ===================================
6091 11:56:49.343303 memory_type:LPDDR4
6092 11:56:49.343383 GP_NUM : 10
6093 11:56:49.346549 SRAM_EN : 1
6094 11:56:49.346657 MD32_EN : 0
6095 11:56:49.350410 ===================================
6096 11:56:49.353467 [ANA_INIT] >>>>>>>>>>>>>>
6097 11:56:49.356627 <<<<<< [CONFIGURE PHASE]: ANA_TX
6098 11:56:49.360460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6099 11:56:49.363568 ===================================
6100 11:56:49.366672 data_rate = 800,PCW = 0X7400
6101 11:56:49.370435 ===================================
6102 11:56:49.373182 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6103 11:56:49.376484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 11:56:49.390089 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6105 11:56:49.393405 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6106 11:56:49.397119 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6107 11:56:49.400143 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6108 11:56:49.403706 [ANA_INIT] flow start
6109 11:56:49.406899 [ANA_INIT] PLL >>>>>>>>
6110 11:56:49.406979 [ANA_INIT] PLL <<<<<<<<
6111 11:56:49.410012 [ANA_INIT] MIDPI >>>>>>>>
6112 11:56:49.413201 [ANA_INIT] MIDPI <<<<<<<<
6113 11:56:49.413280 [ANA_INIT] DLL >>>>>>>>
6114 11:56:49.417161 [ANA_INIT] flow end
6115 11:56:49.420155 ============ LP4 DIFF to SE enter ============
6116 11:56:49.423308 ============ LP4 DIFF to SE exit ============
6117 11:56:49.426592 [ANA_INIT] <<<<<<<<<<<<<
6118 11:56:49.429920 [Flow] Enable top DCM control >>>>>
6119 11:56:49.433045 [Flow] Enable top DCM control <<<<<
6120 11:56:49.436615 Enable DLL master slave shuffle
6121 11:56:49.443644 ==============================================================
6122 11:56:49.443768 Gating Mode config
6123 11:56:49.450055 ==============================================================
6124 11:56:49.450157 Config description:
6125 11:56:49.460054 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6126 11:56:49.466390 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6127 11:56:49.472964 SELPH_MODE 0: By rank 1: By Phase
6128 11:56:49.479653 ==============================================================
6129 11:56:49.479734 GAT_TRACK_EN = 0
6130 11:56:49.482978 RX_GATING_MODE = 2
6131 11:56:49.486282 RX_GATING_TRACK_MODE = 2
6132 11:56:49.490275 SELPH_MODE = 1
6133 11:56:49.492996 PICG_EARLY_EN = 1
6134 11:56:49.496112 VALID_LAT_VALUE = 1
6135 11:56:49.502879 ==============================================================
6136 11:56:49.505939 Enter into Gating configuration >>>>
6137 11:56:49.509484 Exit from Gating configuration <<<<
6138 11:56:49.513112 Enter into DVFS_PRE_config >>>>>
6139 11:56:49.522893 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6140 11:56:49.526333 Exit from DVFS_PRE_config <<<<<
6141 11:56:49.529393 Enter into PICG configuration >>>>
6142 11:56:49.532454 Exit from PICG configuration <<<<
6143 11:56:49.535849 [RX_INPUT] configuration >>>>>
6144 11:56:49.535929 [RX_INPUT] configuration <<<<<
6145 11:56:49.542659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6146 11:56:49.549403 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6147 11:56:49.552423 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6148 11:56:49.559282 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6149 11:56:49.565678 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6150 11:56:49.572789 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6151 11:56:49.575507 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6152 11:56:49.578762 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6153 11:56:49.585732 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6154 11:56:49.589097 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6155 11:56:49.592218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6156 11:56:49.599164 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6157 11:56:49.602085 ===================================
6158 11:56:49.602165 LPDDR4 DRAM CONFIGURATION
6159 11:56:49.605757 ===================================
6160 11:56:49.609112 EX_ROW_EN[0] = 0x0
6161 11:56:49.609192 EX_ROW_EN[1] = 0x0
6162 11:56:49.612860 LP4Y_EN = 0x0
6163 11:56:49.612941 WORK_FSP = 0x0
6164 11:56:49.615575 WL = 0x2
6165 11:56:49.619112 RL = 0x2
6166 11:56:49.619197 BL = 0x2
6167 11:56:49.622567 RPST = 0x0
6168 11:56:49.622647 RD_PRE = 0x0
6169 11:56:49.625728 WR_PRE = 0x1
6170 11:56:49.625808 WR_PST = 0x0
6171 11:56:49.628793 DBI_WR = 0x0
6172 11:56:49.628873 DBI_RD = 0x0
6173 11:56:49.632012 OTF = 0x1
6174 11:56:49.635803 ===================================
6175 11:56:49.638925 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6176 11:56:49.642017 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6177 11:56:49.649090 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6178 11:56:49.649192 ===================================
6179 11:56:49.652423 LPDDR4 DRAM CONFIGURATION
6180 11:56:49.655416 ===================================
6181 11:56:49.658946 EX_ROW_EN[0] = 0x10
6182 11:56:49.659026 EX_ROW_EN[1] = 0x0
6183 11:56:49.662119 LP4Y_EN = 0x0
6184 11:56:49.662198 WORK_FSP = 0x0
6185 11:56:49.665289 WL = 0x2
6186 11:56:49.665369 RL = 0x2
6187 11:56:49.668984 BL = 0x2
6188 11:56:49.669064 RPST = 0x0
6189 11:56:49.672126 RD_PRE = 0x0
6190 11:56:49.675300 WR_PRE = 0x1
6191 11:56:49.675380 WR_PST = 0x0
6192 11:56:49.679200 DBI_WR = 0x0
6193 11:56:49.679280 DBI_RD = 0x0
6194 11:56:49.682529 OTF = 0x1
6195 11:56:49.685456 ===================================
6196 11:56:49.688721 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6197 11:56:49.693790 nWR fixed to 30
6198 11:56:49.697474 [ModeRegInit_LP4] CH0 RK0
6199 11:56:49.697585 [ModeRegInit_LP4] CH0 RK1
6200 11:56:49.700574 [ModeRegInit_LP4] CH1 RK0
6201 11:56:49.704289 [ModeRegInit_LP4] CH1 RK1
6202 11:56:49.704386 match AC timing 19
6203 11:56:49.710915 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6204 11:56:49.713866 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6205 11:56:49.717187 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6206 11:56:49.723593 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6207 11:56:49.727267 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6208 11:56:49.727364 ==
6209 11:56:49.730501 Dram Type= 6, Freq= 0, CH_0, rank 0
6210 11:56:49.733604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6211 11:56:49.733691 ==
6212 11:56:49.740484 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6213 11:56:49.747102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6214 11:56:49.750530 [CA 0] Center 36 (8~64) winsize 57
6215 11:56:49.753747 [CA 1] Center 36 (8~64) winsize 57
6216 11:56:49.756875 [CA 2] Center 36 (8~64) winsize 57
6217 11:56:49.756973 [CA 3] Center 36 (8~64) winsize 57
6218 11:56:49.760498 [CA 4] Center 36 (8~64) winsize 57
6219 11:56:49.763582 [CA 5] Center 36 (8~64) winsize 57
6220 11:56:49.763654
6221 11:56:49.770431 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6222 11:56:49.770507
6223 11:56:49.773789 [CATrainingPosCal] consider 1 rank data
6224 11:56:49.776760 u2DelayCellTimex100 = 270/100 ps
6225 11:56:49.780587 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:56:49.783584 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 11:56:49.787300 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 11:56:49.790290 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 11:56:49.793795 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 11:56:49.797266 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6231 11:56:49.797362
6232 11:56:49.800225 CA PerBit enable=1, Macro0, CA PI delay=36
6233 11:56:49.800322
6234 11:56:49.803852 [CBTSetCACLKResult] CA Dly = 36
6235 11:56:49.806980 CS Dly: 1 (0~32)
6236 11:56:49.807068 ==
6237 11:56:49.810231 Dram Type= 6, Freq= 0, CH_0, rank 1
6238 11:56:49.813689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6239 11:56:49.813762 ==
6240 11:56:49.820540 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6241 11:56:49.823699 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6242 11:56:49.826722 [CA 0] Center 36 (8~64) winsize 57
6243 11:56:49.830471 [CA 1] Center 36 (8~64) winsize 57
6244 11:56:49.833443 [CA 2] Center 36 (8~64) winsize 57
6245 11:56:49.836730 [CA 3] Center 36 (8~64) winsize 57
6246 11:56:49.839933 [CA 4] Center 36 (8~64) winsize 57
6247 11:56:49.843353 [CA 5] Center 36 (8~64) winsize 57
6248 11:56:49.843426
6249 11:56:49.846637 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6250 11:56:49.846712
6251 11:56:49.850478 [CATrainingPosCal] consider 2 rank data
6252 11:56:49.853238 u2DelayCellTimex100 = 270/100 ps
6253 11:56:49.856780 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:56:49.859853 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 11:56:49.866995 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 11:56:49.870139 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 11:56:49.873880 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 11:56:49.876557 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6259 11:56:49.876658
6260 11:56:49.879882 CA PerBit enable=1, Macro0, CA PI delay=36
6261 11:56:49.879979
6262 11:56:49.883376 [CBTSetCACLKResult] CA Dly = 36
6263 11:56:49.883450 CS Dly: 1 (0~32)
6264 11:56:49.883511
6265 11:56:49.886622 ----->DramcWriteLeveling(PI) begin...
6266 11:56:49.886695 ==
6267 11:56:49.889819 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 11:56:49.896744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 11:56:49.896850 ==
6270 11:56:49.899852 Write leveling (Byte 0): 40 => 8
6271 11:56:49.903177 Write leveling (Byte 1): 40 => 8
6272 11:56:49.903261 DramcWriteLeveling(PI) end<-----
6273 11:56:49.903325
6274 11:56:49.906672 ==
6275 11:56:49.910132 Dram Type= 6, Freq= 0, CH_0, rank 0
6276 11:56:49.913520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6277 11:56:49.913621 ==
6278 11:56:49.916654 [Gating] SW mode calibration
6279 11:56:49.923358 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6280 11:56:49.926556 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6281 11:56:49.933694 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 11:56:49.936701 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6283 11:56:49.939830 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 11:56:49.946727 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 11:56:49.949703 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 11:56:49.953257 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 11:56:49.959618 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 11:56:49.963260 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6289 11:56:49.966603 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6290 11:56:49.969667 Total UI for P1: 0, mck2ui 16
6291 11:56:49.973107 best dqsien dly found for B0: ( 0, 14, 24)
6292 11:56:49.976236 Total UI for P1: 0, mck2ui 16
6293 11:56:49.979920 best dqsien dly found for B1: ( 0, 14, 24)
6294 11:56:49.982939 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6295 11:56:49.986452 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6296 11:56:49.986541
6297 11:56:49.992951 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 11:56:49.996313 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6299 11:56:49.996409 [Gating] SW calibration Done
6300 11:56:49.999889 ==
6301 11:56:49.999984 Dram Type= 6, Freq= 0, CH_0, rank 0
6302 11:56:50.006612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6303 11:56:50.006681 ==
6304 11:56:50.006744 RX Vref Scan: 0
6305 11:56:50.006801
6306 11:56:50.009449 RX Vref 0 -> 0, step: 1
6307 11:56:50.009540
6308 11:56:50.012698 RX Delay -410 -> 252, step: 16
6309 11:56:50.015905 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6310 11:56:50.019836 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6311 11:56:50.026356 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6312 11:56:50.029118 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6313 11:56:50.033366 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6314 11:56:50.039471 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6315 11:56:50.042927 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6316 11:56:50.046366 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6317 11:56:50.049450 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6318 11:56:50.055613 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6319 11:56:50.058987 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6320 11:56:50.062598 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6321 11:56:50.065769 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6322 11:56:50.071952 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6323 11:56:50.075463 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6324 11:56:50.078590 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6325 11:56:50.078674 ==
6326 11:56:50.082090 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 11:56:50.085731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 11:56:50.088998 ==
6329 11:56:50.089077 DQS Delay:
6330 11:56:50.089140 DQS0 = 27, DQS1 = 35
6331 11:56:50.092532 DQM Delay:
6332 11:56:50.092626 DQM0 = 10, DQM1 = 11
6333 11:56:50.095510 DQ Delay:
6334 11:56:50.095589 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6335 11:56:50.099194 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6336 11:56:50.102176 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6337 11:56:50.105771 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6338 11:56:50.105850
6339 11:56:50.105911
6340 11:56:50.109194 ==
6341 11:56:50.112216 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:56:50.115761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:56:50.115842 ==
6344 11:56:50.115905
6345 11:56:50.115964
6346 11:56:50.118708 TX Vref Scan disable
6347 11:56:50.118788 == TX Byte 0 ==
6348 11:56:50.121987 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:56:50.128864 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:56:50.128946 == TX Byte 1 ==
6351 11:56:50.131894 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 11:56:50.138795 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 11:56:50.138877 ==
6354 11:56:50.141849 Dram Type= 6, Freq= 0, CH_0, rank 0
6355 11:56:50.145069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6356 11:56:50.145150 ==
6357 11:56:50.145214
6358 11:56:50.145272
6359 11:56:50.148619 TX Vref Scan disable
6360 11:56:50.148698 == TX Byte 0 ==
6361 11:56:50.151888 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6362 11:56:50.158852 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6363 11:56:50.158936 == TX Byte 1 ==
6364 11:56:50.162243 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6365 11:56:50.168601 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6366 11:56:50.168682
6367 11:56:50.168746 [DATLAT]
6368 11:56:50.168805 Freq=400, CH0 RK0
6369 11:56:50.168862
6370 11:56:50.171760 DATLAT Default: 0xf
6371 11:56:50.174882 0, 0xFFFF, sum = 0
6372 11:56:50.174963 1, 0xFFFF, sum = 0
6373 11:56:50.178752 2, 0xFFFF, sum = 0
6374 11:56:50.178833 3, 0xFFFF, sum = 0
6375 11:56:50.181871 4, 0xFFFF, sum = 0
6376 11:56:50.181952 5, 0xFFFF, sum = 0
6377 11:56:50.184865 6, 0xFFFF, sum = 0
6378 11:56:50.184946 7, 0xFFFF, sum = 0
6379 11:56:50.188583 8, 0xFFFF, sum = 0
6380 11:56:50.188665 9, 0xFFFF, sum = 0
6381 11:56:50.192259 10, 0xFFFF, sum = 0
6382 11:56:50.192340 11, 0xFFFF, sum = 0
6383 11:56:50.195097 12, 0xFFFF, sum = 0
6384 11:56:50.195178 13, 0x0, sum = 1
6385 11:56:50.198509 14, 0x0, sum = 2
6386 11:56:50.198624 15, 0x0, sum = 3
6387 11:56:50.201702 16, 0x0, sum = 4
6388 11:56:50.201783 best_step = 14
6389 11:56:50.201846
6390 11:56:50.201905 ==
6391 11:56:50.204970 Dram Type= 6, Freq= 0, CH_0, rank 0
6392 11:56:50.208330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6393 11:56:50.211850 ==
6394 11:56:50.211930 RX Vref Scan: 1
6395 11:56:50.211992
6396 11:56:50.214955 RX Vref 0 -> 0, step: 1
6397 11:56:50.215036
6398 11:56:50.218743 RX Delay -311 -> 252, step: 8
6399 11:56:50.218823
6400 11:56:50.221839 Set Vref, RX VrefLevel [Byte0]: 61
6401 11:56:50.224934 [Byte1]: 50
6402 11:56:50.225014
6403 11:56:50.228497 Final RX Vref Byte 0 = 61 to rank0
6404 11:56:50.231815 Final RX Vref Byte 1 = 50 to rank0
6405 11:56:50.235066 Final RX Vref Byte 0 = 61 to rank1
6406 11:56:50.238743 Final RX Vref Byte 1 = 50 to rank1==
6407 11:56:50.241558 Dram Type= 6, Freq= 0, CH_0, rank 0
6408 11:56:50.244846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6409 11:56:50.244926 ==
6410 11:56:50.248683 DQS Delay:
6411 11:56:50.248762 DQS0 = 24, DQS1 = 36
6412 11:56:50.251545 DQM Delay:
6413 11:56:50.251625 DQM0 = 7, DQM1 = 13
6414 11:56:50.251688 DQ Delay:
6415 11:56:50.255648 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6416 11:56:50.258702 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6417 11:56:50.261697 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6418 11:56:50.265079 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6419 11:56:50.265159
6420 11:56:50.265222
6421 11:56:50.274688 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb7, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 384 ps
6422 11:56:50.274769 CH0 RK0: MR19=C0C, MR18=CBB7
6423 11:56:50.281513 CH0_RK0: MR19=0xC0C, MR18=0xCBB7, DQSOSC=384, MR23=63, INC=400, DEC=267
6424 11:56:50.281628 ==
6425 11:56:50.284640 Dram Type= 6, Freq= 0, CH_0, rank 1
6426 11:56:50.291342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6427 11:56:50.291422 ==
6428 11:56:50.291485 [Gating] SW mode calibration
6429 11:56:50.301305 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6430 11:56:50.304616 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6431 11:56:50.311241 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 11:56:50.314652 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6433 11:56:50.318354 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 11:56:50.321212 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 11:56:50.327910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 11:56:50.331371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 11:56:50.334983 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 11:56:50.341285 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6439 11:56:50.344984 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6440 11:56:50.347796 Total UI for P1: 0, mck2ui 16
6441 11:56:50.350909 best dqsien dly found for B0: ( 0, 14, 24)
6442 11:56:50.354789 Total UI for P1: 0, mck2ui 16
6443 11:56:50.358200 best dqsien dly found for B1: ( 0, 14, 24)
6444 11:56:50.361250 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6445 11:56:50.364324 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6446 11:56:50.364404
6447 11:56:50.367974 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 11:56:50.370827 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6449 11:56:50.374618 [Gating] SW calibration Done
6450 11:56:50.374698 ==
6451 11:56:50.377533 Dram Type= 6, Freq= 0, CH_0, rank 1
6452 11:56:50.384487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6453 11:56:50.384568 ==
6454 11:56:50.384632 RX Vref Scan: 0
6455 11:56:50.384691
6456 11:56:50.387775 RX Vref 0 -> 0, step: 1
6457 11:56:50.387863
6458 11:56:50.390818 RX Delay -410 -> 252, step: 16
6459 11:56:50.394490 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6460 11:56:50.397707 iDelay=230, Bit 1, Center -11 (-234 ~ 213) 448
6461 11:56:50.401440 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6462 11:56:50.407663 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6463 11:56:50.410900 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6464 11:56:50.414488 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6465 11:56:50.418065 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6466 11:56:50.424189 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6467 11:56:50.427442 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6468 11:56:50.431030 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6469 11:56:50.434169 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6470 11:56:50.441258 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6471 11:56:50.444158 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6472 11:56:50.447285 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6473 11:56:50.454289 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6474 11:56:50.457779 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6475 11:56:50.457852 ==
6476 11:56:50.461111 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 11:56:50.464722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 11:56:50.464805 ==
6479 11:56:50.464869 DQS Delay:
6480 11:56:50.468062 DQS0 = 27, DQS1 = 35
6481 11:56:50.468142 DQM Delay:
6482 11:56:50.471049 DQM0 = 12, DQM1 = 11
6483 11:56:50.471130 DQ Delay:
6484 11:56:50.474487 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6485 11:56:50.477776 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6486 11:56:50.480825 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6487 11:56:50.484401 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6488 11:56:50.484481
6489 11:56:50.484544
6490 11:56:50.484638 ==
6491 11:56:50.487287 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 11:56:50.491090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:56:50.491172 ==
6494 11:56:50.491235
6495 11:56:50.494175
6496 11:56:50.494255 TX Vref Scan disable
6497 11:56:50.497827 == TX Byte 0 ==
6498 11:56:50.500792 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6499 11:56:50.503985 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6500 11:56:50.507408 == TX Byte 1 ==
6501 11:56:50.510894 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6502 11:56:50.514108 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6503 11:56:50.514216 ==
6504 11:56:50.517408 Dram Type= 6, Freq= 0, CH_0, rank 1
6505 11:56:50.521148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6506 11:56:50.521229 ==
6507 11:56:50.521293
6508 11:56:50.524288
6509 11:56:50.524367 TX Vref Scan disable
6510 11:56:50.527416 == TX Byte 0 ==
6511 11:56:50.531124 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6512 11:56:50.534307 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6513 11:56:50.537392 == TX Byte 1 ==
6514 11:56:50.540772 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6515 11:56:50.544018 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6516 11:56:50.544127
6517 11:56:50.544219 [DATLAT]
6518 11:56:50.547576 Freq=400, CH0 RK1
6519 11:56:50.547659
6520 11:56:50.547723 DATLAT Default: 0xe
6521 11:56:50.551091 0, 0xFFFF, sum = 0
6522 11:56:50.551199 1, 0xFFFF, sum = 0
6523 11:56:50.554365 2, 0xFFFF, sum = 0
6524 11:56:50.554446 3, 0xFFFF, sum = 0
6525 11:56:50.557821 4, 0xFFFF, sum = 0
6526 11:56:50.557903 5, 0xFFFF, sum = 0
6527 11:56:50.561063 6, 0xFFFF, sum = 0
6528 11:56:50.564235 7, 0xFFFF, sum = 0
6529 11:56:50.564317 8, 0xFFFF, sum = 0
6530 11:56:50.567426 9, 0xFFFF, sum = 0
6531 11:56:50.567508 10, 0xFFFF, sum = 0
6532 11:56:50.571146 11, 0xFFFF, sum = 0
6533 11:56:50.571245 12, 0xFFFF, sum = 0
6534 11:56:50.574300 13, 0x0, sum = 1
6535 11:56:50.574374 14, 0x0, sum = 2
6536 11:56:50.577520 15, 0x0, sum = 3
6537 11:56:50.577627 16, 0x0, sum = 4
6538 11:56:50.580804 best_step = 14
6539 11:56:50.580884
6540 11:56:50.580995 ==
6541 11:56:50.584010 Dram Type= 6, Freq= 0, CH_0, rank 1
6542 11:56:50.587407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6543 11:56:50.587488 ==
6544 11:56:50.587552 RX Vref Scan: 0
6545 11:56:50.587611
6546 11:56:50.590474 RX Vref 0 -> 0, step: 1
6547 11:56:50.590554
6548 11:56:50.594277 RX Delay -311 -> 252, step: 8
6549 11:56:50.601504 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6550 11:56:50.604699 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6551 11:56:50.607694 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6552 11:56:50.611000 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6553 11:56:50.617833 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6554 11:56:50.620911 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6555 11:56:50.624642 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6556 11:56:50.627947 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6557 11:56:50.634350 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6558 11:56:50.637620 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6559 11:56:50.641294 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6560 11:56:50.644526 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6561 11:56:50.651031 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6562 11:56:50.654662 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6563 11:56:50.657630 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6564 11:56:50.661190 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6565 11:56:50.664359 ==
6566 11:56:50.667370 Dram Type= 6, Freq= 0, CH_0, rank 1
6567 11:56:50.671119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6568 11:56:50.671200 ==
6569 11:56:50.671263 DQS Delay:
6570 11:56:50.674476 DQS0 = 24, DQS1 = 32
6571 11:56:50.674556 DQM Delay:
6572 11:56:50.677406 DQM0 = 9, DQM1 = 9
6573 11:56:50.677486 DQ Delay:
6574 11:56:50.681292 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6575 11:56:50.684110 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6576 11:56:50.687996 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6577 11:56:50.690569 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6578 11:56:50.690648
6579 11:56:50.690711
6580 11:56:50.697327 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe5f, (MSB)MR19= 0xc0c, tDQSOscB0 = 397 ps tDQSOscB1 = 386 ps
6581 11:56:50.700914 CH0 RK1: MR19=C0C, MR18=BE5F
6582 11:56:50.707337 CH0_RK1: MR19=0xC0C, MR18=0xBE5F, DQSOSC=386, MR23=63, INC=396, DEC=264
6583 11:56:50.710657 [RxdqsGatingPostProcess] freq 400
6584 11:56:50.714057 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6585 11:56:50.717620 best DQS0 dly(2T, 0.5T) = (0, 10)
6586 11:56:50.720821 best DQS1 dly(2T, 0.5T) = (0, 10)
6587 11:56:50.724587 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6588 11:56:50.727646 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6589 11:56:50.730755 best DQS0 dly(2T, 0.5T) = (0, 10)
6590 11:56:50.734152 best DQS1 dly(2T, 0.5T) = (0, 10)
6591 11:56:50.737509 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6592 11:56:50.740497 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6593 11:56:50.743935 Pre-setting of DQS Precalculation
6594 11:56:50.747752 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6595 11:56:50.747833 ==
6596 11:56:50.750627 Dram Type= 6, Freq= 0, CH_1, rank 0
6597 11:56:50.757624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 11:56:50.757734 ==
6599 11:56:50.761072 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6600 11:56:50.768052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6601 11:56:50.771039 [CA 0] Center 36 (8~64) winsize 57
6602 11:56:50.774311 [CA 1] Center 36 (8~64) winsize 57
6603 11:56:50.777485 [CA 2] Center 36 (8~64) winsize 57
6604 11:56:50.781046 [CA 3] Center 36 (8~64) winsize 57
6605 11:56:50.784414 [CA 4] Center 36 (8~64) winsize 57
6606 11:56:50.787639 [CA 5] Center 36 (8~64) winsize 57
6607 11:56:50.787719
6608 11:56:50.790964 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6609 11:56:50.791070
6610 11:56:50.794139 [CATrainingPosCal] consider 1 rank data
6611 11:56:50.797230 u2DelayCellTimex100 = 270/100 ps
6612 11:56:50.800340 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:56:50.804230 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 11:56:50.806944 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 11:56:50.810425 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 11:56:50.814066 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 11:56:50.816999 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6618 11:56:50.817082
6619 11:56:50.823754 CA PerBit enable=1, Macro0, CA PI delay=36
6620 11:56:50.823834
6621 11:56:50.827578 [CBTSetCACLKResult] CA Dly = 36
6622 11:56:50.827659 CS Dly: 1 (0~32)
6623 11:56:50.827724 ==
6624 11:56:50.830719 Dram Type= 6, Freq= 0, CH_1, rank 1
6625 11:56:50.834154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 11:56:50.834246 ==
6627 11:56:50.840659 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6628 11:56:50.847113 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6629 11:56:50.850755 [CA 0] Center 36 (8~64) winsize 57
6630 11:56:50.854000 [CA 1] Center 36 (8~64) winsize 57
6631 11:56:50.857100 [CA 2] Center 36 (8~64) winsize 57
6632 11:56:50.860435 [CA 3] Center 36 (8~64) winsize 57
6633 11:56:50.860516 [CA 4] Center 36 (8~64) winsize 57
6634 11:56:50.864486 [CA 5] Center 36 (8~64) winsize 57
6635 11:56:50.864566
6636 11:56:50.871090 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6637 11:56:50.871198
6638 11:56:50.873801 [CATrainingPosCal] consider 2 rank data
6639 11:56:50.877171 u2DelayCellTimex100 = 270/100 ps
6640 11:56:50.880476 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:56:50.884244 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 11:56:50.887131 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 11:56:50.890535 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 11:56:50.893701 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 11:56:50.897112 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6646 11:56:50.897191
6647 11:56:50.900640 CA PerBit enable=1, Macro0, CA PI delay=36
6648 11:56:50.900721
6649 11:56:50.903910 [CBTSetCACLKResult] CA Dly = 36
6650 11:56:50.907392 CS Dly: 1 (0~32)
6651 11:56:50.907514
6652 11:56:50.911107 ----->DramcWriteLeveling(PI) begin...
6653 11:56:50.911189 ==
6654 11:56:50.913831 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 11:56:50.917529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 11:56:50.917638 ==
6657 11:56:50.920609 Write leveling (Byte 0): 40 => 8
6658 11:56:50.923766 Write leveling (Byte 1): 40 => 8
6659 11:56:50.926964 DramcWriteLeveling(PI) end<-----
6660 11:56:50.927073
6661 11:56:50.927175 ==
6662 11:56:50.930642 Dram Type= 6, Freq= 0, CH_1, rank 0
6663 11:56:50.933534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6664 11:56:50.933664 ==
6665 11:56:50.937005 [Gating] SW mode calibration
6666 11:56:50.943732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6667 11:56:50.950603 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6668 11:56:50.953768 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 11:56:50.957332 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6670 11:56:50.964379 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 11:56:50.967627 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 11:56:50.970835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 11:56:50.977203 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 11:56:50.980389 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 11:56:50.983599 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6676 11:56:50.990568 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6677 11:56:50.990649 Total UI for P1: 0, mck2ui 16
6678 11:56:50.997449 best dqsien dly found for B0: ( 0, 14, 24)
6679 11:56:50.997554 Total UI for P1: 0, mck2ui 16
6680 11:56:51.000224 best dqsien dly found for B1: ( 0, 14, 24)
6681 11:56:51.007015 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6682 11:56:51.010709 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6683 11:56:51.010791
6684 11:56:51.014066 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 11:56:51.016957 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6686 11:56:51.020285 [Gating] SW calibration Done
6687 11:56:51.020366 ==
6688 11:56:51.023663 Dram Type= 6, Freq= 0, CH_1, rank 0
6689 11:56:51.027112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6690 11:56:51.027194 ==
6691 11:56:51.030595 RX Vref Scan: 0
6692 11:56:51.030675
6693 11:56:51.030739 RX Vref 0 -> 0, step: 1
6694 11:56:51.030798
6695 11:56:51.033772 RX Delay -410 -> 252, step: 16
6696 11:56:51.040582 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6697 11:56:51.043909 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6698 11:56:51.046713 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6699 11:56:51.050510 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6700 11:56:51.053539 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6701 11:56:51.062813 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6702 11:56:51.063616 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6703 11:56:51.066830 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6704 11:56:51.070305 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6705 11:56:51.076669 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6706 11:56:51.080779 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6707 11:56:51.083951 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6708 11:56:51.090175 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6709 11:56:51.093307 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6710 11:56:51.096548 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6711 11:56:51.099766 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6712 11:56:51.099861 ==
6713 11:56:51.103442 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 11:56:51.109742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 11:56:51.109842 ==
6716 11:56:51.109936 DQS Delay:
6717 11:56:51.113449 DQS0 = 27, DQS1 = 27
6718 11:56:51.113547 DQM Delay:
6719 11:56:51.113658 DQM0 = 11, DQM1 = 8
6720 11:56:51.116317 DQ Delay:
6721 11:56:51.120035 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6722 11:56:51.120137 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6723 11:56:51.123290 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6724 11:56:51.126704 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16
6725 11:56:51.126782
6726 11:56:51.126846
6727 11:56:51.129660 ==
6728 11:56:51.133451 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:56:51.136591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:56:51.136696 ==
6731 11:56:51.136791
6732 11:56:51.136854
6733 11:56:51.139638 TX Vref Scan disable
6734 11:56:51.139713 == TX Byte 0 ==
6735 11:56:51.143688 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:56:51.149888 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:56:51.149985 == TX Byte 1 ==
6738 11:56:51.153561 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 11:56:51.156945 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 11:56:51.159766 ==
6741 11:56:51.163662 Dram Type= 6, Freq= 0, CH_1, rank 0
6742 11:56:51.166616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6743 11:56:51.166759 ==
6744 11:56:51.166823
6745 11:56:51.166885
6746 11:56:51.169585 TX Vref Scan disable
6747 11:56:51.169697 == TX Byte 0 ==
6748 11:56:51.172952 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6749 11:56:51.179555 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6750 11:56:51.179634 == TX Byte 1 ==
6751 11:56:51.183410 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6752 11:56:51.189542 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6753 11:56:51.189638
6754 11:56:51.189723 [DATLAT]
6755 11:56:51.189784 Freq=400, CH1 RK0
6756 11:56:51.189842
6757 11:56:51.192580 DATLAT Default: 0xf
6758 11:56:51.192679 0, 0xFFFF, sum = 0
6759 11:56:51.196396 1, 0xFFFF, sum = 0
6760 11:56:51.199526 2, 0xFFFF, sum = 0
6761 11:56:51.199620 3, 0xFFFF, sum = 0
6762 11:56:51.202714 4, 0xFFFF, sum = 0
6763 11:56:51.202807 5, 0xFFFF, sum = 0
6764 11:56:51.206347 6, 0xFFFF, sum = 0
6765 11:56:51.206415 7, 0xFFFF, sum = 0
6766 11:56:51.209554 8, 0xFFFF, sum = 0
6767 11:56:51.209675 9, 0xFFFF, sum = 0
6768 11:56:51.212742 10, 0xFFFF, sum = 0
6769 11:56:51.212811 11, 0xFFFF, sum = 0
6770 11:56:51.216402 12, 0xFFFF, sum = 0
6771 11:56:51.216499 13, 0x0, sum = 1
6772 11:56:51.219546 14, 0x0, sum = 2
6773 11:56:51.219644 15, 0x0, sum = 3
6774 11:56:51.222567 16, 0x0, sum = 4
6775 11:56:51.222664 best_step = 14
6776 11:56:51.222755
6777 11:56:51.222840 ==
6778 11:56:51.226005 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 11:56:51.229322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 11:56:51.232452 ==
6781 11:56:51.232559 RX Vref Scan: 1
6782 11:56:51.232651
6783 11:56:51.236300 RX Vref 0 -> 0, step: 1
6784 11:56:51.236401
6785 11:56:51.239302 RX Delay -295 -> 252, step: 8
6786 11:56:51.239401
6787 11:56:51.242423 Set Vref, RX VrefLevel [Byte0]: 55
6788 11:56:51.246026 [Byte1]: 53
6789 11:56:51.246103
6790 11:56:51.249501 Final RX Vref Byte 0 = 55 to rank0
6791 11:56:51.253049 Final RX Vref Byte 1 = 53 to rank0
6792 11:56:51.255734 Final RX Vref Byte 0 = 55 to rank1
6793 11:56:51.259117 Final RX Vref Byte 1 = 53 to rank1==
6794 11:56:51.262363 Dram Type= 6, Freq= 0, CH_1, rank 0
6795 11:56:51.265719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6796 11:56:51.265830 ==
6797 11:56:51.268780 DQS Delay:
6798 11:56:51.268854 DQS0 = 28, DQS1 = 32
6799 11:56:51.272468 DQM Delay:
6800 11:56:51.272568 DQM0 = 9, DQM1 = 10
6801 11:56:51.272658 DQ Delay:
6802 11:56:51.275396 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6803 11:56:51.279224 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6804 11:56:51.282370 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6805 11:56:51.285476 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6806 11:56:51.285598
6807 11:56:51.285695
6808 11:56:51.295591 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc6, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6809 11:56:51.295703 CH1 RK0: MR19=C0C, MR18=8CC6
6810 11:56:51.302209 CH1_RK0: MR19=0xC0C, MR18=0x8CC6, DQSOSC=385, MR23=63, INC=398, DEC=265
6811 11:56:51.302284 ==
6812 11:56:51.305286 Dram Type= 6, Freq= 0, CH_1, rank 1
6813 11:56:51.312129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6814 11:56:51.312206 ==
6815 11:56:51.315399 [Gating] SW mode calibration
6816 11:56:51.322126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6817 11:56:51.325722 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6818 11:56:51.331913 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 11:56:51.335444 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6820 11:56:51.338687 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 11:56:51.345301 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 11:56:51.348497 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 11:56:51.352288 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 11:56:51.358552 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 11:56:51.361517 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6826 11:56:51.365387 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6827 11:56:51.368783 Total UI for P1: 0, mck2ui 16
6828 11:56:51.371914 best dqsien dly found for B0: ( 0, 14, 24)
6829 11:56:51.375065 Total UI for P1: 0, mck2ui 16
6830 11:56:51.378211 best dqsien dly found for B1: ( 0, 14, 24)
6831 11:56:51.381805 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6832 11:56:51.384925 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6833 11:56:51.384999
6834 11:56:51.388483 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 11:56:51.395541 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6836 11:56:51.395621 [Gating] SW calibration Done
6837 11:56:51.395684 ==
6838 11:56:51.398340 Dram Type= 6, Freq= 0, CH_1, rank 1
6839 11:56:51.405351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6840 11:56:51.405450 ==
6841 11:56:51.405540 RX Vref Scan: 0
6842 11:56:51.405634
6843 11:56:51.408328 RX Vref 0 -> 0, step: 1
6844 11:56:51.408400
6845 11:56:51.411946 RX Delay -410 -> 252, step: 16
6846 11:56:51.414717 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6847 11:56:51.418422 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6848 11:56:51.425261 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6849 11:56:51.428281 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6850 11:56:51.431903 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6851 11:56:51.434987 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6852 11:56:51.441817 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6853 11:56:51.444977 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6854 11:56:51.448359 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6855 11:56:51.451580 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6856 11:56:51.458234 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6857 11:56:51.461789 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6858 11:56:51.465039 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6859 11:56:51.468152 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6860 11:56:51.475131 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6861 11:56:51.478379 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6862 11:56:51.478477 ==
6863 11:56:51.481548 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 11:56:51.485141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 11:56:51.485247 ==
6866 11:56:51.488122 DQS Delay:
6867 11:56:51.488222 DQS0 = 35, DQS1 = 35
6868 11:56:51.488310 DQM Delay:
6869 11:56:51.491625 DQM0 = 18, DQM1 = 14
6870 11:56:51.491727 DQ Delay:
6871 11:56:51.495380 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6872 11:56:51.498470 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6873 11:56:51.501727 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6874 11:56:51.505490 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6875 11:56:51.505612
6876 11:56:51.505685
6877 11:56:51.505761 ==
6878 11:56:51.508062 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 11:56:51.515034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:56:51.515141 ==
6881 11:56:51.515233
6882 11:56:51.515322
6883 11:56:51.515412 TX Vref Scan disable
6884 11:56:51.517977 == TX Byte 0 ==
6885 11:56:51.521388 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6886 11:56:51.524922 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6887 11:56:51.527843 == TX Byte 1 ==
6888 11:56:51.531265 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6889 11:56:51.534458 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6890 11:56:51.534563 ==
6891 11:56:51.538063 Dram Type= 6, Freq= 0, CH_1, rank 1
6892 11:56:51.544908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6893 11:56:51.545012 ==
6894 11:56:51.545113
6895 11:56:51.545201
6896 11:56:51.545293 TX Vref Scan disable
6897 11:56:51.548299 == TX Byte 0 ==
6898 11:56:51.551517 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6899 11:56:51.554584 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6900 11:56:51.558091 == TX Byte 1 ==
6901 11:56:51.561414 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6902 11:56:51.564916 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6903 11:56:51.565018
6904 11:56:51.568153 [DATLAT]
6905 11:56:51.568261 Freq=400, CH1 RK1
6906 11:56:51.568360
6907 11:56:51.571076 DATLAT Default: 0xe
6908 11:56:51.571175 0, 0xFFFF, sum = 0
6909 11:56:51.574329 1, 0xFFFF, sum = 0
6910 11:56:51.574437 2, 0xFFFF, sum = 0
6911 11:56:51.578100 3, 0xFFFF, sum = 0
6912 11:56:51.578198 4, 0xFFFF, sum = 0
6913 11:56:51.581377 5, 0xFFFF, sum = 0
6914 11:56:51.581460 6, 0xFFFF, sum = 0
6915 11:56:51.584674 7, 0xFFFF, sum = 0
6916 11:56:51.584749 8, 0xFFFF, sum = 0
6917 11:56:51.587595 9, 0xFFFF, sum = 0
6918 11:56:51.587691 10, 0xFFFF, sum = 0
6919 11:56:51.591500 11, 0xFFFF, sum = 0
6920 11:56:51.594326 12, 0xFFFF, sum = 0
6921 11:56:51.594427 13, 0x0, sum = 1
6922 11:56:51.594518 14, 0x0, sum = 2
6923 11:56:51.597491 15, 0x0, sum = 3
6924 11:56:51.597568 16, 0x0, sum = 4
6925 11:56:51.601193 best_step = 14
6926 11:56:51.601283
6927 11:56:51.601367 ==
6928 11:56:51.604218 Dram Type= 6, Freq= 0, CH_1, rank 1
6929 11:56:51.608411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6930 11:56:51.608515 ==
6931 11:56:51.611426 RX Vref Scan: 0
6932 11:56:51.611529
6933 11:56:51.611616 RX Vref 0 -> 0, step: 1
6934 11:56:51.611705
6935 11:56:51.614518 RX Delay -311 -> 252, step: 8
6936 11:56:51.622533 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6937 11:56:51.625997 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6938 11:56:51.629263 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6939 11:56:51.633110 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6940 11:56:51.639022 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6941 11:56:51.642439 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6942 11:56:51.645724 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6943 11:56:51.648858 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6944 11:56:51.655801 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6945 11:56:51.659010 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6946 11:56:51.662099 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6947 11:56:51.665734 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6948 11:56:51.671868 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6949 11:56:51.675393 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6950 11:56:51.679166 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6951 11:56:51.685360 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6952 11:56:51.685434 ==
6953 11:56:51.689244 Dram Type= 6, Freq= 0, CH_1, rank 1
6954 11:56:51.692376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6955 11:56:51.692473 ==
6956 11:56:51.692561 DQS Delay:
6957 11:56:51.695444 DQS0 = 28, DQS1 = 32
6958 11:56:51.695540 DQM Delay:
6959 11:56:51.698621 DQM0 = 11, DQM1 = 12
6960 11:56:51.698777 DQ Delay:
6961 11:56:51.702342 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6962 11:56:51.705430 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
6963 11:56:51.709037 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6964 11:56:51.712293 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6965 11:56:51.712393
6966 11:56:51.712482
6967 11:56:51.718586 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6968 11:56:51.722327 CH1 RK1: MR19=C0C, MR18=C455
6969 11:56:51.728630 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
6970 11:56:51.732700 [RxdqsGatingPostProcess] freq 400
6971 11:56:51.738676 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6972 11:56:51.738757 best DQS0 dly(2T, 0.5T) = (0, 10)
6973 11:56:51.742060 best DQS1 dly(2T, 0.5T) = (0, 10)
6974 11:56:51.745406 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6975 11:56:51.748572 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6976 11:56:51.752454 best DQS0 dly(2T, 0.5T) = (0, 10)
6977 11:56:51.755221 best DQS1 dly(2T, 0.5T) = (0, 10)
6978 11:56:51.758356 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6979 11:56:51.761822 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6980 11:56:51.764999 Pre-setting of DQS Precalculation
6981 11:56:51.768288 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6982 11:56:51.778356 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6983 11:56:51.784988 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6984 11:56:51.785108
6985 11:56:51.785211
6986 11:56:51.788194 [Calibration Summary] 800 Mbps
6987 11:56:51.788267 CH 0, Rank 0
6988 11:56:51.791480 SW Impedance : PASS
6989 11:56:51.791568 DUTY Scan : NO K
6990 11:56:51.794872 ZQ Calibration : PASS
6991 11:56:51.798488 Jitter Meter : NO K
6992 11:56:51.798563 CBT Training : PASS
6993 11:56:51.801517 Write leveling : PASS
6994 11:56:51.805164 RX DQS gating : PASS
6995 11:56:51.805272 RX DQ/DQS(RDDQC) : PASS
6996 11:56:51.808306 TX DQ/DQS : PASS
6997 11:56:51.811375 RX DATLAT : PASS
6998 11:56:51.811448 RX DQ/DQS(Engine): PASS
6999 11:56:51.815316 TX OE : NO K
7000 11:56:51.815412 All Pass.
7001 11:56:51.815502
7002 11:56:51.818416 CH 0, Rank 1
7003 11:56:51.818488 SW Impedance : PASS
7004 11:56:51.821887 DUTY Scan : NO K
7005 11:56:51.825407 ZQ Calibration : PASS
7006 11:56:51.825479 Jitter Meter : NO K
7007 11:56:51.828459 CBT Training : PASS
7008 11:56:51.831811 Write leveling : NO K
7009 11:56:51.831916 RX DQS gating : PASS
7010 11:56:51.834678 RX DQ/DQS(RDDQC) : PASS
7011 11:56:51.834777 TX DQ/DQS : PASS
7012 11:56:51.838738 RX DATLAT : PASS
7013 11:56:51.841683 RX DQ/DQS(Engine): PASS
7014 11:56:51.841753 TX OE : NO K
7015 11:56:51.844748 All Pass.
7016 11:56:51.844865
7017 11:56:51.844957 CH 1, Rank 0
7018 11:56:51.847931 SW Impedance : PASS
7019 11:56:51.848030 DUTY Scan : NO K
7020 11:56:51.851729 ZQ Calibration : PASS
7021 11:56:51.854864 Jitter Meter : NO K
7022 11:56:51.854960 CBT Training : PASS
7023 11:56:51.858348 Write leveling : PASS
7024 11:56:51.861349 RX DQS gating : PASS
7025 11:56:51.861424 RX DQ/DQS(RDDQC) : PASS
7026 11:56:51.864368 TX DQ/DQS : PASS
7027 11:56:51.868264 RX DATLAT : PASS
7028 11:56:51.868365 RX DQ/DQS(Engine): PASS
7029 11:56:51.871281 TX OE : NO K
7030 11:56:51.871350 All Pass.
7031 11:56:51.871410
7032 11:56:51.875050 CH 1, Rank 1
7033 11:56:51.875148 SW Impedance : PASS
7034 11:56:51.878005 DUTY Scan : NO K
7035 11:56:51.881275 ZQ Calibration : PASS
7036 11:56:51.881350 Jitter Meter : NO K
7037 11:56:51.884595 CBT Training : PASS
7038 11:56:51.887828 Write leveling : NO K
7039 11:56:51.887901 RX DQS gating : PASS
7040 11:56:51.891525 RX DQ/DQS(RDDQC) : PASS
7041 11:56:51.891600 TX DQ/DQS : PASS
7042 11:56:51.894335 RX DATLAT : PASS
7043 11:56:51.897903 RX DQ/DQS(Engine): PASS
7044 11:56:51.898000 TX OE : NO K
7045 11:56:51.901335 All Pass.
7046 11:56:51.901433
7047 11:56:51.901541 DramC Write-DBI off
7048 11:56:51.904426 PER_BANK_REFRESH: Hybrid Mode
7049 11:56:51.907703 TX_TRACKING: ON
7050 11:56:51.914415 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7051 11:56:51.917863 [FAST_K] Save calibration result to emmc
7052 11:56:51.921018 dramc_set_vcore_voltage set vcore to 725000
7053 11:56:51.924475 Read voltage for 1600, 0
7054 11:56:51.924548 Vio18 = 0
7055 11:56:51.928017 Vcore = 725000
7056 11:56:51.928091 Vdram = 0
7057 11:56:51.928164 Vddq = 0
7058 11:56:51.931426 Vmddr = 0
7059 11:56:51.934412 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7060 11:56:51.941027 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7061 11:56:51.941104 MEM_TYPE=3, freq_sel=13
7062 11:56:51.945144 sv_algorithm_assistance_LP4_3733
7063 11:56:51.951190 ============ PULL DRAM RESETB DOWN ============
7064 11:56:51.954662 ========== PULL DRAM RESETB DOWN end =========
7065 11:56:51.957741 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7066 11:56:51.960930 ===================================
7067 11:56:51.964178 LPDDR4 DRAM CONFIGURATION
7068 11:56:51.967689 ===================================
7069 11:56:51.971050 EX_ROW_EN[0] = 0x0
7070 11:56:51.971119 EX_ROW_EN[1] = 0x0
7071 11:56:51.974316 LP4Y_EN = 0x0
7072 11:56:51.974409 WORK_FSP = 0x1
7073 11:56:51.977431 WL = 0x5
7074 11:56:51.977523 RL = 0x5
7075 11:56:51.981042 BL = 0x2
7076 11:56:51.981108 RPST = 0x0
7077 11:56:51.984155 RD_PRE = 0x0
7078 11:56:51.984235 WR_PRE = 0x1
7079 11:56:51.987876 WR_PST = 0x1
7080 11:56:51.987950 DBI_WR = 0x0
7081 11:56:51.990928 DBI_RD = 0x0
7082 11:56:51.991000 OTF = 0x1
7083 11:56:51.994370 ===================================
7084 11:56:51.997489 ===================================
7085 11:56:52.000687 ANA top config
7086 11:56:52.003891 ===================================
7087 11:56:52.007655 DLL_ASYNC_EN = 0
7088 11:56:52.007755 ALL_SLAVE_EN = 0
7089 11:56:52.010771 NEW_RANK_MODE = 1
7090 11:56:52.014501 DLL_IDLE_MODE = 1
7091 11:56:52.017547 LP45_APHY_COMB_EN = 1
7092 11:56:52.017682 TX_ODT_DIS = 0
7093 11:56:52.020649 NEW_8X_MODE = 1
7094 11:56:52.024254 ===================================
7095 11:56:52.027238 ===================================
7096 11:56:52.030547 data_rate = 3200
7097 11:56:52.034000 CKR = 1
7098 11:56:52.037435 DQ_P2S_RATIO = 8
7099 11:56:52.040456 ===================================
7100 11:56:52.043708 CA_P2S_RATIO = 8
7101 11:56:52.043837 DQ_CA_OPEN = 0
7102 11:56:52.046916 DQ_SEMI_OPEN = 0
7103 11:56:52.050606 CA_SEMI_OPEN = 0
7104 11:56:52.053822 CA_FULL_RATE = 0
7105 11:56:52.056964 DQ_CKDIV4_EN = 0
7106 11:56:52.060153 CA_CKDIV4_EN = 0
7107 11:56:52.060232 CA_PREDIV_EN = 0
7108 11:56:52.063982 PH8_DLY = 12
7109 11:56:52.067238 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7110 11:56:52.070318 DQ_AAMCK_DIV = 4
7111 11:56:52.073497 CA_AAMCK_DIV = 4
7112 11:56:52.077087 CA_ADMCK_DIV = 4
7113 11:56:52.077205 DQ_TRACK_CA_EN = 0
7114 11:56:52.080671 CA_PICK = 1600
7115 11:56:52.083862 CA_MCKIO = 1600
7116 11:56:52.086755 MCKIO_SEMI = 0
7117 11:56:52.089969 PLL_FREQ = 3068
7118 11:56:52.093989 DQ_UI_PI_RATIO = 32
7119 11:56:52.097159 CA_UI_PI_RATIO = 0
7120 11:56:52.100542 ===================================
7121 11:56:52.103358 ===================================
7122 11:56:52.103433 memory_type:LPDDR4
7123 11:56:52.106828 GP_NUM : 10
7124 11:56:52.110460 SRAM_EN : 1
7125 11:56:52.110532 MD32_EN : 0
7126 11:56:52.113700 ===================================
7127 11:56:52.116936 [ANA_INIT] >>>>>>>>>>>>>>
7128 11:56:52.120346 <<<<<< [CONFIGURE PHASE]: ANA_TX
7129 11:56:52.123467 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7130 11:56:52.127332 ===================================
7131 11:56:52.130136 data_rate = 3200,PCW = 0X7600
7132 11:56:52.133330 ===================================
7133 11:56:52.137086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7134 11:56:52.139958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 11:56:52.146882 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7136 11:56:52.150492 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7137 11:56:52.153767 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7138 11:56:52.156980 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7139 11:56:52.160118 [ANA_INIT] flow start
7140 11:56:52.163712 [ANA_INIT] PLL >>>>>>>>
7141 11:56:52.163815 [ANA_INIT] PLL <<<<<<<<
7142 11:56:52.167283 [ANA_INIT] MIDPI >>>>>>>>
7143 11:56:52.170149 [ANA_INIT] MIDPI <<<<<<<<
7144 11:56:52.170247 [ANA_INIT] DLL >>>>>>>>
7145 11:56:52.173493 [ANA_INIT] DLL <<<<<<<<
7146 11:56:52.176894 [ANA_INIT] flow end
7147 11:56:52.180227 ============ LP4 DIFF to SE enter ============
7148 11:56:52.183428 ============ LP4 DIFF to SE exit ============
7149 11:56:52.187130 [ANA_INIT] <<<<<<<<<<<<<
7150 11:56:52.190172 [Flow] Enable top DCM control >>>>>
7151 11:56:52.193302 [Flow] Enable top DCM control <<<<<
7152 11:56:52.197039 Enable DLL master slave shuffle
7153 11:56:52.200213 ==============================================================
7154 11:56:52.203376 Gating Mode config
7155 11:56:52.209974 ==============================================================
7156 11:56:52.210049 Config description:
7157 11:56:52.220101 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7158 11:56:52.227065 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7159 11:56:52.230026 SELPH_MODE 0: By rank 1: By Phase
7160 11:56:52.237159 ==============================================================
7161 11:56:52.240423 GAT_TRACK_EN = 1
7162 11:56:52.243452 RX_GATING_MODE = 2
7163 11:56:52.246808 RX_GATING_TRACK_MODE = 2
7164 11:56:52.250075 SELPH_MODE = 1
7165 11:56:52.253846 PICG_EARLY_EN = 1
7166 11:56:52.257043 VALID_LAT_VALUE = 1
7167 11:56:52.260276 ==============================================================
7168 11:56:52.263243 Enter into Gating configuration >>>>
7169 11:56:52.266571 Exit from Gating configuration <<<<
7170 11:56:52.270426 Enter into DVFS_PRE_config >>>>>
7171 11:56:52.280482 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7172 11:56:52.283409 Exit from DVFS_PRE_config <<<<<
7173 11:56:52.286989 Enter into PICG configuration >>>>
7174 11:56:52.290321 Exit from PICG configuration <<<<
7175 11:56:52.293697 [RX_INPUT] configuration >>>>>
7176 11:56:52.297125 [RX_INPUT] configuration <<<<<
7177 11:56:52.303556 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7178 11:56:52.306737 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7179 11:56:52.313775 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7180 11:56:52.320060 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7181 11:56:52.327004 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7182 11:56:52.333765 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7183 11:56:52.336655 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7184 11:56:52.340416 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7185 11:56:52.343175 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7186 11:56:52.349918 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7187 11:56:52.353369 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7188 11:56:52.356551 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7189 11:56:52.360117 ===================================
7190 11:56:52.363123 LPDDR4 DRAM CONFIGURATION
7191 11:56:52.366982 ===================================
7192 11:56:52.367068 EX_ROW_EN[0] = 0x0
7193 11:56:52.369770 EX_ROW_EN[1] = 0x0
7194 11:56:52.369842 LP4Y_EN = 0x0
7195 11:56:52.373665 WORK_FSP = 0x1
7196 11:56:52.376621 WL = 0x5
7197 11:56:52.376741 RL = 0x5
7198 11:56:52.379788 BL = 0x2
7199 11:56:52.379884 RPST = 0x0
7200 11:56:52.382959 RD_PRE = 0x0
7201 11:56:52.383029 WR_PRE = 0x1
7202 11:56:52.386862 WR_PST = 0x1
7203 11:56:52.386933 DBI_WR = 0x0
7204 11:56:52.390021 DBI_RD = 0x0
7205 11:56:52.390118 OTF = 0x1
7206 11:56:52.393021 ===================================
7207 11:56:52.396481 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7208 11:56:52.403318 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7209 11:56:52.406281 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7210 11:56:52.409771 ===================================
7211 11:56:52.413112 LPDDR4 DRAM CONFIGURATION
7212 11:56:52.416518 ===================================
7213 11:56:52.416623 EX_ROW_EN[0] = 0x10
7214 11:56:52.419711 EX_ROW_EN[1] = 0x0
7215 11:56:52.419816 LP4Y_EN = 0x0
7216 11:56:52.423366 WORK_FSP = 0x1
7217 11:56:52.423483 WL = 0x5
7218 11:56:52.426227 RL = 0x5
7219 11:56:52.426329 BL = 0x2
7220 11:56:52.429798 RPST = 0x0
7221 11:56:52.432929 RD_PRE = 0x0
7222 11:56:52.433024 WR_PRE = 0x1
7223 11:56:52.436102 WR_PST = 0x1
7224 11:56:52.436198 DBI_WR = 0x0
7225 11:56:52.439803 DBI_RD = 0x0
7226 11:56:52.439903 OTF = 0x1
7227 11:56:52.442939 ===================================
7228 11:56:52.449734 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7229 11:56:52.449838 ==
7230 11:56:52.453228 Dram Type= 6, Freq= 0, CH_0, rank 0
7231 11:56:52.456399 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7232 11:56:52.456510 ==
7233 11:56:52.460045 [Duty_Offset_Calibration]
7234 11:56:52.460143 B0:2 B1:1 CA:1
7235 11:56:52.460242
7236 11:56:52.463363 [DutyScan_Calibration_Flow] k_type=0
7237 11:56:52.474356
7238 11:56:52.474460 ==CLK 0==
7239 11:56:52.477746 Final CLK duty delay cell = 0
7240 11:56:52.481286 [0] MAX Duty = 5187%(X100), DQS PI = 22
7241 11:56:52.484596 [0] MIN Duty = 4876%(X100), DQS PI = 48
7242 11:56:52.487658 [0] AVG Duty = 5031%(X100)
7243 11:56:52.487765
7244 11:56:52.490871 CH0 CLK Duty spec in!! Max-Min= 311%
7245 11:56:52.494704 [DutyScan_Calibration_Flow] ====Done====
7246 11:56:52.494813
7247 11:56:52.497565 [DutyScan_Calibration_Flow] k_type=1
7248 11:56:52.514090
7249 11:56:52.514187 ==DQS 0 ==
7250 11:56:52.516897 Final DQS duty delay cell = -4
7251 11:56:52.520415 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7252 11:56:52.523457 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7253 11:56:52.527024 [-4] AVG Duty = 4891%(X100)
7254 11:56:52.527125
7255 11:56:52.527215 ==DQS 1 ==
7256 11:56:52.530247 Final DQS duty delay cell = 0
7257 11:56:52.533596 [0] MAX Duty = 5187%(X100), DQS PI = 4
7258 11:56:52.536878 [0] MIN Duty = 5031%(X100), DQS PI = 54
7259 11:56:52.539970 [0] AVG Duty = 5109%(X100)
7260 11:56:52.540076
7261 11:56:52.543463 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7262 11:56:52.543579
7263 11:56:52.546719 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7264 11:56:52.550572 [DutyScan_Calibration_Flow] ====Done====
7265 11:56:52.550714
7266 11:56:52.553644 [DutyScan_Calibration_Flow] k_type=3
7267 11:56:52.570259
7268 11:56:52.570362 ==DQM 0 ==
7269 11:56:52.573795 Final DQM duty delay cell = 0
7270 11:56:52.576830 [0] MAX Duty = 5187%(X100), DQS PI = 26
7271 11:56:52.580183 [0] MIN Duty = 4907%(X100), DQS PI = 56
7272 11:56:52.580251 [0] AVG Duty = 5047%(X100)
7273 11:56:52.583503
7274 11:56:52.583572 ==DQM 1 ==
7275 11:56:52.586777 Final DQM duty delay cell = -4
7276 11:56:52.590442 [-4] MAX Duty = 4938%(X100), DQS PI = 0
7277 11:56:52.593621 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7278 11:56:52.596871 [-4] AVG Duty = 4875%(X100)
7279 11:56:52.596966
7280 11:56:52.600499 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7281 11:56:52.600594
7282 11:56:52.603522 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7283 11:56:52.606977 [DutyScan_Calibration_Flow] ====Done====
7284 11:56:52.607068
7285 11:56:52.610460 [DutyScan_Calibration_Flow] k_type=2
7286 11:56:52.627616
7287 11:56:52.627715 ==DQ 0 ==
7288 11:56:52.631001 Final DQ duty delay cell = 0
7289 11:56:52.634842 [0] MAX Duty = 5062%(X100), DQS PI = 24
7290 11:56:52.637727 [0] MIN Duty = 4907%(X100), DQS PI = 0
7291 11:56:52.637805 [0] AVG Duty = 4984%(X100)
7292 11:56:52.637869
7293 11:56:52.641254 ==DQ 1 ==
7294 11:56:52.644220 Final DQ duty delay cell = 0
7295 11:56:52.647819 [0] MAX Duty = 5156%(X100), DQS PI = 22
7296 11:56:52.650644 [0] MIN Duty = 4938%(X100), DQS PI = 34
7297 11:56:52.650748 [0] AVG Duty = 5047%(X100)
7298 11:56:52.650840
7299 11:56:52.654686 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7300 11:56:52.654786
7301 11:56:52.660926 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7302 11:56:52.663935 [DutyScan_Calibration_Flow] ====Done====
7303 11:56:52.664007 ==
7304 11:56:52.667556 Dram Type= 6, Freq= 0, CH_1, rank 0
7305 11:56:52.670784 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7306 11:56:52.670860 ==
7307 11:56:52.673994 [Duty_Offset_Calibration]
7308 11:56:52.674077 B0:1 B1:0 CA:0
7309 11:56:52.674139
7310 11:56:52.677671 [DutyScan_Calibration_Flow] k_type=0
7311 11:56:52.686747
7312 11:56:52.686824 ==CLK 0==
7313 11:56:52.690398 Final CLK duty delay cell = -4
7314 11:56:52.693521 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7315 11:56:52.697230 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7316 11:56:52.700357 [-4] AVG Duty = 4922%(X100)
7317 11:56:52.700459
7318 11:56:52.703677 CH1 CLK Duty spec in!! Max-Min= 156%
7319 11:56:52.706728 [DutyScan_Calibration_Flow] ====Done====
7320 11:56:52.706830
7321 11:56:52.710481 [DutyScan_Calibration_Flow] k_type=1
7322 11:56:52.726938
7323 11:56:52.727040 ==DQS 0 ==
7324 11:56:52.730951 Final DQS duty delay cell = 0
7325 11:56:52.733683 [0] MAX Duty = 5094%(X100), DQS PI = 14
7326 11:56:52.737559 [0] MIN Duty = 4844%(X100), DQS PI = 48
7327 11:56:52.740283 [0] AVG Duty = 4969%(X100)
7328 11:56:52.740382
7329 11:56:52.740481 ==DQS 1 ==
7330 11:56:52.743617 Final DQS duty delay cell = 0
7331 11:56:52.746841 [0] MAX Duty = 5249%(X100), DQS PI = 16
7332 11:56:52.750571 [0] MIN Duty = 4969%(X100), DQS PI = 6
7333 11:56:52.753736 [0] AVG Duty = 5109%(X100)
7334 11:56:52.753811
7335 11:56:52.757091 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7336 11:56:52.757189
7337 11:56:52.760351 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7338 11:56:52.763322 [DutyScan_Calibration_Flow] ====Done====
7339 11:56:52.763410
7340 11:56:52.767007 [DutyScan_Calibration_Flow] k_type=3
7341 11:56:52.783780
7342 11:56:52.783939 ==DQM 0 ==
7343 11:56:52.787207 Final DQM duty delay cell = 0
7344 11:56:52.790503 [0] MAX Duty = 5218%(X100), DQS PI = 16
7345 11:56:52.794101 [0] MIN Duty = 4969%(X100), DQS PI = 48
7346 11:56:52.797562 [0] AVG Duty = 5093%(X100)
7347 11:56:52.797743
7348 11:56:52.797846 ==DQM 1 ==
7349 11:56:52.800986 Final DQM duty delay cell = 0
7350 11:56:52.804276 [0] MAX Duty = 5093%(X100), DQS PI = 16
7351 11:56:52.807362 [0] MIN Duty = 4938%(X100), DQS PI = 6
7352 11:56:52.807460 [0] AVG Duty = 5015%(X100)
7353 11:56:52.811009
7354 11:56:52.814510 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7355 11:56:52.814581
7356 11:56:52.817364 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7357 11:56:52.821030 [DutyScan_Calibration_Flow] ====Done====
7358 11:56:52.821125
7359 11:56:52.824080 [DutyScan_Calibration_Flow] k_type=2
7360 11:56:52.839767
7361 11:56:52.839874 ==DQ 0 ==
7362 11:56:52.843566 Final DQ duty delay cell = -4
7363 11:56:52.846867 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7364 11:56:52.850358 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7365 11:56:52.853411 [-4] AVG Duty = 4968%(X100)
7366 11:56:52.853506
7367 11:56:52.853629 ==DQ 1 ==
7368 11:56:52.856405 Final DQ duty delay cell = 0
7369 11:56:52.860349 [0] MAX Duty = 5124%(X100), DQS PI = 18
7370 11:56:52.863363 [0] MIN Duty = 4938%(X100), DQS PI = 8
7371 11:56:52.866442 [0] AVG Duty = 5031%(X100)
7372 11:56:52.866511
7373 11:56:52.870219 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7374 11:56:52.870291
7375 11:56:52.873337 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7376 11:56:52.876297 [DutyScan_Calibration_Flow] ====Done====
7377 11:56:52.880039 nWR fixed to 30
7378 11:56:52.880138 [ModeRegInit_LP4] CH0 RK0
7379 11:56:52.883006 [ModeRegInit_LP4] CH0 RK1
7380 11:56:52.886502 [ModeRegInit_LP4] CH1 RK0
7381 11:56:52.889715 [ModeRegInit_LP4] CH1 RK1
7382 11:56:52.889783 match AC timing 5
7383 11:56:52.896528 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7384 11:56:52.899676 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7385 11:56:52.903376 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7386 11:56:52.910062 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7387 11:56:52.912969 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7388 11:56:52.913066 [MiockJmeterHQA]
7389 11:56:52.913162
7390 11:56:52.916421 [DramcMiockJmeter] u1RxGatingPI = 0
7391 11:56:52.919817 0 : 4252, 4027
7392 11:56:52.919906 4 : 4363, 4137
7393 11:56:52.923283 8 : 4252, 4027
7394 11:56:52.923380 12 : 4252, 4027
7395 11:56:52.923473 16 : 4366, 4139
7396 11:56:52.926214 20 : 4253, 4027
7397 11:56:52.926317 24 : 4255, 4029
7398 11:56:52.929740 28 : 4253, 4027
7399 11:56:52.929814 32 : 4363, 4138
7400 11:56:52.933303 36 : 4363, 4138
7401 11:56:52.933400 40 : 4252, 4027
7402 11:56:52.933492 44 : 4252, 4027
7403 11:56:52.936245 48 : 4253, 4027
7404 11:56:52.936340 52 : 4252, 4026
7405 11:56:52.939441 56 : 4252, 4027
7406 11:56:52.939536 60 : 4363, 4137
7407 11:56:52.943027 64 : 4250, 4027
7408 11:56:52.943122 68 : 4250, 4027
7409 11:56:52.946242 72 : 4250, 4027
7410 11:56:52.946338 76 : 4250, 4027
7411 11:56:52.949423 80 : 4250, 4027
7412 11:56:52.949518 84 : 4361, 4137
7413 11:56:52.949641 88 : 4360, 99
7414 11:56:52.953115 92 : 4249, 0
7415 11:56:52.953212 96 : 4252, 0
7416 11:56:52.953302 100 : 4361, 0
7417 11:56:52.956149 104 : 4361, 0
7418 11:56:52.956252 108 : 4250, 0
7419 11:56:52.959896 112 : 4250, 0
7420 11:56:52.959968 116 : 4250, 0
7421 11:56:52.960028 120 : 4253, 0
7422 11:56:52.963121 124 : 4250, 0
7423 11:56:52.963186 128 : 4250, 0
7424 11:56:52.966824 132 : 4253, 0
7425 11:56:52.966891 136 : 4361, 0
7426 11:56:52.966948 140 : 4361, 0
7427 11:56:52.970378 144 : 4360, 0
7428 11:56:52.970444 148 : 4249, 0
7429 11:56:52.970502 152 : 4250, 0
7430 11:56:52.973104 156 : 4250, 0
7431 11:56:52.973197 160 : 4249, 0
7432 11:56:52.976544 164 : 4250, 0
7433 11:56:52.976637 168 : 4250, 0
7434 11:56:52.976723 172 : 4253, 0
7435 11:56:52.979627 176 : 4250, 0
7436 11:56:52.979720 180 : 4250, 0
7437 11:56:52.982752 184 : 4250, 0
7438 11:56:52.982849 188 : 4360, 0
7439 11:56:52.982940 192 : 4361, 0
7440 11:56:52.986383 196 : 4360, 0
7441 11:56:52.986449 200 : 4249, 0
7442 11:56:52.989501 204 : 4250, 1151
7443 11:56:52.989596 208 : 4360, 4061
7444 11:56:52.992699 212 : 4250, 4027
7445 11:56:52.992791 216 : 4250, 4027
7446 11:56:52.992865 220 : 4361, 4137
7447 11:56:52.996362 224 : 4250, 4027
7448 11:56:52.996454 228 : 4249, 4027
7449 11:56:52.999312 232 : 4360, 4138
7450 11:56:52.999407 236 : 4250, 4027
7451 11:56:53.002949 240 : 4250, 4027
7452 11:56:53.003048 244 : 4249, 4027
7453 11:56:53.005890 248 : 4250, 4027
7454 11:56:53.005959 252 : 4250, 4027
7455 11:56:53.009554 256 : 4250, 4027
7456 11:56:53.009702 260 : 4361, 4138
7457 11:56:53.012577 264 : 4250, 4027
7458 11:56:53.012685 268 : 4250, 4027
7459 11:56:53.015833 272 : 4361, 4137
7460 11:56:53.015935 276 : 4250, 4027
7461 11:56:53.019345 280 : 4249, 4027
7462 11:56:53.019445 284 : 4360, 4138
7463 11:56:53.019541 288 : 4250, 4027
7464 11:56:53.022510 292 : 4250, 4027
7465 11:56:53.022611 296 : 4249, 4027
7466 11:56:53.026229 300 : 4250, 4027
7467 11:56:53.026328 304 : 4250, 4027
7468 11:56:53.029140 308 : 4250, 3995
7469 11:56:53.029239 312 : 4360, 2273
7470 11:56:53.032872 316 : 4250, 23
7471 11:56:53.032975
7472 11:56:53.033063 MIOCK jitter meter ch=0
7473 11:56:53.033153
7474 11:56:53.035762 1T = (316-88) = 228 dly cells
7475 11:56:53.042842 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7476 11:56:53.042939 ==
7477 11:56:53.046394 Dram Type= 6, Freq= 0, CH_0, rank 0
7478 11:56:53.049326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7479 11:56:53.049424 ==
7480 11:56:53.056002 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7481 11:56:53.059006 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7482 11:56:53.062282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7483 11:56:53.069136 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7484 11:56:53.078739 [CA 0] Center 42 (12~73) winsize 62
7485 11:56:53.082636 [CA 1] Center 42 (12~73) winsize 62
7486 11:56:53.085644 [CA 2] Center 37 (8~67) winsize 60
7487 11:56:53.088931 [CA 3] Center 37 (7~67) winsize 61
7488 11:56:53.092061 [CA 4] Center 36 (6~66) winsize 61
7489 11:56:53.095667 [CA 5] Center 35 (6~64) winsize 59
7490 11:56:53.095759
7491 11:56:53.099115 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7492 11:56:53.099181
7493 11:56:53.102346 [CATrainingPosCal] consider 1 rank data
7494 11:56:53.105351 u2DelayCellTimex100 = 285/100 ps
7495 11:56:53.108842 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7496 11:56:53.115431 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7497 11:56:53.118630 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7498 11:56:53.122149 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7499 11:56:53.126078 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7500 11:56:53.128913 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7501 11:56:53.129014
7502 11:56:53.132094 CA PerBit enable=1, Macro0, CA PI delay=35
7503 11:56:53.132197
7504 11:56:53.135832 [CBTSetCACLKResult] CA Dly = 35
7505 11:56:53.135929 CS Dly: 9 (0~40)
7506 11:56:53.142371 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7507 11:56:53.145543 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7508 11:56:53.145661 ==
7509 11:56:53.149427 Dram Type= 6, Freq= 0, CH_0, rank 1
7510 11:56:53.152632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7511 11:56:53.152720 ==
7512 11:56:53.159179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7513 11:56:53.162355 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7514 11:56:53.165853 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7515 11:56:53.172536 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7516 11:56:53.182349 [CA 0] Center 42 (12~73) winsize 62
7517 11:56:53.185554 [CA 1] Center 42 (12~73) winsize 62
7518 11:56:53.188605 [CA 2] Center 37 (8~67) winsize 60
7519 11:56:53.192529 [CA 3] Center 38 (8~68) winsize 61
7520 11:56:53.195417 [CA 4] Center 35 (5~65) winsize 61
7521 11:56:53.198620 [CA 5] Center 35 (5~65) winsize 61
7522 11:56:53.198692
7523 11:56:53.202539 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7524 11:56:53.202609
7525 11:56:53.205829 [CATrainingPosCal] consider 2 rank data
7526 11:56:53.208900 u2DelayCellTimex100 = 285/100 ps
7527 11:56:53.211884 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7528 11:56:53.218645 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7529 11:56:53.222111 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7530 11:56:53.225294 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7531 11:56:53.228464 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7532 11:56:53.232136 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7533 11:56:53.232240
7534 11:56:53.235266 CA PerBit enable=1, Macro0, CA PI delay=35
7535 11:56:53.235382
7536 11:56:53.239032 [CBTSetCACLKResult] CA Dly = 35
7537 11:56:53.242325 CS Dly: 10 (0~42)
7538 11:56:53.245444 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7539 11:56:53.248599 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7540 11:56:53.248722
7541 11:56:53.252086 ----->DramcWriteLeveling(PI) begin...
7542 11:56:53.252195 ==
7543 11:56:53.255815 Dram Type= 6, Freq= 0, CH_0, rank 0
7544 11:56:53.258911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7545 11:56:53.258989 ==
7546 11:56:53.261966 Write leveling (Byte 0): 36 => 36
7547 11:56:53.265282 Write leveling (Byte 1): 28 => 28
7548 11:56:53.268832 DramcWriteLeveling(PI) end<-----
7549 11:56:53.268938
7550 11:56:53.269027 ==
7551 11:56:53.272418 Dram Type= 6, Freq= 0, CH_0, rank 0
7552 11:56:53.278664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7553 11:56:53.278764 ==
7554 11:56:53.278854 [Gating] SW mode calibration
7555 11:56:53.289186 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7556 11:56:53.292081 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7557 11:56:53.295344 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7558 11:56:53.301847 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7559 11:56:53.305383 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7560 11:56:53.308453 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7561 11:56:53.315491 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7562 11:56:53.318552 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7563 11:56:53.322010 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7564 11:56:53.328907 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7565 11:56:53.331930 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7566 11:56:53.335623 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7567 11:56:53.342300 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7568 11:56:53.345277 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7569 11:56:53.348408 1 5 16 | B1->B0 | 3333 2928 | 1 1 | (1 1) (0 0)
7570 11:56:53.355639 1 5 20 | B1->B0 | 2424 2828 | 0 0 | (1 0) (0 0)
7571 11:56:53.358672 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7572 11:56:53.361837 1 5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7573 11:56:53.368655 1 6 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7574 11:56:53.371682 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7575 11:56:53.375087 1 6 8 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)
7576 11:56:53.381877 1 6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)
7577 11:56:53.385255 1 6 16 | B1->B0 | 2b2b 4645 | 1 1 | (0 0) (0 0)
7578 11:56:53.388447 1 6 20 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)
7579 11:56:53.391909 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7580 11:56:53.398963 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 11:56:53.402051 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 11:56:53.405174 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7583 11:56:53.411975 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7584 11:56:53.415257 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7585 11:56:53.418562 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7586 11:56:53.425373 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7587 11:56:53.428600 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7588 11:56:53.431546 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:56:53.438342 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:56:53.441639 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:56:53.444636 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:56:53.451791 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:56:53.454925 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:56:53.457948 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:56:53.465075 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:56:53.468134 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:56:53.471863 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:56:53.478214 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:56:53.481311 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:56:53.485187 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7601 11:56:53.491341 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 11:56:53.491446 Total UI for P1: 0, mck2ui 16
7603 11:56:53.498036 best dqsien dly found for B0: ( 1, 9, 12)
7604 11:56:53.501378 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7605 11:56:53.505123 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 11:56:53.508347 Total UI for P1: 0, mck2ui 16
7607 11:56:53.511345 best dqsien dly found for B1: ( 1, 9, 18)
7608 11:56:53.514839 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7609 11:56:53.517927 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7610 11:56:53.518021
7611 11:56:53.524568 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7612 11:56:53.528240 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7613 11:56:53.528334 [Gating] SW calibration Done
7614 11:56:53.531178 ==
7615 11:56:53.534861 Dram Type= 6, Freq= 0, CH_0, rank 0
7616 11:56:53.537778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7617 11:56:53.537874 ==
7618 11:56:53.537972 RX Vref Scan: 0
7619 11:56:53.538061
7620 11:56:53.541456 RX Vref 0 -> 0, step: 1
7621 11:56:53.541549
7622 11:56:53.545073 RX Delay 0 -> 252, step: 8
7623 11:56:53.547642 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7624 11:56:53.551303 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7625 11:56:53.554378 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7626 11:56:53.560991 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7627 11:56:53.565187 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7628 11:56:53.567915 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7629 11:56:53.571810 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7630 11:56:53.574607 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7631 11:56:53.581572 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7632 11:56:53.584612 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7633 11:56:53.587621 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7634 11:56:53.591674 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7635 11:56:53.594467 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7636 11:56:53.600901 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7637 11:56:53.604644 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7638 11:56:53.607727 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7639 11:56:53.607822 ==
7640 11:56:53.610842 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 11:56:53.614722 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 11:56:53.614801 ==
7643 11:56:53.617808 DQS Delay:
7644 11:56:53.617876 DQS0 = 0, DQS1 = 0
7645 11:56:53.620981 DQM Delay:
7646 11:56:53.621074 DQM0 = 137, DQM1 = 130
7647 11:56:53.621169 DQ Delay:
7648 11:56:53.627644 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7649 11:56:53.631143 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7650 11:56:53.634252 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7651 11:56:53.637889 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7652 11:56:53.637960
7653 11:56:53.638020
7654 11:56:53.638114 ==
7655 11:56:53.641126 Dram Type= 6, Freq= 0, CH_0, rank 0
7656 11:56:53.644210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7657 11:56:53.644309 ==
7658 11:56:53.644399
7659 11:56:53.644487
7660 11:56:53.647873 TX Vref Scan disable
7661 11:56:53.650831 == TX Byte 0 ==
7662 11:56:53.654118 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7663 11:56:53.658101 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7664 11:56:53.660775 == TX Byte 1 ==
7665 11:56:53.664400 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7666 11:56:53.667851 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7667 11:56:53.667945 ==
7668 11:56:53.670997 Dram Type= 6, Freq= 0, CH_0, rank 0
7669 11:56:53.674141 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7670 11:56:53.677664 ==
7671 11:56:53.688321
7672 11:56:53.691349 TX Vref early break, caculate TX vref
7673 11:56:53.694889 TX Vref=16, minBit 0, minWin=23, winSum=379
7674 11:56:53.698160 TX Vref=18, minBit 1, minWin=23, winSum=386
7675 11:56:53.701238 TX Vref=20, minBit 0, minWin=24, winSum=400
7676 11:56:53.704592 TX Vref=22, minBit 0, minWin=24, winSum=405
7677 11:56:53.708282 TX Vref=24, minBit 0, minWin=25, winSum=417
7678 11:56:53.714975 TX Vref=26, minBit 2, minWin=25, winSum=425
7679 11:56:53.718212 TX Vref=28, minBit 2, minWin=25, winSum=425
7680 11:56:53.721322 TX Vref=30, minBit 8, minWin=24, winSum=411
7681 11:56:53.724573 TX Vref=32, minBit 1, minWin=24, winSum=400
7682 11:56:53.731372 [TxChooseVref] Worse bit 2, Min win 25, Win sum 425, Final Vref 26
7683 11:56:53.731476
7684 11:56:53.734669 Final TX Range 0 Vref 26
7685 11:56:53.734739
7686 11:56:53.734803 ==
7687 11:56:53.737785 Dram Type= 6, Freq= 0, CH_0, rank 0
7688 11:56:53.740844 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7689 11:56:53.740936 ==
7690 11:56:53.741022
7691 11:56:53.741104
7692 11:56:53.744843 TX Vref Scan disable
7693 11:56:53.748036 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7694 11:56:53.751436 == TX Byte 0 ==
7695 11:56:53.754381 u2DelayCellOfst[0]=10 cells (3 PI)
7696 11:56:53.758411 u2DelayCellOfst[1]=13 cells (4 PI)
7697 11:56:53.761188 u2DelayCellOfst[2]=10 cells (3 PI)
7698 11:56:53.764573 u2DelayCellOfst[3]=10 cells (3 PI)
7699 11:56:53.767576 u2DelayCellOfst[4]=6 cells (2 PI)
7700 11:56:53.771344 u2DelayCellOfst[5]=0 cells (0 PI)
7701 11:56:53.771436 u2DelayCellOfst[6]=13 cells (4 PI)
7702 11:56:53.774415 u2DelayCellOfst[7]=13 cells (4 PI)
7703 11:56:53.781455 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7704 11:56:53.784520 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7705 11:56:53.784619 == TX Byte 1 ==
7706 11:56:53.787609 u2DelayCellOfst[8]=3 cells (1 PI)
7707 11:56:53.791432 u2DelayCellOfst[9]=0 cells (0 PI)
7708 11:56:53.794279 u2DelayCellOfst[10]=6 cells (2 PI)
7709 11:56:53.797925 u2DelayCellOfst[11]=6 cells (2 PI)
7710 11:56:53.801140 u2DelayCellOfst[12]=10 cells (3 PI)
7711 11:56:53.804544 u2DelayCellOfst[13]=10 cells (3 PI)
7712 11:56:53.808100 u2DelayCellOfst[14]=17 cells (5 PI)
7713 11:56:53.810942 u2DelayCellOfst[15]=10 cells (3 PI)
7714 11:56:53.814317 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7715 11:56:53.817694 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7716 11:56:53.820783 DramC Write-DBI on
7717 11:56:53.820895 ==
7718 11:56:53.824249 Dram Type= 6, Freq= 0, CH_0, rank 0
7719 11:56:53.827688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7720 11:56:53.827788 ==
7721 11:56:53.827879
7722 11:56:53.827967
7723 11:56:53.830864 TX Vref Scan disable
7724 11:56:53.834577 == TX Byte 0 ==
7725 11:56:53.837390 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7726 11:56:53.840827 == TX Byte 1 ==
7727 11:56:53.844553 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7728 11:56:53.844650 DramC Write-DBI off
7729 11:56:53.844783
7730 11:56:53.847569 [DATLAT]
7731 11:56:53.847662 Freq=1600, CH0 RK0
7732 11:56:53.847747
7733 11:56:53.850912 DATLAT Default: 0xf
7734 11:56:53.850979 0, 0xFFFF, sum = 0
7735 11:56:53.854020 1, 0xFFFF, sum = 0
7736 11:56:53.854114 2, 0xFFFF, sum = 0
7737 11:56:53.857744 3, 0xFFFF, sum = 0
7738 11:56:53.857838 4, 0xFFFF, sum = 0
7739 11:56:53.861060 5, 0xFFFF, sum = 0
7740 11:56:53.861151 6, 0xFFFF, sum = 0
7741 11:56:53.864311 7, 0xFFFF, sum = 0
7742 11:56:53.864404 8, 0xFFFF, sum = 0
7743 11:56:53.867685 9, 0xFFFF, sum = 0
7744 11:56:53.870565 10, 0xFFFF, sum = 0
7745 11:56:53.870630 11, 0xFFFF, sum = 0
7746 11:56:53.874633 12, 0xFFFF, sum = 0
7747 11:56:53.874699 13, 0xFFFF, sum = 0
7748 11:56:53.877660 14, 0x0, sum = 1
7749 11:56:53.877751 15, 0x0, sum = 2
7750 11:56:53.880698 16, 0x0, sum = 3
7751 11:56:53.880766 17, 0x0, sum = 4
7752 11:56:53.880823 best_step = 15
7753 11:56:53.884428
7754 11:56:53.884516 ==
7755 11:56:53.887338 Dram Type= 6, Freq= 0, CH_0, rank 0
7756 11:56:53.890948 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7757 11:56:53.891046 ==
7758 11:56:53.891133 RX Vref Scan: 1
7759 11:56:53.891217
7760 11:56:53.894109 Set Vref Range= 24 -> 127
7761 11:56:53.894173
7762 11:56:53.897788 RX Vref 24 -> 127, step: 1
7763 11:56:53.897852
7764 11:56:53.900669 RX Delay 19 -> 252, step: 4
7765 11:56:53.900758
7766 11:56:53.904365 Set Vref, RX VrefLevel [Byte0]: 24
7767 11:56:53.907497 [Byte1]: 24
7768 11:56:53.907586
7769 11:56:53.910814 Set Vref, RX VrefLevel [Byte0]: 25
7770 11:56:53.913793 [Byte1]: 25
7771 11:56:53.913860
7772 11:56:53.916996 Set Vref, RX VrefLevel [Byte0]: 26
7773 11:56:53.921053 [Byte1]: 26
7774 11:56:53.924454
7775 11:56:53.924543 Set Vref, RX VrefLevel [Byte0]: 27
7776 11:56:53.927108 [Byte1]: 27
7777 11:56:53.931499
7778 11:56:53.931572 Set Vref, RX VrefLevel [Byte0]: 28
7779 11:56:53.935422 [Byte1]: 28
7780 11:56:53.939214
7781 11:56:53.939289 Set Vref, RX VrefLevel [Byte0]: 29
7782 11:56:53.942571 [Byte1]: 29
7783 11:56:53.946835
7784 11:56:53.946903 Set Vref, RX VrefLevel [Byte0]: 30
7785 11:56:53.950184 [Byte1]: 30
7786 11:56:53.954294
7787 11:56:53.954361 Set Vref, RX VrefLevel [Byte0]: 31
7788 11:56:53.957490 [Byte1]: 31
7789 11:56:53.961998
7790 11:56:53.962066 Set Vref, RX VrefLevel [Byte0]: 32
7791 11:56:53.965435 [Byte1]: 32
7792 11:56:53.969584
7793 11:56:53.969660 Set Vref, RX VrefLevel [Byte0]: 33
7794 11:56:53.973002 [Byte1]: 33
7795 11:56:53.977546
7796 11:56:53.977651 Set Vref, RX VrefLevel [Byte0]: 34
7797 11:56:53.980455 [Byte1]: 34
7798 11:56:53.984732
7799 11:56:53.984826 Set Vref, RX VrefLevel [Byte0]: 35
7800 11:56:53.987804 [Byte1]: 35
7801 11:56:53.992496
7802 11:56:53.992567 Set Vref, RX VrefLevel [Byte0]: 36
7803 11:56:53.995797 [Byte1]: 36
7804 11:56:53.999687
7805 11:56:53.999783 Set Vref, RX VrefLevel [Byte0]: 37
7806 11:56:54.003543 [Byte1]: 37
7807 11:56:54.007601
7808 11:56:54.007690 Set Vref, RX VrefLevel [Byte0]: 38
7809 11:56:54.010625 [Byte1]: 38
7810 11:56:54.014977
7811 11:56:54.015073 Set Vref, RX VrefLevel [Byte0]: 39
7812 11:56:54.018221 [Byte1]: 39
7813 11:56:54.022534
7814 11:56:54.022602 Set Vref, RX VrefLevel [Byte0]: 40
7815 11:56:54.025570 [Byte1]: 40
7816 11:56:54.030004
7817 11:56:54.030100 Set Vref, RX VrefLevel [Byte0]: 41
7818 11:56:54.033380 [Byte1]: 41
7819 11:56:54.037611
7820 11:56:54.037705 Set Vref, RX VrefLevel [Byte0]: 42
7821 11:56:54.040769 [Byte1]: 42
7822 11:56:54.045119
7823 11:56:54.045228 Set Vref, RX VrefLevel [Byte0]: 43
7824 11:56:54.048839 [Byte1]: 43
7825 11:56:54.053117
7826 11:56:54.053190 Set Vref, RX VrefLevel [Byte0]: 44
7827 11:56:54.056246 [Byte1]: 44
7828 11:56:54.060359
7829 11:56:54.060464 Set Vref, RX VrefLevel [Byte0]: 45
7830 11:56:54.064070 [Byte1]: 45
7831 11:56:54.067824
7832 11:56:54.067894 Set Vref, RX VrefLevel [Byte0]: 46
7833 11:56:54.071353 [Byte1]: 46
7834 11:56:54.075295
7835 11:56:54.075392 Set Vref, RX VrefLevel [Byte0]: 47
7836 11:56:54.078909 [Byte1]: 47
7837 11:56:54.083371
7838 11:56:54.083441 Set Vref, RX VrefLevel [Byte0]: 48
7839 11:56:54.086649 [Byte1]: 48
7840 11:56:54.090670
7841 11:56:54.090742 Set Vref, RX VrefLevel [Byte0]: 49
7842 11:56:54.094495 [Byte1]: 49
7843 11:56:54.098410
7844 11:56:54.098484 Set Vref, RX VrefLevel [Byte0]: 50
7845 11:56:54.101374 [Byte1]: 50
7846 11:56:54.105905
7847 11:56:54.105980 Set Vref, RX VrefLevel [Byte0]: 51
7848 11:56:54.109322 [Byte1]: 51
7849 11:56:54.113558
7850 11:56:54.113641 Set Vref, RX VrefLevel [Byte0]: 52
7851 11:56:54.116655 [Byte1]: 52
7852 11:56:54.121242
7853 11:56:54.121339 Set Vref, RX VrefLevel [Byte0]: 53
7854 11:56:54.124438 [Byte1]: 53
7855 11:56:54.128709
7856 11:56:54.128812 Set Vref, RX VrefLevel [Byte0]: 54
7857 11:56:54.132041 [Byte1]: 54
7858 11:56:54.136363
7859 11:56:54.136469 Set Vref, RX VrefLevel [Byte0]: 55
7860 11:56:54.139523 [Byte1]: 55
7861 11:56:54.143432
7862 11:56:54.143531 Set Vref, RX VrefLevel [Byte0]: 56
7863 11:56:54.146705 [Byte1]: 56
7864 11:56:54.151173
7865 11:56:54.151249 Set Vref, RX VrefLevel [Byte0]: 57
7866 11:56:54.155008 [Byte1]: 57
7867 11:56:54.158585
7868 11:56:54.158683 Set Vref, RX VrefLevel [Byte0]: 58
7869 11:56:54.161976 [Byte1]: 58
7870 11:56:54.166718
7871 11:56:54.166789 Set Vref, RX VrefLevel [Byte0]: 59
7872 11:56:54.169506 [Byte1]: 59
7873 11:56:54.173862
7874 11:56:54.173934 Set Vref, RX VrefLevel [Byte0]: 60
7875 11:56:54.177156 [Byte1]: 60
7876 11:56:54.181688
7877 11:56:54.181786 Set Vref, RX VrefLevel [Byte0]: 61
7878 11:56:54.184852 [Byte1]: 61
7879 11:56:54.189001
7880 11:56:54.189074 Set Vref, RX VrefLevel [Byte0]: 62
7881 11:56:54.192900 [Byte1]: 62
7882 11:56:54.197022
7883 11:56:54.197102 Set Vref, RX VrefLevel [Byte0]: 63
7884 11:56:54.199873 [Byte1]: 63
7885 11:56:54.204135
7886 11:56:54.204230 Set Vref, RX VrefLevel [Byte0]: 64
7887 11:56:54.207548 [Byte1]: 64
7888 11:56:54.212181
7889 11:56:54.212279 Set Vref, RX VrefLevel [Byte0]: 65
7890 11:56:54.215399 [Byte1]: 65
7891 11:56:54.219591
7892 11:56:54.219689 Set Vref, RX VrefLevel [Byte0]: 66
7893 11:56:54.222723 [Byte1]: 66
7894 11:56:54.226715
7895 11:56:54.226789 Set Vref, RX VrefLevel [Byte0]: 67
7896 11:56:54.230159 [Byte1]: 67
7897 11:56:54.234340
7898 11:56:54.234445 Set Vref, RX VrefLevel [Byte0]: 68
7899 11:56:54.237562 [Byte1]: 68
7900 11:56:54.241828
7901 11:56:54.241928 Set Vref, RX VrefLevel [Byte0]: 69
7902 11:56:54.245491 [Byte1]: 69
7903 11:56:54.249818
7904 11:56:54.249892 Set Vref, RX VrefLevel [Byte0]: 70
7905 11:56:54.253431 [Byte1]: 70
7906 11:56:54.257132
7907 11:56:54.257231 Set Vref, RX VrefLevel [Byte0]: 71
7908 11:56:54.260699 [Byte1]: 71
7909 11:56:54.265057
7910 11:56:54.265154 Set Vref, RX VrefLevel [Byte0]: 72
7911 11:56:54.268413 [Byte1]: 72
7912 11:56:54.272322
7913 11:56:54.272416 Set Vref, RX VrefLevel [Byte0]: 73
7914 11:56:54.276358 [Byte1]: 73
7915 11:56:54.280141
7916 11:56:54.280234 Final RX Vref Byte 0 = 55 to rank0
7917 11:56:54.283131 Final RX Vref Byte 1 = 59 to rank0
7918 11:56:54.286909 Final RX Vref Byte 0 = 55 to rank1
7919 11:56:54.290097 Final RX Vref Byte 1 = 59 to rank1==
7920 11:56:54.293586 Dram Type= 6, Freq= 0, CH_0, rank 0
7921 11:56:54.300010 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7922 11:56:54.300124 ==
7923 11:56:54.300215 DQS Delay:
7924 11:56:54.300303 DQS0 = 0, DQS1 = 0
7925 11:56:54.303210 DQM Delay:
7926 11:56:54.303332 DQM0 = 133, DQM1 = 128
7927 11:56:54.306450 DQ Delay:
7928 11:56:54.309969 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7929 11:56:54.313209 DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138
7930 11:56:54.316875 DQ8 =118, DQ9 =118, DQ10 =128, DQ11 =120
7931 11:56:54.319947 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =136
7932 11:56:54.320020
7933 11:56:54.320080
7934 11:56:54.320137
7935 11:56:54.323124 [DramC_TX_OE_Calibration] TA2
7936 11:56:54.326331 Original DQ_B0 (3 6) =30, OEN = 27
7937 11:56:54.330041 Original DQ_B1 (3 6) =30, OEN = 27
7938 11:56:54.333107 24, 0x0, End_B0=24 End_B1=24
7939 11:56:54.333211 25, 0x0, End_B0=25 End_B1=25
7940 11:56:54.336737 26, 0x0, End_B0=26 End_B1=26
7941 11:56:54.340114 27, 0x0, End_B0=27 End_B1=27
7942 11:56:54.343352 28, 0x0, End_B0=28 End_B1=28
7943 11:56:54.343451 29, 0x0, End_B0=29 End_B1=29
7944 11:56:54.346641 30, 0x0, End_B0=30 End_B1=30
7945 11:56:54.349731 31, 0x4141, End_B0=30 End_B1=30
7946 11:56:54.353400 Byte0 end_step=30 best_step=27
7947 11:56:54.356341 Byte1 end_step=30 best_step=27
7948 11:56:54.359899 Byte0 TX OE(2T, 0.5T) = (3, 3)
7949 11:56:54.359997 Byte1 TX OE(2T, 0.5T) = (3, 3)
7950 11:56:54.363312
7951 11:56:54.363383
7952 11:56:54.369953 [DQSOSCAuto] RK0, (LSB)MR18= 0x2722, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
7953 11:56:54.373430 CH0 RK0: MR19=303, MR18=2722
7954 11:56:54.380130 CH0_RK0: MR19=0x303, MR18=0x2722, DQSOSC=390, MR23=63, INC=24, DEC=16
7955 11:56:54.380233
7956 11:56:54.383259 ----->DramcWriteLeveling(PI) begin...
7957 11:56:54.383334 ==
7958 11:56:54.386521 Dram Type= 6, Freq= 0, CH_0, rank 1
7959 11:56:54.389653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7960 11:56:54.389752 ==
7961 11:56:54.392838 Write leveling (Byte 0): 37 => 37
7962 11:56:54.396569 Write leveling (Byte 1): 29 => 29
7963 11:56:54.399585 DramcWriteLeveling(PI) end<-----
7964 11:56:54.399684
7965 11:56:54.399773 ==
7966 11:56:54.402812 Dram Type= 6, Freq= 0, CH_0, rank 1
7967 11:56:54.406923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7968 11:56:54.407021 ==
7969 11:56:54.409829 [Gating] SW mode calibration
7970 11:56:54.416115 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7971 11:56:54.422888 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7972 11:56:54.426710 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7973 11:56:54.429903 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7974 11:56:54.435986 1 4 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7975 11:56:54.439275 1 4 12 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7976 11:56:54.442879 1 4 16 | B1->B0 | 2a2a 3535 | 1 0 | (1 1) (0 0)
7977 11:56:54.450111 1 4 20 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
7978 11:56:54.452819 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7979 11:56:54.456265 1 4 28 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7980 11:56:54.463050 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7981 11:56:54.466342 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7982 11:56:54.469667 1 5 8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 1)
7983 11:56:54.476059 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
7984 11:56:54.479145 1 5 16 | B1->B0 | 2e2e 2929 | 0 0 | (1 0) (0 1)
7985 11:56:54.482581 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7986 11:56:54.489335 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7987 11:56:54.492977 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7988 11:56:54.496444 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7989 11:56:54.503232 1 6 4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (1 1)
7990 11:56:54.506459 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 11:56:54.509442 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7992 11:56:54.513150 1 6 16 | B1->B0 | 4040 4645 | 0 1 | (0 0) (0 0)
7993 11:56:54.519393 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 11:56:54.522744 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 11:56:54.526234 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 11:56:54.532504 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 11:56:54.535916 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 11:56:54.539240 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 11:56:54.545896 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8000 11:56:54.549616 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8001 11:56:54.552673 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:56:54.559477 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:56:54.562716 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:56:54.565917 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:56:54.572732 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:56:54.575808 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:56:54.579179 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:56:54.585789 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:56:54.588942 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:56:54.592482 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 11:56:54.598830 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:56:54.602666 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:56:54.605712 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:56:54.612598 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:56:54.615983 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8016 11:56:54.619163 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8017 11:56:54.625468 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8018 11:56:54.625597 Total UI for P1: 0, mck2ui 16
8019 11:56:54.629205 best dqsien dly found for B0: ( 1, 9, 14)
8020 11:56:54.632323 Total UI for P1: 0, mck2ui 16
8021 11:56:54.635903 best dqsien dly found for B1: ( 1, 9, 14)
8022 11:56:54.642401 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8023 11:56:54.645502 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8024 11:56:54.645627
8025 11:56:54.649409 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8026 11:56:54.652568 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8027 11:56:54.655604 [Gating] SW calibration Done
8028 11:56:54.655675 ==
8029 11:56:54.659315 Dram Type= 6, Freq= 0, CH_0, rank 1
8030 11:56:54.662368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8031 11:56:54.662437 ==
8032 11:56:54.665569 RX Vref Scan: 0
8033 11:56:54.665658
8034 11:56:54.665715 RX Vref 0 -> 0, step: 1
8035 11:56:54.665774
8036 11:56:54.668658 RX Delay 0 -> 252, step: 8
8037 11:56:54.672155 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8038 11:56:54.678528 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8039 11:56:54.682352 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8040 11:56:54.685903 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8041 11:56:54.688943 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8042 11:56:54.692341 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8043 11:56:54.695490 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8044 11:56:54.702273 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8045 11:56:54.705400 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8046 11:56:54.708742 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8047 11:56:54.711945 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8048 11:56:54.715350 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8049 11:56:54.721932 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8050 11:56:54.725572 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8051 11:56:54.728693 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8052 11:56:54.731899 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8053 11:56:54.731975 ==
8054 11:56:54.735051 Dram Type= 6, Freq= 0, CH_0, rank 1
8055 11:56:54.741786 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8056 11:56:54.741867 ==
8057 11:56:54.741934 DQS Delay:
8058 11:56:54.745428 DQS0 = 0, DQS1 = 0
8059 11:56:54.745525 DQM Delay:
8060 11:56:54.745618 DQM0 = 137, DQM1 = 129
8061 11:56:54.748626 DQ Delay:
8062 11:56:54.751738 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8063 11:56:54.754974 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8064 11:56:54.758584 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8065 11:56:54.761979 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =139
8066 11:56:54.762048
8067 11:56:54.762111
8068 11:56:54.762168 ==
8069 11:56:54.764898 Dram Type= 6, Freq= 0, CH_0, rank 1
8070 11:56:54.771341 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8071 11:56:54.771417 ==
8072 11:56:54.771477
8073 11:56:54.771533
8074 11:56:54.771591 TX Vref Scan disable
8075 11:56:54.775237 == TX Byte 0 ==
8076 11:56:54.778865 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8077 11:56:54.785014 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8078 11:56:54.785114 == TX Byte 1 ==
8079 11:56:54.788418 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8080 11:56:54.791706 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8081 11:56:54.795528 ==
8082 11:56:54.798571 Dram Type= 6, Freq= 0, CH_0, rank 1
8083 11:56:54.802048 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8084 11:56:54.802149 ==
8085 11:56:54.814852
8086 11:56:54.818527 TX Vref early break, caculate TX vref
8087 11:56:54.821405 TX Vref=16, minBit 0, minWin=23, winSum=387
8088 11:56:54.824974 TX Vref=18, minBit 4, minWin=23, winSum=396
8089 11:56:54.828467 TX Vref=20, minBit 1, minWin=23, winSum=404
8090 11:56:54.831306 TX Vref=22, minBit 3, minWin=24, winSum=411
8091 11:56:54.834723 TX Vref=24, minBit 1, minWin=24, winSum=418
8092 11:56:54.841421 TX Vref=26, minBit 1, minWin=25, winSum=425
8093 11:56:54.845074 TX Vref=28, minBit 3, minWin=25, winSum=426
8094 11:56:54.848030 TX Vref=30, minBit 3, minWin=25, winSum=420
8095 11:56:54.851716 TX Vref=32, minBit 0, minWin=24, winSum=406
8096 11:56:54.854952 TX Vref=34, minBit 0, minWin=24, winSum=403
8097 11:56:54.861414 [TxChooseVref] Worse bit 3, Min win 25, Win sum 426, Final Vref 28
8098 11:56:54.861487
8099 11:56:54.865073 Final TX Range 0 Vref 28
8100 11:56:54.865167
8101 11:56:54.865255 ==
8102 11:56:54.868253 Dram Type= 6, Freq= 0, CH_0, rank 1
8103 11:56:54.871799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8104 11:56:54.871901 ==
8105 11:56:54.871989
8106 11:56:54.872074
8107 11:56:54.874776 TX Vref Scan disable
8108 11:56:54.881541 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8109 11:56:54.881648 == TX Byte 0 ==
8110 11:56:54.884675 u2DelayCellOfst[0]=10 cells (3 PI)
8111 11:56:54.888401 u2DelayCellOfst[1]=13 cells (4 PI)
8112 11:56:54.891558 u2DelayCellOfst[2]=10 cells (3 PI)
8113 11:56:54.895086 u2DelayCellOfst[3]=10 cells (3 PI)
8114 11:56:54.898323 u2DelayCellOfst[4]=6 cells (2 PI)
8115 11:56:54.901687 u2DelayCellOfst[5]=0 cells (0 PI)
8116 11:56:54.905404 u2DelayCellOfst[6]=13 cells (4 PI)
8117 11:56:54.905525 u2DelayCellOfst[7]=13 cells (4 PI)
8118 11:56:54.911719 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8119 11:56:54.914604 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8120 11:56:54.914680 == TX Byte 1 ==
8121 11:56:54.918072 u2DelayCellOfst[8]=0 cells (0 PI)
8122 11:56:54.921417 u2DelayCellOfst[9]=0 cells (0 PI)
8123 11:56:54.924479 u2DelayCellOfst[10]=6 cells (2 PI)
8124 11:56:54.928487 u2DelayCellOfst[11]=3 cells (1 PI)
8125 11:56:54.931270 u2DelayCellOfst[12]=10 cells (3 PI)
8126 11:56:54.935158 u2DelayCellOfst[13]=10 cells (3 PI)
8127 11:56:54.938103 u2DelayCellOfst[14]=13 cells (4 PI)
8128 11:56:54.941847 u2DelayCellOfst[15]=10 cells (3 PI)
8129 11:56:54.944974 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8130 11:56:54.951289 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8131 11:56:54.951400 DramC Write-DBI on
8132 11:56:54.951490 ==
8133 11:56:54.955000 Dram Type= 6, Freq= 0, CH_0, rank 1
8134 11:56:54.958280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8135 11:56:54.958375 ==
8136 11:56:54.958471
8137 11:56:54.961488
8138 11:56:54.961617 TX Vref Scan disable
8139 11:56:54.964548 == TX Byte 0 ==
8140 11:56:54.967968 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8141 11:56:54.971216 == TX Byte 1 ==
8142 11:56:54.974818 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8143 11:56:54.974891 DramC Write-DBI off
8144 11:56:54.977988
8145 11:56:54.978059 [DATLAT]
8146 11:56:54.978123 Freq=1600, CH0 RK1
8147 11:56:54.978180
8148 11:56:54.981252 DATLAT Default: 0xf
8149 11:56:54.981346 0, 0xFFFF, sum = 0
8150 11:56:54.984507 1, 0xFFFF, sum = 0
8151 11:56:54.984576 2, 0xFFFF, sum = 0
8152 11:56:54.988250 3, 0xFFFF, sum = 0
8153 11:56:54.988348 4, 0xFFFF, sum = 0
8154 11:56:54.991478 5, 0xFFFF, sum = 0
8155 11:56:54.994631 6, 0xFFFF, sum = 0
8156 11:56:54.994720 7, 0xFFFF, sum = 0
8157 11:56:54.997790 8, 0xFFFF, sum = 0
8158 11:56:54.997866 9, 0xFFFF, sum = 0
8159 11:56:55.001237 10, 0xFFFF, sum = 0
8160 11:56:55.001316 11, 0xFFFF, sum = 0
8161 11:56:55.004706 12, 0xFFFF, sum = 0
8162 11:56:55.004792 13, 0xFFFF, sum = 0
8163 11:56:55.008029 14, 0x0, sum = 1
8164 11:56:55.008106 15, 0x0, sum = 2
8165 11:56:55.011024 16, 0x0, sum = 3
8166 11:56:55.011160 17, 0x0, sum = 4
8167 11:56:55.014429 best_step = 15
8168 11:56:55.014504
8169 11:56:55.014577 ==
8170 11:56:55.018100 Dram Type= 6, Freq= 0, CH_0, rank 1
8171 11:56:55.021524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8172 11:56:55.021617 ==
8173 11:56:55.021679 RX Vref Scan: 0
8174 11:56:55.024530
8175 11:56:55.024600 RX Vref 0 -> 0, step: 1
8176 11:56:55.024659
8177 11:56:55.027684 RX Delay 19 -> 252, step: 4
8178 11:56:55.031139 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8179 11:56:55.037974 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8180 11:56:55.040888 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8181 11:56:55.044619 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8182 11:56:55.047967 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8183 11:56:55.051264 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8184 11:56:55.057861 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8185 11:56:55.061320 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8186 11:56:55.064609 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8187 11:56:55.067632 iDelay=191, Bit 9, Center 118 (67 ~ 170) 104
8188 11:56:55.070767 iDelay=191, Bit 10, Center 130 (79 ~ 182) 104
8189 11:56:55.077560 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8190 11:56:55.081372 iDelay=191, Bit 12, Center 132 (83 ~ 182) 100
8191 11:56:55.084468 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8192 11:56:55.087694 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8193 11:56:55.090904 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8194 11:56:55.091005 ==
8195 11:56:55.094482 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 11:56:55.101086 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 11:56:55.101159 ==
8198 11:56:55.101219 DQS Delay:
8199 11:56:55.104185 DQS0 = 0, DQS1 = 0
8200 11:56:55.104273 DQM Delay:
8201 11:56:55.107554 DQM0 = 134, DQM1 = 127
8202 11:56:55.107633 DQ Delay:
8203 11:56:55.110697 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8204 11:56:55.114390 DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140
8205 11:56:55.117769 DQ8 =118, DQ9 =118, DQ10 =130, DQ11 =118
8206 11:56:55.120901 DQ12 =132, DQ13 =134, DQ14 =136, DQ15 =134
8207 11:56:55.120981
8208 11:56:55.121054
8209 11:56:55.121112
8210 11:56:55.124229 [DramC_TX_OE_Calibration] TA2
8211 11:56:55.127945 Original DQ_B0 (3 6) =30, OEN = 27
8212 11:56:55.131255 Original DQ_B1 (3 6) =30, OEN = 27
8213 11:56:55.134135 24, 0x0, End_B0=24 End_B1=24
8214 11:56:55.134234 25, 0x0, End_B0=25 End_B1=25
8215 11:56:55.137452 26, 0x0, End_B0=26 End_B1=26
8216 11:56:55.140978 27, 0x0, End_B0=27 End_B1=27
8217 11:56:55.144313 28, 0x0, End_B0=28 End_B1=28
8218 11:56:55.147444 29, 0x0, End_B0=29 End_B1=29
8219 11:56:55.147526 30, 0x0, End_B0=30 End_B1=30
8220 11:56:55.151048 31, 0x4545, End_B0=30 End_B1=30
8221 11:56:55.154012 Byte0 end_step=30 best_step=27
8222 11:56:55.157546 Byte1 end_step=30 best_step=27
8223 11:56:55.161116 Byte0 TX OE(2T, 0.5T) = (3, 3)
8224 11:56:55.164112 Byte1 TX OE(2T, 0.5T) = (3, 3)
8225 11:56:55.164224
8226 11:56:55.164358
8227 11:56:55.170631 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8228 11:56:55.173764 CH0 RK1: MR19=303, MR18=1E07
8229 11:56:55.180554 CH0_RK1: MR19=0x303, MR18=0x1E07, DQSOSC=394, MR23=63, INC=23, DEC=15
8230 11:56:55.183649 [RxdqsGatingPostProcess] freq 1600
8231 11:56:55.187482 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8232 11:56:55.190752 best DQS0 dly(2T, 0.5T) = (1, 1)
8233 11:56:55.193698 best DQS1 dly(2T, 0.5T) = (1, 1)
8234 11:56:55.197233 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8235 11:56:55.200438 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8236 11:56:55.204413 best DQS0 dly(2T, 0.5T) = (1, 1)
8237 11:56:55.207119 best DQS1 dly(2T, 0.5T) = (1, 1)
8238 11:56:55.210531 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8239 11:56:55.214058 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8240 11:56:55.217120 Pre-setting of DQS Precalculation
8241 11:56:55.220334 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8242 11:56:55.220415 ==
8243 11:56:55.224097 Dram Type= 6, Freq= 0, CH_1, rank 0
8244 11:56:55.227281 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8245 11:56:55.230492 ==
8246 11:56:55.233978 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8247 11:56:55.237034 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8248 11:56:55.243850 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8249 11:56:55.250468 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8250 11:56:55.257798 [CA 0] Center 42 (12~72) winsize 61
8251 11:56:55.260599 [CA 1] Center 42 (13~72) winsize 60
8252 11:56:55.264594 [CA 2] Center 39 (10~68) winsize 59
8253 11:56:55.267845 [CA 3] Center 38 (9~67) winsize 59
8254 11:56:55.270942 [CA 4] Center 38 (9~68) winsize 60
8255 11:56:55.274099 [CA 5] Center 37 (8~67) winsize 60
8256 11:56:55.274180
8257 11:56:55.277542 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8258 11:56:55.277668
8259 11:56:55.281100 [CATrainingPosCal] consider 1 rank data
8260 11:56:55.284342 u2DelayCellTimex100 = 285/100 ps
8261 11:56:55.287609 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8262 11:56:55.294519 CA1 delay=42 (13~72),Diff = 5 PI (17 cell)
8263 11:56:55.297567 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8264 11:56:55.300776 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8265 11:56:55.303911 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8266 11:56:55.307307 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8267 11:56:55.307405
8268 11:56:55.311201 CA PerBit enable=1, Macro0, CA PI delay=37
8269 11:56:55.311283
8270 11:56:55.314157 [CBTSetCACLKResult] CA Dly = 37
8271 11:56:55.317193 CS Dly: 10 (0~41)
8272 11:56:55.320885 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8273 11:56:55.324000 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8274 11:56:55.324081 ==
8275 11:56:55.327607 Dram Type= 6, Freq= 0, CH_1, rank 1
8276 11:56:55.331273 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8277 11:56:55.333898 ==
8278 11:56:55.337513 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8279 11:56:55.340781 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8280 11:56:55.347221 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8281 11:56:55.350383 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8282 11:56:55.360629 [CA 0] Center 42 (13~72) winsize 60
8283 11:56:55.364330 [CA 1] Center 41 (12~71) winsize 60
8284 11:56:55.367997 [CA 2] Center 38 (9~68) winsize 60
8285 11:56:55.370851 [CA 3] Center 37 (8~67) winsize 60
8286 11:56:55.374127 [CA 4] Center 38 (8~68) winsize 61
8287 11:56:55.377556 [CA 5] Center 37 (8~67) winsize 60
8288 11:56:55.377664
8289 11:56:55.380990 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8290 11:56:55.381071
8291 11:56:55.384527 [CATrainingPosCal] consider 2 rank data
8292 11:56:55.387938 u2DelayCellTimex100 = 285/100 ps
8293 11:56:55.391337 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8294 11:56:55.397502 CA1 delay=42 (13~71),Diff = 5 PI (17 cell)
8295 11:56:55.400784 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8296 11:56:55.404299 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8297 11:56:55.407580 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8298 11:56:55.410648 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8299 11:56:55.410729
8300 11:56:55.414328 CA PerBit enable=1, Macro0, CA PI delay=37
8301 11:56:55.414410
8302 11:56:55.417484 [CBTSetCACLKResult] CA Dly = 37
8303 11:56:55.421206 CS Dly: 12 (0~45)
8304 11:56:55.424165 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8305 11:56:55.427340 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8306 11:56:55.427439
8307 11:56:55.430584 ----->DramcWriteLeveling(PI) begin...
8308 11:56:55.430680 ==
8309 11:56:55.434236 Dram Type= 6, Freq= 0, CH_1, rank 0
8310 11:56:55.440387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8311 11:56:55.440468 ==
8312 11:56:55.444068 Write leveling (Byte 0): 26 => 26
8313 11:56:55.444148 Write leveling (Byte 1): 27 => 27
8314 11:56:55.447087 DramcWriteLeveling(PI) end<-----
8315 11:56:55.447167
8316 11:56:55.447230 ==
8317 11:56:55.450635 Dram Type= 6, Freq= 0, CH_1, rank 0
8318 11:56:55.457238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 11:56:55.457349 ==
8320 11:56:55.460569 [Gating] SW mode calibration
8321 11:56:55.467013 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8322 11:56:55.470235 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8323 11:56:55.476979 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 11:56:55.480383 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8325 11:56:55.484016 1 4 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
8326 11:56:55.490681 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
8327 11:56:55.494013 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 11:56:55.497395 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 11:56:55.504205 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 11:56:55.507206 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 11:56:55.510366 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 11:56:55.513728 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8333 11:56:55.520490 1 5 8 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8334 11:56:55.523514 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8335 11:56:55.527262 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 11:56:55.533461 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 11:56:55.537134 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 11:56:55.540145 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 11:56:55.547020 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 11:56:55.550138 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 11:56:55.553464 1 6 8 | B1->B0 | 2626 3d3c | 0 1 | (0 0) (0 0)
8342 11:56:55.559985 1 6 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8343 11:56:55.563708 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 11:56:55.566713 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 11:56:55.573699 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 11:56:55.576762 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 11:56:55.580194 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 11:56:55.586597 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 11:56:55.590034 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8350 11:56:55.593417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8351 11:56:55.599997 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:56:55.603129 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:56:55.606543 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:56:55.613286 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:56:55.616634 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:56:55.620049 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:56:55.626792 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:56:55.629873 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:56:55.633545 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:56:55.639850 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:56:55.642972 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:56:55.646905 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:56:55.653184 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:56:55.656620 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:56:55.660535 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8366 11:56:55.663050 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8367 11:56:55.669517 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:56:55.672902 Total UI for P1: 0, mck2ui 16
8369 11:56:55.676175 best dqsien dly found for B0: ( 1, 9, 10)
8370 11:56:55.679504 Total UI for P1: 0, mck2ui 16
8371 11:56:55.683275 best dqsien dly found for B1: ( 1, 9, 12)
8372 11:56:55.686400 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8373 11:56:55.689644 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8374 11:56:55.689725
8375 11:56:55.693193 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 11:56:55.696498 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8377 11:56:55.699591 [Gating] SW calibration Done
8378 11:56:55.699671 ==
8379 11:56:55.703205 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 11:56:55.706651 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 11:56:55.706733 ==
8382 11:56:55.709772 RX Vref Scan: 0
8383 11:56:55.709854
8384 11:56:55.712711 RX Vref 0 -> 0, step: 1
8385 11:56:55.712815
8386 11:56:55.712906 RX Delay 0 -> 252, step: 8
8387 11:56:55.719432 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8388 11:56:55.722742 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8389 11:56:55.726346 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8390 11:56:55.730267 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8391 11:56:55.732818 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8392 11:56:55.736085 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8393 11:56:55.742745 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8394 11:56:55.746670 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8395 11:56:55.749756 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8396 11:56:55.752736 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8397 11:56:55.756452 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8398 11:56:55.762858 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8399 11:56:55.766209 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8400 11:56:55.769667 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8401 11:56:55.772556 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8402 11:56:55.779494 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8403 11:56:55.779591 ==
8404 11:56:55.783079 Dram Type= 6, Freq= 0, CH_1, rank 0
8405 11:56:55.786073 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 11:56:55.786147 ==
8407 11:56:55.786210 DQS Delay:
8408 11:56:55.789856 DQS0 = 0, DQS1 = 0
8409 11:56:55.789936 DQM Delay:
8410 11:56:55.792960 DQM0 = 136, DQM1 = 133
8411 11:56:55.793040 DQ Delay:
8412 11:56:55.796117 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8413 11:56:55.799859 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8414 11:56:55.803189 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8415 11:56:55.806622 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8416 11:56:55.806727
8417 11:56:55.806792
8418 11:56:55.806851 ==
8419 11:56:55.809748 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 11:56:55.815927 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 11:56:55.816009 ==
8422 11:56:55.816072
8423 11:56:55.816131
8424 11:56:55.816188 TX Vref Scan disable
8425 11:56:55.819701 == TX Byte 0 ==
8426 11:56:55.823260 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8427 11:56:55.829489 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8428 11:56:55.829569 == TX Byte 1 ==
8429 11:56:55.833277 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8430 11:56:55.839378 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8431 11:56:55.839463 ==
8432 11:56:55.843218 Dram Type= 6, Freq= 0, CH_1, rank 0
8433 11:56:55.846363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8434 11:56:55.846438 ==
8435 11:56:55.858143
8436 11:56:55.861467 TX Vref early break, caculate TX vref
8437 11:56:55.865152 TX Vref=16, minBit 0, minWin=23, winSum=378
8438 11:56:55.868186 TX Vref=18, minBit 1, minWin=23, winSum=389
8439 11:56:55.871317 TX Vref=20, minBit 1, minWin=23, winSum=395
8440 11:56:55.875036 TX Vref=22, minBit 6, minWin=24, winSum=410
8441 11:56:55.878170 TX Vref=24, minBit 1, minWin=25, winSum=419
8442 11:56:55.884620 TX Vref=26, minBit 1, minWin=25, winSum=428
8443 11:56:55.888156 TX Vref=28, minBit 0, minWin=25, winSum=424
8444 11:56:55.891304 TX Vref=30, minBit 0, minWin=25, winSum=422
8445 11:56:55.894536 TX Vref=32, minBit 0, minWin=24, winSum=414
8446 11:56:55.898406 TX Vref=34, minBit 0, minWin=24, winSum=402
8447 11:56:55.904968 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8448 11:56:55.905049
8449 11:56:55.907979 Final TX Range 0 Vref 26
8450 11:56:55.908060
8451 11:56:55.908124 ==
8452 11:56:55.911152 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:56:55.914855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:56:55.914936 ==
8455 11:56:55.915057
8456 11:56:55.915157
8457 11:56:55.917758 TX Vref Scan disable
8458 11:56:55.924462 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8459 11:56:55.924543 == TX Byte 0 ==
8460 11:56:55.927773 u2DelayCellOfst[0]=13 cells (4 PI)
8461 11:56:55.931088 u2DelayCellOfst[1]=10 cells (3 PI)
8462 11:56:55.935103 u2DelayCellOfst[2]=0 cells (0 PI)
8463 11:56:55.937850 u2DelayCellOfst[3]=6 cells (2 PI)
8464 11:56:55.941132 u2DelayCellOfst[4]=6 cells (2 PI)
8465 11:56:55.944664 u2DelayCellOfst[5]=17 cells (5 PI)
8466 11:56:55.947774 u2DelayCellOfst[6]=17 cells (5 PI)
8467 11:56:55.947850 u2DelayCellOfst[7]=6 cells (2 PI)
8468 11:56:55.954683 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8469 11:56:55.957981 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8470 11:56:55.958063 == TX Byte 1 ==
8471 11:56:55.961295 u2DelayCellOfst[8]=0 cells (0 PI)
8472 11:56:55.964509 u2DelayCellOfst[9]=3 cells (1 PI)
8473 11:56:55.967509 u2DelayCellOfst[10]=13 cells (4 PI)
8474 11:56:55.971462 u2DelayCellOfst[11]=3 cells (1 PI)
8475 11:56:55.974591 u2DelayCellOfst[12]=17 cells (5 PI)
8476 11:56:55.977820 u2DelayCellOfst[13]=17 cells (5 PI)
8477 11:56:55.981011 u2DelayCellOfst[14]=17 cells (5 PI)
8478 11:56:55.984835 u2DelayCellOfst[15]=17 cells (5 PI)
8479 11:56:55.987697 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8480 11:56:55.994596 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8481 11:56:55.994678 DramC Write-DBI on
8482 11:56:55.994742 ==
8483 11:56:55.997790 Dram Type= 6, Freq= 0, CH_1, rank 0
8484 11:56:56.000581 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8485 11:56:56.004333 ==
8486 11:56:56.004413
8487 11:56:56.004477
8488 11:56:56.004536 TX Vref Scan disable
8489 11:56:56.007648 == TX Byte 0 ==
8490 11:56:56.010615 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8491 11:56:56.013774 == TX Byte 1 ==
8492 11:56:56.017752 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8493 11:56:56.020770 DramC Write-DBI off
8494 11:56:56.020850
8495 11:56:56.020913 [DATLAT]
8496 11:56:56.020973 Freq=1600, CH1 RK0
8497 11:56:56.021031
8498 11:56:56.024039 DATLAT Default: 0xf
8499 11:56:56.024120 0, 0xFFFF, sum = 0
8500 11:56:56.027977 1, 0xFFFF, sum = 0
8501 11:56:56.028059 2, 0xFFFF, sum = 0
8502 11:56:56.030652 3, 0xFFFF, sum = 0
8503 11:56:56.033725 4, 0xFFFF, sum = 0
8504 11:56:56.033807 5, 0xFFFF, sum = 0
8505 11:56:56.037219 6, 0xFFFF, sum = 0
8506 11:56:56.037305 7, 0xFFFF, sum = 0
8507 11:56:56.040534 8, 0xFFFF, sum = 0
8508 11:56:56.040603 9, 0xFFFF, sum = 0
8509 11:56:56.043977 10, 0xFFFF, sum = 0
8510 11:56:56.044052 11, 0xFFFF, sum = 0
8511 11:56:56.046909 12, 0xFFFF, sum = 0
8512 11:56:56.046983 13, 0xFFFF, sum = 0
8513 11:56:56.050574 14, 0x0, sum = 1
8514 11:56:56.050649 15, 0x0, sum = 2
8515 11:56:56.053817 16, 0x0, sum = 3
8516 11:56:56.053893 17, 0x0, sum = 4
8517 11:56:56.056909 best_step = 15
8518 11:56:56.057004
8519 11:56:56.057092 ==
8520 11:56:56.061951 Dram Type= 6, Freq= 0, CH_1, rank 0
8521 11:56:56.063865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8522 11:56:56.063964 ==
8523 11:56:56.066859 RX Vref Scan: 1
8524 11:56:56.066933
8525 11:56:56.066994 Set Vref Range= 24 -> 127
8526 11:56:56.067055
8527 11:56:56.070378 RX Vref 24 -> 127, step: 1
8528 11:56:56.070453
8529 11:56:56.073672 RX Delay 27 -> 252, step: 4
8530 11:56:56.073754
8531 11:56:56.077202 Set Vref, RX VrefLevel [Byte0]: 24
8532 11:56:56.080457 [Byte1]: 24
8533 11:56:56.080591
8534 11:56:56.083685 Set Vref, RX VrefLevel [Byte0]: 25
8535 11:56:56.086954 [Byte1]: 25
8536 11:56:56.087035
8537 11:56:56.090648 Set Vref, RX VrefLevel [Byte0]: 26
8538 11:56:56.093968 [Byte1]: 26
8539 11:56:56.097739
8540 11:56:56.097819 Set Vref, RX VrefLevel [Byte0]: 27
8541 11:56:56.101168 [Byte1]: 27
8542 11:56:56.105552
8543 11:56:56.105660 Set Vref, RX VrefLevel [Byte0]: 28
8544 11:56:56.108402 [Byte1]: 28
8545 11:56:56.112645
8546 11:56:56.112728 Set Vref, RX VrefLevel [Byte0]: 29
8547 11:56:56.116120 [Byte1]: 29
8548 11:56:56.120293
8549 11:56:56.120373 Set Vref, RX VrefLevel [Byte0]: 30
8550 11:56:56.123636 [Byte1]: 30
8551 11:56:56.127689
8552 11:56:56.127768 Set Vref, RX VrefLevel [Byte0]: 31
8553 11:56:56.131141 [Byte1]: 31
8554 11:56:56.135496
8555 11:56:56.135576 Set Vref, RX VrefLevel [Byte0]: 32
8556 11:56:56.138588 [Byte1]: 32
8557 11:56:56.142900
8558 11:56:56.142979 Set Vref, RX VrefLevel [Byte0]: 33
8559 11:56:56.146410 [Byte1]: 33
8560 11:56:56.150268
8561 11:56:56.150347 Set Vref, RX VrefLevel [Byte0]: 34
8562 11:56:56.153612 [Byte1]: 34
8563 11:56:56.157479
8564 11:56:56.161354 Set Vref, RX VrefLevel [Byte0]: 35
8565 11:56:56.161459 [Byte1]: 35
8566 11:56:56.165117
8567 11:56:56.165196 Set Vref, RX VrefLevel [Byte0]: 36
8568 11:56:56.168856 [Byte1]: 36
8569 11:56:56.173221
8570 11:56:56.173300 Set Vref, RX VrefLevel [Byte0]: 37
8571 11:56:56.176421 [Byte1]: 37
8572 11:56:56.180572
8573 11:56:56.180652 Set Vref, RX VrefLevel [Byte0]: 38
8574 11:56:56.183937 [Byte1]: 38
8575 11:56:56.188166
8576 11:56:56.188245 Set Vref, RX VrefLevel [Byte0]: 39
8577 11:56:56.191144 [Byte1]: 39
8578 11:56:56.195848
8579 11:56:56.195927 Set Vref, RX VrefLevel [Byte0]: 40
8580 11:56:56.199018 [Byte1]: 40
8581 11:56:56.203220
8582 11:56:56.203331 Set Vref, RX VrefLevel [Byte0]: 41
8583 11:56:56.206460 [Byte1]: 41
8584 11:56:56.210825
8585 11:56:56.210900 Set Vref, RX VrefLevel [Byte0]: 42
8586 11:56:56.214123 [Byte1]: 42
8587 11:56:56.218287
8588 11:56:56.218365 Set Vref, RX VrefLevel [Byte0]: 43
8589 11:56:56.221222 [Byte1]: 43
8590 11:56:56.225351
8591 11:56:56.225463 Set Vref, RX VrefLevel [Byte0]: 44
8592 11:56:56.228992 [Byte1]: 44
8593 11:56:56.233117
8594 11:56:56.233221 Set Vref, RX VrefLevel [Byte0]: 45
8595 11:56:56.236192 [Byte1]: 45
8596 11:56:56.240783
8597 11:56:56.240890 Set Vref, RX VrefLevel [Byte0]: 46
8598 11:56:56.243905 [Byte1]: 46
8599 11:56:56.248338
8600 11:56:56.248439 Set Vref, RX VrefLevel [Byte0]: 47
8601 11:56:56.251668 [Byte1]: 47
8602 11:56:56.255922
8603 11:56:56.256002 Set Vref, RX VrefLevel [Byte0]: 48
8604 11:56:56.258862 [Byte1]: 48
8605 11:56:56.263660
8606 11:56:56.263739 Set Vref, RX VrefLevel [Byte0]: 49
8607 11:56:56.266637 [Byte1]: 49
8608 11:56:56.270754
8609 11:56:56.270833 Set Vref, RX VrefLevel [Byte0]: 50
8610 11:56:56.273861 [Byte1]: 50
8611 11:56:56.278311
8612 11:56:56.278389 Set Vref, RX VrefLevel [Byte0]: 51
8613 11:56:56.281596 [Byte1]: 51
8614 11:56:56.285585
8615 11:56:56.285664 Set Vref, RX VrefLevel [Byte0]: 52
8616 11:56:56.289480 [Byte1]: 52
8617 11:56:56.293190
8618 11:56:56.293268 Set Vref, RX VrefLevel [Byte0]: 53
8619 11:56:56.296617 [Byte1]: 53
8620 11:56:56.300778
8621 11:56:56.300856 Set Vref, RX VrefLevel [Byte0]: 54
8622 11:56:56.304204 [Byte1]: 54
8623 11:56:56.308380
8624 11:56:56.308459 Set Vref, RX VrefLevel [Byte0]: 55
8625 11:56:56.311634 [Byte1]: 55
8626 11:56:56.315833
8627 11:56:56.315911 Set Vref, RX VrefLevel [Byte0]: 56
8628 11:56:56.319364 [Byte1]: 56
8629 11:56:56.323705
8630 11:56:56.323784 Set Vref, RX VrefLevel [Byte0]: 57
8631 11:56:56.326736 [Byte1]: 57
8632 11:56:56.331125
8633 11:56:56.331204 Set Vref, RX VrefLevel [Byte0]: 58
8634 11:56:56.334323 [Byte1]: 58
8635 11:56:56.338782
8636 11:56:56.338863 Set Vref, RX VrefLevel [Byte0]: 59
8637 11:56:56.342020 [Byte1]: 59
8638 11:56:56.346110
8639 11:56:56.346216 Set Vref, RX VrefLevel [Byte0]: 60
8640 11:56:56.349502 [Byte1]: 60
8641 11:56:56.353572
8642 11:56:56.353730 Set Vref, RX VrefLevel [Byte0]: 61
8643 11:56:56.357166 [Byte1]: 61
8644 11:56:56.361530
8645 11:56:56.361677 Set Vref, RX VrefLevel [Byte0]: 62
8646 11:56:56.364535 [Byte1]: 62
8647 11:56:56.368739
8648 11:56:56.368817 Set Vref, RX VrefLevel [Byte0]: 63
8649 11:56:56.371719 [Byte1]: 63
8650 11:56:56.376322
8651 11:56:56.376401 Set Vref, RX VrefLevel [Byte0]: 64
8652 11:56:56.379594 [Byte1]: 64
8653 11:56:56.383776
8654 11:56:56.383855 Set Vref, RX VrefLevel [Byte0]: 65
8655 11:56:56.386816 [Byte1]: 65
8656 11:56:56.391324
8657 11:56:56.391404 Set Vref, RX VrefLevel [Byte0]: 66
8658 11:56:56.394477 [Byte1]: 66
8659 11:56:56.398933
8660 11:56:56.399016 Set Vref, RX VrefLevel [Byte0]: 67
8661 11:56:56.402106 [Byte1]: 67
8662 11:56:56.406692
8663 11:56:56.406771 Set Vref, RX VrefLevel [Byte0]: 68
8664 11:56:56.409558 [Byte1]: 68
8665 11:56:56.414167
8666 11:56:56.414246 Set Vref, RX VrefLevel [Byte0]: 69
8667 11:56:56.417106 [Byte1]: 69
8668 11:56:56.421361
8669 11:56:56.421439 Set Vref, RX VrefLevel [Byte0]: 70
8670 11:56:56.424757 [Byte1]: 70
8671 11:56:56.428655
8672 11:56:56.428734 Set Vref, RX VrefLevel [Byte0]: 71
8673 11:56:56.432012 [Byte1]: 71
8674 11:56:56.436243
8675 11:56:56.436349 Set Vref, RX VrefLevel [Byte0]: 72
8676 11:56:56.439519 [Byte1]: 72
8677 11:56:56.443828
8678 11:56:56.443940 Set Vref, RX VrefLevel [Byte0]: 73
8679 11:56:56.447456 [Byte1]: 73
8680 11:56:56.451536
8681 11:56:56.451616 Set Vref, RX VrefLevel [Byte0]: 74
8682 11:56:56.454781 [Byte1]: 74
8683 11:56:56.459028
8684 11:56:56.459106 Set Vref, RX VrefLevel [Byte0]: 75
8685 11:56:56.462069 [Byte1]: 75
8686 11:56:56.466986
8687 11:56:56.467073 Final RX Vref Byte 0 = 57 to rank0
8688 11:56:56.470089 Final RX Vref Byte 1 = 62 to rank0
8689 11:56:56.473419 Final RX Vref Byte 0 = 57 to rank1
8690 11:56:56.476446 Final RX Vref Byte 1 = 62 to rank1==
8691 11:56:56.480247 Dram Type= 6, Freq= 0, CH_1, rank 0
8692 11:56:56.486769 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8693 11:56:56.486883 ==
8694 11:56:56.486987 DQS Delay:
8695 11:56:56.487084 DQS0 = 0, DQS1 = 0
8696 11:56:56.490180 DQM Delay:
8697 11:56:56.490288 DQM0 = 133, DQM1 = 131
8698 11:56:56.493126 DQ Delay:
8699 11:56:56.496300 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8700 11:56:56.499873 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8701 11:56:56.503053 DQ8 =118, DQ9 =120, DQ10 =132, DQ11 =124
8702 11:56:56.506760 DQ12 =140, DQ13 =138, DQ14 =138, DQ15 =140
8703 11:56:56.506842
8704 11:56:56.506924
8705 11:56:56.507002
8706 11:56:56.509754 [DramC_TX_OE_Calibration] TA2
8707 11:56:56.512934 Original DQ_B0 (3 6) =30, OEN = 27
8708 11:56:56.516203 Original DQ_B1 (3 6) =30, OEN = 27
8709 11:56:56.519364 24, 0x0, End_B0=24 End_B1=24
8710 11:56:56.519448 25, 0x0, End_B0=25 End_B1=25
8711 11:56:56.523092 26, 0x0, End_B0=26 End_B1=26
8712 11:56:56.526149 27, 0x0, End_B0=27 End_B1=27
8713 11:56:56.529820 28, 0x0, End_B0=28 End_B1=28
8714 11:56:56.532851 29, 0x0, End_B0=29 End_B1=29
8715 11:56:56.532938 30, 0x0, End_B0=30 End_B1=30
8716 11:56:56.536419 31, 0x4545, End_B0=30 End_B1=30
8717 11:56:56.539720 Byte0 end_step=30 best_step=27
8718 11:56:56.542754 Byte1 end_step=30 best_step=27
8719 11:56:56.546186 Byte0 TX OE(2T, 0.5T) = (3, 3)
8720 11:56:56.549603 Byte1 TX OE(2T, 0.5T) = (3, 3)
8721 11:56:56.549699
8722 11:56:56.549781
8723 11:56:56.556239 [DQSOSCAuto] RK0, (LSB)MR18= 0x1825, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
8724 11:56:56.559397 CH1 RK0: MR19=303, MR18=1825
8725 11:56:56.566467 CH1_RK0: MR19=0x303, MR18=0x1825, DQSOSC=391, MR23=63, INC=24, DEC=16
8726 11:56:56.566551
8727 11:56:56.569537 ----->DramcWriteLeveling(PI) begin...
8728 11:56:56.569654 ==
8729 11:56:56.572367 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 11:56:56.576066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 11:56:56.576148 ==
8732 11:56:56.579241 Write leveling (Byte 0): 26 => 26
8733 11:56:56.582548 Write leveling (Byte 1): 29 => 29
8734 11:56:56.585985 DramcWriteLeveling(PI) end<-----
8735 11:56:56.586067
8736 11:56:56.586164 ==
8737 11:56:56.589044 Dram Type= 6, Freq= 0, CH_1, rank 1
8738 11:56:56.592834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 11:56:56.592915 ==
8740 11:56:56.595801 [Gating] SW mode calibration
8741 11:56:56.602811 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8742 11:56:56.608909 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8743 11:56:56.612715 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 11:56:56.619079 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 11:56:56.623108 1 4 8 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
8746 11:56:56.626120 1 4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
8747 11:56:56.629329 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8748 11:56:56.636350 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8749 11:56:56.639393 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8750 11:56:56.642455 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8751 11:56:56.649256 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8752 11:56:56.652483 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8753 11:56:56.655653 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 1)
8754 11:56:56.662735 1 5 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8755 11:56:56.666360 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8756 11:56:56.669421 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8757 11:56:56.676187 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8758 11:56:56.679223 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8759 11:56:56.682572 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8760 11:56:56.689280 1 6 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8761 11:56:56.692538 1 6 8 | B1->B0 | 3f3f 2424 | 1 0 | (0 0) (0 0)
8762 11:56:56.696116 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
8763 11:56:56.702382 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8764 11:56:56.705826 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8765 11:56:56.709433 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8766 11:56:56.715827 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8767 11:56:56.719271 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8768 11:56:56.722551 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8769 11:56:56.725568 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8770 11:56:56.732420 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8771 11:56:56.735613 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8772 11:56:56.739242 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 11:56:56.746054 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 11:56:56.749074 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 11:56:56.752275 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 11:56:56.758907 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8777 11:56:56.762806 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 11:56:56.765708 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:56:56.772665 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:56:56.775920 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:56:56.778916 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:56:56.786288 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:56:56.788595 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:56:56.792096 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:56:56.798999 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8786 11:56:56.802130 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8787 11:56:56.805386 Total UI for P1: 0, mck2ui 16
8788 11:56:56.808906 best dqsien dly found for B1: ( 1, 9, 8)
8789 11:56:56.812492 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8790 11:56:56.818752 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8791 11:56:56.818832 Total UI for P1: 0, mck2ui 16
8792 11:56:56.825478 best dqsien dly found for B0: ( 1, 9, 14)
8793 11:56:56.828578 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8794 11:56:56.832164 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8795 11:56:56.832243
8796 11:56:56.835341 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8797 11:56:56.838789 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8798 11:56:56.842484 [Gating] SW calibration Done
8799 11:56:56.842564 ==
8800 11:56:56.845548 Dram Type= 6, Freq= 0, CH_1, rank 1
8801 11:56:56.849237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8802 11:56:56.849343 ==
8803 11:56:56.852527 RX Vref Scan: 0
8804 11:56:56.852606
8805 11:56:56.852668 RX Vref 0 -> 0, step: 1
8806 11:56:56.852727
8807 11:56:56.855636 RX Delay 0 -> 252, step: 8
8808 11:56:56.859149 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8809 11:56:56.862243 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8810 11:56:56.868846 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8811 11:56:56.871970 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8812 11:56:56.875735 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8813 11:56:56.878850 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8814 11:56:56.882279 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8815 11:56:56.888563 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8816 11:56:56.892331 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8817 11:56:56.895384 iDelay=208, Bit 9, Center 123 (72 ~ 175) 104
8818 11:56:56.898998 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8819 11:56:56.902076 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8820 11:56:56.908447 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8821 11:56:56.912090 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8822 11:56:56.915516 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8823 11:56:56.918674 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8824 11:56:56.918753 ==
8825 11:56:56.922187 Dram Type= 6, Freq= 0, CH_1, rank 1
8826 11:56:56.928653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8827 11:56:56.928730 ==
8828 11:56:56.928791 DQS Delay:
8829 11:56:56.928849 DQS0 = 0, DQS1 = 0
8830 11:56:56.931914 DQM Delay:
8831 11:56:56.932007 DQM0 = 136, DQM1 = 134
8832 11:56:56.935398 DQ Delay:
8833 11:56:56.938733 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8834 11:56:56.942484 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8835 11:56:56.945744 DQ8 =119, DQ9 =123, DQ10 =135, DQ11 =127
8836 11:56:56.948384 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8837 11:56:56.948455
8838 11:56:56.948515
8839 11:56:56.948571 ==
8840 11:56:56.952130 Dram Type= 6, Freq= 0, CH_1, rank 1
8841 11:56:56.955376 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8842 11:56:56.958714 ==
8843 11:56:56.958785
8844 11:56:56.958845
8845 11:56:56.958900 TX Vref Scan disable
8846 11:56:56.962526 == TX Byte 0 ==
8847 11:56:56.965524 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8848 11:56:56.968525 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8849 11:56:56.972118 == TX Byte 1 ==
8850 11:56:56.975201 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8851 11:56:56.978362 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8852 11:56:56.978436 ==
8853 11:56:56.982186 Dram Type= 6, Freq= 0, CH_1, rank 1
8854 11:56:56.988525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8855 11:56:56.988597 ==
8856 11:56:57.001539
8857 11:56:57.004593 TX Vref early break, caculate TX vref
8858 11:56:57.008182 TX Vref=16, minBit 1, minWin=23, winSum=382
8859 11:56:57.011330 TX Vref=18, minBit 6, minWin=23, winSum=391
8860 11:56:57.015156 TX Vref=20, minBit 0, minWin=23, winSum=402
8861 11:56:57.018200 TX Vref=22, minBit 0, minWin=24, winSum=407
8862 11:56:57.021280 TX Vref=24, minBit 0, minWin=25, winSum=418
8863 11:56:57.028457 TX Vref=26, minBit 0, minWin=25, winSum=424
8864 11:56:57.031467 TX Vref=28, minBit 0, minWin=25, winSum=425
8865 11:56:57.035207 TX Vref=30, minBit 1, minWin=25, winSum=421
8866 11:56:57.038075 TX Vref=32, minBit 0, minWin=25, winSum=414
8867 11:56:57.041604 TX Vref=34, minBit 0, minWin=24, winSum=404
8868 11:56:57.044806 TX Vref=36, minBit 0, minWin=24, winSum=398
8869 11:56:57.051535 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8870 11:56:57.051610
8871 11:56:57.054746 Final TX Range 0 Vref 28
8872 11:56:57.054819
8873 11:56:57.054879 ==
8874 11:56:57.058006 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 11:56:57.061613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 11:56:57.061692 ==
8877 11:56:57.061754
8878 11:56:57.061809
8879 11:56:57.064985 TX Vref Scan disable
8880 11:56:57.071510 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8881 11:56:57.071582 == TX Byte 0 ==
8882 11:56:57.074747 u2DelayCellOfst[0]=17 cells (5 PI)
8883 11:56:57.078049 u2DelayCellOfst[1]=10 cells (3 PI)
8884 11:56:57.081568 u2DelayCellOfst[2]=0 cells (0 PI)
8885 11:56:57.084647 u2DelayCellOfst[3]=6 cells (2 PI)
8886 11:56:57.088441 u2DelayCellOfst[4]=10 cells (3 PI)
8887 11:56:57.091351 u2DelayCellOfst[5]=20 cells (6 PI)
8888 11:56:57.094870 u2DelayCellOfst[6]=17 cells (5 PI)
8889 11:56:57.097890 u2DelayCellOfst[7]=6 cells (2 PI)
8890 11:56:57.101698 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8891 11:56:57.104696 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8892 11:56:57.107953 == TX Byte 1 ==
8893 11:56:57.108027 u2DelayCellOfst[8]=0 cells (0 PI)
8894 11:56:57.111753 u2DelayCellOfst[9]=3 cells (1 PI)
8895 11:56:57.114630 u2DelayCellOfst[10]=10 cells (3 PI)
8896 11:56:57.117786 u2DelayCellOfst[11]=3 cells (1 PI)
8897 11:56:57.121543 u2DelayCellOfst[12]=13 cells (4 PI)
8898 11:56:57.124708 u2DelayCellOfst[13]=17 cells (5 PI)
8899 11:56:57.128131 u2DelayCellOfst[14]=17 cells (5 PI)
8900 11:56:57.131661 u2DelayCellOfst[15]=17 cells (5 PI)
8901 11:56:57.134816 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8902 11:56:57.141692 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8903 11:56:57.141772 DramC Write-DBI on
8904 11:56:57.141837 ==
8905 11:56:57.144479 Dram Type= 6, Freq= 0, CH_1, rank 1
8906 11:56:57.148280 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8907 11:56:57.151331 ==
8908 11:56:57.151406
8909 11:56:57.151466
8910 11:56:57.151522 TX Vref Scan disable
8911 11:56:57.154453 == TX Byte 0 ==
8912 11:56:57.157977 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8913 11:56:57.160981 == TX Byte 1 ==
8914 11:56:57.164542 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8915 11:56:57.167681 DramC Write-DBI off
8916 11:56:57.167747
8917 11:56:57.167807 [DATLAT]
8918 11:56:57.167866 Freq=1600, CH1 RK1
8919 11:56:57.167920
8920 11:56:57.171077 DATLAT Default: 0xf
8921 11:56:57.171145 0, 0xFFFF, sum = 0
8922 11:56:57.174514 1, 0xFFFF, sum = 0
8923 11:56:57.177741 2, 0xFFFF, sum = 0
8924 11:56:57.177816 3, 0xFFFF, sum = 0
8925 11:56:57.181173 4, 0xFFFF, sum = 0
8926 11:56:57.181247 5, 0xFFFF, sum = 0
8927 11:56:57.184706 6, 0xFFFF, sum = 0
8928 11:56:57.184798 7, 0xFFFF, sum = 0
8929 11:56:57.188236 8, 0xFFFF, sum = 0
8930 11:56:57.188314 9, 0xFFFF, sum = 0
8931 11:56:57.191280 10, 0xFFFF, sum = 0
8932 11:56:57.191352 11, 0xFFFF, sum = 0
8933 11:56:57.194740 12, 0xFFFF, sum = 0
8934 11:56:57.194813 13, 0xFFFF, sum = 0
8935 11:56:57.197815 14, 0x0, sum = 1
8936 11:56:57.197889 15, 0x0, sum = 2
8937 11:56:57.201788 16, 0x0, sum = 3
8938 11:56:57.201861 17, 0x0, sum = 4
8939 11:56:57.204493 best_step = 15
8940 11:56:57.204567
8941 11:56:57.204626 ==
8942 11:56:57.208089 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 11:56:57.211168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 11:56:57.211238 ==
8945 11:56:57.211303 RX Vref Scan: 0
8946 11:56:57.214333
8947 11:56:57.214402 RX Vref 0 -> 0, step: 1
8948 11:56:57.214464
8949 11:56:57.217695 RX Delay 19 -> 252, step: 4
8950 11:56:57.221235 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8951 11:56:57.227891 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8952 11:56:57.230999 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8953 11:56:57.234996 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8954 11:56:57.237831 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8955 11:56:57.241015 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8956 11:56:57.244705 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8957 11:56:57.251303 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8958 11:56:57.254502 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8959 11:56:57.258070 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8960 11:56:57.261160 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8961 11:56:57.264413 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8962 11:56:57.271117 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8963 11:56:57.274423 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8964 11:56:57.277595 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8965 11:56:57.281189 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8966 11:56:57.281271 ==
8967 11:56:57.284446 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 11:56:57.291079 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 11:56:57.291162 ==
8970 11:56:57.291245 DQS Delay:
8971 11:56:57.291324 DQS0 = 0, DQS1 = 0
8972 11:56:57.294716 DQM Delay:
8973 11:56:57.294819 DQM0 = 134, DQM1 = 130
8974 11:56:57.297694 DQ Delay:
8975 11:56:57.301703 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
8976 11:56:57.304316 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8977 11:56:57.307844 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8978 11:56:57.311021 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8979 11:56:57.311103
8980 11:56:57.311186
8981 11:56:57.311264
8982 11:56:57.314225 [DramC_TX_OE_Calibration] TA2
8983 11:56:57.317948 Original DQ_B0 (3 6) =30, OEN = 27
8984 11:56:57.320824 Original DQ_B1 (3 6) =30, OEN = 27
8985 11:56:57.324567 24, 0x0, End_B0=24 End_B1=24
8986 11:56:57.324651 25, 0x0, End_B0=25 End_B1=25
8987 11:56:57.327817 26, 0x0, End_B0=26 End_B1=26
8988 11:56:57.330805 27, 0x0, End_B0=27 End_B1=27
8989 11:56:57.334691 28, 0x0, End_B0=28 End_B1=28
8990 11:56:57.337688 29, 0x0, End_B0=29 End_B1=29
8991 11:56:57.337771 30, 0x0, End_B0=30 End_B1=30
8992 11:56:57.340740 31, 0x4141, End_B0=30 End_B1=30
8993 11:56:57.344036 Byte0 end_step=30 best_step=27
8994 11:56:57.347692 Byte1 end_step=30 best_step=27
8995 11:56:57.350915 Byte0 TX OE(2T, 0.5T) = (3, 3)
8996 11:56:57.354600 Byte1 TX OE(2T, 0.5T) = (3, 3)
8997 11:56:57.354675
8998 11:56:57.354735
8999 11:56:57.360868 [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
9000 11:56:57.364325 CH1 RK1: MR19=303, MR18=2207
9001 11:56:57.371116 CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16
9002 11:56:57.374881 [RxdqsGatingPostProcess] freq 1600
9003 11:56:57.377795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9004 11:56:57.380833 best DQS0 dly(2T, 0.5T) = (1, 1)
9005 11:56:57.384315 best DQS1 dly(2T, 0.5T) = (1, 1)
9006 11:56:57.387724 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9007 11:56:57.390611 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9008 11:56:57.394243 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 11:56:57.397321 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 11:56:57.401021 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 11:56:57.404132 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 11:56:57.407774 Pre-setting of DQS Precalculation
9013 11:56:57.410884 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9014 11:56:57.417511 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9015 11:56:57.424184 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9016 11:56:57.427200
9017 11:56:57.427281
9018 11:56:57.427364 [Calibration Summary] 3200 Mbps
9019 11:56:57.431198 CH 0, Rank 0
9020 11:56:57.431280 SW Impedance : PASS
9021 11:56:57.433818 DUTY Scan : NO K
9022 11:56:57.437378 ZQ Calibration : PASS
9023 11:56:57.437485 Jitter Meter : NO K
9024 11:56:57.440553 CBT Training : PASS
9025 11:56:57.444103 Write leveling : PASS
9026 11:56:57.444186 RX DQS gating : PASS
9027 11:56:57.447285 RX DQ/DQS(RDDQC) : PASS
9028 11:56:57.450387 TX DQ/DQS : PASS
9029 11:56:57.450469 RX DATLAT : PASS
9030 11:56:57.453526 RX DQ/DQS(Engine): PASS
9031 11:56:57.457314 TX OE : PASS
9032 11:56:57.457420 All Pass.
9033 11:56:57.457519
9034 11:56:57.457638 CH 0, Rank 1
9035 11:56:57.460368 SW Impedance : PASS
9036 11:56:57.463639 DUTY Scan : NO K
9037 11:56:57.463721 ZQ Calibration : PASS
9038 11:56:57.467661 Jitter Meter : NO K
9039 11:56:57.470219 CBT Training : PASS
9040 11:56:57.470300 Write leveling : PASS
9041 11:56:57.474152 RX DQS gating : PASS
9042 11:56:57.474233 RX DQ/DQS(RDDQC) : PASS
9043 11:56:57.477338 TX DQ/DQS : PASS
9044 11:56:57.480638 RX DATLAT : PASS
9045 11:56:57.480720 RX DQ/DQS(Engine): PASS
9046 11:56:57.483577 TX OE : PASS
9047 11:56:57.483659 All Pass.
9048 11:56:57.483742
9049 11:56:57.487071 CH 1, Rank 0
9050 11:56:57.487177 SW Impedance : PASS
9051 11:56:57.490184 DUTY Scan : NO K
9052 11:56:57.493857 ZQ Calibration : PASS
9053 11:56:57.493939 Jitter Meter : NO K
9054 11:56:57.497264 CBT Training : PASS
9055 11:56:57.500596 Write leveling : PASS
9056 11:56:57.500678 RX DQS gating : PASS
9057 11:56:57.503809 RX DQ/DQS(RDDQC) : PASS
9058 11:56:57.507708 TX DQ/DQS : PASS
9059 11:56:57.507790 RX DATLAT : PASS
9060 11:56:57.510437 RX DQ/DQS(Engine): PASS
9061 11:56:57.513534 TX OE : PASS
9062 11:56:57.513640 All Pass.
9063 11:56:57.513724
9064 11:56:57.513819 CH 1, Rank 1
9065 11:56:57.517153 SW Impedance : PASS
9066 11:56:57.520391 DUTY Scan : NO K
9067 11:56:57.520474 ZQ Calibration : PASS
9068 11:56:57.523512 Jitter Meter : NO K
9069 11:56:57.523593 CBT Training : PASS
9070 11:56:57.527227 Write leveling : PASS
9071 11:56:57.530200 RX DQS gating : PASS
9072 11:56:57.530281 RX DQ/DQS(RDDQC) : PASS
9073 11:56:57.533913 TX DQ/DQS : PASS
9074 11:56:57.536829 RX DATLAT : PASS
9075 11:56:57.536910 RX DQ/DQS(Engine): PASS
9076 11:56:57.540720 TX OE : PASS
9077 11:56:57.540802 All Pass.
9078 11:56:57.540885
9079 11:56:57.543818 DramC Write-DBI on
9080 11:56:57.546809 PER_BANK_REFRESH: Hybrid Mode
9081 11:56:57.546891 TX_TRACKING: ON
9082 11:56:57.557022 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9083 11:56:57.563473 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9084 11:56:57.570397 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9085 11:56:57.573325 [FAST_K] Save calibration result to emmc
9086 11:56:57.577229 sync common calibartion params.
9087 11:56:57.580348 sync cbt_mode0:1, 1:1
9088 11:56:57.583406 dram_init: ddr_geometry: 2
9089 11:56:57.583488 dram_init: ddr_geometry: 2
9090 11:56:57.587057 dram_init: ddr_geometry: 2
9091 11:56:57.590530 0:dram_rank_size:100000000
9092 11:56:57.593490 1:dram_rank_size:100000000
9093 11:56:57.596836 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9094 11:56:57.600511 DFS_SHUFFLE_HW_MODE: ON
9095 11:56:57.603436 dramc_set_vcore_voltage set vcore to 725000
9096 11:56:57.607059 Read voltage for 1600, 0
9097 11:56:57.607144 Vio18 = 0
9098 11:56:57.607235 Vcore = 725000
9099 11:56:57.609978 Vdram = 0
9100 11:56:57.610059 Vddq = 0
9101 11:56:57.610143 Vmddr = 0
9102 11:56:57.613447 switch to 3200 Mbps bootup
9103 11:56:57.613529 [DramcRunTimeConfig]
9104 11:56:57.616758 PHYPLL
9105 11:56:57.616840 DPM_CONTROL_AFTERK: ON
9106 11:56:57.620188 PER_BANK_REFRESH: ON
9107 11:56:57.623325 REFRESH_OVERHEAD_REDUCTION: ON
9108 11:56:57.623406 CMD_PICG_NEW_MODE: OFF
9109 11:56:57.627050 XRTWTW_NEW_MODE: ON
9110 11:56:57.627132 XRTRTR_NEW_MODE: ON
9111 11:56:57.630145 TX_TRACKING: ON
9112 11:56:57.630226 RDSEL_TRACKING: OFF
9113 11:56:57.633394 DQS Precalculation for DVFS: ON
9114 11:56:57.636566 RX_TRACKING: OFF
9115 11:56:57.636648 HW_GATING DBG: ON
9116 11:56:57.639885 ZQCS_ENABLE_LP4: ON
9117 11:56:57.640031 RX_PICG_NEW_MODE: ON
9118 11:56:57.643490 TX_PICG_NEW_MODE: ON
9119 11:56:57.646793 ENABLE_RX_DCM_DPHY: ON
9120 11:56:57.649772 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9121 11:56:57.649854 DUMMY_READ_FOR_TRACKING: OFF
9122 11:56:57.653216 !!! SPM_CONTROL_AFTERK: OFF
9123 11:56:57.656234 !!! SPM could not control APHY
9124 11:56:57.659718 IMPEDANCE_TRACKING: ON
9125 11:56:57.659799 TEMP_SENSOR: ON
9126 11:56:57.663330 HW_SAVE_FOR_SR: OFF
9127 11:56:57.663413 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9128 11:56:57.669894 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9129 11:56:57.669977 Read ODT Tracking: ON
9130 11:56:57.673231 Refresh Rate DeBounce: ON
9131 11:56:57.673312 DFS_NO_QUEUE_FLUSH: ON
9132 11:56:57.676225 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9133 11:56:57.679429 ENABLE_DFS_RUNTIME_MRW: OFF
9134 11:56:57.683185 DDR_RESERVE_NEW_MODE: ON
9135 11:56:57.683307 MR_CBT_SWITCH_FREQ: ON
9136 11:56:57.686497 =========================
9137 11:56:57.706206 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9138 11:56:57.708964 dram_init: ddr_geometry: 2
9139 11:56:57.727435 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9140 11:56:57.730828 dram_init: dram init end (result: 0)
9141 11:56:57.736977 DRAM-K: Full calibration passed in 24459 msecs
9142 11:56:57.740572 MRC: failed to locate region type 0.
9143 11:56:57.740652 DRAM rank0 size:0x100000000,
9144 11:56:57.744091 DRAM rank1 size=0x100000000
9145 11:56:57.753964 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9146 11:56:57.760157 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9147 11:56:57.766798 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9148 11:56:57.773727 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9149 11:56:57.776941 DRAM rank0 size:0x100000000,
9150 11:56:57.780013 DRAM rank1 size=0x100000000
9151 11:56:57.780081 CBMEM:
9152 11:56:57.783501 IMD: root @ 0xfffff000 254 entries.
9153 11:56:57.786562 IMD: root @ 0xffffec00 62 entries.
9154 11:56:57.790126 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9155 11:56:57.796913 WARNING: RO_VPD is uninitialized or empty.
9156 11:56:57.800104 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9157 11:56:57.807056 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9158 11:56:57.820318 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9159 11:56:57.831551 BS: romstage times (exec / console): total (unknown) / 23988 ms
9160 11:56:57.831628
9161 11:56:57.831690
9162 11:56:57.841789 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9163 11:56:57.844784 ARM64: Exception handlers installed.
9164 11:56:57.848493 ARM64: Testing exception
9165 11:56:57.851229 ARM64: Done test exception
9166 11:56:57.851297 Enumerating buses...
9167 11:56:57.854416 Show all devs... Before device enumeration.
9168 11:56:57.858079 Root Device: enabled 1
9169 11:56:57.861251 CPU_CLUSTER: 0: enabled 1
9170 11:56:57.861317 CPU: 00: enabled 1
9171 11:56:57.864515 Compare with tree...
9172 11:56:57.864579 Root Device: enabled 1
9173 11:56:57.868303 CPU_CLUSTER: 0: enabled 1
9174 11:56:57.871157 CPU: 00: enabled 1
9175 11:56:57.871221 Root Device scanning...
9176 11:56:57.874226 scan_static_bus for Root Device
9177 11:56:57.878320 CPU_CLUSTER: 0 enabled
9178 11:56:57.881228 scan_static_bus for Root Device done
9179 11:56:57.884209 scan_bus: bus Root Device finished in 8 msecs
9180 11:56:57.884282 done
9181 11:56:57.891090 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9182 11:56:57.894601 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9183 11:56:57.901012 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9184 11:56:57.904355 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9185 11:56:57.907549 Allocating resources...
9186 11:56:57.911439 Reading resources...
9187 11:56:57.914473 Root Device read_resources bus 0 link: 0
9188 11:56:57.914542 DRAM rank0 size:0x100000000,
9189 11:56:57.917593 DRAM rank1 size=0x100000000
9190 11:56:57.921391 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9191 11:56:57.924638 CPU: 00 missing read_resources
9192 11:56:57.927872 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9193 11:56:57.934739 Root Device read_resources bus 0 link: 0 done
9194 11:56:57.934808 Done reading resources.
9195 11:56:57.941375 Show resources in subtree (Root Device)...After reading.
9196 11:56:57.944807 Root Device child on link 0 CPU_CLUSTER: 0
9197 11:56:57.947892 CPU_CLUSTER: 0 child on link 0 CPU: 00
9198 11:56:57.958189 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9199 11:56:57.958271 CPU: 00
9200 11:56:57.961350 Root Device assign_resources, bus 0 link: 0
9201 11:56:57.964333 CPU_CLUSTER: 0 missing set_resources
9202 11:56:57.967974 Root Device assign_resources, bus 0 link: 0 done
9203 11:56:57.970950 Done setting resources.
9204 11:56:57.977867 Show resources in subtree (Root Device)...After assigning values.
9205 11:56:57.981115 Root Device child on link 0 CPU_CLUSTER: 0
9206 11:56:57.984229 CPU_CLUSTER: 0 child on link 0 CPU: 00
9207 11:56:57.994113 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9208 11:56:57.994191 CPU: 00
9209 11:56:57.997442 Done allocating resources.
9210 11:56:58.001061 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9211 11:56:58.004173 Enabling resources...
9212 11:56:58.004243 done.
9213 11:56:58.010481 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9214 11:56:58.010560 Initializing devices...
9215 11:56:58.013869 Root Device init
9216 11:56:58.013946 init hardware done!
9217 11:56:58.017716 0x00000018: ctrlr->caps
9218 11:56:58.020880 52.000 MHz: ctrlr->f_max
9219 11:56:58.020949 0.400 MHz: ctrlr->f_min
9220 11:56:58.023962 0x40ff8080: ctrlr->voltages
9221 11:56:58.024036 sclk: 390625
9222 11:56:58.027166 Bus Width = 1
9223 11:56:58.027238 sclk: 390625
9224 11:56:58.030811 Bus Width = 1
9225 11:56:58.030889 Early init status = 3
9226 11:56:58.037021 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9227 11:56:58.040887 in-header: 03 fc 00 00 01 00 00 00
9228 11:56:58.043884 in-data: 00
9229 11:56:58.047242 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9230 11:56:58.052321 in-header: 03 fd 00 00 00 00 00 00
9231 11:56:58.055939 in-data:
9232 11:56:58.058680 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9233 11:56:58.063354 in-header: 03 fc 00 00 01 00 00 00
9234 11:56:58.066681 in-data: 00
9235 11:56:58.069684 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9236 11:56:58.075378 in-header: 03 fd 00 00 00 00 00 00
9237 11:56:58.079190 in-data:
9238 11:56:58.081883 [SSUSB] Setting up USB HOST controller...
9239 11:56:58.085459 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9240 11:56:58.088546 [SSUSB] phy power-on done.
9241 11:56:58.092398 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9242 11:56:58.098924 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9243 11:56:58.102002 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9244 11:56:58.108568 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9245 11:56:58.115471 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9246 11:56:58.121914 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9247 11:56:58.128243 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9248 11:56:58.135379 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9249 11:56:58.138455 SPM: binary array size = 0x9dc
9250 11:56:58.141768 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9251 11:56:58.147879 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9252 11:56:58.155150 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9253 11:56:58.161486 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9254 11:56:58.164685 configure_display: Starting display init
9255 11:56:58.198467 anx7625_power_on_init: Init interface.
9256 11:56:58.202107 anx7625_disable_pd_protocol: Disabled PD feature.
9257 11:56:58.205332 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9258 11:56:58.233459 anx7625_start_dp_work: Secure OCM version=00
9259 11:56:58.236380 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9260 11:56:58.251361 sp_tx_get_edid_block: EDID Block = 1
9261 11:56:58.353832 Extracted contents:
9262 11:56:58.357135 header: 00 ff ff ff ff ff ff 00
9263 11:56:58.360374 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9264 11:56:58.363458 version: 01 04
9265 11:56:58.366771 basic params: 95 1f 11 78 0a
9266 11:56:58.370336 chroma info: 76 90 94 55 54 90 27 21 50 54
9267 11:56:58.373493 established: 00 00 00
9268 11:56:58.380502 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9269 11:56:58.384335 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9270 11:56:58.390500 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9271 11:56:58.396793 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9272 11:56:58.403663 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9273 11:56:58.406589 extensions: 00
9274 11:56:58.406665 checksum: fb
9275 11:56:58.406745
9276 11:56:58.410241 Manufacturer: IVO Model 57d Serial Number 0
9277 11:56:58.413550 Made week 0 of 2020
9278 11:56:58.413665 EDID version: 1.4
9279 11:56:58.417063 Digital display
9280 11:56:58.420294 6 bits per primary color channel
9281 11:56:58.420378 DisplayPort interface
9282 11:56:58.423404 Maximum image size: 31 cm x 17 cm
9283 11:56:58.426719 Gamma: 220%
9284 11:56:58.426838 Check DPMS levels
9285 11:56:58.429842 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9286 11:56:58.433476 First detailed timing is preferred timing
9287 11:56:58.436728 Established timings supported:
9288 11:56:58.439997 Standard timings supported:
9289 11:56:58.443258 Detailed timings
9290 11:56:58.446362 Hex of detail: 383680a07038204018303c0035ae10000019
9291 11:56:58.450130 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9292 11:56:58.456736 0780 0798 07c8 0820 hborder 0
9293 11:56:58.459667 0438 043b 0447 0458 vborder 0
9294 11:56:58.463209 -hsync -vsync
9295 11:56:58.463347 Did detailed timing
9296 11:56:58.469570 Hex of detail: 000000000000000000000000000000000000
9297 11:56:58.469682 Manufacturer-specified data, tag 0
9298 11:56:58.476616 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9299 11:56:58.479643 ASCII string: InfoVision
9300 11:56:58.482919 Hex of detail: 000000fe00523134304e574635205248200a
9301 11:56:58.486573 ASCII string: R140NWF5 RH
9302 11:56:58.486651 Checksum
9303 11:56:58.486713 Checksum: 0xfb (valid)
9304 11:56:58.493199 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9305 11:56:58.496214 DSI data_rate: 832800000 bps
9306 11:56:58.499796 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9307 11:56:58.506664 anx7625_parse_edid: pixelclock(138800).
9308 11:56:58.509459 hactive(1920), hsync(48), hfp(24), hbp(88)
9309 11:56:58.513114 vactive(1080), vsync(12), vfp(3), vbp(17)
9310 11:56:58.516293 anx7625_dsi_config: config dsi.
9311 11:56:58.523085 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9312 11:56:58.535925 anx7625_dsi_config: success to config DSI
9313 11:56:58.539382 anx7625_dp_start: MIPI phy setup OK.
9314 11:56:58.542103 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9315 11:56:58.545725 mtk_ddp_mode_set invalid vrefresh 60
9316 11:56:58.548887 main_disp_path_setup
9317 11:56:58.548967 ovl_layer_smi_id_en
9318 11:56:58.552308 ovl_layer_smi_id_en
9319 11:56:58.552418 ccorr_config
9320 11:56:58.552508 aal_config
9321 11:56:58.555413 gamma_config
9322 11:56:58.555494 postmask_config
9323 11:56:58.558453 dither_config
9324 11:56:58.561804 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9325 11:56:58.568832 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9326 11:56:58.571899 Root Device init finished in 555 msecs
9327 11:56:58.575514 CPU_CLUSTER: 0 init
9328 11:56:58.582092 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9329 11:56:58.588837 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9330 11:56:58.588920 APU_MBOX 0x190000b0 = 0x10001
9331 11:56:58.591866 APU_MBOX 0x190001b0 = 0x10001
9332 11:56:58.595600 APU_MBOX 0x190005b0 = 0x10001
9333 11:56:58.598538 APU_MBOX 0x190006b0 = 0x10001
9334 11:56:58.605347 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9335 11:56:58.614333 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9336 11:56:58.626977 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9337 11:56:58.633504 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9338 11:56:58.645827 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9339 11:56:58.654759 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9340 11:56:58.657811 CPU_CLUSTER: 0 init finished in 81 msecs
9341 11:56:58.661456 Devices initialized
9342 11:56:58.664550 Show all devs... After init.
9343 11:56:58.664644 Root Device: enabled 1
9344 11:56:58.667952 CPU_CLUSTER: 0: enabled 1
9345 11:56:58.671135 CPU: 00: enabled 1
9346 11:56:58.674569 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9347 11:56:58.677711 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9348 11:56:58.681369 ELOG: NV offset 0x57f000 size 0x1000
9349 11:56:58.687864 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9350 11:56:58.694522 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9351 11:56:58.697499 ELOG: Event(17) added with size 13 at 2023-11-23 11:54:46 UTC
9352 11:56:58.701207 out: cmd=0x121: 03 db 21 01 00 00 00 00
9353 11:56:58.704917 in-header: 03 da 00 00 2c 00 00 00
9354 11:56:58.717926 in-data: 85 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9355 11:56:58.724620 ELOG: Event(A1) added with size 10 at 2023-11-23 11:54:46 UTC
9356 11:56:58.732142 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9357 11:56:58.738061 ELOG: Event(A0) added with size 9 at 2023-11-23 11:54:46 UTC
9358 11:56:58.741557 elog_add_boot_reason: Logged dev mode boot
9359 11:56:58.744928 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9360 11:56:58.748220 Finalize devices...
9361 11:56:58.748303 Devices finalized
9362 11:56:58.754627 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9363 11:56:58.757804 Writing coreboot table at 0xffe64000
9364 11:56:58.761787 0. 000000000010a000-0000000000113fff: RAMSTAGE
9365 11:56:58.765106 1. 0000000040000000-00000000400fffff: RAM
9366 11:56:58.767762 2. 0000000040100000-000000004032afff: RAMSTAGE
9367 11:56:58.774582 3. 000000004032b000-00000000545fffff: RAM
9368 11:56:58.778032 4. 0000000054600000-000000005465ffff: BL31
9369 11:56:58.781247 5. 0000000054660000-00000000ffe63fff: RAM
9370 11:56:58.788030 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9371 11:56:58.791077 7. 0000000100000000-000000023fffffff: RAM
9372 11:56:58.791158 Passing 5 GPIOs to payload:
9373 11:56:58.797726 NAME | PORT | POLARITY | VALUE
9374 11:56:58.801130 EC in RW | 0x000000aa | low | undefined
9375 11:56:58.807509 EC interrupt | 0x00000005 | low | undefined
9376 11:56:58.811338 TPM interrupt | 0x000000ab | high | undefined
9377 11:56:58.814533 SD card detect | 0x00000011 | high | undefined
9378 11:56:58.821319 speaker enable | 0x00000093 | high | undefined
9379 11:56:58.824439 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9380 11:56:58.827989 in-header: 03 f9 00 00 02 00 00 00
9381 11:56:58.828061 in-data: 02 00
9382 11:56:58.830725 ADC[4]: Raw value=904357 ID=7
9383 11:56:58.834932 ADC[3]: Raw value=213441 ID=1
9384 11:56:58.838000 RAM Code: 0x71
9385 11:56:58.838071 ADC[6]: Raw value=75701 ID=0
9386 11:56:58.840996 ADC[5]: Raw value=213072 ID=1
9387 11:56:58.844065 SKU Code: 0x1
9388 11:56:58.847336 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum b2c3
9389 11:56:58.851074 coreboot table: 964 bytes.
9390 11:56:58.854039 IMD ROOT 0. 0xfffff000 0x00001000
9391 11:56:58.857827 IMD SMALL 1. 0xffffe000 0x00001000
9392 11:56:58.861109 RO MCACHE 2. 0xffffc000 0x00001104
9393 11:56:58.863976 CONSOLE 3. 0xfff7c000 0x00080000
9394 11:56:58.867666 FMAP 4. 0xfff7b000 0x00000452
9395 11:56:58.870728 TIME STAMP 5. 0xfff7a000 0x00000910
9396 11:56:58.874270 VBOOT WORK 6. 0xfff66000 0x00014000
9397 11:56:58.877669 RAMOOPS 7. 0xffe66000 0x00100000
9398 11:56:58.881024 COREBOOT 8. 0xffe64000 0x00002000
9399 11:56:58.881118 IMD small region:
9400 11:56:58.884153 IMD ROOT 0. 0xffffec00 0x00000400
9401 11:56:58.887319 VPD 1. 0xffffeb80 0x0000006c
9402 11:56:58.890905 MMC STATUS 2. 0xffffeb60 0x00000004
9403 11:56:58.897810 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9404 11:56:58.900899 Probing TPM: done!
9405 11:56:58.904068 Connected to device vid:did:rid of 1ae0:0028:00
9406 11:56:58.914102 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9407 11:56:58.917496 Initialized TPM device CR50 revision 0
9408 11:56:58.921825 Checking cr50 for pending updates
9409 11:56:58.924592 Reading cr50 TPM mode
9410 11:56:58.933795 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9411 11:56:58.939920 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9412 11:56:58.979898 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9413 11:56:58.983643 Checking segment from ROM address 0x40100000
9414 11:56:58.986466 Checking segment from ROM address 0x4010001c
9415 11:56:58.993531 Loading segment from ROM address 0x40100000
9416 11:56:58.993662 code (compression=0)
9417 11:56:59.003406 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9418 11:56:59.009885 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9419 11:56:59.009966 it's not compressed!
9420 11:56:59.016460 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9421 11:56:59.020189 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9422 11:56:59.040646 Loading segment from ROM address 0x4010001c
9423 11:56:59.040743 Entry Point 0x80000000
9424 11:56:59.043897 Loaded segments
9425 11:56:59.047234 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9426 11:56:59.053765 Jumping to boot code at 0x80000000(0xffe64000)
9427 11:56:59.060543 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9428 11:56:59.067414 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9429 11:56:59.074837 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9430 11:56:59.078132 Checking segment from ROM address 0x40100000
9431 11:56:59.081850 Checking segment from ROM address 0x4010001c
9432 11:56:59.088093 Loading segment from ROM address 0x40100000
9433 11:56:59.088177 code (compression=1)
9434 11:56:59.094722 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9435 11:56:59.105085 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9436 11:56:59.105168 using LZMA
9437 11:56:59.113051 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9438 11:56:59.119962 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9439 11:56:59.123042 Loading segment from ROM address 0x4010001c
9440 11:56:59.123124 Entry Point 0x54601000
9441 11:56:59.126815 Loaded segments
9442 11:56:59.129786 NOTICE: MT8192 bl31_setup
9443 11:56:59.137167 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9444 11:56:59.139929 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9445 11:56:59.143377 WARNING: region 0:
9446 11:56:59.147169 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9447 11:56:59.147253 WARNING: region 1:
9448 11:56:59.153454 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9449 11:56:59.157029 WARNING: region 2:
9450 11:56:59.160216 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9451 11:56:59.163658 WARNING: region 3:
9452 11:56:59.167093 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9453 11:56:59.170528 WARNING: region 4:
9454 11:56:59.174148 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9455 11:56:59.177255 WARNING: region 5:
9456 11:56:59.180251 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9457 11:56:59.183692 WARNING: region 6:
9458 11:56:59.187443 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9459 11:56:59.187526 WARNING: region 7:
9460 11:56:59.193819 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 11:56:59.200670 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9462 11:56:59.203817 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9463 11:56:59.207324 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9464 11:56:59.213822 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9465 11:56:59.217071 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9466 11:56:59.220452 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9467 11:56:59.227308 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9468 11:56:59.230429 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9469 11:56:59.234306 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9470 11:56:59.240630 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9471 11:56:59.244139 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9472 11:56:59.247285 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9473 11:56:59.253799 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9474 11:56:59.257884 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9475 11:56:59.264265 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9476 11:56:59.267113 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9477 11:56:59.270724 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9478 11:56:59.277348 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9479 11:56:59.280840 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9480 11:56:59.283770 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9481 11:56:59.290692 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9482 11:56:59.294701 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9483 11:56:59.300601 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9484 11:56:59.304374 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9485 11:56:59.307408 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9486 11:56:59.314377 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9487 11:56:59.317409 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9488 11:56:59.324019 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9489 11:56:59.327558 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9490 11:56:59.330867 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9491 11:56:59.337517 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9492 11:56:59.340519 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9493 11:56:59.343894 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9494 11:56:59.350537 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9495 11:56:59.354160 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9496 11:56:59.357545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9497 11:56:59.360791 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9498 11:56:59.367821 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9499 11:56:59.371050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9500 11:56:59.373913 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9501 11:56:59.377550 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9502 11:56:59.380748 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9503 11:56:59.387678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9504 11:56:59.390713 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9505 11:56:59.394413 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9506 11:56:59.400672 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9507 11:56:59.404029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9508 11:56:59.407632 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9509 11:56:59.411164 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9510 11:56:59.417520 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9511 11:56:59.421231 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9512 11:56:59.427388 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9513 11:56:59.431145 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9514 11:56:59.437462 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9515 11:56:59.440946 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9516 11:56:59.444544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9517 11:56:59.451411 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9518 11:56:59.454500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9519 11:56:59.461152 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9520 11:56:59.464129 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9521 11:56:59.471310 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9522 11:56:59.474677 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9523 11:56:59.477755 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9524 11:56:59.484459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9525 11:56:59.487575 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9526 11:56:59.494544 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9527 11:56:59.497932 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9528 11:56:59.504105 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9529 11:56:59.507765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9530 11:56:59.510893 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9531 11:56:59.517586 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9532 11:56:59.521165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9533 11:56:59.527481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9534 11:56:59.531083 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9535 11:56:59.537530 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9536 11:56:59.541239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9537 11:56:59.547927 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9538 11:56:59.551327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9539 11:56:59.554091 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9540 11:56:59.560967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9541 11:56:59.564642 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9542 11:56:59.570757 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9543 11:56:59.574392 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9544 11:56:59.577862 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9545 11:56:59.584696 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9546 11:56:59.587935 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9547 11:56:59.594683 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9548 11:56:59.598072 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9549 11:56:59.604640 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9550 11:56:59.608458 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9551 11:56:59.611395 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9552 11:56:59.618263 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9553 11:56:59.621486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9554 11:56:59.627795 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9555 11:56:59.631386 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9556 11:56:59.637873 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9557 11:56:59.641521 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9558 11:56:59.644732 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9559 11:56:59.648234 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9560 11:56:59.655178 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9561 11:56:59.658040 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9562 11:56:59.661463 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9563 11:56:59.668608 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9564 11:56:59.671896 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9565 11:56:59.674851 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9566 11:56:59.681409 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9567 11:56:59.684766 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9568 11:56:59.691274 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9569 11:56:59.694899 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9570 11:56:59.698529 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9571 11:56:59.705001 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9572 11:56:59.708399 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9573 11:56:59.715248 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9574 11:56:59.718733 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9575 11:56:59.721836 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9576 11:56:59.728132 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9577 11:56:59.731733 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9578 11:56:59.735579 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9579 11:56:59.741994 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9580 11:56:59.744855 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9581 11:56:59.748137 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9582 11:56:59.751668 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9583 11:56:59.754771 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9584 11:56:59.761870 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9585 11:56:59.764933 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9586 11:56:59.771737 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9587 11:56:59.775081 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9588 11:56:59.778177 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9589 11:56:59.785205 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9590 11:56:59.788761 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9591 11:56:59.792097 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9592 11:56:59.798700 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9593 11:56:59.801819 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9594 11:56:59.808462 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9595 11:56:59.812030 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9596 11:56:59.815092 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9597 11:56:59.822132 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9598 11:56:59.825226 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9599 11:56:59.828441 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9600 11:56:59.835617 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9601 11:56:59.838911 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9602 11:56:59.845085 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9603 11:56:59.848884 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9604 11:56:59.851756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9605 11:56:59.858621 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9606 11:56:59.861839 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9607 11:56:59.868420 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9608 11:56:59.872130 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9609 11:56:59.875310 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9610 11:56:59.881794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9611 11:56:59.885463 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9612 11:56:59.888705 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9613 11:56:59.895484 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9614 11:56:59.898605 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9615 11:56:59.905320 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9616 11:56:59.909120 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9617 11:56:59.912537 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9618 11:56:59.918810 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9619 11:56:59.922491 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9620 11:56:59.928588 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9621 11:56:59.931778 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9622 11:56:59.935519 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9623 11:56:59.941722 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9624 11:56:59.945272 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9625 11:56:59.951922 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9626 11:56:59.955654 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9627 11:56:59.958578 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9628 11:56:59.965301 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9629 11:56:59.968954 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9630 11:56:59.972104 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9631 11:56:59.978428 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9632 11:56:59.982197 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9633 11:56:59.988796 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9634 11:56:59.991727 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9635 11:56:59.995652 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9636 11:57:00.001747 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9637 11:57:00.005431 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9638 11:57:00.011744 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9639 11:57:00.015132 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9640 11:57:00.018482 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9641 11:57:00.025458 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9642 11:57:00.028813 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9643 11:57:00.031940 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9644 11:57:00.038570 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9645 11:57:00.041827 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9646 11:57:00.048889 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9647 11:57:00.051903 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9648 11:57:00.054959 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9649 11:57:00.061776 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9650 11:57:00.064943 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9651 11:57:00.071612 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9652 11:57:00.074955 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9653 11:57:00.081797 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9654 11:57:00.084746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9655 11:57:00.088279 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9656 11:57:00.094915 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9657 11:57:00.098161 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9658 11:57:00.104648 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9659 11:57:00.108436 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9660 11:57:00.111506 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9661 11:57:00.118150 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9662 11:57:00.121137 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9663 11:57:00.127804 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9664 11:57:00.131821 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9665 11:57:00.138022 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9666 11:57:00.141173 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9667 11:57:00.144492 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9668 11:57:00.151542 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9669 11:57:00.154700 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9670 11:57:00.161601 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9671 11:57:00.164712 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9672 11:57:00.168221 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9673 11:57:00.175186 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9674 11:57:00.178060 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9675 11:57:00.185226 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9676 11:57:00.188361 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9677 11:57:00.194499 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9678 11:57:00.197958 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9679 11:57:00.201422 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9680 11:57:00.208307 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9681 11:57:00.212060 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9682 11:57:00.218391 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9683 11:57:00.221391 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9684 11:57:00.225019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9685 11:57:00.231301 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9686 11:57:00.234898 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9687 11:57:00.241246 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9688 11:57:00.245207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9689 11:57:00.248136 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9690 11:57:00.254916 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9691 11:57:00.257649 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9692 11:57:00.261480 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9693 11:57:00.264633 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9694 11:57:00.271836 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9695 11:57:00.274542 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9696 11:57:00.278541 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9697 11:57:00.284836 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9698 11:57:00.288035 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9699 11:57:00.291854 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9700 11:57:00.298085 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9701 11:57:00.301332 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9702 11:57:00.307784 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9703 11:57:00.311200 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9704 11:57:00.314647 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9705 11:57:00.320869 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9706 11:57:00.325067 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9707 11:57:00.327640 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9708 11:57:00.334782 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9709 11:57:00.337914 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9710 11:57:00.341377 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9711 11:57:00.348008 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9712 11:57:00.351290 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9713 11:57:00.357422 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9714 11:57:00.360849 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9715 11:57:00.364356 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9716 11:57:00.371163 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9717 11:57:00.374905 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9718 11:57:00.377975 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9719 11:57:00.384176 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9720 11:57:00.387702 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9721 11:57:00.394283 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9722 11:57:00.397977 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9723 11:57:00.400940 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9724 11:57:00.407921 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9725 11:57:00.410463 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9726 11:57:00.414376 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9727 11:57:00.421192 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9728 11:57:00.423917 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9729 11:57:00.428096 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9730 11:57:00.433914 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9731 11:57:00.437616 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9732 11:57:00.440851 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9733 11:57:00.443617 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9734 11:57:00.447256 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9735 11:57:00.454096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9736 11:57:00.457308 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9737 11:57:00.460702 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9738 11:57:00.464097 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9739 11:57:00.470399 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9740 11:57:00.473899 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9741 11:57:00.477488 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9742 11:57:00.483789 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9743 11:57:00.487622 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9744 11:57:00.490636 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9745 11:57:00.497501 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9746 11:57:00.500466 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9747 11:57:00.507461 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9748 11:57:00.510547 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9749 11:57:00.517287 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9750 11:57:00.520516 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9751 11:57:00.523979 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9752 11:57:00.531034 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9753 11:57:00.534412 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9754 11:57:00.537255 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9755 11:57:00.543894 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9756 11:57:00.547256 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9757 11:57:00.553469 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9758 11:57:00.557000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9759 11:57:00.560388 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9760 11:57:00.566937 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9761 11:57:00.570270 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9762 11:57:00.577228 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9763 11:57:00.580390 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9764 11:57:00.587072 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9765 11:57:00.590012 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9766 11:57:00.593818 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9767 11:57:00.600519 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9768 11:57:00.603696 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9769 11:57:00.610025 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9770 11:57:00.613728 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9771 11:57:00.620149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9772 11:57:00.622920 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9773 11:57:00.626663 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9774 11:57:00.633065 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9775 11:57:00.636690 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9776 11:57:00.643719 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9777 11:57:00.646285 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9778 11:57:00.649960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9779 11:57:00.656073 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9780 11:57:00.660030 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9781 11:57:00.666116 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9782 11:57:00.669434 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9783 11:57:00.672785 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9784 11:57:00.679886 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9785 11:57:00.683200 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9786 11:57:00.690380 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9787 11:57:00.693352 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9788 11:57:00.696437 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9789 11:57:00.703544 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9790 11:57:00.706559 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9791 11:57:00.713210 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9792 11:57:00.716169 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9793 11:57:00.720235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9794 11:57:00.726179 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9795 11:57:00.730034 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9796 11:57:00.736381 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9797 11:57:00.740072 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9798 11:57:00.742772 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9799 11:57:00.749064 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9800 11:57:00.753123 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9801 11:57:00.759466 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9802 11:57:00.762490 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9803 11:57:00.769241 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9804 11:57:00.773133 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9805 11:57:00.776188 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9806 11:57:00.782551 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9807 11:57:00.785988 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9808 11:57:00.792308 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9809 11:57:00.796090 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9810 11:57:00.799237 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9811 11:57:00.805976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9812 11:57:00.809463 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9813 11:57:00.816060 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9814 11:57:00.818946 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9815 11:57:00.822628 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9816 11:57:00.829039 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9817 11:57:00.832763 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9818 11:57:00.839636 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9819 11:57:00.842551 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9820 11:57:00.849095 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9821 11:57:00.852422 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9822 11:57:00.855743 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9823 11:57:00.862036 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9824 11:57:00.865641 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9825 11:57:00.872329 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9826 11:57:00.875750 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9827 11:57:00.882252 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9828 11:57:00.885756 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9829 11:57:00.892145 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9830 11:57:00.895730 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9831 11:57:00.899185 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9832 11:57:00.905692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9833 11:57:00.908591 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9834 11:57:00.915692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9835 11:57:00.919075 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9836 11:57:00.926016 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9837 11:57:00.929064 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9838 11:57:00.932114 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9839 11:57:00.938888 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9840 11:57:00.942026 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9841 11:57:00.948506 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9842 11:57:00.951773 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9843 11:57:00.958804 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9844 11:57:00.962027 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9845 11:57:00.968599 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9846 11:57:00.972040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9847 11:57:00.975183 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9848 11:57:00.982319 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9849 11:57:00.985207 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9850 11:57:00.991571 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9851 11:57:00.995408 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9852 11:57:01.001903 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9853 11:57:01.005315 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9854 11:57:01.008415 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9855 11:57:01.015115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9856 11:57:01.018205 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9857 11:57:01.025138 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9858 11:57:01.028870 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9859 11:57:01.035003 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9860 11:57:01.038610 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9861 11:57:01.041597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9862 11:57:01.048478 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9863 11:57:01.051544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9864 11:57:01.058041 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9865 11:57:01.061209 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9866 11:57:01.065108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9867 11:57:01.071474 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9868 11:57:01.074387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9869 11:57:01.081524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9870 11:57:01.085096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9871 11:57:01.091220 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9872 11:57:01.094488 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9873 11:57:01.101372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9874 11:57:01.104783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9875 11:57:01.111407 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9876 11:57:01.114511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9877 11:57:01.121050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9878 11:57:01.124604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9879 11:57:01.131340 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9880 11:57:01.134430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9881 11:57:01.140837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9882 11:57:01.144415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9883 11:57:01.151263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9884 11:57:01.154448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9885 11:57:01.161050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9886 11:57:01.164742 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9887 11:57:01.170775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9888 11:57:01.174592 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9889 11:57:01.181089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9890 11:57:01.184661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9891 11:57:01.191186 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9892 11:57:01.194232 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9893 11:57:01.201208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9894 11:57:01.204187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9895 11:57:01.207440 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9896 11:57:01.211054 INFO: [APUAPC] vio 0
9897 11:57:01.217851 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9898 11:57:01.221071 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9899 11:57:01.224148 INFO: [APUAPC] D0_APC_0: 0x400510
9900 11:57:01.227591 INFO: [APUAPC] D0_APC_1: 0x0
9901 11:57:01.231177 INFO: [APUAPC] D0_APC_2: 0x1540
9902 11:57:01.233683 INFO: [APUAPC] D0_APC_3: 0x0
9903 11:57:01.237558 INFO: [APUAPC] D1_APC_0: 0xffffffff
9904 11:57:01.240625 INFO: [APUAPC] D1_APC_1: 0xffffffff
9905 11:57:01.243738 INFO: [APUAPC] D1_APC_2: 0x3fffff
9906 11:57:01.246843 INFO: [APUAPC] D1_APC_3: 0x0
9907 11:57:01.250303 INFO: [APUAPC] D2_APC_0: 0xffffffff
9908 11:57:01.253520 INFO: [APUAPC] D2_APC_1: 0xffffffff
9909 11:57:01.257396 INFO: [APUAPC] D2_APC_2: 0x3fffff
9910 11:57:01.260130 INFO: [APUAPC] D2_APC_3: 0x0
9911 11:57:01.264013 INFO: [APUAPC] D3_APC_0: 0xffffffff
9912 11:57:01.267160 INFO: [APUAPC] D3_APC_1: 0xffffffff
9913 11:57:01.270202 INFO: [APUAPC] D3_APC_2: 0x3fffff
9914 11:57:01.274012 INFO: [APUAPC] D3_APC_3: 0x0
9915 11:57:01.277069 INFO: [APUAPC] D4_APC_0: 0xffffffff
9916 11:57:01.280013 INFO: [APUAPC] D4_APC_1: 0xffffffff
9917 11:57:01.283806 INFO: [APUAPC] D4_APC_2: 0x3fffff
9918 11:57:01.284358 INFO: [APUAPC] D4_APC_3: 0x0
9919 11:57:01.287089 INFO: [APUAPC] D5_APC_0: 0xffffffff
9920 11:57:01.293777 INFO: [APUAPC] D5_APC_1: 0xffffffff
9921 11:57:01.294330 INFO: [APUAPC] D5_APC_2: 0x3fffff
9922 11:57:01.297105 INFO: [APUAPC] D5_APC_3: 0x0
9923 11:57:01.300218 INFO: [APUAPC] D6_APC_0: 0xffffffff
9924 11:57:01.304136 INFO: [APUAPC] D6_APC_1: 0xffffffff
9925 11:57:01.306788 INFO: [APUAPC] D6_APC_2: 0x3fffff
9926 11:57:01.310015 INFO: [APUAPC] D6_APC_3: 0x0
9927 11:57:01.313988 INFO: [APUAPC] D7_APC_0: 0xffffffff
9928 11:57:01.317447 INFO: [APUAPC] D7_APC_1: 0xffffffff
9929 11:57:01.320181 INFO: [APUAPC] D7_APC_2: 0x3fffff
9930 11:57:01.323690 INFO: [APUAPC] D7_APC_3: 0x0
9931 11:57:01.326848 INFO: [APUAPC] D8_APC_0: 0xffffffff
9932 11:57:01.330185 INFO: [APUAPC] D8_APC_1: 0xffffffff
9933 11:57:01.333627 INFO: [APUAPC] D8_APC_2: 0x3fffff
9934 11:57:01.336749 INFO: [APUAPC] D8_APC_3: 0x0
9935 11:57:01.339547 INFO: [APUAPC] D9_APC_0: 0xffffffff
9936 11:57:01.343519 INFO: [APUAPC] D9_APC_1: 0xffffffff
9937 11:57:01.346913 INFO: [APUAPC] D9_APC_2: 0x3fffff
9938 11:57:01.349973 INFO: [APUAPC] D9_APC_3: 0x0
9939 11:57:01.352948 INFO: [APUAPC] D10_APC_0: 0xffffffff
9940 11:57:01.357020 INFO: [APUAPC] D10_APC_1: 0xffffffff
9941 11:57:01.360083 INFO: [APUAPC] D10_APC_2: 0x3fffff
9942 11:57:01.363265 INFO: [APUAPC] D10_APC_3: 0x0
9943 11:57:01.366228 INFO: [APUAPC] D11_APC_0: 0xffffffff
9944 11:57:01.369517 INFO: [APUAPC] D11_APC_1: 0xffffffff
9945 11:57:01.373507 INFO: [APUAPC] D11_APC_2: 0x3fffff
9946 11:57:01.376598 INFO: [APUAPC] D11_APC_3: 0x0
9947 11:57:01.380068 INFO: [APUAPC] D12_APC_0: 0xffffffff
9948 11:57:01.382952 INFO: [APUAPC] D12_APC_1: 0xffffffff
9949 11:57:01.386604 INFO: [APUAPC] D12_APC_2: 0x3fffff
9950 11:57:01.389682 INFO: [APUAPC] D12_APC_3: 0x0
9951 11:57:01.393137 INFO: [APUAPC] D13_APC_0: 0xffffffff
9952 11:57:01.396951 INFO: [APUAPC] D13_APC_1: 0xffffffff
9953 11:57:01.399419 INFO: [APUAPC] D13_APC_2: 0x3fffff
9954 11:57:01.403245 INFO: [APUAPC] D13_APC_3: 0x0
9955 11:57:01.406442 INFO: [APUAPC] D14_APC_0: 0xffffffff
9956 11:57:01.409699 INFO: [APUAPC] D14_APC_1: 0xffffffff
9957 11:57:01.412957 INFO: [APUAPC] D14_APC_2: 0x3fffff
9958 11:57:01.416694 INFO: [APUAPC] D14_APC_3: 0x0
9959 11:57:01.419577 INFO: [APUAPC] D15_APC_0: 0xffffffff
9960 11:57:01.423108 INFO: [APUAPC] D15_APC_1: 0xffffffff
9961 11:57:01.426534 INFO: [APUAPC] D15_APC_2: 0x3fffff
9962 11:57:01.429741 INFO: [APUAPC] D15_APC_3: 0x0
9963 11:57:01.432777 INFO: [APUAPC] APC_CON: 0x4
9964 11:57:01.435953 INFO: [NOCDAPC] D0_APC_0: 0x0
9965 11:57:01.439745 INFO: [NOCDAPC] D0_APC_1: 0x0
9966 11:57:01.443141 INFO: [NOCDAPC] D1_APC_0: 0x0
9967 11:57:01.446430 INFO: [NOCDAPC] D1_APC_1: 0xfff
9968 11:57:01.447007 INFO: [NOCDAPC] D2_APC_0: 0x0
9969 11:57:01.449068 INFO: [NOCDAPC] D2_APC_1: 0xfff
9970 11:57:01.452846 INFO: [NOCDAPC] D3_APC_0: 0x0
9971 11:57:01.455922 INFO: [NOCDAPC] D3_APC_1: 0xfff
9972 11:57:01.459259 INFO: [NOCDAPC] D4_APC_0: 0x0
9973 11:57:01.462527 INFO: [NOCDAPC] D4_APC_1: 0xfff
9974 11:57:01.466068 INFO: [NOCDAPC] D5_APC_0: 0x0
9975 11:57:01.469702 INFO: [NOCDAPC] D5_APC_1: 0xfff
9976 11:57:01.472865 INFO: [NOCDAPC] D6_APC_0: 0x0
9977 11:57:01.475991 INFO: [NOCDAPC] D6_APC_1: 0xfff
9978 11:57:01.479659 INFO: [NOCDAPC] D7_APC_0: 0x0
9979 11:57:01.480212 INFO: [NOCDAPC] D7_APC_1: 0xfff
9980 11:57:01.483121 INFO: [NOCDAPC] D8_APC_0: 0x0
9981 11:57:01.486199 INFO: [NOCDAPC] D8_APC_1: 0xfff
9982 11:57:01.489665 INFO: [NOCDAPC] D9_APC_0: 0x0
9983 11:57:01.492323 INFO: [NOCDAPC] D9_APC_1: 0xfff
9984 11:57:01.496128 INFO: [NOCDAPC] D10_APC_0: 0x0
9985 11:57:01.499433 INFO: [NOCDAPC] D10_APC_1: 0xfff
9986 11:57:01.502629 INFO: [NOCDAPC] D11_APC_0: 0x0
9987 11:57:01.506169 INFO: [NOCDAPC] D11_APC_1: 0xfff
9988 11:57:01.509364 INFO: [NOCDAPC] D12_APC_0: 0x0
9989 11:57:01.513276 INFO: [NOCDAPC] D12_APC_1: 0xfff
9990 11:57:01.516410 INFO: [NOCDAPC] D13_APC_0: 0x0
9991 11:57:01.519494 INFO: [NOCDAPC] D13_APC_1: 0xfff
9992 11:57:01.520046 INFO: [NOCDAPC] D14_APC_0: 0x0
9993 11:57:01.522903 INFO: [NOCDAPC] D14_APC_1: 0xfff
9994 11:57:01.526208 INFO: [NOCDAPC] D15_APC_0: 0x0
9995 11:57:01.529345 INFO: [NOCDAPC] D15_APC_1: 0xfff
9996 11:57:01.533200 INFO: [NOCDAPC] APC_CON: 0x4
9997 11:57:01.535947 INFO: [APUAPC] set_apusys_apc done
9998 11:57:01.539333 INFO: [DEVAPC] devapc_init done
9999 11:57:01.543252 INFO: GICv3 without legacy support detected.
10000 11:57:01.549446 INFO: ARM GICv3 driver initialized in EL3
10001 11:57:01.552834 INFO: Maximum SPI INTID supported: 639
10002 11:57:01.556090 INFO: BL31: Initializing runtime services
10003 11:57:01.562233 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10004 11:57:01.562694 INFO: SPM: enable CPC mode
10005 11:57:01.568873 INFO: mcdi ready for mcusys-off-idle and system suspend
10006 11:57:01.572424 INFO: BL31: Preparing for EL3 exit to normal world
10007 11:57:01.579096 INFO: Entry point address = 0x80000000
10008 11:57:01.579651 INFO: SPSR = 0x8
10009 11:57:01.585516
10010 11:57:01.586116
10011 11:57:01.586480
10012 11:57:01.588664 Starting depthcharge on Spherion...
10013 11:57:01.589122
10014 11:57:01.589477 Wipe memory regions:
10015 11:57:01.589877
10016 11:57:01.592737 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10017 11:57:01.593341 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10018 11:57:01.593837 Setting prompt string to ['asurada:']
10019 11:57:01.594265 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10020 11:57:01.594983 [0x00000040000000, 0x00000054600000)
10021 11:57:01.713980
10022 11:57:01.714524 [0x00000054660000, 0x00000080000000)
10023 11:57:01.974223
10024 11:57:01.974774 [0x000000821a7280, 0x000000ffe64000)
10025 11:57:02.717809
10026 11:57:02.718438 [0x00000100000000, 0x00000240000000)
10027 11:57:04.605009
10028 11:57:04.607766 Initializing XHCI USB controller at 0x11200000.
10029 11:57:05.646148
10030 11:57:05.649650 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10031 11:57:05.650104
10032 11:57:05.650457
10033 11:57:05.650931
10034 11:57:05.651912 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10036 11:57:05.753325 asurada: tftpboot 192.168.201.1 12066541/tftp-deploy-wp7f11ac/kernel/image.itb 12066541/tftp-deploy-wp7f11ac/kernel/cmdline
10037 11:57:05.753996 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10038 11:57:05.754451 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10039 11:57:05.758963 tftpboot 192.168.201.1 12066541/tftp-deploy-wp7f11ac/kernel/image.itbtp-deploy-wp7f11ac/kernel/cmdline
10040 11:57:05.759428
10041 11:57:05.759785 Waiting for link
10042 11:57:05.919932
10043 11:57:05.920492 R8152: Initializing
10044 11:57:05.920847
10045 11:57:05.923006 Version 9 (ocp_data = 6010)
10046 11:57:05.923560
10047 11:57:05.925970 R8152: Done initializing
10048 11:57:05.926426
10049 11:57:05.926784 Adding net device
10050 11:57:07.794999
10051 11:57:07.795589 done.
10052 11:57:07.796189
10053 11:57:07.796864 MAC: 00:e0:4c:78:7a:aa
10054 11:57:07.797513
10055 11:57:07.798461 Sending DHCP discover... done.
10056 11:57:07.798847
10057 11:57:07.801658 Waiting for reply... done.
10058 11:57:07.802207
10059 11:57:07.804625 Sending DHCP request... done.
10060 11:57:07.805080
10061 11:57:07.808467 Waiting for reply... done.
10062 11:57:07.809012
10063 11:57:07.809406 My ip is 192.168.201.12
10064 11:57:07.810005
10065 11:57:07.812106 The DHCP server ip is 192.168.201.1
10066 11:57:07.812678
10067 11:57:07.818218 TFTP server IP predefined by user: 192.168.201.1
10068 11:57:07.818831
10069 11:57:07.825366 Bootfile predefined by user: 12066541/tftp-deploy-wp7f11ac/kernel/image.itb
10070 11:57:07.826066
10071 11:57:07.826606 Sending tftp read request... done.
10072 11:57:07.828178
10073 11:57:07.835001 Waiting for the transfer...
10074 11:57:07.835721
10075 11:57:08.249377 00000000 ################################################################
10076 11:57:08.249923
10077 11:57:08.558306 00080000 ################################################################
10078 11:57:08.558439
10079 11:57:08.833689 00100000 ################################################################
10080 11:57:08.833819
10081 11:57:09.095277 00180000 ################################################################
10082 11:57:09.095448
10083 11:57:09.364166 00200000 ################################################################
10084 11:57:09.364298
10085 11:57:09.639836 00280000 ################################################################
10086 11:57:09.639965
10087 11:57:09.931130 00300000 ################################################################
10088 11:57:09.931258
10089 11:57:10.208507 00380000 ################################################################
10090 11:57:10.208641
10091 11:57:10.480813 00400000 ################################################################
10092 11:57:10.480945
10093 11:57:10.780439 00480000 ################################################################
10094 11:57:10.780572
10095 11:57:11.160207 00500000 ################################################################
10096 11:57:11.160757
10097 11:57:11.571528 00580000 ################################################################
10098 11:57:11.572017
10099 11:57:11.961880 00600000 ################################################################
10100 11:57:11.962366
10101 11:57:12.362109 00680000 ################################################################
10102 11:57:12.362625
10103 11:57:12.785849 00700000 ################################################################
10104 11:57:12.786411
10105 11:57:13.185281 00780000 ################################################################
10106 11:57:13.185829
10107 11:57:13.590758 00800000 ################################################################
10108 11:57:13.591246
10109 11:57:13.972069 00880000 ################################################################
10110 11:57:13.972672
10111 11:57:14.336918 00900000 ################################################################
10112 11:57:14.337066
10113 11:57:14.608065 00980000 ################################################################
10114 11:57:14.608201
10115 11:57:14.898496 00a00000 ################################################################
10116 11:57:14.898632
10117 11:57:15.190191 00a80000 ################################################################
10118 11:57:15.190344
10119 11:57:15.488133 00b00000 ################################################################
10120 11:57:15.488278
10121 11:57:15.787558 00b80000 ################################################################
10122 11:57:15.787697
10123 11:57:16.087574 00c00000 ################################################################
10124 11:57:16.087714
10125 11:57:16.383687 00c80000 ################################################################
10126 11:57:16.383826
10127 11:57:16.675887 00d00000 ################################################################
10128 11:57:16.676050
10129 11:57:16.966331 00d80000 ################################################################
10130 11:57:16.966466
10131 11:57:17.261582 00e00000 ################################################################
10132 11:57:17.261756
10133 11:57:17.663209 00e80000 ################################################################
10134 11:57:17.663838
10135 11:57:18.056460 00f00000 ################################################################
10136 11:57:18.057019
10137 11:57:18.433022 00f80000 ################################################################
10138 11:57:18.433750
10139 11:57:18.835863 01000000 ################################################################
10140 11:57:18.836370
10141 11:57:19.238948 01080000 ################################################################
10142 11:57:19.239456
10143 11:57:19.549524 01100000 ################################################################
10144 11:57:19.549689
10145 11:57:19.816493 01180000 ################################################################
10146 11:57:19.816620
10147 11:57:20.075351 01200000 ################################################################
10148 11:57:20.075486
10149 11:57:20.366086 01280000 ################################################################
10150 11:57:20.366225
10151 11:57:20.661269 01300000 ################################################################
10152 11:57:20.661406
10153 11:57:20.954856 01380000 ################################################################
10154 11:57:20.954995
10155 11:57:21.233377 01400000 ################################################################
10156 11:57:21.233521
10157 11:57:21.532551 01480000 ################################################################
10158 11:57:21.532688
10159 11:57:21.830895 01500000 ################################################################
10160 11:57:21.831034
10161 11:57:22.128153 01580000 ################################################################
10162 11:57:22.128290
10163 11:57:22.406280 01600000 ################################################################
10164 11:57:22.406418
10165 11:57:22.694642 01680000 ################################################################
10166 11:57:22.694782
10167 11:57:23.081388 01700000 ################################################################
10168 11:57:23.081964
10169 11:57:23.479596 01780000 ################################################################
10170 11:57:23.480106
10171 11:57:23.868328 01800000 ################################################################
10172 11:57:23.868836
10173 11:57:24.270904 01880000 ################################################################
10174 11:57:24.271422
10175 11:57:24.661652 01900000 ################################################################
10176 11:57:24.662162
10177 11:57:25.057148 01980000 ################################################################
10178 11:57:25.057700
10179 11:57:25.447227 01a00000 ################################################################
10180 11:57:25.447747
10181 11:57:25.827506 01a80000 ################################################################
10182 11:57:25.828018
10183 11:57:26.245955 01b00000 ################################################################
10184 11:57:26.246520
10185 11:57:26.671142 01b80000 ################################################################
10186 11:57:26.671799
10187 11:57:27.082727 01c00000 ################################################################
10188 11:57:27.083246
10189 11:57:27.480871 01c80000 ################################################################
10190 11:57:27.481409
10191 11:57:27.896296 01d00000 ################################################################
10192 11:57:27.896925
10193 11:57:28.282758 01d80000 ################################################################
10194 11:57:28.283263
10195 11:57:28.678074 01e00000 ################################################################
10196 11:57:28.678582
10197 11:57:29.076086 01e80000 ################################################################
10198 11:57:29.076596
10199 11:57:29.382077 01f00000 ################################################################
10200 11:57:29.382249
10201 11:57:29.671183 01f80000 ################################################################
10202 11:57:29.671322
10203 11:57:29.961405 02000000 ################################################################
10204 11:57:29.961569
10205 11:57:30.258861 02080000 ################################################################
10206 11:57:30.259000
10207 11:57:30.559495 02100000 ################################################################
10208 11:57:30.559640
10209 11:57:30.845878 02180000 ################################################################
10210 11:57:30.846026
10211 11:57:31.143905 02200000 ################################################################
10212 11:57:31.144079
10213 11:57:31.421212 02280000 ################################################################
10214 11:57:31.421339
10215 11:57:31.688947 02300000 ################################################################
10216 11:57:31.689108
10217 11:57:31.961126 02380000 ################################################################
10218 11:57:31.961261
10219 11:57:32.219147 02400000 ################################################################
10220 11:57:32.219289
10221 11:57:32.487057 02480000 ################################################################
10222 11:57:32.487186
10223 11:57:32.758567 02500000 ################################################################
10224 11:57:32.758727
10225 11:57:33.022642 02580000 ################################################################
10226 11:57:33.022804
10227 11:57:33.302444 02600000 ################################################################
10228 11:57:33.302577
10229 11:57:33.575285 02680000 ################################################################
10230 11:57:33.575413
10231 11:57:33.841087 02700000 ################################################################
10232 11:57:33.841247
10233 11:57:34.095138 02780000 ################################################################
10234 11:57:34.095269
10235 11:57:34.349264 02800000 ################################################################
10236 11:57:34.349455
10237 11:57:34.613396 02880000 ################################################################
10238 11:57:34.613558
10239 11:57:34.890624 02900000 ################################################################
10240 11:57:34.890759
10241 11:57:35.159393 02980000 ################################################################
10242 11:57:35.159556
10243 11:57:35.437675 02a00000 ################################################################
10244 11:57:35.437823
10245 11:57:35.711670 02a80000 ################################################################
10246 11:57:35.711800
10247 11:57:35.990703 02b00000 ################################################################
10248 11:57:35.990844
10249 11:57:36.268663 02b80000 ################################################################
10250 11:57:36.268808
10251 11:57:36.543406 02c00000 ################################################################
10252 11:57:36.543546
10253 11:57:36.802313 02c80000 ################################################################
10254 11:57:36.802442
10255 11:57:37.057843 02d00000 ################################################################
10256 11:57:37.058005
10257 11:57:37.318638 02d80000 ################################################################
10258 11:57:37.318774
10259 11:57:37.601275 02e00000 ################################################################
10260 11:57:37.601477
10261 11:57:37.879668 02e80000 ################################################################
10262 11:57:37.879804
10263 11:57:38.150539 02f00000 ################################################################
10264 11:57:38.150701
10265 11:57:38.426349 02f80000 ################################################################
10266 11:57:38.426489
10267 11:57:38.483676 03000000 ############### done.
10268 11:57:38.483775
10269 11:57:38.487075 The bootfile was 50451422 bytes long.
10270 11:57:38.487158
10271 11:57:38.490528 Sending tftp read request... done.
10272 11:57:38.490616
10273 11:57:38.493949 Waiting for the transfer...
10274 11:57:38.494032
10275 11:57:38.497535 00000000 # done.
10276 11:57:38.497660
10277 11:57:38.503637 Command line loaded dynamically from TFTP file: 12066541/tftp-deploy-wp7f11ac/kernel/cmdline
10278 11:57:38.503720
10279 11:57:38.517088 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10280 11:57:38.517176
10281 11:57:38.517241 Loading FIT.
10282 11:57:38.517301
10283 11:57:38.520241 Image ramdisk-1 has 39354927 bytes.
10284 11:57:38.520323
10285 11:57:38.523737 Image fdt-1 has 47278 bytes.
10286 11:57:38.523819
10287 11:57:38.527256 Image kernel-1 has 11047184 bytes.
10288 11:57:38.527338
10289 11:57:38.537094 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10290 11:57:38.537178
10291 11:57:38.553741 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10292 11:57:38.553829
10293 11:57:38.560197 Choosing best match conf-1 for compat google,spherion-rev2.
10294 11:57:38.560279
10295 11:57:38.567721 Connected to device vid:did:rid of 1ae0:0028:00
10296 11:57:38.576311
10297 11:57:38.579272 tpm_get_response: command 0x17b, return code 0x0
10298 11:57:38.579354
10299 11:57:38.583211 ec_init: CrosEC protocol v3 supported (256, 248)
10300 11:57:38.587268
10301 11:57:38.590665 tpm_cleanup: add release locality here.
10302 11:57:38.590747
10303 11:57:38.590811 Shutting down all USB controllers.
10304 11:57:38.593969
10305 11:57:38.594050 Removing current net device
10306 11:57:38.594114
10307 11:57:38.600510 Exiting depthcharge with code 4 at timestamp: 66296745
10308 11:57:38.600604
10309 11:57:38.604568 LZMA decompressing kernel-1 to 0x821a6718
10310 11:57:38.604648
10311 11:57:38.607285 LZMA decompressing kernel-1 to 0x40000000
10312 11:57:39.996884
10313 11:57:39.997378 jumping to kernel
10314 11:57:39.999443 end: 2.2.4 bootloader-commands (duration 00:00:38) [common]
10315 11:57:39.999946 start: 2.2.5 auto-login-action (timeout 00:03:47) [common]
10316 11:57:40.000330 Setting prompt string to ['Linux version [0-9]']
10317 11:57:40.000668 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10318 11:57:40.001008 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10319 11:57:40.078365
10320 11:57:40.082060 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10321 11:57:40.085296 start: 2.2.5.1 login-action (timeout 00:03:47) [common]
10322 11:57:40.085836 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10323 11:57:40.086236 Setting prompt string to []
10324 11:57:40.086662 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10325 11:57:40.087059 Using line separator: #'\n'#
10326 11:57:40.087389 No login prompt set.
10327 11:57:40.087718 Parsing kernel messages
10328 11:57:40.088024 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10329 11:57:40.088580 [login-action] Waiting for messages, (timeout 00:03:47)
10330 11:57:40.104675 [ 0.000000] Linux version 6.1.62-cip9 (KernelCI@build-j21388-arm64-gcc-10-defconfig-arm64-chromebook-kz5n5) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023
10331 11:57:40.108149 [ 0.000000] random: crng init done
10332 11:57:40.114583 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10333 11:57:40.114667 [ 0.000000] efi: UEFI not found.
10334 11:57:40.124676 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10335 11:57:40.131093 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10336 11:57:40.140986 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10337 11:57:40.150893 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10338 11:57:40.157555 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10339 11:57:40.164496 [ 0.000000] printk: bootconsole [mtk8250] enabled
10340 11:57:40.167822 [ 0.000000] NUMA: No NUMA configuration found
10341 11:57:40.177439 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10342 11:57:40.181566 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10343 11:57:40.184531 [ 0.000000] Zone ranges:
10344 11:57:40.191300 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10345 11:57:40.194386 [ 0.000000] DMA32 empty
10346 11:57:40.201026 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10347 11:57:40.204343 [ 0.000000] Movable zone start for each node
10348 11:57:40.207758 [ 0.000000] Early memory node ranges
10349 11:57:40.214738 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10350 11:57:40.221388 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10351 11:57:40.228020 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10352 11:57:40.231077 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10353 11:57:40.237951 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10354 11:57:40.244368 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10355 11:57:40.302698 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10356 11:57:40.309536 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10357 11:57:40.316039 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10358 11:57:40.319064 [ 0.000000] psci: probing for conduit method from DT.
10359 11:57:40.325874 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10360 11:57:40.328882 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10361 11:57:40.336144 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10362 11:57:40.338832 [ 0.000000] psci: SMC Calling Convention v1.2
10363 11:57:40.345875 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10364 11:57:40.349053 [ 0.000000] Detected VIPT I-cache on CPU0
10365 11:57:40.355906 [ 0.000000] CPU features: detected: GIC system register CPU interface
10366 11:57:40.362472 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10367 11:57:40.368957 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10368 11:57:40.375629 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10369 11:57:40.381971 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10370 11:57:40.389150 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10371 11:57:40.396182 [ 0.000000] alternatives: applying boot alternatives
10372 11:57:40.399158 [ 0.000000] Fallback order for Node 0: 0
10373 11:57:40.405540 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10374 11:57:40.408919 [ 0.000000] Policy zone: Normal
10375 11:57:40.425786 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10376 11:57:40.435177 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10377 11:57:40.447284 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10378 11:57:40.456980 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10379 11:57:40.463065 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10380 11:57:40.466272 <6>[ 0.000000] software IO TLB: area num 8.
10381 11:57:40.523851 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10382 11:57:40.672435 <6>[ 0.000000] Memory: 7931188K/8385536K available (17984K kernel code, 4116K rwdata, 17312K rodata, 8384K init, 615K bss, 421580K reserved, 32768K cma-reserved)
10383 11:57:40.678621 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10384 11:57:40.685126 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10385 11:57:40.688392 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10386 11:57:40.694664 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10387 11:57:40.701686 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10388 11:57:40.704695 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10389 11:57:40.714951 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10390 11:57:40.721851 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10391 11:57:40.727829 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10392 11:57:40.734597 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10393 11:57:40.737764 <6>[ 0.000000] GICv3: 608 SPIs implemented
10394 11:57:40.741314 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10395 11:57:40.748118 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10396 11:57:40.751302 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10397 11:57:40.757938 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10398 11:57:40.771321 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10399 11:57:40.781508 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10400 11:57:40.791681 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10401 11:57:40.798989 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10402 11:57:40.811751 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10403 11:57:40.818597 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10404 11:57:40.825490 <6>[ 0.009228] Console: colour dummy device 80x25
10405 11:57:40.835537 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10406 11:57:40.842418 <6>[ 0.024397] pid_max: default: 32768 minimum: 301
10407 11:57:40.845938 <6>[ 0.029269] LSM: Security Framework initializing
10408 11:57:40.852196 <6>[ 0.034236] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10409 11:57:40.862333 <6>[ 0.042050] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 11:57:40.868712 <6>[ 0.051453] cblist_init_generic: Setting adjustable number of callback queues.
10411 11:57:40.875273 <6>[ 0.058896] cblist_init_generic: Setting shift to 3 and lim to 1.
10412 11:57:40.884640 <6>[ 0.065236] cblist_init_generic: Setting adjustable number of callback queues.
10413 11:57:40.891373 <6>[ 0.072708] cblist_init_generic: Setting shift to 3 and lim to 1.
10414 11:57:40.894860 <6>[ 0.079108] rcu: Hierarchical SRCU implementation.
10415 11:57:40.901558 <6>[ 0.084123] rcu: Max phase no-delay instances is 1000.
10416 11:57:40.908294 <6>[ 0.091144] EFI services will not be available.
10417 11:57:40.911365 <6>[ 0.096127] smp: Bringing up secondary CPUs ...
10418 11:57:40.919367 <6>[ 0.101174] Detected VIPT I-cache on CPU1
10419 11:57:40.926388 <6>[ 0.101242] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10420 11:57:40.932512 <6>[ 0.101274] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10421 11:57:40.936296 <6>[ 0.101610] Detected VIPT I-cache on CPU2
10422 11:57:40.943059 <6>[ 0.101658] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10423 11:57:40.953368 <6>[ 0.101673] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10424 11:57:40.956487 <6>[ 0.101933] Detected VIPT I-cache on CPU3
10425 11:57:40.962875 <6>[ 0.101979] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10426 11:57:40.969336 <6>[ 0.101992] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10427 11:57:40.973039 <6>[ 0.102294] CPU features: detected: Spectre-v4
10428 11:57:40.979707 <6>[ 0.102301] CPU features: detected: Spectre-BHB
10429 11:57:40.982265 <6>[ 0.102305] Detected PIPT I-cache on CPU4
10430 11:57:40.989733 <6>[ 0.102362] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10431 11:57:40.995933 <6>[ 0.102378] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10432 11:57:41.002353 <6>[ 0.102669] Detected PIPT I-cache on CPU5
10433 11:57:41.009549 <6>[ 0.102732] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10434 11:57:41.015969 <6>[ 0.102748] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10435 11:57:41.019346 <6>[ 0.103029] Detected PIPT I-cache on CPU6
10436 11:57:41.025771 <6>[ 0.103093] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10437 11:57:41.032357 <6>[ 0.103109] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10438 11:57:41.039647 <6>[ 0.103403] Detected PIPT I-cache on CPU7
10439 11:57:41.045519 <6>[ 0.103468] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10440 11:57:41.052536 <6>[ 0.103485] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10441 11:57:41.056155 <6>[ 0.103531] smp: Brought up 1 node, 8 CPUs
10442 11:57:41.062261 <6>[ 0.244915] SMP: Total of 8 processors activated.
10443 11:57:41.065647 <6>[ 0.249866] CPU features: detected: 32-bit EL0 Support
10444 11:57:41.075726 <6>[ 0.255229] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10445 11:57:41.082087 <6>[ 0.264029] CPU features: detected: Common not Private translations
10446 11:57:41.088733 <6>[ 0.270504] CPU features: detected: CRC32 instructions
10447 11:57:41.091836 <6>[ 0.275855] CPU features: detected: RCpc load-acquire (LDAPR)
10448 11:57:41.098771 <6>[ 0.281815] CPU features: detected: LSE atomic instructions
10449 11:57:41.105394 <6>[ 0.287596] CPU features: detected: Privileged Access Never
10450 11:57:41.108620 <6>[ 0.293376] CPU features: detected: RAS Extension Support
10451 11:57:41.118786 <6>[ 0.298984] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10452 11:57:41.121707 <6>[ 0.306204] CPU: All CPU(s) started at EL2
10453 11:57:41.128147 <6>[ 0.310520] alternatives: applying system-wide alternatives
10454 11:57:41.137949 <6>[ 0.321210] devtmpfs: initialized
10455 11:57:41.149519 <6>[ 0.330181] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10456 11:57:41.159728 <6>[ 0.340145] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10457 11:57:41.166142 <6>[ 0.348170] pinctrl core: initialized pinctrl subsystem
10458 11:57:41.169954 <6>[ 0.354841] DMI not present or invalid.
10459 11:57:41.176184 <6>[ 0.359254] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10460 11:57:41.186095 <6>[ 0.366077] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10461 11:57:41.192830 <6>[ 0.373665] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10462 11:57:41.202797 <6>[ 0.381881] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10463 11:57:41.206186 <6>[ 0.390127] audit: initializing netlink subsys (disabled)
10464 11:57:41.216365 <5>[ 0.395823] audit: type=2000 audit(0.280:1): state=initialized audit_enabled=0 res=1
10465 11:57:41.222915 <6>[ 0.396533] thermal_sys: Registered thermal governor 'step_wise'
10466 11:57:41.229105 <6>[ 0.403793] thermal_sys: Registered thermal governor 'power_allocator'
10467 11:57:41.232503 <6>[ 0.410050] cpuidle: using governor menu
10468 11:57:41.238935 <6>[ 0.421014] NET: Registered PF_QIPCRTR protocol family
10469 11:57:41.246153 <6>[ 0.426503] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10470 11:57:41.249309 <6>[ 0.433607] ASID allocator initialised with 32768 entries
10471 11:57:41.256800 <6>[ 0.440186] Serial: AMBA PL011 UART driver
10472 11:57:41.265398 <4>[ 0.448977] Trying to register duplicate clock ID: 134
10473 11:57:41.321541 <6>[ 0.508551] KASLR enabled
10474 11:57:41.335988 <6>[ 0.516206] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10475 11:57:41.342437 <6>[ 0.523225] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10476 11:57:41.348922 <6>[ 0.529716] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10477 11:57:41.355893 <6>[ 0.536726] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10478 11:57:41.361956 <6>[ 0.543219] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10479 11:57:41.369159 <6>[ 0.550229] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10480 11:57:41.375389 <6>[ 0.556722] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10481 11:57:41.381990 <6>[ 0.563733] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10482 11:57:41.385458 <6>[ 0.571247] ACPI: Interpreter disabled.
10483 11:57:41.393817 <6>[ 0.577657] iommu: Default domain type: Translated
10484 11:57:41.400456 <6>[ 0.582772] iommu: DMA domain TLB invalidation policy: strict mode
10485 11:57:41.404145 <5>[ 0.589430] SCSI subsystem initialized
10486 11:57:41.410694 <6>[ 0.593595] usbcore: registered new interface driver usbfs
10487 11:57:41.416954 <6>[ 0.599329] usbcore: registered new interface driver hub
10488 11:57:41.420083 <6>[ 0.604882] usbcore: registered new device driver usb
10489 11:57:41.427167 <6>[ 0.610988] pps_core: LinuxPPS API ver. 1 registered
10490 11:57:41.437443 <6>[ 0.616186] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10491 11:57:41.440577 <6>[ 0.625538] PTP clock support registered
10492 11:57:41.444300 <6>[ 0.629781] EDAC MC: Ver: 3.0.0
10493 11:57:41.451265 <6>[ 0.634912] FPGA manager framework
10494 11:57:41.458101 <6>[ 0.638591] Advanced Linux Sound Architecture Driver Initialized.
10495 11:57:41.461020 <6>[ 0.645361] vgaarb: loaded
10496 11:57:41.467302 <6>[ 0.648526] clocksource: Switched to clocksource arch_sys_counter
10497 11:57:41.471109 <5>[ 0.654958] VFS: Disk quotas dquot_6.6.0
10498 11:57:41.478176 <6>[ 0.659142] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10499 11:57:41.480789 <6>[ 0.666333] pnp: PnP ACPI: disabled
10500 11:57:41.489360 <6>[ 0.672978] NET: Registered PF_INET protocol family
10501 11:57:41.499496 <6>[ 0.678559] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10502 11:57:41.510259 <6>[ 0.690890] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10503 11:57:41.520523 <6>[ 0.699706] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10504 11:57:41.526968 <6>[ 0.707677] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10505 11:57:41.533636 <6>[ 0.716378] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10506 11:57:41.546139 <6>[ 0.726132] TCP: Hash tables configured (established 65536 bind 65536)
10507 11:57:41.553061 <6>[ 0.732994] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10508 11:57:41.560080 <6>[ 0.740197] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10509 11:57:41.566061 <6>[ 0.747899] NET: Registered PF_UNIX/PF_LOCAL protocol family
10510 11:57:41.572847 <6>[ 0.754074] RPC: Registered named UNIX socket transport module.
10511 11:57:41.575409 <6>[ 0.760230] RPC: Registered udp transport module.
10512 11:57:41.582013 <6>[ 0.765162] RPC: Registered tcp transport module.
10513 11:57:41.588946 <6>[ 0.770098] RPC: Registered tcp NFSv4.1 backchannel transport module.
10514 11:57:41.591968 <6>[ 0.776767] PCI: CLS 0 bytes, default 64
10515 11:57:41.595213 <6>[ 0.781166] Unpacking initramfs...
10516 11:57:41.620630 <6>[ 0.800629] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10517 11:57:41.630361 <6>[ 0.809304] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10518 11:57:41.633467 <6>[ 0.818113] kvm [1]: IPA Size Limit: 40 bits
10519 11:57:41.640041 <6>[ 0.822646] kvm [1]: GICv3: no GICV resource entry
10520 11:57:41.643906 <6>[ 0.827670] kvm [1]: disabling GICv2 emulation
10521 11:57:41.650592 <6>[ 0.832358] kvm [1]: GIC system register CPU interface enabled
10522 11:57:41.653430 <6>[ 0.838523] kvm [1]: vgic interrupt IRQ18
10523 11:57:41.660022 <6>[ 0.842877] kvm [1]: VHE mode initialized successfully
10524 11:57:41.666796 <5>[ 0.849360] Initialise system trusted keyrings
10525 11:57:41.674009 <6>[ 0.854186] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10526 11:57:41.680396 <6>[ 0.864174] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10527 11:57:41.687708 <5>[ 0.870570] NFS: Registering the id_resolver key type
10528 11:57:41.690485 <5>[ 0.875875] Key type id_resolver registered
10529 11:57:41.697202 <5>[ 0.880291] Key type id_legacy registered
10530 11:57:41.703674 <6>[ 0.884576] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10531 11:57:41.710595 <6>[ 0.891499] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10532 11:57:41.717149 <6>[ 0.899213] 9p: Installing v9fs 9p2000 file system support
10533 11:57:41.752951 <5>[ 0.936947] Key type asymmetric registered
10534 11:57:41.756659 <5>[ 0.941280] Asymmetric key parser 'x509' registered
10535 11:57:41.766390 <6>[ 0.946464] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10536 11:57:41.769408 <6>[ 0.954084] io scheduler mq-deadline registered
10537 11:57:41.773232 <6>[ 0.958854] io scheduler kyber registered
10538 11:57:41.791611 <6>[ 0.975908] EINJ: ACPI disabled.
10539 11:57:41.823832 <4>[ 1.001450] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10540 11:57:41.833825 <4>[ 1.012090] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10541 11:57:41.848961 <6>[ 1.033053] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10542 11:57:41.857235 <6>[ 1.041107] printk: console [ttyS0] disabled
10543 11:57:41.885348 <6>[ 1.065754] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10544 11:57:41.891875 <6>[ 1.075232] printk: console [ttyS0] enabled
10545 11:57:41.895115 <6>[ 1.075232] printk: console [ttyS0] enabled
10546 11:57:41.902297 <6>[ 1.084124] printk: bootconsole [mtk8250] disabled
10547 11:57:41.905373 <6>[ 1.084124] printk: bootconsole [mtk8250] disabled
10548 11:57:41.911621 <6>[ 1.095399] SuperH (H)SCI(F) driver initialized
10549 11:57:41.914895 <6>[ 1.100693] msm_serial: driver initialized
10550 11:57:41.929462 <6>[ 1.109678] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10551 11:57:41.939496 <6>[ 1.118223] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10552 11:57:41.945932 <6>[ 1.126764] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10553 11:57:41.955806 <6>[ 1.135392] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10554 11:57:41.962647 <6>[ 1.144100] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10555 11:57:41.972629 <6>[ 1.152822] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10556 11:57:41.982193 <6>[ 1.161363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10557 11:57:41.988914 <6>[ 1.170165] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10558 11:57:41.998460 <6>[ 1.178709] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10559 11:57:42.010294 <6>[ 1.194294] loop: module loaded
10560 11:57:42.016956 <6>[ 1.200257] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10561 11:57:42.039831 <4>[ 1.224028] mtk-pmic-keys: Failed to locate of_node [id: -1]
10562 11:57:42.047117 <6>[ 1.231122] megasas: 07.719.03.00-rc1
10563 11:57:42.056730 <6>[ 1.240953] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10564 11:57:42.063913 <6>[ 1.247918] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10565 11:57:42.080897 <6>[ 1.264532] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10566 11:57:42.136468 <6>[ 1.314121] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10567 11:57:43.192386 <6>[ 2.376616] Freeing initrd memory: 38428K
10568 11:57:43.203154 <6>[ 2.386985] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10569 11:57:43.214306 <6>[ 2.397964] tun: Universal TUN/TAP device driver, 1.6
10570 11:57:43.217221 <6>[ 2.404030] thunder_xcv, ver 1.0
10571 11:57:43.220860 <6>[ 2.407533] thunder_bgx, ver 1.0
10572 11:57:43.224309 <6>[ 2.411032] nicpf, ver 1.0
10573 11:57:43.234372 <6>[ 2.415060] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10574 11:57:43.237827 <6>[ 2.422535] hns3: Copyright (c) 2017 Huawei Corporation.
10575 11:57:43.244432 <6>[ 2.428123] hclge is initializing
10576 11:57:43.248046 <6>[ 2.431704] e1000: Intel(R) PRO/1000 Network Driver
10577 11:57:43.254160 <6>[ 2.436833] e1000: Copyright (c) 1999-2006 Intel Corporation.
10578 11:57:43.257739 <6>[ 2.442848] e1000e: Intel(R) PRO/1000 Network Driver
10579 11:57:43.264112 <6>[ 2.448064] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10580 11:57:43.270651 <6>[ 2.454249] igb: Intel(R) Gigabit Ethernet Network Driver
10581 11:57:43.277067 <6>[ 2.459899] igb: Copyright (c) 2007-2014 Intel Corporation.
10582 11:57:43.284242 <6>[ 2.465734] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10583 11:57:43.290576 <6>[ 2.472252] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10584 11:57:43.294117 <6>[ 2.478721] sky2: driver version 1.30
10585 11:57:43.300674 <6>[ 2.483717] VFIO - User Level meta-driver version: 0.3
10586 11:57:43.308224 <6>[ 2.491952] usbcore: registered new interface driver usb-storage
10587 11:57:43.314450 <6>[ 2.498398] usbcore: registered new device driver onboard-usb-hub
10588 11:57:43.323524 <6>[ 2.507554] mt6397-rtc mt6359-rtc: registered as rtc0
10589 11:57:43.333616 <6>[ 2.513021] mt6397-rtc mt6359-rtc: setting system clock to 2023-11-23T11:55:31 UTC (1700740531)
10590 11:57:43.336721 <6>[ 2.522585] i2c_dev: i2c /dev entries driver
10591 11:57:43.353752 <6>[ 2.534262] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10592 11:57:43.373566 <6>[ 2.557267] cpu cpu0: EM: created perf domain
10593 11:57:43.376794 <6>[ 2.562195] cpu cpu4: EM: created perf domain
10594 11:57:43.383983 <6>[ 2.567815] sdhci: Secure Digital Host Controller Interface driver
10595 11:57:43.390590 <6>[ 2.574247] sdhci: Copyright(c) Pierre Ossman
10596 11:57:43.397056 <6>[ 2.579202] Synopsys Designware Multimedia Card Interface Driver
10597 11:57:43.404076 <6>[ 2.585847] sdhci-pltfm: SDHCI platform and OF driver helper
10598 11:57:43.407352 <6>[ 2.585896] mmc0: CQHCI version 5.10
10599 11:57:43.413786 <6>[ 2.596037] ledtrig-cpu: registered to indicate activity on CPUs
10600 11:57:43.420368 <6>[ 2.603136] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10601 11:57:43.426904 <6>[ 2.610197] usbcore: registered new interface driver usbhid
10602 11:57:43.430512 <6>[ 2.616020] usbhid: USB HID core driver
10603 11:57:43.436756 <6>[ 2.620221] spi_master spi0: will run message pump with realtime priority
10604 11:57:43.483173 <6>[ 2.660687] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10605 11:57:43.502611 <6>[ 2.676483] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10606 11:57:43.509846 <6>[ 2.691854] cros-ec-spi spi0.0: Chrome EC device registered
10607 11:57:43.513068 <6>[ 2.697910] mmc0: Command Queue Engine enabled
10608 11:57:43.519682 <6>[ 2.702654] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10609 11:57:43.526182 <6>[ 2.710136] mmcblk0: mmc0:0001 DA4128 116 GiB
10610 11:57:43.536420 <6>[ 2.711630] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10611 11:57:43.539967 <6>[ 2.720665] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10612 11:57:43.546456 <6>[ 2.725314] NET: Registered PF_PACKET protocol family
10613 11:57:43.552955 <6>[ 2.731615] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 11:57:43.556451 <6>[ 2.735464] 9pnet: Installing 9P2000 support
10615 11:57:43.562861 <6>[ 2.741500] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10616 11:57:43.566251 <5>[ 2.745157] Key type dns_resolver registered
10617 11:57:43.572416 <6>[ 2.751074] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 11:57:43.576090 <6>[ 2.755319] registered taskstats version 1
10619 11:57:43.582430 <5>[ 2.765776] Loading compiled-in X.509 certificates
10620 11:57:43.615045 <4>[ 2.792589] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10621 11:57:43.625306 <4>[ 2.803317] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 11:57:43.631886 <3>[ 2.813845] debugfs: File 'uA_load' in directory '/' already present!
10623 11:57:43.638520 <3>[ 2.820696] debugfs: File 'min_uV' in directory '/' already present!
10624 11:57:43.645297 <3>[ 2.827314] debugfs: File 'max_uV' in directory '/' already present!
10625 11:57:43.651555 <3>[ 2.833921] debugfs: File 'constraint_flags' in directory '/' already present!
10626 11:57:43.664506 <3>[ 2.845037] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10627 11:57:43.677417 <6>[ 2.861338] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10628 11:57:43.685162 <6>[ 2.868205] xhci-mtk 11200000.usb: xHCI Host Controller
10629 11:57:43.691065 <6>[ 2.873705] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10630 11:57:43.701089 <6>[ 2.881545] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10631 11:57:43.707870 <6>[ 2.890967] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10632 11:57:43.714346 <6>[ 2.897037] xhci-mtk 11200000.usb: xHCI Host Controller
10633 11:57:43.720701 <6>[ 2.902515] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10634 11:57:43.727508 <6>[ 2.910165] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10635 11:57:43.733845 <6>[ 2.917779] hub 1-0:1.0: USB hub found
10636 11:57:43.737369 <6>[ 2.921804] hub 1-0:1.0: 1 port detected
10637 11:57:43.743658 <6>[ 2.926074] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10638 11:57:43.750871 <6>[ 2.934639] hub 2-0:1.0: USB hub found
10639 11:57:43.753690 <6>[ 2.938657] hub 2-0:1.0: 1 port detected
10640 11:57:43.761212 <6>[ 2.945742] mtk-msdc 11f70000.mmc: Got CD GPIO
10641 11:57:43.771505 <6>[ 2.952592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10642 11:57:43.778298 <6>[ 2.960620] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10643 11:57:43.788467 <4>[ 2.968556] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10644 11:57:43.798218 <6>[ 2.978082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10645 11:57:43.804810 <6>[ 2.986177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10646 11:57:43.811658 <6>[ 2.994319] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10647 11:57:43.821268 <6>[ 3.002256] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10648 11:57:43.828233 <6>[ 3.010082] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10649 11:57:43.838072 <6>[ 3.017902] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10650 11:57:43.848131 <6>[ 3.028375] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10651 11:57:43.854767 <6>[ 3.036753] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10652 11:57:43.864481 <6>[ 3.045095] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10653 11:57:43.871229 <6>[ 3.053434] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10654 11:57:43.881415 <6>[ 3.061771] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10655 11:57:43.887705 <6>[ 3.070111] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10656 11:57:43.898120 <6>[ 3.078452] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10657 11:57:43.904597 <6>[ 3.086790] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10658 11:57:43.914351 <6>[ 3.095128] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10659 11:57:43.920933 <6>[ 3.103467] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10660 11:57:43.931525 <6>[ 3.111805] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10661 11:57:43.937745 <6>[ 3.120144] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10662 11:57:43.947655 <6>[ 3.128481] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10663 11:57:43.957527 <6>[ 3.136823] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10664 11:57:43.963859 <6>[ 3.145164] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10665 11:57:43.970643 <6>[ 3.153924] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10666 11:57:43.977414 <6>[ 3.161076] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10667 11:57:43.983829 <6>[ 3.167823] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10668 11:57:43.990539 <6>[ 3.174584] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10669 11:57:43.997197 <6>[ 3.181520] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10670 11:57:44.007475 <6>[ 3.188361] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10671 11:57:44.017515 <6>[ 3.197487] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10672 11:57:44.027260 <6>[ 3.206608] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10673 11:57:44.037584 <6>[ 3.215903] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10674 11:57:44.044040 <6>[ 3.225375] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10675 11:57:44.054031 <6>[ 3.234843] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10676 11:57:44.063680 <6>[ 3.243984] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10677 11:57:44.073290 <6>[ 3.253470] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10678 11:57:44.083283 <6>[ 3.262588] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10679 11:57:44.093341 <6>[ 3.271882] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10680 11:57:44.103532 <6>[ 3.282043] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10681 11:57:44.113440 <6>[ 3.293620] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10682 11:57:44.144455 <6>[ 3.325020] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10683 11:57:44.171388 <6>[ 3.355508] hub 2-1:1.0: USB hub found
10684 11:57:44.174152 <6>[ 3.359936] hub 2-1:1.0: 3 ports detected
10685 11:57:44.182747 <6>[ 3.366658] hub 2-1:1.0: USB hub found
10686 11:57:44.185827 <6>[ 3.371141] hub 2-1:1.0: 3 ports detected
10687 11:57:44.295707 <6>[ 3.476811] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10688 11:57:44.450086 <6>[ 3.634542] hub 1-1:1.0: USB hub found
10689 11:57:44.453574 <6>[ 3.639035] hub 1-1:1.0: 4 ports detected
10690 11:57:44.462481 <6>[ 3.646822] hub 1-1:1.0: USB hub found
10691 11:57:44.466161 <6>[ 3.651357] hub 1-1:1.0: 4 ports detected
10692 11:57:44.536087 <6>[ 3.716897] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10693 11:57:44.787926 <6>[ 3.968852] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10694 11:57:44.920042 <6>[ 4.104572] hub 1-1.4:1.0: USB hub found
10695 11:57:44.923381 <6>[ 4.109206] hub 1-1.4:1.0: 2 ports detected
10696 11:57:44.933258 <6>[ 4.117780] hub 1-1.4:1.0: USB hub found
10697 11:57:44.936355 <6>[ 4.122376] hub 1-1.4:1.0: 2 ports detected
10698 11:57:45.235597 <6>[ 4.416808] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10699 11:57:45.427563 <6>[ 4.608808] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10700 11:57:56.408685 <6>[ 15.597809] ALSA device list:
10701 11:57:56.415144 <6>[ 15.601105] No soundcards found.
10702 11:57:56.423616 <6>[ 15.609066] Freeing unused kernel memory: 8384K
10703 11:57:56.427191 <6>[ 15.614047] Run /init as init process
10704 11:57:56.476253 <6>[ 15.662255] NET: Registered PF_INET6 protocol family
10705 11:57:56.483202 <6>[ 15.668618] Segment Routing with IPv6
10706 11:57:56.486492 <6>[ 15.672575] In-situ OAM (IOAM) with IPv6
10707 11:57:56.520352 <30>[ 15.689747] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10708 11:57:56.528008 <30>[ 15.713881] systemd[1]: Detected architecture arm64.
10709 11:57:56.528101
10710 11:57:56.534494 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10711 11:57:56.534578
10712 11:57:56.547274 <30>[ 15.732799] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10713 11:57:56.710474 <30>[ 15.893171] systemd[1]: Queued start job for default target Graphical Interface.
10714 11:57:56.759995 <30>[ 15.945564] systemd[1]: Created slice system-getty.slice.
10715 11:57:56.766471 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10716 11:57:56.783933 <30>[ 15.969495] systemd[1]: Created slice system-modprobe.slice.
10717 11:57:56.789912 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10718 11:57:56.807368 <30>[ 15.993270] systemd[1]: Created slice system-serial\x2dgetty.slice.
10719 11:57:56.817278 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10720 11:57:56.831203 <30>[ 16.017081] systemd[1]: Created slice User and Session Slice.
10721 11:57:56.837724 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10722 11:57:56.858990 <30>[ 16.041346] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10723 11:57:56.868938 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10724 11:57:56.887462 <30>[ 16.069443] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10725 11:57:56.893706 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10726 11:57:56.917477 <30>[ 16.096891] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10727 11:57:56.924278 <30>[ 16.109045] systemd[1]: Reached target Local Encrypted Volumes.
10728 11:57:56.931083 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10729 11:57:56.947376 <30>[ 16.133341] systemd[1]: Reached target Paths.
10730 11:57:56.950883 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10731 11:57:56.967687 <30>[ 16.152814] systemd[1]: Reached target Remote File Systems.
10732 11:57:56.973750 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10733 11:57:56.991401 <30>[ 16.177174] systemd[1]: Reached target Slices.
10734 11:57:56.998044 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10735 11:57:57.010897 <30>[ 16.196841] systemd[1]: Reached target Swap.
10736 11:57:57.014050 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10737 11:57:57.034537 <30>[ 16.217286] systemd[1]: Listening on initctl Compatibility Named Pipe.
10738 11:57:57.041218 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10739 11:57:57.047921 <30>[ 16.232500] systemd[1]: Listening on Journal Audit Socket.
10740 11:57:57.054211 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10741 11:57:57.067495 <30>[ 16.253269] systemd[1]: Listening on Journal Socket (/dev/log).
10742 11:57:57.074223 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10743 11:57:57.092126 <30>[ 16.278039] systemd[1]: Listening on Journal Socket.
10744 11:57:57.098634 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10745 11:57:57.114796 <30>[ 16.297507] systemd[1]: Listening on Network Service Netlink Socket.
10746 11:57:57.121515 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10747 11:57:57.136333 <30>[ 16.322013] systemd[1]: Listening on udev Control Socket.
10748 11:57:57.142890 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10749 11:57:57.159748 <30>[ 16.345902] systemd[1]: Listening on udev Kernel Socket.
10750 11:57:57.166245 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10751 11:57:57.219155 <30>[ 16.405047] systemd[1]: Mounting Huge Pages File System...
10752 11:57:57.225676 Mounting [0;1;39mHuge Pages File System[0m...
10753 11:57:57.240547 <30>[ 16.426489] systemd[1]: Mounting POSIX Message Queue File System...
10754 11:57:57.247186 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10755 11:57:57.264483 <30>[ 16.450740] systemd[1]: Mounting Kernel Debug File System...
10756 11:57:57.271051 Mounting [0;1;39mKernel Debug File System[0m...
10757 11:57:57.290534 <30>[ 16.473007] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10758 11:57:57.301716 <30>[ 16.484262] systemd[1]: Starting Create list of static device nodes for the current kernel...
10759 11:57:57.308380 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10760 11:57:57.359630 <30>[ 16.545561] systemd[1]: Starting Load Kernel Module configfs...
10761 11:57:57.366546 Starting [0;1;39mLoad Kernel Module configfs[0m...
10762 11:57:57.383376 <30>[ 16.569342] systemd[1]: Starting Load Kernel Module drm...
10763 11:57:57.389720 Starting [0;1;39mLoad Kernel Module drm[0m...
10764 11:57:57.406841 <30>[ 16.589205] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10765 11:57:57.455928 <30>[ 16.641750] systemd[1]: Starting Journal Service...
10766 11:57:57.459305 Starting [0;1;39mJournal Service[0m...
10767 11:57:57.480550 <30>[ 16.666638] systemd[1]: Starting Load Kernel Modules...
10768 11:57:57.487444 Starting [0;1;39mLoad Kernel Modules[0m...
10769 11:57:57.511079 <30>[ 16.693653] systemd[1]: Starting Remount Root and Kernel File Systems...
10770 11:57:57.517633 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10771 11:57:57.532979 <30>[ 16.719135] systemd[1]: Starting Coldplug All udev Devices...
10772 11:57:57.539506 Starting [0;1;39mColdplug All udev Devices[0m...
10773 11:57:57.557914 <30>[ 16.743687] systemd[1]: Started Journal Service.
10774 11:57:57.564026 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10775 11:57:57.580666 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10776 11:57:57.595963 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10777 11:57:57.612066 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10778 11:57:57.632023 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10779 11:57:57.649414 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10780 11:57:57.669712 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10781 11:57:57.689480 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10782 11:57:57.708822 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10783 11:57:57.723209 See 'systemctl status systemd-remount-fs.service' for details.
10784 11:57:57.773811 Mounting [0;1;39mKernel Configuration File System[0m...
10785 11:57:57.793792 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10786 11:57:57.807279 <46>[ 16.990039] systemd-journald[185]: Received client request to flush runtime journal.
10787 11:57:57.817302 Starting [0;1;39mLoad/Save Random Seed[0m...
10788 11:57:57.835201 Starting [0;1;39mApply Kernel Variables[0m...
10789 11:57:57.855977 Starting [0;1;39mCreate System Users[0m...
10790 11:57:57.876778 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10791 11:57:57.896168 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10792 11:57:57.915651 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10793 11:57:57.933193 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10794 11:57:57.948815 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10795 11:57:57.965001 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10796 11:57:58.031880 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10797 11:57:58.056694 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10798 11:57:58.075532 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10799 11:57:58.094859 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10800 11:57:58.139160 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10801 11:57:58.162851 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10802 11:57:58.180101 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10803 11:57:58.201238 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10804 11:57:58.221562 Starting [0;1;39mNetwork Service[0m...
10805 11:57:58.241616 Starting [0;1;39mNetwork Time Synchronization[0m...
10806 11:57:58.260666 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10807 11:57:58.288878 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10808 11:57:58.337867 Starting [0;1;39mNetwork Name Resolution[0m...
10809 11:57:58.352537 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10810 11:57:58.372823 <6>[ 17.555538] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10811 11:57:58.386051 [[0;32m OK [0m] Finished [0;1;39mUpdate UTM<6>[ 17.566679] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10812 11:57:58.392754 <6>[ 17.567214] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10813 11:57:58.402711 P about System B<6>[ 17.579321] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10814 11:57:58.406360 oot/Shutdown[0m.
10815 11:57:58.416426 <6>[ 17.602483] remoteproc remoteproc0: scp is available
10816 11:57:58.423206 <6>[ 17.607966] remoteproc remoteproc0: powering up scp
10817 11:57:58.433778 [[0;32m OK [<6>[ 17.614432] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10818 11:57:58.443600 0m] Started [0;<3>[ 17.625249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10819 11:57:58.449954 <6>[ 17.625603] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10820 11:57:58.456470 1;39mNetwork Nam<3>[ 17.633774] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10821 11:57:58.466362 <4>[ 17.645684] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10822 11:57:58.472928 e Resolution[0m<3>[ 17.649062] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10823 11:57:58.476425 .
10824 11:57:58.488657 <4>[ 17.671085] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10825 11:57:58.494855 <3>[ 17.671667] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 11:57:58.505055 <3>[ 17.686580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10827 11:57:58.511546 <3>[ 17.694682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10828 11:57:58.518073 <3>[ 17.702779] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10829 11:57:58.528324 [[0;32m OK [<3>[ 17.710874] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 11:57:58.538766 0m] Found device<3>[ 17.721571] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 11:57:58.545059 [0;1;39m/dev/t<6>[ 17.724757] usbcore: registered new interface driver r8152
10832 11:57:58.548005 tyS0[0m.
10833 11:57:58.554611 <3>[ 17.737438] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 11:57:58.564921 <3>[ 17.746464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10835 11:57:58.568116 <6>[ 17.749037] mc: Linux media interface: v0.10
10836 11:57:58.574631 <6>[ 17.751666] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10837 11:57:58.581254 <6>[ 17.751679] pci_bus 0000:00: root bus resource [bus 00-ff]
10838 11:57:58.587877 <6>[ 17.751688] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10839 11:57:58.597814 <6>[ 17.751696] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10840 11:57:58.605078 <6>[ 17.751749] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10841 11:57:58.610990 <6>[ 17.751781] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10842 11:57:58.618259 <6>[ 17.751888] pci 0000:00:00.0: supports D1 D2
10843 11:57:58.624493 <6>[ 17.751894] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10844 11:57:58.630730 <3>[ 17.754580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 11:57:58.640807 <3>[ 17.758350] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 11:57:58.647269 <6>[ 17.765086] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10847 11:57:58.654321 <6>[ 17.765086] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10848 11:57:58.664705 <3>[ 17.766364] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10849 11:57:58.671518 <6>[ 17.769446] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10850 11:57:58.677958 <6>[ 17.771945] remoteproc remoteproc0: remote processor scp is now up
10851 11:57:58.687966 <3>[ 17.779154] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10852 11:57:58.694384 <6>[ 17.784184] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10853 11:57:58.701713 <6>[ 17.784222] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10854 11:57:58.707789 <6>[ 17.784245] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10855 11:57:58.714305 <6>[ 17.784262] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10856 11:57:58.720897 <6>[ 17.784393] pci 0000:01:00.0: supports D1 D2
10857 11:57:58.727353 <6>[ 17.784395] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10858 11:57:58.734300 <6>[ 17.791395] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10859 11:57:58.744118 <3>[ 17.795319] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10860 11:57:58.750705 <3>[ 17.795325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10861 11:57:58.757636 <3>[ 17.801719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10862 11:57:58.767786 <6>[ 17.803763] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10863 11:57:58.777354 <4>[ 17.816151] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10864 11:57:58.780494 <4>[ 17.816151] Fallback method does not support PEC.
10865 11:57:58.787231 <6>[ 17.819380] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10866 11:57:58.797236 <6>[ 17.819455] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10867 11:57:58.804859 <6>[ 17.819463] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10868 11:57:58.811598 <6>[ 17.819480] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10869 11:57:58.821881 <6>[ 17.819496] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10870 11:57:58.827861 <6>[ 17.819512] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10871 11:57:58.834841 <6>[ 17.819529] pci 0000:00:00.0: PCI bridge to [bus 01]
10872 11:57:58.841509 <6>[ 17.819538] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10873 11:57:58.847937 <6>[ 17.823738] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10874 11:57:58.855503 <6>[ 17.847679] videodev: Linux video capture interface: v2.00
10875 11:57:58.861849 <6>[ 17.911093] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10876 11:57:58.868408 <6>[ 17.915190] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10877 11:57:58.875086 <6>[ 17.915423] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10878 11:57:58.884954 <3>[ 17.918325] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10879 11:57:58.895004 <6>[ 17.918842] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10880 11:57:58.901920 <6>[ 17.919119] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10881 11:57:58.911543 <4>[ 17.957851] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10882 11:57:58.918249 <6>[ 17.961651] usbcore: registered new interface driver cdc_ether
10883 11:57:58.925400 <4>[ 17.975972] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10884 11:57:58.935144 <5>[ 17.977749] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10885 11:57:58.941762 <6>[ 17.978249] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10886 11:57:58.952332 <6>[ 17.981245] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10887 11:57:58.955496 <6>[ 17.984665] Bluetooth: Core ver 2.22
10888 11:57:58.958928 <6>[ 17.984731] NET: Registered PF_BLUETOOTH protocol family
10889 11:57:58.966091 <6>[ 17.984734] Bluetooth: HCI device and connection manager initialized
10890 11:57:58.972670 <6>[ 17.984752] Bluetooth: HCI socket layer initialized
10891 11:57:58.975787 <6>[ 17.984758] Bluetooth: L2CAP socket layer initialized
10892 11:57:58.982648 <6>[ 17.984770] Bluetooth: SCO socket layer initialized
10893 11:57:58.990050 <6>[ 17.988715] usbcore: registered new interface driver r8153_ecm
10894 11:57:58.996759 <5>[ 18.005101] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10895 11:57:59.002942 <6>[ 18.020317] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10896 11:57:59.006707 <6>[ 18.026693] usbcore: registered new interface driver btusb
10897 11:57:59.012898 <6>[ 18.027367] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10898 11:57:59.022793 <4>[ 18.034424] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10899 11:57:59.033166 <4>[ 18.034425] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10900 11:57:59.039739 <3>[ 18.034436] Bluetooth: hci0: Failed to load firmware file (-2)
10901 11:57:59.046085 <3>[ 18.034440] Bluetooth: hci0: Failed to set up firmware (-2)
10902 11:57:59.056730 <4>[ 18.034444] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10903 11:57:59.063269 <6>[ 18.101563] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10904 11:57:59.069324 <6>[ 18.102905] cfg80211: failed to load regulatory.db
10905 11:57:59.083437 <6>[ 18.103799] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10906 11:57:59.086634 <6>[ 18.103966] usbcore: registered new interface driver uvcvideo
10907 11:57:59.093526 <6>[ 18.109101] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10908 11:57:59.096312 <6>[ 18.117437] r8152 2-1.3:1.0 eth0: v1.12.13
10909 11:57:59.106547 <3>[ 18.118445] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10910 11:57:59.113602 <3>[ 18.119109] power_supply sbs-5-000b: driver failed to report `health' property: -6
10911 11:57:59.120756 <6>[ 18.144650] mt7921e 0000:01:00.0: ASIC revision: 79610010
10912 11:57:59.130269 <3>[ 18.154980] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 11:57:59.136782 <6>[ 18.162820] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10914 11:57:59.143326 <3>[ 18.163189] power_supply sbs-5-000b: driver failed to report `capacity_error_margin' property: -6
10915 11:57:59.153160 <3>[ 18.181898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:57:59.163469 <4>[ 18.251872] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10917 11:57:59.173631 <3>[ 18.276963] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10918 11:57:59.179964 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10919 11:57:59.208110 [[0;32m OK [0m] Reached target [0;1;39mNetw<4>[ 18.387129] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10920 11:57:59.218230 <3>[ 18.387762] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:57:59.218667 ork[0m.
10922 11:57:59.234983 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10923 11:57:59.254740 [[0;32m OK [0m] Reached targ<3>[ 18.435330] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10924 11:57:59.258104 et [0;1;39mSystem Time Set[0m.
10925 11:57:59.271294 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10926 11:57:59.282907 <3>[ 18.465360] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 11:57:59.330301 <4>[ 18.509094] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 11:57:59.336976 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10929 11:57:59.359642 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10930 11:57:59.451354 <4>[ 18.630496] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10931 11:57:59.524182 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10932 11:57:59.543698 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10933 11:57:59.567003 [[0;32m OK [<4>[ 18.747049] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10934 11:57:59.573261 0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10935 11:57:59.591642 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10936 11:57:59.606929 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10937 11:57:59.626849 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10938 11:57:59.639030 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10939 11:57:59.655452 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10940 11:57:59.676265 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10941 11:57:59.685989 <4>[ 18.867219] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10942 11:57:59.740082 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10943 11:57:59.775560 Starting [0;1;39mUser Login Management[0m...
10944 11:57:59.810214 <4>[ 18.989654] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10945 11:57:59.816593 Starting [0;1;39mPermit User Sessions[0m...
10946 11:57:59.836461 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10947 11:57:59.852338 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10948 11:57:59.871834 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10949 11:57:59.887007 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10950 11:57:59.908457 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10951 11:57:59.933009 <4>[ 19.112080] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10952 11:57:59.939591 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10953 11:57:59.952204 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10954 11:57:59.969966 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10955 11:57:59.988669 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10956 11:58:00.051284 <4>[ 19.230767] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10957 11:58:00.058227 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10958 11:58:00.086455 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10959 11:58:00.126591
10960 11:58:00.127041
10961 11:58:00.129503 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10962 11:58:00.129920
10963 11:58:00.132906 debian-bullseye-arm64 login: root (automatic login)
10964 11:58:00.133407
10965 11:58:00.133838
10966 11:58:00.175055 Linux debian-bullseye-arm64 6.1.<4>[ 19.353195] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10967 11:58:00.178910 62-cip9 #1 SMP PREEMPT Thu Nov 23 11:35:49 UTC 2023 aarch64
10968 11:58:00.179427
10969 11:58:00.185648 The programs included with the Debian GNU/Linux system are free software;
10970 11:58:00.191656 the exact distribution terms for each program are described in the
10971 11:58:00.198497 individual files in /usr/share/doc/*/copyright.
10972 11:58:00.198932
10973 11:58:00.201510 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10974 11:58:00.204828 permitted by applicable law.
10975 11:58:00.206032 Matched prompt #10: / #
10977 11:58:00.206942 Setting prompt string to ['/ #']
10978 11:58:00.207330 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10980 11:58:00.208210 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10981 11:58:00.208610 start: 2.2.6 expect-shell-connection (timeout 00:03:27) [common]
10982 11:58:00.208921 Setting prompt string to ['/ #']
10983 11:58:00.209200 Forcing a shell prompt, looking for ['/ #']
10985 11:58:00.259985 / #
10986 11:58:00.260579 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10987 11:58:00.261025 Waiting using forced prompt support (timeout 00:02:30)
10988 11:58:00.266460
10989 11:58:00.267221 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10990 11:58:00.267696 start: 2.2.7 export-device-env (timeout 00:03:27) [common]
10991 11:58:00.268151 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10992 11:58:00.268572 end: 2.2 depthcharge-retry (duration 00:01:33) [common]
10993 11:58:00.268990 end: 2 depthcharge-action (duration 00:01:33) [common]
10994 11:58:00.269434 start: 3 lava-test-retry (timeout 00:08:06) [common]
10995 11:58:00.269909 start: 3.1 lava-test-shell (timeout 00:08:06) [common]
10996 11:58:00.270276 Using namespace: common
10998 11:58:00.371435 / # #
10999 11:58:00.372158 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11000 11:58:00.372834 <3>[ 19.473016] mt7921e 0000:01:00.0: hardware init failed
11001 11:58:00.377891 #
11002 11:58:00.378690 Using /lava-12066541
11004 11:58:00.480090 / # export SHELL=/bin/sh
11005 11:58:00.487254 export SHELL=/bin/sh
11007 11:58:00.588867 / # . /lava-12066541/environment
11008 11:58:00.589622 <6>[ 19.722982] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
11009 11:58:00.590045 <6>[ 19.730705] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
11010 11:58:00.595361 . /lava-12066541/environment
11012 11:58:00.696948 / # /lava-12066541/bin/lava-test-runner /lava-12066541/0
11013 11:58:00.697523 Test shell timeout: 10s (minimum of the action and connection timeout)
11014 11:58:00.702938 /lava-12066541/bin/lava-test-runner /lava-12066541/0
11015 11:58:00.728238 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11016 11:58:00.734571 + cd /lava-12066541/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11017 11:58:00.735214 + cat uuid
11018 11:58:00.738066 + UUID=12066541_1.5.2.3.1
11019 11:58:00.738498 + set +x
11020 11:58:00.744697 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 12066541_1.5.2.3.1>
11021 11:58:00.745388 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 12066541_1.5.2.3.1
11022 11:58:00.745805 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (12066541_1.5.2.3.1)
11023 11:58:00.746249 Skipping test definition patterns.
11024 11:58:00.748289 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11025 11:58:00.754721 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11026 11:58:00.755148 device: /dev/video0
11027 11:58:00.755732 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11029 11:58:00.771019 <4>[ 19.945863] use of bytesused == 0 is deprecated and will be removed in the future,
11030 11:58:00.771918 <4>[ 19.954048] use the actual size instead.
11031 11:58:00.781910 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11032 11:58:00.793416 v4l2-compliance SHA: 16e70e28584c 2023-06-22 09:47:27
11033 11:58:00.800442
11034 11:58:00.815648 Compliance test for mtk-vcodec-enc device /dev/video0:
11035 11:58:00.823849
11036 11:58:00.834786 Driver Info:
11037 11:58:00.843822 Driver name : mtk-vcodec-enc
11038 11:58:00.859565 Card type : MT8192 video encoder
11039 11:58:00.875282 Bus info : platform:17020000.vcodec
11040 11:58:00.882988 Driver version : 6.1.62
11041 11:58:00.897785 Capabilities : 0x84204000
11042 11:58:00.909932 Video Memory-to-Memory Multiplanar
11043 11:58:00.924670 Streaming
11044 11:58:00.935939 Extended Pix Format
11045 11:58:00.946703 Device Capabilities
11046 11:58:00.957344 Device Caps : 0x04204000
11047 11:58:00.969818 Video Memory-to-Memory Multiplanar
11048 11:58:00.984018 Streaming
11049 11:58:00.995842 Extended Pix Format
11050 11:58:01.006589 Detected Stateful Encoder
11051 11:58:01.017185
11052 11:58:01.032655 Required ioctls:
11053 11:58:01.047187 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11054 11:58:01.047844 test VIDIOC_QUERYCAP: OK
11055 11:58:01.048634 Received signal: <TESTSET> START Required-ioctls
11056 11:58:01.049168 Starting test_set Required-ioctls
11057 11:58:01.071065 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11058 11:58:01.071827 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11060 11:58:01.074338 test invalid ioctls: OK
11061 11:58:01.095529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11062 11:58:01.096044
11063 11:58:01.096635 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11065 11:58:01.106573 Allow for multiple opens:
11066 11:58:01.114645 <LAVA_SIGNAL_TESTSET STOP>
11067 11:58:01.115417 Received signal: <TESTSET> STOP
11068 11:58:01.115775 Closing test_set Required-ioctls
11069 11:58:01.124293 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11070 11:58:01.125069 Received signal: <TESTSET> START Allow-for-multiple-opens
11071 11:58:01.125420 Starting test_set Allow-for-multiple-opens
11072 11:58:01.127089 test second /dev/video0 open: OK
11073 11:58:01.147995 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video0-open RESULT=pass>
11074 11:58:01.148781 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video0-open RESULT=pass
11076 11:58:01.151333 test VIDIOC_QUERYCAP: OK
11077 11:58:01.177477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11078 11:58:01.178341 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11080 11:58:01.180527 test VIDIOC_G/S_PRIORITY: OK
11081 11:58:01.203908 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11082 11:58:01.204689 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11084 11:58:01.207514 test for unlimited opens: OK
11085 11:58:01.228459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11086 11:58:01.228977
11087 11:58:01.229621 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11089 11:58:01.240663 Debug ioctls:
11090 11:58:01.246363 <LAVA_SIGNAL_TESTSET STOP>
11091 11:58:01.247029 Received signal: <TESTSET> STOP
11092 11:58:01.247372 Closing test_set Allow-for-multiple-opens
11093 11:58:01.256295 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11094 11:58:01.257081 Received signal: <TESTSET> START Debug-ioctls
11095 11:58:01.257435 Starting test_set Debug-ioctls
11096 11:58:01.259427 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11097 11:58:01.282130 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11098 11:58:01.282910 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11100 11:58:01.288614 test VIDIOC_LOG_STATUS: OK (Not Supported)
11101 11:58:01.305907 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11102 11:58:01.306526
11103 11:58:01.307263 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11105 11:58:01.316464 Input ioctls:
11106 11:58:01.325473 <LAVA_SIGNAL_TESTSET STOP>
11107 11:58:01.326317 Received signal: <TESTSET> STOP
11108 11:58:01.326682 Closing test_set Debug-ioctls
11109 11:58:01.335750 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11110 11:58:01.336533 Received signal: <TESTSET> START Input-ioctls
11111 11:58:01.336883 Starting test_set Input-ioctls
11112 11:58:01.338661 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11113 11:58:01.364161 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11114 11:58:01.364942 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11116 11:58:01.366557 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11117 11:58:01.387082 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11118 11:58:01.388159 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11120 11:58:01.393520 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11121 11:58:01.412873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11122 11:58:01.413690 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11124 11:58:01.419252 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11125 11:58:01.438937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11126 11:58:01.439702 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11128 11:58:01.445646 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11129 11:58:01.463729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11130 11:58:01.464521 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11132 11:58:01.467452 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11133 11:58:01.489613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11134 11:58:01.490372 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11136 11:58:01.492634 Inputs: 0 Audio Inputs: 0 Tuners: 0
11137 11:58:01.500516
11138 11:58:01.518674 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11139 11:58:01.539954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11140 11:58:01.540722 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11142 11:58:01.545984 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11143 11:58:01.565864 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11144 11:58:01.566622 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11146 11:58:01.572308 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11147 11:58:01.592022 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11148 11:58:01.592793 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11150 11:58:01.598384 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11151 11:58:01.617985 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11152 11:58:01.618787 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11154 11:58:01.624313 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11155 11:58:01.642466 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11156 11:58:01.643629 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11158 11:58:01.645501
11159 11:58:01.661953 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11160 11:58:01.684184 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11161 11:58:01.684963 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11163 11:58:01.690720 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11164 11:58:01.711472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11165 11:58:01.712279 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11167 11:58:01.714734 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11168 11:58:01.732964 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11169 11:58:01.733716 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11171 11:58:01.736237 test VIDIOC_G/S_EDID: OK (Not Supported)
11172 11:58:01.757722 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11173 11:58:01.758324
11174 11:58:01.759125 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11176 11:58:01.767490 Control ioctls:
11177 11:58:01.775511 <LAVA_SIGNAL_TESTSET STOP>
11178 11:58:01.776318 Received signal: <TESTSET> STOP
11179 11:58:01.776690 Closing test_set Input-ioctls
11180 11:58:01.785208 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11181 11:58:01.786050 Received signal: <TESTSET> START Control-ioctls
11182 11:58:01.786405 Starting test_set Control-ioctls
11183 11:58:01.788332 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11184 11:58:01.812681 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11185 11:58:01.813220 test VIDIOC_QUERYCTRL: OK
11186 11:58:01.813893 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11188 11:58:01.838694 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11189 11:58:01.839356 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11191 11:58:01.841705 test VIDIOC_G/S_CTRL: OK
11192 11:58:01.864029 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11193 11:58:01.864843 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11195 11:58:01.867143 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11196 11:58:01.889139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11197 11:58:01.890098 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11199 11:58:01.898156 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11200 11:58:01.901494 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11201 11:58:01.934493 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11202 11:58:01.935138 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11204 11:58:01.937244 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11205 11:58:01.956537 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11206 11:58:01.957275 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11208 11:58:01.960199 Standard Controls: 16 Private Controls: 0
11209 11:58:01.968573
11210 11:58:01.978822 Format ioctls:
11211 11:58:01.985498 <LAVA_SIGNAL_TESTSET STOP>
11212 11:58:01.986202 Received signal: <TESTSET> STOP
11213 11:58:01.986540 Closing test_set Control-ioctls
11214 11:58:01.994351 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11215 11:58:01.995012 Received signal: <TESTSET> START Format-ioctls
11216 11:58:01.995411 Starting test_set Format-ioctls
11217 11:58:01.997647 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11218 11:58:02.023442 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11219 11:58:02.024234 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11221 11:58:02.027211 test VIDIOC_G/S_PARM: OK
11222 11:58:02.043530 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11223 11:58:02.044286 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11225 11:58:02.047317 test VIDIOC_G_FBUF: OK (Not Supported)
11226 11:58:02.068776 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11227 11:58:02.069650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11229 11:58:02.071728 test VIDIOC_G_FMT: OK
11230 11:58:02.093933 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11231 11:58:02.094770 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11233 11:58:02.096852 test VIDIOC_TRY_FMT: OK
11234 11:58:02.118476 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11235 11:58:02.119231 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11237 11:58:02.128485 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11238 11:58:02.132701 test VIDIOC_S_FMT: FAIL
11239 11:58:02.160034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11240 11:58:02.160792 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11242 11:58:02.163546 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11243 11:58:02.185801 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11244 11:58:02.186573 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11246 11:58:02.188790 test Cropping: OK
11247 11:58:02.212513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11248 11:58:02.213359 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11250 11:58:02.216055 test Composing: OK (Not Supported)
11251 11:58:02.238720 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11252 11:58:02.239487 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11254 11:58:02.242502 test Scaling: OK (Not Supported)
11255 11:58:02.264848 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11256 11:58:02.265301
11257 11:58:02.266075 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11259 11:58:02.277750 Codec ioctls:
11260 11:58:02.283634 <LAVA_SIGNAL_TESTSET STOP>
11261 11:58:02.284456 Received signal: <TESTSET> STOP
11262 11:58:02.284834 Closing test_set Format-ioctls
11263 11:58:02.293568 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11264 11:58:02.294440 Received signal: <TESTSET> START Codec-ioctls
11265 11:58:02.294827 Starting test_set Codec-ioctls
11266 11:58:02.296521 test VIDIOC_(TRY_)ENCODER_CMD: OK
11267 11:58:02.322708 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11268 11:58:02.323645 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11270 11:58:02.329864 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11271 11:58:02.347269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11272 11:58:02.347961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11274 11:58:02.353700 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11275 11:58:02.378983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11276 11:58:02.379436
11277 11:58:02.380171 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11279 11:58:02.389181 Buffer ioctls:
11280 11:58:02.396169 <LAVA_SIGNAL_TESTSET STOP>
11281 11:58:02.396840 Received signal: <TESTSET> STOP
11282 11:58:02.397185 Closing test_set Codec-ioctls
11283 11:58:02.406103 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11284 11:58:02.406772 Received signal: <TESTSET> START Buffer-ioctls
11285 11:58:02.407117 Starting test_set Buffer-ioctls
11286 11:58:02.409072 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11287 11:58:02.434982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11288 11:58:02.435362 test VIDIOC_EXPBUF: OK
11289 11:58:02.435823 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11291 11:58:02.457394 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11292 11:58:02.457865 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11294 11:58:02.460150 test Requests: OK (Not Supported)
11295 11:58:02.482141 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11296 11:58:02.482502
11297 11:58:02.482961 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11299 11:58:02.494988 Test input 0:
11300 11:58:02.512900
11301 11:58:02.526251 Streaming ioctls:
11302 11:58:02.533804 <LAVA_SIGNAL_TESTSET STOP>
11303 11:58:02.534535 Received signal: <TESTSET> STOP
11304 11:58:02.534889 Closing test_set Buffer-ioctls
11305 11:58:02.543493 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11306 11:58:02.544414 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11307 11:58:02.544840 Starting test_set Streaming-ioctls_Test-input-0
11308 11:58:02.546794 test read/write: OK (Not Supported)
11309 11:58:02.571351 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11310 11:58:02.572133 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11312 11:58:02.577838 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2798): node->streamon(q.g_type())
11313 11:58:02.588046 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2845): testBlockingDQBuf(node, q)
11314 11:58:02.597473 test blocking wait: FAIL
11315 11:58:02.624007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11316 11:58:02.624821 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11318 11:58:02.633820 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11319 11:58:02.634351 test MMAP (select): FAIL
11320 11:58:02.657485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11321 11:58:02.658347 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11323 11:58:02.664260 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11324 11:58:02.667302 test MMAP (epoll): FAIL
11325 11:58:02.691802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11326 11:58:02.692562 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11328 11:58:02.701839 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11329 11:58:02.707895 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11330 11:58:02.712881 test USERPTR (select): FAIL
11331 11:58:02.742982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11332 11:58:02.743540 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11334 11:58:02.749260 test DMABUF: Cannot test, specify --expbuf-device
11335 11:58:02.760049
11336 11:58:02.778437 Total for mtk-vcodec-enc device /dev/video0: 50, Succeeded: 44, Failed: 6, Warnings: 0
11337 11:58:02.781386 <LAVA_TEST_RUNNER EXIT>
11338 11:58:02.782098 ok: lava_test_shell seems to have completed
11339 11:58:02.782502 Marking unfinished test run as failed
11341 11:58:02.787062 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video0-open:
result: pass
set: Allow-for-multiple-opens
11342 11:58:02.787499 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11343 11:58:02.787821 end: 3 lava-test-retry (duration 00:00:03) [common]
11344 11:58:02.788144 start: 4 finalize (timeout 00:08:03) [common]
11345 11:58:02.788542 start: 4.1 power-off (timeout 00:00:30) [common]
11346 11:58:02.789597 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11347 11:58:02.880271 >> Command sent successfully.
11348 11:58:02.882755 Returned 0 in 0 seconds
11349 11:58:02.983553 end: 4.1 power-off (duration 00:00:00) [common]
11351 11:58:02.985195 start: 4.2 read-feedback (timeout 00:08:03) [common]
11352 11:58:02.986429 Listened to connection for namespace 'common' for up to 1s
11353 11:58:03.986981 Finalising connection for namespace 'common'
11354 11:58:03.987296 Disconnecting from shell: Finalise
11355 11:58:03.987465 / #
11356 11:58:04.088158 end: 4.2 read-feedback (duration 00:00:01) [common]
11357 11:58:04.088787 end: 4 finalize (duration 00:00:01) [common]
11358 11:58:04.089302 Cleaning after the job
11359 11:58:04.089812 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/ramdisk
11360 11:58:04.114232 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/kernel
11361 11:58:04.134903 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/dtb
11362 11:58:04.135229 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12066541/tftp-deploy-wp7f11ac/modules
11363 11:58:04.145666 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12066541
11364 11:58:04.214365 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12066541
11365 11:58:04.214543 Job finished correctly