Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 18
- Kernel Errors: 27
- Errors: 2
1 22:59:42.763680 lava-dispatcher, installed at version: 2023.10
2 22:59:42.763886 start: 0 validate
3 22:59:42.764011 Start time: 2023-12-03 22:59:42.764004+00:00 (UTC)
4 22:59:42.764118 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:59:42.764250 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 22:59:43.037820 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:59:43.038554 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:59:43.308722 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:59:43.309544 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:59:43.579697 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:59:43.580454 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:59:43.849554 validate duration: 1.09
14 22:59:43.849968 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:59:43.850081 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:59:43.850184 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:59:43.850325 Not decompressing ramdisk as can be used compressed.
18 22:59:43.850425 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/arm64/rootfs.cpio.gz
19 22:59:43.850502 saving as /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/ramdisk/rootfs.cpio.gz
20 22:59:43.850605 total size: 8181372 (7 MB)
21 22:59:43.852145 progress 0 % (0 MB)
22 22:59:43.854673 progress 5 % (0 MB)
23 22:59:43.856803 progress 10 % (0 MB)
24 22:59:43.859162 progress 15 % (1 MB)
25 22:59:43.861343 progress 20 % (1 MB)
26 22:59:43.863668 progress 25 % (1 MB)
27 22:59:43.865795 progress 30 % (2 MB)
28 22:59:43.868084 progress 35 % (2 MB)
29 22:59:43.870362 progress 40 % (3 MB)
30 22:59:43.872768 progress 45 % (3 MB)
31 22:59:43.874913 progress 50 % (3 MB)
32 22:59:43.877144 progress 55 % (4 MB)
33 22:59:43.879249 progress 60 % (4 MB)
34 22:59:43.881483 progress 65 % (5 MB)
35 22:59:43.883584 progress 70 % (5 MB)
36 22:59:43.885854 progress 75 % (5 MB)
37 22:59:43.887921 progress 80 % (6 MB)
38 22:59:43.890191 progress 85 % (6 MB)
39 22:59:43.892361 progress 90 % (7 MB)
40 22:59:43.894627 progress 95 % (7 MB)
41 22:59:43.896714 progress 100 % (7 MB)
42 22:59:43.896922 7 MB downloaded in 0.05 s (168.45 MB/s)
43 22:59:43.897093 end: 1.1.1 http-download (duration 00:00:00) [common]
45 22:59:43.897365 end: 1.1 download-retry (duration 00:00:00) [common]
46 22:59:43.897468 start: 1.2 download-retry (timeout 00:10:00) [common]
47 22:59:43.897597 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 22:59:43.897744 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:59:43.897847 saving as /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/kernel/Image
50 22:59:43.897944 total size: 49172992 (46 MB)
51 22:59:43.898043 No compression specified
52 22:59:43.899695 progress 0 % (0 MB)
53 22:59:43.912427 progress 5 % (2 MB)
54 22:59:43.925206 progress 10 % (4 MB)
55 22:59:43.938322 progress 15 % (7 MB)
56 22:59:43.951117 progress 20 % (9 MB)
57 22:59:43.963822 progress 25 % (11 MB)
58 22:59:43.976637 progress 30 % (14 MB)
59 22:59:43.989454 progress 35 % (16 MB)
60 22:59:44.002506 progress 40 % (18 MB)
61 22:59:44.015484 progress 45 % (21 MB)
62 22:59:44.028874 progress 50 % (23 MB)
63 22:59:44.041912 progress 55 % (25 MB)
64 22:59:44.054824 progress 60 % (28 MB)
65 22:59:44.067722 progress 65 % (30 MB)
66 22:59:44.080540 progress 70 % (32 MB)
67 22:59:44.093495 progress 75 % (35 MB)
68 22:59:44.106275 progress 80 % (37 MB)
69 22:59:44.119139 progress 85 % (39 MB)
70 22:59:44.131824 progress 90 % (42 MB)
71 22:59:44.144397 progress 95 % (44 MB)
72 22:59:44.156842 progress 100 % (46 MB)
73 22:59:44.157058 46 MB downloaded in 0.26 s (180.98 MB/s)
74 22:59:44.157265 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:59:44.157525 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:59:44.157703 start: 1.3 download-retry (timeout 00:10:00) [common]
78 22:59:44.157807 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 22:59:44.157963 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:59:44.158063 saving as /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/dtb/mt8192-asurada-spherion-r0.dtb
81 22:59:44.158161 total size: 47278 (0 MB)
82 22:59:44.158261 No compression specified
83 22:59:44.159940 progress 69 % (0 MB)
84 22:59:44.160250 progress 100 % (0 MB)
85 22:59:44.160446 0 MB downloaded in 0.00 s (19.75 MB/s)
86 22:59:44.160624 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:59:44.160912 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:59:44.161016 start: 1.4 download-retry (timeout 00:10:00) [common]
90 22:59:44.161115 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 22:59:44.161274 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:59:44.161371 saving as /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/modules/modules.tar
93 22:59:44.161467 total size: 8614132 (8 MB)
94 22:59:44.161566 Using unxz to decompress xz
95 22:59:44.166446 progress 0 % (0 MB)
96 22:59:44.187839 progress 5 % (0 MB)
97 22:59:44.211610 progress 10 % (0 MB)
98 22:59:44.234963 progress 15 % (1 MB)
99 22:59:44.258424 progress 20 % (1 MB)
100 22:59:44.282525 progress 25 % (2 MB)
101 22:59:44.307920 progress 30 % (2 MB)
102 22:59:44.333592 progress 35 % (2 MB)
103 22:59:44.356709 progress 40 % (3 MB)
104 22:59:44.381151 progress 45 % (3 MB)
105 22:59:44.406430 progress 50 % (4 MB)
106 22:59:44.430439 progress 55 % (4 MB)
107 22:59:44.454817 progress 60 % (4 MB)
108 22:59:44.480023 progress 65 % (5 MB)
109 22:59:44.507041 progress 70 % (5 MB)
110 22:59:44.530400 progress 75 % (6 MB)
111 22:59:44.556833 progress 80 % (6 MB)
112 22:59:44.581987 progress 85 % (7 MB)
113 22:59:44.606478 progress 90 % (7 MB)
114 22:59:44.635829 progress 95 % (7 MB)
115 22:59:44.663517 progress 100 % (8 MB)
116 22:59:44.669685 8 MB downloaded in 0.51 s (16.16 MB/s)
117 22:59:44.669947 end: 1.4.1 http-download (duration 00:00:01) [common]
119 22:59:44.670230 end: 1.4 download-retry (duration 00:00:01) [common]
120 22:59:44.670336 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 22:59:44.670449 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 22:59:44.670546 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:59:44.670650 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 22:59:44.670900 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb
125 22:59:44.671073 makedir: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin
126 22:59:44.671215 makedir: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/tests
127 22:59:44.671351 makedir: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/results
128 22:59:44.671481 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-add-keys
129 22:59:44.671646 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-add-sources
130 22:59:44.671819 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-background-process-start
131 22:59:44.671992 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-background-process-stop
132 22:59:44.672162 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-common-functions
133 22:59:44.672330 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-echo-ipv4
134 22:59:44.672497 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-install-packages
135 22:59:44.672665 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-installed-packages
136 22:59:44.672827 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-os-build
137 22:59:44.672967 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-probe-channel
138 22:59:44.673107 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-probe-ip
139 22:59:44.673256 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-target-ip
140 22:59:44.673424 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-target-mac
141 22:59:44.673593 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-target-storage
142 22:59:44.673797 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-case
143 22:59:44.673964 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-event
144 22:59:44.674128 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-feedback
145 22:59:44.674275 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-raise
146 22:59:44.674445 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-reference
147 22:59:44.674612 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-runner
148 22:59:44.674783 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-set
149 22:59:44.674952 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-test-shell
150 22:59:44.675124 Updating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-install-packages (oe)
151 22:59:44.675318 Updating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/bin/lava-installed-packages (oe)
152 22:59:44.675479 Creating /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/environment
153 22:59:44.675613 LAVA metadata
154 22:59:44.675717 - LAVA_JOB_ID=12172435
155 22:59:44.675818 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:59:44.675968 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 22:59:44.676065 skipped lava-vland-overlay
158 22:59:44.676190 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:59:44.676314 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 22:59:44.676407 skipped lava-multinode-overlay
161 22:59:44.676524 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:59:44.676644 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 22:59:44.676756 Loading test definitions
164 22:59:44.676890 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 22:59:44.677000 Using /lava-12172435 at stage 0
166 22:59:44.677436 uuid=12172435_1.5.2.3.1 testdef=None
167 22:59:44.677555 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:59:44.677732 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 22:59:44.678490 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:59:44.678846 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 22:59:44.679772 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:59:44.680140 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 22:59:44.681041 runner path: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/0/tests/0_dmesg test_uuid 12172435_1.5.2.3.1
176 22:59:44.681238 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:59:44.681634 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 22:59:44.681742 Using /lava-12172435 at stage 1
180 22:59:44.682068 uuid=12172435_1.5.2.3.5 testdef=None
181 22:59:44.682162 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 22:59:44.682261 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 22:59:44.682742 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 22:59:44.682985 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 22:59:44.684449 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 22:59:44.684724 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 22:59:44.685646 runner path: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/1/tests/1_bootrr test_uuid 12172435_1.5.2.3.5
190 22:59:44.685821 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 22:59:44.686136 Creating lava-test-runner.conf files
193 22:59:44.686217 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/0 for stage 0
194 22:59:44.686333 - 0_dmesg
195 22:59:44.686451 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172435/lava-overlay-i5f6nzjb/lava-12172435/1 for stage 1
196 22:59:44.686560 - 1_bootrr
197 22:59:44.686694 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 22:59:44.686818 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 22:59:44.695377 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 22:59:44.695490 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 22:59:44.695588 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 22:59:44.695687 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 22:59:44.695788 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 22:59:44.942945 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 22:59:44.943342 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 22:59:44.943481 extracting modules file /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172435/extract-overlay-ramdisk-tru6b8yq/ramdisk
207 22:59:45.163187 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 22:59:45.163366 start: 1.5.5 apply-overlay-tftp (timeout 00:09:59) [common]
209 22:59:45.163486 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172435/compress-overlay-6liwabvb/overlay-1.5.2.4.tar.gz to ramdisk
210 22:59:45.163565 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172435/compress-overlay-6liwabvb/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172435/extract-overlay-ramdisk-tru6b8yq/ramdisk
211 22:59:45.171877 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 22:59:45.172022 start: 1.5.6 configure-preseed-file (timeout 00:09:59) [common]
213 22:59:45.172136 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 22:59:45.172241 start: 1.5.7 compress-ramdisk (timeout 00:09:59) [common]
215 22:59:45.172331 Building ramdisk /var/lib/lava/dispatcher/tmp/12172435/extract-overlay-ramdisk-tru6b8yq/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172435/extract-overlay-ramdisk-tru6b8yq/ramdisk
216 22:59:45.578357 >> 145329 blocks
217 22:59:47.820858 rename /var/lib/lava/dispatcher/tmp/12172435/extract-overlay-ramdisk-tru6b8yq/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/ramdisk/ramdisk.cpio.gz
218 22:59:47.821342 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 22:59:47.821536 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 22:59:47.821738 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 22:59:47.821917 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/kernel/Image'
222 22:59:59.716371 Returned 0 in 11 seconds
223 22:59:59.817515 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/kernel/image.itb
224 23:00:00.243295 output: FIT description: Kernel Image image with one or more FDT blobs
225 23:00:00.243677 output: Created: Sun Dec 3 23:00:00 2023
226 23:00:00.243779 output: Image 0 (kernel-1)
227 23:00:00.243864 output: Description:
228 23:00:00.243948 output: Created: Sun Dec 3 23:00:00 2023
229 23:00:00.244029 output: Type: Kernel Image
230 23:00:00.244128 output: Compression: lzma compressed
231 23:00:00.244225 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
232 23:00:00.244323 output: Architecture: AArch64
233 23:00:00.244418 output: OS: Linux
234 23:00:00.244513 output: Load Address: 0x00000000
235 23:00:00.244612 output: Entry Point: 0x00000000
236 23:00:00.244706 output: Hash algo: crc32
237 23:00:00.244801 output: Hash value: c85ea8f0
238 23:00:00.244897 output: Image 1 (fdt-1)
239 23:00:00.244992 output: Description: mt8192-asurada-spherion-r0
240 23:00:00.245083 output: Created: Sun Dec 3 23:00:00 2023
241 23:00:00.245174 output: Type: Flat Device Tree
242 23:00:00.245264 output: Compression: uncompressed
243 23:00:00.245354 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
244 23:00:00.245444 output: Architecture: AArch64
245 23:00:00.245533 output: Hash algo: crc32
246 23:00:00.245665 output: Hash value: cc4352de
247 23:00:00.245755 output: Image 2 (ramdisk-1)
248 23:00:00.245845 output: Description: unavailable
249 23:00:00.245934 output: Created: Sun Dec 3 23:00:00 2023
250 23:00:00.246024 output: Type: RAMDisk Image
251 23:00:00.246113 output: Compression: Unknown Compression
252 23:00:00.246203 output: Data Size: 21402291 Bytes = 20900.67 KiB = 20.41 MiB
253 23:00:00.246292 output: Architecture: AArch64
254 23:00:00.246382 output: OS: Linux
255 23:00:00.246470 output: Load Address: unavailable
256 23:00:00.246560 output: Entry Point: unavailable
257 23:00:00.246649 output: Hash algo: crc32
258 23:00:00.246737 output: Hash value: a2e8b363
259 23:00:00.246826 output: Default Configuration: 'conf-1'
260 23:00:00.246915 output: Configuration 0 (conf-1)
261 23:00:00.247003 output: Description: mt8192-asurada-spherion-r0
262 23:00:00.247093 output: Kernel: kernel-1
263 23:00:00.247181 output: Init Ramdisk: ramdisk-1
264 23:00:00.247271 output: FDT: fdt-1
265 23:00:00.247359 output: Loadables: kernel-1
266 23:00:00.247447 output:
267 23:00:00.247690 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 23:00:00.247827 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 23:00:00.247967 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 23:00:00.248102 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:44) [common]
271 23:00:00.248219 No LXC device requested
272 23:00:00.248341 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 23:00:00.248466 start: 1.7 deploy-device-env (timeout 00:09:44) [common]
274 23:00:00.248582 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 23:00:00.248691 Checking files for TFTP limit of 4294967296 bytes.
276 23:00:00.249345 end: 1 tftp-deploy (duration 00:00:16) [common]
277 23:00:00.249484 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 23:00:00.249656 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 23:00:00.249823 substitutions:
280 23:00:00.249895 - {DTB}: 12172435/tftp-deploy-us5g40g6/dtb/mt8192-asurada-spherion-r0.dtb
281 23:00:00.249977 - {INITRD}: 12172435/tftp-deploy-us5g40g6/ramdisk/ramdisk.cpio.gz
282 23:00:00.250056 - {KERNEL}: 12172435/tftp-deploy-us5g40g6/kernel/Image
283 23:00:00.250133 - {LAVA_MAC}: None
284 23:00:00.250210 - {PRESEED_CONFIG}: None
285 23:00:00.250304 - {PRESEED_LOCAL}: None
286 23:00:00.250397 - {RAMDISK}: 12172435/tftp-deploy-us5g40g6/ramdisk/ramdisk.cpio.gz
287 23:00:00.250490 - {ROOT_PART}: None
288 23:00:00.250583 - {ROOT}: None
289 23:00:00.250675 - {SERVER_IP}: 192.168.201.1
290 23:00:00.250767 - {TEE}: None
291 23:00:00.250859 Parsed boot commands:
292 23:00:00.250948 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 23:00:00.251180 Parsed boot commands: tftpboot 192.168.201.1 12172435/tftp-deploy-us5g40g6/kernel/image.itb 12172435/tftp-deploy-us5g40g6/kernel/cmdline
294 23:00:00.251306 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 23:00:00.251436 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 23:00:00.251570 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 23:00:00.251696 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 23:00:00.251804 Not connected, no need to disconnect.
299 23:00:00.251918 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 23:00:00.252043 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 23:00:00.252144 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
302 23:00:00.256295 Setting prompt string to ['lava-test: # ']
303 23:00:00.256662 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 23:00:00.256781 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 23:00:00.256893 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 23:00:00.257167 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 23:00:00.257400 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
308 23:00:05.407328 >> Command sent successfully.
309 23:00:05.413275 Returned 0 in 5 seconds
310 23:00:05.514091 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 23:00:05.515819 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 23:00:05.516502 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 23:00:05.517103 Setting prompt string to 'Starting depthcharge on Spherion...'
315 23:00:05.517573 Changing prompt to 'Starting depthcharge on Spherion...'
316 23:00:05.518113 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 23:00:05.519612 [Enter `^Ec?' for help]
318 23:00:05.687150
319 23:00:05.687707
320 23:00:05.688173 F0: 102B 0000
321 23:00:05.688612
322 23:00:05.689033 F3: 1001 0000 [0200]
323 23:00:05.689439
324 23:00:05.690522 F3: 1001 0000
325 23:00:05.690956
326 23:00:05.691407 F7: 102D 0000
327 23:00:05.691831
328 23:00:05.692242 F1: 0000 0000
329 23:00:05.692644
330 23:00:05.694479 V0: 0000 0000 [0001]
331 23:00:05.695054
332 23:00:05.695498 00: 0007 8000
333 23:00:05.696036
334 23:00:05.696448 01: 0000 0000
335 23:00:05.698250
336 23:00:05.698682 BP: 0C00 0209 [0000]
337 23:00:05.699123
338 23:00:05.699543 G0: 1182 0000
339 23:00:05.699951
340 23:00:05.702209 EC: 0000 0021 [4000]
341 23:00:05.702640
342 23:00:05.703081 S7: 0000 0000 [0000]
343 23:00:05.703496
344 23:00:05.705982 CC: 0000 0000 [0001]
345 23:00:05.706417
346 23:00:05.706860 T0: 0000 0040 [010F]
347 23:00:05.707401
348 23:00:05.709157 Jump to BL
349 23:00:05.709625
350 23:00:05.733787
351 23:00:05.734335
352 23:00:05.734788
353 23:00:05.741152 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 23:00:05.745144 ARM64: Exception handlers installed.
355 23:00:05.748370 ARM64: Testing exception
356 23:00:05.752432 ARM64: Done test exception
357 23:00:05.759151 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 23:00:05.766143 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 23:00:05.773164 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 23:00:05.784523 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 23:00:05.790530 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 23:00:05.801068 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 23:00:05.811773 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 23:00:05.818295 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 23:00:05.836294 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 23:00:05.839853 WDT: Last reset was cold boot
367 23:00:05.842994 SPI1(PAD0) initialized at 2873684 Hz
368 23:00:05.846856 SPI5(PAD0) initialized at 992727 Hz
369 23:00:05.849822 VBOOT: Loading verstage.
370 23:00:05.856443 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 23:00:05.859378 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 23:00:05.862956 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 23:00:05.866336 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 23:00:05.873744 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 23:00:05.880362 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 23:00:05.891550 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 23:00:05.892115
378 23:00:05.892620
379 23:00:05.902037 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 23:00:05.905323 ARM64: Exception handlers installed.
381 23:00:05.905843 ARM64: Testing exception
382 23:00:05.908435 ARM64: Done test exception
383 23:00:05.912001 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 23:00:05.918491 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 23:00:05.932425 Probing TPM: . done!
386 23:00:05.933004 TPM ready after 0 ms
387 23:00:05.940421 Connected to device vid:did:rid of 1ae0:0028:00
388 23:00:05.947754 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
389 23:00:06.006094 Initialized TPM device CR50 revision 0
390 23:00:06.017448 tlcl_send_startup: Startup return code is 0
391 23:00:06.017956 TPM: setup succeeded
392 23:00:06.029610 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 23:00:06.037916 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 23:00:06.049958 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 23:00:06.059994 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 23:00:06.064053 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 23:00:06.067996 in-header: 03 07 00 00 08 00 00 00
398 23:00:06.071150 in-data: aa e4 47 04 13 02 00 00
399 23:00:06.071634 Chrome EC: UHEPI supported
400 23:00:06.078289 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 23:00:06.082543 in-header: 03 95 00 00 08 00 00 00
402 23:00:06.086287 in-data: 18 20 20 08 00 00 00 00
403 23:00:06.086871 Phase 1
404 23:00:06.090266 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 23:00:06.096885 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 23:00:06.104836 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 23:00:06.105366 Recovery requested (1009000e)
408 23:00:06.117670 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 23:00:06.121071 tlcl_extend: response is 0
410 23:00:06.130011 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 23:00:06.135192 tlcl_extend: response is 0
412 23:00:06.142913 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 23:00:06.161744 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
414 23:00:06.168895 BS: bootblock times (exec / console): total (unknown) / 149 ms
415 23:00:06.169528
416 23:00:06.169964
417 23:00:06.178795 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 23:00:06.182184 ARM64: Exception handlers installed.
419 23:00:06.185400 ARM64: Testing exception
420 23:00:06.185950 ARM64: Done test exception
421 23:00:06.207793 pmic_efuse_setting: Set efuses in 11 msecs
422 23:00:06.210919 pmwrap_interface_init: Select PMIF_VLD_RDY
423 23:00:06.217668 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 23:00:06.221247 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 23:00:06.227893 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 23:00:06.231581 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 23:00:06.235833 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 23:00:06.242135 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 23:00:06.246747 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 23:00:06.250314 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 23:00:06.254168 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 23:00:06.261903 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 23:00:06.265546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 23:00:06.268660 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 23:00:06.272297 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 23:00:06.279895 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 23:00:06.287296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 23:00:06.291021 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 23:00:06.298221 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 23:00:06.301964 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 23:00:06.309630 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 23:00:06.313420 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 23:00:06.320799 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 23:00:06.324863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 23:00:06.332068 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 23:00:06.335505 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 23:00:06.343236 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 23:00:06.347200 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 23:00:06.350487 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 23:00:06.357753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 23:00:06.361095 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 23:00:06.365086 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 23:00:06.372357 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 23:00:06.376148 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 23:00:06.380017 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 23:00:06.387361 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 23:00:06.390847 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 23:00:06.398291 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 23:00:06.402433 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 23:00:06.405755 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 23:00:06.409324 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 23:00:06.416830 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 23:00:06.420280 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 23:00:06.424207 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 23:00:06.427662 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 23:00:06.431999 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 23:00:06.439243 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 23:00:06.442981 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 23:00:06.446550 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 23:00:06.450148 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 23:00:06.453961 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 23:00:06.457238 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 23:00:06.461704 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 23:00:06.469131 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 23:00:06.479468 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 23:00:06.483770 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 23:00:06.491431 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 23:00:06.498895 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 23:00:06.506107 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 23:00:06.510007 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 23:00:06.513349 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 23:00:06.521160 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
483 23:00:06.524318 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 23:00:06.532400 [RTC]rtc_osc_init,62: osc32con val = 0xde70
485 23:00:06.535745 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 23:00:06.545028 [RTC]rtc_get_frequency_meter,154: input=15, output=759
487 23:00:06.555168 [RTC]rtc_get_frequency_meter,154: input=23, output=942
488 23:00:06.563832 [RTC]rtc_get_frequency_meter,154: input=19, output=852
489 23:00:06.574075 [RTC]rtc_get_frequency_meter,154: input=17, output=804
490 23:00:06.583118 [RTC]rtc_get_frequency_meter,154: input=16, output=782
491 23:00:06.592487 [RTC]rtc_get_frequency_meter,154: input=16, output=781
492 23:00:06.602524 [RTC]rtc_get_frequency_meter,154: input=17, output=805
493 23:00:06.606636 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
494 23:00:06.609951 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
495 23:00:06.613672 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 23:00:06.621288 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 23:00:06.625071 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 23:00:06.628981 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 23:00:06.632681 ADC[4]: Raw value=906203 ID=7
500 23:00:06.633147 ADC[3]: Raw value=213441 ID=1
501 23:00:06.636448 RAM Code: 0x71
502 23:00:06.640352 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 23:00:06.644062 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 23:00:06.651612 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 23:00:06.659168 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 23:00:06.662862 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 23:00:06.666834 in-header: 03 07 00 00 08 00 00 00
508 23:00:06.670344 in-data: aa e4 47 04 13 02 00 00
509 23:00:06.673952 Chrome EC: UHEPI supported
510 23:00:06.677338 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 23:00:06.681675 in-header: 03 95 00 00 08 00 00 00
512 23:00:06.685159 in-data: 18 20 20 08 00 00 00 00
513 23:00:06.688601 MRC: failed to locate region type 0.
514 23:00:06.696329 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 23:00:06.700028 DRAM-K: Running full calibration
516 23:00:06.703429 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 23:00:06.707611 header.status = 0x0
518 23:00:06.711549 header.version = 0x6 (expected: 0x6)
519 23:00:06.714458 header.size = 0xd00 (expected: 0xd00)
520 23:00:06.714881 header.flags = 0x0
521 23:00:06.721436 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 23:00:06.739887 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
523 23:00:06.747060 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 23:00:06.750322 dram_init: ddr_geometry: 2
525 23:00:06.750789 [EMI] MDL number = 2
526 23:00:06.753693 [EMI] Get MDL freq = 0
527 23:00:06.754157 dram_init: ddr_type: 0
528 23:00:06.757547 is_discrete_lpddr4: 1
529 23:00:06.761622 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 23:00:06.762139
531 23:00:06.762475
532 23:00:06.762783 [Bian_co] ETT version 0.0.0.1
533 23:00:06.768941 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 23:00:06.769502
535 23:00:06.772497 dramc_set_vcore_voltage set vcore to 650000
536 23:00:06.772989 Read voltage for 800, 4
537 23:00:06.775991 Vio18 = 0
538 23:00:06.776546 Vcore = 650000
539 23:00:06.776918 Vdram = 0
540 23:00:06.779541 Vddq = 0
541 23:00:06.780004 Vmddr = 0
542 23:00:06.780372 dram_init: config_dvfs: 1
543 23:00:06.787001 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 23:00:06.791064 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 23:00:06.794797 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
546 23:00:06.798628 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
547 23:00:06.802163 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
548 23:00:06.805273 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
549 23:00:06.808653 MEM_TYPE=3, freq_sel=18
550 23:00:06.811984 sv_algorithm_assistance_LP4_1600
551 23:00:06.815345 ============ PULL DRAM RESETB DOWN ============
552 23:00:06.822873 ========== PULL DRAM RESETB DOWN end =========
553 23:00:06.825990 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 23:00:06.830162 ===================================
555 23:00:06.830591 LPDDR4 DRAM CONFIGURATION
556 23:00:06.833442 ===================================
557 23:00:06.837714 EX_ROW_EN[0] = 0x0
558 23:00:06.838241 EX_ROW_EN[1] = 0x0
559 23:00:06.841048 LP4Y_EN = 0x0
560 23:00:06.841471 WORK_FSP = 0x0
561 23:00:06.844833 WL = 0x2
562 23:00:06.845367 RL = 0x2
563 23:00:06.848327 BL = 0x2
564 23:00:06.848843 RPST = 0x0
565 23:00:06.851747 RD_PRE = 0x0
566 23:00:06.852283 WR_PRE = 0x1
567 23:00:06.855231 WR_PST = 0x0
568 23:00:06.855751 DBI_WR = 0x0
569 23:00:06.858592 DBI_RD = 0x0
570 23:00:06.859016 OTF = 0x1
571 23:00:06.861690 ===================================
572 23:00:06.865218 ===================================
573 23:00:06.865801 ANA top config
574 23:00:06.868633 ===================================
575 23:00:06.872419 DLL_ASYNC_EN = 0
576 23:00:06.876644 ALL_SLAVE_EN = 1
577 23:00:06.877178 NEW_RANK_MODE = 1
578 23:00:06.879464 DLL_IDLE_MODE = 1
579 23:00:06.883278 LP45_APHY_COMB_EN = 1
580 23:00:06.886573 TX_ODT_DIS = 1
581 23:00:06.887093 NEW_8X_MODE = 1
582 23:00:06.890107 ===================================
583 23:00:06.893284 ===================================
584 23:00:06.897019 data_rate = 1600
585 23:00:06.900214 CKR = 1
586 23:00:06.903669 DQ_P2S_RATIO = 8
587 23:00:06.906962 ===================================
588 23:00:06.909858 CA_P2S_RATIO = 8
589 23:00:06.913442 DQ_CA_OPEN = 0
590 23:00:06.914129 DQ_SEMI_OPEN = 0
591 23:00:06.917092 CA_SEMI_OPEN = 0
592 23:00:06.920245 CA_FULL_RATE = 0
593 23:00:06.923269 DQ_CKDIV4_EN = 1
594 23:00:06.926612 CA_CKDIV4_EN = 1
595 23:00:06.927158 CA_PREDIV_EN = 0
596 23:00:06.930544 PH8_DLY = 0
597 23:00:06.933351 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 23:00:06.937059 DQ_AAMCK_DIV = 4
599 23:00:06.940441 CA_AAMCK_DIV = 4
600 23:00:06.943705 CA_ADMCK_DIV = 4
601 23:00:06.944270 DQ_TRACK_CA_EN = 0
602 23:00:06.946983 CA_PICK = 800
603 23:00:06.950587 CA_MCKIO = 800
604 23:00:06.953963 MCKIO_SEMI = 0
605 23:00:06.957764 PLL_FREQ = 3068
606 23:00:06.958318 DQ_UI_PI_RATIO = 32
607 23:00:06.961747 CA_UI_PI_RATIO = 0
608 23:00:06.965641 ===================================
609 23:00:06.969127 ===================================
610 23:00:06.973305 memory_type:LPDDR4
611 23:00:06.973838 GP_NUM : 10
612 23:00:06.977761 SRAM_EN : 1
613 23:00:06.978318 MD32_EN : 0
614 23:00:06.980839 ===================================
615 23:00:06.984807 [ANA_INIT] >>>>>>>>>>>>>>
616 23:00:06.985360 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 23:00:06.988574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 23:00:06.992029 ===================================
619 23:00:06.995625 data_rate = 1600,PCW = 0X7600
620 23:00:06.998442 ===================================
621 23:00:07.001941 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 23:00:07.008402 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 23:00:07.011718 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 23:00:07.018418 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 23:00:07.021444 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 23:00:07.025214 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 23:00:07.025877 [ANA_INIT] flow start
628 23:00:07.028228 [ANA_INIT] PLL >>>>>>>>
629 23:00:07.031529 [ANA_INIT] PLL <<<<<<<<
630 23:00:07.034810 [ANA_INIT] MIDPI >>>>>>>>
631 23:00:07.035237 [ANA_INIT] MIDPI <<<<<<<<
632 23:00:07.038149 [ANA_INIT] DLL >>>>>>>>
633 23:00:07.038615 [ANA_INIT] flow end
634 23:00:07.044850 ============ LP4 DIFF to SE enter ============
635 23:00:07.048365 ============ LP4 DIFF to SE exit ============
636 23:00:07.052070 [ANA_INIT] <<<<<<<<<<<<<
637 23:00:07.054677 [Flow] Enable top DCM control >>>>>
638 23:00:07.058218 [Flow] Enable top DCM control <<<<<
639 23:00:07.058837 Enable DLL master slave shuffle
640 23:00:07.064747 ==============================================================
641 23:00:07.068140 Gating Mode config
642 23:00:07.071300 ==============================================================
643 23:00:07.074536 Config description:
644 23:00:07.085270 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 23:00:07.091887 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 23:00:07.095239 SELPH_MODE 0: By rank 1: By Phase
647 23:00:07.101053 ==============================================================
648 23:00:07.104548 GAT_TRACK_EN = 1
649 23:00:07.108090 RX_GATING_MODE = 2
650 23:00:07.111139 RX_GATING_TRACK_MODE = 2
651 23:00:07.114267 SELPH_MODE = 1
652 23:00:07.114343 PICG_EARLY_EN = 1
653 23:00:07.118279 VALID_LAT_VALUE = 1
654 23:00:07.124750 ==============================================================
655 23:00:07.128040 Enter into Gating configuration >>>>
656 23:00:07.131777 Exit from Gating configuration <<<<
657 23:00:07.134932 Enter into DVFS_PRE_config >>>>>
658 23:00:07.144570 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 23:00:07.148160 Exit from DVFS_PRE_config <<<<<
660 23:00:07.151420 Enter into PICG configuration >>>>
661 23:00:07.154398 Exit from PICG configuration <<<<
662 23:00:07.158314 [RX_INPUT] configuration >>>>>
663 23:00:07.161139 [RX_INPUT] configuration <<<<<
664 23:00:07.164371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 23:00:07.170978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 23:00:07.178012 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 23:00:07.184473 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 23:00:07.188116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 23:00:07.194463 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 23:00:07.197913 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 23:00:07.204724 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 23:00:07.208042 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 23:00:07.211215 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 23:00:07.214471 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 23:00:07.221283 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 23:00:07.224698 ===================================
677 23:00:07.224773 LPDDR4 DRAM CONFIGURATION
678 23:00:07.227737 ===================================
679 23:00:07.231732 EX_ROW_EN[0] = 0x0
680 23:00:07.234884 EX_ROW_EN[1] = 0x0
681 23:00:07.234967 LP4Y_EN = 0x0
682 23:00:07.238274 WORK_FSP = 0x0
683 23:00:07.238356 WL = 0x2
684 23:00:07.241247 RL = 0x2
685 23:00:07.241357 BL = 0x2
686 23:00:07.244801 RPST = 0x0
687 23:00:07.244901 RD_PRE = 0x0
688 23:00:07.247997 WR_PRE = 0x1
689 23:00:07.248101 WR_PST = 0x0
690 23:00:07.251279 DBI_WR = 0x0
691 23:00:07.251383 DBI_RD = 0x0
692 23:00:07.254368 OTF = 0x1
693 23:00:07.258173 ===================================
694 23:00:07.261085 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 23:00:07.264847 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 23:00:07.271515 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 23:00:07.274692 ===================================
698 23:00:07.274793 LPDDR4 DRAM CONFIGURATION
699 23:00:07.278002 ===================================
700 23:00:07.281153 EX_ROW_EN[0] = 0x10
701 23:00:07.281252 EX_ROW_EN[1] = 0x0
702 23:00:07.284743 LP4Y_EN = 0x0
703 23:00:07.284819 WORK_FSP = 0x0
704 23:00:07.287830 WL = 0x2
705 23:00:07.291334 RL = 0x2
706 23:00:07.291410 BL = 0x2
707 23:00:07.294839 RPST = 0x0
708 23:00:07.294937 RD_PRE = 0x0
709 23:00:07.298060 WR_PRE = 0x1
710 23:00:07.298156 WR_PST = 0x0
711 23:00:07.301544 DBI_WR = 0x0
712 23:00:07.301669 DBI_RD = 0x0
713 23:00:07.304946 OTF = 0x1
714 23:00:07.308034 ===================================
715 23:00:07.311409 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 23:00:07.316727 nWR fixed to 40
717 23:00:07.320414 [ModeRegInit_LP4] CH0 RK0
718 23:00:07.320514 [ModeRegInit_LP4] CH0 RK1
719 23:00:07.323806 [ModeRegInit_LP4] CH1 RK0
720 23:00:07.326592 [ModeRegInit_LP4] CH1 RK1
721 23:00:07.326663 match AC timing 13
722 23:00:07.333729 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 23:00:07.336946 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 23:00:07.340116 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 23:00:07.346912 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 23:00:07.350403 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 23:00:07.350478 [EMI DOE] emi_dcm 0
728 23:00:07.356572 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 23:00:07.356646 ==
730 23:00:07.360099 Dram Type= 6, Freq= 0, CH_0, rank 0
731 23:00:07.363415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 23:00:07.363539 ==
733 23:00:07.370469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 23:00:07.376753 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 23:00:07.384425 [CA 0] Center 36 (6~67) winsize 62
736 23:00:07.387585 [CA 1] Center 36 (6~67) winsize 62
737 23:00:07.390840 [CA 2] Center 34 (3~65) winsize 63
738 23:00:07.394445 [CA 3] Center 33 (3~64) winsize 62
739 23:00:07.397449 [CA 4] Center 33 (3~63) winsize 61
740 23:00:07.401163 [CA 5] Center 33 (3~63) winsize 61
741 23:00:07.401390
742 23:00:07.404344 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 23:00:07.404530
744 23:00:07.407652 [CATrainingPosCal] consider 1 rank data
745 23:00:07.410862 u2DelayCellTimex100 = 270/100 ps
746 23:00:07.414056 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
747 23:00:07.421331 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
748 23:00:07.424380 CA2 delay=34 (3~65),Diff = 1 PI (7 cell)
749 23:00:07.427844 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
750 23:00:07.431129 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
751 23:00:07.434609 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
752 23:00:07.435097
753 23:00:07.437898 CA PerBit enable=1, Macro0, CA PI delay=33
754 23:00:07.438319
755 23:00:07.441465 [CBTSetCACLKResult] CA Dly = 33
756 23:00:07.441937 CS Dly: 4 (0~35)
757 23:00:07.444579 ==
758 23:00:07.445179 Dram Type= 6, Freq= 0, CH_0, rank 1
759 23:00:07.451336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 23:00:07.451758 ==
761 23:00:07.454995 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 23:00:07.461852 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 23:00:07.470666 [CA 0] Center 36 (6~67) winsize 62
764 23:00:07.473911 [CA 1] Center 36 (6~67) winsize 62
765 23:00:07.477385 [CA 2] Center 34 (4~65) winsize 62
766 23:00:07.481070 [CA 3] Center 34 (3~65) winsize 63
767 23:00:07.483976 [CA 4] Center 33 (3~64) winsize 62
768 23:00:07.487974 [CA 5] Center 32 (2~63) winsize 62
769 23:00:07.488558
770 23:00:07.490938 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 23:00:07.491364
772 23:00:07.494254 [CATrainingPosCal] consider 2 rank data
773 23:00:07.497941 u2DelayCellTimex100 = 270/100 ps
774 23:00:07.500945 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
775 23:00:07.504239 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
776 23:00:07.507608 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 23:00:07.514299 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
778 23:00:07.517469 CA4 delay=33 (3~63),Diff = 0 PI (0 cell)
779 23:00:07.520747 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
780 23:00:07.521166
781 23:00:07.524356 CA PerBit enable=1, Macro0, CA PI delay=33
782 23:00:07.524873
783 23:00:07.527739 [CBTSetCACLKResult] CA Dly = 33
784 23:00:07.528288 CS Dly: 5 (0~37)
785 23:00:07.528623
786 23:00:07.530933 ----->DramcWriteLeveling(PI) begin...
787 23:00:07.531363 ==
788 23:00:07.535202 Dram Type= 6, Freq= 0, CH_0, rank 0
789 23:00:07.538376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 23:00:07.542132 ==
791 23:00:07.542556 Write leveling (Byte 0): 32 => 32
792 23:00:07.545888 Write leveling (Byte 1): 32 => 32
793 23:00:07.549466 DramcWriteLeveling(PI) end<-----
794 23:00:07.549934
795 23:00:07.550275 ==
796 23:00:07.553324 Dram Type= 6, Freq= 0, CH_0, rank 0
797 23:00:07.556913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 23:00:07.557368 ==
799 23:00:07.559862 [Gating] SW mode calibration
800 23:00:07.566826 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 23:00:07.573259 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 23:00:07.576852 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 23:00:07.580600 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 23:00:07.587345 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 23:00:07.590066 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:00:07.593471 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:00:07.596886 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:00:07.603670 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:00:07.607328 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:00:07.610656 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:00:07.617086 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:00:07.620867 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 23:00:07.623968 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 23:00:07.630594 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 23:00:07.634014 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 23:00:07.637423 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 23:00:07.644336 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 23:00:07.647335 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 23:00:07.650330 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
820 23:00:07.657191 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
821 23:00:07.660852 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
822 23:00:07.664111 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:00:07.667181 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:00:07.674121 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:00:07.677427 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:00:07.680421 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:00:07.687852 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
828 23:00:07.690503 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
829 23:00:07.694071 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 23:00:07.701090 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 23:00:07.704295 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 23:00:07.707384 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 23:00:07.714150 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 23:00:07.717432 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 23:00:07.720794 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
836 23:00:07.727613 0 10 8 | B1->B0 | 3232 2828 | 0 0 | (0 0) (1 0)
837 23:00:07.730750 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
838 23:00:07.734321 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 23:00:07.737429 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 23:00:07.744237 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 23:00:07.747455 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 23:00:07.751599 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 23:00:07.757710 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
844 23:00:07.761388 0 11 8 | B1->B0 | 2929 3f3f | 0 1 | (1 1) (0 0)
845 23:00:07.764505 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
846 23:00:07.770902 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 23:00:07.774157 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 23:00:07.777879 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 23:00:07.784735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 23:00:07.787900 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 23:00:07.791243 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
852 23:00:07.797544 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 23:00:07.801301 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 23:00:07.804217 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 23:00:07.810743 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 23:00:07.814540 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 23:00:07.818058 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 23:00:07.824093 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 23:00:07.827513 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 23:00:07.830972 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 23:00:07.834474 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 23:00:07.841424 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 23:00:07.844471 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 23:00:07.848301 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 23:00:07.854286 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 23:00:07.857856 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 23:00:07.860984 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 23:00:07.867842 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
869 23:00:07.868405 Total UI for P1: 0, mck2ui 16
870 23:00:07.874461 best dqsien dly found for B0: ( 0, 14, 4)
871 23:00:07.878135 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 23:00:07.880883 Total UI for P1: 0, mck2ui 16
873 23:00:07.884813 best dqsien dly found for B1: ( 0, 14, 10)
874 23:00:07.888664 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 23:00:07.891933 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
876 23:00:07.892354
877 23:00:07.895322 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 23:00:07.898690 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
879 23:00:07.902018 [Gating] SW calibration Done
880 23:00:07.902437 ==
881 23:00:07.905139 Dram Type= 6, Freq= 0, CH_0, rank 0
882 23:00:07.909084 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 23:00:07.909700 ==
884 23:00:07.911884 RX Vref Scan: 0
885 23:00:07.912387
886 23:00:07.912756 RX Vref 0 -> 0, step: 1
887 23:00:07.913100
888 23:00:07.915054 RX Delay -130 -> 252, step: 16
889 23:00:07.921730 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
890 23:00:07.925286 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
891 23:00:07.928422 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
892 23:00:07.931620 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
893 23:00:07.935190 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 23:00:07.938277 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 23:00:07.945334 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
896 23:00:07.948573 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
897 23:00:07.951730 iDelay=222, Bit 8, Center 69 (-34 ~ 173) 208
898 23:00:07.955593 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
899 23:00:07.958868 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
900 23:00:07.965793 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
901 23:00:07.968928 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
902 23:00:07.972491 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
903 23:00:07.975265 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
904 23:00:07.978873 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
905 23:00:07.982322 ==
906 23:00:07.985961 Dram Type= 6, Freq= 0, CH_0, rank 0
907 23:00:07.988638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 23:00:07.989215 ==
909 23:00:07.989647 DQS Delay:
910 23:00:07.992111 DQS0 = 0, DQS1 = 0
911 23:00:07.992577 DQM Delay:
912 23:00:07.995462 DQM0 = 92, DQM1 = 85
913 23:00:07.995928 DQ Delay:
914 23:00:07.998699 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
915 23:00:08.002063 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
916 23:00:08.005545 DQ8 =69, DQ9 =77, DQ10 =85, DQ11 =77
917 23:00:08.009016 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
918 23:00:08.009631
919 23:00:08.010158
920 23:00:08.010685 ==
921 23:00:08.012205 Dram Type= 6, Freq= 0, CH_0, rank 0
922 23:00:08.015540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 23:00:08.016149 ==
924 23:00:08.016692
925 23:00:08.017206
926 23:00:08.018941 TX Vref Scan disable
927 23:00:08.022117 == TX Byte 0 ==
928 23:00:08.025412 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 23:00:08.028985 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 23:00:08.031633 == TX Byte 1 ==
931 23:00:08.035053 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
932 23:00:08.038604 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
933 23:00:08.039149 ==
934 23:00:08.041637 Dram Type= 6, Freq= 0, CH_0, rank 0
935 23:00:08.045415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 23:00:08.048507 ==
937 23:00:08.059613 TX Vref=22, minBit 4, minWin=27, winSum=444
938 23:00:08.062673 TX Vref=24, minBit 0, minWin=28, winSum=453
939 23:00:08.066331 TX Vref=26, minBit 0, minWin=28, winSum=456
940 23:00:08.069406 TX Vref=28, minBit 11, minWin=27, winSum=456
941 23:00:08.072967 TX Vref=30, minBit 10, minWin=27, winSum=453
942 23:00:08.079346 TX Vref=32, minBit 12, minWin=27, winSum=455
943 23:00:08.082686 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 26
944 23:00:08.082932
945 23:00:08.086176 Final TX Range 1 Vref 26
946 23:00:08.086403
947 23:00:08.086579 ==
948 23:00:08.089323 Dram Type= 6, Freq= 0, CH_0, rank 0
949 23:00:08.092871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 23:00:08.093097 ==
951 23:00:08.096166
952 23:00:08.096390
953 23:00:08.096570 TX Vref Scan disable
954 23:00:08.099623 == TX Byte 0 ==
955 23:00:08.102564 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
956 23:00:08.106350 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
957 23:00:08.109559 == TX Byte 1 ==
958 23:00:08.112397 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
959 23:00:08.119198 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
960 23:00:08.119423
961 23:00:08.119598 [DATLAT]
962 23:00:08.119764 Freq=800, CH0 RK0
963 23:00:08.119927
964 23:00:08.122882 DATLAT Default: 0xa
965 23:00:08.123107 0, 0xFFFF, sum = 0
966 23:00:08.125925 1, 0xFFFF, sum = 0
967 23:00:08.126159 2, 0xFFFF, sum = 0
968 23:00:08.129178 3, 0xFFFF, sum = 0
969 23:00:08.132792 4, 0xFFFF, sum = 0
970 23:00:08.133022 5, 0xFFFF, sum = 0
971 23:00:08.136381 6, 0xFFFF, sum = 0
972 23:00:08.136609 7, 0xFFFF, sum = 0
973 23:00:08.139606 8, 0xFFFF, sum = 0
974 23:00:08.139834 9, 0x0, sum = 1
975 23:00:08.140025 10, 0x0, sum = 2
976 23:00:08.143148 11, 0x0, sum = 3
977 23:00:08.143376 12, 0x0, sum = 4
978 23:00:08.145824 best_step = 10
979 23:00:08.146049
980 23:00:08.146226 ==
981 23:00:08.149505 Dram Type= 6, Freq= 0, CH_0, rank 0
982 23:00:08.153050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 23:00:08.153276 ==
984 23:00:08.156375 RX Vref Scan: 1
985 23:00:08.156600
986 23:00:08.156779 Set Vref Range= 32 -> 127
987 23:00:08.159230
988 23:00:08.159454 RX Vref 32 -> 127, step: 1
989 23:00:08.159633
990 23:00:08.162786 RX Delay -79 -> 252, step: 8
991 23:00:08.163013
992 23:00:08.166236 Set Vref, RX VrefLevel [Byte0]: 32
993 23:00:08.169656 [Byte1]: 32
994 23:00:08.169883
995 23:00:08.172872 Set Vref, RX VrefLevel [Byte0]: 33
996 23:00:08.176115 [Byte1]: 33
997 23:00:08.179755
998 23:00:08.180075 Set Vref, RX VrefLevel [Byte0]: 34
999 23:00:08.182742 [Byte1]: 34
1000 23:00:08.187292
1001 23:00:08.187520 Set Vref, RX VrefLevel [Byte0]: 35
1002 23:00:08.190573 [Byte1]: 35
1003 23:00:08.194725
1004 23:00:08.194951 Set Vref, RX VrefLevel [Byte0]: 36
1005 23:00:08.198005 [Byte1]: 36
1006 23:00:08.202867
1007 23:00:08.203114 Set Vref, RX VrefLevel [Byte0]: 37
1008 23:00:08.205991 [Byte1]: 37
1009 23:00:08.210055
1010 23:00:08.210284 Set Vref, RX VrefLevel [Byte0]: 38
1011 23:00:08.213306 [Byte1]: 38
1012 23:00:08.217381
1013 23:00:08.217719 Set Vref, RX VrefLevel [Byte0]: 39
1014 23:00:08.220853 [Byte1]: 39
1015 23:00:08.225525
1016 23:00:08.225781 Set Vref, RX VrefLevel [Byte0]: 40
1017 23:00:08.228689 [Byte1]: 40
1018 23:00:08.233030
1019 23:00:08.233259 Set Vref, RX VrefLevel [Byte0]: 41
1020 23:00:08.235959 [Byte1]: 41
1021 23:00:08.239830
1022 23:00:08.240059 Set Vref, RX VrefLevel [Byte0]: 42
1023 23:00:08.243370 [Byte1]: 42
1024 23:00:08.247445
1025 23:00:08.247763 Set Vref, RX VrefLevel [Byte0]: 43
1026 23:00:08.250753 [Byte1]: 43
1027 23:00:08.255289
1028 23:00:08.255513 Set Vref, RX VrefLevel [Byte0]: 44
1029 23:00:08.258685 [Byte1]: 44
1030 23:00:08.262709
1031 23:00:08.262932 Set Vref, RX VrefLevel [Byte0]: 45
1032 23:00:08.265908 [Byte1]: 45
1033 23:00:08.270447
1034 23:00:08.270670 Set Vref, RX VrefLevel [Byte0]: 46
1035 23:00:08.273545 [Byte1]: 46
1036 23:00:08.277913
1037 23:00:08.278136 Set Vref, RX VrefLevel [Byte0]: 47
1038 23:00:08.281339 [Byte1]: 47
1039 23:00:08.285087
1040 23:00:08.285322 Set Vref, RX VrefLevel [Byte0]: 48
1041 23:00:08.288568 [Byte1]: 48
1042 23:00:08.292709
1043 23:00:08.292932 Set Vref, RX VrefLevel [Byte0]: 49
1044 23:00:08.296431 [Byte1]: 49
1045 23:00:08.300433
1046 23:00:08.300658 Set Vref, RX VrefLevel [Byte0]: 50
1047 23:00:08.303635 [Byte1]: 50
1048 23:00:08.307984
1049 23:00:08.308208 Set Vref, RX VrefLevel [Byte0]: 51
1050 23:00:08.311198 [Byte1]: 51
1051 23:00:08.315535
1052 23:00:08.315763 Set Vref, RX VrefLevel [Byte0]: 52
1053 23:00:08.318671 [Byte1]: 52
1054 23:00:08.323006
1055 23:00:08.323230 Set Vref, RX VrefLevel [Byte0]: 53
1056 23:00:08.326151 [Byte1]: 53
1057 23:00:08.330516
1058 23:00:08.330792 Set Vref, RX VrefLevel [Byte0]: 54
1059 23:00:08.333769 [Byte1]: 54
1060 23:00:08.338091
1061 23:00:08.338569 Set Vref, RX VrefLevel [Byte0]: 55
1062 23:00:08.341213 [Byte1]: 55
1063 23:00:08.345745
1064 23:00:08.346209 Set Vref, RX VrefLevel [Byte0]: 56
1065 23:00:08.348737 [Byte1]: 56
1066 23:00:08.353168
1067 23:00:08.353723 Set Vref, RX VrefLevel [Byte0]: 57
1068 23:00:08.356436 [Byte1]: 57
1069 23:00:08.361374
1070 23:00:08.361846 Set Vref, RX VrefLevel [Byte0]: 58
1071 23:00:08.364228 [Byte1]: 58
1072 23:00:08.368624
1073 23:00:08.368983 Set Vref, RX VrefLevel [Byte0]: 59
1074 23:00:08.371592 [Byte1]: 59
1075 23:00:08.376614
1076 23:00:08.377046 Set Vref, RX VrefLevel [Byte0]: 60
1077 23:00:08.379387 [Byte1]: 60
1078 23:00:08.383612
1079 23:00:08.383971 Set Vref, RX VrefLevel [Byte0]: 61
1080 23:00:08.387307 [Byte1]: 61
1081 23:00:08.390816
1082 23:00:08.391181 Set Vref, RX VrefLevel [Byte0]: 62
1083 23:00:08.394311 [Byte1]: 62
1084 23:00:08.398700
1085 23:00:08.399067 Set Vref, RX VrefLevel [Byte0]: 63
1086 23:00:08.402510 [Byte1]: 63
1087 23:00:08.406322
1088 23:00:08.406686 Set Vref, RX VrefLevel [Byte0]: 64
1089 23:00:08.409542 [Byte1]: 64
1090 23:00:08.413772
1091 23:00:08.414131 Set Vref, RX VrefLevel [Byte0]: 65
1092 23:00:08.416830 [Byte1]: 65
1093 23:00:08.421813
1094 23:00:08.422178 Set Vref, RX VrefLevel [Byte0]: 66
1095 23:00:08.424536 [Byte1]: 66
1096 23:00:08.429150
1097 23:00:08.429684 Set Vref, RX VrefLevel [Byte0]: 67
1098 23:00:08.432130 [Byte1]: 67
1099 23:00:08.436357
1100 23:00:08.436721 Set Vref, RX VrefLevel [Byte0]: 68
1101 23:00:08.440005 [Byte1]: 68
1102 23:00:08.444149
1103 23:00:08.444562 Set Vref, RX VrefLevel [Byte0]: 69
1104 23:00:08.447470 [Byte1]: 69
1105 23:00:08.451536
1106 23:00:08.451897 Set Vref, RX VrefLevel [Byte0]: 70
1107 23:00:08.454606 [Byte1]: 70
1108 23:00:08.458958
1109 23:00:08.459320 Set Vref, RX VrefLevel [Byte0]: 71
1110 23:00:08.462233 [Byte1]: 71
1111 23:00:08.466552
1112 23:00:08.466915 Set Vref, RX VrefLevel [Byte0]: 72
1113 23:00:08.469965 [Byte1]: 72
1114 23:00:08.474076
1115 23:00:08.474425 Set Vref, RX VrefLevel [Byte0]: 73
1116 23:00:08.477792 [Byte1]: 73
1117 23:00:08.481700
1118 23:00:08.482050 Set Vref, RX VrefLevel [Byte0]: 74
1119 23:00:08.484941 [Byte1]: 74
1120 23:00:08.489301
1121 23:00:08.489863 Set Vref, RX VrefLevel [Byte0]: 75
1122 23:00:08.492336 [Byte1]: 75
1123 23:00:08.496842
1124 23:00:08.497169 Set Vref, RX VrefLevel [Byte0]: 76
1125 23:00:08.500094 [Byte1]: 76
1126 23:00:08.504353
1127 23:00:08.504793 Set Vref, RX VrefLevel [Byte0]: 77
1128 23:00:08.507457 [Byte1]: 77
1129 23:00:08.512008
1130 23:00:08.512288 Final RX Vref Byte 0 = 60 to rank0
1131 23:00:08.515183 Final RX Vref Byte 1 = 65 to rank0
1132 23:00:08.518718 Final RX Vref Byte 0 = 60 to rank1
1133 23:00:08.522036 Final RX Vref Byte 1 = 65 to rank1==
1134 23:00:08.525039 Dram Type= 6, Freq= 0, CH_0, rank 0
1135 23:00:08.528352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 23:00:08.531980 ==
1137 23:00:08.532059 DQS Delay:
1138 23:00:08.532122 DQS0 = 0, DQS1 = 0
1139 23:00:08.535258 DQM Delay:
1140 23:00:08.535337 DQM0 = 92, DQM1 = 86
1141 23:00:08.538471 DQ Delay:
1142 23:00:08.538557 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1143 23:00:08.541861 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1144 23:00:08.545300 DQ8 =80, DQ9 =76, DQ10 =84, DQ11 =76
1145 23:00:08.548433 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
1146 23:00:08.551777
1147 23:00:08.551854
1148 23:00:08.558160 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1149 23:00:08.561654 CH0 RK0: MR19=606, MR18=4D43
1150 23:00:08.568439 CH0_RK0: MR19=0x606, MR18=0x4D43, DQSOSC=390, MR23=63, INC=97, DEC=64
1151 23:00:08.568530
1152 23:00:08.572181 ----->DramcWriteLeveling(PI) begin...
1153 23:00:08.572313 ==
1154 23:00:08.575216 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 23:00:08.578693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 23:00:08.578809 ==
1157 23:00:08.581612 Write leveling (Byte 0): 32 => 32
1158 23:00:08.585601 Write leveling (Byte 1): 30 => 30
1159 23:00:08.588353 DramcWriteLeveling(PI) end<-----
1160 23:00:08.588539
1161 23:00:08.588670 ==
1162 23:00:08.591859 Dram Type= 6, Freq= 0, CH_0, rank 1
1163 23:00:08.595532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1164 23:00:08.595772 ==
1165 23:00:08.598707 [Gating] SW mode calibration
1166 23:00:08.605117 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1167 23:00:08.649264 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1168 23:00:08.650235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1169 23:00:08.650721 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1170 23:00:08.651100 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1171 23:00:08.651580 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:00:08.652030 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:00:08.652536 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:00:08.652992 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:00:08.653448 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:00:08.653950 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:00:08.693289 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:00:08.694204 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 23:00:08.694771 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 23:00:08.695275 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 23:00:08.695741 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 23:00:08.696095 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 23:00:08.696491 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 23:00:08.696975 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 23:00:08.697489 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 23:00:08.697937 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1187 23:00:08.737978 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1188 23:00:08.738678 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:00:08.739034 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:00:08.739427 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:00:08.739779 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:00:08.740118 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:00:08.740524 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1194 23:00:08.740851 0 9 8 | B1->B0 | 2c2c 2c2c | 1 1 | (1 1) (0 0)
1195 23:00:08.741180 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1196 23:00:08.741448 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1197 23:00:08.749222 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1198 23:00:08.749891 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1199 23:00:08.752533 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1200 23:00:08.755682 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1201 23:00:08.758620 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1202 23:00:08.765544 0 10 8 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (0 0)
1203 23:00:08.769159 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1204 23:00:08.772662 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1205 23:00:08.779546 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1206 23:00:08.783231 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1207 23:00:08.786732 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1208 23:00:08.790744 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1209 23:00:08.794729 0 11 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1210 23:00:08.800784 0 11 8 | B1->B0 | 3b3b 3b3b | 1 0 | (0 0) (0 0)
1211 23:00:08.804505 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 23:00:08.808113 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 23:00:08.811190 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1214 23:00:08.817958 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1215 23:00:08.821789 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1216 23:00:08.824643 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 23:00:08.831634 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1218 23:00:08.834806 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1219 23:00:08.838014 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 23:00:08.845012 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 23:00:08.848160 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 23:00:08.851471 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 23:00:08.857936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 23:00:08.862292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 23:00:08.864621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 23:00:08.871420 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 23:00:08.875466 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 23:00:08.878355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1229 23:00:08.884976 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 23:00:08.888797 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 23:00:08.892239 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1232 23:00:08.898184 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1233 23:00:08.901729 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1234 23:00:08.904637 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1235 23:00:08.908111 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1236 23:00:08.912017 Total UI for P1: 0, mck2ui 16
1237 23:00:08.914989 best dqsien dly found for B0: ( 0, 14, 8)
1238 23:00:08.918406 Total UI for P1: 0, mck2ui 16
1239 23:00:08.921378 best dqsien dly found for B1: ( 0, 14, 8)
1240 23:00:08.925312 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1241 23:00:08.928381 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1242 23:00:08.931682
1243 23:00:08.934756 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1244 23:00:08.938729 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1245 23:00:08.941537 [Gating] SW calibration Done
1246 23:00:08.941989 ==
1247 23:00:08.944782 Dram Type= 6, Freq= 0, CH_0, rank 1
1248 23:00:08.948030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1249 23:00:08.948580 ==
1250 23:00:08.949054 RX Vref Scan: 0
1251 23:00:08.949506
1252 23:00:08.951645 RX Vref 0 -> 0, step: 1
1253 23:00:08.952212
1254 23:00:08.954806 RX Delay -130 -> 252, step: 16
1255 23:00:08.958109 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1256 23:00:08.961682 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1257 23:00:08.968233 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1258 23:00:08.971534 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1259 23:00:08.974636 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1260 23:00:08.977868 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1261 23:00:08.981328 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1262 23:00:08.988066 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1263 23:00:08.991520 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1264 23:00:08.994814 iDelay=222, Bit 9, Center 61 (-50 ~ 173) 224
1265 23:00:08.998682 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1266 23:00:09.001391 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1267 23:00:09.008893 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1268 23:00:09.011849 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1269 23:00:09.014892 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1270 23:00:09.018653 iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208
1271 23:00:09.019071 ==
1272 23:00:09.021751 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 23:00:09.025276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 23:00:09.028246 ==
1275 23:00:09.028827 DQS Delay:
1276 23:00:09.029295 DQS0 = 0, DQS1 = 0
1277 23:00:09.031661 DQM Delay:
1278 23:00:09.032078 DQM0 = 93, DQM1 = 82
1279 23:00:09.035039 DQ Delay:
1280 23:00:09.038297 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1281 23:00:09.038718 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1282 23:00:09.041891 DQ8 =77, DQ9 =61, DQ10 =77, DQ11 =77
1283 23:00:09.044915 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1284 23:00:09.048431
1285 23:00:09.048845
1286 23:00:09.049179 ==
1287 23:00:09.051940 Dram Type= 6, Freq= 0, CH_0, rank 1
1288 23:00:09.055021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1289 23:00:09.055443 ==
1290 23:00:09.055775
1291 23:00:09.056081
1292 23:00:09.058377 TX Vref Scan disable
1293 23:00:09.058816 == TX Byte 0 ==
1294 23:00:09.065052 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1295 23:00:09.068124 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1296 23:00:09.068684 == TX Byte 1 ==
1297 23:00:09.075109 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1298 23:00:09.078441 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1299 23:00:09.079003 ==
1300 23:00:09.081570 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 23:00:09.084865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 23:00:09.085362 ==
1303 23:00:09.098678 TX Vref=22, minBit 10, minWin=27, winSum=449
1304 23:00:09.101945 TX Vref=24, minBit 12, minWin=27, winSum=452
1305 23:00:09.105573 TX Vref=26, minBit 7, minWin=28, winSum=455
1306 23:00:09.108708 TX Vref=28, minBit 7, minWin=28, winSum=460
1307 23:00:09.112060 TX Vref=30, minBit 7, minWin=28, winSum=460
1308 23:00:09.115077 TX Vref=32, minBit 4, minWin=28, winSum=457
1309 23:00:09.122207 [TxChooseVref] Worse bit 7, Min win 28, Win sum 460, Final Vref 28
1310 23:00:09.122389
1311 23:00:09.125653 Final TX Range 1 Vref 28
1312 23:00:09.125834
1313 23:00:09.125978 ==
1314 23:00:09.128979 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 23:00:09.132009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 23:00:09.132190 ==
1317 23:00:09.132332
1318 23:00:09.132463
1319 23:00:09.135817 TX Vref Scan disable
1320 23:00:09.138893 == TX Byte 0 ==
1321 23:00:09.141995 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1322 23:00:09.145802 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1323 23:00:09.148920 == TX Byte 1 ==
1324 23:00:09.152377 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1325 23:00:09.155688 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1326 23:00:09.155886
1327 23:00:09.159151 [DATLAT]
1328 23:00:09.159331 Freq=800, CH0 RK1
1329 23:00:09.159474
1330 23:00:09.162626 DATLAT Default: 0xa
1331 23:00:09.162811 0, 0xFFFF, sum = 0
1332 23:00:09.165712 1, 0xFFFF, sum = 0
1333 23:00:09.165900 2, 0xFFFF, sum = 0
1334 23:00:09.169054 3, 0xFFFF, sum = 0
1335 23:00:09.169136 4, 0xFFFF, sum = 0
1336 23:00:09.172559 5, 0xFFFF, sum = 0
1337 23:00:09.172641 6, 0xFFFF, sum = 0
1338 23:00:09.175488 7, 0xFFFF, sum = 0
1339 23:00:09.175600 8, 0xFFFF, sum = 0
1340 23:00:09.178774 9, 0x0, sum = 1
1341 23:00:09.178855 10, 0x0, sum = 2
1342 23:00:09.182514 11, 0x0, sum = 3
1343 23:00:09.182622 12, 0x0, sum = 4
1344 23:00:09.185701 best_step = 10
1345 23:00:09.185788
1346 23:00:09.185860 ==
1347 23:00:09.189309 Dram Type= 6, Freq= 0, CH_0, rank 1
1348 23:00:09.192275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1349 23:00:09.192356 ==
1350 23:00:09.195764 RX Vref Scan: 0
1351 23:00:09.195844
1352 23:00:09.195908 RX Vref 0 -> 0, step: 1
1353 23:00:09.195974
1354 23:00:09.199157 RX Delay -95 -> 252, step: 8
1355 23:00:09.205403 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1356 23:00:09.208899 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1357 23:00:09.212244 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1358 23:00:09.215675 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1359 23:00:09.218925 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1360 23:00:09.222379 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1361 23:00:09.229051 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1362 23:00:09.232343 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1363 23:00:09.235770 iDelay=209, Bit 8, Center 72 (-31 ~ 176) 208
1364 23:00:09.239111 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1365 23:00:09.242103 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1366 23:00:09.249068 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1367 23:00:09.252571 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1368 23:00:09.255932 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1369 23:00:09.259190 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1370 23:00:09.262614 iDelay=209, Bit 15, Center 88 (-15 ~ 192) 208
1371 23:00:09.265475 ==
1372 23:00:09.268842 Dram Type= 6, Freq= 0, CH_0, rank 1
1373 23:00:09.272541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1374 23:00:09.272656 ==
1375 23:00:09.272759 DQS Delay:
1376 23:00:09.276037 DQS0 = 0, DQS1 = 0
1377 23:00:09.276128 DQM Delay:
1378 23:00:09.279325 DQM0 = 93, DQM1 = 83
1379 23:00:09.279422 DQ Delay:
1380 23:00:09.282797 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1381 23:00:09.285642 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1382 23:00:09.289022 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1383 23:00:09.292457 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =88
1384 23:00:09.292586
1385 23:00:09.292691
1386 23:00:09.299033 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1387 23:00:09.302812 CH0 RK1: MR19=606, MR18=3F10
1388 23:00:09.309176 CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63
1389 23:00:09.312644 [RxdqsGatingPostProcess] freq 800
1390 23:00:09.316107 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1391 23:00:09.319182 Pre-setting of DQS Precalculation
1392 23:00:09.326203 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1393 23:00:09.326505 ==
1394 23:00:09.329327 Dram Type= 6, Freq= 0, CH_1, rank 0
1395 23:00:09.332729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 23:00:09.333030 ==
1397 23:00:09.339500 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 23:00:09.345697 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 23:00:09.353522 [CA 0] Center 36 (6~67) winsize 62
1400 23:00:09.357088 [CA 1] Center 37 (6~68) winsize 63
1401 23:00:09.360257 [CA 2] Center 34 (4~65) winsize 62
1402 23:00:09.364198 [CA 3] Center 34 (4~65) winsize 62
1403 23:00:09.367259 [CA 4] Center 34 (4~65) winsize 62
1404 23:00:09.370321 [CA 5] Center 34 (4~64) winsize 61
1405 23:00:09.370616
1406 23:00:09.374241 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1407 23:00:09.374549
1408 23:00:09.377254 [CATrainingPosCal] consider 1 rank data
1409 23:00:09.380655 u2DelayCellTimex100 = 270/100 ps
1410 23:00:09.383854 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1411 23:00:09.387289 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1412 23:00:09.393780 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1413 23:00:09.396936 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1414 23:00:09.400208 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1415 23:00:09.403862 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1416 23:00:09.404277
1417 23:00:09.406991 CA PerBit enable=1, Macro0, CA PI delay=34
1418 23:00:09.407312
1419 23:00:09.410357 [CBTSetCACLKResult] CA Dly = 34
1420 23:00:09.410744 CS Dly: 6 (0~37)
1421 23:00:09.411024 ==
1422 23:00:09.413632 Dram Type= 6, Freq= 0, CH_1, rank 1
1423 23:00:09.420688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1424 23:00:09.420998 ==
1425 23:00:09.424037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1426 23:00:09.431022 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1427 23:00:09.440049 [CA 0] Center 36 (6~67) winsize 62
1428 23:00:09.443779 [CA 1] Center 37 (6~68) winsize 63
1429 23:00:09.447372 [CA 2] Center 35 (5~66) winsize 62
1430 23:00:09.451239 [CA 3] Center 35 (5~65) winsize 61
1431 23:00:09.455385 [CA 4] Center 35 (5~66) winsize 62
1432 23:00:09.458465 [CA 5] Center 34 (4~65) winsize 62
1433 23:00:09.458783
1434 23:00:09.462108 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1435 23:00:09.462435
1436 23:00:09.465878 [CATrainingPosCal] consider 2 rank data
1437 23:00:09.466236 u2DelayCellTimex100 = 270/100 ps
1438 23:00:09.470147 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1439 23:00:09.473489 CA1 delay=37 (6~68),Diff = 3 PI (21 cell)
1440 23:00:09.476859 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1441 23:00:09.480612 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1442 23:00:09.486995 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1443 23:00:09.490453 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1444 23:00:09.490853
1445 23:00:09.493741 CA PerBit enable=1, Macro0, CA PI delay=34
1446 23:00:09.494039
1447 23:00:09.496950 [CBTSetCACLKResult] CA Dly = 34
1448 23:00:09.497243 CS Dly: 6 (0~38)
1449 23:00:09.497476
1450 23:00:09.500395 ----->DramcWriteLeveling(PI) begin...
1451 23:00:09.500692 ==
1452 23:00:09.503716 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 23:00:09.510125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 23:00:09.510437 ==
1455 23:00:09.513873 Write leveling (Byte 0): 27 => 27
1456 23:00:09.514171 Write leveling (Byte 1): 29 => 29
1457 23:00:09.517048 DramcWriteLeveling(PI) end<-----
1458 23:00:09.517351
1459 23:00:09.520704 ==
1460 23:00:09.521003 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 23:00:09.527537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 23:00:09.527619 ==
1463 23:00:09.530480 [Gating] SW mode calibration
1464 23:00:09.536754 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1465 23:00:09.540611 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1466 23:00:09.546938 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1467 23:00:09.550394 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1468 23:00:09.553493 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 23:00:09.557064 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:00:09.563526 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:00:09.567227 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:00:09.570066 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:00:09.577144 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:00:09.580415 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:00:09.583783 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:00:09.590488 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 23:00:09.593826 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 23:00:09.596827 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 23:00:09.603871 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 23:00:09.607358 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 23:00:09.610515 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 23:00:09.617130 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1483 23:00:09.620122 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1484 23:00:09.623589 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 23:00:09.630314 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 23:00:09.633987 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:00:09.637128 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:00:09.644036 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:00:09.647123 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:00:09.650530 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:00:09.653550 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (1 1)
1492 23:00:09.660329 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1493 23:00:09.663508 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1494 23:00:09.666888 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1495 23:00:09.673617 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1496 23:00:09.677095 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1497 23:00:09.680185 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 23:00:09.686947 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1499 23:00:09.690129 0 10 4 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
1500 23:00:09.693736 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1501 23:00:09.700330 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 23:00:09.703691 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1503 23:00:09.707019 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1504 23:00:09.713610 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1505 23:00:09.717100 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 23:00:09.720432 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 23:00:09.727011 0 11 4 | B1->B0 | 2626 3535 | 0 1 | (0 0) (0 0)
1508 23:00:09.730184 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1509 23:00:09.734140 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 23:00:09.740381 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1511 23:00:09.743856 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 23:00:09.746994 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1513 23:00:09.750250 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 23:00:09.757212 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 23:00:09.760938 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1516 23:00:09.763624 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1517 23:00:09.770730 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 23:00:09.774316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 23:00:09.777305 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 23:00:09.783783 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 23:00:09.787280 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 23:00:09.790501 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 23:00:09.796911 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 23:00:09.800768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 23:00:09.803733 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 23:00:09.811099 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 23:00:09.813941 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 23:00:09.817392 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 23:00:09.823908 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 23:00:09.827373 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1531 23:00:09.830703 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1532 23:00:09.834167 Total UI for P1: 0, mck2ui 16
1533 23:00:09.837438 best dqsien dly found for B1: ( 0, 14, 0)
1534 23:00:09.841241 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1535 23:00:09.844133 Total UI for P1: 0, mck2ui 16
1536 23:00:09.847437 best dqsien dly found for B0: ( 0, 14, 4)
1537 23:00:09.850982 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1538 23:00:09.854084 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1539 23:00:09.854181
1540 23:00:09.861294 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1541 23:00:09.864279 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1542 23:00:09.864411 [Gating] SW calibration Done
1543 23:00:09.867516 ==
1544 23:00:09.870998 Dram Type= 6, Freq= 0, CH_1, rank 0
1545 23:00:09.874024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1546 23:00:09.874096 ==
1547 23:00:09.874157 RX Vref Scan: 0
1548 23:00:09.874214
1549 23:00:09.877453 RX Vref 0 -> 0, step: 1
1550 23:00:09.877573
1551 23:00:09.881033 RX Delay -130 -> 252, step: 16
1552 23:00:09.884344 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1553 23:00:09.887596 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1554 23:00:09.890988 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1555 23:00:09.897504 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1556 23:00:09.900758 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1557 23:00:09.903983 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1558 23:00:09.907218 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1559 23:00:09.910559 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1560 23:00:09.917481 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1561 23:00:09.920838 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1562 23:00:09.924135 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1563 23:00:09.927605 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1564 23:00:09.930633 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1565 23:00:09.937377 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1566 23:00:09.941482 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1567 23:00:09.944041 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1568 23:00:09.944128 ==
1569 23:00:09.947653 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 23:00:09.951088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 23:00:09.954546 ==
1572 23:00:09.954645 DQS Delay:
1573 23:00:09.954724 DQS0 = 0, DQS1 = 0
1574 23:00:09.957343 DQM Delay:
1575 23:00:09.957470 DQM0 = 93, DQM1 = 87
1576 23:00:09.960688 DQ Delay:
1577 23:00:09.960879 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1578 23:00:09.964815 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1579 23:00:09.967631 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1580 23:00:09.970923 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1581 23:00:09.974250
1582 23:00:09.974398
1583 23:00:09.974516 ==
1584 23:00:09.977376 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 23:00:09.980684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 23:00:09.980885 ==
1587 23:00:09.981051
1588 23:00:09.981199
1589 23:00:09.984326 TX Vref Scan disable
1590 23:00:09.984488 == TX Byte 0 ==
1591 23:00:09.991460 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1592 23:00:09.994477 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1593 23:00:09.994855 == TX Byte 1 ==
1594 23:00:10.001636 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1595 23:00:10.004509 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1596 23:00:10.004950 ==
1597 23:00:10.008360 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 23:00:10.011392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 23:00:10.011809 ==
1600 23:00:10.025571 TX Vref=22, minBit 0, minWin=26, winSum=437
1601 23:00:10.029025 TX Vref=24, minBit 1, minWin=26, winSum=441
1602 23:00:10.032250 TX Vref=26, minBit 3, minWin=26, winSum=442
1603 23:00:10.035937 TX Vref=28, minBit 1, minWin=27, winSum=445
1604 23:00:10.039025 TX Vref=30, minBit 1, minWin=27, winSum=448
1605 23:00:10.042368 TX Vref=32, minBit 0, minWin=27, winSum=446
1606 23:00:10.049386 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
1607 23:00:10.049862
1608 23:00:10.052358 Final TX Range 1 Vref 30
1609 23:00:10.052770
1610 23:00:10.053089 ==
1611 23:00:10.055804 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 23:00:10.058836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 23:00:10.059250 ==
1614 23:00:10.059574
1615 23:00:10.059875
1616 23:00:10.062107 TX Vref Scan disable
1617 23:00:10.065304 == TX Byte 0 ==
1618 23:00:10.068755 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1619 23:00:10.071949 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1620 23:00:10.075856 == TX Byte 1 ==
1621 23:00:10.078899 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1622 23:00:10.082026 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1623 23:00:10.082436
1624 23:00:10.082758 [DATLAT]
1625 23:00:10.085912 Freq=800, CH1 RK0
1626 23:00:10.086323
1627 23:00:10.088946 DATLAT Default: 0xa
1628 23:00:10.089355 0, 0xFFFF, sum = 0
1629 23:00:10.092025 1, 0xFFFF, sum = 0
1630 23:00:10.092441 2, 0xFFFF, sum = 0
1631 23:00:10.095509 3, 0xFFFF, sum = 0
1632 23:00:10.096157 4, 0xFFFF, sum = 0
1633 23:00:10.099281 5, 0xFFFF, sum = 0
1634 23:00:10.099698 6, 0xFFFF, sum = 0
1635 23:00:10.102512 7, 0xFFFF, sum = 0
1636 23:00:10.102930 8, 0xFFFF, sum = 0
1637 23:00:10.105716 9, 0x0, sum = 1
1638 23:00:10.106134 10, 0x0, sum = 2
1639 23:00:10.109017 11, 0x0, sum = 3
1640 23:00:10.109431 12, 0x0, sum = 4
1641 23:00:10.109798 best_step = 10
1642 23:00:10.110102
1643 23:00:10.112473 ==
1644 23:00:10.115492 Dram Type= 6, Freq= 0, CH_1, rank 0
1645 23:00:10.118730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1646 23:00:10.119175 ==
1647 23:00:10.119538 RX Vref Scan: 1
1648 23:00:10.119850
1649 23:00:10.122293 Set Vref Range= 32 -> 127
1650 23:00:10.122989
1651 23:00:10.125642 RX Vref 32 -> 127, step: 1
1652 23:00:10.126051
1653 23:00:10.128908 RX Delay -79 -> 252, step: 8
1654 23:00:10.129342
1655 23:00:10.132131 Set Vref, RX VrefLevel [Byte0]: 32
1656 23:00:10.135759 [Byte1]: 32
1657 23:00:10.136246
1658 23:00:10.138853 Set Vref, RX VrefLevel [Byte0]: 33
1659 23:00:10.142211 [Byte1]: 33
1660 23:00:10.142638
1661 23:00:10.145463 Set Vref, RX VrefLevel [Byte0]: 34
1662 23:00:10.149271 [Byte1]: 34
1663 23:00:10.152049
1664 23:00:10.152451 Set Vref, RX VrefLevel [Byte0]: 35
1665 23:00:10.155580 [Byte1]: 35
1666 23:00:10.159598
1667 23:00:10.160003 Set Vref, RX VrefLevel [Byte0]: 36
1668 23:00:10.162966 [Byte1]: 36
1669 23:00:10.167204
1670 23:00:10.167612 Set Vref, RX VrefLevel [Byte0]: 37
1671 23:00:10.170429 [Byte1]: 37
1672 23:00:10.174881
1673 23:00:10.175289 Set Vref, RX VrefLevel [Byte0]: 38
1674 23:00:10.178048 [Byte1]: 38
1675 23:00:10.182610
1676 23:00:10.183016 Set Vref, RX VrefLevel [Byte0]: 39
1677 23:00:10.185862 [Byte1]: 39
1678 23:00:10.190091
1679 23:00:10.190499 Set Vref, RX VrefLevel [Byte0]: 40
1680 23:00:10.193508 [Byte1]: 40
1681 23:00:10.197608
1682 23:00:10.198014 Set Vref, RX VrefLevel [Byte0]: 41
1683 23:00:10.200882 [Byte1]: 41
1684 23:00:10.204890
1685 23:00:10.205300 Set Vref, RX VrefLevel [Byte0]: 42
1686 23:00:10.208469 [Byte1]: 42
1687 23:00:10.213004
1688 23:00:10.213415 Set Vref, RX VrefLevel [Byte0]: 43
1689 23:00:10.216081 [Byte1]: 43
1690 23:00:10.220771
1691 23:00:10.221180 Set Vref, RX VrefLevel [Byte0]: 44
1692 23:00:10.223393 [Byte1]: 44
1693 23:00:10.228037
1694 23:00:10.228442 Set Vref, RX VrefLevel [Byte0]: 45
1695 23:00:10.230870 [Byte1]: 45
1696 23:00:10.235256
1697 23:00:10.235661 Set Vref, RX VrefLevel [Byte0]: 46
1698 23:00:10.238429 [Byte1]: 46
1699 23:00:10.242684
1700 23:00:10.243090 Set Vref, RX VrefLevel [Byte0]: 47
1701 23:00:10.246604 [Byte1]: 47
1702 23:00:10.250315
1703 23:00:10.250722 Set Vref, RX VrefLevel [Byte0]: 48
1704 23:00:10.253820 [Byte1]: 48
1705 23:00:10.257847
1706 23:00:10.258425 Set Vref, RX VrefLevel [Byte0]: 49
1707 23:00:10.261193 [Byte1]: 49
1708 23:00:10.265717
1709 23:00:10.266133 Set Vref, RX VrefLevel [Byte0]: 50
1710 23:00:10.269076 [Byte1]: 50
1711 23:00:10.272997
1712 23:00:10.273637 Set Vref, RX VrefLevel [Byte0]: 51
1713 23:00:10.276088 [Byte1]: 51
1714 23:00:10.280755
1715 23:00:10.281164 Set Vref, RX VrefLevel [Byte0]: 52
1716 23:00:10.284307 [Byte1]: 52
1717 23:00:10.288213
1718 23:00:10.288618 Set Vref, RX VrefLevel [Byte0]: 53
1719 23:00:10.291274 [Byte1]: 53
1720 23:00:10.295690
1721 23:00:10.296095 Set Vref, RX VrefLevel [Byte0]: 54
1722 23:00:10.298880 [Byte1]: 54
1723 23:00:10.303389
1724 23:00:10.303792 Set Vref, RX VrefLevel [Byte0]: 55
1725 23:00:10.306422 [Byte1]: 55
1726 23:00:10.310612
1727 23:00:10.311018 Set Vref, RX VrefLevel [Byte0]: 56
1728 23:00:10.313941 [Byte1]: 56
1729 23:00:10.318707
1730 23:00:10.319115 Set Vref, RX VrefLevel [Byte0]: 57
1731 23:00:10.321295 [Byte1]: 57
1732 23:00:10.326018
1733 23:00:10.326498 Set Vref, RX VrefLevel [Byte0]: 58
1734 23:00:10.329055 [Byte1]: 58
1735 23:00:10.333554
1736 23:00:10.334062 Set Vref, RX VrefLevel [Byte0]: 59
1737 23:00:10.336587 [Byte1]: 59
1738 23:00:10.340784
1739 23:00:10.341270 Set Vref, RX VrefLevel [Byte0]: 60
1740 23:00:10.344071 [Byte1]: 60
1741 23:00:10.348311
1742 23:00:10.348860 Set Vref, RX VrefLevel [Byte0]: 61
1743 23:00:10.351806 [Byte1]: 61
1744 23:00:10.356209
1745 23:00:10.356705 Set Vref, RX VrefLevel [Byte0]: 62
1746 23:00:10.359311 [Byte1]: 62
1747 23:00:10.363901
1748 23:00:10.364406 Set Vref, RX VrefLevel [Byte0]: 63
1749 23:00:10.366996 [Byte1]: 63
1750 23:00:10.370957
1751 23:00:10.371469 Set Vref, RX VrefLevel [Byte0]: 64
1752 23:00:10.374321 [Byte1]: 64
1753 23:00:10.378610
1754 23:00:10.379067 Set Vref, RX VrefLevel [Byte0]: 65
1755 23:00:10.382220 [Byte1]: 65
1756 23:00:10.386330
1757 23:00:10.386771 Set Vref, RX VrefLevel [Byte0]: 66
1758 23:00:10.389681 [Byte1]: 66
1759 23:00:10.393525
1760 23:00:10.394088 Set Vref, RX VrefLevel [Byte0]: 67
1761 23:00:10.397200 [Byte1]: 67
1762 23:00:10.401814
1763 23:00:10.402326 Set Vref, RX VrefLevel [Byte0]: 68
1764 23:00:10.404744 [Byte1]: 68
1765 23:00:10.408770
1766 23:00:10.409202 Set Vref, RX VrefLevel [Byte0]: 69
1767 23:00:10.411966 [Byte1]: 69
1768 23:00:10.416186
1769 23:00:10.416761 Set Vref, RX VrefLevel [Byte0]: 70
1770 23:00:10.419794 [Byte1]: 70
1771 23:00:10.424145
1772 23:00:10.424576 Set Vref, RX VrefLevel [Byte0]: 71
1773 23:00:10.427351 [Byte1]: 71
1774 23:00:10.431723
1775 23:00:10.432321 Final RX Vref Byte 0 = 58 to rank0
1776 23:00:10.434758 Final RX Vref Byte 1 = 52 to rank0
1777 23:00:10.438202 Final RX Vref Byte 0 = 58 to rank1
1778 23:00:10.441517 Final RX Vref Byte 1 = 52 to rank1==
1779 23:00:10.445053 Dram Type= 6, Freq= 0, CH_1, rank 0
1780 23:00:10.451513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1781 23:00:10.452031 ==
1782 23:00:10.452473 DQS Delay:
1783 23:00:10.452890 DQS0 = 0, DQS1 = 0
1784 23:00:10.454788 DQM Delay:
1785 23:00:10.455217 DQM0 = 96, DQM1 = 89
1786 23:00:10.458528 DQ Delay:
1787 23:00:10.461567 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =92
1788 23:00:10.465139 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92
1789 23:00:10.468731 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =84
1790 23:00:10.471833 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1791 23:00:10.472290
1792 23:00:10.472783
1793 23:00:10.478239 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1794 23:00:10.481692 CH1 RK0: MR19=606, MR18=304C
1795 23:00:10.488376 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1796 23:00:10.488872
1797 23:00:10.491864 ----->DramcWriteLeveling(PI) begin...
1798 23:00:10.492280 ==
1799 23:00:10.494790 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 23:00:10.498116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 23:00:10.498530 ==
1802 23:00:10.501780 Write leveling (Byte 0): 26 => 26
1803 23:00:10.504818 Write leveling (Byte 1): 31 => 31
1804 23:00:10.508081 DramcWriteLeveling(PI) end<-----
1805 23:00:10.508496
1806 23:00:10.508821 ==
1807 23:00:10.511648 Dram Type= 6, Freq= 0, CH_1, rank 1
1808 23:00:10.514871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1809 23:00:10.515393 ==
1810 23:00:10.518274 [Gating] SW mode calibration
1811 23:00:10.524850 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1812 23:00:10.531495 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1813 23:00:10.534831 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1814 23:00:10.537970 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1815 23:00:10.544784 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1816 23:00:10.548529 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 23:00:10.551646 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:00:10.558414 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:00:10.561720 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:00:10.564763 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:00:10.571440 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:00:10.574944 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:00:10.578064 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:00:10.584615 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 23:00:10.588000 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 23:00:10.591928 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 23:00:10.598208 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 23:00:10.601474 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 23:00:10.604941 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1830 23:00:10.608368 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1831 23:00:10.614869 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 23:00:10.618418 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 23:00:10.621816 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 23:00:10.628588 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:00:10.631626 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:00:10.634925 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:00:10.641610 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:00:10.645129 0 9 4 | B1->B0 | 2929 2323 | 1 0 | (0 0) (0 0)
1839 23:00:10.648239 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
1840 23:00:10.655371 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 23:00:10.658383 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 23:00:10.661740 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 23:00:10.668494 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 23:00:10.671847 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 23:00:10.675397 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1846 23:00:10.678676 0 10 4 | B1->B0 | 2c2c 3030 | 0 0 | (0 1) (0 1)
1847 23:00:10.685329 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1848 23:00:10.688535 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 23:00:10.692042 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 23:00:10.698530 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 23:00:10.702003 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 23:00:10.705454 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 23:00:10.712069 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1854 23:00:10.715388 0 11 4 | B1->B0 | 3d3d 2929 | 0 0 | (0 0) (0 0)
1855 23:00:10.718719 0 11 8 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
1856 23:00:10.725428 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 23:00:10.728854 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 23:00:10.732297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 23:00:10.738499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 23:00:10.742439 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 23:00:10.745419 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 23:00:10.752066 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1863 23:00:10.755459 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 23:00:10.758669 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 23:00:10.761945 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 23:00:10.768425 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 23:00:10.772204 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 23:00:10.775868 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 23:00:10.782848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 23:00:10.785244 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 23:00:10.788840 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 23:00:10.795647 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 23:00:10.799553 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 23:00:10.802094 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 23:00:10.808933 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 23:00:10.812108 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 23:00:10.815998 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1878 23:00:10.822148 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1879 23:00:10.822568 Total UI for P1: 0, mck2ui 16
1880 23:00:10.829061 best dqsien dly found for B1: ( 0, 14, 0)
1881 23:00:10.832209 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 23:00:10.835205 Total UI for P1: 0, mck2ui 16
1883 23:00:10.839072 best dqsien dly found for B0: ( 0, 14, 4)
1884 23:00:10.842392 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1885 23:00:10.845678 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1886 23:00:10.846098
1887 23:00:10.848650 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1888 23:00:10.851974 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1889 23:00:10.855285 [Gating] SW calibration Done
1890 23:00:10.855698 ==
1891 23:00:10.858847 Dram Type= 6, Freq= 0, CH_1, rank 1
1892 23:00:10.862274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1893 23:00:10.862688 ==
1894 23:00:10.865364 RX Vref Scan: 0
1895 23:00:10.865850
1896 23:00:10.868776 RX Vref 0 -> 0, step: 1
1897 23:00:10.869187
1898 23:00:10.869509 RX Delay -130 -> 252, step: 16
1899 23:00:10.875391 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1900 23:00:10.878511 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1901 23:00:10.882189 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1902 23:00:10.886005 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1903 23:00:10.888750 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1904 23:00:10.895478 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1905 23:00:10.898924 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1906 23:00:10.902190 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1907 23:00:10.905477 iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208
1908 23:00:10.908795 iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208
1909 23:00:10.911969 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1910 23:00:10.918824 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1911 23:00:10.922483 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1912 23:00:10.925765 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1913 23:00:10.928973 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1914 23:00:10.935408 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1915 23:00:10.935898 ==
1916 23:00:10.939135 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 23:00:10.942121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 23:00:10.942535 ==
1919 23:00:10.942862 DQS Delay:
1920 23:00:10.945522 DQS0 = 0, DQS1 = 0
1921 23:00:10.946038 DQM Delay:
1922 23:00:10.948986 DQM0 = 92, DQM1 = 90
1923 23:00:10.949396 DQ Delay:
1924 23:00:10.952265 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
1925 23:00:10.955354 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1926 23:00:10.958660 DQ8 =85, DQ9 =85, DQ10 =93, DQ11 =85
1927 23:00:10.961962 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1928 23:00:10.962373
1929 23:00:10.962696
1930 23:00:10.962997 ==
1931 23:00:10.965460 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 23:00:10.968821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 23:00:10.969236 ==
1934 23:00:10.969561
1935 23:00:10.969916
1936 23:00:10.972258 TX Vref Scan disable
1937 23:00:10.975041 == TX Byte 0 ==
1938 23:00:10.978884 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1939 23:00:10.982384 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1940 23:00:10.985635 == TX Byte 1 ==
1941 23:00:10.988853 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1942 23:00:10.991995 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1943 23:00:10.992408 ==
1944 23:00:10.995271 Dram Type= 6, Freq= 0, CH_1, rank 1
1945 23:00:11.001989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1946 23:00:11.002403 ==
1947 23:00:11.014276 TX Vref=22, minBit 5, minWin=26, winSum=437
1948 23:00:11.017754 TX Vref=24, minBit 0, minWin=27, winSum=443
1949 23:00:11.021124 TX Vref=26, minBit 0, minWin=27, winSum=444
1950 23:00:11.024272 TX Vref=28, minBit 0, minWin=27, winSum=451
1951 23:00:11.027307 TX Vref=30, minBit 2, minWin=27, winSum=449
1952 23:00:11.030973 TX Vref=32, minBit 0, minWin=27, winSum=447
1953 23:00:11.037523 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 28
1954 23:00:11.038095
1955 23:00:11.040689 Final TX Range 1 Vref 28
1956 23:00:11.041177
1957 23:00:11.041665 ==
1958 23:00:11.043948 Dram Type= 6, Freq= 0, CH_1, rank 1
1959 23:00:11.047427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1960 23:00:11.047845 ==
1961 23:00:11.048176
1962 23:00:11.050604
1963 23:00:11.051016 TX Vref Scan disable
1964 23:00:11.054131 == TX Byte 0 ==
1965 23:00:11.057338 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1966 23:00:11.064621 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1967 23:00:11.065028 == TX Byte 1 ==
1968 23:00:11.067359 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1969 23:00:11.070646 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1970 23:00:11.073998
1971 23:00:11.074400 [DATLAT]
1972 23:00:11.074723 Freq=800, CH1 RK1
1973 23:00:11.075023
1974 23:00:11.077400 DATLAT Default: 0xa
1975 23:00:11.077856 0, 0xFFFF, sum = 0
1976 23:00:11.080686 1, 0xFFFF, sum = 0
1977 23:00:11.081098 2, 0xFFFF, sum = 0
1978 23:00:11.084542 3, 0xFFFF, sum = 0
1979 23:00:11.085070 4, 0xFFFF, sum = 0
1980 23:00:11.087626 5, 0xFFFF, sum = 0
1981 23:00:11.090798 6, 0xFFFF, sum = 0
1982 23:00:11.091213 7, 0xFFFF, sum = 0
1983 23:00:11.094126 8, 0xFFFF, sum = 0
1984 23:00:11.094540 9, 0x0, sum = 1
1985 23:00:11.094870 10, 0x0, sum = 2
1986 23:00:11.097277 11, 0x0, sum = 3
1987 23:00:11.097817 12, 0x0, sum = 4
1988 23:00:11.100819 best_step = 10
1989 23:00:11.101230
1990 23:00:11.101554 ==
1991 23:00:11.104045 Dram Type= 6, Freq= 0, CH_1, rank 1
1992 23:00:11.107255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1993 23:00:11.107730 ==
1994 23:00:11.110976 RX Vref Scan: 0
1995 23:00:11.111435
1996 23:00:11.111865 RX Vref 0 -> 0, step: 1
1997 23:00:11.112387
1998 23:00:11.113693 RX Delay -63 -> 252, step: 8
1999 23:00:11.120677 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2000 23:00:11.123849 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2001 23:00:11.127282 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2002 23:00:11.130797 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2003 23:00:11.134166 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2004 23:00:11.137607 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2005 23:00:11.144119 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2006 23:00:11.147232 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2007 23:00:11.150471 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2008 23:00:11.154313 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2009 23:00:11.157300 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2010 23:00:11.163805 iDelay=209, Bit 11, Center 84 (-15 ~ 184) 200
2011 23:00:11.167094 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2012 23:00:11.170366 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2013 23:00:11.173680 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2014 23:00:11.177195 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2015 23:00:11.180282 ==
2016 23:00:11.180723 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:00:11.187394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:00:11.187814 ==
2019 23:00:11.188239 DQS Delay:
2020 23:00:11.190301 DQS0 = 0, DQS1 = 0
2021 23:00:11.190713 DQM Delay:
2022 23:00:11.194194 DQM0 = 97, DQM1 = 90
2023 23:00:11.194607 DQ Delay:
2024 23:00:11.196965 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2025 23:00:11.201100 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2026 23:00:11.204238 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
2027 23:00:11.207030 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2028 23:00:11.207443
2029 23:00:11.207768
2030 23:00:11.214387 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a14, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
2031 23:00:11.217223 CH1 RK1: MR19=606, MR18=4A14
2032 23:00:11.224041 CH1_RK1: MR19=0x606, MR18=0x4A14, DQSOSC=391, MR23=63, INC=96, DEC=64
2033 23:00:11.227294 [RxdqsGatingPostProcess] freq 800
2034 23:00:11.230464 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2035 23:00:11.233973 Pre-setting of DQS Precalculation
2036 23:00:11.240841 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2037 23:00:11.247289 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2038 23:00:11.253907 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2039 23:00:11.254325
2040 23:00:11.254654
2041 23:00:11.257569 [Calibration Summary] 1600 Mbps
2042 23:00:11.260842 CH 0, Rank 0
2043 23:00:11.261252 SW Impedance : PASS
2044 23:00:11.264105 DUTY Scan : NO K
2045 23:00:11.264517 ZQ Calibration : PASS
2046 23:00:11.267224 Jitter Meter : NO K
2047 23:00:11.270511 CBT Training : PASS
2048 23:00:11.270921 Write leveling : PASS
2049 23:00:11.274242 RX DQS gating : PASS
2050 23:00:11.277612 RX DQ/DQS(RDDQC) : PASS
2051 23:00:11.278039 TX DQ/DQS : PASS
2052 23:00:11.280539 RX DATLAT : PASS
2053 23:00:11.283976 RX DQ/DQS(Engine): PASS
2054 23:00:11.284388 TX OE : NO K
2055 23:00:11.284719 All Pass.
2056 23:00:11.287953
2057 23:00:11.288443 CH 0, Rank 1
2058 23:00:11.291052 SW Impedance : PASS
2059 23:00:11.291463 DUTY Scan : NO K
2060 23:00:11.294024 ZQ Calibration : PASS
2061 23:00:11.294437 Jitter Meter : NO K
2062 23:00:11.297483 CBT Training : PASS
2063 23:00:11.300871 Write leveling : PASS
2064 23:00:11.301334 RX DQS gating : PASS
2065 23:00:11.304572 RX DQ/DQS(RDDQC) : PASS
2066 23:00:11.307718 TX DQ/DQS : PASS
2067 23:00:11.308261 RX DATLAT : PASS
2068 23:00:11.310892 RX DQ/DQS(Engine): PASS
2069 23:00:11.314573 TX OE : NO K
2070 23:00:11.315043 All Pass.
2071 23:00:11.315386
2072 23:00:11.315688 CH 1, Rank 0
2073 23:00:11.317826 SW Impedance : PASS
2074 23:00:11.320971 DUTY Scan : NO K
2075 23:00:11.321573 ZQ Calibration : PASS
2076 23:00:11.324526 Jitter Meter : NO K
2077 23:00:11.327677 CBT Training : PASS
2078 23:00:11.328182 Write leveling : PASS
2079 23:00:11.330781 RX DQS gating : PASS
2080 23:00:11.334206 RX DQ/DQS(RDDQC) : PASS
2081 23:00:11.334617 TX DQ/DQS : PASS
2082 23:00:11.337462 RX DATLAT : PASS
2083 23:00:11.337919 RX DQ/DQS(Engine): PASS
2084 23:00:11.340996 TX OE : NO K
2085 23:00:11.341410 All Pass.
2086 23:00:11.341822
2087 23:00:11.343874 CH 1, Rank 1
2088 23:00:11.344280 SW Impedance : PASS
2089 23:00:11.347679 DUTY Scan : NO K
2090 23:00:11.351016 ZQ Calibration : PASS
2091 23:00:11.351524 Jitter Meter : NO K
2092 23:00:11.354417 CBT Training : PASS
2093 23:00:11.357652 Write leveling : PASS
2094 23:00:11.358058 RX DQS gating : PASS
2095 23:00:11.360801 RX DQ/DQS(RDDQC) : PASS
2096 23:00:11.364409 TX DQ/DQS : PASS
2097 23:00:11.364819 RX DATLAT : PASS
2098 23:00:11.367494 RX DQ/DQS(Engine): PASS
2099 23:00:11.370639 TX OE : NO K
2100 23:00:11.371048 All Pass.
2101 23:00:11.371369
2102 23:00:11.371694 DramC Write-DBI off
2103 23:00:11.374305 PER_BANK_REFRESH: Hybrid Mode
2104 23:00:11.378004 TX_TRACKING: ON
2105 23:00:11.380789 [GetDramInforAfterCalByMRR] Vendor 6.
2106 23:00:11.384611 [GetDramInforAfterCalByMRR] Revision 606.
2107 23:00:11.387665 [GetDramInforAfterCalByMRR] Revision 2 0.
2108 23:00:11.388074 MR0 0x3b3b
2109 23:00:11.390875 MR8 0x5151
2110 23:00:11.394435 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2111 23:00:11.394846
2112 23:00:11.395168 MR0 0x3b3b
2113 23:00:11.395465 MR8 0x5151
2114 23:00:11.397809 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2115 23:00:11.401127
2116 23:00:11.407615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2117 23:00:11.410864 [FAST_K] Save calibration result to emmc
2118 23:00:11.414211 [FAST_K] Save calibration result to emmc
2119 23:00:11.417468 dram_init: config_dvfs: 1
2120 23:00:11.420620 dramc_set_vcore_voltage set vcore to 662500
2121 23:00:11.423890 Read voltage for 1200, 2
2122 23:00:11.424298 Vio18 = 0
2123 23:00:11.427344 Vcore = 662500
2124 23:00:11.427768 Vdram = 0
2125 23:00:11.428093 Vddq = 0
2126 23:00:11.428394 Vmddr = 0
2127 23:00:11.434214 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2128 23:00:11.440500 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2129 23:00:11.441047 MEM_TYPE=3, freq_sel=15
2130 23:00:11.443899 sv_algorithm_assistance_LP4_1600
2131 23:00:11.447626 ============ PULL DRAM RESETB DOWN ============
2132 23:00:11.453851 ========== PULL DRAM RESETB DOWN end =========
2133 23:00:11.457356 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2134 23:00:11.460893 ===================================
2135 23:00:11.464202 LPDDR4 DRAM CONFIGURATION
2136 23:00:11.467441 ===================================
2137 23:00:11.467854 EX_ROW_EN[0] = 0x0
2138 23:00:11.470787 EX_ROW_EN[1] = 0x0
2139 23:00:11.471202 LP4Y_EN = 0x0
2140 23:00:11.474069 WORK_FSP = 0x0
2141 23:00:11.474480 WL = 0x4
2142 23:00:11.477749 RL = 0x4
2143 23:00:11.478163 BL = 0x2
2144 23:00:11.480916 RPST = 0x0
2145 23:00:11.481328 RD_PRE = 0x0
2146 23:00:11.484098 WR_PRE = 0x1
2147 23:00:11.487173 WR_PST = 0x0
2148 23:00:11.487582 DBI_WR = 0x0
2149 23:00:11.491390 DBI_RD = 0x0
2150 23:00:11.491799 OTF = 0x1
2151 23:00:11.493900 ===================================
2152 23:00:11.497400 ===================================
2153 23:00:11.497886 ANA top config
2154 23:00:11.500823 ===================================
2155 23:00:11.504202 DLL_ASYNC_EN = 0
2156 23:00:11.507414 ALL_SLAVE_EN = 0
2157 23:00:11.510711 NEW_RANK_MODE = 1
2158 23:00:11.513801 DLL_IDLE_MODE = 1
2159 23:00:11.514252 LP45_APHY_COMB_EN = 1
2160 23:00:11.517523 TX_ODT_DIS = 1
2161 23:00:11.520957 NEW_8X_MODE = 1
2162 23:00:11.524142 ===================================
2163 23:00:11.527365 ===================================
2164 23:00:11.530573 data_rate = 2400
2165 23:00:11.534181 CKR = 1
2166 23:00:11.534592 DQ_P2S_RATIO = 8
2167 23:00:11.537256 ===================================
2168 23:00:11.541398 CA_P2S_RATIO = 8
2169 23:00:11.543785 DQ_CA_OPEN = 0
2170 23:00:11.547405 DQ_SEMI_OPEN = 0
2171 23:00:11.550662 CA_SEMI_OPEN = 0
2172 23:00:11.551072 CA_FULL_RATE = 0
2173 23:00:11.554631 DQ_CKDIV4_EN = 0
2174 23:00:11.557681 CA_CKDIV4_EN = 0
2175 23:00:11.560802 CA_PREDIV_EN = 0
2176 23:00:11.564286 PH8_DLY = 17
2177 23:00:11.567387 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2178 23:00:11.567792 DQ_AAMCK_DIV = 4
2179 23:00:11.570652 CA_AAMCK_DIV = 4
2180 23:00:11.574352 CA_ADMCK_DIV = 4
2181 23:00:11.577472 DQ_TRACK_CA_EN = 0
2182 23:00:11.580668 CA_PICK = 1200
2183 23:00:11.583812 CA_MCKIO = 1200
2184 23:00:11.587623 MCKIO_SEMI = 0
2185 23:00:11.588036 PLL_FREQ = 2366
2186 23:00:11.591134 DQ_UI_PI_RATIO = 32
2187 23:00:11.594046 CA_UI_PI_RATIO = 0
2188 23:00:11.597800 ===================================
2189 23:00:11.600732 ===================================
2190 23:00:11.604180 memory_type:LPDDR4
2191 23:00:11.604587 GP_NUM : 10
2192 23:00:11.607568 SRAM_EN : 1
2193 23:00:11.611163 MD32_EN : 0
2194 23:00:11.614667 ===================================
2195 23:00:11.615080 [ANA_INIT] >>>>>>>>>>>>>>
2196 23:00:11.617662 <<<<<< [CONFIGURE PHASE]: ANA_TX
2197 23:00:11.621069 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2198 23:00:11.624048 ===================================
2199 23:00:11.627791 data_rate = 2400,PCW = 0X5b00
2200 23:00:11.631142 ===================================
2201 23:00:11.634470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2202 23:00:11.640949 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 23:00:11.644438 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 23:00:11.651037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2205 23:00:11.654260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2206 23:00:11.657451 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2207 23:00:11.658068 [ANA_INIT] flow start
2208 23:00:11.660771 [ANA_INIT] PLL >>>>>>>>
2209 23:00:11.664414 [ANA_INIT] PLL <<<<<<<<
2210 23:00:11.664955 [ANA_INIT] MIDPI >>>>>>>>
2211 23:00:11.667845 [ANA_INIT] MIDPI <<<<<<<<
2212 23:00:11.670885 [ANA_INIT] DLL >>>>>>>>
2213 23:00:11.671293 [ANA_INIT] DLL <<<<<<<<
2214 23:00:11.674221 [ANA_INIT] flow end
2215 23:00:11.677501 ============ LP4 DIFF to SE enter ============
2216 23:00:11.684702 ============ LP4 DIFF to SE exit ============
2217 23:00:11.685142 [ANA_INIT] <<<<<<<<<<<<<
2218 23:00:11.687848 [Flow] Enable top DCM control >>>>>
2219 23:00:11.691248 [Flow] Enable top DCM control <<<<<
2220 23:00:11.694488 Enable DLL master slave shuffle
2221 23:00:11.701496 ==============================================================
2222 23:00:11.701975 Gating Mode config
2223 23:00:11.707738 ==============================================================
2224 23:00:11.710882 Config description:
2225 23:00:11.718310 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2226 23:00:11.724605 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2227 23:00:11.731130 SELPH_MODE 0: By rank 1: By Phase
2228 23:00:11.734429 ==============================================================
2229 23:00:11.737773 GAT_TRACK_EN = 1
2230 23:00:11.741629 RX_GATING_MODE = 2
2231 23:00:11.744597 RX_GATING_TRACK_MODE = 2
2232 23:00:11.747771 SELPH_MODE = 1
2233 23:00:11.751477 PICG_EARLY_EN = 1
2234 23:00:11.754377 VALID_LAT_VALUE = 1
2235 23:00:11.761143 ==============================================================
2236 23:00:11.764656 Enter into Gating configuration >>>>
2237 23:00:11.768072 Exit from Gating configuration <<<<
2238 23:00:11.768481 Enter into DVFS_PRE_config >>>>>
2239 23:00:11.781021 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2240 23:00:11.784408 Exit from DVFS_PRE_config <<<<<
2241 23:00:11.788169 Enter into PICG configuration >>>>
2242 23:00:11.791106 Exit from PICG configuration <<<<
2243 23:00:11.791529 [RX_INPUT] configuration >>>>>
2244 23:00:11.794880 [RX_INPUT] configuration <<<<<
2245 23:00:11.801528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2246 23:00:11.804789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2247 23:00:11.811616 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2248 23:00:11.817942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2249 23:00:11.824889 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2250 23:00:11.831084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2251 23:00:11.834907 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2252 23:00:11.837911 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2253 23:00:11.841561 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2254 23:00:11.848104 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2255 23:00:11.851421 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2256 23:00:11.855050 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2257 23:00:11.858051 ===================================
2258 23:00:11.861441 LPDDR4 DRAM CONFIGURATION
2259 23:00:11.865262 ===================================
2260 23:00:11.868225 EX_ROW_EN[0] = 0x0
2261 23:00:11.868637 EX_ROW_EN[1] = 0x0
2262 23:00:11.871476 LP4Y_EN = 0x0
2263 23:00:11.871888 WORK_FSP = 0x0
2264 23:00:11.874902 WL = 0x4
2265 23:00:11.875314 RL = 0x4
2266 23:00:11.877956 BL = 0x2
2267 23:00:11.878417 RPST = 0x0
2268 23:00:11.881758 RD_PRE = 0x0
2269 23:00:11.882171 WR_PRE = 0x1
2270 23:00:11.885024 WR_PST = 0x0
2271 23:00:11.885617 DBI_WR = 0x0
2272 23:00:11.888254 DBI_RD = 0x0
2273 23:00:11.888666 OTF = 0x1
2274 23:00:11.891512 ===================================
2275 23:00:11.894860 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2276 23:00:11.901260 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2277 23:00:11.904730 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2278 23:00:11.907986 ===================================
2279 23:00:11.911235 LPDDR4 DRAM CONFIGURATION
2280 23:00:11.914708 ===================================
2281 23:00:11.914818 EX_ROW_EN[0] = 0x10
2282 23:00:11.917791 EX_ROW_EN[1] = 0x0
2283 23:00:11.920803 LP4Y_EN = 0x0
2284 23:00:11.920895 WORK_FSP = 0x0
2285 23:00:11.924612 WL = 0x4
2286 23:00:11.924705 RL = 0x4
2287 23:00:11.927635 BL = 0x2
2288 23:00:11.927734 RPST = 0x0
2289 23:00:11.930916 RD_PRE = 0x0
2290 23:00:11.931025 WR_PRE = 0x1
2291 23:00:11.934458 WR_PST = 0x0
2292 23:00:11.934567 DBI_WR = 0x0
2293 23:00:11.937737 DBI_RD = 0x0
2294 23:00:11.937857 OTF = 0x1
2295 23:00:11.941006 ===================================
2296 23:00:11.948058 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2297 23:00:11.948208 ==
2298 23:00:11.950876 Dram Type= 6, Freq= 0, CH_0, rank 0
2299 23:00:11.954629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2300 23:00:11.954800 ==
2301 23:00:11.957718 [Duty_Offset_Calibration]
2302 23:00:11.961537 B0:2 B1:1 CA:1
2303 23:00:11.961791
2304 23:00:11.964563 [DutyScan_Calibration_Flow] k_type=0
2305 23:00:11.972972
2306 23:00:11.973521 ==CLK 0==
2307 23:00:11.976205 Final CLK duty delay cell = 0
2308 23:00:11.979913 [0] MAX Duty = 5218%(X100), DQS PI = 24
2309 23:00:11.982858 [0] MIN Duty = 4875%(X100), DQS PI = 0
2310 23:00:11.983276 [0] AVG Duty = 5046%(X100)
2311 23:00:11.986376
2312 23:00:11.986790 CH0 CLK Duty spec in!! Max-Min= 343%
2313 23:00:11.993114 [DutyScan_Calibration_Flow] ====Done====
2314 23:00:11.993527
2315 23:00:11.995951 [DutyScan_Calibration_Flow] k_type=1
2316 23:00:12.011088
2317 23:00:12.011501 ==DQS 0 ==
2318 23:00:12.014648 Final DQS duty delay cell = -4
2319 23:00:12.018231 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2320 23:00:12.021326 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2321 23:00:12.024915 [-4] AVG Duty = 4953%(X100)
2322 23:00:12.025325
2323 23:00:12.025704 ==DQS 1 ==
2324 23:00:12.028098 Final DQS duty delay cell = 0
2325 23:00:12.031234 [0] MAX Duty = 5156%(X100), DQS PI = 0
2326 23:00:12.034467 [0] MIN Duty = 5000%(X100), DQS PI = 34
2327 23:00:12.037719 [0] AVG Duty = 5078%(X100)
2328 23:00:12.038259
2329 23:00:12.041223 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2330 23:00:12.041787
2331 23:00:12.044744 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2332 23:00:12.048414 [DutyScan_Calibration_Flow] ====Done====
2333 23:00:12.048856
2334 23:00:12.051125 [DutyScan_Calibration_Flow] k_type=3
2335 23:00:12.068495
2336 23:00:12.068916 ==DQM 0 ==
2337 23:00:12.071192 Final DQM duty delay cell = 0
2338 23:00:12.074477 [0] MAX Duty = 5156%(X100), DQS PI = 30
2339 23:00:12.077760 [0] MIN Duty = 4875%(X100), DQS PI = 58
2340 23:00:12.077840 [0] AVG Duty = 5015%(X100)
2341 23:00:12.081043
2342 23:00:12.081123 ==DQM 1 ==
2343 23:00:12.084386 Final DQM duty delay cell = 0
2344 23:00:12.087601 [0] MAX Duty = 5093%(X100), DQS PI = 0
2345 23:00:12.091362 [0] MIN Duty = 5031%(X100), DQS PI = 18
2346 23:00:12.091443 [0] AVG Duty = 5062%(X100)
2347 23:00:12.091507
2348 23:00:12.098219 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2349 23:00:12.098299
2350 23:00:12.101135 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2351 23:00:12.104496 [DutyScan_Calibration_Flow] ====Done====
2352 23:00:12.104576
2353 23:00:12.108052 [DutyScan_Calibration_Flow] k_type=2
2354 23:00:12.124259
2355 23:00:12.124347 ==DQ 0 ==
2356 23:00:12.127795 Final DQ duty delay cell = 0
2357 23:00:12.131060 [0] MAX Duty = 5062%(X100), DQS PI = 32
2358 23:00:12.134519 [0] MIN Duty = 4875%(X100), DQS PI = 62
2359 23:00:12.134622 [0] AVG Duty = 4968%(X100)
2360 23:00:12.134703
2361 23:00:12.137602 ==DQ 1 ==
2362 23:00:12.140981 Final DQ duty delay cell = 0
2363 23:00:12.144706 [0] MAX Duty = 5093%(X100), DQS PI = 24
2364 23:00:12.147665 [0] MIN Duty = 4938%(X100), DQS PI = 36
2365 23:00:12.147799 [0] AVG Duty = 5015%(X100)
2366 23:00:12.147904
2367 23:00:12.151072 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2368 23:00:12.151258
2369 23:00:12.154073 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2370 23:00:12.161019 [DutyScan_Calibration_Flow] ====Done====
2371 23:00:12.161216 ==
2372 23:00:12.164247 Dram Type= 6, Freq= 0, CH_1, rank 0
2373 23:00:12.167721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2374 23:00:12.167961 ==
2375 23:00:12.171013 [Duty_Offset_Calibration]
2376 23:00:12.171306 B0:1 B1:0 CA:0
2377 23:00:12.171537
2378 23:00:12.174775 [DutyScan_Calibration_Flow] k_type=0
2379 23:00:12.183653
2380 23:00:12.184104 ==CLK 0==
2381 23:00:12.186929 Final CLK duty delay cell = -4
2382 23:00:12.190596 [-4] MAX Duty = 5000%(X100), DQS PI = 20
2383 23:00:12.193917 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2384 23:00:12.197047 [-4] AVG Duty = 4937%(X100)
2385 23:00:12.197462
2386 23:00:12.200564 CH1 CLK Duty spec in!! Max-Min= 125%
2387 23:00:12.203597 [DutyScan_Calibration_Flow] ====Done====
2388 23:00:12.204008
2389 23:00:12.207308 [DutyScan_Calibration_Flow] k_type=1
2390 23:00:12.223689
2391 23:00:12.224101 ==DQS 0 ==
2392 23:00:12.226985 Final DQS duty delay cell = 0
2393 23:00:12.230123 [0] MAX Duty = 5094%(X100), DQS PI = 24
2394 23:00:12.233674 [0] MIN Duty = 4875%(X100), DQS PI = 0
2395 23:00:12.234091 [0] AVG Duty = 4984%(X100)
2396 23:00:12.236750
2397 23:00:12.237157 ==DQS 1 ==
2398 23:00:12.240389 Final DQS duty delay cell = 0
2399 23:00:12.243568 [0] MAX Duty = 5187%(X100), DQS PI = 18
2400 23:00:12.246963 [0] MIN Duty = 4969%(X100), DQS PI = 8
2401 23:00:12.247376 [0] AVG Duty = 5078%(X100)
2402 23:00:12.247704
2403 23:00:12.253610 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2404 23:00:12.254038
2405 23:00:12.256728 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2406 23:00:12.260289 [DutyScan_Calibration_Flow] ====Done====
2407 23:00:12.260704
2408 23:00:12.263445 [DutyScan_Calibration_Flow] k_type=3
2409 23:00:12.280591
2410 23:00:12.281000 ==DQM 0 ==
2411 23:00:12.283730 Final DQM duty delay cell = 0
2412 23:00:12.286654 [0] MAX Duty = 5156%(X100), DQS PI = 6
2413 23:00:12.289950 [0] MIN Duty = 5031%(X100), DQS PI = 0
2414 23:00:12.290367 [0] AVG Duty = 5093%(X100)
2415 23:00:12.290781
2416 23:00:12.293288 ==DQM 1 ==
2417 23:00:12.296886 Final DQM duty delay cell = 0
2418 23:00:12.299924 [0] MAX Duty = 5031%(X100), DQS PI = 16
2419 23:00:12.303219 [0] MIN Duty = 4907%(X100), DQS PI = 34
2420 23:00:12.303689 [0] AVG Duty = 4969%(X100)
2421 23:00:12.304041
2422 23:00:12.309941 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2423 23:00:12.310464
2424 23:00:12.313570 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2425 23:00:12.316430 [DutyScan_Calibration_Flow] ====Done====
2426 23:00:12.316944
2427 23:00:12.320228 [DutyScan_Calibration_Flow] k_type=2
2428 23:00:12.336220
2429 23:00:12.336652 ==DQ 0 ==
2430 23:00:12.339685 Final DQ duty delay cell = -4
2431 23:00:12.342976 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2432 23:00:12.345948 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2433 23:00:12.349192 [-4] AVG Duty = 5000%(X100)
2434 23:00:12.349638
2435 23:00:12.349980 ==DQ 1 ==
2436 23:00:12.352414 Final DQ duty delay cell = 0
2437 23:00:12.355929 [0] MAX Duty = 5125%(X100), DQS PI = 20
2438 23:00:12.359183 [0] MIN Duty = 4969%(X100), DQS PI = 12
2439 23:00:12.359602 [0] AVG Duty = 5047%(X100)
2440 23:00:12.362412
2441 23:00:12.365685 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2442 23:00:12.366105
2443 23:00:12.369354 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2444 23:00:12.372420 [DutyScan_Calibration_Flow] ====Done====
2445 23:00:12.375868 nWR fixed to 30
2446 23:00:12.376286 [ModeRegInit_LP4] CH0 RK0
2447 23:00:12.379003 [ModeRegInit_LP4] CH0 RK1
2448 23:00:12.382156 [ModeRegInit_LP4] CH1 RK0
2449 23:00:12.385427 [ModeRegInit_LP4] CH1 RK1
2450 23:00:12.386003 match AC timing 7
2451 23:00:12.388898 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2452 23:00:12.396132 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2453 23:00:12.399150 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2454 23:00:12.406147 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2455 23:00:12.409036 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2456 23:00:12.409453 ==
2457 23:00:12.412420 Dram Type= 6, Freq= 0, CH_0, rank 0
2458 23:00:12.415471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2459 23:00:12.415889 ==
2460 23:00:12.422102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2461 23:00:12.429130 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2462 23:00:12.435914 [CA 0] Center 39 (8~70) winsize 63
2463 23:00:12.439585 [CA 1] Center 39 (8~70) winsize 63
2464 23:00:12.442717 [CA 2] Center 35 (5~66) winsize 62
2465 23:00:12.446178 [CA 3] Center 34 (4~65) winsize 62
2466 23:00:12.449213 [CA 4] Center 33 (3~64) winsize 62
2467 23:00:12.452616 [CA 5] Center 32 (3~62) winsize 60
2468 23:00:12.453053
2469 23:00:12.455905 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2470 23:00:12.456325
2471 23:00:12.459382 [CATrainingPosCal] consider 1 rank data
2472 23:00:12.462384 u2DelayCellTimex100 = 270/100 ps
2473 23:00:12.466255 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2474 23:00:12.469420 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2475 23:00:12.476048 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2476 23:00:12.479329 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2477 23:00:12.482587 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2478 23:00:12.486051 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2479 23:00:12.486475
2480 23:00:12.489078 CA PerBit enable=1, Macro0, CA PI delay=32
2481 23:00:12.489513
2482 23:00:12.492557 [CBTSetCACLKResult] CA Dly = 32
2483 23:00:12.492976 CS Dly: 6 (0~37)
2484 23:00:12.493322 ==
2485 23:00:12.495979 Dram Type= 6, Freq= 0, CH_0, rank 1
2486 23:00:12.502878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2487 23:00:12.503304 ==
2488 23:00:12.506207 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2489 23:00:12.512807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2490 23:00:12.521565 [CA 0] Center 38 (8~69) winsize 62
2491 23:00:12.525317 [CA 1] Center 38 (8~69) winsize 62
2492 23:00:12.528267 [CA 2] Center 35 (4~66) winsize 63
2493 23:00:12.531829 [CA 3] Center 34 (4~65) winsize 62
2494 23:00:12.535443 [CA 4] Center 33 (3~64) winsize 62
2495 23:00:12.538532 [CA 5] Center 32 (2~62) winsize 61
2496 23:00:12.538949
2497 23:00:12.541913 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2498 23:00:12.542325
2499 23:00:12.545016 [CATrainingPosCal] consider 2 rank data
2500 23:00:12.548512 u2DelayCellTimex100 = 270/100 ps
2501 23:00:12.551825 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2502 23:00:12.555051 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2503 23:00:12.561905 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2504 23:00:12.564810 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2505 23:00:12.568798 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2506 23:00:12.571811 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2507 23:00:12.572224
2508 23:00:12.575439 CA PerBit enable=1, Macro0, CA PI delay=32
2509 23:00:12.575855
2510 23:00:12.578469 [CBTSetCACLKResult] CA Dly = 32
2511 23:00:12.578884 CS Dly: 6 (0~38)
2512 23:00:12.579212
2513 23:00:12.582093 ----->DramcWriteLeveling(PI) begin...
2514 23:00:12.584891 ==
2515 23:00:12.585307 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:00:12.592105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:00:12.592518 ==
2518 23:00:12.595317 Write leveling (Byte 0): 34 => 34
2519 23:00:12.598761 Write leveling (Byte 1): 30 => 30
2520 23:00:12.602277 DramcWriteLeveling(PI) end<-----
2521 23:00:12.602705
2522 23:00:12.603039 ==
2523 23:00:12.605291 Dram Type= 6, Freq= 0, CH_0, rank 0
2524 23:00:12.608594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2525 23:00:12.609050 ==
2526 23:00:12.611979 [Gating] SW mode calibration
2527 23:00:12.618560 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2528 23:00:12.622468 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2529 23:00:12.628473 0 15 0 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
2530 23:00:12.631840 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (0 0) (1 1)
2531 23:00:12.635309 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 23:00:12.641832 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 23:00:12.645375 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 23:00:12.648452 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 23:00:12.655237 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
2536 23:00:12.658469 0 15 28 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2537 23:00:12.662263 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2538 23:00:12.668770 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 23:00:12.671992 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 23:00:12.675097 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 23:00:12.682113 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 23:00:12.685677 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 23:00:12.689145 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2544 23:00:12.692091 1 0 28 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
2545 23:00:12.698525 1 1 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
2546 23:00:12.702141 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 23:00:12.705383 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 23:00:12.711694 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 23:00:12.715502 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 23:00:12.718926 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 23:00:12.725372 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 23:00:12.728976 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 23:00:12.732146 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 23:00:12.738822 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:00:12.742227 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 23:00:12.745862 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 23:00:12.752124 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 23:00:12.755568 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 23:00:12.758829 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 23:00:12.762095 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 23:00:12.768706 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 23:00:12.772045 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 23:00:12.775332 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 23:00:12.782382 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 23:00:12.785692 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 23:00:12.788727 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 23:00:12.795251 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 23:00:12.798717 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2569 23:00:12.802422 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2570 23:00:12.805952 Total UI for P1: 0, mck2ui 16
2571 23:00:12.808944 best dqsien dly found for B0: ( 1, 3, 26)
2572 23:00:12.815222 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2573 23:00:12.815655 Total UI for P1: 0, mck2ui 16
2574 23:00:12.822082 best dqsien dly found for B1: ( 1, 4, 0)
2575 23:00:12.825371 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2576 23:00:12.828700 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2577 23:00:12.829148
2578 23:00:12.832214 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2579 23:00:12.835777 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2580 23:00:12.839428 [Gating] SW calibration Done
2581 23:00:12.839998 ==
2582 23:00:12.842540 Dram Type= 6, Freq= 0, CH_0, rank 0
2583 23:00:12.845647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2584 23:00:12.846116 ==
2585 23:00:12.849421 RX Vref Scan: 0
2586 23:00:12.849922
2587 23:00:12.850312 RX Vref 0 -> 0, step: 1
2588 23:00:12.850642
2589 23:00:12.852654 RX Delay -40 -> 252, step: 8
2590 23:00:12.855553 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2591 23:00:12.859303 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2592 23:00:12.865707 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2593 23:00:12.868818 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2594 23:00:12.872356 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2595 23:00:12.875991 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2596 23:00:12.879268 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2597 23:00:12.885574 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2598 23:00:12.889032 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2599 23:00:12.892223 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2600 23:00:12.895608 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2601 23:00:12.899029 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2602 23:00:12.905759 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2603 23:00:12.909250 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2604 23:00:12.912268 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2605 23:00:12.915827 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2606 23:00:12.916359 ==
2607 23:00:12.919105 Dram Type= 6, Freq= 0, CH_0, rank 0
2608 23:00:12.922725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2609 23:00:12.925926 ==
2610 23:00:12.926379 DQS Delay:
2611 23:00:12.926853 DQS0 = 0, DQS1 = 0
2612 23:00:12.929509 DQM Delay:
2613 23:00:12.929969 DQM0 = 121, DQM1 = 113
2614 23:00:12.932701 DQ Delay:
2615 23:00:12.935841 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2616 23:00:12.939319 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2617 23:00:12.942523 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2618 23:00:12.946098 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2619 23:00:12.946546
2620 23:00:12.946944
2621 23:00:12.947278 ==
2622 23:00:12.949703 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 23:00:12.952722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 23:00:12.953140 ==
2625 23:00:12.953487
2626 23:00:12.955924
2627 23:00:12.956505 TX Vref Scan disable
2628 23:00:12.959245 == TX Byte 0 ==
2629 23:00:12.962771 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2630 23:00:12.965620 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2631 23:00:12.969365 == TX Byte 1 ==
2632 23:00:12.972607 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2633 23:00:12.975951 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2634 23:00:12.976455 ==
2635 23:00:12.979344 Dram Type= 6, Freq= 0, CH_0, rank 0
2636 23:00:12.986154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2637 23:00:12.986731 ==
2638 23:00:12.996839 TX Vref=22, minBit 4, minWin=24, winSum=408
2639 23:00:13.000242 TX Vref=24, minBit 3, minWin=25, winSum=411
2640 23:00:13.003702 TX Vref=26, minBit 7, minWin=25, winSum=415
2641 23:00:13.006594 TX Vref=28, minBit 10, minWin=25, winSum=419
2642 23:00:13.009904 TX Vref=30, minBit 0, minWin=26, winSum=420
2643 23:00:13.013245 TX Vref=32, minBit 0, minWin=26, winSum=420
2644 23:00:13.019927 [TxChooseVref] Worse bit 0, Min win 26, Win sum 420, Final Vref 30
2645 23:00:13.020505
2646 23:00:13.023179 Final TX Range 1 Vref 30
2647 23:00:13.023602
2648 23:00:13.023932 ==
2649 23:00:13.026460 Dram Type= 6, Freq= 0, CH_0, rank 0
2650 23:00:13.030131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2651 23:00:13.030590 ==
2652 23:00:13.030962
2653 23:00:13.031276
2654 23:00:13.033208 TX Vref Scan disable
2655 23:00:13.036858 == TX Byte 0 ==
2656 23:00:13.039963 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2657 23:00:13.043377 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2658 23:00:13.046722 == TX Byte 1 ==
2659 23:00:13.050631 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2660 23:00:13.053681 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2661 23:00:13.054134
2662 23:00:13.057004 [DATLAT]
2663 23:00:13.057421 Freq=1200, CH0 RK0
2664 23:00:13.057816
2665 23:00:13.060519 DATLAT Default: 0xd
2666 23:00:13.060935 0, 0xFFFF, sum = 0
2667 23:00:13.063666 1, 0xFFFF, sum = 0
2668 23:00:13.064089 2, 0xFFFF, sum = 0
2669 23:00:13.067008 3, 0xFFFF, sum = 0
2670 23:00:13.067433 4, 0xFFFF, sum = 0
2671 23:00:13.070283 5, 0xFFFF, sum = 0
2672 23:00:13.070709 6, 0xFFFF, sum = 0
2673 23:00:13.073698 7, 0xFFFF, sum = 0
2674 23:00:13.074124 8, 0xFFFF, sum = 0
2675 23:00:13.076580 9, 0xFFFF, sum = 0
2676 23:00:13.080398 10, 0xFFFF, sum = 0
2677 23:00:13.080842 11, 0xFFFF, sum = 0
2678 23:00:13.081217 12, 0x0, sum = 1
2679 23:00:13.083229 13, 0x0, sum = 2
2680 23:00:13.083675 14, 0x0, sum = 3
2681 23:00:13.086625 15, 0x0, sum = 4
2682 23:00:13.087170 best_step = 13
2683 23:00:13.087510
2684 23:00:13.087852 ==
2685 23:00:13.090343 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 23:00:13.096616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 23:00:13.097183 ==
2688 23:00:13.097721 RX Vref Scan: 1
2689 23:00:13.098162
2690 23:00:13.099942 Set Vref Range= 32 -> 127
2691 23:00:13.100499
2692 23:00:13.103292 RX Vref 32 -> 127, step: 1
2693 23:00:13.103884
2694 23:00:13.106574 RX Delay -13 -> 252, step: 4
2695 23:00:13.107028
2696 23:00:13.110157 Set Vref, RX VrefLevel [Byte0]: 32
2697 23:00:13.113355 [Byte1]: 32
2698 23:00:13.113821
2699 23:00:13.116504 Set Vref, RX VrefLevel [Byte0]: 33
2700 23:00:13.120496 [Byte1]: 33
2701 23:00:13.121050
2702 23:00:13.123204 Set Vref, RX VrefLevel [Byte0]: 34
2703 23:00:13.127116 [Byte1]: 34
2704 23:00:13.130533
2705 23:00:13.130949 Set Vref, RX VrefLevel [Byte0]: 35
2706 23:00:13.134577 [Byte1]: 35
2707 23:00:13.138808
2708 23:00:13.139221 Set Vref, RX VrefLevel [Byte0]: 36
2709 23:00:13.141688 [Byte1]: 36
2710 23:00:13.146428
2711 23:00:13.146936 Set Vref, RX VrefLevel [Byte0]: 37
2712 23:00:13.150064 [Byte1]: 37
2713 23:00:13.154322
2714 23:00:13.154737 Set Vref, RX VrefLevel [Byte0]: 38
2715 23:00:13.157313 [Byte1]: 38
2716 23:00:13.162048
2717 23:00:13.165514 Set Vref, RX VrefLevel [Byte0]: 39
2718 23:00:13.168786 [Byte1]: 39
2719 23:00:13.169243
2720 23:00:13.171669 Set Vref, RX VrefLevel [Byte0]: 40
2721 23:00:13.175247 [Byte1]: 40
2722 23:00:13.175642
2723 23:00:13.178777 Set Vref, RX VrefLevel [Byte0]: 41
2724 23:00:13.182032 [Byte1]: 41
2725 23:00:13.185916
2726 23:00:13.186329 Set Vref, RX VrefLevel [Byte0]: 42
2727 23:00:13.189071 [Byte1]: 42
2728 23:00:13.193524
2729 23:00:13.194117 Set Vref, RX VrefLevel [Byte0]: 43
2730 23:00:13.197307 [Byte1]: 43
2731 23:00:13.201741
2732 23:00:13.202158 Set Vref, RX VrefLevel [Byte0]: 44
2733 23:00:13.204714 [Byte1]: 44
2734 23:00:13.210066
2735 23:00:13.210486 Set Vref, RX VrefLevel [Byte0]: 45
2736 23:00:13.212707 [Byte1]: 45
2737 23:00:13.217312
2738 23:00:13.217803 Set Vref, RX VrefLevel [Byte0]: 46
2739 23:00:13.220979 [Byte1]: 46
2740 23:00:13.225552
2741 23:00:13.226018 Set Vref, RX VrefLevel [Byte0]: 47
2742 23:00:13.231614 [Byte1]: 47
2743 23:00:13.232035
2744 23:00:13.235125 Set Vref, RX VrefLevel [Byte0]: 48
2745 23:00:13.238065 [Byte1]: 48
2746 23:00:13.238526
2747 23:00:13.241398 Set Vref, RX VrefLevel [Byte0]: 49
2748 23:00:13.244623 [Byte1]: 49
2749 23:00:13.248980
2750 23:00:13.249501 Set Vref, RX VrefLevel [Byte0]: 50
2751 23:00:13.252344 [Byte1]: 50
2752 23:00:13.256846
2753 23:00:13.257248 Set Vref, RX VrefLevel [Byte0]: 51
2754 23:00:13.260083 [Byte1]: 51
2755 23:00:13.264620
2756 23:00:13.265188 Set Vref, RX VrefLevel [Byte0]: 52
2757 23:00:13.267838 [Byte1]: 52
2758 23:00:13.272761
2759 23:00:13.273179 Set Vref, RX VrefLevel [Byte0]: 53
2760 23:00:13.275777 [Byte1]: 53
2761 23:00:13.280470
2762 23:00:13.280886 Set Vref, RX VrefLevel [Byte0]: 54
2763 23:00:13.283834 [Byte1]: 54
2764 23:00:13.288735
2765 23:00:13.289152 Set Vref, RX VrefLevel [Byte0]: 55
2766 23:00:13.291732 [Byte1]: 55
2767 23:00:13.296247
2768 23:00:13.296661 Set Vref, RX VrefLevel [Byte0]: 56
2769 23:00:13.299631 [Byte1]: 56
2770 23:00:13.304136
2771 23:00:13.304550 Set Vref, RX VrefLevel [Byte0]: 57
2772 23:00:13.307151 [Byte1]: 57
2773 23:00:13.312211
2774 23:00:13.312649 Set Vref, RX VrefLevel [Byte0]: 58
2775 23:00:13.315872 [Byte1]: 58
2776 23:00:13.319912
2777 23:00:13.320489 Set Vref, RX VrefLevel [Byte0]: 59
2778 23:00:13.323466 [Byte1]: 59
2779 23:00:13.327681
2780 23:00:13.328121 Set Vref, RX VrefLevel [Byte0]: 60
2781 23:00:13.331177 [Byte1]: 60
2782 23:00:13.335914
2783 23:00:13.336334 Set Vref, RX VrefLevel [Byte0]: 61
2784 23:00:13.339206 [Byte1]: 61
2785 23:00:13.343362
2786 23:00:13.343777 Set Vref, RX VrefLevel [Byte0]: 62
2787 23:00:13.347193 [Byte1]: 62
2788 23:00:13.351780
2789 23:00:13.352196 Set Vref, RX VrefLevel [Byte0]: 63
2790 23:00:13.354767 [Byte1]: 63
2791 23:00:13.359183
2792 23:00:13.359603 Set Vref, RX VrefLevel [Byte0]: 64
2793 23:00:13.363072 [Byte1]: 64
2794 23:00:13.366988
2795 23:00:13.367404 Set Vref, RX VrefLevel [Byte0]: 65
2796 23:00:13.370433 [Byte1]: 65
2797 23:00:13.375234
2798 23:00:13.375652 Set Vref, RX VrefLevel [Byte0]: 66
2799 23:00:13.378389 [Byte1]: 66
2800 23:00:13.383030
2801 23:00:13.383479 Set Vref, RX VrefLevel [Byte0]: 67
2802 23:00:13.385974 [Byte1]: 67
2803 23:00:13.390975
2804 23:00:13.391436 Set Vref, RX VrefLevel [Byte0]: 68
2805 23:00:13.394129 [Byte1]: 68
2806 23:00:13.398528
2807 23:00:13.398957 Set Vref, RX VrefLevel [Byte0]: 69
2808 23:00:13.402405 [Byte1]: 69
2809 23:00:13.406519
2810 23:00:13.406938 Set Vref, RX VrefLevel [Byte0]: 70
2811 23:00:13.409929 [Byte1]: 70
2812 23:00:13.414686
2813 23:00:13.415103 Final RX Vref Byte 0 = 54 to rank0
2814 23:00:13.417898 Final RX Vref Byte 1 = 46 to rank0
2815 23:00:13.421519 Final RX Vref Byte 0 = 54 to rank1
2816 23:00:13.424622 Final RX Vref Byte 1 = 46 to rank1==
2817 23:00:13.427928 Dram Type= 6, Freq= 0, CH_0, rank 0
2818 23:00:13.434591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2819 23:00:13.435029 ==
2820 23:00:13.435363 DQS Delay:
2821 23:00:13.435671 DQS0 = 0, DQS1 = 0
2822 23:00:13.437915 DQM Delay:
2823 23:00:13.438350 DQM0 = 120, DQM1 = 110
2824 23:00:13.441214 DQ Delay:
2825 23:00:13.444599 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2826 23:00:13.447862 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2827 23:00:13.451131 DQ8 =98, DQ9 =98, DQ10 =112, DQ11 =102
2828 23:00:13.454934 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118
2829 23:00:13.455384
2830 23:00:13.455718
2831 23:00:13.461672 [DQSOSCAuto] RK0, (LSB)MR18= 0x130d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2832 23:00:13.465021 CH0 RK0: MR19=404, MR18=130D
2833 23:00:13.471730 CH0_RK0: MR19=0x404, MR18=0x130D, DQSOSC=402, MR23=63, INC=40, DEC=27
2834 23:00:13.472150
2835 23:00:13.474755 ----->DramcWriteLeveling(PI) begin...
2836 23:00:13.475184 ==
2837 23:00:13.478559 Dram Type= 6, Freq= 0, CH_0, rank 1
2838 23:00:13.481879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2839 23:00:13.482301 ==
2840 23:00:13.485129 Write leveling (Byte 0): 34 => 34
2841 23:00:13.488331 Write leveling (Byte 1): 29 => 29
2842 23:00:13.491525 DramcWriteLeveling(PI) end<-----
2843 23:00:13.492032
2844 23:00:13.492373 ==
2845 23:00:13.494832 Dram Type= 6, Freq= 0, CH_0, rank 1
2846 23:00:13.498420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2847 23:00:13.498838 ==
2848 23:00:13.502115 [Gating] SW mode calibration
2849 23:00:13.508304 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2850 23:00:13.515017 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2851 23:00:13.518431 0 15 0 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (0 0)
2852 23:00:13.525072 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2853 23:00:13.528522 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 23:00:13.531648 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 23:00:13.538312 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 23:00:13.541783 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 23:00:13.545265 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 23:00:13.551743 0 15 28 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 0)
2859 23:00:13.555567 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
2860 23:00:13.558818 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2861 23:00:13.562151 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 23:00:13.568559 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 23:00:13.571788 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 23:00:13.575558 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 23:00:13.582337 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 23:00:13.585402 1 0 28 | B1->B0 | 3636 3434 | 0 0 | (0 0) (0 0)
2867 23:00:13.588546 1 1 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
2868 23:00:13.595483 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2869 23:00:13.598614 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 23:00:13.602084 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 23:00:13.609180 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 23:00:13.611683 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 23:00:13.615305 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 23:00:13.622109 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2875 23:00:13.625102 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 23:00:13.628672 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 23:00:13.632760 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 23:00:13.638817 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 23:00:13.642011 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 23:00:13.645289 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 23:00:13.652351 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 23:00:13.655385 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 23:00:13.658879 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 23:00:13.666003 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 23:00:13.668936 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 23:00:13.672335 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 23:00:13.678723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 23:00:13.682157 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 23:00:13.685519 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2890 23:00:13.692266 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
2891 23:00:13.695696 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2892 23:00:13.698913 Total UI for P1: 0, mck2ui 16
2893 23:00:13.702329 best dqsien dly found for B0: ( 1, 3, 30)
2894 23:00:13.705487 Total UI for P1: 0, mck2ui 16
2895 23:00:13.708891 best dqsien dly found for B1: ( 1, 3, 26)
2896 23:00:13.712193 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2897 23:00:13.715706 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
2898 23:00:13.716181
2899 23:00:13.718905 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2900 23:00:13.722548 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
2901 23:00:13.725688 [Gating] SW calibration Done
2902 23:00:13.726105 ==
2903 23:00:13.728833 Dram Type= 6, Freq= 0, CH_0, rank 1
2904 23:00:13.732345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2905 23:00:13.732763 ==
2906 23:00:13.735986 RX Vref Scan: 0
2907 23:00:13.736401
2908 23:00:13.736728 RX Vref 0 -> 0, step: 1
2909 23:00:13.738807
2910 23:00:13.739368 RX Delay -40 -> 252, step: 8
2911 23:00:13.745651 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2912 23:00:13.748994 iDelay=200, Bit 1, Center 123 (56 ~ 191) 136
2913 23:00:13.752243 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2914 23:00:13.755882 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2915 23:00:13.759063 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2916 23:00:13.762417 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2917 23:00:13.769109 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2918 23:00:13.772652 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2919 23:00:13.775665 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2920 23:00:13.779079 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2921 23:00:13.782581 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2922 23:00:13.789035 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2923 23:00:13.792695 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2924 23:00:13.796009 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2925 23:00:13.799355 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2926 23:00:13.802830 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2927 23:00:13.805972 ==
2928 23:00:13.809014 Dram Type= 6, Freq= 0, CH_0, rank 1
2929 23:00:13.812518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2930 23:00:13.812981 ==
2931 23:00:13.813455 DQS Delay:
2932 23:00:13.815947 DQS0 = 0, DQS1 = 0
2933 23:00:13.816324 DQM Delay:
2934 23:00:13.818993 DQM0 = 122, DQM1 = 112
2935 23:00:13.819584 DQ Delay:
2936 23:00:13.822318 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2937 23:00:13.825697 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2938 23:00:13.828948 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2939 23:00:13.832326 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
2940 23:00:13.832748
2941 23:00:13.833098
2942 23:00:13.833458 ==
2943 23:00:13.836107 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 23:00:13.842351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 23:00:13.842801 ==
2946 23:00:13.843187
2947 23:00:13.843512
2948 23:00:13.843843 TX Vref Scan disable
2949 23:00:13.845794 == TX Byte 0 ==
2950 23:00:13.849354 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2951 23:00:13.852711 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2952 23:00:13.856052 == TX Byte 1 ==
2953 23:00:13.859276 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2954 23:00:13.862987 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2955 23:00:13.866000 ==
2956 23:00:13.866440 Dram Type= 6, Freq= 0, CH_0, rank 1
2957 23:00:13.872846 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2958 23:00:13.873360 ==
2959 23:00:13.884147 TX Vref=22, minBit 5, minWin=24, winSum=408
2960 23:00:13.887553 TX Vref=24, minBit 3, minWin=25, winSum=418
2961 23:00:13.890921 TX Vref=26, minBit 13, minWin=25, winSum=419
2962 23:00:13.894362 TX Vref=28, minBit 1, minWin=26, winSum=424
2963 23:00:13.897921 TX Vref=30, minBit 5, minWin=25, winSum=423
2964 23:00:13.901052 TX Vref=32, minBit 5, minWin=25, winSum=421
2965 23:00:13.907507 [TxChooseVref] Worse bit 1, Min win 26, Win sum 424, Final Vref 28
2966 23:00:13.907953
2967 23:00:13.911100 Final TX Range 1 Vref 28
2968 23:00:13.911515
2969 23:00:13.911842 ==
2970 23:00:13.914750 Dram Type= 6, Freq= 0, CH_0, rank 1
2971 23:00:13.917480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2972 23:00:13.917959 ==
2973 23:00:13.918325
2974 23:00:13.920766
2975 23:00:13.921270 TX Vref Scan disable
2976 23:00:13.924773 == TX Byte 0 ==
2977 23:00:13.927841 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2978 23:00:13.930996 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2979 23:00:13.934334 == TX Byte 1 ==
2980 23:00:13.938022 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2981 23:00:13.940867 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2982 23:00:13.944456
2983 23:00:13.945020 [DATLAT]
2984 23:00:13.945412 Freq=1200, CH0 RK1
2985 23:00:13.945823
2986 23:00:13.947641 DATLAT Default: 0xd
2987 23:00:13.948116 0, 0xFFFF, sum = 0
2988 23:00:13.950916 1, 0xFFFF, sum = 0
2989 23:00:13.951362 2, 0xFFFF, sum = 0
2990 23:00:13.954230 3, 0xFFFF, sum = 0
2991 23:00:13.954815 4, 0xFFFF, sum = 0
2992 23:00:13.958003 5, 0xFFFF, sum = 0
2993 23:00:13.958624 6, 0xFFFF, sum = 0
2994 23:00:13.961326 7, 0xFFFF, sum = 0
2995 23:00:13.964431 8, 0xFFFF, sum = 0
2996 23:00:13.965003 9, 0xFFFF, sum = 0
2997 23:00:13.967619 10, 0xFFFF, sum = 0
2998 23:00:13.968040 11, 0xFFFF, sum = 0
2999 23:00:13.970954 12, 0x0, sum = 1
3000 23:00:13.971433 13, 0x0, sum = 2
3001 23:00:13.974644 14, 0x0, sum = 3
3002 23:00:13.975096 15, 0x0, sum = 4
3003 23:00:13.975477 best_step = 13
3004 23:00:13.975790
3005 23:00:13.977640 ==
3006 23:00:13.978064 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 23:00:13.984340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 23:00:13.984888 ==
3009 23:00:13.985403 RX Vref Scan: 0
3010 23:00:13.985898
3011 23:00:13.987903 RX Vref 0 -> 0, step: 1
3012 23:00:13.988460
3013 23:00:13.991125 RX Delay -13 -> 252, step: 4
3014 23:00:13.994218 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3015 23:00:13.997880 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3016 23:00:14.005059 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3017 23:00:14.008139 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3018 23:00:14.011029 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3019 23:00:14.014720 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3020 23:00:14.018174 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3021 23:00:14.024693 iDelay=195, Bit 7, Center 128 (63 ~ 194) 132
3022 23:00:14.028046 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3023 23:00:14.031387 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3024 23:00:14.034737 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3025 23:00:14.037816 iDelay=195, Bit 11, Center 100 (35 ~ 166) 132
3026 23:00:14.044757 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3027 23:00:14.047688 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3028 23:00:14.051176 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3029 23:00:14.054864 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3030 23:00:14.055287 ==
3031 23:00:14.058074 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 23:00:14.061212 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 23:00:14.064693 ==
3034 23:00:14.065115 DQS Delay:
3035 23:00:14.065446 DQS0 = 0, DQS1 = 0
3036 23:00:14.067819 DQM Delay:
3037 23:00:14.068384 DQM0 = 121, DQM1 = 109
3038 23:00:14.071709 DQ Delay:
3039 23:00:14.074485 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3040 23:00:14.077987 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128
3041 23:00:14.081339 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100
3042 23:00:14.085537 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118
3043 23:00:14.086150
3044 23:00:14.086626
3045 23:00:14.091543 [DQSOSCAuto] RK1, (LSB)MR18= 0x11f2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 403 ps
3046 23:00:14.094629 CH0 RK1: MR19=403, MR18=11F2
3047 23:00:14.101131 CH0_RK1: MR19=0x403, MR18=0x11F2, DQSOSC=403, MR23=63, INC=40, DEC=26
3048 23:00:14.104475 [RxdqsGatingPostProcess] freq 1200
3049 23:00:14.111317 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3050 23:00:14.111869 best DQS0 dly(2T, 0.5T) = (0, 11)
3051 23:00:14.114659 best DQS1 dly(2T, 0.5T) = (0, 12)
3052 23:00:14.118074 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3053 23:00:14.121318 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3054 23:00:14.124605 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 23:00:14.127975 best DQS1 dly(2T, 0.5T) = (0, 11)
3056 23:00:14.131583 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 23:00:14.134925 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3058 23:00:14.137989 Pre-setting of DQS Precalculation
3059 23:00:14.141280 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3060 23:00:14.144960 ==
3061 23:00:14.148828 Dram Type= 6, Freq= 0, CH_1, rank 0
3062 23:00:14.151618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 23:00:14.152138 ==
3064 23:00:14.154899 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3065 23:00:14.161467 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3066 23:00:14.170789 [CA 0] Center 37 (7~68) winsize 62
3067 23:00:14.174260 [CA 1] Center 37 (7~68) winsize 62
3068 23:00:14.177510 [CA 2] Center 35 (5~65) winsize 61
3069 23:00:14.180497 [CA 3] Center 35 (5~65) winsize 61
3070 23:00:14.184013 [CA 4] Center 34 (5~64) winsize 60
3071 23:00:14.187340 [CA 5] Center 33 (3~63) winsize 61
3072 23:00:14.187751
3073 23:00:14.190958 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3074 23:00:14.191374
3075 23:00:14.193878 [CATrainingPosCal] consider 1 rank data
3076 23:00:14.197622 u2DelayCellTimex100 = 270/100 ps
3077 23:00:14.200787 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3078 23:00:14.203959 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3079 23:00:14.210511 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3080 23:00:14.214431 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3081 23:00:14.217355 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3082 23:00:14.220912 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3083 23:00:14.221339
3084 23:00:14.224386 CA PerBit enable=1, Macro0, CA PI delay=33
3085 23:00:14.224802
3086 23:00:14.227887 [CBTSetCACLKResult] CA Dly = 33
3087 23:00:14.228300 CS Dly: 8 (0~39)
3088 23:00:14.228897 ==
3089 23:00:14.230995 Dram Type= 6, Freq= 0, CH_1, rank 1
3090 23:00:14.237555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3091 23:00:14.238010 ==
3092 23:00:14.240849 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3093 23:00:14.247655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3094 23:00:14.256403 [CA 0] Center 37 (7~68) winsize 62
3095 23:00:14.260322 [CA 1] Center 37 (7~68) winsize 62
3096 23:00:14.262949 [CA 2] Center 35 (5~65) winsize 61
3097 23:00:14.266203 [CA 3] Center 34 (4~65) winsize 62
3098 23:00:14.269838 [CA 4] Center 34 (4~65) winsize 62
3099 23:00:14.273050 [CA 5] Center 33 (4~63) winsize 60
3100 23:00:14.273462
3101 23:00:14.276207 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3102 23:00:14.276620
3103 23:00:14.279731 [CATrainingPosCal] consider 2 rank data
3104 23:00:14.282978 u2DelayCellTimex100 = 270/100 ps
3105 23:00:14.286234 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3106 23:00:14.289923 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3107 23:00:14.293146 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3108 23:00:14.299629 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
3109 23:00:14.303105 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3110 23:00:14.306348 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3111 23:00:14.306757
3112 23:00:14.309883 CA PerBit enable=1, Macro0, CA PI delay=33
3113 23:00:14.310330
3114 23:00:14.312876 [CBTSetCACLKResult] CA Dly = 33
3115 23:00:14.313287 CS Dly: 8 (0~40)
3116 23:00:14.313643
3117 23:00:14.316732 ----->DramcWriteLeveling(PI) begin...
3118 23:00:14.317145 ==
3119 23:00:14.319741 Dram Type= 6, Freq= 0, CH_1, rank 0
3120 23:00:14.326574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3121 23:00:14.327013 ==
3122 23:00:14.329651 Write leveling (Byte 0): 25 => 25
3123 23:00:14.332930 Write leveling (Byte 1): 27 => 27
3124 23:00:14.333341 DramcWriteLeveling(PI) end<-----
3125 23:00:14.336504
3126 23:00:14.336963 ==
3127 23:00:14.340163 Dram Type= 6, Freq= 0, CH_1, rank 0
3128 23:00:14.343222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3129 23:00:14.343637 ==
3130 23:00:14.346564 [Gating] SW mode calibration
3131 23:00:14.353035 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3132 23:00:14.356729 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3133 23:00:14.363109 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3134 23:00:14.366558 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3135 23:00:14.369708 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 23:00:14.377140 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 23:00:14.380074 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 23:00:14.383752 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 23:00:14.389719 0 15 24 | B1->B0 | 3131 2a2a | 0 0 | (0 1) (0 1)
3140 23:00:14.393299 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
3141 23:00:14.396793 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3142 23:00:14.403041 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3143 23:00:14.406661 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 23:00:14.409875 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 23:00:14.417023 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 23:00:14.420024 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3147 23:00:14.423008 1 0 24 | B1->B0 | 3838 4545 | 0 0 | (0 0) (0 0)
3148 23:00:14.427124 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 23:00:14.433238 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 23:00:14.436878 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3151 23:00:14.439651 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 23:00:14.446585 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 23:00:14.450403 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 23:00:14.453693 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 23:00:14.460511 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3156 23:00:14.463346 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 23:00:14.467191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 23:00:14.473649 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 23:00:14.476812 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 23:00:14.479788 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 23:00:14.486553 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 23:00:14.490111 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 23:00:14.493247 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 23:00:14.496772 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 23:00:14.503461 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 23:00:14.506663 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 23:00:14.510515 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 23:00:14.516736 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 23:00:14.520468 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 23:00:14.523350 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 23:00:14.530414 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3172 23:00:14.533848 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3173 23:00:14.536902 Total UI for P1: 0, mck2ui 16
3174 23:00:14.540167 best dqsien dly found for B0: ( 1, 3, 24)
3175 23:00:14.544029 Total UI for P1: 0, mck2ui 16
3176 23:00:14.547014 best dqsien dly found for B1: ( 1, 3, 24)
3177 23:00:14.550653 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3178 23:00:14.553659 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3179 23:00:14.554072
3180 23:00:14.557023 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3181 23:00:14.560252 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3182 23:00:14.563343 [Gating] SW calibration Done
3183 23:00:14.563768 ==
3184 23:00:14.566627 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 23:00:14.570006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 23:00:14.573811 ==
3187 23:00:14.574223 RX Vref Scan: 0
3188 23:00:14.574549
3189 23:00:14.577012 RX Vref 0 -> 0, step: 1
3190 23:00:14.577423
3191 23:00:14.577787 RX Delay -40 -> 252, step: 8
3192 23:00:14.583730 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3193 23:00:14.587136 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3194 23:00:14.590110 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3195 23:00:14.593478 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3196 23:00:14.597068 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3197 23:00:14.603717 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3198 23:00:14.606784 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3199 23:00:14.610655 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3200 23:00:14.613856 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3201 23:00:14.616899 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3202 23:00:14.624111 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3203 23:00:14.627081 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3204 23:00:14.630511 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3205 23:00:14.633718 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3206 23:00:14.637094 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3207 23:00:14.644211 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3208 23:00:14.644645 ==
3209 23:00:14.647411 Dram Type= 6, Freq= 0, CH_1, rank 0
3210 23:00:14.651088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3211 23:00:14.651628 ==
3212 23:00:14.652079 DQS Delay:
3213 23:00:14.653781 DQS0 = 0, DQS1 = 0
3214 23:00:14.654206 DQM Delay:
3215 23:00:14.657032 DQM0 = 120, DQM1 = 116
3216 23:00:14.657465 DQ Delay:
3217 23:00:14.660605 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3218 23:00:14.663838 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =119
3219 23:00:14.667353 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3220 23:00:14.670462 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3221 23:00:14.670892
3222 23:00:14.671327
3223 23:00:14.673655 ==
3224 23:00:14.674088 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 23:00:14.680485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 23:00:14.680918 ==
3227 23:00:14.681358
3228 23:00:14.681839
3229 23:00:14.683860 TX Vref Scan disable
3230 23:00:14.684287 == TX Byte 0 ==
3231 23:00:14.687429 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3232 23:00:14.693683 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3233 23:00:14.694128 == TX Byte 1 ==
3234 23:00:14.697133 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3235 23:00:14.704044 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3236 23:00:14.704555 ==
3237 23:00:14.707280 Dram Type= 6, Freq= 0, CH_1, rank 0
3238 23:00:14.710410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3239 23:00:14.710841 ==
3240 23:00:14.722471 TX Vref=22, minBit 11, minWin=24, winSum=409
3241 23:00:14.725833 TX Vref=24, minBit 9, minWin=24, winSum=417
3242 23:00:14.729330 TX Vref=26, minBit 9, minWin=25, winSum=420
3243 23:00:14.732712 TX Vref=28, minBit 1, minWin=26, winSum=427
3244 23:00:14.735736 TX Vref=30, minBit 1, minWin=26, winSum=427
3245 23:00:14.742074 TX Vref=32, minBit 10, minWin=26, winSum=433
3246 23:00:14.745435 [TxChooseVref] Worse bit 10, Min win 26, Win sum 433, Final Vref 32
3247 23:00:14.745889
3248 23:00:14.748986 Final TX Range 1 Vref 32
3249 23:00:14.749416
3250 23:00:14.749901 ==
3251 23:00:14.752223 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 23:00:14.755705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 23:00:14.756136 ==
3254 23:00:14.758761
3255 23:00:14.759188
3256 23:00:14.759627 TX Vref Scan disable
3257 23:00:14.762539 == TX Byte 0 ==
3258 23:00:14.765289 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3259 23:00:14.768877 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3260 23:00:14.772257 == TX Byte 1 ==
3261 23:00:14.776370 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3262 23:00:14.779489 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3263 23:00:14.779920
3264 23:00:14.782511 [DATLAT]
3265 23:00:14.782940 Freq=1200, CH1 RK0
3266 23:00:14.783380
3267 23:00:14.785684 DATLAT Default: 0xd
3268 23:00:14.786111 0, 0xFFFF, sum = 0
3269 23:00:14.789118 1, 0xFFFF, sum = 0
3270 23:00:14.789547 2, 0xFFFF, sum = 0
3271 23:00:14.792578 3, 0xFFFF, sum = 0
3272 23:00:14.793009 4, 0xFFFF, sum = 0
3273 23:00:14.795616 5, 0xFFFF, sum = 0
3274 23:00:14.796052 6, 0xFFFF, sum = 0
3275 23:00:14.799684 7, 0xFFFF, sum = 0
3276 23:00:14.800118 8, 0xFFFF, sum = 0
3277 23:00:14.802367 9, 0xFFFF, sum = 0
3278 23:00:14.802782 10, 0xFFFF, sum = 0
3279 23:00:14.806230 11, 0xFFFF, sum = 0
3280 23:00:14.806650 12, 0x0, sum = 1
3281 23:00:14.809494 13, 0x0, sum = 2
3282 23:00:14.809947 14, 0x0, sum = 3
3283 23:00:14.812471 15, 0x0, sum = 4
3284 23:00:14.812887 best_step = 13
3285 23:00:14.813216
3286 23:00:14.813519 ==
3287 23:00:14.815771 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 23:00:14.822708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 23:00:14.823132 ==
3290 23:00:14.823469 RX Vref Scan: 1
3291 23:00:14.823780
3292 23:00:14.825607 Set Vref Range= 32 -> 127
3293 23:00:14.826028
3294 23:00:14.829370 RX Vref 32 -> 127, step: 1
3295 23:00:14.829825
3296 23:00:14.832661 RX Delay -5 -> 252, step: 4
3297 23:00:14.833075
3298 23:00:14.836139 Set Vref, RX VrefLevel [Byte0]: 32
3299 23:00:14.836566 [Byte1]: 32
3300 23:00:14.840540
3301 23:00:14.841060 Set Vref, RX VrefLevel [Byte0]: 33
3302 23:00:14.844075 [Byte1]: 33
3303 23:00:14.848847
3304 23:00:14.849254 Set Vref, RX VrefLevel [Byte0]: 34
3305 23:00:14.852022 [Byte1]: 34
3306 23:00:14.856184
3307 23:00:14.856593 Set Vref, RX VrefLevel [Byte0]: 35
3308 23:00:14.859544 [Byte1]: 35
3309 23:00:14.864122
3310 23:00:14.864544 Set Vref, RX VrefLevel [Byte0]: 36
3311 23:00:14.867292 [Byte1]: 36
3312 23:00:14.871974
3313 23:00:14.872381 Set Vref, RX VrefLevel [Byte0]: 37
3314 23:00:14.875226 [Byte1]: 37
3315 23:00:14.880149
3316 23:00:14.880558 Set Vref, RX VrefLevel [Byte0]: 38
3317 23:00:14.883182 [Byte1]: 38
3318 23:00:14.888084
3319 23:00:14.888492 Set Vref, RX VrefLevel [Byte0]: 39
3320 23:00:14.890695 [Byte1]: 39
3321 23:00:14.895369
3322 23:00:14.895777 Set Vref, RX VrefLevel [Byte0]: 40
3323 23:00:14.899013 [Byte1]: 40
3324 23:00:14.903068
3325 23:00:14.903641 Set Vref, RX VrefLevel [Byte0]: 41
3326 23:00:14.906494 [Byte1]: 41
3327 23:00:14.910868
3328 23:00:14.911275 Set Vref, RX VrefLevel [Byte0]: 42
3329 23:00:14.914664 [Byte1]: 42
3330 23:00:14.918754
3331 23:00:14.919160 Set Vref, RX VrefLevel [Byte0]: 43
3332 23:00:14.922473 [Byte1]: 43
3333 23:00:14.926945
3334 23:00:14.927350 Set Vref, RX VrefLevel [Byte0]: 44
3335 23:00:14.930348 [Byte1]: 44
3336 23:00:14.934623
3337 23:00:14.935028 Set Vref, RX VrefLevel [Byte0]: 45
3338 23:00:14.938077 [Byte1]: 45
3339 23:00:14.942859
3340 23:00:14.943265 Set Vref, RX VrefLevel [Byte0]: 46
3341 23:00:14.946041 [Byte1]: 46
3342 23:00:14.950818
3343 23:00:14.951330 Set Vref, RX VrefLevel [Byte0]: 47
3344 23:00:14.954163 [Byte1]: 47
3345 23:00:14.958070
3346 23:00:14.958479 Set Vref, RX VrefLevel [Byte0]: 48
3347 23:00:14.961542 [Byte1]: 48
3348 23:00:14.966217
3349 23:00:14.966628 Set Vref, RX VrefLevel [Byte0]: 49
3350 23:00:14.969538 [Byte1]: 49
3351 23:00:14.974110
3352 23:00:14.974524 Set Vref, RX VrefLevel [Byte0]: 50
3353 23:00:14.977742 [Byte1]: 50
3354 23:00:14.981702
3355 23:00:14.982149 Set Vref, RX VrefLevel [Byte0]: 51
3356 23:00:14.985169 [Byte1]: 51
3357 23:00:14.989821
3358 23:00:14.990232 Set Vref, RX VrefLevel [Byte0]: 52
3359 23:00:14.993107 [Byte1]: 52
3360 23:00:14.997765
3361 23:00:14.998176 Set Vref, RX VrefLevel [Byte0]: 53
3362 23:00:15.000896 [Byte1]: 53
3363 23:00:15.005547
3364 23:00:15.005990 Set Vref, RX VrefLevel [Byte0]: 54
3365 23:00:15.009210 [Byte1]: 54
3366 23:00:15.013345
3367 23:00:15.013804 Set Vref, RX VrefLevel [Byte0]: 55
3368 23:00:15.016848 [Byte1]: 55
3369 23:00:15.021068
3370 23:00:15.021673 Set Vref, RX VrefLevel [Byte0]: 56
3371 23:00:15.024372 [Byte1]: 56
3372 23:00:15.028850
3373 23:00:15.029258 Set Vref, RX VrefLevel [Byte0]: 57
3374 23:00:15.032120 [Byte1]: 57
3375 23:00:15.037040
3376 23:00:15.037556 Set Vref, RX VrefLevel [Byte0]: 58
3377 23:00:15.043013 [Byte1]: 58
3378 23:00:15.043421
3379 23:00:15.046428 Set Vref, RX VrefLevel [Byte0]: 59
3380 23:00:15.049871 [Byte1]: 59
3381 23:00:15.050284
3382 23:00:15.053205 Set Vref, RX VrefLevel [Byte0]: 60
3383 23:00:15.056275 [Byte1]: 60
3384 23:00:15.060013
3385 23:00:15.060429 Set Vref, RX VrefLevel [Byte0]: 61
3386 23:00:15.063528 [Byte1]: 61
3387 23:00:15.068103
3388 23:00:15.068512 Set Vref, RX VrefLevel [Byte0]: 62
3389 23:00:15.071559 [Byte1]: 62
3390 23:00:15.075864
3391 23:00:15.076275 Set Vref, RX VrefLevel [Byte0]: 63
3392 23:00:15.079243 [Byte1]: 63
3393 23:00:15.084167
3394 23:00:15.084580 Set Vref, RX VrefLevel [Byte0]: 64
3395 23:00:15.087060 [Byte1]: 64
3396 23:00:15.092088
3397 23:00:15.092500 Set Vref, RX VrefLevel [Byte0]: 65
3398 23:00:15.094908 [Byte1]: 65
3399 23:00:15.099399
3400 23:00:15.099809 Set Vref, RX VrefLevel [Byte0]: 66
3401 23:00:15.103097 [Byte1]: 66
3402 23:00:15.107690
3403 23:00:15.108102 Set Vref, RX VrefLevel [Byte0]: 67
3404 23:00:15.110902 [Byte1]: 67
3405 23:00:15.115411
3406 23:00:15.115822 Set Vref, RX VrefLevel [Byte0]: 68
3407 23:00:15.118910 [Byte1]: 68
3408 23:00:15.123191
3409 23:00:15.123630 Final RX Vref Byte 0 = 54 to rank0
3410 23:00:15.126885 Final RX Vref Byte 1 = 48 to rank0
3411 23:00:15.129862 Final RX Vref Byte 0 = 54 to rank1
3412 23:00:15.133409 Final RX Vref Byte 1 = 48 to rank1==
3413 23:00:15.136836 Dram Type= 6, Freq= 0, CH_1, rank 0
3414 23:00:15.143020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3415 23:00:15.143447 ==
3416 23:00:15.143779 DQS Delay:
3417 23:00:15.144137 DQS0 = 0, DQS1 = 0
3418 23:00:15.146620 DQM Delay:
3419 23:00:15.147034 DQM0 = 119, DQM1 = 116
3420 23:00:15.149929 DQ Delay:
3421 23:00:15.153371 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116
3422 23:00:15.156449 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3423 23:00:15.159723 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3424 23:00:15.163004 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3425 23:00:15.163420
3426 23:00:15.163750
3427 23:00:15.169985 [DQSOSCAuto] RK0, (LSB)MR18= 0xfd10, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 411 ps
3428 23:00:15.173393 CH1 RK0: MR19=304, MR18=FD10
3429 23:00:15.180143 CH1_RK0: MR19=0x304, MR18=0xFD10, DQSOSC=403, MR23=63, INC=40, DEC=26
3430 23:00:15.180560
3431 23:00:15.183417 ----->DramcWriteLeveling(PI) begin...
3432 23:00:15.183835 ==
3433 23:00:15.186901 Dram Type= 6, Freq= 0, CH_1, rank 1
3434 23:00:15.189859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3435 23:00:15.193573 ==
3436 23:00:15.194034 Write leveling (Byte 0): 26 => 26
3437 23:00:15.196466 Write leveling (Byte 1): 29 => 29
3438 23:00:15.199900 DramcWriteLeveling(PI) end<-----
3439 23:00:15.200325
3440 23:00:15.200756 ==
3441 23:00:15.203163 Dram Type= 6, Freq= 0, CH_1, rank 1
3442 23:00:15.209787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3443 23:00:15.210219 ==
3444 23:00:15.210659 [Gating] SW mode calibration
3445 23:00:15.219890 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3446 23:00:15.223172 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3447 23:00:15.226782 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3448 23:00:15.233737 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3449 23:00:15.236821 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3450 23:00:15.239957 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3451 23:00:15.246742 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3452 23:00:15.249989 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3453 23:00:15.253199 0 15 24 | B1->B0 | 2a2a 3434 | 0 1 | (0 1) (1 0)
3454 23:00:15.259971 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3455 23:00:15.262877 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3456 23:00:15.266759 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3457 23:00:15.272845 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3458 23:00:15.276380 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3459 23:00:15.279800 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3460 23:00:15.286390 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3461 23:00:15.289665 1 0 24 | B1->B0 | 4545 3333 | 0 1 | (0 0) (0 0)
3462 23:00:15.293039 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3463 23:00:15.299839 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3464 23:00:15.303168 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3465 23:00:15.306348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3466 23:00:15.312942 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3467 23:00:15.316512 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3468 23:00:15.319725 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3469 23:00:15.326310 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3470 23:00:15.329319 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 23:00:15.332680 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 23:00:15.339563 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 23:00:15.342673 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 23:00:15.345852 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 23:00:15.352877 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 23:00:15.355977 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 23:00:15.359437 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 23:00:15.366173 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3479 23:00:15.369260 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3480 23:00:15.372299 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3481 23:00:15.379170 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3482 23:00:15.382407 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3483 23:00:15.385536 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3484 23:00:15.391972 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3485 23:00:15.395400 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3486 23:00:15.398512 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3487 23:00:15.401751 Total UI for P1: 0, mck2ui 16
3488 23:00:15.405521 best dqsien dly found for B1: ( 1, 3, 22)
3489 23:00:15.411793 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3490 23:00:15.412223 Total UI for P1: 0, mck2ui 16
3491 23:00:15.415006 best dqsien dly found for B0: ( 1, 3, 28)
3492 23:00:15.421824 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3493 23:00:15.425461 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3494 23:00:15.425942
3495 23:00:15.428311 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3496 23:00:15.432058 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3497 23:00:15.434838 [Gating] SW calibration Done
3498 23:00:15.435257 ==
3499 23:00:15.438758 Dram Type= 6, Freq= 0, CH_1, rank 1
3500 23:00:15.441644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3501 23:00:15.442092 ==
3502 23:00:15.444890 RX Vref Scan: 0
3503 23:00:15.445315
3504 23:00:15.445856 RX Vref 0 -> 0, step: 1
3505 23:00:15.446201
3506 23:00:15.448694 RX Delay -40 -> 252, step: 8
3507 23:00:15.452244 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3508 23:00:15.459023 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3509 23:00:15.462115 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3510 23:00:15.465804 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3511 23:00:15.468531 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3512 23:00:15.472173 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3513 23:00:15.478311 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3514 23:00:15.481070 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3515 23:00:15.485101 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3516 23:00:15.488228 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3517 23:00:15.491624 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3518 23:00:15.497901 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3519 23:00:15.501052 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3520 23:00:15.504355 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3521 23:00:15.507672 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3522 23:00:15.510864 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3523 23:00:15.514086 ==
3524 23:00:15.517619 Dram Type= 6, Freq= 0, CH_1, rank 1
3525 23:00:15.520587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3526 23:00:15.520753 ==
3527 23:00:15.520887 DQS Delay:
3528 23:00:15.524043 DQS0 = 0, DQS1 = 0
3529 23:00:15.524210 DQM Delay:
3530 23:00:15.527407 DQM0 = 121, DQM1 = 119
3531 23:00:15.527600 DQ Delay:
3532 23:00:15.531152 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3533 23:00:15.534316 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3534 23:00:15.537946 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3535 23:00:15.541441 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3536 23:00:15.541909
3537 23:00:15.542246
3538 23:00:15.544226 ==
3539 23:00:15.544653 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 23:00:15.550962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 23:00:15.551375 ==
3542 23:00:15.551742
3543 23:00:15.552060
3544 23:00:15.553837 TX Vref Scan disable
3545 23:00:15.554253 == TX Byte 0 ==
3546 23:00:15.557942 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3547 23:00:15.564297 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3548 23:00:15.564812 == TX Byte 1 ==
3549 23:00:15.567523 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3550 23:00:15.573728 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3551 23:00:15.574142 ==
3552 23:00:15.577225 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 23:00:15.580390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 23:00:15.580801 ==
3555 23:00:15.592458 TX Vref=22, minBit 9, minWin=25, winSum=421
3556 23:00:15.595983 TX Vref=24, minBit 2, minWin=26, winSum=424
3557 23:00:15.599460 TX Vref=26, minBit 8, minWin=26, winSum=430
3558 23:00:15.603021 TX Vref=28, minBit 8, minWin=26, winSum=432
3559 23:00:15.606172 TX Vref=30, minBit 9, minWin=26, winSum=437
3560 23:00:15.612570 TX Vref=32, minBit 9, minWin=26, winSum=439
3561 23:00:15.616121 [TxChooseVref] Worse bit 9, Min win 26, Win sum 439, Final Vref 32
3562 23:00:15.616533
3563 23:00:15.619327 Final TX Range 1 Vref 32
3564 23:00:15.619737
3565 23:00:15.620116 ==
3566 23:00:15.622329 Dram Type= 6, Freq= 0, CH_1, rank 1
3567 23:00:15.626000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3568 23:00:15.626459 ==
3569 23:00:15.629225
3570 23:00:15.629823
3571 23:00:15.630266 TX Vref Scan disable
3572 23:00:15.632872 == TX Byte 0 ==
3573 23:00:15.636009 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3574 23:00:15.639134 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3575 23:00:15.642548 == TX Byte 1 ==
3576 23:00:15.645876 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3577 23:00:15.649489 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3578 23:00:15.652811
3579 23:00:15.653221 [DATLAT]
3580 23:00:15.653548 Freq=1200, CH1 RK1
3581 23:00:15.653889
3582 23:00:15.655877 DATLAT Default: 0xd
3583 23:00:15.656287 0, 0xFFFF, sum = 0
3584 23:00:15.659129 1, 0xFFFF, sum = 0
3585 23:00:15.659551 2, 0xFFFF, sum = 0
3586 23:00:15.662744 3, 0xFFFF, sum = 0
3587 23:00:15.663165 4, 0xFFFF, sum = 0
3588 23:00:15.665806 5, 0xFFFF, sum = 0
3589 23:00:15.669017 6, 0xFFFF, sum = 0
3590 23:00:15.669446 7, 0xFFFF, sum = 0
3591 23:00:15.672386 8, 0xFFFF, sum = 0
3592 23:00:15.672906 9, 0xFFFF, sum = 0
3593 23:00:15.675682 10, 0xFFFF, sum = 0
3594 23:00:15.676097 11, 0xFFFF, sum = 0
3595 23:00:15.679242 12, 0x0, sum = 1
3596 23:00:15.679660 13, 0x0, sum = 2
3597 23:00:15.682482 14, 0x0, sum = 3
3598 23:00:15.682897 15, 0x0, sum = 4
3599 23:00:15.683229 best_step = 13
3600 23:00:15.683533
3601 23:00:15.685757 ==
3602 23:00:15.689264 Dram Type= 6, Freq= 0, CH_1, rank 1
3603 23:00:15.692507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3604 23:00:15.692984 ==
3605 23:00:15.693356 RX Vref Scan: 0
3606 23:00:15.693810
3607 23:00:15.695987 RX Vref 0 -> 0, step: 1
3608 23:00:15.696395
3609 23:00:15.698668 RX Delay -5 -> 252, step: 4
3610 23:00:15.702618 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3611 23:00:15.709378 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3612 23:00:15.712271 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3613 23:00:15.715436 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3614 23:00:15.718615 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3615 23:00:15.722604 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3616 23:00:15.728721 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3617 23:00:15.731877 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3618 23:00:15.735192 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3619 23:00:15.738710 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3620 23:00:15.742054 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3621 23:00:15.748600 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3622 23:00:15.752019 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3623 23:00:15.755360 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3624 23:00:15.758703 iDelay=195, Bit 14, Center 122 (63 ~ 182) 120
3625 23:00:15.762038 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3626 23:00:15.765092 ==
3627 23:00:15.768718 Dram Type= 6, Freq= 0, CH_1, rank 1
3628 23:00:15.772023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3629 23:00:15.772443 ==
3630 23:00:15.772936 DQS Delay:
3631 23:00:15.775286 DQS0 = 0, DQS1 = 0
3632 23:00:15.775736 DQM Delay:
3633 23:00:15.778313 DQM0 = 120, DQM1 = 116
3634 23:00:15.778966 DQ Delay:
3635 23:00:15.781542 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3636 23:00:15.784812 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3637 23:00:15.788335 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3638 23:00:15.791988 DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =124
3639 23:00:15.792399
3640 23:00:15.792724
3641 23:00:15.801852 [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps
3642 23:00:15.804988 CH1 RK1: MR19=403, MR18=11EE
3643 23:00:15.808339 CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26
3644 23:00:15.811276 [RxdqsGatingPostProcess] freq 1200
3645 23:00:15.818726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3646 23:00:15.821458 best DQS0 dly(2T, 0.5T) = (0, 11)
3647 23:00:15.824790 best DQS1 dly(2T, 0.5T) = (0, 11)
3648 23:00:15.828570 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3649 23:00:15.831325 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3650 23:00:15.834658 best DQS0 dly(2T, 0.5T) = (0, 11)
3651 23:00:15.838247 best DQS1 dly(2T, 0.5T) = (0, 11)
3652 23:00:15.841635 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3653 23:00:15.844797 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3654 23:00:15.845355 Pre-setting of DQS Precalculation
3655 23:00:15.851589 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3656 23:00:15.857949 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3657 23:00:15.864665 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3658 23:00:15.865151
3659 23:00:15.865481
3660 23:00:15.868160 [Calibration Summary] 2400 Mbps
3661 23:00:15.871289 CH 0, Rank 0
3662 23:00:15.871696 SW Impedance : PASS
3663 23:00:15.874850 DUTY Scan : NO K
3664 23:00:15.878271 ZQ Calibration : PASS
3665 23:00:15.878683 Jitter Meter : NO K
3666 23:00:15.881317 CBT Training : PASS
3667 23:00:15.884622 Write leveling : PASS
3668 23:00:15.885032 RX DQS gating : PASS
3669 23:00:15.887812 RX DQ/DQS(RDDQC) : PASS
3670 23:00:15.891414 TX DQ/DQS : PASS
3671 23:00:15.891827 RX DATLAT : PASS
3672 23:00:15.894338 RX DQ/DQS(Engine): PASS
3673 23:00:15.898086 TX OE : NO K
3674 23:00:15.898514 All Pass.
3675 23:00:15.898847
3676 23:00:15.899152 CH 0, Rank 1
3677 23:00:15.901132 SW Impedance : PASS
3678 23:00:15.901544 DUTY Scan : NO K
3679 23:00:15.904389 ZQ Calibration : PASS
3680 23:00:15.907989 Jitter Meter : NO K
3681 23:00:15.908447 CBT Training : PASS
3682 23:00:15.911633 Write leveling : PASS
3683 23:00:15.914237 RX DQS gating : PASS
3684 23:00:15.914677 RX DQ/DQS(RDDQC) : PASS
3685 23:00:15.917502 TX DQ/DQS : PASS
3686 23:00:15.920970 RX DATLAT : PASS
3687 23:00:15.921384 RX DQ/DQS(Engine): PASS
3688 23:00:15.924578 TX OE : NO K
3689 23:00:15.924992 All Pass.
3690 23:00:15.925321
3691 23:00:15.927625 CH 1, Rank 0
3692 23:00:15.928035 SW Impedance : PASS
3693 23:00:15.931090 DUTY Scan : NO K
3694 23:00:15.934497 ZQ Calibration : PASS
3695 23:00:15.934913 Jitter Meter : NO K
3696 23:00:15.937658 CBT Training : PASS
3697 23:00:15.940953 Write leveling : PASS
3698 23:00:15.941512 RX DQS gating : PASS
3699 23:00:15.944042 RX DQ/DQS(RDDQC) : PASS
3700 23:00:15.947819 TX DQ/DQS : PASS
3701 23:00:15.948233 RX DATLAT : PASS
3702 23:00:15.951377 RX DQ/DQS(Engine): PASS
3703 23:00:15.951789 TX OE : NO K
3704 23:00:15.954393 All Pass.
3705 23:00:15.954806
3706 23:00:15.955137 CH 1, Rank 1
3707 23:00:15.957828 SW Impedance : PASS
3708 23:00:15.958237 DUTY Scan : NO K
3709 23:00:15.961068 ZQ Calibration : PASS
3710 23:00:15.964370 Jitter Meter : NO K
3711 23:00:15.964780 CBT Training : PASS
3712 23:00:15.967993 Write leveling : PASS
3713 23:00:15.971193 RX DQS gating : PASS
3714 23:00:15.971759 RX DQ/DQS(RDDQC) : PASS
3715 23:00:15.974233 TX DQ/DQS : PASS
3716 23:00:15.977648 RX DATLAT : PASS
3717 23:00:15.978062 RX DQ/DQS(Engine): PASS
3718 23:00:15.980794 TX OE : NO K
3719 23:00:15.981231 All Pass.
3720 23:00:15.981741
3721 23:00:15.984032 DramC Write-DBI off
3722 23:00:15.987637 PER_BANK_REFRESH: Hybrid Mode
3723 23:00:15.988157 TX_TRACKING: ON
3724 23:00:15.997555 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3725 23:00:16.000632 [FAST_K] Save calibration result to emmc
3726 23:00:16.004147 dramc_set_vcore_voltage set vcore to 650000
3727 23:00:16.007597 Read voltage for 600, 5
3728 23:00:16.008123 Vio18 = 0
3729 23:00:16.008456 Vcore = 650000
3730 23:00:16.010829 Vdram = 0
3731 23:00:16.011345 Vddq = 0
3732 23:00:16.011673 Vmddr = 0
3733 23:00:16.017699 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3734 23:00:16.021080 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3735 23:00:16.024189 MEM_TYPE=3, freq_sel=19
3736 23:00:16.027031 sv_algorithm_assistance_LP4_1600
3737 23:00:16.030824 ============ PULL DRAM RESETB DOWN ============
3738 23:00:16.033893 ========== PULL DRAM RESETB DOWN end =========
3739 23:00:16.040451 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3740 23:00:16.043763 ===================================
3741 23:00:16.046955 LPDDR4 DRAM CONFIGURATION
3742 23:00:16.050558 ===================================
3743 23:00:16.050975 EX_ROW_EN[0] = 0x0
3744 23:00:16.053705 EX_ROW_EN[1] = 0x0
3745 23:00:16.054126 LP4Y_EN = 0x0
3746 23:00:16.057334 WORK_FSP = 0x0
3747 23:00:16.057776 WL = 0x2
3748 23:00:16.060302 RL = 0x2
3749 23:00:16.060719 BL = 0x2
3750 23:00:16.063490 RPST = 0x0
3751 23:00:16.063904 RD_PRE = 0x0
3752 23:00:16.067100 WR_PRE = 0x1
3753 23:00:16.067540 WR_PST = 0x0
3754 23:00:16.070333 DBI_WR = 0x0
3755 23:00:16.070743 DBI_RD = 0x0
3756 23:00:16.073776 OTF = 0x1
3757 23:00:16.076794 ===================================
3758 23:00:16.080041 ===================================
3759 23:00:16.080453 ANA top config
3760 23:00:16.084158 ===================================
3761 23:00:16.087290 DLL_ASYNC_EN = 0
3762 23:00:16.090434 ALL_SLAVE_EN = 1
3763 23:00:16.093550 NEW_RANK_MODE = 1
3764 23:00:16.094043 DLL_IDLE_MODE = 1
3765 23:00:16.096954 LP45_APHY_COMB_EN = 1
3766 23:00:16.100207 TX_ODT_DIS = 1
3767 23:00:16.103516 NEW_8X_MODE = 1
3768 23:00:16.107145 ===================================
3769 23:00:16.110171 ===================================
3770 23:00:16.113517 data_rate = 1200
3771 23:00:16.113969 CKR = 1
3772 23:00:16.116797 DQ_P2S_RATIO = 8
3773 23:00:16.120171 ===================================
3774 23:00:16.123412 CA_P2S_RATIO = 8
3775 23:00:16.126792 DQ_CA_OPEN = 0
3776 23:00:16.130075 DQ_SEMI_OPEN = 0
3777 23:00:16.133506 CA_SEMI_OPEN = 0
3778 23:00:16.134017 CA_FULL_RATE = 0
3779 23:00:16.136807 DQ_CKDIV4_EN = 1
3780 23:00:16.139936 CA_CKDIV4_EN = 1
3781 23:00:16.143575 CA_PREDIV_EN = 0
3782 23:00:16.147007 PH8_DLY = 0
3783 23:00:16.150391 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3784 23:00:16.150807 DQ_AAMCK_DIV = 4
3785 23:00:16.153869 CA_AAMCK_DIV = 4
3786 23:00:16.156908 CA_ADMCK_DIV = 4
3787 23:00:16.160432 DQ_TRACK_CA_EN = 0
3788 23:00:16.163523 CA_PICK = 600
3789 23:00:16.167019 CA_MCKIO = 600
3790 23:00:16.167447 MCKIO_SEMI = 0
3791 23:00:16.169956 PLL_FREQ = 2288
3792 23:00:16.173352 DQ_UI_PI_RATIO = 32
3793 23:00:16.177144 CA_UI_PI_RATIO = 0
3794 23:00:16.180139 ===================================
3795 23:00:16.183324 ===================================
3796 23:00:16.186398 memory_type:LPDDR4
3797 23:00:16.186810 GP_NUM : 10
3798 23:00:16.190056 SRAM_EN : 1
3799 23:00:16.193189 MD32_EN : 0
3800 23:00:16.196613 ===================================
3801 23:00:16.197114 [ANA_INIT] >>>>>>>>>>>>>>
3802 23:00:16.200018 <<<<<< [CONFIGURE PHASE]: ANA_TX
3803 23:00:16.203334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3804 23:00:16.206509 ===================================
3805 23:00:16.209844 data_rate = 1200,PCW = 0X5800
3806 23:00:16.213334 ===================================
3807 23:00:16.216178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3808 23:00:16.223264 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3809 23:00:16.226210 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3810 23:00:16.232804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3811 23:00:16.236366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3812 23:00:16.239570 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3813 23:00:16.242918 [ANA_INIT] flow start
3814 23:00:16.243332 [ANA_INIT] PLL >>>>>>>>
3815 23:00:16.246273 [ANA_INIT] PLL <<<<<<<<
3816 23:00:16.249468 [ANA_INIT] MIDPI >>>>>>>>
3817 23:00:16.249963 [ANA_INIT] MIDPI <<<<<<<<
3818 23:00:16.252799 [ANA_INIT] DLL >>>>>>>>
3819 23:00:16.256196 [ANA_INIT] flow end
3820 23:00:16.259429 ============ LP4 DIFF to SE enter ============
3821 23:00:16.262740 ============ LP4 DIFF to SE exit ============
3822 23:00:16.266183 [ANA_INIT] <<<<<<<<<<<<<
3823 23:00:16.269267 [Flow] Enable top DCM control >>>>>
3824 23:00:16.273251 [Flow] Enable top DCM control <<<<<
3825 23:00:16.276192 Enable DLL master slave shuffle
3826 23:00:16.279757 ==============================================================
3827 23:00:16.282956 Gating Mode config
3828 23:00:16.289620 ==============================================================
3829 23:00:16.290231 Config description:
3830 23:00:16.299224 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3831 23:00:16.306295 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3832 23:00:16.309527 SELPH_MODE 0: By rank 1: By Phase
3833 23:00:16.316362 ==============================================================
3834 23:00:16.319356 GAT_TRACK_EN = 1
3835 23:00:16.322364 RX_GATING_MODE = 2
3836 23:00:16.325779 RX_GATING_TRACK_MODE = 2
3837 23:00:16.329232 SELPH_MODE = 1
3838 23:00:16.332898 PICG_EARLY_EN = 1
3839 23:00:16.336345 VALID_LAT_VALUE = 1
3840 23:00:16.339109 ==============================================================
3841 23:00:16.342450 Enter into Gating configuration >>>>
3842 23:00:16.345998 Exit from Gating configuration <<<<
3843 23:00:16.349296 Enter into DVFS_PRE_config >>>>>
3844 23:00:16.362170 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3845 23:00:16.362595 Exit from DVFS_PRE_config <<<<<
3846 23:00:16.365501 Enter into PICG configuration >>>>
3847 23:00:16.368826 Exit from PICG configuration <<<<
3848 23:00:16.372359 [RX_INPUT] configuration >>>>>
3849 23:00:16.376209 [RX_INPUT] configuration <<<<<
3850 23:00:16.382290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3851 23:00:16.385463 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3852 23:00:16.392300 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3853 23:00:16.398633 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3854 23:00:16.405412 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3855 23:00:16.411997 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3856 23:00:16.415391 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3857 23:00:16.418682 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3858 23:00:16.421965 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3859 23:00:16.428269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3860 23:00:16.431672 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3861 23:00:16.435259 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3862 23:00:16.438237 ===================================
3863 23:00:16.441712 LPDDR4 DRAM CONFIGURATION
3864 23:00:16.444862 ===================================
3865 23:00:16.445149 EX_ROW_EN[0] = 0x0
3866 23:00:16.448362 EX_ROW_EN[1] = 0x0
3867 23:00:16.451832 LP4Y_EN = 0x0
3868 23:00:16.451997 WORK_FSP = 0x0
3869 23:00:16.454994 WL = 0x2
3870 23:00:16.455182 RL = 0x2
3871 23:00:16.458237 BL = 0x2
3872 23:00:16.458395 RPST = 0x0
3873 23:00:16.461529 RD_PRE = 0x0
3874 23:00:16.461707 WR_PRE = 0x1
3875 23:00:16.465182 WR_PST = 0x0
3876 23:00:16.465380 DBI_WR = 0x0
3877 23:00:16.467968 DBI_RD = 0x0
3878 23:00:16.468134 OTF = 0x1
3879 23:00:16.471782 ===================================
3880 23:00:16.475062 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3881 23:00:16.481214 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3882 23:00:16.485070 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3883 23:00:16.488293 ===================================
3884 23:00:16.491622 LPDDR4 DRAM CONFIGURATION
3885 23:00:16.494797 ===================================
3886 23:00:16.494927 EX_ROW_EN[0] = 0x10
3887 23:00:16.498046 EX_ROW_EN[1] = 0x0
3888 23:00:16.498186 LP4Y_EN = 0x0
3889 23:00:16.501348 WORK_FSP = 0x0
3890 23:00:16.504637 WL = 0x2
3891 23:00:16.504763 RL = 0x2
3892 23:00:16.508179 BL = 0x2
3893 23:00:16.508312 RPST = 0x0
3894 23:00:16.511278 RD_PRE = 0x0
3895 23:00:16.511406 WR_PRE = 0x1
3896 23:00:16.514734 WR_PST = 0x0
3897 23:00:16.514861 DBI_WR = 0x0
3898 23:00:16.518062 DBI_RD = 0x0
3899 23:00:16.518205 OTF = 0x1
3900 23:00:16.521287 ===================================
3901 23:00:16.528027 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3902 23:00:16.531660 nWR fixed to 30
3903 23:00:16.535318 [ModeRegInit_LP4] CH0 RK0
3904 23:00:16.535516 [ModeRegInit_LP4] CH0 RK1
3905 23:00:16.538491 [ModeRegInit_LP4] CH1 RK0
3906 23:00:16.542095 [ModeRegInit_LP4] CH1 RK1
3907 23:00:16.542285 match AC timing 17
3908 23:00:16.548411 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3909 23:00:16.551668 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3910 23:00:16.555500 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3911 23:00:16.562159 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3912 23:00:16.565330 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3913 23:00:16.565517 ==
3914 23:00:16.568390 Dram Type= 6, Freq= 0, CH_0, rank 0
3915 23:00:16.571702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3916 23:00:16.571978 ==
3917 23:00:16.578361 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3918 23:00:16.585510 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3919 23:00:16.588995 [CA 0] Center 36 (5~67) winsize 63
3920 23:00:16.591727 [CA 1] Center 36 (5~67) winsize 63
3921 23:00:16.595109 [CA 2] Center 34 (3~65) winsize 63
3922 23:00:16.598999 [CA 3] Center 33 (3~64) winsize 62
3923 23:00:16.602273 [CA 4] Center 33 (2~64) winsize 63
3924 23:00:16.605657 [CA 5] Center 32 (2~63) winsize 62
3925 23:00:16.606075
3926 23:00:16.608745 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3927 23:00:16.609158
3928 23:00:16.611859 [CATrainingPosCal] consider 1 rank data
3929 23:00:16.615298 u2DelayCellTimex100 = 270/100 ps
3930 23:00:16.618663 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3931 23:00:16.621970 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3932 23:00:16.625080 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3933 23:00:16.628229 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3934 23:00:16.631722 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3935 23:00:16.638400 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3936 23:00:16.638995
3937 23:00:16.641670 CA PerBit enable=1, Macro0, CA PI delay=32
3938 23:00:16.642048
3939 23:00:16.645097 [CBTSetCACLKResult] CA Dly = 32
3940 23:00:16.645692 CS Dly: 3 (0~34)
3941 23:00:16.646073 ==
3942 23:00:16.648455 Dram Type= 6, Freq= 0, CH_0, rank 1
3943 23:00:16.651655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3944 23:00:16.654874 ==
3945 23:00:16.658266 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3946 23:00:16.665341 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3947 23:00:16.668665 [CA 0] Center 35 (5~66) winsize 62
3948 23:00:16.671458 [CA 1] Center 35 (5~66) winsize 62
3949 23:00:16.675065 [CA 2] Center 34 (3~65) winsize 63
3950 23:00:16.678221 [CA 3] Center 34 (3~65) winsize 63
3951 23:00:16.681930 [CA 4] Center 33 (2~64) winsize 63
3952 23:00:16.684986 [CA 5] Center 32 (2~63) winsize 62
3953 23:00:16.685632
3954 23:00:16.688269 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3955 23:00:16.688878
3956 23:00:16.691392 [CATrainingPosCal] consider 2 rank data
3957 23:00:16.694849 u2DelayCellTimex100 = 270/100 ps
3958 23:00:16.698002 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3959 23:00:16.701535 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3960 23:00:16.704589 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
3961 23:00:16.711386 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3962 23:00:16.715090 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3963 23:00:16.718014 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3964 23:00:16.718425
3965 23:00:16.721263 CA PerBit enable=1, Macro0, CA PI delay=32
3966 23:00:16.721715
3967 23:00:16.725115 [CBTSetCACLKResult] CA Dly = 32
3968 23:00:16.725524 CS Dly: 4 (0~36)
3969 23:00:16.725887
3970 23:00:16.727943 ----->DramcWriteLeveling(PI) begin...
3971 23:00:16.728357 ==
3972 23:00:16.731704 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 23:00:16.738487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 23:00:16.738899 ==
3975 23:00:16.741813 Write leveling (Byte 0): 34 => 34
3976 23:00:16.744604 Write leveling (Byte 1): 34 => 34
3977 23:00:16.745010 DramcWriteLeveling(PI) end<-----
3978 23:00:16.748117
3979 23:00:16.748629 ==
3980 23:00:16.751480 Dram Type= 6, Freq= 0, CH_0, rank 0
3981 23:00:16.754447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3982 23:00:16.754861 ==
3983 23:00:16.758331 [Gating] SW mode calibration
3984 23:00:16.764386 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3985 23:00:16.767866 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3986 23:00:16.774324 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3987 23:00:16.777739 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3988 23:00:16.781310 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3989 23:00:16.787693 0 9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)
3990 23:00:16.791039 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
3991 23:00:16.794811 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3992 23:00:16.801502 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3993 23:00:16.804582 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3994 23:00:16.808166 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3995 23:00:16.814507 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3996 23:00:16.818017 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3997 23:00:16.820954 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (1 1)
3998 23:00:16.827930 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
3999 23:00:16.830922 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4000 23:00:16.834695 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4001 23:00:16.841182 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4002 23:00:16.844470 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4003 23:00:16.847772 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4004 23:00:16.854244 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4005 23:00:16.857474 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4006 23:00:16.860917 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4007 23:00:16.864525 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 23:00:16.870816 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 23:00:16.874165 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 23:00:16.877514 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 23:00:16.884207 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 23:00:16.887626 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 23:00:16.890798 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4014 23:00:16.897898 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4015 23:00:16.900635 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4016 23:00:16.904056 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4017 23:00:16.911388 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4018 23:00:16.914775 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4019 23:00:16.917806 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4020 23:00:16.924289 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4021 23:00:16.927577 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4022 23:00:16.930640 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4023 23:00:16.934364 Total UI for P1: 0, mck2ui 16
4024 23:00:16.937858 best dqsien dly found for B0: ( 0, 13, 12)
4025 23:00:16.944058 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4026 23:00:16.944509 Total UI for P1: 0, mck2ui 16
4027 23:00:16.947893 best dqsien dly found for B1: ( 0, 13, 16)
4028 23:00:16.950974 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4029 23:00:16.957951 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4030 23:00:16.958380
4031 23:00:16.961018 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4032 23:00:16.963987 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4033 23:00:16.967272 [Gating] SW calibration Done
4034 23:00:16.967352 ==
4035 23:00:16.970793 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 23:00:16.974504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 23:00:16.974584 ==
4038 23:00:16.977557 RX Vref Scan: 0
4039 23:00:16.977650
4040 23:00:16.977719 RX Vref 0 -> 0, step: 1
4041 23:00:16.977782
4042 23:00:16.980927 RX Delay -230 -> 252, step: 16
4043 23:00:16.984157 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4044 23:00:16.990902 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4045 23:00:16.994022 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4046 23:00:16.997391 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4047 23:00:17.000898 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4048 23:00:17.004291 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4049 23:00:17.010766 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4050 23:00:17.013970 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4051 23:00:17.017395 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4052 23:00:17.020816 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4053 23:00:17.027555 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4054 23:00:17.031454 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4055 23:00:17.033958 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4056 23:00:17.037683 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4057 23:00:17.043952 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4058 23:00:17.047346 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4059 23:00:17.047437 ==
4060 23:00:17.050583 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 23:00:17.053973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 23:00:17.054053 ==
4063 23:00:17.054118 DQS Delay:
4064 23:00:17.056992 DQS0 = 0, DQS1 = 0
4065 23:00:17.057067 DQM Delay:
4066 23:00:17.060478 DQM0 = 53, DQM1 = 46
4067 23:00:17.060546 DQ Delay:
4068 23:00:17.064100 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49
4069 23:00:17.067493 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4070 23:00:17.070483 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =49
4071 23:00:17.074168 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4072 23:00:17.074273
4073 23:00:17.074356
4074 23:00:17.074430 ==
4075 23:00:17.077248 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 23:00:17.080845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 23:00:17.083901 ==
4078 23:00:17.084010
4079 23:00:17.084096
4080 23:00:17.084177 TX Vref Scan disable
4081 23:00:17.087212 == TX Byte 0 ==
4082 23:00:17.090802 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4083 23:00:17.093744 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4084 23:00:17.096886 == TX Byte 1 ==
4085 23:00:17.100640 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4086 23:00:17.104094 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4087 23:00:17.107543 ==
4088 23:00:17.111075 Dram Type= 6, Freq= 0, CH_0, rank 0
4089 23:00:17.113815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4090 23:00:17.114108 ==
4091 23:00:17.114300
4092 23:00:17.114554
4093 23:00:17.117471 TX Vref Scan disable
4094 23:00:17.117881 == TX Byte 0 ==
4095 23:00:17.123894 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4096 23:00:17.126860 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4097 23:00:17.126948 == TX Byte 1 ==
4098 23:00:17.133492 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4099 23:00:17.136862 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4100 23:00:17.136943
4101 23:00:17.137018 [DATLAT]
4102 23:00:17.140336 Freq=600, CH0 RK0
4103 23:00:17.140417
4104 23:00:17.140480 DATLAT Default: 0x9
4105 23:00:17.143583 0, 0xFFFF, sum = 0
4106 23:00:17.143666 1, 0xFFFF, sum = 0
4107 23:00:17.146830 2, 0xFFFF, sum = 0
4108 23:00:17.146912 3, 0xFFFF, sum = 0
4109 23:00:17.150355 4, 0xFFFF, sum = 0
4110 23:00:17.153568 5, 0xFFFF, sum = 0
4111 23:00:17.153663 6, 0xFFFF, sum = 0
4112 23:00:17.156733 7, 0xFFFF, sum = 0
4113 23:00:17.156857 8, 0x0, sum = 1
4114 23:00:17.156937 9, 0x0, sum = 2
4115 23:00:17.160048 10, 0x0, sum = 3
4116 23:00:17.160162 11, 0x0, sum = 4
4117 23:00:17.163784 best_step = 9
4118 23:00:17.163912
4119 23:00:17.163994 ==
4120 23:00:17.167192 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 23:00:17.170343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 23:00:17.170507 ==
4123 23:00:17.173380 RX Vref Scan: 1
4124 23:00:17.173553
4125 23:00:17.173694 RX Vref 0 -> 0, step: 1
4126 23:00:17.173799
4127 23:00:17.176916 RX Delay -163 -> 252, step: 8
4128 23:00:17.177138
4129 23:00:17.180130 Set Vref, RX VrefLevel [Byte0]: 54
4130 23:00:17.183235 [Byte1]: 46
4131 23:00:17.187358
4132 23:00:17.187535 Final RX Vref Byte 0 = 54 to rank0
4133 23:00:17.191122 Final RX Vref Byte 1 = 46 to rank0
4134 23:00:17.194327 Final RX Vref Byte 0 = 54 to rank1
4135 23:00:17.197858 Final RX Vref Byte 1 = 46 to rank1==
4136 23:00:17.200838 Dram Type= 6, Freq= 0, CH_0, rank 0
4137 23:00:17.207665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4138 23:00:17.208053 ==
4139 23:00:17.208359 DQS Delay:
4140 23:00:17.208646 DQS0 = 0, DQS1 = 0
4141 23:00:17.210706 DQM Delay:
4142 23:00:17.211147 DQM0 = 53, DQM1 = 48
4143 23:00:17.214451 DQ Delay:
4144 23:00:17.217906 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4145 23:00:17.218325 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =56
4146 23:00:17.221137 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4147 23:00:17.227793 DQ12 =52, DQ13 =52, DQ14 =60, DQ15 =56
4148 23:00:17.228209
4149 23:00:17.228540
4150 23:00:17.234423 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4151 23:00:17.237791 CH0 RK0: MR19=808, MR18=6F62
4152 23:00:17.244465 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4153 23:00:17.244890
4154 23:00:17.247560 ----->DramcWriteLeveling(PI) begin...
4155 23:00:17.247986 ==
4156 23:00:17.251132 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 23:00:17.254534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 23:00:17.254983 ==
4159 23:00:17.258010 Write leveling (Byte 0): 37 => 37
4160 23:00:17.261014 Write leveling (Byte 1): 32 => 32
4161 23:00:17.264256 DramcWriteLeveling(PI) end<-----
4162 23:00:17.264673
4163 23:00:17.265002 ==
4164 23:00:17.267350 Dram Type= 6, Freq= 0, CH_0, rank 1
4165 23:00:17.270705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4166 23:00:17.271147 ==
4167 23:00:17.274091 [Gating] SW mode calibration
4168 23:00:17.280592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4169 23:00:17.287306 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4170 23:00:17.290861 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4171 23:00:17.294103 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4172 23:00:17.300437 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4173 23:00:17.303907 0 9 12 | B1->B0 | 3434 3434 | 0 0 | (0 1) (0 0)
4174 23:00:17.307055 0 9 16 | B1->B0 | 2a2a 2626 | 0 0 | (0 0) (0 0)
4175 23:00:17.314003 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4176 23:00:17.317690 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4177 23:00:17.320288 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4178 23:00:17.327532 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4179 23:00:17.330461 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 23:00:17.334082 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 23:00:17.340857 0 10 12 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
4182 23:00:17.344205 0 10 16 | B1->B0 | 3b3b 4444 | 0 0 | (0 0) (0 0)
4183 23:00:17.347346 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4184 23:00:17.353965 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4185 23:00:17.356982 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4186 23:00:17.360665 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4187 23:00:17.367086 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4188 23:00:17.370315 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4189 23:00:17.374066 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4190 23:00:17.380309 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4191 23:00:17.383916 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 23:00:17.387047 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 23:00:17.393791 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 23:00:17.397054 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 23:00:17.400650 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 23:00:17.407060 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 23:00:17.410273 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 23:00:17.413536 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 23:00:17.417121 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 23:00:17.423737 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 23:00:17.426973 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 23:00:17.430208 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 23:00:17.436799 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 23:00:17.440573 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 23:00:17.443888 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4206 23:00:17.450332 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4207 23:00:17.453507 Total UI for P1: 0, mck2ui 16
4208 23:00:17.456848 best dqsien dly found for B0: ( 0, 13, 12)
4209 23:00:17.457285 Total UI for P1: 0, mck2ui 16
4210 23:00:17.464209 best dqsien dly found for B1: ( 0, 13, 14)
4211 23:00:17.466741 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4212 23:00:17.470267 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4213 23:00:17.470352
4214 23:00:17.473369 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4215 23:00:17.476718 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4216 23:00:17.480335 [Gating] SW calibration Done
4217 23:00:17.480428 ==
4218 23:00:17.483215 Dram Type= 6, Freq= 0, CH_0, rank 1
4219 23:00:17.487039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4220 23:00:17.487148 ==
4221 23:00:17.490051 RX Vref Scan: 0
4222 23:00:17.490160
4223 23:00:17.490247 RX Vref 0 -> 0, step: 1
4224 23:00:17.490327
4225 23:00:17.493321 RX Delay -230 -> 252, step: 16
4226 23:00:17.500248 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4227 23:00:17.503060 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4228 23:00:17.506533 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4229 23:00:17.509968 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4230 23:00:17.513888 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4231 23:00:17.520092 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4232 23:00:17.523794 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4233 23:00:17.526830 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4234 23:00:17.529907 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4235 23:00:17.536718 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4236 23:00:17.539743 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4237 23:00:17.543458 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4238 23:00:17.546708 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4239 23:00:17.553029 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4240 23:00:17.556348 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4241 23:00:17.559739 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4242 23:00:17.560152 ==
4243 23:00:17.563326 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 23:00:17.566537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 23:00:17.569887 ==
4246 23:00:17.570303 DQS Delay:
4247 23:00:17.570629 DQS0 = 0, DQS1 = 0
4248 23:00:17.573010 DQM Delay:
4249 23:00:17.573419 DQM0 = 52, DQM1 = 44
4250 23:00:17.576622 DQ Delay:
4251 23:00:17.577029 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4252 23:00:17.579574 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4253 23:00:17.583099 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4254 23:00:17.586340 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4255 23:00:17.586752
4256 23:00:17.589866
4257 23:00:17.590273 ==
4258 23:00:17.593183 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 23:00:17.596420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 23:00:17.596866 ==
4261 23:00:17.597192
4262 23:00:17.597493
4263 23:00:17.599526 TX Vref Scan disable
4264 23:00:17.599932 == TX Byte 0 ==
4265 23:00:17.606182 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4266 23:00:17.610120 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4267 23:00:17.610534 == TX Byte 1 ==
4268 23:00:17.616702 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4269 23:00:17.620109 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4270 23:00:17.620523 ==
4271 23:00:17.623161 Dram Type= 6, Freq= 0, CH_0, rank 1
4272 23:00:17.626231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4273 23:00:17.626644 ==
4274 23:00:17.627050
4275 23:00:17.627368
4276 23:00:17.629323 TX Vref Scan disable
4277 23:00:17.633077 == TX Byte 0 ==
4278 23:00:17.636232 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4279 23:00:17.639556 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4280 23:00:17.643006 == TX Byte 1 ==
4281 23:00:17.645870 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4282 23:00:17.649214 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4283 23:00:17.652516
4284 23:00:17.652926 [DATLAT]
4285 23:00:17.653363 Freq=600, CH0 RK1
4286 23:00:17.653761
4287 23:00:17.656092 DATLAT Default: 0x9
4288 23:00:17.656505 0, 0xFFFF, sum = 0
4289 23:00:17.659248 1, 0xFFFF, sum = 0
4290 23:00:17.659669 2, 0xFFFF, sum = 0
4291 23:00:17.662403 3, 0xFFFF, sum = 0
4292 23:00:17.662819 4, 0xFFFF, sum = 0
4293 23:00:17.666080 5, 0xFFFF, sum = 0
4294 23:00:17.666497 6, 0xFFFF, sum = 0
4295 23:00:17.669363 7, 0xFFFF, sum = 0
4296 23:00:17.669858 8, 0x0, sum = 1
4297 23:00:17.672668 9, 0x0, sum = 2
4298 23:00:17.673086 10, 0x0, sum = 3
4299 23:00:17.675753 11, 0x0, sum = 4
4300 23:00:17.676174 best_step = 9
4301 23:00:17.676500
4302 23:00:17.676803 ==
4303 23:00:17.679157 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 23:00:17.685615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 23:00:17.686175 ==
4306 23:00:17.686620 RX Vref Scan: 0
4307 23:00:17.687080
4308 23:00:17.689459 RX Vref 0 -> 0, step: 1
4309 23:00:17.690080
4310 23:00:17.692844 RX Delay -163 -> 252, step: 8
4311 23:00:17.695622 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4312 23:00:17.702453 iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280
4313 23:00:17.705682 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4314 23:00:17.708908 iDelay=197, Bit 3, Center 48 (-99 ~ 196) 296
4315 23:00:17.712184 iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280
4316 23:00:17.715799 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4317 23:00:17.719008 iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272
4318 23:00:17.725200 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4319 23:00:17.728723 iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280
4320 23:00:17.732304 iDelay=197, Bit 9, Center 32 (-107 ~ 172) 280
4321 23:00:17.735536 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4322 23:00:17.742422 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4323 23:00:17.745660 iDelay=197, Bit 12, Center 52 (-83 ~ 188) 272
4324 23:00:17.749110 iDelay=197, Bit 13, Center 48 (-91 ~ 188) 280
4325 23:00:17.752121 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4326 23:00:17.755735 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4327 23:00:17.756199 ==
4328 23:00:17.759374 Dram Type= 6, Freq= 0, CH_0, rank 1
4329 23:00:17.765851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4330 23:00:17.766268 ==
4331 23:00:17.766596 DQS Delay:
4332 23:00:17.768957 DQS0 = 0, DQS1 = 0
4333 23:00:17.769369 DQM Delay:
4334 23:00:17.769760 DQM0 = 53, DQM1 = 46
4335 23:00:17.772299 DQ Delay:
4336 23:00:17.775638 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =48
4337 23:00:17.779162 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4338 23:00:17.782168 DQ8 =40, DQ9 =32, DQ10 =48, DQ11 =40
4339 23:00:17.785555 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4340 23:00:17.786072
4341 23:00:17.786434
4342 23:00:17.792482 [DQSOSCAuto] RK1, (LSB)MR18= 0x6223, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4343 23:00:17.795555 CH0 RK1: MR19=808, MR18=6223
4344 23:00:17.801830 CH0_RK1: MR19=0x808, MR18=0x6223, DQSOSC=391, MR23=63, INC=171, DEC=114
4345 23:00:17.805523 [RxdqsGatingPostProcess] freq 600
4346 23:00:17.809220 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4347 23:00:17.812486 Pre-setting of DQS Precalculation
4348 23:00:17.818932 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4349 23:00:17.819432 ==
4350 23:00:17.822528 Dram Type= 6, Freq= 0, CH_1, rank 0
4351 23:00:17.825429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4352 23:00:17.825885 ==
4353 23:00:17.832131 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4354 23:00:17.838665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4355 23:00:17.842109 [CA 0] Center 36 (5~67) winsize 63
4356 23:00:17.845742 [CA 1] Center 36 (5~67) winsize 63
4357 23:00:17.849048 [CA 2] Center 34 (4~65) winsize 62
4358 23:00:17.851945 [CA 3] Center 34 (4~65) winsize 62
4359 23:00:17.855187 [CA 4] Center 34 (4~65) winsize 62
4360 23:00:17.858689 [CA 5] Center 33 (3~64) winsize 62
4361 23:00:17.859387
4362 23:00:17.861901 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4363 23:00:17.862386
4364 23:00:17.865153 [CATrainingPosCal] consider 1 rank data
4365 23:00:17.868769 u2DelayCellTimex100 = 270/100 ps
4366 23:00:17.871648 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4367 23:00:17.874973 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4368 23:00:17.878015 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4369 23:00:17.881472 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4370 23:00:17.885239 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4371 23:00:17.888062 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4372 23:00:17.888490
4373 23:00:17.895147 CA PerBit enable=1, Macro0, CA PI delay=33
4374 23:00:17.895659
4375 23:00:17.896173 [CBTSetCACLKResult] CA Dly = 33
4376 23:00:17.898299 CS Dly: 5 (0~36)
4377 23:00:17.898731 ==
4378 23:00:17.901501 Dram Type= 6, Freq= 0, CH_1, rank 1
4379 23:00:17.905170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4380 23:00:17.905638 ==
4381 23:00:17.911525 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4382 23:00:17.918529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4383 23:00:17.921735 [CA 0] Center 36 (5~67) winsize 63
4384 23:00:17.924676 [CA 1] Center 36 (5~67) winsize 63
4385 23:00:17.928289 [CA 2] Center 34 (4~65) winsize 62
4386 23:00:17.931287 [CA 3] Center 34 (4~65) winsize 62
4387 23:00:17.934596 [CA 4] Center 34 (4~65) winsize 62
4388 23:00:17.938008 [CA 5] Center 34 (4~65) winsize 62
4389 23:00:17.938538
4390 23:00:17.941458 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4391 23:00:17.942002
4392 23:00:17.944546 [CATrainingPosCal] consider 2 rank data
4393 23:00:17.948174 u2DelayCellTimex100 = 270/100 ps
4394 23:00:17.951286 CA0 delay=36 (5~67),Diff = 2 PI (19 cell)
4395 23:00:17.954613 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4396 23:00:17.957882 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4397 23:00:17.961020 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4398 23:00:17.964614 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4399 23:00:17.971583 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4400 23:00:17.972133
4401 23:00:17.974974 CA PerBit enable=1, Macro0, CA PI delay=34
4402 23:00:17.975399
4403 23:00:17.977908 [CBTSetCACLKResult] CA Dly = 34
4404 23:00:17.978328 CS Dly: 5 (0~37)
4405 23:00:17.978729
4406 23:00:17.981083 ----->DramcWriteLeveling(PI) begin...
4407 23:00:17.981526 ==
4408 23:00:17.984550 Dram Type= 6, Freq= 0, CH_1, rank 0
4409 23:00:17.988037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4410 23:00:17.991534 ==
4411 23:00:17.992101 Write leveling (Byte 0): 32 => 32
4412 23:00:17.994305 Write leveling (Byte 1): 30 => 30
4413 23:00:17.997720 DramcWriteLeveling(PI) end<-----
4414 23:00:17.998136
4415 23:00:17.998549 ==
4416 23:00:18.001279 Dram Type= 6, Freq= 0, CH_1, rank 0
4417 23:00:18.007489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4418 23:00:18.007945 ==
4419 23:00:18.011426 [Gating] SW mode calibration
4420 23:00:18.017878 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4421 23:00:18.021376 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4422 23:00:18.027917 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4423 23:00:18.030927 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4424 23:00:18.034100 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4425 23:00:18.040948 0 9 12 | B1->B0 | 2f2f 2b2b | 0 0 | (0 1) (1 0)
4426 23:00:18.044212 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4427 23:00:18.047654 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4428 23:00:18.050809 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4429 23:00:18.057863 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4430 23:00:18.061285 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4431 23:00:18.064498 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4432 23:00:18.070905 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4433 23:00:18.074523 0 10 12 | B1->B0 | 3838 3a3a | 0 0 | (0 0) (1 1)
4434 23:00:18.077906 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4435 23:00:18.084515 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4436 23:00:18.087682 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4437 23:00:18.090808 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4438 23:00:18.097817 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4439 23:00:18.101023 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4440 23:00:18.103533 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4441 23:00:18.110466 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4442 23:00:18.114030 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4443 23:00:18.117378 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 23:00:18.124091 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 23:00:18.127519 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 23:00:18.130865 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 23:00:18.133858 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 23:00:18.140754 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 23:00:18.144028 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 23:00:18.147420 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4451 23:00:18.153886 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4452 23:00:18.157029 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4453 23:00:18.160388 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4454 23:00:18.167647 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4455 23:00:18.170292 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4456 23:00:18.174079 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4457 23:00:18.180495 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4458 23:00:18.183652 Total UI for P1: 0, mck2ui 16
4459 23:00:18.187091 best dqsien dly found for B0: ( 0, 13, 8)
4460 23:00:18.190477 Total UI for P1: 0, mck2ui 16
4461 23:00:18.193920 best dqsien dly found for B1: ( 0, 13, 10)
4462 23:00:18.197241 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4463 23:00:18.200779 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4464 23:00:18.201376
4465 23:00:18.203745 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4466 23:00:18.207601 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4467 23:00:18.211125 [Gating] SW calibration Done
4468 23:00:18.211660 ==
4469 23:00:18.214094 Dram Type= 6, Freq= 0, CH_1, rank 0
4470 23:00:18.217141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 23:00:18.217753 ==
4472 23:00:18.220703 RX Vref Scan: 0
4473 23:00:18.221145
4474 23:00:18.221517 RX Vref 0 -> 0, step: 1
4475 23:00:18.221938
4476 23:00:18.223982 RX Delay -230 -> 252, step: 16
4477 23:00:18.230903 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4478 23:00:18.233877 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4479 23:00:18.237522 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4480 23:00:18.240774 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4481 23:00:18.243676 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4482 23:00:18.250456 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4483 23:00:18.254056 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4484 23:00:18.256969 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4485 23:00:18.260338 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4486 23:00:18.264031 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4487 23:00:18.270705 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4488 23:00:18.274112 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4489 23:00:18.277344 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4490 23:00:18.280813 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4491 23:00:18.287213 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4492 23:00:18.290152 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4493 23:00:18.290629 ==
4494 23:00:18.293657 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 23:00:18.297088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 23:00:18.297643 ==
4497 23:00:18.300118 DQS Delay:
4498 23:00:18.300686 DQS0 = 0, DQS1 = 0
4499 23:00:18.301198 DQM Delay:
4500 23:00:18.304052 DQM0 = 55, DQM1 = 53
4501 23:00:18.304527 DQ Delay:
4502 23:00:18.307423 DQ0 =65, DQ1 =49, DQ2 =49, DQ3 =49
4503 23:00:18.310528 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4504 23:00:18.313683 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4505 23:00:18.316814 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4506 23:00:18.317375
4507 23:00:18.317774
4508 23:00:18.318091 ==
4509 23:00:18.320235 Dram Type= 6, Freq= 0, CH_1, rank 0
4510 23:00:18.326501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4511 23:00:18.327157 ==
4512 23:00:18.327549
4513 23:00:18.328161
4514 23:00:18.328742 TX Vref Scan disable
4515 23:00:18.330212 == TX Byte 0 ==
4516 23:00:18.333950 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4517 23:00:18.340070 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4518 23:00:18.340699 == TX Byte 1 ==
4519 23:00:18.343380 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4520 23:00:18.350440 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4521 23:00:18.350899 ==
4522 23:00:18.353781 Dram Type= 6, Freq= 0, CH_1, rank 0
4523 23:00:18.356765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4524 23:00:18.357277 ==
4525 23:00:18.357790
4526 23:00:18.358133
4527 23:00:18.360574 TX Vref Scan disable
4528 23:00:18.363775 == TX Byte 0 ==
4529 23:00:18.367002 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4530 23:00:18.369835 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4531 23:00:18.373246 == TX Byte 1 ==
4532 23:00:18.376776 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4533 23:00:18.379939 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4534 23:00:18.380507
4535 23:00:18.380888 [DATLAT]
4536 23:00:18.383098 Freq=600, CH1 RK0
4537 23:00:18.383575
4538 23:00:18.387085 DATLAT Default: 0x9
4539 23:00:18.387506 0, 0xFFFF, sum = 0
4540 23:00:18.390538 1, 0xFFFF, sum = 0
4541 23:00:18.390960 2, 0xFFFF, sum = 0
4542 23:00:18.393250 3, 0xFFFF, sum = 0
4543 23:00:18.393725 4, 0xFFFF, sum = 0
4544 23:00:18.396642 5, 0xFFFF, sum = 0
4545 23:00:18.397202 6, 0xFFFF, sum = 0
4546 23:00:18.400350 7, 0xFFFF, sum = 0
4547 23:00:18.400842 8, 0x0, sum = 1
4548 23:00:18.403098 9, 0x0, sum = 2
4549 23:00:18.403568 10, 0x0, sum = 3
4550 23:00:18.406339 11, 0x0, sum = 4
4551 23:00:18.406789 best_step = 9
4552 23:00:18.407169
4553 23:00:18.407484 ==
4554 23:00:18.410106 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 23:00:18.413158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 23:00:18.413737 ==
4557 23:00:18.416367 RX Vref Scan: 1
4558 23:00:18.416928
4559 23:00:18.419717 RX Vref 0 -> 0, step: 1
4560 23:00:18.420152
4561 23:00:18.420573 RX Delay -147 -> 252, step: 8
4562 23:00:18.421028
4563 23:00:18.423016 Set Vref, RX VrefLevel [Byte0]: 54
4564 23:00:18.426155 [Byte1]: 48
4565 23:00:18.431053
4566 23:00:18.431461 Final RX Vref Byte 0 = 54 to rank0
4567 23:00:18.433855 Final RX Vref Byte 1 = 48 to rank0
4568 23:00:18.438022 Final RX Vref Byte 0 = 54 to rank1
4569 23:00:18.440720 Final RX Vref Byte 1 = 48 to rank1==
4570 23:00:18.444010 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:00:18.450328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:00:18.450743 ==
4573 23:00:18.451069 DQS Delay:
4574 23:00:18.453684 DQS0 = 0, DQS1 = 0
4575 23:00:18.454095 DQM Delay:
4576 23:00:18.454425 DQM0 = 48, DQM1 = 46
4577 23:00:18.457328 DQ Delay:
4578 23:00:18.460256 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4579 23:00:18.464124 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4580 23:00:18.467372 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4581 23:00:18.470714 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4582 23:00:18.471198
4583 23:00:18.471542
4584 23:00:18.477127 [DQSOSCAuto] RK0, (LSB)MR18= 0x446a, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4585 23:00:18.480773 CH1 RK0: MR19=808, MR18=446A
4586 23:00:18.487097 CH1_RK0: MR19=0x808, MR18=0x446A, DQSOSC=389, MR23=63, INC=173, DEC=115
4587 23:00:18.487508
4588 23:00:18.490733 ----->DramcWriteLeveling(PI) begin...
4589 23:00:18.491157 ==
4590 23:00:18.494232 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 23:00:18.497274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 23:00:18.497875 ==
4593 23:00:18.500624 Write leveling (Byte 0): 30 => 30
4594 23:00:18.503995 Write leveling (Byte 1): 30 => 30
4595 23:00:18.507724 DramcWriteLeveling(PI) end<-----
4596 23:00:18.508142
4597 23:00:18.508470 ==
4598 23:00:18.510511 Dram Type= 6, Freq= 0, CH_1, rank 1
4599 23:00:18.513705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 23:00:18.514128 ==
4601 23:00:18.517079 [Gating] SW mode calibration
4602 23:00:18.523877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4603 23:00:18.530469 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4604 23:00:18.533743 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4605 23:00:18.537190 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4606 23:00:18.543602 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4607 23:00:18.546993 0 9 12 | B1->B0 | 2d2d 2f2f | 0 1 | (1 1) (1 1)
4608 23:00:18.550376 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4609 23:00:18.557085 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4610 23:00:18.560372 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4611 23:00:18.563811 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4612 23:00:18.570212 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4613 23:00:18.573490 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4614 23:00:18.576960 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4615 23:00:18.583501 0 10 12 | B1->B0 | 3737 3434 | 0 0 | (1 1) (1 1)
4616 23:00:18.586893 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 23:00:18.590685 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4618 23:00:18.597239 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4619 23:00:18.599909 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4620 23:00:18.603381 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4621 23:00:18.610261 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4622 23:00:18.613421 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4623 23:00:18.617109 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:00:18.623583 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 23:00:18.626538 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 23:00:18.629959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 23:00:18.636768 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 23:00:18.640039 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 23:00:18.643490 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 23:00:18.650461 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 23:00:18.653382 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 23:00:18.657027 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 23:00:18.660624 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4634 23:00:18.666643 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4635 23:00:18.670218 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4636 23:00:18.673046 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4637 23:00:18.680041 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4638 23:00:18.682924 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4639 23:00:18.686488 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4640 23:00:18.690149 Total UI for P1: 0, mck2ui 16
4641 23:00:18.692896 best dqsien dly found for B1: ( 0, 13, 10)
4642 23:00:18.699662 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4643 23:00:18.702684 Total UI for P1: 0, mck2ui 16
4644 23:00:18.706291 best dqsien dly found for B0: ( 0, 13, 12)
4645 23:00:18.709609 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4646 23:00:18.712936 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4647 23:00:18.713528
4648 23:00:18.716169 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4649 23:00:18.720075 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4650 23:00:18.723035 [Gating] SW calibration Done
4651 23:00:18.723565 ==
4652 23:00:18.726334 Dram Type= 6, Freq= 0, CH_1, rank 1
4653 23:00:18.729493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4654 23:00:18.730005 ==
4655 23:00:18.732879 RX Vref Scan: 0
4656 23:00:18.733448
4657 23:00:18.736391 RX Vref 0 -> 0, step: 1
4658 23:00:18.736832
4659 23:00:18.737206 RX Delay -230 -> 252, step: 16
4660 23:00:18.743027 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4661 23:00:18.746193 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4662 23:00:18.749381 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4663 23:00:18.752866 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4664 23:00:18.759629 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4665 23:00:18.762690 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4666 23:00:18.766012 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4667 23:00:18.770083 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4668 23:00:18.772993 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4669 23:00:18.779728 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4670 23:00:18.782374 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4671 23:00:18.785987 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4672 23:00:18.789084 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4673 23:00:18.795953 iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304
4674 23:00:18.799291 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4675 23:00:18.802453 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4676 23:00:18.802873 ==
4677 23:00:18.805813 Dram Type= 6, Freq= 0, CH_1, rank 1
4678 23:00:18.809407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4679 23:00:18.809926 ==
4680 23:00:18.812763 DQS Delay:
4681 23:00:18.813374 DQS0 = 0, DQS1 = 0
4682 23:00:18.815724 DQM Delay:
4683 23:00:18.816305 DQM0 = 51, DQM1 = 51
4684 23:00:18.816780 DQ Delay:
4685 23:00:18.819383 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =49
4686 23:00:18.823125 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4687 23:00:18.825852 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4688 23:00:18.828887 DQ12 =65, DQ13 =65, DQ14 =57, DQ15 =65
4689 23:00:18.829450
4690 23:00:18.830038
4691 23:00:18.830432 ==
4692 23:00:18.832357 Dram Type= 6, Freq= 0, CH_1, rank 1
4693 23:00:18.838975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4694 23:00:18.839448 ==
4695 23:00:18.839896
4696 23:00:18.840402
4697 23:00:18.840890 TX Vref Scan disable
4698 23:00:18.843208 == TX Byte 0 ==
4699 23:00:18.846476 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4700 23:00:18.852867 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4701 23:00:18.853421 == TX Byte 1 ==
4702 23:00:18.856491 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 23:00:18.862788 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 23:00:18.863337 ==
4705 23:00:18.866133 Dram Type= 6, Freq= 0, CH_1, rank 1
4706 23:00:18.869543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4707 23:00:18.870065 ==
4708 23:00:18.870425
4709 23:00:18.870778
4710 23:00:18.872974 TX Vref Scan disable
4711 23:00:18.876623 == TX Byte 0 ==
4712 23:00:18.879409 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4713 23:00:18.883107 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4714 23:00:18.886092 == TX Byte 1 ==
4715 23:00:18.889329 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4716 23:00:18.892750 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4717 23:00:18.893326
4718 23:00:18.893875 [DATLAT]
4719 23:00:18.895988 Freq=600, CH1 RK1
4720 23:00:18.896549
4721 23:00:18.896894 DATLAT Default: 0x9
4722 23:00:18.899699 0, 0xFFFF, sum = 0
4723 23:00:18.900124 1, 0xFFFF, sum = 0
4724 23:00:18.902993 2, 0xFFFF, sum = 0
4725 23:00:18.906340 3, 0xFFFF, sum = 0
4726 23:00:18.906872 4, 0xFFFF, sum = 0
4727 23:00:18.909348 5, 0xFFFF, sum = 0
4728 23:00:18.909924 6, 0xFFFF, sum = 0
4729 23:00:18.912981 7, 0xFFFF, sum = 0
4730 23:00:18.913641 8, 0x0, sum = 1
4731 23:00:18.914022 9, 0x0, sum = 2
4732 23:00:18.915906 10, 0x0, sum = 3
4733 23:00:18.916478 11, 0x0, sum = 4
4734 23:00:18.919940 best_step = 9
4735 23:00:18.920517
4736 23:00:18.921009 ==
4737 23:00:18.922850 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 23:00:18.926069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 23:00:18.926630 ==
4740 23:00:18.929839 RX Vref Scan: 0
4741 23:00:18.930332
4742 23:00:18.930658 RX Vref 0 -> 0, step: 1
4743 23:00:18.930962
4744 23:00:18.932900 RX Delay -163 -> 252, step: 8
4745 23:00:18.939739 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4746 23:00:18.943362 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4747 23:00:18.946495 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4748 23:00:18.949778 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4749 23:00:18.953558 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4750 23:00:18.959962 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4751 23:00:18.963349 iDelay=205, Bit 6, Center 56 (-91 ~ 204) 296
4752 23:00:18.966693 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4753 23:00:18.969772 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4754 23:00:18.976615 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4755 23:00:18.979849 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4756 23:00:18.983298 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4757 23:00:18.986651 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4758 23:00:18.989688 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4759 23:00:18.996682 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4760 23:00:18.999925 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4761 23:00:19.000336 ==
4762 23:00:19.003504 Dram Type= 6, Freq= 0, CH_1, rank 1
4763 23:00:19.006320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4764 23:00:19.006738 ==
4765 23:00:19.009832 DQS Delay:
4766 23:00:19.010271 DQS0 = 0, DQS1 = 0
4767 23:00:19.010644 DQM Delay:
4768 23:00:19.013073 DQM0 = 48, DQM1 = 46
4769 23:00:19.013486 DQ Delay:
4770 23:00:19.016198 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4771 23:00:19.019428 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4772 23:00:19.023437 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4773 23:00:19.026100 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4774 23:00:19.026511
4775 23:00:19.026877
4776 23:00:19.036001 [DQSOSCAuto] RK1, (LSB)MR18= 0x651d, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4777 23:00:19.039545 CH1 RK1: MR19=808, MR18=651D
4778 23:00:19.043271 CH1_RK1: MR19=0x808, MR18=0x651D, DQSOSC=390, MR23=63, INC=172, DEC=114
4779 23:00:19.046042 [RxdqsGatingPostProcess] freq 600
4780 23:00:19.052933 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4781 23:00:19.056307 Pre-setting of DQS Precalculation
4782 23:00:19.059455 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4783 23:00:19.065923 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4784 23:00:19.076094 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4785 23:00:19.076508
4786 23:00:19.076829
4787 23:00:19.079431 [Calibration Summary] 1200 Mbps
4788 23:00:19.079846 CH 0, Rank 0
4789 23:00:19.082668 SW Impedance : PASS
4790 23:00:19.083079 DUTY Scan : NO K
4791 23:00:19.086338 ZQ Calibration : PASS
4792 23:00:19.089229 Jitter Meter : NO K
4793 23:00:19.089685 CBT Training : PASS
4794 23:00:19.092673 Write leveling : PASS
4795 23:00:19.093082 RX DQS gating : PASS
4796 23:00:19.096306 RX DQ/DQS(RDDQC) : PASS
4797 23:00:19.099503 TX DQ/DQS : PASS
4798 23:00:19.099913 RX DATLAT : PASS
4799 23:00:19.103011 RX DQ/DQS(Engine): PASS
4800 23:00:19.106116 TX OE : NO K
4801 23:00:19.106527 All Pass.
4802 23:00:19.106852
4803 23:00:19.107154 CH 0, Rank 1
4804 23:00:19.109212 SW Impedance : PASS
4805 23:00:19.112656 DUTY Scan : NO K
4806 23:00:19.113063 ZQ Calibration : PASS
4807 23:00:19.116142 Jitter Meter : NO K
4808 23:00:19.119262 CBT Training : PASS
4809 23:00:19.119675 Write leveling : PASS
4810 23:00:19.122758 RX DQS gating : PASS
4811 23:00:19.125955 RX DQ/DQS(RDDQC) : PASS
4812 23:00:19.126364 TX DQ/DQS : PASS
4813 23:00:19.129076 RX DATLAT : PASS
4814 23:00:19.132502 RX DQ/DQS(Engine): PASS
4815 23:00:19.132957 TX OE : NO K
4816 23:00:19.135818 All Pass.
4817 23:00:19.136231
4818 23:00:19.136557 CH 1, Rank 0
4819 23:00:19.139065 SW Impedance : PASS
4820 23:00:19.139519 DUTY Scan : NO K
4821 23:00:19.142633 ZQ Calibration : PASS
4822 23:00:19.145713 Jitter Meter : NO K
4823 23:00:19.146125 CBT Training : PASS
4824 23:00:19.148907 Write leveling : PASS
4825 23:00:19.149320 RX DQS gating : PASS
4826 23:00:19.152270 RX DQ/DQS(RDDQC) : PASS
4827 23:00:19.155475 TX DQ/DQS : PASS
4828 23:00:19.155909 RX DATLAT : PASS
4829 23:00:19.159119 RX DQ/DQS(Engine): PASS
4830 23:00:19.162359 TX OE : NO K
4831 23:00:19.162861 All Pass.
4832 23:00:19.163200
4833 23:00:19.163590 CH 1, Rank 1
4834 23:00:19.165749 SW Impedance : PASS
4835 23:00:19.168807 DUTY Scan : NO K
4836 23:00:19.169290 ZQ Calibration : PASS
4837 23:00:19.172225 Jitter Meter : NO K
4838 23:00:19.176098 CBT Training : PASS
4839 23:00:19.176565 Write leveling : PASS
4840 23:00:19.178893 RX DQS gating : PASS
4841 23:00:19.182039 RX DQ/DQS(RDDQC) : PASS
4842 23:00:19.182510 TX DQ/DQS : PASS
4843 23:00:19.185419 RX DATLAT : PASS
4844 23:00:19.188754 RX DQ/DQS(Engine): PASS
4845 23:00:19.189204 TX OE : NO K
4846 23:00:19.189641 All Pass.
4847 23:00:19.192673
4848 23:00:19.193111 DramC Write-DBI off
4849 23:00:19.195415 PER_BANK_REFRESH: Hybrid Mode
4850 23:00:19.195833 TX_TRACKING: ON
4851 23:00:19.205682 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4852 23:00:19.209410 [FAST_K] Save calibration result to emmc
4853 23:00:19.212023 dramc_set_vcore_voltage set vcore to 662500
4854 23:00:19.215904 Read voltage for 933, 3
4855 23:00:19.216355 Vio18 = 0
4856 23:00:19.219226 Vcore = 662500
4857 23:00:19.219638 Vdram = 0
4858 23:00:19.219967 Vddq = 0
4859 23:00:19.220271 Vmddr = 0
4860 23:00:19.225573 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4861 23:00:19.232299 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4862 23:00:19.232749 MEM_TYPE=3, freq_sel=17
4863 23:00:19.235851 sv_algorithm_assistance_LP4_1600
4864 23:00:19.238773 ============ PULL DRAM RESETB DOWN ============
4865 23:00:19.245291 ========== PULL DRAM RESETB DOWN end =========
4866 23:00:19.248803 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4867 23:00:19.251855 ===================================
4868 23:00:19.255396 LPDDR4 DRAM CONFIGURATION
4869 23:00:19.259077 ===================================
4870 23:00:19.259497 EX_ROW_EN[0] = 0x0
4871 23:00:19.262401 EX_ROW_EN[1] = 0x0
4872 23:00:19.262821 LP4Y_EN = 0x0
4873 23:00:19.265642 WORK_FSP = 0x0
4874 23:00:19.266054 WL = 0x3
4875 23:00:19.268528 RL = 0x3
4876 23:00:19.268945 BL = 0x2
4877 23:00:19.272057 RPST = 0x0
4878 23:00:19.275409 RD_PRE = 0x0
4879 23:00:19.275832 WR_PRE = 0x1
4880 23:00:19.278900 WR_PST = 0x0
4881 23:00:19.279317 DBI_WR = 0x0
4882 23:00:19.281937 DBI_RD = 0x0
4883 23:00:19.282353 OTF = 0x1
4884 23:00:19.285440 ===================================
4885 23:00:19.288677 ===================================
4886 23:00:19.289099 ANA top config
4887 23:00:19.291777 ===================================
4888 23:00:19.296009 DLL_ASYNC_EN = 0
4889 23:00:19.298581 ALL_SLAVE_EN = 1
4890 23:00:19.301527 NEW_RANK_MODE = 1
4891 23:00:19.305088 DLL_IDLE_MODE = 1
4892 23:00:19.305543 LP45_APHY_COMB_EN = 1
4893 23:00:19.308370 TX_ODT_DIS = 1
4894 23:00:19.311967 NEW_8X_MODE = 1
4895 23:00:19.314888 ===================================
4896 23:00:19.318312 ===================================
4897 23:00:19.321889 data_rate = 1866
4898 23:00:19.325351 CKR = 1
4899 23:00:19.325804 DQ_P2S_RATIO = 8
4900 23:00:19.328536 ===================================
4901 23:00:19.332073 CA_P2S_RATIO = 8
4902 23:00:19.335035 DQ_CA_OPEN = 0
4903 23:00:19.338378 DQ_SEMI_OPEN = 0
4904 23:00:19.341658 CA_SEMI_OPEN = 0
4905 23:00:19.344897 CA_FULL_RATE = 0
4906 23:00:19.345310 DQ_CKDIV4_EN = 1
4907 23:00:19.348242 CA_CKDIV4_EN = 1
4908 23:00:19.351679 CA_PREDIV_EN = 0
4909 23:00:19.354882 PH8_DLY = 0
4910 23:00:19.358247 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4911 23:00:19.361348 DQ_AAMCK_DIV = 4
4912 23:00:19.361857 CA_AAMCK_DIV = 4
4913 23:00:19.364925 CA_ADMCK_DIV = 4
4914 23:00:19.368047 DQ_TRACK_CA_EN = 0
4915 23:00:19.371920 CA_PICK = 933
4916 23:00:19.375108 CA_MCKIO = 933
4917 23:00:19.378039 MCKIO_SEMI = 0
4918 23:00:19.381440 PLL_FREQ = 3732
4919 23:00:19.381941 DQ_UI_PI_RATIO = 32
4920 23:00:19.384746 CA_UI_PI_RATIO = 0
4921 23:00:19.388036 ===================================
4922 23:00:19.391493 ===================================
4923 23:00:19.394553 memory_type:LPDDR4
4924 23:00:19.398000 GP_NUM : 10
4925 23:00:19.398417 SRAM_EN : 1
4926 23:00:19.401171 MD32_EN : 0
4927 23:00:19.404445 ===================================
4928 23:00:19.408057 [ANA_INIT] >>>>>>>>>>>>>>
4929 23:00:19.408470 <<<<<< [CONFIGURE PHASE]: ANA_TX
4930 23:00:19.411353 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4931 23:00:19.414836 ===================================
4932 23:00:19.417902 data_rate = 1866,PCW = 0X8f00
4933 23:00:19.421078 ===================================
4934 23:00:19.424837 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4935 23:00:19.431334 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4936 23:00:19.438108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4937 23:00:19.441121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4938 23:00:19.444583 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4939 23:00:19.447707 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4940 23:00:19.450963 [ANA_INIT] flow start
4941 23:00:19.451464 [ANA_INIT] PLL >>>>>>>>
4942 23:00:19.454232 [ANA_INIT] PLL <<<<<<<<
4943 23:00:19.458003 [ANA_INIT] MIDPI >>>>>>>>
4944 23:00:19.458414 [ANA_INIT] MIDPI <<<<<<<<
4945 23:00:19.461328 [ANA_INIT] DLL >>>>>>>>
4946 23:00:19.464378 [ANA_INIT] flow end
4947 23:00:19.467664 ============ LP4 DIFF to SE enter ============
4948 23:00:19.471030 ============ LP4 DIFF to SE exit ============
4949 23:00:19.474689 [ANA_INIT] <<<<<<<<<<<<<
4950 23:00:19.478063 [Flow] Enable top DCM control >>>>>
4951 23:00:19.481108 [Flow] Enable top DCM control <<<<<
4952 23:00:19.484479 Enable DLL master slave shuffle
4953 23:00:19.487944 ==============================================================
4954 23:00:19.491530 Gating Mode config
4955 23:00:19.498341 ==============================================================
4956 23:00:19.498762 Config description:
4957 23:00:19.508050 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4958 23:00:19.514214 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4959 23:00:19.517511 SELPH_MODE 0: By rank 1: By Phase
4960 23:00:19.524145 ==============================================================
4961 23:00:19.527706 GAT_TRACK_EN = 1
4962 23:00:19.530895 RX_GATING_MODE = 2
4963 23:00:19.534120 RX_GATING_TRACK_MODE = 2
4964 23:00:19.537542 SELPH_MODE = 1
4965 23:00:19.541018 PICG_EARLY_EN = 1
4966 23:00:19.544295 VALID_LAT_VALUE = 1
4967 23:00:19.547820 ==============================================================
4968 23:00:19.550646 Enter into Gating configuration >>>>
4969 23:00:19.553963 Exit from Gating configuration <<<<
4970 23:00:19.557234 Enter into DVFS_PRE_config >>>>>
4971 23:00:19.570758 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4972 23:00:19.574083 Exit from DVFS_PRE_config <<<<<
4973 23:00:19.574498 Enter into PICG configuration >>>>
4974 23:00:19.577560 Exit from PICG configuration <<<<
4975 23:00:19.581081 [RX_INPUT] configuration >>>>>
4976 23:00:19.583953 [RX_INPUT] configuration <<<<<
4977 23:00:19.590563 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4978 23:00:19.594345 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4979 23:00:19.600936 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4980 23:00:19.607456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4981 23:00:19.614416 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4982 23:00:19.620394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4983 23:00:19.624350 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4984 23:00:19.627683 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4985 23:00:19.630589 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4986 23:00:19.637121 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4987 23:00:19.640796 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4988 23:00:19.643916 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4989 23:00:19.647109 ===================================
4990 23:00:19.650533 LPDDR4 DRAM CONFIGURATION
4991 23:00:19.654227 ===================================
4992 23:00:19.654638 EX_ROW_EN[0] = 0x0
4993 23:00:19.657152 EX_ROW_EN[1] = 0x0
4994 23:00:19.660900 LP4Y_EN = 0x0
4995 23:00:19.661309 WORK_FSP = 0x0
4996 23:00:19.664210 WL = 0x3
4997 23:00:19.664806 RL = 0x3
4998 23:00:19.667017 BL = 0x2
4999 23:00:19.667434 RPST = 0x0
5000 23:00:19.670259 RD_PRE = 0x0
5001 23:00:19.670677 WR_PRE = 0x1
5002 23:00:19.673661 WR_PST = 0x0
5003 23:00:19.674156 DBI_WR = 0x0
5004 23:00:19.677167 DBI_RD = 0x0
5005 23:00:19.677618 OTF = 0x1
5006 23:00:19.680609 ===================================
5007 23:00:19.683572 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5008 23:00:19.690223 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5009 23:00:19.693489 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5010 23:00:19.697073 ===================================
5011 23:00:19.700382 LPDDR4 DRAM CONFIGURATION
5012 23:00:19.703504 ===================================
5013 23:00:19.703838 EX_ROW_EN[0] = 0x10
5014 23:00:19.706477 EX_ROW_EN[1] = 0x0
5015 23:00:19.710216 LP4Y_EN = 0x0
5016 23:00:19.710323 WORK_FSP = 0x0
5017 23:00:19.713302 WL = 0x3
5018 23:00:19.713382 RL = 0x3
5019 23:00:19.717026 BL = 0x2
5020 23:00:19.717434 RPST = 0x0
5021 23:00:19.720095 RD_PRE = 0x0
5022 23:00:19.720576 WR_PRE = 0x1
5023 23:00:19.723525 WR_PST = 0x0
5024 23:00:19.723830 DBI_WR = 0x0
5025 23:00:19.726537 DBI_RD = 0x0
5026 23:00:19.726618 OTF = 0x1
5027 23:00:19.729796 ===================================
5028 23:00:19.736195 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5029 23:00:19.740509 nWR fixed to 30
5030 23:00:19.743700 [ModeRegInit_LP4] CH0 RK0
5031 23:00:19.743806 [ModeRegInit_LP4] CH0 RK1
5032 23:00:19.747098 [ModeRegInit_LP4] CH1 RK0
5033 23:00:19.750754 [ModeRegInit_LP4] CH1 RK1
5034 23:00:19.750826 match AC timing 9
5035 23:00:19.757024 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5036 23:00:19.760719 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5037 23:00:19.764329 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5038 23:00:19.770559 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5039 23:00:19.774449 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5040 23:00:19.774577 ==
5041 23:00:19.777132 Dram Type= 6, Freq= 0, CH_0, rank 0
5042 23:00:19.780433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5043 23:00:19.780574 ==
5044 23:00:19.787014 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5045 23:00:19.793799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5046 23:00:19.797278 [CA 0] Center 37 (6~68) winsize 63
5047 23:00:19.800534 [CA 1] Center 37 (6~68) winsize 63
5048 23:00:19.803739 [CA 2] Center 34 (4~65) winsize 62
5049 23:00:19.807106 [CA 3] Center 34 (3~65) winsize 63
5050 23:00:19.810536 [CA 4] Center 33 (3~64) winsize 62
5051 23:00:19.814162 [CA 5] Center 32 (2~62) winsize 61
5052 23:00:19.814246
5053 23:00:19.817141 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5054 23:00:19.817230
5055 23:00:19.820054 [CATrainingPosCal] consider 1 rank data
5056 23:00:19.823559 u2DelayCellTimex100 = 270/100 ps
5057 23:00:19.826749 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5058 23:00:19.830232 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5059 23:00:19.833963 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5060 23:00:19.837335 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5061 23:00:19.840494 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5062 23:00:19.843875 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5063 23:00:19.847532
5064 23:00:19.850436 CA PerBit enable=1, Macro0, CA PI delay=32
5065 23:00:19.850638
5066 23:00:19.854080 [CBTSetCACLKResult] CA Dly = 32
5067 23:00:19.854213 CS Dly: 5 (0~36)
5068 23:00:19.854319 ==
5069 23:00:19.857180 Dram Type= 6, Freq= 0, CH_0, rank 1
5070 23:00:19.860733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5071 23:00:19.860813 ==
5072 23:00:19.866980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5073 23:00:19.873531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5074 23:00:19.877141 [CA 0] Center 37 (6~68) winsize 63
5075 23:00:19.880397 [CA 1] Center 37 (7~68) winsize 62
5076 23:00:19.883569 [CA 2] Center 34 (4~65) winsize 62
5077 23:00:19.887044 [CA 3] Center 34 (4~65) winsize 62
5078 23:00:19.890497 [CA 4] Center 33 (3~63) winsize 61
5079 23:00:19.894030 [CA 5] Center 32 (2~62) winsize 61
5080 23:00:19.894441
5081 23:00:19.897718 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5082 23:00:19.898135
5083 23:00:19.900463 [CATrainingPosCal] consider 2 rank data
5084 23:00:19.904237 u2DelayCellTimex100 = 270/100 ps
5085 23:00:19.907173 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5086 23:00:19.910486 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5087 23:00:19.913794 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5088 23:00:19.917073 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5089 23:00:19.920305 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5090 23:00:19.927283 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5091 23:00:19.927693
5092 23:00:19.929967 CA PerBit enable=1, Macro0, CA PI delay=32
5093 23:00:19.930048
5094 23:00:19.933563 [CBTSetCACLKResult] CA Dly = 32
5095 23:00:19.933684 CS Dly: 5 (0~37)
5096 23:00:19.933748
5097 23:00:19.936963 ----->DramcWriteLeveling(PI) begin...
5098 23:00:19.937044 ==
5099 23:00:19.940468 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 23:00:19.947151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 23:00:19.947234 ==
5102 23:00:19.950036 Write leveling (Byte 0): 32 => 32
5103 23:00:19.950116 Write leveling (Byte 1): 27 => 27
5104 23:00:19.953145 DramcWriteLeveling(PI) end<-----
5105 23:00:19.953229
5106 23:00:19.953294 ==
5107 23:00:19.956693 Dram Type= 6, Freq= 0, CH_0, rank 0
5108 23:00:19.963181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5109 23:00:19.963274 ==
5110 23:00:19.966544 [Gating] SW mode calibration
5111 23:00:19.973450 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5112 23:00:19.976950 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5113 23:00:19.983054 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5114 23:00:19.986737 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5115 23:00:19.989915 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5116 23:00:19.996697 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5117 23:00:20.000127 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5118 23:00:20.003406 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5119 23:00:20.009998 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5120 23:00:20.013355 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 1) (1 0)
5121 23:00:20.016799 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5122 23:00:20.023663 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 23:00:20.026795 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5124 23:00:20.030171 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5125 23:00:20.033412 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5126 23:00:20.039642 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5127 23:00:20.042778 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5128 23:00:20.046284 0 15 28 | B1->B0 | 2323 3c3c | 0 1 | (0 0) (1 1)
5129 23:00:20.052965 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5130 23:00:20.056194 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 23:00:20.059456 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5132 23:00:20.066559 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5133 23:00:20.069336 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5134 23:00:20.072979 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5135 23:00:20.079458 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5136 23:00:20.082758 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5137 23:00:20.086469 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5138 23:00:20.093053 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 23:00:20.096555 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 23:00:20.099735 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 23:00:20.106514 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 23:00:20.109795 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 23:00:20.113260 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 23:00:20.119669 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 23:00:20.122806 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 23:00:20.126261 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5147 23:00:20.133415 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5148 23:00:20.136599 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5149 23:00:20.140062 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5150 23:00:20.146575 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5151 23:00:20.149809 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5152 23:00:20.152812 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5153 23:00:20.156131 Total UI for P1: 0, mck2ui 16
5154 23:00:20.159745 best dqsien dly found for B0: ( 1, 2, 24)
5155 23:00:20.162959 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5156 23:00:20.166386 Total UI for P1: 0, mck2ui 16
5157 23:00:20.169869 best dqsien dly found for B1: ( 1, 2, 28)
5158 23:00:20.173145 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5159 23:00:20.179585 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5160 23:00:20.180032
5161 23:00:20.182936 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5162 23:00:20.186422 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5163 23:00:20.189775 [Gating] SW calibration Done
5164 23:00:20.190185 ==
5165 23:00:20.192959 Dram Type= 6, Freq= 0, CH_0, rank 0
5166 23:00:20.196259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5167 23:00:20.196671 ==
5168 23:00:20.196996 RX Vref Scan: 0
5169 23:00:20.199335
5170 23:00:20.199883 RX Vref 0 -> 0, step: 1
5171 23:00:20.200289
5172 23:00:20.202935 RX Delay -80 -> 252, step: 8
5173 23:00:20.206067 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5174 23:00:20.209564 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5175 23:00:20.216318 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5176 23:00:20.219890 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5177 23:00:20.222723 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5178 23:00:20.226014 iDelay=208, Bit 5, Center 95 (8 ~ 183) 176
5179 23:00:20.229832 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5180 23:00:20.232617 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5181 23:00:20.239912 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5182 23:00:20.243091 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5183 23:00:20.246511 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5184 23:00:20.249693 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5185 23:00:20.252944 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5186 23:00:20.256049 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5187 23:00:20.262941 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5188 23:00:20.266429 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5189 23:00:20.266842 ==
5190 23:00:20.269193 Dram Type= 6, Freq= 0, CH_0, rank 0
5191 23:00:20.272639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5192 23:00:20.273051 ==
5193 23:00:20.275755 DQS Delay:
5194 23:00:20.276167 DQS0 = 0, DQS1 = 0
5195 23:00:20.276496 DQM Delay:
5196 23:00:20.279532 DQM0 = 103, DQM1 = 95
5197 23:00:20.279983 DQ Delay:
5198 23:00:20.282820 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5199 23:00:20.286012 DQ4 =103, DQ5 =95, DQ6 =111, DQ7 =111
5200 23:00:20.289189 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5201 23:00:20.292509 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5202 23:00:20.292925
5203 23:00:20.293253
5204 23:00:20.295960 ==
5205 23:00:20.296377 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 23:00:20.302603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 23:00:20.303037 ==
5208 23:00:20.303370
5209 23:00:20.303678
5210 23:00:20.305777 TX Vref Scan disable
5211 23:00:20.306290 == TX Byte 0 ==
5212 23:00:20.308803 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5213 23:00:20.315556 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5214 23:00:20.315971 == TX Byte 1 ==
5215 23:00:20.318857 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5216 23:00:20.326129 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5217 23:00:20.326547 ==
5218 23:00:20.328757 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 23:00:20.332333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 23:00:20.332763 ==
5221 23:00:20.333092
5222 23:00:20.333394
5223 23:00:20.335525 TX Vref Scan disable
5224 23:00:20.338769 == TX Byte 0 ==
5225 23:00:20.342112 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5226 23:00:20.345654 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5227 23:00:20.348689 == TX Byte 1 ==
5228 23:00:20.351823 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5229 23:00:20.355207 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5230 23:00:20.355620
5231 23:00:20.358850 [DATLAT]
5232 23:00:20.359262 Freq=933, CH0 RK0
5233 23:00:20.359590
5234 23:00:20.361947 DATLAT Default: 0xd
5235 23:00:20.362362 0, 0xFFFF, sum = 0
5236 23:00:20.365492 1, 0xFFFF, sum = 0
5237 23:00:20.365944 2, 0xFFFF, sum = 0
5238 23:00:20.368748 3, 0xFFFF, sum = 0
5239 23:00:20.369166 4, 0xFFFF, sum = 0
5240 23:00:20.371863 5, 0xFFFF, sum = 0
5241 23:00:20.372283 6, 0xFFFF, sum = 0
5242 23:00:20.375268 7, 0xFFFF, sum = 0
5243 23:00:20.375688 8, 0xFFFF, sum = 0
5244 23:00:20.378590 9, 0xFFFF, sum = 0
5245 23:00:20.379011 10, 0x0, sum = 1
5246 23:00:20.381985 11, 0x0, sum = 2
5247 23:00:20.382411 12, 0x0, sum = 3
5248 23:00:20.385220 13, 0x0, sum = 4
5249 23:00:20.385684 best_step = 11
5250 23:00:20.386025
5251 23:00:20.386332 ==
5252 23:00:20.388806 Dram Type= 6, Freq= 0, CH_0, rank 0
5253 23:00:20.391882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5254 23:00:20.395205 ==
5255 23:00:20.395620 RX Vref Scan: 1
5256 23:00:20.395956
5257 23:00:20.398485 RX Vref 0 -> 0, step: 1
5258 23:00:20.398897
5259 23:00:20.401816 RX Delay -45 -> 252, step: 4
5260 23:00:20.402243
5261 23:00:20.405547 Set Vref, RX VrefLevel [Byte0]: 54
5262 23:00:20.408779 [Byte1]: 46
5263 23:00:20.409194
5264 23:00:20.412132 Final RX Vref Byte 0 = 54 to rank0
5265 23:00:20.415430 Final RX Vref Byte 1 = 46 to rank0
5266 23:00:20.418387 Final RX Vref Byte 0 = 54 to rank1
5267 23:00:20.421871 Final RX Vref Byte 1 = 46 to rank1==
5268 23:00:20.425329 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 23:00:20.428746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 23:00:20.429164 ==
5271 23:00:20.429494 DQS Delay:
5272 23:00:20.431609 DQS0 = 0, DQS1 = 0
5273 23:00:20.432023 DQM Delay:
5274 23:00:20.434972 DQM0 = 104, DQM1 = 94
5275 23:00:20.435386 DQ Delay:
5276 23:00:20.438235 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104
5277 23:00:20.441850 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5278 23:00:20.444998 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =90
5279 23:00:20.448354 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5280 23:00:20.448838
5281 23:00:20.449202
5282 23:00:20.458205 [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5283 23:00:20.461835 CH0 RK0: MR19=505, MR18=3129
5284 23:00:20.468028 CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43
5285 23:00:20.468446
5286 23:00:20.471494 ----->DramcWriteLeveling(PI) begin...
5287 23:00:20.471914 ==
5288 23:00:20.474665 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 23:00:20.478174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 23:00:20.478591 ==
5291 23:00:20.481687 Write leveling (Byte 0): 32 => 32
5292 23:00:20.485015 Write leveling (Byte 1): 28 => 28
5293 23:00:20.488116 DramcWriteLeveling(PI) end<-----
5294 23:00:20.488527
5295 23:00:20.488855 ==
5296 23:00:20.491544 Dram Type= 6, Freq= 0, CH_0, rank 1
5297 23:00:20.494848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5298 23:00:20.495409 ==
5299 23:00:20.498201 [Gating] SW mode calibration
5300 23:00:20.505046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5301 23:00:20.511470 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5302 23:00:20.515001 0 14 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5303 23:00:20.518467 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5304 23:00:20.524607 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5305 23:00:20.528101 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5306 23:00:20.531420 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5307 23:00:20.538044 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5308 23:00:20.541275 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5309 23:00:20.545031 0 14 28 | B1->B0 | 2a2a 2e2e | 1 0 | (1 0) (0 0)
5310 23:00:20.551299 0 15 0 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5311 23:00:20.554516 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 23:00:20.557609 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5313 23:00:20.564388 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5314 23:00:20.567861 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5315 23:00:20.571298 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5316 23:00:20.577903 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5317 23:00:20.581239 0 15 28 | B1->B0 | 3838 3636 | 1 1 | (0 0) (0 0)
5318 23:00:20.584086 1 0 0 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5319 23:00:20.591152 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 23:00:20.594591 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5321 23:00:20.597842 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5322 23:00:20.601092 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5323 23:00:20.607843 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5324 23:00:20.611007 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5325 23:00:20.614371 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5326 23:00:20.621227 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:00:20.624423 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:00:20.627886 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 23:00:20.634344 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 23:00:20.637947 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 23:00:20.641514 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 23:00:20.647871 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 23:00:20.651462 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 23:00:20.654519 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 23:00:20.660963 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 23:00:20.664451 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5337 23:00:20.667779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5338 23:00:20.674644 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5339 23:00:20.677780 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5340 23:00:20.681051 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5341 23:00:20.687725 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5342 23:00:20.690722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 23:00:20.694345 Total UI for P1: 0, mck2ui 16
5344 23:00:20.697357 best dqsien dly found for B0: ( 1, 2, 28)
5345 23:00:20.700758 Total UI for P1: 0, mck2ui 16
5346 23:00:20.704604 best dqsien dly found for B1: ( 1, 2, 28)
5347 23:00:20.707398 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5348 23:00:20.710768 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5349 23:00:20.711182
5350 23:00:20.714109 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5351 23:00:20.717392 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5352 23:00:20.720622 [Gating] SW calibration Done
5353 23:00:20.721033 ==
5354 23:00:20.724091 Dram Type= 6, Freq= 0, CH_0, rank 1
5355 23:00:20.727571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5356 23:00:20.728036 ==
5357 23:00:20.730933 RX Vref Scan: 0
5358 23:00:20.731341
5359 23:00:20.733703 RX Vref 0 -> 0, step: 1
5360 23:00:20.734117
5361 23:00:20.734442 RX Delay -80 -> 252, step: 8
5362 23:00:20.741059 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5363 23:00:20.744078 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5364 23:00:20.747436 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5365 23:00:20.750709 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5366 23:00:20.754187 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5367 23:00:20.757608 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5368 23:00:20.764116 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5369 23:00:20.767193 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5370 23:00:20.771023 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5371 23:00:20.773910 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5372 23:00:20.777267 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5373 23:00:20.780662 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5374 23:00:20.787320 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5375 23:00:20.790743 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5376 23:00:20.793712 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5377 23:00:20.796967 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5378 23:00:20.797377 ==
5379 23:00:20.800582 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 23:00:20.803758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 23:00:20.807427 ==
5382 23:00:20.807835 DQS Delay:
5383 23:00:20.808159 DQS0 = 0, DQS1 = 0
5384 23:00:20.810700 DQM Delay:
5385 23:00:20.811191 DQM0 = 104, DQM1 = 93
5386 23:00:20.813857 DQ Delay:
5387 23:00:20.817298 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5388 23:00:20.820340 DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115
5389 23:00:20.823903 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5390 23:00:20.827008 DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99
5391 23:00:20.827420
5392 23:00:20.827747
5393 23:00:20.828052 ==
5394 23:00:20.830689 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 23:00:20.833889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 23:00:20.834307 ==
5397 23:00:20.834635
5398 23:00:20.834938
5399 23:00:20.837203 TX Vref Scan disable
5400 23:00:20.837648 == TX Byte 0 ==
5401 23:00:20.843908 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5402 23:00:20.846943 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5403 23:00:20.847358 == TX Byte 1 ==
5404 23:00:20.853504 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5405 23:00:20.856913 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5406 23:00:20.857353 ==
5407 23:00:20.860050 Dram Type= 6, Freq= 0, CH_0, rank 1
5408 23:00:20.863348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5409 23:00:20.863713 ==
5410 23:00:20.864029
5411 23:00:20.864323
5412 23:00:20.866604 TX Vref Scan disable
5413 23:00:20.870677 == TX Byte 0 ==
5414 23:00:20.873961 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5415 23:00:20.877052 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5416 23:00:20.880429 == TX Byte 1 ==
5417 23:00:20.883661 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5418 23:00:20.887414 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5419 23:00:20.887834
5420 23:00:20.890166 [DATLAT]
5421 23:00:20.890637 Freq=933, CH0 RK1
5422 23:00:20.890999
5423 23:00:20.893621 DATLAT Default: 0xb
5424 23:00:20.894049 0, 0xFFFF, sum = 0
5425 23:00:20.896929 1, 0xFFFF, sum = 0
5426 23:00:20.897348 2, 0xFFFF, sum = 0
5427 23:00:20.900169 3, 0xFFFF, sum = 0
5428 23:00:20.900722 4, 0xFFFF, sum = 0
5429 23:00:20.904046 5, 0xFFFF, sum = 0
5430 23:00:20.904467 6, 0xFFFF, sum = 0
5431 23:00:20.906773 7, 0xFFFF, sum = 0
5432 23:00:20.907327 8, 0xFFFF, sum = 0
5433 23:00:20.910417 9, 0xFFFF, sum = 0
5434 23:00:20.910835 10, 0x0, sum = 1
5435 23:00:20.913525 11, 0x0, sum = 2
5436 23:00:20.914023 12, 0x0, sum = 3
5437 23:00:20.916776 13, 0x0, sum = 4
5438 23:00:20.917289 best_step = 11
5439 23:00:20.917676
5440 23:00:20.918103 ==
5441 23:00:20.919986 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 23:00:20.926969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 23:00:20.927464 ==
5444 23:00:20.927801 RX Vref Scan: 0
5445 23:00:20.928207
5446 23:00:20.930184 RX Vref 0 -> 0, step: 1
5447 23:00:20.930600
5448 23:00:20.933674 RX Delay -45 -> 252, step: 4
5449 23:00:20.936626 iDelay=195, Bit 0, Center 102 (15 ~ 190) 176
5450 23:00:20.940016 iDelay=195, Bit 1, Center 106 (19 ~ 194) 176
5451 23:00:20.946856 iDelay=195, Bit 2, Center 102 (15 ~ 190) 176
5452 23:00:20.950147 iDelay=195, Bit 3, Center 102 (15 ~ 190) 176
5453 23:00:20.953354 iDelay=195, Bit 4, Center 106 (19 ~ 194) 176
5454 23:00:20.956739 iDelay=195, Bit 5, Center 96 (7 ~ 186) 180
5455 23:00:20.959843 iDelay=195, Bit 6, Center 110 (27 ~ 194) 168
5456 23:00:20.967205 iDelay=195, Bit 7, Center 110 (27 ~ 194) 168
5457 23:00:20.970128 iDelay=195, Bit 8, Center 84 (-1 ~ 170) 172
5458 23:00:20.973102 iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168
5459 23:00:20.977035 iDelay=195, Bit 10, Center 94 (11 ~ 178) 168
5460 23:00:20.979900 iDelay=195, Bit 11, Center 88 (7 ~ 170) 164
5461 23:00:20.986854 iDelay=195, Bit 12, Center 100 (19 ~ 182) 164
5462 23:00:20.990451 iDelay=195, Bit 13, Center 98 (15 ~ 182) 168
5463 23:00:20.993425 iDelay=195, Bit 14, Center 102 (19 ~ 186) 168
5464 23:00:20.996840 iDelay=195, Bit 15, Center 102 (19 ~ 186) 168
5465 23:00:20.997317 ==
5466 23:00:20.999721 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 23:00:21.003080 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 23:00:21.006771 ==
5469 23:00:21.007194 DQS Delay:
5470 23:00:21.007525 DQS0 = 0, DQS1 = 0
5471 23:00:21.010021 DQM Delay:
5472 23:00:21.010432 DQM0 = 104, DQM1 = 93
5473 23:00:21.013345 DQ Delay:
5474 23:00:21.016318 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5475 23:00:21.019884 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5476 23:00:21.022853 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5477 23:00:21.026830 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5478 23:00:21.027245
5479 23:00:21.027571
5480 23:00:21.032876 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c05, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5481 23:00:21.037172 CH0 RK1: MR19=505, MR18=2C05
5482 23:00:21.043363 CH0_RK1: MR19=0x505, MR18=0x2C05, DQSOSC=408, MR23=63, INC=65, DEC=43
5483 23:00:21.046608 [RxdqsGatingPostProcess] freq 933
5484 23:00:21.052721 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5485 23:00:21.053137 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 23:00:21.056755 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 23:00:21.060022 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 23:00:21.062737 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 23:00:21.066186 best DQS0 dly(2T, 0.5T) = (0, 10)
5490 23:00:21.069620 best DQS1 dly(2T, 0.5T) = (0, 10)
5491 23:00:21.072712 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5492 23:00:21.076245 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5493 23:00:21.079880 Pre-setting of DQS Precalculation
5494 23:00:21.083274 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5495 23:00:21.086295 ==
5496 23:00:21.086709 Dram Type= 6, Freq= 0, CH_1, rank 0
5497 23:00:21.092835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5498 23:00:21.093324 ==
5499 23:00:21.096208 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5500 23:00:21.102865 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5501 23:00:21.106687 [CA 0] Center 36 (6~67) winsize 62
5502 23:00:21.109827 [CA 1] Center 37 (6~68) winsize 63
5503 23:00:21.113459 [CA 2] Center 34 (4~65) winsize 62
5504 23:00:21.116632 [CA 3] Center 34 (4~65) winsize 62
5505 23:00:21.120054 [CA 4] Center 34 (4~65) winsize 62
5506 23:00:21.123396 [CA 5] Center 33 (3~64) winsize 62
5507 23:00:21.123811
5508 23:00:21.126475 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5509 23:00:21.126890
5510 23:00:21.129853 [CATrainingPosCal] consider 1 rank data
5511 23:00:21.133515 u2DelayCellTimex100 = 270/100 ps
5512 23:00:21.136680 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5513 23:00:21.140024 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5514 23:00:21.146143 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5515 23:00:21.149972 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5516 23:00:21.153196 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5517 23:00:21.156451 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5518 23:00:21.156861
5519 23:00:21.159804 CA PerBit enable=1, Macro0, CA PI delay=33
5520 23:00:21.160214
5521 23:00:21.163094 [CBTSetCACLKResult] CA Dly = 33
5522 23:00:21.163716 CS Dly: 7 (0~38)
5523 23:00:21.166653 ==
5524 23:00:21.167299 Dram Type= 6, Freq= 0, CH_1, rank 1
5525 23:00:21.173256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 23:00:21.173770 ==
5527 23:00:21.176556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5528 23:00:21.183024 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5529 23:00:21.186628 [CA 0] Center 36 (6~67) winsize 62
5530 23:00:21.189929 [CA 1] Center 37 (6~68) winsize 63
5531 23:00:21.193096 [CA 2] Center 35 (5~65) winsize 61
5532 23:00:21.196213 [CA 3] Center 34 (4~65) winsize 62
5533 23:00:21.199599 [CA 4] Center 34 (4~65) winsize 62
5534 23:00:21.203423 [CA 5] Center 33 (3~64) winsize 62
5535 23:00:21.203839
5536 23:00:21.206420 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5537 23:00:21.206832
5538 23:00:21.209905 [CATrainingPosCal] consider 2 rank data
5539 23:00:21.212669 u2DelayCellTimex100 = 270/100 ps
5540 23:00:21.215893 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5541 23:00:21.222770 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5542 23:00:21.226315 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5543 23:00:21.229350 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5544 23:00:21.232771 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5545 23:00:21.235915 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5546 23:00:21.236505
5547 23:00:21.239276 CA PerBit enable=1, Macro0, CA PI delay=33
5548 23:00:21.239814
5549 23:00:21.242925 [CBTSetCACLKResult] CA Dly = 33
5550 23:00:21.245833 CS Dly: 8 (0~40)
5551 23:00:21.246248
5552 23:00:21.249271 ----->DramcWriteLeveling(PI) begin...
5553 23:00:21.249732 ==
5554 23:00:21.252926 Dram Type= 6, Freq= 0, CH_1, rank 0
5555 23:00:21.256164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5556 23:00:21.256580 ==
5557 23:00:21.259606 Write leveling (Byte 0): 27 => 27
5558 23:00:21.262934 Write leveling (Byte 1): 27 => 27
5559 23:00:21.266120 DramcWriteLeveling(PI) end<-----
5560 23:00:21.266536
5561 23:00:21.266859 ==
5562 23:00:21.269641 Dram Type= 6, Freq= 0, CH_1, rank 0
5563 23:00:21.272587 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 23:00:21.273017 ==
5565 23:00:21.276074 [Gating] SW mode calibration
5566 23:00:21.282856 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5567 23:00:21.289426 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5568 23:00:21.292788 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 23:00:21.296141 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 23:00:21.302836 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 23:00:21.306305 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5572 23:00:21.309348 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5573 23:00:21.315533 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5574 23:00:21.319481 0 14 24 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)
5575 23:00:21.322461 0 14 28 | B1->B0 | 2828 2323 | 0 0 | (1 0) (1 0)
5576 23:00:21.329158 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 23:00:21.332383 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 23:00:21.335551 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 23:00:21.342507 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5580 23:00:21.346126 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5581 23:00:21.348907 0 15 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5582 23:00:21.352123 0 15 24 | B1->B0 | 2525 3636 | 0 1 | (0 0) (0 0)
5583 23:00:21.358770 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
5584 23:00:21.362804 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 23:00:21.365969 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 23:00:21.372092 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 23:00:21.375353 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5588 23:00:21.378792 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5589 23:00:21.385882 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5590 23:00:21.389249 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5591 23:00:21.392433 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:00:21.398698 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:00:21.402510 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 23:00:21.405541 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 23:00:21.411827 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 23:00:21.415361 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 23:00:21.418664 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 23:00:21.425432 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 23:00:21.429280 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 23:00:21.432359 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 23:00:21.438802 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 23:00:21.442510 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 23:00:21.445563 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5604 23:00:21.452275 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5605 23:00:21.455471 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5606 23:00:21.459120 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5607 23:00:21.462085 Total UI for P1: 0, mck2ui 16
5608 23:00:21.465236 best dqsien dly found for B0: ( 1, 2, 20)
5609 23:00:21.468644 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5610 23:00:21.475288 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 23:00:21.479205 Total UI for P1: 0, mck2ui 16
5612 23:00:21.482427 best dqsien dly found for B1: ( 1, 2, 24)
5613 23:00:21.485703 best DQS0 dly(MCK, UI, PI) = (1, 2, 20)
5614 23:00:21.488579 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5615 23:00:21.488992
5616 23:00:21.492072 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 20)
5617 23:00:21.495660 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5618 23:00:21.498809 [Gating] SW calibration Done
5619 23:00:21.499242 ==
5620 23:00:21.502393 Dram Type= 6, Freq= 0, CH_1, rank 0
5621 23:00:21.505853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5622 23:00:21.506271 ==
5623 23:00:21.508906 RX Vref Scan: 0
5624 23:00:21.509428
5625 23:00:21.512317 RX Vref 0 -> 0, step: 1
5626 23:00:21.512733
5627 23:00:21.513141 RX Delay -80 -> 252, step: 8
5628 23:00:21.518422 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5629 23:00:21.521681 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5630 23:00:21.525200 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5631 23:00:21.528522 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5632 23:00:21.532289 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5633 23:00:21.535079 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5634 23:00:21.541750 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5635 23:00:21.545350 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5636 23:00:21.548186 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5637 23:00:21.551620 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5638 23:00:21.555078 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5639 23:00:21.558262 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5640 23:00:21.564929 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5641 23:00:21.568181 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5642 23:00:21.572218 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5643 23:00:21.574851 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5644 23:00:21.575264 ==
5645 23:00:21.578352 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 23:00:21.585096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 23:00:21.585801 ==
5648 23:00:21.586154 DQS Delay:
5649 23:00:21.586489 DQS0 = 0, DQS1 = 0
5650 23:00:21.588637 DQM Delay:
5651 23:00:21.589062 DQM0 = 103, DQM1 = 98
5652 23:00:21.591906 DQ Delay:
5653 23:00:21.595003 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5654 23:00:21.598627 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5655 23:00:21.601503 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5656 23:00:21.604862 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5657 23:00:21.605278
5658 23:00:21.605727
5659 23:00:21.606056 ==
5660 23:00:21.608266 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 23:00:21.611294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 23:00:21.611734 ==
5663 23:00:21.612268
5664 23:00:21.612627
5665 23:00:21.614627 TX Vref Scan disable
5666 23:00:21.618042 == TX Byte 0 ==
5667 23:00:21.621383 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5668 23:00:21.625210 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5669 23:00:21.628361 == TX Byte 1 ==
5670 23:00:21.631410 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5671 23:00:21.634548 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5672 23:00:21.634963 ==
5673 23:00:21.637958 Dram Type= 6, Freq= 0, CH_1, rank 0
5674 23:00:21.641856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5675 23:00:21.644727 ==
5676 23:00:21.645138
5677 23:00:21.645463
5678 23:00:21.645812 TX Vref Scan disable
5679 23:00:21.648174 == TX Byte 0 ==
5680 23:00:21.651799 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5681 23:00:21.658259 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5682 23:00:21.658670 == TX Byte 1 ==
5683 23:00:21.661361 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5684 23:00:21.668430 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5685 23:00:21.668845
5686 23:00:21.669169 [DATLAT]
5687 23:00:21.669475 Freq=933, CH1 RK0
5688 23:00:21.669801
5689 23:00:21.671777 DATLAT Default: 0xd
5690 23:00:21.672189 0, 0xFFFF, sum = 0
5691 23:00:21.675191 1, 0xFFFF, sum = 0
5692 23:00:21.678541 2, 0xFFFF, sum = 0
5693 23:00:21.678961 3, 0xFFFF, sum = 0
5694 23:00:21.681467 4, 0xFFFF, sum = 0
5695 23:00:21.681921 5, 0xFFFF, sum = 0
5696 23:00:21.684905 6, 0xFFFF, sum = 0
5697 23:00:21.685490 7, 0xFFFF, sum = 0
5698 23:00:21.687894 8, 0xFFFF, sum = 0
5699 23:00:21.687982 9, 0xFFFF, sum = 0
5700 23:00:21.691254 10, 0x0, sum = 1
5701 23:00:21.691336 11, 0x0, sum = 2
5702 23:00:21.694652 12, 0x0, sum = 3
5703 23:00:21.694734 13, 0x0, sum = 4
5704 23:00:21.694800 best_step = 11
5705 23:00:21.697610
5706 23:00:21.697704 ==
5707 23:00:21.700869 Dram Type= 6, Freq= 0, CH_1, rank 0
5708 23:00:21.704695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5709 23:00:21.704784 ==
5710 23:00:21.704853 RX Vref Scan: 1
5711 23:00:21.704918
5712 23:00:21.707477 RX Vref 0 -> 0, step: 1
5713 23:00:21.707570
5714 23:00:21.711213 RX Delay -45 -> 252, step: 4
5715 23:00:21.711306
5716 23:00:21.714377 Set Vref, RX VrefLevel [Byte0]: 54
5717 23:00:21.718185 [Byte1]: 48
5718 23:00:21.718604
5719 23:00:21.721126 Final RX Vref Byte 0 = 54 to rank0
5720 23:00:21.724532 Final RX Vref Byte 1 = 48 to rank0
5721 23:00:21.727768 Final RX Vref Byte 0 = 54 to rank1
5722 23:00:21.731399 Final RX Vref Byte 1 = 48 to rank1==
5723 23:00:21.734316 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 23:00:21.737571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 23:00:21.741035 ==
5726 23:00:21.741449 DQS Delay:
5727 23:00:21.741902 DQS0 = 0, DQS1 = 0
5728 23:00:21.744572 DQM Delay:
5729 23:00:21.744987 DQM0 = 102, DQM1 = 99
5730 23:00:21.747521 DQ Delay:
5731 23:00:21.751253 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =100
5732 23:00:21.754419 DQ4 =102, DQ5 =112, DQ6 =110, DQ7 =102
5733 23:00:21.757687 DQ8 =90, DQ9 =90, DQ10 =98, DQ11 =90
5734 23:00:21.761224 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108
5735 23:00:21.761753
5736 23:00:21.762093
5737 23:00:21.767675 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5738 23:00:21.771023 CH1 RK0: MR19=505, MR18=1830
5739 23:00:21.777655 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5740 23:00:21.778092
5741 23:00:21.780867 ----->DramcWriteLeveling(PI) begin...
5742 23:00:21.781310 ==
5743 23:00:21.784306 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 23:00:21.787795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 23:00:21.788232 ==
5746 23:00:21.790736 Write leveling (Byte 0): 25 => 25
5747 23:00:21.794084 Write leveling (Byte 1): 30 => 30
5748 23:00:21.797250 DramcWriteLeveling(PI) end<-----
5749 23:00:21.797722
5750 23:00:21.798162 ==
5751 23:00:21.800724 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 23:00:21.803892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 23:00:21.807484 ==
5754 23:00:21.807915 [Gating] SW mode calibration
5755 23:00:21.817531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5756 23:00:21.820851 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5757 23:00:21.824073 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 23:00:21.831409 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 23:00:21.833965 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5760 23:00:21.837180 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5761 23:00:21.844175 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5762 23:00:21.847259 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5763 23:00:21.850638 0 14 24 | B1->B0 | 2f2f 3232 | 1 1 | (1 0) (1 1)
5764 23:00:21.857554 0 14 28 | B1->B0 | 2323 2828 | 0 0 | (1 0) (1 0)
5765 23:00:21.860901 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 23:00:21.864090 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 23:00:21.870904 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5768 23:00:21.873816 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5769 23:00:21.877168 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5770 23:00:21.884159 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5771 23:00:21.887153 0 15 24 | B1->B0 | 3636 2828 | 1 0 | (0 0) (0 0)
5772 23:00:21.890524 0 15 28 | B1->B0 | 4545 3d3d | 0 0 | (0 0) (0 0)
5773 23:00:21.897141 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 23:00:21.900578 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 23:00:21.903624 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5776 23:00:21.910320 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5777 23:00:21.913693 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5778 23:00:21.916977 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5779 23:00:21.920481 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5780 23:00:21.926601 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:00:21.930769 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:00:21.933651 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 23:00:21.940182 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 23:00:21.943526 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 23:00:21.946768 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 23:00:21.953328 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 23:00:21.956756 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 23:00:21.959971 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 23:00:21.966804 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 23:00:21.970452 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 23:00:21.973394 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5792 23:00:21.979910 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5793 23:00:21.983562 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5794 23:00:21.987138 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5795 23:00:21.993477 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5796 23:00:21.996622 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5797 23:00:21.999878 Total UI for P1: 0, mck2ui 16
5798 23:00:22.003298 best dqsien dly found for B1: ( 1, 2, 24)
5799 23:00:22.006510 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 23:00:22.010062 Total UI for P1: 0, mck2ui 16
5801 23:00:22.013050 best dqsien dly found for B0: ( 1, 2, 26)
5802 23:00:22.016745 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5803 23:00:22.019875 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5804 23:00:22.020287
5805 23:00:22.026464 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5806 23:00:22.029931 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5807 23:00:22.030347 [Gating] SW calibration Done
5808 23:00:22.032970 ==
5809 23:00:22.036364 Dram Type= 6, Freq= 0, CH_1, rank 1
5810 23:00:22.039853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5811 23:00:22.040267 ==
5812 23:00:22.040595 RX Vref Scan: 0
5813 23:00:22.040899
5814 23:00:22.043185 RX Vref 0 -> 0, step: 1
5815 23:00:22.043600
5816 23:00:22.046204 RX Delay -80 -> 252, step: 8
5817 23:00:22.049502 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5818 23:00:22.052988 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5819 23:00:22.056664 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5820 23:00:22.062838 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5821 23:00:22.066454 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5822 23:00:22.069330 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5823 23:00:22.072847 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5824 23:00:22.076480 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5825 23:00:22.079783 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5826 23:00:22.086278 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5827 23:00:22.089343 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5828 23:00:22.092785 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5829 23:00:22.096207 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5830 23:00:22.099670 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5831 23:00:22.102887 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5832 23:00:22.109742 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5833 23:00:22.110168 ==
5834 23:00:22.112681 Dram Type= 6, Freq= 0, CH_1, rank 1
5835 23:00:22.116131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5836 23:00:22.116564 ==
5837 23:00:22.116893 DQS Delay:
5838 23:00:22.119300 DQS0 = 0, DQS1 = 0
5839 23:00:22.119717 DQM Delay:
5840 23:00:22.122605 DQM0 = 103, DQM1 = 98
5841 23:00:22.123016 DQ Delay:
5842 23:00:22.125898 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5843 23:00:22.129752 DQ4 =95, DQ5 =119, DQ6 =115, DQ7 =99
5844 23:00:22.133127 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5845 23:00:22.136114 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5846 23:00:22.136529
5847 23:00:22.136855
5848 23:00:22.137156 ==
5849 23:00:22.139235 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 23:00:22.146079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 23:00:22.146499 ==
5852 23:00:22.146845
5853 23:00:22.147188
5854 23:00:22.147528 TX Vref Scan disable
5855 23:00:22.149531 == TX Byte 0 ==
5856 23:00:22.152800 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5857 23:00:22.159377 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5858 23:00:22.159933 == TX Byte 1 ==
5859 23:00:22.163357 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5860 23:00:22.169430 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5861 23:00:22.169887 ==
5862 23:00:22.172594 Dram Type= 6, Freq= 0, CH_1, rank 1
5863 23:00:22.175891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5864 23:00:22.175972 ==
5865 23:00:22.176037
5866 23:00:22.176097
5867 23:00:22.178819 TX Vref Scan disable
5868 23:00:22.178900 == TX Byte 0 ==
5869 23:00:22.185861 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5870 23:00:22.188544 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5871 23:00:22.192126 == TX Byte 1 ==
5872 23:00:22.195195 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5873 23:00:22.198505 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5874 23:00:22.198587
5875 23:00:22.198650 [DATLAT]
5876 23:00:22.202299 Freq=933, CH1 RK1
5877 23:00:22.202386
5878 23:00:22.202453 DATLAT Default: 0xb
5879 23:00:22.205479 0, 0xFFFF, sum = 0
5880 23:00:22.208725 1, 0xFFFF, sum = 0
5881 23:00:22.208819 2, 0xFFFF, sum = 0
5882 23:00:22.212150 3, 0xFFFF, sum = 0
5883 23:00:22.212251 4, 0xFFFF, sum = 0
5884 23:00:22.215403 5, 0xFFFF, sum = 0
5885 23:00:22.215566 6, 0xFFFF, sum = 0
5886 23:00:22.218673 7, 0xFFFF, sum = 0
5887 23:00:22.218787 8, 0xFFFF, sum = 0
5888 23:00:22.222317 9, 0xFFFF, sum = 0
5889 23:00:22.222398 10, 0x0, sum = 1
5890 23:00:22.225506 11, 0x0, sum = 2
5891 23:00:22.225610 12, 0x0, sum = 3
5892 23:00:22.228745 13, 0x0, sum = 4
5893 23:00:22.228831 best_step = 11
5894 23:00:22.228899
5895 23:00:22.228961 ==
5896 23:00:22.231935 Dram Type= 6, Freq= 0, CH_1, rank 1
5897 23:00:22.235729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5898 23:00:22.236174 ==
5899 23:00:22.239107 RX Vref Scan: 0
5900 23:00:22.239602
5901 23:00:22.242017 RX Vref 0 -> 0, step: 1
5902 23:00:22.242430
5903 23:00:22.242846 RX Delay -45 -> 252, step: 4
5904 23:00:22.249794 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5905 23:00:22.253303 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5906 23:00:22.256521 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5907 23:00:22.259951 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5908 23:00:22.263425 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5909 23:00:22.269802 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5910 23:00:22.273151 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5911 23:00:22.276135 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5912 23:00:22.279602 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5913 23:00:22.283195 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5914 23:00:22.289470 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5915 23:00:22.293009 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5916 23:00:22.296402 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5917 23:00:22.299592 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5918 23:00:22.303212 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5919 23:00:22.309428 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5920 23:00:22.309881 ==
5921 23:00:22.312987 Dram Type= 6, Freq= 0, CH_1, rank 1
5922 23:00:22.316265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5923 23:00:22.316686 ==
5924 23:00:22.317063 DQS Delay:
5925 23:00:22.319500 DQS0 = 0, DQS1 = 0
5926 23:00:22.319916 DQM Delay:
5927 23:00:22.322983 DQM0 = 105, DQM1 = 100
5928 23:00:22.323506 DQ Delay:
5929 23:00:22.326219 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =100
5930 23:00:22.329301 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5931 23:00:22.332964 DQ8 =88, DQ9 =88, DQ10 =102, DQ11 =92
5932 23:00:22.336218 DQ12 =110, DQ13 =108, DQ14 =106, DQ15 =108
5933 23:00:22.336633
5934 23:00:22.336957
5935 23:00:22.346526 [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5936 23:00:22.350086 CH1 RK1: MR19=505, MR18=2D01
5937 23:00:22.352629 CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43
5938 23:00:22.356536 [RxdqsGatingPostProcess] freq 933
5939 23:00:22.363143 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5940 23:00:22.366527 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 23:00:22.369878 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 23:00:22.372772 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 23:00:22.376270 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 23:00:22.379488 best DQS0 dly(2T, 0.5T) = (0, 10)
5945 23:00:22.382849 best DQS1 dly(2T, 0.5T) = (0, 10)
5946 23:00:22.386050 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5947 23:00:22.389415 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5948 23:00:22.389862 Pre-setting of DQS Precalculation
5949 23:00:22.395882 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5950 23:00:22.402447 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5951 23:00:22.409476 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5952 23:00:22.409937
5953 23:00:22.410269
5954 23:00:22.412579 [Calibration Summary] 1866 Mbps
5955 23:00:22.415626 CH 0, Rank 0
5956 23:00:22.416042 SW Impedance : PASS
5957 23:00:22.419276 DUTY Scan : NO K
5958 23:00:22.422204 ZQ Calibration : PASS
5959 23:00:22.422623 Jitter Meter : NO K
5960 23:00:22.426071 CBT Training : PASS
5961 23:00:22.429309 Write leveling : PASS
5962 23:00:22.429767 RX DQS gating : PASS
5963 23:00:22.432632 RX DQ/DQS(RDDQC) : PASS
5964 23:00:22.435803 TX DQ/DQS : PASS
5965 23:00:22.436357 RX DATLAT : PASS
5966 23:00:22.439316 RX DQ/DQS(Engine): PASS
5967 23:00:22.439732 TX OE : NO K
5968 23:00:22.442574 All Pass.
5969 23:00:22.442987
5970 23:00:22.443314 CH 0, Rank 1
5971 23:00:22.445885 SW Impedance : PASS
5972 23:00:22.446297 DUTY Scan : NO K
5973 23:00:22.449004 ZQ Calibration : PASS
5974 23:00:22.452292 Jitter Meter : NO K
5975 23:00:22.452732 CBT Training : PASS
5976 23:00:22.455739 Write leveling : PASS
5977 23:00:22.459054 RX DQS gating : PASS
5978 23:00:22.459464 RX DQ/DQS(RDDQC) : PASS
5979 23:00:22.462531 TX DQ/DQS : PASS
5980 23:00:22.465781 RX DATLAT : PASS
5981 23:00:22.466193 RX DQ/DQS(Engine): PASS
5982 23:00:22.468939 TX OE : NO K
5983 23:00:22.469350 All Pass.
5984 23:00:22.469710
5985 23:00:22.472388 CH 1, Rank 0
5986 23:00:22.472798 SW Impedance : PASS
5987 23:00:22.475654 DUTY Scan : NO K
5988 23:00:22.478987 ZQ Calibration : PASS
5989 23:00:22.479402 Jitter Meter : NO K
5990 23:00:22.482589 CBT Training : PASS
5991 23:00:22.485526 Write leveling : PASS
5992 23:00:22.486027 RX DQS gating : PASS
5993 23:00:22.489166 RX DQ/DQS(RDDQC) : PASS
5994 23:00:22.489632 TX DQ/DQS : PASS
5995 23:00:22.492202 RX DATLAT : PASS
5996 23:00:22.495549 RX DQ/DQS(Engine): PASS
5997 23:00:22.496008 TX OE : NO K
5998 23:00:22.498556 All Pass.
5999 23:00:22.498962
6000 23:00:22.499285 CH 1, Rank 1
6001 23:00:22.502368 SW Impedance : PASS
6002 23:00:22.502826 DUTY Scan : NO K
6003 23:00:22.505728 ZQ Calibration : PASS
6004 23:00:22.509020 Jitter Meter : NO K
6005 23:00:22.509460 CBT Training : PASS
6006 23:00:22.512027 Write leveling : PASS
6007 23:00:22.515602 RX DQS gating : PASS
6008 23:00:22.516022 RX DQ/DQS(RDDQC) : PASS
6009 23:00:22.518769 TX DQ/DQS : PASS
6010 23:00:22.521909 RX DATLAT : PASS
6011 23:00:22.522317 RX DQ/DQS(Engine): PASS
6012 23:00:22.525695 TX OE : NO K
6013 23:00:22.526120 All Pass.
6014 23:00:22.526450
6015 23:00:22.528438 DramC Write-DBI off
6016 23:00:22.532165 PER_BANK_REFRESH: Hybrid Mode
6017 23:00:22.532579 TX_TRACKING: ON
6018 23:00:22.542087 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6019 23:00:22.545686 [FAST_K] Save calibration result to emmc
6020 23:00:22.548706 dramc_set_vcore_voltage set vcore to 650000
6021 23:00:22.551967 Read voltage for 400, 6
6022 23:00:22.552459 Vio18 = 0
6023 23:00:22.552896 Vcore = 650000
6024 23:00:22.555033 Vdram = 0
6025 23:00:22.555464 Vddq = 0
6026 23:00:22.556085 Vmddr = 0
6027 23:00:22.561898 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6028 23:00:22.565397 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6029 23:00:22.568436 MEM_TYPE=3, freq_sel=20
6030 23:00:22.571608 sv_algorithm_assistance_LP4_800
6031 23:00:22.575603 ============ PULL DRAM RESETB DOWN ============
6032 23:00:22.578484 ========== PULL DRAM RESETB DOWN end =========
6033 23:00:22.585296 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6034 23:00:22.588369 ===================================
6035 23:00:22.588787 LPDDR4 DRAM CONFIGURATION
6036 23:00:22.591958 ===================================
6037 23:00:22.595311 EX_ROW_EN[0] = 0x0
6038 23:00:22.598711 EX_ROW_EN[1] = 0x0
6039 23:00:22.599122 LP4Y_EN = 0x0
6040 23:00:22.601612 WORK_FSP = 0x0
6041 23:00:22.602029 WL = 0x2
6042 23:00:22.605052 RL = 0x2
6043 23:00:22.605466 BL = 0x2
6044 23:00:22.608571 RPST = 0x0
6045 23:00:22.608987 RD_PRE = 0x0
6046 23:00:22.611622 WR_PRE = 0x1
6047 23:00:22.612034 WR_PST = 0x0
6048 23:00:22.614954 DBI_WR = 0x0
6049 23:00:22.615370 DBI_RD = 0x0
6050 23:00:22.618190 OTF = 0x1
6051 23:00:22.621909 ===================================
6052 23:00:22.625095 ===================================
6053 23:00:22.625511 ANA top config
6054 23:00:22.628133 ===================================
6055 23:00:22.631739 DLL_ASYNC_EN = 0
6056 23:00:22.634635 ALL_SLAVE_EN = 1
6057 23:00:22.637948 NEW_RANK_MODE = 1
6058 23:00:22.638424 DLL_IDLE_MODE = 1
6059 23:00:22.641665 LP45_APHY_COMB_EN = 1
6060 23:00:22.644839 TX_ODT_DIS = 1
6061 23:00:22.648523 NEW_8X_MODE = 1
6062 23:00:22.651825 ===================================
6063 23:00:22.654954 ===================================
6064 23:00:22.655471 data_rate = 800
6065 23:00:22.658537 CKR = 1
6066 23:00:22.661564 DQ_P2S_RATIO = 4
6067 23:00:22.665271 ===================================
6068 23:00:22.668879 CA_P2S_RATIO = 4
6069 23:00:22.671450 DQ_CA_OPEN = 0
6070 23:00:22.674951 DQ_SEMI_OPEN = 1
6071 23:00:22.675388 CA_SEMI_OPEN = 1
6072 23:00:22.678249 CA_FULL_RATE = 0
6073 23:00:22.681403 DQ_CKDIV4_EN = 0
6074 23:00:22.684907 CA_CKDIV4_EN = 1
6075 23:00:22.688393 CA_PREDIV_EN = 0
6076 23:00:22.691858 PH8_DLY = 0
6077 23:00:22.692284 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6078 23:00:22.695193 DQ_AAMCK_DIV = 0
6079 23:00:22.698110 CA_AAMCK_DIV = 0
6080 23:00:22.701306 CA_ADMCK_DIV = 4
6081 23:00:22.704738 DQ_TRACK_CA_EN = 0
6082 23:00:22.708147 CA_PICK = 800
6083 23:00:22.711266 CA_MCKIO = 400
6084 23:00:22.711767 MCKIO_SEMI = 400
6085 23:00:22.715054 PLL_FREQ = 3016
6086 23:00:22.718335 DQ_UI_PI_RATIO = 32
6087 23:00:22.721735 CA_UI_PI_RATIO = 32
6088 23:00:22.724705 ===================================
6089 23:00:22.728382 ===================================
6090 23:00:22.731882 memory_type:LPDDR4
6091 23:00:22.732372 GP_NUM : 10
6092 23:00:22.735090 SRAM_EN : 1
6093 23:00:22.737832 MD32_EN : 0
6094 23:00:22.741741 ===================================
6095 23:00:22.742171 [ANA_INIT] >>>>>>>>>>>>>>
6096 23:00:22.744889 <<<<<< [CONFIGURE PHASE]: ANA_TX
6097 23:00:22.747967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6098 23:00:22.751120 ===================================
6099 23:00:22.755015 data_rate = 800,PCW = 0X7400
6100 23:00:22.757866 ===================================
6101 23:00:22.761262 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6102 23:00:22.768305 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6103 23:00:22.777655 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6104 23:00:22.781501 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6105 23:00:22.788101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6106 23:00:22.791110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6107 23:00:22.791550 [ANA_INIT] flow start
6108 23:00:22.794358 [ANA_INIT] PLL >>>>>>>>
6109 23:00:22.797673 [ANA_INIT] PLL <<<<<<<<
6110 23:00:22.798094 [ANA_INIT] MIDPI >>>>>>>>
6111 23:00:22.801438 [ANA_INIT] MIDPI <<<<<<<<
6112 23:00:22.804175 [ANA_INIT] DLL >>>>>>>>
6113 23:00:22.804747 [ANA_INIT] flow end
6114 23:00:22.807660 ============ LP4 DIFF to SE enter ============
6115 23:00:22.814205 ============ LP4 DIFF to SE exit ============
6116 23:00:22.814628 [ANA_INIT] <<<<<<<<<<<<<
6117 23:00:22.817643 [Flow] Enable top DCM control >>>>>
6118 23:00:22.820698 [Flow] Enable top DCM control <<<<<
6119 23:00:22.824387 Enable DLL master slave shuffle
6120 23:00:22.830919 ==============================================================
6121 23:00:22.831415 Gating Mode config
6122 23:00:22.837042 ==============================================================
6123 23:00:22.840423 Config description:
6124 23:00:22.850372 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6125 23:00:22.857558 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6126 23:00:22.860252 SELPH_MODE 0: By rank 1: By Phase
6127 23:00:22.866916 ==============================================================
6128 23:00:22.870831 GAT_TRACK_EN = 0
6129 23:00:22.873881 RX_GATING_MODE = 2
6130 23:00:22.874308 RX_GATING_TRACK_MODE = 2
6131 23:00:22.877496 SELPH_MODE = 1
6132 23:00:22.880651 PICG_EARLY_EN = 1
6133 23:00:22.883549 VALID_LAT_VALUE = 1
6134 23:00:22.890449 ==============================================================
6135 23:00:22.893563 Enter into Gating configuration >>>>
6136 23:00:22.896668 Exit from Gating configuration <<<<
6137 23:00:22.900287 Enter into DVFS_PRE_config >>>>>
6138 23:00:22.910099 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6139 23:00:22.913442 Exit from DVFS_PRE_config <<<<<
6140 23:00:22.917070 Enter into PICG configuration >>>>
6141 23:00:22.920108 Exit from PICG configuration <<<<
6142 23:00:22.923821 [RX_INPUT] configuration >>>>>
6143 23:00:22.926961 [RX_INPUT] configuration <<<<<
6144 23:00:22.930467 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6145 23:00:22.936959 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6146 23:00:22.943626 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6147 23:00:22.950059 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6148 23:00:22.953425 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6149 23:00:22.960356 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6150 23:00:22.963711 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6151 23:00:22.970012 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6152 23:00:22.973337 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6153 23:00:22.976565 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6154 23:00:22.980058 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6155 23:00:22.986826 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6156 23:00:22.990338 ===================================
6157 23:00:22.990587 LPDDR4 DRAM CONFIGURATION
6158 23:00:22.993653 ===================================
6159 23:00:22.996743 EX_ROW_EN[0] = 0x0
6160 23:00:23.000687 EX_ROW_EN[1] = 0x0
6161 23:00:23.001028 LP4Y_EN = 0x0
6162 23:00:23.003556 WORK_FSP = 0x0
6163 23:00:23.004033 WL = 0x2
6164 23:00:23.007076 RL = 0x2
6165 23:00:23.007494 BL = 0x2
6166 23:00:23.010526 RPST = 0x0
6167 23:00:23.010942 RD_PRE = 0x0
6168 23:00:23.013840 WR_PRE = 0x1
6169 23:00:23.014415 WR_PST = 0x0
6170 23:00:23.017044 DBI_WR = 0x0
6171 23:00:23.017653 DBI_RD = 0x0
6172 23:00:23.020401 OTF = 0x1
6173 23:00:23.023766 ===================================
6174 23:00:23.026853 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6175 23:00:23.030401 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6176 23:00:23.037168 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 23:00:23.040506 ===================================
6178 23:00:23.040953 LPDDR4 DRAM CONFIGURATION
6179 23:00:23.043912 ===================================
6180 23:00:23.047246 EX_ROW_EN[0] = 0x10
6181 23:00:23.047659 EX_ROW_EN[1] = 0x0
6182 23:00:23.050509 LP4Y_EN = 0x0
6183 23:00:23.050923 WORK_FSP = 0x0
6184 23:00:23.053704 WL = 0x2
6185 23:00:23.057668 RL = 0x2
6186 23:00:23.058081 BL = 0x2
6187 23:00:23.060766 RPST = 0x0
6188 23:00:23.061178 RD_PRE = 0x0
6189 23:00:23.064690 WR_PRE = 0x1
6190 23:00:23.065212 WR_PST = 0x0
6191 23:00:23.067490 DBI_WR = 0x0
6192 23:00:23.067904 DBI_RD = 0x0
6193 23:00:23.070371 OTF = 0x1
6194 23:00:23.073776 ===================================
6195 23:00:23.076968 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6196 23:00:23.083005 nWR fixed to 30
6197 23:00:23.085915 [ModeRegInit_LP4] CH0 RK0
6198 23:00:23.086325 [ModeRegInit_LP4] CH0 RK1
6199 23:00:23.089073 [ModeRegInit_LP4] CH1 RK0
6200 23:00:23.092772 [ModeRegInit_LP4] CH1 RK1
6201 23:00:23.093188 match AC timing 19
6202 23:00:23.099347 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6203 23:00:23.102565 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6204 23:00:23.106076 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6205 23:00:23.112448 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6206 23:00:23.115788 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6207 23:00:23.116206 ==
6208 23:00:23.119626 Dram Type= 6, Freq= 0, CH_0, rank 0
6209 23:00:23.122359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6210 23:00:23.122778 ==
6211 23:00:23.129013 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6212 23:00:23.135778 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6213 23:00:23.139351 [CA 0] Center 36 (8~64) winsize 57
6214 23:00:23.142879 [CA 1] Center 36 (8~64) winsize 57
6215 23:00:23.145818 [CA 2] Center 36 (8~64) winsize 57
6216 23:00:23.146237 [CA 3] Center 36 (8~64) winsize 57
6217 23:00:23.149069 [CA 4] Center 36 (8~64) winsize 57
6218 23:00:23.152716 [CA 5] Center 36 (8~64) winsize 57
6219 23:00:23.153146
6220 23:00:23.156353 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6221 23:00:23.159354
6222 23:00:23.163177 [CATrainingPosCal] consider 1 rank data
6223 23:00:23.163639 u2DelayCellTimex100 = 270/100 ps
6224 23:00:23.169476 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 23:00:23.172611 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 23:00:23.175499 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6227 23:00:23.178977 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6228 23:00:23.182040 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6229 23:00:23.185825 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6230 23:00:23.186292
6231 23:00:23.188729 CA PerBit enable=1, Macro0, CA PI delay=36
6232 23:00:23.189196
6233 23:00:23.191807 [CBTSetCACLKResult] CA Dly = 36
6234 23:00:23.195542 CS Dly: 1 (0~32)
6235 23:00:23.195957 ==
6236 23:00:23.198592 Dram Type= 6, Freq= 0, CH_0, rank 1
6237 23:00:23.201974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6238 23:00:23.202393 ==
6239 23:00:23.208779 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6240 23:00:23.215189 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6241 23:00:23.218112 [CA 0] Center 36 (8~64) winsize 57
6242 23:00:23.218523 [CA 1] Center 36 (8~64) winsize 57
6243 23:00:23.221669 [CA 2] Center 36 (8~64) winsize 57
6244 23:00:23.224968 [CA 3] Center 36 (8~64) winsize 57
6245 23:00:23.228554 [CA 4] Center 36 (8~64) winsize 57
6246 23:00:23.231650 [CA 5] Center 36 (8~64) winsize 57
6247 23:00:23.232066
6248 23:00:23.235054 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6249 23:00:23.235471
6250 23:00:23.238478 [CATrainingPosCal] consider 2 rank data
6251 23:00:23.241521 u2DelayCellTimex100 = 270/100 ps
6252 23:00:23.244959 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 23:00:23.252063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 23:00:23.254676 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6255 23:00:23.257815 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6256 23:00:23.261344 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6257 23:00:23.264521 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6258 23:00:23.265131
6259 23:00:23.268074 CA PerBit enable=1, Macro0, CA PI delay=36
6260 23:00:23.268679
6261 23:00:23.271278 [CBTSetCACLKResult] CA Dly = 36
6262 23:00:23.274577 CS Dly: 1 (0~32)
6263 23:00:23.275116
6264 23:00:23.278261 ----->DramcWriteLeveling(PI) begin...
6265 23:00:23.278687 ==
6266 23:00:23.280935 Dram Type= 6, Freq= 0, CH_0, rank 0
6267 23:00:23.284611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6268 23:00:23.285213 ==
6269 23:00:23.287985 Write leveling (Byte 0): 40 => 8
6270 23:00:23.290839 Write leveling (Byte 1): 40 => 8
6271 23:00:23.294314 DramcWriteLeveling(PI) end<-----
6272 23:00:23.294860
6273 23:00:23.295330 ==
6274 23:00:23.297384 Dram Type= 6, Freq= 0, CH_0, rank 0
6275 23:00:23.301223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6276 23:00:23.301875 ==
6277 23:00:23.304645 [Gating] SW mode calibration
6278 23:00:23.311060 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6279 23:00:23.317491 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6280 23:00:23.321041 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6281 23:00:23.323970 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6282 23:00:23.330680 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6283 23:00:23.333763 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 23:00:23.337490 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6285 23:00:23.343995 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6286 23:00:23.347120 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6287 23:00:23.350375 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6288 23:00:23.357633 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6289 23:00:23.358058 Total UI for P1: 0, mck2ui 16
6290 23:00:23.364336 best dqsien dly found for B0: ( 0, 14, 24)
6291 23:00:23.364756 Total UI for P1: 0, mck2ui 16
6292 23:00:23.370564 best dqsien dly found for B1: ( 0, 14, 24)
6293 23:00:23.373972 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6294 23:00:23.377301 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6295 23:00:23.377768
6296 23:00:23.380190 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6297 23:00:23.383856 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6298 23:00:23.386870 [Gating] SW calibration Done
6299 23:00:23.386950 ==
6300 23:00:23.389837 Dram Type= 6, Freq= 0, CH_0, rank 0
6301 23:00:23.393287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 23:00:23.393368 ==
6303 23:00:23.396672 RX Vref Scan: 0
6304 23:00:23.396752
6305 23:00:23.396816 RX Vref 0 -> 0, step: 1
6306 23:00:23.396876
6307 23:00:23.399877 RX Delay -410 -> 252, step: 16
6308 23:00:23.406862 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6309 23:00:23.409889 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6310 23:00:23.413229 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6311 23:00:23.416837 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6312 23:00:23.423600 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6313 23:00:23.426792 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6314 23:00:23.429745 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6315 23:00:23.433365 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6316 23:00:23.440357 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6317 23:00:23.442979 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6318 23:00:23.446486 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6319 23:00:23.450024 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6320 23:00:23.456683 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6321 23:00:23.460160 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6322 23:00:23.463066 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6323 23:00:23.467054 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6324 23:00:23.470188 ==
6325 23:00:23.470477 Dram Type= 6, Freq= 0, CH_0, rank 0
6326 23:00:23.476934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6327 23:00:23.477471 ==
6328 23:00:23.477930 DQS Delay:
6329 23:00:23.480058 DQS0 = 27, DQS1 = 35
6330 23:00:23.480535 DQM Delay:
6331 23:00:23.483304 DQM0 = 9, DQM1 = 12
6332 23:00:23.483725 DQ Delay:
6333 23:00:23.486983 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6334 23:00:23.490501 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6335 23:00:23.490909 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6336 23:00:23.496836 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6337 23:00:23.497308
6338 23:00:23.497777
6339 23:00:23.498170 ==
6340 23:00:23.499959 Dram Type= 6, Freq= 0, CH_0, rank 0
6341 23:00:23.503040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 23:00:23.503447 ==
6343 23:00:23.503769
6344 23:00:23.504093
6345 23:00:23.506712 TX Vref Scan disable
6346 23:00:23.507192 == TX Byte 0 ==
6347 23:00:23.510354 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6348 23:00:23.516920 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6349 23:00:23.517354 == TX Byte 1 ==
6350 23:00:23.519658 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 23:00:23.526884 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 23:00:23.527297 ==
6353 23:00:23.530454 Dram Type= 6, Freq= 0, CH_0, rank 0
6354 23:00:23.533258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6355 23:00:23.533808 ==
6356 23:00:23.534146
6357 23:00:23.534447
6358 23:00:23.536536 TX Vref Scan disable
6359 23:00:23.536942 == TX Byte 0 ==
6360 23:00:23.543513 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6361 23:00:23.546539 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6362 23:00:23.546967 == TX Byte 1 ==
6363 23:00:23.550085 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6364 23:00:23.556569 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6365 23:00:23.556989
6366 23:00:23.557320 [DATLAT]
6367 23:00:23.559982 Freq=400, CH0 RK0
6368 23:00:23.560400
6369 23:00:23.560733 DATLAT Default: 0xf
6370 23:00:23.563059 0, 0xFFFF, sum = 0
6371 23:00:23.563485 1, 0xFFFF, sum = 0
6372 23:00:23.566446 2, 0xFFFF, sum = 0
6373 23:00:23.566872 3, 0xFFFF, sum = 0
6374 23:00:23.570390 4, 0xFFFF, sum = 0
6375 23:00:23.570807 5, 0xFFFF, sum = 0
6376 23:00:23.573515 6, 0xFFFF, sum = 0
6377 23:00:23.573966 7, 0xFFFF, sum = 0
6378 23:00:23.576867 8, 0xFFFF, sum = 0
6379 23:00:23.577284 9, 0xFFFF, sum = 0
6380 23:00:23.580207 10, 0xFFFF, sum = 0
6381 23:00:23.580623 11, 0xFFFF, sum = 0
6382 23:00:23.583043 12, 0xFFFF, sum = 0
6383 23:00:23.583458 13, 0x0, sum = 1
6384 23:00:23.586507 14, 0x0, sum = 2
6385 23:00:23.586922 15, 0x0, sum = 3
6386 23:00:23.589978 16, 0x0, sum = 4
6387 23:00:23.590395 best_step = 14
6388 23:00:23.590716
6389 23:00:23.591013 ==
6390 23:00:23.593339 Dram Type= 6, Freq= 0, CH_0, rank 0
6391 23:00:23.599849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6392 23:00:23.600261 ==
6393 23:00:23.600588 RX Vref Scan: 1
6394 23:00:23.600887
6395 23:00:23.603200 RX Vref 0 -> 0, step: 1
6396 23:00:23.603610
6397 23:00:23.606676 RX Delay -311 -> 252, step: 8
6398 23:00:23.607139
6399 23:00:23.609852 Set Vref, RX VrefLevel [Byte0]: 54
6400 23:00:23.612822 [Byte1]: 46
6401 23:00:23.612904
6402 23:00:23.615902 Final RX Vref Byte 0 = 54 to rank0
6403 23:00:23.619365 Final RX Vref Byte 1 = 46 to rank0
6404 23:00:23.623249 Final RX Vref Byte 0 = 54 to rank1
6405 23:00:23.626478 Final RX Vref Byte 1 = 46 to rank1==
6406 23:00:23.629712 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 23:00:23.632796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 23:00:23.633217 ==
6409 23:00:23.636147 DQS Delay:
6410 23:00:23.636563 DQS0 = 28, DQS1 = 36
6411 23:00:23.639577 DQM Delay:
6412 23:00:23.640000 DQM0 = 11, DQM1 = 13
6413 23:00:23.642625 DQ Delay:
6414 23:00:23.643031 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6415 23:00:23.646144 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6416 23:00:23.649856 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8
6417 23:00:23.652698 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6418 23:00:23.653162
6419 23:00:23.653514
6420 23:00:23.663419 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6421 23:00:23.666221 CH0 RK0: MR19=C0C, MR18=CBB8
6422 23:00:23.669685 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6423 23:00:23.672859 ==
6424 23:00:23.676096 Dram Type= 6, Freq= 0, CH_0, rank 1
6425 23:00:23.679375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 23:00:23.679793 ==
6427 23:00:23.682533 [Gating] SW mode calibration
6428 23:00:23.689232 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6429 23:00:23.692694 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6430 23:00:23.699102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6431 23:00:23.702897 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6432 23:00:23.705745 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6433 23:00:23.712669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 23:00:23.716257 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6435 23:00:23.719198 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6436 23:00:23.726040 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6437 23:00:23.729293 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6438 23:00:23.732656 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6439 23:00:23.735735 Total UI for P1: 0, mck2ui 16
6440 23:00:23.739345 best dqsien dly found for B0: ( 0, 14, 24)
6441 23:00:23.742813 Total UI for P1: 0, mck2ui 16
6442 23:00:23.746144 best dqsien dly found for B1: ( 0, 14, 24)
6443 23:00:23.749354 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6444 23:00:23.752503 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6445 23:00:23.752985
6446 23:00:23.755861 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6447 23:00:23.762746 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6448 23:00:23.763160 [Gating] SW calibration Done
6449 23:00:23.766520 ==
6450 23:00:23.766935 Dram Type= 6, Freq= 0, CH_0, rank 1
6451 23:00:23.772568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 23:00:23.772979 ==
6453 23:00:23.773304 RX Vref Scan: 0
6454 23:00:23.773629
6455 23:00:23.776166 RX Vref 0 -> 0, step: 1
6456 23:00:23.776628
6457 23:00:23.779391 RX Delay -410 -> 252, step: 16
6458 23:00:23.782456 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6459 23:00:23.785651 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6460 23:00:23.792766 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6461 23:00:23.795653 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6462 23:00:23.799221 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6463 23:00:23.802258 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6464 23:00:23.809023 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6465 23:00:23.812048 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6466 23:00:23.816052 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6467 23:00:23.818979 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6468 23:00:23.825894 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6469 23:00:23.829118 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6470 23:00:23.832164 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6471 23:00:23.836010 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6472 23:00:23.842044 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6473 23:00:23.845323 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6474 23:00:23.845776 ==
6475 23:00:23.848707 Dram Type= 6, Freq= 0, CH_0, rank 1
6476 23:00:23.852280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 23:00:23.852799 ==
6478 23:00:23.855709 DQS Delay:
6479 23:00:23.856118 DQS0 = 27, DQS1 = 35
6480 23:00:23.858770 DQM Delay:
6481 23:00:23.859180 DQM0 = 12, DQM1 = 12
6482 23:00:23.862117 DQ Delay:
6483 23:00:23.862581 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6484 23:00:23.865452 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6485 23:00:23.868666 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6486 23:00:23.871667 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6487 23:00:23.872077
6488 23:00:23.872399
6489 23:00:23.872791 ==
6490 23:00:23.875101 Dram Type= 6, Freq= 0, CH_0, rank 1
6491 23:00:23.881374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 23:00:23.881455 ==
6493 23:00:23.881519
6494 23:00:23.881581
6495 23:00:23.881671 TX Vref Scan disable
6496 23:00:23.884643 == TX Byte 0 ==
6497 23:00:23.888579 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6498 23:00:23.891041 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6499 23:00:23.894573 == TX Byte 1 ==
6500 23:00:23.897938 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6501 23:00:23.901837 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6502 23:00:23.901937 ==
6503 23:00:23.904593 Dram Type= 6, Freq= 0, CH_0, rank 1
6504 23:00:23.911562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6505 23:00:23.911982 ==
6506 23:00:23.912310
6507 23:00:23.912614
6508 23:00:23.912907 TX Vref Scan disable
6509 23:00:23.915374 == TX Byte 0 ==
6510 23:00:23.918560 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6511 23:00:23.922007 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6512 23:00:23.925493 == TX Byte 1 ==
6513 23:00:23.928493 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6514 23:00:23.931852 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6515 23:00:23.932266
6516 23:00:23.934804 [DATLAT]
6517 23:00:23.935221 Freq=400, CH0 RK1
6518 23:00:23.935548
6519 23:00:23.938497 DATLAT Default: 0xe
6520 23:00:23.938929 0, 0xFFFF, sum = 0
6521 23:00:23.941293 1, 0xFFFF, sum = 0
6522 23:00:23.941869 2, 0xFFFF, sum = 0
6523 23:00:23.944617 3, 0xFFFF, sum = 0
6524 23:00:23.945035 4, 0xFFFF, sum = 0
6525 23:00:23.947956 5, 0xFFFF, sum = 0
6526 23:00:23.948375 6, 0xFFFF, sum = 0
6527 23:00:23.951868 7, 0xFFFF, sum = 0
6528 23:00:23.952284 8, 0xFFFF, sum = 0
6529 23:00:23.954313 9, 0xFFFF, sum = 0
6530 23:00:23.957908 10, 0xFFFF, sum = 0
6531 23:00:23.957990 11, 0xFFFF, sum = 0
6532 23:00:23.961309 12, 0xFFFF, sum = 0
6533 23:00:23.961390 13, 0x0, sum = 1
6534 23:00:23.964722 14, 0x0, sum = 2
6535 23:00:23.964803 15, 0x0, sum = 3
6536 23:00:23.964868 16, 0x0, sum = 4
6537 23:00:23.967474 best_step = 14
6538 23:00:23.967554
6539 23:00:23.967618 ==
6540 23:00:23.971477 Dram Type= 6, Freq= 0, CH_0, rank 1
6541 23:00:23.974514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6542 23:00:23.974594 ==
6543 23:00:23.977876 RX Vref Scan: 0
6544 23:00:23.977956
6545 23:00:23.981006 RX Vref 0 -> 0, step: 1
6546 23:00:23.981091
6547 23:00:23.981158 RX Delay -311 -> 252, step: 8
6548 23:00:23.990079 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6549 23:00:23.993068 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6550 23:00:23.996324 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6551 23:00:23.999876 iDelay=217, Bit 3, Center -20 (-247 ~ 208) 456
6552 23:00:24.006661 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6553 23:00:24.009846 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6554 23:00:24.013224 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6555 23:00:24.016261 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6556 23:00:24.022796 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6557 23:00:24.026330 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6558 23:00:24.029570 iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432
6559 23:00:24.032767 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6560 23:00:24.039447 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6561 23:00:24.042811 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6562 23:00:24.046509 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6563 23:00:24.049449 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6564 23:00:24.052556 ==
6565 23:00:24.055972 Dram Type= 6, Freq= 0, CH_0, rank 1
6566 23:00:24.060014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6567 23:00:24.060187 ==
6568 23:00:24.060276 DQS Delay:
6569 23:00:24.062847 DQS0 = 24, DQS1 = 36
6570 23:00:24.063012 DQM Delay:
6571 23:00:24.066435 DQM0 = 8, DQM1 = 13
6572 23:00:24.066577 DQ Delay:
6573 23:00:24.069441 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =4
6574 23:00:24.073129 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6575 23:00:24.076451 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =8
6576 23:00:24.079669 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6577 23:00:24.079801
6578 23:00:24.079905
6579 23:00:24.086360 [DQSOSCAuto] RK1, (LSB)MR18= 0xb85a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6580 23:00:24.089563 CH0 RK1: MR19=C0C, MR18=B85A
6581 23:00:24.095812 CH0_RK1: MR19=0xC0C, MR18=0xB85A, DQSOSC=386, MR23=63, INC=396, DEC=264
6582 23:00:24.099226 [RxdqsGatingPostProcess] freq 400
6583 23:00:24.102308 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6584 23:00:24.105894 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 23:00:24.109277 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 23:00:24.112645 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 23:00:24.115772 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 23:00:24.119221 best DQS0 dly(2T, 0.5T) = (0, 10)
6589 23:00:24.122566 best DQS1 dly(2T, 0.5T) = (0, 10)
6590 23:00:24.126278 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6591 23:00:24.129652 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6592 23:00:24.132819 Pre-setting of DQS Precalculation
6593 23:00:24.136409 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6594 23:00:24.136606 ==
6595 23:00:24.139256 Dram Type= 6, Freq= 0, CH_1, rank 0
6596 23:00:24.145898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6597 23:00:24.145979 ==
6598 23:00:24.149106 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6599 23:00:24.156241 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6600 23:00:24.159219 [CA 0] Center 36 (8~64) winsize 57
6601 23:00:24.162526 [CA 1] Center 36 (8~64) winsize 57
6602 23:00:24.165479 [CA 2] Center 36 (8~64) winsize 57
6603 23:00:24.169399 [CA 3] Center 36 (8~64) winsize 57
6604 23:00:24.172656 [CA 4] Center 36 (8~64) winsize 57
6605 23:00:24.175818 [CA 5] Center 36 (8~64) winsize 57
6606 23:00:24.175981
6607 23:00:24.178759 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6608 23:00:24.178893
6609 23:00:24.182393 [CATrainingPosCal] consider 1 rank data
6610 23:00:24.185348 u2DelayCellTimex100 = 270/100 ps
6611 23:00:24.189151 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 23:00:24.192556 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 23:00:24.195571 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6614 23:00:24.198871 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6615 23:00:24.202623 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6616 23:00:24.209254 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6617 23:00:24.209847
6618 23:00:24.212529 CA PerBit enable=1, Macro0, CA PI delay=36
6619 23:00:24.212947
6620 23:00:24.215762 [CBTSetCACLKResult] CA Dly = 36
6621 23:00:24.216177 CS Dly: 1 (0~32)
6622 23:00:24.216591 ==
6623 23:00:24.218936 Dram Type= 6, Freq= 0, CH_1, rank 1
6624 23:00:24.222338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6625 23:00:24.225453 ==
6626 23:00:24.228488 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6627 23:00:24.235285 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6628 23:00:24.238526 [CA 0] Center 36 (8~64) winsize 57
6629 23:00:24.242346 [CA 1] Center 36 (8~64) winsize 57
6630 23:00:24.245702 [CA 2] Center 36 (8~64) winsize 57
6631 23:00:24.248761 [CA 3] Center 36 (8~64) winsize 57
6632 23:00:24.251990 [CA 4] Center 36 (8~64) winsize 57
6633 23:00:24.255506 [CA 5] Center 36 (8~64) winsize 57
6634 23:00:24.255592
6635 23:00:24.258467 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6636 23:00:24.258559
6637 23:00:24.262616 [CATrainingPosCal] consider 2 rank data
6638 23:00:24.265222 u2DelayCellTimex100 = 270/100 ps
6639 23:00:24.268431 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 23:00:24.272113 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 23:00:24.275158 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6642 23:00:24.278726 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6643 23:00:24.281873 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6644 23:00:24.285627 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6645 23:00:24.285830
6646 23:00:24.289204 CA PerBit enable=1, Macro0, CA PI delay=36
6647 23:00:24.289437
6648 23:00:24.292115 [CBTSetCACLKResult] CA Dly = 36
6649 23:00:24.295549 CS Dly: 1 (0~32)
6650 23:00:24.295628
6651 23:00:24.298747 ----->DramcWriteLeveling(PI) begin...
6652 23:00:24.298921 ==
6653 23:00:24.302309 Dram Type= 6, Freq= 0, CH_1, rank 0
6654 23:00:24.305149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6655 23:00:24.305237 ==
6656 23:00:24.308447 Write leveling (Byte 0): 40 => 8
6657 23:00:24.312074 Write leveling (Byte 1): 40 => 8
6658 23:00:24.315225 DramcWriteLeveling(PI) end<-----
6659 23:00:24.315306
6660 23:00:24.315369 ==
6661 23:00:24.318309 Dram Type= 6, Freq= 0, CH_1, rank 0
6662 23:00:24.321990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 23:00:24.322401 ==
6664 23:00:24.325527 [Gating] SW mode calibration
6665 23:00:24.332133 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6666 23:00:24.339041 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6667 23:00:24.342431 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6668 23:00:24.345874 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6669 23:00:24.352603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6670 23:00:24.355633 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 23:00:24.359345 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6672 23:00:24.365696 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6673 23:00:24.368418 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6674 23:00:24.371885 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6675 23:00:24.378699 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6676 23:00:24.382061 Total UI for P1: 0, mck2ui 16
6677 23:00:24.385685 best dqsien dly found for B0: ( 0, 14, 24)
6678 23:00:24.386148 Total UI for P1: 0, mck2ui 16
6679 23:00:24.391936 best dqsien dly found for B1: ( 0, 14, 24)
6680 23:00:24.395426 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6681 23:00:24.398624 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6682 23:00:24.399040
6683 23:00:24.402113 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6684 23:00:24.405685 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6685 23:00:24.409035 [Gating] SW calibration Done
6686 23:00:24.409453 ==
6687 23:00:24.412292 Dram Type= 6, Freq= 0, CH_1, rank 0
6688 23:00:24.415445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 23:00:24.415868 ==
6690 23:00:24.418810 RX Vref Scan: 0
6691 23:00:24.419227
6692 23:00:24.419557 RX Vref 0 -> 0, step: 1
6693 23:00:24.419869
6694 23:00:24.421755 RX Delay -410 -> 252, step: 16
6695 23:00:24.428385 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6696 23:00:24.432069 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6697 23:00:24.434923 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6698 23:00:24.438008 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6699 23:00:24.444719 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6700 23:00:24.448237 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6701 23:00:24.451552 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6702 23:00:24.454543 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6703 23:00:24.461527 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6704 23:00:24.464831 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6705 23:00:24.468201 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6706 23:00:24.471292 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6707 23:00:24.478096 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6708 23:00:24.481499 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6709 23:00:24.484802 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6710 23:00:24.488269 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6711 23:00:24.491318 ==
6712 23:00:24.494808 Dram Type= 6, Freq= 0, CH_1, rank 0
6713 23:00:24.497989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6714 23:00:24.498071 ==
6715 23:00:24.498136 DQS Delay:
6716 23:00:24.500990 DQS0 = 35, DQS1 = 35
6717 23:00:24.501071 DQM Delay:
6718 23:00:24.504804 DQM0 = 17, DQM1 = 13
6719 23:00:24.504885 DQ Delay:
6720 23:00:24.507883 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6721 23:00:24.511005 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6722 23:00:24.514612 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6723 23:00:24.517844 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6724 23:00:24.517961
6725 23:00:24.518061
6726 23:00:24.518121 ==
6727 23:00:24.521109 Dram Type= 6, Freq= 0, CH_1, rank 0
6728 23:00:24.524442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6729 23:00:24.524524 ==
6730 23:00:24.524588
6731 23:00:24.524647
6732 23:00:24.528069 TX Vref Scan disable
6733 23:00:24.528157 == TX Byte 0 ==
6734 23:00:24.534437 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6735 23:00:24.537921 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6736 23:00:24.538026 == TX Byte 1 ==
6737 23:00:24.544400 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 23:00:24.547777 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 23:00:24.547903 ==
6740 23:00:24.551050 Dram Type= 6, Freq= 0, CH_1, rank 0
6741 23:00:24.554972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6742 23:00:24.555155 ==
6743 23:00:24.555312
6744 23:00:24.555462
6745 23:00:24.558438 TX Vref Scan disable
6746 23:00:24.558595 == TX Byte 0 ==
6747 23:00:24.565488 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6748 23:00:24.568638 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6749 23:00:24.569059 == TX Byte 1 ==
6750 23:00:24.574892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6751 23:00:24.577829 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6752 23:00:24.577911
6753 23:00:24.577975 [DATLAT]
6754 23:00:24.581451 Freq=400, CH1 RK0
6755 23:00:24.581537
6756 23:00:24.581638 DATLAT Default: 0xf
6757 23:00:24.584281 0, 0xFFFF, sum = 0
6758 23:00:24.584390 1, 0xFFFF, sum = 0
6759 23:00:24.588109 2, 0xFFFF, sum = 0
6760 23:00:24.588219 3, 0xFFFF, sum = 0
6761 23:00:24.591362 4, 0xFFFF, sum = 0
6762 23:00:24.591481 5, 0xFFFF, sum = 0
6763 23:00:24.594523 6, 0xFFFF, sum = 0
6764 23:00:24.594604 7, 0xFFFF, sum = 0
6765 23:00:24.597613 8, 0xFFFF, sum = 0
6766 23:00:24.597709 9, 0xFFFF, sum = 0
6767 23:00:24.601298 10, 0xFFFF, sum = 0
6768 23:00:24.604919 11, 0xFFFF, sum = 0
6769 23:00:24.605345 12, 0xFFFF, sum = 0
6770 23:00:24.607960 13, 0x0, sum = 1
6771 23:00:24.608385 14, 0x0, sum = 2
6772 23:00:24.608788 15, 0x0, sum = 3
6773 23:00:24.611440 16, 0x0, sum = 4
6774 23:00:24.611918 best_step = 14
6775 23:00:24.612255
6776 23:00:24.614783 ==
6777 23:00:24.615216 Dram Type= 6, Freq= 0, CH_1, rank 0
6778 23:00:24.621357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6779 23:00:24.621829 ==
6780 23:00:24.621894 RX Vref Scan: 1
6781 23:00:24.621953
6782 23:00:24.624119 RX Vref 0 -> 0, step: 1
6783 23:00:24.624198
6784 23:00:24.627549 RX Delay -311 -> 252, step: 8
6785 23:00:24.627635
6786 23:00:24.631266 Set Vref, RX VrefLevel [Byte0]: 54
6787 23:00:24.634088 [Byte1]: 48
6788 23:00:24.637748
6789 23:00:24.637849 Final RX Vref Byte 0 = 54 to rank0
6790 23:00:24.640713 Final RX Vref Byte 1 = 48 to rank0
6791 23:00:24.644574 Final RX Vref Byte 0 = 54 to rank1
6792 23:00:24.647688 Final RX Vref Byte 1 = 48 to rank1==
6793 23:00:24.651005 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 23:00:24.658065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 23:00:24.658155 ==
6796 23:00:24.658220 DQS Delay:
6797 23:00:24.658280 DQS0 = 32, DQS1 = 32
6798 23:00:24.661319 DQM Delay:
6799 23:00:24.661398 DQM0 = 13, DQM1 = 11
6800 23:00:24.664485 DQ Delay:
6801 23:00:24.667313 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6802 23:00:24.667383 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6803 23:00:24.670980 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6804 23:00:24.674224 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6805 23:00:24.674358
6806 23:00:24.678014
6807 23:00:24.684731 [DQSOSCAuto] RK0, (LSB)MR18= 0x93cb, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6808 23:00:24.687931 CH1 RK0: MR19=C0C, MR18=93CB
6809 23:00:24.694109 CH1_RK0: MR19=0xC0C, MR18=0x93CB, DQSOSC=384, MR23=63, INC=400, DEC=267
6810 23:00:24.694277 ==
6811 23:00:24.697805 Dram Type= 6, Freq= 0, CH_1, rank 1
6812 23:00:24.701068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 23:00:24.701255 ==
6814 23:00:24.704471 [Gating] SW mode calibration
6815 23:00:24.710929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6816 23:00:24.717807 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6817 23:00:24.720959 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6818 23:00:24.724243 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6819 23:00:24.727931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6820 23:00:24.734068 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 23:00:24.737969 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6822 23:00:24.740827 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6823 23:00:24.747685 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6824 23:00:24.750753 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6825 23:00:24.754438 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6826 23:00:24.757678 Total UI for P1: 0, mck2ui 16
6827 23:00:24.760853 best dqsien dly found for B0: ( 0, 14, 24)
6828 23:00:24.763948 Total UI for P1: 0, mck2ui 16
6829 23:00:24.767462 best dqsien dly found for B1: ( 0, 14, 24)
6830 23:00:24.770823 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6831 23:00:24.774096 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6832 23:00:24.777479
6833 23:00:24.780594 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6834 23:00:24.784106 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6835 23:00:24.787966 [Gating] SW calibration Done
6836 23:00:24.788377 ==
6837 23:00:24.790680 Dram Type= 6, Freq= 0, CH_1, rank 1
6838 23:00:24.794249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 23:00:24.794666 ==
6840 23:00:24.794995 RX Vref Scan: 0
6841 23:00:24.797196
6842 23:00:24.797628 RX Vref 0 -> 0, step: 1
6843 23:00:24.797960
6844 23:00:24.800669 RX Delay -410 -> 252, step: 16
6845 23:00:24.803844 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6846 23:00:24.810757 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6847 23:00:24.814031 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6848 23:00:24.817436 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6849 23:00:24.820845 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6850 23:00:24.827101 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6851 23:00:24.831195 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6852 23:00:24.834444 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6853 23:00:24.837553 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6854 23:00:24.844164 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6855 23:00:24.847322 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6856 23:00:24.850443 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6857 23:00:24.853611 iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464
6858 23:00:24.860126 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6859 23:00:24.863743 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6860 23:00:24.866926 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6861 23:00:24.867339 ==
6862 23:00:24.870299 Dram Type= 6, Freq= 0, CH_1, rank 1
6863 23:00:24.873798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 23:00:24.876936 ==
6865 23:00:24.877344 DQS Delay:
6866 23:00:24.877731 DQS0 = 35, DQS1 = 35
6867 23:00:24.880082 DQM Delay:
6868 23:00:24.880581 DQM0 = 20, DQM1 = 17
6869 23:00:24.884095 DQ Delay:
6870 23:00:24.886845 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6871 23:00:24.887289 DQ4 =24, DQ5 =32, DQ6 =32, DQ7 =16
6872 23:00:24.890570 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6873 23:00:24.893642 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6874 23:00:24.894058
6875 23:00:24.894407
6876 23:00:24.897283 ==
6877 23:00:24.900527 Dram Type= 6, Freq= 0, CH_1, rank 1
6878 23:00:24.903709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 23:00:24.904130 ==
6880 23:00:24.904462
6881 23:00:24.904863
6882 23:00:24.907162 TX Vref Scan disable
6883 23:00:24.907576 == TX Byte 0 ==
6884 23:00:24.910378 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6885 23:00:24.917141 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6886 23:00:24.917569 == TX Byte 1 ==
6887 23:00:24.920209 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6888 23:00:24.927024 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6889 23:00:24.927439 ==
6890 23:00:24.930335 Dram Type= 6, Freq= 0, CH_1, rank 1
6891 23:00:24.933641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6892 23:00:24.934161 ==
6893 23:00:24.934520
6894 23:00:24.934824
6895 23:00:24.937277 TX Vref Scan disable
6896 23:00:24.937771 == TX Byte 0 ==
6897 23:00:24.940100 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6898 23:00:24.947022 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6899 23:00:24.947459 == TX Byte 1 ==
6900 23:00:24.949774 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6901 23:00:24.956747 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6902 23:00:24.957197
6903 23:00:24.957565 [DATLAT]
6904 23:00:24.957915 Freq=400, CH1 RK1
6905 23:00:24.958220
6906 23:00:24.960195 DATLAT Default: 0xe
6907 23:00:24.960605 0, 0xFFFF, sum = 0
6908 23:00:24.963612 1, 0xFFFF, sum = 0
6909 23:00:24.966878 2, 0xFFFF, sum = 0
6910 23:00:24.967300 3, 0xFFFF, sum = 0
6911 23:00:24.970239 4, 0xFFFF, sum = 0
6912 23:00:24.970657 5, 0xFFFF, sum = 0
6913 23:00:24.973179 6, 0xFFFF, sum = 0
6914 23:00:24.973627 7, 0xFFFF, sum = 0
6915 23:00:24.976913 8, 0xFFFF, sum = 0
6916 23:00:24.977332 9, 0xFFFF, sum = 0
6917 23:00:24.979783 10, 0xFFFF, sum = 0
6918 23:00:24.980201 11, 0xFFFF, sum = 0
6919 23:00:24.983113 12, 0xFFFF, sum = 0
6920 23:00:24.983531 13, 0x0, sum = 1
6921 23:00:24.986744 14, 0x0, sum = 2
6922 23:00:24.987208 15, 0x0, sum = 3
6923 23:00:24.989624 16, 0x0, sum = 4
6924 23:00:24.990045 best_step = 14
6925 23:00:24.990376
6926 23:00:24.990679 ==
6927 23:00:24.993323 Dram Type= 6, Freq= 0, CH_1, rank 1
6928 23:00:24.996435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6929 23:00:25.000179 ==
6930 23:00:25.000591 RX Vref Scan: 0
6931 23:00:25.000920
6932 23:00:25.003560 RX Vref 0 -> 0, step: 1
6933 23:00:25.003975
6934 23:00:25.006717 RX Delay -311 -> 252, step: 8
6935 23:00:25.010202 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6936 23:00:25.016669 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
6937 23:00:25.019604 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6938 23:00:25.023313 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6939 23:00:25.026260 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6940 23:00:25.033259 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6941 23:00:25.036706 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6942 23:00:25.039469 iDelay=217, Bit 7, Center -24 (-247 ~ 200) 448
6943 23:00:25.043067 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6944 23:00:25.049448 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6945 23:00:25.053034 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
6946 23:00:25.055993 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6947 23:00:25.059509 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6948 23:00:25.066215 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6949 23:00:25.069339 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6950 23:00:25.072636 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6951 23:00:25.073047 ==
6952 23:00:25.075966 Dram Type= 6, Freq= 0, CH_1, rank 1
6953 23:00:25.082548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6954 23:00:25.082959 ==
6955 23:00:25.083286 DQS Delay:
6956 23:00:25.086155 DQS0 = 28, DQS1 = 36
6957 23:00:25.086561 DQM Delay:
6958 23:00:25.086882 DQM0 = 9, DQM1 = 15
6959 23:00:25.089600 DQ Delay:
6960 23:00:25.092419 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6961 23:00:25.092806 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6962 23:00:25.096000 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =12
6963 23:00:25.099085 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
6964 23:00:25.099163
6965 23:00:25.102578
6966 23:00:25.108752 [DQSOSCAuto] RK1, (LSB)MR18= 0xc154, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
6967 23:00:25.112044 CH1 RK1: MR19=C0C, MR18=C154
6968 23:00:25.118929 CH1_RK1: MR19=0xC0C, MR18=0xC154, DQSOSC=385, MR23=63, INC=398, DEC=265
6969 23:00:25.121956 [RxdqsGatingPostProcess] freq 400
6970 23:00:25.125333 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6971 23:00:25.128981 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 23:00:25.132096 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 23:00:25.135464 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 23:00:25.139264 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 23:00:25.142269 best DQS0 dly(2T, 0.5T) = (0, 10)
6976 23:00:25.145412 best DQS1 dly(2T, 0.5T) = (0, 10)
6977 23:00:25.148613 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6978 23:00:25.152273 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6979 23:00:25.155825 Pre-setting of DQS Precalculation
6980 23:00:25.159450 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6981 23:00:25.166337 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6982 23:00:25.175295 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6983 23:00:25.175376
6984 23:00:25.175439
6985 23:00:25.178484 [Calibration Summary] 800 Mbps
6986 23:00:25.178564 CH 0, Rank 0
6987 23:00:25.181892 SW Impedance : PASS
6988 23:00:25.181978 DUTY Scan : NO K
6989 23:00:25.185030 ZQ Calibration : PASS
6990 23:00:25.185110 Jitter Meter : NO K
6991 23:00:25.188270 CBT Training : PASS
6992 23:00:25.191690 Write leveling : PASS
6993 23:00:25.191770 RX DQS gating : PASS
6994 23:00:25.194861 RX DQ/DQS(RDDQC) : PASS
6995 23:00:25.198593 TX DQ/DQS : PASS
6996 23:00:25.198704 RX DATLAT : PASS
6997 23:00:25.201781 RX DQ/DQS(Engine): PASS
6998 23:00:25.205287 TX OE : NO K
6999 23:00:25.205367 All Pass.
7000 23:00:25.205431
7001 23:00:25.205489 CH 0, Rank 1
7002 23:00:25.208677 SW Impedance : PASS
7003 23:00:25.211695 DUTY Scan : NO K
7004 23:00:25.211775 ZQ Calibration : PASS
7005 23:00:25.214925 Jitter Meter : NO K
7006 23:00:25.218443 CBT Training : PASS
7007 23:00:25.218522 Write leveling : NO K
7008 23:00:25.221547 RX DQS gating : PASS
7009 23:00:25.224913 RX DQ/DQS(RDDQC) : PASS
7010 23:00:25.224993 TX DQ/DQS : PASS
7011 23:00:25.228165 RX DATLAT : PASS
7012 23:00:25.231412 RX DQ/DQS(Engine): PASS
7013 23:00:25.231504 TX OE : NO K
7014 23:00:25.231576 All Pass.
7015 23:00:25.235421
7016 23:00:25.235513 CH 1, Rank 0
7017 23:00:25.238240 SW Impedance : PASS
7018 23:00:25.238339 DUTY Scan : NO K
7019 23:00:25.241326 ZQ Calibration : PASS
7020 23:00:25.241434 Jitter Meter : NO K
7021 23:00:25.245283 CBT Training : PASS
7022 23:00:25.248486 Write leveling : PASS
7023 23:00:25.248666 RX DQS gating : PASS
7024 23:00:25.251555 RX DQ/DQS(RDDQC) : PASS
7025 23:00:25.254866 TX DQ/DQS : PASS
7026 23:00:25.255000 RX DATLAT : PASS
7027 23:00:25.258587 RX DQ/DQS(Engine): PASS
7028 23:00:25.262143 TX OE : NO K
7029 23:00:25.262561 All Pass.
7030 23:00:25.262890
7031 23:00:25.263192 CH 1, Rank 1
7032 23:00:25.265133 SW Impedance : PASS
7033 23:00:25.268719 DUTY Scan : NO K
7034 23:00:25.269130 ZQ Calibration : PASS
7035 23:00:25.271899 Jitter Meter : NO K
7036 23:00:25.275126 CBT Training : PASS
7037 23:00:25.275536 Write leveling : NO K
7038 23:00:25.278442 RX DQS gating : PASS
7039 23:00:25.282011 RX DQ/DQS(RDDQC) : PASS
7040 23:00:25.282421 TX DQ/DQS : PASS
7041 23:00:25.284885 RX DATLAT : PASS
7042 23:00:25.288290 RX DQ/DQS(Engine): PASS
7043 23:00:25.288705 TX OE : NO K
7044 23:00:25.289037 All Pass.
7045 23:00:25.291970
7046 23:00:25.292381 DramC Write-DBI off
7047 23:00:25.295322 PER_BANK_REFRESH: Hybrid Mode
7048 23:00:25.295835 TX_TRACKING: ON
7049 23:00:25.305184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7050 23:00:25.308505 [FAST_K] Save calibration result to emmc
7051 23:00:25.311755 dramc_set_vcore_voltage set vcore to 725000
7052 23:00:25.315227 Read voltage for 1600, 0
7053 23:00:25.315639 Vio18 = 0
7054 23:00:25.318415 Vcore = 725000
7055 23:00:25.318908 Vdram = 0
7056 23:00:25.319423 Vddq = 0
7057 23:00:25.319762 Vmddr = 0
7058 23:00:25.324584 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7059 23:00:25.331418 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7060 23:00:25.331834 MEM_TYPE=3, freq_sel=13
7061 23:00:25.334495 sv_algorithm_assistance_LP4_3733
7062 23:00:25.338429 ============ PULL DRAM RESETB DOWN ============
7063 23:00:25.344971 ========== PULL DRAM RESETB DOWN end =========
7064 23:00:25.348472 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7065 23:00:25.351670 ===================================
7066 23:00:25.354985 LPDDR4 DRAM CONFIGURATION
7067 23:00:25.357775 ===================================
7068 23:00:25.358192 EX_ROW_EN[0] = 0x0
7069 23:00:25.361314 EX_ROW_EN[1] = 0x0
7070 23:00:25.361756 LP4Y_EN = 0x0
7071 23:00:25.364737 WORK_FSP = 0x1
7072 23:00:25.365145 WL = 0x5
7073 23:00:25.367980 RL = 0x5
7074 23:00:25.370962 BL = 0x2
7075 23:00:25.371374 RPST = 0x0
7076 23:00:25.374932 RD_PRE = 0x0
7077 23:00:25.375339 WR_PRE = 0x1
7078 23:00:25.378743 WR_PST = 0x1
7079 23:00:25.379151 DBI_WR = 0x0
7080 23:00:25.381428 DBI_RD = 0x0
7081 23:00:25.381905 OTF = 0x1
7082 23:00:25.385090 ===================================
7083 23:00:25.388403 ===================================
7084 23:00:25.391348 ANA top config
7085 23:00:25.394629 ===================================
7086 23:00:25.395135 DLL_ASYNC_EN = 0
7087 23:00:25.397682 ALL_SLAVE_EN = 0
7088 23:00:25.401085 NEW_RANK_MODE = 1
7089 23:00:25.404531 DLL_IDLE_MODE = 1
7090 23:00:25.404989 LP45_APHY_COMB_EN = 1
7091 23:00:25.408023 TX_ODT_DIS = 0
7092 23:00:25.411280 NEW_8X_MODE = 1
7093 23:00:25.414888 ===================================
7094 23:00:25.417937 ===================================
7095 23:00:25.421767 data_rate = 3200
7096 23:00:25.425036 CKR = 1
7097 23:00:25.425444 DQ_P2S_RATIO = 8
7098 23:00:25.428083 ===================================
7099 23:00:25.431022 CA_P2S_RATIO = 8
7100 23:00:25.434553 DQ_CA_OPEN = 0
7101 23:00:25.437900 DQ_SEMI_OPEN = 0
7102 23:00:25.441124 CA_SEMI_OPEN = 0
7103 23:00:25.444499 CA_FULL_RATE = 0
7104 23:00:25.447780 DQ_CKDIV4_EN = 0
7105 23:00:25.448192 CA_CKDIV4_EN = 0
7106 23:00:25.451213 CA_PREDIV_EN = 0
7107 23:00:25.454036 PH8_DLY = 12
7108 23:00:25.457655 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7109 23:00:25.461100 DQ_AAMCK_DIV = 4
7110 23:00:25.463933 CA_AAMCK_DIV = 4
7111 23:00:25.464343 CA_ADMCK_DIV = 4
7112 23:00:25.467397 DQ_TRACK_CA_EN = 0
7113 23:00:25.470744 CA_PICK = 1600
7114 23:00:25.474015 CA_MCKIO = 1600
7115 23:00:25.476811 MCKIO_SEMI = 0
7116 23:00:25.480157 PLL_FREQ = 3068
7117 23:00:25.483822 DQ_UI_PI_RATIO = 32
7118 23:00:25.483898 CA_UI_PI_RATIO = 0
7119 23:00:25.486621 ===================================
7120 23:00:25.490414 ===================================
7121 23:00:25.493507 memory_type:LPDDR4
7122 23:00:25.496977 GP_NUM : 10
7123 23:00:25.497074 SRAM_EN : 1
7124 23:00:25.499780 MD32_EN : 0
7125 23:00:25.503611 ===================================
7126 23:00:25.506938 [ANA_INIT] >>>>>>>>>>>>>>
7127 23:00:25.509878 <<<<<< [CONFIGURE PHASE]: ANA_TX
7128 23:00:25.513211 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7129 23:00:25.516428 ===================================
7130 23:00:25.516514 data_rate = 3200,PCW = 0X7600
7131 23:00:25.519734 ===================================
7132 23:00:25.523244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7133 23:00:25.530663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7134 23:00:25.537117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7135 23:00:25.540028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7136 23:00:25.543804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7137 23:00:25.546724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7138 23:00:25.549807 [ANA_INIT] flow start
7139 23:00:25.553487 [ANA_INIT] PLL >>>>>>>>
7140 23:00:25.553734 [ANA_INIT] PLL <<<<<<<<
7141 23:00:25.556967 [ANA_INIT] MIDPI >>>>>>>>
7142 23:00:25.560353 [ANA_INIT] MIDPI <<<<<<<<
7143 23:00:25.560536 [ANA_INIT] DLL >>>>>>>>
7144 23:00:25.563446 [ANA_INIT] DLL <<<<<<<<
7145 23:00:25.566801 [ANA_INIT] flow end
7146 23:00:25.570333 ============ LP4 DIFF to SE enter ============
7147 23:00:25.573507 ============ LP4 DIFF to SE exit ============
7148 23:00:25.576738 [ANA_INIT] <<<<<<<<<<<<<
7149 23:00:25.579664 [Flow] Enable top DCM control >>>>>
7150 23:00:25.583069 [Flow] Enable top DCM control <<<<<
7151 23:00:25.586735 Enable DLL master slave shuffle
7152 23:00:25.590248 ==============================================================
7153 23:00:25.592918 Gating Mode config
7154 23:00:25.599480 ==============================================================
7155 23:00:25.599555 Config description:
7156 23:00:25.609452 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7157 23:00:25.616144 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7158 23:00:25.619886 SELPH_MODE 0: By rank 1: By Phase
7159 23:00:25.626502 ==============================================================
7160 23:00:25.629414 GAT_TRACK_EN = 1
7161 23:00:25.633112 RX_GATING_MODE = 2
7162 23:00:25.636361 RX_GATING_TRACK_MODE = 2
7163 23:00:25.639944 SELPH_MODE = 1
7164 23:00:25.643339 PICG_EARLY_EN = 1
7165 23:00:25.646322 VALID_LAT_VALUE = 1
7166 23:00:25.650037 ==============================================================
7167 23:00:25.653364 Enter into Gating configuration >>>>
7168 23:00:25.656382 Exit from Gating configuration <<<<
7169 23:00:25.660071 Enter into DVFS_PRE_config >>>>>
7170 23:00:25.670545 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7171 23:00:25.673161 Exit from DVFS_PRE_config <<<<<
7172 23:00:25.676399 Enter into PICG configuration >>>>
7173 23:00:25.680151 Exit from PICG configuration <<<<
7174 23:00:25.683524 [RX_INPUT] configuration >>>>>
7175 23:00:25.686506 [RX_INPUT] configuration <<<<<
7176 23:00:25.693307 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7177 23:00:25.696246 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7178 23:00:25.703021 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7179 23:00:25.709781 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7180 23:00:25.715951 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7181 23:00:25.722669 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7182 23:00:25.726990 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7183 23:00:25.729332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7184 23:00:25.733111 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7185 23:00:25.739175 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7186 23:00:25.742656 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7187 23:00:25.746186 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 23:00:25.749024 ===================================
7189 23:00:25.752340 LPDDR4 DRAM CONFIGURATION
7190 23:00:25.755992 ===================================
7191 23:00:25.759006 EX_ROW_EN[0] = 0x0
7192 23:00:25.759423 EX_ROW_EN[1] = 0x0
7193 23:00:25.762153 LP4Y_EN = 0x0
7194 23:00:25.762569 WORK_FSP = 0x1
7195 23:00:25.765628 WL = 0x5
7196 23:00:25.766049 RL = 0x5
7197 23:00:25.768958 BL = 0x2
7198 23:00:25.769432 RPST = 0x0
7199 23:00:25.772272 RD_PRE = 0x0
7200 23:00:25.772762 WR_PRE = 0x1
7201 23:00:25.775734 WR_PST = 0x1
7202 23:00:25.776231 DBI_WR = 0x0
7203 23:00:25.779239 DBI_RD = 0x0
7204 23:00:25.779654 OTF = 0x1
7205 23:00:25.782686 ===================================
7206 23:00:25.785492 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7207 23:00:25.792300 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7208 23:00:25.795656 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 23:00:25.798795 ===================================
7210 23:00:25.802390 LPDDR4 DRAM CONFIGURATION
7211 23:00:25.805776 ===================================
7212 23:00:25.806194 EX_ROW_EN[0] = 0x10
7213 23:00:25.808638 EX_ROW_EN[1] = 0x0
7214 23:00:25.812096 LP4Y_EN = 0x0
7215 23:00:25.812547 WORK_FSP = 0x1
7216 23:00:25.815548 WL = 0x5
7217 23:00:25.815971 RL = 0x5
7218 23:00:25.818772 BL = 0x2
7219 23:00:25.819182 RPST = 0x0
7220 23:00:25.822143 RD_PRE = 0x0
7221 23:00:25.822568 WR_PRE = 0x1
7222 23:00:25.825361 WR_PST = 0x1
7223 23:00:25.825832 DBI_WR = 0x0
7224 23:00:25.829069 DBI_RD = 0x0
7225 23:00:25.829479 OTF = 0x1
7226 23:00:25.831719 ===================================
7227 23:00:25.838681 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7228 23:00:25.839091 ==
7229 23:00:25.842118 Dram Type= 6, Freq= 0, CH_0, rank 0
7230 23:00:25.845065 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7231 23:00:25.848624 ==
7232 23:00:25.849122 [Duty_Offset_Calibration]
7233 23:00:25.851956 B0:2 B1:1 CA:1
7234 23:00:25.852505
7235 23:00:25.855316 [DutyScan_Calibration_Flow] k_type=0
7236 23:00:25.864004
7237 23:00:25.864430 ==CLK 0==
7238 23:00:25.867371 Final CLK duty delay cell = 0
7239 23:00:25.871039 [0] MAX Duty = 5156%(X100), DQS PI = 22
7240 23:00:25.874417 [0] MIN Duty = 4907%(X100), DQS PI = 0
7241 23:00:25.874868 [0] AVG Duty = 5031%(X100)
7242 23:00:25.877683
7243 23:00:25.878055 CH0 CLK Duty spec in!! Max-Min= 249%
7244 23:00:25.883720 [DutyScan_Calibration_Flow] ====Done====
7245 23:00:25.884094
7246 23:00:25.887648 [DutyScan_Calibration_Flow] k_type=1
7247 23:00:25.903247
7248 23:00:25.903837 ==DQS 0 ==
7249 23:00:25.906463 Final DQS duty delay cell = -4
7250 23:00:25.910084 [-4] MAX Duty = 5125%(X100), DQS PI = 24
7251 23:00:25.913807 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7252 23:00:25.916407 [-4] AVG Duty = 4891%(X100)
7253 23:00:25.916855
7254 23:00:25.917186 ==DQS 1 ==
7255 23:00:25.920138 Final DQS duty delay cell = 0
7256 23:00:25.923648 [0] MAX Duty = 5187%(X100), DQS PI = 20
7257 23:00:25.926284 [0] MIN Duty = 5031%(X100), DQS PI = 52
7258 23:00:25.929792 [0] AVG Duty = 5109%(X100)
7259 23:00:25.930216
7260 23:00:25.933099 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7261 23:00:25.933530
7262 23:00:25.936183 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7263 23:00:25.939818 [DutyScan_Calibration_Flow] ====Done====
7264 23:00:25.940210
7265 23:00:25.942900 [DutyScan_Calibration_Flow] k_type=3
7266 23:00:25.960822
7267 23:00:25.961240 ==DQM 0 ==
7268 23:00:25.963809 Final DQM duty delay cell = 0
7269 23:00:25.967276 [0] MAX Duty = 5187%(X100), DQS PI = 28
7270 23:00:25.970661 [0] MIN Duty = 4875%(X100), DQS PI = 60
7271 23:00:25.973827 [0] AVG Duty = 5031%(X100)
7272 23:00:25.974206
7273 23:00:25.974590 ==DQM 1 ==
7274 23:00:25.977045 Final DQM duty delay cell = 0
7275 23:00:25.980885 [0] MAX Duty = 5187%(X100), DQS PI = 2
7276 23:00:25.983440 [0] MIN Duty = 5062%(X100), DQS PI = 14
7277 23:00:25.986498 [0] AVG Duty = 5124%(X100)
7278 23:00:25.986602
7279 23:00:25.989939 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7280 23:00:25.990019
7281 23:00:25.993388 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7282 23:00:25.997201 [DutyScan_Calibration_Flow] ====Done====
7283 23:00:25.997691
7284 23:00:26.000398 [DutyScan_Calibration_Flow] k_type=2
7285 23:00:26.017714
7286 23:00:26.018134 ==DQ 0 ==
7287 23:00:26.020926 Final DQ duty delay cell = 0
7288 23:00:26.024622 [0] MAX Duty = 5062%(X100), DQS PI = 26
7289 23:00:26.027718 [0] MIN Duty = 4907%(X100), DQS PI = 0
7290 23:00:26.028150 [0] AVG Duty = 4984%(X100)
7291 23:00:26.028508
7292 23:00:26.031079 ==DQ 1 ==
7293 23:00:26.034380 Final DQ duty delay cell = 0
7294 23:00:26.038238 [0] MAX Duty = 5156%(X100), DQS PI = 22
7295 23:00:26.041211 [0] MIN Duty = 4907%(X100), DQS PI = 34
7296 23:00:26.041610 [0] AVG Duty = 5031%(X100)
7297 23:00:26.041938
7298 23:00:26.044408 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7299 23:00:26.047928
7300 23:00:26.051240 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7301 23:00:26.054497 [DutyScan_Calibration_Flow] ====Done====
7302 23:00:26.054919 ==
7303 23:00:26.057701 Dram Type= 6, Freq= 0, CH_1, rank 0
7304 23:00:26.060953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7305 23:00:26.061393 ==
7306 23:00:26.064064 [Duty_Offset_Calibration]
7307 23:00:26.064422 B0:1 B1:0 CA:0
7308 23:00:26.064725
7309 23:00:26.067311 [DutyScan_Calibration_Flow] k_type=0
7310 23:00:26.077163
7311 23:00:26.077783 ==CLK 0==
7312 23:00:26.080470 Final CLK duty delay cell = -4
7313 23:00:26.083711 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7314 23:00:26.087219 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7315 23:00:26.090307 [-4] AVG Duty = 4906%(X100)
7316 23:00:26.090745
7317 23:00:26.093635 CH1 CLK Duty spec in!! Max-Min= 125%
7318 23:00:26.097017 [DutyScan_Calibration_Flow] ====Done====
7319 23:00:26.097513
7320 23:00:26.100214 [DutyScan_Calibration_Flow] k_type=1
7321 23:00:26.116918
7322 23:00:26.117525 ==DQS 0 ==
7323 23:00:26.120462 Final DQS duty delay cell = 0
7324 23:00:26.123736 [0] MAX Duty = 5094%(X100), DQS PI = 16
7325 23:00:26.127339 [0] MIN Duty = 4875%(X100), DQS PI = 0
7326 23:00:26.130579 [0] AVG Duty = 4984%(X100)
7327 23:00:26.130984
7328 23:00:26.131301 ==DQS 1 ==
7329 23:00:26.133667 Final DQS duty delay cell = 0
7330 23:00:26.137453 [0] MAX Duty = 5249%(X100), DQS PI = 16
7331 23:00:26.140323 [0] MIN Duty = 4969%(X100), DQS PI = 6
7332 23:00:26.140728 [0] AVG Duty = 5109%(X100)
7333 23:00:26.144095
7334 23:00:26.146762 CH1 DQS 0 Duty spec in!! Max-Min= 219%
7335 23:00:26.147359
7336 23:00:26.150103 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7337 23:00:26.153459 [DutyScan_Calibration_Flow] ====Done====
7338 23:00:26.154004
7339 23:00:26.156655 [DutyScan_Calibration_Flow] k_type=3
7340 23:00:26.174253
7341 23:00:26.174660 ==DQM 0 ==
7342 23:00:26.177637 Final DQM duty delay cell = 0
7343 23:00:26.180967 [0] MAX Duty = 5218%(X100), DQS PI = 18
7344 23:00:26.183984 [0] MIN Duty = 4969%(X100), DQS PI = 48
7345 23:00:26.187396 [0] AVG Duty = 5093%(X100)
7346 23:00:26.187825
7347 23:00:26.188154 ==DQM 1 ==
7348 23:00:26.191078 Final DQM duty delay cell = 0
7349 23:00:26.193960 [0] MAX Duty = 5093%(X100), DQS PI = 40
7350 23:00:26.197745 [0] MIN Duty = 4907%(X100), DQS PI = 32
7351 23:00:26.198153 [0] AVG Duty = 5000%(X100)
7352 23:00:26.201029
7353 23:00:26.204062 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7354 23:00:26.204470
7355 23:00:26.207146 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7356 23:00:26.210355 [DutyScan_Calibration_Flow] ====Done====
7357 23:00:26.210434
7358 23:00:26.213553 [DutyScan_Calibration_Flow] k_type=2
7359 23:00:26.230027
7360 23:00:26.230129 ==DQ 0 ==
7361 23:00:26.233448 Final DQ duty delay cell = -4
7362 23:00:26.236560 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7363 23:00:26.240215 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7364 23:00:26.243534 [-4] AVG Duty = 4968%(X100)
7365 23:00:26.243942
7366 23:00:26.244265 ==DQ 1 ==
7367 23:00:26.247191 Final DQ duty delay cell = 0
7368 23:00:26.250047 [0] MAX Duty = 5124%(X100), DQS PI = 18
7369 23:00:26.253276 [0] MIN Duty = 4938%(X100), DQS PI = 8
7370 23:00:26.256774 [0] AVG Duty = 5031%(X100)
7371 23:00:26.257184
7372 23:00:26.259684 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7373 23:00:26.260098
7374 23:00:26.263063 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7375 23:00:26.266438 [DutyScan_Calibration_Flow] ====Done====
7376 23:00:26.269902 nWR fixed to 30
7377 23:00:26.273237 [ModeRegInit_LP4] CH0 RK0
7378 23:00:26.273690 [ModeRegInit_LP4] CH0 RK1
7379 23:00:26.276757 [ModeRegInit_LP4] CH1 RK0
7380 23:00:26.279990 [ModeRegInit_LP4] CH1 RK1
7381 23:00:26.280403 match AC timing 5
7382 23:00:26.286489 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7383 23:00:26.289469 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7384 23:00:26.293244 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7385 23:00:26.299639 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7386 23:00:26.302768 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7387 23:00:26.303179 [MiockJmeterHQA]
7388 23:00:26.303505
7389 23:00:26.305875 [DramcMiockJmeter] u1RxGatingPI = 0
7390 23:00:26.309200 0 : 4366, 4139
7391 23:00:26.309307 4 : 4255, 4029
7392 23:00:26.312484 8 : 4253, 4026
7393 23:00:26.312565 12 : 4253, 4026
7394 23:00:26.315673 16 : 4252, 4027
7395 23:00:26.315772 20 : 4363, 4137
7396 23:00:26.315840 24 : 4252, 4027
7397 23:00:26.319290 28 : 4365, 4140
7398 23:00:26.319376 32 : 4252, 4027
7399 23:00:26.322810 36 : 4252, 4027
7400 23:00:26.322903 40 : 4253, 4026
7401 23:00:26.325565 44 : 4252, 4027
7402 23:00:26.325675 48 : 4365, 4140
7403 23:00:26.325762 52 : 4252, 4027
7404 23:00:26.329067 56 : 4363, 4138
7405 23:00:26.329167 60 : 4253, 4026
7406 23:00:26.332704 64 : 4252, 4027
7407 23:00:26.332813 68 : 4252, 4027
7408 23:00:26.336205 72 : 4360, 4137
7409 23:00:26.336679 76 : 4250, 4027
7410 23:00:26.339441 80 : 4360, 4137
7411 23:00:26.339858 84 : 4250, 4024
7412 23:00:26.340186 88 : 4250, 75
7413 23:00:26.342688 92 : 4252, 0
7414 23:00:26.343103 96 : 4363, 0
7415 23:00:26.346175 100 : 4250, 0
7416 23:00:26.346709 104 : 4250, 0
7417 23:00:26.347047 108 : 4250, 0
7418 23:00:26.349261 112 : 4361, 0
7419 23:00:26.349717 116 : 4363, 0
7420 23:00:26.350055 120 : 4247, 0
7421 23:00:26.352607 124 : 4250, 0
7422 23:00:26.353027 128 : 4360, 0
7423 23:00:26.356145 132 : 4361, 0
7424 23:00:26.356737 136 : 4250, 0
7425 23:00:26.357104 140 : 4250, 0
7426 23:00:26.359678 144 : 4249, 0
7427 23:00:26.360294 148 : 4250, 0
7428 23:00:26.362724 152 : 4250, 0
7429 23:00:26.363149 156 : 4250, 0
7430 23:00:26.363486 160 : 4250, 0
7431 23:00:26.366030 164 : 4250, 0
7432 23:00:26.366499 168 : 4250, 0
7433 23:00:26.369729 172 : 4250, 0
7434 23:00:26.370156 176 : 4360, 0
7435 23:00:26.370594 180 : 4360, 0
7436 23:00:26.372779 184 : 4247, 0
7437 23:00:26.373307 188 : 4250, 0
7438 23:00:26.373809 192 : 4250, 0
7439 23:00:26.375950 196 : 4250, 0
7440 23:00:26.376454 200 : 4250, 0
7441 23:00:26.379450 204 : 4250, 1416
7442 23:00:26.379867 208 : 4250, 3998
7443 23:00:26.382346 212 : 4253, 4029
7444 23:00:26.382760 216 : 4250, 4027
7445 23:00:26.386193 220 : 4250, 4027
7446 23:00:26.386605 224 : 4250, 4027
7447 23:00:26.389030 228 : 4250, 4027
7448 23:00:26.389442 232 : 4249, 4027
7449 23:00:26.390040 236 : 4361, 4137
7450 23:00:26.392707 240 : 4361, 4137
7451 23:00:26.393119 244 : 4247, 4025
7452 23:00:26.396237 248 : 4360, 4138
7453 23:00:26.396672 252 : 4360, 4137
7454 23:00:26.399260 256 : 4250, 4027
7455 23:00:26.399677 260 : 4250, 4027
7456 23:00:26.402646 264 : 4250, 4027
7457 23:00:26.403057 268 : 4249, 4027
7458 23:00:26.405905 272 : 4250, 4027
7459 23:00:26.406317 276 : 4250, 4027
7460 23:00:26.409050 280 : 4250, 4027
7461 23:00:26.409463 284 : 4249, 4027
7462 23:00:26.412259 288 : 4360, 4137
7463 23:00:26.412687 292 : 4361, 4137
7464 23:00:26.415656 296 : 4247, 4025
7465 23:00:26.416071 300 : 4360, 4138
7466 23:00:26.416398 304 : 4360, 4137
7467 23:00:26.419090 308 : 4361, 4066
7468 23:00:26.419671 312 : 4250, 2018
7469 23:00:26.420096
7470 23:00:26.422155 MIOCK jitter meter ch=0
7471 23:00:26.422730
7472 23:00:26.425562 1T = (312-88) = 224 dly cells
7473 23:00:26.432209 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7474 23:00:26.432628 ==
7475 23:00:26.435681 Dram Type= 6, Freq= 0, CH_0, rank 0
7476 23:00:26.439257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7477 23:00:26.439783 ==
7478 23:00:26.445469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7479 23:00:26.449126 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7480 23:00:26.452049 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7481 23:00:26.458969 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7482 23:00:26.467937 [CA 0] Center 42 (12~73) winsize 62
7483 23:00:26.471190 [CA 1] Center 42 (12~73) winsize 62
7484 23:00:26.474823 [CA 2] Center 37 (8~67) winsize 60
7485 23:00:26.477911 [CA 3] Center 37 (7~67) winsize 61
7486 23:00:26.481173 [CA 4] Center 36 (6~66) winsize 61
7487 23:00:26.484392 [CA 5] Center 35 (6~64) winsize 59
7488 23:00:26.484837
7489 23:00:26.487992 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7490 23:00:26.488405
7491 23:00:26.491355 [CATrainingPosCal] consider 1 rank data
7492 23:00:26.494730 u2DelayCellTimex100 = 290/100 ps
7493 23:00:26.497967 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7494 23:00:26.504595 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7495 23:00:26.507681 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7496 23:00:26.511430 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7497 23:00:26.514343 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7498 23:00:26.517874 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7499 23:00:26.518348
7500 23:00:26.521018 CA PerBit enable=1, Macro0, CA PI delay=35
7501 23:00:26.521449
7502 23:00:26.524322 [CBTSetCACLKResult] CA Dly = 35
7503 23:00:26.524901 CS Dly: 9 (0~40)
7504 23:00:26.531109 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7505 23:00:26.534309 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7506 23:00:26.534754 ==
7507 23:00:26.537935 Dram Type= 6, Freq= 0, CH_0, rank 1
7508 23:00:26.540849 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7509 23:00:26.541263 ==
7510 23:00:26.547469 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7511 23:00:26.550986 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7512 23:00:26.557838 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7513 23:00:26.561069 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7514 23:00:26.570911 [CA 0] Center 42 (12~73) winsize 62
7515 23:00:26.574561 [CA 1] Center 42 (12~73) winsize 62
7516 23:00:26.577882 [CA 2] Center 38 (8~68) winsize 61
7517 23:00:26.580927 [CA 3] Center 38 (8~68) winsize 61
7518 23:00:26.584609 [CA 4] Center 36 (6~66) winsize 61
7519 23:00:26.587445 [CA 5] Center 35 (5~65) winsize 61
7520 23:00:26.587852
7521 23:00:26.590525 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7522 23:00:26.591038
7523 23:00:26.594389 [CATrainingPosCal] consider 2 rank data
7524 23:00:26.597415 u2DelayCellTimex100 = 290/100 ps
7525 23:00:26.600733 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7526 23:00:26.607390 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7527 23:00:26.610546 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7528 23:00:26.614105 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7529 23:00:26.617283 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7530 23:00:26.620317 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7531 23:00:26.620730
7532 23:00:26.623939 CA PerBit enable=1, Macro0, CA PI delay=35
7533 23:00:26.624347
7534 23:00:26.627549 [CBTSetCACLKResult] CA Dly = 35
7535 23:00:26.630631 CS Dly: 10 (0~42)
7536 23:00:26.633756 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7537 23:00:26.636902 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7538 23:00:26.637311
7539 23:00:26.640704 ----->DramcWriteLeveling(PI) begin...
7540 23:00:26.641118 ==
7541 23:00:26.644003 Dram Type= 6, Freq= 0, CH_0, rank 0
7542 23:00:26.650851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7543 23:00:26.651267 ==
7544 23:00:26.653743 Write leveling (Byte 0): 36 => 36
7545 23:00:26.654175 Write leveling (Byte 1): 29 => 29
7546 23:00:26.657028 DramcWriteLeveling(PI) end<-----
7547 23:00:26.657436
7548 23:00:26.657879 ==
7549 23:00:26.660875 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 23:00:26.666760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 23:00:26.667350 ==
7552 23:00:26.670141 [Gating] SW mode calibration
7553 23:00:26.676921 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7554 23:00:26.680156 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7555 23:00:26.687128 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7556 23:00:26.690215 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7557 23:00:26.693665 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7558 23:00:26.700138 1 4 12 | B1->B0 | 2323 3938 | 0 1 | (0 0) (0 0)
7559 23:00:26.703636 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7560 23:00:26.706983 1 4 20 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7561 23:00:26.713172 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7562 23:00:26.716345 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7563 23:00:26.720043 1 5 0 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 1)
7564 23:00:26.726800 1 5 4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7565 23:00:26.730022 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7566 23:00:26.733658 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7567 23:00:26.740248 1 5 16 | B1->B0 | 3333 2525 | 0 0 | (0 0) (1 0)
7568 23:00:26.743345 1 5 20 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
7569 23:00:26.746446 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 23:00:26.749734 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7571 23:00:26.756493 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7572 23:00:26.759873 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7573 23:00:26.763176 1 6 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
7574 23:00:26.770094 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7575 23:00:26.773057 1 6 16 | B1->B0 | 2929 4646 | 0 0 | (1 1) (0 0)
7576 23:00:26.776713 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 23:00:26.783174 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7578 23:00:26.787102 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 23:00:26.790514 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 23:00:26.796789 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7581 23:00:26.800270 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7582 23:00:26.803302 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7583 23:00:26.809724 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7584 23:00:26.813296 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 23:00:26.816124 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7586 23:00:26.822777 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 23:00:26.826442 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 23:00:26.829468 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 23:00:26.836338 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 23:00:26.839327 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 23:00:26.842779 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 23:00:26.849549 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 23:00:26.852832 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 23:00:26.856241 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 23:00:26.862783 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 23:00:26.866064 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 23:00:26.869970 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 23:00:26.875873 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7599 23:00:26.879437 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7600 23:00:26.883103 Total UI for P1: 0, mck2ui 16
7601 23:00:26.885916 best dqsien dly found for B0: ( 1, 9, 12)
7602 23:00:26.889315 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7603 23:00:26.892565 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7604 23:00:26.895716 Total UI for P1: 0, mck2ui 16
7605 23:00:26.899194 best dqsien dly found for B1: ( 1, 9, 18)
7606 23:00:26.905605 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7607 23:00:26.909394 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7608 23:00:26.909849
7609 23:00:26.912674 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7610 23:00:26.915897 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7611 23:00:26.918961 [Gating] SW calibration Done
7612 23:00:26.919371 ==
7613 23:00:26.922206 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 23:00:26.925846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 23:00:26.926269 ==
7616 23:00:26.928958 RX Vref Scan: 0
7617 23:00:26.929365
7618 23:00:26.929733 RX Vref 0 -> 0, step: 1
7619 23:00:26.930046
7620 23:00:26.932327 RX Delay 0 -> 252, step: 8
7621 23:00:26.935967 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7622 23:00:26.942027 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7623 23:00:26.945651 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7624 23:00:26.948682 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7625 23:00:26.952109 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7626 23:00:26.955430 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7627 23:00:26.962107 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7628 23:00:26.965317 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7629 23:00:26.969300 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7630 23:00:26.972473 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7631 23:00:26.975537 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7632 23:00:26.978969 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7633 23:00:26.985291 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7634 23:00:26.988941 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7635 23:00:26.991976 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7636 23:00:26.995280 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7637 23:00:26.995847 ==
7638 23:00:26.998559 Dram Type= 6, Freq= 0, CH_0, rank 0
7639 23:00:27.005451 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7640 23:00:27.005921 ==
7641 23:00:27.006251 DQS Delay:
7642 23:00:27.008495 DQS0 = 0, DQS1 = 0
7643 23:00:27.008973 DQM Delay:
7644 23:00:27.012028 DQM0 = 136, DQM1 = 131
7645 23:00:27.012444 DQ Delay:
7646 23:00:27.015665 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7647 23:00:27.018951 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7648 23:00:27.021878 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7649 23:00:27.025205 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7650 23:00:27.025655
7651 23:00:27.025990
7652 23:00:27.026297 ==
7653 23:00:27.028507 Dram Type= 6, Freq= 0, CH_0, rank 0
7654 23:00:27.035310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7655 23:00:27.035732 ==
7656 23:00:27.036062
7657 23:00:27.036366
7658 23:00:27.036659 TX Vref Scan disable
7659 23:00:27.039096 == TX Byte 0 ==
7660 23:00:27.042079 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7661 23:00:27.048435 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7662 23:00:27.048857 == TX Byte 1 ==
7663 23:00:27.051702 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7664 23:00:27.058638 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7665 23:00:27.059061 ==
7666 23:00:27.062223 Dram Type= 6, Freq= 0, CH_0, rank 0
7667 23:00:27.065117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7668 23:00:27.065550 ==
7669 23:00:27.077762
7670 23:00:27.081416 TX Vref early break, caculate TX vref
7671 23:00:27.085120 TX Vref=16, minBit 0, minWin=22, winSum=375
7672 23:00:27.088036 TX Vref=18, minBit 1, minWin=23, winSum=383
7673 23:00:27.091371 TX Vref=20, minBit 4, minWin=23, winSum=393
7674 23:00:27.094612 TX Vref=22, minBit 7, minWin=24, winSum=410
7675 23:00:27.097678 TX Vref=24, minBit 0, minWin=25, winSum=417
7676 23:00:27.104812 TX Vref=26, minBit 6, minWin=25, winSum=425
7677 23:00:27.107916 TX Vref=28, minBit 6, minWin=25, winSum=425
7678 23:00:27.111228 TX Vref=30, minBit 6, minWin=24, winSum=417
7679 23:00:27.114327 TX Vref=32, minBit 0, minWin=24, winSum=405
7680 23:00:27.117668 TX Vref=34, minBit 4, minWin=23, winSum=393
7681 23:00:27.124406 [TxChooseVref] Worse bit 6, Min win 25, Win sum 425, Final Vref 26
7682 23:00:27.124822
7683 23:00:27.127849 Final TX Range 0 Vref 26
7684 23:00:27.128261
7685 23:00:27.128586 ==
7686 23:00:27.131000 Dram Type= 6, Freq= 0, CH_0, rank 0
7687 23:00:27.134213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7688 23:00:27.134742 ==
7689 23:00:27.135131
7690 23:00:27.135633
7691 23:00:27.137309 TX Vref Scan disable
7692 23:00:27.144410 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7693 23:00:27.144953 == TX Byte 0 ==
7694 23:00:27.147673 u2DelayCellOfst[0]=10 cells (3 PI)
7695 23:00:27.150768 u2DelayCellOfst[1]=13 cells (4 PI)
7696 23:00:27.154380 u2DelayCellOfst[2]=10 cells (3 PI)
7697 23:00:27.157656 u2DelayCellOfst[3]=10 cells (3 PI)
7698 23:00:27.160734 u2DelayCellOfst[4]=6 cells (2 PI)
7699 23:00:27.164205 u2DelayCellOfst[5]=0 cells (0 PI)
7700 23:00:27.167732 u2DelayCellOfst[6]=16 cells (5 PI)
7701 23:00:27.171028 u2DelayCellOfst[7]=16 cells (5 PI)
7702 23:00:27.174299 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7703 23:00:27.177538 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7704 23:00:27.180841 == TX Byte 1 ==
7705 23:00:27.181252 u2DelayCellOfst[8]=0 cells (0 PI)
7706 23:00:27.184144 u2DelayCellOfst[9]=0 cells (0 PI)
7707 23:00:27.187871 u2DelayCellOfst[10]=6 cells (2 PI)
7708 23:00:27.191047 u2DelayCellOfst[11]=3 cells (1 PI)
7709 23:00:27.194309 u2DelayCellOfst[12]=10 cells (3 PI)
7710 23:00:27.197551 u2DelayCellOfst[13]=13 cells (4 PI)
7711 23:00:27.200799 u2DelayCellOfst[14]=16 cells (5 PI)
7712 23:00:27.204111 u2DelayCellOfst[15]=10 cells (3 PI)
7713 23:00:27.207653 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7714 23:00:27.213941 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7715 23:00:27.214621 DramC Write-DBI on
7716 23:00:27.215120 ==
7717 23:00:27.217976 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 23:00:27.220838 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 23:00:27.221249 ==
7720 23:00:27.224227
7721 23:00:27.224632
7722 23:00:27.224954 TX Vref Scan disable
7723 23:00:27.227387 == TX Byte 0 ==
7724 23:00:27.230606 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7725 23:00:27.234079 == TX Byte 1 ==
7726 23:00:27.237422 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7727 23:00:27.240964 DramC Write-DBI off
7728 23:00:27.241376
7729 23:00:27.241740 [DATLAT]
7730 23:00:27.242047 Freq=1600, CH0 RK0
7731 23:00:27.242342
7732 23:00:27.244441 DATLAT Default: 0xf
7733 23:00:27.244853 0, 0xFFFF, sum = 0
7734 23:00:27.247719 1, 0xFFFF, sum = 0
7735 23:00:27.248137 2, 0xFFFF, sum = 0
7736 23:00:27.251121 3, 0xFFFF, sum = 0
7737 23:00:27.254217 4, 0xFFFF, sum = 0
7738 23:00:27.254636 5, 0xFFFF, sum = 0
7739 23:00:27.257512 6, 0xFFFF, sum = 0
7740 23:00:27.257965 7, 0xFFFF, sum = 0
7741 23:00:27.261306 8, 0xFFFF, sum = 0
7742 23:00:27.261773 9, 0xFFFF, sum = 0
7743 23:00:27.264284 10, 0xFFFF, sum = 0
7744 23:00:27.264701 11, 0xFFFF, sum = 0
7745 23:00:27.267883 12, 0xFFFF, sum = 0
7746 23:00:27.268302 13, 0xFFFF, sum = 0
7747 23:00:27.271247 14, 0x0, sum = 1
7748 23:00:27.271773 15, 0x0, sum = 2
7749 23:00:27.274087 16, 0x0, sum = 3
7750 23:00:27.274507 17, 0x0, sum = 4
7751 23:00:27.277503 best_step = 15
7752 23:00:27.277966
7753 23:00:27.278294 ==
7754 23:00:27.281008 Dram Type= 6, Freq= 0, CH_0, rank 0
7755 23:00:27.284343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7756 23:00:27.284879 ==
7757 23:00:27.285256 RX Vref Scan: 1
7758 23:00:27.285821
7759 23:00:27.287722 Set Vref Range= 24 -> 127
7760 23:00:27.288365
7761 23:00:27.290545 RX Vref 24 -> 127, step: 1
7762 23:00:27.290952
7763 23:00:27.294437 RX Delay 27 -> 252, step: 4
7764 23:00:27.294847
7765 23:00:27.297466 Set Vref, RX VrefLevel [Byte0]: 24
7766 23:00:27.301070 [Byte1]: 24
7767 23:00:27.301478
7768 23:00:27.303866 Set Vref, RX VrefLevel [Byte0]: 25
7769 23:00:27.307639 [Byte1]: 25
7770 23:00:27.308066
7771 23:00:27.310517 Set Vref, RX VrefLevel [Byte0]: 26
7772 23:00:27.314015 [Byte1]: 26
7773 23:00:27.317490
7774 23:00:27.317972 Set Vref, RX VrefLevel [Byte0]: 27
7775 23:00:27.320699 [Byte1]: 27
7776 23:00:27.325009
7777 23:00:27.325420 Set Vref, RX VrefLevel [Byte0]: 28
7778 23:00:27.328496 [Byte1]: 28
7779 23:00:27.332736
7780 23:00:27.333146 Set Vref, RX VrefLevel [Byte0]: 29
7781 23:00:27.335718 [Byte1]: 29
7782 23:00:27.339986
7783 23:00:27.340439 Set Vref, RX VrefLevel [Byte0]: 30
7784 23:00:27.343236 [Byte1]: 30
7785 23:00:27.347564
7786 23:00:27.347977 Set Vref, RX VrefLevel [Byte0]: 31
7787 23:00:27.351113 [Byte1]: 31
7788 23:00:27.355188
7789 23:00:27.355603 Set Vref, RX VrefLevel [Byte0]: 32
7790 23:00:27.358472 [Byte1]: 32
7791 23:00:27.363218
7792 23:00:27.363788 Set Vref, RX VrefLevel [Byte0]: 33
7793 23:00:27.366586 [Byte1]: 33
7794 23:00:27.370209
7795 23:00:27.370621 Set Vref, RX VrefLevel [Byte0]: 34
7796 23:00:27.373680 [Byte1]: 34
7797 23:00:27.377985
7798 23:00:27.378393 Set Vref, RX VrefLevel [Byte0]: 35
7799 23:00:27.381228 [Byte1]: 35
7800 23:00:27.385682
7801 23:00:27.386092 Set Vref, RX VrefLevel [Byte0]: 36
7802 23:00:27.388827 [Byte1]: 36
7803 23:00:27.392899
7804 23:00:27.393306 Set Vref, RX VrefLevel [Byte0]: 37
7805 23:00:27.399086 [Byte1]: 37
7806 23:00:27.399500
7807 23:00:27.402826 Set Vref, RX VrefLevel [Byte0]: 38
7808 23:00:27.406051 [Byte1]: 38
7809 23:00:27.406519
7810 23:00:27.408973 Set Vref, RX VrefLevel [Byte0]: 39
7811 23:00:27.412721 [Byte1]: 39
7812 23:00:27.413202
7813 23:00:27.416171 Set Vref, RX VrefLevel [Byte0]: 40
7814 23:00:27.419018 [Byte1]: 40
7815 23:00:27.423392
7816 23:00:27.423805 Set Vref, RX VrefLevel [Byte0]: 41
7817 23:00:27.426420 [Byte1]: 41
7818 23:00:27.430925
7819 23:00:27.431332 Set Vref, RX VrefLevel [Byte0]: 42
7820 23:00:27.433705 [Byte1]: 42
7821 23:00:27.437834
7822 23:00:27.438453 Set Vref, RX VrefLevel [Byte0]: 43
7823 23:00:27.441336 [Byte1]: 43
7824 23:00:27.445800
7825 23:00:27.446210 Set Vref, RX VrefLevel [Byte0]: 44
7826 23:00:27.449053 [Byte1]: 44
7827 23:00:27.453169
7828 23:00:27.453727 Set Vref, RX VrefLevel [Byte0]: 45
7829 23:00:27.456748 [Byte1]: 45
7830 23:00:27.460604
7831 23:00:27.461023 Set Vref, RX VrefLevel [Byte0]: 46
7832 23:00:27.464071 [Byte1]: 46
7833 23:00:27.468144
7834 23:00:27.468556 Set Vref, RX VrefLevel [Byte0]: 47
7835 23:00:27.471592 [Byte1]: 47
7836 23:00:27.475557
7837 23:00:27.475970 Set Vref, RX VrefLevel [Byte0]: 48
7838 23:00:27.479296 [Byte1]: 48
7839 23:00:27.483530
7840 23:00:27.483945 Set Vref, RX VrefLevel [Byte0]: 49
7841 23:00:27.486534 [Byte1]: 49
7842 23:00:27.491026
7843 23:00:27.491444 Set Vref, RX VrefLevel [Byte0]: 50
7844 23:00:27.494120 [Byte1]: 50
7845 23:00:27.498550
7846 23:00:27.498964 Set Vref, RX VrefLevel [Byte0]: 51
7847 23:00:27.501491 [Byte1]: 51
7848 23:00:27.505980
7849 23:00:27.506394 Set Vref, RX VrefLevel [Byte0]: 52
7850 23:00:27.509205 [Byte1]: 52
7851 23:00:27.513362
7852 23:00:27.513829 Set Vref, RX VrefLevel [Byte0]: 53
7853 23:00:27.516550 [Byte1]: 53
7854 23:00:27.520889
7855 23:00:27.521301 Set Vref, RX VrefLevel [Byte0]: 54
7856 23:00:27.524535 [Byte1]: 54
7857 23:00:27.528855
7858 23:00:27.529259 Set Vref, RX VrefLevel [Byte0]: 55
7859 23:00:27.531828 [Byte1]: 55
7860 23:00:27.536186
7861 23:00:27.536592 Set Vref, RX VrefLevel [Byte0]: 56
7862 23:00:27.539544 [Byte1]: 56
7863 23:00:27.543595
7864 23:00:27.544002 Set Vref, RX VrefLevel [Byte0]: 57
7865 23:00:27.546807 [Byte1]: 57
7866 23:00:27.550906
7867 23:00:27.551331 Set Vref, RX VrefLevel [Byte0]: 58
7868 23:00:27.554222 [Byte1]: 58
7869 23:00:27.558221
7870 23:00:27.558637 Set Vref, RX VrefLevel [Byte0]: 59
7871 23:00:27.561667 [Byte1]: 59
7872 23:00:27.565898
7873 23:00:27.566319 Set Vref, RX VrefLevel [Byte0]: 60
7874 23:00:27.569263 [Byte1]: 60
7875 23:00:27.573622
7876 23:00:27.574045 Set Vref, RX VrefLevel [Byte0]: 61
7877 23:00:27.576827 [Byte1]: 61
7878 23:00:27.580944
7879 23:00:27.581355 Set Vref, RX VrefLevel [Byte0]: 62
7880 23:00:27.584527 [Byte1]: 62
7881 23:00:27.588872
7882 23:00:27.589368 Set Vref, RX VrefLevel [Byte0]: 63
7883 23:00:27.591871 [Byte1]: 63
7884 23:00:27.596328
7885 23:00:27.596746 Set Vref, RX VrefLevel [Byte0]: 64
7886 23:00:27.599370 [Byte1]: 64
7887 23:00:27.604223
7888 23:00:27.604636 Set Vref, RX VrefLevel [Byte0]: 65
7889 23:00:27.607559 [Byte1]: 65
7890 23:00:27.611660
7891 23:00:27.612067 Set Vref, RX VrefLevel [Byte0]: 66
7892 23:00:27.614498 [Byte1]: 66
7893 23:00:27.618713
7894 23:00:27.619120 Set Vref, RX VrefLevel [Byte0]: 67
7895 23:00:27.622528 [Byte1]: 67
7896 23:00:27.626152
7897 23:00:27.626566 Set Vref, RX VrefLevel [Byte0]: 68
7898 23:00:27.629530 [Byte1]: 68
7899 23:00:27.633848
7900 23:00:27.634253 Set Vref, RX VrefLevel [Byte0]: 69
7901 23:00:27.637127 [Byte1]: 69
7902 23:00:27.641544
7903 23:00:27.642019 Set Vref, RX VrefLevel [Byte0]: 70
7904 23:00:27.645126 [Byte1]: 70
7905 23:00:27.648756
7906 23:00:27.649179 Set Vref, RX VrefLevel [Byte0]: 71
7907 23:00:27.652096 [Byte1]: 71
7908 23:00:27.656386
7909 23:00:27.656795 Set Vref, RX VrefLevel [Byte0]: 72
7910 23:00:27.663032 [Byte1]: 72
7911 23:00:27.663457
7912 23:00:27.666402 Set Vref, RX VrefLevel [Byte0]: 73
7913 23:00:27.669680 [Byte1]: 73
7914 23:00:27.670121
7915 23:00:27.672469 Final RX Vref Byte 0 = 55 to rank0
7916 23:00:27.676207 Final RX Vref Byte 1 = 63 to rank0
7917 23:00:27.679310 Final RX Vref Byte 0 = 55 to rank1
7918 23:00:27.682847 Final RX Vref Byte 1 = 63 to rank1==
7919 23:00:27.686037 Dram Type= 6, Freq= 0, CH_0, rank 0
7920 23:00:27.689364 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7921 23:00:27.689834 ==
7922 23:00:27.692651 DQS Delay:
7923 23:00:27.693069 DQS0 = 0, DQS1 = 0
7924 23:00:27.693399 DQM Delay:
7925 23:00:27.696063 DQM0 = 133, DQM1 = 128
7926 23:00:27.696482 DQ Delay:
7927 23:00:27.699283 DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130
7928 23:00:27.702461 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =138
7929 23:00:27.709196 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7930 23:00:27.713073 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7931 23:00:27.713480
7932 23:00:27.713859
7933 23:00:27.714199
7934 23:00:27.716187 [DramC_TX_OE_Calibration] TA2
7935 23:00:27.719148 Original DQ_B0 (3 6) =30, OEN = 27
7936 23:00:27.722271 Original DQ_B1 (3 6) =30, OEN = 27
7937 23:00:27.722817 24, 0x0, End_B0=24 End_B1=24
7938 23:00:27.726091 25, 0x0, End_B0=25 End_B1=25
7939 23:00:27.729765 26, 0x0, End_B0=26 End_B1=26
7940 23:00:27.732914 27, 0x0, End_B0=27 End_B1=27
7941 23:00:27.733327 28, 0x0, End_B0=28 End_B1=28
7942 23:00:27.736029 29, 0x0, End_B0=29 End_B1=29
7943 23:00:27.739319 30, 0x0, End_B0=30 End_B1=30
7944 23:00:27.742448 31, 0x4141, End_B0=30 End_B1=30
7945 23:00:27.745249 Byte0 end_step=30 best_step=27
7946 23:00:27.748918 Byte1 end_step=30 best_step=27
7947 23:00:27.749406 Byte0 TX OE(2T, 0.5T) = (3, 3)
7948 23:00:27.752192 Byte1 TX OE(2T, 0.5T) = (3, 3)
7949 23:00:27.752786
7950 23:00:27.753261
7951 23:00:27.762181 [DQSOSCAuto] RK0, (LSB)MR18= 0x231e, (MSB)MR19= 0x303, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
7952 23:00:27.765361 CH0 RK0: MR19=303, MR18=231E
7953 23:00:27.768773 CH0_RK0: MR19=0x303, MR18=0x231E, DQSOSC=392, MR23=63, INC=24, DEC=16
7954 23:00:27.769188
7955 23:00:27.772491 ----->DramcWriteLeveling(PI) begin...
7956 23:00:27.775875 ==
7957 23:00:27.776293 Dram Type= 6, Freq= 0, CH_0, rank 1
7958 23:00:27.782454 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7959 23:00:27.782877 ==
7960 23:00:27.785605 Write leveling (Byte 0): 38 => 38
7961 23:00:27.789165 Write leveling (Byte 1): 28 => 28
7962 23:00:27.792374 DramcWriteLeveling(PI) end<-----
7963 23:00:27.792791
7964 23:00:27.793119 ==
7965 23:00:27.795385 Dram Type= 6, Freq= 0, CH_0, rank 1
7966 23:00:27.798641 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7967 23:00:27.799062 ==
7968 23:00:27.801887 [Gating] SW mode calibration
7969 23:00:27.808669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7970 23:00:27.812310 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7971 23:00:27.818650 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7972 23:00:27.822157 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7973 23:00:27.825381 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7974 23:00:27.831815 1 4 12 | B1->B0 | 2323 2827 | 0 1 | (0 0) (1 1)
7975 23:00:27.835287 1 4 16 | B1->B0 | 3333 3636 | 1 1 | (1 1) (0 0)
7976 23:00:27.838657 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 23:00:27.845242 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7978 23:00:27.848494 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7979 23:00:27.852105 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7980 23:00:27.858732 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7981 23:00:27.862192 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (1 1)
7982 23:00:27.865352 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
7983 23:00:27.872111 1 5 16 | B1->B0 | 2d2d 2727 | 1 1 | (1 0) (1 0)
7984 23:00:27.875410 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7985 23:00:27.878669 1 5 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7986 23:00:27.885220 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7987 23:00:27.888417 1 6 0 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
7988 23:00:27.891961 1 6 4 | B1->B0 | 2323 1313 | 0 1 | (0 0) (0 0)
7989 23:00:27.898582 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7990 23:00:27.901937 1 6 12 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7991 23:00:27.905270 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7992 23:00:27.911598 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 23:00:27.914870 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7994 23:00:27.918595 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7995 23:00:27.925025 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7996 23:00:27.928933 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7997 23:00:27.931859 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7998 23:00:27.935297 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7999 23:00:27.941657 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8000 23:00:27.944970 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 23:00:27.948538 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 23:00:27.955008 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 23:00:27.958491 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 23:00:27.961643 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 23:00:27.968274 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 23:00:27.971851 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 23:00:27.975177 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 23:00:27.982104 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 23:00:27.985389 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 23:00:27.988403 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 23:00:27.995117 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 23:00:27.998165 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 23:00:28.002020 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 23:00:28.008597 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8015 23:00:28.011838 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 23:00:28.015133 Total UI for P1: 0, mck2ui 16
8017 23:00:28.018478 best dqsien dly found for B0: ( 1, 9, 12)
8018 23:00:28.021694 Total UI for P1: 0, mck2ui 16
8019 23:00:28.024999 best dqsien dly found for B1: ( 1, 9, 12)
8020 23:00:28.028513 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8021 23:00:28.031770 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8022 23:00:28.032184
8023 23:00:28.034816 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8024 23:00:28.038391 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8025 23:00:28.041689 [Gating] SW calibration Done
8026 23:00:28.042111 ==
8027 23:00:28.044919 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 23:00:28.048583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 23:00:28.049109 ==
8030 23:00:28.051986 RX Vref Scan: 0
8031 23:00:28.052404
8032 23:00:28.054942 RX Vref 0 -> 0, step: 1
8033 23:00:28.055360
8034 23:00:28.055688 RX Delay 0 -> 252, step: 8
8035 23:00:28.061637 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8036 23:00:28.064725 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8037 23:00:28.067878 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8038 23:00:28.071413 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8039 23:00:28.074976 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8040 23:00:28.081417 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8041 23:00:28.085293 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8042 23:00:28.088392 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8043 23:00:28.091398 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8044 23:00:28.094913 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8045 23:00:28.100955 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8046 23:00:28.104502 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8047 23:00:28.107703 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8048 23:00:28.110923 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8049 23:00:28.117405 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8050 23:00:28.120723 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8051 23:00:28.121141 ==
8052 23:00:28.124101 Dram Type= 6, Freq= 0, CH_0, rank 1
8053 23:00:28.127424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8054 23:00:28.127844 ==
8055 23:00:28.131025 DQS Delay:
8056 23:00:28.131442 DQS0 = 0, DQS1 = 0
8057 23:00:28.131773 DQM Delay:
8058 23:00:28.134700 DQM0 = 136, DQM1 = 128
8059 23:00:28.135116 DQ Delay:
8060 23:00:28.137304 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8061 23:00:28.140880 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8062 23:00:28.144335 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8063 23:00:28.150737 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8064 23:00:28.151257
8065 23:00:28.151591
8066 23:00:28.151895 ==
8067 23:00:28.153886 Dram Type= 6, Freq= 0, CH_0, rank 1
8068 23:00:28.157503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8069 23:00:28.157966 ==
8070 23:00:28.158296
8071 23:00:28.158603
8072 23:00:28.160685 TX Vref Scan disable
8073 23:00:28.161098 == TX Byte 0 ==
8074 23:00:28.166953 Update DQ dly =995 (3 ,6, 35) DQ OEN =(3 ,3)
8075 23:00:28.170822 Update DQM dly =995 (3 ,6, 35) DQM OEN =(3 ,3)
8076 23:00:28.174142 == TX Byte 1 ==
8077 23:00:28.177284 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8078 23:00:28.180511 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8079 23:00:28.181053 ==
8080 23:00:28.183871 Dram Type= 6, Freq= 0, CH_0, rank 1
8081 23:00:28.187373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8082 23:00:28.190325 ==
8083 23:00:28.203919
8084 23:00:28.207191 TX Vref early break, caculate TX vref
8085 23:00:28.210452 TX Vref=16, minBit 1, minWin=23, winSum=388
8086 23:00:28.213674 TX Vref=18, minBit 0, minWin=23, winSum=396
8087 23:00:28.216906 TX Vref=20, minBit 3, minWin=24, winSum=407
8088 23:00:28.220944 TX Vref=22, minBit 3, minWin=24, winSum=411
8089 23:00:28.223893 TX Vref=24, minBit 1, minWin=25, winSum=419
8090 23:00:28.230019 TX Vref=26, minBit 2, minWin=25, winSum=427
8091 23:00:28.233718 TX Vref=28, minBit 1, minWin=26, winSum=428
8092 23:00:28.236785 TX Vref=30, minBit 1, minWin=25, winSum=417
8093 23:00:28.240527 TX Vref=32, minBit 0, minWin=24, winSum=410
8094 23:00:28.243670 TX Vref=34, minBit 0, minWin=24, winSum=406
8095 23:00:28.247241 TX Vref=36, minBit 0, minWin=24, winSum=396
8096 23:00:28.253712 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 28
8097 23:00:28.254130
8098 23:00:28.256783 Final TX Range 0 Vref 28
8099 23:00:28.257195
8100 23:00:28.257520 ==
8101 23:00:28.260139 Dram Type= 6, Freq= 0, CH_0, rank 1
8102 23:00:28.263670 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8103 23:00:28.264089 ==
8104 23:00:28.264414
8105 23:00:28.264713
8106 23:00:28.267051 TX Vref Scan disable
8107 23:00:28.273468 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8108 23:00:28.273956 == TX Byte 0 ==
8109 23:00:28.276969 u2DelayCellOfst[0]=13 cells (4 PI)
8110 23:00:28.280346 u2DelayCellOfst[1]=16 cells (5 PI)
8111 23:00:28.283541 u2DelayCellOfst[2]=13 cells (4 PI)
8112 23:00:28.286877 u2DelayCellOfst[3]=13 cells (4 PI)
8113 23:00:28.290094 u2DelayCellOfst[4]=10 cells (3 PI)
8114 23:00:28.293427 u2DelayCellOfst[5]=0 cells (0 PI)
8115 23:00:28.297394 u2DelayCellOfst[6]=16 cells (5 PI)
8116 23:00:28.300185 u2DelayCellOfst[7]=16 cells (5 PI)
8117 23:00:28.303231 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8118 23:00:28.306572 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8119 23:00:28.309945 == TX Byte 1 ==
8120 23:00:28.313629 u2DelayCellOfst[8]=0 cells (0 PI)
8121 23:00:28.316935 u2DelayCellOfst[9]=0 cells (0 PI)
8122 23:00:28.317444 u2DelayCellOfst[10]=6 cells (2 PI)
8123 23:00:28.319844 u2DelayCellOfst[11]=3 cells (1 PI)
8124 23:00:28.323228 u2DelayCellOfst[12]=10 cells (3 PI)
8125 23:00:28.326588 u2DelayCellOfst[13]=10 cells (3 PI)
8126 23:00:28.330392 u2DelayCellOfst[14]=13 cells (4 PI)
8127 23:00:28.333340 u2DelayCellOfst[15]=10 cells (3 PI)
8128 23:00:28.336437 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8129 23:00:28.343579 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8130 23:00:28.343994 DramC Write-DBI on
8131 23:00:28.344322 ==
8132 23:00:28.347078 Dram Type= 6, Freq= 0, CH_0, rank 1
8133 23:00:28.353169 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8134 23:00:28.353618 ==
8135 23:00:28.353963
8136 23:00:28.354269
8137 23:00:28.354563 TX Vref Scan disable
8138 23:00:28.357135 == TX Byte 0 ==
8139 23:00:28.360816 Update DQM dly =739 (2 ,6, 35) DQM OEN =(3 ,3)
8140 23:00:28.364063 == TX Byte 1 ==
8141 23:00:28.367071 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8142 23:00:28.370794 DramC Write-DBI off
8143 23:00:28.371207
8144 23:00:28.371532 [DATLAT]
8145 23:00:28.371839 Freq=1600, CH0 RK1
8146 23:00:28.372136
8147 23:00:28.374307 DATLAT Default: 0xf
8148 23:00:28.374715 0, 0xFFFF, sum = 0
8149 23:00:28.377126 1, 0xFFFF, sum = 0
8150 23:00:28.380358 2, 0xFFFF, sum = 0
8151 23:00:28.380774 3, 0xFFFF, sum = 0
8152 23:00:28.383627 4, 0xFFFF, sum = 0
8153 23:00:28.384047 5, 0xFFFF, sum = 0
8154 23:00:28.387095 6, 0xFFFF, sum = 0
8155 23:00:28.387534 7, 0xFFFF, sum = 0
8156 23:00:28.390264 8, 0xFFFF, sum = 0
8157 23:00:28.390681 9, 0xFFFF, sum = 0
8158 23:00:28.393371 10, 0xFFFF, sum = 0
8159 23:00:28.393845 11, 0xFFFF, sum = 0
8160 23:00:28.396786 12, 0xFFFF, sum = 0
8161 23:00:28.397213 13, 0xFFFF, sum = 0
8162 23:00:28.400378 14, 0x0, sum = 1
8163 23:00:28.400798 15, 0x0, sum = 2
8164 23:00:28.403556 16, 0x0, sum = 3
8165 23:00:28.403975 17, 0x0, sum = 4
8166 23:00:28.406956 best_step = 15
8167 23:00:28.407366
8168 23:00:28.407690 ==
8169 23:00:28.410426 Dram Type= 6, Freq= 0, CH_0, rank 1
8170 23:00:28.413570 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8171 23:00:28.414124 ==
8172 23:00:28.416893 RX Vref Scan: 0
8173 23:00:28.417377
8174 23:00:28.417764 RX Vref 0 -> 0, step: 1
8175 23:00:28.418082
8176 23:00:28.420383 RX Delay 19 -> 252, step: 4
8177 23:00:28.423705 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8178 23:00:28.430723 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8179 23:00:28.433470 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8180 23:00:28.436872 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8181 23:00:28.440599 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8182 23:00:28.443577 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8183 23:00:28.450356 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8184 23:00:28.453260 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8185 23:00:28.456777 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8186 23:00:28.459839 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8187 23:00:28.463345 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8188 23:00:28.469813 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8189 23:00:28.473648 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8190 23:00:28.476438 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8191 23:00:28.480148 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8192 23:00:28.483465 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8193 23:00:28.486996 ==
8194 23:00:28.490190 Dram Type= 6, Freq= 0, CH_0, rank 1
8195 23:00:28.493182 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8196 23:00:28.493624 ==
8197 23:00:28.493960 DQS Delay:
8198 23:00:28.496576 DQS0 = 0, DQS1 = 0
8199 23:00:28.496987 DQM Delay:
8200 23:00:28.500056 DQM0 = 134, DQM1 = 127
8201 23:00:28.500469 DQ Delay:
8202 23:00:28.503453 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132
8203 23:00:28.506568 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8204 23:00:28.510369 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8205 23:00:28.513156 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =136
8206 23:00:28.513568
8207 23:00:28.513965
8208 23:00:28.514272
8209 23:00:28.516612 [DramC_TX_OE_Calibration] TA2
8210 23:00:28.520054 Original DQ_B0 (3 6) =30, OEN = 27
8211 23:00:28.523430 Original DQ_B1 (3 6) =30, OEN = 27
8212 23:00:28.526830 24, 0x0, End_B0=24 End_B1=24
8213 23:00:28.530180 25, 0x0, End_B0=25 End_B1=25
8214 23:00:28.530599 26, 0x0, End_B0=26 End_B1=26
8215 23:00:28.533438 27, 0x0, End_B0=27 End_B1=27
8216 23:00:28.536548 28, 0x0, End_B0=28 End_B1=28
8217 23:00:28.539771 29, 0x0, End_B0=29 End_B1=29
8218 23:00:28.540193 30, 0x0, End_B0=30 End_B1=30
8219 23:00:28.543416 31, 0x4141, End_B0=30 End_B1=30
8220 23:00:28.546360 Byte0 end_step=30 best_step=27
8221 23:00:28.549609 Byte1 end_step=30 best_step=27
8222 23:00:28.553177 Byte0 TX OE(2T, 0.5T) = (3, 3)
8223 23:00:28.556769 Byte1 TX OE(2T, 0.5T) = (3, 3)
8224 23:00:28.557189
8225 23:00:28.557724
8226 23:00:28.563434 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8227 23:00:28.567049 CH0 RK1: MR19=303, MR18=2008
8228 23:00:28.573533 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8229 23:00:28.576490 [RxdqsGatingPostProcess] freq 1600
8230 23:00:28.579907 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8231 23:00:28.583323 best DQS0 dly(2T, 0.5T) = (1, 1)
8232 23:00:28.586197 best DQS1 dly(2T, 0.5T) = (1, 1)
8233 23:00:28.590246 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8234 23:00:28.593668 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8235 23:00:28.596868 best DQS0 dly(2T, 0.5T) = (1, 1)
8236 23:00:28.600134 best DQS1 dly(2T, 0.5T) = (1, 1)
8237 23:00:28.603372 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8238 23:00:28.606842 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8239 23:00:28.610210 Pre-setting of DQS Precalculation
8240 23:00:28.613034 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8241 23:00:28.613454 ==
8242 23:00:28.616331 Dram Type= 6, Freq= 0, CH_1, rank 0
8243 23:00:28.622953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 23:00:28.623375 ==
8245 23:00:28.626215 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8246 23:00:28.629676 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8247 23:00:28.636176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8248 23:00:28.642896 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8249 23:00:28.650202 [CA 0] Center 42 (12~72) winsize 61
8250 23:00:28.653633 [CA 1] Center 42 (12~72) winsize 61
8251 23:00:28.656711 [CA 2] Center 38 (9~68) winsize 60
8252 23:00:28.660085 [CA 3] Center 38 (9~67) winsize 59
8253 23:00:28.663363 [CA 4] Center 38 (9~68) winsize 60
8254 23:00:28.667598 [CA 5] Center 37 (8~67) winsize 60
8255 23:00:28.668019
8256 23:00:28.670411 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8257 23:00:28.670832
8258 23:00:28.673843 [CATrainingPosCal] consider 1 rank data
8259 23:00:28.677447 u2DelayCellTimex100 = 290/100 ps
8260 23:00:28.680323 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8261 23:00:28.687228 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8262 23:00:28.690017 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8263 23:00:28.693366 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8264 23:00:28.696575 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8265 23:00:28.700686 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8266 23:00:28.701211
8267 23:00:28.703361 CA PerBit enable=1, Macro0, CA PI delay=37
8268 23:00:28.703937
8269 23:00:28.706866 [CBTSetCACLKResult] CA Dly = 37
8270 23:00:28.710135 CS Dly: 12 (0~43)
8271 23:00:28.713853 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8272 23:00:28.717277 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8273 23:00:28.717946 ==
8274 23:00:28.720086 Dram Type= 6, Freq= 0, CH_1, rank 1
8275 23:00:28.723259 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8276 23:00:28.723706 ==
8277 23:00:28.729854 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8278 23:00:28.733194 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8279 23:00:28.740156 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8280 23:00:28.743016 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8281 23:00:28.753642 [CA 0] Center 42 (12~72) winsize 61
8282 23:00:28.756750 [CA 1] Center 41 (12~71) winsize 60
8283 23:00:28.760079 [CA 2] Center 38 (9~68) winsize 60
8284 23:00:28.763424 [CA 3] Center 37 (8~67) winsize 60
8285 23:00:28.766350 [CA 4] Center 38 (8~68) winsize 61
8286 23:00:28.770355 [CA 5] Center 37 (8~67) winsize 60
8287 23:00:28.770774
8288 23:00:28.773636 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8289 23:00:28.774207
8290 23:00:28.777398 [CATrainingPosCal] consider 2 rank data
8291 23:00:28.779989 u2DelayCellTimex100 = 290/100 ps
8292 23:00:28.783380 CA0 delay=42 (12~72),Diff = 5 PI (16 cell)
8293 23:00:28.790206 CA1 delay=41 (12~71),Diff = 4 PI (13 cell)
8294 23:00:28.793536 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8295 23:00:28.796773 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8296 23:00:28.799717 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8297 23:00:28.803309 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8298 23:00:28.803893
8299 23:00:28.806514 CA PerBit enable=1, Macro0, CA PI delay=37
8300 23:00:28.806946
8301 23:00:28.810118 [CBTSetCACLKResult] CA Dly = 37
8302 23:00:28.813241 CS Dly: 12 (0~44)
8303 23:00:28.816682 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8304 23:00:28.819839 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8305 23:00:28.820285
8306 23:00:28.823352 ----->DramcWriteLeveling(PI) begin...
8307 23:00:28.823825 ==
8308 23:00:28.826708 Dram Type= 6, Freq= 0, CH_1, rank 0
8309 23:00:28.830106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8310 23:00:28.833401 ==
8311 23:00:28.833985 Write leveling (Byte 0): 26 => 26
8312 23:00:28.836519 Write leveling (Byte 1): 28 => 28
8313 23:00:28.839792 DramcWriteLeveling(PI) end<-----
8314 23:00:28.840217
8315 23:00:28.840613 ==
8316 23:00:28.843055 Dram Type= 6, Freq= 0, CH_1, rank 0
8317 23:00:28.850024 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8318 23:00:28.850595 ==
8319 23:00:28.851177 [Gating] SW mode calibration
8320 23:00:28.860269 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8321 23:00:28.863478 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8322 23:00:28.870060 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 23:00:28.872886 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8324 23:00:28.876444 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8325 23:00:28.879733 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8326 23:00:28.886815 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 23:00:28.890236 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 23:00:28.892991 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 23:00:28.899477 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 23:00:28.902757 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 23:00:28.906688 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8332 23:00:28.913286 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8333 23:00:28.916072 1 5 12 | B1->B0 | 2525 2323 | 0 0 | (0 1) (1 0)
8334 23:00:28.919488 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
8335 23:00:28.926242 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 23:00:28.929399 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 23:00:28.933097 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 23:00:28.940045 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 23:00:28.943208 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8340 23:00:28.946355 1 6 8 | B1->B0 | 2d2d 4141 | 0 0 | (1 1) (0 0)
8341 23:00:28.952898 1 6 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8342 23:00:28.956108 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 23:00:28.959956 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 23:00:28.966484 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 23:00:28.969684 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 23:00:28.973106 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8347 23:00:28.979250 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8348 23:00:28.982873 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8349 23:00:28.985987 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8350 23:00:28.992258 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 23:00:28.995762 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 23:00:28.999329 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 23:00:29.006084 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 23:00:29.009403 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 23:00:29.012561 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 23:00:29.015876 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 23:00:29.022898 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 23:00:29.026096 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 23:00:29.029625 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 23:00:29.035941 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 23:00:29.039141 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 23:00:29.042754 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 23:00:29.049424 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 23:00:29.052477 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8365 23:00:29.055718 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8366 23:00:29.062779 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 23:00:29.065898 Total UI for P1: 0, mck2ui 16
8368 23:00:29.068930 best dqsien dly found for B0: ( 1, 9, 10)
8369 23:00:29.069425 Total UI for P1: 0, mck2ui 16
8370 23:00:29.075612 best dqsien dly found for B1: ( 1, 9, 10)
8371 23:00:29.079202 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8372 23:00:29.082429 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8373 23:00:29.082839
8374 23:00:29.085544 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8375 23:00:29.088876 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8376 23:00:29.092277 [Gating] SW calibration Done
8377 23:00:29.092689 ==
8378 23:00:29.095675 Dram Type= 6, Freq= 0, CH_1, rank 0
8379 23:00:29.099306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8380 23:00:29.099846 ==
8381 23:00:29.102403 RX Vref Scan: 0
8382 23:00:29.102816
8383 23:00:29.103146 RX Vref 0 -> 0, step: 1
8384 23:00:29.105493
8385 23:00:29.105995 RX Delay 0 -> 252, step: 8
8386 23:00:29.112124 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8387 23:00:29.115555 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8388 23:00:29.118910 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8389 23:00:29.121985 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8390 23:00:29.125650 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8391 23:00:29.129106 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8392 23:00:29.135603 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8393 23:00:29.138477 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8394 23:00:29.142211 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8395 23:00:29.145295 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8396 23:00:29.148616 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8397 23:00:29.155443 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8398 23:00:29.159034 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8399 23:00:29.161923 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8400 23:00:29.165427 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8401 23:00:29.172264 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8402 23:00:29.172802 ==
8403 23:00:29.175165 Dram Type= 6, Freq= 0, CH_1, rank 0
8404 23:00:29.178452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8405 23:00:29.178875 ==
8406 23:00:29.179207 DQS Delay:
8407 23:00:29.181710 DQS0 = 0, DQS1 = 0
8408 23:00:29.182238 DQM Delay:
8409 23:00:29.185160 DQM0 = 136, DQM1 = 132
8410 23:00:29.185774 DQ Delay:
8411 23:00:29.188504 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8412 23:00:29.192242 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8413 23:00:29.195433 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8414 23:00:29.198836 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8415 23:00:29.199375
8416 23:00:29.199723
8417 23:00:29.200033 ==
8418 23:00:29.202071 Dram Type= 6, Freq= 0, CH_1, rank 0
8419 23:00:29.208799 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8420 23:00:29.209380 ==
8421 23:00:29.209948
8422 23:00:29.210363
8423 23:00:29.210697 TX Vref Scan disable
8424 23:00:29.212634 == TX Byte 0 ==
8425 23:00:29.215741 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8426 23:00:29.218861 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8427 23:00:29.222091 == TX Byte 1 ==
8428 23:00:29.225448 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8429 23:00:29.231970 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8430 23:00:29.232575 ==
8431 23:00:29.235426 Dram Type= 6, Freq= 0, CH_1, rank 0
8432 23:00:29.238841 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8433 23:00:29.239294 ==
8434 23:00:29.251122
8435 23:00:29.254265 TX Vref early break, caculate TX vref
8436 23:00:29.257300 TX Vref=16, minBit 1, minWin=21, winSum=369
8437 23:00:29.260976 TX Vref=18, minBit 0, minWin=22, winSum=382
8438 23:00:29.264098 TX Vref=20, minBit 0, minWin=23, winSum=397
8439 23:00:29.267488 TX Vref=22, minBit 1, minWin=23, winSum=403
8440 23:00:29.270803 TX Vref=24, minBit 6, minWin=24, winSum=416
8441 23:00:29.277708 TX Vref=26, minBit 0, minWin=25, winSum=422
8442 23:00:29.280694 TX Vref=28, minBit 0, minWin=25, winSum=425
8443 23:00:29.284012 TX Vref=30, minBit 2, minWin=24, winSum=419
8444 23:00:29.287384 TX Vref=32, minBit 0, minWin=24, winSum=411
8445 23:00:29.290921 TX Vref=34, minBit 2, minWin=23, winSum=398
8446 23:00:29.297882 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8447 23:00:29.298296
8448 23:00:29.300813 Final TX Range 0 Vref 28
8449 23:00:29.301224
8450 23:00:29.301546 ==
8451 23:00:29.304450 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 23:00:29.307582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 23:00:29.308176 ==
8454 23:00:29.308733
8455 23:00:29.309227
8456 23:00:29.310644 TX Vref Scan disable
8457 23:00:29.318030 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8458 23:00:29.318507 == TX Byte 0 ==
8459 23:00:29.320953 u2DelayCellOfst[0]=16 cells (5 PI)
8460 23:00:29.324377 u2DelayCellOfst[1]=10 cells (3 PI)
8461 23:00:29.327623 u2DelayCellOfst[2]=0 cells (0 PI)
8462 23:00:29.330880 u2DelayCellOfst[3]=6 cells (2 PI)
8463 23:00:29.334059 u2DelayCellOfst[4]=6 cells (2 PI)
8464 23:00:29.337552 u2DelayCellOfst[5]=16 cells (5 PI)
8465 23:00:29.338105 u2DelayCellOfst[6]=16 cells (5 PI)
8466 23:00:29.340758 u2DelayCellOfst[7]=6 cells (2 PI)
8467 23:00:29.347616 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8468 23:00:29.350740 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8469 23:00:29.351273 == TX Byte 1 ==
8470 23:00:29.354044 u2DelayCellOfst[8]=0 cells (0 PI)
8471 23:00:29.357314 u2DelayCellOfst[9]=3 cells (1 PI)
8472 23:00:29.360807 u2DelayCellOfst[10]=13 cells (4 PI)
8473 23:00:29.363910 u2DelayCellOfst[11]=3 cells (1 PI)
8474 23:00:29.367285 u2DelayCellOfst[12]=13 cells (4 PI)
8475 23:00:29.370340 u2DelayCellOfst[13]=13 cells (4 PI)
8476 23:00:29.373643 u2DelayCellOfst[14]=16 cells (5 PI)
8477 23:00:29.377134 u2DelayCellOfst[15]=16 cells (5 PI)
8478 23:00:29.380378 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8479 23:00:29.383782 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 23:00:29.387046 DramC Write-DBI on
8481 23:00:29.387657 ==
8482 23:00:29.390519 Dram Type= 6, Freq= 0, CH_1, rank 0
8483 23:00:29.394170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8484 23:00:29.394595 ==
8485 23:00:29.394922
8486 23:00:29.397562
8487 23:00:29.398022 TX Vref Scan disable
8488 23:00:29.400765 == TX Byte 0 ==
8489 23:00:29.403911 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8490 23:00:29.407129 == TX Byte 1 ==
8491 23:00:29.410522 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8492 23:00:29.411055 DramC Write-DBI off
8493 23:00:29.411503
8494 23:00:29.413439 [DATLAT]
8495 23:00:29.413951 Freq=1600, CH1 RK0
8496 23:00:29.414288
8497 23:00:29.417010 DATLAT Default: 0xf
8498 23:00:29.417488 0, 0xFFFF, sum = 0
8499 23:00:29.420332 1, 0xFFFF, sum = 0
8500 23:00:29.420747 2, 0xFFFF, sum = 0
8501 23:00:29.423490 3, 0xFFFF, sum = 0
8502 23:00:29.423952 4, 0xFFFF, sum = 0
8503 23:00:29.426717 5, 0xFFFF, sum = 0
8504 23:00:29.430011 6, 0xFFFF, sum = 0
8505 23:00:29.430428 7, 0xFFFF, sum = 0
8506 23:00:29.433616 8, 0xFFFF, sum = 0
8507 23:00:29.434036 9, 0xFFFF, sum = 0
8508 23:00:29.436698 10, 0xFFFF, sum = 0
8509 23:00:29.437163 11, 0xFFFF, sum = 0
8510 23:00:29.440137 12, 0xFFFF, sum = 0
8511 23:00:29.440635 13, 0xFFFF, sum = 0
8512 23:00:29.443513 14, 0x0, sum = 1
8513 23:00:29.443935 15, 0x0, sum = 2
8514 23:00:29.446593 16, 0x0, sum = 3
8515 23:00:29.447024 17, 0x0, sum = 4
8516 23:00:29.450123 best_step = 15
8517 23:00:29.450650
8518 23:00:29.451005 ==
8519 23:00:29.453127 Dram Type= 6, Freq= 0, CH_1, rank 0
8520 23:00:29.456496 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8521 23:00:29.456959 ==
8522 23:00:29.457301 RX Vref Scan: 1
8523 23:00:29.459982
8524 23:00:29.460439 Set Vref Range= 24 -> 127
8525 23:00:29.460802
8526 23:00:29.463022 RX Vref 24 -> 127, step: 1
8527 23:00:29.463522
8528 23:00:29.466662 RX Delay 27 -> 252, step: 4
8529 23:00:29.467075
8530 23:00:29.469971 Set Vref, RX VrefLevel [Byte0]: 24
8531 23:00:29.473160 [Byte1]: 24
8532 23:00:29.473569
8533 23:00:29.476330 Set Vref, RX VrefLevel [Byte0]: 25
8534 23:00:29.479982 [Byte1]: 25
8535 23:00:29.480394
8536 23:00:29.483840 Set Vref, RX VrefLevel [Byte0]: 26
8537 23:00:29.486509 [Byte1]: 26
8538 23:00:29.490089
8539 23:00:29.490549 Set Vref, RX VrefLevel [Byte0]: 27
8540 23:00:29.493469 [Byte1]: 27
8541 23:00:29.497905
8542 23:00:29.498320 Set Vref, RX VrefLevel [Byte0]: 28
8543 23:00:29.501135 [Byte1]: 28
8544 23:00:29.505215
8545 23:00:29.505740 Set Vref, RX VrefLevel [Byte0]: 29
8546 23:00:29.508847 [Byte1]: 29
8547 23:00:29.512674
8548 23:00:29.513104 Set Vref, RX VrefLevel [Byte0]: 30
8549 23:00:29.516078 [Byte1]: 30
8550 23:00:29.520334
8551 23:00:29.520772 Set Vref, RX VrefLevel [Byte0]: 31
8552 23:00:29.523562 [Byte1]: 31
8553 23:00:29.528278
8554 23:00:29.528725 Set Vref, RX VrefLevel [Byte0]: 32
8555 23:00:29.531528 [Byte1]: 32
8556 23:00:29.535326
8557 23:00:29.535753 Set Vref, RX VrefLevel [Byte0]: 33
8558 23:00:29.539080 [Byte1]: 33
8559 23:00:29.542618
8560 23:00:29.543065 Set Vref, RX VrefLevel [Byte0]: 34
8561 23:00:29.545883 [Byte1]: 34
8562 23:00:29.550491
8563 23:00:29.550905 Set Vref, RX VrefLevel [Byte0]: 35
8564 23:00:29.553942 [Byte1]: 35
8565 23:00:29.557976
8566 23:00:29.558459 Set Vref, RX VrefLevel [Byte0]: 36
8567 23:00:29.561458 [Byte1]: 36
8568 23:00:29.565342
8569 23:00:29.565822 Set Vref, RX VrefLevel [Byte0]: 37
8570 23:00:29.568820 [Byte1]: 37
8571 23:00:29.573078
8572 23:00:29.573489 Set Vref, RX VrefLevel [Byte0]: 38
8573 23:00:29.576791 [Byte1]: 38
8574 23:00:29.580512
8575 23:00:29.580921 Set Vref, RX VrefLevel [Byte0]: 39
8576 23:00:29.583957 [Byte1]: 39
8577 23:00:29.588302
8578 23:00:29.588723 Set Vref, RX VrefLevel [Byte0]: 40
8579 23:00:29.591562 [Byte1]: 40
8580 23:00:29.595627
8581 23:00:29.596043 Set Vref, RX VrefLevel [Byte0]: 41
8582 23:00:29.599105 [Byte1]: 41
8583 23:00:29.603046
8584 23:00:29.603138 Set Vref, RX VrefLevel [Byte0]: 42
8585 23:00:29.606386 [Byte1]: 42
8586 23:00:29.610291
8587 23:00:29.610373 Set Vref, RX VrefLevel [Byte0]: 43
8588 23:00:29.613747 [Byte1]: 43
8589 23:00:29.617908
8590 23:00:29.618028 Set Vref, RX VrefLevel [Byte0]: 44
8591 23:00:29.620959 [Byte1]: 44
8592 23:00:29.625453
8593 23:00:29.625566 Set Vref, RX VrefLevel [Byte0]: 45
8594 23:00:29.628855 [Byte1]: 45
8595 23:00:29.633039
8596 23:00:29.633119 Set Vref, RX VrefLevel [Byte0]: 46
8597 23:00:29.636629 [Byte1]: 46
8598 23:00:29.640906
8599 23:00:29.640997 Set Vref, RX VrefLevel [Byte0]: 47
8600 23:00:29.643722 [Byte1]: 47
8601 23:00:29.648148
8602 23:00:29.648227 Set Vref, RX VrefLevel [Byte0]: 48
8603 23:00:29.651418 [Byte1]: 48
8604 23:00:29.655595
8605 23:00:29.655680 Set Vref, RX VrefLevel [Byte0]: 49
8606 23:00:29.658905 [Byte1]: 49
8607 23:00:29.663252
8608 23:00:29.663330 Set Vref, RX VrefLevel [Byte0]: 50
8609 23:00:29.666397 [Byte1]: 50
8610 23:00:29.670843
8611 23:00:29.670934 Set Vref, RX VrefLevel [Byte0]: 51
8612 23:00:29.674531 [Byte1]: 51
8613 23:00:29.678230
8614 23:00:29.678328 Set Vref, RX VrefLevel [Byte0]: 52
8615 23:00:29.681866 [Byte1]: 52
8616 23:00:29.686070
8617 23:00:29.686481 Set Vref, RX VrefLevel [Byte0]: 53
8618 23:00:29.689058 [Byte1]: 53
8619 23:00:29.694025
8620 23:00:29.694445 Set Vref, RX VrefLevel [Byte0]: 54
8621 23:00:29.696269 [Byte1]: 54
8622 23:00:29.700936
8623 23:00:29.701344 Set Vref, RX VrefLevel [Byte0]: 55
8624 23:00:29.704583 [Byte1]: 55
8625 23:00:29.708572
8626 23:00:29.709001 Set Vref, RX VrefLevel [Byte0]: 56
8627 23:00:29.712132 [Byte1]: 56
8628 23:00:29.716359
8629 23:00:29.716839 Set Vref, RX VrefLevel [Byte0]: 57
8630 23:00:29.719319 [Byte1]: 57
8631 23:00:29.723702
8632 23:00:29.724122 Set Vref, RX VrefLevel [Byte0]: 58
8633 23:00:29.727441 [Byte1]: 58
8634 23:00:29.731492
8635 23:00:29.731993 Set Vref, RX VrefLevel [Byte0]: 59
8636 23:00:29.734366 [Byte1]: 59
8637 23:00:29.738924
8638 23:00:29.739348 Set Vref, RX VrefLevel [Byte0]: 60
8639 23:00:29.742314 [Byte1]: 60
8640 23:00:29.746581
8641 23:00:29.747001 Set Vref, RX VrefLevel [Byte0]: 61
8642 23:00:29.749410 [Byte1]: 61
8643 23:00:29.753883
8644 23:00:29.754310 Set Vref, RX VrefLevel [Byte0]: 62
8645 23:00:29.757157 [Byte1]: 62
8646 23:00:29.761449
8647 23:00:29.762047 Set Vref, RX VrefLevel [Byte0]: 63
8648 23:00:29.764829 [Byte1]: 63
8649 23:00:29.768873
8650 23:00:29.769280 Set Vref, RX VrefLevel [Byte0]: 64
8651 23:00:29.772365 [Byte1]: 64
8652 23:00:29.776986
8653 23:00:29.777065 Set Vref, RX VrefLevel [Byte0]: 65
8654 23:00:29.779521 [Byte1]: 65
8655 23:00:29.783847
8656 23:00:29.783928 Set Vref, RX VrefLevel [Byte0]: 66
8657 23:00:29.787331 [Byte1]: 66
8658 23:00:29.791712
8659 23:00:29.792167 Set Vref, RX VrefLevel [Byte0]: 67
8660 23:00:29.794426 [Byte1]: 67
8661 23:00:29.798519
8662 23:00:29.798598 Set Vref, RX VrefLevel [Byte0]: 68
8663 23:00:29.802017 [Byte1]: 68
8664 23:00:29.806755
8665 23:00:29.806915 Set Vref, RX VrefLevel [Byte0]: 69
8666 23:00:29.809294 [Byte1]: 69
8667 23:00:29.813982
8668 23:00:29.814074 Set Vref, RX VrefLevel [Byte0]: 70
8669 23:00:29.817151 [Byte1]: 70
8670 23:00:29.821480
8671 23:00:29.821608 Set Vref, RX VrefLevel [Byte0]: 71
8672 23:00:29.824482 [Byte1]: 71
8673 23:00:29.828717
8674 23:00:29.828808 Set Vref, RX VrefLevel [Byte0]: 72
8675 23:00:29.832030 [Byte1]: 72
8676 23:00:29.836105
8677 23:00:29.836229 Set Vref, RX VrefLevel [Byte0]: 73
8678 23:00:29.839612 [Byte1]: 73
8679 23:00:29.843884
8680 23:00:29.843979 Set Vref, RX VrefLevel [Byte0]: 74
8681 23:00:29.846829 [Byte1]: 74
8682 23:00:29.851200
8683 23:00:29.851292 Set Vref, RX VrefLevel [Byte0]: 75
8684 23:00:29.854370 [Byte1]: 75
8685 23:00:29.859096
8686 23:00:29.859188 Set Vref, RX VrefLevel [Byte0]: 76
8687 23:00:29.862266 [Byte1]: 76
8688 23:00:29.866433
8689 23:00:29.866541 Set Vref, RX VrefLevel [Byte0]: 77
8690 23:00:29.869761 [Byte1]: 77
8691 23:00:29.874067
8692 23:00:29.874185 Final RX Vref Byte 0 = 57 to rank0
8693 23:00:29.877462 Final RX Vref Byte 1 = 57 to rank0
8694 23:00:29.880695 Final RX Vref Byte 0 = 57 to rank1
8695 23:00:29.883924 Final RX Vref Byte 1 = 57 to rank1==
8696 23:00:29.887433 Dram Type= 6, Freq= 0, CH_1, rank 0
8697 23:00:29.894426 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8698 23:00:29.894623 ==
8699 23:00:29.894811 DQS Delay:
8700 23:00:29.894985 DQS0 = 0, DQS1 = 0
8701 23:00:29.897455 DQM Delay:
8702 23:00:29.897716 DQM0 = 134, DQM1 = 131
8703 23:00:29.900719 DQ Delay:
8704 23:00:29.903890 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8705 23:00:29.907568 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8706 23:00:29.911093 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8707 23:00:29.914352 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8708 23:00:29.914759
8709 23:00:29.915081
8710 23:00:29.915381
8711 23:00:29.917567 [DramC_TX_OE_Calibration] TA2
8712 23:00:29.920770 Original DQ_B0 (3 6) =30, OEN = 27
8713 23:00:29.924165 Original DQ_B1 (3 6) =30, OEN = 27
8714 23:00:29.927668 24, 0x0, End_B0=24 End_B1=24
8715 23:00:29.928084 25, 0x0, End_B0=25 End_B1=25
8716 23:00:29.930742 26, 0x0, End_B0=26 End_B1=26
8717 23:00:29.933940 27, 0x0, End_B0=27 End_B1=27
8718 23:00:29.937136 28, 0x0, End_B0=28 End_B1=28
8719 23:00:29.940551 29, 0x0, End_B0=29 End_B1=29
8720 23:00:29.940631 30, 0x0, End_B0=30 End_B1=30
8721 23:00:29.944145 31, 0x4141, End_B0=30 End_B1=30
8722 23:00:29.946880 Byte0 end_step=30 best_step=27
8723 23:00:29.950412 Byte1 end_step=30 best_step=27
8724 23:00:29.953533 Byte0 TX OE(2T, 0.5T) = (3, 3)
8725 23:00:29.956949 Byte1 TX OE(2T, 0.5T) = (3, 3)
8726 23:00:29.957141
8727 23:00:29.957245
8728 23:00:29.963485 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8729 23:00:29.966859 CH1 RK0: MR19=303, MR18=1724
8730 23:00:29.973820 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8731 23:00:29.973939
8732 23:00:29.976927 ----->DramcWriteLeveling(PI) begin...
8733 23:00:29.977138 ==
8734 23:00:29.980396 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 23:00:29.983732 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 23:00:29.983883 ==
8737 23:00:29.987117 Write leveling (Byte 0): 26 => 26
8738 23:00:29.990062 Write leveling (Byte 1): 29 => 29
8739 23:00:29.993356 DramcWriteLeveling(PI) end<-----
8740 23:00:29.993436
8741 23:00:29.993498 ==
8742 23:00:29.996615 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 23:00:29.999971 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 23:00:30.000063 ==
8745 23:00:30.003438 [Gating] SW mode calibration
8746 23:00:30.009907 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8747 23:00:30.016529 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8748 23:00:30.020250 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 23:00:30.026583 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 23:00:30.029713 1 4 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
8751 23:00:30.033083 1 4 12 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
8752 23:00:30.036465 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 23:00:30.042967 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 23:00:30.046272 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 23:00:30.049645 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 23:00:30.056583 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 23:00:30.059506 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 23:00:30.063166 1 5 8 | B1->B0 | 2525 3434 | 0 1 | (1 0) (1 0)
8759 23:00:30.069942 1 5 12 | B1->B0 | 2323 3131 | 0 0 | (1 0) (0 1)
8760 23:00:30.073311 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 23:00:30.076562 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 23:00:30.083240 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 23:00:30.086668 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 23:00:30.089794 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 23:00:30.096524 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 23:00:30.100042 1 6 8 | B1->B0 | 4040 2323 | 0 0 | (0 0) (0 0)
8767 23:00:30.103104 1 6 12 | B1->B0 | 4646 3938 | 0 1 | (0 0) (0 0)
8768 23:00:30.109513 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 23:00:30.113324 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 23:00:30.116015 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 23:00:30.122908 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 23:00:30.126761 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 23:00:30.129744 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8774 23:00:30.136995 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8775 23:00:30.139788 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8776 23:00:30.143073 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8777 23:00:30.149498 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 23:00:30.152967 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 23:00:30.156245 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 23:00:30.159956 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 23:00:30.166520 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 23:00:30.169500 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 23:00:30.172740 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 23:00:30.179391 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 23:00:30.183165 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 23:00:30.186055 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 23:00:30.192741 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 23:00:30.195893 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 23:00:30.199398 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8790 23:00:30.205892 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8791 23:00:30.209223 Total UI for P1: 0, mck2ui 16
8792 23:00:30.212750 best dqsien dly found for B1: ( 1, 9, 4)
8793 23:00:30.215730 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8794 23:00:30.219601 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8795 23:00:30.226215 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8796 23:00:30.226391 Total UI for P1: 0, mck2ui 16
8797 23:00:30.232713 best dqsien dly found for B0: ( 1, 9, 12)
8798 23:00:30.236247 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8799 23:00:30.239340 best DQS1 dly(MCK, UI, PI) = (1, 9, 4)
8800 23:00:30.239441
8801 23:00:30.243061 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8802 23:00:30.246158 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 4)
8803 23:00:30.249221 [Gating] SW calibration Done
8804 23:00:30.249302 ==
8805 23:00:30.252398 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 23:00:30.255653 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 23:00:30.255772 ==
8808 23:00:30.259111 RX Vref Scan: 0
8809 23:00:30.259218
8810 23:00:30.259314 RX Vref 0 -> 0, step: 1
8811 23:00:30.259406
8812 23:00:30.262590 RX Delay 0 -> 252, step: 8
8813 23:00:30.266595 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8814 23:00:30.269975 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8815 23:00:30.276350 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8816 23:00:30.279776 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8817 23:00:30.282716 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8818 23:00:30.286095 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8819 23:00:30.292773 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8820 23:00:30.296049 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8821 23:00:30.299367 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8822 23:00:30.302754 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8823 23:00:30.306317 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8824 23:00:30.312549 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8825 23:00:30.316107 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8826 23:00:30.319457 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8827 23:00:30.322496 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8828 23:00:30.325649 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8829 23:00:30.328929 ==
8830 23:00:30.332324 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 23:00:30.335773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 23:00:30.336313 ==
8833 23:00:30.336782 DQS Delay:
8834 23:00:30.338950 DQS0 = 0, DQS1 = 0
8835 23:00:30.339361 DQM Delay:
8836 23:00:30.342361 DQM0 = 136, DQM1 = 133
8837 23:00:30.342889 DQ Delay:
8838 23:00:30.345949 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8839 23:00:30.349196 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8840 23:00:30.352526 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8841 23:00:30.355978 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8842 23:00:30.356409
8843 23:00:30.356730
8844 23:00:30.357029 ==
8845 23:00:30.359112 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 23:00:30.365634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 23:00:30.366054 ==
8848 23:00:30.366413
8849 23:00:30.366728
8850 23:00:30.367015 TX Vref Scan disable
8851 23:00:30.369346 == TX Byte 0 ==
8852 23:00:30.372680 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8853 23:00:30.376098 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8854 23:00:30.379411 == TX Byte 1 ==
8855 23:00:30.382495 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8856 23:00:30.386190 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8857 23:00:30.389258 ==
8858 23:00:30.392827 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 23:00:30.396129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 23:00:30.396566 ==
8861 23:00:30.409217
8862 23:00:30.412553 TX Vref early break, caculate TX vref
8863 23:00:30.416103 TX Vref=16, minBit 2, minWin=22, winSum=381
8864 23:00:30.418934 TX Vref=18, minBit 2, minWin=23, winSum=392
8865 23:00:30.422135 TX Vref=20, minBit 0, minWin=24, winSum=401
8866 23:00:30.425771 TX Vref=22, minBit 1, minWin=24, winSum=407
8867 23:00:30.428860 TX Vref=24, minBit 0, minWin=25, winSum=420
8868 23:00:30.435581 TX Vref=26, minBit 0, minWin=25, winSum=423
8869 23:00:30.439306 TX Vref=28, minBit 0, minWin=25, winSum=427
8870 23:00:30.442241 TX Vref=30, minBit 0, minWin=25, winSum=422
8871 23:00:30.445534 TX Vref=32, minBit 0, minWin=24, winSum=415
8872 23:00:30.448955 TX Vref=34, minBit 1, minWin=24, winSum=405
8873 23:00:30.452193 TX Vref=36, minBit 0, minWin=23, winSum=394
8874 23:00:30.459034 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8875 23:00:30.459446
8876 23:00:30.462068 Final TX Range 0 Vref 28
8877 23:00:30.462533
8878 23:00:30.462908 ==
8879 23:00:30.465531 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 23:00:30.468865 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 23:00:30.469280 ==
8882 23:00:30.469640
8883 23:00:30.469953
8884 23:00:30.472196 TX Vref Scan disable
8885 23:00:30.479003 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8886 23:00:30.479417 == TX Byte 0 ==
8887 23:00:30.482774 u2DelayCellOfst[0]=16 cells (5 PI)
8888 23:00:30.485775 u2DelayCellOfst[1]=13 cells (4 PI)
8889 23:00:30.488676 u2DelayCellOfst[2]=0 cells (0 PI)
8890 23:00:30.492135 u2DelayCellOfst[3]=6 cells (2 PI)
8891 23:00:30.495309 u2DelayCellOfst[4]=10 cells (3 PI)
8892 23:00:30.499237 u2DelayCellOfst[5]=20 cells (6 PI)
8893 23:00:30.502190 u2DelayCellOfst[6]=20 cells (6 PI)
8894 23:00:30.505172 u2DelayCellOfst[7]=6 cells (2 PI)
8895 23:00:30.508765 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8896 23:00:30.512138 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8897 23:00:30.515264 == TX Byte 1 ==
8898 23:00:30.518579 u2DelayCellOfst[8]=0 cells (0 PI)
8899 23:00:30.519006 u2DelayCellOfst[9]=3 cells (1 PI)
8900 23:00:30.522084 u2DelayCellOfst[10]=10 cells (3 PI)
8901 23:00:30.525351 u2DelayCellOfst[11]=3 cells (1 PI)
8902 23:00:30.528663 u2DelayCellOfst[12]=13 cells (4 PI)
8903 23:00:30.532216 u2DelayCellOfst[13]=13 cells (4 PI)
8904 23:00:30.535270 u2DelayCellOfst[14]=13 cells (4 PI)
8905 23:00:30.538477 u2DelayCellOfst[15]=16 cells (5 PI)
8906 23:00:30.545289 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8907 23:00:30.548533 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8908 23:00:30.548944 DramC Write-DBI on
8909 23:00:30.549268 ==
8910 23:00:30.551820 Dram Type= 6, Freq= 0, CH_1, rank 1
8911 23:00:30.558416 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8912 23:00:30.558828 ==
8913 23:00:30.559158
8914 23:00:30.559456
8915 23:00:30.559751 TX Vref Scan disable
8916 23:00:30.562509 == TX Byte 0 ==
8917 23:00:30.565649 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8918 23:00:30.569127 == TX Byte 1 ==
8919 23:00:30.572350 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8920 23:00:30.575857 DramC Write-DBI off
8921 23:00:30.576264
8922 23:00:30.576584 [DATLAT]
8923 23:00:30.576886 Freq=1600, CH1 RK1
8924 23:00:30.577173
8925 23:00:30.578827 DATLAT Default: 0xf
8926 23:00:30.579235 0, 0xFFFF, sum = 0
8927 23:00:30.582452 1, 0xFFFF, sum = 0
8928 23:00:30.585893 2, 0xFFFF, sum = 0
8929 23:00:30.586314 3, 0xFFFF, sum = 0
8930 23:00:30.589183 4, 0xFFFF, sum = 0
8931 23:00:30.589696 5, 0xFFFF, sum = 0
8932 23:00:30.592100 6, 0xFFFF, sum = 0
8933 23:00:30.592472 7, 0xFFFF, sum = 0
8934 23:00:30.596097 8, 0xFFFF, sum = 0
8935 23:00:30.596514 9, 0xFFFF, sum = 0
8936 23:00:30.598992 10, 0xFFFF, sum = 0
8937 23:00:30.599407 11, 0xFFFF, sum = 0
8938 23:00:30.602339 12, 0xFFFF, sum = 0
8939 23:00:30.602751 13, 0xFFFF, sum = 0
8940 23:00:30.605343 14, 0x0, sum = 1
8941 23:00:30.605810 15, 0x0, sum = 2
8942 23:00:30.609126 16, 0x0, sum = 3
8943 23:00:30.609692 17, 0x0, sum = 4
8944 23:00:30.611842 best_step = 15
8945 23:00:30.612440
8946 23:00:30.612778 ==
8947 23:00:30.615551 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 23:00:30.618736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 23:00:30.619149 ==
8950 23:00:30.621697 RX Vref Scan: 0
8951 23:00:30.622109
8952 23:00:30.622439 RX Vref 0 -> 0, step: 1
8953 23:00:30.622745
8954 23:00:30.625372 RX Delay 19 -> 252, step: 4
8955 23:00:30.628298 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8956 23:00:30.635566 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
8957 23:00:30.638396 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8958 23:00:30.641825 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8959 23:00:30.644999 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8960 23:00:30.649171 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8961 23:00:30.654921 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8962 23:00:30.658407 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
8963 23:00:30.662025 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8964 23:00:30.665282 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8965 23:00:30.668715 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8966 23:00:30.675658 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8967 23:00:30.678679 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8968 23:00:30.681647 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8969 23:00:30.684948 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8970 23:00:30.688238 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8971 23:00:30.691633 ==
8972 23:00:30.692043 Dram Type= 6, Freq= 0, CH_1, rank 1
8973 23:00:30.698415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8974 23:00:30.698827 ==
8975 23:00:30.699155 DQS Delay:
8976 23:00:30.701660 DQS0 = 0, DQS1 = 0
8977 23:00:30.702070 DQM Delay:
8978 23:00:30.705047 DQM0 = 133, DQM1 = 130
8979 23:00:30.705456 DQ Delay:
8980 23:00:30.708808 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
8981 23:00:30.711809 DQ4 =130, DQ5 =146, DQ6 =142, DQ7 =132
8982 23:00:30.715282 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8983 23:00:30.718470 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8984 23:00:30.718930
8985 23:00:30.719258
8986 23:00:30.719594
8987 23:00:30.722011 [DramC_TX_OE_Calibration] TA2
8988 23:00:30.725394 Original DQ_B0 (3 6) =30, OEN = 27
8989 23:00:30.728425 Original DQ_B1 (3 6) =30, OEN = 27
8990 23:00:30.731654 24, 0x0, End_B0=24 End_B1=24
8991 23:00:30.735454 25, 0x0, End_B0=25 End_B1=25
8992 23:00:30.735869 26, 0x0, End_B0=26 End_B1=26
8993 23:00:30.738866 27, 0x0, End_B0=27 End_B1=27
8994 23:00:30.741709 28, 0x0, End_B0=28 End_B1=28
8995 23:00:30.745088 29, 0x0, End_B0=29 End_B1=29
8996 23:00:30.745505 30, 0x0, End_B0=30 End_B1=30
8997 23:00:30.748418 31, 0x4141, End_B0=30 End_B1=30
8998 23:00:30.751676 Byte0 end_step=30 best_step=27
8999 23:00:30.755281 Byte1 end_step=30 best_step=27
9000 23:00:30.758861 Byte0 TX OE(2T, 0.5T) = (3, 3)
9001 23:00:30.762002 Byte1 TX OE(2T, 0.5T) = (3, 3)
9002 23:00:30.762414
9003 23:00:30.762739
9004 23:00:30.768038 [DQSOSCAuto] RK1, (LSB)MR18= 0x2308, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9005 23:00:30.771683 CH1 RK1: MR19=303, MR18=2308
9006 23:00:30.778690 CH1_RK1: MR19=0x303, MR18=0x2308, DQSOSC=392, MR23=63, INC=24, DEC=16
9007 23:00:30.781839 [RxdqsGatingPostProcess] freq 1600
9008 23:00:30.784962 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9009 23:00:30.788115 best DQS0 dly(2T, 0.5T) = (1, 1)
9010 23:00:30.791363 best DQS1 dly(2T, 0.5T) = (1, 1)
9011 23:00:30.794918 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9012 23:00:30.797883 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9013 23:00:30.801426 best DQS0 dly(2T, 0.5T) = (1, 1)
9014 23:00:30.804991 best DQS1 dly(2T, 0.5T) = (1, 1)
9015 23:00:30.808334 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9016 23:00:30.811683 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9017 23:00:30.814955 Pre-setting of DQS Precalculation
9018 23:00:30.817915 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9019 23:00:30.824663 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9020 23:00:30.834621 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9021 23:00:30.835033
9022 23:00:30.835357
9023 23:00:30.835659 [Calibration Summary] 3200 Mbps
9024 23:00:30.838148 CH 0, Rank 0
9025 23:00:30.841551 SW Impedance : PASS
9026 23:00:30.842014 DUTY Scan : NO K
9027 23:00:30.844579 ZQ Calibration : PASS
9028 23:00:30.844988 Jitter Meter : NO K
9029 23:00:30.848023 CBT Training : PASS
9030 23:00:30.851246 Write leveling : PASS
9031 23:00:30.851655 RX DQS gating : PASS
9032 23:00:30.854721 RX DQ/DQS(RDDQC) : PASS
9033 23:00:30.857976 TX DQ/DQS : PASS
9034 23:00:30.858385 RX DATLAT : PASS
9035 23:00:30.861270 RX DQ/DQS(Engine): PASS
9036 23:00:30.864661 TX OE : PASS
9037 23:00:30.865073 All Pass.
9038 23:00:30.865392
9039 23:00:30.865754 CH 0, Rank 1
9040 23:00:30.868373 SW Impedance : PASS
9041 23:00:30.871500 DUTY Scan : NO K
9042 23:00:30.871909 ZQ Calibration : PASS
9043 23:00:30.874993 Jitter Meter : NO K
9044 23:00:30.877906 CBT Training : PASS
9045 23:00:30.878318 Write leveling : PASS
9046 23:00:30.881392 RX DQS gating : PASS
9047 23:00:30.884428 RX DQ/DQS(RDDQC) : PASS
9048 23:00:30.884901 TX DQ/DQS : PASS
9049 23:00:30.887796 RX DATLAT : PASS
9050 23:00:30.891245 RX DQ/DQS(Engine): PASS
9051 23:00:30.891657 TX OE : PASS
9052 23:00:30.891986 All Pass.
9053 23:00:30.894628
9054 23:00:30.895035 CH 1, Rank 0
9055 23:00:30.897702 SW Impedance : PASS
9056 23:00:30.898112 DUTY Scan : NO K
9057 23:00:30.901091 ZQ Calibration : PASS
9058 23:00:30.901499 Jitter Meter : NO K
9059 23:00:30.904447 CBT Training : PASS
9060 23:00:30.907416 Write leveling : PASS
9061 23:00:30.907496 RX DQS gating : PASS
9062 23:00:30.910777 RX DQ/DQS(RDDQC) : PASS
9063 23:00:30.914247 TX DQ/DQS : PASS
9064 23:00:30.914327 RX DATLAT : PASS
9065 23:00:30.917499 RX DQ/DQS(Engine): PASS
9066 23:00:30.921217 TX OE : PASS
9067 23:00:30.921659 All Pass.
9068 23:00:30.921988
9069 23:00:30.922291 CH 1, Rank 1
9070 23:00:30.924798 SW Impedance : PASS
9071 23:00:30.927692 DUTY Scan : NO K
9072 23:00:30.928103 ZQ Calibration : PASS
9073 23:00:30.930930 Jitter Meter : NO K
9074 23:00:30.934218 CBT Training : PASS
9075 23:00:30.934630 Write leveling : PASS
9076 23:00:30.937630 RX DQS gating : PASS
9077 23:00:30.938045 RX DQ/DQS(RDDQC) : PASS
9078 23:00:30.941076 TX DQ/DQS : PASS
9079 23:00:30.944549 RX DATLAT : PASS
9080 23:00:30.944961 RX DQ/DQS(Engine): PASS
9081 23:00:30.947650 TX OE : PASS
9082 23:00:30.948073 All Pass.
9083 23:00:30.948497
9084 23:00:30.950962 DramC Write-DBI on
9085 23:00:30.954834 PER_BANK_REFRESH: Hybrid Mode
9086 23:00:30.955285 TX_TRACKING: ON
9087 23:00:30.964234 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9088 23:00:30.971135 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9089 23:00:30.978083 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9090 23:00:30.984163 [FAST_K] Save calibration result to emmc
9091 23:00:30.984585 sync common calibartion params.
9092 23:00:30.987681 sync cbt_mode0:1, 1:1
9093 23:00:30.990801 dram_init: ddr_geometry: 2
9094 23:00:30.991206 dram_init: ddr_geometry: 2
9095 23:00:30.994143 dram_init: ddr_geometry: 2
9096 23:00:30.997636 0:dram_rank_size:100000000
9097 23:00:31.001004 1:dram_rank_size:100000000
9098 23:00:31.004346 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9099 23:00:31.007395 DFS_SHUFFLE_HW_MODE: ON
9100 23:00:31.010684 dramc_set_vcore_voltage set vcore to 725000
9101 23:00:31.014276 Read voltage for 1600, 0
9102 23:00:31.014687 Vio18 = 0
9103 23:00:31.016950 Vcore = 725000
9104 23:00:31.017029 Vdram = 0
9105 23:00:31.017093 Vddq = 0
9106 23:00:31.017151 Vmddr = 0
9107 23:00:31.020682 switch to 3200 Mbps bootup
9108 23:00:31.024128 [DramcRunTimeConfig]
9109 23:00:31.024207 PHYPLL
9110 23:00:31.026790 DPM_CONTROL_AFTERK: ON
9111 23:00:31.026870 PER_BANK_REFRESH: ON
9112 23:00:31.030180 REFRESH_OVERHEAD_REDUCTION: ON
9113 23:00:31.033898 CMD_PICG_NEW_MODE: OFF
9114 23:00:31.033977 XRTWTW_NEW_MODE: ON
9115 23:00:31.037137 XRTRTR_NEW_MODE: ON
9116 23:00:31.037216 TX_TRACKING: ON
9117 23:00:31.040281 RDSEL_TRACKING: OFF
9118 23:00:31.040360 DQS Precalculation for DVFS: ON
9119 23:00:31.043596 RX_TRACKING: OFF
9120 23:00:31.043675 HW_GATING DBG: ON
9121 23:00:31.047004 ZQCS_ENABLE_LP4: ON
9122 23:00:31.050395 RX_PICG_NEW_MODE: ON
9123 23:00:31.050475 TX_PICG_NEW_MODE: ON
9124 23:00:31.053781 ENABLE_RX_DCM_DPHY: ON
9125 23:00:31.056775 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9126 23:00:31.056904 DUMMY_READ_FOR_TRACKING: OFF
9127 23:00:31.060384 !!! SPM_CONTROL_AFTERK: OFF
9128 23:00:31.063406 !!! SPM could not control APHY
9129 23:00:31.066739 IMPEDANCE_TRACKING: ON
9130 23:00:31.066894 TEMP_SENSOR: ON
9131 23:00:31.070272 HW_SAVE_FOR_SR: OFF
9132 23:00:31.073641 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9133 23:00:31.076944 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9134 23:00:31.077111 Read ODT Tracking: ON
9135 23:00:31.079978 Refresh Rate DeBounce: ON
9136 23:00:31.083425 DFS_NO_QUEUE_FLUSH: ON
9137 23:00:31.086848 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9138 23:00:31.087071 ENABLE_DFS_RUNTIME_MRW: OFF
9139 23:00:31.090085 DDR_RESERVE_NEW_MODE: ON
9140 23:00:31.093155 MR_CBT_SWITCH_FREQ: ON
9141 23:00:31.093322 =========================
9142 23:00:31.114095 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9143 23:00:31.116596 dram_init: ddr_geometry: 2
9144 23:00:31.135607 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9145 23:00:31.138899 dram_init: dram init end (result: 0)
9146 23:00:31.145063 DRAM-K: Full calibration passed in 24434 msecs
9147 23:00:31.148598 MRC: failed to locate region type 0.
9148 23:00:31.149117 DRAM rank0 size:0x100000000,
9149 23:00:31.151650 DRAM rank1 size=0x100000000
9150 23:00:31.161859 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9151 23:00:31.168171 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9152 23:00:31.174906 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9153 23:00:31.181659 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9154 23:00:31.184513 DRAM rank0 size:0x100000000,
9155 23:00:31.188006 DRAM rank1 size=0x100000000
9156 23:00:31.188416 CBMEM:
9157 23:00:31.191527 IMD: root @ 0xfffff000 254 entries.
9158 23:00:31.194515 IMD: root @ 0xffffec00 62 entries.
9159 23:00:31.197820 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9160 23:00:31.201347 WARNING: RO_VPD is uninitialized or empty.
9161 23:00:31.207435 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9162 23:00:31.214678 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9163 23:00:31.227392 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9164 23:00:31.239275 BS: romstage times (exec / console): total (unknown) / 23968 ms
9165 23:00:31.239356
9166 23:00:31.239420
9167 23:00:31.248762 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9168 23:00:31.251992 ARM64: Exception handlers installed.
9169 23:00:31.255388 ARM64: Testing exception
9170 23:00:31.259142 ARM64: Done test exception
9171 23:00:31.259242 Enumerating buses...
9172 23:00:31.262093 Show all devs... Before device enumeration.
9173 23:00:31.265547 Root Device: enabled 1
9174 23:00:31.268900 CPU_CLUSTER: 0: enabled 1
9175 23:00:31.269019 CPU: 00: enabled 1
9176 23:00:31.272142 Compare with tree...
9177 23:00:31.272274 Root Device: enabled 1
9178 23:00:31.275300 CPU_CLUSTER: 0: enabled 1
9179 23:00:31.278938 CPU: 00: enabled 1
9180 23:00:31.279086 Root Device scanning...
9181 23:00:31.282179 scan_static_bus for Root Device
9182 23:00:31.285423 CPU_CLUSTER: 0 enabled
9183 23:00:31.288480 scan_static_bus for Root Device done
9184 23:00:31.292148 scan_bus: bus Root Device finished in 8 msecs
9185 23:00:31.292313 done
9186 23:00:31.299278 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9187 23:00:31.301905 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9188 23:00:31.308901 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9189 23:00:31.312069 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9190 23:00:31.315309 Allocating resources...
9191 23:00:31.319147 Reading resources...
9192 23:00:31.321864 Root Device read_resources bus 0 link: 0
9193 23:00:31.321944 DRAM rank0 size:0x100000000,
9194 23:00:31.325356 DRAM rank1 size=0x100000000
9195 23:00:31.328923 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9196 23:00:31.332153 CPU: 00 missing read_resources
9197 23:00:31.335369 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9198 23:00:31.342273 Root Device read_resources bus 0 link: 0 done
9199 23:00:31.342356 Done reading resources.
9200 23:00:31.348379 Show resources in subtree (Root Device)...After reading.
9201 23:00:31.352074 Root Device child on link 0 CPU_CLUSTER: 0
9202 23:00:31.355083 CPU_CLUSTER: 0 child on link 0 CPU: 00
9203 23:00:31.365500 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9204 23:00:31.366043 CPU: 00
9205 23:00:31.368698 Root Device assign_resources, bus 0 link: 0
9206 23:00:31.371987 CPU_CLUSTER: 0 missing set_resources
9207 23:00:31.375624 Root Device assign_resources, bus 0 link: 0 done
9208 23:00:31.378855 Done setting resources.
9209 23:00:31.385281 Show resources in subtree (Root Device)...After assigning values.
9210 23:00:31.388539 Root Device child on link 0 CPU_CLUSTER: 0
9211 23:00:31.392164 CPU_CLUSTER: 0 child on link 0 CPU: 00
9212 23:00:31.402163 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9213 23:00:31.402579 CPU: 00
9214 23:00:31.405255 Done allocating resources.
9215 23:00:31.408748 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9216 23:00:31.412267 Enabling resources...
9217 23:00:31.412676 done.
9218 23:00:31.418832 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9219 23:00:31.419248 Initializing devices...
9220 23:00:31.421943 Root Device init
9221 23:00:31.422352 init hardware done!
9222 23:00:31.425717 0x00000018: ctrlr->caps
9223 23:00:31.429155 52.000 MHz: ctrlr->f_max
9224 23:00:31.429571 0.400 MHz: ctrlr->f_min
9225 23:00:31.432225 0x40ff8080: ctrlr->voltages
9226 23:00:31.432705 sclk: 390625
9227 23:00:31.435384 Bus Width = 1
9228 23:00:31.435791 sclk: 390625
9229 23:00:31.438818 Bus Width = 1
9230 23:00:31.439229 Early init status = 3
9231 23:00:31.445303 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9232 23:00:31.448527 in-header: 03 fc 00 00 01 00 00 00
9233 23:00:31.448937 in-data: 00
9234 23:00:31.455191 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9235 23:00:31.458189 in-header: 03 fd 00 00 00 00 00 00
9236 23:00:31.461712 in-data:
9237 23:00:31.464702 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9238 23:00:31.468119 in-header: 03 fc 00 00 01 00 00 00
9239 23:00:31.471525 in-data: 00
9240 23:00:31.475156 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9241 23:00:31.479117 in-header: 03 fd 00 00 00 00 00 00
9242 23:00:31.482515 in-data:
9243 23:00:31.485880 [SSUSB] Setting up USB HOST controller...
9244 23:00:31.489034 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9245 23:00:31.492454 [SSUSB] phy power-on done.
9246 23:00:31.495797 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9247 23:00:31.502278 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9248 23:00:31.505336 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9249 23:00:31.512922 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9250 23:00:31.519293 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9251 23:00:31.525862 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9252 23:00:31.532280 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9253 23:00:31.538971 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9254 23:00:31.542489 SPM: binary array size = 0x9dc
9255 23:00:31.545846 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9256 23:00:31.552214 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9257 23:00:31.558216 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9258 23:00:31.562403 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9259 23:00:31.568544 configure_display: Starting display init
9260 23:00:31.602612 anx7625_power_on_init: Init interface.
9261 23:00:31.605694 anx7625_disable_pd_protocol: Disabled PD feature.
9262 23:00:31.609000 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9263 23:00:31.636829 anx7625_start_dp_work: Secure OCM version=00
9264 23:00:31.640649 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9265 23:00:31.654859 sp_tx_get_edid_block: EDID Block = 1
9266 23:00:31.758089 Extracted contents:
9267 23:00:31.761034 header: 00 ff ff ff ff ff ff 00
9268 23:00:31.764331 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9269 23:00:31.767864 version: 01 04
9270 23:00:31.771023 basic params: 95 1f 11 78 0a
9271 23:00:31.774280 chroma info: 76 90 94 55 54 90 27 21 50 54
9272 23:00:31.777385 established: 00 00 00
9273 23:00:31.784435 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9274 23:00:31.787385 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9275 23:00:31.794318 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9276 23:00:31.800595 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9277 23:00:31.807581 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9278 23:00:31.810726 extensions: 00
9279 23:00:31.811138 checksum: fb
9280 23:00:31.811497
9281 23:00:31.813789 Manufacturer: IVO Model 57d Serial Number 0
9282 23:00:31.817145 Made week 0 of 2020
9283 23:00:31.817737 EDID version: 1.4
9284 23:00:31.820629 Digital display
9285 23:00:31.823961 6 bits per primary color channel
9286 23:00:31.824379 DisplayPort interface
9287 23:00:31.827435 Maximum image size: 31 cm x 17 cm
9288 23:00:31.830494 Gamma: 220%
9289 23:00:31.830902 Check DPMS levels
9290 23:00:31.834145 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9291 23:00:31.838729 First detailed timing is preferred timing
9292 23:00:31.840740 Established timings supported:
9293 23:00:31.843978 Standard timings supported:
9294 23:00:31.844382 Detailed timings
9295 23:00:31.850814 Hex of detail: 383680a07038204018303c0035ae10000019
9296 23:00:31.853979 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9297 23:00:31.860694 0780 0798 07c8 0820 hborder 0
9298 23:00:31.863845 0438 043b 0447 0458 vborder 0
9299 23:00:31.864272 -hsync -vsync
9300 23:00:31.867752 Did detailed timing
9301 23:00:31.870525 Hex of detail: 000000000000000000000000000000000000
9302 23:00:31.874118 Manufacturer-specified data, tag 0
9303 23:00:31.880382 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9304 23:00:31.880812 ASCII string: InfoVision
9305 23:00:31.886947 Hex of detail: 000000fe00523134304e574635205248200a
9306 23:00:31.890656 ASCII string: R140NWF5 RH
9307 23:00:31.891152 Checksum
9308 23:00:31.891477 Checksum: 0xfb (valid)
9309 23:00:31.897123 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9310 23:00:31.900127 DSI data_rate: 832800000 bps
9311 23:00:31.903765 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9312 23:00:31.910170 anx7625_parse_edid: pixelclock(138800).
9313 23:00:31.913440 hactive(1920), hsync(48), hfp(24), hbp(88)
9314 23:00:31.916926 vactive(1080), vsync(12), vfp(3), vbp(17)
9315 23:00:31.920401 anx7625_dsi_config: config dsi.
9316 23:00:31.926845 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9317 23:00:31.939493 anx7625_dsi_config: success to config DSI
9318 23:00:31.942757 anx7625_dp_start: MIPI phy setup OK.
9319 23:00:31.946481 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9320 23:00:31.949569 mtk_ddp_mode_set invalid vrefresh 60
9321 23:00:31.952661 main_disp_path_setup
9322 23:00:31.953072 ovl_layer_smi_id_en
9323 23:00:31.956411 ovl_layer_smi_id_en
9324 23:00:31.956823 ccorr_config
9325 23:00:31.957151 aal_config
9326 23:00:31.959834 gamma_config
9327 23:00:31.960246 postmask_config
9328 23:00:31.962945 dither_config
9329 23:00:31.965999 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9330 23:00:31.972906 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9331 23:00:31.975861 Root Device init finished in 551 msecs
9332 23:00:31.979236 CPU_CLUSTER: 0 init
9333 23:00:31.986211 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9334 23:00:31.989419 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9335 23:00:31.992588 APU_MBOX 0x190000b0 = 0x10001
9336 23:00:31.995821 APU_MBOX 0x190001b0 = 0x10001
9337 23:00:31.999101 APU_MBOX 0x190005b0 = 0x10001
9338 23:00:32.002452 APU_MBOX 0x190006b0 = 0x10001
9339 23:00:32.005636 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9340 23:00:32.018643 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9341 23:00:32.031334 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9342 23:00:32.037317 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9343 23:00:32.049175 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9344 23:00:32.058337 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9345 23:00:32.061774 CPU_CLUSTER: 0 init finished in 81 msecs
9346 23:00:32.065035 Devices initialized
9347 23:00:32.068420 Show all devs... After init.
9348 23:00:32.068714 Root Device: enabled 1
9349 23:00:32.071329 CPU_CLUSTER: 0: enabled 1
9350 23:00:32.074879 CPU: 00: enabled 1
9351 23:00:32.078414 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9352 23:00:32.081594 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9353 23:00:32.084746 ELOG: NV offset 0x57f000 size 0x1000
9354 23:00:32.091602 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9355 23:00:32.098316 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9356 23:00:32.101683 ELOG: Event(17) added with size 13 at 2023-12-03 22:58:19 UTC
9357 23:00:32.105189 out: cmd=0x121: 03 db 21 01 00 00 00 00
9358 23:00:32.108688 in-header: 03 f6 00 00 2c 00 00 00
9359 23:00:32.121760 in-data: 69 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9360 23:00:32.128282 ELOG: Event(A1) added with size 10 at 2023-12-03 22:58:19 UTC
9361 23:00:32.135299 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9362 23:00:32.142318 ELOG: Event(A0) added with size 9 at 2023-12-03 22:58:20 UTC
9363 23:00:32.145451 elog_add_boot_reason: Logged dev mode boot
9364 23:00:32.148768 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9365 23:00:32.151864 Finalize devices...
9366 23:00:32.152304 Devices finalized
9367 23:00:32.158726 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9368 23:00:32.162102 Writing coreboot table at 0xffe64000
9369 23:00:32.165086 0. 000000000010a000-0000000000113fff: RAMSTAGE
9370 23:00:32.168560 1. 0000000040000000-00000000400fffff: RAM
9371 23:00:32.172141 2. 0000000040100000-000000004032afff: RAMSTAGE
9372 23:00:32.178492 3. 000000004032b000-00000000545fffff: RAM
9373 23:00:32.182330 4. 0000000054600000-000000005465ffff: BL31
9374 23:00:32.185726 5. 0000000054660000-00000000ffe63fff: RAM
9375 23:00:32.188632 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9376 23:00:32.195356 7. 0000000100000000-000000023fffffff: RAM
9377 23:00:32.195810 Passing 5 GPIOs to payload:
9378 23:00:32.202255 NAME | PORT | POLARITY | VALUE
9379 23:00:32.205484 EC in RW | 0x000000aa | low | undefined
9380 23:00:32.211717 EC interrupt | 0x00000005 | low | undefined
9381 23:00:32.215291 TPM interrupt | 0x000000ab | high | undefined
9382 23:00:32.218313 SD card detect | 0x00000011 | high | undefined
9383 23:00:32.225013 speaker enable | 0x00000093 | high | undefined
9384 23:00:32.228262 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9385 23:00:32.231718 in-header: 03 f9 00 00 02 00 00 00
9386 23:00:32.232223 in-data: 02 00
9387 23:00:32.234945 ADC[4]: Raw value=904357 ID=7
9388 23:00:32.238145 ADC[3]: Raw value=213441 ID=1
9389 23:00:32.238604 RAM Code: 0x71
9390 23:00:32.241414 ADC[6]: Raw value=75701 ID=0
9391 23:00:32.244822 ADC[5]: Raw value=212703 ID=1
9392 23:00:32.245231 SKU Code: 0x1
9393 23:00:32.251201 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9394 23:00:32.255120 coreboot table: 964 bytes.
9395 23:00:32.258037 IMD ROOT 0. 0xfffff000 0x00001000
9396 23:00:32.261263 IMD SMALL 1. 0xffffe000 0x00001000
9397 23:00:32.264493 RO MCACHE 2. 0xffffc000 0x00001104
9398 23:00:32.267715 CONSOLE 3. 0xfff7c000 0x00080000
9399 23:00:32.270946 FMAP 4. 0xfff7b000 0x00000452
9400 23:00:32.274527 TIME STAMP 5. 0xfff7a000 0x00000910
9401 23:00:32.277502 VBOOT WORK 6. 0xfff66000 0x00014000
9402 23:00:32.281210 RAMOOPS 7. 0xffe66000 0x00100000
9403 23:00:32.284147 COREBOOT 8. 0xffe64000 0x00002000
9404 23:00:32.284558 IMD small region:
9405 23:00:32.287759 IMD ROOT 0. 0xffffec00 0x00000400
9406 23:00:32.291274 VPD 1. 0xffffeb80 0x0000006c
9407 23:00:32.294399 MMC STATUS 2. 0xffffeb60 0x00000004
9408 23:00:32.301041 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9409 23:00:32.304386 Probing TPM: done!
9410 23:00:32.307295 Connected to device vid:did:rid of 1ae0:0028:00
9411 23:00:32.317343 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9412 23:00:32.320714 Initialized TPM device CR50 revision 0
9413 23:00:32.324957 Checking cr50 for pending updates
9414 23:00:32.328260 Reading cr50 TPM mode
9415 23:00:32.336944 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9416 23:00:32.343072 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9417 23:00:32.383773 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9418 23:00:32.387172 Checking segment from ROM address 0x40100000
9419 23:00:32.390102 Checking segment from ROM address 0x4010001c
9420 23:00:32.396682 Loading segment from ROM address 0x40100000
9421 23:00:32.397294 code (compression=0)
9422 23:00:32.403677 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9423 23:00:32.413425 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9424 23:00:32.414031 it's not compressed!
9425 23:00:32.420121 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9426 23:00:32.423669 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9427 23:00:32.443866 Loading segment from ROM address 0x4010001c
9428 23:00:32.444401 Entry Point 0x80000000
9429 23:00:32.446961 Loaded segments
9430 23:00:32.450639 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9431 23:00:32.457653 Jumping to boot code at 0x80000000(0xffe64000)
9432 23:00:32.463951 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9433 23:00:32.470863 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9434 23:00:32.478496 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9435 23:00:32.481624 Checking segment from ROM address 0x40100000
9436 23:00:32.484922 Checking segment from ROM address 0x4010001c
9437 23:00:32.491561 Loading segment from ROM address 0x40100000
9438 23:00:32.492081 code (compression=1)
9439 23:00:32.498142 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9440 23:00:32.508611 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9441 23:00:32.509191 using LZMA
9442 23:00:32.516593 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9443 23:00:32.523521 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9444 23:00:32.527024 Loading segment from ROM address 0x4010001c
9445 23:00:32.527605 Entry Point 0x54601000
9446 23:00:32.530035 Loaded segments
9447 23:00:32.533201 NOTICE: MT8192 bl31_setup
9448 23:00:32.539962 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9449 23:00:32.543571 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9450 23:00:32.546718 WARNING: region 0:
9451 23:00:32.550278 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9452 23:00:32.550699 WARNING: region 1:
9453 23:00:32.556937 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9454 23:00:32.560740 WARNING: region 2:
9455 23:00:32.563827 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9456 23:00:32.567288 WARNING: region 3:
9457 23:00:32.570141 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9458 23:00:32.573322 WARNING: region 4:
9459 23:00:32.580071 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9460 23:00:32.580483 WARNING: region 5:
9461 23:00:32.583757 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9462 23:00:32.586762 WARNING: region 6:
9463 23:00:32.590553 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9464 23:00:32.593498 WARNING: region 7:
9465 23:00:32.596956 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9466 23:00:32.603880 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9467 23:00:32.606865 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9468 23:00:32.610494 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9469 23:00:32.617362 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9470 23:00:32.620256 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9471 23:00:32.623931 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9472 23:00:32.630776 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9473 23:00:32.634030 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9474 23:00:32.637343 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9475 23:00:32.643851 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9476 23:00:32.647413 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9477 23:00:32.650893 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9478 23:00:32.657279 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9479 23:00:32.660635 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9480 23:00:32.667413 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9481 23:00:32.670707 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9482 23:00:32.674207 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9483 23:00:32.680979 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9484 23:00:32.683939 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9485 23:00:32.687399 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9486 23:00:32.694074 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9487 23:00:32.697409 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9488 23:00:32.703713 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9489 23:00:32.707344 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9490 23:00:32.710495 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9491 23:00:32.716934 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9492 23:00:32.720724 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9493 23:00:32.727398 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9494 23:00:32.730690 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9495 23:00:32.733904 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9496 23:00:32.740763 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9497 23:00:32.743993 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9498 23:00:32.747582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9499 23:00:32.753879 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9500 23:00:32.757435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9501 23:00:32.760516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9502 23:00:32.763858 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9503 23:00:32.770880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9504 23:00:32.773833 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9505 23:00:32.777230 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9506 23:00:32.780744 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9507 23:00:32.787340 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9508 23:00:32.790722 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9509 23:00:32.793994 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9510 23:00:32.797754 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9511 23:00:32.804052 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9512 23:00:32.807466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9513 23:00:32.811032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9514 23:00:32.817896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9515 23:00:32.820732 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9516 23:00:32.824116 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9517 23:00:32.830999 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9518 23:00:32.834645 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9519 23:00:32.841380 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9520 23:00:32.844080 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9521 23:00:32.847466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9522 23:00:32.853914 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9523 23:00:32.857544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9524 23:00:32.864290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9525 23:00:32.867537 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9526 23:00:32.874348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9527 23:00:32.877978 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9528 23:00:32.884678 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9529 23:00:32.887649 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9530 23:00:32.891222 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9531 23:00:32.897665 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9532 23:00:32.901174 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9533 23:00:32.907681 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9534 23:00:32.911137 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9535 23:00:32.918144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9536 23:00:32.921480 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9537 23:00:32.923997 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9538 23:00:32.931230 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9539 23:00:32.934237 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9540 23:00:32.940964 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9541 23:00:32.944144 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9542 23:00:32.950896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9543 23:00:32.954281 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9544 23:00:32.958023 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9545 23:00:32.964254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9546 23:00:32.967636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9547 23:00:32.974206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9548 23:00:32.977665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9549 23:00:32.984474 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9550 23:00:32.987839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9551 23:00:32.991412 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9552 23:00:32.998100 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9553 23:00:33.001485 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9554 23:00:33.007892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9555 23:00:33.011329 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9556 23:00:33.014248 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9557 23:00:33.020892 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9558 23:00:33.024421 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9559 23:00:33.031274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9560 23:00:33.034351 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9561 23:00:33.041161 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9562 23:00:33.044609 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9563 23:00:33.047793 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9564 23:00:33.050779 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9565 23:00:33.057888 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9566 23:00:33.061112 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9567 23:00:33.064040 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9568 23:00:33.070899 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9569 23:00:33.074304 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9570 23:00:33.081144 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9571 23:00:33.084034 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9572 23:00:33.087422 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9573 23:00:33.094583 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9574 23:00:33.097494 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9575 23:00:33.104180 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9576 23:00:33.107443 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9577 23:00:33.110842 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9578 23:00:33.117557 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9579 23:00:33.121239 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9580 23:00:33.127571 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9581 23:00:33.131051 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9582 23:00:33.134453 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9583 23:00:33.138142 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9584 23:00:33.144796 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9585 23:00:33.147851 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9586 23:00:33.151457 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9587 23:00:33.155291 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9588 23:00:33.161860 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9589 23:00:33.164717 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9590 23:00:33.168459 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9591 23:00:33.174889 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9592 23:00:33.178960 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9593 23:00:33.181967 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9594 23:00:33.188200 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9595 23:00:33.191750 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9596 23:00:33.198538 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9597 23:00:33.201772 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9598 23:00:33.204901 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9599 23:00:33.211754 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9600 23:00:33.214806 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9601 23:00:33.218566 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9602 23:00:33.224874 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9603 23:00:33.228407 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9604 23:00:33.235045 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9605 23:00:33.238455 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9606 23:00:33.241563 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9607 23:00:33.248620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9608 23:00:33.252017 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9609 23:00:33.258430 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9610 23:00:33.261796 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9611 23:00:33.265015 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9612 23:00:33.271664 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9613 23:00:33.275173 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9614 23:00:33.278408 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9615 23:00:33.284909 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9616 23:00:33.288243 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9617 23:00:33.295061 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9618 23:00:33.298579 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9619 23:00:33.301652 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9620 23:00:33.308609 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9621 23:00:33.311676 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9622 23:00:33.318707 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9623 23:00:33.321981 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9624 23:00:33.325087 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9625 23:00:33.332014 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9626 23:00:33.335105 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9627 23:00:33.338726 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9628 23:00:33.345297 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9629 23:00:33.348639 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9630 23:00:33.355375 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9631 23:00:33.358296 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9632 23:00:33.361560 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9633 23:00:33.368492 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9634 23:00:33.371778 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9635 23:00:33.378220 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9636 23:00:33.381500 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9637 23:00:33.384950 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9638 23:00:33.392001 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9639 23:00:33.395008 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9640 23:00:33.401339 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9641 23:00:33.404660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9642 23:00:33.408144 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9643 23:00:33.414892 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9644 23:00:33.418041 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9645 23:00:33.421500 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9646 23:00:33.427744 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9647 23:00:33.431160 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9648 23:00:33.437845 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9649 23:00:33.440990 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9650 23:00:33.447629 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9651 23:00:33.451252 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9652 23:00:33.454463 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9653 23:00:33.461360 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9654 23:00:33.464164 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9655 23:00:33.471024 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9656 23:00:33.474049 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9657 23:00:33.478022 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9658 23:00:33.483963 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9659 23:00:33.487244 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9660 23:00:33.494041 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9661 23:00:33.497458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9662 23:00:33.501092 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9663 23:00:33.507367 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9664 23:00:33.511110 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9665 23:00:33.517411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9666 23:00:33.521081 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9667 23:00:33.524279 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9668 23:00:33.530880 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9669 23:00:33.534269 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9670 23:00:33.540806 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9671 23:00:33.544076 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9672 23:00:33.550487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9673 23:00:33.554003 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9674 23:00:33.557494 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9675 23:00:33.564150 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9676 23:00:33.567453 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9677 23:00:33.573887 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9678 23:00:33.577188 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9679 23:00:33.583920 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9680 23:00:33.587092 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9681 23:00:33.590163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9682 23:00:33.596617 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9683 23:00:33.600093 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9684 23:00:33.607231 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9685 23:00:33.610146 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9686 23:00:33.616553 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9687 23:00:33.620635 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9688 23:00:33.623617 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9689 23:00:33.629960 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9690 23:00:33.633068 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9691 23:00:33.640211 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9692 23:00:33.643308 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9693 23:00:33.646882 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9694 23:00:33.653207 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9695 23:00:33.656713 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9696 23:00:33.660217 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9697 23:00:33.663250 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9698 23:00:33.669823 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9699 23:00:33.673072 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9700 23:00:33.676248 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9701 23:00:33.683204 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9702 23:00:33.686364 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9703 23:00:33.692911 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9704 23:00:33.696311 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9705 23:00:33.699526 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9706 23:00:33.706237 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9707 23:00:33.709671 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9708 23:00:33.713281 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9709 23:00:33.719578 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9710 23:00:33.722814 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9711 23:00:33.726518 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9712 23:00:33.732552 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9713 23:00:33.736421 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9714 23:00:33.739387 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9715 23:00:33.746199 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9716 23:00:33.749489 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9717 23:00:33.756209 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9718 23:00:33.759508 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9719 23:00:33.763027 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9720 23:00:33.769767 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9721 23:00:33.773145 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9722 23:00:33.775907 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9723 23:00:33.782841 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9724 23:00:33.785927 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9725 23:00:33.789220 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9726 23:00:33.796675 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9727 23:00:33.799117 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9728 23:00:33.805781 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9729 23:00:33.809228 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9730 23:00:33.812777 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9731 23:00:33.819170 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9732 23:00:33.822355 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9733 23:00:33.828743 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9734 23:00:33.832482 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9735 23:00:33.835789 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9736 23:00:33.838751 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9737 23:00:33.842354 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9738 23:00:33.848836 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9739 23:00:33.852292 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9740 23:00:33.855286 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9741 23:00:33.858717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9742 23:00:33.864816 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9743 23:00:33.868146 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9744 23:00:33.871405 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9745 23:00:33.874898 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9746 23:00:33.882100 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9747 23:00:33.885200 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9748 23:00:33.888538 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9749 23:00:33.894873 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9750 23:00:33.898321 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9751 23:00:33.905227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9752 23:00:33.908682 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9753 23:00:33.915085 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9754 23:00:33.918646 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9755 23:00:33.921846 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9756 23:00:33.928592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9757 23:00:33.932250 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9758 23:00:33.938477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9759 23:00:33.942257 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9760 23:00:33.945750 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9761 23:00:33.951582 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9762 23:00:33.954919 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9763 23:00:33.961758 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9764 23:00:33.965124 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9765 23:00:33.968218 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9766 23:00:33.974795 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9767 23:00:33.978135 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9768 23:00:33.984721 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9769 23:00:33.988060 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9770 23:00:33.994868 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9771 23:00:33.998085 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9772 23:00:34.001282 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9773 23:00:34.008101 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9774 23:00:34.011384 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9775 23:00:34.017723 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9776 23:00:34.021005 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9777 23:00:34.024566 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9778 23:00:34.031279 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9779 23:00:34.034261 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9780 23:00:34.040957 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9781 23:00:34.044733 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9782 23:00:34.047597 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9783 23:00:34.054624 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9784 23:00:34.058478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9785 23:00:34.064753 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9786 23:00:34.067844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9787 23:00:34.071146 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9788 23:00:34.078084 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9789 23:00:34.081057 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9790 23:00:34.087845 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9791 23:00:34.091381 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9792 23:00:34.094643 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9793 23:00:34.100953 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9794 23:00:34.104582 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9795 23:00:34.111862 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9796 23:00:34.114496 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9797 23:00:34.117931 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9798 23:00:34.124313 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9799 23:00:34.127756 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9800 23:00:34.134688 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9801 23:00:34.137638 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9802 23:00:34.144561 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9803 23:00:34.147993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9804 23:00:34.151203 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9805 23:00:34.157725 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9806 23:00:34.161135 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9807 23:00:34.167516 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9808 23:00:34.171766 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9809 23:00:34.174770 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9810 23:00:34.180811 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9811 23:00:34.184506 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9812 23:00:34.187729 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9813 23:00:34.194219 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9814 23:00:34.197283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9815 23:00:34.204257 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9816 23:00:34.207670 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9817 23:00:34.214169 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9818 23:00:34.217902 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9819 23:00:34.221423 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9820 23:00:34.227353 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9821 23:00:34.230634 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9822 23:00:34.237327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9823 23:00:34.240780 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9824 23:00:34.247459 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9825 23:00:34.250673 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9826 23:00:34.257506 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9827 23:00:34.260326 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9828 23:00:34.263699 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9829 23:00:34.270734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9830 23:00:34.273852 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9831 23:00:34.280484 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9832 23:00:34.283839 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9833 23:00:34.290830 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9834 23:00:34.293936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9835 23:00:34.296922 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9836 23:00:34.303743 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9837 23:00:34.307535 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9838 23:00:34.313977 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9839 23:00:34.316981 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9840 23:00:34.323471 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9841 23:00:34.326898 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9842 23:00:34.333379 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9843 23:00:34.336808 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9844 23:00:34.340047 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9845 23:00:34.347057 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9846 23:00:34.350084 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9847 23:00:34.356953 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9848 23:00:34.360211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9849 23:00:34.363631 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9850 23:00:34.370591 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9851 23:00:34.373352 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9852 23:00:34.380192 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9853 23:00:34.383370 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9854 23:00:34.390092 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9855 23:00:34.393727 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9856 23:00:34.396983 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9857 23:00:34.403442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9858 23:00:34.406794 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9859 23:00:34.413089 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9860 23:00:34.416595 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9861 23:00:34.422981 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9862 23:00:34.426624 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9863 23:00:34.429981 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9864 23:00:34.437126 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9865 23:00:34.440012 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9866 23:00:34.446850 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9867 23:00:34.450055 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9868 23:00:34.453501 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9869 23:00:34.459661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9870 23:00:34.463194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9871 23:00:34.469434 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9872 23:00:34.472792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9873 23:00:34.479792 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9874 23:00:34.482797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9875 23:00:34.489495 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9876 23:00:34.492748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9877 23:00:34.499195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9878 23:00:34.502755 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9879 23:00:34.509108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9880 23:00:34.512704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9881 23:00:34.519568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9882 23:00:34.522714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9883 23:00:34.529299 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9884 23:00:34.532738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9885 23:00:34.539604 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9886 23:00:34.542833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9887 23:00:34.549483 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9888 23:00:34.552698 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9889 23:00:34.559411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9890 23:00:34.562317 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9891 23:00:34.569287 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9892 23:00:34.572078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9893 23:00:34.579083 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9894 23:00:34.582676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9895 23:00:34.588628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9896 23:00:34.592145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9897 23:00:34.599034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9898 23:00:34.602225 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9899 23:00:34.608759 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9900 23:00:34.612266 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9901 23:00:34.615301 INFO: [APUAPC] vio 0
9902 23:00:34.618704 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9903 23:00:34.625390 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9904 23:00:34.628446 INFO: [APUAPC] D0_APC_0: 0x400510
9905 23:00:34.628858 INFO: [APUAPC] D0_APC_1: 0x0
9906 23:00:34.631819 INFO: [APUAPC] D0_APC_2: 0x1540
9907 23:00:34.635310 INFO: [APUAPC] D0_APC_3: 0x0
9908 23:00:34.638673 INFO: [APUAPC] D1_APC_0: 0xffffffff
9909 23:00:34.642033 INFO: [APUAPC] D1_APC_1: 0xffffffff
9910 23:00:34.645672 INFO: [APUAPC] D1_APC_2: 0x3fffff
9911 23:00:34.649046 INFO: [APUAPC] D1_APC_3: 0x0
9912 23:00:34.652126 INFO: [APUAPC] D2_APC_0: 0xffffffff
9913 23:00:34.655113 INFO: [APUAPC] D2_APC_1: 0xffffffff
9914 23:00:34.658374 INFO: [APUAPC] D2_APC_2: 0x3fffff
9915 23:00:34.661453 INFO: [APUAPC] D2_APC_3: 0x0
9916 23:00:34.664782 INFO: [APUAPC] D3_APC_0: 0xffffffff
9917 23:00:34.668316 INFO: [APUAPC] D3_APC_1: 0xffffffff
9918 23:00:34.671720 INFO: [APUAPC] D3_APC_2: 0x3fffff
9919 23:00:34.675049 INFO: [APUAPC] D3_APC_3: 0x0
9920 23:00:34.678494 INFO: [APUAPC] D4_APC_0: 0xffffffff
9921 23:00:34.681644 INFO: [APUAPC] D4_APC_1: 0xffffffff
9922 23:00:34.684915 INFO: [APUAPC] D4_APC_2: 0x3fffff
9923 23:00:34.688268 INFO: [APUAPC] D4_APC_3: 0x0
9924 23:00:34.691679 INFO: [APUAPC] D5_APC_0: 0xffffffff
9925 23:00:34.694941 INFO: [APUAPC] D5_APC_1: 0xffffffff
9926 23:00:34.698535 INFO: [APUAPC] D5_APC_2: 0x3fffff
9927 23:00:34.701520 INFO: [APUAPC] D5_APC_3: 0x0
9928 23:00:34.704914 INFO: [APUAPC] D6_APC_0: 0xffffffff
9929 23:00:34.708070 INFO: [APUAPC] D6_APC_1: 0xffffffff
9930 23:00:34.711869 INFO: [APUAPC] D6_APC_2: 0x3fffff
9931 23:00:34.714970 INFO: [APUAPC] D6_APC_3: 0x0
9932 23:00:34.717980 INFO: [APUAPC] D7_APC_0: 0xffffffff
9933 23:00:34.721741 INFO: [APUAPC] D7_APC_1: 0xffffffff
9934 23:00:34.725052 INFO: [APUAPC] D7_APC_2: 0x3fffff
9935 23:00:34.728043 INFO: [APUAPC] D7_APC_3: 0x0
9936 23:00:34.731759 INFO: [APUAPC] D8_APC_0: 0xffffffff
9937 23:00:34.735247 INFO: [APUAPC] D8_APC_1: 0xffffffff
9938 23:00:34.737913 INFO: [APUAPC] D8_APC_2: 0x3fffff
9939 23:00:34.741824 INFO: [APUAPC] D8_APC_3: 0x0
9940 23:00:34.744436 INFO: [APUAPC] D9_APC_0: 0xffffffff
9941 23:00:34.747978 INFO: [APUAPC] D9_APC_1: 0xffffffff
9942 23:00:34.751455 INFO: [APUAPC] D9_APC_2: 0x3fffff
9943 23:00:34.751916 INFO: [APUAPC] D9_APC_3: 0x0
9944 23:00:34.757901 INFO: [APUAPC] D10_APC_0: 0xffffffff
9945 23:00:34.761194 INFO: [APUAPC] D10_APC_1: 0xffffffff
9946 23:00:34.764645 INFO: [APUAPC] D10_APC_2: 0x3fffff
9947 23:00:34.767545 INFO: [APUAPC] D10_APC_3: 0x0
9948 23:00:34.771302 INFO: [APUAPC] D11_APC_0: 0xffffffff
9949 23:00:34.774231 INFO: [APUAPC] D11_APC_1: 0xffffffff
9950 23:00:34.777432 INFO: [APUAPC] D11_APC_2: 0x3fffff
9951 23:00:34.780812 INFO: [APUAPC] D11_APC_3: 0x0
9952 23:00:34.783969 INFO: [APUAPC] D12_APC_0: 0xffffffff
9953 23:00:34.787624 INFO: [APUAPC] D12_APC_1: 0xffffffff
9954 23:00:34.791435 INFO: [APUAPC] D12_APC_2: 0x3fffff
9955 23:00:34.794685 INFO: [APUAPC] D12_APC_3: 0x0
9956 23:00:34.797709 INFO: [APUAPC] D13_APC_0: 0xffffffff
9957 23:00:34.800763 INFO: [APUAPC] D13_APC_1: 0xffffffff
9958 23:00:34.804228 INFO: [APUAPC] D13_APC_2: 0x3fffff
9959 23:00:34.807404 INFO: [APUAPC] D13_APC_3: 0x0
9960 23:00:34.810628 INFO: [APUAPC] D14_APC_0: 0xffffffff
9961 23:00:34.814394 INFO: [APUAPC] D14_APC_1: 0xffffffff
9962 23:00:34.817683 INFO: [APUAPC] D14_APC_2: 0x3fffff
9963 23:00:34.820817 INFO: [APUAPC] D14_APC_3: 0x0
9964 23:00:34.824099 INFO: [APUAPC] D15_APC_0: 0xffffffff
9965 23:00:34.827238 INFO: [APUAPC] D15_APC_1: 0xffffffff
9966 23:00:34.830775 INFO: [APUAPC] D15_APC_2: 0x3fffff
9967 23:00:34.833967 INFO: [APUAPC] D15_APC_3: 0x0
9968 23:00:34.837169 INFO: [APUAPC] APC_CON: 0x4
9969 23:00:34.837621 INFO: [NOCDAPC] D0_APC_0: 0x0
9970 23:00:34.840576 INFO: [NOCDAPC] D0_APC_1: 0x0
9971 23:00:34.843765 INFO: [NOCDAPC] D1_APC_0: 0x0
9972 23:00:34.847245 INFO: [NOCDAPC] D1_APC_1: 0xfff
9973 23:00:34.850572 INFO: [NOCDAPC] D2_APC_0: 0x0
9974 23:00:34.853562 INFO: [NOCDAPC] D2_APC_1: 0xfff
9975 23:00:34.857011 INFO: [NOCDAPC] D3_APC_0: 0x0
9976 23:00:34.860187 INFO: [NOCDAPC] D3_APC_1: 0xfff
9977 23:00:34.863671 INFO: [NOCDAPC] D4_APC_0: 0x0
9978 23:00:34.866863 INFO: [NOCDAPC] D4_APC_1: 0xfff
9979 23:00:34.870055 INFO: [NOCDAPC] D5_APC_0: 0x0
9980 23:00:34.870470 INFO: [NOCDAPC] D5_APC_1: 0xfff
9981 23:00:34.873324 INFO: [NOCDAPC] D6_APC_0: 0x0
9982 23:00:34.876815 INFO: [NOCDAPC] D6_APC_1: 0xfff
9983 23:00:34.880290 INFO: [NOCDAPC] D7_APC_0: 0x0
9984 23:00:34.883420 INFO: [NOCDAPC] D7_APC_1: 0xfff
9985 23:00:34.886782 INFO: [NOCDAPC] D8_APC_0: 0x0
9986 23:00:34.889947 INFO: [NOCDAPC] D8_APC_1: 0xfff
9987 23:00:34.893342 INFO: [NOCDAPC] D9_APC_0: 0x0
9988 23:00:34.896540 INFO: [NOCDAPC] D9_APC_1: 0xfff
9989 23:00:34.899800 INFO: [NOCDAPC] D10_APC_0: 0x0
9990 23:00:34.902977 INFO: [NOCDAPC] D10_APC_1: 0xfff
9991 23:00:34.906354 INFO: [NOCDAPC] D11_APC_0: 0x0
9992 23:00:34.909639 INFO: [NOCDAPC] D11_APC_1: 0xfff
9993 23:00:34.910057 INFO: [NOCDAPC] D12_APC_0: 0x0
9994 23:00:34.913108 INFO: [NOCDAPC] D12_APC_1: 0xfff
9995 23:00:34.916800 INFO: [NOCDAPC] D13_APC_0: 0x0
9996 23:00:34.919519 INFO: [NOCDAPC] D13_APC_1: 0xfff
9997 23:00:34.923080 INFO: [NOCDAPC] D14_APC_0: 0x0
9998 23:00:34.926667 INFO: [NOCDAPC] D14_APC_1: 0xfff
9999 23:00:34.929930 INFO: [NOCDAPC] D15_APC_0: 0x0
10000 23:00:34.932980 INFO: [NOCDAPC] D15_APC_1: 0xfff
10001 23:00:34.936342 INFO: [NOCDAPC] APC_CON: 0x4
10002 23:00:34.939572 INFO: [APUAPC] set_apusys_apc done
10003 23:00:34.943209 INFO: [DEVAPC] devapc_init done
10004 23:00:34.946625 INFO: GICv3 without legacy support detected.
10005 23:00:34.949633 INFO: ARM GICv3 driver initialized in EL3
10006 23:00:34.953222 INFO: Maximum SPI INTID supported: 639
10007 23:00:34.959715 INFO: BL31: Initializing runtime services
10008 23:00:34.963137 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10009 23:00:34.966629 INFO: SPM: enable CPC mode
10010 23:00:34.973116 INFO: mcdi ready for mcusys-off-idle and system suspend
10011 23:00:34.976484 INFO: BL31: Preparing for EL3 exit to normal world
10012 23:00:34.979467 INFO: Entry point address = 0x80000000
10013 23:00:34.983303 INFO: SPSR = 0x8
10014 23:00:34.988231
10015 23:00:34.988644
10016 23:00:34.988973
10017 23:00:34.992014 Starting depthcharge on Spherion...
10018 23:00:34.992426
10019 23:00:34.992755 Wipe memory regions:
10020 23:00:34.993059
10021 23:00:34.995731 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10022 23:00:34.996258 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10023 23:00:34.996673 Setting prompt string to ['asurada:']
10024 23:00:34.997069 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10025 23:00:34.997788 [0x00000040000000, 0x00000054600000)
10026 23:00:35.117077
10027 23:00:35.117667 [0x00000054660000, 0x00000080000000)
10028 23:00:35.377787
10029 23:00:35.378259 [0x000000821a7280, 0x000000ffe64000)
10030 23:00:36.122311
10031 23:00:36.122812 [0x00000100000000, 0x00000240000000)
10032 23:00:38.012599
10033 23:00:38.015465 Initializing XHCI USB controller at 0x11200000.
10034 23:00:39.053385
10035 23:00:39.056290 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10036 23:00:39.056782
10037 23:00:39.057176
10038 23:00:39.057501
10039 23:00:39.058412 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10041 23:00:39.159660 asurada: tftpboot 192.168.201.1 12172435/tftp-deploy-us5g40g6/kernel/image.itb 12172435/tftp-deploy-us5g40g6/kernel/cmdline
10042 23:00:39.160299 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10043 23:00:39.160726 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10044 23:00:39.164826 tftpboot 192.168.201.1 12172435/tftp-deploy-us5g40g6/kernel/image.ittp-deploy-us5g40g6/kernel/cmdline
10045 23:00:39.165272
10046 23:00:39.165695 Waiting for link
10047 23:00:39.325385
10048 23:00:39.325534 R8152: Initializing
10049 23:00:39.325609
10050 23:00:39.328799 Version 9 (ocp_data = 6010)
10051 23:00:39.328870
10052 23:00:39.331581 R8152: Done initializing
10053 23:00:39.331654
10054 23:00:39.331715 Adding net device
10055 23:00:41.275132
10056 23:00:41.275762 done.
10057 23:00:41.276230
10058 23:00:41.276600 MAC: 00:e0:4c:78:7a:aa
10059 23:00:41.276944
10060 23:00:41.278311 Sending DHCP discover... done.
10061 23:00:41.278733
10062 23:00:41.281653 Waiting for reply... done.
10063 23:00:41.282091
10064 23:00:41.284764 Sending DHCP request... done.
10065 23:00:41.285289
10066 23:00:41.288464 Waiting for reply... done.
10067 23:00:41.288959
10068 23:00:41.289300 My ip is 192.168.201.12
10069 23:00:41.289759
10070 23:00:41.291485 The DHCP server ip is 192.168.201.1
10071 23:00:41.291907
10072 23:00:41.294905 TFTP server IP predefined by user: 192.168.201.1
10073 23:00:41.298400
10074 23:00:41.305104 Bootfile predefined by user: 12172435/tftp-deploy-us5g40g6/kernel/image.itb
10075 23:00:41.305656
10076 23:00:41.306040 Sending tftp read request... done.
10077 23:00:41.306411
10078 23:00:41.313716 Waiting for the transfer...
10079 23:00:41.314160
10080 23:00:41.583899 00000000 ################################################################
10081 23:00:41.584056
10082 23:00:41.837406 00080000 ################################################################
10083 23:00:41.837565
10084 23:00:42.103163 00100000 ################################################################
10085 23:00:42.103329
10086 23:00:42.379986 00180000 ################################################################
10087 23:00:42.380146
10088 23:00:42.652177 00200000 ################################################################
10089 23:00:42.652321
10090 23:00:42.940912 00280000 ################################################################
10091 23:00:42.941136
10092 23:00:43.336849 00300000 ################################################################
10093 23:00:43.337333
10094 23:00:43.764435 00380000 ################################################################
10095 23:00:43.764940
10096 23:00:44.098316 00400000 ################################################################
10097 23:00:44.098462
10098 23:00:44.400344 00480000 ################################################################
10099 23:00:44.400489
10100 23:00:44.684310 00500000 ################################################################
10101 23:00:44.684470
10102 23:00:44.966852 00580000 ################################################################
10103 23:00:44.966993
10104 23:00:45.259348 00600000 ################################################################
10105 23:00:45.259499
10106 23:00:45.562853 00680000 ################################################################
10107 23:00:45.562999
10108 23:00:45.864431 00700000 ################################################################
10109 23:00:45.864581
10110 23:00:46.160045 00780000 ################################################################
10111 23:00:46.160184
10112 23:00:46.444573 00800000 ################################################################
10113 23:00:46.444725
10114 23:00:46.736287 00880000 ################################################################
10115 23:00:46.736435
10116 23:00:47.022169 00900000 ################################################################
10117 23:00:47.022314
10118 23:00:47.308379 00980000 ################################################################
10119 23:00:47.308525
10120 23:00:47.583955 00a00000 ################################################################
10121 23:00:47.584107
10122 23:00:47.877743 00a80000 ################################################################
10123 23:00:47.877900
10124 23:00:48.173790 00b00000 ################################################################
10125 23:00:48.173938
10126 23:00:48.454816 00b80000 ################################################################
10127 23:00:48.454970
10128 23:00:48.746962 00c00000 ################################################################
10129 23:00:48.747113
10130 23:00:49.042654 00c80000 ################################################################
10131 23:00:49.042802
10132 23:00:49.321398 00d00000 ################################################################
10133 23:00:49.321580
10134 23:00:49.592094 00d80000 ################################################################
10135 23:00:49.592240
10136 23:00:49.866812 00e00000 ################################################################
10137 23:00:49.866954
10138 23:00:50.133720 00e80000 ################################################################
10139 23:00:50.133868
10140 23:00:50.399427 00f00000 ################################################################
10141 23:00:50.399573
10142 23:00:50.689692 00f80000 ################################################################
10143 23:00:50.689837
10144 23:00:50.985370 01000000 ################################################################
10145 23:00:50.985517
10146 23:00:51.277820 01080000 ################################################################
10147 23:00:51.277967
10148 23:00:51.559603 01100000 ################################################################
10149 23:00:51.559750
10150 23:00:51.838810 01180000 ################################################################
10151 23:00:51.838960
10152 23:00:52.138269 01200000 ################################################################
10153 23:00:52.138419
10154 23:00:52.424045 01280000 ################################################################
10155 23:00:52.424201
10156 23:00:52.695675 01300000 ################################################################
10157 23:00:52.695826
10158 23:00:52.958574 01380000 ################################################################
10159 23:00:52.958726
10160 23:00:53.238417 01400000 ################################################################
10161 23:00:53.238566
10162 23:00:53.503251 01480000 ################################################################
10163 23:00:53.503406
10164 23:00:53.777913 01500000 ################################################################
10165 23:00:53.778091
10166 23:00:54.069992 01580000 ################################################################
10167 23:00:54.070139
10168 23:00:54.369288 01600000 ################################################################
10169 23:00:54.369439
10170 23:00:54.664211 01680000 ################################################################
10171 23:00:54.664359
10172 23:00:54.960897 01700000 ################################################################
10173 23:00:54.961047
10174 23:00:55.257062 01780000 ################################################################
10175 23:00:55.257213
10176 23:00:55.547170 01800000 ################################################################
10177 23:00:55.547323
10178 23:00:55.843956 01880000 ################################################################
10179 23:00:55.844114
10180 23:00:56.135832 01900000 ################################################################
10181 23:00:56.135983
10182 23:00:56.431206 01980000 ################################################################
10183 23:00:56.431357
10184 23:00:56.725058 01a00000 ################################################################
10185 23:00:56.725212
10186 23:00:57.004450 01a80000 ################################################################
10187 23:00:57.004604
10188 23:00:57.261428 01b00000 ################################################################
10189 23:00:57.261609
10190 23:00:57.516977 01b80000 ################################################################
10191 23:00:57.517182
10192 23:00:57.790461 01c00000 ################################################################
10193 23:00:57.790616
10194 23:00:58.093583 01c80000 ################################################################
10195 23:00:58.093756
10196 23:00:58.396269 01d00000 ################################################################
10197 23:00:58.396422
10198 23:00:58.686734 01d80000 ################################################################
10199 23:00:58.686907
10200 23:00:58.980392 01e00000 ################################################################
10201 23:00:58.980539
10202 23:00:59.273223 01e80000 ################################################################ done.
10203 23:00:59.273371
10204 23:00:59.276218 The bootfile was 32500950 bytes long.
10205 23:00:59.276301
10206 23:00:59.279541 Sending tftp read request... done.
10207 23:00:59.279626
10208 23:00:59.282901 Waiting for the transfer...
10209 23:00:59.283015
10210 23:00:59.283108 00000000 # done.
10211 23:00:59.283198
10212 23:00:59.292830 Command line loaded dynamically from TFTP file: 12172435/tftp-deploy-us5g40g6/kernel/cmdline
10213 23:00:59.292922
10214 23:00:59.306165 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10215 23:00:59.306265
10216 23:00:59.306329 Loading FIT.
10217 23:00:59.306389
10218 23:00:59.309608 Image ramdisk-1 has 21402291 bytes.
10219 23:00:59.309706
10220 23:00:59.312920 Image fdt-1 has 47278 bytes.
10221 23:00:59.313001
10222 23:00:59.316400 Image kernel-1 has 11049348 bytes.
10223 23:00:59.316481
10224 23:00:59.326015 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10225 23:00:59.326110
10226 23:00:59.342422 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10227 23:00:59.342541
10228 23:00:59.349469 Choosing best match conf-1 for compat google,spherion-rev2.
10229 23:00:59.349559
10230 23:00:59.357319 Connected to device vid:did:rid of 1ae0:0028:00
10231 23:00:59.365260
10232 23:00:59.368390 tpm_get_response: command 0x17b, return code 0x0
10233 23:00:59.368474
10234 23:00:59.371268 ec_init: CrosEC protocol v3 supported (256, 248)
10235 23:00:59.375990
10236 23:00:59.378795 tpm_cleanup: add release locality here.
10237 23:00:59.378904
10238 23:00:59.378995 Shutting down all USB controllers.
10239 23:00:59.382456
10240 23:00:59.382566 Removing current net device
10241 23:00:59.382640
10242 23:00:59.388889 Exiting depthcharge with code 4 at timestamp: 53652306
10243 23:00:59.388975
10244 23:00:59.392382 LZMA decompressing kernel-1 to 0x821a6718
10245 23:00:59.392465
10246 23:00:59.395338 LZMA decompressing kernel-1 to 0x40000000
10247 23:01:00.783932
10248 23:01:00.784089 jumping to kernel
10249 23:01:00.784551 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
10250 23:01:00.784652 start: 2.2.5 auto-login-action (timeout 00:03:59) [common]
10251 23:01:00.784747 Setting prompt string to ['Linux version [0-9]']
10252 23:01:00.784816 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10253 23:01:00.784884 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10254 23:01:00.865650
10255 23:01:00.868748 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10256 23:01:00.872044 start: 2.2.5.1 login-action (timeout 00:03:59) [common]
10257 23:01:00.872139 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10258 23:01:00.872239 Setting prompt string to []
10259 23:01:00.872317 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10260 23:01:00.872392 Using line separator: #'\n'#
10261 23:01:00.872450 No login prompt set.
10262 23:01:00.872509 Parsing kernel messages
10263 23:01:00.872562 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10264 23:01:00.872658 [login-action] Waiting for messages, (timeout 00:03:59)
10265 23:01:00.891927 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10266 23:01:00.895787 [ 0.000000] random: crng init done
10267 23:01:00.902182 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10268 23:01:00.905506 [ 0.000000] efi: UEFI not found.
10269 23:01:00.912341 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10270 23:01:00.919181 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10271 23:01:00.928554 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10272 23:01:00.938360 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10273 23:01:00.944934 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10274 23:01:00.951788 [ 0.000000] printk: bootconsole [mtk8250] enabled
10275 23:01:00.958322 [ 0.000000] NUMA: No NUMA configuration found
10276 23:01:00.964681 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10277 23:01:00.967900 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10278 23:01:00.971601 [ 0.000000] Zone ranges:
10279 23:01:00.977832 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10280 23:01:00.981386 [ 0.000000] DMA32 empty
10281 23:01:00.987971 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10282 23:01:00.991044 [ 0.000000] Movable zone start for each node
10283 23:01:00.994878 [ 0.000000] Early memory node ranges
10284 23:01:01.000969 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10285 23:01:01.007468 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10286 23:01:01.014410 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10287 23:01:01.021108 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10288 23:01:01.027538 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10289 23:01:01.034452 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10290 23:01:01.090223 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10291 23:01:01.096655 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10292 23:01:01.103152 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10293 23:01:01.106456 [ 0.000000] psci: probing for conduit method from DT.
10294 23:01:01.113189 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10295 23:01:01.116519 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10296 23:01:01.123176 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10297 23:01:01.126160 [ 0.000000] psci: SMC Calling Convention v1.2
10298 23:01:01.133292 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10299 23:01:01.136185 [ 0.000000] Detected VIPT I-cache on CPU0
10300 23:01:01.143097 [ 0.000000] CPU features: detected: GIC system register CPU interface
10301 23:01:01.150046 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10302 23:01:01.156376 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10303 23:01:01.163105 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10304 23:01:01.169758 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10305 23:01:01.179844 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10306 23:01:01.182785 [ 0.000000] alternatives: applying boot alternatives
10307 23:01:01.189722 [ 0.000000] Fallback order for Node 0: 0
10308 23:01:01.195872 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10309 23:01:01.199250 [ 0.000000] Policy zone: Normal
10310 23:01:01.212525 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10311 23:01:01.222034 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10312 23:01:01.233505 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10313 23:01:01.243261 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10314 23:01:01.250613 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10315 23:01:01.253008 <6>[ 0.000000] software IO TLB: area num 8.
10316 23:01:01.309246 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10317 23:01:01.459173 <6>[ 0.000000] Memory: 7948656K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 404112K reserved, 32768K cma-reserved)
10318 23:01:01.465570 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10319 23:01:01.472158 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10320 23:01:01.475663 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10321 23:01:01.482040 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10322 23:01:01.488948 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10323 23:01:01.492137 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10324 23:01:01.502187 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10325 23:01:01.508811 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10326 23:01:01.512241 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10327 23:01:01.519875 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10328 23:01:01.523398 <6>[ 0.000000] GICv3: 608 SPIs implemented
10329 23:01:01.529807 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10330 23:01:01.533106 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10331 23:01:01.539833 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10332 23:01:01.546243 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10333 23:01:01.556509 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10334 23:01:01.569424 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10335 23:01:01.575883 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10336 23:01:01.585678 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10337 23:01:01.598797 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10338 23:01:01.605523 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10339 23:01:01.612416 <6>[ 0.009189] Console: colour dummy device 80x25
10340 23:01:01.622289 <6>[ 0.013935] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10341 23:01:01.625439 <6>[ 0.024378] pid_max: default: 32768 minimum: 301
10342 23:01:01.632106 <6>[ 0.029278] LSM: Security Framework initializing
10343 23:01:01.638336 <6>[ 0.034216] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10344 23:01:01.649113 <6>[ 0.042079] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10345 23:01:01.655393 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10346 23:01:01.661725 <6>[ 0.058932] cblist_init_generic: Setting shift to 3 and lim to 1.
10347 23:01:01.671609 <6>[ 0.065270] cblist_init_generic: Setting adjustable number of callback queues.
10348 23:01:01.678501 <6>[ 0.072743] cblist_init_generic: Setting shift to 3 and lim to 1.
10349 23:01:01.681497 <6>[ 0.079208] rcu: Hierarchical SRCU implementation.
10350 23:01:01.688198 <6>[ 0.079210] rcu: Max phase no-delay instances is 1000.
10351 23:01:01.694879 <6>[ 0.079233] printk: bootconsole [mtk8250] printing thread started
10352 23:01:01.701581 <6>[ 0.097573] EFI services will not be available.
10353 23:01:01.704882 <6>[ 0.097770] smp: Bringing up secondary CPUs ...
10354 23:01:01.708396 <6>[ 0.098084] Detected VIPT I-cache on CPU1
10355 23:01:01.718271 <6>[ 0.098152] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10356 23:01:01.724692 <6>[ 0.098184] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10357 23:01:01.733914 <6>[ 0.126020] Detected VIPT I-cache on CPU2
10358 23:01:01.740343 <6>[ 0.126070] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10359 23:01:01.747305 <6>[ 0.126088] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10360 23:01:01.753866 <6>[ 0.126345] Detected VIPT I-cache on CPU3
10361 23:01:01.760559 <6>[ 0.126392] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10362 23:01:01.766956 <6>[ 0.126406] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10363 23:01:01.770440 <6>[ 0.126716] CPU features: detected: Spectre-v4
10364 23:01:01.776925 <6>[ 0.126721] CPU features: detected: Spectre-BHB
10365 23:01:01.780069 <6>[ 0.126726] Detected PIPT I-cache on CPU4
10366 23:01:01.787181 <6>[ 0.126783] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10367 23:01:01.793788 <6>[ 0.126800] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10368 23:01:01.800006 <6>[ 0.127088] Detected PIPT I-cache on CPU5
10369 23:01:01.806963 <6>[ 0.127149] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10370 23:01:01.813246 <6>[ 0.127165] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10371 23:01:01.816742 <6>[ 0.127439] Detected PIPT I-cache on CPU6
10372 23:01:01.823417 <6>[ 0.127504] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10373 23:01:01.830013 <6>[ 0.127520] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10374 23:01:01.836798 <6>[ 0.127809] Detected PIPT I-cache on CPU7
10375 23:01:01.843311 <6>[ 0.127872] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10376 23:01:01.849923 <6>[ 0.127888] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10377 23:01:01.853504 <6>[ 0.127934] smp: Brought up 1 node, 8 CPUs
10378 23:01:01.859803 <6>[ 0.127939] SMP: Total of 8 processors activated.
10379 23:01:01.863052 <6>[ 0.127942] CPU features: detected: 32-bit EL0 Support
10380 23:01:01.872804 <6>[ 0.127943] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10381 23:01:01.879457 <6>[ 0.127946] CPU features: detected: Common not Private translations
10382 23:01:01.886079 <6>[ 0.127948] CPU features: detected: CRC32 instructions
10383 23:01:01.892324 <6>[ 0.127950] CPU features: detected: RCpc load-acquire (LDAPR)
10384 23:01:01.895632 <6>[ 0.127952] CPU features: detected: LSE atomic instructions
10385 23:01:01.902356 <6>[ 0.127953] CPU features: detected: Privileged Access Never
10386 23:01:01.909366 <6>[ 0.127955] CPU features: detected: RAS Extension Support
10387 23:01:01.915643 <6>[ 0.127958] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10388 23:01:01.919161 <6>[ 0.128028] CPU: All CPU(s) started at EL2
10389 23:01:01.925556 <6>[ 0.128030] alternatives: applying system-wide alternatives
10390 23:01:01.929358 <6>[ 0.141119] devtmpfs: initialized
10391 23:01:01.938680 <6>[ 0.147389] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10392 23:01:01.960672 �1�iV�.�Y�iYȨ�_INET protocol family
10393 23:01:01.967871 <6>[ 0.3<64556] printk: console [ttyS0] printing thread started
10394 23:01:01.974235 6>[ <6>[ 0.364580] printk: console [ttyS0] enabled
10395 23:01:01.980327 0.228764] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10396 23:01:01.988532 <6>[ 0.364585] printk: bootconsole [mtk8250] disabled
10397 23:01:01.995345 <6>[ 0.382669] printk: bootconsole [mtk8250] printing thread stopped
10398 23:01:01.998182 <6>[ 0.383904] SuperH (H)SCI(F) driver initialized
10399 23:01:02.004601 <6>[ 0.384391] msm_serial: driver initialized
10400 23:01:02.011326 <6>[ 0.388983] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10401 23:01:02.021262 <6>[ 0.389018] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10402 23:01:02.027887 <6>[ 0.389049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10403 23:01:02.038418 <6>[ 0.389078] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10404 23:01:02.049822 <6>[ 0.389099] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10405 23:01:02.061555 <6>[ 0.389127] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10406 23:01:02.077293 <6>[ 0.389155] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10407 23:01:02.078661 <6>[ 0.389263] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10408 23:01:02.084041 <6>[ 0.389292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10409 23:01:02.091520 <6>[ 0.400226] loop: module loaded
10410 23:01:02.097217 <6>[ 0.402852] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10411 23:01:02.100873 <4>[ 0.419708] mtk-pmic-keys: Failed to locate of_node [id: -1]
10412 23:01:02.104286 <6>[ 0.420641] megasas: 07.719.03.00-rc1
10413 23:01:02.107880 <6>[ 0.432830] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10414 23:01:02.110705 <6>[ 0.432930] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10415 23:01:02.117485 <6>[ 0.445613] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10416 23:01:02.131091 <6>[ 0.501944] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10417 23:01:02.764493 <6>[ 1.161028] Freeing initrd memory: 20896K
10418 23:01:02.776325 <6>[ 1.172466] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10419 23:01:02.782575 <6>[ 1.177112] tun: Universal TUN/TAP device driver, 1.6
10420 23:01:02.786608 <6>[ 1.177863] thunder_xcv, ver 1.0
10421 23:01:02.789488 <6>[ 1.177880] thunder_bgx, ver 1.0
10422 23:01:02.792559 <6>[ 1.177896] nicpf, ver 1.0
10423 23:01:02.799563 <6>[ 1.178937] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10424 23:01:02.806879 <6>[ 1.178940] hns3: Copyright (c) 2017 Huawei Corporation.
10425 23:01:02.809298 <6>[ 1.178964] hclge is initializing
10426 23:01:02.812977 <6>[ 1.178979] e1000: Intel(R) PRO/1000 Network Driver
10427 23:01:02.819660 <6>[ 1.178981] e1000: Copyright (c) 1999-2006 Intel Corporation.
10428 23:01:02.826446 <6>[ 1.179001] e1000e: Intel(R) PRO/1000 Network Driver
10429 23:01:02.830284 <6>[ 1.179002] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10430 23:01:02.837818 <6>[ 1.179018] igb: Intel(R) Gigabit Ethernet Network Driver
10431 23:01:02.844754 <6>[ 1.179020] igb: Copyright (c) 2007-2014 Intel Corporation.
10432 23:01:02.848118 <6>[ 1.179032] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10433 23:01:02.854829 <6>[ 1.179034] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10434 23:01:02.858240 <6>[ 1.179323] sky2: driver version 1.30
10435 23:01:02.865448 <6>[ 1.180375] VFIO - User Level meta-driver version: 0.3
10436 23:01:02.871897 <6>[ 1.183198] usbcore: registered new interface driver usb-storage
10437 23:01:02.878632 <6>[ 1.183374] usbcore: registered new device driver onboard-usb-hub
10438 23:01:02.881919 <6>[ 1.186150] mt6397-rtc mt6359-rtc: registered as rtc0
10439 23:01:02.891953 <6>[ 1.186306] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T22:58:50 UTC (1701644330)
10440 23:01:02.895237 <6>[ 1.186913] i2c_dev: i2c /dev entries driver
10441 23:01:02.905171 <6>[ 1.193967] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10442 23:01:02.908871 <6>[ 1.209944] cpu cpu0: EM: created perf domain
10443 23:01:02.915306 <6>[ 1.210259] cpu cpu4: EM: created perf domain
10444 23:01:02.922002 <6>[ 1.211663] sdhci: Secure Digital Host Controller Interface driver
10445 23:01:02.925069 <6>[ 1.211664] sdhci: Copyright(c) Pierre Ossman
10446 23:01:02.931923 <6>[ 1.212020] Synopsys Designware Multimedia Card Interface Driver
10447 23:01:02.938498 <6>[ 1.212379] sdhci-pltfm: SDHCI platform and OF driver helper
10448 23:01:02.941551 <6>[ 1.216998] mmc0: CQHCI version 5.10
10449 23:01:02.948145 <6>[ 1.223091] ledtrig-cpu: registered to indicate activity on CPUs
10450 23:01:02.954931 <6>[ 1.224753] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10451 23:01:02.958596 <6>[ 1.225472] usbcore: registered new interface driver usbhid
10452 23:01:02.965104 <6>[ 1.225477] usbhid: USB HID core driver
10453 23:01:02.971588 <6>[ 1.225679] spi_master spi0: will run message pump with realtime priority
10454 23:01:02.985218 <6>[ 1.258286] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10455 23:01:02.998148 <6>[ 1.261031] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10456 23:01:03.002102 <6>[ 1.262192] cros-ec-spi spi0.0: Chrome EC device registered
10457 23:01:03.011791 <6>[ 1.280410] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10458 23:01:03.018567 <6>[ 1.281363] NET: Registered PF_PACKET protocol family
10459 23:01:03.021482 <6>[ 1.281461] 9pnet: Installing 9P2000 support
10460 23:01:03.025037 <5>[ 1.281502] Key type dns_resolver registered
10461 23:01:03.032112 <6>[ 1.281930] registered taskstats version 1
10462 23:01:03.035440 <5>[ 1.281944] Loading compiled-in X.509 certificates
10463 23:01:03.045211 <4>[ 1.304995] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10464 23:01:03.055100 <4>[ 1.305179] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10465 23:01:03.061854 <3>[ 1.305190] debugfs: File 'uA_load' in directory '/' already present!
10466 23:01:03.069439 <3>[ 1.305198] debugfs: File 'min_uV' in directory '/' already present!
10467 23:01:03.075251 <3>[ 1.305201] debugfs: File 'max_uV' in directory '/' already present!
10468 23:01:03.085343 <3>[ 1.305204] debugfs: File 'constraint_flags' in directory '/' already present!
10469 23:01:03.092346 <3>[ 1.307568] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10470 23:01:03.098553 <6>[ 1.311474] mmc0: Command Queue Engine enabled
10471 23:01:03.105059 <6>[ 1.311485] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10472 23:01:03.108759 <6>[ 1.312035] mmcblk0: mmc0:0001 DA4128 116 GiB
10473 23:01:03.115103 <6>[ 1.315459] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10474 23:01:03.118649 <6>[ 1.316628] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10475 23:01:03.125338 <6>[ 1.317130] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10476 23:01:03.131575 <6>[ 1.317532] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10477 23:01:03.134842 <6>[ 1.317835] xhci-mtk 11200000.usb: xHCI Host Controller
10478 23:01:03.144945 <6>[ 1.317869] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10479 23:01:03.154556 <6>[ 1.318122] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10480 23:01:03.158500 <6>[ 1.318180] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10481 23:01:03.165008 <6>[ 1.318212] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10482 23:01:03.171187 <6>[ 1.318269] xhci-mtk 11200000.usb: xHCI Host Controller
10483 23:01:03.177920 <6>[ 1.318275] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10484 23:01:03.187926 <6>[ 1.318282] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10485 23:01:03.191133 <6>[ 1.318711] hub 1-0:1.0: USB hub found
10486 23:01:03.194420 <6>[ 1.318739] hub 1-0:1.0: 1 port detected
10487 23:01:03.204520 <6>[ 1.318965] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10488 23:01:03.207747 <6>[ 1.319237] hub 2-0:1.0: USB hub found
10489 23:01:03.210966 <6>[ 1.319256] hub 2-0:1.0: 1 port detected
10490 23:01:03.214346 <6>[ 1.322240] mtk-msdc 11f70000.mmc: Got CD GPIO
10491 23:01:03.224650 <6>[ 1.336351] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10492 23:01:03.231111 <6>[ 1.336360] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10493 23:01:03.240967 <4>[ 1.336507] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10494 23:01:03.247533 <6>[ 1.337142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10495 23:01:03.257358 <6>[ 1.337145] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10496 23:01:03.263911 <6>[ 1.337271] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10497 23:01:03.271058 <6>[ 1.337282] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10498 23:01:03.280978 <6>[ 1.337286] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10499 23:01:03.290582 <6>[ 1.337291] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10500 23:01:03.297255 <6>[ 1.338791] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10501 23:01:03.307043 <6>[ 1.338810] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10502 23:01:03.313880 <6>[ 1.338817] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10503 23:01:03.323643 <6>[ 1.338823] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10504 23:01:03.330235 <6>[ 1.338829] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10505 23:01:03.340228 <6>[ 1.338835] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10506 23:01:03.347036 <6>[ 1.338842] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10507 23:01:03.356766 <6>[ 1.338848] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10508 23:01:03.363304 <6>[ 1.338854] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10509 23:01:03.373284 <6>[ 1.338860] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10510 23:01:03.379673 <6>[ 1.338866] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10511 23:01:03.389558 <6>[ 1.338873] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10512 23:01:03.396577 <6>[ 1.338878] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10513 23:01:03.406210 <6>[ 1.338885] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10514 23:01:03.412958 <6>[ 1.338891] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10515 23:01:03.419702 <6>[ 1.339380] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10516 23:01:03.426009 <6>[ 1.340207] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10517 23:01:03.432800 <6>[ 1.340748] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10518 23:01:03.439564 <6>[ 1.341364] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10519 23:01:03.445892 <6>[ 1.342039] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10520 23:01:03.456130 <6>[ 1.342241] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10521 23:01:03.465957 <6>[ 1.342255] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10522 23:01:03.475868 <6>[ 1.342261] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10523 23:01:03.485828 <6>[ 1.342266] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10524 23:01:03.492191 <6>[ 1.342271] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10525 23:01:03.502104 <6>[ 1.342277] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10526 23:01:03.512630 <6>[ 1.342282] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10527 23:01:03.522110 <6>[ 1.342287] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10528 23:01:03.531638 <6>[ 1.342292] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10529 23:01:03.541463 <6>[ 1.342298] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10530 23:01:03.551393 <6>[ 1.342303] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10531 23:01:03.558075 <6>[ 1.343214] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10532 23:01:03.564480 <6>[ 1.737558] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10533 23:01:03.571149 <6>[ 1.890126] hub 1-1:1.0: USB hub found
10534 23:01:03.575145 <6>[ 1.890523] hub 1-1:1.0: 4 ports detected
10535 23:01:03.578419 <6>[ 1.894237] hub 1-1:1.0: USB hub found
10536 23:01:03.581051 <6>[ 1.894553] hub 1-1:1.0: 4 ports detected
10537 23:01:03.627382 <6>[ 2.017706] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10538 23:01:03.647959 <6>[ 2.043096] hub 2-1:1.0: USB hub found
10539 23:01:03.651309 <6>[ 2.043505] hub 2-1:1.0: 3 ports detected
10540 23:01:03.655149 <6>[ 2.046722] hub 2-1:1.0: USB hub found
10541 23:01:03.658082 <6>[ 2.047120] hub 2-1:1.0: 3 ports detected
10542 23:01:03.815624 <6>[ 2.205691] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10543 23:01:03.936521 <6>[ 2.332592] hub 1-1.4:1.0: USB hub found
10544 23:01:03.939509 <6>[ 2.332898] hub 1-1.4:1.0: 2 ports detected
10545 23:01:03.942785 <6>[ 2.336074] hub 1-1.4:1.0: USB hub found
10546 23:01:03.949549 <6>[ 2.336380] hub 1-1.4:1.0: 2 ports detected
10547 23:01:04.020356 <6>[ 2.409822] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10548 23:01:04.235481 <6>[ 2.625692] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10549 23:01:04.419600 <6>[ 2.809698] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10550 23:01:15.236308 <6>[ 13.634699] ALSA device list:
10551 23:01:15.242663 <6>[ 13.634721] No soundcards found.
10552 23:01:15.245801 <6>[ 13.639138] Freeing unused kernel memory: 8448K
10553 23:01:15.249093 <6>[ 13.639227] Run /init as init process
10554 23:01:15.258706 Starting syslogd: OK
10555 23:01:15.264597 Starting klogd: OK
10556 23:01:15.273973 Running sysctl: OK
10557 23:01:15.284090 Populating /dev using udev: <30>[ 13.680283] udevd[199]: starting version 3.2.9
10558 23:01:15.287294 <27>[ 13.682426] udevd[199]: specified user 'tss' unknown
10559 23:01:15.294040 <27>[ 13.682445] udevd[199]: specified group 'tss' unknown
10560 23:01:15.297691 <30>[ 13.683143] udevd[200]: starting eudev-3.2.9
10561 23:01:15.434864 <6>[ 13.826586] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10562 23:01:15.441150 <6>[ 13.826686] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10563 23:01:15.451511 <6>[ 13.826695] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10564 23:01:15.466608 <6>[ 13.858124] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10565 23:01:15.475448 <6>[ 13.871877] remoteproc remoteproc0: scp is available
10566 23:01:15.482027 <6>[ 13.872070] remoteproc remoteproc0: powering up scp
10567 23:01:15.488698 <6>[ 13.872091] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10568 23:01:15.495401 <6>[ 13.872133] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10569 23:01:15.501824 <3>[ 13.877974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10570 23:01:15.511545 <3>[ 13.877993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10571 23:01:15.518373 <3>[ 13.877997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10572 23:01:15.528320 <3>[ 13.878087] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10573 23:01:15.534968 <3>[ 13.878091] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10574 23:01:15.544889 <3>[ 13.878094] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10575 23:01:15.551653 <3>[ 13.878098] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10576 23:01:15.562080 <3>[ 13.878106] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10577 23:01:15.568947 <3>[ 13.878131] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10578 23:01:15.575881 <3>[ 13.878150] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10579 23:01:15.585949 <3>[ 13.878152] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10580 23:01:15.592728 <3>[ 13.878155] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10581 23:01:15.599799 <3>[ 13.878179] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10582 23:01:15.609342 <3>[ 13.878183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10583 23:01:15.616036 <3>[ 13.878186] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10584 23:01:15.623005 <3>[ 13.878188] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10585 23:01:15.632873 <3>[ 13.878191] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10586 23:01:15.639336 <3>[ 13.878208] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10587 23:01:15.649291 <4>[ 13.923892] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10588 23:01:15.653035 <6>[ 13.924406] usbcore: registered new interface driver r8152
10589 23:01:15.659773 <6>[ 13.924428] mc: Linux media interface: v0.10
10590 23:01:15.665954 <4>[ 13.925717] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10591 23:01:15.672632 <6>[ 13.927025] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10592 23:01:15.682651 <4>[ 13.952155] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10593 23:01:15.685682 <4>[ 13.952155] Fallback method does not support PEC.
10594 23:01:15.692360 <6>[ 13.956525] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10595 23:01:15.699399 <6>[ 13.956562] pci_bus 0000:00: root bus resource [bus 00-ff]
10596 23:01:15.705484 <6>[ 13.956594] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10597 23:01:15.715677 <6>[ 13.956605] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10598 23:01:15.722648 <6>[ 13.956723] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10599 23:01:15.729054 <6>[ 13.956774] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10600 23:01:15.735766 <6>[ 13.956965] pci 0000:00:00.0: supports D1 D2
10601 23:01:15.742240 <6>[ 13.956970] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10602 23:01:15.748864 <6>[ 13.960196] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10603 23:01:15.755856 <6>[ 13.960475] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10604 23:01:15.762118 <6>[ 13.960774] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10605 23:01:15.772444 <6>[ 13.960798] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10606 23:01:15.779261 <6>[ 13.960831] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10607 23:01:15.782155 <6>[ 13.960987] pci 0000:01:00.0: supports D1 D2
10608 23:01:15.788784 <6>[ 13.960995] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10609 23:01:15.799027 <3>[ 13.970590] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10610 23:01:15.805411 <6>[ 13.974430] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10611 23:01:15.815572 <6>[ 13.974742] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10612 23:01:15.821900 <6>[ 13.974761] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10613 23:01:15.828659 <6>[ 13.974790] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10614 23:01:15.838495 <6>[ 13.974827] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10615 23:01:15.844782 <6>[ 13.974847] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10616 23:01:15.851411 <6>[ 13.974866] pci 0000:00:00.0: PCI bridge to [bus 01]
10617 23:01:15.857892 <6>[ 13.974879] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10618 23:01:15.864377 <6>[ 13.975889] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10619 23:01:15.871258 <6>[ 13.984186] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10620 23:01:15.878317 <6>[ 13.995859] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10621 23:01:15.884618 <6>[ 13.997890] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10622 23:01:15.891070 <6>[ 13.997901] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10623 23:01:15.897891 <6>[ 13.997908] remoteproc remoteproc0: remote processor scp is now up
10624 23:01:15.904175 <6>[ 13.999394] videodev: Linux video capture interface: v2.00
10625 23:01:15.914402 <3>[ 14.000396] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10626 23:01:15.920671 <6>[ 14.009698] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10627 23:01:15.930971 <6>[ 14.032872] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10628 23:01:15.937568 <6>[ 14.037217] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10629 23:01:15.947714 <6>[ 14.038867] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10630 23:01:15.953883 <4>[ 14.038990] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10631 23:01:15.964235 <4>[ 14.038997] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10632 23:01:15.973970 <6>[ 14.041918] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10633 23:01:15.984045 <6>[ 14.042246] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10634 23:01:15.990783 <5>[ 14.061849] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10635 23:01:15.997547 <6>[ 14.069340] usbcore: registered new interface driver cdc_ether
10636 23:01:16.003901 <6>[ 14.077333] usbcore: registered new interface driver r8153_ecm
10637 23:01:16.007090 <6>[ 14.077413] Bluetooth: Core ver 2.22
10638 23:01:16.010616 <6>[ 14.077529] NET: Registered PF_BLUETOOTH protocol family
10639 23:01:16.017433 <6>[ 14.077533] Bluetooth: HCI device and connection manager initialized
10640 23:01:16.023742 <6>[ 14.077586] Bluetooth: HCI socket layer initialized
10641 23:01:16.030411 <6>[ 14.077600] Bluetooth: L2CAP socket layer initialized
10642 23:01:16.033799 <6>[ 14.077630] Bluetooth: SCO socket layer initialized
10643 23:01:16.040439 <5>[ 14.096073] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10644 23:01:16.050116 <4>[ 14.096138] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10645 23:01:16.053554 <6>[ 14.096144] cfg80211: failed to load regulatory.db
10646 23:01:16.063390 <6>[ 14.111586] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10647 23:01:16.073139 <6>[ 14.112801] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10648 23:01:16.079817 <6>[ 14.112964] usbcore: registered new interface driver uvcvideo
10649 23:01:16.083600 <6>[ 14.121662] r8152 2-1.3:1.0 eth0: v1.12.13
10650 23:01:16.089922 <6>[ 14.139041] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10651 23:01:16.096505 <6>[ 14.153708] usbcore: registered new interface driver btusb
10652 23:01:16.106687 <4>[ 14.154977] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10653 23:01:16.113141 <3>[ 14.154991] Bluetooth: hci0: Failed to load firmware file (-2)
10654 23:01:16.120002 <3>[ 14.154994] Bluetooth: hci0: Failed to set up firmware (-2)
10655 23:01:16.129731 <4>[ 14.154998] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10656 23:01:16.136363 <6>[ 14.193909] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10657 23:01:16.142749 <6>[ 14.194005] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10658 23:01:16.149436 <6>[ 14.213595] mt7921e 0000:01:00.0: ASIC revision: 79610010
10659 23:01:16.160002 <4>[ 14.308339] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10660 23:01:16.172172 <4>[ 14.415278] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10661 23:01:16.181956 <4>[ 14.522898] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10662 23:01:16.211063 done
10663 23:01:16.238746 Saving random seed: <4>[ 14.629151] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10664 23:01:16.238858 OK
10665 23:01:16.259469 Starting network: OK
10666 23:01:16.295564 Starting dropbear sshd: OK
10667 23:01:16.298208 <6>[ 14.693748] NET: Registered PF_INET6 protocol family
10668 23:01:16.305435 /bin/sh: can't access tty<6>[ 14.695090] Segment Routing with IPv6
10669 23:01:16.312522 <6>[ 14.695101] In-situ OAM (IOAM) with IPv6
10670 23:01:16.312628 ; job control turned off
10671 23:01:16.312958 Matched prompt #10: / #
10673 23:01:16.313156 Setting prompt string to ['/ #']
10674 23:01:16.313256 end: 2.2.5.1 login-action (duration 00:00:15) [common]
10676 23:01:16.313557 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10677 23:01:16.313693 start: 2.2.6 expect-shell-connection (timeout 00:03:44) [common]
10678 23:01:16.313765 Setting prompt string to ['/ #']
10679 23:01:16.313829 Forcing a shell prompt, looking for ['/ #']
10681 23:01:16.364015 / #
10682 23:01:16.364145 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10683 23:01:16.364247 Waiting using forced prompt support (timeout 00:02:30)
10684 23:01:16.364379 <4>[ 14.739976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10685 23:01:16.369478
10686 23:01:16.369783 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10687 23:01:16.369874 start: 2.2.7 export-device-env (timeout 00:03:44) [common]
10688 23:01:16.369971 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10689 23:01:16.370059 end: 2.2 depthcharge-retry (duration 00:01:16) [common]
10690 23:01:16.370141 end: 2 depthcharge-action (duration 00:01:16) [common]
10691 23:01:16.370229 start: 3 lava-test-retry (timeout 00:01:00) [common]
10692 23:01:16.370314 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10693 23:01:16.370389 Using namespace: common
10695 23:01:16.470659 / # #
10696 23:01:16.470788 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10697 23:01:16.470895 #<4>[ 14.847809] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10698 23:01:16.475960
10699 23:01:16.476221 Using /lava-12172435
10701 23:01:16.576546 / # export SHELL=/bin/sh
10702 23:01:16.576702 export SHELL=/bin/sh<4>[ 14.956307] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10703 23:01:16.581531
10705 23:01:16.681998 / # . /lava-12172435/environment
10706 23:01:16.682147 . /lava-12172435/environment<4>[ 15.064265] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10707 23:01:16.687581
10709 23:01:16.788089 / # /lava-12172435/bin/lava-test-runner /lava-12172435/0
10710 23:01:16.788234 Test shell timeout: 10s (minimum of the action and connection timeout)
10711 23:01:16.788717 /lava-12172435/bin/lava-test-runner /lava-12172435/0<4>[ 15.172326] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10712 23:01:16.793509
10713 23:01:16.837775 + export 'TESTRUN_ID=0_dmesg'
10714 23:01:16.838049 + cd /lava-121724<8>[ 15.215568] <LAVA_SIGNAL_STARTRUN 0_dmesg 12172435_1.5.2.3.1>
10715 23:01:16.838221 35/0/tests/0_dmesg
10716 23:01:16.838380 + cat uuid
10717 23:01:16.838598 + UUID=12172435_1.5.2.3.1
10718 23:01:16.839069 Received signal: <STARTRUN> 0_dmesg 12172435_1.5.2.3.1
10719 23:01:16.839253 Starting test lava.0_dmesg (12172435_1.5.2.3.1)
10720 23:01:16.839457 Skipping test definition patterns.
10721 23:01:16.839696 + set<8>[ 15.229359] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10722 23:01:16.839872 +x
10723 23:01:16.840225 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10725 23:01:16.848707 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dme<8>[ 15.240785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10726 23:01:16.849030 sg.sh
10727 23:01:16.849503 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10729 23:01:16.858878 <8>[ 15.253328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10730 23:01:16.859317 + set +x
10731 23:01:16.859920 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10733 23:01:16.861670 <LAVA_TEST_RUNNER EXIT>
10734 23:01:16.862360 ok: lava_test_shell seems to have completed
10735 23:01:16.862752 Marking unfinished test run as failed
10737 23:01:16.863725 alert: pass
crit: pass
emerg: pass
10738 23:01:16.864145 end: 3.1 lava-test-shell (duration 00:00:00) [common]
10739 23:01:16.864713 end: 3 lava-test-retry (duration 00:00:00) [common]
10740 23:01:16.865292 start: 4 lava-test-retry (timeout 00:01:00) [common]
10741 23:01:16.865889 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10742 23:01:16.866243 Using namespace: common
10744 23:01:16.967175 / # <8>[ 15.2#
10745 23:01:16.967838 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10746 23:01:16.968371 Using /lava-12172435
10748 23:01:17.069341 export SHELL=/bin/sh
10749 23:01:17.070072 62617] <LAVA_SIGNAL_ENDRUN 0_dmesg 12172435_1.5.2.3.1>
10750 23:01:17.070703 <4>[ 15.280196] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 23:01:17.071302 #
10752 23:01:17.071896 / # <3>[ 15.386315] mt7921e 0000:01:00.0: hardware init failed
10754 23:01:17.173693 export SHELL=/bin/sh. /lava-12172435/environment
10755 23:01:17.174508
10757 23:01:17.276104 / # . /lava-12172435/environment/lava-12172435/bin/lava-test-runner /lava-12172435/1
10758 23:01:17.276767 Test shell timeout: 10s (minimum of the action and connection timeout)
10759 23:01:17.277351
10760 23:01:17.282653 / # /lava-12172435/bin/lava-test-runner /lava-12172435/1
10761 23:01:17.301161 + export 'TESTRUN_ID=1_bootrr'
10762 23:01:17.310877 + cd /lava-12172<8>[ 15.704733] <LAVA_SIGNAL_STARTRUN 1_bootrr 12172435_1.5.2.3.5>
10763 23:01:17.311303 435/1/tests/1_bootrr
10764 23:01:17.311652 + cat uuid
10765 23:01:17.312399 Received signal: <STARTRUN> 1_bootrr 12172435_1.5.2.3.5
10766 23:01:17.312854 Starting test lava.1_bootrr (12172435_1.5.2.3.5)
10767 23:01:17.313294 Skipping test definition patterns.
10768 23:01:17.314316 + UUID=12172435_1.5.2.3.5
10769 23:01:17.314768 + set +x
10770 23:01:17.327560 + export 'PATH=/opt/bootrr/libexec/bootrr<8>[ 15.718785] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10771 23:01:17.328259 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10773 23:01:17.334324 /helpers:/lava-12172435/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10774 23:01:17.344100 + cd /opt/bootrr/libexec/bootrr<8>[ 15.733941] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10775 23:01:17.344651
10776 23:01:17.345000 + sh helpers/bootrr-auto
10777 23:01:17.345613 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10779 23:01:17.347462 /lava-12172435/1/../bin/lava-test-case
10780 23:01:17.350986 /lava-12172435/1/../bin/lava-test-case
10781 23:01:17.354189 /usr/bin/tpm2_getcap
10782 23:01:17.377259 /lava-12172435/1/../bin/lava-test-case
10783 23:01:17.387307 <8>[ 15.779749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10784 23:01:17.388165 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10786 23:01:17.395250 /lava-12172435/1/../bin/lava-test-case
10787 23:01:17.401478 <8>[ 15.796961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10788 23:01:17.401759 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10790 23:01:17.404995 /lava-12172435/1/../bin/lava-test-case
10791 23:01:17.414998 <8>[ 15.808460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10792 23:01:17.415249 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10794 23:01:17.417900 /lava-12172435/1/../bin/lava-test-case
10795 23:01:17.424676 <8>[ 15.820448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10796 23:01:17.424926 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10798 23:01:17.428099 /lava-12172435/1/../bin/lava-test-case
10799 23:01:17.441966 <8>[ 15.833431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10800 23:01:17.442227 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10802 23:01:17.445467 /lava-12172435/1/../bin/lava-test-case
10803 23:01:17.457731 /lava-12172435/1<8>[ 15.849768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10804 23:01:17.457982 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10806 23:01:17.467977 /../bin/lava-tes<8>[ 15.858532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10807 23:01:17.468227 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10809 23:01:17.471022 t-case
10810 23:01:17.474234 /lava-12172435/1/../bin/lava-test-case
10811 23:01:17.481014 <8>[ 15.875745] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10812 23:01:17.481265 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10814 23:01:17.484243 /lava-12172435/1/../bin/lava-test-case
10815 23:01:17.494489 <8>[ 15.888286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10816 23:01:17.494740 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10818 23:01:17.497923 /lava-12172435/1/../bin/lava-test-case
10819 23:01:17.510294 <8>[ 15.901678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10820 23:01:17.510546 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10822 23:01:17.513684 /lava-12172435/1/../bin/lava-test-case
10823 23:01:17.523668 <8>[ 15.917379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10824 23:01:17.523948 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10826 23:01:17.526867 /lava-12172435/1/../bin/lava-test-case
10827 23:01:17.538764 <8>[ 15.929888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10828 23:01:17.539014 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10830 23:01:17.541546 /lava-12172435/1/../bin/lava-test-case
10831 23:01:17.554180 <8>[ 15.946120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10832 23:01:17.554440 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10834 23:01:17.557473 /lava-12172435/1/../bin/lava-test-case
10835 23:01:17.570030 <8>[ 15.962898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10836 23:01:17.570280 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10838 23:01:17.573403 /lava-12172435/1/../bin/lava-test-case
10839 23:01:17.586750 <8>[ 15.979268] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10840 23:01:17.587002 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10842 23:01:17.589702 /lava-12172435/1/../bin/lava-test-case
10843 23:01:17.596312 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10845 23:01:17.599725 <8>[ 15.993315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10846 23:01:17.602907 /lava-12172435/1/../bin/lava-test-case
10847 23:01:17.614018 <8>[ 16.005907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10848 23:01:17.614270 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10850 23:01:17.617368 /lava-12172435/1/../bin/lava-test-case
10851 23:01:17.624381 <8>[ 16.020274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10852 23:01:17.624632 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10854 23:01:17.630737 /lava-12172435/1/../bin/lava-test-case
10855 23:01:17.637388 <8>[ 16.032645] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10856 23:01:17.637664 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10858 23:01:17.641232 /lava-12172435/1/../bin/lava-test-case
10859 23:01:17.650745 <8>[ 16.045124] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10860 23:01:17.650996 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10862 23:01:17.653971 /lava-12172435/1/../bin/lava-test-case
10863 23:01:17.666455 <8>[ 16.058123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10864 23:01:17.666705 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10866 23:01:17.670095 /lava-12172435/1/../bin/lava-test-case
10867 23:01:17.682898 <8>[ 16.073868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10868 23:01:17.683149 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10870 23:01:17.685846 /lava-12172435/1/../bin/lava-test-case
10871 23:01:17.698994 <8>[ 16.090002] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10872 23:01:17.699244 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10874 23:01:17.701803 /lava-12172435/1/../bin/lava-test-case
10875 23:01:17.714486 /lava-12172435/1<8>[ 16.106126] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10876 23:01:17.714739 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10878 23:01:17.724373 /../bin/lava-tes<8>[ 16.113452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10879 23:01:17.724454 t-case
10880 23:01:17.724686 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10882 23:01:17.731051 /lava-12172435/1/../bin/lava-test-case
10883 23:01:17.737452 <8>[ 16.131966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10884 23:01:17.737742 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10886 23:01:17.740621 /lava-12172435/1/../bin/lava-test-case
10887 23:01:17.750843 <8>[ 16.144423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10888 23:01:17.751093 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10890 23:01:17.754383 /lava-12172435/1/../bin/lava-test-case
10891 23:01:17.766145 <8>[ 16.158648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10892 23:01:17.766402 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10894 23:01:17.769500 /lava-12172435/1/../bin/lava-test-case
10895 23:01:17.782611 <8>[ 16.174760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10896 23:01:17.782888 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10898 23:01:17.785663 /lava-12172435/1/../bin/lava-test-case
10899 23:01:17.798143 <8>[ 16.189930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10900 23:01:17.798395 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10902 23:01:17.801529 /lava-12172435/1/../bin/lava-test-case
10903 23:01:17.814020 /lava-12172435/1<8>[ 16.205597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10904 23:01:17.814273 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10906 23:01:17.823641 /../bin/lava-tes<8>[ 16.213537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10907 23:01:17.823892 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10909 23:01:17.827388 t-case
10910 23:01:17.830805 /lava-12172435/1/../bin/lava-test-case
10911 23:01:17.836802 <8>[ 16.232411] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10912 23:01:17.837052 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10914 23:01:17.840505 /lava-12172435/1/../bin/lava-test-case
10915 23:01:17.850240 <8>[ 16.244362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10916 23:01:17.850490 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10918 23:01:17.853736 /lava-12172435/1/../bin/lava-test-case
10919 23:01:17.863670 <8>[ 16.256966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10920 23:01:17.863920 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10922 23:01:17.867332 /lava-12172435/1/../bin/lava-test-case
10923 23:01:17.878125 <8>[ 16.270716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10924 23:01:17.878399 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10926 23:01:17.881137 /lava-12172435/1/../bin/lava-test-case
10927 23:01:17.894444 <8>[ 16.285618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10928 23:01:17.894698 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10930 23:01:17.897943 /lava-12172435/1/../bin/lava-test-case
10931 23:01:17.910356 <8>[ 16.302951] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10932 23:01:17.910612 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10934 23:01:17.913628 /lava-12172435/1/../bin/lava-test-case
10935 23:01:17.926624 <8>[ 16.317840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10936 23:01:17.926880 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10938 23:01:17.929482 /lava-12172435/1/../bin/lava-test-case
10939 23:01:17.936681 <8>[ 16.332888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10940 23:01:17.936927 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10942 23:01:17.939925 /lava-12172435/1/../bin/lava-test-case
10943 23:01:17.950215 <8>[ 16.344273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10944 23:01:17.950489 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10946 23:01:17.953375 /lava-12172435/1/../bin/lava-test-case
10947 23:01:17.966431 <8>[ 16.357689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10948 23:01:17.966720 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10950 23:01:17.969791 /lava-12172435/1/../bin/lava-test-case
10951 23:01:17.982523 <8>[ 16.374168] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10952 23:01:17.982798 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
10954 23:01:17.985708 /lava-12172435/1/../bin/lava-test-case
10955 23:01:17.998405 /lava-12172435/1<8>[ 16.390119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
10956 23:01:17.998654 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
10958 23:01:18.008544 /../bin/lava-tes<8>[ 16.398648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
10959 23:01:18.008649 t-case
10960 23:01:18.008941 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
10962 23:01:18.011450 /lava-12172435/1/../bin/lava-test-case
10963 23:01:18.022470 <8>[ 16.415005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
10964 23:01:18.022745 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
10966 23:01:18.025552 /lava-12172435/1/../bin/lava-test-case
10967 23:01:18.035595 <8>[ 16.427904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
10968 23:01:18.035843 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
10970 23:01:18.039004 /lava-12172435/1/../bin/lava-test-case
10971 23:01:18.045612 <8>[ 16.441071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
10972 23:01:18.045890 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
10974 23:01:18.049060 /lava-12172435/1/../bin/lava-test-case
10975 23:01:18.058856 <8>[ 16.452613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
10976 23:01:18.059111 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
10978 23:01:18.062481 /lava-12172435/1/../bin/lava-test-case
10979 23:01:18.069295 <8>[ 16.464904] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass>
10980 23:01:18.069581 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=pass
10982 23:01:18.072588 /lava-12172435/1/../bin/lava-test-case
10983 23:01:18.082206 <8>[ 16.476783] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass>
10984 23:01:18.082459 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=pass
10986 23:01:18.085717 /lava-12172435/1/../bin/lava-test-case
10987 23:01:18.091867 <8>[ 16.488920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
10988 23:01:18.092118 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
10990 23:01:18.098699 /lava-12172435/1/../bin/lava-test-case
10991 23:01:18.105185 <8>[ 16.501234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
10992 23:01:18.105464 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
10994 23:01:18.108722 /lava-12172435/1/../bin/lava-test-case
10995 23:01:18.115834 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
10997 23:01:18.118535 <8>[ 16.512569] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
10998 23:01:18.122381 /lava-12172435/1/../bin/lava-test-case
10999 23:01:18.128507 <8>[ 16.523930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11000 23:01:18.128783 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11002 23:01:18.132055 /lava-12172435/1/../bin/lava-test-case
11003 23:01:18.141691 <8>[ 16.537177] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11004 23:01:18.141941 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11006 23:01:18.145352 /lava-12172435/1/../bin/lava-test-case
11007 23:01:18.152271 <8>[ 16.548923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11008 23:01:18.152537 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11010 23:01:18.155342 /lava-12172435/1/../bin/lava-test-case
11011 23:01:18.166230 <8>[ 16.559913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11012 23:01:18.166494 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11014 23:01:18.169441 /lava-12172435/1/../bin/lava-test-case
11015 23:01:18.176421 <8>[ 16.572458] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11016 23:01:18.176698 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11018 23:01:18.179599 /lava-12172435/1/../bin/lava-test-case
11019 23:01:18.189934 <8>[ 16.583760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11020 23:01:18.190206 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11022 23:01:18.193252 /lava-12172435/1/../bin/lava-test-case
11023 23:01:18.200096 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11025 23:01:18.203172 <8>[ 16.596820] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11026 23:01:18.206912 /lava-12172435/1/../bin/lava-test-case
11027 23:01:18.213275 <8>[ 16.608652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11028 23:01:18.213616 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11030 23:01:18.216708 /lava-12172435/1/../bin/lava-test-case
11031 23:01:18.226380 <8>[ 16.620953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11032 23:01:18.226701 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11034 23:01:18.229873 /lava-12172435/1/../bin/lava-test-case
11035 23:01:18.241740 /lava-12172435/1<8>[ 16.633586] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11036 23:01:18.242026 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11038 23:01:18.251447 /../bin/lava-tes<8>[ 16.641071] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11039 23:01:18.251562 t-case
11040 23:01:18.251827 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11042 23:01:18.255085 /lava-12172435/1/../bin/lava-test-case
11043 23:01:18.266183 <8>[ 16.659100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11044 23:01:18.266460 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11046 23:01:18.269876 /lava-12172435/1/../bin/lava-test-case
11047 23:01:18.276461 <8>[ 16.673077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11048 23:01:18.276738 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11050 23:01:18.279654 /lava-12172435/1/../bin/lava-test-case
11051 23:01:18.290360 <8>[ 16.684225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11052 23:01:18.290615 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11054 23:01:18.293693 /lava-12172435/1/../bin/lava-test-case
11055 23:01:18.300175 <8>[ 16.697041] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11056 23:01:18.300422 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11058 23:01:18.303671 /lava-12172435/1/../bin/lava-test-case
11059 23:01:18.314246 <8>[ 16.709189] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11060 23:01:18.314506 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11062 23:01:18.317582 /lava-12172435/1/../bin/lava-test-case
11063 23:01:18.324162 <8>[ 16.720885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11064 23:01:18.324416 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11066 23:01:18.327315 /lava-12172435/1/../bin/lava-test-case
11067 23:01:18.338106 <8>[ 16.732328] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11068 23:01:18.338391 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11070 23:01:18.341484 /lava-12172435/1/../bin/lava-test-case
11071 23:01:18.354572 <8>[ 16.745604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11072 23:01:18.354822 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11074 23:01:18.357820 /lava-12172435/1/../bin/lava-test-case
11075 23:01:18.364010 <8>[ 16.761344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11076 23:01:18.364299 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11078 23:01:18.367759 /lava-12172435/1/../bin/lava-test-case
11079 23:01:18.377899 <8>[ 16.773333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11080 23:01:18.378148 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11082 23:01:18.381367 /lava-12172435/1/../bin/lava-test-case
11083 23:01:18.388303 <8>[ 16.784392] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11084 23:01:18.388554 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11086 23:01:18.391283 /lava-12172435/1/../bin/lava-test-case
11087 23:01:18.401833 <8>[ 16.796338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11088 23:01:18.402091 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11090 23:01:18.405125 /lava-12172435/1/../bin/lava-test-case
11091 23:01:18.411922 <8>[ 16.808229] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11092 23:01:18.412202 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11094 23:01:18.415434 /lava-12172435/1/../bin/lava-test-case
11095 23:01:18.425920 <8>[ 16.820940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11096 23:01:18.426168 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11098 23:01:18.428887 /lava-12172435/1/../bin/lava-test-case
11099 23:01:18.435657 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11101 23:01:18.438936 <8>[ 16.832088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11102 23:01:18.442074 /lava-12172435/1/../bin/lava-test-case
11103 23:01:18.453963 <8>[ 16.845855] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11104 23:01:18.454246 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11106 23:01:18.457477 /lava-12172435/1/../bin/lava-test-case
11107 23:01:18.463949 <8>[ 16.860788] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11108 23:01:18.464224 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11110 23:01:18.467074 /lava-12172435/1/../bin/lava-test-case
11111 23:01:18.477645 <8>[ 16.872298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11112 23:01:18.477889 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11114 23:01:18.481450 /lava-12172435/1/../bin/lava-test-case
11115 23:01:18.488024 <8>[ 16.885236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11116 23:01:18.488270 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11118 23:01:18.490969 /lava-12172435/1/../bin/lava-test-case
11119 23:01:18.502160 <8>[ 16.896062] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11120 23:01:18.502409 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11122 23:01:18.505272 /lava-12172435/1/../bin/lava-test-case
11123 23:01:18.517761 <8>[ 16.910201] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11124 23:01:18.518013 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11126 23:01:18.521090 /lava-12172435/1/../bin/lava-test-case
11127 23:01:18.531456 <8>[ 16.925184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11128 23:01:18.531706 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11130 23:01:18.534784 /lava-12172435/1/../bin/lava-test-case
11131 23:01:18.541221 <8>[ 16.936688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11132 23:01:18.541497 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11134 23:01:18.544401 /lava-12172435/1/../bin/lava-test-case
11135 23:01:18.554725 <8>[ 16.948842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11136 23:01:18.554982 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11138 23:01:18.557589 /lava-12172435/1/../bin/lava-test-case
11139 23:01:18.564098 <8>[ 16.960585] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11140 23:01:18.564341 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11142 23:01:18.568231 /lava-12172435/1/../bin/lava-test-case
11143 23:01:18.578176 <8>[ 16.972408] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11144 23:01:18.578423 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11146 23:01:18.581217 /lava-12172435/1/../bin/lava-test-case
11147 23:01:18.593765 <8>[ 16.985501] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11148 23:01:18.594010 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11150 23:01:18.597347 /lava-12172435/1/../bin/lava-test-case
11151 23:01:18.603842 <8>[ 17.000653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11152 23:01:18.604120 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11154 23:01:18.610545 /lava-12172435/1/../bin/lava-test-case
11155 23:01:18.616977 <8>[ 17.013096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11156 23:01:18.617257 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11158 23:01:18.620517 /lava-12172435/1/../bin/lava-test-case
11159 23:01:18.634016 <8>[ 17.026289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11160 23:01:18.634297 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11162 23:01:18.637445 /lava-12172435/1/../bin/lava-test-case
11163 23:01:18.644035 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11165 23:01:18.646891 <8>[ 17.040017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11166 23:01:18.650520 /lava-12172435/1/../bin/lava-test-case
11167 23:01:18.656969 <8>[ 17.053118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11168 23:01:18.657215 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11170 23:01:18.660658 /lava-12172435/1/../bin/lava-test-case
11171 23:01:18.670229 <8>[ 17.063526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11172 23:01:18.670473 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11174 23:01:19.674268 /lava-12172435/1/../bin/lava-test-case
11175 23:01:19.685805 <8>[ 18.078579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11176 23:01:19.686099 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11178 23:01:19.688889 /lava-12172435/1/../bin/lava-test-case
11179 23:01:19.698649 <8>[ 18.091535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11180 23:01:19.698907 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11182 23:01:20.701972 /lava-12172435/1/../bin/lava-test-case
11183 23:01:20.713926 <8>[ 19.106116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11184 23:01:20.714201 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11186 23:01:20.717574 /lava-12172435/1/../bin/lava-test-case
11187 23:01:20.727088 <8>[ 19.120047] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11188 23:01:20.727366 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11190 23:01:21.729283 /lava-12172435/1/../bin/lava-test-case
11191 23:01:21.741932 <8>[ 20.134074] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11192 23:01:21.742192 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11194 23:01:21.745222 /lava-12172435/1/../bin/lava-test-case
11195 23:01:21.752065 <8>[ 20.148579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11196 23:01:21.752339 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11198 23:01:22.757454 /lava-12172435/1/../bin/lava-test-case
11199 23:01:22.769558 <8>[ 21.162135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11200 23:01:22.769849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11202 23:01:22.772927 /lava-12172435/1/../bin/lava-test-case
11203 23:01:22.779638 <8>[ 21.176394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11204 23:01:22.779881 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11206 23:01:23.785874 /lava-12172435/1/../bin/lava-test-case
11207 23:01:23.797444 <8>[ 22.189491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11208 23:01:23.797733 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11210 23:01:23.800740 /lava-12172435/1/../bin/lava-test-case
11211 23:01:23.810399 <8>[ 22.203925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11212 23:01:23.810646 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11214 23:01:24.812784 /lava-12172435/1/../bin/lava-test-case
11215 23:01:24.825113 <8>[ 23.217574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11216 23:01:24.825415 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11218 23:01:24.828349 /lava-12172435/1/../bin/lava-test-case
11219 23:01:24.838156 <8>[ 23.233251] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11220 23:01:24.838434 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11222 23:01:25.841589 /lava-12172435/1/../bin/lava-test-case
11223 23:01:25.855653 <8>[ 24.246691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11224 23:01:25.855919 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11226 23:01:25.858778 /lava-12172435/1/../bin/lava-test-case
11227 23:01:25.869499 <8>[ 24.262500] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11228 23:01:25.869786 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11230 23:01:25.872731 /lava-12172435/1/../bin/lava-test-case
11231 23:01:25.885004 <8>[ 24.279034] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11232 23:01:25.885280 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11234 23:01:26.889053 /lava-12172435/1/../bin/lava-test-case
11235 23:01:26.896094 <8>[ 25.292573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11236 23:01:26.896379 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11238 23:01:26.899233 /lava-12172435/1/../bin/lava-test-case
11239 23:01:26.912849 <8>[ 25.305592] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11240 23:01:26.913130 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11242 23:01:26.916128 /lava-12172435/1/../bin/lava-test-case
11243 23:01:26.929741 <8>[ 25.321575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11244 23:01:26.930013 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11246 23:01:26.932472 /lava-12172435/1/../bin/lava-test-case
11247 23:01:26.944862 <8>[ 25.338121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11248 23:01:26.945138 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11250 23:01:26.948520 /lava-12172435/1/../bin/lava-test-case
11251 23:01:26.958298 <8>[ 25.353154] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11252 23:01:26.958546 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11254 23:01:26.961480 /lava-12172435/1/../bin/lava-test-case
11255 23:01:26.968424 <8>[ 25.364811] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11256 23:01:26.968697 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11258 23:01:26.971428 /lava-12172435/1/../bin/lava-test-case
11259 23:01:26.985181 <8>[ 25.378431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11260 23:01:26.985462 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11262 23:01:26.988537 /lava-12172435/1/../bin/lava-test-case
11263 23:01:27.000986 <8>[ 25.394510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11264 23:01:27.001260 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11266 23:01:27.004567 /lava-12172435/1/../bin/lava-test-case
11267 23:01:27.014469 <8>[ 25.409354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11268 23:01:27.014730 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11270 23:01:27.017927 /lava-12172435/1/../bin/lava-test-case
11271 23:01:27.024455 <8>[ 25.421026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11272 23:01:27.024732 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11274 23:01:27.027773 /lava-12172435/1/../bin/lava-test-case
11275 23:01:27.041185 <8>[ 25.433418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11276 23:01:27.041465 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11278 23:01:27.044510 /lava-12172435/1/../bin/lava-test-case
11279 23:01:27.057108 <8>[ 25.450600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11280 23:01:27.057384 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11282 23:01:27.060467 /lava-12172435/1/../bin/lava-test-case
11283 23:01:27.070489 <8>[ 25.464536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11284 23:01:27.070761 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11286 23:01:27.073437 /lava-12172435/1/../bin/lava-test-case
11287 23:01:27.080466 <8>[ 25.477127] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11288 23:01:27.080749 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11290 23:01:27.083506 /lava-12172435/1/../bin/lava-test-case
11291 23:01:27.093384 <8>[ 25.488823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11292 23:01:27.093659 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11294 23:01:27.096965 /lava-12172435/1/../bin/lava-test-case
11295 23:01:27.108755 <8>[ 25.502270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11296 23:01:27.108999 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11298 23:01:27.111948 /lava-12172435/1/../bin/lava-test-case
11299 23:01:27.124811 <8>[ 25.517545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11300 23:01:27.125082 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11302 23:01:27.128132 /lava-12172435/1/../bin/lava-test-case
11303 23:01:27.141250 <8>[ 25.534638] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11304 23:01:27.141522 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11306 23:01:27.144813 /lava-12172435/1/../bin/lava-test-case
11307 23:01:27.151184 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11309 23:01:27.154452 <8>[ 25.548566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11310 23:01:27.157667 /lava-12172435/1/../bin/lava-test-case
11311 23:01:27.164543 <8>[ 25.560548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11312 23:01:27.164793 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11314 23:01:27.167396 /lava-12172435/1/../bin/lava-test-case
11315 23:01:27.177726 <8>[ 25.572980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11316 23:01:27.177978 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11318 23:01:28.181844 /lava-12172435/1/../bin/lava-test-case
11319 23:01:28.193678 <8>[ 26.586413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11320 23:01:28.194378 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11322 23:01:29.195919 /lava-12172435/1/../bin/lava-test-case
11323 23:01:29.202788 <8>[ 27.600684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11324 23:01:29.203574 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11326 23:01:29.205953 /lava-12172435/1/../bin/lava-test-case
11327 23:01:29.217450 <8>[ 27.611691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11328 23:01:29.218286 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11330 23:01:29.220504 /lava-12172435/1/../bin/lava-test-case
11331 23:01:29.227666 <8>[ 27.624657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11332 23:01:29.228565 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11334 23:01:29.230707 /lava-12172435/1/../bin/lava-test-case
11335 23:01:29.241391 <8>[ 27.635660] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11336 23:01:29.242317 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11338 23:01:29.244209 /lava-12172435/1/../bin/lava-test-case
11339 23:01:29.257227 <8>[ 27.651228] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11340 23:01:29.258005 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11342 23:01:29.260297 /lava-12172435/1/../bin/lava-test-case
11343 23:01:29.266725 <8>[ 27.664356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11344 23:01:29.267447 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11346 23:01:29.273670 /lava-12172435/1/../bin/lava-test-case
11347 23:01:29.279991 <8>[ 27.676218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11348 23:01:29.280666 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11350 23:01:29.283540 /lava-12172435/1/../bin/lava-test-case
11351 23:01:29.293457 <8>[ 27.688079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11352 23:01:29.294203 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11354 23:01:29.296843 /lava-12172435/1/../bin/lava-test-case
11355 23:01:29.303568 <8>[ 27.701319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11356 23:01:29.304382 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11358 23:01:29.307295 /lava-12172435/1/../bin/lava-test-case
11359 23:01:29.317673 <8>[ 27.711741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11360 23:01:29.318349 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11362 23:01:29.320803 /lava-12172435/1/../bin/lava-test-case
11363 23:01:29.327400 <8>[ 27.724387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11364 23:01:29.328160 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11366 23:01:29.330942 /lava-12172435/1/../bin/lava-test-case
11367 23:01:29.341504 <8>[ 27.735588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11368 23:01:29.342226 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11370 23:01:29.344353 /lava-12172435/1/../bin/lava-test-case
11371 23:01:29.350777 <8>[ 27.749289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11372 23:01:29.351475 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11374 23:01:29.354484 /lava-12172435/1/../bin/lava-test-case
11375 23:01:29.365132 <8>[ 27.759866] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11376 23:01:29.365875 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11378 23:01:29.368210 /lava-12172435/1/../bin/lava-test-case
11379 23:01:29.375679 <8>[ 27.772422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11380 23:01:29.376376 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11382 23:01:29.378162 /lava-12172435/1/../bin/lava-test-case
11383 23:01:29.388918 <8>[ 27.783689] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11384 23:01:29.389647 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11386 23:01:29.392384 /lava-12172435/1/../bin/lava-test-case
11387 23:01:29.398919 <8>[ 27.797106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11388 23:01:29.399609 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11390 23:01:29.402128 /lava-12172435/1/../bin/lava-test-case
11391 23:01:29.412906 <8>[ 27.807555] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11392 23:01:29.413671 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11394 23:01:29.416506 /lava-12172435/1/../bin/lava-test-case
11395 23:01:29.422734 <8>[ 27.820968] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11396 23:01:29.423432 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11398 23:01:29.426081 /lava-12172435/1/../bin/lava-test-case
11399 23:01:29.437167 <8>[ 27.832339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11400 23:01:29.438074 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11402 23:01:29.440788 /lava-12172435/1/../bin/lava-test-case
11403 23:01:29.446814 <8>[ 27.845318] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11404 23:01:29.447508 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11406 23:01:30.451758 /lava-12172435/1/../bin/lava-test-case
11407 23:01:30.461771 <8>[ 28.855463] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11408 23:01:30.462568 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11410 23:01:31.462302 /lava-12172435/1/../bin/lava-test-case
11411 23:01:31.472287 <8>[ 29.866066] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11412 23:01:31.472585 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11413 23:01:31.472699 Bad test result: blocked
11414 23:01:31.475740 /lava-12172435/1/../bin/lava-test-case
11415 23:01:31.488478 <8>[ 29.882063] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11416 23:01:31.488756 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11418 23:01:32.491890 /lava-12172435/1/../bin/lava-test-case
11419 23:01:32.498649 <8>[ 30.895766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11420 23:01:32.499419 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11422 23:01:32.501623 /lava-12172435/1/../bin/lava-test-case
11423 23:01:32.512674 <8>[ 30.908294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11424 23:01:32.513360 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11426 23:01:32.516488 /lava-12172435/1/../bin/lava-test-case
11427 23:01:32.523118 <8>[ 30.921121] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11428 23:01:32.523841 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11430 23:01:32.525964 /lava-12172435/1/../bin/lava-test-case
11431 23:01:32.536470 <8>[ 30.932343] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11432 23:01:32.537200 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11434 23:01:32.539935 /lava-12172435/1/../bin/lava-test-case
11435 23:01:32.550018 <8>[ 30.943704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11436 23:01:32.550948 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11438 23:01:32.553467 /lava-12172435/1/../bin/lava-test-case
11439 23:01:32.564951 <8>[ 30.958834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11440 23:01:32.565697 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11442 23:01:32.567948 /lava-12172435/1/../bin/lava-test-case
11443 23:01:32.575146 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11445 23:01:32.577883 <8>[ 30.972209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11446 23:01:33.582124 /lava-12172435/1/../bin/lava-test-case
11447 23:01:33.591974 /lava-12172435/1<8>[ 31.985574] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11448 23:01:33.592787 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11450 23:01:33.602033 /../bin/lava-tes<8>[ 31.992646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11451 23:01:33.602471 t-case
11452 23:01:33.603058 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11454 23:01:34.603668 /lava-12172435/1/../bin/lava-test-case
11455 23:01:34.610155 <8>[ 33.007944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11456 23:01:34.611407 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11458 23:01:34.613107 /lava-12172435/1/../bin/lava-test-case
11459 23:01:34.623758 <8>[ 33.021247] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11460 23:01:34.624024 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11462 23:01:35.631415 /lava-12172435/1/../bin/lava-test-case
11463 23:01:35.638073 <8>[ 34.035671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11464 23:01:35.638795 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11466 23:01:35.641143 /lava-12172435/1/../bin/lava-test-case
11467 23:01:35.652765 <8>[ 34.047559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11468 23:01:35.653700 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11470 23:01:36.658609 /lava-12172435/1/../bin/lava-test-case
11471 23:01:36.668481 <8>[ 35.064583] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11472 23:01:36.669324 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11474 23:01:36.672010 /lava-12172435/1/../bin/lava-test-case
11475 23:01:36.679025 <8>[ 35.076425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11476 23:01:36.679706 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11478 23:01:36.682037 /lava-12172435/1/../bin/lava-test-case
11479 23:01:36.692164 <8>[ 35.088191] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11480 23:01:36.692838 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11482 23:01:36.695735 /lava-12172435/1/../bin/lava-test-case
11483 23:01:36.702581 <8>[ 35.099497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11484 23:01:36.703254 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11486 23:01:36.705373 /lava-12172435/1/../bin/lava-test-case
11487 23:01:36.716211 <8>[ 35.111532] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11488 23:01:36.716883 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11490 23:01:36.719620 /lava-12172435/1/../bin/lava-test-case
11491 23:01:36.726099 <8>[ 35.124284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11492 23:01:36.726800 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11494 23:01:36.729695 /lava-12172435/1/../bin/lava-test-case
11495 23:01:36.744366 <8>[ 35.137492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11496 23:01:36.745037 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11498 23:01:36.747702 /lava-12172435/1/../bin/lava-test-case
11499 23:01:36.760374 /lava-12172435/1<8>[ 35.153810] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11500 23:01:36.761046 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11502 23:01:36.770350 <8>[ 35.163850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11503 23:01:36.770790 /../bin/lava-test-case
11504 23:01:36.771383 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11506 23:01:36.773662 /lava-12172435/1/../bin/lava-test-case
11507 23:01:36.776886 + set +x
11508 23:01:36.783286 <8>[ 35.178560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass>
11509 23:01:36.783955 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=pass
11511 23:01:36.790262 <8>[ 35.180729] <LAVA_SIGNAL_ENDRUN 1_bootrr 12172435_1.5.2.3.5>
11512 23:01:36.790961 Received signal: <ENDRUN> 1_bootrr 12172435_1.5.2.3.5
11513 23:01:36.791417 Ending use of test pattern.
11514 23:01:36.791805 Ending test lava.1_bootrr (12172435_1.5.2.3.5), duration 19.48
11516 23:01:36.793738 ok: lava_test_shell seems to have completed
11517 23:01:36.798697 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: pass
cros-ec-rpmsg-probed: pass
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: pass
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11518 23:01:36.799451 end: 4.1 lava-test-shell (duration 00:00:20) [common]
11519 23:01:36.799970 end: 4 lava-test-retry (duration 00:00:20) [common]
11520 23:01:36.800511 start: 5 finalize (timeout 00:08:07) [common]
11521 23:01:36.801053 start: 5.1 power-off (timeout 00:00:30) [common]
11522 23:01:36.801929 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11523 23:01:36.920641 >> Command sent successfully.
11524 23:01:36.924540 Returned 0 in 0 seconds
11525 23:01:37.025405 end: 5.1 power-off (duration 00:00:00) [common]
11527 23:01:37.027018 start: 5.2 read-feedback (timeout 00:08:07) [common]
11529 23:01:37.029210 Listened to connection for namespace 'common' for up to 1s
11530 23:01:38.028998 Finalising connection for namespace 'common'
11531 23:01:38.029704 Disconnecting from shell: Finalise
11532 23:01:38.030171 / #
11533 23:01:38.131166 end: 5.2 read-feedback (duration 00:00:01) [common]
11534 23:01:38.131856 end: 5 finalize (duration 00:00:01) [common]
11535 23:01:38.132531 Cleaning after the job
11536 23:01:38.133079 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/ramdisk
11537 23:01:38.147188 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/kernel
11538 23:01:38.172153 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/dtb
11539 23:01:38.172515 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172435/tftp-deploy-us5g40g6/modules
11540 23:01:38.183757 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172435
11541 23:01:38.231338 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172435
11542 23:01:38.231515 Job finished correctly