Boot log: mt8192-asurada-spherion-r0

    1 23:02:02.811773  lava-dispatcher, installed at version: 2023.10
    2 23:02:02.811980  start: 0 validate
    3 23:02:02.812117  Start time: 2023-12-03 23:02:02.812109+00:00 (UTC)
    4 23:02:02.812244  Using caching service: 'http://localhost/cache/?uri=%s'
    5 23:02:02.812380  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
    6 23:02:03.079177  Using caching service: 'http://localhost/cache/?uri=%s'
    7 23:02:03.079346  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 23:02:03.344148  Using caching service: 'http://localhost/cache/?uri=%s'
    9 23:02:03.344335  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 23:02:03.601309  Using caching service: 'http://localhost/cache/?uri=%s'
   11 23:02:03.601476  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
   12 23:02:03.868013  Using caching service: 'http://localhost/cache/?uri=%s'
   13 23:02:03.868199  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   14 23:02:04.134600  validate duration: 1.32
   16 23:02:04.134856  start: 1 tftp-deploy (timeout 00:10:00) [common]
   17 23:02:04.134952  start: 1.1 download-retry (timeout 00:10:00) [common]
   18 23:02:04.135038  start: 1.1.1 http-download (timeout 00:10:00) [common]
   19 23:02:04.135167  Not decompressing ramdisk as can be used compressed.
   20 23:02:04.135255  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/initrd.cpio.gz
   21 23:02:04.135317  saving as /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/ramdisk/initrd.cpio.gz
   22 23:02:04.135378  total size: 4665412 (4 MB)
   23 23:02:04.136423  progress   0 % (0 MB)
   24 23:02:04.138034  progress   5 % (0 MB)
   25 23:02:04.139338  progress  10 % (0 MB)
   26 23:02:04.140571  progress  15 % (0 MB)
   27 23:02:04.141843  progress  20 % (0 MB)
   28 23:02:04.143139  progress  25 % (1 MB)
   29 23:02:04.144363  progress  30 % (1 MB)
   30 23:02:04.145716  progress  35 % (1 MB)
   31 23:02:04.146916  progress  40 % (1 MB)
   32 23:02:04.148278  progress  45 % (2 MB)
   33 23:02:04.149545  progress  50 % (2 MB)
   34 23:02:04.150834  progress  55 % (2 MB)
   35 23:02:04.152044  progress  60 % (2 MB)
   36 23:02:04.153378  progress  65 % (2 MB)
   37 23:02:04.154633  progress  70 % (3 MB)
   38 23:02:04.155839  progress  75 % (3 MB)
   39 23:02:04.157123  progress  80 % (3 MB)
   40 23:02:04.158536  progress  85 % (3 MB)
   41 23:02:04.159741  progress  90 % (4 MB)
   42 23:02:04.160942  progress  95 % (4 MB)
   43 23:02:04.162199  progress 100 % (4 MB)
   44 23:02:04.162348  4 MB downloaded in 0.03 s (164.97 MB/s)
   45 23:02:04.162498  end: 1.1.1 http-download (duration 00:00:00) [common]
   47 23:02:04.162818  end: 1.1 download-retry (duration 00:00:00) [common]
   48 23:02:04.162932  start: 1.2 download-retry (timeout 00:10:00) [common]
   49 23:02:04.163025  start: 1.2.1 http-download (timeout 00:10:00) [common]
   50 23:02:04.163159  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   51 23:02:04.163235  saving as /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/kernel/Image
   52 23:02:04.163293  total size: 49172992 (46 MB)
   53 23:02:04.163351  No compression specified
   54 23:02:04.164455  progress   0 % (0 MB)
   55 23:02:04.177343  progress   5 % (2 MB)
   56 23:02:04.190111  progress  10 % (4 MB)
   57 23:02:04.203191  progress  15 % (7 MB)
   58 23:02:04.216302  progress  20 % (9 MB)
   59 23:02:04.229111  progress  25 % (11 MB)
   60 23:02:04.241905  progress  30 % (14 MB)
   61 23:02:04.255182  progress  35 % (16 MB)
   62 23:02:04.268005  progress  40 % (18 MB)
   63 23:02:04.280740  progress  45 % (21 MB)
   64 23:02:04.293550  progress  50 % (23 MB)
   65 23:02:04.306474  progress  55 % (25 MB)
   66 23:02:04.319372  progress  60 % (28 MB)
   67 23:02:04.332183  progress  65 % (30 MB)
   68 23:02:04.345093  progress  70 % (32 MB)
   69 23:02:04.357796  progress  75 % (35 MB)
   70 23:02:04.370456  progress  80 % (37 MB)
   71 23:02:04.383701  progress  85 % (39 MB)
   72 23:02:04.396774  progress  90 % (42 MB)
   73 23:02:04.409466  progress  95 % (44 MB)
   74 23:02:04.422125  progress 100 % (46 MB)
   75 23:02:04.422361  46 MB downloaded in 0.26 s (181.02 MB/s)
   76 23:02:04.422514  end: 1.2.1 http-download (duration 00:00:00) [common]
   78 23:02:04.422739  end: 1.2 download-retry (duration 00:00:00) [common]
   79 23:02:04.422825  start: 1.3 download-retry (timeout 00:10:00) [common]
   80 23:02:04.422912  start: 1.3.1 http-download (timeout 00:10:00) [common]
   81 23:02:04.423051  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   82 23:02:04.423118  saving as /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/dtb/mt8192-asurada-spherion-r0.dtb
   83 23:02:04.423179  total size: 47278 (0 MB)
   84 23:02:04.423239  No compression specified
   85 23:02:04.424363  progress  69 % (0 MB)
   86 23:02:04.424640  progress 100 % (0 MB)
   87 23:02:04.424796  0 MB downloaded in 0.00 s (27.92 MB/s)
   88 23:02:04.424915  end: 1.3.1 http-download (duration 00:00:00) [common]
   90 23:02:04.425136  end: 1.3 download-retry (duration 00:00:00) [common]
   91 23:02:04.425219  start: 1.4 download-retry (timeout 00:10:00) [common]
   92 23:02:04.425298  start: 1.4.1 http-download (timeout 00:10:00) [common]
   93 23:02:04.425410  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20230623.0/arm64/full.rootfs.tar.xz
   94 23:02:04.425475  saving as /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/nfsrootfs/full.rootfs.tar
   95 23:02:04.425534  total size: 125290964 (119 MB)
   96 23:02:04.425604  Using unxz to decompress xz
   97 23:02:04.429750  progress   0 % (0 MB)
   98 23:02:04.751574  progress   5 % (6 MB)
   99 23:02:05.079668  progress  10 % (11 MB)
  100 23:02:05.406684  progress  15 % (17 MB)
  101 23:02:05.592561  progress  20 % (23 MB)
  102 23:02:05.772335  progress  25 % (29 MB)
  103 23:02:06.121565  progress  30 % (35 MB)
  104 23:02:06.472675  progress  35 % (41 MB)
  105 23:02:06.856634  progress  40 % (47 MB)
  106 23:02:07.228810  progress  45 % (53 MB)
  107 23:02:07.610392  progress  50 % (59 MB)
  108 23:02:07.958986  progress  55 % (65 MB)
  109 23:02:08.322705  progress  60 % (71 MB)
  110 23:02:08.661382  progress  65 % (77 MB)
  111 23:02:09.022923  progress  70 % (83 MB)
  112 23:02:09.397983  progress  75 % (89 MB)
  113 23:02:09.811234  progress  80 % (95 MB)
  114 23:02:10.221563  progress  85 % (101 MB)
  115 23:02:10.463844  progress  90 % (107 MB)
  116 23:02:10.798810  progress  95 % (113 MB)
  117 23:02:11.168894  progress 100 % (119 MB)
  118 23:02:11.174593  119 MB downloaded in 6.75 s (17.70 MB/s)
  119 23:02:11.174867  end: 1.4.1 http-download (duration 00:00:07) [common]
  121 23:02:11.175127  end: 1.4 download-retry (duration 00:00:07) [common]
  122 23:02:11.175216  start: 1.5 download-retry (timeout 00:09:53) [common]
  123 23:02:11.175303  start: 1.5.1 http-download (timeout 00:09:53) [common]
  124 23:02:11.175458  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
  125 23:02:11.175527  saving as /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/modules/modules.tar
  126 23:02:11.175586  total size: 8614132 (8 MB)
  127 23:02:11.175649  Using unxz to decompress xz
  128 23:02:11.179958  progress   0 % (0 MB)
  129 23:02:11.201413  progress   5 % (0 MB)
  130 23:02:11.226217  progress  10 % (0 MB)
  131 23:02:11.250860  progress  15 % (1 MB)
  132 23:02:11.275251  progress  20 % (1 MB)
  133 23:02:11.300287  progress  25 % (2 MB)
  134 23:02:11.326581  progress  30 % (2 MB)
  135 23:02:11.353112  progress  35 % (2 MB)
  136 23:02:11.376695  progress  40 % (3 MB)
  137 23:02:11.401979  progress  45 % (3 MB)
  138 23:02:11.428427  progress  50 % (4 MB)
  139 23:02:11.453291  progress  55 % (4 MB)
  140 23:02:11.479929  progress  60 % (4 MB)
  141 23:02:11.509005  progress  65 % (5 MB)
  142 23:02:11.539941  progress  70 % (5 MB)
  143 23:02:11.565484  progress  75 % (6 MB)
  144 23:02:11.593441  progress  80 % (6 MB)
  145 23:02:11.621890  progress  85 % (7 MB)
  146 23:02:11.649114  progress  90 % (7 MB)
  147 23:02:11.680054  progress  95 % (7 MB)
  148 23:02:11.708853  progress 100 % (8 MB)
  149 23:02:11.715308  8 MB downloaded in 0.54 s (15.22 MB/s)
  150 23:02:11.715586  end: 1.5.1 http-download (duration 00:00:01) [common]
  152 23:02:11.715859  end: 1.5 download-retry (duration 00:00:01) [common]
  153 23:02:11.715953  start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
  154 23:02:11.716049  start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
  155 23:02:13.951238  Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3
  156 23:02:13.951440  end: 1.6.1 extract-nfsrootfs (duration 00:00:02) [common]
  157 23:02:13.951545  start: 1.6.2 lava-overlay (timeout 00:09:50) [common]
  158 23:02:13.951714  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay
  159 23:02:13.951846  makedir: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin
  160 23:02:13.951947  makedir: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/tests
  161 23:02:13.952060  makedir: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/results
  162 23:02:13.952163  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-add-keys
  163 23:02:13.952309  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-add-sources
  164 23:02:13.952438  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-background-process-start
  165 23:02:13.952566  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-background-process-stop
  166 23:02:13.952692  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-common-functions
  167 23:02:13.952815  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-echo-ipv4
  168 23:02:13.952939  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-install-packages
  169 23:02:13.953063  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-installed-packages
  170 23:02:13.953185  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-os-build
  171 23:02:13.953308  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-probe-channel
  172 23:02:13.953429  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-probe-ip
  173 23:02:13.953552  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-target-ip
  174 23:02:13.953715  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-target-mac
  175 23:02:13.953839  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-target-storage
  176 23:02:13.953964  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-case
  177 23:02:13.954090  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-event
  178 23:02:13.954213  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-feedback
  179 23:02:13.954336  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-raise
  180 23:02:13.954461  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-reference
  181 23:02:13.954586  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-runner
  182 23:02:13.954709  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-set
  183 23:02:13.954833  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-test-shell
  184 23:02:13.954956  Updating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-install-packages (oe)
  185 23:02:13.955107  Updating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/bin/lava-installed-packages (oe)
  186 23:02:13.955226  Creating /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/environment
  187 23:02:13.955320  LAVA metadata
  188 23:02:13.955389  - LAVA_JOB_ID=12172473
  189 23:02:13.955450  - LAVA_DISPATCHER_IP=192.168.201.1
  190 23:02:13.955550  start: 1.6.2.1 lava-vland-overlay (timeout 00:09:50) [common]
  191 23:02:13.955614  skipped lava-vland-overlay
  192 23:02:13.955687  end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
  193 23:02:13.955763  start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:50) [common]
  194 23:02:13.955823  skipped lava-multinode-overlay
  195 23:02:13.955892  end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  196 23:02:13.955968  start: 1.6.2.3 test-definition (timeout 00:09:50) [common]
  197 23:02:13.956039  Loading test definitions
  198 23:02:13.956134  start: 1.6.2.3.1 inline-repo-action (timeout 00:09:50) [common]
  199 23:02:13.956204  Using /lava-12172473 at stage 0
  200 23:02:13.956507  uuid=12172473_1.6.2.3.1 testdef=None
  201 23:02:13.956594  end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
  202 23:02:13.956681  start: 1.6.2.3.2 test-overlay (timeout 00:09:50) [common]
  203 23:02:13.957182  end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
  205 23:02:13.957394  start: 1.6.2.3.3 test-install-overlay (timeout 00:09:50) [common]
  206 23:02:13.958045  end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
  208 23:02:13.958267  start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:50) [common]
  209 23:02:13.958876  runner path: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/0/tests/0_dmesg test_uuid 12172473_1.6.2.3.1
  210 23:02:13.959029  end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  212 23:02:13.959246  start: 1.6.2.3.5 inline-repo-action (timeout 00:09:50) [common]
  213 23:02:13.959316  Using /lava-12172473 at stage 1
  214 23:02:13.959616  uuid=12172473_1.6.2.3.5 testdef=None
  215 23:02:13.959701  end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
  216 23:02:13.959783  start: 1.6.2.3.6 test-overlay (timeout 00:09:50) [common]
  217 23:02:13.960240  end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
  219 23:02:13.960449  start: 1.6.2.3.7 test-install-overlay (timeout 00:09:50) [common]
  220 23:02:13.961103  end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
  222 23:02:13.961324  start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:50) [common]
  223 23:02:13.961955  runner path: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/1/tests/1_bootrr test_uuid 12172473_1.6.2.3.5
  224 23:02:13.962106  end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
  226 23:02:13.962301  Creating lava-test-runner.conf files
  227 23:02:13.962362  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/0 for stage 0
  228 23:02:13.962450  - 0_dmesg
  229 23:02:13.962527  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172473/lava-overlay-_xxid_ay/lava-12172473/1 for stage 1
  230 23:02:13.962628  - 1_bootrr
  231 23:02:13.962723  end: 1.6.2.3 test-definition (duration 00:00:00) [common]
  232 23:02:13.962808  start: 1.6.2.4 compress-overlay (timeout 00:09:50) [common]
  233 23:02:13.970243  end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
  234 23:02:13.970349  start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:50) [common]
  235 23:02:13.970433  end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  236 23:02:13.970517  end: 1.6.2 lava-overlay (duration 00:00:00) [common]
  237 23:02:13.970599  start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:50) [common]
  238 23:02:14.091694  end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
  239 23:02:14.092087  start: 1.6.4 extract-modules (timeout 00:09:50) [common]
  240 23:02:14.092217  extracting modules file /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3
  241 23:02:14.314690  extracting modules file /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172473/extract-overlay-ramdisk-zdgq8sbb/ramdisk
  242 23:02:14.543850  end: 1.6.4 extract-modules (duration 00:00:00) [common]
  243 23:02:14.544022  start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
  244 23:02:14.544126  [common] Applying overlay to NFS
  245 23:02:14.544198  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172473/compress-overlay-qyserx4h/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3
  246 23:02:14.552401  end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
  247 23:02:14.552526  start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
  248 23:02:14.552619  end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
  249 23:02:14.552707  start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
  250 23:02:14.552785  Building ramdisk /var/lib/lava/dispatcher/tmp/12172473/extract-overlay-ramdisk-zdgq8sbb/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172473/extract-overlay-ramdisk-zdgq8sbb/ramdisk
  251 23:02:14.896862  >> 119416 blocks

  252 23:02:16.878088  rename /var/lib/lava/dispatcher/tmp/12172473/extract-overlay-ramdisk-zdgq8sbb/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/ramdisk/ramdisk.cpio.gz
  253 23:02:16.878542  end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
  254 23:02:16.878663  start: 1.6.8 prepare-kernel (timeout 00:09:47) [common]
  255 23:02:16.878769  start: 1.6.8.1 prepare-fit (timeout 00:09:47) [common]
  256 23:02:16.878880  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/kernel/Image'
  257 23:02:29.350820  Returned 0 in 12 seconds
  258 23:02:29.451421  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/kernel/image.itb
  259 23:02:29.798306  output: FIT description: Kernel Image image with one or more FDT blobs
  260 23:02:29.798690  output: Created:         Sun Dec  3 23:02:29 2023
  261 23:02:29.798797  output:  Image 0 (kernel-1)
  262 23:02:29.798897  output:   Description:  
  263 23:02:29.798992  output:   Created:      Sun Dec  3 23:02:29 2023
  264 23:02:29.799082  output:   Type:         Kernel Image
  265 23:02:29.799181  output:   Compression:  lzma compressed
  266 23:02:29.799268  output:   Data Size:    11049348 Bytes = 10790.38 KiB = 10.54 MiB
  267 23:02:29.799377  output:   Architecture: AArch64
  268 23:02:29.799479  output:   OS:           Linux
  269 23:02:29.799565  output:   Load Address: 0x00000000
  270 23:02:29.799650  output:   Entry Point:  0x00000000
  271 23:02:29.799736  output:   Hash algo:    crc32
  272 23:02:29.799821  output:   Hash value:   c85ea8f0
  273 23:02:29.799909  output:  Image 1 (fdt-1)
  274 23:02:29.799992  output:   Description:  mt8192-asurada-spherion-r0
  275 23:02:29.800073  output:   Created:      Sun Dec  3 23:02:29 2023
  276 23:02:29.800155  output:   Type:         Flat Device Tree
  277 23:02:29.800236  output:   Compression:  uncompressed
  278 23:02:29.800317  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  279 23:02:29.800397  output:   Architecture: AArch64
  280 23:02:29.800477  output:   Hash algo:    crc32
  281 23:02:29.800558  output:   Hash value:   cc4352de
  282 23:02:29.800638  output:  Image 2 (ramdisk-1)
  283 23:02:29.800718  output:   Description:  unavailable
  284 23:02:29.800798  output:   Created:      Sun Dec  3 23:02:29 2023
  285 23:02:29.800879  output:   Type:         RAMDisk Image
  286 23:02:29.800959  output:   Compression:  Unknown Compression
  287 23:02:29.801040  output:   Data Size:    17793953 Bytes = 17376.91 KiB = 16.97 MiB
  288 23:02:29.801121  output:   Architecture: AArch64
  289 23:02:29.801201  output:   OS:           Linux
  290 23:02:29.801281  output:   Load Address: unavailable
  291 23:02:29.801361  output:   Entry Point:  unavailable
  292 23:02:29.801441  output:   Hash algo:    crc32
  293 23:02:29.801521  output:   Hash value:   484fd537
  294 23:02:29.801637  output:  Default Configuration: 'conf-1'
  295 23:02:29.801722  output:  Configuration 0 (conf-1)
  296 23:02:29.801774  output:   Description:  mt8192-asurada-spherion-r0
  297 23:02:29.801855  output:   Kernel:       kernel-1
  298 23:02:29.801907  output:   Init Ramdisk: ramdisk-1
  299 23:02:29.801958  output:   FDT:          fdt-1
  300 23:02:29.802009  output:   Loadables:    kernel-1
  301 23:02:29.802060  output: 
  302 23:02:29.802266  end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
  303 23:02:29.802362  end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
  304 23:02:29.802467  end: 1.6 prepare-tftp-overlay (duration 00:00:18) [common]
  305 23:02:29.802557  start: 1.7 lxc-create-udev-rule-action (timeout 00:09:34) [common]
  306 23:02:29.802638  No LXC device requested
  307 23:02:29.802715  end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
  308 23:02:29.802799  start: 1.8 deploy-device-env (timeout 00:09:34) [common]
  309 23:02:29.802873  end: 1.8 deploy-device-env (duration 00:00:00) [common]
  310 23:02:29.802940  Checking files for TFTP limit of 4294967296 bytes.
  311 23:02:29.803529  end: 1 tftp-deploy (duration 00:00:26) [common]
  312 23:02:29.803635  start: 2 depthcharge-action (timeout 00:05:00) [common]
  313 23:02:29.803724  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  314 23:02:29.803853  substitutions:
  315 23:02:29.803919  - {DTB}: 12172473/tftp-deploy-msudd3vb/dtb/mt8192-asurada-spherion-r0.dtb
  316 23:02:29.803982  - {INITRD}: 12172473/tftp-deploy-msudd3vb/ramdisk/ramdisk.cpio.gz
  317 23:02:29.804043  - {KERNEL}: 12172473/tftp-deploy-msudd3vb/kernel/Image
  318 23:02:29.804099  - {LAVA_MAC}: None
  319 23:02:29.804158  - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3
  320 23:02:29.804213  - {NFS_SERVER_IP}: 192.168.201.1
  321 23:02:29.804268  - {PRESEED_CONFIG}: None
  322 23:02:29.804323  - {PRESEED_LOCAL}: None
  323 23:02:29.804377  - {RAMDISK}: 12172473/tftp-deploy-msudd3vb/ramdisk/ramdisk.cpio.gz
  324 23:02:29.804431  - {ROOT_PART}: None
  325 23:02:29.804487  - {ROOT}: None
  326 23:02:29.804541  - {SERVER_IP}: 192.168.201.1
  327 23:02:29.804594  - {TEE}: None
  328 23:02:29.804646  Parsed boot commands:
  329 23:02:29.804698  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  330 23:02:29.804885  Parsed boot commands: tftpboot 192.168.201.1 12172473/tftp-deploy-msudd3vb/kernel/image.itb 12172473/tftp-deploy-msudd3vb/kernel/cmdline 
  331 23:02:29.804973  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  332 23:02:29.805057  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  333 23:02:29.805148  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  334 23:02:29.805234  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  335 23:02:29.805303  Not connected, no need to disconnect.
  336 23:02:29.805410  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  337 23:02:29.805535  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  338 23:02:29.805665  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
  339 23:02:29.809878  Setting prompt string to ['lava-test: # ']
  340 23:02:29.810341  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  341 23:02:29.810502  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  342 23:02:29.810662  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  343 23:02:29.810811  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  344 23:02:29.811186  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
  345 23:02:34.946439  >> Command sent successfully.

  346 23:02:34.948847  Returned 0 in 5 seconds
  347 23:02:35.049206  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  349 23:02:35.049507  end: 2.2.2 reset-device (duration 00:00:05) [common]
  350 23:02:35.049655  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  351 23:02:35.049748  Setting prompt string to 'Starting depthcharge on Spherion...'
  352 23:02:35.049818  Changing prompt to 'Starting depthcharge on Spherion...'
  353 23:02:35.049891  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  354 23:02:35.050159  [Enter `^Ec?' for help]

  355 23:02:35.222099  

  356 23:02:35.222231  

  357 23:02:35.222304  F0: 102B 0000

  358 23:02:35.222370  

  359 23:02:35.226076  F3: 1001 0000 [0200]

  360 23:02:35.226160  

  361 23:02:35.226226  F3: 1001 0000

  362 23:02:35.226287  

  363 23:02:35.226344  F7: 102D 0000

  364 23:02:35.226401  

  365 23:02:35.226457  F1: 0000 0000

  366 23:02:35.229964  

  367 23:02:35.230046  V0: 0000 0000 [0001]

  368 23:02:35.230115  

  369 23:02:35.230176  00: 0007 8000

  370 23:02:35.230240  

  371 23:02:35.233174  01: 0000 0000

  372 23:02:35.233258  

  373 23:02:35.233324  BP: 0C00 0209 [0000]

  374 23:02:35.233384  

  375 23:02:35.237029  G0: 1182 0000

  376 23:02:35.237111  

  377 23:02:35.237175  EC: 0000 0021 [4000]

  378 23:02:35.237236  

  379 23:02:35.240400  S7: 0000 0000 [0000]

  380 23:02:35.240483  

  381 23:02:35.240548  CC: 0000 0000 [0001]

  382 23:02:35.240608  

  383 23:02:35.243932  T0: 0000 0040 [010F]

  384 23:02:35.244015  

  385 23:02:35.244081  Jump to BL

  386 23:02:35.244142  

  387 23:02:35.269496  

  388 23:02:35.269653  

  389 23:02:35.269724  

  390 23:02:35.276499  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  391 23:02:35.280577  ARM64: Exception handlers installed.

  392 23:02:35.284407  ARM64: Testing exception

  393 23:02:35.288066  ARM64: Done test exception

  394 23:02:35.295099  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  395 23:02:35.302301  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  396 23:02:35.309469  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  397 23:02:35.320086  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  398 23:02:35.326544  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  399 23:02:35.337127  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  400 23:02:35.347881  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  401 23:02:35.354216  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  402 23:02:35.372137  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  403 23:02:35.375356  WDT: Last reset was cold boot

  404 23:02:35.378796  SPI1(PAD0) initialized at 2873684 Hz

  405 23:02:35.382469  SPI5(PAD0) initialized at 992727 Hz

  406 23:02:35.386038  VBOOT: Loading verstage.

  407 23:02:35.392369  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  408 23:02:35.396896  FMAP: Found "FLASH" version 1.1 at 0x20000.

  409 23:02:35.399836  FMAP: base = 0x0 size = 0x800000 #areas = 25

  410 23:02:35.403292  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  411 23:02:35.410044  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  412 23:02:35.416375  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  413 23:02:35.427585  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  414 23:02:35.427678  

  415 23:02:35.427744  

  416 23:02:35.437479  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  417 23:02:35.440817  ARM64: Exception handlers installed.

  418 23:02:35.444298  ARM64: Testing exception

  419 23:02:35.444386  ARM64: Done test exception

  420 23:02:35.450942  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  421 23:02:35.454277  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  422 23:02:35.467923  Probing TPM: . done!

  423 23:02:35.468018  TPM ready after 0 ms

  424 23:02:35.475920  Connected to device vid:did:rid of 1ae0:0028:00

  425 23:02:35.482545  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  426 23:02:35.541973  Initialized TPM device CR50 revision 0

  427 23:02:35.553074  tlcl_send_startup: Startup return code is 0

  428 23:02:35.553197  TPM: setup succeeded

  429 23:02:35.564808  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  430 23:02:35.573381  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  431 23:02:35.587185  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  432 23:02:35.594596  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  433 23:02:35.597546  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  434 23:02:35.601736  in-header: 03 07 00 00 08 00 00 00 

  435 23:02:35.605459  in-data: aa e4 47 04 13 02 00 00 

  436 23:02:35.608746  Chrome EC: UHEPI supported

  437 23:02:35.615850  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  438 23:02:35.619847  in-header: 03 95 00 00 08 00 00 00 

  439 23:02:35.623470  in-data: 18 20 20 08 00 00 00 00 

  440 23:02:35.623554  Phase 1

  441 23:02:35.627660  FMAP: area GBB found @ 3f5000 (12032 bytes)

  442 23:02:35.631450  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  443 23:02:35.639070  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  444 23:02:35.641936  Recovery requested (1009000e)

  445 23:02:35.650571  TPM: Extending digest for VBOOT: boot mode into PCR 0

  446 23:02:35.656045  tlcl_extend: response is 0

  447 23:02:35.664975  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  448 23:02:35.670632  tlcl_extend: response is 0

  449 23:02:35.677791  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  450 23:02:35.697797  read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps

  451 23:02:35.703878  BS: bootblock times (exec / console): total (unknown) / 148 ms

  452 23:02:35.703963  

  453 23:02:35.704029  

  454 23:02:35.713921  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  455 23:02:35.717786  ARM64: Exception handlers installed.

  456 23:02:35.720771  ARM64: Testing exception

  457 23:02:35.720854  ARM64: Done test exception

  458 23:02:35.743450  pmic_efuse_setting: Set efuses in 11 msecs

  459 23:02:35.746328  pmwrap_interface_init: Select PMIF_VLD_RDY

  460 23:02:35.753078  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  461 23:02:35.756629  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  462 23:02:35.764182  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  463 23:02:35.767601  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  464 23:02:35.771245  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  465 23:02:35.775390  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  466 23:02:35.782779  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  467 23:02:35.786942  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  468 23:02:35.790729  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  469 23:02:35.794725  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  470 23:02:35.801560  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  471 23:02:35.805364  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  472 23:02:35.809481  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  473 23:02:35.816715  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  474 23:02:35.820469  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  475 23:02:35.828061  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  476 23:02:35.831641  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  477 23:02:35.839765  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  478 23:02:35.843072  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  479 23:02:35.850635  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  480 23:02:35.854174  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  481 23:02:35.861776  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  482 23:02:35.865139  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  483 23:02:35.872984  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  484 23:02:35.876792  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  485 23:02:35.883672  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  486 23:02:35.887665  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  487 23:02:35.891250  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  488 23:02:35.898603  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  489 23:02:35.902287  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  490 23:02:35.906237  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  491 23:02:35.913381  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  492 23:02:35.917099  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  493 23:02:35.921001  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  494 23:02:35.928047  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  495 23:02:35.931784  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  496 23:02:35.935986  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  497 23:02:35.943035  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  498 23:02:35.946760  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  499 23:02:35.950424  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  500 23:02:35.954013  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  501 23:02:35.961702  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  502 23:02:35.964826  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  503 23:02:35.968760  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  504 23:02:35.972541  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  505 23:02:35.976318  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  506 23:02:35.979843  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  507 23:02:35.987405  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  508 23:02:35.990577  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  509 23:02:35.994365  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  510 23:02:35.998255  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  511 23:02:36.005796  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  512 23:02:36.013306  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  513 23:02:36.021398  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  514 23:02:36.028077  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  515 23:02:36.035585  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  516 23:02:36.039305  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  517 23:02:36.043481  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  518 23:02:36.050449  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  519 23:02:36.054552  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0

  520 23:02:36.062287  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  521 23:02:36.065840  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  522 23:02:36.069115  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  523 23:02:36.080687  [RTC]rtc_get_frequency_meter,154: input=15, output=760

  524 23:02:36.090435  [RTC]rtc_get_frequency_meter,154: input=23, output=943

  525 23:02:36.099594  [RTC]rtc_get_frequency_meter,154: input=19, output=851

  526 23:02:36.109123  [RTC]rtc_get_frequency_meter,154: input=17, output=804

  527 23:02:36.118904  [RTC]rtc_get_frequency_meter,154: input=16, output=783

  528 23:02:36.128057  [RTC]rtc_get_frequency_meter,154: input=16, output=782

  529 23:02:36.138177  [RTC]rtc_get_frequency_meter,154: input=17, output=804

  530 23:02:36.141755  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  531 23:02:36.148923  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  532 23:02:36.152785  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  533 23:02:36.156688  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  534 23:02:36.159564  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  535 23:02:36.163471  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  536 23:02:36.167194  ADC[4]: Raw value=906203 ID=7

  537 23:02:36.170971  ADC[3]: Raw value=213441 ID=1

  538 23:02:36.171078  RAM Code: 0x71

  539 23:02:36.174497  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  540 23:02:36.182378  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  541 23:02:36.190015  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  542 23:02:36.197090  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  543 23:02:36.197174  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  544 23:02:36.201573  in-header: 03 07 00 00 08 00 00 00 

  545 23:02:36.205494  in-data: aa e4 47 04 13 02 00 00 

  546 23:02:36.209415  Chrome EC: UHEPI supported

  547 23:02:36.216630  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  548 23:02:36.220371  in-header: 03 95 00 00 08 00 00 00 

  549 23:02:36.220453  in-data: 18 20 20 08 00 00 00 00 

  550 23:02:36.224399  MRC: failed to locate region type 0.

  551 23:02:36.231436  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  552 23:02:36.235164  DRAM-K: Running full calibration

  553 23:02:36.239271  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  554 23:02:36.243303  header.status = 0x0

  555 23:02:36.247139  header.version = 0x6 (expected: 0x6)

  556 23:02:36.250502  header.size = 0xd00 (expected: 0xd00)

  557 23:02:36.250585  header.flags = 0x0

  558 23:02:36.257917  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  559 23:02:36.276095  read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps

  560 23:02:36.283328  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  561 23:02:36.283413  dram_init: ddr_geometry: 2

  562 23:02:36.287353  [EMI] MDL number = 2

  563 23:02:36.287461  [EMI] Get MDL freq = 0

  564 23:02:36.290241  dram_init: ddr_type: 0

  565 23:02:36.294458  is_discrete_lpddr4: 1

  566 23:02:36.294539  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  567 23:02:36.297962  

  568 23:02:36.298044  

  569 23:02:36.298109  [Bian_co] ETT version 0.0.0.1

  570 23:02:36.302091   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  571 23:02:36.306206  

  572 23:02:36.306287  dramc_set_vcore_voltage set vcore to 650000

  573 23:02:36.309442  Read voltage for 800, 4

  574 23:02:36.309523  Vio18 = 0

  575 23:02:36.313521  Vcore = 650000

  576 23:02:36.313640  Vdram = 0

  577 23:02:36.313706  Vddq = 0

  578 23:02:36.313766  Vmddr = 0

  579 23:02:36.317029  dram_init: config_dvfs: 1

  580 23:02:36.327746  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  581 23:02:36.328079  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  582 23:02:36.331287  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  583 23:02:36.334992  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  584 23:02:36.338851  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  585 23:02:36.342435  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  586 23:02:36.345271  MEM_TYPE=3, freq_sel=18

  587 23:02:36.348807  sv_algorithm_assistance_LP4_1600 

  588 23:02:36.352191  ============ PULL DRAM RESETB DOWN ============

  589 23:02:36.355571  ========== PULL DRAM RESETB DOWN end =========

  590 23:02:36.363058  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  591 23:02:36.363143  =================================== 

  592 23:02:36.366675  LPDDR4 DRAM CONFIGURATION

  593 23:02:36.370602  =================================== 

  594 23:02:36.370694  EX_ROW_EN[0]    = 0x0

  595 23:02:36.373836  EX_ROW_EN[1]    = 0x0

  596 23:02:36.373920  LP4Y_EN      = 0x0

  597 23:02:36.377528  WORK_FSP     = 0x0

  598 23:02:36.377678  WL           = 0x2

  599 23:02:36.380975  RL           = 0x2

  600 23:02:36.381090  BL           = 0x2

  601 23:02:36.384602  RPST         = 0x0

  602 23:02:36.384702  RD_PRE       = 0x0

  603 23:02:36.388048  WR_PRE       = 0x1

  604 23:02:36.388149  WR_PST       = 0x0

  605 23:02:36.391279  DBI_WR       = 0x0

  606 23:02:36.391353  DBI_RD       = 0x0

  607 23:02:36.394694  OTF          = 0x1

  608 23:02:36.397546  =================================== 

  609 23:02:36.401614  =================================== 

  610 23:02:36.401709  ANA top config

  611 23:02:36.405128  =================================== 

  612 23:02:36.408498  DLL_ASYNC_EN            =  0

  613 23:02:36.412350  ALL_SLAVE_EN            =  1

  614 23:02:36.412432  NEW_RANK_MODE           =  1

  615 23:02:36.415347  DLL_IDLE_MODE           =  1

  616 23:02:36.418666  LP45_APHY_COMB_EN       =  1

  617 23:02:36.422154  TX_ODT_DIS              =  1

  618 23:02:36.422236  NEW_8X_MODE             =  1

  619 23:02:36.426327  =================================== 

  620 23:02:36.429834  =================================== 

  621 23:02:36.433374  data_rate                  = 1600

  622 23:02:36.436670  CKR                        = 1

  623 23:02:36.440119  DQ_P2S_RATIO               = 8

  624 23:02:36.442847  =================================== 

  625 23:02:36.446451  CA_P2S_RATIO               = 8

  626 23:02:36.446533  DQ_CA_OPEN                 = 0

  627 23:02:36.449843  DQ_SEMI_OPEN               = 0

  628 23:02:36.452885  CA_SEMI_OPEN               = 0

  629 23:02:36.456403  CA_FULL_RATE               = 0

  630 23:02:36.459682  DQ_CKDIV4_EN               = 1

  631 23:02:36.459804  CA_CKDIV4_EN               = 1

  632 23:02:36.463061  CA_PREDIV_EN               = 0

  633 23:02:36.466728  PH8_DLY                    = 0

  634 23:02:36.469765  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  635 23:02:36.473223  DQ_AAMCK_DIV               = 4

  636 23:02:36.476948  CA_AAMCK_DIV               = 4

  637 23:02:36.477066  CA_ADMCK_DIV               = 4

  638 23:02:36.479657  DQ_TRACK_CA_EN             = 0

  639 23:02:36.483059  CA_PICK                    = 800

  640 23:02:36.486645  CA_MCKIO                   = 800

  641 23:02:36.489951  MCKIO_SEMI                 = 0

  642 23:02:36.494013  PLL_FREQ                   = 3068

  643 23:02:36.494093  DQ_UI_PI_RATIO             = 32

  644 23:02:36.497347  CA_UI_PI_RATIO             = 0

  645 23:02:36.501343  =================================== 

  646 23:02:36.504799  =================================== 

  647 23:02:36.508497  memory_type:LPDDR4         

  648 23:02:36.508604  GP_NUM     : 10       

  649 23:02:36.512931  SRAM_EN    : 1       

  650 23:02:36.513035  MD32_EN    : 0       

  651 23:02:36.517052  =================================== 

  652 23:02:36.520485  [ANA_INIT] >>>>>>>>>>>>>> 

  653 23:02:36.520593  <<<<<< [CONFIGURE PHASE]: ANA_TX

  654 23:02:36.524606  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  655 23:02:36.527498  =================================== 

  656 23:02:36.530855  data_rate = 1600,PCW = 0X7600

  657 23:02:36.533953  =================================== 

  658 23:02:36.538018  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  659 23:02:36.544287  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  660 23:02:36.547362  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  661 23:02:36.554300  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  662 23:02:36.557334  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  663 23:02:36.560851  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  664 23:02:36.560934  [ANA_INIT] flow start 

  665 23:02:36.564455  [ANA_INIT] PLL >>>>>>>> 

  666 23:02:36.567564  [ANA_INIT] PLL <<<<<<<< 

  667 23:02:36.567672  [ANA_INIT] MIDPI >>>>>>>> 

  668 23:02:36.570887  [ANA_INIT] MIDPI <<<<<<<< 

  669 23:02:36.574325  [ANA_INIT] DLL >>>>>>>> 

  670 23:02:36.574404  [ANA_INIT] flow end 

  671 23:02:36.581365  ============ LP4 DIFF to SE enter ============

  672 23:02:36.584656  ============ LP4 DIFF to SE exit  ============

  673 23:02:36.587545  [ANA_INIT] <<<<<<<<<<<<< 

  674 23:02:36.591186  [Flow] Enable top DCM control >>>>> 

  675 23:02:36.594437  [Flow] Enable top DCM control <<<<< 

  676 23:02:36.594518  Enable DLL master slave shuffle 

  677 23:02:36.601261  ============================================================== 

  678 23:02:36.604844  Gating Mode config

  679 23:02:36.608044  ============================================================== 

  680 23:02:36.611110  Config description: 

  681 23:02:36.621289  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  682 23:02:36.628031  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  683 23:02:36.631341  SELPH_MODE            0: By rank         1: By Phase 

  684 23:02:36.637950  ============================================================== 

  685 23:02:36.641391  GAT_TRACK_EN                 =  1

  686 23:02:36.644926  RX_GATING_MODE               =  2

  687 23:02:36.645008  RX_GATING_TRACK_MODE         =  2

  688 23:02:36.647839  SELPH_MODE                   =  1

  689 23:02:36.651258  PICG_EARLY_EN                =  1

  690 23:02:36.654735  VALID_LAT_VALUE              =  1

  691 23:02:36.661336  ============================================================== 

  692 23:02:36.664720  Enter into Gating configuration >>>> 

  693 23:02:36.667896  Exit from Gating configuration <<<< 

  694 23:02:36.671162  Enter into  DVFS_PRE_config >>>>> 

  695 23:02:36.681422  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  696 23:02:36.684863  Exit from  DVFS_PRE_config <<<<< 

  697 23:02:36.687836  Enter into PICG configuration >>>> 

  698 23:02:36.691581  Exit from PICG configuration <<<< 

  699 23:02:36.694742  [RX_INPUT] configuration >>>>> 

  700 23:02:36.698047  [RX_INPUT] configuration <<<<< 

  701 23:02:36.701766  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  702 23:02:36.708341  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  703 23:02:36.711816  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  704 23:02:36.718561  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  705 23:02:36.725076  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  706 23:02:36.731485  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  707 23:02:36.734915  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  708 23:02:36.738217  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  709 23:02:36.745254  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  710 23:02:36.748184  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  711 23:02:36.751533  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  712 23:02:36.755108  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  713 23:02:36.758671  =================================== 

  714 23:02:36.762196  LPDDR4 DRAM CONFIGURATION

  715 23:02:36.765150  =================================== 

  716 23:02:36.768485  EX_ROW_EN[0]    = 0x0

  717 23:02:36.768584  EX_ROW_EN[1]    = 0x0

  718 23:02:36.771967  LP4Y_EN      = 0x0

  719 23:02:36.772074  WORK_FSP     = 0x0

  720 23:02:36.775553  WL           = 0x2

  721 23:02:36.775663  RL           = 0x2

  722 23:02:36.778837  BL           = 0x2

  723 23:02:36.778912  RPST         = 0x0

  724 23:02:36.781984  RD_PRE       = 0x0

  725 23:02:36.782053  WR_PRE       = 0x1

  726 23:02:36.785347  WR_PST       = 0x0

  727 23:02:36.788564  DBI_WR       = 0x0

  728 23:02:36.788666  DBI_RD       = 0x0

  729 23:02:36.791974  OTF          = 0x1

  730 23:02:36.795135  =================================== 

  731 23:02:36.798430  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  732 23:02:36.801992  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  733 23:02:36.805318  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  734 23:02:36.808602  =================================== 

  735 23:02:36.811542  LPDDR4 DRAM CONFIGURATION

  736 23:02:36.815042  =================================== 

  737 23:02:36.818543  EX_ROW_EN[0]    = 0x10

  738 23:02:36.818625  EX_ROW_EN[1]    = 0x0

  739 23:02:36.821469  LP4Y_EN      = 0x0

  740 23:02:36.821600  WORK_FSP     = 0x0

  741 23:02:36.824931  WL           = 0x2

  742 23:02:36.825038  RL           = 0x2

  743 23:02:36.828262  BL           = 0x2

  744 23:02:36.828362  RPST         = 0x0

  745 23:02:36.831695  RD_PRE       = 0x0

  746 23:02:36.831768  WR_PRE       = 0x1

  747 23:02:36.835254  WR_PST       = 0x0

  748 23:02:36.835336  DBI_WR       = 0x0

  749 23:02:36.838212  DBI_RD       = 0x0

  750 23:02:36.838284  OTF          = 0x1

  751 23:02:36.841784  =================================== 

  752 23:02:36.848026  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  753 23:02:36.853273  nWR fixed to 40

  754 23:02:36.856574  [ModeRegInit_LP4] CH0 RK0

  755 23:02:36.856677  [ModeRegInit_LP4] CH0 RK1

  756 23:02:36.860022  [ModeRegInit_LP4] CH1 RK0

  757 23:02:36.862909  [ModeRegInit_LP4] CH1 RK1

  758 23:02:36.863008  match AC timing 13

  759 23:02:36.869479  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  760 23:02:36.872893  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  761 23:02:36.876348  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  762 23:02:36.883253  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  763 23:02:36.886614  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  764 23:02:36.886719  [EMI DOE] emi_dcm 0

  765 23:02:36.893534  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  766 23:02:36.893676  ==

  767 23:02:36.896456  Dram Type= 6, Freq= 0, CH_0, rank 0

  768 23:02:36.899935  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  769 23:02:36.900037  ==

  770 23:02:36.906657  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  771 23:02:36.909933  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  772 23:02:36.921186  [CA 0] Center 36 (6~67) winsize 62

  773 23:02:36.924062  [CA 1] Center 36 (6~67) winsize 62

  774 23:02:36.927171  [CA 2] Center 34 (4~65) winsize 62

  775 23:02:36.930539  [CA 3] Center 33 (3~64) winsize 62

  776 23:02:36.934136  [CA 4] Center 33 (3~63) winsize 61

  777 23:02:36.937062  [CA 5] Center 32 (3~62) winsize 60

  778 23:02:36.937167  

  779 23:02:36.940497  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  780 23:02:36.940595  

  781 23:02:36.944081  [CATrainingPosCal] consider 1 rank data

  782 23:02:36.946968  u2DelayCellTimex100 = 270/100 ps

  783 23:02:36.950485  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  784 23:02:36.954151  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  785 23:02:36.960729  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  786 23:02:36.964007  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  787 23:02:36.967121  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  788 23:02:36.970683  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  789 23:02:36.970768  

  790 23:02:36.973723  CA PerBit enable=1, Macro0, CA PI delay=32

  791 23:02:36.973796  

  792 23:02:36.977451  [CBTSetCACLKResult] CA Dly = 32

  793 23:02:36.977562  CS Dly: 4 (0~35)

  794 23:02:36.977679  ==

  795 23:02:36.980446  Dram Type= 6, Freq= 0, CH_0, rank 1

  796 23:02:36.987519  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  797 23:02:36.987596  ==

  798 23:02:36.990523  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  799 23:02:36.997270  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  800 23:02:37.006672  [CA 0] Center 36 (6~67) winsize 62

  801 23:02:37.010113  [CA 1] Center 36 (6~67) winsize 62

  802 23:02:37.013563  [CA 2] Center 34 (4~64) winsize 61

  803 23:02:37.016903  [CA 3] Center 33 (3~64) winsize 62

  804 23:02:37.020275  [CA 4] Center 32 (2~63) winsize 62

  805 23:02:37.023188  [CA 5] Center 32 (2~63) winsize 62

  806 23:02:37.023270  

  807 23:02:37.026778  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  808 23:02:37.026874  

  809 23:02:37.030137  [CATrainingPosCal] consider 2 rank data

  810 23:02:37.033350  u2DelayCellTimex100 = 270/100 ps

  811 23:02:37.036645  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  812 23:02:37.040196  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  813 23:02:37.046677  CA2 delay=34 (4~64),Diff = 2 PI (14 cell)

  814 23:02:37.050247  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  815 23:02:37.053529  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  816 23:02:37.056976  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  817 23:02:37.057085  

  818 23:02:37.060212  CA PerBit enable=1, Macro0, CA PI delay=32

  819 23:02:37.060310  

  820 23:02:37.063586  [CBTSetCACLKResult] CA Dly = 32

  821 23:02:37.063689  CS Dly: 5 (0~37)

  822 23:02:37.063779  

  823 23:02:37.067058  ----->DramcWriteLeveling(PI) begin...

  824 23:02:37.067159  ==

  825 23:02:37.070447  Dram Type= 6, Freq= 0, CH_0, rank 0

  826 23:02:37.074402  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  827 23:02:37.078676  ==

  828 23:02:37.078758  Write leveling (Byte 0): 33 => 33

  829 23:02:37.082018  Write leveling (Byte 1): 30 => 30

  830 23:02:37.085744  DramcWriteLeveling(PI) end<-----

  831 23:02:37.085825  

  832 23:02:37.085889  ==

  833 23:02:37.089087  Dram Type= 6, Freq= 0, CH_0, rank 0

  834 23:02:37.092416  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  835 23:02:37.092524  ==

  836 23:02:37.095987  [Gating] SW mode calibration

  837 23:02:37.103155  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  838 23:02:37.106522  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  839 23:02:37.112943   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  840 23:02:37.116375   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  841 23:02:37.119844   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  842 23:02:37.126391   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  843 23:02:37.130052   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  844 23:02:37.133486   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  845 23:02:37.140186   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  846 23:02:37.143485   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  847 23:02:37.146861   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  848 23:02:37.152911   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  849 23:02:37.156605   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  850 23:02:37.160079   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  851 23:02:37.166280   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  852 23:02:37.169916   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  853 23:02:37.173276   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  854 23:02:37.179949   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  855 23:02:37.183214   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  856 23:02:37.186652   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  857 23:02:37.190114   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

  858 23:02:37.196510   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  859 23:02:37.200137   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  860 23:02:37.203612   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  861 23:02:37.209822   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  862 23:02:37.213195   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  863 23:02:37.216641   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  864 23:02:37.223708   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  865 23:02:37.226847   0  9  8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)

  866 23:02:37.230091   0  9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

  867 23:02:37.237013   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  868 23:02:37.240067   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  869 23:02:37.243386   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  870 23:02:37.250440   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  871 23:02:37.253336   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  872 23:02:37.256928   0 10  4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

  873 23:02:37.263282   0 10  8 | B1->B0 | 3333 2727 | 0 0 | (0 1) (1 1)

  874 23:02:37.266958   0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

  875 23:02:37.270445   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  876 23:02:37.273481   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  877 23:02:37.279948   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  878 23:02:37.283302   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  879 23:02:37.286710   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  880 23:02:37.293423   0 11  4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)

  881 23:02:37.296808   0 11  8 | B1->B0 | 2e2e 3b3b | 0 1 | (0 0) (0 0)

  882 23:02:37.300178   0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

  883 23:02:37.306558   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  884 23:02:37.310283   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  885 23:02:37.313853   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  886 23:02:37.320763   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  887 23:02:37.323569   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  888 23:02:37.327179   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  889 23:02:37.333883   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  890 23:02:37.337035   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  891 23:02:37.340389   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  892 23:02:37.344022   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  893 23:02:37.350331   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  894 23:02:37.353707   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  895 23:02:37.357271   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  896 23:02:37.363654   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  897 23:02:37.367049   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  898 23:02:37.370529   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  899 23:02:37.376961   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  900 23:02:37.380560   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  901 23:02:37.383915   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  902 23:02:37.390535   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  903 23:02:37.393854   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  904 23:02:37.397347   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  905 23:02:37.403651   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  906 23:02:37.403757  Total UI for P1: 0, mck2ui 16

  907 23:02:37.410808  best dqsien dly found for B0: ( 0, 14,  6)

  908 23:02:37.414116   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  909 23:02:37.417104  Total UI for P1: 0, mck2ui 16

  910 23:02:37.420950  best dqsien dly found for B1: ( 0, 14,  8)

  911 23:02:37.424470  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  912 23:02:37.427746  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

  913 23:02:37.427821  

  914 23:02:37.431060  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  915 23:02:37.434362  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

  916 23:02:37.438000  [Gating] SW calibration Done

  917 23:02:37.438078  ==

  918 23:02:37.441466  Dram Type= 6, Freq= 0, CH_0, rank 0

  919 23:02:37.444776  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  920 23:02:37.444853  ==

  921 23:02:37.447993  RX Vref Scan: 0

  922 23:02:37.448102  

  923 23:02:37.448235  RX Vref 0 -> 0, step: 1

  924 23:02:37.448324  

  925 23:02:37.451329  RX Delay -130 -> 252, step: 16

  926 23:02:37.454298  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

  927 23:02:37.461274  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  928 23:02:37.464398  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  929 23:02:37.467934  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  930 23:02:37.471322  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  931 23:02:37.474385  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  932 23:02:37.480892  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

  933 23:02:37.484348  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  934 23:02:37.487690  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

  935 23:02:37.491198  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  936 23:02:37.494748  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

  937 23:02:37.501026  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  938 23:02:37.504910  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

  939 23:02:37.507705  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

  940 23:02:37.511184  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

  941 23:02:37.514758  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

  942 23:02:37.518075  ==

  943 23:02:37.518172  Dram Type= 6, Freq= 0, CH_0, rank 0

  944 23:02:37.524461  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  945 23:02:37.524569  ==

  946 23:02:37.524661  DQS Delay:

  947 23:02:37.527948  DQS0 = 0, DQS1 = 0

  948 23:02:37.528021  DQM Delay:

  949 23:02:37.530942  DQM0 = 90, DQM1 = 85

  950 23:02:37.531061  DQ Delay:

  951 23:02:37.534666  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

  952 23:02:37.537886  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101

  953 23:02:37.541061  DQ8 =77, DQ9 =69, DQ10 =85, DQ11 =77

  954 23:02:37.544359  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

  955 23:02:37.544458  

  956 23:02:37.544546  

  957 23:02:37.544641  ==

  958 23:02:37.547674  Dram Type= 6, Freq= 0, CH_0, rank 0

  959 23:02:37.551525  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  960 23:02:37.551602  ==

  961 23:02:37.551664  

  962 23:02:37.551721  

  963 23:02:37.554558  	TX Vref Scan disable

  964 23:02:37.557913   == TX Byte 0 ==

  965 23:02:37.561730  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  966 23:02:37.565142  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  967 23:02:37.565223   == TX Byte 1 ==

  968 23:02:37.571651  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  969 23:02:37.574803  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  970 23:02:37.574884  ==

  971 23:02:37.578415  Dram Type= 6, Freq= 0, CH_0, rank 0

  972 23:02:37.581379  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  973 23:02:37.581487  ==

  974 23:02:37.595587  TX Vref=22, minBit 10, minWin=27, winSum=449

  975 23:02:37.599158  TX Vref=24, minBit 14, minWin=27, winSum=452

  976 23:02:37.602681  TX Vref=26, minBit 7, minWin=28, winSum=455

  977 23:02:37.606057  TX Vref=28, minBit 5, minWin=28, winSum=458

  978 23:02:37.609111  TX Vref=30, minBit 8, minWin=28, winSum=458

  979 23:02:37.616026  TX Vref=32, minBit 1, minWin=28, winSum=454

  980 23:02:37.619271  [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 28

  981 23:02:37.619346  

  982 23:02:37.622591  Final TX Range 1 Vref 28

  983 23:02:37.622664  

  984 23:02:37.622724  ==

  985 23:02:37.626207  Dram Type= 6, Freq= 0, CH_0, rank 0

  986 23:02:37.629186  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  987 23:02:37.629289  ==

  988 23:02:37.629352  

  989 23:02:37.632537  

  990 23:02:37.632617  	TX Vref Scan disable

  991 23:02:37.635988   == TX Byte 0 ==

  992 23:02:37.638929  Update DQ  dly =583 (2 ,1, 39)  DQ  OEN =(1 ,6)

  993 23:02:37.642383  Update DQM dly =583 (2 ,1, 39)  DQM OEN =(1 ,6)

  994 23:02:37.645829   == TX Byte 1 ==

  995 23:02:37.649376  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

  996 23:02:37.652719  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

  997 23:02:37.655653  

  998 23:02:37.655751  [DATLAT]

  999 23:02:37.655840  Freq=800, CH0 RK0

 1000 23:02:37.655935  

 1001 23:02:37.658994  DATLAT Default: 0xa

 1002 23:02:37.659090  0, 0xFFFF, sum = 0

 1003 23:02:37.662593  1, 0xFFFF, sum = 0

 1004 23:02:37.662693  2, 0xFFFF, sum = 0

 1005 23:02:37.666095  3, 0xFFFF, sum = 0

 1006 23:02:37.666209  4, 0xFFFF, sum = 0

 1007 23:02:37.668974  5, 0xFFFF, sum = 0

 1008 23:02:37.672314  6, 0xFFFF, sum = 0

 1009 23:02:37.672422  7, 0xFFFF, sum = 0

 1010 23:02:37.676025  8, 0xFFFF, sum = 0

 1011 23:02:37.676104  9, 0x0, sum = 1

 1012 23:02:37.676167  10, 0x0, sum = 2

 1013 23:02:37.679391  11, 0x0, sum = 3

 1014 23:02:37.679494  12, 0x0, sum = 4

 1015 23:02:37.682355  best_step = 10

 1016 23:02:37.682456  

 1017 23:02:37.682549  ==

 1018 23:02:37.685889  Dram Type= 6, Freq= 0, CH_0, rank 0

 1019 23:02:37.689119  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1020 23:02:37.689219  ==

 1021 23:02:37.692403  RX Vref Scan: 1

 1022 23:02:37.692499  

 1023 23:02:37.692586  Set Vref Range= 32 -> 127

 1024 23:02:37.695484  

 1025 23:02:37.695584  RX Vref 32 -> 127, step: 1

 1026 23:02:37.695681  

 1027 23:02:37.699290  RX Delay -95 -> 252, step: 8

 1028 23:02:37.699364  

 1029 23:02:37.702120  Set Vref, RX VrefLevel [Byte0]: 32

 1030 23:02:37.705682                           [Byte1]: 32

 1031 23:02:37.705762  

 1032 23:02:37.709031  Set Vref, RX VrefLevel [Byte0]: 33

 1033 23:02:37.711998                           [Byte1]: 33

 1034 23:02:37.715919  

 1035 23:02:37.716022  Set Vref, RX VrefLevel [Byte0]: 34

 1036 23:02:37.719332                           [Byte1]: 34

 1037 23:02:37.724061  

 1038 23:02:37.724164  Set Vref, RX VrefLevel [Byte0]: 35

 1039 23:02:37.726952                           [Byte1]: 35

 1040 23:02:37.731767  

 1041 23:02:37.731837  Set Vref, RX VrefLevel [Byte0]: 36

 1042 23:02:37.735098                           [Byte1]: 36

 1043 23:02:37.739143  

 1044 23:02:37.739240  Set Vref, RX VrefLevel [Byte0]: 37

 1045 23:02:37.742398                           [Byte1]: 37

 1046 23:02:37.746716  

 1047 23:02:37.746814  Set Vref, RX VrefLevel [Byte0]: 38

 1048 23:02:37.750261                           [Byte1]: 38

 1049 23:02:37.754640  

 1050 23:02:37.754714  Set Vref, RX VrefLevel [Byte0]: 39

 1051 23:02:37.758189                           [Byte1]: 39

 1052 23:02:37.761569  

 1053 23:02:37.761705  Set Vref, RX VrefLevel [Byte0]: 40

 1054 23:02:37.765388                           [Byte1]: 40

 1055 23:02:37.769819  

 1056 23:02:37.769924  Set Vref, RX VrefLevel [Byte0]: 41

 1057 23:02:37.772956                           [Byte1]: 41

 1058 23:02:37.777028  

 1059 23:02:37.777103  Set Vref, RX VrefLevel [Byte0]: 42

 1060 23:02:37.780528                           [Byte1]: 42

 1061 23:02:37.784626  

 1062 23:02:37.784723  Set Vref, RX VrefLevel [Byte0]: 43

 1063 23:02:37.787927                           [Byte1]: 43

 1064 23:02:37.792037  

 1065 23:02:37.792132  Set Vref, RX VrefLevel [Byte0]: 44

 1066 23:02:37.795394                           [Byte1]: 44

 1067 23:02:37.799726  

 1068 23:02:37.799828  Set Vref, RX VrefLevel [Byte0]: 45

 1069 23:02:37.803342                           [Byte1]: 45

 1070 23:02:37.807376  

 1071 23:02:37.807446  Set Vref, RX VrefLevel [Byte0]: 46

 1072 23:02:37.810710                           [Byte1]: 46

 1073 23:02:37.814880  

 1074 23:02:37.814950  Set Vref, RX VrefLevel [Byte0]: 47

 1075 23:02:37.818288                           [Byte1]: 47

 1076 23:02:37.822306  

 1077 23:02:37.822391  Set Vref, RX VrefLevel [Byte0]: 48

 1078 23:02:37.825787                           [Byte1]: 48

 1079 23:02:37.830453  

 1080 23:02:37.830552  Set Vref, RX VrefLevel [Byte0]: 49

 1081 23:02:37.833311                           [Byte1]: 49

 1082 23:02:37.837474  

 1083 23:02:37.837570  Set Vref, RX VrefLevel [Byte0]: 50

 1084 23:02:37.840875                           [Byte1]: 50

 1085 23:02:37.845249  

 1086 23:02:37.845347  Set Vref, RX VrefLevel [Byte0]: 51

 1087 23:02:37.849111                           [Byte1]: 51

 1088 23:02:37.853059  

 1089 23:02:37.853159  Set Vref, RX VrefLevel [Byte0]: 52

 1090 23:02:37.856402                           [Byte1]: 52

 1091 23:02:37.860767  

 1092 23:02:37.860862  Set Vref, RX VrefLevel [Byte0]: 53

 1093 23:02:37.863822                           [Byte1]: 53

 1094 23:02:37.868607  

 1095 23:02:37.868708  Set Vref, RX VrefLevel [Byte0]: 54

 1096 23:02:37.871515                           [Byte1]: 54

 1097 23:02:37.876182  

 1098 23:02:37.876258  Set Vref, RX VrefLevel [Byte0]: 55

 1099 23:02:37.878975                           [Byte1]: 55

 1100 23:02:37.883592  

 1101 23:02:37.883695  Set Vref, RX VrefLevel [Byte0]: 56

 1102 23:02:37.886526                           [Byte1]: 56

 1103 23:02:37.891162  

 1104 23:02:37.891258  Set Vref, RX VrefLevel [Byte0]: 57

 1105 23:02:37.894524                           [Byte1]: 57

 1106 23:02:37.898627  

 1107 23:02:37.898696  Set Vref, RX VrefLevel [Byte0]: 58

 1108 23:02:37.901807                           [Byte1]: 58

 1109 23:02:37.906310  

 1110 23:02:37.906379  Set Vref, RX VrefLevel [Byte0]: 59

 1111 23:02:37.909924                           [Byte1]: 59

 1112 23:02:37.914095  

 1113 23:02:37.914190  Set Vref, RX VrefLevel [Byte0]: 60

 1114 23:02:37.917007                           [Byte1]: 60

 1115 23:02:37.921194  

 1116 23:02:37.921293  Set Vref, RX VrefLevel [Byte0]: 61

 1117 23:02:37.924474                           [Byte1]: 61

 1118 23:02:37.929062  

 1119 23:02:37.929166  Set Vref, RX VrefLevel [Byte0]: 62

 1120 23:02:37.932247                           [Byte1]: 62

 1121 23:02:37.936515  

 1122 23:02:37.936587  Set Vref, RX VrefLevel [Byte0]: 63

 1123 23:02:37.940071                           [Byte1]: 63

 1124 23:02:37.944332  

 1125 23:02:37.944433  Set Vref, RX VrefLevel [Byte0]: 64

 1126 23:02:37.947770                           [Byte1]: 64

 1127 23:02:37.951682  

 1128 23:02:37.951788  Set Vref, RX VrefLevel [Byte0]: 65

 1129 23:02:37.954757                           [Byte1]: 65

 1130 23:02:37.959292  

 1131 23:02:37.959403  Set Vref, RX VrefLevel [Byte0]: 66

 1132 23:02:37.962724                           [Byte1]: 66

 1133 23:02:37.967132  

 1134 23:02:37.967233  Set Vref, RX VrefLevel [Byte0]: 67

 1135 23:02:37.970436                           [Byte1]: 67

 1136 23:02:37.974793  

 1137 23:02:37.974865  Set Vref, RX VrefLevel [Byte0]: 68

 1138 23:02:37.977934                           [Byte1]: 68

 1139 23:02:37.982111  

 1140 23:02:37.982183  Set Vref, RX VrefLevel [Byte0]: 69

 1141 23:02:37.985695                           [Byte1]: 69

 1142 23:02:37.989783  

 1143 23:02:37.989859  Set Vref, RX VrefLevel [Byte0]: 70

 1144 23:02:37.993213                           [Byte1]: 70

 1145 23:02:37.997163  

 1146 23:02:37.997268  Set Vref, RX VrefLevel [Byte0]: 71

 1147 23:02:38.000427                           [Byte1]: 71

 1148 23:02:38.005189  

 1149 23:02:38.005293  Set Vref, RX VrefLevel [Byte0]: 72

 1150 23:02:38.008202                           [Byte1]: 72

 1151 23:02:38.012371  

 1152 23:02:38.012466  Set Vref, RX VrefLevel [Byte0]: 73

 1153 23:02:38.016052                           [Byte1]: 73

 1154 23:02:38.020098  

 1155 23:02:38.020203  Set Vref, RX VrefLevel [Byte0]: 74

 1156 23:02:38.023517                           [Byte1]: 74

 1157 23:02:38.027858  

 1158 23:02:38.027934  Set Vref, RX VrefLevel [Byte0]: 75

 1159 23:02:38.030738                           [Byte1]: 75

 1160 23:02:38.035484  

 1161 23:02:38.035557  Final RX Vref Byte 0 = 54 to rank0

 1162 23:02:38.038888  Final RX Vref Byte 1 = 59 to rank0

 1163 23:02:38.042329  Final RX Vref Byte 0 = 54 to rank1

 1164 23:02:38.045736  Final RX Vref Byte 1 = 59 to rank1==

 1165 23:02:38.049016  Dram Type= 6, Freq= 0, CH_0, rank 0

 1166 23:02:38.052188  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1167 23:02:38.055763  ==

 1168 23:02:38.055866  DQS Delay:

 1169 23:02:38.055957  DQS0 = 0, DQS1 = 0

 1170 23:02:38.058687  DQM Delay:

 1171 23:02:38.058792  DQM0 = 91, DQM1 = 85

 1172 23:02:38.062139  DQ Delay:

 1173 23:02:38.062209  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1174 23:02:38.065569  DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100

 1175 23:02:38.069034  DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76

 1176 23:02:38.072353  DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92

 1177 23:02:38.072451  

 1178 23:02:38.075803  

 1179 23:02:38.082455  [DQSOSCAuto] RK0, (LSB)MR18= 0x4a3f, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 1180 23:02:38.085742  CH0 RK0: MR19=606, MR18=4A3F

 1181 23:02:38.092146  CH0_RK0: MR19=0x606, MR18=0x4A3F, DQSOSC=391, MR23=63, INC=96, DEC=64

 1182 23:02:38.092259  

 1183 23:02:38.095608  ----->DramcWriteLeveling(PI) begin...

 1184 23:02:38.095716  ==

 1185 23:02:38.098987  Dram Type= 6, Freq= 0, CH_0, rank 1

 1186 23:02:38.102363  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1187 23:02:38.102460  ==

 1188 23:02:38.105735  Write leveling (Byte 0): 33 => 33

 1189 23:02:38.108814  Write leveling (Byte 1): 29 => 29

 1190 23:02:38.112322  DramcWriteLeveling(PI) end<-----

 1191 23:02:38.112415  

 1192 23:02:38.112502  ==

 1193 23:02:38.115704  Dram Type= 6, Freq= 0, CH_0, rank 1

 1194 23:02:38.119249  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1195 23:02:38.119346  ==

 1196 23:02:38.122277  [Gating] SW mode calibration

 1197 23:02:38.129226  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1198 23:02:38.135730  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1199 23:02:38.139337   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1200 23:02:38.142632   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

 1201 23:02:38.186794   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1202 23:02:38.187382   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1203 23:02:38.187662   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1204 23:02:38.187786   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1205 23:02:38.187889   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1206 23:02:38.188430   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1207 23:02:38.188708   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1208 23:02:38.188983   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1209 23:02:38.189073   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1210 23:02:38.189202   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1211 23:02:38.230719   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1212 23:02:38.230808   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1213 23:02:38.231061   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1214 23:02:38.231128   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1215 23:02:38.231187   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1216 23:02:38.231255   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

 1217 23:02:38.231500   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1218 23:02:38.231561   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1219 23:02:38.231617   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1220 23:02:38.231682   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1221 23:02:38.274751   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1222 23:02:38.275315   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1223 23:02:38.276152   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1224 23:02:38.276284   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1225 23:02:38.276639   0  9  8 | B1->B0 | 2e2e 2c2c | 1 1 | (1 1) (1 1)

 1226 23:02:38.276723   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1227 23:02:38.276800   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1228 23:02:38.276891   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1229 23:02:38.276952   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1230 23:02:38.277019   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1231 23:02:38.284080   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1232 23:02:38.287691   0 10  4 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)

 1233 23:02:38.291135   0 10  8 | B1->B0 | 2525 2828 | 0 0 | (0 0) (1 0)

 1234 23:02:38.293942   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1235 23:02:38.297353   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1236 23:02:38.300843   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1237 23:02:38.307229   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1238 23:02:38.310657   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1239 23:02:38.314625   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1240 23:02:38.317977   0 11  4 | B1->B0 | 2626 2828 | 0 0 | (1 1) (0 0)

 1241 23:02:38.321948   0 11  8 | B1->B0 | 3e3e 3939 | 0 0 | (1 1) (0 0)

 1242 23:02:38.328826   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1243 23:02:38.332615   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1244 23:02:38.335563   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1245 23:02:38.342949   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1246 23:02:38.346404   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1247 23:02:38.349909   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1248 23:02:38.353120   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1249 23:02:38.360329   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1250 23:02:38.363264   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1251 23:02:38.366642   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1252 23:02:38.369781   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1253 23:02:38.376979   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1254 23:02:38.379972   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1255 23:02:38.383311   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1256 23:02:38.389825   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1257 23:02:38.393302   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1258 23:02:38.396624   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1259 23:02:38.403388   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1260 23:02:38.406841   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1261 23:02:38.410240   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1262 23:02:38.416621   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1263 23:02:38.419978   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1264 23:02:38.423496   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1265 23:02:38.429939   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1266 23:02:38.433501   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1267 23:02:38.436460  Total UI for P1: 0, mck2ui 16

 1268 23:02:38.439865  best dqsien dly found for B1: ( 0, 14, 10)

 1269 23:02:38.443275   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1270 23:02:38.446602  Total UI for P1: 0, mck2ui 16

 1271 23:02:38.449785  best dqsien dly found for B0: ( 0, 14, 12)

 1272 23:02:38.453264  best DQS0 dly(MCK, UI, PI) = (0, 14, 12)

 1273 23:02:38.456644  best DQS1 dly(MCK, UI, PI) = (0, 14, 10)

 1274 23:02:38.456718  

 1275 23:02:38.463256  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 12)

 1276 23:02:38.466956  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)

 1277 23:02:38.467032  [Gating] SW calibration Done

 1278 23:02:38.470431  ==

 1279 23:02:38.470504  Dram Type= 6, Freq= 0, CH_0, rank 1

 1280 23:02:38.476671  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1281 23:02:38.476766  ==

 1282 23:02:38.476850  RX Vref Scan: 0

 1283 23:02:38.476924  

 1284 23:02:38.480190  RX Vref 0 -> 0, step: 1

 1285 23:02:38.480270  

 1286 23:02:38.483489  RX Delay -130 -> 252, step: 16

 1287 23:02:38.487037  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1288 23:02:38.490292  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1289 23:02:38.493090  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1290 23:02:38.500293  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1291 23:02:38.503152  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1292 23:02:38.506426  iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240

 1293 23:02:38.509799  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1294 23:02:38.513182  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1295 23:02:38.519995  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1296 23:02:38.523508  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1297 23:02:38.526297  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1298 23:02:38.530038  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1299 23:02:38.533413  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1300 23:02:38.539739  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1301 23:02:38.543256  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1302 23:02:38.546542  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

 1303 23:02:38.546622  ==

 1304 23:02:38.550090  Dram Type= 6, Freq= 0, CH_0, rank 1

 1305 23:02:38.553461  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1306 23:02:38.556783  ==

 1307 23:02:38.556863  DQS Delay:

 1308 23:02:38.556926  DQS0 = 0, DQS1 = 0

 1309 23:02:38.560238  DQM Delay:

 1310 23:02:38.560317  DQM0 = 91, DQM1 = 83

 1311 23:02:38.560430  DQ Delay:

 1312 23:02:38.563277  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

 1313 23:02:38.566763  DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101

 1314 23:02:38.569878  DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77

 1315 23:02:38.573273  DQ12 =85, DQ13 =93, DQ14 =93, DQ15 =85

 1316 23:02:38.573373  

 1317 23:02:38.573462  

 1318 23:02:38.576985  ==

 1319 23:02:38.580042  Dram Type= 6, Freq= 0, CH_0, rank 1

 1320 23:02:38.583356  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1321 23:02:38.583430  ==

 1322 23:02:38.583491  

 1323 23:02:38.583548  

 1324 23:02:38.586757  	TX Vref Scan disable

 1325 23:02:38.586837   == TX Byte 0 ==

 1326 23:02:38.593524  Update DQ  dly =585 (2 ,1, 41)  DQ  OEN =(1 ,6)

 1327 23:02:38.596573  Update DQM dly =585 (2 ,1, 41)  DQM OEN =(1 ,6)

 1328 23:02:38.596652   == TX Byte 1 ==

 1329 23:02:38.599876  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1330 23:02:38.606599  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1331 23:02:38.606704  ==

 1332 23:02:38.610104  Dram Type= 6, Freq= 0, CH_0, rank 1

 1333 23:02:38.613534  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1334 23:02:38.613640  ==

 1335 23:02:38.627283  TX Vref=22, minBit 8, minWin=27, winSum=446

 1336 23:02:38.630178  TX Vref=24, minBit 15, minWin=27, winSum=450

 1337 23:02:38.633731  TX Vref=26, minBit 1, minWin=28, winSum=455

 1338 23:02:38.637240  TX Vref=28, minBit 4, minWin=28, winSum=455

 1339 23:02:38.640181  TX Vref=30, minBit 5, minWin=28, winSum=458

 1340 23:02:38.647106  TX Vref=32, minBit 1, minWin=28, winSum=458

 1341 23:02:38.650401  [TxChooseVref] Worse bit 5, Min win 28, Win sum 458, Final Vref 30

 1342 23:02:38.650482  

 1343 23:02:38.654014  Final TX Range 1 Vref 30

 1344 23:02:38.654149  

 1345 23:02:38.654214  ==

 1346 23:02:38.657450  Dram Type= 6, Freq= 0, CH_0, rank 1

 1347 23:02:38.660464  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1348 23:02:38.660550  ==

 1349 23:02:38.663915  

 1350 23:02:38.663993  

 1351 23:02:38.664055  	TX Vref Scan disable

 1352 23:02:38.667160   == TX Byte 0 ==

 1353 23:02:38.670785  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

 1354 23:02:38.673995  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

 1355 23:02:38.676936   == TX Byte 1 ==

 1356 23:02:38.680348  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1357 23:02:38.687393  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1358 23:02:38.687473  

 1359 23:02:38.687535  [DATLAT]

 1360 23:02:38.687593  Freq=800, CH0 RK1

 1361 23:02:38.687651  

 1362 23:02:38.690800  DATLAT Default: 0xa

 1363 23:02:38.690878  0, 0xFFFF, sum = 0

 1364 23:02:38.693686  1, 0xFFFF, sum = 0

 1365 23:02:38.693766  2, 0xFFFF, sum = 0

 1366 23:02:38.697279  3, 0xFFFF, sum = 0

 1367 23:02:38.700372  4, 0xFFFF, sum = 0

 1368 23:02:38.700452  5, 0xFFFF, sum = 0

 1369 23:02:38.704177  6, 0xFFFF, sum = 0

 1370 23:02:38.704256  7, 0xFFFF, sum = 0

 1371 23:02:38.707209  8, 0xFFFF, sum = 0

 1372 23:02:38.707288  9, 0x0, sum = 1

 1373 23:02:38.707352  10, 0x0, sum = 2

 1374 23:02:38.710328  11, 0x0, sum = 3

 1375 23:02:38.710407  12, 0x0, sum = 4

 1376 23:02:38.713463  best_step = 10

 1377 23:02:38.713570  

 1378 23:02:38.713670  ==

 1379 23:02:38.717024  Dram Type= 6, Freq= 0, CH_0, rank 1

 1380 23:02:38.720284  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1381 23:02:38.720389  ==

 1382 23:02:38.723507  RX Vref Scan: 0

 1383 23:02:38.723611  

 1384 23:02:38.723701  RX Vref 0 -> 0, step: 1

 1385 23:02:38.723787  

 1386 23:02:38.726738  RX Delay -79 -> 252, step: 8

 1387 23:02:38.734073  iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216

 1388 23:02:38.737085  iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216

 1389 23:02:38.740451  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1390 23:02:38.743942  iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224

 1391 23:02:38.747499  iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224

 1392 23:02:38.754057  iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216

 1393 23:02:38.757692  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1394 23:02:38.760638  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1395 23:02:38.764065  iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216

 1396 23:02:38.767590  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1397 23:02:38.773850  iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216

 1398 23:02:38.777479  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1399 23:02:38.780640  iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208

 1400 23:02:38.783857  iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216

 1401 23:02:38.787600  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1402 23:02:38.794002  iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216

 1403 23:02:38.794081  ==

 1404 23:02:38.797495  Dram Type= 6, Freq= 0, CH_0, rank 1

 1405 23:02:38.800473  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1406 23:02:38.800552  ==

 1407 23:02:38.800614  DQS Delay:

 1408 23:02:38.804049  DQS0 = 0, DQS1 = 0

 1409 23:02:38.804136  DQM Delay:

 1410 23:02:38.807679  DQM0 = 92, DQM1 = 84

 1411 23:02:38.807757  DQ Delay:

 1412 23:02:38.810961  DQ0 =92, DQ1 =92, DQ2 =88, DQ3 =88

 1413 23:02:38.813788  DQ4 =96, DQ5 =84, DQ6 =100, DQ7 =100

 1414 23:02:38.817139  DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76

 1415 23:02:38.821016  DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92

 1416 23:02:38.821109  

 1417 23:02:38.821185  

 1418 23:02:38.827347  [DQSOSCAuto] RK1, (LSB)MR18= 0x4011, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 1419 23:02:38.830796  CH0 RK1: MR19=606, MR18=4011

 1420 23:02:38.837462  CH0_RK1: MR19=0x606, MR18=0x4011, DQSOSC=393, MR23=63, INC=95, DEC=63

 1421 23:02:38.840646  [RxdqsGatingPostProcess] freq 800

 1422 23:02:38.847378  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1423 23:02:38.847458  Pre-setting of DQS Precalculation

 1424 23:02:38.854108  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1425 23:02:38.854201  ==

 1426 23:02:38.857353  Dram Type= 6, Freq= 0, CH_1, rank 0

 1427 23:02:38.860644  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1428 23:02:38.860724  ==

 1429 23:02:38.867617  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1430 23:02:38.873953  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1431 23:02:38.882024  [CA 0] Center 36 (6~67) winsize 62

 1432 23:02:38.885476  [CA 1] Center 36 (6~67) winsize 62

 1433 23:02:38.888670  [CA 2] Center 35 (5~66) winsize 62

 1434 23:02:38.892437  [CA 3] Center 34 (4~65) winsize 62

 1435 23:02:38.895760  [CA 4] Center 34 (4~65) winsize 62

 1436 23:02:38.898785  [CA 5] Center 34 (4~64) winsize 61

 1437 23:02:38.898864  

 1438 23:02:38.902370  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1439 23:02:38.902450  

 1440 23:02:38.905768  [CATrainingPosCal] consider 1 rank data

 1441 23:02:38.908676  u2DelayCellTimex100 = 270/100 ps

 1442 23:02:38.912104  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1443 23:02:38.915343  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1444 23:02:38.922421  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1445 23:02:38.925638  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1446 23:02:38.928803  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 1447 23:02:38.932401  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1448 23:02:38.932480  

 1449 23:02:38.935247  CA PerBit enable=1, Macro0, CA PI delay=34

 1450 23:02:38.935326  

 1451 23:02:38.938826  [CBTSetCACLKResult] CA Dly = 34

 1452 23:02:38.938906  CS Dly: 5 (0~36)

 1453 23:02:38.942424  ==

 1454 23:02:38.942503  Dram Type= 6, Freq= 0, CH_1, rank 1

 1455 23:02:38.948900  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1456 23:02:38.949015  ==

 1457 23:02:38.952359  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1458 23:02:38.958822  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1459 23:02:38.968232  [CA 0] Center 36 (6~67) winsize 62

 1460 23:02:38.971896  [CA 1] Center 37 (6~68) winsize 63

 1461 23:02:38.975113  [CA 2] Center 35 (4~66) winsize 63

 1462 23:02:38.979043  [CA 3] Center 34 (4~65) winsize 62

 1463 23:02:38.982593  [CA 4] Center 35 (5~66) winsize 62

 1464 23:02:38.986375  [CA 5] Center 34 (4~65) winsize 62

 1465 23:02:38.986456  

 1466 23:02:38.989852  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1467 23:02:38.989983  

 1468 23:02:38.993867  [CATrainingPosCal] consider 2 rank data

 1469 23:02:38.997880  u2DelayCellTimex100 = 270/100 ps

 1470 23:02:39.001562  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1471 23:02:39.004993  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1472 23:02:39.009497  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1473 23:02:39.009591  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1474 23:02:39.012968  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1475 23:02:39.016534  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1476 23:02:39.016615  

 1477 23:02:39.023559  CA PerBit enable=1, Macro0, CA PI delay=34

 1478 23:02:39.023639  

 1479 23:02:39.023702  [CBTSetCACLKResult] CA Dly = 34

 1480 23:02:39.026452  CS Dly: 6 (0~38)

 1481 23:02:39.026531  

 1482 23:02:39.029954  ----->DramcWriteLeveling(PI) begin...

 1483 23:02:39.030060  ==

 1484 23:02:39.033204  Dram Type= 6, Freq= 0, CH_1, rank 0

 1485 23:02:39.036326  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1486 23:02:39.036406  ==

 1487 23:02:39.039672  Write leveling (Byte 0): 26 => 26

 1488 23:02:39.043175  Write leveling (Byte 1): 28 => 28

 1489 23:02:39.046807  DramcWriteLeveling(PI) end<-----

 1490 23:02:39.046887  

 1491 23:02:39.046950  ==

 1492 23:02:39.049613  Dram Type= 6, Freq= 0, CH_1, rank 0

 1493 23:02:39.053001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1494 23:02:39.056548  ==

 1495 23:02:39.056627  [Gating] SW mode calibration

 1496 23:02:39.063021  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1497 23:02:39.070070  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1498 23:02:39.073358   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1499 23:02:39.079747   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1500 23:02:39.083061   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1501 23:02:39.086814   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1502 23:02:39.093386   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1503 23:02:39.096545   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1504 23:02:39.100144   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1505 23:02:39.106305   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1506 23:02:39.109840   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1507 23:02:39.113104   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1508 23:02:39.116513   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1509 23:02:39.123634   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1510 23:02:39.127095   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1511 23:02:39.129892   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1512 23:02:39.137072   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1513 23:02:39.139882   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1514 23:02:39.143502   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1515 23:02:39.149747   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1516 23:02:39.153398   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1517 23:02:39.156442   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1518 23:02:39.163274   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1519 23:02:39.166950   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1520 23:02:39.170261   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1521 23:02:39.176402   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1522 23:02:39.180170   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1523 23:02:39.183531   0  9  4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)

 1524 23:02:39.190015   0  9  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 1525 23:02:39.193345   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1526 23:02:39.196579   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1527 23:02:39.203323   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1528 23:02:39.206571   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1529 23:02:39.210324   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1530 23:02:39.213634   0 10  0 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)

 1531 23:02:39.220443   0 10  4 | B1->B0 | 3333 2e2e | 0 1 | (0 1) (0 1)

 1532 23:02:39.223578   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1533 23:02:39.226740   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1534 23:02:39.233322   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1535 23:02:39.236683   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1536 23:02:39.240142   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1537 23:02:39.246556   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1538 23:02:39.249777   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1539 23:02:39.253487   0 11  4 | B1->B0 | 2a2a 3a3a | 0 0 | (0 0) (0 0)

 1540 23:02:39.259925   0 11  8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 1541 23:02:39.263568   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1542 23:02:39.266991   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1543 23:02:39.273475   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1544 23:02:39.277066   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1545 23:02:39.279860   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1546 23:02:39.283393   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1547 23:02:39.290294   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1548 23:02:39.293273   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1549 23:02:39.296851   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1550 23:02:39.303611   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1551 23:02:39.306677   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1552 23:02:39.310326   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1553 23:02:39.317309   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1554 23:02:39.320661   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1555 23:02:39.323457   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1556 23:02:39.330178   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1557 23:02:39.333330   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1558 23:02:39.337230   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1559 23:02:39.343665   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1560 23:02:39.346911   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1561 23:02:39.350265   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1562 23:02:39.357028   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1563 23:02:39.360147   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1564 23:02:39.363584   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1565 23:02:39.367040  Total UI for P1: 0, mck2ui 16

 1566 23:02:39.370245  best dqsien dly found for B0: ( 0, 14,  6)

 1567 23:02:39.373711  Total UI for P1: 0, mck2ui 16

 1568 23:02:39.377086  best dqsien dly found for B1: ( 0, 14,  4)

 1569 23:02:39.380056  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1570 23:02:39.383402  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1571 23:02:39.383480  

 1572 23:02:39.387182  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1573 23:02:39.390356  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1574 23:02:39.393682  [Gating] SW calibration Done

 1575 23:02:39.393759  ==

 1576 23:02:39.397069  Dram Type= 6, Freq= 0, CH_1, rank 0

 1577 23:02:39.403491  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1578 23:02:39.403578  ==

 1579 23:02:39.403643  RX Vref Scan: 0

 1580 23:02:39.403711  

 1581 23:02:39.407052  RX Vref 0 -> 0, step: 1

 1582 23:02:39.407126  

 1583 23:02:39.410366  RX Delay -130 -> 252, step: 16

 1584 23:02:39.413384  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1585 23:02:39.417200  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1586 23:02:39.420568  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1587 23:02:39.424111  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1588 23:02:39.430381  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1589 23:02:39.433874  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1590 23:02:39.437202  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1591 23:02:39.440226  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1592 23:02:39.443641  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1593 23:02:39.450156  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1594 23:02:39.453508  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1595 23:02:39.457131  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1596 23:02:39.460154  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1597 23:02:39.463988  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1598 23:02:39.470635  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1599 23:02:39.473718  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1600 23:02:39.473804  ==

 1601 23:02:39.477173  Dram Type= 6, Freq= 0, CH_1, rank 0

 1602 23:02:39.480632  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1603 23:02:39.480714  ==

 1604 23:02:39.483671  DQS Delay:

 1605 23:02:39.483753  DQS0 = 0, DQS1 = 0

 1606 23:02:39.483818  DQM Delay:

 1607 23:02:39.487121  DQM0 = 92, DQM1 = 87

 1608 23:02:39.487202  DQ Delay:

 1609 23:02:39.490684  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93

 1610 23:02:39.493632  DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93

 1611 23:02:39.496906  DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85

 1612 23:02:39.500403  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1613 23:02:39.500484  

 1614 23:02:39.500548  

 1615 23:02:39.500607  ==

 1616 23:02:39.503776  Dram Type= 6, Freq= 0, CH_1, rank 0

 1617 23:02:39.510129  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1618 23:02:39.510211  ==

 1619 23:02:39.510275  

 1620 23:02:39.510334  

 1621 23:02:39.510391  	TX Vref Scan disable

 1622 23:02:39.513657   == TX Byte 0 ==

 1623 23:02:39.517188  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1624 23:02:39.520382  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1625 23:02:39.524165   == TX Byte 1 ==

 1626 23:02:39.527132  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1627 23:02:39.530498  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1628 23:02:39.534045  ==

 1629 23:02:39.536924  Dram Type= 6, Freq= 0, CH_1, rank 0

 1630 23:02:39.540691  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1631 23:02:39.540814  ==

 1632 23:02:39.552597  TX Vref=22, minBit 0, minWin=26, winSum=438

 1633 23:02:39.556356  TX Vref=24, minBit 0, minWin=26, winSum=441

 1634 23:02:39.560250  TX Vref=26, minBit 0, minWin=27, winSum=444

 1635 23:02:39.563751  TX Vref=28, minBit 1, minWin=26, winSum=446

 1636 23:02:39.567451  TX Vref=30, minBit 0, minWin=27, winSum=448

 1637 23:02:39.570269  TX Vref=32, minBit 0, minWin=27, winSum=447

 1638 23:02:39.577257  [TxChooseVref] Worse bit 0, Min win 27, Win sum 448, Final Vref 30

 1639 23:02:39.577364  

 1640 23:02:39.580322  Final TX Range 1 Vref 30

 1641 23:02:39.580406  

 1642 23:02:39.580469  ==

 1643 23:02:39.583498  Dram Type= 6, Freq= 0, CH_1, rank 0

 1644 23:02:39.587249  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1645 23:02:39.587348  ==

 1646 23:02:39.587414  

 1647 23:02:39.587481  

 1648 23:02:39.590702  	TX Vref Scan disable

 1649 23:02:39.593583   == TX Byte 0 ==

 1650 23:02:39.597054  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1651 23:02:39.600491  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1652 23:02:39.603978   == TX Byte 1 ==

 1653 23:02:39.607089  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1654 23:02:39.610793  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1655 23:02:39.610886  

 1656 23:02:39.610963  [DATLAT]

 1657 23:02:39.614300  Freq=800, CH1 RK0

 1658 23:02:39.614379  

 1659 23:02:39.617248  DATLAT Default: 0xa

 1660 23:02:39.617326  0, 0xFFFF, sum = 0

 1661 23:02:39.620697  1, 0xFFFF, sum = 0

 1662 23:02:39.620807  2, 0xFFFF, sum = 0

 1663 23:02:39.624248  3, 0xFFFF, sum = 0

 1664 23:02:39.624322  4, 0xFFFF, sum = 0

 1665 23:02:39.627521  5, 0xFFFF, sum = 0

 1666 23:02:39.627598  6, 0xFFFF, sum = 0

 1667 23:02:39.630696  7, 0xFFFF, sum = 0

 1668 23:02:39.630767  8, 0xFFFF, sum = 0

 1669 23:02:39.634156  9, 0x0, sum = 1

 1670 23:02:39.634237  10, 0x0, sum = 2

 1671 23:02:39.637433  11, 0x0, sum = 3

 1672 23:02:39.637505  12, 0x0, sum = 4

 1673 23:02:39.637571  best_step = 10

 1674 23:02:39.637673  

 1675 23:02:39.641237  ==

 1676 23:02:39.641304  Dram Type= 6, Freq= 0, CH_1, rank 0

 1677 23:02:39.647778  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1678 23:02:39.647853  ==

 1679 23:02:39.647920  RX Vref Scan: 1

 1680 23:02:39.647979  

 1681 23:02:39.650741  Set Vref Range= 32 -> 127

 1682 23:02:39.650814  

 1683 23:02:39.654413  RX Vref 32 -> 127, step: 1

 1684 23:02:39.654487  

 1685 23:02:39.657961  RX Delay -79 -> 252, step: 8

 1686 23:02:39.658030  

 1687 23:02:39.661012  Set Vref, RX VrefLevel [Byte0]: 32

 1688 23:02:39.664407                           [Byte1]: 32

 1689 23:02:39.664511  

 1690 23:02:39.667902  Set Vref, RX VrefLevel [Byte0]: 33

 1691 23:02:39.670610                           [Byte1]: 33

 1692 23:02:39.670687  

 1693 23:02:39.674284  Set Vref, RX VrefLevel [Byte0]: 34

 1694 23:02:39.677488                           [Byte1]: 34

 1695 23:02:39.677620  

 1696 23:02:39.680639  Set Vref, RX VrefLevel [Byte0]: 35

 1697 23:02:39.684120                           [Byte1]: 35

 1698 23:02:39.688155  

 1699 23:02:39.688227  Set Vref, RX VrefLevel [Byte0]: 36

 1700 23:02:39.691414                           [Byte1]: 36

 1701 23:02:39.695499  

 1702 23:02:39.695578  Set Vref, RX VrefLevel [Byte0]: 37

 1703 23:02:39.699045                           [Byte1]: 37

 1704 23:02:39.702984  

 1705 23:02:39.703062  Set Vref, RX VrefLevel [Byte0]: 38

 1706 23:02:39.706291                           [Byte1]: 38

 1707 23:02:39.710534  

 1708 23:02:39.710613  Set Vref, RX VrefLevel [Byte0]: 39

 1709 23:02:39.713896                           [Byte1]: 39

 1710 23:02:39.718269  

 1711 23:02:39.718348  Set Vref, RX VrefLevel [Byte0]: 40

 1712 23:02:39.721221                           [Byte1]: 40

 1713 23:02:39.725892  

 1714 23:02:39.725970  Set Vref, RX VrefLevel [Byte0]: 41

 1715 23:02:39.729271                           [Byte1]: 41

 1716 23:02:39.733228  

 1717 23:02:39.733306  Set Vref, RX VrefLevel [Byte0]: 42

 1718 23:02:39.736640                           [Byte1]: 42

 1719 23:02:39.740801  

 1720 23:02:39.740879  Set Vref, RX VrefLevel [Byte0]: 43

 1721 23:02:39.744370                           [Byte1]: 43

 1722 23:02:39.748510  

 1723 23:02:39.748589  Set Vref, RX VrefLevel [Byte0]: 44

 1724 23:02:39.752072                           [Byte1]: 44

 1725 23:02:39.756114  

 1726 23:02:39.756193  Set Vref, RX VrefLevel [Byte0]: 45

 1727 23:02:39.759627                           [Byte1]: 45

 1728 23:02:39.763252  

 1729 23:02:39.763340  Set Vref, RX VrefLevel [Byte0]: 46

 1730 23:02:39.766606                           [Byte1]: 46

 1731 23:02:39.771312  

 1732 23:02:39.771391  Set Vref, RX VrefLevel [Byte0]: 47

 1733 23:02:39.774345                           [Byte1]: 47

 1734 23:02:39.778702  

 1735 23:02:39.778808  Set Vref, RX VrefLevel [Byte0]: 48

 1736 23:02:39.781885                           [Byte1]: 48

 1737 23:02:39.786335  

 1738 23:02:39.786428  Set Vref, RX VrefLevel [Byte0]: 49

 1739 23:02:39.789570                           [Byte1]: 49

 1740 23:02:39.793629  

 1741 23:02:39.793709  Set Vref, RX VrefLevel [Byte0]: 50

 1742 23:02:39.796701                           [Byte1]: 50

 1743 23:02:39.801043  

 1744 23:02:39.801123  Set Vref, RX VrefLevel [Byte0]: 51

 1745 23:02:39.804486                           [Byte1]: 51

 1746 23:02:39.808848  

 1747 23:02:39.808958  Set Vref, RX VrefLevel [Byte0]: 52

 1748 23:02:39.812184                           [Byte1]: 52

 1749 23:02:39.816317  

 1750 23:02:39.816423  Set Vref, RX VrefLevel [Byte0]: 53

 1751 23:02:39.819580                           [Byte1]: 53

 1752 23:02:39.824128  

 1753 23:02:39.824207  Set Vref, RX VrefLevel [Byte0]: 54

 1754 23:02:39.827385                           [Byte1]: 54

 1755 23:02:39.831300  

 1756 23:02:39.831380  Set Vref, RX VrefLevel [Byte0]: 55

 1757 23:02:39.834946                           [Byte1]: 55

 1758 23:02:39.838941  

 1759 23:02:39.839020  Set Vref, RX VrefLevel [Byte0]: 56

 1760 23:02:39.842354                           [Byte1]: 56

 1761 23:02:39.846810  

 1762 23:02:39.846916  Set Vref, RX VrefLevel [Byte0]: 57

 1763 23:02:39.850091                           [Byte1]: 57

 1764 23:02:39.854264  

 1765 23:02:39.854375  Set Vref, RX VrefLevel [Byte0]: 58

 1766 23:02:39.857184                           [Byte1]: 58

 1767 23:02:39.861944  

 1768 23:02:39.862026  Set Vref, RX VrefLevel [Byte0]: 59

 1769 23:02:39.864930                           [Byte1]: 59

 1770 23:02:39.869078  

 1771 23:02:39.869158  Set Vref, RX VrefLevel [Byte0]: 60

 1772 23:02:39.872599                           [Byte1]: 60

 1773 23:02:39.876544  

 1774 23:02:39.876628  Set Vref, RX VrefLevel [Byte0]: 61

 1775 23:02:39.880172                           [Byte1]: 61

 1776 23:02:39.884392  

 1777 23:02:39.884472  Set Vref, RX VrefLevel [Byte0]: 62

 1778 23:02:39.887253                           [Byte1]: 62

 1779 23:02:39.891793  

 1780 23:02:39.891874  Set Vref, RX VrefLevel [Byte0]: 63

 1781 23:02:39.895291                           [Byte1]: 63

 1782 23:02:39.899321  

 1783 23:02:39.899401  Set Vref, RX VrefLevel [Byte0]: 64

 1784 23:02:39.902748                           [Byte1]: 64

 1785 23:02:39.906597  

 1786 23:02:39.906676  Set Vref, RX VrefLevel [Byte0]: 65

 1787 23:02:39.910242                           [Byte1]: 65

 1788 23:02:39.914501  

 1789 23:02:39.914581  Set Vref, RX VrefLevel [Byte0]: 66

 1790 23:02:39.918193                           [Byte1]: 66

 1791 23:02:39.922062  

 1792 23:02:39.922171  Set Vref, RX VrefLevel [Byte0]: 67

 1793 23:02:39.925096                           [Byte1]: 67

 1794 23:02:39.929707  

 1795 23:02:39.929786  Set Vref, RX VrefLevel [Byte0]: 68

 1796 23:02:39.932923                           [Byte1]: 68

 1797 23:02:39.937137  

 1798 23:02:39.937216  Set Vref, RX VrefLevel [Byte0]: 69

 1799 23:02:39.940663                           [Byte1]: 69

 1800 23:02:39.944824  

 1801 23:02:39.944903  Set Vref, RX VrefLevel [Byte0]: 70

 1802 23:02:39.948246                           [Byte1]: 70

 1803 23:02:39.952186  

 1804 23:02:39.952266  Set Vref, RX VrefLevel [Byte0]: 71

 1805 23:02:39.955247                           [Byte1]: 71

 1806 23:02:39.959830  

 1807 23:02:39.959910  Set Vref, RX VrefLevel [Byte0]: 72

 1808 23:02:39.963147                           [Byte1]: 72

 1809 23:02:39.967437  

 1810 23:02:39.967517  Set Vref, RX VrefLevel [Byte0]: 73

 1811 23:02:39.970749                           [Byte1]: 73

 1812 23:02:39.975061  

 1813 23:02:39.975140  Set Vref, RX VrefLevel [Byte0]: 74

 1814 23:02:39.977858                           [Byte1]: 74

 1815 23:02:39.982739  

 1816 23:02:39.982820  Final RX Vref Byte 0 = 59 to rank0

 1817 23:02:39.985501  Final RX Vref Byte 1 = 55 to rank0

 1818 23:02:39.989086  Final RX Vref Byte 0 = 59 to rank1

 1819 23:02:39.992047  Final RX Vref Byte 1 = 55 to rank1==

 1820 23:02:39.995441  Dram Type= 6, Freq= 0, CH_1, rank 0

 1821 23:02:40.002236  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1822 23:02:40.002317  ==

 1823 23:02:40.002381  DQS Delay:

 1824 23:02:40.002440  DQS0 = 0, DQS1 = 0

 1825 23:02:40.005563  DQM Delay:

 1826 23:02:40.005669  DQM0 = 96, DQM1 = 89

 1827 23:02:40.009033  DQ Delay:

 1828 23:02:40.012349  DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88

 1829 23:02:40.015289  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =96

 1830 23:02:40.018636  DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84

 1831 23:02:40.022162  DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96

 1832 23:02:40.022256  

 1833 23:02:40.022331  

 1834 23:02:40.028952  [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 1835 23:02:40.032026  CH1 RK0: MR19=606, MR18=2C48

 1836 23:02:40.038828  CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64

 1837 23:02:40.038908  

 1838 23:02:40.042114  ----->DramcWriteLeveling(PI) begin...

 1839 23:02:40.042195  ==

 1840 23:02:40.045441  Dram Type= 6, Freq= 0, CH_1, rank 1

 1841 23:02:40.048839  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1842 23:02:40.048932  ==

 1843 23:02:40.052189  Write leveling (Byte 0): 26 => 26

 1844 23:02:40.055815  Write leveling (Byte 1): 29 => 29

 1845 23:02:40.058837  DramcWriteLeveling(PI) end<-----

 1846 23:02:40.058918  

 1847 23:02:40.058981  ==

 1848 23:02:40.062513  Dram Type= 6, Freq= 0, CH_1, rank 1

 1849 23:02:40.065495  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1850 23:02:40.065586  ==

 1851 23:02:40.068783  [Gating] SW mode calibration

 1852 23:02:40.075882  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1853 23:02:40.082163  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1854 23:02:40.085785   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1855 23:02:40.089272   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1856 23:02:40.095672   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1857 23:02:40.099316   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1858 23:02:40.102834   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1859 23:02:40.109087   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1860 23:02:40.112522   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1861 23:02:40.115853   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1862 23:02:40.122407   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1863 23:02:40.125725   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1864 23:02:40.129252   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1865 23:02:40.135870   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1866 23:02:40.139169   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1867 23:02:40.142823   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1868 23:02:40.145596   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1869 23:02:40.152719   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)

 1870 23:02:40.155592   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1871 23:02:40.159277   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1872 23:02:40.165779   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1873 23:02:40.169097   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1874 23:02:40.172553   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1875 23:02:40.179118   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1876 23:02:40.182224   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1877 23:02:40.185709   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1878 23:02:40.192041   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1879 23:02:40.195731   0  9  4 | B1->B0 | 2828 2323 | 1 0 | (0 0) (0 0)

 1880 23:02:40.199137   0  9  8 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)

 1881 23:02:40.205698   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1882 23:02:40.209104   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1883 23:02:40.212414   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1884 23:02:40.218997   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1885 23:02:40.222423   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1886 23:02:40.225759   0 10  0 | B1->B0 | 3232 3434 | 1 1 | (1 0) (1 1)

 1887 23:02:40.232455   0 10  4 | B1->B0 | 2e2e 3333 | 1 1 | (1 0) (1 0)

 1888 23:02:40.235535   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 1889 23:02:40.238987   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1890 23:02:40.245762   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1891 23:02:40.249297   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1892 23:02:40.252071   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1893 23:02:40.259157   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1894 23:02:40.262440   0 11  0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1895 23:02:40.265292   0 11  4 | B1->B0 | 4040 2b2b | 0 1 | (0 0) (1 1)

 1896 23:02:40.268802   0 11  8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)

 1897 23:02:40.275878   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1898 23:02:40.278751   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1899 23:02:40.282382   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1900 23:02:40.289146   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1901 23:02:40.292087   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1902 23:02:40.295805   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1903 23:02:40.302215   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1904 23:02:40.305524   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1905 23:02:40.308839   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1906 23:02:40.315335   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1907 23:02:40.318971   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1908 23:02:40.322439   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1909 23:02:40.328745   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1910 23:02:40.332648   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1911 23:02:40.335866   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1912 23:02:40.339361   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1913 23:02:40.346121   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1914 23:02:40.348995   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1915 23:02:40.352430   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1916 23:02:40.359505   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1917 23:02:40.362401   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1918 23:02:40.366053   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1919 23:02:40.373012   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1920 23:02:40.376221   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1921 23:02:40.379748  Total UI for P1: 0, mck2ui 16

 1922 23:02:40.383161  best dqsien dly found for B0: ( 0, 14,  4)

 1923 23:02:40.385971  Total UI for P1: 0, mck2ui 16

 1924 23:02:40.389409  best dqsien dly found for B1: ( 0, 14,  4)

 1925 23:02:40.392497  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1926 23:02:40.395979  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1927 23:02:40.396058  

 1928 23:02:40.399617  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1929 23:02:40.402527  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1930 23:02:40.405766  [Gating] SW calibration Done

 1931 23:02:40.405845  ==

 1932 23:02:40.409547  Dram Type= 6, Freq= 0, CH_1, rank 1

 1933 23:02:40.412855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1934 23:02:40.412951  ==

 1935 23:02:40.416202  RX Vref Scan: 0

 1936 23:02:40.416282  

 1937 23:02:40.419285  RX Vref 0 -> 0, step: 1

 1938 23:02:40.419363  

 1939 23:02:40.419426  RX Delay -130 -> 252, step: 16

 1940 23:02:40.425954  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1941 23:02:40.429327  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1942 23:02:40.432753  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1943 23:02:40.435786  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1944 23:02:40.439312  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1945 23:02:40.446069  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1946 23:02:40.449423  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1947 23:02:40.452796  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1948 23:02:40.456236  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1949 23:02:40.459569  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1950 23:02:40.466130  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1951 23:02:40.469015  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1952 23:02:40.472359  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1953 23:02:40.476119  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1954 23:02:40.479056  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1955 23:02:40.485969  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1956 23:02:40.486050  ==

 1957 23:02:40.489242  Dram Type= 6, Freq= 0, CH_1, rank 1

 1958 23:02:40.492813  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1959 23:02:40.492893  ==

 1960 23:02:40.492956  DQS Delay:

 1961 23:02:40.495617  DQS0 = 0, DQS1 = 0

 1962 23:02:40.495710  DQM Delay:

 1963 23:02:40.499133  DQM0 = 92, DQM1 = 88

 1964 23:02:40.499211  DQ Delay:

 1965 23:02:40.502555  DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85

 1966 23:02:40.506192  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1967 23:02:40.508944  DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85

 1968 23:02:40.512234  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1969 23:02:40.512313  

 1970 23:02:40.512376  

 1971 23:02:40.512434  ==

 1972 23:02:40.515872  Dram Type= 6, Freq= 0, CH_1, rank 1

 1973 23:02:40.519379  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1974 23:02:40.522431  ==

 1975 23:02:40.522510  

 1976 23:02:40.522573  

 1977 23:02:40.522630  	TX Vref Scan disable

 1978 23:02:40.525774   == TX Byte 0 ==

 1979 23:02:40.529072  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1980 23:02:40.532614  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1981 23:02:40.535950   == TX Byte 1 ==

 1982 23:02:40.539441  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1983 23:02:40.542828  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1984 23:02:40.542908  ==

 1985 23:02:40.545912  Dram Type= 6, Freq= 0, CH_1, rank 1

 1986 23:02:40.552213  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1987 23:02:40.552305  ==

 1988 23:02:40.564675  TX Vref=22, minBit 1, minWin=26, winSum=441

 1989 23:02:40.568106  TX Vref=24, minBit 0, minWin=27, winSum=444

 1990 23:02:40.571188  TX Vref=26, minBit 0, minWin=27, winSum=446

 1991 23:02:40.574698  TX Vref=28, minBit 1, minWin=27, winSum=449

 1992 23:02:40.578082  TX Vref=30, minBit 2, minWin=27, winSum=451

 1993 23:02:40.581532  TX Vref=32, minBit 0, minWin=27, winSum=448

 1994 23:02:40.588056  [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30

 1995 23:02:40.588137  

 1996 23:02:40.591247  Final TX Range 1 Vref 30

 1997 23:02:40.591320  

 1998 23:02:40.591379  ==

 1999 23:02:40.594598  Dram Type= 6, Freq= 0, CH_1, rank 1

 2000 23:02:40.598148  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2001 23:02:40.598228  ==

 2002 23:02:40.598290  

 2003 23:02:40.601007  

 2004 23:02:40.601078  	TX Vref Scan disable

 2005 23:02:40.604580   == TX Byte 0 ==

 2006 23:02:40.608185  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 2007 23:02:40.611029  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 2008 23:02:40.614570   == TX Byte 1 ==

 2009 23:02:40.618188  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 2010 23:02:40.621354  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 2011 23:02:40.624580  

 2012 23:02:40.624658  [DATLAT]

 2013 23:02:40.624721  Freq=800, CH1 RK1

 2014 23:02:40.624780  

 2015 23:02:40.628184  DATLAT Default: 0xa

 2016 23:02:40.628263  0, 0xFFFF, sum = 0

 2017 23:02:40.631082  1, 0xFFFF, sum = 0

 2018 23:02:40.631240  2, 0xFFFF, sum = 0

 2019 23:02:40.634430  3, 0xFFFF, sum = 0

 2020 23:02:40.634511  4, 0xFFFF, sum = 0

 2021 23:02:40.638053  5, 0xFFFF, sum = 0

 2022 23:02:40.641414  6, 0xFFFF, sum = 0

 2023 23:02:40.641494  7, 0xFFFF, sum = 0

 2024 23:02:40.644748  8, 0xFFFF, sum = 0

 2025 23:02:40.644828  9, 0x0, sum = 1

 2026 23:02:40.644892  10, 0x0, sum = 2

 2027 23:02:40.647928  11, 0x0, sum = 3

 2028 23:02:40.648008  12, 0x0, sum = 4

 2029 23:02:40.651211  best_step = 10

 2030 23:02:40.651290  

 2031 23:02:40.651367  ==

 2032 23:02:40.654896  Dram Type= 6, Freq= 0, CH_1, rank 1

 2033 23:02:40.658231  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2034 23:02:40.658312  ==

 2035 23:02:40.661694  RX Vref Scan: 0

 2036 23:02:40.661773  

 2037 23:02:40.661835  RX Vref 0 -> 0, step: 1

 2038 23:02:40.661893  

 2039 23:02:40.664960  RX Delay -79 -> 252, step: 8

 2040 23:02:40.671186  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 2041 23:02:40.675011  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 2042 23:02:40.678154  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 2043 23:02:40.681595  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 2044 23:02:40.685058  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 2045 23:02:40.687952  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 2046 23:02:40.694841  iDelay=209, Bit 6, Center 108 (9 ~ 208) 200

 2047 23:02:40.698193  iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208

 2048 23:02:40.701547  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 2049 23:02:40.704720  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 2050 23:02:40.707955  iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216

 2051 23:02:40.714535  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 2052 23:02:40.718097  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 2053 23:02:40.721534  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 2054 23:02:40.724522  iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208

 2055 23:02:40.728358  iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216

 2056 23:02:40.728438  ==

 2057 23:02:40.731428  Dram Type= 6, Freq= 0, CH_1, rank 1

 2058 23:02:40.738088  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2059 23:02:40.738168  ==

 2060 23:02:40.738231  DQS Delay:

 2061 23:02:40.741667  DQS0 = 0, DQS1 = 0

 2062 23:02:40.741746  DQM Delay:

 2063 23:02:40.744567  DQM0 = 97, DQM1 = 91

 2064 23:02:40.744645  DQ Delay:

 2065 23:02:40.748053  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2066 23:02:40.751399  DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96

 2067 23:02:40.755003  DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88

 2068 23:02:40.758396  DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100

 2069 23:02:40.758494  

 2070 23:02:40.758557  

 2071 23:02:40.764628  [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps

 2072 23:02:40.768333  CH1 RK1: MR19=606, MR18=4610

 2073 23:02:40.774741  CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64

 2074 23:02:40.778582  [RxdqsGatingPostProcess] freq 800

 2075 23:02:40.781764  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2076 23:02:40.784726  Pre-setting of DQS Precalculation

 2077 23:02:40.791674  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2078 23:02:40.798248  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2079 23:02:40.804665  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2080 23:02:40.804745  

 2081 23:02:40.804807  

 2082 23:02:40.808104  [Calibration Summary] 1600 Mbps

 2083 23:02:40.808183  CH 0, Rank 0

 2084 23:02:40.811618  SW Impedance     : PASS

 2085 23:02:40.815148  DUTY Scan        : NO K

 2086 23:02:40.815228  ZQ Calibration   : PASS

 2087 23:02:40.818266  Jitter Meter     : NO K

 2088 23:02:40.821500  CBT Training     : PASS

 2089 23:02:40.821600  Write leveling   : PASS

 2090 23:02:40.825281  RX DQS gating    : PASS

 2091 23:02:40.828886  RX DQ/DQS(RDDQC) : PASS

 2092 23:02:40.828965  TX DQ/DQS        : PASS

 2093 23:02:40.831402  RX DATLAT        : PASS

 2094 23:02:40.834749  RX DQ/DQS(Engine): PASS

 2095 23:02:40.834828  TX OE            : NO K

 2096 23:02:40.838089  All Pass.

 2097 23:02:40.838168  

 2098 23:02:40.838229  CH 0, Rank 1

 2099 23:02:40.841869  SW Impedance     : PASS

 2100 23:02:40.841948  DUTY Scan        : NO K

 2101 23:02:40.844753  ZQ Calibration   : PASS

 2102 23:02:40.848279  Jitter Meter     : NO K

 2103 23:02:40.848358  CBT Training     : PASS

 2104 23:02:40.851978  Write leveling   : PASS

 2105 23:02:40.852071  RX DQS gating    : PASS

 2106 23:02:40.855296  RX DQ/DQS(RDDQC) : PASS

 2107 23:02:40.858510  TX DQ/DQS        : PASS

 2108 23:02:40.858589  RX DATLAT        : PASS

 2109 23:02:40.861573  RX DQ/DQS(Engine): PASS

 2110 23:02:40.865096  TX OE            : NO K

 2111 23:02:40.865175  All Pass.

 2112 23:02:40.865237  

 2113 23:02:40.865294  CH 1, Rank 0

 2114 23:02:40.868527  SW Impedance     : PASS

 2115 23:02:40.872115  DUTY Scan        : NO K

 2116 23:02:40.872195  ZQ Calibration   : PASS

 2117 23:02:40.875520  Jitter Meter     : NO K

 2118 23:02:40.878381  CBT Training     : PASS

 2119 23:02:40.878461  Write leveling   : PASS

 2120 23:02:40.882053  RX DQS gating    : PASS

 2121 23:02:40.882145  RX DQ/DQS(RDDQC) : PASS

 2122 23:02:40.885120  TX DQ/DQS        : PASS

 2123 23:02:40.888841  RX DATLAT        : PASS

 2124 23:02:40.888920  RX DQ/DQS(Engine): PASS

 2125 23:02:40.892294  TX OE            : NO K

 2126 23:02:40.892373  All Pass.

 2127 23:02:40.892435  

 2128 23:02:40.895062  CH 1, Rank 1

 2129 23:02:40.895140  SW Impedance     : PASS

 2130 23:02:40.898578  DUTY Scan        : NO K

 2131 23:02:40.902036  ZQ Calibration   : PASS

 2132 23:02:40.902115  Jitter Meter     : NO K

 2133 23:02:40.905202  CBT Training     : PASS

 2134 23:02:40.908525  Write leveling   : PASS

 2135 23:02:40.908604  RX DQS gating    : PASS

 2136 23:02:40.911844  RX DQ/DQS(RDDQC) : PASS

 2137 23:02:40.915047  TX DQ/DQS        : PASS

 2138 23:02:40.915127  RX DATLAT        : PASS

 2139 23:02:40.918902  RX DQ/DQS(Engine): PASS

 2140 23:02:40.918982  TX OE            : NO K

 2141 23:02:40.921951  All Pass.

 2142 23:02:40.922047  

 2143 23:02:40.922110  DramC Write-DBI off

 2144 23:02:40.925433  	PER_BANK_REFRESH: Hybrid Mode

 2145 23:02:40.928456  TX_TRACKING: ON

 2146 23:02:40.931909  [GetDramInforAfterCalByMRR] Vendor 6.

 2147 23:02:40.935151  [GetDramInforAfterCalByMRR] Revision 606.

 2148 23:02:40.938793  [GetDramInforAfterCalByMRR] Revision 2 0.

 2149 23:02:40.938872  MR0 0x3b3b

 2150 23:02:40.938935  MR8 0x5151

 2151 23:02:40.945518  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2152 23:02:40.945611  

 2153 23:02:40.945670  MR0 0x3b3b

 2154 23:02:40.945727  MR8 0x5151

 2155 23:02:40.948589  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2156 23:02:40.948653  

 2157 23:02:40.958822  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2158 23:02:40.961919  [FAST_K] Save calibration result to emmc

 2159 23:02:40.965331  [FAST_K] Save calibration result to emmc

 2160 23:02:40.968846  dram_init: config_dvfs: 1

 2161 23:02:40.971799  dramc_set_vcore_voltage set vcore to 662500

 2162 23:02:40.975362  Read voltage for 1200, 2

 2163 23:02:40.975439  Vio18 = 0

 2164 23:02:40.975520  Vcore = 662500

 2165 23:02:40.978455  Vdram = 0

 2166 23:02:40.978528  Vddq = 0

 2167 23:02:40.978629  Vmddr = 0

 2168 23:02:40.985195  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2169 23:02:40.988503  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2170 23:02:40.991645  MEM_TYPE=3, freq_sel=15

 2171 23:02:40.995650  sv_algorithm_assistance_LP4_1600 

 2172 23:02:40.998319  ============ PULL DRAM RESETB DOWN ============

 2173 23:02:41.005158  ========== PULL DRAM RESETB DOWN end =========

 2174 23:02:41.008389  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2175 23:02:41.011826  =================================== 

 2176 23:02:41.015096  LPDDR4 DRAM CONFIGURATION

 2177 23:02:41.018698  =================================== 

 2178 23:02:41.018798  EX_ROW_EN[0]    = 0x0

 2179 23:02:41.022331  EX_ROW_EN[1]    = 0x0

 2180 23:02:41.022405  LP4Y_EN      = 0x0

 2181 23:02:41.025284  WORK_FSP     = 0x0

 2182 23:02:41.025383  WL           = 0x4

 2183 23:02:41.028826  RL           = 0x4

 2184 23:02:41.028928  BL           = 0x2

 2185 23:02:41.032276  RPST         = 0x0

 2186 23:02:41.032354  RD_PRE       = 0x0

 2187 23:02:41.035815  WR_PRE       = 0x1

 2188 23:02:41.035887  WR_PST       = 0x0

 2189 23:02:41.039036  DBI_WR       = 0x0

 2190 23:02:41.039114  DBI_RD       = 0x0

 2191 23:02:41.042723  OTF          = 0x1

 2192 23:02:41.045497  =================================== 

 2193 23:02:41.048989  =================================== 

 2194 23:02:41.049087  ANA top config

 2195 23:02:41.052428  =================================== 

 2196 23:02:41.055745  DLL_ASYNC_EN            =  0

 2197 23:02:41.058790  ALL_SLAVE_EN            =  0

 2198 23:02:41.061967  NEW_RANK_MODE           =  1

 2199 23:02:41.062042  DLL_IDLE_MODE           =  1

 2200 23:02:41.065454  LP45_APHY_COMB_EN       =  1

 2201 23:02:41.068988  TX_ODT_DIS              =  1

 2202 23:02:41.072506  NEW_8X_MODE             =  1

 2203 23:02:41.075534  =================================== 

 2204 23:02:41.079059  =================================== 

 2205 23:02:41.081962  data_rate                  = 2400

 2206 23:02:41.082040  CKR                        = 1

 2207 23:02:41.085302  DQ_P2S_RATIO               = 8

 2208 23:02:41.088872  =================================== 

 2209 23:02:41.092370  CA_P2S_RATIO               = 8

 2210 23:02:41.095789  DQ_CA_OPEN                 = 0

 2211 23:02:41.098983  DQ_SEMI_OPEN               = 0

 2212 23:02:41.099060  CA_SEMI_OPEN               = 0

 2213 23:02:41.102467  CA_FULL_RATE               = 0

 2214 23:02:41.105501  DQ_CKDIV4_EN               = 0

 2215 23:02:41.108588  CA_CKDIV4_EN               = 0

 2216 23:02:41.112422  CA_PREDIV_EN               = 0

 2217 23:02:41.115433  PH8_DLY                    = 17

 2218 23:02:41.115512  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2219 23:02:41.119003  DQ_AAMCK_DIV               = 4

 2220 23:02:41.122037  CA_AAMCK_DIV               = 4

 2221 23:02:41.125524  CA_ADMCK_DIV               = 4

 2222 23:02:41.129031  DQ_TRACK_CA_EN             = 0

 2223 23:02:41.132182  CA_PICK                    = 1200

 2224 23:02:41.132261  CA_MCKIO                   = 1200

 2225 23:02:41.135905  MCKIO_SEMI                 = 0

 2226 23:02:41.139125  PLL_FREQ                   = 2366

 2227 23:02:41.142936  DQ_UI_PI_RATIO             = 32

 2228 23:02:41.145668  CA_UI_PI_RATIO             = 0

 2229 23:02:41.149180  =================================== 

 2230 23:02:41.152691  =================================== 

 2231 23:02:41.156111  memory_type:LPDDR4         

 2232 23:02:41.156198  GP_NUM     : 10       

 2233 23:02:41.159426  SRAM_EN    : 1       

 2234 23:02:41.159504  MD32_EN    : 0       

 2235 23:02:41.162763  =================================== 

 2236 23:02:41.165966  [ANA_INIT] >>>>>>>>>>>>>> 

 2237 23:02:41.169324  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2238 23:02:41.172749  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2239 23:02:41.175673  =================================== 

 2240 23:02:41.179294  data_rate = 2400,PCW = 0X5b00

 2241 23:02:41.182819  =================================== 

 2242 23:02:41.186219  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2243 23:02:41.189026  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2244 23:02:41.195756  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2245 23:02:41.199346  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2246 23:02:41.202661  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2247 23:02:41.209129  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2248 23:02:41.209204  [ANA_INIT] flow start 

 2249 23:02:41.212483  [ANA_INIT] PLL >>>>>>>> 

 2250 23:02:41.212558  [ANA_INIT] PLL <<<<<<<< 

 2251 23:02:41.215983  [ANA_INIT] MIDPI >>>>>>>> 

 2252 23:02:41.219193  [ANA_INIT] MIDPI <<<<<<<< 

 2253 23:02:41.222616  [ANA_INIT] DLL >>>>>>>> 

 2254 23:02:41.222696  [ANA_INIT] DLL <<<<<<<< 

 2255 23:02:41.225941  [ANA_INIT] flow end 

 2256 23:02:41.229758  ============ LP4 DIFF to SE enter ============

 2257 23:02:41.232798  ============ LP4 DIFF to SE exit  ============

 2258 23:02:41.236366  [ANA_INIT] <<<<<<<<<<<<< 

 2259 23:02:41.239223  [Flow] Enable top DCM control >>>>> 

 2260 23:02:41.242575  [Flow] Enable top DCM control <<<<< 

 2261 23:02:41.246219  Enable DLL master slave shuffle 

 2262 23:02:41.252924  ============================================================== 

 2263 23:02:41.253004  Gating Mode config

 2264 23:02:41.259577  ============================================================== 

 2265 23:02:41.259658  Config description: 

 2266 23:02:41.269188  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2267 23:02:41.275796  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2268 23:02:41.282689  SELPH_MODE            0: By rank         1: By Phase 

 2269 23:02:41.286332  ============================================================== 

 2270 23:02:41.289758  GAT_TRACK_EN                 =  1

 2271 23:02:41.293073  RX_GATING_MODE               =  2

 2272 23:02:41.295990  RX_GATING_TRACK_MODE         =  2

 2273 23:02:41.299536  SELPH_MODE                   =  1

 2274 23:02:41.303132  PICG_EARLY_EN                =  1

 2275 23:02:41.306053  VALID_LAT_VALUE              =  1

 2276 23:02:41.309966  ============================================================== 

 2277 23:02:41.312983  Enter into Gating configuration >>>> 

 2278 23:02:41.316480  Exit from Gating configuration <<<< 

 2279 23:02:41.319974  Enter into  DVFS_PRE_config >>>>> 

 2280 23:02:41.333286  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2281 23:02:41.333373  Exit from  DVFS_PRE_config <<<<< 

 2282 23:02:41.336574  Enter into PICG configuration >>>> 

 2283 23:02:41.339703  Exit from PICG configuration <<<< 

 2284 23:02:41.343191  [RX_INPUT] configuration >>>>> 

 2285 23:02:41.346387  [RX_INPUT] configuration <<<<< 

 2286 23:02:41.352713  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2287 23:02:41.356116  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2288 23:02:41.363433  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2289 23:02:41.369705  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2290 23:02:41.376059  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2291 23:02:41.383127  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2292 23:02:41.386556  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2293 23:02:41.389496  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2294 23:02:41.393091  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2295 23:02:41.400215  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2296 23:02:41.403033  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2297 23:02:41.406413  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2298 23:02:41.409853  =================================== 

 2299 23:02:41.413130  LPDDR4 DRAM CONFIGURATION

 2300 23:02:41.416291  =================================== 

 2301 23:02:41.416370  EX_ROW_EN[0]    = 0x0

 2302 23:02:41.419555  EX_ROW_EN[1]    = 0x0

 2303 23:02:41.419634  LP4Y_EN      = 0x0

 2304 23:02:41.423081  WORK_FSP     = 0x0

 2305 23:02:41.423160  WL           = 0x4

 2306 23:02:41.426604  RL           = 0x4

 2307 23:02:41.426682  BL           = 0x2

 2308 23:02:41.430068  RPST         = 0x0

 2309 23:02:41.430147  RD_PRE       = 0x0

 2310 23:02:41.433457  WR_PRE       = 0x1

 2311 23:02:41.436694  WR_PST       = 0x0

 2312 23:02:41.436772  DBI_WR       = 0x0

 2313 23:02:41.440151  DBI_RD       = 0x0

 2314 23:02:41.440230  OTF          = 0x1

 2315 23:02:41.443252  =================================== 

 2316 23:02:41.446820  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2317 23:02:41.449749  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2318 23:02:41.456393  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2319 23:02:41.459839  =================================== 

 2320 23:02:41.463217  LPDDR4 DRAM CONFIGURATION

 2321 23:02:41.466581  =================================== 

 2322 23:02:41.466661  EX_ROW_EN[0]    = 0x10

 2323 23:02:41.469815  EX_ROW_EN[1]    = 0x0

 2324 23:02:41.469894  LP4Y_EN      = 0x0

 2325 23:02:41.473369  WORK_FSP     = 0x0

 2326 23:02:41.473448  WL           = 0x4

 2327 23:02:41.476550  RL           = 0x4

 2328 23:02:41.476629  BL           = 0x2

 2329 23:02:41.479685  RPST         = 0x0

 2330 23:02:41.479764  RD_PRE       = 0x0

 2331 23:02:41.483448  WR_PRE       = 0x1

 2332 23:02:41.483529  WR_PST       = 0x0

 2333 23:02:41.486719  DBI_WR       = 0x0

 2334 23:02:41.486802  DBI_RD       = 0x0

 2335 23:02:41.490054  OTF          = 0x1

 2336 23:02:41.493187  =================================== 

 2337 23:02:41.499788  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2338 23:02:41.499871  ==

 2339 23:02:41.503214  Dram Type= 6, Freq= 0, CH_0, rank 0

 2340 23:02:41.506765  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2341 23:02:41.506843  ==

 2342 23:02:41.509730  [Duty_Offset_Calibration]

 2343 23:02:41.509809  	B0:2	B1:1	CA:1

 2344 23:02:41.509888  

 2345 23:02:41.513337  [DutyScan_Calibration_Flow] k_type=0

 2346 23:02:41.523579  

 2347 23:02:41.523661  ==CLK 0==

 2348 23:02:41.527108  Final CLK duty delay cell = 0

 2349 23:02:41.530196  [0] MAX Duty = 5187%(X100), DQS PI = 24

 2350 23:02:41.533752  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2351 23:02:41.533825  [0] AVG Duty = 5031%(X100)

 2352 23:02:41.536918  

 2353 23:02:41.536989  CH0 CLK Duty spec in!! Max-Min= 312%

 2354 23:02:41.543557  [DutyScan_Calibration_Flow] ====Done====

 2355 23:02:41.543662  

 2356 23:02:41.546782  [DutyScan_Calibration_Flow] k_type=1

 2357 23:02:41.562354  

 2358 23:02:41.562440  ==DQS 0 ==

 2359 23:02:41.565858  Final DQS duty delay cell = -4

 2360 23:02:41.568881  [-4] MAX Duty = 5124%(X100), DQS PI = 22

 2361 23:02:41.572158  [-4] MIN Duty = 4782%(X100), DQS PI = 0

 2362 23:02:41.575679  [-4] AVG Duty = 4953%(X100)

 2363 23:02:41.575757  

 2364 23:02:41.575818  ==DQS 1 ==

 2365 23:02:41.579095  Final DQS duty delay cell = 0

 2366 23:02:41.581850  [0] MAX Duty = 5156%(X100), DQS PI = 46

 2367 23:02:41.585426  [0] MIN Duty = 5000%(X100), DQS PI = 34

 2368 23:02:41.588863  [0] AVG Duty = 5078%(X100)

 2369 23:02:41.588941  

 2370 23:02:41.592467  CH0 DQS 0 Duty spec in!! Max-Min= 342%

 2371 23:02:41.592546  

 2372 23:02:41.595557  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 2373 23:02:41.598977  [DutyScan_Calibration_Flow] ====Done====

 2374 23:02:41.599056  

 2375 23:02:41.602010  [DutyScan_Calibration_Flow] k_type=3

 2376 23:02:41.619093  

 2377 23:02:41.619233  ==DQM 0 ==

 2378 23:02:41.622636  Final DQM duty delay cell = 0

 2379 23:02:41.625396  [0] MAX Duty = 5156%(X100), DQS PI = 30

 2380 23:02:41.628938  [0] MIN Duty = 4906%(X100), DQS PI = 52

 2381 23:02:41.632330  [0] AVG Duty = 5031%(X100)

 2382 23:02:41.632411  

 2383 23:02:41.632474  ==DQM 1 ==

 2384 23:02:41.635460  Final DQM duty delay cell = 0

 2385 23:02:41.638919  [0] MAX Duty = 5093%(X100), DQS PI = 0

 2386 23:02:41.642180  [0] MIN Duty = 5031%(X100), DQS PI = 16

 2387 23:02:41.642259  [0] AVG Duty = 5062%(X100)

 2388 23:02:41.645678  

 2389 23:02:41.649128  CH0 DQM 0 Duty spec in!! Max-Min= 250%

 2390 23:02:41.649207  

 2391 23:02:41.652246  CH0 DQM 1 Duty spec in!! Max-Min= 62%

 2392 23:02:41.655499  [DutyScan_Calibration_Flow] ====Done====

 2393 23:02:41.655578  

 2394 23:02:41.658894  [DutyScan_Calibration_Flow] k_type=2

 2395 23:02:41.675608  

 2396 23:02:41.675691  ==DQ 0 ==

 2397 23:02:41.679002  Final DQ duty delay cell = 0

 2398 23:02:41.682143  [0] MAX Duty = 5062%(X100), DQS PI = 34

 2399 23:02:41.685821  [0] MIN Duty = 4875%(X100), DQS PI = 62

 2400 23:02:41.685902  [0] AVG Duty = 4968%(X100)

 2401 23:02:41.685965  

 2402 23:02:41.689194  ==DQ 1 ==

 2403 23:02:41.692180  Final DQ duty delay cell = 0

 2404 23:02:41.695447  [0] MAX Duty = 5093%(X100), DQS PI = 26

 2405 23:02:41.698565  [0] MIN Duty = 4938%(X100), DQS PI = 36

 2406 23:02:41.698645  [0] AVG Duty = 5015%(X100)

 2407 23:02:41.698708  

 2408 23:02:41.701916  CH0 DQ 0 Duty spec in!! Max-Min= 187%

 2409 23:02:41.705411  

 2410 23:02:41.708875  CH0 DQ 1 Duty spec in!! Max-Min= 155%

 2411 23:02:41.711814  [DutyScan_Calibration_Flow] ====Done====

 2412 23:02:41.711893  ==

 2413 23:02:41.715293  Dram Type= 6, Freq= 0, CH_1, rank 0

 2414 23:02:41.719160  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2415 23:02:41.719240  ==

 2416 23:02:41.722184  [Duty_Offset_Calibration]

 2417 23:02:41.722268  	B0:1	B1:0	CA:0

 2418 23:02:41.722330  

 2419 23:02:41.725274  [DutyScan_Calibration_Flow] k_type=0

 2420 23:02:41.734692  

 2421 23:02:41.734771  ==CLK 0==

 2422 23:02:41.738046  Final CLK duty delay cell = -4

 2423 23:02:41.741183  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2424 23:02:41.744418  [-4] MIN Duty = 4875%(X100), DQS PI = 50

 2425 23:02:41.748025  [-4] AVG Duty = 4953%(X100)

 2426 23:02:41.748105  

 2427 23:02:41.751595  CH1 CLK Duty spec in!! Max-Min= 156%

 2428 23:02:41.754807  [DutyScan_Calibration_Flow] ====Done====

 2429 23:02:41.754888  

 2430 23:02:41.758334  [DutyScan_Calibration_Flow] k_type=1

 2431 23:02:41.774436  

 2432 23:02:41.774516  ==DQS 0 ==

 2433 23:02:41.778032  Final DQS duty delay cell = 0

 2434 23:02:41.781110  [0] MAX Duty = 5094%(X100), DQS PI = 24

 2435 23:02:41.784660  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2436 23:02:41.787419  [0] AVG Duty = 4984%(X100)

 2437 23:02:41.787500  

 2438 23:02:41.787562  ==DQS 1 ==

 2439 23:02:41.790711  Final DQS duty delay cell = 0

 2440 23:02:41.794064  [0] MAX Duty = 5187%(X100), DQS PI = 18

 2441 23:02:41.797505  [0] MIN Duty = 4938%(X100), DQS PI = 10

 2442 23:02:41.801129  [0] AVG Duty = 5062%(X100)

 2443 23:02:41.801207  

 2444 23:02:41.803930  CH1 DQS 0 Duty spec in!! Max-Min= 219%

 2445 23:02:41.804009  

 2446 23:02:41.807356  CH1 DQS 1 Duty spec in!! Max-Min= 249%

 2447 23:02:41.810896  [DutyScan_Calibration_Flow] ====Done====

 2448 23:02:41.810975  

 2449 23:02:41.813935  [DutyScan_Calibration_Flow] k_type=3

 2450 23:02:41.830930  

 2451 23:02:41.831009  ==DQM 0 ==

 2452 23:02:41.834288  Final DQM duty delay cell = 0

 2453 23:02:41.837459  [0] MAX Duty = 5156%(X100), DQS PI = 8

 2454 23:02:41.841130  [0] MIN Duty = 5000%(X100), DQS PI = 62

 2455 23:02:41.841210  [0] AVG Duty = 5078%(X100)

 2456 23:02:41.844083  

 2457 23:02:41.844161  ==DQM 1 ==

 2458 23:02:41.848094  Final DQM duty delay cell = 0

 2459 23:02:41.850768  [0] MAX Duty = 5031%(X100), DQS PI = 16

 2460 23:02:41.854140  [0] MIN Duty = 4907%(X100), DQS PI = 34

 2461 23:02:41.854219  [0] AVG Duty = 4969%(X100)

 2462 23:02:41.857533  

 2463 23:02:41.861074  CH1 DQM 0 Duty spec in!! Max-Min= 156%

 2464 23:02:41.861154  

 2465 23:02:41.864250  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2466 23:02:41.867514  [DutyScan_Calibration_Flow] ====Done====

 2467 23:02:41.867593  

 2468 23:02:41.871143  [DutyScan_Calibration_Flow] k_type=2

 2469 23:02:41.886980  

 2470 23:02:41.887064  ==DQ 0 ==

 2471 23:02:41.890004  Final DQ duty delay cell = -4

 2472 23:02:41.893429  [-4] MAX Duty = 5062%(X100), DQS PI = 8

 2473 23:02:41.896946  [-4] MIN Duty = 4938%(X100), DQS PI = 0

 2474 23:02:41.900200  [-4] AVG Duty = 5000%(X100)

 2475 23:02:41.900280  

 2476 23:02:41.900358  ==DQ 1 ==

 2477 23:02:41.903172  Final DQ duty delay cell = 0

 2478 23:02:41.906603  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2479 23:02:41.910108  [0] MIN Duty = 4938%(X100), DQS PI = 34

 2480 23:02:41.910188  [0] AVG Duty = 5031%(X100)

 2481 23:02:41.913038  

 2482 23:02:41.916615  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2483 23:02:41.916697  

 2484 23:02:41.920171  CH1 DQ 1 Duty spec in!! Max-Min= 187%

 2485 23:02:41.923181  [DutyScan_Calibration_Flow] ====Done====

 2486 23:02:41.926705  nWR fixed to 30

 2487 23:02:41.929475  [ModeRegInit_LP4] CH0 RK0

 2488 23:02:41.929554  [ModeRegInit_LP4] CH0 RK1

 2489 23:02:41.933076  [ModeRegInit_LP4] CH1 RK0

 2490 23:02:41.936583  [ModeRegInit_LP4] CH1 RK1

 2491 23:02:41.936662  match AC timing 7

 2492 23:02:41.942882  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2493 23:02:41.946409  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2494 23:02:41.949764  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2495 23:02:41.956536  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2496 23:02:41.959699  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2497 23:02:41.959779  ==

 2498 23:02:41.962763  Dram Type= 6, Freq= 0, CH_0, rank 0

 2499 23:02:41.966617  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2500 23:02:41.966697  ==

 2501 23:02:41.972791  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2502 23:02:41.979668  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2503 23:02:41.986686  [CA 0] Center 39 (8~70) winsize 63

 2504 23:02:41.990228  [CA 1] Center 39 (8~70) winsize 63

 2505 23:02:41.993570  [CA 2] Center 35 (5~66) winsize 62

 2506 23:02:41.996769  [CA 3] Center 34 (4~65) winsize 62

 2507 23:02:42.000298  [CA 4] Center 33 (3~64) winsize 62

 2508 23:02:42.003545  [CA 5] Center 32 (3~62) winsize 60

 2509 23:02:42.003624  

 2510 23:02:42.007238  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2511 23:02:42.007319  

 2512 23:02:42.010515  [CATrainingPosCal] consider 1 rank data

 2513 23:02:42.013790  u2DelayCellTimex100 = 270/100 ps

 2514 23:02:42.017292  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2515 23:02:42.020784  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2516 23:02:42.023779  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2517 23:02:42.030589  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2518 23:02:42.034016  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2519 23:02:42.036978  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2520 23:02:42.037057  

 2521 23:02:42.040627  CA PerBit enable=1, Macro0, CA PI delay=32

 2522 23:02:42.040723  

 2523 23:02:42.043550  [CBTSetCACLKResult] CA Dly = 32

 2524 23:02:42.043629  CS Dly: 6 (0~37)

 2525 23:02:42.043691  ==

 2526 23:02:42.047062  Dram Type= 6, Freq= 0, CH_0, rank 1

 2527 23:02:42.053893  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2528 23:02:42.053988  ==

 2529 23:02:42.057496  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2530 23:02:42.064061  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2531 23:02:42.072692  [CA 0] Center 38 (8~69) winsize 62

 2532 23:02:42.076361  [CA 1] Center 38 (8~69) winsize 62

 2533 23:02:42.079141  [CA 2] Center 35 (5~66) winsize 62

 2534 23:02:42.082615  [CA 3] Center 34 (4~65) winsize 62

 2535 23:02:42.086137  [CA 4] Center 33 (3~64) winsize 62

 2536 23:02:42.089326  [CA 5] Center 32 (3~62) winsize 60

 2537 23:02:42.089406  

 2538 23:02:42.092744  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2539 23:02:42.092840  

 2540 23:02:42.096085  [CATrainingPosCal] consider 2 rank data

 2541 23:02:42.099268  u2DelayCellTimex100 = 270/100 ps

 2542 23:02:42.102317  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2543 23:02:42.105633  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2544 23:02:42.112632  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2545 23:02:42.116101  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2546 23:02:42.119143  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2547 23:02:42.122792  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2548 23:02:42.122872  

 2549 23:02:42.125887  CA PerBit enable=1, Macro0, CA PI delay=32

 2550 23:02:42.125966  

 2551 23:02:42.129511  [CBTSetCACLKResult] CA Dly = 32

 2552 23:02:42.129615  CS Dly: 6 (0~38)

 2553 23:02:42.129680  

 2554 23:02:42.132588  ----->DramcWriteLeveling(PI) begin...

 2555 23:02:42.136028  ==

 2556 23:02:42.136108  Dram Type= 6, Freq= 0, CH_0, rank 0

 2557 23:02:42.142628  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2558 23:02:42.142708  ==

 2559 23:02:42.145726  Write leveling (Byte 0): 33 => 33

 2560 23:02:42.149173  Write leveling (Byte 1): 29 => 29

 2561 23:02:42.152660  DramcWriteLeveling(PI) end<-----

 2562 23:02:42.152739  

 2563 23:02:42.152800  ==

 2564 23:02:42.156159  Dram Type= 6, Freq= 0, CH_0, rank 0

 2565 23:02:42.159569  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2566 23:02:42.159648  ==

 2567 23:02:42.162424  [Gating] SW mode calibration

 2568 23:02:42.169257  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2569 23:02:42.172764  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2570 23:02:42.179295   0 15  0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)

 2571 23:02:42.182586   0 15  4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)

 2572 23:02:42.185967   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2573 23:02:42.192964   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2574 23:02:42.196125   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2575 23:02:42.199334   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2576 23:02:42.205716   0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 2577 23:02:42.209058   0 15 28 | B1->B0 | 3434 2626 | 0 0 | (0 0) (1 0)

 2578 23:02:42.212468   1  0  0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)

 2579 23:02:42.219247   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2580 23:02:42.222639   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2581 23:02:42.225753   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2582 23:02:42.232502   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2583 23:02:42.235552   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2584 23:02:42.238804   1  0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 2585 23:02:42.245730   1  0 28 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)

 2586 23:02:42.249094   1  1  0 | B1->B0 | 3434 4646 | 1 0 | (0 0) (0 0)

 2587 23:02:42.252632   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2588 23:02:42.259012   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2589 23:02:42.262375   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2590 23:02:42.266042   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2591 23:02:42.272187   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2592 23:02:42.275578   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2593 23:02:42.279226   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2594 23:02:42.282725   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2595 23:02:42.289049   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2596 23:02:42.292430   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2597 23:02:42.295972   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2598 23:02:42.302665   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2599 23:02:42.305484   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2600 23:02:42.309037   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2601 23:02:42.315667   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2602 23:02:42.319226   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2603 23:02:42.322720   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2604 23:02:42.329259   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2605 23:02:42.332587   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2606 23:02:42.335622   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2607 23:02:42.342731   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2608 23:02:42.345743   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2609 23:02:42.349329   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2610 23:02:42.356214   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2611 23:02:42.356319  Total UI for P1: 0, mck2ui 16

 2612 23:02:42.359364  best dqsien dly found for B0: ( 1,  3, 26)

 2613 23:02:42.366011   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2614 23:02:42.369357  Total UI for P1: 0, mck2ui 16

 2615 23:02:42.373019  best dqsien dly found for B1: ( 1,  4,  0)

 2616 23:02:42.376399  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2617 23:02:42.379403  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2618 23:02:42.379482  

 2619 23:02:42.382820  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2620 23:02:42.386463  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2621 23:02:42.389428  [Gating] SW calibration Done

 2622 23:02:42.389506  ==

 2623 23:02:42.392845  Dram Type= 6, Freq= 0, CH_0, rank 0

 2624 23:02:42.396342  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2625 23:02:42.396421  ==

 2626 23:02:42.399688  RX Vref Scan: 0

 2627 23:02:42.399766  

 2628 23:02:42.399829  RX Vref 0 -> 0, step: 1

 2629 23:02:42.399886  

 2630 23:02:42.402615  RX Delay -40 -> 252, step: 8

 2631 23:02:42.406186  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2632 23:02:42.412694  iDelay=200, Bit 1, Center 127 (56 ~ 199) 144

 2633 23:02:42.416078  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2634 23:02:42.419459  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2635 23:02:42.422961  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2636 23:02:42.426482  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2637 23:02:42.433027  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2638 23:02:42.436156  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2639 23:02:42.439399  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2640 23:02:42.442792  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2641 23:02:42.446300  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2642 23:02:42.449509  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2643 23:02:42.456624  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 2644 23:02:42.459745  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2645 23:02:42.462816  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2646 23:02:42.466614  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 2647 23:02:42.466699  ==

 2648 23:02:42.469648  Dram Type= 6, Freq= 0, CH_0, rank 0

 2649 23:02:42.476260  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2650 23:02:42.476335  ==

 2651 23:02:42.476405  DQS Delay:

 2652 23:02:42.479516  DQS0 = 0, DQS1 = 0

 2653 23:02:42.479618  DQM Delay:

 2654 23:02:42.479701  DQM0 = 121, DQM1 = 114

 2655 23:02:42.482858  DQ Delay:

 2656 23:02:42.486343  DQ0 =119, DQ1 =127, DQ2 =119, DQ3 =119

 2657 23:02:42.489817  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2658 23:02:42.493397  DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107

 2659 23:02:42.496513  DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =123

 2660 23:02:42.496613  

 2661 23:02:42.496700  

 2662 23:02:42.496787  ==

 2663 23:02:42.499566  Dram Type= 6, Freq= 0, CH_0, rank 0

 2664 23:02:42.503000  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2665 23:02:42.506511  ==

 2666 23:02:42.506582  

 2667 23:02:42.506641  

 2668 23:02:42.506697  	TX Vref Scan disable

 2669 23:02:42.509459   == TX Byte 0 ==

 2670 23:02:42.513082  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2671 23:02:42.516315  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2672 23:02:42.519676   == TX Byte 1 ==

 2673 23:02:42.523046  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2674 23:02:42.526375  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2675 23:02:42.526455  ==

 2676 23:02:42.529981  Dram Type= 6, Freq= 0, CH_0, rank 0

 2677 23:02:42.536536  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2678 23:02:42.536615  ==

 2679 23:02:42.547565  TX Vref=22, minBit 0, minWin=25, winSum=407

 2680 23:02:42.551193  TX Vref=24, minBit 1, minWin=25, winSum=416

 2681 23:02:42.554017  TX Vref=26, minBit 7, minWin=25, winSum=418

 2682 23:02:42.557412  TX Vref=28, minBit 0, minWin=26, winSum=423

 2683 23:02:42.561022  TX Vref=30, minBit 3, minWin=26, winSum=426

 2684 23:02:42.564412  TX Vref=32, minBit 0, minWin=26, winSum=421

 2685 23:02:42.571013  [TxChooseVref] Worse bit 3, Min win 26, Win sum 426, Final Vref 30

 2686 23:02:42.571115  

 2687 23:02:42.574394  Final TX Range 1 Vref 30

 2688 23:02:42.574478  

 2689 23:02:42.574540  ==

 2690 23:02:42.577398  Dram Type= 6, Freq= 0, CH_0, rank 0

 2691 23:02:42.580728  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2692 23:02:42.580828  ==

 2693 23:02:42.580918  

 2694 23:02:42.584304  

 2695 23:02:42.584409  	TX Vref Scan disable

 2696 23:02:42.587570   == TX Byte 0 ==

 2697 23:02:42.590713  Update DQ  dly =851 (3 ,2, 19)  DQ  OEN =(2 ,7)

 2698 23:02:42.593851  Update DQM dly =851 (3 ,2, 19)  DQM OEN =(2 ,7)

 2699 23:02:42.597312   == TX Byte 1 ==

 2700 23:02:42.600850  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2701 23:02:42.604403  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2702 23:02:42.604488  

 2703 23:02:42.607575  [DATLAT]

 2704 23:02:42.607649  Freq=1200, CH0 RK0

 2705 23:02:42.607743  

 2706 23:02:42.610448  DATLAT Default: 0xd

 2707 23:02:42.610516  0, 0xFFFF, sum = 0

 2708 23:02:42.614074  1, 0xFFFF, sum = 0

 2709 23:02:42.614152  2, 0xFFFF, sum = 0

 2710 23:02:42.617304  3, 0xFFFF, sum = 0

 2711 23:02:42.617385  4, 0xFFFF, sum = 0

 2712 23:02:42.620794  5, 0xFFFF, sum = 0

 2713 23:02:42.620870  6, 0xFFFF, sum = 0

 2714 23:02:42.623989  7, 0xFFFF, sum = 0

 2715 23:02:42.624065  8, 0xFFFF, sum = 0

 2716 23:02:42.627356  9, 0xFFFF, sum = 0

 2717 23:02:42.630803  10, 0xFFFF, sum = 0

 2718 23:02:42.630916  11, 0xFFFF, sum = 0

 2719 23:02:42.634070  12, 0x0, sum = 1

 2720 23:02:42.634182  13, 0x0, sum = 2

 2721 23:02:42.634281  14, 0x0, sum = 3

 2722 23:02:42.637523  15, 0x0, sum = 4

 2723 23:02:42.637620  best_step = 13

 2724 23:02:42.637712  

 2725 23:02:42.641037  ==

 2726 23:02:42.641136  Dram Type= 6, Freq= 0, CH_0, rank 0

 2727 23:02:42.647549  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2728 23:02:42.647671  ==

 2729 23:02:42.647754  RX Vref Scan: 1

 2730 23:02:42.647816  

 2731 23:02:42.650893  Set Vref Range= 32 -> 127

 2732 23:02:42.650979  

 2733 23:02:42.653805  RX Vref 32 -> 127, step: 1

 2734 23:02:42.653915  

 2735 23:02:42.657245  RX Delay -13 -> 252, step: 4

 2736 23:02:42.657356  

 2737 23:02:42.660776  Set Vref, RX VrefLevel [Byte0]: 32

 2738 23:02:42.663643                           [Byte1]: 32

 2739 23:02:42.663743  

 2740 23:02:42.667634  Set Vref, RX VrefLevel [Byte0]: 33

 2741 23:02:42.670937                           [Byte1]: 33

 2742 23:02:42.671034  

 2743 23:02:42.673848  Set Vref, RX VrefLevel [Byte0]: 34

 2744 23:02:42.677051                           [Byte1]: 34

 2745 23:02:42.681433  

 2746 23:02:42.681533  Set Vref, RX VrefLevel [Byte0]: 35

 2747 23:02:42.684810                           [Byte1]: 35

 2748 23:02:42.689441  

 2749 23:02:42.689592  Set Vref, RX VrefLevel [Byte0]: 36

 2750 23:02:42.692340                           [Byte1]: 36

 2751 23:02:42.696962  

 2752 23:02:42.697073  Set Vref, RX VrefLevel [Byte0]: 37

 2753 23:02:42.700911                           [Byte1]: 37

 2754 23:02:42.704865  

 2755 23:02:42.705002  Set Vref, RX VrefLevel [Byte0]: 38

 2756 23:02:42.708384                           [Byte1]: 38

 2757 23:02:42.712805  

 2758 23:02:42.712890  Set Vref, RX VrefLevel [Byte0]: 39

 2759 23:02:42.716224                           [Byte1]: 39

 2760 23:02:42.721050  

 2761 23:02:42.721141  Set Vref, RX VrefLevel [Byte0]: 40

 2762 23:02:42.724202                           [Byte1]: 40

 2763 23:02:42.728998  

 2764 23:02:42.729136  Set Vref, RX VrefLevel [Byte0]: 41

 2765 23:02:42.731930                           [Byte1]: 41

 2766 23:02:42.736480  

 2767 23:02:42.736593  Set Vref, RX VrefLevel [Byte0]: 42

 2768 23:02:42.739783                           [Byte1]: 42

 2769 23:02:42.744443  

 2770 23:02:42.744574  Set Vref, RX VrefLevel [Byte0]: 43

 2771 23:02:42.747666                           [Byte1]: 43

 2772 23:02:42.752500  

 2773 23:02:42.752594  Set Vref, RX VrefLevel [Byte0]: 44

 2774 23:02:42.755723                           [Byte1]: 44

 2775 23:02:42.760285  

 2776 23:02:42.760387  Set Vref, RX VrefLevel [Byte0]: 45

 2777 23:02:42.763323                           [Byte1]: 45

 2778 23:02:42.768355  

 2779 23:02:42.768459  Set Vref, RX VrefLevel [Byte0]: 46

 2780 23:02:42.771701                           [Byte1]: 46

 2781 23:02:42.776513  

 2782 23:02:42.776618  Set Vref, RX VrefLevel [Byte0]: 47

 2783 23:02:42.779356                           [Byte1]: 47

 2784 23:02:42.783790  

 2785 23:02:42.783884  Set Vref, RX VrefLevel [Byte0]: 48

 2786 23:02:42.787103                           [Byte1]: 48

 2787 23:02:42.791792  

 2788 23:02:42.791916  Set Vref, RX VrefLevel [Byte0]: 49

 2789 23:02:42.795126                           [Byte1]: 49

 2790 23:02:42.799775  

 2791 23:02:42.799872  Set Vref, RX VrefLevel [Byte0]: 50

 2792 23:02:42.803063                           [Byte1]: 50

 2793 23:02:42.807738  

 2794 23:02:42.807826  Set Vref, RX VrefLevel [Byte0]: 51

 2795 23:02:42.811133                           [Byte1]: 51

 2796 23:02:42.815768  

 2797 23:02:42.815875  Set Vref, RX VrefLevel [Byte0]: 52

 2798 23:02:42.818603                           [Byte1]: 52

 2799 23:02:42.823163  

 2800 23:02:42.823251  Set Vref, RX VrefLevel [Byte0]: 53

 2801 23:02:42.826484                           [Byte1]: 53

 2802 23:02:42.831428  

 2803 23:02:42.831559  Set Vref, RX VrefLevel [Byte0]: 54

 2804 23:02:42.834551                           [Byte1]: 54

 2805 23:02:42.838876  

 2806 23:02:42.838968  Set Vref, RX VrefLevel [Byte0]: 55

 2807 23:02:42.842853                           [Byte1]: 55

 2808 23:02:42.847194  

 2809 23:02:42.847289  Set Vref, RX VrefLevel [Byte0]: 56

 2810 23:02:42.850352                           [Byte1]: 56

 2811 23:02:42.854764  

 2812 23:02:42.854861  Set Vref, RX VrefLevel [Byte0]: 57

 2813 23:02:42.858256                           [Byte1]: 57

 2814 23:02:42.862865  

 2815 23:02:42.862982  Set Vref, RX VrefLevel [Byte0]: 58

 2816 23:02:42.866265                           [Byte1]: 58

 2817 23:02:42.870433  

 2818 23:02:42.874070  Set Vref, RX VrefLevel [Byte0]: 59

 2819 23:02:42.877326                           [Byte1]: 59

 2820 23:02:42.877422  

 2821 23:02:42.880817  Set Vref, RX VrefLevel [Byte0]: 60

 2822 23:02:42.883874                           [Byte1]: 60

 2823 23:02:42.883970  

 2824 23:02:42.887254  Set Vref, RX VrefLevel [Byte0]: 61

 2825 23:02:42.890825                           [Byte1]: 61

 2826 23:02:42.894646  

 2827 23:02:42.894734  Set Vref, RX VrefLevel [Byte0]: 62

 2828 23:02:42.897908                           [Byte1]: 62

 2829 23:02:42.902056  

 2830 23:02:42.902150  Set Vref, RX VrefLevel [Byte0]: 63

 2831 23:02:42.905539                           [Byte1]: 63

 2832 23:02:42.910140  

 2833 23:02:42.910226  Set Vref, RX VrefLevel [Byte0]: 64

 2834 23:02:42.913620                           [Byte1]: 64

 2835 23:02:42.918289  

 2836 23:02:42.918375  Set Vref, RX VrefLevel [Byte0]: 65

 2837 23:02:42.921146                           [Byte1]: 65

 2838 23:02:42.926047  

 2839 23:02:42.926134  Set Vref, RX VrefLevel [Byte0]: 66

 2840 23:02:42.929192                           [Byte1]: 66

 2841 23:02:42.933756  

 2842 23:02:42.933841  Set Vref, RX VrefLevel [Byte0]: 67

 2843 23:02:42.937077                           [Byte1]: 67

 2844 23:02:42.942023  

 2845 23:02:42.942116  Set Vref, RX VrefLevel [Byte0]: 68

 2846 23:02:42.945270                           [Byte1]: 68

 2847 23:02:42.949997  

 2848 23:02:42.950100  Final RX Vref Byte 0 = 54 to rank0

 2849 23:02:42.952838  Final RX Vref Byte 1 = 48 to rank0

 2850 23:02:42.956222  Final RX Vref Byte 0 = 54 to rank1

 2851 23:02:42.959435  Final RX Vref Byte 1 = 48 to rank1==

 2852 23:02:42.962818  Dram Type= 6, Freq= 0, CH_0, rank 0

 2853 23:02:42.969360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2854 23:02:42.969485  ==

 2855 23:02:42.969605  DQS Delay:

 2856 23:02:42.969701  DQS0 = 0, DQS1 = 0

 2857 23:02:42.972994  DQM Delay:

 2858 23:02:42.973090  DQM0 = 120, DQM1 = 112

 2859 23:02:42.975840  DQ Delay:

 2860 23:02:42.979202  DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118

 2861 23:02:42.982762  DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126

 2862 23:02:42.986513  DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106

 2863 23:02:42.989228  DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122

 2864 23:02:42.989312  

 2865 23:02:42.989375  

 2866 23:02:42.999206  [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps

 2867 23:02:42.999327  CH0 RK0: MR19=404, MR18=140D

 2868 23:02:43.006310  CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27

 2869 23:02:43.006439  

 2870 23:02:43.009042  ----->DramcWriteLeveling(PI) begin...

 2871 23:02:43.009149  ==

 2872 23:02:43.012709  Dram Type= 6, Freq= 0, CH_0, rank 1

 2873 23:02:43.019250  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2874 23:02:43.019345  ==

 2875 23:02:43.022705  Write leveling (Byte 0): 33 => 33

 2876 23:02:43.022792  Write leveling (Byte 1): 28 => 28

 2877 23:02:43.026226  DramcWriteLeveling(PI) end<-----

 2878 23:02:43.026309  

 2879 23:02:43.026374  ==

 2880 23:02:43.029207  Dram Type= 6, Freq= 0, CH_0, rank 1

 2881 23:02:43.036358  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2882 23:02:43.036486  ==

 2883 23:02:43.039561  [Gating] SW mode calibration

 2884 23:02:43.046087  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2885 23:02:43.049727  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2886 23:02:43.055944   0 15  0 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 0)

 2887 23:02:43.059599   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2888 23:02:43.062705   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2889 23:02:43.066108   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2890 23:02:43.072550   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2891 23:02:43.076418   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2892 23:02:43.079186   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2893 23:02:43.085976   0 15 28 | B1->B0 | 3232 3030 | 0 0 | (0 0) (0 1)

 2894 23:02:43.089650   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2895 23:02:43.093057   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2896 23:02:43.099757   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2897 23:02:43.102972   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2898 23:02:43.106366   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2899 23:02:43.112723   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2900 23:02:43.116179   1  0 24 | B1->B0 | 2525 2726 | 0 1 | (0 0) (0 0)

 2901 23:02:43.119401   1  0 28 | B1->B0 | 3737 3636 | 0 0 | (0 0) (0 0)

 2902 23:02:43.126229   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2903 23:02:43.129691   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2904 23:02:43.132742   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2905 23:02:43.139546   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2906 23:02:43.143067   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2907 23:02:43.146049   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2908 23:02:43.152734   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2909 23:02:43.156438   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2910 23:02:43.159791   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 2911 23:02:43.163290   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2912 23:02:43.170250   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2913 23:02:43.172852   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2914 23:02:43.176297   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2915 23:02:43.182741   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2916 23:02:43.186419   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2917 23:02:43.190028   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2918 23:02:43.196155   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2919 23:02:43.199806   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2920 23:02:43.203312   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2921 23:02:43.209714   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2922 23:02:43.213221   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2923 23:02:43.216648   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2924 23:02:43.222932   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2925 23:02:43.226281   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2926 23:02:43.230131   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2927 23:02:43.233059   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2928 23:02:43.236572  Total UI for P1: 0, mck2ui 16

 2929 23:02:43.240078  best dqsien dly found for B0: ( 1,  3, 30)

 2930 23:02:43.243037  Total UI for P1: 0, mck2ui 16

 2931 23:02:43.246500  best dqsien dly found for B1: ( 1,  3, 30)

 2932 23:02:43.250070  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2933 23:02:43.253531  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2934 23:02:43.256618  

 2935 23:02:43.259664  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2936 23:02:43.263082  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2937 23:02:43.266522  [Gating] SW calibration Done

 2938 23:02:43.266662  ==

 2939 23:02:43.269767  Dram Type= 6, Freq= 0, CH_0, rank 1

 2940 23:02:43.273487  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2941 23:02:43.273644  ==

 2942 23:02:43.273714  RX Vref Scan: 0

 2943 23:02:43.273774  

 2944 23:02:43.276305  RX Vref 0 -> 0, step: 1

 2945 23:02:43.276417  

 2946 23:02:43.279975  RX Delay -40 -> 252, step: 8

 2947 23:02:43.283571  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2948 23:02:43.286521  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2949 23:02:43.292952  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2950 23:02:43.296778  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2951 23:02:43.299871  iDelay=200, Bit 4, Center 127 (56 ~ 199) 144

 2952 23:02:43.303299  iDelay=200, Bit 5, Center 119 (48 ~ 191) 144

 2953 23:02:43.306465  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2954 23:02:43.313121  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2955 23:02:43.316096  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2956 23:02:43.319659  iDelay=200, Bit 9, Center 103 (32 ~ 175) 144

 2957 23:02:43.323257  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2958 23:02:43.326621  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2959 23:02:43.333299  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2960 23:02:43.336676  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2961 23:02:43.339816  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2962 23:02:43.343496  iDelay=200, Bit 15, Center 119 (56 ~ 183) 128

 2963 23:02:43.343597  ==

 2964 23:02:43.346531  Dram Type= 6, Freq= 0, CH_0, rank 1

 2965 23:02:43.350223  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2966 23:02:43.353027  ==

 2967 23:02:43.353129  DQS Delay:

 2968 23:02:43.353229  DQS0 = 0, DQS1 = 0

 2969 23:02:43.356479  DQM Delay:

 2970 23:02:43.356588  DQM0 = 122, DQM1 = 112

 2971 23:02:43.360081  DQ Delay:

 2972 23:02:43.363102  DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119

 2973 23:02:43.366565  DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127

 2974 23:02:43.370254  DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107

 2975 23:02:43.373545  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119

 2976 23:02:43.373710  

 2977 23:02:43.373804  

 2978 23:02:43.373891  ==

 2979 23:02:43.376306  Dram Type= 6, Freq= 0, CH_0, rank 1

 2980 23:02:43.380078  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2981 23:02:43.380158  ==

 2982 23:02:43.380221  

 2983 23:02:43.380278  

 2984 23:02:43.383382  	TX Vref Scan disable

 2985 23:02:43.386970   == TX Byte 0 ==

 2986 23:02:43.389870  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2987 23:02:43.393253  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2988 23:02:43.396555   == TX Byte 1 ==

 2989 23:02:43.400074  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 2990 23:02:43.402944  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 2991 23:02:43.403038  ==

 2992 23:02:43.406854  Dram Type= 6, Freq= 0, CH_0, rank 1

 2993 23:02:43.412953  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2994 23:02:43.413078  ==

 2995 23:02:43.423961  TX Vref=22, minBit 1, minWin=24, winSum=409

 2996 23:02:43.427083  TX Vref=24, minBit 13, minWin=25, winSum=419

 2997 23:02:43.430321  TX Vref=26, minBit 10, minWin=25, winSum=420

 2998 23:02:43.433714  TX Vref=28, minBit 0, minWin=26, winSum=426

 2999 23:02:43.437244  TX Vref=30, minBit 3, minWin=26, winSum=428

 3000 23:02:43.444105  TX Vref=32, minBit 13, minWin=25, winSum=424

 3001 23:02:43.446942  [TxChooseVref] Worse bit 3, Min win 26, Win sum 428, Final Vref 30

 3002 23:02:43.447017  

 3003 23:02:43.450616  Final TX Range 1 Vref 30

 3004 23:02:43.450702  

 3005 23:02:43.450769  ==

 3006 23:02:43.454156  Dram Type= 6, Freq= 0, CH_0, rank 1

 3007 23:02:43.457041  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3008 23:02:43.460684  ==

 3009 23:02:43.460767  

 3010 23:02:43.460832  

 3011 23:02:43.460892  	TX Vref Scan disable

 3012 23:02:43.464162   == TX Byte 0 ==

 3013 23:02:43.467225  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 3014 23:02:43.470662  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 3015 23:02:43.474139   == TX Byte 1 ==

 3016 23:02:43.477087  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3017 23:02:43.480688  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3018 23:02:43.484291  

 3019 23:02:43.484363  [DATLAT]

 3020 23:02:43.484435  Freq=1200, CH0 RK1

 3021 23:02:43.484497  

 3022 23:02:43.487512  DATLAT Default: 0xd

 3023 23:02:43.487581  0, 0xFFFF, sum = 0

 3024 23:02:43.490702  1, 0xFFFF, sum = 0

 3025 23:02:43.490769  2, 0xFFFF, sum = 0

 3026 23:02:43.494055  3, 0xFFFF, sum = 0

 3027 23:02:43.494129  4, 0xFFFF, sum = 0

 3028 23:02:43.497499  5, 0xFFFF, sum = 0

 3029 23:02:43.500595  6, 0xFFFF, sum = 0

 3030 23:02:43.500676  7, 0xFFFF, sum = 0

 3031 23:02:43.504049  8, 0xFFFF, sum = 0

 3032 23:02:43.504126  9, 0xFFFF, sum = 0

 3033 23:02:43.507452  10, 0xFFFF, sum = 0

 3034 23:02:43.507527  11, 0xFFFF, sum = 0

 3035 23:02:43.511183  12, 0x0, sum = 1

 3036 23:02:43.511251  13, 0x0, sum = 2

 3037 23:02:43.514086  14, 0x0, sum = 3

 3038 23:02:43.514166  15, 0x0, sum = 4

 3039 23:02:43.514233  best_step = 13

 3040 23:02:43.514291  

 3041 23:02:43.517334  ==

 3042 23:02:43.520950  Dram Type= 6, Freq= 0, CH_0, rank 1

 3043 23:02:43.524302  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3044 23:02:43.524375  ==

 3045 23:02:43.524446  RX Vref Scan: 0

 3046 23:02:43.524505  

 3047 23:02:43.527634  RX Vref 0 -> 0, step: 1

 3048 23:02:43.527708  

 3049 23:02:43.530477  RX Delay -13 -> 252, step: 4

 3050 23:02:43.533844  iDelay=195, Bit 0, Center 120 (51 ~ 190) 140

 3051 23:02:43.541002  iDelay=195, Bit 1, Center 122 (55 ~ 190) 136

 3052 23:02:43.543935  iDelay=195, Bit 2, Center 118 (51 ~ 186) 136

 3053 23:02:43.547294  iDelay=195, Bit 3, Center 118 (51 ~ 186) 136

 3054 23:02:43.550512  iDelay=195, Bit 4, Center 122 (55 ~ 190) 136

 3055 23:02:43.554028  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3056 23:02:43.557692  iDelay=195, Bit 6, Center 128 (63 ~ 194) 132

 3057 23:02:43.564011  iDelay=195, Bit 7, Center 128 (63 ~ 194) 132

 3058 23:02:43.567562  iDelay=195, Bit 8, Center 100 (35 ~ 166) 132

 3059 23:02:43.570696  iDelay=195, Bit 9, Center 98 (31 ~ 166) 136

 3060 23:02:43.573739  iDelay=195, Bit 10, Center 110 (47 ~ 174) 128

 3061 23:02:43.577341  iDelay=195, Bit 11, Center 102 (39 ~ 166) 128

 3062 23:02:43.583795  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3063 23:02:43.587244  iDelay=195, Bit 13, Center 116 (55 ~ 178) 124

 3064 23:02:43.590888  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3065 23:02:43.594379  iDelay=195, Bit 15, Center 120 (55 ~ 186) 132

 3066 23:02:43.594522  ==

 3067 23:02:43.597305  Dram Type= 6, Freq= 0, CH_0, rank 1

 3068 23:02:43.603903  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3069 23:02:43.603985  ==

 3070 23:02:43.604049  DQS Delay:

 3071 23:02:43.607423  DQS0 = 0, DQS1 = 0

 3072 23:02:43.607500  DQM Delay:

 3073 23:02:43.607560  DQM0 = 121, DQM1 = 110

 3074 23:02:43.610540  DQ Delay:

 3075 23:02:43.613961  DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118

 3076 23:02:43.617480  DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =128

 3077 23:02:43.620827  DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102

 3078 23:02:43.624096  DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120

 3079 23:02:43.624182  

 3080 23:02:43.624254  

 3081 23:02:43.631089  [DQSOSCAuto] RK1, (LSB)MR18= 0xeef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps

 3082 23:02:43.634016  CH0 RK1: MR19=403, MR18=EEF

 3083 23:02:43.640830  CH0_RK1: MR19=0x403, MR18=0xEEF, DQSOSC=404, MR23=63, INC=40, DEC=26

 3084 23:02:43.644285  [RxdqsGatingPostProcess] freq 1200

 3085 23:02:43.650801  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3086 23:02:43.654202  best DQS0 dly(2T, 0.5T) = (0, 11)

 3087 23:02:43.654280  best DQS1 dly(2T, 0.5T) = (0, 12)

 3088 23:02:43.657599  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3089 23:02:43.660892  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3090 23:02:43.664304  best DQS0 dly(2T, 0.5T) = (0, 11)

 3091 23:02:43.667928  best DQS1 dly(2T, 0.5T) = (0, 11)

 3092 23:02:43.670871  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3093 23:02:43.674426  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3094 23:02:43.677556  Pre-setting of DQS Precalculation

 3095 23:02:43.681136  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3096 23:02:43.684421  ==

 3097 23:02:43.688053  Dram Type= 6, Freq= 0, CH_1, rank 0

 3098 23:02:43.691587  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3099 23:02:43.691699  ==

 3100 23:02:43.694400  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3101 23:02:43.700734  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3102 23:02:43.710472  [CA 0] Center 37 (7~68) winsize 62

 3103 23:02:43.713890  [CA 1] Center 37 (7~68) winsize 62

 3104 23:02:43.717198  [CA 2] Center 35 (5~65) winsize 61

 3105 23:02:43.720226  [CA 3] Center 34 (4~64) winsize 61

 3106 23:02:43.723820  [CA 4] Center 34 (4~64) winsize 61

 3107 23:02:43.727157  [CA 5] Center 33 (3~63) winsize 61

 3108 23:02:43.727266  

 3109 23:02:43.730449  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3110 23:02:43.730537  

 3111 23:02:43.733483  [CATrainingPosCal] consider 1 rank data

 3112 23:02:43.737062  u2DelayCellTimex100 = 270/100 ps

 3113 23:02:43.740453  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3114 23:02:43.743430  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3115 23:02:43.747043  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3116 23:02:43.753412  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3117 23:02:43.756966  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3118 23:02:43.760148  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3119 23:02:43.760232  

 3120 23:02:43.763759  CA PerBit enable=1, Macro0, CA PI delay=33

 3121 23:02:43.763937  

 3122 23:02:43.767032  [CBTSetCACLKResult] CA Dly = 33

 3123 23:02:43.767130  CS Dly: 8 (0~39)

 3124 23:02:43.767195  ==

 3125 23:02:43.770394  Dram Type= 6, Freq= 0, CH_1, rank 1

 3126 23:02:43.776805  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3127 23:02:43.776890  ==

 3128 23:02:43.780361  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3129 23:02:43.786779  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3130 23:02:43.796160  [CA 0] Center 37 (7~68) winsize 62

 3131 23:02:43.798990  [CA 1] Center 38 (7~69) winsize 63

 3132 23:02:43.802597  [CA 2] Center 35 (5~65) winsize 61

 3133 23:02:43.805977  [CA 3] Center 34 (4~65) winsize 62

 3134 23:02:43.809350  [CA 4] Center 35 (5~65) winsize 61

 3135 23:02:43.812965  [CA 5] Center 34 (4~64) winsize 61

 3136 23:02:43.813049  

 3137 23:02:43.815877  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3138 23:02:43.815959  

 3139 23:02:43.819319  [CATrainingPosCal] consider 2 rank data

 3140 23:02:43.822442  u2DelayCellTimex100 = 270/100 ps

 3141 23:02:43.826112  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3142 23:02:43.829267  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3143 23:02:43.835964  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3144 23:02:43.839433  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3145 23:02:43.842994  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3146 23:02:43.845937  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3147 23:02:43.846023  

 3148 23:02:43.849266  CA PerBit enable=1, Macro0, CA PI delay=33

 3149 23:02:43.849382  

 3150 23:02:43.852935  [CBTSetCACLKResult] CA Dly = 33

 3151 23:02:43.853023  CS Dly: 8 (0~40)

 3152 23:02:43.853088  

 3153 23:02:43.855862  ----->DramcWriteLeveling(PI) begin...

 3154 23:02:43.855946  ==

 3155 23:02:43.859509  Dram Type= 6, Freq= 0, CH_1, rank 0

 3156 23:02:43.865993  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3157 23:02:43.866103  ==

 3158 23:02:43.869297  Write leveling (Byte 0): 27 => 27

 3159 23:02:43.872684  Write leveling (Byte 1): 28 => 28

 3160 23:02:43.872778  DramcWriteLeveling(PI) end<-----

 3161 23:02:43.875835  

 3162 23:02:43.875916  ==

 3163 23:02:43.879203  Dram Type= 6, Freq= 0, CH_1, rank 0

 3164 23:02:43.882669  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3165 23:02:43.882790  ==

 3166 23:02:43.886150  [Gating] SW mode calibration

 3167 23:02:43.892321  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3168 23:02:43.895867  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3169 23:02:43.902691   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3170 23:02:43.905937   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3171 23:02:43.909649   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3172 23:02:43.916370   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3173 23:02:43.919286   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3174 23:02:43.922729   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3175 23:02:43.929278   0 15 24 | B1->B0 | 3434 2c2c | 1 1 | (0 1) (1 0)

 3176 23:02:43.932599   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 3177 23:02:43.935983   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3178 23:02:43.942285   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3179 23:02:43.946205   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3180 23:02:43.949054   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3181 23:02:43.956093   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3182 23:02:43.959566   1  0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3183 23:02:43.962368   1  0 24 | B1->B0 | 2b2b 3b3b | 1 0 | (0 0) (0 0)

 3184 23:02:43.969326   1  0 28 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 3185 23:02:43.972280   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3186 23:02:43.975779   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3187 23:02:43.979196   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3188 23:02:43.985610   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3189 23:02:43.989058   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3190 23:02:43.992661   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3191 23:02:43.999070   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3192 23:02:44.002285   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3193 23:02:44.006133   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3194 23:02:44.012320   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3195 23:02:44.015907   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3196 23:02:44.019051   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3197 23:02:44.025657   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3198 23:02:44.029135   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3199 23:02:44.032212   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3200 23:02:44.039080   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3201 23:02:44.042645   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3202 23:02:44.045469   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3203 23:02:44.052598   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3204 23:02:44.055957   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3205 23:02:44.059377   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3206 23:02:44.065788   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3207 23:02:44.069278   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3208 23:02:44.072296   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3209 23:02:44.079310   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3210 23:02:44.079460  Total UI for P1: 0, mck2ui 16

 3211 23:02:44.082636  best dqsien dly found for B0: ( 1,  3, 26)

 3212 23:02:44.086093  Total UI for P1: 0, mck2ui 16

 3213 23:02:44.089543  best dqsien dly found for B1: ( 1,  3, 26)

 3214 23:02:44.092277  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3215 23:02:44.096009  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3216 23:02:44.099350  

 3217 23:02:44.102319  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3218 23:02:44.105767  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3219 23:02:44.109161  [Gating] SW calibration Done

 3220 23:02:44.109286  ==

 3221 23:02:44.112486  Dram Type= 6, Freq= 0, CH_1, rank 0

 3222 23:02:44.115983  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3223 23:02:44.116137  ==

 3224 23:02:44.116247  RX Vref Scan: 0

 3225 23:02:44.116346  

 3226 23:02:44.119300  RX Vref 0 -> 0, step: 1

 3227 23:02:44.119420  

 3228 23:02:44.122340  RX Delay -40 -> 252, step: 8

 3229 23:02:44.125769  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3230 23:02:44.129471  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3231 23:02:44.135912  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3232 23:02:44.139308  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3233 23:02:44.142818  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3234 23:02:44.146395  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3235 23:02:44.149069  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3236 23:02:44.152465  iDelay=200, Bit 7, Center 119 (48 ~ 191) 144

 3237 23:02:44.159005  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3238 23:02:44.162587  iDelay=200, Bit 9, Center 103 (40 ~ 167) 128

 3239 23:02:44.165945  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3240 23:02:44.169328  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3241 23:02:44.175707  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3242 23:02:44.179310  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3243 23:02:44.182624  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3244 23:02:44.185784  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3245 23:02:44.185948  ==

 3246 23:02:44.189114  Dram Type= 6, Freq= 0, CH_1, rank 0

 3247 23:02:44.192631  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3248 23:02:44.195926  ==

 3249 23:02:44.196072  DQS Delay:

 3250 23:02:44.196186  DQS0 = 0, DQS1 = 0

 3251 23:02:44.199600  DQM Delay:

 3252 23:02:44.199739  DQM0 = 119, DQM1 = 116

 3253 23:02:44.203130  DQ Delay:

 3254 23:02:44.206106  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3255 23:02:44.209647  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119

 3256 23:02:44.213027  DQ8 =103, DQ9 =103, DQ10 =115, DQ11 =111

 3257 23:02:44.216279  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3258 23:02:44.216398  

 3259 23:02:44.216499  

 3260 23:02:44.216597  ==

 3261 23:02:44.219182  Dram Type= 6, Freq= 0, CH_1, rank 0

 3262 23:02:44.222669  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3263 23:02:44.222802  ==

 3264 23:02:44.222904  

 3265 23:02:44.222991  

 3266 23:02:44.226119  	TX Vref Scan disable

 3267 23:02:44.229584   == TX Byte 0 ==

 3268 23:02:44.232954  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3269 23:02:44.236160  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3270 23:02:44.239661   == TX Byte 1 ==

 3271 23:02:44.242919  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3272 23:02:44.246255  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3273 23:02:44.246348  ==

 3274 23:02:44.249468  Dram Type= 6, Freq= 0, CH_1, rank 0

 3275 23:02:44.252691  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3276 23:02:44.256251  ==

 3277 23:02:44.266200  TX Vref=22, minBit 9, minWin=25, winSum=415

 3278 23:02:44.269697  TX Vref=24, minBit 9, minWin=25, winSum=418

 3279 23:02:44.272986  TX Vref=26, minBit 10, minWin=25, winSum=422

 3280 23:02:44.275981  TX Vref=28, minBit 1, minWin=26, winSum=427

 3281 23:02:44.279577  TX Vref=30, minBit 1, minWin=26, winSum=431

 3282 23:02:44.282540  TX Vref=32, minBit 9, minWin=25, winSum=429

 3283 23:02:44.289410  [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30

 3284 23:02:44.289555  

 3285 23:02:44.292975  Final TX Range 1 Vref 30

 3286 23:02:44.293085  

 3287 23:02:44.293184  ==

 3288 23:02:44.296328  Dram Type= 6, Freq= 0, CH_1, rank 0

 3289 23:02:44.299217  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3290 23:02:44.299330  ==

 3291 23:02:44.299427  

 3292 23:02:44.302664  

 3293 23:02:44.302772  	TX Vref Scan disable

 3294 23:02:44.306297   == TX Byte 0 ==

 3295 23:02:44.309095  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3296 23:02:44.312740  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3297 23:02:44.316440   == TX Byte 1 ==

 3298 23:02:44.319091  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3299 23:02:44.322537  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3300 23:02:44.322653  

 3301 23:02:44.326218  [DATLAT]

 3302 23:02:44.326327  Freq=1200, CH1 RK0

 3303 23:02:44.326424  

 3304 23:02:44.329156  DATLAT Default: 0xd

 3305 23:02:44.329263  0, 0xFFFF, sum = 0

 3306 23:02:44.332719  1, 0xFFFF, sum = 0

 3307 23:02:44.332832  2, 0xFFFF, sum = 0

 3308 23:02:44.336364  3, 0xFFFF, sum = 0

 3309 23:02:44.336473  4, 0xFFFF, sum = 0

 3310 23:02:44.339255  5, 0xFFFF, sum = 0

 3311 23:02:44.339356  6, 0xFFFF, sum = 0

 3312 23:02:44.342620  7, 0xFFFF, sum = 0

 3313 23:02:44.342738  8, 0xFFFF, sum = 0

 3314 23:02:44.346342  9, 0xFFFF, sum = 0

 3315 23:02:44.349342  10, 0xFFFF, sum = 0

 3316 23:02:44.349477  11, 0xFFFF, sum = 0

 3317 23:02:44.352987  12, 0x0, sum = 1

 3318 23:02:44.353112  13, 0x0, sum = 2

 3319 23:02:44.353208  14, 0x0, sum = 3

 3320 23:02:44.355965  15, 0x0, sum = 4

 3321 23:02:44.356080  best_step = 13

 3322 23:02:44.356180  

 3323 23:02:44.359488  ==

 3324 23:02:44.359609  Dram Type= 6, Freq= 0, CH_1, rank 0

 3325 23:02:44.366125  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3326 23:02:44.366264  ==

 3327 23:02:44.366367  RX Vref Scan: 1

 3328 23:02:44.366459  

 3329 23:02:44.369460  Set Vref Range= 32 -> 127

 3330 23:02:44.369572  

 3331 23:02:44.372800  RX Vref 32 -> 127, step: 1

 3332 23:02:44.372893  

 3333 23:02:44.376006  RX Delay -5 -> 252, step: 4

 3334 23:02:44.376101  

 3335 23:02:44.379599  Set Vref, RX VrefLevel [Byte0]: 32

 3336 23:02:44.382600                           [Byte1]: 32

 3337 23:02:44.382694  

 3338 23:02:44.386005  Set Vref, RX VrefLevel [Byte0]: 33

 3339 23:02:44.389633                           [Byte1]: 33

 3340 23:02:44.389759  

 3341 23:02:44.392652  Set Vref, RX VrefLevel [Byte0]: 34

 3342 23:02:44.396149                           [Byte1]: 34

 3343 23:02:44.400273  

 3344 23:02:44.400366  Set Vref, RX VrefLevel [Byte0]: 35

 3345 23:02:44.403235                           [Byte1]: 35

 3346 23:02:44.407633  

 3347 23:02:44.407725  Set Vref, RX VrefLevel [Byte0]: 36

 3348 23:02:44.411128                           [Byte1]: 36

 3349 23:02:44.415687  

 3350 23:02:44.415804  Set Vref, RX VrefLevel [Byte0]: 37

 3351 23:02:44.419082                           [Byte1]: 37

 3352 23:02:44.423728  

 3353 23:02:44.423817  Set Vref, RX VrefLevel [Byte0]: 38

 3354 23:02:44.426672                           [Byte1]: 38

 3355 23:02:44.431345  

 3356 23:02:44.431434  Set Vref, RX VrefLevel [Byte0]: 39

 3357 23:02:44.434944                           [Byte1]: 39

 3358 23:02:44.439468  

 3359 23:02:44.439561  Set Vref, RX VrefLevel [Byte0]: 40

 3360 23:02:44.442245                           [Byte1]: 40

 3361 23:02:44.447072  

 3362 23:02:44.447222  Set Vref, RX VrefLevel [Byte0]: 41

 3363 23:02:44.450434                           [Byte1]: 41

 3364 23:02:44.455008  

 3365 23:02:44.455145  Set Vref, RX VrefLevel [Byte0]: 42

 3366 23:02:44.458098                           [Byte1]: 42

 3367 23:02:44.462745  

 3368 23:02:44.462842  Set Vref, RX VrefLevel [Byte0]: 43

 3369 23:02:44.466380                           [Byte1]: 43

 3370 23:02:44.470726  

 3371 23:02:44.470812  Set Vref, RX VrefLevel [Byte0]: 44

 3372 23:02:44.473819                           [Byte1]: 44

 3373 23:02:44.478323  

 3374 23:02:44.481566  Set Vref, RX VrefLevel [Byte0]: 45

 3375 23:02:44.484782                           [Byte1]: 45

 3376 23:02:44.484872  

 3377 23:02:44.488317  Set Vref, RX VrefLevel [Byte0]: 46

 3378 23:02:44.491596                           [Byte1]: 46

 3379 23:02:44.491709  

 3380 23:02:44.495442  Set Vref, RX VrefLevel [Byte0]: 47

 3381 23:02:44.498201                           [Byte1]: 47

 3382 23:02:44.501983  

 3383 23:02:44.502065  Set Vref, RX VrefLevel [Byte0]: 48

 3384 23:02:44.504958                           [Byte1]: 48

 3385 23:02:44.509759  

 3386 23:02:44.509843  Set Vref, RX VrefLevel [Byte0]: 49

 3387 23:02:44.513179                           [Byte1]: 49

 3388 23:02:44.517601  

 3389 23:02:44.517714  Set Vref, RX VrefLevel [Byte0]: 50

 3390 23:02:44.521055                           [Byte1]: 50

 3391 23:02:44.525843  

 3392 23:02:44.525928  Set Vref, RX VrefLevel [Byte0]: 51

 3393 23:02:44.528443                           [Byte1]: 51

 3394 23:02:44.533274  

 3395 23:02:44.533386  Set Vref, RX VrefLevel [Byte0]: 52

 3396 23:02:44.536782                           [Byte1]: 52

 3397 23:02:44.541257  

 3398 23:02:44.541342  Set Vref, RX VrefLevel [Byte0]: 53

 3399 23:02:44.544759                           [Byte1]: 53

 3400 23:02:44.548947  

 3401 23:02:44.549055  Set Vref, RX VrefLevel [Byte0]: 54

 3402 23:02:44.552584                           [Byte1]: 54

 3403 23:02:44.556712  

 3404 23:02:44.556831  Set Vref, RX VrefLevel [Byte0]: 55

 3405 23:02:44.560304                           [Byte1]: 55

 3406 23:02:44.564620  

 3407 23:02:44.564717  Set Vref, RX VrefLevel [Byte0]: 56

 3408 23:02:44.567851                           [Byte1]: 56

 3409 23:02:44.572415  

 3410 23:02:44.572512  Set Vref, RX VrefLevel [Byte0]: 57

 3411 23:02:44.575801                           [Byte1]: 57

 3412 23:02:44.580639  

 3413 23:02:44.580771  Set Vref, RX VrefLevel [Byte0]: 58

 3414 23:02:44.583467                           [Byte1]: 58

 3415 23:02:44.588244  

 3416 23:02:44.588372  Set Vref, RX VrefLevel [Byte0]: 59

 3417 23:02:44.591535                           [Byte1]: 59

 3418 23:02:44.595900  

 3419 23:02:44.596017  Set Vref, RX VrefLevel [Byte0]: 60

 3420 23:02:44.599591                           [Byte1]: 60

 3421 23:02:44.604134  

 3422 23:02:44.604261  Set Vref, RX VrefLevel [Byte0]: 61

 3423 23:02:44.607055                           [Byte1]: 61

 3424 23:02:44.612173  

 3425 23:02:44.612295  Set Vref, RX VrefLevel [Byte0]: 62

 3426 23:02:44.615089                           [Byte1]: 62

 3427 23:02:44.619390  

 3428 23:02:44.619472  Set Vref, RX VrefLevel [Byte0]: 63

 3429 23:02:44.622756                           [Byte1]: 63

 3430 23:02:44.627450  

 3431 23:02:44.627534  Set Vref, RX VrefLevel [Byte0]: 64

 3432 23:02:44.630923                           [Byte1]: 64

 3433 23:02:44.635213  

 3434 23:02:44.635303  Set Vref, RX VrefLevel [Byte0]: 65

 3435 23:02:44.638629                           [Byte1]: 65

 3436 23:02:44.643377  

 3437 23:02:44.643469  Set Vref, RX VrefLevel [Byte0]: 66

 3438 23:02:44.646184                           [Byte1]: 66

 3439 23:02:44.650969  

 3440 23:02:44.651048  Set Vref, RX VrefLevel [Byte0]: 67

 3441 23:02:44.654441                           [Byte1]: 67

 3442 23:02:44.659172  

 3443 23:02:44.659263  Set Vref, RX VrefLevel [Byte0]: 68

 3444 23:02:44.662082                           [Byte1]: 68

 3445 23:02:44.666793  

 3446 23:02:44.666904  Set Vref, RX VrefLevel [Byte0]: 69

 3447 23:02:44.670054                           [Byte1]: 69

 3448 23:02:44.674382  

 3449 23:02:44.674464  Final RX Vref Byte 0 = 52 to rank0

 3450 23:02:44.678127  Final RX Vref Byte 1 = 46 to rank0

 3451 23:02:44.681444  Final RX Vref Byte 0 = 52 to rank1

 3452 23:02:44.684640  Final RX Vref Byte 1 = 46 to rank1==

 3453 23:02:44.687648  Dram Type= 6, Freq= 0, CH_1, rank 0

 3454 23:02:44.694399  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3455 23:02:44.694495  ==

 3456 23:02:44.694601  DQS Delay:

 3457 23:02:44.694700  DQS0 = 0, DQS1 = 0

 3458 23:02:44.697775  DQM Delay:

 3459 23:02:44.697853  DQM0 = 120, DQM1 = 116

 3460 23:02:44.701099  DQ Delay:

 3461 23:02:44.704733  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118

 3462 23:02:44.707666  DQ4 =118, DQ5 =128, DQ6 =130, DQ7 =120

 3463 23:02:44.711298  DQ8 =102, DQ9 =106, DQ10 =118, DQ11 =108

 3464 23:02:44.714513  DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126

 3465 23:02:44.714609  

 3466 23:02:44.714703  

 3467 23:02:44.721347  [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps

 3468 23:02:44.724790  CH1 RK0: MR19=404, MR18=113

 3469 23:02:44.731275  CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27

 3470 23:02:44.731422  

 3471 23:02:44.734645  ----->DramcWriteLeveling(PI) begin...

 3472 23:02:44.734761  ==

 3473 23:02:44.737907  Dram Type= 6, Freq= 0, CH_1, rank 1

 3474 23:02:44.741231  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3475 23:02:44.741359  ==

 3476 23:02:44.744430  Write leveling (Byte 0): 27 => 27

 3477 23:02:44.747948  Write leveling (Byte 1): 29 => 29

 3478 23:02:44.751177  DramcWriteLeveling(PI) end<-----

 3479 23:02:44.751319  

 3480 23:02:44.751418  ==

 3481 23:02:44.754463  Dram Type= 6, Freq= 0, CH_1, rank 1

 3482 23:02:44.758199  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3483 23:02:44.761572  ==

 3484 23:02:44.761702  [Gating] SW mode calibration

 3485 23:02:44.771300  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3486 23:02:44.774865  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3487 23:02:44.778214   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3488 23:02:44.784780   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3489 23:02:44.787999   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3490 23:02:44.791590   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3491 23:02:44.797699   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3492 23:02:44.801496   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 3493 23:02:44.805053   0 15 24 | B1->B0 | 2828 3131 | 1 1 | (1 0) (1 1)

 3494 23:02:44.811581   0 15 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 3495 23:02:44.814946   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3496 23:02:44.817753   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3497 23:02:44.824615   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3498 23:02:44.828119   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3499 23:02:44.831154   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3500 23:02:44.838103   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3501 23:02:44.841498   1  0 24 | B1->B0 | 4444 3030 | 0 0 | (0 0) (0 0)

 3502 23:02:44.844517   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3503 23:02:44.847872   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3504 23:02:44.854925   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3505 23:02:44.857864   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3506 23:02:44.861398   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3507 23:02:44.868112   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3508 23:02:44.871467   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3509 23:02:44.874927   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3510 23:02:44.881478   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3511 23:02:44.884655   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3512 23:02:44.887976   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3513 23:02:44.894554   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3514 23:02:44.898024   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3515 23:02:44.901638   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3516 23:02:44.907756   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3517 23:02:44.910889   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3518 23:02:44.914426   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3519 23:02:44.921207   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3520 23:02:44.924710   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3521 23:02:44.928074   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3522 23:02:44.934530   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3523 23:02:44.937463   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3524 23:02:44.941139   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3525 23:02:44.948039   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3526 23:02:44.950965   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3527 23:02:44.954325  Total UI for P1: 0, mck2ui 16

 3528 23:02:44.957656  best dqsien dly found for B1: ( 1,  3, 22)

 3529 23:02:44.961329   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3530 23:02:44.964368  Total UI for P1: 0, mck2ui 16

 3531 23:02:44.967564  best dqsien dly found for B0: ( 1,  3, 26)

 3532 23:02:44.971347  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3533 23:02:44.974014  best DQS1 dly(MCK, UI, PI) = (1, 3, 22)

 3534 23:02:44.974126  

 3535 23:02:44.977697  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3536 23:02:44.984293  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3537 23:02:44.984422  [Gating] SW calibration Done

 3538 23:02:44.984518  ==

 3539 23:02:44.987873  Dram Type= 6, Freq= 0, CH_1, rank 1

 3540 23:02:44.994472  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3541 23:02:44.994597  ==

 3542 23:02:44.994696  RX Vref Scan: 0

 3543 23:02:44.994785  

 3544 23:02:44.997511  RX Vref 0 -> 0, step: 1

 3545 23:02:44.997636  

 3546 23:02:45.000954  RX Delay -40 -> 252, step: 8

 3547 23:02:45.004349  iDelay=200, Bit 0, Center 127 (64 ~ 191) 128

 3548 23:02:45.007974  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3549 23:02:45.010931  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3550 23:02:45.018005  iDelay=200, Bit 3, Center 119 (56 ~ 183) 128

 3551 23:02:45.020738  iDelay=200, Bit 4, Center 119 (56 ~ 183) 128

 3552 23:02:45.023972  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3553 23:02:45.027682  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3554 23:02:45.031028  iDelay=200, Bit 7, Center 119 (48 ~ 191) 144

 3555 23:02:45.034133  iDelay=200, Bit 8, Center 107 (40 ~ 175) 136

 3556 23:02:45.040662  iDelay=200, Bit 9, Center 103 (40 ~ 167) 128

 3557 23:02:45.044531  iDelay=200, Bit 10, Center 119 (56 ~ 183) 128

 3558 23:02:45.047443  iDelay=200, Bit 11, Center 115 (48 ~ 183) 136

 3559 23:02:45.051185  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3560 23:02:45.057209  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3561 23:02:45.060774  iDelay=200, Bit 14, Center 119 (56 ~ 183) 128

 3562 23:02:45.064134  iDelay=200, Bit 15, Center 127 (64 ~ 191) 128

 3563 23:02:45.064256  ==

 3564 23:02:45.067110  Dram Type= 6, Freq= 0, CH_1, rank 1

 3565 23:02:45.070528  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3566 23:02:45.070638  ==

 3567 23:02:45.074022  DQS Delay:

 3568 23:02:45.074110  DQS0 = 0, DQS1 = 0

 3569 23:02:45.077393  DQM Delay:

 3570 23:02:45.077509  DQM0 = 121, DQM1 = 118

 3571 23:02:45.080765  DQ Delay:

 3572 23:02:45.083956  DQ0 =127, DQ1 =115, DQ2 =107, DQ3 =119

 3573 23:02:45.087175  DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119

 3574 23:02:45.090657  DQ8 =107, DQ9 =103, DQ10 =119, DQ11 =115

 3575 23:02:45.093565  DQ12 =127, DQ13 =127, DQ14 =119, DQ15 =127

 3576 23:02:45.093669  

 3577 23:02:45.093736  

 3578 23:02:45.093797  ==

 3579 23:02:45.097147  Dram Type= 6, Freq= 0, CH_1, rank 1

 3580 23:02:45.100526  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3581 23:02:45.100643  ==

 3582 23:02:45.100749  

 3583 23:02:45.100849  

 3584 23:02:45.104087  	TX Vref Scan disable

 3585 23:02:45.107217   == TX Byte 0 ==

 3586 23:02:45.110439  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3587 23:02:45.113668  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3588 23:02:45.117014   == TX Byte 1 ==

 3589 23:02:45.120517  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3590 23:02:45.124103  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3591 23:02:45.124215  ==

 3592 23:02:45.127154  Dram Type= 6, Freq= 0, CH_1, rank 1

 3593 23:02:45.130281  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3594 23:02:45.133739  ==

 3595 23:02:45.143868  TX Vref=22, minBit 1, minWin=25, winSum=419

 3596 23:02:45.147104  TX Vref=24, minBit 1, minWin=26, winSum=425

 3597 23:02:45.150349  TX Vref=26, minBit 4, minWin=26, winSum=428

 3598 23:02:45.153982  TX Vref=28, minBit 9, minWin=26, winSum=432

 3599 23:02:45.156764  TX Vref=30, minBit 9, minWin=26, winSum=436

 3600 23:02:45.163597  TX Vref=32, minBit 9, minWin=26, winSum=436

 3601 23:02:45.167152  [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 30

 3602 23:02:45.167249  

 3603 23:02:45.170046  Final TX Range 1 Vref 30

 3604 23:02:45.170133  

 3605 23:02:45.170198  ==

 3606 23:02:45.173584  Dram Type= 6, Freq= 0, CH_1, rank 1

 3607 23:02:45.177155  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3608 23:02:45.179811  ==

 3609 23:02:45.179933  

 3610 23:02:45.180049  

 3611 23:02:45.180164  	TX Vref Scan disable

 3612 23:02:45.183430   == TX Byte 0 ==

 3613 23:02:45.186981  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3614 23:02:45.193521  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3615 23:02:45.193662   == TX Byte 1 ==

 3616 23:02:45.196402  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3617 23:02:45.203503  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3618 23:02:45.203635  

 3619 23:02:45.203752  [DATLAT]

 3620 23:02:45.203860  Freq=1200, CH1 RK1

 3621 23:02:45.203974  

 3622 23:02:45.206441  DATLAT Default: 0xd

 3623 23:02:45.209898  0, 0xFFFF, sum = 0

 3624 23:02:45.210022  1, 0xFFFF, sum = 0

 3625 23:02:45.212892  2, 0xFFFF, sum = 0

 3626 23:02:45.213004  3, 0xFFFF, sum = 0

 3627 23:02:45.216197  4, 0xFFFF, sum = 0

 3628 23:02:45.216317  5, 0xFFFF, sum = 0

 3629 23:02:45.219885  6, 0xFFFF, sum = 0

 3630 23:02:45.219973  7, 0xFFFF, sum = 0

 3631 23:02:45.223076  8, 0xFFFF, sum = 0

 3632 23:02:45.223163  9, 0xFFFF, sum = 0

 3633 23:02:45.226585  10, 0xFFFF, sum = 0

 3634 23:02:45.226675  11, 0xFFFF, sum = 0

 3635 23:02:45.229462  12, 0x0, sum = 1

 3636 23:02:45.229548  13, 0x0, sum = 2

 3637 23:02:45.232851  14, 0x0, sum = 3

 3638 23:02:45.232929  15, 0x0, sum = 4

 3639 23:02:45.236200  best_step = 13

 3640 23:02:45.236278  

 3641 23:02:45.236340  ==

 3642 23:02:45.239520  Dram Type= 6, Freq= 0, CH_1, rank 1

 3643 23:02:45.242875  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3644 23:02:45.242957  ==

 3645 23:02:45.243024  RX Vref Scan: 0

 3646 23:02:45.246305  

 3647 23:02:45.246382  RX Vref 0 -> 0, step: 1

 3648 23:02:45.246445  

 3649 23:02:45.249419  RX Delay -5 -> 252, step: 4

 3650 23:02:45.252817  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3651 23:02:45.259326  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3652 23:02:45.262750  iDelay=195, Bit 2, Center 110 (51 ~ 170) 120

 3653 23:02:45.266234  iDelay=195, Bit 3, Center 116 (55 ~ 178) 124

 3654 23:02:45.269729  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3655 23:02:45.273203  iDelay=195, Bit 5, Center 132 (71 ~ 194) 124

 3656 23:02:45.279592  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3657 23:02:45.283005  iDelay=195, Bit 7, Center 118 (55 ~ 182) 128

 3658 23:02:45.286297  iDelay=195, Bit 8, Center 104 (43 ~ 166) 124

 3659 23:02:45.289372  iDelay=195, Bit 9, Center 106 (47 ~ 166) 120

 3660 23:02:45.292876  iDelay=195, Bit 10, Center 116 (55 ~ 178) 124

 3661 23:02:45.299213  iDelay=195, Bit 11, Center 110 (51 ~ 170) 120

 3662 23:02:45.302869  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3663 23:02:45.305943  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3664 23:02:45.309758  iDelay=195, Bit 14, Center 120 (63 ~ 178) 116

 3665 23:02:45.316048  iDelay=195, Bit 15, Center 124 (63 ~ 186) 124

 3666 23:02:45.316188  ==

 3667 23:02:45.319546  Dram Type= 6, Freq= 0, CH_1, rank 1

 3668 23:02:45.322855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3669 23:02:45.322993  ==

 3670 23:02:45.323097  DQS Delay:

 3671 23:02:45.326169  DQS0 = 0, DQS1 = 0

 3672 23:02:45.326304  DQM Delay:

 3673 23:02:45.329257  DQM0 = 120, DQM1 = 116

 3674 23:02:45.329370  DQ Delay:

 3675 23:02:45.332580  DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116

 3676 23:02:45.336044  DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =118

 3677 23:02:45.339018  DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110

 3678 23:02:45.342339  DQ12 =126, DQ13 =124, DQ14 =120, DQ15 =124

 3679 23:02:45.342452  

 3680 23:02:45.342547  

 3681 23:02:45.352753  [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps

 3682 23:02:45.355933  CH1 RK1: MR19=403, MR18=11EE

 3683 23:02:45.359387  CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26

 3684 23:02:45.362474  [RxdqsGatingPostProcess] freq 1200

 3685 23:02:45.369099  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3686 23:02:45.372667  best DQS0 dly(2T, 0.5T) = (0, 11)

 3687 23:02:45.376017  best DQS1 dly(2T, 0.5T) = (0, 11)

 3688 23:02:45.378989  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3689 23:02:45.382558  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3690 23:02:45.386096  best DQS0 dly(2T, 0.5T) = (0, 11)

 3691 23:02:45.388979  best DQS1 dly(2T, 0.5T) = (0, 11)

 3692 23:02:45.392429  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3693 23:02:45.395982  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3694 23:02:45.399494  Pre-setting of DQS Precalculation

 3695 23:02:45.402569  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3696 23:02:45.408958  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3697 23:02:45.415941  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3698 23:02:45.416069  

 3699 23:02:45.418955  

 3700 23:02:45.419055  [Calibration Summary] 2400 Mbps

 3701 23:02:45.422479  CH 0, Rank 0

 3702 23:02:45.422590  SW Impedance     : PASS

 3703 23:02:45.425820  DUTY Scan        : NO K

 3704 23:02:45.429273  ZQ Calibration   : PASS

 3705 23:02:45.429385  Jitter Meter     : NO K

 3706 23:02:45.432259  CBT Training     : PASS

 3707 23:02:45.435523  Write leveling   : PASS

 3708 23:02:45.435635  RX DQS gating    : PASS

 3709 23:02:45.439317  RX DQ/DQS(RDDQC) : PASS

 3710 23:02:45.442412  TX DQ/DQS        : PASS

 3711 23:02:45.442494  RX DATLAT        : PASS

 3712 23:02:45.446055  RX DQ/DQS(Engine): PASS

 3713 23:02:45.449282  TX OE            : NO K

 3714 23:02:45.449386  All Pass.

 3715 23:02:45.449488  

 3716 23:02:45.449587  CH 0, Rank 1

 3717 23:02:45.452110  SW Impedance     : PASS

 3718 23:02:45.455406  DUTY Scan        : NO K

 3719 23:02:45.455511  ZQ Calibration   : PASS

 3720 23:02:45.458817  Jitter Meter     : NO K

 3721 23:02:45.458906  CBT Training     : PASS

 3722 23:02:45.462260  Write leveling   : PASS

 3723 23:02:45.465562  RX DQS gating    : PASS

 3724 23:02:45.465689  RX DQ/DQS(RDDQC) : PASS

 3725 23:02:45.468837  TX DQ/DQS        : PASS

 3726 23:02:45.472434  RX DATLAT        : PASS

 3727 23:02:45.472517  RX DQ/DQS(Engine): PASS

 3728 23:02:45.475390  TX OE            : NO K

 3729 23:02:45.475471  All Pass.

 3730 23:02:45.475536  

 3731 23:02:45.478876  CH 1, Rank 0

 3732 23:02:45.478958  SW Impedance     : PASS

 3733 23:02:45.482597  DUTY Scan        : NO K

 3734 23:02:45.485451  ZQ Calibration   : PASS

 3735 23:02:45.485563  Jitter Meter     : NO K

 3736 23:02:45.488755  CBT Training     : PASS

 3737 23:02:45.492154  Write leveling   : PASS

 3738 23:02:45.492272  RX DQS gating    : PASS

 3739 23:02:45.495783  RX DQ/DQS(RDDQC) : PASS

 3740 23:02:45.498778  TX DQ/DQS        : PASS

 3741 23:02:45.498892  RX DATLAT        : PASS

 3742 23:02:45.502291  RX DQ/DQS(Engine): PASS

 3743 23:02:45.502388  TX OE            : NO K

 3744 23:02:45.505817  All Pass.

 3745 23:02:45.505894  

 3746 23:02:45.505957  CH 1, Rank 1

 3747 23:02:45.508615  SW Impedance     : PASS

 3748 23:02:45.508714  DUTY Scan        : NO K

 3749 23:02:45.512349  ZQ Calibration   : PASS

 3750 23:02:45.515253  Jitter Meter     : NO K

 3751 23:02:45.515354  CBT Training     : PASS

 3752 23:02:45.518812  Write leveling   : PASS

 3753 23:02:45.521920  RX DQS gating    : PASS

 3754 23:02:45.522035  RX DQ/DQS(RDDQC) : PASS

 3755 23:02:45.525446  TX DQ/DQS        : PASS

 3756 23:02:45.529003  RX DATLAT        : PASS

 3757 23:02:45.529113  RX DQ/DQS(Engine): PASS

 3758 23:02:45.532104  TX OE            : NO K

 3759 23:02:45.532184  All Pass.

 3760 23:02:45.532256  

 3761 23:02:45.535175  DramC Write-DBI off

 3762 23:02:45.538585  	PER_BANK_REFRESH: Hybrid Mode

 3763 23:02:45.538668  TX_TRACKING: ON

 3764 23:02:45.548607  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3765 23:02:45.551614  [FAST_K] Save calibration result to emmc

 3766 23:02:45.555494  dramc_set_vcore_voltage set vcore to 650000

 3767 23:02:45.558424  Read voltage for 600, 5

 3768 23:02:45.558587  Vio18 = 0

 3769 23:02:45.558687  Vcore = 650000

 3770 23:02:45.561680  Vdram = 0

 3771 23:02:45.561818  Vddq = 0

 3772 23:02:45.561916  Vmddr = 0

 3773 23:02:45.568299  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3774 23:02:45.571408  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3775 23:02:45.574746  MEM_TYPE=3, freq_sel=19

 3776 23:02:45.577983  sv_algorithm_assistance_LP4_1600 

 3777 23:02:45.581283  ============ PULL DRAM RESETB DOWN ============

 3778 23:02:45.588170  ========== PULL DRAM RESETB DOWN end =========

 3779 23:02:45.591224  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3780 23:02:45.594482  =================================== 

 3781 23:02:45.598065  LPDDR4 DRAM CONFIGURATION

 3782 23:02:45.601653  =================================== 

 3783 23:02:45.601740  EX_ROW_EN[0]    = 0x0

 3784 23:02:45.604556  EX_ROW_EN[1]    = 0x0

 3785 23:02:45.604665  LP4Y_EN      = 0x0

 3786 23:02:45.608229  WORK_FSP     = 0x0

 3787 23:02:45.608338  WL           = 0x2

 3788 23:02:45.611261  RL           = 0x2

 3789 23:02:45.611342  BL           = 0x2

 3790 23:02:45.614932  RPST         = 0x0

 3791 23:02:45.615011  RD_PRE       = 0x0

 3792 23:02:45.617816  WR_PRE       = 0x1

 3793 23:02:45.617919  WR_PST       = 0x0

 3794 23:02:45.621490  DBI_WR       = 0x0

 3795 23:02:45.624439  DBI_RD       = 0x0

 3796 23:02:45.624528  OTF          = 0x1

 3797 23:02:45.628114  =================================== 

 3798 23:02:45.631275  =================================== 

 3799 23:02:45.631366  ANA top config

 3800 23:02:45.634813  =================================== 

 3801 23:02:45.637756  DLL_ASYNC_EN            =  0

 3802 23:02:45.640800  ALL_SLAVE_EN            =  1

 3803 23:02:45.644293  NEW_RANK_MODE           =  1

 3804 23:02:45.647998  DLL_IDLE_MODE           =  1

 3805 23:02:45.648098  LP45_APHY_COMB_EN       =  1

 3806 23:02:45.650798  TX_ODT_DIS              =  1

 3807 23:02:45.654104  NEW_8X_MODE             =  1

 3808 23:02:45.657473  =================================== 

 3809 23:02:45.661162  =================================== 

 3810 23:02:45.664531  data_rate                  = 1200

 3811 23:02:45.667712  CKR                        = 1

 3812 23:02:45.667791  DQ_P2S_RATIO               = 8

 3813 23:02:45.670878  =================================== 

 3814 23:02:45.674269  CA_P2S_RATIO               = 8

 3815 23:02:45.677377  DQ_CA_OPEN                 = 0

 3816 23:02:45.680733  DQ_SEMI_OPEN               = 0

 3817 23:02:45.684238  CA_SEMI_OPEN               = 0

 3818 23:02:45.687619  CA_FULL_RATE               = 0

 3819 23:02:45.687725  DQ_CKDIV4_EN               = 1

 3820 23:02:45.690991  CA_CKDIV4_EN               = 1

 3821 23:02:45.694029  CA_PREDIV_EN               = 0

 3822 23:02:45.697483  PH8_DLY                    = 0

 3823 23:02:45.700896  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3824 23:02:45.704039  DQ_AAMCK_DIV               = 4

 3825 23:02:45.704152  CA_AAMCK_DIV               = 4

 3826 23:02:45.707493  CA_ADMCK_DIV               = 4

 3827 23:02:45.711314  DQ_TRACK_CA_EN             = 0

 3828 23:02:45.714321  CA_PICK                    = 600

 3829 23:02:45.717794  CA_MCKIO                   = 600

 3830 23:02:45.720843  MCKIO_SEMI                 = 0

 3831 23:02:45.724344  PLL_FREQ                   = 2288

 3832 23:02:45.724453  DQ_UI_PI_RATIO             = 32

 3833 23:02:45.727420  CA_UI_PI_RATIO             = 0

 3834 23:02:45.731246  =================================== 

 3835 23:02:45.734096  =================================== 

 3836 23:02:45.737760  memory_type:LPDDR4         

 3837 23:02:45.740572  GP_NUM     : 10       

 3838 23:02:45.740653  SRAM_EN    : 1       

 3839 23:02:45.744271  MD32_EN    : 0       

 3840 23:02:45.747373  =================================== 

 3841 23:02:45.747483  [ANA_INIT] >>>>>>>>>>>>>> 

 3842 23:02:45.750990  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3843 23:02:45.753808  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3844 23:02:45.757423  =================================== 

 3845 23:02:45.760846  data_rate = 1200,PCW = 0X5800

 3846 23:02:45.763821  =================================== 

 3847 23:02:45.767302  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3848 23:02:45.773789  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3849 23:02:45.780824  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3850 23:02:45.784067  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3851 23:02:45.787272  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3852 23:02:45.790652  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3853 23:02:45.793812  [ANA_INIT] flow start 

 3854 23:02:45.793892  [ANA_INIT] PLL >>>>>>>> 

 3855 23:02:45.797085  [ANA_INIT] PLL <<<<<<<< 

 3856 23:02:45.800587  [ANA_INIT] MIDPI >>>>>>>> 

 3857 23:02:45.800693  [ANA_INIT] MIDPI <<<<<<<< 

 3858 23:02:45.803724  [ANA_INIT] DLL >>>>>>>> 

 3859 23:02:45.807066  [ANA_INIT] flow end 

 3860 23:02:45.810360  ============ LP4 DIFF to SE enter ============

 3861 23:02:45.813509  ============ LP4 DIFF to SE exit  ============

 3862 23:02:45.816852  [ANA_INIT] <<<<<<<<<<<<< 

 3863 23:02:45.820049  [Flow] Enable top DCM control >>>>> 

 3864 23:02:45.823756  [Flow] Enable top DCM control <<<<< 

 3865 23:02:45.826712  Enable DLL master slave shuffle 

 3866 23:02:45.830311  ============================================================== 

 3867 23:02:45.833282  Gating Mode config

 3868 23:02:45.840061  ============================================================== 

 3869 23:02:45.840169  Config description: 

 3870 23:02:45.850141  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3871 23:02:45.856387  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3872 23:02:45.863064  SELPH_MODE            0: By rank         1: By Phase 

 3873 23:02:45.866578  ============================================================== 

 3874 23:02:45.869586  GAT_TRACK_EN                 =  1

 3875 23:02:45.873212  RX_GATING_MODE               =  2

 3876 23:02:45.876786  RX_GATING_TRACK_MODE         =  2

 3877 23:02:45.879576  SELPH_MODE                   =  1

 3878 23:02:45.882871  PICG_EARLY_EN                =  1

 3879 23:02:45.886356  VALID_LAT_VALUE              =  1

 3880 23:02:45.890047  ============================================================== 

 3881 23:02:45.893041  Enter into Gating configuration >>>> 

 3882 23:02:45.896530  Exit from Gating configuration <<<< 

 3883 23:02:45.899863  Enter into  DVFS_PRE_config >>>>> 

 3884 23:02:45.912686  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3885 23:02:45.915944  Exit from  DVFS_PRE_config <<<<< 

 3886 23:02:45.919802  Enter into PICG configuration >>>> 

 3887 23:02:45.919900  Exit from PICG configuration <<<< 

 3888 23:02:45.922883  [RX_INPUT] configuration >>>>> 

 3889 23:02:45.926312  [RX_INPUT] configuration <<<<< 

 3890 23:02:45.984006  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3891 23:02:45.984179  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3892 23:02:45.984305  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3893 23:02:45.984404  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3894 23:02:45.984536  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3895 23:02:45.984691  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3896 23:02:45.984831  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3897 23:02:45.984930  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3898 23:02:45.985037  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3899 23:02:45.985146  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3900 23:02:45.985283  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3901 23:02:45.985706  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3902 23:02:45.989282  =================================== 

 3903 23:02:45.992512  LPDDR4 DRAM CONFIGURATION

 3904 23:02:45.996065  =================================== 

 3905 23:02:45.999207  EX_ROW_EN[0]    = 0x0

 3906 23:02:45.999359  EX_ROW_EN[1]    = 0x0

 3907 23:02:46.002839  LP4Y_EN      = 0x0

 3908 23:02:46.002973  WORK_FSP     = 0x0

 3909 23:02:46.005834  WL           = 0x2

 3910 23:02:46.005922  RL           = 0x2

 3911 23:02:46.009407  BL           = 0x2

 3912 23:02:46.009531  RPST         = 0x0

 3913 23:02:46.012633  RD_PRE       = 0x0

 3914 23:02:46.012747  WR_PRE       = 0x1

 3915 23:02:46.015691  WR_PST       = 0x0

 3916 23:02:46.015807  DBI_WR       = 0x0

 3917 23:02:46.019120  DBI_RD       = 0x0

 3918 23:02:46.019235  OTF          = 0x1

 3919 23:02:46.022774  =================================== 

 3920 23:02:46.029503  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3921 23:02:46.032367  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3922 23:02:46.035740  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3923 23:02:46.039427  =================================== 

 3924 23:02:46.042413  LPDDR4 DRAM CONFIGURATION

 3925 23:02:46.045920  =================================== 

 3926 23:02:46.046006  EX_ROW_EN[0]    = 0x10

 3927 23:02:46.049215  EX_ROW_EN[1]    = 0x0

 3928 23:02:46.052385  LP4Y_EN      = 0x0

 3929 23:02:46.052492  WORK_FSP     = 0x0

 3930 23:02:46.055499  WL           = 0x2

 3931 23:02:46.055602  RL           = 0x2

 3932 23:02:46.059042  BL           = 0x2

 3933 23:02:46.059152  RPST         = 0x0

 3934 23:02:46.062657  RD_PRE       = 0x0

 3935 23:02:46.062734  WR_PRE       = 0x1

 3936 23:02:46.065688  WR_PST       = 0x0

 3937 23:02:46.065778  DBI_WR       = 0x0

 3938 23:02:46.069205  DBI_RD       = 0x0

 3939 23:02:46.069313  OTF          = 0x1

 3940 23:02:46.072712  =================================== 

 3941 23:02:46.079272  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3942 23:02:46.083512  nWR fixed to 30

 3943 23:02:46.087111  [ModeRegInit_LP4] CH0 RK0

 3944 23:02:46.087260  [ModeRegInit_LP4] CH0 RK1

 3945 23:02:46.090142  [ModeRegInit_LP4] CH1 RK0

 3946 23:02:46.093450  [ModeRegInit_LP4] CH1 RK1

 3947 23:02:46.093601  match AC timing 17

 3948 23:02:46.099897  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3949 23:02:46.103330  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3950 23:02:46.106691  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3951 23:02:46.113447  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3952 23:02:46.116384  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3953 23:02:46.116524  ==

 3954 23:02:46.119692  Dram Type= 6, Freq= 0, CH_0, rank 0

 3955 23:02:46.123382  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3956 23:02:46.123520  ==

 3957 23:02:46.130055  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3958 23:02:46.136509  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3959 23:02:46.140205  [CA 0] Center 36 (5~67) winsize 63

 3960 23:02:46.143008  [CA 1] Center 36 (5~67) winsize 63

 3961 23:02:46.146388  [CA 2] Center 33 (3~64) winsize 62

 3962 23:02:46.149971  [CA 3] Center 33 (2~64) winsize 63

 3963 23:02:46.153308  [CA 4] Center 33 (2~64) winsize 63

 3964 23:02:46.156664  [CA 5] Center 32 (2~63) winsize 62

 3965 23:02:46.156758  

 3966 23:02:46.159970  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3967 23:02:46.160063  

 3968 23:02:46.163122  [CATrainingPosCal] consider 1 rank data

 3969 23:02:46.166470  u2DelayCellTimex100 = 270/100 ps

 3970 23:02:46.169607  CA0 delay=36 (5~67),Diff = 4 PI (38 cell)

 3971 23:02:46.173243  CA1 delay=36 (5~67),Diff = 4 PI (38 cell)

 3972 23:02:46.176344  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3973 23:02:46.179766  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3974 23:02:46.183095  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3975 23:02:46.186125  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3976 23:02:46.189593  

 3977 23:02:46.193133  CA PerBit enable=1, Macro0, CA PI delay=32

 3978 23:02:46.193291  

 3979 23:02:46.196198  [CBTSetCACLKResult] CA Dly = 32

 3980 23:02:46.196342  CS Dly: 5 (0~36)

 3981 23:02:46.196460  ==

 3982 23:02:46.199666  Dram Type= 6, Freq= 0, CH_0, rank 1

 3983 23:02:46.202668  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3984 23:02:46.206374  ==

 3985 23:02:46.209766  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3986 23:02:46.215926  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3987 23:02:46.219634  [CA 0] Center 35 (5~66) winsize 62

 3988 23:02:46.222562  [CA 1] Center 35 (5~66) winsize 62

 3989 23:02:46.226099  [CA 2] Center 34 (3~65) winsize 63

 3990 23:02:46.229387  [CA 3] Center 33 (3~64) winsize 62

 3991 23:02:46.232751  [CA 4] Center 33 (2~64) winsize 63

 3992 23:02:46.235700  [CA 5] Center 32 (2~63) winsize 62

 3993 23:02:46.235815  

 3994 23:02:46.239628  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3995 23:02:46.239718  

 3996 23:02:46.242498  [CATrainingPosCal] consider 2 rank data

 3997 23:02:46.246167  u2DelayCellTimex100 = 270/100 ps

 3998 23:02:46.249071  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3999 23:02:46.252638  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 4000 23:02:46.256278  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 4001 23:02:46.259253  CA3 delay=33 (3~64),Diff = 1 PI (9 cell)

 4002 23:02:46.265629  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 4003 23:02:46.269071  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 4004 23:02:46.269246  

 4005 23:02:46.272497  CA PerBit enable=1, Macro0, CA PI delay=32

 4006 23:02:46.272588  

 4007 23:02:46.276022  [CBTSetCACLKResult] CA Dly = 32

 4008 23:02:46.276109  CS Dly: 5 (0~36)

 4009 23:02:46.276174  

 4010 23:02:46.279132  ----->DramcWriteLeveling(PI) begin...

 4011 23:02:46.279217  ==

 4012 23:02:46.282307  Dram Type= 6, Freq= 0, CH_0, rank 0

 4013 23:02:46.288952  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4014 23:02:46.289049  ==

 4015 23:02:46.292273  Write leveling (Byte 0): 32 => 32

 4016 23:02:46.295933  Write leveling (Byte 1): 32 => 32

 4017 23:02:46.296020  DramcWriteLeveling(PI) end<-----

 4018 23:02:46.296086  

 4019 23:02:46.298910  ==

 4020 23:02:46.302394  Dram Type= 6, Freq= 0, CH_0, rank 0

 4021 23:02:46.305809  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4022 23:02:46.305922  ==

 4023 23:02:46.308940  [Gating] SW mode calibration

 4024 23:02:46.316065  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4025 23:02:46.318905  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4026 23:02:46.325811   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4027 23:02:46.329240   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4028 23:02:46.332306   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 4029 23:02:46.339324   0  9 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)

 4030 23:02:46.341996   0  9 16 | B1->B0 | 3232 2323 | 1 0 | (1 1) (0 0)

 4031 23:02:46.345331   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4032 23:02:46.351860   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4033 23:02:46.355367   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4034 23:02:46.359008   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4035 23:02:46.365513   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4036 23:02:46.368606   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4037 23:02:46.372045   0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)

 4038 23:02:46.378601   0 10 16 | B1->B0 | 3232 4646 | 1 0 | (1 1) (0 0)

 4039 23:02:46.382054   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4040 23:02:46.385746   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4041 23:02:46.391835   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4042 23:02:46.395279   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4043 23:02:46.398709   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4044 23:02:46.405158   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4045 23:02:46.408365   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4046 23:02:46.411568   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4047 23:02:46.418459   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4048 23:02:46.421345   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4049 23:02:46.425067   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4050 23:02:46.431833   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4051 23:02:46.434850   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4052 23:02:46.438354   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4053 23:02:46.441380   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4054 23:02:46.448501   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4055 23:02:46.451198   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4056 23:02:46.454516   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4057 23:02:46.461120   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4058 23:02:46.464696   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4059 23:02:46.467704   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4060 23:02:46.474865   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4061 23:02:46.477727   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4062 23:02:46.481333   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4063 23:02:46.484766  Total UI for P1: 0, mck2ui 16

 4064 23:02:46.487605  best dqsien dly found for B0: ( 0, 13, 12)

 4065 23:02:46.494933   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4066 23:02:46.497506  Total UI for P1: 0, mck2ui 16

 4067 23:02:46.500928  best dqsien dly found for B1: ( 0, 13, 16)

 4068 23:02:46.504450  best DQS0 dly(MCK, UI, PI) = (0, 13, 12)

 4069 23:02:46.507589  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4070 23:02:46.507670  

 4071 23:02:46.511182  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4072 23:02:46.514357  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4073 23:02:46.517740  [Gating] SW calibration Done

 4074 23:02:46.517821  ==

 4075 23:02:46.520992  Dram Type= 6, Freq= 0, CH_0, rank 0

 4076 23:02:46.523966  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4077 23:02:46.524086  ==

 4078 23:02:46.527946  RX Vref Scan: 0

 4079 23:02:46.528061  

 4080 23:02:46.530690  RX Vref 0 -> 0, step: 1

 4081 23:02:46.530779  

 4082 23:02:46.530846  RX Delay -230 -> 252, step: 16

 4083 23:02:46.537572  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4084 23:02:46.540782  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4085 23:02:46.544255  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4086 23:02:46.547390  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4087 23:02:46.554028  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4088 23:02:46.557484  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4089 23:02:46.560551  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4090 23:02:46.563847  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4091 23:02:46.567131  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4092 23:02:46.574144  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4093 23:02:46.577083  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4094 23:02:46.580480  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4095 23:02:46.583830  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4096 23:02:46.590378  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4097 23:02:46.593804  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4098 23:02:46.597268  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4099 23:02:46.597361  ==

 4100 23:02:46.600383  Dram Type= 6, Freq= 0, CH_0, rank 0

 4101 23:02:46.603784  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4102 23:02:46.607408  ==

 4103 23:02:46.607497  DQS Delay:

 4104 23:02:46.607564  DQS0 = 0, DQS1 = 0

 4105 23:02:46.610395  DQM Delay:

 4106 23:02:46.610479  DQM0 = 51, DQM1 = 45

 4107 23:02:46.613962  DQ Delay:

 4108 23:02:46.617029  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49

 4109 23:02:46.617113  DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57

 4110 23:02:46.620628  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4111 23:02:46.623622  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49

 4112 23:02:46.627210  

 4113 23:02:46.627294  

 4114 23:02:46.627358  ==

 4115 23:02:46.630640  Dram Type= 6, Freq= 0, CH_0, rank 0

 4116 23:02:46.633987  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4117 23:02:46.634073  ==

 4118 23:02:46.634139  

 4119 23:02:46.634199  

 4120 23:02:46.637167  	TX Vref Scan disable

 4121 23:02:46.637251   == TX Byte 0 ==

 4122 23:02:46.643663  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4123 23:02:46.647070  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4124 23:02:46.647171   == TX Byte 1 ==

 4125 23:02:46.653822  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4126 23:02:46.657382  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4127 23:02:46.657499  ==

 4128 23:02:46.660398  Dram Type= 6, Freq= 0, CH_0, rank 0

 4129 23:02:46.663348  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4130 23:02:46.663436  ==

 4131 23:02:46.663503  

 4132 23:02:46.663567  

 4133 23:02:46.667006  	TX Vref Scan disable

 4134 23:02:46.670004   == TX Byte 0 ==

 4135 23:02:46.673716  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4136 23:02:46.676720  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4137 23:02:46.680230   == TX Byte 1 ==

 4138 23:02:46.683547  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4139 23:02:46.686677  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4140 23:02:46.686807  

 4141 23:02:46.690281  [DATLAT]

 4142 23:02:46.690407  Freq=600, CH0 RK0

 4143 23:02:46.690496  

 4144 23:02:46.693426  DATLAT Default: 0x9

 4145 23:02:46.693550  0, 0xFFFF, sum = 0

 4146 23:02:46.696713  1, 0xFFFF, sum = 0

 4147 23:02:46.696820  2, 0xFFFF, sum = 0

 4148 23:02:46.700201  3, 0xFFFF, sum = 0

 4149 23:02:46.700315  4, 0xFFFF, sum = 0

 4150 23:02:46.703800  5, 0xFFFF, sum = 0

 4151 23:02:46.703925  6, 0xFFFF, sum = 0

 4152 23:02:46.706680  7, 0xFFFF, sum = 0

 4153 23:02:46.706802  8, 0x0, sum = 1

 4154 23:02:46.710236  9, 0x0, sum = 2

 4155 23:02:46.710318  10, 0x0, sum = 3

 4156 23:02:46.713329  11, 0x0, sum = 4

 4157 23:02:46.713444  best_step = 9

 4158 23:02:46.713544  

 4159 23:02:46.713642  ==

 4160 23:02:46.716834  Dram Type= 6, Freq= 0, CH_0, rank 0

 4161 23:02:46.723694  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4162 23:02:46.723789  ==

 4163 23:02:46.723855  RX Vref Scan: 1

 4164 23:02:46.723916  

 4165 23:02:46.726600  RX Vref 0 -> 0, step: 1

 4166 23:02:46.726684  

 4167 23:02:46.730096  RX Delay -163 -> 252, step: 8

 4168 23:02:46.730174  

 4169 23:02:46.733545  Set Vref, RX VrefLevel [Byte0]: 54

 4170 23:02:46.736573                           [Byte1]: 48

 4171 23:02:46.736654  

 4172 23:02:46.740250  Final RX Vref Byte 0 = 54 to rank0

 4173 23:02:46.743186  Final RX Vref Byte 1 = 48 to rank0

 4174 23:02:46.746681  Final RX Vref Byte 0 = 54 to rank1

 4175 23:02:46.750340  Final RX Vref Byte 1 = 48 to rank1==

 4176 23:02:46.753147  Dram Type= 6, Freq= 0, CH_0, rank 0

 4177 23:02:46.756491  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4178 23:02:46.756572  ==

 4179 23:02:46.759878  DQS Delay:

 4180 23:02:46.759954  DQS0 = 0, DQS1 = 0

 4181 23:02:46.760035  DQM Delay:

 4182 23:02:46.763002  DQM0 = 53, DQM1 = 46

 4183 23:02:46.763087  DQ Delay:

 4184 23:02:46.766630  DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =52

 4185 23:02:46.770312  DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56

 4186 23:02:46.773289  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4187 23:02:46.776877  DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52

 4188 23:02:46.776992  

 4189 23:02:46.777090  

 4190 23:02:46.786435  [DQSOSCAuto] RK0, (LSB)MR18= 0x6f63, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps

 4191 23:02:46.786568  CH0 RK0: MR19=808, MR18=6F63

 4192 23:02:46.793165  CH0_RK0: MR19=0x808, MR18=0x6F63, DQSOSC=389, MR23=63, INC=173, DEC=115

 4193 23:02:46.793269  

 4194 23:02:46.796595  ----->DramcWriteLeveling(PI) begin...

 4195 23:02:46.800032  ==

 4196 23:02:46.800159  Dram Type= 6, Freq= 0, CH_0, rank 1

 4197 23:02:46.806112  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4198 23:02:46.806255  ==

 4199 23:02:46.809998  Write leveling (Byte 0): 34 => 34

 4200 23:02:46.812804  Write leveling (Byte 1): 31 => 31

 4201 23:02:46.816371  DramcWriteLeveling(PI) end<-----

 4202 23:02:46.816497  

 4203 23:02:46.816593  ==

 4204 23:02:46.819923  Dram Type= 6, Freq= 0, CH_0, rank 1

 4205 23:02:46.823271  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4206 23:02:46.823368  ==

 4207 23:02:46.826227  [Gating] SW mode calibration

 4208 23:02:46.832786  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4209 23:02:46.836723  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4210 23:02:46.843038   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4211 23:02:46.845978   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4212 23:02:46.849524   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4213 23:02:46.856226   0  9 12 | B1->B0 | 3434 3333 | 0 0 | (0 1) (0 1)

 4214 23:02:46.859711   0  9 16 | B1->B0 | 2c2c 2c2c | 1 1 | (1 0) (1 0)

 4215 23:02:46.862635   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4216 23:02:46.869161   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4217 23:02:46.872730   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4218 23:02:46.875957   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4219 23:02:46.882777   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4220 23:02:46.885730   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4221 23:02:46.889131   0 10 12 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)

 4222 23:02:46.895766   0 10 16 | B1->B0 | 3c3c 4444 | 0 0 | (0 0) (0 0)

 4223 23:02:46.899461   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4224 23:02:46.902453   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4225 23:02:46.909172   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4226 23:02:46.912281   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4227 23:02:46.915569   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4228 23:02:46.922445   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4229 23:02:46.925928   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4230 23:02:46.929201   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4231 23:02:46.935617   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4232 23:02:46.939345   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4233 23:02:46.942305   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4234 23:02:46.948755   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4235 23:02:46.952300   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4236 23:02:46.955402   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4237 23:02:46.961980   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4238 23:02:46.965454   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4239 23:02:46.968575   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4240 23:02:46.975078   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4241 23:02:46.978614   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4242 23:02:46.981733   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4243 23:02:46.988995   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4244 23:02:46.992111   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4245 23:02:46.995328   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4246 23:02:46.998532  Total UI for P1: 0, mck2ui 16

 4247 23:02:47.002069  best dqsien dly found for B0: ( 0, 13,  8)

 4248 23:02:47.005007   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4249 23:02:47.008469  Total UI for P1: 0, mck2ui 16

 4250 23:02:47.012071  best dqsien dly found for B1: ( 0, 13, 12)

 4251 23:02:47.015038  best DQS0 dly(MCK, UI, PI) = (0, 13, 8)

 4252 23:02:47.021683  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4253 23:02:47.021779  

 4254 23:02:47.025076  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)

 4255 23:02:47.028373  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4256 23:02:47.031772  [Gating] SW calibration Done

 4257 23:02:47.031879  ==

 4258 23:02:47.034981  Dram Type= 6, Freq= 0, CH_0, rank 1

 4259 23:02:47.038285  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4260 23:02:47.038371  ==

 4261 23:02:47.041910  RX Vref Scan: 0

 4262 23:02:47.041998  

 4263 23:02:47.042064  RX Vref 0 -> 0, step: 1

 4264 23:02:47.042126  

 4265 23:02:47.045079  RX Delay -230 -> 252, step: 16

 4266 23:02:47.048426  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4267 23:02:47.054831  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4268 23:02:47.058297  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4269 23:02:47.062036  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4270 23:02:47.064909  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4271 23:02:47.068166  iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304

 4272 23:02:47.075119  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4273 23:02:47.077979  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4274 23:02:47.081602  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4275 23:02:47.084632  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4276 23:02:47.091403  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4277 23:02:47.094739  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4278 23:02:47.098044  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4279 23:02:47.101265  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4280 23:02:47.107740  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4281 23:02:47.110855  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4282 23:02:47.110968  ==

 4283 23:02:47.114765  Dram Type= 6, Freq= 0, CH_0, rank 1

 4284 23:02:47.118062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4285 23:02:47.118143  ==

 4286 23:02:47.121276  DQS Delay:

 4287 23:02:47.121367  DQS0 = 0, DQS1 = 0

 4288 23:02:47.121430  DQM Delay:

 4289 23:02:47.124373  DQM0 = 52, DQM1 = 43

 4290 23:02:47.124452  DQ Delay:

 4291 23:02:47.127524  DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49

 4292 23:02:47.130842  DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57

 4293 23:02:47.134624  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33

 4294 23:02:47.137621  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4295 23:02:47.137725  

 4296 23:02:47.137801  

 4297 23:02:47.137863  ==

 4298 23:02:47.141155  Dram Type= 6, Freq= 0, CH_0, rank 1

 4299 23:02:47.147516  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4300 23:02:47.147631  ==

 4301 23:02:47.147723  

 4302 23:02:47.147785  

 4303 23:02:47.147842  	TX Vref Scan disable

 4304 23:02:47.151179   == TX Byte 0 ==

 4305 23:02:47.154546  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4306 23:02:47.161458  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4307 23:02:47.161547   == TX Byte 1 ==

 4308 23:02:47.164433  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4309 23:02:47.171143  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4310 23:02:47.171234  ==

 4311 23:02:47.174712  Dram Type= 6, Freq= 0, CH_0, rank 1

 4312 23:02:47.178157  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4313 23:02:47.178243  ==

 4314 23:02:47.178309  

 4315 23:02:47.178368  

 4316 23:02:47.181164  	TX Vref Scan disable

 4317 23:02:47.184811   == TX Byte 0 ==

 4318 23:02:47.187927  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4319 23:02:47.191548  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4320 23:02:47.194568   == TX Byte 1 ==

 4321 23:02:47.197595  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4322 23:02:47.201250  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4323 23:02:47.201332  

 4324 23:02:47.201396  [DATLAT]

 4325 23:02:47.204644  Freq=600, CH0 RK1

 4326 23:02:47.204729  

 4327 23:02:47.207580  DATLAT Default: 0x9

 4328 23:02:47.207662  0, 0xFFFF, sum = 0

 4329 23:02:47.211236  1, 0xFFFF, sum = 0

 4330 23:02:47.211321  2, 0xFFFF, sum = 0

 4331 23:02:47.214228  3, 0xFFFF, sum = 0

 4332 23:02:47.214313  4, 0xFFFF, sum = 0

 4333 23:02:47.217960  5, 0xFFFF, sum = 0

 4334 23:02:47.218054  6, 0xFFFF, sum = 0

 4335 23:02:47.221007  7, 0xFFFF, sum = 0

 4336 23:02:47.221094  8, 0x0, sum = 1

 4337 23:02:47.224720  9, 0x0, sum = 2

 4338 23:02:47.224806  10, 0x0, sum = 3

 4339 23:02:47.224894  11, 0x0, sum = 4

 4340 23:02:47.227474  best_step = 9

 4341 23:02:47.227559  

 4342 23:02:47.227645  ==

 4343 23:02:47.230818  Dram Type= 6, Freq= 0, CH_0, rank 1

 4344 23:02:47.234525  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4345 23:02:47.234613  ==

 4346 23:02:47.237400  RX Vref Scan: 0

 4347 23:02:47.237508  

 4348 23:02:47.237609  RX Vref 0 -> 0, step: 1

 4349 23:02:47.241036  

 4350 23:02:47.241123  RX Delay -163 -> 252, step: 8

 4351 23:02:47.248608  iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288

 4352 23:02:47.252096  iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280

 4353 23:02:47.255462  iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288

 4354 23:02:47.258419  iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288

 4355 23:02:47.261863  iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280

 4356 23:02:47.268366  iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288

 4357 23:02:47.271585  iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272

 4358 23:02:47.274925  iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272

 4359 23:02:47.278362  iDelay=197, Bit 8, Center 40 (-99 ~ 180) 280

 4360 23:02:47.281809  iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288

 4361 23:02:47.288446  iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280

 4362 23:02:47.291515  iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280

 4363 23:02:47.295005  iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280

 4364 23:02:47.298417  iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288

 4365 23:02:47.305038  iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280

 4366 23:02:47.308174  iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288

 4367 23:02:47.308256  ==

 4368 23:02:47.311632  Dram Type= 6, Freq= 0, CH_0, rank 1

 4369 23:02:47.315181  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4370 23:02:47.315259  ==

 4371 23:02:47.315320  DQS Delay:

 4372 23:02:47.318139  DQS0 = 0, DQS1 = 0

 4373 23:02:47.318240  DQM Delay:

 4374 23:02:47.321644  DQM0 = 54, DQM1 = 46

 4375 23:02:47.321723  DQ Delay:

 4376 23:02:47.324618  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4377 23:02:47.328239  DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60

 4378 23:02:47.331387  DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40

 4379 23:02:47.334948  DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52

 4380 23:02:47.335030  

 4381 23:02:47.335098  

 4382 23:02:47.344953  [DQSOSCAuto] RK1, (LSB)MR18= 0x6527, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 390 ps

 4383 23:02:47.345083  CH0 RK1: MR19=808, MR18=6527

 4384 23:02:47.351299  CH0_RK1: MR19=0x808, MR18=0x6527, DQSOSC=390, MR23=63, INC=172, DEC=114

 4385 23:02:47.354917  [RxdqsGatingPostProcess] freq 600

 4386 23:02:47.361548  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4387 23:02:47.364386  Pre-setting of DQS Precalculation

 4388 23:02:47.367758  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4389 23:02:47.367872  ==

 4390 23:02:47.371263  Dram Type= 6, Freq= 0, CH_1, rank 0

 4391 23:02:47.377621  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4392 23:02:47.377734  ==

 4393 23:02:47.381432  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4394 23:02:47.387945  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4395 23:02:47.391029  [CA 0] Center 36 (5~67) winsize 63

 4396 23:02:47.394912  [CA 1] Center 36 (5~67) winsize 63

 4397 23:02:47.398276  [CA 2] Center 34 (4~65) winsize 62

 4398 23:02:47.400928  [CA 3] Center 34 (4~65) winsize 62

 4399 23:02:47.404765  [CA 4] Center 34 (4~65) winsize 62

 4400 23:02:47.407655  [CA 5] Center 33 (3~64) winsize 62

 4401 23:02:47.407762  

 4402 23:02:47.411075  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4403 23:02:47.411182  

 4404 23:02:47.414263  [CATrainingPosCal] consider 1 rank data

 4405 23:02:47.417737  u2DelayCellTimex100 = 270/100 ps

 4406 23:02:47.421358  CA0 delay=36 (5~67),Diff = 3 PI (28 cell)

 4407 23:02:47.424281  CA1 delay=36 (5~67),Diff = 3 PI (28 cell)

 4408 23:02:47.428024  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4409 23:02:47.434629  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 4410 23:02:47.437591  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4411 23:02:47.441418  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4412 23:02:47.441502  

 4413 23:02:47.444665  CA PerBit enable=1, Macro0, CA PI delay=33

 4414 23:02:47.444748  

 4415 23:02:47.447864  [CBTSetCACLKResult] CA Dly = 33

 4416 23:02:47.447977  CS Dly: 6 (0~37)

 4417 23:02:47.448072  ==

 4418 23:02:47.450961  Dram Type= 6, Freq= 0, CH_1, rank 1

 4419 23:02:47.457892  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4420 23:02:47.457997  ==

 4421 23:02:47.461386  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4422 23:02:47.467860  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4423 23:02:47.471015  [CA 0] Center 36 (6~67) winsize 62

 4424 23:02:47.474570  [CA 1] Center 36 (5~67) winsize 63

 4425 23:02:47.478203  [CA 2] Center 34 (4~65) winsize 62

 4426 23:02:47.481216  [CA 3] Center 34 (4~65) winsize 62

 4427 23:02:47.484514  [CA 4] Center 34 (4~65) winsize 62

 4428 23:02:47.487306  [CA 5] Center 34 (4~65) winsize 62

 4429 23:02:47.487405  

 4430 23:02:47.491106  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4431 23:02:47.491215  

 4432 23:02:47.494147  [CATrainingPosCal] consider 2 rank data

 4433 23:02:47.497597  u2DelayCellTimex100 = 270/100 ps

 4434 23:02:47.500916  CA0 delay=36 (6~67),Diff = 2 PI (19 cell)

 4435 23:02:47.504539  CA1 delay=36 (5~67),Diff = 2 PI (19 cell)

 4436 23:02:47.510732  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 4437 23:02:47.513900  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4438 23:02:47.517525  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4439 23:02:47.520525  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 4440 23:02:47.520633  

 4441 23:02:47.523814  CA PerBit enable=1, Macro0, CA PI delay=34

 4442 23:02:47.523920  

 4443 23:02:47.527370  [CBTSetCACLKResult] CA Dly = 34

 4444 23:02:47.527449  CS Dly: 6 (0~38)

 4445 23:02:47.527535  

 4446 23:02:47.530981  ----->DramcWriteLeveling(PI) begin...

 4447 23:02:47.533909  ==

 4448 23:02:47.537546  Dram Type= 6, Freq= 0, CH_1, rank 0

 4449 23:02:47.540749  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4450 23:02:47.540825  ==

 4451 23:02:47.544262  Write leveling (Byte 0): 31 => 31

 4452 23:02:47.547284  Write leveling (Byte 1): 31 => 31

 4453 23:02:47.550714  DramcWriteLeveling(PI) end<-----

 4454 23:02:47.550828  

 4455 23:02:47.550924  ==

 4456 23:02:47.554085  Dram Type= 6, Freq= 0, CH_1, rank 0

 4457 23:02:47.568308  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4458 23:02:47.568480  ==

 4459 23:02:47.568591  [Gating] SW mode calibration

 4460 23:02:47.568690  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4461 23:02:47.573610  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4462 23:02:47.577143   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4463 23:02:47.580317   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4464 23:02:47.587276   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4465 23:02:47.590158   0  9 12 | B1->B0 | 2f2f 2e2e | 1 0 | (1 0) (0 0)

 4466 23:02:47.593976   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4467 23:02:47.600166   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4468 23:02:47.603541   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4469 23:02:47.607187   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4470 23:02:47.610061   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4471 23:02:47.616967   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4472 23:02:47.620361   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4473 23:02:47.623239   0 10 12 | B1->B0 | 3737 4343 | 1 0 | (0 0) (0 0)

 4474 23:02:47.630250   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4475 23:02:47.633423   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4476 23:02:47.637031   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4477 23:02:47.643496   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4478 23:02:47.646731   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4479 23:02:47.650261   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4480 23:02:47.656845   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4481 23:02:47.659857   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4482 23:02:47.663181   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4483 23:02:47.669973   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4484 23:02:47.673228   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4485 23:02:47.676699   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4486 23:02:47.683103   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4487 23:02:47.686841   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4488 23:02:47.689858   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4489 23:02:47.696342   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4490 23:02:47.699661   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4491 23:02:47.703038   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4492 23:02:47.709881   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4493 23:02:47.713306   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4494 23:02:47.716428   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4495 23:02:47.723267   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4496 23:02:47.726587   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4497 23:02:47.729723   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4498 23:02:47.733188  Total UI for P1: 0, mck2ui 16

 4499 23:02:47.736588  best dqsien dly found for B0: ( 0, 13, 10)

 4500 23:02:47.739602  Total UI for P1: 0, mck2ui 16

 4501 23:02:47.743164  best dqsien dly found for B1: ( 0, 13, 10)

 4502 23:02:47.746232  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4503 23:02:47.749755  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4504 23:02:47.749869  

 4505 23:02:47.752871  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4506 23:02:47.759861  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4507 23:02:47.759954  [Gating] SW calibration Done

 4508 23:02:47.760020  ==

 4509 23:02:47.762906  Dram Type= 6, Freq= 0, CH_1, rank 0

 4510 23:02:47.769378  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4511 23:02:47.769475  ==

 4512 23:02:47.769541  RX Vref Scan: 0

 4513 23:02:47.769614  

 4514 23:02:47.772736  RX Vref 0 -> 0, step: 1

 4515 23:02:47.772820  

 4516 23:02:47.776010  RX Delay -230 -> 252, step: 16

 4517 23:02:47.779601  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4518 23:02:47.783023  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4519 23:02:47.789731  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4520 23:02:47.792770  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4521 23:02:47.796476  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4522 23:02:47.799386  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4523 23:02:47.802775  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4524 23:02:47.809330  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4525 23:02:47.812819  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4526 23:02:47.816151  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4527 23:02:47.819312  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4528 23:02:47.825554  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4529 23:02:47.829443  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4530 23:02:47.832839  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4531 23:02:47.836041  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4532 23:02:47.842520  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4533 23:02:47.842628  ==

 4534 23:02:47.845915  Dram Type= 6, Freq= 0, CH_1, rank 0

 4535 23:02:47.849394  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4536 23:02:47.849514  ==

 4537 23:02:47.849621  DQS Delay:

 4538 23:02:47.852414  DQS0 = 0, DQS1 = 0

 4539 23:02:47.852500  DQM Delay:

 4540 23:02:47.856194  DQM0 = 47, DQM1 = 46

 4541 23:02:47.856287  DQ Delay:

 4542 23:02:47.859101  DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41

 4543 23:02:47.862195  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4544 23:02:47.865929  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4545 23:02:47.868969  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4546 23:02:47.869064  

 4547 23:02:47.869149  

 4548 23:02:47.869230  ==

 4549 23:02:47.872343  Dram Type= 6, Freq= 0, CH_1, rank 0

 4550 23:02:47.876014  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4551 23:02:47.876104  ==

 4552 23:02:47.876189  

 4553 23:02:47.876269  

 4554 23:02:47.879312  	TX Vref Scan disable

 4555 23:02:47.882799   == TX Byte 0 ==

 4556 23:02:47.885823  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4557 23:02:47.889353  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4558 23:02:47.892251   == TX Byte 1 ==

 4559 23:02:47.895782  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4560 23:02:47.899395  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4561 23:02:47.899485  ==

 4562 23:02:47.902356  Dram Type= 6, Freq= 0, CH_1, rank 0

 4563 23:02:47.908723  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4564 23:02:47.908841  ==

 4565 23:02:47.908933  

 4566 23:02:47.909018  

 4567 23:02:47.909077  	TX Vref Scan disable

 4568 23:02:47.913141   == TX Byte 0 ==

 4569 23:02:47.916697  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4570 23:02:47.920182  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4571 23:02:47.923509   == TX Byte 1 ==

 4572 23:02:47.926799  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4573 23:02:47.930148  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4574 23:02:47.933531  

 4575 23:02:47.933642  [DATLAT]

 4576 23:02:47.933713  Freq=600, CH1 RK0

 4577 23:02:47.933776  

 4578 23:02:47.936481  DATLAT Default: 0x9

 4579 23:02:47.936564  0, 0xFFFF, sum = 0

 4580 23:02:47.939821  1, 0xFFFF, sum = 0

 4581 23:02:47.939907  2, 0xFFFF, sum = 0

 4582 23:02:47.943281  3, 0xFFFF, sum = 0

 4583 23:02:47.943367  4, 0xFFFF, sum = 0

 4584 23:02:47.946742  5, 0xFFFF, sum = 0

 4585 23:02:47.950033  6, 0xFFFF, sum = 0

 4586 23:02:47.950131  7, 0xFFFF, sum = 0

 4587 23:02:47.950220  8, 0x0, sum = 1

 4588 23:02:47.953526  9, 0x0, sum = 2

 4589 23:02:47.953635  10, 0x0, sum = 3

 4590 23:02:47.956324  11, 0x0, sum = 4

 4591 23:02:47.956412  best_step = 9

 4592 23:02:47.956497  

 4593 23:02:47.956578  ==

 4594 23:02:47.959975  Dram Type= 6, Freq= 0, CH_1, rank 0

 4595 23:02:47.966557  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4596 23:02:47.966658  ==

 4597 23:02:47.966749  RX Vref Scan: 1

 4598 23:02:47.966830  

 4599 23:02:47.970100  RX Vref 0 -> 0, step: 1

 4600 23:02:47.970220  

 4601 23:02:47.973382  RX Delay -163 -> 252, step: 8

 4602 23:02:47.973485  

 4603 23:02:47.976857  Set Vref, RX VrefLevel [Byte0]: 52

 4604 23:02:47.979573                           [Byte1]: 46

 4605 23:02:47.979702  

 4606 23:02:47.982942  Final RX Vref Byte 0 = 52 to rank0

 4607 23:02:47.986558  Final RX Vref Byte 1 = 46 to rank0

 4608 23:02:47.989546  Final RX Vref Byte 0 = 52 to rank1

 4609 23:02:47.993190  Final RX Vref Byte 1 = 46 to rank1==

 4610 23:02:47.996647  Dram Type= 6, Freq= 0, CH_1, rank 0

 4611 23:02:47.999548  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4612 23:02:47.999674  ==

 4613 23:02:48.003185  DQS Delay:

 4614 23:02:48.003306  DQS0 = 0, DQS1 = 0

 4615 23:02:48.003412  DQM Delay:

 4616 23:02:48.006118  DQM0 = 48, DQM1 = 46

 4617 23:02:48.006236  DQ Delay:

 4618 23:02:48.009529  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4619 23:02:48.013069  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48

 4620 23:02:48.016165  DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40

 4621 23:02:48.019625  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56

 4622 23:02:48.019752  

 4623 23:02:48.019849  

 4624 23:02:48.029274  [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps

 4625 23:02:48.032708  CH1 RK0: MR19=808, MR18=476C

 4626 23:02:48.039486  CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115

 4627 23:02:48.039587  

 4628 23:02:48.042695  ----->DramcWriteLeveling(PI) begin...

 4629 23:02:48.042821  ==

 4630 23:02:48.046186  Dram Type= 6, Freq= 0, CH_1, rank 1

 4631 23:02:48.049263  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4632 23:02:48.049377  ==

 4633 23:02:48.052757  Write leveling (Byte 0): 28 => 28

 4634 23:02:48.056262  Write leveling (Byte 1): 30 => 30

 4635 23:02:48.058960  DramcWriteLeveling(PI) end<-----

 4636 23:02:48.059073  

 4637 23:02:48.059174  ==

 4638 23:02:48.062329  Dram Type= 6, Freq= 0, CH_1, rank 1

 4639 23:02:48.066007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4640 23:02:48.066139  ==

 4641 23:02:48.068870  [Gating] SW mode calibration

 4642 23:02:48.075489  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4643 23:02:48.082321  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4644 23:02:48.085358   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4645 23:02:48.088702   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4646 23:02:48.095323   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4647 23:02:48.099000   0  9 12 | B1->B0 | 2f2f 3030 | 0 0 | (1 1) (0 1)

 4648 23:02:48.101902   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 4649 23:02:48.109019   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4650 23:02:48.111824   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4651 23:02:48.115235   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4652 23:02:48.122053   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4653 23:02:48.125091   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4654 23:02:48.128770   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 4655 23:02:48.135372   0 10 12 | B1->B0 | 3c3c 3333 | 0 1 | (1 1) (0 0)

 4656 23:02:48.138208   0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 4657 23:02:48.141612   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4658 23:02:48.148431   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4659 23:02:48.151939   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4660 23:02:48.155160   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4661 23:02:48.161465   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4662 23:02:48.164859   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4663 23:02:48.168430   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4664 23:02:48.175134   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4665 23:02:48.178307   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4666 23:02:48.181758   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4667 23:02:48.185203   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4668 23:02:48.191983   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4669 23:02:48.194796   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4670 23:02:48.198406   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4671 23:02:48.204958   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4672 23:02:48.208448   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4673 23:02:48.211446   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4674 23:02:48.218536   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4675 23:02:48.221304   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4676 23:02:48.225190   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4677 23:02:48.231337   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4678 23:02:48.234964   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4679 23:02:48.237939   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4680 23:02:48.244914   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4681 23:02:48.245011  Total UI for P1: 0, mck2ui 16

 4682 23:02:48.251377  best dqsien dly found for B0: ( 0, 13, 14)

 4683 23:02:48.251503  Total UI for P1: 0, mck2ui 16

 4684 23:02:48.258016  best dqsien dly found for B1: ( 0, 13, 10)

 4685 23:02:48.261499  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4686 23:02:48.265097  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4687 23:02:48.265210  

 4688 23:02:48.268219  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4689 23:02:48.271003  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4690 23:02:48.274835  [Gating] SW calibration Done

 4691 23:02:48.274960  ==

 4692 23:02:48.277669  Dram Type= 6, Freq= 0, CH_1, rank 1

 4693 23:02:48.281207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4694 23:02:48.281314  ==

 4695 23:02:48.284786  RX Vref Scan: 0

 4696 23:02:48.284906  

 4697 23:02:48.285018  RX Vref 0 -> 0, step: 1

 4698 23:02:48.285116  

 4699 23:02:48.288139  RX Delay -230 -> 252, step: 16

 4700 23:02:48.294447  iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288

 4701 23:02:48.297774  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4702 23:02:48.301341  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4703 23:02:48.304849  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4704 23:02:48.307847  iDelay=218, Bit 4, Center 57 (-86 ~ 201) 288

 4705 23:02:48.314434  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4706 23:02:48.317744  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4707 23:02:48.321189  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4708 23:02:48.324152  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4709 23:02:48.327638  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4710 23:02:48.334294  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4711 23:02:48.338006  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4712 23:02:48.340981  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4713 23:02:48.344657  iDelay=218, Bit 13, Center 65 (-86 ~ 217) 304

 4714 23:02:48.351200  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4715 23:02:48.354506  iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304

 4716 23:02:48.354629  ==

 4717 23:02:48.357495  Dram Type= 6, Freq= 0, CH_1, rank 1

 4718 23:02:48.361207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4719 23:02:48.361337  ==

 4720 23:02:48.364271  DQS Delay:

 4721 23:02:48.364396  DQS0 = 0, DQS1 = 0

 4722 23:02:48.364495  DQM Delay:

 4723 23:02:48.367857  DQM0 = 53, DQM1 = 49

 4724 23:02:48.367983  DQ Delay:

 4725 23:02:48.370943  DQ0 =57, DQ1 =49, DQ2 =33, DQ3 =49

 4726 23:02:48.374267  DQ4 =57, DQ5 =65, DQ6 =65, DQ7 =49

 4727 23:02:48.377573  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4728 23:02:48.381041  DQ12 =57, DQ13 =65, DQ14 =49, DQ15 =65

 4729 23:02:48.381123  

 4730 23:02:48.381191  

 4731 23:02:48.381251  ==

 4732 23:02:48.384222  Dram Type= 6, Freq= 0, CH_1, rank 1

 4733 23:02:48.390678  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4734 23:02:48.390812  ==

 4735 23:02:48.390916  

 4736 23:02:48.391020  

 4737 23:02:48.391136  	TX Vref Scan disable

 4738 23:02:48.394253   == TX Byte 0 ==

 4739 23:02:48.398005  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4740 23:02:48.404341  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4741 23:02:48.404471   == TX Byte 1 ==

 4742 23:02:48.407848  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4743 23:02:48.414729  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4744 23:02:48.414851  ==

 4745 23:02:48.417804  Dram Type= 6, Freq= 0, CH_1, rank 1

 4746 23:02:48.420933  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4747 23:02:48.421056  ==

 4748 23:02:48.421154  

 4749 23:02:48.421267  

 4750 23:02:48.424345  	TX Vref Scan disable

 4751 23:02:48.427740   == TX Byte 0 ==

 4752 23:02:48.430921  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4753 23:02:48.434759  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4754 23:02:48.434880   == TX Byte 1 ==

 4755 23:02:48.441135  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4756 23:02:48.444206  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4757 23:02:48.444328  

 4758 23:02:48.444434  [DATLAT]

 4759 23:02:48.447773  Freq=600, CH1 RK1

 4760 23:02:48.447887  

 4761 23:02:48.447998  DATLAT Default: 0x9

 4762 23:02:48.451250  0, 0xFFFF, sum = 0

 4763 23:02:48.451365  1, 0xFFFF, sum = 0

 4764 23:02:48.454238  2, 0xFFFF, sum = 0

 4765 23:02:48.457532  3, 0xFFFF, sum = 0

 4766 23:02:48.457655  4, 0xFFFF, sum = 0

 4767 23:02:48.461020  5, 0xFFFF, sum = 0

 4768 23:02:48.461153  6, 0xFFFF, sum = 0

 4769 23:02:48.464095  7, 0xFFFF, sum = 0

 4770 23:02:48.464224  8, 0x0, sum = 1

 4771 23:02:48.464330  9, 0x0, sum = 2

 4772 23:02:48.467729  10, 0x0, sum = 3

 4773 23:02:48.467847  11, 0x0, sum = 4

 4774 23:02:48.471501  best_step = 9

 4775 23:02:48.471617  

 4776 23:02:48.471729  ==

 4777 23:02:48.474354  Dram Type= 6, Freq= 0, CH_1, rank 1

 4778 23:02:48.478062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4779 23:02:48.478184  ==

 4780 23:02:48.480958  RX Vref Scan: 0

 4781 23:02:48.481078  

 4782 23:02:48.481184  RX Vref 0 -> 0, step: 1

 4783 23:02:48.481281  

 4784 23:02:48.484423  RX Delay -163 -> 252, step: 8

 4785 23:02:48.491432  iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280

 4786 23:02:48.494807  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4787 23:02:48.497920  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4788 23:02:48.501653  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4789 23:02:48.504635  iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280

 4790 23:02:48.511807  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4791 23:02:48.514798  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4792 23:02:48.517819  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4793 23:02:48.521200  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4794 23:02:48.524653  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4795 23:02:48.531189  iDelay=205, Bit 10, Center 44 (-99 ~ 188) 288

 4796 23:02:48.534625  iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288

 4797 23:02:48.537931  iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296

 4798 23:02:48.541523  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4799 23:02:48.547977  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4800 23:02:48.551104  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4801 23:02:48.551236  ==

 4802 23:02:48.554678  Dram Type= 6, Freq= 0, CH_1, rank 1

 4803 23:02:48.558246  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4804 23:02:48.558363  ==

 4805 23:02:48.561142  DQS Delay:

 4806 23:02:48.561253  DQS0 = 0, DQS1 = 0

 4807 23:02:48.561364  DQM Delay:

 4808 23:02:48.564594  DQM0 = 49, DQM1 = 44

 4809 23:02:48.564713  DQ Delay:

 4810 23:02:48.567999  DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44

 4811 23:02:48.571018  DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48

 4812 23:02:48.574515  DQ8 =32, DQ9 =32, DQ10 =44, DQ11 =36

 4813 23:02:48.578198  DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52

 4814 23:02:48.578291  

 4815 23:02:48.578357  

 4816 23:02:48.587718  [DQSOSCAuto] RK1, (LSB)MR18= 0x6a22, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps

 4817 23:02:48.591287  CH1 RK1: MR19=808, MR18=6A22

 4818 23:02:48.594264  CH1_RK1: MR19=0x808, MR18=0x6A22, DQSOSC=389, MR23=63, INC=173, DEC=115

 4819 23:02:48.598068  [RxdqsGatingPostProcess] freq 600

 4820 23:02:48.604192  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4821 23:02:48.607679  Pre-setting of DQS Precalculation

 4822 23:02:48.610907  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4823 23:02:48.617275  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4824 23:02:48.627245  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4825 23:02:48.627342  

 4826 23:02:48.627412  

 4827 23:02:48.630806  [Calibration Summary] 1200 Mbps

 4828 23:02:48.630888  CH 0, Rank 0

 4829 23:02:48.634230  SW Impedance     : PASS

 4830 23:02:48.634311  DUTY Scan        : NO K

 4831 23:02:48.637279  ZQ Calibration   : PASS

 4832 23:02:48.640731  Jitter Meter     : NO K

 4833 23:02:48.640811  CBT Training     : PASS

 4834 23:02:48.644341  Write leveling   : PASS

 4835 23:02:48.647355  RX DQS gating    : PASS

 4836 23:02:48.647460  RX DQ/DQS(RDDQC) : PASS

 4837 23:02:48.650748  TX DQ/DQS        : PASS

 4838 23:02:48.650826  RX DATLAT        : PASS

 4839 23:02:48.654169  RX DQ/DQS(Engine): PASS

 4840 23:02:48.657167  TX OE            : NO K

 4841 23:02:48.657252  All Pass.

 4842 23:02:48.657316  

 4843 23:02:48.657385  CH 0, Rank 1

 4844 23:02:48.660952  SW Impedance     : PASS

 4845 23:02:48.664158  DUTY Scan        : NO K

 4846 23:02:48.664238  ZQ Calibration   : PASS

 4847 23:02:48.667206  Jitter Meter     : NO K

 4848 23:02:48.671092  CBT Training     : PASS

 4849 23:02:48.671188  Write leveling   : PASS

 4850 23:02:48.673785  RX DQS gating    : PASS

 4851 23:02:48.677194  RX DQ/DQS(RDDQC) : PASS

 4852 23:02:48.677295  TX DQ/DQS        : PASS

 4853 23:02:48.680491  RX DATLAT        : PASS

 4854 23:02:48.683944  RX DQ/DQS(Engine): PASS

 4855 23:02:48.684051  TX OE            : NO K

 4856 23:02:48.687132  All Pass.

 4857 23:02:48.687237  

 4858 23:02:48.687328  CH 1, Rank 0

 4859 23:02:48.690555  SW Impedance     : PASS

 4860 23:02:48.690669  DUTY Scan        : NO K

 4861 23:02:48.694015  ZQ Calibration   : PASS

 4862 23:02:48.697653  Jitter Meter     : NO K

 4863 23:02:48.697768  CBT Training     : PASS

 4864 23:02:48.700437  Write leveling   : PASS

 4865 23:02:48.700547  RX DQS gating    : PASS

 4866 23:02:48.704156  RX DQ/DQS(RDDQC) : PASS

 4867 23:02:48.707241  TX DQ/DQS        : PASS

 4868 23:02:48.707325  RX DATLAT        : PASS

 4869 23:02:48.710759  RX DQ/DQS(Engine): PASS

 4870 23:02:48.713688  TX OE            : NO K

 4871 23:02:48.713773  All Pass.

 4872 23:02:48.713837  

 4873 23:02:48.713897  CH 1, Rank 1

 4874 23:02:48.717057  SW Impedance     : PASS

 4875 23:02:48.720386  DUTY Scan        : NO K

 4876 23:02:48.720497  ZQ Calibration   : PASS

 4877 23:02:48.724251  Jitter Meter     : NO K

 4878 23:02:48.727193  CBT Training     : PASS

 4879 23:02:48.727272  Write leveling   : PASS

 4880 23:02:48.730184  RX DQS gating    : PASS

 4881 23:02:48.733542  RX DQ/DQS(RDDQC) : PASS

 4882 23:02:48.733634  TX DQ/DQS        : PASS

 4883 23:02:48.736991  RX DATLAT        : PASS

 4884 23:02:48.740582  RX DQ/DQS(Engine): PASS

 4885 23:02:48.740671  TX OE            : NO K

 4886 23:02:48.740749  All Pass.

 4887 23:02:48.744128  

 4888 23:02:48.744209  DramC Write-DBI off

 4889 23:02:48.746882  	PER_BANK_REFRESH: Hybrid Mode

 4890 23:02:48.746967  TX_TRACKING: ON

 4891 23:02:48.757215  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4892 23:02:48.760204  [FAST_K] Save calibration result to emmc

 4893 23:02:48.763727  dramc_set_vcore_voltage set vcore to 662500

 4894 23:02:48.766874  Read voltage for 933, 3

 4895 23:02:48.767041  Vio18 = 0

 4896 23:02:48.770441  Vcore = 662500

 4897 23:02:48.770610  Vdram = 0

 4898 23:02:48.770744  Vddq = 0

 4899 23:02:48.770882  Vmddr = 0

 4900 23:02:48.776931  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4901 23:02:48.783574  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4902 23:02:48.783753  MEM_TYPE=3, freq_sel=17

 4903 23:02:48.786865  sv_algorithm_assistance_LP4_1600 

 4904 23:02:48.790134  ============ PULL DRAM RESETB DOWN ============

 4905 23:02:48.796626  ========== PULL DRAM RESETB DOWN end =========

 4906 23:02:48.800326  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4907 23:02:48.803234  =================================== 

 4908 23:02:48.806560  LPDDR4 DRAM CONFIGURATION

 4909 23:02:48.810125  =================================== 

 4910 23:02:48.810290  EX_ROW_EN[0]    = 0x0

 4911 23:02:48.813157  EX_ROW_EN[1]    = 0x0

 4912 23:02:48.813314  LP4Y_EN      = 0x0

 4913 23:02:48.816613  WORK_FSP     = 0x0

 4914 23:02:48.816772  WL           = 0x3

 4915 23:02:48.820313  RL           = 0x3

 4916 23:02:48.820473  BL           = 0x2

 4917 23:02:48.823205  RPST         = 0x0

 4918 23:02:48.826835  RD_PRE       = 0x0

 4919 23:02:48.827002  WR_PRE       = 0x1

 4920 23:02:48.830030  WR_PST       = 0x0

 4921 23:02:48.830191  DBI_WR       = 0x0

 4922 23:02:48.833464  DBI_RD       = 0x0

 4923 23:02:48.833638  OTF          = 0x1

 4924 23:02:48.837007  =================================== 

 4925 23:02:48.840559  =================================== 

 4926 23:02:48.840727  ANA top config

 4927 23:02:48.843502  =================================== 

 4928 23:02:48.846511  DLL_ASYNC_EN            =  0

 4929 23:02:48.850157  ALL_SLAVE_EN            =  1

 4930 23:02:48.853346  NEW_RANK_MODE           =  1

 4931 23:02:48.856373  DLL_IDLE_MODE           =  1

 4932 23:02:48.856472  LP45_APHY_COMB_EN       =  1

 4933 23:02:48.860068  TX_ODT_DIS              =  1

 4934 23:02:48.863038  NEW_8X_MODE             =  1

 4935 23:02:48.866815  =================================== 

 4936 23:02:48.869717  =================================== 

 4937 23:02:48.873294  data_rate                  = 1866

 4938 23:02:48.876478  CKR                        = 1

 4939 23:02:48.876611  DQ_P2S_RATIO               = 8

 4940 23:02:48.879770  =================================== 

 4941 23:02:48.883219  CA_P2S_RATIO               = 8

 4942 23:02:48.886629  DQ_CA_OPEN                 = 0

 4943 23:02:48.889569  DQ_SEMI_OPEN               = 0

 4944 23:02:48.893178  CA_SEMI_OPEN               = 0

 4945 23:02:48.896698  CA_FULL_RATE               = 0

 4946 23:02:48.896821  DQ_CKDIV4_EN               = 1

 4947 23:02:48.899828  CA_CKDIV4_EN               = 1

 4948 23:02:48.903187  CA_PREDIV_EN               = 0

 4949 23:02:48.906302  PH8_DLY                    = 0

 4950 23:02:48.909794  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4951 23:02:48.913148  DQ_AAMCK_DIV               = 4

 4952 23:02:48.913251  CA_AAMCK_DIV               = 4

 4953 23:02:48.916102  CA_ADMCK_DIV               = 4

 4954 23:02:48.919651  DQ_TRACK_CA_EN             = 0

 4955 23:02:48.923229  CA_PICK                    = 933

 4956 23:02:48.925939  CA_MCKIO                   = 933

 4957 23:02:48.929846  MCKIO_SEMI                 = 0

 4958 23:02:48.933157  PLL_FREQ                   = 3732

 4959 23:02:48.933262  DQ_UI_PI_RATIO             = 32

 4960 23:02:48.936054  CA_UI_PI_RATIO             = 0

 4961 23:02:48.939428  =================================== 

 4962 23:02:48.942689  =================================== 

 4963 23:02:48.946191  memory_type:LPDDR4         

 4964 23:02:48.949308  GP_NUM     : 10       

 4965 23:02:48.949415  SRAM_EN    : 1       

 4966 23:02:48.952760  MD32_EN    : 0       

 4967 23:02:48.955789  =================================== 

 4968 23:02:48.959253  [ANA_INIT] >>>>>>>>>>>>>> 

 4969 23:02:48.959345  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4970 23:02:48.962955  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4971 23:02:48.965904  =================================== 

 4972 23:02:48.969443  data_rate = 1866,PCW = 0X8f00

 4973 23:02:48.972457  =================================== 

 4974 23:02:48.975934  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4975 23:02:48.982797  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4976 23:02:48.989484  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4977 23:02:48.992937  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4978 23:02:48.995909  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4979 23:02:48.999397  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4980 23:02:49.002959  [ANA_INIT] flow start 

 4981 23:02:49.003062  [ANA_INIT] PLL >>>>>>>> 

 4982 23:02:49.005898  [ANA_INIT] PLL <<<<<<<< 

 4983 23:02:49.009290  [ANA_INIT] MIDPI >>>>>>>> 

 4984 23:02:49.009378  [ANA_INIT] MIDPI <<<<<<<< 

 4985 23:02:49.012412  [ANA_INIT] DLL >>>>>>>> 

 4986 23:02:49.016014  [ANA_INIT] flow end 

 4987 23:02:49.019452  ============ LP4 DIFF to SE enter ============

 4988 23:02:49.022802  ============ LP4 DIFF to SE exit  ============

 4989 23:02:49.025606  [ANA_INIT] <<<<<<<<<<<<< 

 4990 23:02:49.029090  [Flow] Enable top DCM control >>>>> 

 4991 23:02:49.032728  [Flow] Enable top DCM control <<<<< 

 4992 23:02:49.035922  Enable DLL master slave shuffle 

 4993 23:02:49.039167  ============================================================== 

 4994 23:02:49.042488  Gating Mode config

 4995 23:02:49.049034  ============================================================== 

 4996 23:02:49.049211  Config description: 

 4997 23:02:49.059112  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4998 23:02:49.066033  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4999 23:02:49.072675  SELPH_MODE            0: By rank         1: By Phase 

 5000 23:02:49.075674  ============================================================== 

 5001 23:02:49.079168  GAT_TRACK_EN                 =  1

 5002 23:02:49.082757  RX_GATING_MODE               =  2

 5003 23:02:49.085942  RX_GATING_TRACK_MODE         =  2

 5004 23:02:49.089278  SELPH_MODE                   =  1

 5005 23:02:49.092998  PICG_EARLY_EN                =  1

 5006 23:02:49.095770  VALID_LAT_VALUE              =  1

 5007 23:02:49.099200  ============================================================== 

 5008 23:02:49.102398  Enter into Gating configuration >>>> 

 5009 23:02:49.105940  Exit from Gating configuration <<<< 

 5010 23:02:49.108975  Enter into  DVFS_PRE_config >>>>> 

 5011 23:02:49.122327  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 5012 23:02:49.122443  Exit from  DVFS_PRE_config <<<<< 

 5013 23:02:49.125662  Enter into PICG configuration >>>> 

 5014 23:02:49.128798  Exit from PICG configuration <<<< 

 5015 23:02:49.132271  [RX_INPUT] configuration >>>>> 

 5016 23:02:49.135407  [RX_INPUT] configuration <<<<< 

 5017 23:02:49.142108  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 5018 23:02:49.145687  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 5019 23:02:49.151962  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 5020 23:02:49.159288  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 5021 23:02:49.165593  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 5022 23:02:49.172482  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 5023 23:02:49.175420  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 5024 23:02:49.179079  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 5025 23:02:49.182086  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 5026 23:02:49.189066  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 5027 23:02:49.191846  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 5028 23:02:49.195389  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5029 23:02:49.198881  =================================== 

 5030 23:02:49.202451  LPDDR4 DRAM CONFIGURATION

 5031 23:02:49.205472  =================================== 

 5032 23:02:49.205598  EX_ROW_EN[0]    = 0x0

 5033 23:02:49.208891  EX_ROW_EN[1]    = 0x0

 5034 23:02:49.212399  LP4Y_EN      = 0x0

 5035 23:02:49.212491  WORK_FSP     = 0x0

 5036 23:02:49.215468  WL           = 0x3

 5037 23:02:49.215575  RL           = 0x3

 5038 23:02:49.219029  BL           = 0x2

 5039 23:02:49.219144  RPST         = 0x0

 5040 23:02:49.222071  RD_PRE       = 0x0

 5041 23:02:49.222172  WR_PRE       = 0x1

 5042 23:02:49.225487  WR_PST       = 0x0

 5043 23:02:49.225605  DBI_WR       = 0x0

 5044 23:02:49.229094  DBI_RD       = 0x0

 5045 23:02:49.229193  OTF          = 0x1

 5046 23:02:49.232103  =================================== 

 5047 23:02:49.235447  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5048 23:02:49.242421  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5049 23:02:49.245312  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5050 23:02:49.248692  =================================== 

 5051 23:02:49.252273  LPDDR4 DRAM CONFIGURATION

 5052 23:02:49.255345  =================================== 

 5053 23:02:49.255427  EX_ROW_EN[0]    = 0x10

 5054 23:02:49.259028  EX_ROW_EN[1]    = 0x0

 5055 23:02:49.259113  LP4Y_EN      = 0x0

 5056 23:02:49.262241  WORK_FSP     = 0x0

 5057 23:02:49.262355  WL           = 0x3

 5058 23:02:49.265295  RL           = 0x3

 5059 23:02:49.269005  BL           = 0x2

 5060 23:02:49.269085  RPST         = 0x0

 5061 23:02:49.271967  RD_PRE       = 0x0

 5062 23:02:49.272055  WR_PRE       = 0x1

 5063 23:02:49.275190  WR_PST       = 0x0

 5064 23:02:49.275272  DBI_WR       = 0x0

 5065 23:02:49.278950  DBI_RD       = 0x0

 5066 23:02:49.279062  OTF          = 0x1

 5067 23:02:49.281895  =================================== 

 5068 23:02:49.288572  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5069 23:02:49.292848  nWR fixed to 30

 5070 23:02:49.295579  [ModeRegInit_LP4] CH0 RK0

 5071 23:02:49.295678  [ModeRegInit_LP4] CH0 RK1

 5072 23:02:49.299461  [ModeRegInit_LP4] CH1 RK0

 5073 23:02:49.302326  [ModeRegInit_LP4] CH1 RK1

 5074 23:02:49.302425  match AC timing 9

 5075 23:02:49.308863  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5076 23:02:49.312183  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5077 23:02:49.315677  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5078 23:02:49.322317  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5079 23:02:49.326065  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5080 23:02:49.326180  ==

 5081 23:02:49.328743  Dram Type= 6, Freq= 0, CH_0, rank 0

 5082 23:02:49.332238  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5083 23:02:49.332326  ==

 5084 23:02:49.339182  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5085 23:02:49.345720  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5086 23:02:49.348802  [CA 0] Center 37 (6~68) winsize 63

 5087 23:02:49.352286  [CA 1] Center 37 (7~68) winsize 62

 5088 23:02:49.355594  [CA 2] Center 34 (4~65) winsize 62

 5089 23:02:49.358746  [CA 3] Center 34 (3~65) winsize 63

 5090 23:02:49.361819  [CA 4] Center 33 (3~64) winsize 62

 5091 23:02:49.365282  [CA 5] Center 32 (2~62) winsize 61

 5092 23:02:49.365394  

 5093 23:02:49.368800  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5094 23:02:49.368900  

 5095 23:02:49.372262  [CATrainingPosCal] consider 1 rank data

 5096 23:02:49.375306  u2DelayCellTimex100 = 270/100 ps

 5097 23:02:49.378925  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5098 23:02:49.381779  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5099 23:02:49.385408  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5100 23:02:49.388468  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5101 23:02:49.392002  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5102 23:02:49.398455  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5103 23:02:49.398552  

 5104 23:02:49.402228  CA PerBit enable=1, Macro0, CA PI delay=32

 5105 23:02:49.402307  

 5106 23:02:49.405145  [CBTSetCACLKResult] CA Dly = 32

 5107 23:02:49.405259  CS Dly: 5 (0~36)

 5108 23:02:49.405348  ==

 5109 23:02:49.408853  Dram Type= 6, Freq= 0, CH_0, rank 1

 5110 23:02:49.411789  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5111 23:02:49.415376  ==

 5112 23:02:49.418675  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5113 23:02:49.425374  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5114 23:02:49.428338  [CA 0] Center 37 (6~68) winsize 63

 5115 23:02:49.431603  [CA 1] Center 37 (7~68) winsize 62

 5116 23:02:49.435050  [CA 2] Center 34 (4~65) winsize 62

 5117 23:02:49.438725  [CA 3] Center 33 (3~64) winsize 62

 5118 23:02:49.441645  [CA 4] Center 33 (3~63) winsize 61

 5119 23:02:49.445005  [CA 5] Center 32 (2~62) winsize 61

 5120 23:02:49.445088  

 5121 23:02:49.448465  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5122 23:02:49.448563  

 5123 23:02:49.452055  [CATrainingPosCal] consider 2 rank data

 5124 23:02:49.454804  u2DelayCellTimex100 = 270/100 ps

 5125 23:02:49.458353  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5126 23:02:49.461813  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5127 23:02:49.464904  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5128 23:02:49.468653  CA3 delay=33 (3~64),Diff = 1 PI (6 cell)

 5129 23:02:49.474925  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5130 23:02:49.478637  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5131 23:02:49.478813  

 5132 23:02:49.481603  CA PerBit enable=1, Macro0, CA PI delay=32

 5133 23:02:49.481762  

 5134 23:02:49.485249  [CBTSetCACLKResult] CA Dly = 32

 5135 23:02:49.485417  CS Dly: 5 (0~37)

 5136 23:02:49.485560  

 5137 23:02:49.487953  ----->DramcWriteLeveling(PI) begin...

 5138 23:02:49.488117  ==

 5139 23:02:49.491586  Dram Type= 6, Freq= 0, CH_0, rank 0

 5140 23:02:49.498347  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5141 23:02:49.498539  ==

 5142 23:02:49.501345  Write leveling (Byte 0): 32 => 32

 5143 23:02:49.501503  Write leveling (Byte 1): 30 => 30

 5144 23:02:49.504805  DramcWriteLeveling(PI) end<-----

 5145 23:02:49.504968  

 5146 23:02:49.508451  ==

 5147 23:02:49.508617  Dram Type= 6, Freq= 0, CH_0, rank 0

 5148 23:02:49.515002  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5149 23:02:49.515170  ==

 5150 23:02:49.518046  [Gating] SW mode calibration

 5151 23:02:49.525276  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5152 23:02:49.528235  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5153 23:02:49.534738   0 14  0 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)

 5154 23:02:49.538168   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5155 23:02:49.541513   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5156 23:02:49.548201   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5157 23:02:49.551323   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5158 23:02:49.554909   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5159 23:02:49.561362   0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 5160 23:02:49.564496   0 14 28 | B1->B0 | 3434 2525 | 1 0 | (1 0) (1 0)

 5161 23:02:49.568034   0 15  0 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)

 5162 23:02:49.574849   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5163 23:02:49.578172   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5164 23:02:49.581606   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5165 23:02:49.584536   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5166 23:02:49.591567   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5167 23:02:49.595005   0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

 5168 23:02:49.597958   0 15 28 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)

 5169 23:02:49.604512   1  0  0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)

 5170 23:02:49.608046   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5171 23:02:49.611157   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5172 23:02:49.618224   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5173 23:02:49.621237   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5174 23:02:49.624843   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5175 23:02:49.631388   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5176 23:02:49.634522   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 5177 23:02:49.638053   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5178 23:02:49.644829   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5179 23:02:49.648466   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5180 23:02:49.651633   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5181 23:02:49.657852   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5182 23:02:49.661518   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5183 23:02:49.664886   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5184 23:02:49.670937   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5185 23:02:49.674337   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5186 23:02:49.677439   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5187 23:02:49.684682   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5188 23:02:49.687757   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5189 23:02:49.690720   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5190 23:02:49.697464   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5191 23:02:49.700695   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5192 23:02:49.704597   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5193 23:02:49.711103   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5194 23:02:49.711239  Total UI for P1: 0, mck2ui 16

 5195 23:02:49.714227  best dqsien dly found for B0: ( 1,  2, 26)

 5196 23:02:49.720763   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5197 23:02:49.724383  Total UI for P1: 0, mck2ui 16

 5198 23:02:49.727380  best dqsien dly found for B1: ( 1,  3,  0)

 5199 23:02:49.731101  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5200 23:02:49.734616  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5201 23:02:49.734718  

 5202 23:02:49.737701  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5203 23:02:49.741288  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5204 23:02:49.744389  [Gating] SW calibration Done

 5205 23:02:49.744473  ==

 5206 23:02:49.748129  Dram Type= 6, Freq= 0, CH_0, rank 0

 5207 23:02:49.750801  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5208 23:02:49.750976  ==

 5209 23:02:49.754267  RX Vref Scan: 0

 5210 23:02:49.754435  

 5211 23:02:49.754577  RX Vref 0 -> 0, step: 1

 5212 23:02:49.754728  

 5213 23:02:49.757805  RX Delay -80 -> 252, step: 8

 5214 23:02:49.764285  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5215 23:02:49.767710  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5216 23:02:49.770865  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5217 23:02:49.774327  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5218 23:02:49.777875  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5219 23:02:49.780765  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5220 23:02:49.787338  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5221 23:02:49.791114  iDelay=208, Bit 7, Center 111 (16 ~ 207) 192

 5222 23:02:49.794072  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5223 23:02:49.797334  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5224 23:02:49.800864  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5225 23:02:49.803823  iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192

 5226 23:02:49.810864  iDelay=208, Bit 12, Center 103 (16 ~ 191) 176

 5227 23:02:49.814166  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5228 23:02:49.817166  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5229 23:02:49.820507  iDelay=208, Bit 15, Center 103 (16 ~ 191) 176

 5230 23:02:49.820674  ==

 5231 23:02:49.824150  Dram Type= 6, Freq= 0, CH_0, rank 0

 5232 23:02:49.830665  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5233 23:02:49.830848  ==

 5234 23:02:49.831006  DQS Delay:

 5235 23:02:49.834483  DQS0 = 0, DQS1 = 0

 5236 23:02:49.834639  DQM Delay:

 5237 23:02:49.834791  DQM0 = 104, DQM1 = 95

 5238 23:02:49.837289  DQ Delay:

 5239 23:02:49.840379  DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99

 5240 23:02:49.843972  DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111

 5241 23:02:49.847529  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87

 5242 23:02:49.850697  DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103

 5243 23:02:49.850861  

 5244 23:02:49.851011  

 5245 23:02:49.851147  ==

 5246 23:02:49.854157  Dram Type= 6, Freq= 0, CH_0, rank 0

 5247 23:02:49.857282  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5248 23:02:49.857447  ==

 5249 23:02:49.857598  

 5250 23:02:49.857750  

 5251 23:02:49.860623  	TX Vref Scan disable

 5252 23:02:49.863821   == TX Byte 0 ==

 5253 23:02:49.867317  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5254 23:02:49.870976  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5255 23:02:49.873983   == TX Byte 1 ==

 5256 23:02:49.877204  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5257 23:02:49.880355  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5258 23:02:49.880530  ==

 5259 23:02:49.883670  Dram Type= 6, Freq= 0, CH_0, rank 0

 5260 23:02:49.890461  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5261 23:02:49.890635  ==

 5262 23:02:49.890798  

 5263 23:02:49.890961  

 5264 23:02:49.891097  	TX Vref Scan disable

 5265 23:02:49.894121   == TX Byte 0 ==

 5266 23:02:49.897661  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5267 23:02:49.904593  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5268 23:02:49.904788   == TX Byte 1 ==

 5269 23:02:49.907511  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5270 23:02:49.914088  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5271 23:02:49.914275  

 5272 23:02:49.914431  [DATLAT]

 5273 23:02:49.914579  Freq=933, CH0 RK0

 5274 23:02:49.914718  

 5275 23:02:49.917731  DATLAT Default: 0xd

 5276 23:02:49.917896  0, 0xFFFF, sum = 0

 5277 23:02:49.921298  1, 0xFFFF, sum = 0

 5278 23:02:49.921456  2, 0xFFFF, sum = 0

 5279 23:02:49.924196  3, 0xFFFF, sum = 0

 5280 23:02:49.927605  4, 0xFFFF, sum = 0

 5281 23:02:49.927773  5, 0xFFFF, sum = 0

 5282 23:02:49.930622  6, 0xFFFF, sum = 0

 5283 23:02:49.930778  7, 0xFFFF, sum = 0

 5284 23:02:49.934259  8, 0xFFFF, sum = 0

 5285 23:02:49.934423  9, 0xFFFF, sum = 0

 5286 23:02:49.937484  10, 0x0, sum = 1

 5287 23:02:49.937655  11, 0x0, sum = 2

 5288 23:02:49.940727  12, 0x0, sum = 3

 5289 23:02:49.940892  13, 0x0, sum = 4

 5290 23:02:49.941032  best_step = 11

 5291 23:02:49.941178  

 5292 23:02:49.944122  ==

 5293 23:02:49.947254  Dram Type= 6, Freq= 0, CH_0, rank 0

 5294 23:02:49.950624  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5295 23:02:49.950787  ==

 5296 23:02:49.950937  RX Vref Scan: 1

 5297 23:02:49.951084  

 5298 23:02:49.954107  RX Vref 0 -> 0, step: 1

 5299 23:02:49.954271  

 5300 23:02:49.957271  RX Delay -53 -> 252, step: 4

 5301 23:02:49.957426  

 5302 23:02:49.960725  Set Vref, RX VrefLevel [Byte0]: 54

 5303 23:02:49.963629                           [Byte1]: 48

 5304 23:02:49.963790  

 5305 23:02:49.967462  Final RX Vref Byte 0 = 54 to rank0

 5306 23:02:49.970321  Final RX Vref Byte 1 = 48 to rank0

 5307 23:02:49.973768  Final RX Vref Byte 0 = 54 to rank1

 5308 23:02:49.976900  Final RX Vref Byte 1 = 48 to rank1==

 5309 23:02:49.980504  Dram Type= 6, Freq= 0, CH_0, rank 0

 5310 23:02:49.986734  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5311 23:02:49.986909  ==

 5312 23:02:49.987059  DQS Delay:

 5313 23:02:49.987203  DQS0 = 0, DQS1 = 0

 5314 23:02:49.990002  DQM Delay:

 5315 23:02:49.990158  DQM0 = 104, DQM1 = 95

 5316 23:02:49.993440  DQ Delay:

 5317 23:02:49.996464  DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102

 5318 23:02:50.000045  DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110

 5319 23:02:50.003572  DQ8 =82, DQ9 =86, DQ10 =96, DQ11 =90

 5320 23:02:50.006517  DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =104

 5321 23:02:50.006676  

 5322 23:02:50.006829  

 5323 23:02:50.013376  [DQSOSCAuto] RK0, (LSB)MR18= 0x3129, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps

 5324 23:02:50.016426  CH0 RK0: MR19=505, MR18=3129

 5325 23:02:50.023628  CH0_RK0: MR19=0x505, MR18=0x3129, DQSOSC=406, MR23=63, INC=65, DEC=43

 5326 23:02:50.023799  

 5327 23:02:50.026481  ----->DramcWriteLeveling(PI) begin...

 5328 23:02:50.026650  ==

 5329 23:02:50.030051  Dram Type= 6, Freq= 0, CH_0, rank 1

 5330 23:02:50.033591  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5331 23:02:50.036552  ==

 5332 23:02:50.036723  Write leveling (Byte 0): 34 => 34

 5333 23:02:50.040155  Write leveling (Byte 1): 31 => 31

 5334 23:02:50.043188  DramcWriteLeveling(PI) end<-----

 5335 23:02:50.043354  

 5336 23:02:50.043498  ==

 5337 23:02:50.046347  Dram Type= 6, Freq= 0, CH_0, rank 1

 5338 23:02:50.053409  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5339 23:02:50.053572  ==

 5340 23:02:50.053736  [Gating] SW mode calibration

 5341 23:02:50.062846  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5342 23:02:50.066375  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5343 23:02:50.073269   0 14  0 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)

 5344 23:02:50.076467   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5345 23:02:50.079586   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5346 23:02:50.083220   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5347 23:02:50.089771   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5348 23:02:50.092821   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5349 23:02:50.096433   0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 5350 23:02:50.102876   0 14 28 | B1->B0 | 2b2b 2a2a | 1 1 | (1 1) (1 0)

 5351 23:02:50.105925   0 15  0 | B1->B0 | 2525 2424 | 0 0 | (0 0) (0 0)

 5352 23:02:50.109660   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5353 23:02:50.116430   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5354 23:02:50.119251   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5355 23:02:50.122478   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5356 23:02:50.129552   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5357 23:02:50.132680   0 15 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 5358 23:02:50.136234   0 15 28 | B1->B0 | 3838 3736 | 0 1 | (0 0) (0 0)

 5359 23:02:50.142751   1  0  0 | B1->B0 | 4646 4040 | 0 1 | (0 0) (0 0)

 5360 23:02:50.145773   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5361 23:02:50.149414   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5362 23:02:50.155920   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5363 23:02:50.159075   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5364 23:02:50.162680   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5365 23:02:50.169178   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5366 23:02:50.172648   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5367 23:02:50.176046   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5368 23:02:50.182724   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5369 23:02:50.185569   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5370 23:02:50.189811   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5371 23:02:50.195822   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5372 23:02:50.198967   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5373 23:02:50.202172   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5374 23:02:50.209203   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5375 23:02:50.212144   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5376 23:02:50.215650   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5377 23:02:50.222429   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5378 23:02:50.225461   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5379 23:02:50.229201   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5380 23:02:50.235883   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5381 23:02:50.238841   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5382 23:02:50.242353   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5383 23:02:50.245311   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5384 23:02:50.248810  Total UI for P1: 0, mck2ui 16

 5385 23:02:50.252317  best dqsien dly found for B0: ( 1,  2, 28)

 5386 23:02:50.255360  Total UI for P1: 0, mck2ui 16

 5387 23:02:50.258797  best dqsien dly found for B1: ( 1,  2, 30)

 5388 23:02:50.261968  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5389 23:02:50.265451  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5390 23:02:50.269120  

 5391 23:02:50.272057  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5392 23:02:50.275784  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5393 23:02:50.278600  [Gating] SW calibration Done

 5394 23:02:50.278683  ==

 5395 23:02:50.282268  Dram Type= 6, Freq= 0, CH_0, rank 1

 5396 23:02:50.285162  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5397 23:02:50.285245  ==

 5398 23:02:50.285309  RX Vref Scan: 0

 5399 23:02:50.288812  

 5400 23:02:50.288893  RX Vref 0 -> 0, step: 1

 5401 23:02:50.288958  

 5402 23:02:50.292282  RX Delay -80 -> 252, step: 8

 5403 23:02:50.295229  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5404 23:02:50.298508  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5405 23:02:50.305109  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5406 23:02:50.308472  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5407 23:02:50.311858  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5408 23:02:50.315167  iDelay=208, Bit 5, Center 99 (8 ~ 191) 184

 5409 23:02:50.318296  iDelay=208, Bit 6, Center 107 (16 ~ 199) 184

 5410 23:02:50.321864  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5411 23:02:50.328197  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5412 23:02:50.331734  iDelay=208, Bit 9, Center 91 (8 ~ 175) 168

 5413 23:02:50.335159  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5414 23:02:50.338354  iDelay=208, Bit 11, Center 91 (8 ~ 175) 168

 5415 23:02:50.341944  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5416 23:02:50.345297  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5417 23:02:50.352027  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5418 23:02:50.355387  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5419 23:02:50.355486  ==

 5420 23:02:50.358431  Dram Type= 6, Freq= 0, CH_0, rank 1

 5421 23:02:50.361849  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5422 23:02:50.361936  ==

 5423 23:02:50.364914  DQS Delay:

 5424 23:02:50.365025  DQS0 = 0, DQS1 = 0

 5425 23:02:50.365112  DQM Delay:

 5426 23:02:50.368469  DQM0 = 104, DQM1 = 95

 5427 23:02:50.368579  DQ Delay:

 5428 23:02:50.371808  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5429 23:02:50.375213  DQ4 =107, DQ5 =99, DQ6 =107, DQ7 =115

 5430 23:02:50.378264  DQ8 =87, DQ9 =91, DQ10 =95, DQ11 =91

 5431 23:02:50.381742  DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =99

 5432 23:02:50.381854  

 5433 23:02:50.381947  

 5434 23:02:50.382036  ==

 5435 23:02:50.384767  Dram Type= 6, Freq= 0, CH_0, rank 1

 5436 23:02:50.391484  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5437 23:02:50.391579  ==

 5438 23:02:50.391665  

 5439 23:02:50.391744  

 5440 23:02:50.394979  	TX Vref Scan disable

 5441 23:02:50.395073   == TX Byte 0 ==

 5442 23:02:50.397995  Update DQ  dly =719 (2 ,6, 15)  DQ  OEN =(2 ,3)

 5443 23:02:50.405162  Update DQM dly =719 (2 ,6, 15)  DQM OEN =(2 ,3)

 5444 23:02:50.405283   == TX Byte 1 ==

 5445 23:02:50.408044  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5446 23:02:50.414723  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5447 23:02:50.414842  ==

 5448 23:02:50.418197  Dram Type= 6, Freq= 0, CH_0, rank 1

 5449 23:02:50.421611  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5450 23:02:50.421718  ==

 5451 23:02:50.421811  

 5452 23:02:50.421899  

 5453 23:02:50.425128  	TX Vref Scan disable

 5454 23:02:50.428120   == TX Byte 0 ==

 5455 23:02:50.431805  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5456 23:02:50.435030  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5457 23:02:50.438365   == TX Byte 1 ==

 5458 23:02:50.441995  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5459 23:02:50.444545  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5460 23:02:50.444627  

 5461 23:02:50.444711  [DATLAT]

 5462 23:02:50.448221  Freq=933, CH0 RK1

 5463 23:02:50.448306  

 5464 23:02:50.451712  DATLAT Default: 0xb

 5465 23:02:50.451797  0, 0xFFFF, sum = 0

 5466 23:02:50.454556  1, 0xFFFF, sum = 0

 5467 23:02:50.454644  2, 0xFFFF, sum = 0

 5468 23:02:50.457951  3, 0xFFFF, sum = 0

 5469 23:02:50.458054  4, 0xFFFF, sum = 0

 5470 23:02:50.461209  5, 0xFFFF, sum = 0

 5471 23:02:50.461316  6, 0xFFFF, sum = 0

 5472 23:02:50.464866  7, 0xFFFF, sum = 0

 5473 23:02:50.464979  8, 0xFFFF, sum = 0

 5474 23:02:50.467891  9, 0xFFFF, sum = 0

 5475 23:02:50.467978  10, 0x0, sum = 1

 5476 23:02:50.471405  11, 0x0, sum = 2

 5477 23:02:50.471523  12, 0x0, sum = 3

 5478 23:02:50.474392  13, 0x0, sum = 4

 5479 23:02:50.474509  best_step = 11

 5480 23:02:50.474583  

 5481 23:02:50.474645  ==

 5482 23:02:50.477805  Dram Type= 6, Freq= 0, CH_0, rank 1

 5483 23:02:50.481382  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5484 23:02:50.481493  ==

 5485 23:02:50.485049  RX Vref Scan: 0

 5486 23:02:50.485134  

 5487 23:02:50.487998  RX Vref 0 -> 0, step: 1

 5488 23:02:50.488099  

 5489 23:02:50.488193  RX Delay -45 -> 252, step: 4

 5490 23:02:50.495844  iDelay=199, Bit 0, Center 100 (11 ~ 190) 180

 5491 23:02:50.498837  iDelay=199, Bit 1, Center 108 (23 ~ 194) 172

 5492 23:02:50.502411  iDelay=199, Bit 2, Center 102 (15 ~ 190) 176

 5493 23:02:50.506026  iDelay=199, Bit 3, Center 102 (15 ~ 190) 176

 5494 23:02:50.509019  iDelay=199, Bit 4, Center 106 (19 ~ 194) 176

 5495 23:02:50.515503  iDelay=199, Bit 5, Center 98 (11 ~ 186) 176

 5496 23:02:50.519108  iDelay=199, Bit 6, Center 110 (27 ~ 194) 168

 5497 23:02:50.522209  iDelay=199, Bit 7, Center 112 (27 ~ 198) 172

 5498 23:02:50.525862  iDelay=199, Bit 8, Center 86 (3 ~ 170) 168

 5499 23:02:50.529518  iDelay=199, Bit 9, Center 84 (-1 ~ 170) 172

 5500 23:02:50.535944  iDelay=199, Bit 10, Center 94 (11 ~ 178) 168

 5501 23:02:50.538931  iDelay=199, Bit 11, Center 88 (7 ~ 170) 164

 5502 23:02:50.542429  iDelay=199, Bit 12, Center 100 (19 ~ 182) 164

 5503 23:02:50.545514  iDelay=199, Bit 13, Center 98 (15 ~ 182) 168

 5504 23:02:50.548966  iDelay=199, Bit 14, Center 104 (23 ~ 186) 164

 5505 23:02:50.555524  iDelay=199, Bit 15, Center 100 (15 ~ 186) 172

 5506 23:02:50.555626  ==

 5507 23:02:50.559117  Dram Type= 6, Freq= 0, CH_0, rank 1

 5508 23:02:50.561939  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5509 23:02:50.562055  ==

 5510 23:02:50.562156  DQS Delay:

 5511 23:02:50.565451  DQS0 = 0, DQS1 = 0

 5512 23:02:50.565555  DQM Delay:

 5513 23:02:50.568519  DQM0 = 104, DQM1 = 94

 5514 23:02:50.568624  DQ Delay:

 5515 23:02:50.571612  DQ0 =100, DQ1 =108, DQ2 =102, DQ3 =102

 5516 23:02:50.574999  DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112

 5517 23:02:50.578340  DQ8 =86, DQ9 =84, DQ10 =94, DQ11 =88

 5518 23:02:50.582163  DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =100

 5519 23:02:50.582286  

 5520 23:02:50.582386  

 5521 23:02:50.591745  [DQSOSCAuto] RK1, (LSB)MR18= 0x26fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps

 5522 23:02:50.595140  CH0 RK1: MR19=504, MR18=26FE

 5523 23:02:50.598273  CH0_RK1: MR19=0x504, MR18=0x26FE, DQSOSC=409, MR23=63, INC=64, DEC=43

 5524 23:02:50.601538  [RxdqsGatingPostProcess] freq 933

 5525 23:02:50.608356  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5526 23:02:50.611506  best DQS0 dly(2T, 0.5T) = (0, 10)

 5527 23:02:50.615045  best DQS1 dly(2T, 0.5T) = (0, 11)

 5528 23:02:50.618682  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5529 23:02:50.621645  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5530 23:02:50.625477  best DQS0 dly(2T, 0.5T) = (0, 10)

 5531 23:02:50.628474  best DQS1 dly(2T, 0.5T) = (0, 10)

 5532 23:02:50.632059  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5533 23:02:50.632172  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5534 23:02:50.635008  Pre-setting of DQS Precalculation

 5535 23:02:50.642098  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5536 23:02:50.642215  ==

 5537 23:02:50.645172  Dram Type= 6, Freq= 0, CH_1, rank 0

 5538 23:02:50.648599  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5539 23:02:50.648706  ==

 5540 23:02:50.655416  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5541 23:02:50.661724  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5542 23:02:50.665259  [CA 0] Center 36 (6~67) winsize 62

 5543 23:02:50.668343  [CA 1] Center 37 (6~68) winsize 63

 5544 23:02:50.671701  [CA 2] Center 34 (4~65) winsize 62

 5545 23:02:50.675405  [CA 3] Center 34 (4~65) winsize 62

 5546 23:02:50.678310  [CA 4] Center 34 (4~64) winsize 61

 5547 23:02:50.681668  [CA 5] Center 33 (3~64) winsize 62

 5548 23:02:50.681752  

 5549 23:02:50.685186  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5550 23:02:50.685292  

 5551 23:02:50.688516  [CATrainingPosCal] consider 1 rank data

 5552 23:02:50.691558  u2DelayCellTimex100 = 270/100 ps

 5553 23:02:50.695186  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5554 23:02:50.698157  CA1 delay=37 (6~68),Diff = 4 PI (24 cell)

 5555 23:02:50.701891  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5556 23:02:50.704819  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5557 23:02:50.707975  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5558 23:02:50.711393  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5559 23:02:50.711490  

 5560 23:02:50.718135  CA PerBit enable=1, Macro0, CA PI delay=33

 5561 23:02:50.718248  

 5562 23:02:50.718342  [CBTSetCACLKResult] CA Dly = 33

 5563 23:02:50.721537  CS Dly: 6 (0~37)

 5564 23:02:50.721663  ==

 5565 23:02:50.725346  Dram Type= 6, Freq= 0, CH_1, rank 1

 5566 23:02:50.728440  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5567 23:02:50.728555  ==

 5568 23:02:50.735038  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5569 23:02:50.741471  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5570 23:02:50.744605  [CA 0] Center 36 (6~67) winsize 62

 5571 23:02:50.748313  [CA 1] Center 37 (7~68) winsize 62

 5572 23:02:50.751153  [CA 2] Center 35 (5~65) winsize 61

 5573 23:02:50.754711  [CA 3] Center 34 (4~65) winsize 62

 5574 23:02:50.758249  [CA 4] Center 34 (4~65) winsize 62

 5575 23:02:50.761241  [CA 5] Center 33 (3~64) winsize 62

 5576 23:02:50.761349  

 5577 23:02:50.764836  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5578 23:02:50.764932  

 5579 23:02:50.767899  [CATrainingPosCal] consider 2 rank data

 5580 23:02:50.771693  u2DelayCellTimex100 = 270/100 ps

 5581 23:02:50.774632  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5582 23:02:50.777980  CA1 delay=37 (7~68),Diff = 4 PI (24 cell)

 5583 23:02:50.781030  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5584 23:02:50.784710  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5585 23:02:50.787642  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5586 23:02:50.791136  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5587 23:02:50.794497  

 5588 23:02:50.797984  CA PerBit enable=1, Macro0, CA PI delay=33

 5589 23:02:50.798116  

 5590 23:02:50.801404  [CBTSetCACLKResult] CA Dly = 33

 5591 23:02:50.801521  CS Dly: 7 (0~40)

 5592 23:02:50.801624  

 5593 23:02:50.804816  ----->DramcWriteLeveling(PI) begin...

 5594 23:02:50.804929  ==

 5595 23:02:50.807556  Dram Type= 6, Freq= 0, CH_1, rank 0

 5596 23:02:50.811086  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5597 23:02:50.814669  ==

 5598 23:02:50.814786  Write leveling (Byte 0): 28 => 28

 5599 23:02:50.817815  Write leveling (Byte 1): 28 => 28

 5600 23:02:50.821127  DramcWriteLeveling(PI) end<-----

 5601 23:02:50.821237  

 5602 23:02:50.821332  ==

 5603 23:02:50.824550  Dram Type= 6, Freq= 0, CH_1, rank 0

 5604 23:02:50.831179  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5605 23:02:50.831304  ==

 5606 23:02:50.831401  [Gating] SW mode calibration

 5607 23:02:50.841347  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5608 23:02:50.844365  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5609 23:02:50.847740   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5610 23:02:50.854257   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5611 23:02:50.857843   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5612 23:02:50.860769   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5613 23:02:50.867841   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5614 23:02:50.870706   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5615 23:02:50.874392   0 14 24 | B1->B0 | 3434 2f2f | 0 0 | (0 1) (0 1)

 5616 23:02:50.880985   0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)

 5617 23:02:50.884621   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5618 23:02:50.887536   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5619 23:02:50.894088   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5620 23:02:50.897607   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5621 23:02:50.900566   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5622 23:02:50.907419   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5623 23:02:50.910683   0 15 24 | B1->B0 | 2727 3130 | 0 1 | (0 0) (1 1)

 5624 23:02:50.914142   0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)

 5625 23:02:50.920505   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5626 23:02:50.924022   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5627 23:02:50.927732   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5628 23:02:50.934056   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5629 23:02:50.937672   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5630 23:02:50.940577   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5631 23:02:50.947709   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5632 23:02:50.950703   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5633 23:02:50.953979   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5634 23:02:50.960636   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5635 23:02:50.964128   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5636 23:02:50.967710   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5637 23:02:50.970736   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5638 23:02:50.977704   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5639 23:02:50.980651   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5640 23:02:50.984481   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5641 23:02:50.990772   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5642 23:02:50.994401   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5643 23:02:50.997829   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5644 23:02:51.004645   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5645 23:02:51.007661   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5646 23:02:51.011078   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5647 23:02:51.017542   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5648 23:02:51.020617   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5649 23:02:51.024141  Total UI for P1: 0, mck2ui 16

 5650 23:02:51.027723  best dqsien dly found for B0: ( 1,  2, 22)

 5651 23:02:51.030984  Total UI for P1: 0, mck2ui 16

 5652 23:02:51.034331  best dqsien dly found for B1: ( 1,  2, 22)

 5653 23:02:51.037169  best DQS0 dly(MCK, UI, PI) = (1, 2, 22)

 5654 23:02:51.040915  best DQS1 dly(MCK, UI, PI) = (1, 2, 22)

 5655 23:02:51.041027  

 5656 23:02:51.044018  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5657 23:02:51.047233  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)

 5658 23:02:51.050662  [Gating] SW calibration Done

 5659 23:02:51.050777  ==

 5660 23:02:51.054143  Dram Type= 6, Freq= 0, CH_1, rank 0

 5661 23:02:51.057544  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5662 23:02:51.060307  ==

 5663 23:02:51.060414  RX Vref Scan: 0

 5664 23:02:51.060504  

 5665 23:02:51.064017  RX Vref 0 -> 0, step: 1

 5666 23:02:51.064125  

 5667 23:02:51.067741  RX Delay -80 -> 252, step: 8

 5668 23:02:51.070311  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5669 23:02:51.073866  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5670 23:02:51.077337  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5671 23:02:51.080310  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5672 23:02:51.083792  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5673 23:02:51.090322  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5674 23:02:51.094067  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5675 23:02:51.097341  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5676 23:02:51.100399  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5677 23:02:51.103444  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5678 23:02:51.107140  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5679 23:02:51.113729  iDelay=208, Bit 11, Center 95 (8 ~ 183) 176

 5680 23:02:51.116704  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5681 23:02:51.120125  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5682 23:02:51.123751  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5683 23:02:51.127198  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5684 23:02:51.130201  ==

 5685 23:02:51.130308  Dram Type= 6, Freq= 0, CH_1, rank 0

 5686 23:02:51.136700  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5687 23:02:51.136815  ==

 5688 23:02:51.136910  DQS Delay:

 5689 23:02:51.140169  DQS0 = 0, DQS1 = 0

 5690 23:02:51.140281  DQM Delay:

 5691 23:02:51.143745  DQM0 = 103, DQM1 = 98

 5692 23:02:51.143847  DQ Delay:

 5693 23:02:51.146760  DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99

 5694 23:02:51.150343  DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103

 5695 23:02:51.153691  DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95

 5696 23:02:51.156567  DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107

 5697 23:02:51.156675  

 5698 23:02:51.156767  

 5699 23:02:51.156860  ==

 5700 23:02:51.160144  Dram Type= 6, Freq= 0, CH_1, rank 0

 5701 23:02:51.163363  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5702 23:02:51.163451  ==

 5703 23:02:51.166612  

 5704 23:02:51.166697  

 5705 23:02:51.166763  	TX Vref Scan disable

 5706 23:02:51.170168   == TX Byte 0 ==

 5707 23:02:51.173589  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5708 23:02:51.176618  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5709 23:02:51.179789   == TX Byte 1 ==

 5710 23:02:51.183353  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5711 23:02:51.186590  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5712 23:02:51.186675  ==

 5713 23:02:51.189917  Dram Type= 6, Freq= 0, CH_1, rank 0

 5714 23:02:51.196245  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5715 23:02:51.196343  ==

 5716 23:02:51.196411  

 5717 23:02:51.196472  

 5718 23:02:51.196533  	TX Vref Scan disable

 5719 23:02:51.201107   == TX Byte 0 ==

 5720 23:02:51.204599  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5721 23:02:51.207429  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5722 23:02:51.210986   == TX Byte 1 ==

 5723 23:02:51.214083  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5724 23:02:51.217672  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5725 23:02:51.220872  

 5726 23:02:51.220951  [DATLAT]

 5727 23:02:51.221014  Freq=933, CH1 RK0

 5728 23:02:51.221074  

 5729 23:02:51.223863  DATLAT Default: 0xd

 5730 23:02:51.223943  0, 0xFFFF, sum = 0

 5731 23:02:51.227355  1, 0xFFFF, sum = 0

 5732 23:02:51.227435  2, 0xFFFF, sum = 0

 5733 23:02:51.231062  3, 0xFFFF, sum = 0

 5734 23:02:51.233946  4, 0xFFFF, sum = 0

 5735 23:02:51.234031  5, 0xFFFF, sum = 0

 5736 23:02:51.237709  6, 0xFFFF, sum = 0

 5737 23:02:51.237797  7, 0xFFFF, sum = 0

 5738 23:02:51.240489  8, 0xFFFF, sum = 0

 5739 23:02:51.240602  9, 0xFFFF, sum = 0

 5740 23:02:51.244035  10, 0x0, sum = 1

 5741 23:02:51.244119  11, 0x0, sum = 2

 5742 23:02:51.247601  12, 0x0, sum = 3

 5743 23:02:51.247680  13, 0x0, sum = 4

 5744 23:02:51.247742  best_step = 11

 5745 23:02:51.247803  

 5746 23:02:51.250487  ==

 5747 23:02:51.254049  Dram Type= 6, Freq= 0, CH_1, rank 0

 5748 23:02:51.257331  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5749 23:02:51.257409  ==

 5750 23:02:51.257472  RX Vref Scan: 1

 5751 23:02:51.257532  

 5752 23:02:51.260977  RX Vref 0 -> 0, step: 1

 5753 23:02:51.261054  

 5754 23:02:51.263753  RX Delay -45 -> 252, step: 4

 5755 23:02:51.263829  

 5756 23:02:51.267478  Set Vref, RX VrefLevel [Byte0]: 52

 5757 23:02:51.270368                           [Byte1]: 46

 5758 23:02:51.270452  

 5759 23:02:51.273607  Final RX Vref Byte 0 = 52 to rank0

 5760 23:02:51.277471  Final RX Vref Byte 1 = 46 to rank0

 5761 23:02:51.280865  Final RX Vref Byte 0 = 52 to rank1

 5762 23:02:51.283508  Final RX Vref Byte 1 = 46 to rank1==

 5763 23:02:51.287016  Dram Type= 6, Freq= 0, CH_1, rank 0

 5764 23:02:51.290554  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5765 23:02:51.290639  ==

 5766 23:02:51.293436  DQS Delay:

 5767 23:02:51.293511  DQS0 = 0, DQS1 = 0

 5768 23:02:51.297062  DQM Delay:

 5769 23:02:51.297138  DQM0 = 103, DQM1 = 98

 5770 23:02:51.300439  DQ Delay:

 5771 23:02:51.300523  DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =100

 5772 23:02:51.307019  DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102

 5773 23:02:51.310103  DQ8 =86, DQ9 =88, DQ10 =98, DQ11 =92

 5774 23:02:51.313628  DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =108

 5775 23:02:51.313709  

 5776 23:02:51.313773  

 5777 23:02:51.319992  [DQSOSCAuto] RK0, (LSB)MR18= 0x1931, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps

 5778 23:02:51.323743  CH1 RK0: MR19=505, MR18=1931

 5779 23:02:51.330179  CH1_RK0: MR19=0x505, MR18=0x1931, DQSOSC=406, MR23=63, INC=65, DEC=43

 5780 23:02:51.330262  

 5781 23:02:51.333802  ----->DramcWriteLeveling(PI) begin...

 5782 23:02:51.333879  ==

 5783 23:02:51.336735  Dram Type= 6, Freq= 0, CH_1, rank 1

 5784 23:02:51.340270  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5785 23:02:51.340355  ==

 5786 23:02:51.343216  Write leveling (Byte 0): 29 => 29

 5787 23:02:51.346725  Write leveling (Byte 1): 30 => 30

 5788 23:02:51.349693  DramcWriteLeveling(PI) end<-----

 5789 23:02:51.349778  

 5790 23:02:51.349844  ==

 5791 23:02:51.353360  Dram Type= 6, Freq= 0, CH_1, rank 1

 5792 23:02:51.356320  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5793 23:02:51.359858  ==

 5794 23:02:51.359961  [Gating] SW mode calibration

 5795 23:02:51.366502  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5796 23:02:51.373103  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5797 23:02:51.376750   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5798 23:02:51.383222   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5799 23:02:51.386480   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5800 23:02:51.390107   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5801 23:02:51.396716   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5802 23:02:51.400287   0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5803 23:02:51.403143   0 14 24 | B1->B0 | 2e2e 3232 | 0 0 | (0 1) (1 0)

 5804 23:02:51.409945   0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 5805 23:02:51.413458   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5806 23:02:51.416738   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5807 23:02:51.423201   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5808 23:02:51.426793   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5809 23:02:51.429805   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5810 23:02:51.436430   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5811 23:02:51.439493   0 15 24 | B1->B0 | 3333 2525 | 1 0 | (0 0) (0 0)

 5812 23:02:51.442870   0 15 28 | B1->B0 | 4646 3e3e | 0 0 | (0 0) (0 0)

 5813 23:02:51.449872   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5814 23:02:51.452704   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5815 23:02:51.456394   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5816 23:02:51.459362   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5817 23:02:51.466120   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5818 23:02:51.469478   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5819 23:02:51.473082   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5820 23:02:51.479572   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5821 23:02:51.483193   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5822 23:02:51.486165   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5823 23:02:51.492747   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5824 23:02:51.496244   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5825 23:02:51.499244   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5826 23:02:51.506357   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5827 23:02:51.509380   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5828 23:02:51.512715   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5829 23:02:51.519420   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5830 23:02:51.522463   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5831 23:02:51.525933   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5832 23:02:51.533026   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5833 23:02:51.535932   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5834 23:02:51.539264   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5835 23:02:51.545954   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5836 23:02:51.549256   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5837 23:02:51.552746   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5838 23:02:51.555889  Total UI for P1: 0, mck2ui 16

 5839 23:02:51.559072  best dqsien dly found for B0: ( 1,  2, 26)

 5840 23:02:51.562221  Total UI for P1: 0, mck2ui 16

 5841 23:02:51.565991  best dqsien dly found for B1: ( 1,  2, 26)

 5842 23:02:51.569076  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5843 23:02:51.572346  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5844 23:02:51.572433  

 5845 23:02:51.575985  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5846 23:02:51.582683  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5847 23:02:51.582770  [Gating] SW calibration Done

 5848 23:02:51.582844  ==

 5849 23:02:51.585929  Dram Type= 6, Freq= 0, CH_1, rank 1

 5850 23:02:51.592254  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5851 23:02:51.592360  ==

 5852 23:02:51.592453  RX Vref Scan: 0

 5853 23:02:51.592556  

 5854 23:02:51.595810  RX Vref 0 -> 0, step: 1

 5855 23:02:51.595910  

 5856 23:02:51.598829  RX Delay -80 -> 252, step: 8

 5857 23:02:51.602374  iDelay=208, Bit 0, Center 111 (24 ~ 199) 176

 5858 23:02:51.605870  iDelay=208, Bit 1, Center 99 (8 ~ 191) 184

 5859 23:02:51.608694  iDelay=208, Bit 2, Center 87 (0 ~ 175) 176

 5860 23:02:51.612341  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5861 23:02:51.618771  iDelay=208, Bit 4, Center 95 (8 ~ 183) 176

 5862 23:02:51.622150  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5863 23:02:51.625711  iDelay=208, Bit 6, Center 111 (24 ~ 199) 176

 5864 23:02:51.629166  iDelay=208, Bit 7, Center 99 (8 ~ 191) 184

 5865 23:02:51.632006  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5866 23:02:51.635478  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5867 23:02:51.642021  iDelay=208, Bit 10, Center 103 (16 ~ 191) 176

 5868 23:02:51.645490  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5869 23:02:51.648531  iDelay=208, Bit 12, Center 103 (8 ~ 199) 192

 5870 23:02:51.652112  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5871 23:02:51.658352  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5872 23:02:51.661818  iDelay=208, Bit 15, Center 107 (24 ~ 191) 168

 5873 23:02:51.661906  ==

 5874 23:02:51.665199  Dram Type= 6, Freq= 0, CH_1, rank 1

 5875 23:02:51.668782  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5876 23:02:51.668867  ==

 5877 23:02:51.668941  DQS Delay:

 5878 23:02:51.671670  DQS0 = 0, DQS1 = 0

 5879 23:02:51.671754  DQM Delay:

 5880 23:02:51.675058  DQM0 = 102, DQM1 = 97

 5881 23:02:51.675138  DQ Delay:

 5882 23:02:51.678290  DQ0 =111, DQ1 =99, DQ2 =87, DQ3 =99

 5883 23:02:51.681803  DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99

 5884 23:02:51.685319  DQ8 =83, DQ9 =87, DQ10 =103, DQ11 =91

 5885 23:02:51.688369  DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107

 5886 23:02:51.688444  

 5887 23:02:51.688507  

 5888 23:02:51.688566  ==

 5889 23:02:51.691529  Dram Type= 6, Freq= 0, CH_1, rank 1

 5890 23:02:51.698671  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5891 23:02:51.698755  ==

 5892 23:02:51.698820  

 5893 23:02:51.698884  

 5894 23:02:51.701516  	TX Vref Scan disable

 5895 23:02:51.701631   == TX Byte 0 ==

 5896 23:02:51.705119  Update DQ  dly =713 (2 ,5, 41)  DQ  OEN =(2 ,2)

 5897 23:02:51.711429  Update DQM dly =713 (2 ,5, 41)  DQM OEN =(2 ,2)

 5898 23:02:51.711540   == TX Byte 1 ==

 5899 23:02:51.714865  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5900 23:02:51.721428  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5901 23:02:51.721532  ==

 5902 23:02:51.724915  Dram Type= 6, Freq= 0, CH_1, rank 1

 5903 23:02:51.728198  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5904 23:02:51.728304  ==

 5905 23:02:51.728396  

 5906 23:02:51.728484  

 5907 23:02:51.731542  	TX Vref Scan disable

 5908 23:02:51.734967   == TX Byte 0 ==

 5909 23:02:51.737854  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5910 23:02:51.741483  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5911 23:02:51.744479   == TX Byte 1 ==

 5912 23:02:51.748328  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5913 23:02:51.751453  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5914 23:02:51.751556  

 5915 23:02:51.751648  [DATLAT]

 5916 23:02:51.754678  Freq=933, CH1 RK1

 5917 23:02:51.754754  

 5918 23:02:51.758021  DATLAT Default: 0xb

 5919 23:02:51.758124  0, 0xFFFF, sum = 0

 5920 23:02:51.761138  1, 0xFFFF, sum = 0

 5921 23:02:51.761240  2, 0xFFFF, sum = 0

 5922 23:02:51.764634  3, 0xFFFF, sum = 0

 5923 23:02:51.764741  4, 0xFFFF, sum = 0

 5924 23:02:51.768109  5, 0xFFFF, sum = 0

 5925 23:02:51.768215  6, 0xFFFF, sum = 0

 5926 23:02:51.771234  7, 0xFFFF, sum = 0

 5927 23:02:51.771335  8, 0xFFFF, sum = 0

 5928 23:02:51.774638  9, 0xFFFF, sum = 0

 5929 23:02:51.774713  10, 0x0, sum = 1

 5930 23:02:51.777607  11, 0x0, sum = 2

 5931 23:02:51.777681  12, 0x0, sum = 3

 5932 23:02:51.781227  13, 0x0, sum = 4

 5933 23:02:51.781330  best_step = 11

 5934 23:02:51.781419  

 5935 23:02:51.781505  ==

 5936 23:02:51.784688  Dram Type= 6, Freq= 0, CH_1, rank 1

 5937 23:02:51.788105  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5938 23:02:51.788207  ==

 5939 23:02:51.791513  RX Vref Scan: 0

 5940 23:02:51.791621  

 5941 23:02:51.794738  RX Vref 0 -> 0, step: 1

 5942 23:02:51.794844  

 5943 23:02:51.794951  RX Delay -53 -> 252, step: 4

 5944 23:02:51.802924  iDelay=203, Bit 0, Center 108 (27 ~ 190) 164

 5945 23:02:51.805948  iDelay=203, Bit 1, Center 100 (19 ~ 182) 164

 5946 23:02:51.809038  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5947 23:02:51.812902  iDelay=203, Bit 3, Center 100 (19 ~ 182) 164

 5948 23:02:51.815745  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5949 23:02:51.822274  iDelay=203, Bit 5, Center 118 (35 ~ 202) 168

 5950 23:02:51.825922  iDelay=203, Bit 6, Center 114 (31 ~ 198) 168

 5951 23:02:51.829277  iDelay=203, Bit 7, Center 102 (19 ~ 186) 168

 5952 23:02:51.832666  iDelay=203, Bit 8, Center 90 (7 ~ 174) 168

 5953 23:02:51.836118  iDelay=203, Bit 9, Center 88 (3 ~ 174) 172

 5954 23:02:51.842279  iDelay=203, Bit 10, Center 100 (15 ~ 186) 172

 5955 23:02:51.845776  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5956 23:02:51.849141  iDelay=203, Bit 12, Center 106 (19 ~ 194) 176

 5957 23:02:51.852737  iDelay=203, Bit 13, Center 102 (19 ~ 186) 168

 5958 23:02:51.855717  iDelay=203, Bit 14, Center 102 (19 ~ 186) 168

 5959 23:02:51.862536  iDelay=203, Bit 15, Center 108 (23 ~ 194) 172

 5960 23:02:51.862686  ==

 5961 23:02:51.865549  Dram Type= 6, Freq= 0, CH_1, rank 1

 5962 23:02:51.868999  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5963 23:02:51.869116  ==

 5964 23:02:51.869212  DQS Delay:

 5965 23:02:51.872188  DQS0 = 0, DQS1 = 0

 5966 23:02:51.872293  DQM Delay:

 5967 23:02:51.875801  DQM0 = 104, DQM1 = 98

 5968 23:02:51.875906  DQ Delay:

 5969 23:02:51.878855  DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100

 5970 23:02:51.882488  DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102

 5971 23:02:51.885403  DQ8 =90, DQ9 =88, DQ10 =100, DQ11 =94

 5972 23:02:51.889094  DQ12 =106, DQ13 =102, DQ14 =102, DQ15 =108

 5973 23:02:51.889182  

 5974 23:02:51.889246  

 5975 23:02:51.898726  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d01, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps

 5976 23:02:51.902170  CH1 RK1: MR19=505, MR18=2D01

 5977 23:02:51.905302  CH1_RK1: MR19=0x505, MR18=0x2D01, DQSOSC=407, MR23=63, INC=65, DEC=43

 5978 23:02:51.908634  [RxdqsGatingPostProcess] freq 933

 5979 23:02:51.915914  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5980 23:02:51.919237  best DQS0 dly(2T, 0.5T) = (0, 10)

 5981 23:02:51.922456  best DQS1 dly(2T, 0.5T) = (0, 10)

 5982 23:02:51.925606  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5983 23:02:51.928650  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5984 23:02:51.931981  best DQS0 dly(2T, 0.5T) = (0, 10)

 5985 23:02:51.935245  best DQS1 dly(2T, 0.5T) = (0, 10)

 5986 23:02:51.939080  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5987 23:02:51.941885  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5988 23:02:51.941966  Pre-setting of DQS Precalculation

 5989 23:02:51.948717  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5990 23:02:51.955642  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5991 23:02:51.962104  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5992 23:02:51.962244  

 5993 23:02:51.962435  

 5994 23:02:51.965073  [Calibration Summary] 1866 Mbps

 5995 23:02:51.968554  CH 0, Rank 0

 5996 23:02:51.968696  SW Impedance     : PASS

 5997 23:02:51.971720  DUTY Scan        : NO K

 5998 23:02:51.975109  ZQ Calibration   : PASS

 5999 23:02:51.975219  Jitter Meter     : NO K

 6000 23:02:51.978773  CBT Training     : PASS

 6001 23:02:51.981627  Write leveling   : PASS

 6002 23:02:51.981742  RX DQS gating    : PASS

 6003 23:02:51.985316  RX DQ/DQS(RDDQC) : PASS

 6004 23:02:51.985442  TX DQ/DQS        : PASS

 6005 23:02:51.989017  RX DATLAT        : PASS

 6006 23:02:51.991938  RX DQ/DQS(Engine): PASS

 6007 23:02:51.992037  TX OE            : NO K

 6008 23:02:51.995145  All Pass.

 6009 23:02:51.995241  

 6010 23:02:51.995333  CH 0, Rank 1

 6011 23:02:51.998291  SW Impedance     : PASS

 6012 23:02:51.998363  DUTY Scan        : NO K

 6013 23:02:52.001917  ZQ Calibration   : PASS

 6014 23:02:52.005301  Jitter Meter     : NO K

 6015 23:02:52.005406  CBT Training     : PASS

 6016 23:02:52.008242  Write leveling   : PASS

 6017 23:02:52.011799  RX DQS gating    : PASS

 6018 23:02:52.011878  RX DQ/DQS(RDDQC) : PASS

 6019 23:02:52.015588  TX DQ/DQS        : PASS

 6020 23:02:52.018175  RX DATLAT        : PASS

 6021 23:02:52.018251  RX DQ/DQS(Engine): PASS

 6022 23:02:52.021721  TX OE            : NO K

 6023 23:02:52.021793  All Pass.

 6024 23:02:52.021859  

 6025 23:02:52.025479  CH 1, Rank 0

 6026 23:02:52.025585  SW Impedance     : PASS

 6027 23:02:52.028427  DUTY Scan        : NO K

 6028 23:02:52.032084  ZQ Calibration   : PASS

 6029 23:02:52.032184  Jitter Meter     : NO K

 6030 23:02:52.034868  CBT Training     : PASS

 6031 23:02:52.038256  Write leveling   : PASS

 6032 23:02:52.038332  RX DQS gating    : PASS

 6033 23:02:52.041399  RX DQ/DQS(RDDQC) : PASS

 6034 23:02:52.041502  TX DQ/DQS        : PASS

 6035 23:02:52.044727  RX DATLAT        : PASS

 6036 23:02:52.048395  RX DQ/DQS(Engine): PASS

 6037 23:02:52.048473  TX OE            : NO K

 6038 23:02:52.051949  All Pass.

 6039 23:02:52.052024  

 6040 23:02:52.052090  CH 1, Rank 1

 6041 23:02:52.054978  SW Impedance     : PASS

 6042 23:02:52.055082  DUTY Scan        : NO K

 6043 23:02:52.058078  ZQ Calibration   : PASS

 6044 23:02:52.061494  Jitter Meter     : NO K

 6045 23:02:52.061613  CBT Training     : PASS

 6046 23:02:52.064741  Write leveling   : PASS

 6047 23:02:52.068373  RX DQS gating    : PASS

 6048 23:02:52.068458  RX DQ/DQS(RDDQC) : PASS

 6049 23:02:52.071596  TX DQ/DQS        : PASS

 6050 23:02:52.075143  RX DATLAT        : PASS

 6051 23:02:52.075258  RX DQ/DQS(Engine): PASS

 6052 23:02:52.077965  TX OE            : NO K

 6053 23:02:52.078045  All Pass.

 6054 23:02:52.078128  

 6055 23:02:52.081504  DramC Write-DBI off

 6056 23:02:52.085237  	PER_BANK_REFRESH: Hybrid Mode

 6057 23:02:52.085349  TX_TRACKING: ON

 6058 23:02:52.094690  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6059 23:02:52.098467  [FAST_K] Save calibration result to emmc

 6060 23:02:52.101307  dramc_set_vcore_voltage set vcore to 650000

 6061 23:02:52.104736  Read voltage for 400, 6

 6062 23:02:52.104848  Vio18 = 0

 6063 23:02:52.104946  Vcore = 650000

 6064 23:02:52.107730  Vdram = 0

 6065 23:02:52.107840  Vddq = 0

 6066 23:02:52.107934  Vmddr = 0

 6067 23:02:52.114693  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6068 23:02:52.118182  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6069 23:02:52.121153  MEM_TYPE=3, freq_sel=20

 6070 23:02:52.124866  sv_algorithm_assistance_LP4_800 

 6071 23:02:52.127832  ============ PULL DRAM RESETB DOWN ============

 6072 23:02:52.131361  ========== PULL DRAM RESETB DOWN end =========

 6073 23:02:52.138114  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6074 23:02:52.141131  =================================== 

 6075 23:02:52.141236  LPDDR4 DRAM CONFIGURATION

 6076 23:02:52.144685  =================================== 

 6077 23:02:52.147890  EX_ROW_EN[0]    = 0x0

 6078 23:02:52.151413  EX_ROW_EN[1]    = 0x0

 6079 23:02:52.151519  LP4Y_EN      = 0x0

 6080 23:02:52.154810  WORK_FSP     = 0x0

 6081 23:02:52.154912  WL           = 0x2

 6082 23:02:52.157780  RL           = 0x2

 6083 23:02:52.157881  BL           = 0x2

 6084 23:02:52.161412  RPST         = 0x0

 6085 23:02:52.161523  RD_PRE       = 0x0

 6086 23:02:52.164396  WR_PRE       = 0x1

 6087 23:02:52.164506  WR_PST       = 0x0

 6088 23:02:52.167751  DBI_WR       = 0x0

 6089 23:02:52.167862  DBI_RD       = 0x0

 6090 23:02:52.171314  OTF          = 0x1

 6091 23:02:52.174606  =================================== 

 6092 23:02:52.177946  =================================== 

 6093 23:02:52.178053  ANA top config

 6094 23:02:52.181216  =================================== 

 6095 23:02:52.184201  DLL_ASYNC_EN            =  0

 6096 23:02:52.187635  ALL_SLAVE_EN            =  1

 6097 23:02:52.187746  NEW_RANK_MODE           =  1

 6098 23:02:52.191267  DLL_IDLE_MODE           =  1

 6099 23:02:52.194751  LP45_APHY_COMB_EN       =  1

 6100 23:02:52.197934  TX_ODT_DIS              =  1

 6101 23:02:52.201093  NEW_8X_MODE             =  1

 6102 23:02:52.204495  =================================== 

 6103 23:02:52.208012  =================================== 

 6104 23:02:52.208119  data_rate                  =  800

 6105 23:02:52.211040  CKR                        = 1

 6106 23:02:52.214557  DQ_P2S_RATIO               = 4

 6107 23:02:52.217692  =================================== 

 6108 23:02:52.221043  CA_P2S_RATIO               = 4

 6109 23:02:52.224657  DQ_CA_OPEN                 = 0

 6110 23:02:52.227547  DQ_SEMI_OPEN               = 1

 6111 23:02:52.227649  CA_SEMI_OPEN               = 1

 6112 23:02:52.231087  CA_FULL_RATE               = 0

 6113 23:02:52.234594  DQ_CKDIV4_EN               = 0

 6114 23:02:52.237709  CA_CKDIV4_EN               = 1

 6115 23:02:52.240776  CA_PREDIV_EN               = 0

 6116 23:02:52.244365  PH8_DLY                    = 0

 6117 23:02:52.244476  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6118 23:02:52.247388  DQ_AAMCK_DIV               = 0

 6119 23:02:52.250866  CA_AAMCK_DIV               = 0

 6120 23:02:52.254500  CA_ADMCK_DIV               = 4

 6121 23:02:52.257909  DQ_TRACK_CA_EN             = 0

 6122 23:02:52.260749  CA_PICK                    = 800

 6123 23:02:52.260868  CA_MCKIO                   = 400

 6124 23:02:52.264108  MCKIO_SEMI                 = 400

 6125 23:02:52.267777  PLL_FREQ                   = 3016

 6126 23:02:52.271215  DQ_UI_PI_RATIO             = 32

 6127 23:02:52.274046  CA_UI_PI_RATIO             = 32

 6128 23:02:52.277651  =================================== 

 6129 23:02:52.280716  =================================== 

 6130 23:02:52.284347  memory_type:LPDDR4         

 6131 23:02:52.284451  GP_NUM     : 10       

 6132 23:02:52.287401  SRAM_EN    : 1       

 6133 23:02:52.291018  MD32_EN    : 0       

 6134 23:02:52.294072  =================================== 

 6135 23:02:52.294178  [ANA_INIT] >>>>>>>>>>>>>> 

 6136 23:02:52.297592  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6137 23:02:52.300884  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6138 23:02:52.304128  =================================== 

 6139 23:02:52.307413  data_rate = 800,PCW = 0X7400

 6140 23:02:52.310645  =================================== 

 6141 23:02:52.313855  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6142 23:02:52.320927  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6143 23:02:52.330491  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6144 23:02:52.333806  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6145 23:02:52.337373  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6146 23:02:52.344068  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6147 23:02:52.344179  [ANA_INIT] flow start 

 6148 23:02:52.347133  [ANA_INIT] PLL >>>>>>>> 

 6149 23:02:52.347214  [ANA_INIT] PLL <<<<<<<< 

 6150 23:02:52.350737  [ANA_INIT] MIDPI >>>>>>>> 

 6151 23:02:52.354294  [ANA_INIT] MIDPI <<<<<<<< 

 6152 23:02:52.357359  [ANA_INIT] DLL >>>>>>>> 

 6153 23:02:52.357476  [ANA_INIT] flow end 

 6154 23:02:52.360301  ============ LP4 DIFF to SE enter ============

 6155 23:02:52.367174  ============ LP4 DIFF to SE exit  ============

 6156 23:02:52.367306  [ANA_INIT] <<<<<<<<<<<<< 

 6157 23:02:52.370267  [Flow] Enable top DCM control >>>>> 

 6158 23:02:52.373997  [Flow] Enable top DCM control <<<<< 

 6159 23:02:52.376860  Enable DLL master slave shuffle 

 6160 23:02:52.383888  ============================================================== 

 6161 23:02:52.384000  Gating Mode config

 6162 23:02:52.390386  ============================================================== 

 6163 23:02:52.394063  Config description: 

 6164 23:02:52.403866  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6165 23:02:52.410578  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6166 23:02:52.413590  SELPH_MODE            0: By rank         1: By Phase 

 6167 23:02:52.420094  ============================================================== 

 6168 23:02:52.423746  GAT_TRACK_EN                 =  0

 6169 23:02:52.423830  RX_GATING_MODE               =  2

 6170 23:02:52.427132  RX_GATING_TRACK_MODE         =  2

 6171 23:02:52.430599  SELPH_MODE                   =  1

 6172 23:02:52.433492  PICG_EARLY_EN                =  1

 6173 23:02:52.436907  VALID_LAT_VALUE              =  1

 6174 23:02:52.443590  ============================================================== 

 6175 23:02:52.446900  Enter into Gating configuration >>>> 

 6176 23:02:52.450038  Exit from Gating configuration <<<< 

 6177 23:02:52.453395  Enter into  DVFS_PRE_config >>>>> 

 6178 23:02:52.463445  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6179 23:02:52.467165  Exit from  DVFS_PRE_config <<<<< 

 6180 23:02:52.469902  Enter into PICG configuration >>>> 

 6181 23:02:52.473296  Exit from PICG configuration <<<< 

 6182 23:02:52.476776  [RX_INPUT] configuration >>>>> 

 6183 23:02:52.480237  [RX_INPUT] configuration <<<<< 

 6184 23:02:52.483456  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6185 23:02:52.490400  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6186 23:02:52.496550  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6187 23:02:52.499952  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6188 23:02:52.506994  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6189 23:02:52.513389  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6190 23:02:52.516337  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6191 23:02:52.523362  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6192 23:02:52.526994  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6193 23:02:52.529818  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6194 23:02:52.533352  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6195 23:02:52.539782  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6196 23:02:52.543281  =================================== 

 6197 23:02:52.543364  LPDDR4 DRAM CONFIGURATION

 6198 23:02:52.546942  =================================== 

 6199 23:02:52.549898  EX_ROW_EN[0]    = 0x0

 6200 23:02:52.553230  EX_ROW_EN[1]    = 0x0

 6201 23:02:52.553338  LP4Y_EN      = 0x0

 6202 23:02:52.556506  WORK_FSP     = 0x0

 6203 23:02:52.556621  WL           = 0x2

 6204 23:02:52.559910  RL           = 0x2

 6205 23:02:52.560017  BL           = 0x2

 6206 23:02:52.563212  RPST         = 0x0

 6207 23:02:52.563317  RD_PRE       = 0x0

 6208 23:02:52.566277  WR_PRE       = 0x1

 6209 23:02:52.566385  WR_PST       = 0x0

 6210 23:02:52.569840  DBI_WR       = 0x0

 6211 23:02:52.569926  DBI_RD       = 0x0

 6212 23:02:52.573354  OTF          = 0x1

 6213 23:02:52.576247  =================================== 

 6214 23:02:52.580021  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6215 23:02:52.583002  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6216 23:02:52.589965  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6217 23:02:52.592931  =================================== 

 6218 23:02:52.593038  LPDDR4 DRAM CONFIGURATION

 6219 23:02:52.596585  =================================== 

 6220 23:02:52.599744  EX_ROW_EN[0]    = 0x10

 6221 23:02:52.599848  EX_ROW_EN[1]    = 0x0

 6222 23:02:52.603359  LP4Y_EN      = 0x0

 6223 23:02:52.606094  WORK_FSP     = 0x0

 6224 23:02:52.606185  WL           = 0x2

 6225 23:02:52.609700  RL           = 0x2

 6226 23:02:52.609799  BL           = 0x2

 6227 23:02:52.613237  RPST         = 0x0

 6228 23:02:52.613319  RD_PRE       = 0x0

 6229 23:02:52.616175  WR_PRE       = 0x1

 6230 23:02:52.616257  WR_PST       = 0x0

 6231 23:02:52.619709  DBI_WR       = 0x0

 6232 23:02:52.619823  DBI_RD       = 0x0

 6233 23:02:52.622705  OTF          = 0x1

 6234 23:02:52.626213  =================================== 

 6235 23:02:52.632812  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6236 23:02:52.636309  nWR fixed to 30

 6237 23:02:52.636429  [ModeRegInit_LP4] CH0 RK0

 6238 23:02:52.639829  [ModeRegInit_LP4] CH0 RK1

 6239 23:02:52.642828  [ModeRegInit_LP4] CH1 RK0

 6240 23:02:52.642936  [ModeRegInit_LP4] CH1 RK1

 6241 23:02:52.646508  match AC timing 19

 6242 23:02:52.649312  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6243 23:02:52.652965  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6244 23:02:52.659784  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6245 23:02:52.662727  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6246 23:02:52.669358  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6247 23:02:52.669531  ==

 6248 23:02:52.672710  Dram Type= 6, Freq= 0, CH_0, rank 0

 6249 23:02:52.675978  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6250 23:02:52.676128  ==

 6251 23:02:52.682811  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6252 23:02:52.686359  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6253 23:02:52.689279  [CA 0] Center 36 (8~64) winsize 57

 6254 23:02:52.692707  [CA 1] Center 36 (8~64) winsize 57

 6255 23:02:52.696298  [CA 2] Center 36 (8~64) winsize 57

 6256 23:02:52.699235  [CA 3] Center 36 (8~64) winsize 57

 6257 23:02:52.702676  [CA 4] Center 36 (8~64) winsize 57

 6258 23:02:52.706269  [CA 5] Center 36 (8~64) winsize 57

 6259 23:02:52.706437  

 6260 23:02:52.709310  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6261 23:02:52.709463  

 6262 23:02:52.712566  [CATrainingPosCal] consider 1 rank data

 6263 23:02:52.716141  u2DelayCellTimex100 = 270/100 ps

 6264 23:02:52.719618  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6265 23:02:52.722648  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6266 23:02:52.726204  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6267 23:02:52.732569  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6268 23:02:52.735757  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6269 23:02:52.739215  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6270 23:02:52.739349  

 6271 23:02:52.742902  CA PerBit enable=1, Macro0, CA PI delay=36

 6272 23:02:52.743039  

 6273 23:02:52.746264  [CBTSetCACLKResult] CA Dly = 36

 6274 23:02:52.746404  CS Dly: 1 (0~32)

 6275 23:02:52.746530  ==

 6276 23:02:52.749376  Dram Type= 6, Freq= 0, CH_0, rank 1

 6277 23:02:52.755963  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6278 23:02:52.756107  ==

 6279 23:02:52.759385  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6280 23:02:52.765949  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6281 23:02:52.769465  [CA 0] Center 36 (8~64) winsize 57

 6282 23:02:52.773010  [CA 1] Center 36 (8~64) winsize 57

 6283 23:02:52.775880  [CA 2] Center 36 (8~64) winsize 57

 6284 23:02:52.779456  [CA 3] Center 36 (8~64) winsize 57

 6285 23:02:52.782352  [CA 4] Center 36 (8~64) winsize 57

 6286 23:02:52.785801  [CA 5] Center 36 (8~64) winsize 57

 6287 23:02:52.785948  

 6288 23:02:52.789225  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6289 23:02:52.789373  

 6290 23:02:52.792627  [CATrainingPosCal] consider 2 rank data

 6291 23:02:52.796018  u2DelayCellTimex100 = 270/100 ps

 6292 23:02:52.799367  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6293 23:02:52.802294  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6294 23:02:52.805888  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6295 23:02:52.809174  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6296 23:02:52.812647  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6297 23:02:52.815524  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6298 23:02:52.815674  

 6299 23:02:52.822279  CA PerBit enable=1, Macro0, CA PI delay=36

 6300 23:02:52.822464  

 6301 23:02:52.825737  [CBTSetCACLKResult] CA Dly = 36

 6302 23:02:52.825876  CS Dly: 1 (0~32)

 6303 23:02:52.826003  

 6304 23:02:52.829175  ----->DramcWriteLeveling(PI) begin...

 6305 23:02:52.829311  ==

 6306 23:02:52.832142  Dram Type= 6, Freq= 0, CH_0, rank 0

 6307 23:02:52.835566  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6308 23:02:52.838764  ==

 6309 23:02:52.838843  Write leveling (Byte 0): 40 => 8

 6310 23:02:52.842254  Write leveling (Byte 1): 40 => 8

 6311 23:02:52.845385  DramcWriteLeveling(PI) end<-----

 6312 23:02:52.845470  

 6313 23:02:52.845536  ==

 6314 23:02:52.849200  Dram Type= 6, Freq= 0, CH_0, rank 0

 6315 23:02:52.855886  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6316 23:02:52.855973  ==

 6317 23:02:52.856039  [Gating] SW mode calibration

 6318 23:02:52.865907  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6319 23:02:52.868829  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6320 23:02:52.872332   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6321 23:02:52.878957   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6322 23:02:52.882055   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6323 23:02:52.885566   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6324 23:02:52.892031   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6325 23:02:52.895527   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6326 23:02:52.898778   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6327 23:02:52.905503   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6328 23:02:52.908872   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6329 23:02:52.912076  Total UI for P1: 0, mck2ui 16

 6330 23:02:52.915389  best dqsien dly found for B0: ( 0, 14, 24)

 6331 23:02:52.918752  Total UI for P1: 0, mck2ui 16

 6332 23:02:52.921817  best dqsien dly found for B1: ( 0, 14, 24)

 6333 23:02:52.925098  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6334 23:02:52.928809  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6335 23:02:52.928995  

 6336 23:02:52.932276  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6337 23:02:52.935502  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6338 23:02:52.938517  [Gating] SW calibration Done

 6339 23:02:52.938636  ==

 6340 23:02:52.942151  Dram Type= 6, Freq= 0, CH_0, rank 0

 6341 23:02:52.948411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6342 23:02:52.948523  ==

 6343 23:02:52.948618  RX Vref Scan: 0

 6344 23:02:52.948681  

 6345 23:02:52.951821  RX Vref 0 -> 0, step: 1

 6346 23:02:52.951916  

 6347 23:02:52.955277  RX Delay -410 -> 252, step: 16

 6348 23:02:52.958309  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6349 23:02:52.961418  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6350 23:02:52.965019  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6351 23:02:52.971789  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6352 23:02:52.974736  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6353 23:02:52.978343  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6354 23:02:52.981718  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6355 23:02:52.988318  iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480

 6356 23:02:52.991322  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6357 23:02:52.994942  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6358 23:02:52.998017  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6359 23:02:53.004965  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6360 23:02:53.008019  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6361 23:02:53.011423  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6362 23:02:53.018390  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6363 23:02:53.021041  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6364 23:02:53.021160  ==

 6365 23:02:53.024421  Dram Type= 6, Freq= 0, CH_0, rank 0

 6366 23:02:53.028107  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6367 23:02:53.028216  ==

 6368 23:02:53.031535  DQS Delay:

 6369 23:02:53.031645  DQS0 = 27, DQS1 = 35

 6370 23:02:53.031748  DQM Delay:

 6371 23:02:53.034487  DQM0 = 8, DQM1 = 11

 6372 23:02:53.034597  DQ Delay:

 6373 23:02:53.037943  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8

 6374 23:02:53.041252  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6375 23:02:53.044842  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6376 23:02:53.047621  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6377 23:02:53.047724  

 6378 23:02:53.047796  

 6379 23:02:53.047856  ==

 6380 23:02:53.051155  Dram Type= 6, Freq= 0, CH_0, rank 0

 6381 23:02:53.054664  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6382 23:02:53.054771  ==

 6383 23:02:53.058163  

 6384 23:02:53.058235  

 6385 23:02:53.058304  	TX Vref Scan disable

 6386 23:02:53.060971   == TX Byte 0 ==

 6387 23:02:53.064195  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6388 23:02:53.067933  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6389 23:02:53.071421   == TX Byte 1 ==

 6390 23:02:53.074755  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6391 23:02:53.077706  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6392 23:02:53.077812  ==

 6393 23:02:53.081149  Dram Type= 6, Freq= 0, CH_0, rank 0

 6394 23:02:53.084542  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6395 23:02:53.087743  ==

 6396 23:02:53.087852  

 6397 23:02:53.087949  

 6398 23:02:53.088039  	TX Vref Scan disable

 6399 23:02:53.091171   == TX Byte 0 ==

 6400 23:02:53.094215  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6401 23:02:53.097870  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6402 23:02:53.100902   == TX Byte 1 ==

 6403 23:02:53.104295  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6404 23:02:53.107861  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6405 23:02:53.107974  

 6406 23:02:53.108077  [DATLAT]

 6407 23:02:53.111296  Freq=400, CH0 RK0

 6408 23:02:53.111415  

 6409 23:02:53.114311  DATLAT Default: 0xf

 6410 23:02:53.114422  0, 0xFFFF, sum = 0

 6411 23:02:53.117815  1, 0xFFFF, sum = 0

 6412 23:02:53.117900  2, 0xFFFF, sum = 0

 6413 23:02:53.121061  3, 0xFFFF, sum = 0

 6414 23:02:53.121177  4, 0xFFFF, sum = 0

 6415 23:02:53.123999  5, 0xFFFF, sum = 0

 6416 23:02:53.124115  6, 0xFFFF, sum = 0

 6417 23:02:53.127878  7, 0xFFFF, sum = 0

 6418 23:02:53.127992  8, 0xFFFF, sum = 0

 6419 23:02:53.130618  9, 0xFFFF, sum = 0

 6420 23:02:53.130734  10, 0xFFFF, sum = 0

 6421 23:02:53.134028  11, 0xFFFF, sum = 0

 6422 23:02:53.134122  12, 0xFFFF, sum = 0

 6423 23:02:53.137541  13, 0x0, sum = 1

 6424 23:02:53.137645  14, 0x0, sum = 2

 6425 23:02:53.141186  15, 0x0, sum = 3

 6426 23:02:53.141304  16, 0x0, sum = 4

 6427 23:02:53.144109  best_step = 14

 6428 23:02:53.144221  

 6429 23:02:53.144326  ==

 6430 23:02:53.147581  Dram Type= 6, Freq= 0, CH_0, rank 0

 6431 23:02:53.150832  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6432 23:02:53.150944  ==

 6433 23:02:53.154082  RX Vref Scan: 1

 6434 23:02:53.154184  

 6435 23:02:53.154281  RX Vref 0 -> 0, step: 1

 6436 23:02:53.154373  

 6437 23:02:53.157300  RX Delay -311 -> 252, step: 8

 6438 23:02:53.157410  

 6439 23:02:53.160936  Set Vref, RX VrefLevel [Byte0]: 54

 6440 23:02:53.163696                           [Byte1]: 48

 6441 23:02:53.168313  

 6442 23:02:53.168420  Final RX Vref Byte 0 = 54 to rank0

 6443 23:02:53.172122  Final RX Vref Byte 1 = 48 to rank0

 6444 23:02:53.175096  Final RX Vref Byte 0 = 54 to rank1

 6445 23:02:53.178425  Final RX Vref Byte 1 = 48 to rank1==

 6446 23:02:53.181919  Dram Type= 6, Freq= 0, CH_0, rank 0

 6447 23:02:53.188460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6448 23:02:53.188577  ==

 6449 23:02:53.188655  DQS Delay:

 6450 23:02:53.192103  DQS0 = 28, DQS1 = 36

 6451 23:02:53.192210  DQM Delay:

 6452 23:02:53.192301  DQM0 = 11, DQM1 = 12

 6453 23:02:53.195061  DQ Delay:

 6454 23:02:53.198139  DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8

 6455 23:02:53.198241  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6456 23:02:53.201740  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4

 6457 23:02:53.204679  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6458 23:02:53.204797  

 6459 23:02:53.208299  

 6460 23:02:53.214660  [DQSOSCAuto] RK0, (LSB)MR18= 0xcdb9, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps

 6461 23:02:53.218055  CH0 RK0: MR19=C0C, MR18=CDB9

 6462 23:02:53.224679  CH0_RK0: MR19=0xC0C, MR18=0xCDB9, DQSOSC=384, MR23=63, INC=400, DEC=267

 6463 23:02:53.224812  ==

 6464 23:02:53.228182  Dram Type= 6, Freq= 0, CH_0, rank 1

 6465 23:02:53.231369  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6466 23:02:53.231494  ==

 6467 23:02:53.235032  [Gating] SW mode calibration

 6468 23:02:53.241653  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6469 23:02:53.248143  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6470 23:02:53.251272   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6471 23:02:53.254800   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6472 23:02:53.258201   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6473 23:02:53.264879   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6474 23:02:53.268216   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6475 23:02:53.271327   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6476 23:02:53.278042   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6477 23:02:53.281294   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6478 23:02:53.284895   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6479 23:02:53.288376  Total UI for P1: 0, mck2ui 16

 6480 23:02:53.291573  best dqsien dly found for B0: ( 0, 14, 24)

 6481 23:02:53.294609  Total UI for P1: 0, mck2ui 16

 6482 23:02:53.298137  best dqsien dly found for B1: ( 0, 14, 24)

 6483 23:02:53.301216  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6484 23:02:53.304731  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6485 23:02:53.308377  

 6486 23:02:53.311143  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6487 23:02:53.314919  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6488 23:02:53.317888  [Gating] SW calibration Done

 6489 23:02:53.317995  ==

 6490 23:02:53.321317  Dram Type= 6, Freq= 0, CH_0, rank 1

 6491 23:02:53.324961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6492 23:02:53.325071  ==

 6493 23:02:53.325167  RX Vref Scan: 0

 6494 23:02:53.327844  

 6495 23:02:53.327946  RX Vref 0 -> 0, step: 1

 6496 23:02:53.328040  

 6497 23:02:53.331485  RX Delay -410 -> 252, step: 16

 6498 23:02:53.335007  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6499 23:02:53.341475  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6500 23:02:53.344739  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6501 23:02:53.348070  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6502 23:02:53.351262  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6503 23:02:53.357676  iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464

 6504 23:02:53.361177  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6505 23:02:53.364733  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6506 23:02:53.367620  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6507 23:02:53.374417  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6508 23:02:53.377857  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6509 23:02:53.381114  iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448

 6510 23:02:53.384135  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6511 23:02:53.390763  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6512 23:02:53.394101  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6513 23:02:53.397668  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6514 23:02:53.397808  ==

 6515 23:02:53.400882  Dram Type= 6, Freq= 0, CH_0, rank 1

 6516 23:02:53.404465  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6517 23:02:53.407565  ==

 6518 23:02:53.407684  DQS Delay:

 6519 23:02:53.407786  DQS0 = 19, DQS1 = 35

 6520 23:02:53.410969  DQM Delay:

 6521 23:02:53.411075  DQM0 = 5, DQM1 = 12

 6522 23:02:53.414577  DQ Delay:

 6523 23:02:53.414689  DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0

 6524 23:02:53.417501  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6525 23:02:53.421109  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6526 23:02:53.424040  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6527 23:02:53.424154  

 6528 23:02:53.424248  

 6529 23:02:53.424349  ==

 6530 23:02:53.427650  Dram Type= 6, Freq= 0, CH_0, rank 1

 6531 23:02:53.434149  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6532 23:02:53.434288  ==

 6533 23:02:53.434390  

 6534 23:02:53.434468  

 6535 23:02:53.434536  	TX Vref Scan disable

 6536 23:02:53.437297   == TX Byte 0 ==

 6537 23:02:53.440829  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6538 23:02:53.444272  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6539 23:02:53.447210   == TX Byte 1 ==

 6540 23:02:53.450528  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6541 23:02:53.454010  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6542 23:02:53.457552  ==

 6543 23:02:53.457685  Dram Type= 6, Freq= 0, CH_0, rank 1

 6544 23:02:53.464207  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6545 23:02:53.464349  ==

 6546 23:02:53.464452  

 6547 23:02:53.464554  

 6548 23:02:53.467278  	TX Vref Scan disable

 6549 23:02:53.467405   == TX Byte 0 ==

 6550 23:02:53.470529  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6551 23:02:53.477329  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6552 23:02:53.477458   == TX Byte 1 ==

 6553 23:02:53.480252  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6554 23:02:53.483857  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6555 23:02:53.486873  

 6556 23:02:53.487009  [DATLAT]

 6557 23:02:53.487113  Freq=400, CH0 RK1

 6558 23:02:53.487208  

 6559 23:02:53.490454  DATLAT Default: 0xe

 6560 23:02:53.490569  0, 0xFFFF, sum = 0

 6561 23:02:53.493717  1, 0xFFFF, sum = 0

 6562 23:02:53.493830  2, 0xFFFF, sum = 0

 6563 23:02:53.496975  3, 0xFFFF, sum = 0

 6564 23:02:53.497086  4, 0xFFFF, sum = 0

 6565 23:02:53.500537  5, 0xFFFF, sum = 0

 6566 23:02:53.504049  6, 0xFFFF, sum = 0

 6567 23:02:53.504168  7, 0xFFFF, sum = 0

 6568 23:02:53.507061  8, 0xFFFF, sum = 0

 6569 23:02:53.507175  9, 0xFFFF, sum = 0

 6570 23:02:53.510447  10, 0xFFFF, sum = 0

 6571 23:02:53.510562  11, 0xFFFF, sum = 0

 6572 23:02:53.513541  12, 0xFFFF, sum = 0

 6573 23:02:53.513657  13, 0x0, sum = 1

 6574 23:02:53.517276  14, 0x0, sum = 2

 6575 23:02:53.517400  15, 0x0, sum = 3

 6576 23:02:53.520400  16, 0x0, sum = 4

 6577 23:02:53.520532  best_step = 14

 6578 23:02:53.520634  

 6579 23:02:53.520738  ==

 6580 23:02:53.523570  Dram Type= 6, Freq= 0, CH_0, rank 1

 6581 23:02:53.527095  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6582 23:02:53.527214  ==

 6583 23:02:53.530121  RX Vref Scan: 0

 6584 23:02:53.530237  

 6585 23:02:53.533522  RX Vref 0 -> 0, step: 1

 6586 23:02:53.533653  

 6587 23:02:53.533752  RX Delay -311 -> 252, step: 8

 6588 23:02:53.542346  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6589 23:02:53.545981  iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440

 6590 23:02:53.548889  iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456

 6591 23:02:53.552413  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6592 23:02:53.558756  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6593 23:02:53.562265  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6594 23:02:53.565647  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6595 23:02:53.568999  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6596 23:02:53.575624  iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440

 6597 23:02:53.578633  iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440

 6598 23:02:53.582246  iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440

 6599 23:02:53.585608  iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440

 6600 23:02:53.592130  iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440

 6601 23:02:53.595684  iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440

 6602 23:02:53.599219  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6603 23:02:53.602103  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6604 23:02:53.605805  ==

 6605 23:02:53.608786  Dram Type= 6, Freq= 0, CH_0, rank 1

 6606 23:02:53.612192  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6607 23:02:53.612308  ==

 6608 23:02:53.612402  DQS Delay:

 6609 23:02:53.615678  DQS0 = 24, DQS1 = 36

 6610 23:02:53.615785  DQM Delay:

 6611 23:02:53.619052  DQM0 = 8, DQM1 = 13

 6612 23:02:53.619160  DQ Delay:

 6613 23:02:53.622444  DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8

 6614 23:02:53.625680  DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16

 6615 23:02:53.628968  DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8

 6616 23:02:53.632151  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20

 6617 23:02:53.632277  

 6618 23:02:53.632377  

 6619 23:02:53.638622  [DQSOSCAuto] RK1, (LSB)MR18= 0xb756, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 387 ps

 6620 23:02:53.642320  CH0 RK1: MR19=C0C, MR18=B756

 6621 23:02:53.648898  CH0_RK1: MR19=0xC0C, MR18=0xB756, DQSOSC=387, MR23=63, INC=394, DEC=262

 6622 23:02:53.652352  [RxdqsGatingPostProcess] freq 400

 6623 23:02:53.655662  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6624 23:02:53.659037  best DQS0 dly(2T, 0.5T) = (0, 10)

 6625 23:02:53.661893  best DQS1 dly(2T, 0.5T) = (0, 10)

 6626 23:02:53.665602  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6627 23:02:53.669036  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6628 23:02:53.672293  best DQS0 dly(2T, 0.5T) = (0, 10)

 6629 23:02:53.675427  best DQS1 dly(2T, 0.5T) = (0, 10)

 6630 23:02:53.678841  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6631 23:02:53.681799  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6632 23:02:53.685528  Pre-setting of DQS Precalculation

 6633 23:02:53.688763  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6634 23:02:53.688871  ==

 6635 23:02:53.691989  Dram Type= 6, Freq= 0, CH_1, rank 0

 6636 23:02:53.698491  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6637 23:02:53.698613  ==

 6638 23:02:53.702318  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6639 23:02:53.708798  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6640 23:02:53.711834  [CA 0] Center 36 (8~64) winsize 57

 6641 23:02:53.715299  [CA 1] Center 36 (8~64) winsize 57

 6642 23:02:53.718301  [CA 2] Center 36 (8~64) winsize 57

 6643 23:02:53.721933  [CA 3] Center 36 (8~64) winsize 57

 6644 23:02:53.724904  [CA 4] Center 36 (8~64) winsize 57

 6645 23:02:53.728484  [CA 5] Center 36 (8~64) winsize 57

 6646 23:02:53.728568  

 6647 23:02:53.732037  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6648 23:02:53.732115  

 6649 23:02:53.735278  [CATrainingPosCal] consider 1 rank data

 6650 23:02:53.738514  u2DelayCellTimex100 = 270/100 ps

 6651 23:02:53.742016  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6652 23:02:53.745314  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6653 23:02:53.748208  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6654 23:02:53.751751  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6655 23:02:53.755252  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6656 23:02:53.758395  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6657 23:02:53.761672  

 6658 23:02:53.765050  CA PerBit enable=1, Macro0, CA PI delay=36

 6659 23:02:53.765167  

 6660 23:02:53.768554  [CBTSetCACLKResult] CA Dly = 36

 6661 23:02:53.768667  CS Dly: 1 (0~32)

 6662 23:02:53.768763  ==

 6663 23:02:53.771634  Dram Type= 6, Freq= 0, CH_1, rank 1

 6664 23:02:53.775038  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6665 23:02:53.775164  ==

 6666 23:02:53.781416  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6667 23:02:53.788585  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6668 23:02:53.791469  [CA 0] Center 36 (8~64) winsize 57

 6669 23:02:53.795044  [CA 1] Center 36 (8~64) winsize 57

 6670 23:02:53.798298  [CA 2] Center 36 (8~64) winsize 57

 6671 23:02:53.801804  [CA 3] Center 36 (8~64) winsize 57

 6672 23:02:53.804706  [CA 4] Center 36 (8~64) winsize 57

 6673 23:02:53.808311  [CA 5] Center 36 (8~64) winsize 57

 6674 23:02:53.808426  

 6675 23:02:53.811658  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6676 23:02:53.811773  

 6677 23:02:53.814613  [CATrainingPosCal] consider 2 rank data

 6678 23:02:53.818241  u2DelayCellTimex100 = 270/100 ps

 6679 23:02:53.821364  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6680 23:02:53.824907  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6681 23:02:53.828317  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6682 23:02:53.831365  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6683 23:02:53.834983  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6684 23:02:53.837900  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6685 23:02:53.838017  

 6686 23:02:53.841221  CA PerBit enable=1, Macro0, CA PI delay=36

 6687 23:02:53.841331  

 6688 23:02:53.844491  [CBTSetCACLKResult] CA Dly = 36

 6689 23:02:53.847979  CS Dly: 1 (0~32)

 6690 23:02:53.848101  

 6691 23:02:53.851460  ----->DramcWriteLeveling(PI) begin...

 6692 23:02:53.851577  ==

 6693 23:02:53.854819  Dram Type= 6, Freq= 0, CH_1, rank 0

 6694 23:02:53.858226  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6695 23:02:53.858354  ==

 6696 23:02:53.861152  Write leveling (Byte 0): 40 => 8

 6697 23:02:53.864823  Write leveling (Byte 1): 40 => 8

 6698 23:02:53.868035  DramcWriteLeveling(PI) end<-----

 6699 23:02:53.868140  

 6700 23:02:53.868222  ==

 6701 23:02:53.871449  Dram Type= 6, Freq= 0, CH_1, rank 0

 6702 23:02:53.874836  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6703 23:02:53.874935  ==

 6704 23:02:53.878363  [Gating] SW mode calibration

 6705 23:02:53.884219  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6706 23:02:53.891355  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6707 23:02:53.894296   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6708 23:02:53.900990   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6709 23:02:53.904279   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6710 23:02:53.907436   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6711 23:02:53.914486   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6712 23:02:53.917469   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6713 23:02:53.920900   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6714 23:02:53.927548   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6715 23:02:53.931317   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6716 23:02:53.933972  Total UI for P1: 0, mck2ui 16

 6717 23:02:53.937587  best dqsien dly found for B0: ( 0, 14, 24)

 6718 23:02:53.940610  Total UI for P1: 0, mck2ui 16

 6719 23:02:53.944287  best dqsien dly found for B1: ( 0, 14, 24)

 6720 23:02:53.947161  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6721 23:02:53.950545  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6722 23:02:53.950629  

 6723 23:02:53.953809  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6724 23:02:53.957283  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6725 23:02:53.960656  [Gating] SW calibration Done

 6726 23:02:53.960743  ==

 6727 23:02:53.964025  Dram Type= 6, Freq= 0, CH_1, rank 0

 6728 23:02:53.967029  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6729 23:02:53.967115  ==

 6730 23:02:53.970464  RX Vref Scan: 0

 6731 23:02:53.970581  

 6732 23:02:53.974033  RX Vref 0 -> 0, step: 1

 6733 23:02:53.974159  

 6734 23:02:53.974255  RX Delay -410 -> 252, step: 16

 6735 23:02:53.980974  iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480

 6736 23:02:53.984302  iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480

 6737 23:02:53.987508  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6738 23:02:53.990509  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6739 23:02:53.997608  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6740 23:02:54.000775  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6741 23:02:54.004245  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6742 23:02:54.007236  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6743 23:02:54.014018  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6744 23:02:54.017019  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6745 23:02:54.020487  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6746 23:02:54.023932  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6747 23:02:54.030468  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6748 23:02:54.034062  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6749 23:02:54.037528  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6750 23:02:54.044140  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6751 23:02:54.044235  ==

 6752 23:02:54.047066  Dram Type= 6, Freq= 0, CH_1, rank 0

 6753 23:02:54.050697  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6754 23:02:54.050774  ==

 6755 23:02:54.050837  DQS Delay:

 6756 23:02:54.053760  DQS0 = 35, DQS1 = 35

 6757 23:02:54.053844  DQM Delay:

 6758 23:02:54.056995  DQM0 = 17, DQM1 = 12

 6759 23:02:54.057073  DQ Delay:

 6760 23:02:54.060330  DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16

 6761 23:02:54.064022  DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16

 6762 23:02:54.066984  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6763 23:02:54.070318  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =16

 6764 23:02:54.070419  

 6765 23:02:54.070513  

 6766 23:02:54.070603  ==

 6767 23:02:54.073642  Dram Type= 6, Freq= 0, CH_1, rank 0

 6768 23:02:54.077094  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6769 23:02:54.077206  ==

 6770 23:02:54.077299  

 6771 23:02:54.077387  

 6772 23:02:54.080669  	TX Vref Scan disable

 6773 23:02:54.080755   == TX Byte 0 ==

 6774 23:02:54.087176  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6775 23:02:54.090713  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6776 23:02:54.090805   == TX Byte 1 ==

 6777 23:02:54.097214  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6778 23:02:54.100456  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6779 23:02:54.100559  ==

 6780 23:02:54.103748  Dram Type= 6, Freq= 0, CH_1, rank 0

 6781 23:02:54.106885  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6782 23:02:54.106997  ==

 6783 23:02:54.107090  

 6784 23:02:54.107178  

 6785 23:02:54.110442  	TX Vref Scan disable

 6786 23:02:54.113386   == TX Byte 0 ==

 6787 23:02:54.117206  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6788 23:02:54.120563  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6789 23:02:54.120647   == TX Byte 1 ==

 6790 23:02:54.126914  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6791 23:02:54.130082  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6792 23:02:54.130168  

 6793 23:02:54.130233  [DATLAT]

 6794 23:02:54.133686  Freq=400, CH1 RK0

 6795 23:02:54.133770  

 6796 23:02:54.133835  DATLAT Default: 0xf

 6797 23:02:54.137394  0, 0xFFFF, sum = 0

 6798 23:02:54.137478  1, 0xFFFF, sum = 0

 6799 23:02:54.140441  2, 0xFFFF, sum = 0

 6800 23:02:54.140525  3, 0xFFFF, sum = 0

 6801 23:02:54.143657  4, 0xFFFF, sum = 0

 6802 23:02:54.143742  5, 0xFFFF, sum = 0

 6803 23:02:54.147361  6, 0xFFFF, sum = 0

 6804 23:02:54.150326  7, 0xFFFF, sum = 0

 6805 23:02:54.150420  8, 0xFFFF, sum = 0

 6806 23:02:54.153809  9, 0xFFFF, sum = 0

 6807 23:02:54.153893  10, 0xFFFF, sum = 0

 6808 23:02:54.156674  11, 0xFFFF, sum = 0

 6809 23:02:54.156758  12, 0xFFFF, sum = 0

 6810 23:02:54.160185  13, 0x0, sum = 1

 6811 23:02:54.160269  14, 0x0, sum = 2

 6812 23:02:54.163538  15, 0x0, sum = 3

 6813 23:02:54.163653  16, 0x0, sum = 4

 6814 23:02:54.163731  best_step = 14

 6815 23:02:54.166999  

 6816 23:02:54.167116  ==

 6817 23:02:54.169894  Dram Type= 6, Freq= 0, CH_1, rank 0

 6818 23:02:54.173391  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6819 23:02:54.173474  ==

 6820 23:02:54.173539  RX Vref Scan: 1

 6821 23:02:54.173609  

 6822 23:02:54.177039  RX Vref 0 -> 0, step: 1

 6823 23:02:54.177127  

 6824 23:02:54.180314  RX Delay -311 -> 252, step: 8

 6825 23:02:54.180398  

 6826 23:02:54.183655  Set Vref, RX VrefLevel [Byte0]: 52

 6827 23:02:54.187157                           [Byte1]: 46

 6828 23:02:54.190711  

 6829 23:02:54.190809  Final RX Vref Byte 0 = 52 to rank0

 6830 23:02:54.193712  Final RX Vref Byte 1 = 46 to rank0

 6831 23:02:54.197202  Final RX Vref Byte 0 = 52 to rank1

 6832 23:02:54.200087  Final RX Vref Byte 1 = 46 to rank1==

 6833 23:02:54.203413  Dram Type= 6, Freq= 0, CH_1, rank 0

 6834 23:02:54.210322  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6835 23:02:54.210454  ==

 6836 23:02:54.210550  DQS Delay:

 6837 23:02:54.213284  DQS0 = 32, DQS1 = 32

 6838 23:02:54.213384  DQM Delay:

 6839 23:02:54.213474  DQM0 = 13, DQM1 = 11

 6840 23:02:54.216963  DQ Delay:

 6841 23:02:54.219982  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6842 23:02:54.223562  DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12

 6843 23:02:54.223650  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4

 6844 23:02:54.227126  DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20

 6845 23:02:54.229929  

 6846 23:02:54.230003  

 6847 23:02:54.236825  [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps

 6848 23:02:54.240172  CH1 RK0: MR19=C0C, MR18=8CC4

 6849 23:02:54.246989  CH1_RK0: MR19=0xC0C, MR18=0x8CC4, DQSOSC=385, MR23=63, INC=398, DEC=265

 6850 23:02:54.247111  ==

 6851 23:02:54.250049  Dram Type= 6, Freq= 0, CH_1, rank 1

 6852 23:02:54.253573  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6853 23:02:54.253657  ==

 6854 23:02:54.257261  [Gating] SW mode calibration

 6855 23:02:54.263174  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6856 23:02:54.270026  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6857 23:02:54.273375   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6858 23:02:54.277032   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6859 23:02:54.283026   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6860 23:02:54.286487   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6861 23:02:54.289873   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6862 23:02:54.296527   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6863 23:02:54.299625   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6864 23:02:54.303004   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6865 23:02:54.309762   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6866 23:02:54.309864  Total UI for P1: 0, mck2ui 16

 6867 23:02:54.313191  best dqsien dly found for B0: ( 0, 14, 24)

 6868 23:02:54.316741  Total UI for P1: 0, mck2ui 16

 6869 23:02:54.319588  best dqsien dly found for B1: ( 0, 14, 24)

 6870 23:02:54.326812  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6871 23:02:54.329552  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6872 23:02:54.329671  

 6873 23:02:54.333150  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6874 23:02:54.336101  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6875 23:02:54.339652  [Gating] SW calibration Done

 6876 23:02:54.339761  ==

 6877 23:02:54.343079  Dram Type= 6, Freq= 0, CH_1, rank 1

 6878 23:02:54.346457  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6879 23:02:54.346537  ==

 6880 23:02:54.349733  RX Vref Scan: 0

 6881 23:02:54.349817  

 6882 23:02:54.349920  RX Vref 0 -> 0, step: 1

 6883 23:02:54.350013  

 6884 23:02:54.352999  RX Delay -410 -> 252, step: 16

 6885 23:02:54.356655  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6886 23:02:54.362997  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6887 23:02:54.366122  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6888 23:02:54.369598  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6889 23:02:54.373155  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6890 23:02:54.379487  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6891 23:02:54.383213  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6892 23:02:54.386028  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6893 23:02:54.389792  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6894 23:02:54.396072  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6895 23:02:54.399545  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6896 23:02:54.402806  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6897 23:02:54.406125  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6898 23:02:54.413152  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6899 23:02:54.415991  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6900 23:02:54.419475  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6901 23:02:54.419600  ==

 6902 23:02:54.422973  Dram Type= 6, Freq= 0, CH_1, rank 1

 6903 23:02:54.429505  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6904 23:02:54.429634  ==

 6905 23:02:54.429703  DQS Delay:

 6906 23:02:54.432610  DQS0 = 35, DQS1 = 35

 6907 23:02:54.432711  DQM Delay:

 6908 23:02:54.432815  DQM0 = 18, DQM1 = 13

 6909 23:02:54.436001  DQ Delay:

 6910 23:02:54.439654  DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16

 6911 23:02:54.442587  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6912 23:02:54.442676  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6913 23:02:54.449440  DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24

 6914 23:02:54.449548  

 6915 23:02:54.449669  

 6916 23:02:54.449760  ==

 6917 23:02:54.452312  Dram Type= 6, Freq= 0, CH_1, rank 1

 6918 23:02:54.455955  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6919 23:02:54.456055  ==

 6920 23:02:54.456145  

 6921 23:02:54.456231  

 6922 23:02:54.459195  	TX Vref Scan disable

 6923 23:02:54.459296   == TX Byte 0 ==

 6924 23:02:54.462695  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6925 23:02:54.469569  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6926 23:02:54.469677   == TX Byte 1 ==

 6927 23:02:54.472508  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6928 23:02:54.479337  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6929 23:02:54.479420  ==

 6930 23:02:54.482529  Dram Type= 6, Freq= 0, CH_1, rank 1

 6931 23:02:54.486135  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6932 23:02:54.486248  ==

 6933 23:02:54.486317  

 6934 23:02:54.486377  

 6935 23:02:54.489217  	TX Vref Scan disable

 6936 23:02:54.489330   == TX Byte 0 ==

 6937 23:02:54.492275  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6938 23:02:54.499149  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6939 23:02:54.499235   == TX Byte 1 ==

 6940 23:02:54.502584  Update DQ  dly =585 (4 ,2, 9)  DQ  OEN =(3 ,3)

 6941 23:02:54.508707  Update DQM dly =585 (4 ,2, 9)  DQM OEN =(3 ,3)

 6942 23:02:54.508826  

 6943 23:02:54.508922  [DATLAT]

 6944 23:02:54.509012  Freq=400, CH1 RK1

 6945 23:02:54.512035  

 6946 23:02:54.512140  DATLAT Default: 0xe

 6947 23:02:54.515503  0, 0xFFFF, sum = 0

 6948 23:02:54.515581  1, 0xFFFF, sum = 0

 6949 23:02:54.518987  2, 0xFFFF, sum = 0

 6950 23:02:54.519092  3, 0xFFFF, sum = 0

 6951 23:02:54.522586  4, 0xFFFF, sum = 0

 6952 23:02:54.522662  5, 0xFFFF, sum = 0

 6953 23:02:54.525834  6, 0xFFFF, sum = 0

 6954 23:02:54.525918  7, 0xFFFF, sum = 0

 6955 23:02:54.529359  8, 0xFFFF, sum = 0

 6956 23:02:54.529443  9, 0xFFFF, sum = 0

 6957 23:02:54.532249  10, 0xFFFF, sum = 0

 6958 23:02:54.532332  11, 0xFFFF, sum = 0

 6959 23:02:54.535594  12, 0xFFFF, sum = 0

 6960 23:02:54.535678  13, 0x0, sum = 1

 6961 23:02:54.539073  14, 0x0, sum = 2

 6962 23:02:54.539170  15, 0x0, sum = 3

 6963 23:02:54.542367  16, 0x0, sum = 4

 6964 23:02:54.542460  best_step = 14

 6965 23:02:54.542527  

 6966 23:02:54.542589  ==

 6967 23:02:54.545307  Dram Type= 6, Freq= 0, CH_1, rank 1

 6968 23:02:54.552026  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6969 23:02:54.552109  ==

 6970 23:02:54.552174  RX Vref Scan: 0

 6971 23:02:54.552234  

 6972 23:02:54.555688  RX Vref 0 -> 0, step: 1

 6973 23:02:54.555769  

 6974 23:02:54.558617  RX Delay -311 -> 252, step: 8

 6975 23:02:54.565333  iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440

 6976 23:02:54.568813  iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448

 6977 23:02:54.572491  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6978 23:02:54.575333  iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440

 6979 23:02:54.578932  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6980 23:02:54.585518  iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448

 6981 23:02:54.588739  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6982 23:02:54.592074  iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440

 6983 23:02:54.595580  iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448

 6984 23:02:54.602047  iDelay=217, Bit 9, Center -28 (-247 ~ 192) 440

 6985 23:02:54.605445  iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448

 6986 23:02:54.608978  iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448

 6987 23:02:54.612185  iDelay=217, Bit 12, Center -8 (-231 ~ 216) 448

 6988 23:02:54.618558  iDelay=217, Bit 13, Center -12 (-231 ~ 208) 440

 6989 23:02:54.622146  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6990 23:02:54.625001  iDelay=217, Bit 15, Center -12 (-231 ~ 208) 440

 6991 23:02:54.625084  ==

 6992 23:02:54.628526  Dram Type= 6, Freq= 0, CH_1, rank 1

 6993 23:02:54.635372  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6994 23:02:54.635455  ==

 6995 23:02:54.635521  DQS Delay:

 6996 23:02:54.638490  DQS0 = 28, DQS1 = 32

 6997 23:02:54.638572  DQM Delay:

 6998 23:02:54.641721  DQM0 = 10, DQM1 = 13

 6999 23:02:54.641803  DQ Delay:

 7000 23:02:54.645219  DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8

 7001 23:02:54.648696  DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8

 7002 23:02:54.648777  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8

 7003 23:02:54.651516  DQ12 =24, DQ13 =20, DQ14 =16, DQ15 =20

 7004 23:02:54.654968  

 7005 23:02:54.655044  

 7006 23:02:54.661528  [DQSOSCAuto] RK1, (LSB)MR18= 0xc155, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps

 7007 23:02:54.665076  CH1 RK1: MR19=C0C, MR18=C155

 7008 23:02:54.671371  CH1_RK1: MR19=0xC0C, MR18=0xC155, DQSOSC=385, MR23=63, INC=398, DEC=265

 7009 23:02:54.674685  [RxdqsGatingPostProcess] freq 400

 7010 23:02:54.678211  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 7011 23:02:54.681516  best DQS0 dly(2T, 0.5T) = (0, 10)

 7012 23:02:54.685022  best DQS1 dly(2T, 0.5T) = (0, 10)

 7013 23:02:54.688036  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7014 23:02:54.691406  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7015 23:02:54.694638  best DQS0 dly(2T, 0.5T) = (0, 10)

 7016 23:02:54.698024  best DQS1 dly(2T, 0.5T) = (0, 10)

 7017 23:02:54.701506  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 7018 23:02:54.704504  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 7019 23:02:54.708112  Pre-setting of DQS Precalculation

 7020 23:02:54.711546  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 7021 23:02:54.721359  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 7022 23:02:54.728398  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 7023 23:02:54.728481  

 7024 23:02:54.728547  

 7025 23:02:54.731185  [Calibration Summary] 800 Mbps

 7026 23:02:54.731292  CH 0, Rank 0

 7027 23:02:54.734906  SW Impedance     : PASS

 7028 23:02:54.734988  DUTY Scan        : NO K

 7029 23:02:54.737957  ZQ Calibration   : PASS

 7030 23:02:54.741431  Jitter Meter     : NO K

 7031 23:02:54.741514  CBT Training     : PASS

 7032 23:02:54.744352  Write leveling   : PASS

 7033 23:02:54.747648  RX DQS gating    : PASS

 7034 23:02:54.747731  RX DQ/DQS(RDDQC) : PASS

 7035 23:02:54.751439  TX DQ/DQS        : PASS

 7036 23:02:54.751524  RX DATLAT        : PASS

 7037 23:02:54.754745  RX DQ/DQS(Engine): PASS

 7038 23:02:54.757743  TX OE            : NO K

 7039 23:02:54.757826  All Pass.

 7040 23:02:54.757902  

 7041 23:02:54.757994  CH 0, Rank 1

 7042 23:02:54.761125  SW Impedance     : PASS

 7043 23:02:54.764326  DUTY Scan        : NO K

 7044 23:02:54.764409  ZQ Calibration   : PASS

 7045 23:02:54.767751  Jitter Meter     : NO K

 7046 23:02:54.771396  CBT Training     : PASS

 7047 23:02:54.771478  Write leveling   : NO K

 7048 23:02:54.774360  RX DQS gating    : PASS

 7049 23:02:54.777855  RX DQ/DQS(RDDQC) : PASS

 7050 23:02:54.777966  TX DQ/DQS        : PASS

 7051 23:02:54.781312  RX DATLAT        : PASS

 7052 23:02:54.784724  RX DQ/DQS(Engine): PASS

 7053 23:02:54.784810  TX OE            : NO K

 7054 23:02:54.784879  All Pass.

 7055 23:02:54.788074  

 7056 23:02:54.788172  CH 1, Rank 0

 7057 23:02:54.791164  SW Impedance     : PASS

 7058 23:02:54.791262  DUTY Scan        : NO K

 7059 23:02:54.794742  ZQ Calibration   : PASS

 7060 23:02:54.794842  Jitter Meter     : NO K

 7061 23:02:54.797556  CBT Training     : PASS

 7062 23:02:54.800993  Write leveling   : PASS

 7063 23:02:54.801070  RX DQS gating    : PASS

 7064 23:02:54.804441  RX DQ/DQS(RDDQC) : PASS

 7065 23:02:54.808039  TX DQ/DQS        : PASS

 7066 23:02:54.808140  RX DATLAT        : PASS

 7067 23:02:54.810927  RX DQ/DQS(Engine): PASS

 7068 23:02:54.814619  TX OE            : NO K

 7069 23:02:54.814693  All Pass.

 7070 23:02:54.814756  

 7071 23:02:54.814815  CH 1, Rank 1

 7072 23:02:54.818140  SW Impedance     : PASS

 7073 23:02:54.820840  DUTY Scan        : NO K

 7074 23:02:54.820917  ZQ Calibration   : PASS

 7075 23:02:54.824256  Jitter Meter     : NO K

 7076 23:02:54.827744  CBT Training     : PASS

 7077 23:02:54.827846  Write leveling   : NO K

 7078 23:02:54.831123  RX DQS gating    : PASS

 7079 23:02:54.834017  RX DQ/DQS(RDDQC) : PASS

 7080 23:02:54.834090  TX DQ/DQS        : PASS

 7081 23:02:54.837645  RX DATLAT        : PASS

 7082 23:02:54.840663  RX DQ/DQS(Engine): PASS

 7083 23:02:54.840758  TX OE            : NO K

 7084 23:02:54.840850  All Pass.

 7085 23:02:54.844321  

 7086 23:02:54.844390  DramC Write-DBI off

 7087 23:02:54.847462  	PER_BANK_REFRESH: Hybrid Mode

 7088 23:02:54.847546  TX_TRACKING: ON

 7089 23:02:54.857339  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7090 23:02:54.860654  [FAST_K] Save calibration result to emmc

 7091 23:02:54.863935  dramc_set_vcore_voltage set vcore to 725000

 7092 23:02:54.867673  Read voltage for 1600, 0

 7093 23:02:54.867756  Vio18 = 0

 7094 23:02:54.871052  Vcore = 725000

 7095 23:02:54.871134  Vdram = 0

 7096 23:02:54.871199  Vddq = 0

 7097 23:02:54.871259  Vmddr = 0

 7098 23:02:54.877179  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7099 23:02:54.884164  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7100 23:02:54.884249  MEM_TYPE=3, freq_sel=13

 7101 23:02:54.887198  sv_algorithm_assistance_LP4_3733 

 7102 23:02:54.890979  ============ PULL DRAM RESETB DOWN ============

 7103 23:02:54.897263  ========== PULL DRAM RESETB DOWN end =========

 7104 23:02:54.900961  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7105 23:02:54.903925  =================================== 

 7106 23:02:54.907193  LPDDR4 DRAM CONFIGURATION

 7107 23:02:54.910626  =================================== 

 7108 23:02:54.910709  EX_ROW_EN[0]    = 0x0

 7109 23:02:54.914321  EX_ROW_EN[1]    = 0x0

 7110 23:02:54.914402  LP4Y_EN      = 0x0

 7111 23:02:54.917378  WORK_FSP     = 0x1

 7112 23:02:54.917487  WL           = 0x5

 7113 23:02:54.920436  RL           = 0x5

 7114 23:02:54.924037  BL           = 0x2

 7115 23:02:54.924120  RPST         = 0x0

 7116 23:02:54.927494  RD_PRE       = 0x0

 7117 23:02:54.927576  WR_PRE       = 0x1

 7118 23:02:54.930634  WR_PST       = 0x1

 7119 23:02:54.930729  DBI_WR       = 0x0

 7120 23:02:54.933636  DBI_RD       = 0x0

 7121 23:02:54.933719  OTF          = 0x1

 7122 23:02:54.937228  =================================== 

 7123 23:02:54.940744  =================================== 

 7124 23:02:54.943746  ANA top config

 7125 23:02:54.947334  =================================== 

 7126 23:02:54.947417  DLL_ASYNC_EN            =  0

 7127 23:02:54.950396  ALL_SLAVE_EN            =  0

 7128 23:02:54.954028  NEW_RANK_MODE           =  1

 7129 23:02:54.956988  DLL_IDLE_MODE           =  1

 7130 23:02:54.957071  LP45_APHY_COMB_EN       =  1

 7131 23:02:54.960492  TX_ODT_DIS              =  0

 7132 23:02:54.963510  NEW_8X_MODE             =  1

 7133 23:02:54.967214  =================================== 

 7134 23:02:54.970569  =================================== 

 7135 23:02:54.973795  data_rate                  = 3200

 7136 23:02:54.976998  CKR                        = 1

 7137 23:02:54.980458  DQ_P2S_RATIO               = 8

 7138 23:02:54.980541  =================================== 

 7139 23:02:54.983890  CA_P2S_RATIO               = 8

 7140 23:02:54.987242  DQ_CA_OPEN                 = 0

 7141 23:02:54.990668  DQ_SEMI_OPEN               = 0

 7142 23:02:54.994272  CA_SEMI_OPEN               = 0

 7143 23:02:54.997253  CA_FULL_RATE               = 0

 7144 23:02:54.997362  DQ_CKDIV4_EN               = 0

 7145 23:02:55.000437  CA_CKDIV4_EN               = 0

 7146 23:02:55.003617  CA_PREDIV_EN               = 0

 7147 23:02:55.007529  PH8_DLY                    = 12

 7148 23:02:55.010284  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7149 23:02:55.013545  DQ_AAMCK_DIV               = 4

 7150 23:02:55.013636  CA_AAMCK_DIV               = 4

 7151 23:02:55.017033  CA_ADMCK_DIV               = 4

 7152 23:02:55.020676  DQ_TRACK_CA_EN             = 0

 7153 23:02:55.023730  CA_PICK                    = 1600

 7154 23:02:55.027306  CA_MCKIO                   = 1600

 7155 23:02:55.030157  MCKIO_SEMI                 = 0

 7156 23:02:55.033735  PLL_FREQ                   = 3068

 7157 23:02:55.037007  DQ_UI_PI_RATIO             = 32

 7158 23:02:55.037115  CA_UI_PI_RATIO             = 0

 7159 23:02:55.040330  =================================== 

 7160 23:02:55.043677  =================================== 

 7161 23:02:55.046802  memory_type:LPDDR4         

 7162 23:02:55.050237  GP_NUM     : 10       

 7163 23:02:55.050314  SRAM_EN    : 1       

 7164 23:02:55.053260  MD32_EN    : 0       

 7165 23:02:55.056811  =================================== 

 7166 23:02:55.060285  [ANA_INIT] >>>>>>>>>>>>>> 

 7167 23:02:55.063130  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7168 23:02:55.066738  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7169 23:02:55.070275  =================================== 

 7170 23:02:55.070384  data_rate = 3200,PCW = 0X7600

 7171 23:02:55.073155  =================================== 

 7172 23:02:55.076685  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7173 23:02:55.083276  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7174 23:02:55.089771  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7175 23:02:55.093216  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7176 23:02:55.096848  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7177 23:02:55.099687  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7178 23:02:55.103263  [ANA_INIT] flow start 

 7179 23:02:55.103373  [ANA_INIT] PLL >>>>>>>> 

 7180 23:02:55.106585  [ANA_INIT] PLL <<<<<<<< 

 7181 23:02:55.109554  [ANA_INIT] MIDPI >>>>>>>> 

 7182 23:02:55.112891  [ANA_INIT] MIDPI <<<<<<<< 

 7183 23:02:55.112982  [ANA_INIT] DLL >>>>>>>> 

 7184 23:02:55.116297  [ANA_INIT] DLL <<<<<<<< 

 7185 23:02:55.119544  [ANA_INIT] flow end 

 7186 23:02:55.123227  ============ LP4 DIFF to SE enter ============

 7187 23:02:55.126466  ============ LP4 DIFF to SE exit  ============

 7188 23:02:55.129523  [ANA_INIT] <<<<<<<<<<<<< 

 7189 23:02:55.133061  [Flow] Enable top DCM control >>>>> 

 7190 23:02:55.136203  [Flow] Enable top DCM control <<<<< 

 7191 23:02:55.139454  Enable DLL master slave shuffle 

 7192 23:02:55.142556  ============================================================== 

 7193 23:02:55.146197  Gating Mode config

 7194 23:02:55.153094  ============================================================== 

 7195 23:02:55.153183  Config description: 

 7196 23:02:55.162908  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7197 23:02:55.169190  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7198 23:02:55.172887  SELPH_MODE            0: By rank         1: By Phase 

 7199 23:02:55.179417  ============================================================== 

 7200 23:02:55.182507  GAT_TRACK_EN                 =  1

 7201 23:02:55.186127  RX_GATING_MODE               =  2

 7202 23:02:55.188838  RX_GATING_TRACK_MODE         =  2

 7203 23:02:55.192586  SELPH_MODE                   =  1

 7204 23:02:55.195456  PICG_EARLY_EN                =  1

 7205 23:02:55.198730  VALID_LAT_VALUE              =  1

 7206 23:02:55.202072  ============================================================== 

 7207 23:02:55.205483  Enter into Gating configuration >>>> 

 7208 23:02:55.208968  Exit from Gating configuration <<<< 

 7209 23:02:55.212123  Enter into  DVFS_PRE_config >>>>> 

 7210 23:02:55.225531  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7211 23:02:55.225646  Exit from  DVFS_PRE_config <<<<< 

 7212 23:02:55.229217  Enter into PICG configuration >>>> 

 7213 23:02:55.232293  Exit from PICG configuration <<<< 

 7214 23:02:55.235649  [RX_INPUT] configuration >>>>> 

 7215 23:02:55.239100  [RX_INPUT] configuration <<<<< 

 7216 23:02:55.245540  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7217 23:02:55.248783  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7218 23:02:55.255467  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7219 23:02:55.261910  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7220 23:02:55.268735  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7221 23:02:55.275261  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7222 23:02:55.278355  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7223 23:02:55.282093  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7224 23:02:55.284995  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7225 23:02:55.291629  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7226 23:02:55.295295  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7227 23:02:55.298520  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7228 23:02:55.302120  =================================== 

 7229 23:02:55.305145  LPDDR4 DRAM CONFIGURATION

 7230 23:02:55.308719  =================================== 

 7231 23:02:55.308802  EX_ROW_EN[0]    = 0x0

 7232 23:02:55.312335  EX_ROW_EN[1]    = 0x0

 7233 23:02:55.315350  LP4Y_EN      = 0x0

 7234 23:02:55.315461  WORK_FSP     = 0x1

 7235 23:02:55.318449  WL           = 0x5

 7236 23:02:55.318557  RL           = 0x5

 7237 23:02:55.322162  BL           = 0x2

 7238 23:02:55.322243  RPST         = 0x0

 7239 23:02:55.325459  RD_PRE       = 0x0

 7240 23:02:55.325566  WR_PRE       = 0x1

 7241 23:02:55.328938  WR_PST       = 0x1

 7242 23:02:55.329018  DBI_WR       = 0x0

 7243 23:02:55.331966  DBI_RD       = 0x0

 7244 23:02:55.332047  OTF          = 0x1

 7245 23:02:55.335012  =================================== 

 7246 23:02:55.338596  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7247 23:02:55.345021  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7248 23:02:55.348322  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7249 23:02:55.351670  =================================== 

 7250 23:02:55.355235  LPDDR4 DRAM CONFIGURATION

 7251 23:02:55.358348  =================================== 

 7252 23:02:55.358430  EX_ROW_EN[0]    = 0x10

 7253 23:02:55.361829  EX_ROW_EN[1]    = 0x0

 7254 23:02:55.365255  LP4Y_EN      = 0x0

 7255 23:02:55.365348  WORK_FSP     = 0x1

 7256 23:02:55.368093  WL           = 0x5

 7257 23:02:55.368175  RL           = 0x5

 7258 23:02:55.371639  BL           = 0x2

 7259 23:02:55.371720  RPST         = 0x0

 7260 23:02:55.374715  RD_PRE       = 0x0

 7261 23:02:55.374796  WR_PRE       = 0x1

 7262 23:02:55.378344  WR_PST       = 0x1

 7263 23:02:55.378425  DBI_WR       = 0x0

 7264 23:02:55.381961  DBI_RD       = 0x0

 7265 23:02:55.382042  OTF          = 0x1

 7266 23:02:55.384996  =================================== 

 7267 23:02:55.391573  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7268 23:02:55.391677  ==

 7269 23:02:55.394664  Dram Type= 6, Freq= 0, CH_0, rank 0

 7270 23:02:55.398106  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7271 23:02:55.398188  ==

 7272 23:02:55.401147  [Duty_Offset_Calibration]

 7273 23:02:55.405034  	B0:2	B1:1	CA:1

 7274 23:02:55.405116  

 7275 23:02:55.407961  [DutyScan_Calibration_Flow] k_type=0

 7276 23:02:55.416460  

 7277 23:02:55.416543  ==CLK 0==

 7278 23:02:55.420095  Final CLK duty delay cell = 0

 7279 23:02:55.423694  [0] MAX Duty = 5187%(X100), DQS PI = 24

 7280 23:02:55.426565  [0] MIN Duty = 4876%(X100), DQS PI = 48

 7281 23:02:55.426646  [0] AVG Duty = 5031%(X100)

 7282 23:02:55.429842  

 7283 23:02:55.433507  CH0 CLK Duty spec in!! Max-Min= 311%

 7284 23:02:55.436548  [DutyScan_Calibration_Flow] ====Done====

 7285 23:02:55.436629  

 7286 23:02:55.439922  [DutyScan_Calibration_Flow] k_type=1

 7287 23:02:55.456048  

 7288 23:02:55.456132  ==DQS 0 ==

 7289 23:02:55.459496  Final DQS duty delay cell = -4

 7290 23:02:55.462619  [-4] MAX Duty = 5156%(X100), DQS PI = 24

 7291 23:02:55.466389  [-4] MIN Duty = 4688%(X100), DQS PI = 0

 7292 23:02:55.469157  [-4] AVG Duty = 4922%(X100)

 7293 23:02:55.469304  

 7294 23:02:55.469410  ==DQS 1 ==

 7295 23:02:55.472481  Final DQS duty delay cell = 0

 7296 23:02:55.476184  [0] MAX Duty = 5187%(X100), DQS PI = 10

 7297 23:02:55.478937  [0] MIN Duty = 5031%(X100), DQS PI = 30

 7298 23:02:55.482554  [0] AVG Duty = 5109%(X100)

 7299 23:02:55.482638  

 7300 23:02:55.485921  CH0 DQS 0 Duty spec in!! Max-Min= 468%

 7301 23:02:55.486003  

 7302 23:02:55.489086  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7303 23:02:55.492595  [DutyScan_Calibration_Flow] ====Done====

 7304 23:02:55.492675  

 7305 23:02:55.495580  [DutyScan_Calibration_Flow] k_type=3

 7306 23:02:55.513325  

 7307 23:02:55.513411  ==DQM 0 ==

 7308 23:02:55.516958  Final DQM duty delay cell = 0

 7309 23:02:55.520002  [0] MAX Duty = 5218%(X100), DQS PI = 34

 7310 23:02:55.523078  [0] MIN Duty = 4876%(X100), DQS PI = 60

 7311 23:02:55.526609  [0] AVG Duty = 5047%(X100)

 7312 23:02:55.526690  

 7313 23:02:55.526754  ==DQM 1 ==

 7314 23:02:55.530257  Final DQM duty delay cell = 0

 7315 23:02:55.533317  [0] MAX Duty = 5187%(X100), DQS PI = 2

 7316 23:02:55.536694  [0] MIN Duty = 5031%(X100), DQS PI = 50

 7317 23:02:55.539747  [0] AVG Duty = 5109%(X100)

 7318 23:02:55.539853  

 7319 23:02:55.543107  CH0 DQM 0 Duty spec in!! Max-Min= 342%

 7320 23:02:55.543188  

 7321 23:02:55.546380  CH0 DQM 1 Duty spec in!! Max-Min= 156%

 7322 23:02:55.549867  [DutyScan_Calibration_Flow] ====Done====

 7323 23:02:55.549948  

 7324 23:02:55.553048  [DutyScan_Calibration_Flow] k_type=2

 7325 23:02:55.570627  

 7326 23:02:55.570727  ==DQ 0 ==

 7327 23:02:55.573759  Final DQ duty delay cell = 0

 7328 23:02:55.577177  [0] MAX Duty = 5062%(X100), DQS PI = 24

 7329 23:02:55.580363  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7330 23:02:55.580446  [0] AVG Duty = 4984%(X100)

 7331 23:02:55.583522  

 7332 23:02:55.583604  ==DQ 1 ==

 7333 23:02:55.586930  Final DQ duty delay cell = 0

 7334 23:02:55.590541  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7335 23:02:55.594031  [0] MIN Duty = 4907%(X100), DQS PI = 34

 7336 23:02:55.594114  [0] AVG Duty = 5031%(X100)

 7337 23:02:55.594178  

 7338 23:02:55.596964  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7339 23:02:55.600585  

 7340 23:02:55.603738  CH0 DQ 1 Duty spec in!! Max-Min= 249%

 7341 23:02:55.607046  [DutyScan_Calibration_Flow] ====Done====

 7342 23:02:55.607129  ==

 7343 23:02:55.610170  Dram Type= 6, Freq= 0, CH_1, rank 0

 7344 23:02:55.613679  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7345 23:02:55.613762  ==

 7346 23:02:55.616770  [Duty_Offset_Calibration]

 7347 23:02:55.616852  	B0:1	B1:0	CA:0

 7348 23:02:55.616915  

 7349 23:02:55.620248  [DutyScan_Calibration_Flow] k_type=0

 7350 23:02:55.630090  

 7351 23:02:55.630170  ==CLK 0==

 7352 23:02:55.633161  Final CLK duty delay cell = -4

 7353 23:02:55.636698  [-4] MAX Duty = 4969%(X100), DQS PI = 22

 7354 23:02:55.639599  [-4] MIN Duty = 4844%(X100), DQS PI = 50

 7355 23:02:55.643134  [-4] AVG Duty = 4906%(X100)

 7356 23:02:55.643215  

 7357 23:02:55.646691  CH1 CLK Duty spec in!! Max-Min= 125%

 7358 23:02:55.649566  [DutyScan_Calibration_Flow] ====Done====

 7359 23:02:55.649660  

 7360 23:02:55.653077  [DutyScan_Calibration_Flow] k_type=1

 7361 23:02:55.670185  

 7362 23:02:55.670273  ==DQS 0 ==

 7363 23:02:55.673186  Final DQS duty delay cell = 0

 7364 23:02:55.676636  [0] MAX Duty = 5094%(X100), DQS PI = 16

 7365 23:02:55.680073  [0] MIN Duty = 4875%(X100), DQS PI = 0

 7366 23:02:55.680154  [0] AVG Duty = 4984%(X100)

 7367 23:02:55.683336  

 7368 23:02:55.683416  ==DQS 1 ==

 7369 23:02:55.686733  Final DQS duty delay cell = 0

 7370 23:02:55.689570  [0] MAX Duty = 5249%(X100), DQS PI = 16

 7371 23:02:55.693076  [0] MIN Duty = 4969%(X100), DQS PI = 8

 7372 23:02:55.696398  [0] AVG Duty = 5109%(X100)

 7373 23:02:55.696479  

 7374 23:02:55.699851  CH1 DQS 0 Duty spec in!! Max-Min= 219%

 7375 23:02:55.699936  

 7376 23:02:55.703215  CH1 DQS 1 Duty spec in!! Max-Min= 280%

 7377 23:02:55.706283  [DutyScan_Calibration_Flow] ====Done====

 7378 23:02:55.706364  

 7379 23:02:55.709889  [DutyScan_Calibration_Flow] k_type=3

 7380 23:02:55.726696  

 7381 23:02:55.726776  ==DQM 0 ==

 7382 23:02:55.730293  Final DQM duty delay cell = 0

 7383 23:02:55.733270  [0] MAX Duty = 5218%(X100), DQS PI = 18

 7384 23:02:55.736780  [0] MIN Duty = 4969%(X100), DQS PI = 48

 7385 23:02:55.739819  [0] AVG Duty = 5093%(X100)

 7386 23:02:55.739897  

 7387 23:02:55.739959  ==DQM 1 ==

 7388 23:02:55.743482  Final DQM duty delay cell = 0

 7389 23:02:55.746358  [0] MAX Duty = 5093%(X100), DQS PI = 16

 7390 23:02:55.749974  [0] MIN Duty = 4907%(X100), DQS PI = 32

 7391 23:02:55.752968  [0] AVG Duty = 5000%(X100)

 7392 23:02:55.753070  

 7393 23:02:55.756498  CH1 DQM 0 Duty spec in!! Max-Min= 249%

 7394 23:02:55.756569  

 7395 23:02:55.759714  CH1 DQM 1 Duty spec in!! Max-Min= 186%

 7396 23:02:55.763237  [DutyScan_Calibration_Flow] ====Done====

 7397 23:02:55.763340  

 7398 23:02:55.766177  [DutyScan_Calibration_Flow] k_type=2

 7399 23:02:55.782888  

 7400 23:02:55.783000  ==DQ 0 ==

 7401 23:02:55.786318  Final DQ duty delay cell = -4

 7402 23:02:55.789310  [-4] MAX Duty = 5062%(X100), DQS PI = 12

 7403 23:02:55.792781  [-4] MIN Duty = 4875%(X100), DQS PI = 46

 7404 23:02:55.796157  [-4] AVG Duty = 4968%(X100)

 7405 23:02:55.796259  

 7406 23:02:55.796348  ==DQ 1 ==

 7407 23:02:55.799475  Final DQ duty delay cell = 0

 7408 23:02:55.802970  [0] MAX Duty = 5124%(X100), DQS PI = 18

 7409 23:02:55.806115  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7410 23:02:55.806217  [0] AVG Duty = 5031%(X100)

 7411 23:02:55.809695  

 7412 23:02:55.813066  CH1 DQ 0 Duty spec in!! Max-Min= 187%

 7413 23:02:55.813167  

 7414 23:02:55.816333  CH1 DQ 1 Duty spec in!! Max-Min= 186%

 7415 23:02:55.819568  [DutyScan_Calibration_Flow] ====Done====

 7416 23:02:55.822803  nWR fixed to 30

 7417 23:02:55.822896  [ModeRegInit_LP4] CH0 RK0

 7418 23:02:55.826113  [ModeRegInit_LP4] CH0 RK1

 7419 23:02:55.829780  [ModeRegInit_LP4] CH1 RK0

 7420 23:02:55.832875  [ModeRegInit_LP4] CH1 RK1

 7421 23:02:55.832982  match AC timing 5

 7422 23:02:55.836691  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7423 23:02:55.843295  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7424 23:02:55.846226  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7425 23:02:55.849770  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7426 23:02:55.856095  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7427 23:02:55.856195  [MiockJmeterHQA]

 7428 23:02:55.856287  

 7429 23:02:55.859671  [DramcMiockJmeter] u1RxGatingPI = 0

 7430 23:02:55.863223  0 : 4252, 4027

 7431 23:02:55.863327  4 : 4252, 4027

 7432 23:02:55.863420  8 : 4253, 4026

 7433 23:02:55.866300  12 : 4253, 4027

 7434 23:02:55.866401  16 : 4252, 4027

 7435 23:02:55.869442  20 : 4363, 4137

 7436 23:02:55.869545  24 : 4253, 4026

 7437 23:02:55.873062  28 : 4363, 4138

 7438 23:02:55.873179  32 : 4253, 4026

 7439 23:02:55.876220  36 : 4253, 4027

 7440 23:02:55.876357  40 : 4252, 4027

 7441 23:02:55.876449  44 : 4255, 4029

 7442 23:02:55.879895  48 : 4363, 4137

 7443 23:02:55.879989  52 : 4252, 4027

 7444 23:02:55.883021  56 : 4363, 4138

 7445 23:02:55.883126  60 : 4249, 4027

 7446 23:02:55.886525  64 : 4250, 4027

 7447 23:02:55.886631  68 : 4249, 4027

 7448 23:02:55.886747  72 : 4361, 4137

 7449 23:02:55.889829  76 : 4250, 4026

 7450 23:02:55.889942  80 : 4361, 4137

 7451 23:02:55.892839  84 : 4250, 4025

 7452 23:02:55.892922  88 : 4250, 94

 7453 23:02:55.896366  92 : 4252, 0

 7454 23:02:55.896463  96 : 4365, 0

 7455 23:02:55.896527  100 : 4250, 0

 7456 23:02:55.899431  104 : 4250, 0

 7457 23:02:55.899512  108 : 4252, 0

 7458 23:02:55.899576  112 : 4360, 0

 7459 23:02:55.903024  116 : 4250, 0

 7460 23:02:55.903134  120 : 4250, 0

 7461 23:02:55.906349  124 : 4250, 0

 7462 23:02:55.906467  128 : 4250, 0

 7463 23:02:55.906535  132 : 4363, 0

 7464 23:02:55.909938  136 : 4250, 0

 7465 23:02:55.910033  140 : 4249, 0

 7466 23:02:55.912804  144 : 4361, 0

 7467 23:02:55.912884  148 : 4250, 0

 7468 23:02:55.912947  152 : 4250, 0

 7469 23:02:55.916132  156 : 4250, 0

 7470 23:02:55.916213  160 : 4253, 0

 7471 23:02:55.919544  164 : 4360, 0

 7472 23:02:55.919624  168 : 4250, 0

 7473 23:02:55.919689  172 : 4250, 0

 7474 23:02:55.922822  176 : 4250, 0

 7475 23:02:55.922903  180 : 4360, 0

 7476 23:02:55.922967  184 : 4361, 0

 7477 23:02:55.926385  188 : 4250, 0

 7478 23:02:55.926465  192 : 4251, 0

 7479 23:02:55.929614  196 : 4250, 0

 7480 23:02:55.929726  200 : 4253, 0

 7481 23:02:55.929812  204 : 4250, 1258

 7482 23:02:55.933163  208 : 4250, 3999

 7483 23:02:55.933243  212 : 4250, 4026

 7484 23:02:55.936421  216 : 4250, 4027

 7485 23:02:55.936501  220 : 4250, 4027

 7486 23:02:55.939744  224 : 4253, 4026

 7487 23:02:55.939825  228 : 4253, 4029

 7488 23:02:55.942986  232 : 4250, 4027

 7489 23:02:55.943066  236 : 4361, 4138

 7490 23:02:55.946054  240 : 4360, 4137

 7491 23:02:55.946135  244 : 4250, 4026

 7492 23:02:55.949537  248 : 4363, 4140

 7493 23:02:55.949670  252 : 4250, 4027

 7494 23:02:55.952736  256 : 4249, 4027

 7495 23:02:55.952821  260 : 4250, 4026

 7496 23:02:55.952911  264 : 4253, 4029

 7497 23:02:55.956233  268 : 4250, 4027

 7498 23:02:55.956330  272 : 4250, 4027

 7499 23:02:55.959769  276 : 4250, 4026

 7500 23:02:55.959867  280 : 4253, 4029

 7501 23:02:55.962665  284 : 4250, 4027

 7502 23:02:55.962762  288 : 4360, 4138

 7503 23:02:55.966356  292 : 4361, 4137

 7504 23:02:55.966482  296 : 4250, 4027

 7505 23:02:55.969344  300 : 4363, 4139

 7506 23:02:55.969454  304 : 4250, 4027

 7507 23:02:55.972524  308 : 4249, 3978

 7508 23:02:55.972622  312 : 4250, 2131

 7509 23:02:55.972718  316 : 4253, 7

 7510 23:02:55.976144  

 7511 23:02:55.976266  	MIOCK jitter meter	ch=0

 7512 23:02:55.976374  

 7513 23:02:55.979221  1T = (316-88) = 228 dly cells

 7514 23:02:55.986356  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps

 7515 23:02:55.986453  ==

 7516 23:02:55.989433  Dram Type= 6, Freq= 0, CH_0, rank 0

 7517 23:02:55.992911  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7518 23:02:55.993008  ==

 7519 23:02:55.999471  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7520 23:02:56.002910  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7521 23:02:56.006003  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7522 23:02:56.012514  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7523 23:02:56.021559  [CA 0] Center 43 (13~73) winsize 61

 7524 23:02:56.025051  [CA 1] Center 43 (12~74) winsize 63

 7525 23:02:56.028572  [CA 2] Center 38 (8~68) winsize 61

 7526 23:02:56.031594  [CA 3] Center 37 (8~67) winsize 60

 7527 23:02:56.035061  [CA 4] Center 36 (7~66) winsize 60

 7528 23:02:56.038682  [CA 5] Center 35 (6~65) winsize 60

 7529 23:02:56.038780  

 7530 23:02:56.041387  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7531 23:02:56.041484  

 7532 23:02:56.044929  [CATrainingPosCal] consider 1 rank data

 7533 23:02:56.048020  u2DelayCellTimex100 = 285/100 ps

 7534 23:02:56.051358  CA0 delay=43 (13~73),Diff = 8 PI (27 cell)

 7535 23:02:56.058203  CA1 delay=43 (12~74),Diff = 8 PI (27 cell)

 7536 23:02:56.061674  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7537 23:02:56.064575  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7538 23:02:56.068289  CA4 delay=36 (7~66),Diff = 1 PI (3 cell)

 7539 23:02:56.071307  CA5 delay=35 (6~65),Diff = 0 PI (0 cell)

 7540 23:02:56.071405  

 7541 23:02:56.074921  CA PerBit enable=1, Macro0, CA PI delay=35

 7542 23:02:56.075001  

 7543 23:02:56.077945  [CBTSetCACLKResult] CA Dly = 35

 7544 23:02:56.081721  CS Dly: 9 (0~40)

 7545 23:02:56.084718  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7546 23:02:56.088470  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7547 23:02:56.088551  ==

 7548 23:02:56.091328  Dram Type= 6, Freq= 0, CH_0, rank 1

 7549 23:02:56.094856  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7550 23:02:56.097870  ==

 7551 23:02:56.101382  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7552 23:02:56.105073  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7553 23:02:56.111341  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7554 23:02:56.114711  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7555 23:02:56.124813  [CA 0] Center 42 (12~73) winsize 62

 7556 23:02:56.128373  [CA 1] Center 42 (12~73) winsize 62

 7557 23:02:56.131699  [CA 2] Center 37 (8~67) winsize 60

 7558 23:02:56.134822  [CA 3] Center 38 (8~68) winsize 61

 7559 23:02:56.138188  [CA 4] Center 35 (5~65) winsize 61

 7560 23:02:56.141798  [CA 5] Center 35 (5~65) winsize 61

 7561 23:02:56.141896  

 7562 23:02:56.144883  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7563 23:02:56.144964  

 7564 23:02:56.148153  [CATrainingPosCal] consider 2 rank data

 7565 23:02:56.151626  u2DelayCellTimex100 = 285/100 ps

 7566 23:02:56.154723  CA0 delay=43 (13~73),Diff = 8 PI (27 cell)

 7567 23:02:56.161944  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7568 23:02:56.164799  CA2 delay=37 (8~67),Diff = 2 PI (6 cell)

 7569 23:02:56.168072  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7570 23:02:56.171369  CA4 delay=36 (7~65),Diff = 1 PI (3 cell)

 7571 23:02:56.174823  CA5 delay=35 (6~65),Diff = 0 PI (0 cell)

 7572 23:02:56.174921  

 7573 23:02:56.177944  CA PerBit enable=1, Macro0, CA PI delay=35

 7574 23:02:56.178040  

 7575 23:02:56.181709  [CBTSetCACLKResult] CA Dly = 35

 7576 23:02:56.184606  CS Dly: 10 (0~42)

 7577 23:02:56.188122  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7578 23:02:56.191774  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7579 23:02:56.191882  

 7580 23:02:56.194749  ----->DramcWriteLeveling(PI) begin...

 7581 23:02:56.194851  ==

 7582 23:02:56.197863  Dram Type= 6, Freq= 0, CH_0, rank 0

 7583 23:02:56.201341  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7584 23:02:56.204902  ==

 7585 23:02:56.205000  Write leveling (Byte 0): 35 => 35

 7586 23:02:56.207735  Write leveling (Byte 1): 27 => 27

 7587 23:02:56.211440  DramcWriteLeveling(PI) end<-----

 7588 23:02:56.211536  

 7589 23:02:56.211614  ==

 7590 23:02:56.215103  Dram Type= 6, Freq= 0, CH_0, rank 0

 7591 23:02:56.221019  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7592 23:02:56.221114  ==

 7593 23:02:56.224908  [Gating] SW mode calibration

 7594 23:02:56.231273  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7595 23:02:56.234793  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7596 23:02:56.241348   1  4  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7597 23:02:56.244542   1  4  4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)

 7598 23:02:56.248201   1  4  8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 7599 23:02:56.254525   1  4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)

 7600 23:02:56.257832   1  4 16 | B1->B0 | 2323 3636 | 0 1 | (0 0) (1 1)

 7601 23:02:56.260907   1  4 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 7602 23:02:56.264436   1  4 24 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)

 7603 23:02:56.271229   1  4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)

 7604 23:02:56.274616   1  5  0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)

 7605 23:02:56.277928   1  5  4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)

 7606 23:02:56.284623   1  5  8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)

 7607 23:02:56.287753   1  5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)

 7608 23:02:56.291458   1  5 16 | B1->B0 | 3434 2424 | 1 0 | (1 0) (0 0)

 7609 23:02:56.297616   1  5 20 | B1->B0 | 2727 2525 | 0 0 | (1 0) (0 0)

 7610 23:02:56.300790   1  5 24 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)

 7611 23:02:56.304292   1  5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 7612 23:02:56.310999   1  6  0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 7613 23:02:56.314536   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7614 23:02:56.317562   1  6  8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

 7615 23:02:56.324066   1  6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)

 7616 23:02:56.327523   1  6 16 | B1->B0 | 2a2a 4645 | 0 1 | (0 0) (0 0)

 7617 23:02:56.330938   1  6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 7618 23:02:56.337427   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7619 23:02:56.340718   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7620 23:02:56.344408   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7621 23:02:56.350972   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7622 23:02:56.353960   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7623 23:02:56.357422   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7624 23:02:56.364387   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7625 23:02:56.367665   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7626 23:02:56.370918   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7627 23:02:56.377342   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7628 23:02:56.380434   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7629 23:02:56.384057   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7630 23:02:56.390827   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7631 23:02:56.393762   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7632 23:02:56.397396   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7633 23:02:56.403910   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7634 23:02:56.407215   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7635 23:02:56.410519   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7636 23:02:56.416988   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7637 23:02:56.420786   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7638 23:02:56.423611   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7639 23:02:56.430370   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7640 23:02:56.434169   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7641 23:02:56.437291  Total UI for P1: 0, mck2ui 16

 7642 23:02:56.440215  best dqsien dly found for B0: ( 1,  9, 10)

 7643 23:02:56.443811   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7644 23:02:56.446686   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7645 23:02:56.450467  Total UI for P1: 0, mck2ui 16

 7646 23:02:56.453449  best dqsien dly found for B1: ( 1,  9, 18)

 7647 23:02:56.457078  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7648 23:02:56.460535  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 7649 23:02:56.463506  

 7650 23:02:56.467008  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7651 23:02:56.469924  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7652 23:02:56.473346  [Gating] SW calibration Done

 7653 23:02:56.473485  ==

 7654 23:02:56.476962  Dram Type= 6, Freq= 0, CH_0, rank 0

 7655 23:02:56.479914  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7656 23:02:56.480025  ==

 7657 23:02:56.483574  RX Vref Scan: 0

 7658 23:02:56.483656  

 7659 23:02:56.483719  RX Vref 0 -> 0, step: 1

 7660 23:02:56.483778  

 7661 23:02:56.487113  RX Delay 0 -> 252, step: 8

 7662 23:02:56.490023  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7663 23:02:56.493722  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7664 23:02:56.500297  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7665 23:02:56.503672  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 7666 23:02:56.506644  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7667 23:02:56.510408  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7668 23:02:56.513466  iDelay=200, Bit 6, Center 143 (96 ~ 191) 96

 7669 23:02:56.519865  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7670 23:02:56.523456  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7671 23:02:56.527036  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 7672 23:02:56.530181  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7673 23:02:56.533181  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7674 23:02:56.540032  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 7675 23:02:56.543059  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 7676 23:02:56.546625  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7677 23:02:56.549758  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7678 23:02:56.549860  ==

 7679 23:02:56.553527  Dram Type= 6, Freq= 0, CH_0, rank 0

 7680 23:02:56.556471  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7681 23:02:56.559631  ==

 7682 23:02:56.559746  DQS Delay:

 7683 23:02:56.559853  DQS0 = 0, DQS1 = 0

 7684 23:02:56.563267  DQM Delay:

 7685 23:02:56.563370  DQM0 = 136, DQM1 = 129

 7686 23:02:56.566435  DQ Delay:

 7687 23:02:56.569618  DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135

 7688 23:02:56.573302  DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143

 7689 23:02:56.576593  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123

 7690 23:02:56.579729  DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135

 7691 23:02:56.579833  

 7692 23:02:56.579925  

 7693 23:02:56.580011  ==

 7694 23:02:56.583188  Dram Type= 6, Freq= 0, CH_0, rank 0

 7695 23:02:56.586118  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7696 23:02:56.589676  ==

 7697 23:02:56.589779  

 7698 23:02:56.589870  

 7699 23:02:56.589956  	TX Vref Scan disable

 7700 23:02:56.593103   == TX Byte 0 ==

 7701 23:02:56.596373  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 7702 23:02:56.599902  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7703 23:02:56.602985   == TX Byte 1 ==

 7704 23:02:56.606469  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7705 23:02:56.609357  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 7706 23:02:56.609479  ==

 7707 23:02:56.612793  Dram Type= 6, Freq= 0, CH_0, rank 0

 7708 23:02:56.619755  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7709 23:02:56.619851  ==

 7710 23:02:56.631853  

 7711 23:02:56.635669  TX Vref early break, caculate TX vref

 7712 23:02:56.638798  TX Vref=16, minBit 0, minWin=23, winSum=379

 7713 23:02:56.641837  TX Vref=18, minBit 0, minWin=23, winSum=388

 7714 23:02:56.645420  TX Vref=20, minBit 0, minWin=24, winSum=402

 7715 23:02:56.648932  TX Vref=22, minBit 0, minWin=24, winSum=407

 7716 23:02:56.652072  TX Vref=24, minBit 1, minWin=25, winSum=414

 7717 23:02:56.658670  TX Vref=26, minBit 1, minWin=25, winSum=423

 7718 23:02:56.661780  TX Vref=28, minBit 3, minWin=25, winSum=425

 7719 23:02:56.664927  TX Vref=30, minBit 0, minWin=24, winSum=411

 7720 23:02:56.668455  TX Vref=32, minBit 1, minWin=23, winSum=405

 7721 23:02:56.672188  TX Vref=34, minBit 6, minWin=23, winSum=394

 7722 23:02:56.678630  [TxChooseVref] Worse bit 3, Min win 25, Win sum 425, Final Vref 28

 7723 23:02:56.678738  

 7724 23:02:56.681927  Final TX Range 0 Vref 28

 7725 23:02:56.682003  

 7726 23:02:56.682069  ==

 7727 23:02:56.685301  Dram Type= 6, Freq= 0, CH_0, rank 0

 7728 23:02:56.688426  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7729 23:02:56.688529  ==

 7730 23:02:56.688625  

 7731 23:02:56.688720  

 7732 23:02:56.691609  	TX Vref Scan disable

 7733 23:02:56.698225  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 7734 23:02:56.698341   == TX Byte 0 ==

 7735 23:02:56.701590  u2DelayCellOfst[0]=10 cells (3 PI)

 7736 23:02:56.704963  u2DelayCellOfst[1]=17 cells (5 PI)

 7737 23:02:56.708702  u2DelayCellOfst[2]=13 cells (4 PI)

 7738 23:02:56.711908  u2DelayCellOfst[3]=10 cells (3 PI)

 7739 23:02:56.715300  u2DelayCellOfst[4]=6 cells (2 PI)

 7740 23:02:56.718353  u2DelayCellOfst[5]=0 cells (0 PI)

 7741 23:02:56.721911  u2DelayCellOfst[6]=17 cells (5 PI)

 7742 23:02:56.721984  u2DelayCellOfst[7]=17 cells (5 PI)

 7743 23:02:56.728701  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7744 23:02:56.732033  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7745 23:02:56.735160   == TX Byte 1 ==

 7746 23:02:56.735235  u2DelayCellOfst[8]=0 cells (0 PI)

 7747 23:02:56.738497  u2DelayCellOfst[9]=3 cells (1 PI)

 7748 23:02:56.741544  u2DelayCellOfst[10]=10 cells (3 PI)

 7749 23:02:56.745306  u2DelayCellOfst[11]=6 cells (2 PI)

 7750 23:02:56.748912  u2DelayCellOfst[12]=10 cells (3 PI)

 7751 23:02:56.751965  u2DelayCellOfst[13]=13 cells (4 PI)

 7752 23:02:56.755086  u2DelayCellOfst[14]=17 cells (5 PI)

 7753 23:02:56.758629  u2DelayCellOfst[15]=10 cells (3 PI)

 7754 23:02:56.761597  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 7755 23:02:56.768259  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 7756 23:02:56.768365  DramC Write-DBI on

 7757 23:02:56.768467  ==

 7758 23:02:56.771970  Dram Type= 6, Freq= 0, CH_0, rank 0

 7759 23:02:56.775014  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7760 23:02:56.778561  ==

 7761 23:02:56.778666  

 7762 23:02:56.778767  

 7763 23:02:56.778867  	TX Vref Scan disable

 7764 23:02:56.781799   == TX Byte 0 ==

 7765 23:02:56.784780  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 7766 23:02:56.788478   == TX Byte 1 ==

 7767 23:02:56.791637  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 7768 23:02:56.795185  DramC Write-DBI off

 7769 23:02:56.795291  

 7770 23:02:56.795395  [DATLAT]

 7771 23:02:56.795493  Freq=1600, CH0 RK0

 7772 23:02:56.795593  

 7773 23:02:56.798063  DATLAT Default: 0xf

 7774 23:02:56.798166  0, 0xFFFF, sum = 0

 7775 23:02:56.801632  1, 0xFFFF, sum = 0

 7776 23:02:56.804823  2, 0xFFFF, sum = 0

 7777 23:02:56.804927  3, 0xFFFF, sum = 0

 7778 23:02:56.808389  4, 0xFFFF, sum = 0

 7779 23:02:56.808493  5, 0xFFFF, sum = 0

 7780 23:02:56.811684  6, 0xFFFF, sum = 0

 7781 23:02:56.811803  7, 0xFFFF, sum = 0

 7782 23:02:56.815089  8, 0xFFFF, sum = 0

 7783 23:02:56.815195  9, 0xFFFF, sum = 0

 7784 23:02:56.818270  10, 0xFFFF, sum = 0

 7785 23:02:56.818401  11, 0xFFFF, sum = 0

 7786 23:02:56.821420  12, 0xFFFF, sum = 0

 7787 23:02:56.821525  13, 0xFFFF, sum = 0

 7788 23:02:56.824571  14, 0x0, sum = 1

 7789 23:02:56.824658  15, 0x0, sum = 2

 7790 23:02:56.828048  16, 0x0, sum = 3

 7791 23:02:56.828160  17, 0x0, sum = 4

 7792 23:02:56.831765  best_step = 15

 7793 23:02:56.831885  

 7794 23:02:56.831947  ==

 7795 23:02:56.834639  Dram Type= 6, Freq= 0, CH_0, rank 0

 7796 23:02:56.838461  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7797 23:02:56.838536  ==

 7798 23:02:56.841376  RX Vref Scan: 1

 7799 23:02:56.841482  

 7800 23:02:56.841595  Set Vref Range= 24 -> 127

 7801 23:02:56.841704  

 7802 23:02:56.844942  RX Vref 24 -> 127, step: 1

 7803 23:02:56.845046  

 7804 23:02:56.848270  RX Delay 19 -> 252, step: 4

 7805 23:02:56.848391  

 7806 23:02:56.851493  Set Vref, RX VrefLevel [Byte0]: 24

 7807 23:02:56.854956                           [Byte1]: 24

 7808 23:02:56.855037  

 7809 23:02:56.858163  Set Vref, RX VrefLevel [Byte0]: 25

 7810 23:02:56.861748                           [Byte1]: 25

 7811 23:02:56.861899  

 7812 23:02:56.864745  Set Vref, RX VrefLevel [Byte0]: 26

 7813 23:02:56.868379                           [Byte1]: 26

 7814 23:02:56.872219  

 7815 23:02:56.872318  Set Vref, RX VrefLevel [Byte0]: 27

 7816 23:02:56.875393                           [Byte1]: 27

 7817 23:02:56.879807  

 7818 23:02:56.879916  Set Vref, RX VrefLevel [Byte0]: 28

 7819 23:02:56.882891                           [Byte1]: 28

 7820 23:02:56.887397  

 7821 23:02:56.887512  Set Vref, RX VrefLevel [Byte0]: 29

 7822 23:02:56.890493                           [Byte1]: 29

 7823 23:02:56.894870  

 7824 23:02:56.894943  Set Vref, RX VrefLevel [Byte0]: 30

 7825 23:02:56.897868                           [Byte1]: 30

 7826 23:02:56.902166  

 7827 23:02:56.902249  Set Vref, RX VrefLevel [Byte0]: 31

 7828 23:02:56.905380                           [Byte1]: 31

 7829 23:02:56.909752  

 7830 23:02:56.909831  Set Vref, RX VrefLevel [Byte0]: 32

 7831 23:02:56.913390                           [Byte1]: 32

 7832 23:02:56.917774  

 7833 23:02:56.917848  Set Vref, RX VrefLevel [Byte0]: 33

 7834 23:02:56.920638                           [Byte1]: 33

 7835 23:02:56.924930  

 7836 23:02:56.925035  Set Vref, RX VrefLevel [Byte0]: 34

 7837 23:02:56.928158                           [Byte1]: 34

 7838 23:02:56.932729  

 7839 23:02:56.932831  Set Vref, RX VrefLevel [Byte0]: 35

 7840 23:02:56.936191                           [Byte1]: 35

 7841 23:02:56.940286  

 7842 23:02:56.940386  Set Vref, RX VrefLevel [Byte0]: 36

 7843 23:02:56.943690                           [Byte1]: 36

 7844 23:02:56.947661  

 7845 23:02:56.947763  Set Vref, RX VrefLevel [Byte0]: 37

 7846 23:02:56.951194                           [Byte1]: 37

 7847 23:02:56.955418  

 7848 23:02:56.955536  Set Vref, RX VrefLevel [Byte0]: 38

 7849 23:02:56.958311                           [Byte1]: 38

 7850 23:02:56.963121  

 7851 23:02:56.963226  Set Vref, RX VrefLevel [Byte0]: 39

 7852 23:02:56.965948                           [Byte1]: 39

 7853 23:02:56.970595  

 7854 23:02:56.970707  Set Vref, RX VrefLevel [Byte0]: 40

 7855 23:02:56.973958                           [Byte1]: 40

 7856 23:02:56.978371  

 7857 23:02:56.978447  Set Vref, RX VrefLevel [Byte0]: 41

 7858 23:02:56.981012                           [Byte1]: 41

 7859 23:02:56.985405  

 7860 23:02:56.985514  Set Vref, RX VrefLevel [Byte0]: 42

 7861 23:02:56.989070                           [Byte1]: 42

 7862 23:02:56.993312  

 7863 23:02:56.993415  Set Vref, RX VrefLevel [Byte0]: 43

 7864 23:02:56.996375                           [Byte1]: 43

 7865 23:02:57.000770  

 7866 23:02:57.000870  Set Vref, RX VrefLevel [Byte0]: 44

 7867 23:02:57.004342                           [Byte1]: 44

 7868 23:02:57.008075  

 7869 23:02:57.008191  Set Vref, RX VrefLevel [Byte0]: 45

 7870 23:02:57.011757                           [Byte1]: 45

 7871 23:02:57.015902  

 7872 23:02:57.016005  Set Vref, RX VrefLevel [Byte0]: 46

 7873 23:02:57.019076                           [Byte1]: 46

 7874 23:02:57.023769  

 7875 23:02:57.023882  Set Vref, RX VrefLevel [Byte0]: 47

 7876 23:02:57.027022                           [Byte1]: 47

 7877 23:02:57.031268  

 7878 23:02:57.031372  Set Vref, RX VrefLevel [Byte0]: 48

 7879 23:02:57.034556                           [Byte1]: 48

 7880 23:02:57.038946  

 7881 23:02:57.039049  Set Vref, RX VrefLevel [Byte0]: 49

 7882 23:02:57.042019                           [Byte1]: 49

 7883 23:02:57.046110  

 7884 23:02:57.046214  Set Vref, RX VrefLevel [Byte0]: 50

 7885 23:02:57.049639                           [Byte1]: 50

 7886 23:02:57.053656  

 7887 23:02:57.053736  Set Vref, RX VrefLevel [Byte0]: 51

 7888 23:02:57.056905                           [Byte1]: 51

 7889 23:02:57.061008  

 7890 23:02:57.061112  Set Vref, RX VrefLevel [Byte0]: 52

 7891 23:02:57.064676                           [Byte1]: 52

 7892 23:02:57.068768  

 7893 23:02:57.068872  Set Vref, RX VrefLevel [Byte0]: 53

 7894 23:02:57.072244                           [Byte1]: 53

 7895 23:02:57.076275  

 7896 23:02:57.076392  Set Vref, RX VrefLevel [Byte0]: 54

 7897 23:02:57.079746                           [Byte1]: 54

 7898 23:02:57.083926  

 7899 23:02:57.084039  Set Vref, RX VrefLevel [Byte0]: 55

 7900 23:02:57.087669                           [Byte1]: 55

 7901 23:02:57.091987  

 7902 23:02:57.092118  Set Vref, RX VrefLevel [Byte0]: 56

 7903 23:02:57.095027                           [Byte1]: 56

 7904 23:02:57.099357  

 7905 23:02:57.099466  Set Vref, RX VrefLevel [Byte0]: 57

 7906 23:02:57.102552                           [Byte1]: 57

 7907 23:02:57.106638  

 7908 23:02:57.106741  Set Vref, RX VrefLevel [Byte0]: 58

 7909 23:02:57.110140                           [Byte1]: 58

 7910 23:02:57.114160  

 7911 23:02:57.114265  Set Vref, RX VrefLevel [Byte0]: 59

 7912 23:02:57.117910                           [Byte1]: 59

 7913 23:02:57.121996  

 7914 23:02:57.122103  Set Vref, RX VrefLevel [Byte0]: 60

 7915 23:02:57.125461                           [Byte1]: 60

 7916 23:02:57.129681  

 7917 23:02:57.129763  Set Vref, RX VrefLevel [Byte0]: 61

 7918 23:02:57.133012                           [Byte1]: 61

 7919 23:02:57.136902  

 7920 23:02:57.137013  Set Vref, RX VrefLevel [Byte0]: 62

 7921 23:02:57.140431                           [Byte1]: 62

 7922 23:02:57.144609  

 7923 23:02:57.144715  Set Vref, RX VrefLevel [Byte0]: 63

 7924 23:02:57.147614                           [Byte1]: 63

 7925 23:02:57.152070  

 7926 23:02:57.152169  Set Vref, RX VrefLevel [Byte0]: 64

 7927 23:02:57.155649                           [Byte1]: 64

 7928 23:02:57.160024  

 7929 23:02:57.160126  Set Vref, RX VrefLevel [Byte0]: 65

 7930 23:02:57.163475                           [Byte1]: 65

 7931 23:02:57.167432  

 7932 23:02:57.167543  Set Vref, RX VrefLevel [Byte0]: 66

 7933 23:02:57.170372                           [Byte1]: 66

 7934 23:02:57.174648  

 7935 23:02:57.174747  Set Vref, RX VrefLevel [Byte0]: 67

 7936 23:02:57.178111                           [Byte1]: 67

 7937 23:02:57.182287  

 7938 23:02:57.182389  Set Vref, RX VrefLevel [Byte0]: 68

 7939 23:02:57.185733                           [Byte1]: 68

 7940 23:02:57.189965  

 7941 23:02:57.190068  Set Vref, RX VrefLevel [Byte0]: 69

 7942 23:02:57.193332                           [Byte1]: 69

 7943 23:02:57.197775  

 7944 23:02:57.197856  Set Vref, RX VrefLevel [Byte0]: 70

 7945 23:02:57.200772                           [Byte1]: 70

 7946 23:02:57.205012  

 7947 23:02:57.205115  Set Vref, RX VrefLevel [Byte0]: 71

 7948 23:02:57.208185                           [Byte1]: 71

 7949 23:02:57.212904  

 7950 23:02:57.213013  Set Vref, RX VrefLevel [Byte0]: 72

 7951 23:02:57.215896                           [Byte1]: 72

 7952 23:02:57.220316  

 7953 23:02:57.220422  Set Vref, RX VrefLevel [Byte0]: 73

 7954 23:02:57.223409                           [Byte1]: 73

 7955 23:02:57.227942  

 7956 23:02:57.228042  Set Vref, RX VrefLevel [Byte0]: 74

 7957 23:02:57.231243                           [Byte1]: 74

 7958 23:02:57.235504  

 7959 23:02:57.235600  Set Vref, RX VrefLevel [Byte0]: 75

 7960 23:02:57.238560                           [Byte1]: 75

 7961 23:02:57.243163  

 7962 23:02:57.243267  Final RX Vref Byte 0 = 56 to rank0

 7963 23:02:57.246481  Final RX Vref Byte 1 = 61 to rank0

 7964 23:02:57.249533  Final RX Vref Byte 0 = 56 to rank1

 7965 23:02:57.253412  Final RX Vref Byte 1 = 61 to rank1==

 7966 23:02:57.256745  Dram Type= 6, Freq= 0, CH_0, rank 0

 7967 23:02:57.262912  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7968 23:02:57.263010  ==

 7969 23:02:57.263103  DQS Delay:

 7970 23:02:57.263189  DQS0 = 0, DQS1 = 0

 7971 23:02:57.266557  DQM Delay:

 7972 23:02:57.266655  DQM0 = 133, DQM1 = 127

 7973 23:02:57.269531  DQ Delay:

 7974 23:02:57.272751  DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130

 7975 23:02:57.276655  DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138

 7976 23:02:57.279811  DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120

 7977 23:02:57.282659  DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134

 7978 23:02:57.282758  

 7979 23:02:57.282846  

 7980 23:02:57.282931  

 7981 23:02:57.286333  [DramC_TX_OE_Calibration] TA2

 7982 23:02:57.289354  Original DQ_B0 (3 6) =30, OEN = 27

 7983 23:02:57.292877  Original DQ_B1 (3 6) =30, OEN = 27

 7984 23:02:57.295851  24, 0x0, End_B0=24 End_B1=24

 7985 23:02:57.295960  25, 0x0, End_B0=25 End_B1=25

 7986 23:02:57.299218  26, 0x0, End_B0=26 End_B1=26

 7987 23:02:57.303073  27, 0x0, End_B0=27 End_B1=27

 7988 23:02:57.305918  28, 0x0, End_B0=28 End_B1=28

 7989 23:02:57.305991  29, 0x0, End_B0=29 End_B1=29

 7990 23:02:57.309309  30, 0x0, End_B0=30 End_B1=30

 7991 23:02:57.313112  31, 0x4141, End_B0=30 End_B1=30

 7992 23:02:57.316317  Byte0 end_step=30  best_step=27

 7993 23:02:57.319370  Byte1 end_step=30  best_step=27

 7994 23:02:57.323083  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7995 23:02:57.326332  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7996 23:02:57.326435  

 7997 23:02:57.326527  

 7998 23:02:57.333047  [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 7999 23:02:57.336173  CH0 RK0: MR19=303, MR18=2520

 8000 23:02:57.342378  CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16

 8001 23:02:57.342459  

 8002 23:02:57.346006  ----->DramcWriteLeveling(PI) begin...

 8003 23:02:57.346108  ==

 8004 23:02:57.349050  Dram Type= 6, Freq= 0, CH_0, rank 1

 8005 23:02:57.352881  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8006 23:02:57.352978  ==

 8007 23:02:57.356102  Write leveling (Byte 0): 37 => 37

 8008 23:02:57.359049  Write leveling (Byte 1): 28 => 28

 8009 23:02:57.362750  DramcWriteLeveling(PI) end<-----

 8010 23:02:57.362848  

 8011 23:02:57.362939  ==

 8012 23:02:57.365879  Dram Type= 6, Freq= 0, CH_0, rank 1

 8013 23:02:57.368764  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8014 23:02:57.368859  ==

 8015 23:02:57.372386  [Gating] SW mode calibration

 8016 23:02:57.378953  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8017 23:02:57.385453  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8018 23:02:57.389000   1  4  0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)

 8019 23:02:57.395551   1  4  4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)

 8020 23:02:57.399251   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8021 23:02:57.402328   1  4 12 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)

 8022 23:02:57.408784   1  4 16 | B1->B0 | 3030 3535 | 0 1 | (0 0) (1 1)

 8023 23:02:57.411690   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8024 23:02:57.415167   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8025 23:02:57.419025   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8026 23:02:57.425248   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8027 23:02:57.428454   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)

 8028 23:02:57.432108   1  5  8 | B1->B0 | 3434 3939 | 1 1 | (1 1) (0 0)

 8029 23:02:57.438482   1  5 12 | B1->B0 | 3434 3636 | 1 0 | (1 0) (0 1)

 8030 23:02:57.441879   1  5 16 | B1->B0 | 2f2f 2e2d | 0 1 | (0 1) (1 0)

 8031 23:02:57.445460   1  5 20 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)

 8032 23:02:57.451664   1  5 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)

 8033 23:02:57.455425   1  5 28 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)

 8034 23:02:57.458522   1  6  0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)

 8035 23:02:57.464912   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8036 23:02:57.468704   1  6  8 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)

 8037 23:02:57.471857   1  6 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)

 8038 23:02:57.478569   1  6 16 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)

 8039 23:02:57.481669   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8040 23:02:57.484737   1  6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 8041 23:02:57.491586   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8042 23:02:57.495146   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8043 23:02:57.498210   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8044 23:02:57.504763   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8045 23:02:57.508470   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8046 23:02:57.511507   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8047 23:02:57.518293   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8048 23:02:57.521725   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8049 23:02:57.524794   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8050 23:02:57.531401   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8051 23:02:57.534698   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8052 23:02:57.538115   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8053 23:02:57.544766   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8054 23:02:57.547830   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8055 23:02:57.551522   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8056 23:02:57.558034   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8057 23:02:57.561023   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8058 23:02:57.564870   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8059 23:02:57.571348   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8060 23:02:57.574411   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8061 23:02:57.578085   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8062 23:02:57.584923   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8063 23:02:57.587967   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8064 23:02:57.590966  Total UI for P1: 0, mck2ui 16

 8065 23:02:57.594179  best dqsien dly found for B0: ( 1,  9, 14)

 8066 23:02:57.597974  Total UI for P1: 0, mck2ui 16

 8067 23:02:57.601168  best dqsien dly found for B1: ( 1,  9, 14)

 8068 23:02:57.604196  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 8069 23:02:57.607720  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8070 23:02:57.607823  

 8071 23:02:57.610799  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8072 23:02:57.614098  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8073 23:02:57.617782  [Gating] SW calibration Done

 8074 23:02:57.617874  ==

 8075 23:02:57.620874  Dram Type= 6, Freq= 0, CH_0, rank 1

 8076 23:02:57.624055  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8077 23:02:57.624160  ==

 8078 23:02:57.627952  RX Vref Scan: 0

 8079 23:02:57.628053  

 8080 23:02:57.630769  RX Vref 0 -> 0, step: 1

 8081 23:02:57.630875  

 8082 23:02:57.630966  RX Delay 0 -> 252, step: 8

 8083 23:02:57.637389  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8084 23:02:57.641071  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8085 23:02:57.644231  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8086 23:02:57.647285  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8087 23:02:57.651029  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8088 23:02:57.657305  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8089 23:02:57.660781  iDelay=200, Bit 6, Center 139 (88 ~ 191) 104

 8090 23:02:57.664120  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8091 23:02:57.667342  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8092 23:02:57.670666  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8093 23:02:57.677428  iDelay=200, Bit 10, Center 127 (72 ~ 183) 112

 8094 23:02:57.680804  iDelay=200, Bit 11, Center 119 (64 ~ 175) 112

 8095 23:02:57.683980  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8096 23:02:57.687170  iDelay=200, Bit 13, Center 135 (80 ~ 191) 112

 8097 23:02:57.690621  iDelay=200, Bit 14, Center 135 (80 ~ 191) 112

 8098 23:02:57.697159  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 8099 23:02:57.697264  ==

 8100 23:02:57.701147  Dram Type= 6, Freq= 0, CH_0, rank 1

 8101 23:02:57.703972  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8102 23:02:57.704080  ==

 8103 23:02:57.704171  DQS Delay:

 8104 23:02:57.707044  DQS0 = 0, DQS1 = 0

 8105 23:02:57.707152  DQM Delay:

 8106 23:02:57.710616  DQM0 = 136, DQM1 = 128

 8107 23:02:57.710727  DQ Delay:

 8108 23:02:57.713673  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8109 23:02:57.717035  DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143

 8110 23:02:57.720955  DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119

 8111 23:02:57.723968  DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135

 8112 23:02:57.727422  

 8113 23:02:57.727520  

 8114 23:02:57.727610  ==

 8115 23:02:57.730214  Dram Type= 6, Freq= 0, CH_0, rank 1

 8116 23:02:57.734183  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8117 23:02:57.734283  ==

 8118 23:02:57.734383  

 8119 23:02:57.734469  

 8120 23:02:57.737345  	TX Vref Scan disable

 8121 23:02:57.737453   == TX Byte 0 ==

 8122 23:02:57.743876  Update DQ  dly =994 (3 ,6, 34)  DQ  OEN =(3 ,3)

 8123 23:02:57.747020  Update DQM dly =994 (3 ,6, 34)  DQM OEN =(3 ,3)

 8124 23:02:57.747134   == TX Byte 1 ==

 8125 23:02:57.753788  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8126 23:02:57.756653  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8127 23:02:57.756753  ==

 8128 23:02:57.760484  Dram Type= 6, Freq= 0, CH_0, rank 1

 8129 23:02:57.763554  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8130 23:02:57.763663  ==

 8131 23:02:57.778110  

 8132 23:02:57.781530  TX Vref early break, caculate TX vref

 8133 23:02:57.784691  TX Vref=16, minBit 3, minWin=22, winSum=384

 8134 23:02:57.788083  TX Vref=18, minBit 3, minWin=22, winSum=396

 8135 23:02:57.791540  TX Vref=20, minBit 3, minWin=23, winSum=401

 8136 23:02:57.795021  TX Vref=22, minBit 3, minWin=24, winSum=410

 8137 23:02:57.798065  TX Vref=24, minBit 0, minWin=25, winSum=419

 8138 23:02:57.804622  TX Vref=26, minBit 7, minWin=25, winSum=429

 8139 23:02:57.808073  TX Vref=28, minBit 3, minWin=25, winSum=425

 8140 23:02:57.811736  TX Vref=30, minBit 3, minWin=25, winSum=417

 8141 23:02:57.814796  TX Vref=32, minBit 4, minWin=24, winSum=410

 8142 23:02:57.818566  TX Vref=34, minBit 0, minWin=24, winSum=403

 8143 23:02:57.824569  [TxChooseVref] Worse bit 7, Min win 25, Win sum 429, Final Vref 26

 8144 23:02:57.824678  

 8145 23:02:57.828305  Final TX Range 0 Vref 26

 8146 23:02:57.828392  

 8147 23:02:57.828457  ==

 8148 23:02:57.831497  Dram Type= 6, Freq= 0, CH_0, rank 1

 8149 23:02:57.835261  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8150 23:02:57.835344  ==

 8151 23:02:57.835409  

 8152 23:02:57.835490  

 8153 23:02:57.838401  	TX Vref Scan disable

 8154 23:02:57.844514  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8155 23:02:57.844597   == TX Byte 0 ==

 8156 23:02:57.848308  u2DelayCellOfst[0]=10 cells (3 PI)

 8157 23:02:57.851288  u2DelayCellOfst[1]=13 cells (4 PI)

 8158 23:02:57.855001  u2DelayCellOfst[2]=10 cells (3 PI)

 8159 23:02:57.858134  u2DelayCellOfst[3]=10 cells (3 PI)

 8160 23:02:57.861127  u2DelayCellOfst[4]=6 cells (2 PI)

 8161 23:02:57.864620  u2DelayCellOfst[5]=0 cells (0 PI)

 8162 23:02:57.868301  u2DelayCellOfst[6]=13 cells (4 PI)

 8163 23:02:57.868384  u2DelayCellOfst[7]=10 cells (3 PI)

 8164 23:02:57.874492  Update DQ  dly =992 (3 ,6, 32)  DQ  OEN =(3 ,3)

 8165 23:02:57.878080  Update DQM dly =994 (3 ,6, 34)  DQM OEN =(3 ,3)

 8166 23:02:57.881274   == TX Byte 1 ==

 8167 23:02:57.881350  u2DelayCellOfst[8]=3 cells (1 PI)

 8168 23:02:57.884312  u2DelayCellOfst[9]=0 cells (0 PI)

 8169 23:02:57.888073  u2DelayCellOfst[10]=6 cells (2 PI)

 8170 23:02:57.890995  u2DelayCellOfst[11]=3 cells (1 PI)

 8171 23:02:57.894230  u2DelayCellOfst[12]=10 cells (3 PI)

 8172 23:02:57.897968  u2DelayCellOfst[13]=13 cells (4 PI)

 8173 23:02:57.900849  u2DelayCellOfst[14]=13 cells (4 PI)

 8174 23:02:57.904510  u2DelayCellOfst[15]=10 cells (3 PI)

 8175 23:02:57.907707  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8176 23:02:57.914449  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8177 23:02:57.914536  DramC Write-DBI on

 8178 23:02:57.914601  ==

 8179 23:02:57.917622  Dram Type= 6, Freq= 0, CH_0, rank 1

 8180 23:02:57.921187  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8181 23:02:57.921294  ==

 8182 23:02:57.924563  

 8183 23:02:57.924646  

 8184 23:02:57.924710  	TX Vref Scan disable

 8185 23:02:57.927477   == TX Byte 0 ==

 8186 23:02:57.931106  Update DQM dly =738 (2 ,6, 34)  DQM OEN =(3 ,3)

 8187 23:02:57.934229   == TX Byte 1 ==

 8188 23:02:57.937949  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8189 23:02:57.938056  DramC Write-DBI off

 8190 23:02:57.941280  

 8191 23:02:57.941384  [DATLAT]

 8192 23:02:57.941479  Freq=1600, CH0 RK1

 8193 23:02:57.941567  

 8194 23:02:57.944105  DATLAT Default: 0xf

 8195 23:02:57.944208  0, 0xFFFF, sum = 0

 8196 23:02:57.948043  1, 0xFFFF, sum = 0

 8197 23:02:57.948152  2, 0xFFFF, sum = 0

 8198 23:02:57.950856  3, 0xFFFF, sum = 0

 8199 23:02:57.954099  4, 0xFFFF, sum = 0

 8200 23:02:57.954201  5, 0xFFFF, sum = 0

 8201 23:02:57.957593  6, 0xFFFF, sum = 0

 8202 23:02:57.957695  7, 0xFFFF, sum = 0

 8203 23:02:57.960693  8, 0xFFFF, sum = 0

 8204 23:02:57.960793  9, 0xFFFF, sum = 0

 8205 23:02:57.963992  10, 0xFFFF, sum = 0

 8206 23:02:57.964097  11, 0xFFFF, sum = 0

 8207 23:02:57.967768  12, 0xFFFF, sum = 0

 8208 23:02:57.967872  13, 0xFFFF, sum = 0

 8209 23:02:57.970585  14, 0x0, sum = 1

 8210 23:02:57.970689  15, 0x0, sum = 2

 8211 23:02:57.974297  16, 0x0, sum = 3

 8212 23:02:57.974400  17, 0x0, sum = 4

 8213 23:02:57.977324  best_step = 15

 8214 23:02:57.977422  

 8215 23:02:57.977515  ==

 8216 23:02:57.981065  Dram Type= 6, Freq= 0, CH_0, rank 1

 8217 23:02:57.984154  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8218 23:02:57.984233  ==

 8219 23:02:57.984296  RX Vref Scan: 0

 8220 23:02:57.987327  

 8221 23:02:57.987429  RX Vref 0 -> 0, step: 1

 8222 23:02:57.987524  

 8223 23:02:57.990937  RX Delay 19 -> 252, step: 4

 8224 23:02:57.994449  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8225 23:02:58.000568  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8226 23:02:58.003977  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8227 23:02:58.007634  iDelay=191, Bit 3, Center 134 (83 ~ 186) 104

 8228 23:02:58.010938  iDelay=191, Bit 4, Center 136 (87 ~ 186) 100

 8229 23:02:58.013789  iDelay=191, Bit 5, Center 124 (71 ~ 178) 108

 8230 23:02:58.020830  iDelay=191, Bit 6, Center 140 (91 ~ 190) 100

 8231 23:02:58.024024  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8232 23:02:58.027108  iDelay=191, Bit 8, Center 118 (67 ~ 170) 104

 8233 23:02:58.030363  iDelay=191, Bit 9, Center 116 (67 ~ 166) 100

 8234 23:02:58.033808  iDelay=191, Bit 10, Center 128 (75 ~ 182) 108

 8235 23:02:58.040582  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8236 23:02:58.043647  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8237 23:02:58.046798  iDelay=191, Bit 13, Center 134 (83 ~ 186) 104

 8238 23:02:58.050441  iDelay=191, Bit 14, Center 136 (83 ~ 190) 108

 8239 23:02:58.053526  iDelay=191, Bit 15, Center 134 (87 ~ 182) 96

 8240 23:02:58.057147  ==

 8241 23:02:58.060255  Dram Type= 6, Freq= 0, CH_0, rank 1

 8242 23:02:58.063934  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8243 23:02:58.064037  ==

 8244 23:02:58.064139  DQS Delay:

 8245 23:02:58.066890  DQS0 = 0, DQS1 = 0

 8246 23:02:58.066988  DQM Delay:

 8247 23:02:58.069919  DQM0 = 134, DQM1 = 127

 8248 23:02:58.070035  DQ Delay:

 8249 23:02:58.073201  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134

 8250 23:02:58.076685  DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140

 8251 23:02:58.080282  DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118

 8252 23:02:58.083318  DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134

 8253 23:02:58.083430  

 8254 23:02:58.083530  

 8255 23:02:58.083624  

 8256 23:02:58.086437  [DramC_TX_OE_Calibration] TA2

 8257 23:02:58.090217  Original DQ_B0 (3 6) =30, OEN = 27

 8258 23:02:58.093280  Original DQ_B1 (3 6) =30, OEN = 27

 8259 23:02:58.096407  24, 0x0, End_B0=24 End_B1=24

 8260 23:02:58.100074  25, 0x0, End_B0=25 End_B1=25

 8261 23:02:58.103215  26, 0x0, End_B0=26 End_B1=26

 8262 23:02:58.103305  27, 0x0, End_B0=27 End_B1=27

 8263 23:02:58.106272  28, 0x0, End_B0=28 End_B1=28

 8264 23:02:58.109865  29, 0x0, End_B0=29 End_B1=29

 8265 23:02:58.112930  30, 0x0, End_B0=30 End_B1=30

 8266 23:02:58.113039  31, 0x4141, End_B0=30 End_B1=30

 8267 23:02:58.116213  Byte0 end_step=30  best_step=27

 8268 23:02:58.119610  Byte1 end_step=30  best_step=27

 8269 23:02:58.122968  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8270 23:02:58.126294  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8271 23:02:58.126406  

 8272 23:02:58.126501  

 8273 23:02:58.133236  [DQSOSCAuto] RK1, (LSB)MR18= 0x1e06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps

 8274 23:02:58.136363  CH0 RK1: MR19=303, MR18=1E06

 8275 23:02:58.143106  CH0_RK1: MR19=0x303, MR18=0x1E06, DQSOSC=394, MR23=63, INC=23, DEC=15

 8276 23:02:58.146606  [RxdqsGatingPostProcess] freq 1600

 8277 23:02:58.152652  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8278 23:02:58.156342  best DQS0 dly(2T, 0.5T) = (1, 1)

 8279 23:02:58.156456  best DQS1 dly(2T, 0.5T) = (1, 1)

 8280 23:02:58.159702  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8281 23:02:58.162998  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8282 23:02:58.165888  best DQS0 dly(2T, 0.5T) = (1, 1)

 8283 23:02:58.169503  best DQS1 dly(2T, 0.5T) = (1, 1)

 8284 23:02:58.172655  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8285 23:02:58.175845  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8286 23:02:58.179297  Pre-setting of DQS Precalculation

 8287 23:02:58.182626  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8288 23:02:58.185958  ==

 8289 23:02:58.189316  Dram Type= 6, Freq= 0, CH_1, rank 0

 8290 23:02:58.192364  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8291 23:02:58.192472  ==

 8292 23:02:58.196143  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8293 23:02:58.202731  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8294 23:02:58.205925  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8295 23:02:58.212619  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8296 23:02:58.220635  [CA 0] Center 42 (13~72) winsize 60

 8297 23:02:58.224170  [CA 1] Center 42 (13~72) winsize 60

 8298 23:02:58.227055  [CA 2] Center 38 (9~68) winsize 60

 8299 23:02:58.230542  [CA 3] Center 38 (9~68) winsize 60

 8300 23:02:58.233616  [CA 4] Center 39 (10~68) winsize 59

 8301 23:02:58.236889  [CA 5] Center 37 (8~67) winsize 60

 8302 23:02:58.237001  

 8303 23:02:58.240692  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8304 23:02:58.240796  

 8305 23:02:58.247431  [CATrainingPosCal] consider 1 rank data

 8306 23:02:58.247539  u2DelayCellTimex100 = 285/100 ps

 8307 23:02:58.253412  CA0 delay=42 (13~72),Diff = 5 PI (17 cell)

 8308 23:02:58.257177  CA1 delay=42 (13~72),Diff = 5 PI (17 cell)

 8309 23:02:58.260673  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8310 23:02:58.264119  CA3 delay=38 (9~68),Diff = 1 PI (3 cell)

 8311 23:02:58.266857  CA4 delay=39 (10~68),Diff = 2 PI (6 cell)

 8312 23:02:58.270658  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8313 23:02:58.270774  

 8314 23:02:58.273997  CA PerBit enable=1, Macro0, CA PI delay=37

 8315 23:02:58.274076  

 8316 23:02:58.276809  [CBTSetCACLKResult] CA Dly = 37

 8317 23:02:58.280030  CS Dly: 11 (0~42)

 8318 23:02:58.283505  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8319 23:02:58.287332  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8320 23:02:58.287438  ==

 8321 23:02:58.290343  Dram Type= 6, Freq= 0, CH_1, rank 1

 8322 23:02:58.296979  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8323 23:02:58.297087  ==

 8324 23:02:58.299968  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8325 23:02:58.303114  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8326 23:02:58.310509  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8327 23:02:58.316685  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8328 23:02:58.323939  [CA 0] Center 41 (12~71) winsize 60

 8329 23:02:58.327090  [CA 1] Center 42 (13~71) winsize 59

 8330 23:02:58.330700  [CA 2] Center 38 (9~68) winsize 60

 8331 23:02:58.333753  [CA 3] Center 38 (8~68) winsize 61

 8332 23:02:58.337405  [CA 4] Center 38 (8~68) winsize 61

 8333 23:02:58.340867  [CA 5] Center 37 (7~67) winsize 61

 8334 23:02:58.340976  

 8335 23:02:58.343601  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8336 23:02:58.343701  

 8337 23:02:58.347189  [CATrainingPosCal] consider 2 rank data

 8338 23:02:58.350600  u2DelayCellTimex100 = 285/100 ps

 8339 23:02:58.353507  CA0 delay=42 (13~71),Diff = 5 PI (17 cell)

 8340 23:02:58.360336  CA1 delay=42 (13~71),Diff = 5 PI (17 cell)

 8341 23:02:58.363422  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8342 23:02:58.367089  CA3 delay=38 (9~68),Diff = 1 PI (3 cell)

 8343 23:02:58.370081  CA4 delay=39 (10~68),Diff = 2 PI (6 cell)

 8344 23:02:58.373763  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8345 23:02:58.373847  

 8346 23:02:58.377208  CA PerBit enable=1, Macro0, CA PI delay=37

 8347 23:02:58.377291  

 8348 23:02:58.380819  [CBTSetCACLKResult] CA Dly = 37

 8349 23:02:58.383901  CS Dly: 12 (0~45)

 8350 23:02:58.386911  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8351 23:02:58.390349  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8352 23:02:58.390433  

 8353 23:02:58.393624  ----->DramcWriteLeveling(PI) begin...

 8354 23:02:58.393701  ==

 8355 23:02:58.396806  Dram Type= 6, Freq= 0, CH_1, rank 0

 8356 23:02:58.403578  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8357 23:02:58.403661  ==

 8358 23:02:58.407161  Write leveling (Byte 0): 26 => 26

 8359 23:02:58.407239  Write leveling (Byte 1): 26 => 26

 8360 23:02:58.410152  DramcWriteLeveling(PI) end<-----

 8361 23:02:58.410244  

 8362 23:02:58.413419  ==

 8363 23:02:58.413521  Dram Type= 6, Freq= 0, CH_1, rank 0

 8364 23:02:58.420200  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8365 23:02:58.420280  ==

 8366 23:02:58.423309  [Gating] SW mode calibration

 8367 23:02:58.430242  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8368 23:02:58.433177  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8369 23:02:58.439714   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8370 23:02:58.443230   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8371 23:02:58.446356   1  4  8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 8372 23:02:58.453104   1  4 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)

 8373 23:02:58.456344   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8374 23:02:58.459949   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8375 23:02:58.466714   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8376 23:02:58.469893   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8377 23:02:58.472786   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8378 23:02:58.479538   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8379 23:02:58.482943   1  5  8 | B1->B0 | 3434 2f2f | 1 1 | (1 0) (1 0)

 8380 23:02:58.486541   1  5 12 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (1 0)

 8381 23:02:58.492619   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8382 23:02:58.496341   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8383 23:02:58.499288   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8384 23:02:58.506219   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8385 23:02:58.509418   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8386 23:02:58.512584   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8387 23:02:58.519603   1  6  8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)

 8388 23:02:58.522761   1  6 12 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)

 8389 23:02:58.526213   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8390 23:02:58.532422   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8391 23:02:58.536151   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8392 23:02:58.539227   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8393 23:02:58.545681   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8394 23:02:58.549243   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8395 23:02:58.552419   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8396 23:02:58.556277   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8397 23:02:58.562425   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8398 23:02:58.566006   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8399 23:02:58.569040   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8400 23:02:58.575756   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8401 23:02:58.579783   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8402 23:02:58.582849   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8403 23:02:58.589010   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8404 23:02:58.592372   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8405 23:02:58.596045   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8406 23:02:58.602335   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8407 23:02:58.606023   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8408 23:02:58.609101   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8409 23:02:58.615952   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8410 23:02:58.619569   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8411 23:02:58.622790   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8412 23:02:58.629197   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8413 23:02:58.632659   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8414 23:02:58.635796  Total UI for P1: 0, mck2ui 16

 8415 23:02:58.639049  best dqsien dly found for B0: ( 1,  9, 10)

 8416 23:02:58.642690  Total UI for P1: 0, mck2ui 16

 8417 23:02:58.645934  best dqsien dly found for B1: ( 1,  9, 10)

 8418 23:02:58.649373  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8419 23:02:58.652201  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8420 23:02:58.652289  

 8421 23:02:58.655814  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8422 23:02:58.658812  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8423 23:02:58.662516  [Gating] SW calibration Done

 8424 23:02:58.662598  ==

 8425 23:02:58.665412  Dram Type= 6, Freq= 0, CH_1, rank 0

 8426 23:02:58.668549  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8427 23:02:58.672042  ==

 8428 23:02:58.672124  RX Vref Scan: 0

 8429 23:02:58.672189  

 8430 23:02:58.675524  RX Vref 0 -> 0, step: 1

 8431 23:02:58.675608  

 8432 23:02:58.675673  RX Delay 0 -> 252, step: 8

 8433 23:02:58.682428  iDelay=200, Bit 0, Center 139 (88 ~ 191) 104

 8434 23:02:58.685434  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8435 23:02:58.689137  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8436 23:02:58.692291  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8437 23:02:58.695669  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8438 23:02:58.702047  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8439 23:02:58.705246  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8440 23:02:58.708784  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8441 23:02:58.711885  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8442 23:02:58.715510  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8443 23:02:58.722423  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8444 23:02:58.725373  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8445 23:02:58.728366  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8446 23:02:58.731943  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 8447 23:02:58.738408  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8448 23:02:58.742094  iDelay=200, Bit 15, Center 143 (88 ~ 199) 112

 8449 23:02:58.742209  ==

 8450 23:02:58.745010  Dram Type= 6, Freq= 0, CH_1, rank 0

 8451 23:02:58.748767  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8452 23:02:58.748850  ==

 8453 23:02:58.748914  DQS Delay:

 8454 23:02:58.751758  DQS0 = 0, DQS1 = 0

 8455 23:02:58.751841  DQM Delay:

 8456 23:02:58.755115  DQM0 = 135, DQM1 = 132

 8457 23:02:58.755204  DQ Delay:

 8458 23:02:58.758454  DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135

 8459 23:02:58.761693  DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =135

 8460 23:02:58.764916  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127

 8461 23:02:58.768543  DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =143

 8462 23:02:58.772144  

 8463 23:02:58.772227  

 8464 23:02:58.772292  ==

 8465 23:02:58.775177  Dram Type= 6, Freq= 0, CH_1, rank 0

 8466 23:02:58.778434  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8467 23:02:58.778516  ==

 8468 23:02:58.778581  

 8469 23:02:58.778640  

 8470 23:02:58.781751  	TX Vref Scan disable

 8471 23:02:58.781834   == TX Byte 0 ==

 8472 23:02:58.788455  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8473 23:02:58.791652  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8474 23:02:58.791744   == TX Byte 1 ==

 8475 23:02:58.798941  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8476 23:02:58.801820  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8477 23:02:58.801912  ==

 8478 23:02:58.805333  Dram Type= 6, Freq= 0, CH_1, rank 0

 8479 23:02:58.808376  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8480 23:02:58.808459  ==

 8481 23:02:58.822578  

 8482 23:02:58.825495  TX Vref early break, caculate TX vref

 8483 23:02:58.829333  TX Vref=16, minBit 1, minWin=22, winSum=382

 8484 23:02:58.832234  TX Vref=18, minBit 0, minWin=23, winSum=387

 8485 23:02:58.835837  TX Vref=20, minBit 0, minWin=23, winSum=398

 8486 23:02:58.839319  TX Vref=22, minBit 0, minWin=24, winSum=406

 8487 23:02:58.842392  TX Vref=24, minBit 0, minWin=24, winSum=417

 8488 23:02:58.848887  TX Vref=26, minBit 0, minWin=25, winSum=422

 8489 23:02:58.852463  TX Vref=28, minBit 0, minWin=25, winSum=427

 8490 23:02:58.855637  TX Vref=30, minBit 0, minWin=25, winSum=424

 8491 23:02:58.859140  TX Vref=32, minBit 0, minWin=24, winSum=410

 8492 23:02:58.862474  TX Vref=34, minBit 0, minWin=23, winSum=406

 8493 23:02:58.865929  TX Vref=36, minBit 0, minWin=23, winSum=393

 8494 23:02:58.872402  [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28

 8495 23:02:58.872516  

 8496 23:02:58.875601  Final TX Range 0 Vref 28

 8497 23:02:58.875693  

 8498 23:02:58.875758  ==

 8499 23:02:58.878634  Dram Type= 6, Freq= 0, CH_1, rank 0

 8500 23:02:58.882474  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8501 23:02:58.882553  ==

 8502 23:02:58.882617  

 8503 23:02:58.882676  

 8504 23:02:58.885514  	TX Vref Scan disable

 8505 23:02:58.892317  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8506 23:02:58.892430   == TX Byte 0 ==

 8507 23:02:58.895929  u2DelayCellOfst[0]=20 cells (6 PI)

 8508 23:02:58.898888  u2DelayCellOfst[1]=13 cells (4 PI)

 8509 23:02:58.901963  u2DelayCellOfst[2]=0 cells (0 PI)

 8510 23:02:58.905418  u2DelayCellOfst[3]=10 cells (3 PI)

 8511 23:02:58.908711  u2DelayCellOfst[4]=13 cells (4 PI)

 8512 23:02:58.912221  u2DelayCellOfst[5]=20 cells (6 PI)

 8513 23:02:58.915415  u2DelayCellOfst[6]=20 cells (6 PI)

 8514 23:02:58.919041  u2DelayCellOfst[7]=10 cells (3 PI)

 8515 23:02:58.922342  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8516 23:02:58.925426  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8517 23:02:58.928637   == TX Byte 1 ==

 8518 23:02:58.932310  u2DelayCellOfst[8]=0 cells (0 PI)

 8519 23:02:58.932412  u2DelayCellOfst[9]=3 cells (1 PI)

 8520 23:02:58.935377  u2DelayCellOfst[10]=13 cells (4 PI)

 8521 23:02:58.938920  u2DelayCellOfst[11]=3 cells (1 PI)

 8522 23:02:58.941963  u2DelayCellOfst[12]=17 cells (5 PI)

 8523 23:02:58.945402  u2DelayCellOfst[13]=17 cells (5 PI)

 8524 23:02:58.948536  u2DelayCellOfst[14]=17 cells (5 PI)

 8525 23:02:58.951976  u2DelayCellOfst[15]=17 cells (5 PI)

 8526 23:02:58.955416  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8527 23:02:58.961885  Update DQM dly =980 (3 ,6, 20)  DQM OEN =(3 ,3)

 8528 23:02:58.961999  DramC Write-DBI on

 8529 23:02:58.962094  ==

 8530 23:02:58.965538  Dram Type= 6, Freq= 0, CH_1, rank 0

 8531 23:02:58.972291  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8532 23:02:58.972398  ==

 8533 23:02:58.972498  

 8534 23:02:58.972587  

 8535 23:02:58.972678  	TX Vref Scan disable

 8536 23:02:58.975533   == TX Byte 0 ==

 8537 23:02:58.979063  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8538 23:02:58.982516   == TX Byte 1 ==

 8539 23:02:58.985771  Update DQM dly =721 (2 ,6, 17)  DQM OEN =(3 ,3)

 8540 23:02:58.989093  DramC Write-DBI off

 8541 23:02:58.989177  

 8542 23:02:58.989241  [DATLAT]

 8543 23:02:58.989301  Freq=1600, CH1 RK0

 8544 23:02:58.989359  

 8545 23:02:58.992178  DATLAT Default: 0xf

 8546 23:02:58.992257  0, 0xFFFF, sum = 0

 8547 23:02:58.995602  1, 0xFFFF, sum = 0

 8548 23:02:58.995688  2, 0xFFFF, sum = 0

 8549 23:02:58.999044  3, 0xFFFF, sum = 0

 8550 23:02:59.002339  4, 0xFFFF, sum = 0

 8551 23:02:59.002424  5, 0xFFFF, sum = 0

 8552 23:02:59.005766  6, 0xFFFF, sum = 0

 8553 23:02:59.005850  7, 0xFFFF, sum = 0

 8554 23:02:59.008744  8, 0xFFFF, sum = 0

 8555 23:02:59.008828  9, 0xFFFF, sum = 0

 8556 23:02:59.012314  10, 0xFFFF, sum = 0

 8557 23:02:59.012403  11, 0xFFFF, sum = 0

 8558 23:02:59.015665  12, 0xFFFF, sum = 0

 8559 23:02:59.015750  13, 0xFFFF, sum = 0

 8560 23:02:59.018725  14, 0x0, sum = 1

 8561 23:02:59.018810  15, 0x0, sum = 2

 8562 23:02:59.022385  16, 0x0, sum = 3

 8563 23:02:59.022478  17, 0x0, sum = 4

 8564 23:02:59.025568  best_step = 15

 8565 23:02:59.025662  

 8566 23:02:59.025741  ==

 8567 23:02:59.028665  Dram Type= 6, Freq= 0, CH_1, rank 0

 8568 23:02:59.032422  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8569 23:02:59.032505  ==

 8570 23:02:59.032570  RX Vref Scan: 1

 8571 23:02:59.035525  

 8572 23:02:59.035607  Set Vref Range= 24 -> 127

 8573 23:02:59.035672  

 8574 23:02:59.038465  RX Vref 24 -> 127, step: 1

 8575 23:02:59.038536  

 8576 23:02:59.042087  RX Delay 27 -> 252, step: 4

 8577 23:02:59.042157  

 8578 23:02:59.045164  Set Vref, RX VrefLevel [Byte0]: 24

 8579 23:02:59.048348                           [Byte1]: 24

 8580 23:02:59.048433  

 8581 23:02:59.051965  Set Vref, RX VrefLevel [Byte0]: 25

 8582 23:02:59.055412                           [Byte1]: 25

 8583 23:02:59.055519  

 8584 23:02:59.058471  Set Vref, RX VrefLevel [Byte0]: 26

 8585 23:02:59.062026                           [Byte1]: 26

 8586 23:02:59.065608  

 8587 23:02:59.065691  Set Vref, RX VrefLevel [Byte0]: 27

 8588 23:02:59.069312                           [Byte1]: 27

 8589 23:02:59.073638  

 8590 23:02:59.073747  Set Vref, RX VrefLevel [Byte0]: 28

 8591 23:02:59.076603                           [Byte1]: 28

 8592 23:02:59.081056  

 8593 23:02:59.081141  Set Vref, RX VrefLevel [Byte0]: 29

 8594 23:02:59.084501                           [Byte1]: 29

 8595 23:02:59.088178  

 8596 23:02:59.088254  Set Vref, RX VrefLevel [Byte0]: 30

 8597 23:02:59.092007                           [Byte1]: 30

 8598 23:02:59.096006  

 8599 23:02:59.096104  Set Vref, RX VrefLevel [Byte0]: 31

 8600 23:02:59.099349                           [Byte1]: 31

 8601 23:02:59.103632  

 8602 23:02:59.103720  Set Vref, RX VrefLevel [Byte0]: 32

 8603 23:02:59.106607                           [Byte1]: 32

 8604 23:02:59.111162  

 8605 23:02:59.111245  Set Vref, RX VrefLevel [Byte0]: 33

 8606 23:02:59.114525                           [Byte1]: 33

 8607 23:02:59.118645  

 8608 23:02:59.118728  Set Vref, RX VrefLevel [Byte0]: 34

 8609 23:02:59.121920                           [Byte1]: 34

 8610 23:02:59.125944  

 8611 23:02:59.126057  Set Vref, RX VrefLevel [Byte0]: 35

 8612 23:02:59.129589                           [Byte1]: 35

 8613 23:02:59.133882  

 8614 23:02:59.133969  Set Vref, RX VrefLevel [Byte0]: 36

 8615 23:02:59.137088                           [Byte1]: 36

 8616 23:02:59.141277  

 8617 23:02:59.141360  Set Vref, RX VrefLevel [Byte0]: 37

 8618 23:02:59.144398                           [Byte1]: 37

 8619 23:02:59.148593  

 8620 23:02:59.148702  Set Vref, RX VrefLevel [Byte0]: 38

 8621 23:02:59.152370                           [Byte1]: 38

 8622 23:02:59.155955  

 8623 23:02:59.156061  Set Vref, RX VrefLevel [Byte0]: 39

 8624 23:02:59.159584                           [Byte1]: 39

 8625 23:02:59.163785  

 8626 23:02:59.163899  Set Vref, RX VrefLevel [Byte0]: 40

 8627 23:02:59.167299                           [Byte1]: 40

 8628 23:02:59.171253  

 8629 23:02:59.171361  Set Vref, RX VrefLevel [Byte0]: 41

 8630 23:02:59.174268                           [Byte1]: 41

 8631 23:02:59.178630  

 8632 23:02:59.178736  Set Vref, RX VrefLevel [Byte0]: 42

 8633 23:02:59.182329                           [Byte1]: 42

 8634 23:02:59.186042  

 8635 23:02:59.186126  Set Vref, RX VrefLevel [Byte0]: 43

 8636 23:02:59.189471                           [Byte1]: 43

 8637 23:02:59.193851  

 8638 23:02:59.193959  Set Vref, RX VrefLevel [Byte0]: 44

 8639 23:02:59.196918                           [Byte1]: 44

 8640 23:02:59.201124  

 8641 23:02:59.201207  Set Vref, RX VrefLevel [Byte0]: 45

 8642 23:02:59.204763                           [Byte1]: 45

 8643 23:02:59.209082  

 8644 23:02:59.209175  Set Vref, RX VrefLevel [Byte0]: 46

 8645 23:02:59.212054                           [Byte1]: 46

 8646 23:02:59.216309  

 8647 23:02:59.216393  Set Vref, RX VrefLevel [Byte0]: 47

 8648 23:02:59.219775                           [Byte1]: 47

 8649 23:02:59.223962  

 8650 23:02:59.224046  Set Vref, RX VrefLevel [Byte0]: 48

 8651 23:02:59.227279                           [Byte1]: 48

 8652 23:02:59.231475  

 8653 23:02:59.231558  Set Vref, RX VrefLevel [Byte0]: 49

 8654 23:02:59.234945                           [Byte1]: 49

 8655 23:02:59.239205  

 8656 23:02:59.239287  Set Vref, RX VrefLevel [Byte0]: 50

 8657 23:02:59.242071                           [Byte1]: 50

 8658 23:02:59.246402  

 8659 23:02:59.246511  Set Vref, RX VrefLevel [Byte0]: 51

 8660 23:02:59.250134                           [Byte1]: 51

 8661 23:02:59.253938  

 8662 23:02:59.254020  Set Vref, RX VrefLevel [Byte0]: 52

 8663 23:02:59.257621                           [Byte1]: 52

 8664 23:02:59.261858  

 8665 23:02:59.261940  Set Vref, RX VrefLevel [Byte0]: 53

 8666 23:02:59.264887                           [Byte1]: 53

 8667 23:02:59.269291  

 8668 23:02:59.272358  Set Vref, RX VrefLevel [Byte0]: 54

 8669 23:02:59.275441                           [Byte1]: 54

 8670 23:02:59.275525  

 8671 23:02:59.278830  Set Vref, RX VrefLevel [Byte0]: 55

 8672 23:02:59.282376                           [Byte1]: 55

 8673 23:02:59.282459  

 8674 23:02:59.285594  Set Vref, RX VrefLevel [Byte0]: 56

 8675 23:02:59.289171                           [Byte1]: 56

 8676 23:02:59.289254  

 8677 23:02:59.292462  Set Vref, RX VrefLevel [Byte0]: 57

 8678 23:02:59.295760                           [Byte1]: 57

 8679 23:02:59.299442  

 8680 23:02:59.299524  Set Vref, RX VrefLevel [Byte0]: 58

 8681 23:02:59.302396                           [Byte1]: 58

 8682 23:02:59.306813  

 8683 23:02:59.306895  Set Vref, RX VrefLevel [Byte0]: 59

 8684 23:02:59.309883                           [Byte1]: 59

 8685 23:02:59.314270  

 8686 23:02:59.314354  Set Vref, RX VrefLevel [Byte0]: 60

 8687 23:02:59.317806                           [Byte1]: 60

 8688 23:02:59.321966  

 8689 23:02:59.322076  Set Vref, RX VrefLevel [Byte0]: 61

 8690 23:02:59.325333                           [Byte1]: 61

 8691 23:02:59.329496  

 8692 23:02:59.329586  Set Vref, RX VrefLevel [Byte0]: 62

 8693 23:02:59.332866                           [Byte1]: 62

 8694 23:02:59.336936  

 8695 23:02:59.337042  Set Vref, RX VrefLevel [Byte0]: 63

 8696 23:02:59.340425                           [Byte1]: 63

 8697 23:02:59.344501  

 8698 23:02:59.344609  Set Vref, RX VrefLevel [Byte0]: 64

 8699 23:02:59.347471                           [Byte1]: 64

 8700 23:02:59.351908  

 8701 23:02:59.351985  Set Vref, RX VrefLevel [Byte0]: 65

 8702 23:02:59.355268                           [Byte1]: 65

 8703 23:02:59.359768  

 8704 23:02:59.359878  Set Vref, RX VrefLevel [Byte0]: 66

 8705 23:02:59.363106                           [Byte1]: 66

 8706 23:02:59.367350  

 8707 23:02:59.367453  Set Vref, RX VrefLevel [Byte0]: 67

 8708 23:02:59.370255                           [Byte1]: 67

 8709 23:02:59.374457  

 8710 23:02:59.374560  Set Vref, RX VrefLevel [Byte0]: 68

 8711 23:02:59.378120                           [Byte1]: 68

 8712 23:02:59.382312  

 8713 23:02:59.382392  Set Vref, RX VrefLevel [Byte0]: 69

 8714 23:02:59.385638                           [Byte1]: 69

 8715 23:02:59.389354  

 8716 23:02:59.389437  Set Vref, RX VrefLevel [Byte0]: 70

 8717 23:02:59.392877                           [Byte1]: 70

 8718 23:02:59.396980  

 8719 23:02:59.397062  Set Vref, RX VrefLevel [Byte0]: 71

 8720 23:02:59.400247                           [Byte1]: 71

 8721 23:02:59.404493  

 8722 23:02:59.404575  Set Vref, RX VrefLevel [Byte0]: 72

 8723 23:02:59.408274                           [Byte1]: 72

 8724 23:02:59.412367  

 8725 23:02:59.412450  Set Vref, RX VrefLevel [Byte0]: 73

 8726 23:02:59.415541                           [Byte1]: 73

 8727 23:02:59.419806  

 8728 23:02:59.419888  Set Vref, RX VrefLevel [Byte0]: 74

 8729 23:02:59.422787                           [Byte1]: 74

 8730 23:02:59.427628  

 8731 23:02:59.427710  Final RX Vref Byte 0 = 57 to rank0

 8732 23:02:59.430567  Final RX Vref Byte 1 = 58 to rank0

 8733 23:02:59.434241  Final RX Vref Byte 0 = 57 to rank1

 8734 23:02:59.437482  Final RX Vref Byte 1 = 58 to rank1==

 8735 23:02:59.440715  Dram Type= 6, Freq= 0, CH_1, rank 0

 8736 23:02:59.447018  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8737 23:02:59.447102  ==

 8738 23:02:59.447168  DQS Delay:

 8739 23:02:59.450586  DQS0 = 0, DQS1 = 0

 8740 23:02:59.450666  DQM Delay:

 8741 23:02:59.450729  DQM0 = 134, DQM1 = 131

 8742 23:02:59.453712  DQ Delay:

 8743 23:02:59.456706  DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130

 8744 23:02:59.460347  DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132

 8745 23:02:59.463313  DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =124

 8746 23:02:59.466615  DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140

 8747 23:02:59.466693  

 8748 23:02:59.466757  

 8749 23:02:59.466838  

 8750 23:02:59.470041  [DramC_TX_OE_Calibration] TA2

 8751 23:02:59.473530  Original DQ_B0 (3 6) =30, OEN = 27

 8752 23:02:59.476706  Original DQ_B1 (3 6) =30, OEN = 27

 8753 23:02:59.480348  24, 0x0, End_B0=24 End_B1=24

 8754 23:02:59.480462  25, 0x0, End_B0=25 End_B1=25

 8755 23:02:59.483570  26, 0x0, End_B0=26 End_B1=26

 8756 23:02:59.486661  27, 0x0, End_B0=27 End_B1=27

 8757 23:02:59.490289  28, 0x0, End_B0=28 End_B1=28

 8758 23:02:59.493177  29, 0x0, End_B0=29 End_B1=29

 8759 23:02:59.493286  30, 0x0, End_B0=30 End_B1=30

 8760 23:02:59.496655  31, 0x4141, End_B0=30 End_B1=30

 8761 23:02:59.499987  Byte0 end_step=30  best_step=27

 8762 23:02:59.503460  Byte1 end_step=30  best_step=27

 8763 23:02:59.506628  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8764 23:02:59.509675  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8765 23:02:59.509752  

 8766 23:02:59.509815  

 8767 23:02:59.516442  [DQSOSCAuto] RK0, (LSB)MR18= 0x1522, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps

 8768 23:02:59.519668  CH1 RK0: MR19=303, MR18=1522

 8769 23:02:59.526713  CH1_RK0: MR19=0x303, MR18=0x1522, DQSOSC=392, MR23=63, INC=24, DEC=16

 8770 23:02:59.526792  

 8771 23:02:59.530012  ----->DramcWriteLeveling(PI) begin...

 8772 23:02:59.530124  ==

 8773 23:02:59.533082  Dram Type= 6, Freq= 0, CH_1, rank 1

 8774 23:02:59.536160  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8775 23:02:59.536242  ==

 8776 23:02:59.539635  Write leveling (Byte 0): 26 => 26

 8777 23:02:59.542972  Write leveling (Byte 1): 28 => 28

 8778 23:02:59.546240  DramcWriteLeveling(PI) end<-----

 8779 23:02:59.546343  

 8780 23:02:59.546445  ==

 8781 23:02:59.549274  Dram Type= 6, Freq= 0, CH_1, rank 1

 8782 23:02:59.552728  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8783 23:02:59.556224  ==

 8784 23:02:59.556308  [Gating] SW mode calibration

 8785 23:02:59.562776  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8786 23:02:59.569527  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8787 23:02:59.572451   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8788 23:02:59.579234   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8789 23:02:59.583065   1  4  8 | B1->B0 | 2525 2323 | 1 0 | (1 1) (0 0)

 8790 23:02:59.586041   1  4 12 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)

 8791 23:02:59.592777   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8792 23:02:59.595929   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8793 23:02:59.599553   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8794 23:02:59.605789   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8795 23:02:59.609392   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8796 23:02:59.612863   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8797 23:02:59.619756   1  5  8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)

 8798 23:02:59.622685   1  5 12 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (1 0)

 8799 23:02:59.626387   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 8800 23:02:59.632814   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8801 23:02:59.635635   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8802 23:02:59.639350   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8803 23:02:59.645628   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8804 23:02:59.649336   1  6  4 | B1->B0 | 2424 2323 | 1 0 | (0 0) (0 0)

 8805 23:02:59.652366   1  6  8 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)

 8806 23:02:59.656280   1  6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)

 8807 23:02:59.662167   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8808 23:02:59.665580   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8809 23:02:59.669104   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8810 23:02:59.675822   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8811 23:02:59.679122   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8812 23:02:59.682444   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8813 23:02:59.689434   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8814 23:02:59.692350   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8815 23:02:59.695560   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8816 23:02:59.702285   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8817 23:02:59.705875   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8818 23:02:59.709063   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8819 23:02:59.715496   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8820 23:02:59.719281   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8821 23:02:59.722167   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8822 23:02:59.729321   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8823 23:02:59.732636   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8824 23:02:59.735557   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8825 23:02:59.742157   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8826 23:02:59.745772   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8827 23:02:59.749202   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8828 23:02:59.752260   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8829 23:02:59.759148   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8830 23:02:59.762859   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8831 23:02:59.766010  Total UI for P1: 0, mck2ui 16

 8832 23:02:59.768923  best dqsien dly found for B1: ( 1,  9,  8)

 8833 23:02:59.772592   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8834 23:02:59.775532  Total UI for P1: 0, mck2ui 16

 8835 23:02:59.778887  best dqsien dly found for B0: ( 1,  9, 12)

 8836 23:02:59.782457  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8837 23:02:59.785377  best DQS1 dly(MCK, UI, PI) = (1, 9, 8)

 8838 23:02:59.788730  

 8839 23:02:59.792090  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8840 23:02:59.795652  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8841 23:02:59.799033  [Gating] SW calibration Done

 8842 23:02:59.799117  ==

 8843 23:02:59.802153  Dram Type= 6, Freq= 0, CH_1, rank 1

 8844 23:02:59.806103  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8845 23:02:59.806188  ==

 8846 23:02:59.806276  RX Vref Scan: 0

 8847 23:02:59.806358  

 8848 23:02:59.808910  RX Vref 0 -> 0, step: 1

 8849 23:02:59.808995  

 8850 23:02:59.811966  RX Delay 0 -> 252, step: 8

 8851 23:02:59.815526  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8852 23:02:59.819028  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8853 23:02:59.825713  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8854 23:02:59.828716  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8855 23:02:59.832311  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8856 23:02:59.835102  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8857 23:02:59.838735  iDelay=208, Bit 6, Center 147 (96 ~ 199) 104

 8858 23:02:59.845372  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8859 23:02:59.848676  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8860 23:02:59.852374  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8861 23:02:59.855328  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8862 23:02:59.858310  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8863 23:02:59.865059  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8864 23:02:59.868684  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8865 23:02:59.871894  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8866 23:02:59.875125  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8867 23:02:59.875203  ==

 8868 23:02:59.878700  Dram Type= 6, Freq= 0, CH_1, rank 1

 8869 23:02:59.885170  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8870 23:02:59.885252  ==

 8871 23:02:59.885318  DQS Delay:

 8872 23:02:59.888200  DQS0 = 0, DQS1 = 0

 8873 23:02:59.888275  DQM Delay:

 8874 23:02:59.888336  DQM0 = 136, DQM1 = 133

 8875 23:02:59.891438  DQ Delay:

 8876 23:02:59.895027  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131

 8877 23:02:59.898256  DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135

 8878 23:02:59.901571  DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127

 8879 23:02:59.904640  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8880 23:02:59.904746  

 8881 23:02:59.904837  

 8882 23:02:59.904902  ==

 8883 23:02:59.908219  Dram Type= 6, Freq= 0, CH_1, rank 1

 8884 23:02:59.911433  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8885 23:02:59.914846  ==

 8886 23:02:59.914953  

 8887 23:02:59.915050  

 8888 23:02:59.915144  	TX Vref Scan disable

 8889 23:02:59.918219   == TX Byte 0 ==

 8890 23:02:59.921210  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8891 23:02:59.925113  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8892 23:02:59.928231   == TX Byte 1 ==

 8893 23:02:59.931141  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8894 23:02:59.934897  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8895 23:02:59.937748  ==

 8896 23:02:59.937827  Dram Type= 6, Freq= 0, CH_1, rank 1

 8897 23:02:59.944988  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8898 23:02:59.945093  ==

 8899 23:02:59.956407  

 8900 23:02:59.959847  TX Vref early break, caculate TX vref

 8901 23:02:59.963428  TX Vref=16, minBit 0, minWin=22, winSum=378

 8902 23:02:59.966540  TX Vref=18, minBit 0, minWin=23, winSum=393

 8903 23:02:59.970162  TX Vref=20, minBit 6, minWin=23, winSum=399

 8904 23:02:59.973169  TX Vref=22, minBit 0, minWin=24, winSum=408

 8905 23:02:59.976786  TX Vref=24, minBit 0, minWin=25, winSum=420

 8906 23:02:59.983153  TX Vref=26, minBit 0, minWin=25, winSum=426

 8907 23:02:59.986259  TX Vref=28, minBit 0, minWin=26, winSum=429

 8908 23:02:59.989890  TX Vref=30, minBit 1, minWin=25, winSum=421

 8909 23:02:59.992843  TX Vref=32, minBit 1, minWin=25, winSum=414

 8910 23:02:59.996471  TX Vref=34, minBit 0, minWin=24, winSum=406

 8911 23:03:00.002756  [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28

 8912 23:03:00.002836  

 8913 23:03:00.006607  Final TX Range 0 Vref 28

 8914 23:03:00.006708  

 8915 23:03:00.006801  ==

 8916 23:03:00.009407  Dram Type= 6, Freq= 0, CH_1, rank 1

 8917 23:03:00.013022  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8918 23:03:00.013128  ==

 8919 23:03:00.013280  

 8920 23:03:00.013370  

 8921 23:03:00.016505  	TX Vref Scan disable

 8922 23:03:00.022785  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8923 23:03:00.022889   == TX Byte 0 ==

 8924 23:03:00.026181  u2DelayCellOfst[0]=17 cells (5 PI)

 8925 23:03:00.029995  u2DelayCellOfst[1]=10 cells (3 PI)

 8926 23:03:00.032935  u2DelayCellOfst[2]=0 cells (0 PI)

 8927 23:03:00.036135  u2DelayCellOfst[3]=6 cells (2 PI)

 8928 23:03:00.039758  u2DelayCellOfst[4]=6 cells (2 PI)

 8929 23:03:00.042631  u2DelayCellOfst[5]=17 cells (5 PI)

 8930 23:03:00.046022  u2DelayCellOfst[6]=17 cells (5 PI)

 8931 23:03:00.046111  u2DelayCellOfst[7]=6 cells (2 PI)

 8932 23:03:00.053098  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8933 23:03:00.056002  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8934 23:03:00.056077   == TX Byte 1 ==

 8935 23:03:00.059570  u2DelayCellOfst[8]=0 cells (0 PI)

 8936 23:03:00.062795  u2DelayCellOfst[9]=3 cells (1 PI)

 8937 23:03:00.066221  u2DelayCellOfst[10]=10 cells (3 PI)

 8938 23:03:00.069283  u2DelayCellOfst[11]=6 cells (2 PI)

 8939 23:03:00.072548  u2DelayCellOfst[12]=13 cells (4 PI)

 8940 23:03:00.076171  u2DelayCellOfst[13]=13 cells (4 PI)

 8941 23:03:00.079230  u2DelayCellOfst[14]=13 cells (4 PI)

 8942 23:03:00.082397  u2DelayCellOfst[15]=17 cells (5 PI)

 8943 23:03:00.086031  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8944 23:03:00.092340  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8945 23:03:00.092422  DramC Write-DBI on

 8946 23:03:00.092489  ==

 8947 23:03:00.096125  Dram Type= 6, Freq= 0, CH_1, rank 1

 8948 23:03:00.099082  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8949 23:03:00.102226  ==

 8950 23:03:00.102305  

 8951 23:03:00.102369  

 8952 23:03:00.102461  	TX Vref Scan disable

 8953 23:03:00.105784   == TX Byte 0 ==

 8954 23:03:00.108986  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8955 23:03:00.112666   == TX Byte 1 ==

 8956 23:03:00.115567  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8957 23:03:00.118967  DramC Write-DBI off

 8958 23:03:00.119046  

 8959 23:03:00.119137  [DATLAT]

 8960 23:03:00.119228  Freq=1600, CH1 RK1

 8961 23:03:00.119320  

 8962 23:03:00.122373  DATLAT Default: 0xf

 8963 23:03:00.122448  0, 0xFFFF, sum = 0

 8964 23:03:00.125538  1, 0xFFFF, sum = 0

 8965 23:03:00.128883  2, 0xFFFF, sum = 0

 8966 23:03:00.128990  3, 0xFFFF, sum = 0

 8967 23:03:00.131965  4, 0xFFFF, sum = 0

 8968 23:03:00.132071  5, 0xFFFF, sum = 0

 8969 23:03:00.135318  6, 0xFFFF, sum = 0

 8970 23:03:00.135425  7, 0xFFFF, sum = 0

 8971 23:03:00.138552  8, 0xFFFF, sum = 0

 8972 23:03:00.138632  9, 0xFFFF, sum = 0

 8973 23:03:00.141949  10, 0xFFFF, sum = 0

 8974 23:03:00.142060  11, 0xFFFF, sum = 0

 8975 23:03:00.145057  12, 0xFFFF, sum = 0

 8976 23:03:00.145165  13, 0xFFFF, sum = 0

 8977 23:03:00.148882  14, 0x0, sum = 1

 8978 23:03:00.148967  15, 0x0, sum = 2

 8979 23:03:00.151669  16, 0x0, sum = 3

 8980 23:03:00.151753  17, 0x0, sum = 4

 8981 23:03:00.155202  best_step = 15

 8982 23:03:00.155286  

 8983 23:03:00.155350  ==

 8984 23:03:00.158401  Dram Type= 6, Freq= 0, CH_1, rank 1

 8985 23:03:00.162036  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8986 23:03:00.162145  ==

 8987 23:03:00.164994  RX Vref Scan: 0

 8988 23:03:00.165081  

 8989 23:03:00.165147  RX Vref 0 -> 0, step: 1

 8990 23:03:00.165242  

 8991 23:03:00.168503  RX Delay 19 -> 252, step: 4

 8992 23:03:00.174866  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 8993 23:03:00.178256  iDelay=195, Bit 1, Center 130 (83 ~ 178) 96

 8994 23:03:00.181896  iDelay=195, Bit 2, Center 122 (71 ~ 174) 104

 8995 23:03:00.184845  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8996 23:03:00.187972  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 8997 23:03:00.191565  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8998 23:03:00.197786  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 8999 23:03:00.201476  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 9000 23:03:00.204551  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 9001 23:03:00.207759  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 9002 23:03:00.214503  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 9003 23:03:00.217592  iDelay=195, Bit 11, Center 124 (71 ~ 178) 108

 9004 23:03:00.221214  iDelay=195, Bit 12, Center 140 (87 ~ 194) 108

 9005 23:03:00.224160  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 9006 23:03:00.227619  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 9007 23:03:00.234673  iDelay=195, Bit 15, Center 138 (87 ~ 190) 104

 9008 23:03:00.234789  ==

 9009 23:03:00.237663  Dram Type= 6, Freq= 0, CH_1, rank 1

 9010 23:03:00.240661  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 9011 23:03:00.240741  ==

 9012 23:03:00.240821  DQS Delay:

 9013 23:03:00.244349  DQS0 = 0, DQS1 = 0

 9014 23:03:00.244462  DQM Delay:

 9015 23:03:00.247583  DQM0 = 134, DQM1 = 130

 9016 23:03:00.247688  DQ Delay:

 9017 23:03:00.251002  DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130

 9018 23:03:00.253915  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 9019 23:03:00.257239  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124

 9020 23:03:00.260738  DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138

 9021 23:03:00.264113  

 9022 23:03:00.264222  

 9023 23:03:00.264324  

 9024 23:03:00.264418  [DramC_TX_OE_Calibration] TA2

 9025 23:03:00.267338  Original DQ_B0 (3 6) =30, OEN = 27

 9026 23:03:00.271082  Original DQ_B1 (3 6) =30, OEN = 27

 9027 23:03:00.274313  24, 0x0, End_B0=24 End_B1=24

 9028 23:03:00.277089  25, 0x0, End_B0=25 End_B1=25

 9029 23:03:00.280690  26, 0x0, End_B0=26 End_B1=26

 9030 23:03:00.280816  27, 0x0, End_B0=27 End_B1=27

 9031 23:03:00.283658  28, 0x0, End_B0=28 End_B1=28

 9032 23:03:00.287166  29, 0x0, End_B0=29 End_B1=29

 9033 23:03:00.290254  30, 0x0, End_B0=30 End_B1=30

 9034 23:03:00.294147  31, 0x4141, End_B0=30 End_B1=30

 9035 23:03:00.294235  Byte0 end_step=30  best_step=27

 9036 23:03:00.297140  Byte1 end_step=30  best_step=27

 9037 23:03:00.300229  Byte0 TX OE(2T, 0.5T) = (3, 3)

 9038 23:03:00.304007  Byte1 TX OE(2T, 0.5T) = (3, 3)

 9039 23:03:00.304117  

 9040 23:03:00.304214  

 9041 23:03:00.314019  [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps

 9042 23:03:00.314123  CH1 RK1: MR19=303, MR18=2208

 9043 23:03:00.320585  CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16

 9044 23:03:00.323638  [RxdqsGatingPostProcess] freq 1600

 9045 23:03:00.330403  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 9046 23:03:00.333444  best DQS0 dly(2T, 0.5T) = (1, 1)

 9047 23:03:00.337148  best DQS1 dly(2T, 0.5T) = (1, 1)

 9048 23:03:00.340218  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9049 23:03:00.340337  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9050 23:03:00.343602  best DQS0 dly(2T, 0.5T) = (1, 1)

 9051 23:03:00.346956  best DQS1 dly(2T, 0.5T) = (1, 1)

 9052 23:03:00.349999  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9053 23:03:00.353582  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9054 23:03:00.356589  Pre-setting of DQS Precalculation

 9055 23:03:00.363214  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9056 23:03:00.370184  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9057 23:03:00.376671  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9058 23:03:00.376793  

 9059 23:03:00.376863  

 9060 23:03:00.380139  [Calibration Summary] 3200 Mbps

 9061 23:03:00.380215  CH 0, Rank 0

 9062 23:03:00.382961  SW Impedance     : PASS

 9063 23:03:00.386572  DUTY Scan        : NO K

 9064 23:03:00.386680  ZQ Calibration   : PASS

 9065 23:03:00.389620  Jitter Meter     : NO K

 9066 23:03:00.393244  CBT Training     : PASS

 9067 23:03:00.393319  Write leveling   : PASS

 9068 23:03:00.396500  RX DQS gating    : PASS

 9069 23:03:00.399871  RX DQ/DQS(RDDQC) : PASS

 9070 23:03:00.399956  TX DQ/DQS        : PASS

 9071 23:03:00.403650  RX DATLAT        : PASS

 9072 23:03:00.403733  RX DQ/DQS(Engine): PASS

 9073 23:03:00.406425  TX OE            : PASS

 9074 23:03:00.406543  All Pass.

 9075 23:03:00.406642  

 9076 23:03:00.410216  CH 0, Rank 1

 9077 23:03:00.410301  SW Impedance     : PASS

 9078 23:03:00.413058  DUTY Scan        : NO K

 9079 23:03:00.416877  ZQ Calibration   : PASS

 9080 23:03:00.416960  Jitter Meter     : NO K

 9081 23:03:00.420067  CBT Training     : PASS

 9082 23:03:00.423019  Write leveling   : PASS

 9083 23:03:00.423127  RX DQS gating    : PASS

 9084 23:03:00.426712  RX DQ/DQS(RDDQC) : PASS

 9085 23:03:00.429806  TX DQ/DQS        : PASS

 9086 23:03:00.429891  RX DATLAT        : PASS

 9087 23:03:00.433026  RX DQ/DQS(Engine): PASS

 9088 23:03:00.436412  TX OE            : PASS

 9089 23:03:00.436494  All Pass.

 9090 23:03:00.436559  

 9091 23:03:00.436619  CH 1, Rank 0

 9092 23:03:00.439437  SW Impedance     : PASS

 9093 23:03:00.443009  DUTY Scan        : NO K

 9094 23:03:00.443088  ZQ Calibration   : PASS

 9095 23:03:00.446470  Jitter Meter     : NO K

 9096 23:03:00.449413  CBT Training     : PASS

 9097 23:03:00.449517  Write leveling   : PASS

 9098 23:03:00.453004  RX DQS gating    : PASS

 9099 23:03:00.456154  RX DQ/DQS(RDDQC) : PASS

 9100 23:03:00.456276  TX DQ/DQS        : PASS

 9101 23:03:00.459831  RX DATLAT        : PASS

 9102 23:03:00.459946  RX DQ/DQS(Engine): PASS

 9103 23:03:00.462992  TX OE            : PASS

 9104 23:03:00.463076  All Pass.

 9105 23:03:00.463169  

 9106 23:03:00.466121  CH 1, Rank 1

 9107 23:03:00.466203  SW Impedance     : PASS

 9108 23:03:00.469939  DUTY Scan        : NO K

 9109 23:03:00.473321  ZQ Calibration   : PASS

 9110 23:03:00.473428  Jitter Meter     : NO K

 9111 23:03:00.476570  CBT Training     : PASS

 9112 23:03:00.479919  Write leveling   : PASS

 9113 23:03:00.480027  RX DQS gating    : PASS

 9114 23:03:00.483011  RX DQ/DQS(RDDQC) : PASS

 9115 23:03:00.486030  TX DQ/DQS        : PASS

 9116 23:03:00.486109  RX DATLAT        : PASS

 9117 23:03:00.489240  RX DQ/DQS(Engine): PASS

 9118 23:03:00.492562  TX OE            : PASS

 9119 23:03:00.492641  All Pass.

 9120 23:03:00.492706  

 9121 23:03:00.492777  DramC Write-DBI on

 9122 23:03:00.495886  	PER_BANK_REFRESH: Hybrid Mode

 9123 23:03:00.499562  TX_TRACKING: ON

 9124 23:03:00.505944  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9125 23:03:00.516048  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9126 23:03:00.522930  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9127 23:03:00.526121  [FAST_K] Save calibration result to emmc

 9128 23:03:00.529007  sync common calibartion params.

 9129 23:03:00.532776  sync cbt_mode0:1, 1:1

 9130 23:03:00.532895  dram_init: ddr_geometry: 2

 9131 23:03:00.535777  dram_init: ddr_geometry: 2

 9132 23:03:00.539472  dram_init: ddr_geometry: 2

 9133 23:03:00.539586  0:dram_rank_size:100000000

 9134 23:03:00.542257  1:dram_rank_size:100000000

 9135 23:03:00.549194  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9136 23:03:00.549301  DFS_SHUFFLE_HW_MODE: ON

 9137 23:03:00.555557  dramc_set_vcore_voltage set vcore to 725000

 9138 23:03:00.555680  Read voltage for 1600, 0

 9139 23:03:00.559154  Vio18 = 0

 9140 23:03:00.559233  Vcore = 725000

 9141 23:03:00.559317  Vdram = 0

 9142 23:03:00.562270  Vddq = 0

 9143 23:03:00.562386  Vmddr = 0

 9144 23:03:00.565965  switch to 3200 Mbps bootup

 9145 23:03:00.566051  [DramcRunTimeConfig]

 9146 23:03:00.566115  PHYPLL

 9147 23:03:00.568889  DPM_CONTROL_AFTERK: ON

 9148 23:03:00.572592  PER_BANK_REFRESH: ON

 9149 23:03:00.572678  REFRESH_OVERHEAD_REDUCTION: ON

 9150 23:03:00.575741  CMD_PICG_NEW_MODE: OFF

 9151 23:03:00.578969  XRTWTW_NEW_MODE: ON

 9152 23:03:00.579053  XRTRTR_NEW_MODE: ON

 9153 23:03:00.582551  TX_TRACKING: ON

 9154 23:03:00.582638  RDSEL_TRACKING: OFF

 9155 23:03:00.585637  DQS Precalculation for DVFS: ON

 9156 23:03:00.585714  RX_TRACKING: OFF

 9157 23:03:00.589283  HW_GATING DBG: ON

 9158 23:03:00.589363  ZQCS_ENABLE_LP4: ON

 9159 23:03:00.592489  RX_PICG_NEW_MODE: ON

 9160 23:03:00.595971  TX_PICG_NEW_MODE: ON

 9161 23:03:00.596061  ENABLE_RX_DCM_DPHY: ON

 9162 23:03:00.599458  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9163 23:03:00.602055  DUMMY_READ_FOR_TRACKING: OFF

 9164 23:03:00.605461  !!! SPM_CONTROL_AFTERK: OFF

 9165 23:03:00.605584  !!! SPM could not control APHY

 9166 23:03:00.608964  IMPEDANCE_TRACKING: ON

 9167 23:03:00.612360  TEMP_SENSOR: ON

 9168 23:03:00.612473  HW_SAVE_FOR_SR: OFF

 9169 23:03:00.615905  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9170 23:03:00.619371  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9171 23:03:00.622113  Read ODT Tracking: ON

 9172 23:03:00.622194  Refresh Rate DeBounce: ON

 9173 23:03:00.625424  DFS_NO_QUEUE_FLUSH: ON

 9174 23:03:00.629220  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9175 23:03:00.632260  ENABLE_DFS_RUNTIME_MRW: OFF

 9176 23:03:00.632348  DDR_RESERVE_NEW_MODE: ON

 9177 23:03:00.635445  MR_CBT_SWITCH_FREQ: ON

 9178 23:03:00.639033  =========================

 9179 23:03:00.656873  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9180 23:03:00.660355  dram_init: ddr_geometry: 2

 9181 23:03:00.678420  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9182 23:03:00.681494  dram_init: dram init end (result: 0)

 9183 23:03:00.688234  DRAM-K: Full calibration passed in 24442 msecs

 9184 23:03:00.692103  MRC: failed to locate region type 0.

 9185 23:03:00.692194  DRAM rank0 size:0x100000000,

 9186 23:03:00.695184  DRAM rank1 size=0x100000000

 9187 23:03:00.705207  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9188 23:03:00.711897  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9189 23:03:00.718221  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9190 23:03:00.725032  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9191 23:03:00.728204  DRAM rank0 size:0x100000000,

 9192 23:03:00.731951  DRAM rank1 size=0x100000000

 9193 23:03:00.732037  CBMEM:

 9194 23:03:00.734661  IMD: root @ 0xfffff000 254 entries.

 9195 23:03:00.737957  IMD: root @ 0xffffec00 62 entries.

 9196 23:03:00.741518  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9197 23:03:00.745112  WARNING: RO_VPD is uninitialized or empty.

 9198 23:03:00.751187  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9199 23:03:00.758355  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9200 23:03:00.771304  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9201 23:03:00.782341  BS: romstage times (exec / console): total (unknown) / 23974 ms

 9202 23:03:00.782495  

 9203 23:03:00.782594  

 9204 23:03:00.792238  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9205 23:03:00.795793  ARM64: Exception handlers installed.

 9206 23:03:00.799074  ARM64: Testing exception

 9207 23:03:00.802232  ARM64: Done test exception

 9208 23:03:00.802337  Enumerating buses...

 9209 23:03:00.805835  Show all devs... Before device enumeration.

 9210 23:03:00.808877  Root Device: enabled 1

 9211 23:03:00.812335  CPU_CLUSTER: 0: enabled 1

 9212 23:03:00.812452  CPU: 00: enabled 1

 9213 23:03:00.816098  Compare with tree...

 9214 23:03:00.816219  Root Device: enabled 1

 9215 23:03:00.819188   CPU_CLUSTER: 0: enabled 1

 9216 23:03:00.822464    CPU: 00: enabled 1

 9217 23:03:00.822553  Root Device scanning...

 9218 23:03:00.825924  scan_static_bus for Root Device

 9219 23:03:00.829225  CPU_CLUSTER: 0 enabled

 9220 23:03:00.832327  scan_static_bus for Root Device done

 9221 23:03:00.835950  scan_bus: bus Root Device finished in 8 msecs

 9222 23:03:00.836065  done

 9223 23:03:00.842730  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9224 23:03:00.846122  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9225 23:03:00.852693  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9226 23:03:00.855776  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9227 23:03:00.859407  Allocating resources...

 9228 23:03:00.859499  Reading resources...

 9229 23:03:00.865948  Root Device read_resources bus 0 link: 0

 9230 23:03:00.866065  DRAM rank0 size:0x100000000,

 9231 23:03:00.869150  DRAM rank1 size=0x100000000

 9232 23:03:00.872755  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9233 23:03:00.875981  CPU: 00 missing read_resources

 9234 23:03:00.879258  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9235 23:03:00.886330  Root Device read_resources bus 0 link: 0 done

 9236 23:03:00.886423  Done reading resources.

 9237 23:03:00.892335  Show resources in subtree (Root Device)...After reading.

 9238 23:03:00.895862   Root Device child on link 0 CPU_CLUSTER: 0

 9239 23:03:00.898968    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9240 23:03:00.908991    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9241 23:03:00.909086     CPU: 00

 9242 23:03:00.912467  Root Device assign_resources, bus 0 link: 0

 9243 23:03:00.915432  CPU_CLUSTER: 0 missing set_resources

 9244 23:03:00.919029  Root Device assign_resources, bus 0 link: 0 done

 9245 23:03:00.922189  Done setting resources.

 9246 23:03:00.928990  Show resources in subtree (Root Device)...After assigning values.

 9247 23:03:00.931978   Root Device child on link 0 CPU_CLUSTER: 0

 9248 23:03:00.935627    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9249 23:03:00.945649    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9250 23:03:00.945761     CPU: 00

 9251 23:03:00.948874  Done allocating resources.

 9252 23:03:00.951773  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9253 23:03:00.955181  Enabling resources...

 9254 23:03:00.955294  done.

 9255 23:03:00.961918  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9256 23:03:00.962011  Initializing devices...

 9257 23:03:00.964791  Root Device init

 9258 23:03:00.964881  init hardware done!

 9259 23:03:00.968256  0x00000018: ctrlr->caps

 9260 23:03:00.971471  52.000 MHz: ctrlr->f_max

 9261 23:03:00.971582  0.400 MHz: ctrlr->f_min

 9262 23:03:00.975009  0x40ff8080: ctrlr->voltages

 9263 23:03:00.975129  sclk: 390625

 9264 23:03:00.978717  Bus Width = 1

 9265 23:03:00.978805  sclk: 390625

 9266 23:03:00.981822  Bus Width = 1

 9267 23:03:00.981933  Early init status = 3

 9268 23:03:00.988439  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9269 23:03:00.991648  in-header: 03 fc 00 00 01 00 00 00 

 9270 23:03:00.991742  in-data: 00 

 9271 23:03:00.997942  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9272 23:03:01.001337  in-header: 03 fd 00 00 00 00 00 00 

 9273 23:03:01.005072  in-data: 

 9274 23:03:01.008222  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9275 23:03:01.011323  in-header: 03 fc 00 00 01 00 00 00 

 9276 23:03:01.015077  in-data: 00 

 9277 23:03:01.018355  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9278 23:03:01.023128  in-header: 03 fd 00 00 00 00 00 00 

 9279 23:03:01.026915  in-data: 

 9280 23:03:01.029862  [SSUSB] Setting up USB HOST controller...

 9281 23:03:01.033469  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9282 23:03:01.036708  [SSUSB] phy power-on done.

 9283 23:03:01.039702  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9284 23:03:01.046344  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9285 23:03:01.050148  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9286 23:03:01.056797  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9287 23:03:01.063568  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9288 23:03:01.069887  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9289 23:03:01.076740  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9290 23:03:01.083035  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9291 23:03:01.086474  SPM: binary array size = 0x9dc

 9292 23:03:01.089999  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9293 23:03:01.096630  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9294 23:03:01.103085  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9295 23:03:01.106060  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9296 23:03:01.113070  configure_display: Starting display init

 9297 23:03:01.146536  anx7625_power_on_init: Init interface.

 9298 23:03:01.150469  anx7625_disable_pd_protocol: Disabled PD feature.

 9299 23:03:01.153284  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9300 23:03:01.180695  anx7625_start_dp_work: Secure OCM version=00

 9301 23:03:01.184497  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9302 23:03:01.199116  sp_tx_get_edid_block: EDID Block = 1

 9303 23:03:01.301518  Extracted contents:

 9304 23:03:01.304999  header:          00 ff ff ff ff ff ff 00

 9305 23:03:01.308431  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9306 23:03:01.311462  version:         01 04

 9307 23:03:01.314601  basic params:    95 1f 11 78 0a

 9308 23:03:01.317907  chroma info:     76 90 94 55 54 90 27 21 50 54

 9309 23:03:01.321532  established:     00 00 00

 9310 23:03:01.327923  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9311 23:03:01.331670  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9312 23:03:01.337882  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9313 23:03:01.344599  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9314 23:03:01.351105  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9315 23:03:01.354818  extensions:      00

 9316 23:03:01.354921  checksum:        fb

 9317 23:03:01.354987  

 9318 23:03:01.357909  Manufacturer: IVO Model 57d Serial Number 0

 9319 23:03:01.361012  Made week 0 of 2020

 9320 23:03:01.361127  EDID version: 1.4

 9321 23:03:01.364669  Digital display

 9322 23:03:01.367663  6 bits per primary color channel

 9323 23:03:01.367751  DisplayPort interface

 9324 23:03:01.371452  Maximum image size: 31 cm x 17 cm

 9325 23:03:01.374365  Gamma: 220%

 9326 23:03:01.374465  Check DPMS levels

 9327 23:03:01.378041  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9328 23:03:01.384196  First detailed timing is preferred timing

 9329 23:03:01.384298  Established timings supported:

 9330 23:03:01.387760  Standard timings supported:

 9331 23:03:01.391263  Detailed timings

 9332 23:03:01.394803  Hex of detail: 383680a07038204018303c0035ae10000019

 9333 23:03:01.397622  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9334 23:03:01.404517                 0780 0798 07c8 0820 hborder 0

 9335 23:03:01.407667                 0438 043b 0447 0458 vborder 0

 9336 23:03:01.410911                 -hsync -vsync

 9337 23:03:01.411002  Did detailed timing

 9338 23:03:01.417417  Hex of detail: 000000000000000000000000000000000000

 9339 23:03:01.417543  Manufacturer-specified data, tag 0

 9340 23:03:01.424054  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9341 23:03:01.427635  ASCII string: InfoVision

 9342 23:03:01.431003  Hex of detail: 000000fe00523134304e574635205248200a

 9343 23:03:01.434056  ASCII string: R140NWF5 RH 

 9344 23:03:01.434143  Checksum

 9345 23:03:01.437495  Checksum: 0xfb (valid)

 9346 23:03:01.440925  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9347 23:03:01.444377  DSI data_rate: 832800000 bps

 9348 23:03:01.450999  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9349 23:03:01.454097  anx7625_parse_edid: pixelclock(138800).

 9350 23:03:01.457479   hactive(1920), hsync(48), hfp(24), hbp(88)

 9351 23:03:01.460587   vactive(1080), vsync(12), vfp(3), vbp(17)

 9352 23:03:01.464108  anx7625_dsi_config: config dsi.

 9353 23:03:01.471054  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9354 23:03:01.483437  anx7625_dsi_config: success to config DSI

 9355 23:03:01.487022  anx7625_dp_start: MIPI phy setup OK.

 9356 23:03:01.489987  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9357 23:03:01.493711  mtk_ddp_mode_set invalid vrefresh 60

 9358 23:03:01.496598  main_disp_path_setup

 9359 23:03:01.496720  ovl_layer_smi_id_en

 9360 23:03:01.500233  ovl_layer_smi_id_en

 9361 23:03:01.500323  ccorr_config

 9362 23:03:01.500386  aal_config

 9363 23:03:01.503109  gamma_config

 9364 23:03:01.503188  postmask_config

 9365 23:03:01.506732  dither_config

 9366 23:03:01.510064  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9367 23:03:01.516828                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9368 23:03:01.520213  Root Device init finished in 552 msecs

 9369 23:03:01.523367  CPU_CLUSTER: 0 init

 9370 23:03:01.530365  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9371 23:03:01.533340  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9372 23:03:01.536584  APU_MBOX 0x190000b0 = 0x10001

 9373 23:03:01.539773  APU_MBOX 0x190001b0 = 0x10001

 9374 23:03:01.543421  APU_MBOX 0x190005b0 = 0x10001

 9375 23:03:01.546709  APU_MBOX 0x190006b0 = 0x10001

 9376 23:03:01.549763  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9377 23:03:01.562387  read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps

 9378 23:03:01.575347  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9379 23:03:01.581368  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9380 23:03:01.593511  read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps

 9381 23:03:01.602456  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9382 23:03:01.606006  CPU_CLUSTER: 0 init finished in 81 msecs

 9383 23:03:01.609133  Devices initialized

 9384 23:03:01.612375  Show all devs... After init.

 9385 23:03:01.612475  Root Device: enabled 1

 9386 23:03:01.615445  CPU_CLUSTER: 0: enabled 1

 9387 23:03:01.619085  CPU: 00: enabled 1

 9388 23:03:01.622146  BS: BS_DEV_INIT run times (exec / console): 210 / 447 ms

 9389 23:03:01.625792  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9390 23:03:01.628829  ELOG: NV offset 0x57f000 size 0x1000

 9391 23:03:01.635269  read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps

 9392 23:03:01.642088  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9393 23:03:01.645888  ELOG: Event(17) added with size 13 at 2023-12-03 23:00:49 UTC

 9394 23:03:01.648770  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9395 23:03:01.652767  in-header: 03 ee 00 00 2c 00 00 00 

 9396 23:03:01.665926  in-data: 71 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9397 23:03:01.672475  ELOG: Event(A1) added with size 10 at 2023-12-03 23:00:49 UTC

 9398 23:03:01.679090  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9399 23:03:01.686100  ELOG: Event(A0) added with size 9 at 2023-12-03 23:00:49 UTC

 9400 23:03:01.689392  elog_add_boot_reason: Logged dev mode boot

 9401 23:03:01.692457  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9402 23:03:01.696392  Finalize devices...

 9403 23:03:01.696516  Devices finalized

 9404 23:03:01.702500  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9405 23:03:01.705450  Writing coreboot table at 0xffe64000

 9406 23:03:01.709189   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9407 23:03:01.712511   1. 0000000040000000-00000000400fffff: RAM

 9408 23:03:01.715624   2. 0000000040100000-000000004032afff: RAMSTAGE

 9409 23:03:01.722779   3. 000000004032b000-00000000545fffff: RAM

 9410 23:03:01.726258   4. 0000000054600000-000000005465ffff: BL31

 9411 23:03:01.728732   5. 0000000054660000-00000000ffe63fff: RAM

 9412 23:03:01.735840   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9413 23:03:01.739380   7. 0000000100000000-000000023fffffff: RAM

 9414 23:03:01.739488  Passing 5 GPIOs to payload:

 9415 23:03:01.745356              NAME |       PORT | POLARITY |     VALUE

 9416 23:03:01.749003          EC in RW | 0x000000aa |      low | undefined

 9417 23:03:01.755330      EC interrupt | 0x00000005 |      low | undefined

 9418 23:03:01.758962     TPM interrupt | 0x000000ab |     high | undefined

 9419 23:03:01.762203    SD card detect | 0x00000011 |     high | undefined

 9420 23:03:01.769114    speaker enable | 0x00000093 |     high | undefined

 9421 23:03:01.772297  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9422 23:03:01.775312  in-header: 03 f9 00 00 02 00 00 00 

 9423 23:03:01.775402  in-data: 02 00 

 9424 23:03:01.779107  ADC[4]: Raw value=904357 ID=7

 9425 23:03:01.782272  ADC[3]: Raw value=213441 ID=1

 9426 23:03:01.782362  RAM Code: 0x71

 9427 23:03:01.785306  ADC[6]: Raw value=75332 ID=0

 9428 23:03:01.788800  ADC[5]: Raw value=213441 ID=1

 9429 23:03:01.788893  SKU Code: 0x1

 9430 23:03:01.795789  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c

 9431 23:03:01.798988  coreboot table: 964 bytes.

 9432 23:03:01.802212  IMD ROOT    0. 0xfffff000 0x00001000

 9433 23:03:01.805483  IMD SMALL   1. 0xffffe000 0x00001000

 9434 23:03:01.808723  RO MCACHE   2. 0xffffc000 0x00001104

 9435 23:03:01.811783  CONSOLE     3. 0xfff7c000 0x00080000

 9436 23:03:01.815032  FMAP        4. 0xfff7b000 0x00000452

 9437 23:03:01.818932  TIME STAMP  5. 0xfff7a000 0x00000910

 9438 23:03:01.822237  VBOOT WORK  6. 0xfff66000 0x00014000

 9439 23:03:01.825235  RAMOOPS     7. 0xffe66000 0x00100000

 9440 23:03:01.828997  COREBOOT    8. 0xffe64000 0x00002000

 9441 23:03:01.829119  IMD small region:

 9442 23:03:01.832261    IMD ROOT    0. 0xffffec00 0x00000400

 9443 23:03:01.835410    VPD         1. 0xffffeb80 0x0000006c

 9444 23:03:01.838510    MMC STATUS  2. 0xffffeb60 0x00000004

 9445 23:03:01.845500  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9446 23:03:01.849229  Probing TPM:  done!

 9447 23:03:01.852420  Connected to device vid:did:rid of 1ae0:0028:00

 9448 23:03:01.862083  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9449 23:03:01.865241  Initialized TPM device CR50 revision 0

 9450 23:03:01.868953  Checking cr50 for pending updates

 9451 23:03:01.873477  Reading cr50 TPM mode

 9452 23:03:01.881067  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9453 23:03:01.887837  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9454 23:03:01.927707  read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps

 9455 23:03:01.930749  Checking segment from ROM address 0x40100000

 9456 23:03:01.934364  Checking segment from ROM address 0x4010001c

 9457 23:03:01.940969  Loading segment from ROM address 0x40100000

 9458 23:03:01.941106    code (compression=0)

 9459 23:03:01.950896    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9460 23:03:01.957951  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9461 23:03:01.958076  it's not compressed!

 9462 23:03:01.964214  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9463 23:03:01.967923  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9464 23:03:01.987884  Loading segment from ROM address 0x4010001c

 9465 23:03:01.988018    Entry Point 0x80000000

 9466 23:03:01.991589  Loaded segments

 9467 23:03:01.994551  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9468 23:03:02.001601  Jumping to boot code at 0x80000000(0xffe64000)

 9469 23:03:02.008260  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9470 23:03:02.014748  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9471 23:03:02.022774  read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps

 9472 23:03:02.025713  Checking segment from ROM address 0x40100000

 9473 23:03:02.029473  Checking segment from ROM address 0x4010001c

 9474 23:03:02.035673  Loading segment from ROM address 0x40100000

 9475 23:03:02.035790    code (compression=1)

 9476 23:03:02.042712    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9477 23:03:02.052264  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9478 23:03:02.052390  using LZMA

 9479 23:03:02.061027  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9480 23:03:02.067718  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9481 23:03:02.071983  Loading segment from ROM address 0x4010001c

 9482 23:03:02.072094    Entry Point 0x54601000

 9483 23:03:02.074421  Loaded segments

 9484 23:03:02.077740  NOTICE:  MT8192 bl31_setup

 9485 23:03:02.084524  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9486 23:03:02.087600  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9487 23:03:02.091213  WARNING: region 0:

 9488 23:03:02.094364  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9489 23:03:02.094485  WARNING: region 1:

 9490 23:03:02.101220  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9491 23:03:02.104733  WARNING: region 2:

 9492 23:03:02.107737  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9493 23:03:02.111547  WARNING: region 3:

 9494 23:03:02.114560  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9495 23:03:02.117565  WARNING: region 4:

 9496 23:03:02.124253  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9497 23:03:02.124364  WARNING: region 5:

 9498 23:03:02.127930  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9499 23:03:02.131001  WARNING: region 6:

 9500 23:03:02.134260  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9501 23:03:02.137987  WARNING: region 7:

 9502 23:03:02.140821  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9503 23:03:02.147781  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9504 23:03:02.150650  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9505 23:03:02.154435  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9506 23:03:02.161055  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9507 23:03:02.164750  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9508 23:03:02.167762  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9509 23:03:02.174419  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9510 23:03:02.177419  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9511 23:03:02.184515  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9512 23:03:02.187481  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9513 23:03:02.191086  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9514 23:03:02.197565  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9515 23:03:02.201261  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9516 23:03:02.204314  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9517 23:03:02.210663  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9518 23:03:02.214079  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9519 23:03:02.220661  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9520 23:03:02.224411  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9521 23:03:02.227386  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9522 23:03:02.234073  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9523 23:03:02.237176  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9524 23:03:02.240698  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9525 23:03:02.247486  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9526 23:03:02.250637  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9527 23:03:02.257714  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9528 23:03:02.260673  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9529 23:03:02.264005  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9530 23:03:02.270981  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9531 23:03:02.273985  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9532 23:03:02.280578  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9533 23:03:02.284156  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9534 23:03:02.287136  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9535 23:03:02.294560  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9536 23:03:02.297548  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9537 23:03:02.301089  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9538 23:03:02.303954  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9539 23:03:02.310959  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9540 23:03:02.314537  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9541 23:03:02.317326  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9542 23:03:02.320719  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9543 23:03:02.327741  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9544 23:03:02.330643  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9545 23:03:02.334251  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9546 23:03:02.337156  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9547 23:03:02.344278  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9548 23:03:02.347482  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9549 23:03:02.350676  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9550 23:03:02.354233  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9551 23:03:02.360994  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9552 23:03:02.364290  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9553 23:03:02.370680  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9554 23:03:02.374340  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9555 23:03:02.377524  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9556 23:03:02.384286  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9557 23:03:02.388000  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9558 23:03:02.394231  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9559 23:03:02.397466  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9560 23:03:02.404704  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9561 23:03:02.407739  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9562 23:03:02.411031  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9563 23:03:02.417944  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9564 23:03:02.421012  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9565 23:03:02.428344  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9566 23:03:02.431320  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9567 23:03:02.437629  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9568 23:03:02.441082  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9569 23:03:02.444342  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9570 23:03:02.451509  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9571 23:03:02.454566  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9572 23:03:02.460803  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9573 23:03:02.464317  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9574 23:03:02.470936  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9575 23:03:02.474666  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9576 23:03:02.477882  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9577 23:03:02.484416  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9578 23:03:02.487563  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9579 23:03:02.494350  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9580 23:03:02.497633  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9581 23:03:02.504192  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9582 23:03:02.507672  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9583 23:03:02.514542  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9584 23:03:02.517442  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9585 23:03:02.521225  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9586 23:03:02.528078  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9587 23:03:02.531173  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9588 23:03:02.538100  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9589 23:03:02.541308  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9590 23:03:02.544448  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9591 23:03:02.551259  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9592 23:03:02.554467  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9593 23:03:02.561131  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9594 23:03:02.564733  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9595 23:03:02.571120  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9596 23:03:02.574556  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9597 23:03:02.581073  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9598 23:03:02.584343  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9599 23:03:02.587731  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9600 23:03:02.591325  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9601 23:03:02.598073  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9602 23:03:02.601268  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9603 23:03:02.604319  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9604 23:03:02.611397  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9605 23:03:02.614306  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9606 23:03:02.617939  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9607 23:03:02.624514  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9608 23:03:02.627763  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9609 23:03:02.634467  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9610 23:03:02.638125  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9611 23:03:02.641524  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9612 23:03:02.647783  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9613 23:03:02.651131  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9614 23:03:02.658099  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9615 23:03:02.661749  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9616 23:03:02.664483  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9617 23:03:02.671714  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9618 23:03:02.674771  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9619 23:03:02.677862  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9620 23:03:02.685606  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9621 23:03:02.688287  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9622 23:03:02.691291  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9623 23:03:02.694802  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9624 23:03:02.701305  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9625 23:03:02.704926  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9626 23:03:02.708049  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9627 23:03:02.715014  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9628 23:03:02.718325  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9629 23:03:02.721939  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9630 23:03:02.728466  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9631 23:03:02.731495  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9632 23:03:02.735229  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9633 23:03:02.741804  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9634 23:03:02.744971  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9635 23:03:02.751621  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9636 23:03:02.755580  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9637 23:03:02.758698  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9638 23:03:02.765026  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9639 23:03:02.768378  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9640 23:03:02.771944  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9641 23:03:02.778646  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9642 23:03:02.781887  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9643 23:03:02.788342  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9644 23:03:02.792006  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9645 23:03:02.795210  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9646 23:03:02.801731  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9647 23:03:02.805471  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9648 23:03:02.811688  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9649 23:03:02.815402  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9650 23:03:02.818337  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9651 23:03:02.825190  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9652 23:03:02.828441  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9653 23:03:02.831686  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9654 23:03:02.838459  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9655 23:03:02.842020  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9656 23:03:02.848705  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9657 23:03:02.852360  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9658 23:03:02.855412  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9659 23:03:02.861994  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9660 23:03:02.865765  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9661 23:03:02.868994  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9662 23:03:02.875731  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9663 23:03:02.878709  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9664 23:03:02.885409  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9665 23:03:02.888643  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9666 23:03:02.892271  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9667 23:03:02.898970  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9668 23:03:02.902197  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9669 23:03:02.908714  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9670 23:03:02.911953  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9671 23:03:02.915373  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9672 23:03:02.921858  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9673 23:03:02.925600  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9674 23:03:02.932323  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9675 23:03:02.934956  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9676 23:03:02.938673  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9677 23:03:02.944883  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9678 23:03:02.948277  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9679 23:03:02.951737  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9680 23:03:02.958341  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9681 23:03:02.961566  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9682 23:03:02.968219  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9683 23:03:02.971887  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9684 23:03:02.974933  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9685 23:03:02.981944  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9686 23:03:02.985061  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9687 23:03:02.991624  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9688 23:03:02.994675  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9689 23:03:02.998388  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9690 23:03:03.005197  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9691 23:03:03.008301  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9692 23:03:03.014927  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9693 23:03:03.017840  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9694 23:03:03.024875  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9695 23:03:03.027981  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9696 23:03:03.031048  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9697 23:03:03.038002  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9698 23:03:03.041108  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9699 23:03:03.047993  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9700 23:03:03.051154  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9701 23:03:03.054233  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9702 23:03:03.061456  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9703 23:03:03.064374  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9704 23:03:03.071287  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9705 23:03:03.074630  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9706 23:03:03.081302  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9707 23:03:03.084103  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9708 23:03:03.087627  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9709 23:03:03.094537  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9710 23:03:03.097708  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9711 23:03:03.104321  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9712 23:03:03.108060  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9713 23:03:03.111175  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9714 23:03:03.117914  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9715 23:03:03.120990  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9716 23:03:03.127687  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9717 23:03:03.130702  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9718 23:03:03.134508  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9719 23:03:03.141237  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9720 23:03:03.144383  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9721 23:03:03.150672  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9722 23:03:03.154046  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9723 23:03:03.161349  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9724 23:03:03.164156  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9725 23:03:03.167467  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9726 23:03:03.174310  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9727 23:03:03.177434  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9728 23:03:03.184102  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9729 23:03:03.187752  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9730 23:03:03.190705  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9731 23:03:03.197298  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9732 23:03:03.200653  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9733 23:03:03.204216  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9734 23:03:03.207812  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9735 23:03:03.214110  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9736 23:03:03.217470  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9737 23:03:03.220808  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9738 23:03:03.227348  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9739 23:03:03.230674  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9740 23:03:03.234546  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9741 23:03:03.240683  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9742 23:03:03.244142  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9743 23:03:03.250773  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9744 23:03:03.254070  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9745 23:03:03.257173  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9746 23:03:03.263806  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9747 23:03:03.267548  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9748 23:03:03.270739  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9749 23:03:03.277031  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9750 23:03:03.280688  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9751 23:03:03.284079  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9752 23:03:03.290536  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9753 23:03:03.294367  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9754 23:03:03.297345  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9755 23:03:03.303914  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9756 23:03:03.307619  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9757 23:03:03.314234  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9758 23:03:03.317291  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9759 23:03:03.320952  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9760 23:03:03.327454  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9761 23:03:03.330402  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9762 23:03:03.333949  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9763 23:03:03.340438  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9764 23:03:03.343980  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9765 23:03:03.350327  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9766 23:03:03.353684  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9767 23:03:03.357018  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9768 23:03:03.363818  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9769 23:03:03.367011  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9770 23:03:03.370808  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9771 23:03:03.376876  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9772 23:03:03.380228  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9773 23:03:03.383736  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9774 23:03:03.386807  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9775 23:03:03.390036  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9776 23:03:03.396663  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9777 23:03:03.400376  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9778 23:03:03.403943  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9779 23:03:03.406820  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9780 23:03:03.413462  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9781 23:03:03.416514  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9782 23:03:03.420047  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9783 23:03:03.426759  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9784 23:03:03.430028  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9785 23:03:03.433572  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9786 23:03:03.440407  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9787 23:03:03.443467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9788 23:03:03.449976  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9789 23:03:03.453282  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9790 23:03:03.456627  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9791 23:03:03.463367  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9792 23:03:03.466798  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9793 23:03:03.469754  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9794 23:03:03.477014  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9795 23:03:03.480365  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9796 23:03:03.486740  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9797 23:03:03.489693  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9798 23:03:03.496834  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9799 23:03:03.500003  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9800 23:03:03.503220  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9801 23:03:03.509953  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9802 23:03:03.512831  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9803 23:03:03.520098  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9804 23:03:03.523082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9805 23:03:03.526198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9806 23:03:03.533408  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9807 23:03:03.536383  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9808 23:03:03.543200  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9809 23:03:03.546408  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9810 23:03:03.550039  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9811 23:03:03.556213  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9812 23:03:03.559558  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9813 23:03:03.566146  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9814 23:03:03.570025  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9815 23:03:03.577298  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9816 23:03:03.579234  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9817 23:03:03.582925  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9818 23:03:03.589521  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9819 23:03:03.592848  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9820 23:03:03.599351  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9821 23:03:03.602938  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9822 23:03:03.606057  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9823 23:03:03.612760  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9824 23:03:03.615837  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9825 23:03:03.622858  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9826 23:03:03.626263  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9827 23:03:03.629523  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9828 23:03:03.636276  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9829 23:03:03.639201  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9830 23:03:03.646026  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9831 23:03:03.649162  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9832 23:03:03.652856  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9833 23:03:03.659561  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9834 23:03:03.662625  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9835 23:03:03.669195  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9836 23:03:03.672605  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9837 23:03:03.676209  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9838 23:03:03.682618  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9839 23:03:03.685786  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9840 23:03:03.692447  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9841 23:03:03.695884  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9842 23:03:03.699466  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9843 23:03:03.705572  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9844 23:03:03.709238  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9845 23:03:03.715665  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9846 23:03:03.719321  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9847 23:03:03.725542  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9848 23:03:03.729236  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9849 23:03:03.732049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9850 23:03:03.739234  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9851 23:03:03.742587  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9852 23:03:03.749198  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9853 23:03:03.752049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9854 23:03:03.755725  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9855 23:03:03.762062  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9856 23:03:03.765729  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9857 23:03:03.772739  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9858 23:03:03.775777  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9859 23:03:03.778924  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9860 23:03:03.785748  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9861 23:03:03.789246  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9862 23:03:03.795480  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9863 23:03:03.798791  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9864 23:03:03.805347  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9865 23:03:03.809087  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9866 23:03:03.812074  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9867 23:03:03.819082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9868 23:03:03.822280  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9869 23:03:03.828852  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9870 23:03:03.832054  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9871 23:03:03.838602  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9872 23:03:03.842358  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9873 23:03:03.845408  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9874 23:03:03.851963  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9875 23:03:03.855469  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9876 23:03:03.862057  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9877 23:03:03.865811  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9878 23:03:03.871918  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9879 23:03:03.875212  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9880 23:03:03.882044  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9881 23:03:03.885219  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9882 23:03:03.888704  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9883 23:03:03.895583  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9884 23:03:03.898505  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9885 23:03:03.905361  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9886 23:03:03.908711  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9887 23:03:03.915640  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9888 23:03:03.918540  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9889 23:03:03.921698  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9890 23:03:03.928233  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9891 23:03:03.932314  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9892 23:03:03.938737  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9893 23:03:03.941453  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9894 23:03:03.948344  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9895 23:03:03.951953  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9896 23:03:03.955299  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9897 23:03:03.961384  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9898 23:03:03.964796  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9899 23:03:03.971344  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9900 23:03:03.975225  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9901 23:03:03.981819  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9902 23:03:03.984859  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9903 23:03:03.991803  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9904 23:03:03.995082  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9905 23:03:03.997883  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9906 23:03:04.004796  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9907 23:03:04.007821  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9908 23:03:04.014782  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9909 23:03:04.018028  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9910 23:03:04.024466  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9911 23:03:04.027938  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9912 23:03:04.034832  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9913 23:03:04.038160  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9914 23:03:04.044574  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9915 23:03:04.048287  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9916 23:03:04.051286  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9917 23:03:04.058043  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9918 23:03:04.060930  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9919 23:03:04.068087  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9920 23:03:04.071136  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9921 23:03:04.078368  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9922 23:03:04.081301  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9923 23:03:04.088231  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9924 23:03:04.091248  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9925 23:03:04.097927  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9926 23:03:04.101824  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9927 23:03:04.108259  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9928 23:03:04.111339  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9929 23:03:04.117520  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9930 23:03:04.121182  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9931 23:03:04.127608  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9932 23:03:04.130859  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9933 23:03:04.137541  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9934 23:03:04.140876  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9935 23:03:04.147917  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9936 23:03:04.150878  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9937 23:03:04.157192  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9938 23:03:04.157302  INFO:    [APUAPC] vio 0

 9939 23:03:04.164435  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9940 23:03:04.167427  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9941 23:03:04.170996  INFO:    [APUAPC] D0_APC_0: 0x400510

 9942 23:03:04.174378  INFO:    [APUAPC] D0_APC_1: 0x0

 9943 23:03:04.177534  INFO:    [APUAPC] D0_APC_2: 0x1540

 9944 23:03:04.180666  INFO:    [APUAPC] D0_APC_3: 0x0

 9945 23:03:04.183974  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9946 23:03:04.187410  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9947 23:03:04.190837  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9948 23:03:04.194258  INFO:    [APUAPC] D1_APC_3: 0x0

 9949 23:03:04.197266  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9950 23:03:04.200699  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9951 23:03:04.203884  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9952 23:03:04.207615  INFO:    [APUAPC] D2_APC_3: 0x0

 9953 23:03:04.210535  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9954 23:03:04.214121  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9955 23:03:04.217194  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9956 23:03:04.220383  INFO:    [APUAPC] D3_APC_3: 0x0

 9957 23:03:04.224163  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9958 23:03:04.227280  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9959 23:03:04.230448  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9960 23:03:04.230537  INFO:    [APUAPC] D4_APC_3: 0x0

 9961 23:03:04.237389  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9962 23:03:04.240530  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9963 23:03:04.243590  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9964 23:03:04.243684  INFO:    [APUAPC] D5_APC_3: 0x0

 9965 23:03:04.247128  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9966 23:03:04.250597  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9967 23:03:04.253450  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9968 23:03:04.256755  INFO:    [APUAPC] D6_APC_3: 0x0

 9969 23:03:04.260396  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9970 23:03:04.263448  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9971 23:03:04.267206  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9972 23:03:04.270199  INFO:    [APUAPC] D7_APC_3: 0x0

 9973 23:03:04.273296  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9974 23:03:04.277126  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9975 23:03:04.280271  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9976 23:03:04.283872  INFO:    [APUAPC] D8_APC_3: 0x0

 9977 23:03:04.286827  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9978 23:03:04.290040  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9979 23:03:04.293631  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9980 23:03:04.296774  INFO:    [APUAPC] D9_APC_3: 0x0

 9981 23:03:04.299979  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9982 23:03:04.303504  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9983 23:03:04.306759  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9984 23:03:04.310199  INFO:    [APUAPC] D10_APC_3: 0x0

 9985 23:03:04.313541  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9986 23:03:04.316561  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9987 23:03:04.320061  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9988 23:03:04.323357  INFO:    [APUAPC] D11_APC_3: 0x0

 9989 23:03:04.326449  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9990 23:03:04.330228  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9991 23:03:04.333097  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9992 23:03:04.336861  INFO:    [APUAPC] D12_APC_3: 0x0

 9993 23:03:04.340061  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9994 23:03:04.343422  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9995 23:03:04.346774  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9996 23:03:04.349916  INFO:    [APUAPC] D13_APC_3: 0x0

 9997 23:03:04.353759  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9998 23:03:04.356692  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9999 23:03:04.360215  INFO:    [APUAPC] D14_APC_2: 0x3fffff

10000 23:03:04.363246  INFO:    [APUAPC] D14_APC_3: 0x0

10001 23:03:04.366803  INFO:    [APUAPC] D15_APC_0: 0xffffffff

10002 23:03:04.370123  INFO:    [APUAPC] D15_APC_1: 0xffffffff

10003 23:03:04.373210  INFO:    [APUAPC] D15_APC_2: 0x3fffff

10004 23:03:04.376925  INFO:    [APUAPC] D15_APC_3: 0x0

10005 23:03:04.379859  INFO:    [APUAPC] APC_CON: 0x4

10006 23:03:04.383431  INFO:    [NOCDAPC] D0_APC_0: 0x0

10007 23:03:04.386638  INFO:    [NOCDAPC] D0_APC_1: 0x0

10008 23:03:04.389772  INFO:    [NOCDAPC] D1_APC_0: 0x0

10009 23:03:04.393135  INFO:    [NOCDAPC] D1_APC_1: 0xfff

10010 23:03:04.393226  INFO:    [NOCDAPC] D2_APC_0: 0x0

10011 23:03:04.396879  INFO:    [NOCDAPC] D2_APC_1: 0xfff

10012 23:03:04.399796  INFO:    [NOCDAPC] D3_APC_0: 0x0

10013 23:03:04.403177  INFO:    [NOCDAPC] D3_APC_1: 0xfff

10014 23:03:04.406573  INFO:    [NOCDAPC] D4_APC_0: 0x0

10015 23:03:04.410031  INFO:    [NOCDAPC] D4_APC_1: 0xfff

10016 23:03:04.412843  INFO:    [NOCDAPC] D5_APC_0: 0x0

10017 23:03:04.416434  INFO:    [NOCDAPC] D5_APC_1: 0xfff

10018 23:03:04.420392  INFO:    [NOCDAPC] D6_APC_0: 0x0

10019 23:03:04.423528  INFO:    [NOCDAPC] D6_APC_1: 0xfff

10020 23:03:04.426469  INFO:    [NOCDAPC] D7_APC_0: 0x0

10021 23:03:04.426564  INFO:    [NOCDAPC] D7_APC_1: 0xfff

10022 23:03:04.429782  INFO:    [NOCDAPC] D8_APC_0: 0x0

10023 23:03:04.433225  INFO:    [NOCDAPC] D8_APC_1: 0xfff

10024 23:03:04.436358  INFO:    [NOCDAPC] D9_APC_0: 0x0

10025 23:03:04.439950  INFO:    [NOCDAPC] D9_APC_1: 0xfff

10026 23:03:04.442848  INFO:    [NOCDAPC] D10_APC_0: 0x0

10027 23:03:04.446499  INFO:    [NOCDAPC] D10_APC_1: 0xfff

10028 23:03:04.449564  INFO:    [NOCDAPC] D11_APC_0: 0x0

10029 23:03:04.453236  INFO:    [NOCDAPC] D11_APC_1: 0xfff

10030 23:03:04.456269  INFO:    [NOCDAPC] D12_APC_0: 0x0

10031 23:03:04.459570  INFO:    [NOCDAPC] D12_APC_1: 0xfff

10032 23:03:04.463053  INFO:    [NOCDAPC] D13_APC_0: 0x0

10033 23:03:04.466077  INFO:    [NOCDAPC] D13_APC_1: 0xfff

10034 23:03:04.469304  INFO:    [NOCDAPC] D14_APC_0: 0x0

10035 23:03:04.469394  INFO:    [NOCDAPC] D14_APC_1: 0xfff

10036 23:03:04.473227  INFO:    [NOCDAPC] D15_APC_0: 0x0

10037 23:03:04.476246  INFO:    [NOCDAPC] D15_APC_1: 0xfff

10038 23:03:04.479857  INFO:    [NOCDAPC] APC_CON: 0x4

10039 23:03:04.483070  INFO:    [APUAPC] set_apusys_apc done

10040 23:03:04.486700  INFO:    [DEVAPC] devapc_init done

10041 23:03:04.489772  INFO:    GICv3 without legacy support detected.

10042 23:03:04.496243  INFO:    ARM GICv3 driver initialized in EL3

10043 23:03:04.499809  INFO:    Maximum SPI INTID supported: 639

10044 23:03:04.503041  INFO:    BL31: Initializing runtime services

10045 23:03:04.509467  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

10046 23:03:04.509582  INFO:    SPM: enable CPC mode

10047 23:03:04.516339  INFO:    mcdi ready for mcusys-off-idle and system suspend

10048 23:03:04.519415  INFO:    BL31: Preparing for EL3 exit to normal world

10049 23:03:04.526346  INFO:    Entry point address = 0x80000000

10050 23:03:04.526484  INFO:    SPSR = 0x8

10051 23:03:04.532489  

10052 23:03:04.532592  

10053 23:03:04.532657  

10054 23:03:04.535609  Starting depthcharge on Spherion...

10055 23:03:04.535692  

10056 23:03:04.535764  Wipe memory regions:

10057 23:03:04.535833  

10058 23:03:04.536489  end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10059 23:03:04.536591  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10060 23:03:04.536940  Setting prompt string to ['asurada:']
10061 23:03:04.537022  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10062 23:03:04.539231  	[0x00000040000000, 0x00000054600000)

10063 23:03:04.661198  

10064 23:03:04.661336  	[0x00000054660000, 0x00000080000000)

10065 23:03:04.921644  

10066 23:03:04.921784  	[0x000000821a7280, 0x000000ffe64000)

10067 23:03:05.666283  

10068 23:03:05.666415  	[0x00000100000000, 0x00000240000000)

10069 23:03:07.555147  

10070 23:03:07.558454  Initializing XHCI USB controller at 0x11200000.

10071 23:03:08.597424  

10072 23:03:08.600556  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10073 23:03:08.600688  

10074 23:03:08.600798  

10075 23:03:08.600891  

10076 23:03:08.601215  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10078 23:03:08.701600  asurada: tftpboot 192.168.201.1 12172473/tftp-deploy-msudd3vb/kernel/image.itb 12172473/tftp-deploy-msudd3vb/kernel/cmdline 

10079 23:03:08.701756  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10080 23:03:08.701866  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10081 23:03:08.705969  tftpboot 192.168.201.1 12172473/tftp-deploy-msudd3vb/kernel/image.itp-deploy-msudd3vb/kernel/cmdline 

10082 23:03:08.706094  

10083 23:03:08.706200  Waiting for link

10084 23:03:08.866773  

10085 23:03:08.866937  R8152: Initializing

10086 23:03:08.867037  

10087 23:03:08.870081  Version 9 (ocp_data = 6010)

10088 23:03:08.870204  

10089 23:03:08.873255  R8152: Done initializing

10090 23:03:08.873336  

10091 23:03:08.873418  Adding net device

10092 23:03:10.756517  

10093 23:03:10.756689  done.

10094 23:03:10.756764  

10095 23:03:10.756826  MAC: 00:e0:4c:78:7a:aa

10096 23:03:10.756886  

10097 23:03:10.759068  Sending DHCP discover... done.

10098 23:03:10.759188  

10099 23:03:10.763223  Waiting for reply... done.

10100 23:03:10.763343  

10101 23:03:10.765607  Sending DHCP request... done.

10102 23:03:10.765701  

10103 23:03:10.769000  Waiting for reply... done.

10104 23:03:10.769084  

10105 23:03:10.769148  My ip is 192.168.201.12

10106 23:03:10.769247  

10107 23:03:10.772565  The DHCP server ip is 192.168.201.1

10108 23:03:10.772696  

10109 23:03:10.779147  TFTP server IP predefined by user: 192.168.201.1

10110 23:03:10.779251  

10111 23:03:10.786065  Bootfile predefined by user: 12172473/tftp-deploy-msudd3vb/kernel/image.itb

10112 23:03:10.786167  

10113 23:03:10.786272  Sending tftp read request... done.

10114 23:03:10.789382  

10115 23:03:10.792591  Waiting for the transfer... 

10116 23:03:10.792726  

10117 23:03:11.070327  00000000 ################################################################

10118 23:03:11.070481  

10119 23:03:11.352197  00080000 ################################################################

10120 23:03:11.352360  

10121 23:03:11.617031  00100000 ################################################################

10122 23:03:11.617193  

10123 23:03:11.872050  00180000 ################################################################

10124 23:03:11.872184  

10125 23:03:12.133878  00200000 ################################################################

10126 23:03:12.134015  

10127 23:03:12.393320  00280000 ################################################################

10128 23:03:12.393477  

10129 23:03:12.649833  00300000 ################################################################

10130 23:03:12.650005  

10131 23:03:12.902889  00380000 ################################################################

10132 23:03:12.903033  

10133 23:03:13.150045  00400000 ################################################################

10134 23:03:13.150207  

10135 23:03:13.399021  00480000 ################################################################

10136 23:03:13.399193  

10137 23:03:13.645447  00500000 ################################################################

10138 23:03:13.645613  

10139 23:03:13.891122  00580000 ################################################################

10140 23:03:13.891316  

10141 23:03:14.139729  00600000 ################################################################

10142 23:03:14.139906  

10143 23:03:14.387454  00680000 ################################################################

10144 23:03:14.387620  

10145 23:03:14.639874  00700000 ################################################################

10146 23:03:14.640055  

10147 23:03:14.903956  00780000 ################################################################

10148 23:03:14.904100  

10149 23:03:15.152907  00800000 ################################################################

10150 23:03:15.153081  

10151 23:03:15.407205  00880000 ################################################################

10152 23:03:15.407351  

10153 23:03:15.654500  00900000 ################################################################

10154 23:03:15.654646  

10155 23:03:15.904309  00980000 ################################################################

10156 23:03:15.904461  

10157 23:03:16.147186  00a00000 ################################################################

10158 23:03:16.147347  

10159 23:03:16.391331  00a80000 ################################################################

10160 23:03:16.391498  

10161 23:03:16.635588  00b00000 ################################################################

10162 23:03:16.635757  

10163 23:03:16.877971  00b80000 ################################################################

10164 23:03:16.878128  

10165 23:03:17.128606  00c00000 ################################################################

10166 23:03:17.128749  

10167 23:03:17.371314  00c80000 ################################################################

10168 23:03:17.371481  

10169 23:03:17.615821  00d00000 ################################################################

10170 23:03:17.615983  

10171 23:03:17.858338  00d80000 ################################################################

10172 23:03:17.858510  

10173 23:03:18.109012  00e00000 ################################################################

10174 23:03:18.109180  

10175 23:03:18.356179  00e80000 ################################################################

10176 23:03:18.356380  

10177 23:03:18.604351  00f00000 ################################################################

10178 23:03:18.604515  

10179 23:03:18.844981  00f80000 ################################################################

10180 23:03:18.845154  

10181 23:03:19.090910  01000000 ################################################################

10182 23:03:19.091072  

10183 23:03:19.329116  01080000 ################################################################

10184 23:03:19.329287  

10185 23:03:19.564433  01100000 ################################################################

10186 23:03:19.564563  

10187 23:03:19.802455  01180000 ################################################################

10188 23:03:19.802601  

10189 23:03:21.432600  01200000 ################################################################

10190 23:03:21.432788  

10191 23:03:21.432858  01280000 ################################################################

10192 23:03:21.432960  

10193 23:03:21.433034  01300000 ################################################################

10194 23:03:21.433111  

10195 23:03:21.433166  01380000 ################################################################

10196 23:03:21.433223  

10197 23:03:21.433278  01400000 ################################################################

10198 23:03:21.433335  

10199 23:03:21.433389  01480000 ################################################################

10200 23:03:21.433444  

10201 23:03:21.504841  01500000 ################################################################

10202 23:03:21.504982  

10203 23:03:21.742526  01580000 ################################################################

10204 23:03:21.742677  

10205 23:03:21.988019  01600000 ################################################################

10206 23:03:21.988162  

10207 23:03:22.229712  01680000 ################################################################

10208 23:03:22.229841  

10209 23:03:22.475965  01700000 ################################################################

10210 23:03:22.476098  

10211 23:03:22.726428  01780000 ################################################################

10212 23:03:22.726563  

10213 23:03:22.975159  01800000 ################################################################

10214 23:03:22.975306  

10215 23:03:23.234023  01880000 ################################################################

10216 23:03:23.234164  

10217 23:03:23.500500  01900000 ################################################################

10218 23:03:23.500659  

10219 23:03:23.750358  01980000 ################################################################

10220 23:03:23.750517  

10221 23:03:23.997478  01a00000 ################################################################

10222 23:03:23.997646  

10223 23:03:24.246023  01a80000 ################################################################

10224 23:03:24.246184  

10225 23:03:24.501173  01b00000 ################################################################

10226 23:03:24.501327  

10227 23:03:24.531538  01b80000 ####### done.

10228 23:03:24.531649  

10229 23:03:24.534543  The bootfile was 28892614 bytes long.

10230 23:03:24.534627  

10231 23:03:24.538090  Sending tftp read request... done.

10232 23:03:24.538172  

10233 23:03:24.538236  Waiting for the transfer... 

10234 23:03:24.538296  

10235 23:03:24.541183  00000000 # done.

10236 23:03:24.541294  

10237 23:03:24.547967  Command line loaded dynamically from TFTP file: 12172473/tftp-deploy-msudd3vb/kernel/cmdline

10238 23:03:24.548048  

10239 23:03:24.571332  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10240 23:03:24.571456  

10241 23:03:24.571526  Loading FIT.

10242 23:03:24.571587  

10243 23:03:24.574471  Image ramdisk-1 has 17793953 bytes.

10244 23:03:24.574563  

10245 23:03:24.577996  Image fdt-1 has 47278 bytes.

10246 23:03:24.578077  

10247 23:03:24.581527  Image kernel-1 has 11049348 bytes.

10248 23:03:24.581653  

10249 23:03:24.591013  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10250 23:03:24.591096  

10251 23:03:24.607824  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10252 23:03:24.607915  

10253 23:03:24.611428  Choosing best match conf-1 for compat google,spherion-rev2.

10254 23:03:24.617018  

10255 23:03:24.621343  Connected to device vid:did:rid of 1ae0:0028:00

10256 23:03:24.629829  

10257 23:03:24.633244  tpm_get_response: command 0x17b, return code 0x0

10258 23:03:24.633326  

10259 23:03:24.636339  ec_init: CrosEC protocol v3 supported (256, 248)

10260 23:03:24.640352  

10261 23:03:24.643629  tpm_cleanup: add release locality here.

10262 23:03:24.643710  

10263 23:03:24.643774  Shutting down all USB controllers.

10264 23:03:24.647157  

10265 23:03:24.647237  Removing current net device

10266 23:03:24.647301  

10267 23:03:24.653831  Exiting depthcharge with code 4 at timestamp: 49380495

10268 23:03:24.653912  

10269 23:03:24.656965  LZMA decompressing kernel-1 to 0x821a6718

10270 23:03:24.657047  

10271 23:03:24.660076  LZMA decompressing kernel-1 to 0x40000000

10272 23:03:26.048389  

10273 23:03:26.048535  jumping to kernel

10274 23:03:26.049002  end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10275 23:03:26.049107  start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10276 23:03:26.049195  Setting prompt string to ['Linux version [0-9]']
10277 23:03:26.049267  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10278 23:03:26.049336  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10279 23:03:26.130170  

10280 23:03:26.133489  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10281 23:03:26.136932  start: 2.2.5.1 login-action (timeout 00:04:04) [common]
10282 23:03:26.137035  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10283 23:03:26.137142  Setting prompt string to []
10284 23:03:26.137257  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10285 23:03:26.137359  Using line separator: #'\n'#
10286 23:03:26.137454  No login prompt set.
10287 23:03:26.137548  Parsing kernel messages
10288 23:03:26.137628  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10289 23:03:26.137733  [login-action] Waiting for messages, (timeout 00:04:04)
10290 23:03:26.156309  [    0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec  3 22:38:18 UTC 2023

10291 23:03:26.159878  [    0.000000] random: crng init done

10292 23:03:26.166914  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10293 23:03:26.170174  [    0.000000] efi: UEFI not found.

10294 23:03:26.176326  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10295 23:03:26.186264  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10296 23:03:26.196439  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10297 23:03:26.202965  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10298 23:03:26.209785  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10299 23:03:26.216063  [    0.000000] printk: bootconsole [mtk8250] enabled

10300 23:03:26.222420  [    0.000000] NUMA: No NUMA configuration found

10301 23:03:26.229277  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10302 23:03:26.236285  [    0.000000] NUMA: NODE_DATA [mem 0x23efcfa00-0x23efd1fff]

10303 23:03:26.236398  [    0.000000] Zone ranges:

10304 23:03:26.242967  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10305 23:03:26.245722  [    0.000000]   DMA32    empty

10306 23:03:26.252274  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10307 23:03:26.255719  [    0.000000] Movable zone start for each node

10308 23:03:26.258978  [    0.000000] Early memory node ranges

10309 23:03:26.265791  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10310 23:03:26.272138  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10311 23:03:26.278885  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10312 23:03:26.285732  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10313 23:03:26.292453  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10314 23:03:26.299035  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10315 23:03:26.354990  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10316 23:03:26.361909  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10317 23:03:26.368388  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10318 23:03:26.371932  [    0.000000] psci: probing for conduit method from DT.

10319 23:03:26.378443  [    0.000000] psci: PSCIv1.1 detected in firmware.

10320 23:03:26.381390  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10321 23:03:26.388792  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10322 23:03:26.391870  [    0.000000] psci: SMC Calling Convention v1.2

10323 23:03:26.398278  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10324 23:03:26.401363  [    0.000000] Detected VIPT I-cache on CPU0

10325 23:03:26.408166  [    0.000000] CPU features: detected: GIC system register CPU interface

10326 23:03:26.414779  [    0.000000] CPU features: detected: Virtualization Host Extensions

10327 23:03:26.421185  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10328 23:03:26.428223  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10329 23:03:26.434499  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10330 23:03:26.444420  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10331 23:03:26.448121  [    0.000000] alternatives: applying boot alternatives

10332 23:03:26.454909  [    0.000000] Fallback order for Node 0: 0 

10333 23:03:26.461517  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10334 23:03:26.464439  [    0.000000] Policy zone: Normal

10335 23:03:26.487902  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3,tcp,hard ip=dhcp tftpserverip=192.168.201.1

10336 23:03:26.497977  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10337 23:03:26.508546  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10338 23:03:26.518604  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10339 23:03:26.524633  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10340 23:03:26.528347  <6>[    0.000000] software IO TLB: area num 8.

10341 23:03:26.584849  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10342 23:03:26.733655  <6>[    0.000000] Memory: 7952172K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400596K reserved, 32768K cma-reserved)

10343 23:03:26.740655  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10344 23:03:26.746879  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10345 23:03:26.750114  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10346 23:03:26.756939  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10347 23:03:26.763803  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10348 23:03:26.766882  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10349 23:03:26.776782  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10350 23:03:26.783536  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10351 23:03:26.790257  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10352 23:03:26.796979  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10353 23:03:26.799753  <6>[    0.000000] GICv3: 608 SPIs implemented

10354 23:03:26.803430  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10355 23:03:26.809693  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10356 23:03:26.812952  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10357 23:03:26.820066  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10358 23:03:26.832920  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10359 23:03:26.846557  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10360 23:03:26.852552  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10361 23:03:26.860038  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10362 23:03:26.873885  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10363 23:03:26.880044  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10364 23:03:26.886916  <6>[    0.009182] Console: colour dummy device 80x25

10365 23:03:26.896427  <6>[    0.013904] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10366 23:03:26.903641  <6>[    0.024411] pid_max: default: 32768 minimum: 301

10367 23:03:26.906523  <6>[    0.029283] LSM: Security Framework initializing

10368 23:03:26.912940  <6>[    0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10369 23:03:26.922816  <6>[    0.042002] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10370 23:03:26.932706  <6>[    0.051453] cblist_init_generic: Setting adjustable number of callback queues.

10371 23:03:26.936016  <6>[    0.058894] cblist_init_generic: Setting shift to 3 and lim to 1.

10372 23:03:26.945935  <6>[    0.065232] cblist_init_generic: Setting adjustable number of callback queues.

10373 23:03:26.952638  <6>[    0.072659] cblist_init_generic: Setting shift to 3 and lim to 1.

10374 23:03:26.955717  <6>[    0.079097] rcu: Hierarchical SRCU implementation.

10375 23:03:26.962903  <6>[    0.079099] rcu: 	Max phase no-delay instances is 1000.

10376 23:03:26.969126  <6>[    0.079124] printk: bootconsole [mtk8250] printing thread started

10377 23:03:26.975520  <6>[    0.097420] EFI services will not be available.

10378 23:03:26.979342  <6>[    0.097622] smp: Bringing up secondary CPUs ...

10379 23:03:26.985388  <6>[    0.097933] Detected VIPT I-cache on CPU1

10380 23:03:26.992061  <6>[    0.098003] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10381 23:03:26.999016  <6>[    0.098036] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10382 23:03:27.008222  <6>[    0.125856] Detected VIPT I-cache on CPU2

10383 23:03:27.014983  <6>[    0.125898] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10384 23:03:27.022036  <6>[    0.125913] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10385 23:03:27.028552  <6>[    0.126157] Detected VIPT I-cache on CPU3

10386 23:03:27.035000  <6>[    0.126199] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10387 23:03:27.041772  <6>[    0.126213] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10388 23:03:27.044613  <6>[    0.126523] CPU features: detected: Spectre-v4

10389 23:03:27.051640  <6>[    0.126529] CPU features: detected: Spectre-BHB

10390 23:03:27.054836  <6>[    0.126534] Detected PIPT I-cache on CPU4

10391 23:03:27.061196  <6>[    0.126592] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10392 23:03:27.067957  <6>[    0.126608] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10393 23:03:27.074706  <6>[    0.126900] Detected PIPT I-cache on CPU5

10394 23:03:27.081188  <6>[    0.126959] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10395 23:03:27.087697  <6>[    0.126976] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10396 23:03:27.091115  <6>[    0.127252] Detected PIPT I-cache on CPU6

10397 23:03:27.101157  <6>[    0.127316] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10398 23:03:27.108016  <6>[    0.127332] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10399 23:03:27.111338  <6>[    0.127623] Detected PIPT I-cache on CPU7

10400 23:03:27.117526  <6>[    0.127688] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10401 23:03:27.124633  <6>[    0.127704] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10402 23:03:27.127558  <6>[    0.127750] smp: Brought up 1 node, 8 CPUs

10403 23:03:27.134554  <6>[    0.127754] SMP: Total of 8 processors activated.

10404 23:03:27.137345  <6>[    0.127757] CPU features: detected: 32-bit EL0 Support

10405 23:03:27.147403  <6>[    0.127759] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10406 23:03:27.153949  <6>[    0.127762] CPU features: detected: Common not Private translations

10407 23:03:27.160678  <6>[    0.127763] CPU features: detected: CRC32 instructions

10408 23:03:27.167124  <6>[    0.127766] CPU features: detected: RCpc load-acquire (LDAPR)

10409 23:03:27.170405  <6>[    0.127768] CPU features: detected: LSE atomic instructions

10410 23:03:27.177665  <6>[    0.127769] CPU features: detected: Privileged Access Never

10411 23:03:27.183973  <6>[    0.127771] CPU features: detected: RAS Extension Support

10412 23:03:27.190396  <6>[    0.127774] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10413 23:03:27.194177  <6>[    0.127839] CPU: All CPU(s) started at EL2

10414 23:03:27.200328  <6>[    0.127841] alternatives: applying system-wide alternatives

10415 23:03:27.228432  ��ٳ�r�j��<6>[   < 0.348687] printk: console [ttyS0] printing thread started

10416 23:03:27.231847  6<6>[    0.348716] printk: console [ttyS0] enabled

10417 23:03:27.238790  >[    0.225338] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)

10418 23:03:27.247011  <6>[    0.348720] printk: bootconsole [mtk8250] disabled

10419 23:03:27.253271  <6>[    0.366106] printk: bootconsole [mtk8250] printing thread stopped

10420 23:03:27.256753  <6>[    0.367369] SuperH (H)SCI(F) driver initialized

10421 23:03:27.263338  <6>[    0.367850] msm_serial: driver initialized

10422 23:03:27.269890  <6>[    0.372445] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10423 23:03:27.279735  <6>[    0.372475] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10424 23:03:27.286142  <6>[    0.372504] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10425 23:03:27.306337  <6>[    0.372534] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10426 23:03:27.315318  <6>[    0.372555] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10427 23:03:27.315681  <6>[    0.372582] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10428 23:03:27.332564  <6>[    0.372610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10429 23:03:27.332688  <6>[    0.372720] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10430 23:03:27.342049  <6>[    0.372752] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10431 23:03:27.342141  <6>[    0.384326] loop: module loaded

10432 23:03:27.353390  <6>[    0.386940] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10433 23:03:27.356376  <4>[    0.403614] mtk-pmic-keys: Failed to locate of_node [id: -1]

10434 23:03:27.359660  <6>[    0.404526] megasas: 07.719.03.00-rc1

10435 23:03:27.366687  <6>[    0.416636] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10436 23:03:27.370063  <6>[    0.425517] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10437 23:03:27.376133  <6>[    0.428922] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10438 23:03:27.389544  <6>[    0.482045] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10439 23:03:27.855050  <6>[    0.975427] Freeing initrd memory: 17372K

10440 23:03:27.861566  <6>[    0.981327] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10441 23:03:27.864898  <6>[    0.986069] tun: Universal TUN/TAP device driver, 1.6

10442 23:03:27.868110  <6>[    0.986825] thunder_xcv, ver 1.0

10443 23:03:27.871434  <6>[    0.986844] thunder_bgx, ver 1.0

10444 23:03:27.874668  <6>[    0.986861] nicpf, ver 1.0

10445 23:03:27.881209  <6>[    0.987915] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10446 23:03:27.887706  <6>[    0.987918] hns3: Copyright (c) 2017 Huawei Corporation.

10447 23:03:27.891459  <6>[    0.987945] hclge is initializing

10448 23:03:27.897544  <6>[    0.987963] e1000: Intel(R) PRO/1000 Network Driver

10449 23:03:27.904624  <6>[    0.987965] e1000: Copyright (c) 1999-2006 Intel Corporation.

10450 23:03:27.908175  <6>[    0.987986] e1000e: Intel(R) PRO/1000 Network Driver

10451 23:03:27.915593  <6>[    0.987987] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10452 23:03:27.919146  <6>[    0.988003] igb: Intel(R) Gigabit Ethernet Network Driver

10453 23:03:27.925955  <6>[    0.988005] igb: Copyright (c) 2007-2014 Intel Corporation.

10454 23:03:27.932754  <6>[    0.988020] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10455 23:03:27.939654  <6>[    0.988022] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10456 23:03:27.943278  <6>[    0.988312] sky2: driver version 1.30

10457 23:03:27.946306  <6>[    0.989416] VFIO - User Level meta-driver version: 0.3

10458 23:03:27.952959  <6>[    0.992270] usbcore: registered new interface driver usb-storage

10459 23:03:27.959891  <6>[    0.992453] usbcore: registered new device driver onboard-usb-hub

10460 23:03:27.966825  <6>[    0.995278] mt6397-rtc mt6359-rtc: registered as rtc0

10461 23:03:27.973397  <6>[    0.995429] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:01:15 UTC (1701644475)

10462 23:03:27.979798  <6>[    0.996047] i2c_dev: i2c /dev entries driver

10463 23:03:27.986538  <6>[    1.003255] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10464 23:03:27.992934  <6>[    1.018241] cpu cpu0: EM: created perf domain

10465 23:03:27.996284  <6>[    1.018553] cpu cpu4: EM: created perf domain

10466 23:03:28.003026  <6>[    1.019736] sdhci: Secure Digital Host Controller Interface driver

10467 23:03:28.006985  <6>[    1.019738] sdhci: Copyright(c) Pierre Ossman

10468 23:03:28.013541  <6>[    1.020087] Synopsys Designware Multimedia Card Interface Driver

10469 23:03:28.020268  <6>[    1.020451] sdhci-pltfm: SDHCI platform and OF driver helper

10470 23:03:28.026369  <6>[    1.024725] ledtrig-cpu: registered to indicate activity on CPUs

10471 23:03:28.029909  <6>[    1.025496] mmc0: CQHCI version 5.10

10472 23:03:28.036912  <6>[    1.025619] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10473 23:03:28.043550  <6>[    1.025895] usbcore: registered new interface driver usbhid

10474 23:03:28.046499  <6>[    1.025897] usbhid: USB HID core driver

10475 23:03:28.052902  <6>[    1.026011] spi_master spi0: will run message pump with realtime priority

10476 23:03:28.066772  <6>[    1.057495] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10477 23:03:28.079706  <6>[    1.060486] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10478 23:03:28.086549  <6>[    1.061438] cros-ec-spi spi0.0: Chrome EC device registered

10479 23:03:28.093177  <6>[    1.073379] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10480 23:03:28.099669  <6>[    1.074340] NET: Registered PF_PACKET protocol family

10481 23:03:28.103306  <6>[    1.074408] 9pnet: Installing 9P2000 support

10482 23:03:28.109614  <5>[    1.074446] Key type dns_resolver registered

10483 23:03:28.113064  <6>[    1.074847] registered taskstats version 1

10484 23:03:28.119913  <5>[    1.074863] Loading compiled-in X.509 certificates

10485 23:03:28.130071  <4>[    1.089062] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10486 23:03:28.139933  <4>[    1.089216] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10487 23:03:28.146421  <3>[    1.089223] debugfs: File 'uA_load' in directory '/' already present!

10488 23:03:28.152839  <3>[    1.089229] debugfs: File 'min_uV' in directory '/' already present!

10489 23:03:28.159779  <3>[    1.089230] debugfs: File 'max_uV' in directory '/' already present!

10490 23:03:28.166572  <3>[    1.089232] debugfs: File 'constraint_flags' in directory '/' already present!

10491 23:03:28.176085  <3>[    1.091975] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10492 23:03:28.182981  <6>[    1.099946] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10493 23:03:28.186180  <6>[    1.100574] xhci-mtk 11200000.usb: xHCI Host Controller

10494 23:03:28.196090  <6>[    1.100592] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10495 23:03:28.202853  <6>[    1.100786] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10496 23:03:28.209288  <6>[    1.100824] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10497 23:03:28.215948  <6>[    1.100889] xhci-mtk 11200000.usb: xHCI Host Controller

10498 23:03:28.223298  <6>[    1.100892] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10499 23:03:28.229466  <6>[    1.100897] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10500 23:03:28.232775  <6>[    1.101219] hub 1-0:1.0: USB hub found

10501 23:03:28.239704  <6>[    1.101234] hub 1-0:1.0: 1 port detected

10502 23:03:28.246201  <6>[    1.101326] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10503 23:03:28.249308  <6>[    1.101547] hub 2-0:1.0: USB hub found

10504 23:03:28.256361  <6>[    1.101558] hub 2-0:1.0: 1 port detected

10505 23:03:28.259559  <6>[    1.104075] mtk-msdc 11f70000.mmc: Got CD GPIO

10506 23:03:28.265877  <6>[    1.111727] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10507 23:03:28.275969  <6>[    1.111736] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10508 23:03:28.282661  <4>[    1.111804] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10509 23:03:28.293069  <6>[    1.112295] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10510 23:03:28.300005  <6>[    1.112296] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10511 23:03:28.309476  <6>[    1.112430] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10512 23:03:28.316361  <6>[    1.112439] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10513 23:03:28.322585  <6>[    1.112441] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10514 23:03:28.332706  <6>[    1.112444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10515 23:03:28.342513  <6>[    1.113628] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10516 23:03:28.349486  <6>[    1.113644] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10517 23:03:28.359261  <6>[    1.113648] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10518 23:03:28.366023  <6>[    1.113652] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10519 23:03:28.375744  <6>[    1.113655] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10520 23:03:28.382396  <6>[    1.113658] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10521 23:03:28.392722  <6>[    1.113662] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10522 23:03:28.399226  <6>[    1.113666] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10523 23:03:28.409333  <6>[    1.113670] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10524 23:03:28.415415  <6>[    1.113673] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10525 23:03:28.425168  <6>[    1.113680] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10526 23:03:28.431811  <6>[    1.113684] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10527 23:03:28.441932  <6>[    1.113688] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10528 23:03:28.448474  <6>[    1.113691] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10529 23:03:28.458687  <6>[    1.113694] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10530 23:03:28.465307  <6>[    1.114002] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10531 23:03:28.471897  <6>[    1.114634] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10532 23:03:28.478347  <6>[    1.114840] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10533 23:03:28.485131  <6>[    1.115070] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10534 23:03:28.491595  <6>[    1.115309] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10535 23:03:28.501417  <6>[    1.115455] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10536 23:03:28.508416  <6>[    1.115464] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10537 23:03:28.518070  <6>[    1.115466] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10538 23:03:28.527807  <6>[    1.115469] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10539 23:03:28.538119  <6>[    1.115472] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10540 23:03:28.548245  <6>[    1.115475] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10541 23:03:28.554413  <6>[    1.115477] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10542 23:03:28.564455  <6>[    1.115480] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10543 23:03:28.574122  <6>[    1.115482] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10544 23:03:28.584283  <6>[    1.115486] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10545 23:03:28.593971  <6>[    1.115488] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10546 23:03:28.604137  <6>[    1.116076] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10547 23:03:28.607188  <6>[    1.119624] mmc0: Command Queue Engine enabled

10548 23:03:28.614310  <6>[    1.119634] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10549 23:03:28.620692  <6>[    1.120098] mmcblk0: mmc0:0001 DA4128 116 GiB 

10550 23:03:28.623949  <6>[    1.123541]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10551 23:03:28.630559  <6>[    1.124311] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10552 23:03:28.634329  <6>[    1.125040] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10553 23:03:28.640578  <6>[    1.125749] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10554 23:03:28.647189  <6>[    1.137793] Trying to probe devices needed for running init ...

10555 23:03:28.653539  <6>[    1.521312] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10556 23:03:28.660652  <6>[    1.673507] hub 1-1:1.0: USB hub found

10557 23:03:28.663320  <6>[    1.673883] hub 1-1:1.0: 4 ports detected

10558 23:03:28.666971  <6>[    1.676497] hub 1-1:1.0: USB hub found

10559 23:03:28.670524  <6>[    1.676782] hub 1-1:1.0: 4 ports detected

10560 23:03:28.686119  <6>[    1.801561] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10561 23:03:28.707055  <6>[    1.827999] hub 2-1:1.0: USB hub found

10562 23:03:28.710534  <6>[    1.828487] hub 2-1:1.0: 3 ports detected

10563 23:03:28.713545  <6>[    1.831364] hub 2-1:1.0: USB hub found

10564 23:03:28.716726  <6>[    1.831774] hub 2-1:1.0: 3 ports detected

10565 23:03:28.874030  <6>[    1.989513] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10566 23:03:28.994510  <6>[    2.116706] hub 1-1.4:1.0: USB hub found

10567 23:03:28.997945  <6>[    2.117060] hub 1-1.4:1.0: 2 ports detected

10568 23:03:29.001637  <6>[    2.120178] hub 1-1.4:1.0: USB hub found

10569 23:03:29.008054  <6>[    2.120469] hub 1-1.4:1.0: 2 ports detected

10570 23:03:29.082182  <6>[    2.197554] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10571 23:03:29.293567  <6>[    2.409480] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10572 23:03:29.477893  <6>[    2.593483] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10573 23:03:40.286055  <6>[   13.410489] ALSA device list:

10574 23:03:40.293005  <6>[   13.410512]   No soundcards found.

10575 23:03:40.296292  <6>[   13.414945] Freeing unused kernel memory: 8448K

10576 23:03:40.299541  <6>[   13.415115] Run /init as init process

10577 23:03:40.302423  Loading, please wait...

10578 23:03:40.324979  Starting version 247.3-7+deb11u2

10579 23:03:40.548731  <6>[   13.666165] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10580 23:03:40.585492  <6>[   13.693645] remoteproc remoteproc0: scp is available

10581 23:03:40.592068  <6>[   13.693836] remoteproc remoteproc0: powering up scp

10582 23:03:40.598586  <6>[   13.693850] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10583 23:03:40.605093  <6>[   13.693906] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10584 23:03:40.612161  <6>[   13.699711] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10585 23:03:40.621700  <6>[   13.699746] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10586 23:03:40.632056  <6>[   13.699753] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10587 23:03:40.638218  <3>[   13.702593] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10588 23:03:40.645432  <3>[   13.702613] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10589 23:03:40.654997  <3>[   13.702621] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10590 23:03:40.661745  <3>[   13.702769] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10591 23:03:40.671479  <3>[   13.702777] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10592 23:03:40.678431  <3>[   13.702784] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10593 23:03:40.688009  <3>[   13.702793] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10594 23:03:40.694967  <3>[   13.702799] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10595 23:03:40.702148  <3>[   13.702843] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10596 23:03:40.712239  <3>[   13.702906] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10597 23:03:40.718679  <3>[   13.702913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10598 23:03:40.728976  <3>[   13.702920] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10599 23:03:40.735337  <3>[   13.702974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10600 23:03:40.745507  <3>[   13.702981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10601 23:03:40.752425  <3>[   13.702989] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10602 23:03:40.759023  <3>[   13.702996] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10603 23:03:40.768605  <3>[   13.703004] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10604 23:03:40.785122  <3>[   13.703080] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10605 23:03:40.785214  <6>[   13.770445] mc: Linux media interface: v0.10

10606 23:03:40.788737  <4>[   13.771637] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10607 23:03:40.795428  <4>[   13.773538] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10608 23:03:40.801679  <6>[   13.778575] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10609 23:03:40.811965  <4>[   13.805390] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10610 23:03:40.815372  <4>[   13.805390] Fallback method does not support PEC.

10611 23:03:40.821734  <6>[   13.810267] usbcore: registered new interface driver r8152

10612 23:03:40.831505  <3>[   13.820942] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10613 23:03:40.838624  <6>[   13.822819] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10614 23:03:40.844767  <6>[   13.822841] pci_bus 0000:00: root bus resource [bus 00-ff]

10615 23:03:40.851473  <6>[   13.822850] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10616 23:03:40.861358  <6>[   13.822855] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10617 23:03:40.868338  <6>[   13.822917] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10618 23:03:40.874824  <6>[   13.822948] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10619 23:03:40.877835  <6>[   13.823051] pci 0000:00:00.0: supports D1 D2

10620 23:03:40.884690  <6>[   13.823055] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10621 23:03:40.894301  <6>[   13.824751] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10622 23:03:40.901206  <6>[   13.825048] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10623 23:03:40.907473  <6>[   13.825088] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10624 23:03:40.914435  <6>[   13.825111] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10625 23:03:40.921366  <6>[   13.825129] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10626 23:03:40.927644  <6>[   13.825139] videodev: Linux video capture interface: v2.00

10627 23:03:40.934214  <6>[   13.825296] pci 0000:01:00.0: supports D1 D2

10628 23:03:40.940995  <6>[   13.825299] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10629 23:03:40.947367  <6>[   13.838049] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10630 23:03:40.953947  <6>[   13.838058] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10631 23:03:40.960664  <6>[   13.838069] remoteproc remoteproc0: remote processor scp is now up

10632 23:03:40.967701  <6>[   13.841360] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10633 23:03:40.977384  <6>[   13.841433] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10634 23:03:40.983880  <6>[   13.841442] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10635 23:03:40.993927  <6>[   13.841457] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10636 23:03:41.000778  <6>[   13.841473] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10637 23:03:41.007245  <6>[   13.841490] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10638 23:03:41.014291  <6>[   13.841507] pci 0000:00:00.0: PCI bridge to [bus 01]

10639 23:03:41.020189  <6>[   13.841516] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10640 23:03:41.026995  <6>[   13.841864] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10641 23:03:41.033736  <6>[   13.843320] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10642 23:03:41.043539  <3>[   13.843879] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10643 23:03:41.050036  <6>[   13.844102] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10644 23:03:41.056706  <6>[   13.857791] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10645 23:03:41.067086  <6>[   13.859492] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10646 23:03:41.073581  <6>[   13.885502] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10647 23:03:41.083295  <6>[   13.889995] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10648 23:03:41.093656  <6>[   13.890312] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10649 23:03:41.100074  <6>[   13.905212] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10650 23:03:41.106633  <6>[   13.911393] usbcore: registered new interface driver cdc_ether

10651 23:03:41.113084  <5>[   13.915563] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10652 23:03:41.120152  <6>[   13.924838] Bluetooth: Core ver 2.22

10653 23:03:41.123044  <6>[   13.924987] NET: Registered PF_BLUETOOTH protocol family

10654 23:03:41.129627  <6>[   13.924989] Bluetooth: HCI device and connection manager initialized

10655 23:03:41.136430  <6>[   13.925028] Bluetooth: HCI socket layer initialized

10656 23:03:41.139897  <6>[   13.925037] Bluetooth: L2CAP socket layer initialized

10657 23:03:41.146288  <6>[   13.925049] Bluetooth: SCO socket layer initialized

10658 23:03:41.153016  <6>[   13.925048] usbcore: registered new interface driver r8153_ecm

10659 23:03:41.160006  <5>[   13.927471] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10660 23:03:41.169573  <4>[   13.927547] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10661 23:03:41.173127  <6>[   13.927555] cfg80211: failed to load regulatory.db

10662 23:03:41.182885  <4>[   13.929131] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10663 23:03:41.189880  <4>[   13.929139] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10664 23:03:41.196292  <6>[   13.968327] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10665 23:03:41.209412  <6>[   13.969769] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10666 23:03:41.216088  <6>[   13.970006] usbcore: registered new interface driver uvcvideo

10667 23:03:41.222930  <6>[   13.990646] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10668 23:03:41.229677  <6>[   13.996523] usbcore: registered new interface driver btusb

10669 23:03:41.239257  <4>[   13.997852] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10670 23:03:41.245717  <3>[   13.997875] Bluetooth: hci0: Failed to load firmware file (-2)

10671 23:03:41.249070  <3>[   13.997878] Bluetooth: hci0: Failed to set up firmware (-2)

10672 23:03:41.262941  <4>[   13.997882] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10673 23:03:41.266148  <6>[   14.005331] r8152 2-1.3:1.0 eth0: v1.12.13

10674 23:03:41.272896  <6>[   14.019642] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0

10675 23:03:41.279375  <6>[   14.035438] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10676 23:03:41.285995  <6>[   14.035535] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10677 23:03:41.288891  <6>[   14.053458] mt7921e 0000:01:00.0: ASIC revision: 79610010

10678 23:03:41.302457  <4>[   14.152600] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10679 23:03:41.312249  <4>[   14.259085] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10680 23:03:41.325511  <4>[   14.363242] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10681 23:03:41.328978  Begin: Loading essential drivers ... done.

10682 23:03:41.332354  Begin: Running /scripts/init-premount ... done.

10683 23:03:41.338727  Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.

10684 23:03:41.355619  Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for <4>[   14.472466] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10685 23:03:41.358884  any ethernet to become available

10686 23:03:41.365319  Device /sys/class/net/enx00e04c787aaa found

10687 23:03:41.365427  done.

10688 23:03:41.441401  IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10689 23:03:41.468055  <4>[   14.583890] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10690 23:03:41.575596  <4>[   14.690667] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10691 23:03:41.679858  <4>[   14.794495] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10692 23:03:41.784165  <4>[   14.898439] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10693 23:03:41.888100  <4>[   15.002424] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10694 23:03:41.991797  <4>[   15.106311] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10695 23:03:42.085242  <3>[   15.208143] mt7921e 0000:01:00.0: hardware init failed

10696 23:03:42.512856  <6>[   15.634209] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on

10697 23:03:43.371474  IP-Config: no response after 2 secs - giving up

10698 23:03:43.420846  IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP

10699 23:03:43.423826  IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):

10700 23:03:43.430260   address: 192.168.201.12   broadcast: 192.168.201.255  netmask: 255.255.255.0   

10701 23:03:43.437171   gateway: 192.168.201.1    dns0     : 192.168.201.1    dns1   : 0.0.0.0         

10702 23:03:43.443642   host   : mt8192-asurada-spherion-r0-cbg-0                                

10703 23:03:43.450658   domain : lava-rack                                                       

10704 23:03:43.453473   rootserver: 192.168.201.1 rootpath: 

10705 23:03:43.456942   filename  : 

10706 23:03:43.543248  done.

10707 23:03:43.546863  Begin: Running /scripts/nfs-bottom ... done.

10708 23:03:43.565321  Begin: Running /scripts/init-bottom ... done.

10709 23:03:44.717004  <6>[   17.838399] NET: Registered PF_INET6 protocol family

10710 23:03:44.720280  <6>[   17.840077] Segment Routing with IPv6

10711 23:03:44.726558  <6>[   17.840103] In-situ OAM (IOAM) with IPv6

10712 23:03:44.828690  <30>[   17.929356] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10713 23:03:44.832272  <30>[   17.929948] systemd[1]: Detected architecture arm64.

10714 23:03:44.832384  

10715 23:03:44.838502  Welcome to Debian GNU/Linux 11 (bullseye)!

10716 23:03:44.838599  

10717 23:03:44.860924  <30>[   17.983377] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10718 23:03:45.580158  <30>[   18.699174] systemd[1]: Queued start job for default target Graphical Interface.

10719 23:03:45.610948  [  OK  [<30>[   18.731889] systemd[1]: Created slice system-getty.slice.

10720 23:03:45.614365  0m] Created slice system-getty.slice.

10721 23:03:45.633563  [  OK  ] Created slic<30>[   18.754842] systemd[1]: Created slice system-modprobe.slice.

10722 23:03:45.636846  e system-modprobe.slice.

10723 23:03:45.657583  [  OK  ] Created slic<30>[   18.778691] systemd[1]: Created slice system-serial\x2dgetty.slice.

10724 23:03:45.663937  e system-serial\x2dgetty.slice.

10725 23:03:45.682240  [  OK  ] Created slic<30>[   18.803241] systemd[1]: Created slice User and Session Slice.

10726 23:03:45.685860  e User and Session Slice.

10727 23:03:45.708845  [  OK  ] Started [0;<30>[   18.826319] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10728 23:03:45.712205  1;39mDispatch Password …ts to Console Directory Watch.

10729 23:03:45.736596  [  OK  ] Started Forward Pas<30>[   18.854270] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10730 23:03:45.740204  sword R…uests to Wall Directory Watch.

10731 23:03:45.767784  [  OK  ] Reached targ<30>[   18.882045] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10732 23:03:45.774684  et Loca<30>[   18.882297] systemd[1]: Reached target Local Encrypted Volumes.

10733 23:03:45.777851  l Encrypted Volumes.

10734 23:03:45.796882  [  OK  ] Reached target Path<30>[   18.918027] systemd[1]: Reached target Paths.

10735 23:03:45.796968  s.

10736 23:03:45.819454  [  OK  ] Reached target Remo<30>[   18.937467] systemd[1]: Reached target Remote File Systems.

10737 23:03:45.819539  te File Systems.

10738 23:03:45.840827  [  OK  ] Reached target Slic<30>[   18.961786] systemd[1]: Reached target Slices.

10739 23:03:45.840950  es.

10740 23:03:45.860406  [  OK  ] Reached target Swap<30>[   18.981499] systemd[1]: Reached target Swap.

10741 23:03:45.860487  .

10742 23:03:45.884209  [  OK  ] Listening on initct<30>[   19.001965] systemd[1]: Listening on initctl Compatibility Named Pipe.

10743 23:03:45.887629  l Compatibility Named Pipe.

10744 23:03:45.897514  [  OK  ] Listening on Journa<30>[   19.018002] systemd[1]: Listening on Journal Audit Socket.

10745 23:03:45.900462  l Audit Socket.

10746 23:03:45.921948  [  OK  ] Listening on<30>[   19.042720] systemd[1]: Listening on Journal Socket (/dev/log).

10747 23:03:45.925297   Journal Socket (/dev/log).

10748 23:03:45.945705  [  OK  ] Listening on<30>[   19.066767] systemd[1]: Listening on Journal Socket.

10749 23:03:45.949200   Journal Socket.

10750 23:03:45.965790  [  OK  ] Listening on<30>[   19.087076] systemd[1]: Listening on Network Service Netlink Socket.

10751 23:03:45.972158   Network Service Netlink Socket.

10752 23:03:45.992119  [  OK  [<30>[   19.112846] systemd[1]: Listening on udev Control Socket.

10753 23:03:45.995232  0m] Listening on udev Control Socket.

10754 23:03:46.013756  [  OK  ] Listening on<30>[   19.134599] systemd[1]: Listening on udev Kernel Socket.

10755 23:03:46.017291   udev Kernel Socket.

10756 23:03:46.076077           Mounting Huge Pages File Syste<30>[   19.193906] systemd[1]: Mounting Huge Pages File System...

10757 23:03:46.076187  m...

10758 23:03:46.094835           Mounting POSIX<30>[   19.215652] systemd[1]: Mounting POSIX Message Queue File System...

10759 23:03:46.097651   Message Queue File System...

10760 23:03:46.119947           Mountin<30>[   19.240660] systemd[1]: Mounting Kernel Debug File System...

10761 23:03:46.123393  g Kernel Debug File System...

10762 23:03:46.144399  <30>[   19.261848] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10763 23:03:46.154089  <30>[   19.270186] systemd[1]: Starting Create list of static device nodes for the current kernel...

10764 23:03:46.160314           Starting Create list of st…odes for the current kernel...

10765 23:03:46.187579           Startin<30>[   19.308385] systemd[1]: Starting Load Kernel Module configfs...

10766 23:03:46.190413  g Load Kernel Module configfs...

10767 23:03:46.217133           Starting Load <30>[   19.338260] systemd[1]: Starting Load Kernel Module drm...

10768 23:03:46.220711  Kernel Module drm...

10769 23:03:46.248099           Starting Load Kernel Module fu<30>[   19.366087] systemd[1]: Starting Load Kernel Module fuse...

10770 23:03:46.248184  se...

10771 23:03:46.288178  <30>[   19.408868] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10772 23:03:46.296263  <6>[   19.420025] fuse: init (API version 7.37)

10773 23:03:46.336918           Starting Journal Service..<30>[   19.458134] systemd[1]: Starting Journal Service...

10774 23:03:46.337041  .

10775 23:03:46.363120           Startin<30>[   19.484279] systemd[1]: Starting Load Kernel Modules...

10776 23:03:46.366786  g Load Kernel Modules...

10777 23:03:46.391588           Startin<30>[   19.512541] systemd[1]: Starting Remount Root and Kernel File Systems...

10778 23:03:46.397826  g Remount Root and Kernel File Systems...

10779 23:03:46.457528           Starting Coldp<30>[   19.578447] systemd[1]: Starting Coldplug All udev Devices...

10780 23:03:46.460612  lug All udev Devices...

10781 23:03:46.484477  [  OK  ] Mounted Huge Pages <30>[   19.605469] systemd[1]: Mounted Huge Pages File System.

10782 23:03:46.488090  File System.

10783 23:03:46.508194  [  OK  ] Mounted POSIX Messa<30>[   19.626211] systemd[1]: Mounted POSIX Message Queue File System.

10784 23:03:46.508310  ge Queue File System.

10785 23:03:46.523996  <3>[   19.644970] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10786 23:03:46.537315  [  OK  ] Mounted [0;<30>[   19.658322] systemd[1]: Mounted Kernel Debug File System.

10787 23:03:46.540670  1;39mKernel Debug File System.

10788 23:03:46.565612  [  OK  ] Finished [0<30>[   19.682914] systemd[1]: Finished Create list of static device nodes for the current kernel.

10789 23:03:46.575499  ;1;39mCreate lis<3>[   19.684747] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10790 23:03:46.578421  t of st… nodes for the current kernel.

10791 23:03:46.596326  <30>[   19.720288] systemd[1]: modprobe@configfs.service: Succeeded.

10792 23:03:46.603459  <30>[   19.723075] systemd[1]: Finished Load Kernel Module configfs.

10793 23:03:46.617181  [  OK  ] Finished Load Kerne<3>[   19.726039] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10794 23:03:46.627109  l Module configf<3>[   19.745669] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10795 23:03:46.627192  s.

10796 23:03:46.646440  [  OK  ] Finished [0<30>[   19.766200] systemd[1]: modprobe@drm.service: Succeeded.

10797 23:03:46.652965  ;1;39mLoad Kerne<30>[   19.766886] systemd[1]: Finished Load Kernel Module drm.

10798 23:03:46.662802  l Module drm<3>[   19.775383] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10799 23:03:46.662887  .

10800 23:03:46.681946  [  OK  ] Finished [0<30>[   19.802221] systemd[1]: modprobe@fuse.service: Succeeded.

10801 23:03:46.688544  ;1;39mLoad Kerne<30>[   19.802941] systemd[1]: Finished Load Kernel Module fuse.

10802 23:03:46.698688  l Module fuse[0<3>[   19.807485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10803 23:03:46.698771  m.

10804 23:03:46.721281  [  OK  ] Finished [0<3>[   19.837839] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10805 23:03:46.728120  ;1;39mLoad Kerne<30>[   19.838769] systemd[1]: Finished Load Kernel Modules.

10806 23:03:46.728201  l Modules.

10807 23:03:46.739884  <3>[   19.857745] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10808 23:03:46.751105  [  OK  ] Finished [0<30>[   19.871568] systemd[1]: Finished Remount Root and Kernel File Systems.

10809 23:03:46.761318  ;1;39mRemount Ro<3>[   19.879318] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10810 23:03:46.764370  ot and Kernel File Systems.

10811 23:03:46.791989  <3>[   19.909536] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10812 23:03:46.833875  [  OK  ] Started [0;<30>[   19.954880] systemd[1]: Started Journal Service.

10813 23:03:46.836835  1;39mJournal Service.

10814 23:03:46.861800           Mounting FUSE Control File System...

10815 23:03:46.884967           Mounting Kernel Configuration File System...

10816 23:03:46.910579           Starting Flush Journal to Persistent Storage...

10817 23:03:46.937853           Starting Load/Save Random Seed...

10818 23:03:46.955810  <46>[   20.075636] systemd-journald[307]: Received client request to flush runtime journal.

10819 23:03:46.968125           Starting Apply Kernel Variables...

10820 23:03:46.994206           Starting Create System Users...

10821 23:03:47.015899  [  OK  ] Mounted FUSE Control File System.

10822 23:03:47.038675  <4>[   20.151105] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent

10823 23:03:47.048593  <3>[   20.151129] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5

10824 23:03:47.054857  [  OK  ] Mounted Kernel Configuration File System.

10825 23:03:47.075825  [FAILED] Failed to start Coldplug All udev Devices.

10826 23:03:47.089000  See 'systemctl status systemd-udev-trigger.service' for details.

10827 23:03:47.107110  [  OK  ] Finished Load/Save Random Seed.

10828 23:03:47.126728  [  OK  ] Finished Apply Kernel Variables.

10829 23:03:48.380390  [  OK  ] Finished Flush Journal to Persistent Storage.

10830 23:03:48.606238  [  OK  ] Finished Create System Users.

10831 23:03:48.658717           Starting Create Static Device Nodes in /dev...

10832 23:03:48.761017  [  OK  ] Finished Create Static Device Nodes in /dev.

10833 23:03:48.777155  [  OK  ] Reached target Local File Systems (Pre).

10834 23:03:48.792545  [  OK  ] Reached target Local File Systems.

10835 23:03:48.833251           Starting Create Volatile Files and Directories...

10836 23:03:48.864041           Starting Rule-based Manage…for Device Events and Files...

10837 23:03:48.985532  [  OK  ] Started Rule-based Manager for Device Events and Files.

10838 23:03:49.038453           Starting Network Service...

10839 23:03:49.064696  [  OK  ] Finished Create Volatile Files and Directories.

10840 23:03:49.083229           Starting Network Time Synchronization...

10841 23:03:49.104174           Starting Update UTMP about System Boot/Shutdown...

10842 23:03:49.169371  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10843 23:03:49.358441  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10844 23:03:49.414291           Starting Load/Save Screen …of leds:white:kbd_backlight...

10845 23:03:49.438324  [  OK  ] Found device /dev/ttyS0.

10846 23:03:49.639149  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10847 23:03:49.684127  [  OK  ] Reached target Bluetooth.

10848 23:03:49.742130           Starting Load/Save RF Kill Switch Status...

10849 23:03:49.776939  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10850 23:03:49.793505  [  OK  ] Started Load/Save RF Kill Switch Status.

10851 23:03:49.809085  [  OK  ] Started Network Service.

10852 23:03:49.825362  [  OK  ] Started Network Time Synchronization.

10853 23:03:49.841774  [  OK  ] Reached target System Initialization.

10854 23:03:49.859613  [  OK  ] Started Daily Cleanup of Temporary Directories.

10855 23:03:49.872736  [  OK  ] Reached target System Time Set.

10856 23:03:49.888875  [  OK  ] Reached target System Time Synchronized.

10857 23:03:50.609956  [  OK  ] Started Daily apt download activities.

10858 23:03:50.941019  [  OK  ] Started Daily apt upgrade and clean activities.

10859 23:03:50.961473  [  OK  ] Started Periodic ext4 Onli…ata Check for All Filesystems.

10860 23:03:50.982901  [  OK  ] Started Discard unused blocks once a week.

10861 23:03:50.996303  [  OK  ] Reached target Timers.

10862 23:03:51.017942  [  OK  ] Listening on D-Bus System Message Bus Socket.

10863 23:03:51.028406  [  OK  ] Reached target Sockets.

10864 23:03:51.044313  [  OK  ] Reached target Basic System.

10865 23:03:51.101205  [  OK  ] Started D-Bus System Message Bus.

10866 23:03:51.150976           Starting Remove Stale Onli…t4 Metadata Check Snapshots...

10867 23:03:51.189871           Starting User Login Management...

10868 23:03:51.317084           Starting Network Name Resolution...

10869 23:03:51.496164  [  OK  ] Finished Remove Stale Onli…ext4 Metadata Check Snapshots.

10870 23:03:51.512726  [  OK  ] Started User Login Management.

10871 23:03:52.019041  [  OK  ] Started Network Name Resolution.

10872 23:03:52.038410  [  OK  ] Reached target Network.

10873 23:03:52.056551  [  OK  ] Reached target Host and Network Name Lookups.

10874 23:03:52.098416           Starting Permit User Sessions...

10875 23:03:52.130069  [  OK  ] Finished Permit User Sessions.

10876 23:03:52.146113  [  OK  ] Started Getty on tty1.

10877 23:03:52.182599  [  OK  ] Started Serial Getty on ttyS0.

10878 23:03:52.203183  [  OK  ] Reached target Login Prompts.

10879 23:03:52.218127  [  OK  ] Reached target Multi-User System.

10880 23:03:52.238368  [  OK  ] Reached target Graphical Interface.

10881 23:03:52.286297           Starting Update UTMP about System Runlevel Changes...

10882 23:03:52.331726  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10883 23:03:52.393422  

10884 23:03:52.393529  

10885 23:03:52.396714  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10886 23:03:52.396795  

10887 23:03:52.400211  debian-bullseye-arm64 login: root (automatic login)

10888 23:03:52.400293  

10889 23:03:52.400364  

10890 23:03:52.667512  Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec  3 22:38:18 UTC 2023 aarch64

10891 23:03:52.667645  

10892 23:03:52.673899  The programs included with the Debian GNU/Linux system are free software;

10893 23:03:52.680779  the exact distribution terms for each program are described in the

10894 23:03:52.684200  individual files in /usr/share/doc/*/copyright.

10895 23:03:52.684281  

10896 23:03:52.690531  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10897 23:03:52.693838  permitted by applicable law.

10898 23:03:52.752060  Matched prompt #10: / #
10900 23:03:52.752403  Setting prompt string to ['/ #']
10901 23:03:52.752526  end: 2.2.5.1 login-action (duration 00:00:27) [common]
10903 23:03:52.752821  end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10904 23:03:52.752939  start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
10905 23:03:52.753035  Setting prompt string to ['/ #']
10906 23:03:52.753121  Forcing a shell prompt, looking for ['/ #']
10908 23:03:52.803360  / # 

10909 23:03:52.803492  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10910 23:03:52.803594  Waiting using forced prompt support (timeout 00:02:30)
10911 23:03:52.808584  

10912 23:03:52.808870  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10913 23:03:52.808959  start: 2.2.7 export-device-env (timeout 00:03:37) [common]
10915 23:03:52.909242  / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3'

10916 23:03:52.914855  export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172473/extract-nfsrootfs-er14e8z3'

10918 23:03:53.015312  / # export NFS_SERVER_IP='192.168.201.1'

10919 23:03:53.020901  export NFS_SERVER_IP='192.168.201.1'

10920 23:03:53.021208  end: 2.2.7 export-device-env (duration 00:00:00) [common]
10921 23:03:53.021330  end: 2.2 depthcharge-retry (duration 00:01:23) [common]
10922 23:03:53.021445  end: 2 depthcharge-action (duration 00:01:23) [common]
10923 23:03:53.021563  start: 3 lava-test-retry (timeout 00:01:00) [common]
10924 23:03:53.021725  start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10925 23:03:53.021828  Using namespace: common
10927 23:03:53.122152  / # #

10928 23:03:53.122276  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10929 23:03:53.127836  #

10930 23:03:53.128124  Using /lava-12172473
10932 23:03:53.228446  / # export SHELL=/bin/sh

10933 23:03:53.233783  export SHELL=/bin/sh

10935 23:03:53.334254  / # . /lava-12172473/environment

10936 23:03:53.339655  . /lava-12172473/environment

10938 23:03:53.445590  / # /lava-12172473/bin/lava-test-runner /lava-12172473/0

10939 23:03:53.445718  Test shell timeout: 10s (minimum of the action and connection timeout)
10940 23:03:53.451048  /lava-12172473/bin/lava-test-runner /lava-12172473/0

10941 23:03:53.649842  + export TESTRUN_ID=0_dmesg

10942 23:03:53.652813  + cd /lava-12172473/0/tests/0_dmesg

10943 23:03:53.656228  + cat uuid

10944 23:03:53.666988  + UUID=12172473_<8>[   26.788757] <LAVA_SIGNAL_STARTRUN 0_dmesg 12172473_1.6.2.3.1>

10945 23:03:53.667092  1.6.2.3.1

10946 23:03:53.667178  + set +x

10947 23:03:53.667423  Received signal: <STARTRUN> 0_dmesg 12172473_1.6.2.3.1
10948 23:03:53.667523  Starting test lava.0_dmesg (12172473_1.6.2.3.1)
10949 23:03:53.667640  Skipping test definition patterns.
10950 23:03:53.673475  + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh

10951 23:03:53.747319  <8>[   26.865464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>

10952 23:03:53.747612  Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10954 23:03:53.799808  <8>[   26.920120] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>

10955 23:03:53.800081  Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10957 23:03:53.851183  + set +x

10958 23:03:53.860832  <LAVA_TEST_RUNNE<8>[   26.978856] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>

10959 23:03:53.860921  R EXIT>

10960 23:03:53.861157  Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10962 23:03:53.867776  <8>[   26.979834] <LAVA_SIGNAL_ENDRUN 0_dmesg 12172473_1.6.2.3.1>

10963 23:03:53.868027  Received signal: <ENDRUN> 0_dmesg 12172473_1.6.2.3.1
10964 23:03:53.868110  Ending use of test pattern.
10965 23:03:53.868170  Ending test lava.0_dmesg (12172473_1.6.2.3.1), duration 0.20
10967 23:04:10.907418  / # <6>[   44.033628] vpu: disabling

10968 23:04:10.910317  <6>[   44.033771] vproc2: disabling

10969 23:04:10.913829  <6>[   44.033827] vproc1: disabling

10970 23:04:10.917394  <6>[   44.033882] vaud18: disabling

10971 23:04:10.923776  <6>[   44.034136] vsram_others: disabling

10972 23:04:10.927174  <6>[   44.034316] va09: disabling

10973 23:04:10.930726  <6>[   44.034395] vsram_md: disabling

10974 23:04:10.930810  <6>[   44.034532] Vgpu: disabling

10976 23:04:53.021945  end: 3.1 lava-test-shell (duration 00:01:00) [common]
10978 23:04:53.022136  lava-test-retry failed: 1 of 5 attempts. 'lava-test-shell timed out after 60 seconds'
10980 23:04:53.022284  end: 3 lava-test-retry (duration 00:01:00) [common]
10982 23:04:53.022507  Cleaning after the job
10983 23:04:53.022593  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/ramdisk
10984 23:04:53.025179  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/kernel
10985 23:04:53.038671  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/dtb
10986 23:04:53.038966  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/nfsrootfs
10987 23:04:53.117962  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172473/tftp-deploy-msudd3vb/modules
10988 23:04:53.125652  start: 5.1 power-off (timeout 00:00:30) [common]
10989 23:04:53.125869  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
10990 23:04:53.211527  >> Command sent successfully.

10991 23:04:53.214066  Returned 0 in 0 seconds
10992 23:04:53.314500  end: 5.1 power-off (duration 00:00:00) [common]
10994 23:04:53.314843  start: 5.2 read-feedback (timeout 00:10:00) [common]
10995 23:04:53.315127  Listened to connection for namespace 'common' for up to 1s
10996 23:04:54.316109  Finalising connection for namespace 'common'
10997 23:04:54.316268  Disconnecting from shell: Finalise
10998 23:04:54.416825  end: 5.2 read-feedback (duration 00:00:01) [common]
10999 23:04:54.417381  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172473
11000 23:04:54.819679  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172473
11001 23:04:54.819865  TestError: A test failed to run, look at the error message.