Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 17
- Kernel Errors: 33
- Errors: 1
1 23:15:43.357740 lava-dispatcher, installed at version: 2023.10
2 23:15:43.357995 start: 0 validate
3 23:15:43.358129 Start time: 2023-12-03 23:15:43.358121+00:00 (UTC)
4 23:15:43.358256 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:15:43.358413 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
6 23:15:43.620848 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:15:43.621017 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:15:43.888067 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:15:43.888789 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:15:44.149747 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:15:44.150473 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 23:15:44.417649 validate duration: 1.06
14 23:15:44.418972 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 23:15:44.419524 start: 1.1 download-retry (timeout 00:10:00) [common]
16 23:15:44.419967 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 23:15:44.420558 Not decompressing ramdisk as can be used compressed.
18 23:15:44.421012 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/arm64/rootfs.cpio.gz
19 23:15:44.421347 saving as /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/ramdisk/rootfs.cpio.gz
20 23:15:44.421710 total size: 34390042 (32 MB)
21 23:15:44.426449 progress 0 % (0 MB)
22 23:15:44.466601 progress 5 % (1 MB)
23 23:15:44.482341 progress 10 % (3 MB)
24 23:15:44.493680 progress 15 % (4 MB)
25 23:15:44.502960 progress 20 % (6 MB)
26 23:15:44.512109 progress 25 % (8 MB)
27 23:15:44.521149 progress 30 % (9 MB)
28 23:15:44.530279 progress 35 % (11 MB)
29 23:15:44.539189 progress 40 % (13 MB)
30 23:15:44.548294 progress 45 % (14 MB)
31 23:15:44.557196 progress 50 % (16 MB)
32 23:15:44.566365 progress 55 % (18 MB)
33 23:15:44.575281 progress 60 % (19 MB)
34 23:15:44.584342 progress 65 % (21 MB)
35 23:15:44.593242 progress 70 % (22 MB)
36 23:15:44.602353 progress 75 % (24 MB)
37 23:15:44.611299 progress 80 % (26 MB)
38 23:15:44.620413 progress 85 % (27 MB)
39 23:15:44.629261 progress 90 % (29 MB)
40 23:15:44.638280 progress 95 % (31 MB)
41 23:15:44.647091 progress 100 % (32 MB)
42 23:15:44.647297 32 MB downloaded in 0.23 s (145.37 MB/s)
43 23:15:44.647461 end: 1.1.1 http-download (duration 00:00:00) [common]
45 23:15:44.647711 end: 1.1 download-retry (duration 00:00:00) [common]
46 23:15:44.647797 start: 1.2 download-retry (timeout 00:10:00) [common]
47 23:15:44.647880 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 23:15:44.648019 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 23:15:44.648093 saving as /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/kernel/Image
50 23:15:44.648154 total size: 49172992 (46 MB)
51 23:15:44.648215 No compression specified
52 23:15:44.649352 progress 0 % (0 MB)
53 23:15:44.662521 progress 5 % (2 MB)
54 23:15:44.675342 progress 10 % (4 MB)
55 23:15:44.688166 progress 15 % (7 MB)
56 23:15:44.701078 progress 20 % (9 MB)
57 23:15:44.714119 progress 25 % (11 MB)
58 23:15:44.726984 progress 30 % (14 MB)
59 23:15:44.739889 progress 35 % (16 MB)
60 23:15:44.753020 progress 40 % (18 MB)
61 23:15:44.766095 progress 45 % (21 MB)
62 23:15:44.779070 progress 50 % (23 MB)
63 23:15:44.791866 progress 55 % (25 MB)
64 23:15:44.805032 progress 60 % (28 MB)
65 23:15:44.817993 progress 65 % (30 MB)
66 23:15:44.830876 progress 70 % (32 MB)
67 23:15:44.843733 progress 75 % (35 MB)
68 23:15:44.856701 progress 80 % (37 MB)
69 23:15:44.869828 progress 85 % (39 MB)
70 23:15:44.882822 progress 90 % (42 MB)
71 23:15:44.895685 progress 95 % (44 MB)
72 23:15:44.908344 progress 100 % (46 MB)
73 23:15:44.908626 46 MB downloaded in 0.26 s (180.04 MB/s)
74 23:15:44.908783 end: 1.2.1 http-download (duration 00:00:00) [common]
76 23:15:44.909014 end: 1.2 download-retry (duration 00:00:00) [common]
77 23:15:44.909106 start: 1.3 download-retry (timeout 00:10:00) [common]
78 23:15:44.909192 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 23:15:44.909331 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 23:15:44.909402 saving as /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/dtb/mt8192-asurada-spherion-r0.dtb
81 23:15:44.909463 total size: 47278 (0 MB)
82 23:15:44.909524 No compression specified
83 23:15:44.910794 progress 69 % (0 MB)
84 23:15:44.911072 progress 100 % (0 MB)
85 23:15:44.911230 0 MB downloaded in 0.00 s (25.56 MB/s)
86 23:15:44.911355 end: 1.3.1 http-download (duration 00:00:00) [common]
88 23:15:44.911576 end: 1.3 download-retry (duration 00:00:00) [common]
89 23:15:44.911659 start: 1.4 download-retry (timeout 00:10:00) [common]
90 23:15:44.911740 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 23:15:44.911858 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 23:15:44.911925 saving as /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/modules/modules.tar
93 23:15:44.911985 total size: 8614132 (8 MB)
94 23:15:44.912045 Using unxz to decompress xz
95 23:15:44.916316 progress 0 % (0 MB)
96 23:15:44.937328 progress 5 % (0 MB)
97 23:15:44.961237 progress 10 % (0 MB)
98 23:15:44.985442 progress 15 % (1 MB)
99 23:15:45.009570 progress 20 % (1 MB)
100 23:15:45.034145 progress 25 % (2 MB)
101 23:15:45.060005 progress 30 % (2 MB)
102 23:15:45.086542 progress 35 % (2 MB)
103 23:15:45.110183 progress 40 % (3 MB)
104 23:15:45.135056 progress 45 % (3 MB)
105 23:15:45.160939 progress 50 % (4 MB)
106 23:15:45.185407 progress 55 % (4 MB)
107 23:15:45.210943 progress 60 % (4 MB)
108 23:15:45.236801 progress 65 % (5 MB)
109 23:15:45.264299 progress 70 % (5 MB)
110 23:15:45.288149 progress 75 % (6 MB)
111 23:15:45.315747 progress 80 % (6 MB)
112 23:15:45.341635 progress 85 % (7 MB)
113 23:15:45.367206 progress 90 % (7 MB)
114 23:15:45.397424 progress 95 % (7 MB)
115 23:15:45.426331 progress 100 % (8 MB)
116 23:15:45.432887 8 MB downloaded in 0.52 s (15.77 MB/s)
117 23:15:45.433158 end: 1.4.1 http-download (duration 00:00:01) [common]
119 23:15:45.433418 end: 1.4 download-retry (duration 00:00:01) [common]
120 23:15:45.433511 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 23:15:45.433643 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 23:15:45.433728 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 23:15:45.433814 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 23:15:45.434036 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd
125 23:15:45.434172 makedir: /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin
126 23:15:45.434281 makedir: /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/tests
127 23:15:45.434389 makedir: /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/results
128 23:15:45.434507 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-add-keys
129 23:15:45.434663 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-add-sources
130 23:15:45.434798 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-background-process-start
131 23:15:45.434967 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-background-process-stop
132 23:15:45.435128 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-common-functions
133 23:15:45.435297 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-echo-ipv4
134 23:15:45.435588 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-install-packages
135 23:15:45.435744 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-installed-packages
136 23:15:45.435874 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-os-build
137 23:15:45.436018 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-probe-channel
138 23:15:45.436192 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-probe-ip
139 23:15:45.436350 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-target-ip
140 23:15:45.436492 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-target-mac
141 23:15:45.436617 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-target-storage
142 23:15:45.436748 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-case
143 23:15:45.436875 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-event
144 23:15:45.436999 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-feedback
145 23:15:45.437124 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-raise
146 23:15:45.437251 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-reference
147 23:15:45.437376 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-runner
148 23:15:45.437501 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-set
149 23:15:45.437693 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-test-shell
150 23:15:45.437899 Updating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-install-packages (oe)
151 23:15:45.438162 Updating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/bin/lava-installed-packages (oe)
152 23:15:45.438382 Creating /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/environment
153 23:15:45.438517 LAVA metadata
154 23:15:45.438626 - LAVA_JOB_ID=12172418
155 23:15:45.438727 - LAVA_DISPATCHER_IP=192.168.201.1
156 23:15:45.438954 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 23:15:45.439095 skipped lava-vland-overlay
158 23:15:45.439249 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 23:15:45.439362 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 23:15:45.439467 skipped lava-multinode-overlay
161 23:15:45.439560 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 23:15:45.439645 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 23:15:45.439726 Loading test definitions
164 23:15:45.439854 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 23:15:45.439964 Using /lava-12172418 at stage 0
166 23:15:45.440305 uuid=12172418_1.5.2.3.1 testdef=None
167 23:15:45.440395 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 23:15:45.440486 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 23:15:45.441073 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 23:15:45.441295 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 23:15:45.441999 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 23:15:45.442411 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 23:15:45.443025 runner path: /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/0/tests/0_cros-ec test_uuid 12172418_1.5.2.3.1
176 23:15:45.443184 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 23:15:45.443642 Creating lava-test-runner.conf files
179 23:15:45.443740 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172418/lava-overlay-259d1qzd/lava-12172418/0 for stage 0
180 23:15:45.443832 - 0_cros-ec
181 23:15:45.443946 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 23:15:45.444047 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 23:15:45.450945 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 23:15:45.451064 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 23:15:45.451169 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 23:15:45.451272 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 23:15:45.451420 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 23:15:46.454193 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 23:15:46.454582 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 23:15:46.454702 extracting modules file /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172418/extract-overlay-ramdisk-xlrk91qz/ramdisk
191 23:15:46.695571 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 23:15:46.695745 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 23:15:46.695849 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172418/compress-overlay-y6vyj5u1/overlay-1.5.2.4.tar.gz to ramdisk
194 23:15:46.695925 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172418/compress-overlay-y6vyj5u1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172418/extract-overlay-ramdisk-xlrk91qz/ramdisk
195 23:15:46.703244 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 23:15:46.703375 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 23:15:46.703471 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 23:15:46.703563 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 23:15:46.703645 Building ramdisk /var/lib/lava/dispatcher/tmp/12172418/extract-overlay-ramdisk-xlrk91qz/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172418/extract-overlay-ramdisk-xlrk91qz/ramdisk
200 23:15:47.498103 >> 271085 blocks
201 23:15:52.225386 rename /var/lib/lava/dispatcher/tmp/12172418/extract-overlay-ramdisk-xlrk91qz/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/ramdisk/ramdisk.cpio.gz
202 23:15:52.225836 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 23:15:52.225959 start: 1.5.8 prepare-kernel (timeout 00:09:52) [common]
204 23:15:52.226066 start: 1.5.8.1 prepare-fit (timeout 00:09:52) [common]
205 23:15:52.226172 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/kernel/Image'
206 23:16:04.384942 Returned 0 in 12 seconds
207 23:16:04.485553 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/kernel/image.itb
208 23:16:05.212945 output: FIT description: Kernel Image image with one or more FDT blobs
209 23:16:05.213323 output: Created: Sun Dec 3 23:16:05 2023
210 23:16:05.213401 output: Image 0 (kernel-1)
211 23:16:05.213469 output: Description:
212 23:16:05.213535 output: Created: Sun Dec 3 23:16:05 2023
213 23:16:05.213609 output: Type: Kernel Image
214 23:16:05.213708 output: Compression: lzma compressed
215 23:16:05.213768 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
216 23:16:05.213828 output: Architecture: AArch64
217 23:16:05.213882 output: OS: Linux
218 23:16:05.213935 output: Load Address: 0x00000000
219 23:16:05.213990 output: Entry Point: 0x00000000
220 23:16:05.214045 output: Hash algo: crc32
221 23:16:05.214102 output: Hash value: c85ea8f0
222 23:16:05.214159 output: Image 1 (fdt-1)
223 23:16:05.214211 output: Description: mt8192-asurada-spherion-r0
224 23:16:05.214264 output: Created: Sun Dec 3 23:16:05 2023
225 23:16:05.214317 output: Type: Flat Device Tree
226 23:16:05.214369 output: Compression: uncompressed
227 23:16:05.214421 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
228 23:16:05.214473 output: Architecture: AArch64
229 23:16:05.214525 output: Hash algo: crc32
230 23:16:05.214576 output: Hash value: cc4352de
231 23:16:05.214628 output: Image 2 (ramdisk-1)
232 23:16:05.214680 output: Description: unavailable
233 23:16:05.214732 output: Created: Sun Dec 3 23:16:05 2023
234 23:16:05.214785 output: Type: RAMDisk Image
235 23:16:05.214837 output: Compression: Unknown Compression
236 23:16:05.214889 output: Data Size: 47542540 Bytes = 46428.26 KiB = 45.34 MiB
237 23:16:05.214940 output: Architecture: AArch64
238 23:16:05.214992 output: OS: Linux
239 23:16:05.215043 output: Load Address: unavailable
240 23:16:05.215095 output: Entry Point: unavailable
241 23:16:05.215146 output: Hash algo: crc32
242 23:16:05.215197 output: Hash value: 6b8c5a8f
243 23:16:05.215249 output: Default Configuration: 'conf-1'
244 23:16:05.215300 output: Configuration 0 (conf-1)
245 23:16:05.215351 output: Description: mt8192-asurada-spherion-r0
246 23:16:05.215403 output: Kernel: kernel-1
247 23:16:05.215455 output: Init Ramdisk: ramdisk-1
248 23:16:05.215506 output: FDT: fdt-1
249 23:16:05.215558 output: Loadables: kernel-1
250 23:16:05.215609 output:
251 23:16:05.215807 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 23:16:05.215906 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 23:16:05.216009 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 23:16:05.216098 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 23:16:05.216176 No LXC device requested
256 23:16:05.216254 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 23:16:05.216337 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 23:16:05.216418 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 23:16:05.216488 Checking files for TFTP limit of 4294967296 bytes.
260 23:16:05.216997 end: 1 tftp-deploy (duration 00:00:21) [common]
261 23:16:05.217098 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 23:16:05.217184 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 23:16:05.217301 substitutions:
264 23:16:05.217365 - {DTB}: 12172418/tftp-deploy-1y2kapwx/dtb/mt8192-asurada-spherion-r0.dtb
265 23:16:05.217429 - {INITRD}: 12172418/tftp-deploy-1y2kapwx/ramdisk/ramdisk.cpio.gz
266 23:16:05.217488 - {KERNEL}: 12172418/tftp-deploy-1y2kapwx/kernel/Image
267 23:16:05.217544 - {LAVA_MAC}: None
268 23:16:05.217643 - {PRESEED_CONFIG}: None
269 23:16:05.217700 - {PRESEED_LOCAL}: None
270 23:16:05.217753 - {RAMDISK}: 12172418/tftp-deploy-1y2kapwx/ramdisk/ramdisk.cpio.gz
271 23:16:05.217807 - {ROOT_PART}: None
272 23:16:05.217860 - {ROOT}: None
273 23:16:05.217914 - {SERVER_IP}: 192.168.201.1
274 23:16:05.217966 - {TEE}: None
275 23:16:05.218020 Parsed boot commands:
276 23:16:05.218072 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 23:16:05.218252 Parsed boot commands: tftpboot 192.168.201.1 12172418/tftp-deploy-1y2kapwx/kernel/image.itb 12172418/tftp-deploy-1y2kapwx/kernel/cmdline
278 23:16:05.218339 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 23:16:05.218424 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 23:16:05.218514 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 23:16:05.218595 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 23:16:05.218669 Not connected, no need to disconnect.
283 23:16:05.218741 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 23:16:05.218823 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 23:16:05.218885 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
286 23:16:05.222907 Setting prompt string to ['lava-test: # ']
287 23:16:05.223274 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 23:16:05.223380 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 23:16:05.223481 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 23:16:05.223573 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 23:16:05.223807 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
292 23:16:10.371581 >> Command sent successfully.
293 23:16:10.382134 Returned 0 in 5 seconds
294 23:16:10.483333 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 23:16:10.484879 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 23:16:10.485399 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 23:16:10.485963 Setting prompt string to 'Starting depthcharge on Spherion...'
299 23:16:10.486300 Changing prompt to 'Starting depthcharge on Spherion...'
300 23:16:10.486651 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 23:16:10.487888 [Enter `^Ec?' for help]
302 23:16:10.650274
303 23:16:10.650823
304 23:16:10.651188 F0: 102B 0000
305 23:16:10.651518
306 23:16:10.653362 F3: 1001 0000 [0200]
307 23:16:10.653843
308 23:16:10.654207 F3: 1001 0000
309 23:16:10.654526
310 23:16:10.654828 F7: 102D 0000
311 23:16:10.655125
312 23:16:10.656927 F1: 0000 0000
313 23:16:10.657358
314 23:16:10.657842 V0: 0000 0000 [0001]
315 23:16:10.658272
316 23:16:10.660502 00: 0007 8000
317 23:16:10.661065
318 23:16:10.661514 01: 0000 0000
319 23:16:10.661984
320 23:16:10.663549 BP: 0C00 0209 [0000]
321 23:16:10.663981
322 23:16:10.664417 G0: 1182 0000
323 23:16:10.664829
324 23:16:10.667734 EC: 0000 0021 [4000]
325 23:16:10.668272
326 23:16:10.668722 S7: 0000 0000 [0000]
327 23:16:10.669139
328 23:16:10.670945 CC: 0000 0000 [0001]
329 23:16:10.671377
330 23:16:10.671817 T0: 0000 0040 [010F]
331 23:16:10.672234
332 23:16:10.672638 Jump to BL
333 23:16:10.673131
334 23:16:10.698064
335 23:16:10.698588
336 23:16:10.699031
337 23:16:10.705048 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 23:16:10.708826 ARM64: Exception handlers installed.
339 23:16:10.712236 ARM64: Testing exception
340 23:16:10.716015 ARM64: Done test exception
341 23:16:10.722850 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 23:16:10.733379 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 23:16:10.739473 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 23:16:10.750039 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 23:16:10.756338 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 23:16:10.763303 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 23:16:10.774966 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 23:16:10.781124 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 23:16:10.800920 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 23:16:10.803826 WDT: Last reset was cold boot
351 23:16:10.807402 SPI1(PAD0) initialized at 2873684 Hz
352 23:16:10.810523 SPI5(PAD0) initialized at 992727 Hz
353 23:16:10.813640 VBOOT: Loading verstage.
354 23:16:10.820502 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 23:16:10.824337 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 23:16:10.827724 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 23:16:10.830477 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 23:16:10.837883 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 23:16:10.844320 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 23:16:10.855798 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 23:16:10.856316
362 23:16:10.856649
363 23:16:10.866276 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 23:16:10.869530 ARM64: Exception handlers installed.
365 23:16:10.870104 ARM64: Testing exception
366 23:16:10.873047 ARM64: Done test exception
367 23:16:10.876310 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 23:16:10.883182 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 23:16:10.896762 Probing TPM: . done!
370 23:16:10.897323 TPM ready after 0 ms
371 23:16:10.903623 Connected to device vid:did:rid of 1ae0:0028:00
372 23:16:10.910224 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
373 23:16:10.970369 Initialized TPM device CR50 revision 0
374 23:16:10.980775 tlcl_send_startup: Startup return code is 0
375 23:16:10.981245 TPM: setup succeeded
376 23:16:10.992505 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 23:16:11.001411 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 23:16:11.013359 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 23:16:11.023529 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 23:16:11.027355 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 23:16:11.030593 in-header: 03 07 00 00 08 00 00 00
382 23:16:11.034422 in-data: aa e4 47 04 13 02 00 00
383 23:16:11.034907 Chrome EC: UHEPI supported
384 23:16:11.041395 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 23:16:11.045280 in-header: 03 95 00 00 08 00 00 00
386 23:16:11.049150 in-data: 18 20 20 08 00 00 00 00
387 23:16:11.049796 Phase 1
388 23:16:11.053112 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 23:16:11.060804 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 23:16:11.064122 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 23:16:11.068202 Recovery requested (1009000e)
392 23:16:11.077878 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 23:16:11.083480 tlcl_extend: response is 0
394 23:16:11.093076 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 23:16:11.098409 tlcl_extend: response is 0
396 23:16:11.105985 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 23:16:11.125493 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 23:16:11.132016 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 23:16:11.132542
400 23:16:11.132872
401 23:16:11.141946 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 23:16:11.145272 ARM64: Exception handlers installed.
403 23:16:11.148307 ARM64: Testing exception
404 23:16:11.148934 ARM64: Done test exception
405 23:16:11.170991 pmic_efuse_setting: Set efuses in 11 msecs
406 23:16:11.174358 pmwrap_interface_init: Select PMIF_VLD_RDY
407 23:16:11.180518 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 23:16:11.183950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 23:16:11.191486 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 23:16:11.195568 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 23:16:11.198986 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 23:16:11.202375 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 23:16:11.210340 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 23:16:11.213436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 23:16:11.217361 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 23:16:11.224766 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 23:16:11.228290 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 23:16:11.232286 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 23:16:11.235815 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 23:16:11.243115 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 23:16:11.250287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 23:16:11.254156 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 23:16:11.261887 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 23:16:11.265969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 23:16:11.273535 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 23:16:11.276866 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 23:16:11.283863 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 23:16:11.287658 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 23:16:11.295398 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 23:16:11.299243 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 23:16:11.302364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 23:16:11.310223 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 23:16:11.313491 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 23:16:11.321071 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 23:16:11.324652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 23:16:11.329094 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 23:16:11.336421 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 23:16:11.339921 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 23:16:11.344076 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 23:16:11.351194 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 23:16:11.354517 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 23:16:11.358598 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 23:16:11.366775 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 23:16:11.369375 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 23:16:11.372868 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 23:16:11.377226 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 23:16:11.384262 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 23:16:11.387599 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 23:16:11.391692 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 23:16:11.394500 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 23:16:11.402174 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 23:16:11.406299 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 23:16:11.409675 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 23:16:11.413507 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 23:16:11.417664 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 23:16:11.420973 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 23:16:11.424869 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 23:16:11.432478 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 23:16:11.443323 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 23:16:11.446960 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 23:16:11.453931 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 23:16:11.465023 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 23:16:11.468851 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 23:16:11.472443 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 23:16:11.475757 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 23:16:11.483542 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1b
467 23:16:11.487351 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 23:16:11.495346 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 23:16:11.498307 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 23:16:11.508898 [RTC]rtc_get_frequency_meter,154: input=15, output=758
471 23:16:11.518087 [RTC]rtc_get_frequency_meter,154: input=23, output=942
472 23:16:11.526927 [RTC]rtc_get_frequency_meter,154: input=19, output=851
473 23:16:11.536564 [RTC]rtc_get_frequency_meter,154: input=17, output=803
474 23:16:11.546485 [RTC]rtc_get_frequency_meter,154: input=16, output=782
475 23:16:11.555627 [RTC]rtc_get_frequency_meter,154: input=16, output=781
476 23:16:11.565856 [RTC]rtc_get_frequency_meter,154: input=17, output=804
477 23:16:11.570075 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
478 23:16:11.573233 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
479 23:16:11.580556 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 23:16:11.583936 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 23:16:11.587206 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 23:16:11.591499 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 23:16:11.594653 ADC[4]: Raw value=906573 ID=7
484 23:16:11.598750 ADC[3]: Raw value=213441 ID=1
485 23:16:11.599278 RAM Code: 0x71
486 23:16:11.602372 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 23:16:11.606362 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 23:16:11.617732 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 23:16:11.621540 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 23:16:11.624732 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 23:16:11.629497 in-header: 03 07 00 00 08 00 00 00
492 23:16:11.633054 in-data: aa e4 47 04 13 02 00 00
493 23:16:11.636949 Chrome EC: UHEPI supported
494 23:16:11.643659 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 23:16:11.647535 in-header: 03 95 00 00 08 00 00 00
496 23:16:11.651420 in-data: 18 20 20 08 00 00 00 00
497 23:16:11.651839 MRC: failed to locate region type 0.
498 23:16:11.658665 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 23:16:11.661950 DRAM-K: Running full calibration
500 23:16:11.669443 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 23:16:11.669995 header.status = 0x0
502 23:16:11.673289 header.version = 0x6 (expected: 0x6)
503 23:16:11.677065 header.size = 0xd00 (expected: 0xd00)
504 23:16:11.680850 header.flags = 0x0
505 23:16:11.684381 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 23:16:11.704171 read SPI 0x72590 0x1c583: 12500 us, 9287 KB/s, 74.296 Mbps
507 23:16:11.712057 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 23:16:11.712656 dram_init: ddr_geometry: 2
509 23:16:11.715402 [EMI] MDL number = 2
510 23:16:11.715888 [EMI] Get MDL freq = 0
511 23:16:11.719640 dram_init: ddr_type: 0
512 23:16:11.720127 is_discrete_lpddr4: 1
513 23:16:11.723008 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 23:16:11.723467
515 23:16:11.723910
516 23:16:11.726574 [Bian_co] ETT version 0.0.0.1
517 23:16:11.730210 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 23:16:11.730655
519 23:16:11.733976 dramc_set_vcore_voltage set vcore to 650000
520 23:16:11.738050 Read voltage for 800, 4
521 23:16:11.738478 Vio18 = 0
522 23:16:11.741677 Vcore = 650000
523 23:16:11.742105 Vdram = 0
524 23:16:11.742446 Vddq = 0
525 23:16:11.742765 Vmddr = 0
526 23:16:11.745687 dram_init: config_dvfs: 1
527 23:16:11.749128 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 23:16:11.756960 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 23:16:11.760932 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
530 23:16:11.764392 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
531 23:16:11.767952 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
532 23:16:11.771957 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
533 23:16:11.772500 MEM_TYPE=3, freq_sel=18
534 23:16:11.775702 sv_algorithm_assistance_LP4_1600
535 23:16:11.778825 ============ PULL DRAM RESETB DOWN ============
536 23:16:11.785294 ========== PULL DRAM RESETB DOWN end =========
537 23:16:11.789314 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 23:16:11.792718 ===================================
539 23:16:11.795953 LPDDR4 DRAM CONFIGURATION
540 23:16:11.800135 ===================================
541 23:16:11.800693 EX_ROW_EN[0] = 0x0
542 23:16:11.803530 EX_ROW_EN[1] = 0x0
543 23:16:11.804083 LP4Y_EN = 0x0
544 23:16:11.806858 WORK_FSP = 0x0
545 23:16:11.807300 WL = 0x2
546 23:16:11.810587 RL = 0x2
547 23:16:11.811031 BL = 0x2
548 23:16:11.811478 RPST = 0x0
549 23:16:11.813869 RD_PRE = 0x0
550 23:16:11.814464 WR_PRE = 0x1
551 23:16:11.818139 WR_PST = 0x0
552 23:16:11.818564 DBI_WR = 0x0
553 23:16:11.820936 DBI_RD = 0x0
554 23:16:11.821364 OTF = 0x1
555 23:16:11.824349 ===================================
556 23:16:11.827596 ===================================
557 23:16:11.830962 ANA top config
558 23:16:11.834451 ===================================
559 23:16:11.837479 DLL_ASYNC_EN = 0
560 23:16:11.837941 ALL_SLAVE_EN = 1
561 23:16:11.840733 NEW_RANK_MODE = 1
562 23:16:11.844235 DLL_IDLE_MODE = 1
563 23:16:11.847710 LP45_APHY_COMB_EN = 1
564 23:16:11.848235 TX_ODT_DIS = 1
565 23:16:11.851461 NEW_8X_MODE = 1
566 23:16:11.855004 ===================================
567 23:16:11.858481 ===================================
568 23:16:11.861707 data_rate = 1600
569 23:16:11.865258 CKR = 1
570 23:16:11.865709 DQ_P2S_RATIO = 8
571 23:16:11.868637 ===================================
572 23:16:11.871809 CA_P2S_RATIO = 8
573 23:16:11.875612 DQ_CA_OPEN = 0
574 23:16:11.878610 DQ_SEMI_OPEN = 0
575 23:16:11.882190 CA_SEMI_OPEN = 0
576 23:16:11.885328 CA_FULL_RATE = 0
577 23:16:11.885782 DQ_CKDIV4_EN = 1
578 23:16:11.888740 CA_CKDIV4_EN = 1
579 23:16:11.891696 CA_PREDIV_EN = 0
580 23:16:11.895340 PH8_DLY = 0
581 23:16:11.898710 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 23:16:11.902090 DQ_AAMCK_DIV = 4
583 23:16:11.902616 CA_AAMCK_DIV = 4
584 23:16:11.905654 CA_ADMCK_DIV = 4
585 23:16:11.908807 DQ_TRACK_CA_EN = 0
586 23:16:11.912177 CA_PICK = 800
587 23:16:11.915521 CA_MCKIO = 800
588 23:16:11.919381 MCKIO_SEMI = 0
589 23:16:11.919902 PLL_FREQ = 3068
590 23:16:11.923492 DQ_UI_PI_RATIO = 32
591 23:16:11.926422 CA_UI_PI_RATIO = 0
592 23:16:11.930416 ===================================
593 23:16:11.934130 ===================================
594 23:16:11.934559 memory_type:LPDDR4
595 23:16:11.937828 GP_NUM : 10
596 23:16:11.938306 SRAM_EN : 1
597 23:16:11.941054 MD32_EN : 0
598 23:16:11.944828 ===================================
599 23:16:11.945270 [ANA_INIT] >>>>>>>>>>>>>>
600 23:16:11.948542 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 23:16:11.952609 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 23:16:11.955878 ===================================
603 23:16:11.959143 data_rate = 1600,PCW = 0X7600
604 23:16:11.962394 ===================================
605 23:16:11.966201 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 23:16:11.972904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 23:16:11.976291 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 23:16:11.982659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 23:16:11.986021 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 23:16:11.989429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 23:16:11.990065 [ANA_INIT] flow start
612 23:16:11.992945 [ANA_INIT] PLL >>>>>>>>
613 23:16:11.996474 [ANA_INIT] PLL <<<<<<<<
614 23:16:11.997006 [ANA_INIT] MIDPI >>>>>>>>
615 23:16:11.999507 [ANA_INIT] MIDPI <<<<<<<<
616 23:16:12.003020 [ANA_INIT] DLL >>>>>>>>
617 23:16:12.003588 [ANA_INIT] flow end
618 23:16:12.010040 ============ LP4 DIFF to SE enter ============
619 23:16:12.012912 ============ LP4 DIFF to SE exit ============
620 23:16:12.013478 [ANA_INIT] <<<<<<<<<<<<<
621 23:16:12.015992 [Flow] Enable top DCM control >>>>>
622 23:16:12.020034 [Flow] Enable top DCM control <<<<<
623 23:16:12.023355 Enable DLL master slave shuffle
624 23:16:12.029716 ==============================================================
625 23:16:12.030295 Gating Mode config
626 23:16:12.036105 ==============================================================
627 23:16:12.039970 Config description:
628 23:16:12.049754 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 23:16:12.056393 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 23:16:12.059650 SELPH_MODE 0: By rank 1: By Phase
631 23:16:12.066514 ==============================================================
632 23:16:12.070048 GAT_TRACK_EN = 1
633 23:16:12.070630 RX_GATING_MODE = 2
634 23:16:12.073122 RX_GATING_TRACK_MODE = 2
635 23:16:12.076507 SELPH_MODE = 1
636 23:16:12.079963 PICG_EARLY_EN = 1
637 23:16:12.082747 VALID_LAT_VALUE = 1
638 23:16:12.089517 ==============================================================
639 23:16:12.093533 Enter into Gating configuration >>>>
640 23:16:12.096650 Exit from Gating configuration <<<<
641 23:16:12.099896 Enter into DVFS_PRE_config >>>>>
642 23:16:12.110576 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 23:16:12.113176 Exit from DVFS_PRE_config <<<<<
644 23:16:12.116602 Enter into PICG configuration >>>>
645 23:16:12.119969 Exit from PICG configuration <<<<
646 23:16:12.123500 [RX_INPUT] configuration >>>>>
647 23:16:12.124079 [RX_INPUT] configuration <<<<<
648 23:16:12.129923 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 23:16:12.136606 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 23:16:12.139854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 23:16:12.146619 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 23:16:12.153448 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 23:16:12.159926 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 23:16:12.163272 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 23:16:12.166874 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 23:16:12.173357 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 23:16:12.177092 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 23:16:12.180268 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 23:16:12.183345 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 23:16:12.186503 ===================================
661 23:16:12.190092 LPDDR4 DRAM CONFIGURATION
662 23:16:12.193358 ===================================
663 23:16:12.197022 EX_ROW_EN[0] = 0x0
664 23:16:12.197642 EX_ROW_EN[1] = 0x0
665 23:16:12.200030 LP4Y_EN = 0x0
666 23:16:12.200515 WORK_FSP = 0x0
667 23:16:12.203594 WL = 0x2
668 23:16:12.204179 RL = 0x2
669 23:16:12.206906 BL = 0x2
670 23:16:12.207489 RPST = 0x0
671 23:16:12.210512 RD_PRE = 0x0
672 23:16:12.211093 WR_PRE = 0x1
673 23:16:12.213758 WR_PST = 0x0
674 23:16:12.214333 DBI_WR = 0x0
675 23:16:12.217258 DBI_RD = 0x0
676 23:16:12.217791 OTF = 0x1
677 23:16:12.220545 ===================================
678 23:16:12.227059 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 23:16:12.229858 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 23:16:12.233200 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 23:16:12.236771 ===================================
682 23:16:12.240289 LPDDR4 DRAM CONFIGURATION
683 23:16:12.243789 ===================================
684 23:16:12.244342 EX_ROW_EN[0] = 0x10
685 23:16:12.246582 EX_ROW_EN[1] = 0x0
686 23:16:12.250170 LP4Y_EN = 0x0
687 23:16:12.250588 WORK_FSP = 0x0
688 23:16:12.253740 WL = 0x2
689 23:16:12.254260 RL = 0x2
690 23:16:12.256547 BL = 0x2
691 23:16:12.256966 RPST = 0x0
692 23:16:12.259967 RD_PRE = 0x0
693 23:16:12.260385 WR_PRE = 0x1
694 23:16:12.263584 WR_PST = 0x0
695 23:16:12.264002 DBI_WR = 0x0
696 23:16:12.267291 DBI_RD = 0x0
697 23:16:12.267823 OTF = 0x1
698 23:16:12.270519 ===================================
699 23:16:12.277138 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 23:16:12.281208 nWR fixed to 40
701 23:16:12.284541 [ModeRegInit_LP4] CH0 RK0
702 23:16:12.285066 [ModeRegInit_LP4] CH0 RK1
703 23:16:12.288116 [ModeRegInit_LP4] CH1 RK0
704 23:16:12.291229 [ModeRegInit_LP4] CH1 RK1
705 23:16:12.291674 match AC timing 13
706 23:16:12.298064 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 23:16:12.301251 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 23:16:12.304863 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 23:16:12.311207 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 23:16:12.314562 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 23:16:12.315142 [EMI DOE] emi_dcm 0
712 23:16:12.320937 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 23:16:12.321677 ==
714 23:16:12.324281 Dram Type= 6, Freq= 0, CH_0, rank 0
715 23:16:12.327994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 23:16:12.328646 ==
717 23:16:12.334527 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 23:16:12.337770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 23:16:12.348616 [CA 0] Center 36 (6~67) winsize 62
720 23:16:12.352465 [CA 1] Center 36 (6~67) winsize 62
721 23:16:12.355346 [CA 2] Center 34 (4~65) winsize 62
722 23:16:12.358477 [CA 3] Center 34 (4~64) winsize 61
723 23:16:12.361977 [CA 4] Center 33 (2~64) winsize 63
724 23:16:12.365234 [CA 5] Center 32 (2~62) winsize 61
725 23:16:12.365722
726 23:16:12.368862 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 23:16:12.369388
728 23:16:12.372468 [CATrainingPosCal] consider 1 rank data
729 23:16:12.375890 u2DelayCellTimex100 = 270/100 ps
730 23:16:12.378821 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
731 23:16:12.382286 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
732 23:16:12.388629 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
733 23:16:12.392111 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
734 23:16:12.395211 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
735 23:16:12.398533 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
736 23:16:12.399104
737 23:16:12.402028 CA PerBit enable=1, Macro0, CA PI delay=32
738 23:16:12.402589
739 23:16:12.405300 [CBTSetCACLKResult] CA Dly = 32
740 23:16:12.405946 CS Dly: 4 (0~35)
741 23:16:12.408456 ==
742 23:16:12.408927 Dram Type= 6, Freq= 0, CH_0, rank 1
743 23:16:12.415516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 23:16:12.416179 ==
745 23:16:12.418825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 23:16:12.425506 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 23:16:12.434653 [CA 0] Center 36 (6~67) winsize 62
748 23:16:12.438214 [CA 1] Center 36 (6~67) winsize 62
749 23:16:12.441472 [CA 2] Center 34 (3~65) winsize 63
750 23:16:12.444574 [CA 3] Center 34 (3~65) winsize 63
751 23:16:12.448115 [CA 4] Center 33 (3~63) winsize 61
752 23:16:12.451396 [CA 5] Center 32 (2~63) winsize 62
753 23:16:12.451869
754 23:16:12.454888 [CmdBusTrainingLP45] Vref(ca) range 1: 32
755 23:16:12.455466
756 23:16:12.458507 [CATrainingPosCal] consider 2 rank data
757 23:16:12.461631 u2DelayCellTimex100 = 270/100 ps
758 23:16:12.464689 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
759 23:16:12.468283 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
760 23:16:12.474811 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
761 23:16:12.478953 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
762 23:16:12.482117 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
763 23:16:12.485035 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
764 23:16:12.485561
765 23:16:12.488747 CA PerBit enable=1, Macro0, CA PI delay=32
766 23:16:12.489273
767 23:16:12.492133 [CBTSetCACLKResult] CA Dly = 32
768 23:16:12.492657 CS Dly: 5 (0~37)
769 23:16:12.493001
770 23:16:12.494911 ----->DramcWriteLeveling(PI) begin...
771 23:16:12.495358 ==
772 23:16:12.498654 Dram Type= 6, Freq= 0, CH_0, rank 0
773 23:16:12.502437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 23:16:12.506426 ==
775 23:16:12.506853 Write leveling (Byte 0): 35 => 35
776 23:16:12.509690 Write leveling (Byte 1): 32 => 32
777 23:16:12.513718 DramcWriteLeveling(PI) end<-----
778 23:16:12.514280
779 23:16:12.514626 ==
780 23:16:12.516980 Dram Type= 6, Freq= 0, CH_0, rank 0
781 23:16:12.520723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 23:16:12.521161 ==
783 23:16:12.523462 [Gating] SW mode calibration
784 23:16:12.530689 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 23:16:12.537711 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 23:16:12.541105 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 23:16:12.544334 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 23:16:12.550895 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
789 23:16:12.554430 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 23:16:12.558035 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 23:16:12.564618 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 23:16:12.568041 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 23:16:12.571389 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 23:16:12.574696 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 23:16:12.581295 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 23:16:12.584943 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 23:16:12.587571 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 23:16:12.594367 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 23:16:12.598107 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 23:16:12.601025 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 23:16:12.607726 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 23:16:12.611605 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 23:16:12.614451 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 23:16:12.621083 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 23:16:12.624789 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 23:16:12.628613 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 23:16:12.634781 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 23:16:12.637919 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 23:16:12.641555 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 23:16:12.644353 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 23:16:12.651373 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 23:16:12.655184 0 9 8 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
813 23:16:12.658375 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
814 23:16:12.665377 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 23:16:12.668782 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 23:16:12.671652 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 23:16:12.678413 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 23:16:12.681694 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 23:16:12.685293 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
820 23:16:12.691772 0 10 8 | B1->B0 | 2f2f 2828 | 0 0 | (0 1) (0 1)
821 23:16:12.694740 0 10 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
822 23:16:12.698426 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 23:16:12.705266 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 23:16:12.708825 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 23:16:12.711866 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 23:16:12.715162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 23:16:12.721683 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
828 23:16:12.725357 0 11 8 | B1->B0 | 2525 3b3b | 0 0 | (0 0) (1 1)
829 23:16:12.728469 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
830 23:16:12.735206 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 23:16:12.738113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 23:16:12.741643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 23:16:12.748802 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 23:16:12.751891 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 23:16:12.755331 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 23:16:12.761502 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
837 23:16:12.765107 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 23:16:12.768264 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 23:16:12.775514 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 23:16:12.778931 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 23:16:12.781430 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 23:16:12.788163 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 23:16:12.791367 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 23:16:12.794689 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 23:16:12.798722 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 23:16:12.805284 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 23:16:12.808484 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 23:16:12.811925 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 23:16:12.818669 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 23:16:12.822076 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 23:16:12.824930 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
852 23:16:12.831699 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
853 23:16:12.835202 Total UI for P1: 0, mck2ui 16
854 23:16:12.838263 best dqsien dly found for B0: ( 0, 14, 4)
855 23:16:12.841796 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 23:16:12.844763 Total UI for P1: 0, mck2ui 16
857 23:16:12.848069 best dqsien dly found for B1: ( 0, 14, 8)
858 23:16:12.852321 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
859 23:16:12.856218 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 23:16:12.856747
861 23:16:12.859336 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
862 23:16:12.862166 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 23:16:12.865958 [Gating] SW calibration Done
864 23:16:12.866494 ==
865 23:16:12.869114 Dram Type= 6, Freq= 0, CH_0, rank 0
866 23:16:12.872458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 23:16:12.872980 ==
868 23:16:12.875657 RX Vref Scan: 0
869 23:16:12.876084
870 23:16:12.876422 RX Vref 0 -> 0, step: 1
871 23:16:12.876741
872 23:16:12.879168 RX Delay -130 -> 252, step: 16
873 23:16:12.882506 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
874 23:16:12.889300 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
875 23:16:12.892626 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
876 23:16:12.896161 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
877 23:16:12.899476 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
878 23:16:12.902525 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
879 23:16:12.908848 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
880 23:16:12.912661 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
881 23:16:12.916386 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
882 23:16:12.919287 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
883 23:16:12.922079 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
884 23:16:12.929098 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
885 23:16:12.932367 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
886 23:16:12.935728 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
887 23:16:12.938703 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
888 23:16:12.945540 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
889 23:16:12.946168 ==
890 23:16:12.948813 Dram Type= 6, Freq= 0, CH_0, rank 0
891 23:16:12.952481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 23:16:12.953134 ==
893 23:16:12.953765 DQS Delay:
894 23:16:12.955562 DQS0 = 0, DQS1 = 0
895 23:16:12.956187 DQM Delay:
896 23:16:12.959380 DQM0 = 89, DQM1 = 80
897 23:16:12.960141 DQ Delay:
898 23:16:12.962182 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 23:16:12.965461 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
900 23:16:12.968946 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
901 23:16:12.972880 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
902 23:16:12.973406
903 23:16:12.973836
904 23:16:12.974161 ==
905 23:16:12.975597 Dram Type= 6, Freq= 0, CH_0, rank 0
906 23:16:12.979476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 23:16:12.980006 ==
908 23:16:12.980349
909 23:16:12.980668
910 23:16:12.982264 TX Vref Scan disable
911 23:16:12.985659 == TX Byte 0 ==
912 23:16:12.989496 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
913 23:16:12.992197 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
914 23:16:12.995622 == TX Byte 1 ==
915 23:16:12.998919 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
916 23:16:13.002701 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
917 23:16:13.003226 ==
918 23:16:13.005550 Dram Type= 6, Freq= 0, CH_0, rank 0
919 23:16:13.009229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 23:16:13.012627 ==
921 23:16:13.023850 TX Vref=22, minBit 7, minWin=27, winSum=444
922 23:16:13.027241 TX Vref=24, minBit 13, minWin=27, winSum=451
923 23:16:13.031080 TX Vref=26, minBit 0, minWin=28, winSum=454
924 23:16:13.033846 TX Vref=28, minBit 4, minWin=28, winSum=455
925 23:16:13.037405 TX Vref=30, minBit 5, minWin=28, winSum=457
926 23:16:13.043821 TX Vref=32, minBit 11, minWin=27, winSum=452
927 23:16:13.047149 [TxChooseVref] Worse bit 5, Min win 28, Win sum 457, Final Vref 30
928 23:16:13.047833
929 23:16:13.050682 Final TX Range 1 Vref 30
930 23:16:13.051152
931 23:16:13.051524 ==
932 23:16:13.053940 Dram Type= 6, Freq= 0, CH_0, rank 0
933 23:16:13.057471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 23:16:13.058086 ==
935 23:16:13.060238
936 23:16:13.060706
937 23:16:13.061079 TX Vref Scan disable
938 23:16:13.063657 == TX Byte 0 ==
939 23:16:13.067504 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
940 23:16:13.073705 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
941 23:16:13.074184 == TX Byte 1 ==
942 23:16:13.077484 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
943 23:16:13.084033 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
944 23:16:13.084554
945 23:16:13.084890 [DATLAT]
946 23:16:13.085328 Freq=800, CH0 RK0
947 23:16:13.085830
948 23:16:13.087141 DATLAT Default: 0xa
949 23:16:13.087562 0, 0xFFFF, sum = 0
950 23:16:13.090819 1, 0xFFFF, sum = 0
951 23:16:13.091250 2, 0xFFFF, sum = 0
952 23:16:13.094036 3, 0xFFFF, sum = 0
953 23:16:13.094468 4, 0xFFFF, sum = 0
954 23:16:13.097614 5, 0xFFFF, sum = 0
955 23:16:13.100764 6, 0xFFFF, sum = 0
956 23:16:13.101344 7, 0xFFFF, sum = 0
957 23:16:13.103768 8, 0xFFFF, sum = 0
958 23:16:13.104196 9, 0x0, sum = 1
959 23:16:13.104539 10, 0x0, sum = 2
960 23:16:13.107557 11, 0x0, sum = 3
961 23:16:13.108107 12, 0x0, sum = 4
962 23:16:13.110338 best_step = 10
963 23:16:13.110762
964 23:16:13.111096 ==
965 23:16:13.114040 Dram Type= 6, Freq= 0, CH_0, rank 0
966 23:16:13.117490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 23:16:13.118083 ==
968 23:16:13.120756 RX Vref Scan: 1
969 23:16:13.121286
970 23:16:13.121684 Set Vref Range= 32 -> 127
971 23:16:13.122017
972 23:16:13.124121 RX Vref 32 -> 127, step: 1
973 23:16:13.124550
974 23:16:13.127110 RX Delay -95 -> 252, step: 8
975 23:16:13.127534
976 23:16:13.130528 Set Vref, RX VrefLevel [Byte0]: 32
977 23:16:13.134247 [Byte1]: 32
978 23:16:13.134740
979 23:16:13.137312 Set Vref, RX VrefLevel [Byte0]: 33
980 23:16:13.140804 [Byte1]: 33
981 23:16:13.144452
982 23:16:13.145053 Set Vref, RX VrefLevel [Byte0]: 34
983 23:16:13.147664 [Byte1]: 34
984 23:16:13.151890
985 23:16:13.152424 Set Vref, RX VrefLevel [Byte0]: 35
986 23:16:13.155004 [Byte1]: 35
987 23:16:13.160459
988 23:16:13.161010 Set Vref, RX VrefLevel [Byte0]: 36
989 23:16:13.163356 [Byte1]: 36
990 23:16:13.167449
991 23:16:13.167911 Set Vref, RX VrefLevel [Byte0]: 37
992 23:16:13.170366 [Byte1]: 37
993 23:16:13.174681
994 23:16:13.175102 Set Vref, RX VrefLevel [Byte0]: 38
995 23:16:13.178165 [Byte1]: 38
996 23:16:13.182626
997 23:16:13.183141 Set Vref, RX VrefLevel [Byte0]: 39
998 23:16:13.185885 [Byte1]: 39
999 23:16:13.190290
1000 23:16:13.190714 Set Vref, RX VrefLevel [Byte0]: 40
1001 23:16:13.193826 [Byte1]: 40
1002 23:16:13.197453
1003 23:16:13.198070 Set Vref, RX VrefLevel [Byte0]: 41
1004 23:16:13.200942 [Byte1]: 41
1005 23:16:13.204903
1006 23:16:13.205322 Set Vref, RX VrefLevel [Byte0]: 42
1007 23:16:13.208449 [Byte1]: 42
1008 23:16:13.212706
1009 23:16:13.213135 Set Vref, RX VrefLevel [Byte0]: 43
1010 23:16:13.215935 [Byte1]: 43
1011 23:16:13.220682
1012 23:16:13.221204 Set Vref, RX VrefLevel [Byte0]: 44
1013 23:16:13.223310 [Byte1]: 44
1014 23:16:13.228117
1015 23:16:13.228540 Set Vref, RX VrefLevel [Byte0]: 45
1016 23:16:13.231736 [Byte1]: 45
1017 23:16:13.235711
1018 23:16:13.236235 Set Vref, RX VrefLevel [Byte0]: 46
1019 23:16:13.238677 [Byte1]: 46
1020 23:16:13.242746
1021 23:16:13.243164 Set Vref, RX VrefLevel [Byte0]: 47
1022 23:16:13.246183 [Byte1]: 47
1023 23:16:13.251192
1024 23:16:13.251714 Set Vref, RX VrefLevel [Byte0]: 48
1025 23:16:13.253895 [Byte1]: 48
1026 23:16:13.258150
1027 23:16:13.258692 Set Vref, RX VrefLevel [Byte0]: 49
1028 23:16:13.261674 [Byte1]: 49
1029 23:16:13.265891
1030 23:16:13.266414 Set Vref, RX VrefLevel [Byte0]: 50
1031 23:16:13.269683 [Byte1]: 50
1032 23:16:13.273551
1033 23:16:13.274106 Set Vref, RX VrefLevel [Byte0]: 51
1034 23:16:13.277039 [Byte1]: 51
1035 23:16:13.281642
1036 23:16:13.282155 Set Vref, RX VrefLevel [Byte0]: 52
1037 23:16:13.284629 [Byte1]: 52
1038 23:16:13.288687
1039 23:16:13.289203 Set Vref, RX VrefLevel [Byte0]: 53
1040 23:16:13.292144 [Byte1]: 53
1041 23:16:13.296313
1042 23:16:13.296823 Set Vref, RX VrefLevel [Byte0]: 54
1043 23:16:13.299609 [Byte1]: 54
1044 23:16:13.304023
1045 23:16:13.304557 Set Vref, RX VrefLevel [Byte0]: 55
1046 23:16:13.306897 [Byte1]: 55
1047 23:16:13.311527
1048 23:16:13.312031 Set Vref, RX VrefLevel [Byte0]: 56
1049 23:16:13.314518 [Byte1]: 56
1050 23:16:13.318930
1051 23:16:13.319427 Set Vref, RX VrefLevel [Byte0]: 57
1052 23:16:13.322417 [Byte1]: 57
1053 23:16:13.326732
1054 23:16:13.327235 Set Vref, RX VrefLevel [Byte0]: 58
1055 23:16:13.329871 [Byte1]: 58
1056 23:16:13.333993
1057 23:16:13.334427 Set Vref, RX VrefLevel [Byte0]: 59
1058 23:16:13.337452 [Byte1]: 59
1059 23:16:13.341963
1060 23:16:13.342382 Set Vref, RX VrefLevel [Byte0]: 60
1061 23:16:13.345102 [Byte1]: 60
1062 23:16:13.349307
1063 23:16:13.349756 Set Vref, RX VrefLevel [Byte0]: 61
1064 23:16:13.352670 [Byte1]: 61
1065 23:16:13.357388
1066 23:16:13.357968 Set Vref, RX VrefLevel [Byte0]: 62
1067 23:16:13.360870 [Byte1]: 62
1068 23:16:13.364553
1069 23:16:13.365206 Set Vref, RX VrefLevel [Byte0]: 63
1070 23:16:13.367717 [Byte1]: 63
1071 23:16:13.372299
1072 23:16:13.372762 Set Vref, RX VrefLevel [Byte0]: 64
1073 23:16:13.375410 [Byte1]: 64
1074 23:16:13.379604
1075 23:16:13.380104 Set Vref, RX VrefLevel [Byte0]: 65
1076 23:16:13.383041 [Byte1]: 65
1077 23:16:13.387187
1078 23:16:13.387603 Set Vref, RX VrefLevel [Byte0]: 66
1079 23:16:13.390626 [Byte1]: 66
1080 23:16:13.394985
1081 23:16:13.395498 Set Vref, RX VrefLevel [Byte0]: 67
1082 23:16:13.398432 [Byte1]: 67
1083 23:16:13.402423
1084 23:16:13.402842 Set Vref, RX VrefLevel [Byte0]: 68
1085 23:16:13.406027 [Byte1]: 68
1086 23:16:13.410457
1087 23:16:13.410966 Set Vref, RX VrefLevel [Byte0]: 69
1088 23:16:13.413883 [Byte1]: 69
1089 23:16:13.417847
1090 23:16:13.418376 Set Vref, RX VrefLevel [Byte0]: 70
1091 23:16:13.420897 [Byte1]: 70
1092 23:16:13.425613
1093 23:16:13.426034 Set Vref, RX VrefLevel [Byte0]: 71
1094 23:16:13.428385 [Byte1]: 71
1095 23:16:13.433198
1096 23:16:13.433770 Set Vref, RX VrefLevel [Byte0]: 72
1097 23:16:13.436528 [Byte1]: 72
1098 23:16:13.440530
1099 23:16:13.440939 Set Vref, RX VrefLevel [Byte0]: 73
1100 23:16:13.444119 [Byte1]: 73
1101 23:16:13.448505
1102 23:16:13.449000 Set Vref, RX VrefLevel [Byte0]: 74
1103 23:16:13.451497 [Byte1]: 74
1104 23:16:13.455995
1105 23:16:13.456679 Set Vref, RX VrefLevel [Byte0]: 75
1106 23:16:13.459164 [Byte1]: 75
1107 23:16:13.463327
1108 23:16:13.463746 Set Vref, RX VrefLevel [Byte0]: 76
1109 23:16:13.466524 [Byte1]: 76
1110 23:16:13.470759
1111 23:16:13.471312 Set Vref, RX VrefLevel [Byte0]: 77
1112 23:16:13.474011 [Byte1]: 77
1113 23:16:13.478978
1114 23:16:13.479389 Final RX Vref Byte 0 = 60 to rank0
1115 23:16:13.482004 Final RX Vref Byte 1 = 60 to rank0
1116 23:16:13.485264 Final RX Vref Byte 0 = 60 to rank1
1117 23:16:13.488780 Final RX Vref Byte 1 = 60 to rank1==
1118 23:16:13.492156 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 23:16:13.499118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 23:16:13.499629 ==
1121 23:16:13.499958 DQS Delay:
1122 23:16:13.500261 DQS0 = 0, DQS1 = 0
1123 23:16:13.502296 DQM Delay:
1124 23:16:13.502702 DQM0 = 92, DQM1 = 85
1125 23:16:13.506082 DQ Delay:
1126 23:16:13.506593 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1127 23:16:13.509643 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1128 23:16:13.511883 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =80
1129 23:16:13.519038 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1130 23:16:13.519553
1131 23:16:13.519881
1132 23:16:13.525614 [DQSOSCAuto] RK0, (LSB)MR18= 0x463b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1133 23:16:13.528587 CH0 RK0: MR19=606, MR18=463B
1134 23:16:13.535595 CH0_RK0: MR19=0x606, MR18=0x463B, DQSOSC=392, MR23=63, INC=96, DEC=64
1135 23:16:13.536132
1136 23:16:13.538686 ----->DramcWriteLeveling(PI) begin...
1137 23:16:13.539142 ==
1138 23:16:13.542111 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 23:16:13.545652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 23:16:13.546252 ==
1141 23:16:13.548824 Write leveling (Byte 0): 33 => 33
1142 23:16:13.552149 Write leveling (Byte 1): 30 => 30
1143 23:16:13.555344 DramcWriteLeveling(PI) end<-----
1144 23:16:13.555896
1145 23:16:13.556264 ==
1146 23:16:13.558934 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 23:16:13.562390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 23:16:13.562943 ==
1149 23:16:13.565206 [Gating] SW mode calibration
1150 23:16:13.612677 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 23:16:13.613183 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 23:16:13.613872 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 23:16:13.614239 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 23:16:13.614545 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1155 23:16:13.614836 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 23:16:13.615122 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 23:16:13.615459 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 23:16:13.615750 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 23:16:13.616029 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 23:16:13.656967 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 23:16:13.657548 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 23:16:13.657988 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 23:16:13.658328 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 23:16:13.659018 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 23:16:13.659409 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 23:16:13.659860 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 23:16:13.660296 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 23:16:13.660720 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 23:16:13.661143 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1170 23:16:13.701043 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1171 23:16:13.701627 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 23:16:13.702112 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 23:16:13.702569 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 23:16:13.703411 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 23:16:13.703814 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 23:16:13.704247 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 23:16:13.704762 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 23:16:13.705189 0 9 8 | B1->B0 | 3131 2b2b | 0 1 | (0 0) (0 0)
1179 23:16:13.705646 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 23:16:13.715134 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 23:16:13.715725 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 23:16:13.718143 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 23:16:13.718616 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 23:16:13.721544 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 23:16:13.728031 0 10 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
1186 23:16:13.731083 0 10 8 | B1->B0 | 2a2a 2d2d | 0 0 | (0 0) (0 1)
1187 23:16:13.734678 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 23:16:13.741569 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 23:16:13.745342 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 23:16:13.749216 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 23:16:13.752744 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 23:16:13.756671 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 23:16:13.763807 0 11 4 | B1->B0 | 2828 2424 | 0 0 | (1 1) (0 0)
1194 23:16:13.766957 0 11 8 | B1->B0 | 3e3e 3333 | 0 1 | (0 0) (0 0)
1195 23:16:13.771091 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 23:16:13.774272 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 23:16:13.781324 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 23:16:13.784623 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 23:16:13.787607 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 23:16:13.794502 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 23:16:13.797714 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1202 23:16:13.801674 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1203 23:16:13.808466 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 23:16:13.811041 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 23:16:13.814025 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 23:16:13.821074 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 23:16:13.824328 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 23:16:13.827765 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 23:16:13.830950 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 23:16:13.837980 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 23:16:13.841174 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 23:16:13.844341 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 23:16:13.850900 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 23:16:13.854286 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 23:16:13.857615 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 23:16:13.864286 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 23:16:13.867654 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 23:16:13.871116 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1219 23:16:13.877711 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1220 23:16:13.878137 Total UI for P1: 0, mck2ui 16
1221 23:16:13.884615 best dqsien dly found for B1: ( 0, 14, 8)
1222 23:16:13.887836 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1223 23:16:13.890935 Total UI for P1: 0, mck2ui 16
1224 23:16:13.894460 best dqsien dly found for B0: ( 0, 14, 10)
1225 23:16:13.897811 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
1226 23:16:13.901335 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1227 23:16:13.901922
1228 23:16:13.904457 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
1229 23:16:13.908016 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1230 23:16:13.911211 [Gating] SW calibration Done
1231 23:16:13.911735 ==
1232 23:16:13.914434 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 23:16:13.917533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 23:16:13.917997 ==
1235 23:16:13.921080 RX Vref Scan: 0
1236 23:16:13.921503
1237 23:16:13.924643 RX Vref 0 -> 0, step: 1
1238 23:16:13.925159
1239 23:16:13.925637 RX Delay -130 -> 252, step: 16
1240 23:16:13.930976 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1241 23:16:13.934272 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1242 23:16:13.937695 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1243 23:16:13.941210 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1244 23:16:13.944693 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1245 23:16:13.951381 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1246 23:16:13.954581 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1247 23:16:13.957612 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1248 23:16:13.961265 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1249 23:16:13.964607 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1250 23:16:13.971006 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1251 23:16:13.974168 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1252 23:16:13.977962 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1253 23:16:13.981384 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1254 23:16:13.984803 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1255 23:16:13.990997 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1256 23:16:13.991468 ==
1257 23:16:13.994299 Dram Type= 6, Freq= 0, CH_0, rank 1
1258 23:16:13.998460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1259 23:16:13.999038 ==
1260 23:16:13.999541 DQS Delay:
1261 23:16:14.001084 DQS0 = 0, DQS1 = 0
1262 23:16:14.001555 DQM Delay:
1263 23:16:14.004963 DQM0 = 93, DQM1 = 85
1264 23:16:14.005527 DQ Delay:
1265 23:16:14.008162 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1266 23:16:14.011437 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1267 23:16:14.014619 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1268 23:16:14.017978 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1269 23:16:14.018449
1270 23:16:14.018921
1271 23:16:14.019364 ==
1272 23:16:14.021205 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 23:16:14.024675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 23:16:14.025230 ==
1275 23:16:14.025808
1276 23:16:14.028261
1277 23:16:14.028829 TX Vref Scan disable
1278 23:16:14.031244 == TX Byte 0 ==
1279 23:16:14.034634 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1280 23:16:14.037986 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1281 23:16:14.041260 == TX Byte 1 ==
1282 23:16:14.045043 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1283 23:16:14.048215 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1284 23:16:14.048803 ==
1285 23:16:14.051480 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 23:16:14.057973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 23:16:14.058458 ==
1288 23:16:14.070107 TX Vref=22, minBit 8, minWin=27, winSum=446
1289 23:16:14.073314 TX Vref=24, minBit 1, minWin=28, winSum=452
1290 23:16:14.076825 TX Vref=26, minBit 4, minWin=28, winSum=455
1291 23:16:14.080077 TX Vref=28, minBit 5, minWin=28, winSum=460
1292 23:16:14.084156 TX Vref=30, minBit 4, minWin=28, winSum=456
1293 23:16:14.086568 TX Vref=32, minBit 8, minWin=27, winSum=452
1294 23:16:14.093849 [TxChooseVref] Worse bit 5, Min win 28, Win sum 460, Final Vref 28
1295 23:16:14.094279
1296 23:16:14.096659 Final TX Range 1 Vref 28
1297 23:16:14.097079
1298 23:16:14.097398 ==
1299 23:16:14.099846 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 23:16:14.103167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 23:16:14.103580 ==
1302 23:16:14.103902
1303 23:16:14.104197
1304 23:16:14.106587 TX Vref Scan disable
1305 23:16:14.110019 == TX Byte 0 ==
1306 23:16:14.113212 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1307 23:16:14.116704 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1308 23:16:14.119894 == TX Byte 1 ==
1309 23:16:14.123246 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1310 23:16:14.126521 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1311 23:16:14.130172
1312 23:16:14.130576 [DATLAT]
1313 23:16:14.130816 Freq=800, CH0 RK1
1314 23:16:14.131031
1315 23:16:14.133291 DATLAT Default: 0xa
1316 23:16:14.133727 0, 0xFFFF, sum = 0
1317 23:16:14.136452 1, 0xFFFF, sum = 0
1318 23:16:14.136747 2, 0xFFFF, sum = 0
1319 23:16:14.139925 3, 0xFFFF, sum = 0
1320 23:16:14.140262 4, 0xFFFF, sum = 0
1321 23:16:14.143763 5, 0xFFFF, sum = 0
1322 23:16:14.144153 6, 0xFFFF, sum = 0
1323 23:16:14.146559 7, 0xFFFF, sum = 0
1324 23:16:14.149653 8, 0xFFFF, sum = 0
1325 23:16:14.149948 9, 0x0, sum = 1
1326 23:16:14.150182 10, 0x0, sum = 2
1327 23:16:14.153120 11, 0x0, sum = 3
1328 23:16:14.153408 12, 0x0, sum = 4
1329 23:16:14.156832 best_step = 10
1330 23:16:14.157220
1331 23:16:14.157465 ==
1332 23:16:14.159809 Dram Type= 6, Freq= 0, CH_0, rank 1
1333 23:16:14.163441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1334 23:16:14.163828 ==
1335 23:16:14.166795 RX Vref Scan: 0
1336 23:16:14.167283
1337 23:16:14.167594 RX Vref 0 -> 0, step: 1
1338 23:16:14.167871
1339 23:16:14.170221 RX Delay -79 -> 252, step: 8
1340 23:16:14.176752 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1341 23:16:14.180331 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1342 23:16:14.183925 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1343 23:16:14.187149 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1344 23:16:14.190559 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1345 23:16:14.197566 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1346 23:16:14.200332 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1347 23:16:14.203536 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1348 23:16:14.207161 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1349 23:16:14.210136 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1350 23:16:14.213695 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
1351 23:16:14.220504 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1352 23:16:14.223856 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1353 23:16:14.227060 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1354 23:16:14.230259 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1355 23:16:14.234305 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1356 23:16:14.237006 ==
1357 23:16:14.240735 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 23:16:14.244155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 23:16:14.244714 ==
1360 23:16:14.245069 DQS Delay:
1361 23:16:14.247157 DQS0 = 0, DQS1 = 0
1362 23:16:14.247603 DQM Delay:
1363 23:16:14.250565 DQM0 = 93, DQM1 = 84
1364 23:16:14.251102 DQ Delay:
1365 23:16:14.254455 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1366 23:16:14.257355 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1367 23:16:14.260704 DQ8 =72, DQ9 =72, DQ10 =88, DQ11 =76
1368 23:16:14.264104 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1369 23:16:14.264658
1370 23:16:14.265009
1371 23:16:14.270933 [DQSOSCAuto] RK1, (LSB)MR18= 0x3e10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
1372 23:16:14.274182 CH0 RK1: MR19=606, MR18=3E10
1373 23:16:14.281462 CH0_RK1: MR19=0x606, MR18=0x3E10, DQSOSC=394, MR23=63, INC=95, DEC=63
1374 23:16:14.284521 [RxdqsGatingPostProcess] freq 800
1375 23:16:14.287626 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1376 23:16:14.290680 Pre-setting of DQS Precalculation
1377 23:16:14.297697 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1378 23:16:14.298294 ==
1379 23:16:14.300690 Dram Type= 6, Freq= 0, CH_1, rank 0
1380 23:16:14.303911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1381 23:16:14.304479 ==
1382 23:16:14.311099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1383 23:16:14.317322 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1384 23:16:14.325312 [CA 0] Center 36 (6~67) winsize 62
1385 23:16:14.328527 [CA 1] Center 36 (6~67) winsize 62
1386 23:16:14.332301 [CA 2] Center 35 (4~66) winsize 63
1387 23:16:14.334967 [CA 3] Center 34 (4~65) winsize 62
1388 23:16:14.338325 [CA 4] Center 35 (5~65) winsize 61
1389 23:16:14.341814 [CA 5] Center 34 (4~65) winsize 62
1390 23:16:14.342353
1391 23:16:14.345129 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1392 23:16:14.345714
1393 23:16:14.348757 [CATrainingPosCal] consider 1 rank data
1394 23:16:14.352095 u2DelayCellTimex100 = 270/100 ps
1395 23:16:14.355210 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1396 23:16:14.358310 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1397 23:16:14.365241 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1398 23:16:14.368648 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1399 23:16:14.371705 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1400 23:16:14.375014 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1401 23:16:14.375467
1402 23:16:14.378547 CA PerBit enable=1, Macro0, CA PI delay=34
1403 23:16:14.379105
1404 23:16:14.382151 [CBTSetCACLKResult] CA Dly = 34
1405 23:16:14.382692 CS Dly: 6 (0~37)
1406 23:16:14.383051 ==
1407 23:16:14.385012 Dram Type= 6, Freq= 0, CH_1, rank 1
1408 23:16:14.391432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1409 23:16:14.391966 ==
1410 23:16:14.395100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1411 23:16:14.401381 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1412 23:16:14.411842 [CA 0] Center 36 (6~67) winsize 62
1413 23:16:14.415610 [CA 1] Center 37 (7~68) winsize 62
1414 23:16:14.418862 [CA 2] Center 35 (4~66) winsize 63
1415 23:16:14.422534 [CA 3] Center 34 (4~65) winsize 62
1416 23:16:14.426175 [CA 4] Center 35 (5~66) winsize 62
1417 23:16:14.429925 [CA 5] Center 34 (4~65) winsize 62
1418 23:16:14.430351
1419 23:16:14.433547 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1420 23:16:14.434023
1421 23:16:14.437382 [CATrainingPosCal] consider 2 rank data
1422 23:16:14.437886 u2DelayCellTimex100 = 270/100 ps
1423 23:16:14.441069 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1424 23:16:14.444484 CA1 delay=37 (7~67),Diff = 3 PI (21 cell)
1425 23:16:14.451002 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1426 23:16:14.454288 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1427 23:16:14.458240 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1428 23:16:14.461343 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1429 23:16:14.461910
1430 23:16:14.464567 CA PerBit enable=1, Macro0, CA PI delay=34
1431 23:16:14.465120
1432 23:16:14.467965 [CBTSetCACLKResult] CA Dly = 34
1433 23:16:14.468520 CS Dly: 6 (0~38)
1434 23:16:14.468881
1435 23:16:14.471387 ----->DramcWriteLeveling(PI) begin...
1436 23:16:14.474911 ==
1437 23:16:14.475467 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 23:16:14.481561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 23:16:14.482163 ==
1440 23:16:14.484741 Write leveling (Byte 0): 27 => 27
1441 23:16:14.488144 Write leveling (Byte 1): 27 => 27
1442 23:16:14.491298 DramcWriteLeveling(PI) end<-----
1443 23:16:14.491756
1444 23:16:14.492110 ==
1445 23:16:14.494426 Dram Type= 6, Freq= 0, CH_1, rank 0
1446 23:16:14.497974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1447 23:16:14.498534 ==
1448 23:16:14.501857 [Gating] SW mode calibration
1449 23:16:14.508445 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1450 23:16:14.511380 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1451 23:16:14.518134 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1452 23:16:14.521711 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 23:16:14.524495 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1454 23:16:14.531531 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 23:16:14.534569 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 23:16:14.538617 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 23:16:14.544495 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 23:16:14.547838 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 23:16:14.551129 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 23:16:14.558271 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 23:16:14.561363 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 23:16:14.564610 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 23:16:14.571502 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 23:16:14.575087 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 23:16:14.578417 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 23:16:14.581758 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 23:16:14.588175 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1468 23:16:14.591525 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1469 23:16:14.595345 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 23:16:14.601519 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 23:16:14.605373 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 23:16:14.608662 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 23:16:14.614870 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 23:16:14.618065 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 23:16:14.621824 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 23:16:14.628218 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1477 23:16:14.631537 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1478 23:16:14.634844 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 23:16:14.641270 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 23:16:14.644889 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 23:16:14.648013 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 23:16:14.654956 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 23:16:14.658305 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1484 23:16:14.661369 0 10 4 | B1->B0 | 3434 2e2e | 1 1 | (1 0) (1 0)
1485 23:16:14.664538 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)
1486 23:16:14.671580 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 23:16:14.674804 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 23:16:14.678404 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 23:16:14.684850 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 23:16:14.688934 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 23:16:14.691466 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 23:16:14.697892 0 11 4 | B1->B0 | 2a2a 3737 | 1 0 | (0 0) (1 1)
1493 23:16:14.701279 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1494 23:16:14.705057 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 23:16:14.711463 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 23:16:14.715215 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 23:16:14.717735 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 23:16:14.725114 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 23:16:14.728363 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1500 23:16:14.731460 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1501 23:16:14.738148 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 23:16:14.741733 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 23:16:14.744596 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 23:16:14.751206 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 23:16:14.754614 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 23:16:14.758010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 23:16:14.764728 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 23:16:14.768136 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 23:16:14.771371 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 23:16:14.774795 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 23:16:14.781321 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 23:16:14.785261 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 23:16:14.788128 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 23:16:14.794833 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 23:16:14.798205 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 23:16:14.801658 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1517 23:16:14.808443 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1518 23:16:14.812026 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 23:16:14.814846 Total UI for P1: 0, mck2ui 16
1520 23:16:14.818179 best dqsien dly found for B0: ( 0, 14, 6)
1521 23:16:14.821697 Total UI for P1: 0, mck2ui 16
1522 23:16:14.824977 best dqsien dly found for B1: ( 0, 14, 6)
1523 23:16:14.828624 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1524 23:16:14.831408 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1525 23:16:14.831869
1526 23:16:14.834994 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1527 23:16:14.838019 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1528 23:16:14.841280 [Gating] SW calibration Done
1529 23:16:14.841836 ==
1530 23:16:14.845175 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 23:16:14.848430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 23:16:14.848893 ==
1533 23:16:14.851699 RX Vref Scan: 0
1534 23:16:14.852153
1535 23:16:14.855142 RX Vref 0 -> 0, step: 1
1536 23:16:14.855607
1537 23:16:14.856009 RX Delay -130 -> 252, step: 16
1538 23:16:14.861703 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1539 23:16:14.864724 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1540 23:16:14.868825 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1541 23:16:14.872107 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1542 23:16:14.875223 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1543 23:16:14.881561 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1544 23:16:14.885029 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1545 23:16:14.888382 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1546 23:16:14.891728 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1547 23:16:14.894969 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1548 23:16:14.901462 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1549 23:16:14.904813 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1550 23:16:14.908219 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1551 23:16:14.911920 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1552 23:16:14.914970 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1553 23:16:14.921656 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1554 23:16:14.922219 ==
1555 23:16:14.924738 Dram Type= 6, Freq= 0, CH_1, rank 0
1556 23:16:14.928147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1557 23:16:14.928702 ==
1558 23:16:14.929064 DQS Delay:
1559 23:16:14.931524 DQS0 = 0, DQS1 = 0
1560 23:16:14.932114 DQM Delay:
1561 23:16:14.934711 DQM0 = 92, DQM1 = 89
1562 23:16:14.935166 DQ Delay:
1563 23:16:14.937770 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1564 23:16:14.941541 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1565 23:16:14.945056 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1566 23:16:14.948173 DQ12 =93, DQ13 =101, DQ14 =93, DQ15 =101
1567 23:16:14.948724
1568 23:16:14.949094
1569 23:16:14.949433 ==
1570 23:16:14.951519 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 23:16:14.955272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 23:16:14.958130 ==
1573 23:16:14.958587
1574 23:16:14.959018
1575 23:16:14.959549 TX Vref Scan disable
1576 23:16:14.961374 == TX Byte 0 ==
1577 23:16:14.965251 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1578 23:16:14.968237 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1579 23:16:14.971456 == TX Byte 1 ==
1580 23:16:14.974736 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1581 23:16:14.978282 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1582 23:16:14.978843 ==
1583 23:16:14.981527 Dram Type= 6, Freq= 0, CH_1, rank 0
1584 23:16:14.988496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1585 23:16:14.989057 ==
1586 23:16:14.999868 TX Vref=22, minBit 0, minWin=26, winSum=433
1587 23:16:15.003528 TX Vref=24, minBit 1, minWin=27, winSum=440
1588 23:16:15.006262 TX Vref=26, minBit 3, minWin=26, winSum=443
1589 23:16:15.009750 TX Vref=28, minBit 1, minWin=27, winSum=448
1590 23:16:15.013247 TX Vref=30, minBit 1, minWin=27, winSum=451
1591 23:16:15.020108 TX Vref=32, minBit 2, minWin=26, winSum=445
1592 23:16:15.023627 [TxChooseVref] Worse bit 1, Min win 27, Win sum 451, Final Vref 30
1593 23:16:15.024180
1594 23:16:15.026775 Final TX Range 1 Vref 30
1595 23:16:15.027326
1596 23:16:15.027694 ==
1597 23:16:15.030194 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 23:16:15.032849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 23:16:15.036427 ==
1600 23:16:15.036989
1601 23:16:15.037354
1602 23:16:15.037730 TX Vref Scan disable
1603 23:16:15.040178 == TX Byte 0 ==
1604 23:16:15.043228 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1605 23:16:15.047165 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1606 23:16:15.049908 == TX Byte 1 ==
1607 23:16:15.053179 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1608 23:16:15.056662 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1609 23:16:15.060146
1610 23:16:15.060599 [DATLAT]
1611 23:16:15.060961 Freq=800, CH1 RK0
1612 23:16:15.061296
1613 23:16:15.063859 DATLAT Default: 0xa
1614 23:16:15.064413 0, 0xFFFF, sum = 0
1615 23:16:15.066694 1, 0xFFFF, sum = 0
1616 23:16:15.067156 2, 0xFFFF, sum = 0
1617 23:16:15.070045 3, 0xFFFF, sum = 0
1618 23:16:15.070606 4, 0xFFFF, sum = 0
1619 23:16:15.073251 5, 0xFFFF, sum = 0
1620 23:16:15.073747 6, 0xFFFF, sum = 0
1621 23:16:15.076511 7, 0xFFFF, sum = 0
1622 23:16:15.080256 8, 0xFFFF, sum = 0
1623 23:16:15.080796 9, 0x0, sum = 1
1624 23:16:15.081186 10, 0x0, sum = 2
1625 23:16:15.083465 11, 0x0, sum = 3
1626 23:16:15.084046 12, 0x0, sum = 4
1627 23:16:15.086794 best_step = 10
1628 23:16:15.087251
1629 23:16:15.087608 ==
1630 23:16:15.089831 Dram Type= 6, Freq= 0, CH_1, rank 0
1631 23:16:15.093549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1632 23:16:15.093992 ==
1633 23:16:15.096773 RX Vref Scan: 1
1634 23:16:15.097187
1635 23:16:15.097515 Set Vref Range= 32 -> 127
1636 23:16:15.097854
1637 23:16:15.099824 RX Vref 32 -> 127, step: 1
1638 23:16:15.100234
1639 23:16:15.103625 RX Delay -79 -> 252, step: 8
1640 23:16:15.104189
1641 23:16:15.106626 Set Vref, RX VrefLevel [Byte0]: 32
1642 23:16:15.110011 [Byte1]: 32
1643 23:16:15.110584
1644 23:16:15.113325 Set Vref, RX VrefLevel [Byte0]: 33
1645 23:16:15.116326 [Byte1]: 33
1646 23:16:15.120275
1647 23:16:15.120787 Set Vref, RX VrefLevel [Byte0]: 34
1648 23:16:15.123514 [Byte1]: 34
1649 23:16:15.127881
1650 23:16:15.128442 Set Vref, RX VrefLevel [Byte0]: 35
1651 23:16:15.131063 [Byte1]: 35
1652 23:16:15.135166
1653 23:16:15.135579 Set Vref, RX VrefLevel [Byte0]: 36
1654 23:16:15.138231 [Byte1]: 36
1655 23:16:15.142727
1656 23:16:15.143140 Set Vref, RX VrefLevel [Byte0]: 37
1657 23:16:15.146422 [Byte1]: 37
1658 23:16:15.150659
1659 23:16:15.151186 Set Vref, RX VrefLevel [Byte0]: 38
1660 23:16:15.153229 [Byte1]: 38
1661 23:16:15.158033
1662 23:16:15.158550 Set Vref, RX VrefLevel [Byte0]: 39
1663 23:16:15.161211 [Byte1]: 39
1664 23:16:15.165478
1665 23:16:15.166041 Set Vref, RX VrefLevel [Byte0]: 40
1666 23:16:15.168357 [Byte1]: 40
1667 23:16:15.173153
1668 23:16:15.173694 Set Vref, RX VrefLevel [Byte0]: 41
1669 23:16:15.176733 [Byte1]: 41
1670 23:16:15.180864
1671 23:16:15.181406 Set Vref, RX VrefLevel [Byte0]: 42
1672 23:16:15.183983 [Byte1]: 42
1673 23:16:15.188056
1674 23:16:15.188575 Set Vref, RX VrefLevel [Byte0]: 43
1675 23:16:15.191157 [Byte1]: 43
1676 23:16:15.196133
1677 23:16:15.196684 Set Vref, RX VrefLevel [Byte0]: 44
1678 23:16:15.199260 [Byte1]: 44
1679 23:16:15.203409
1680 23:16:15.203920 Set Vref, RX VrefLevel [Byte0]: 45
1681 23:16:15.206777 [Byte1]: 45
1682 23:16:15.210808
1683 23:16:15.211355 Set Vref, RX VrefLevel [Byte0]: 46
1684 23:16:15.214401 [Byte1]: 46
1685 23:16:15.217939
1686 23:16:15.218377 Set Vref, RX VrefLevel [Byte0]: 47
1687 23:16:15.221666 [Byte1]: 47
1688 23:16:15.225641
1689 23:16:15.226055 Set Vref, RX VrefLevel [Byte0]: 48
1690 23:16:15.229099 [Byte1]: 48
1691 23:16:15.233555
1692 23:16:15.234173 Set Vref, RX VrefLevel [Byte0]: 49
1693 23:16:15.236979 [Byte1]: 49
1694 23:16:15.240574
1695 23:16:15.240986 Set Vref, RX VrefLevel [Byte0]: 50
1696 23:16:15.244134 [Byte1]: 50
1697 23:16:15.248605
1698 23:16:15.249017 Set Vref, RX VrefLevel [Byte0]: 51
1699 23:16:15.251827 [Byte1]: 51
1700 23:16:15.256014
1701 23:16:15.256549 Set Vref, RX VrefLevel [Byte0]: 52
1702 23:16:15.259210 [Byte1]: 52
1703 23:16:15.263346
1704 23:16:15.266757 Set Vref, RX VrefLevel [Byte0]: 53
1705 23:16:15.267175 [Byte1]: 53
1706 23:16:15.271313
1707 23:16:15.271823 Set Vref, RX VrefLevel [Byte0]: 54
1708 23:16:15.274152 [Byte1]: 54
1709 23:16:15.278821
1710 23:16:15.279335 Set Vref, RX VrefLevel [Byte0]: 55
1711 23:16:15.281951 [Byte1]: 55
1712 23:16:15.286370
1713 23:16:15.286878 Set Vref, RX VrefLevel [Byte0]: 56
1714 23:16:15.289755 [Byte1]: 56
1715 23:16:15.293874
1716 23:16:15.294399 Set Vref, RX VrefLevel [Byte0]: 57
1717 23:16:15.297281 [Byte1]: 57
1718 23:16:15.301696
1719 23:16:15.302214 Set Vref, RX VrefLevel [Byte0]: 58
1720 23:16:15.304478 [Byte1]: 58
1721 23:16:15.308948
1722 23:16:15.309381 Set Vref, RX VrefLevel [Byte0]: 59
1723 23:16:15.311791 [Byte1]: 59
1724 23:16:15.316434
1725 23:16:15.316947 Set Vref, RX VrefLevel [Byte0]: 60
1726 23:16:15.319713 [Byte1]: 60
1727 23:16:15.323808
1728 23:16:15.324339 Set Vref, RX VrefLevel [Byte0]: 61
1729 23:16:15.327845 [Byte1]: 61
1730 23:16:15.331690
1731 23:16:15.332248 Set Vref, RX VrefLevel [Byte0]: 62
1732 23:16:15.334784 [Byte1]: 62
1733 23:16:15.338646
1734 23:16:15.339083 Set Vref, RX VrefLevel [Byte0]: 63
1735 23:16:15.341898 [Byte1]: 63
1736 23:16:15.346359
1737 23:16:15.346770 Set Vref, RX VrefLevel [Byte0]: 64
1738 23:16:15.349537 [Byte1]: 64
1739 23:16:15.353920
1740 23:16:15.354338 Set Vref, RX VrefLevel [Byte0]: 65
1741 23:16:15.357458 [Byte1]: 65
1742 23:16:15.361682
1743 23:16:15.362213 Set Vref, RX VrefLevel [Byte0]: 66
1744 23:16:15.365022 [Byte1]: 66
1745 23:16:15.368963
1746 23:16:15.369373 Set Vref, RX VrefLevel [Byte0]: 67
1747 23:16:15.372624 [Byte1]: 67
1748 23:16:15.376614
1749 23:16:15.377126 Set Vref, RX VrefLevel [Byte0]: 68
1750 23:16:15.380078 [Byte1]: 68
1751 23:16:15.384239
1752 23:16:15.384757 Set Vref, RX VrefLevel [Byte0]: 69
1753 23:16:15.387354 [Byte1]: 69
1754 23:16:15.391661
1755 23:16:15.392073 Set Vref, RX VrefLevel [Byte0]: 70
1756 23:16:15.395335 [Byte1]: 70
1757 23:16:15.399695
1758 23:16:15.400209 Set Vref, RX VrefLevel [Byte0]: 71
1759 23:16:15.402537 [Byte1]: 71
1760 23:16:15.406673
1761 23:16:15.407089 Final RX Vref Byte 0 = 56 to rank0
1762 23:16:15.410142 Final RX Vref Byte 1 = 57 to rank0
1763 23:16:15.413464 Final RX Vref Byte 0 = 56 to rank1
1764 23:16:15.417663 Final RX Vref Byte 1 = 57 to rank1==
1765 23:16:15.420868 Dram Type= 6, Freq= 0, CH_1, rank 0
1766 23:16:15.427262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1767 23:16:15.427792 ==
1768 23:16:15.428132 DQS Delay:
1769 23:16:15.428435 DQS0 = 0, DQS1 = 0
1770 23:16:15.430209 DQM Delay:
1771 23:16:15.430622 DQM0 = 95, DQM1 = 89
1772 23:16:15.433763 DQ Delay:
1773 23:16:15.437110 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1774 23:16:15.437525 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1775 23:16:15.440596 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1776 23:16:15.443752 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1777 23:16:15.447242
1778 23:16:15.447653
1779 23:16:15.453492 [DQSOSCAuto] RK0, (LSB)MR18= 0x2945, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1780 23:16:15.457128 CH1 RK0: MR19=606, MR18=2945
1781 23:16:15.464170 CH1_RK0: MR19=0x606, MR18=0x2945, DQSOSC=392, MR23=63, INC=96, DEC=64
1782 23:16:15.464691
1783 23:16:15.467067 ----->DramcWriteLeveling(PI) begin...
1784 23:16:15.467488 ==
1785 23:16:15.470273 Dram Type= 6, Freq= 0, CH_1, rank 1
1786 23:16:15.473488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1787 23:16:15.473926 ==
1788 23:16:15.476937 Write leveling (Byte 0): 26 => 26
1789 23:16:15.480528 Write leveling (Byte 1): 30 => 30
1790 23:16:15.484463 DramcWriteLeveling(PI) end<-----
1791 23:16:15.484980
1792 23:16:15.485308 ==
1793 23:16:15.487417 Dram Type= 6, Freq= 0, CH_1, rank 1
1794 23:16:15.490644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1795 23:16:15.491166 ==
1796 23:16:15.493888 [Gating] SW mode calibration
1797 23:16:15.500796 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1798 23:16:15.507196 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1799 23:16:15.510695 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1800 23:16:15.514310 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1801 23:16:15.520759 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1802 23:16:15.523930 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1803 23:16:15.527616 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 23:16:15.533794 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 23:16:15.537238 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 23:16:15.540870 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 23:16:15.547394 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 23:16:15.550287 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 23:16:15.553991 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 23:16:15.557490 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 23:16:15.564269 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 23:16:15.566876 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 23:16:15.570626 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 23:16:15.577178 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 23:16:15.580925 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1816 23:16:15.583691 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 1)
1817 23:16:15.590658 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 23:16:15.593942 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 23:16:15.597364 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 23:16:15.603967 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 23:16:15.607430 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 23:16:15.610722 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 23:16:15.617676 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 23:16:15.621237 0 9 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1825 23:16:15.623721 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1826 23:16:15.630639 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1827 23:16:15.633819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1828 23:16:15.637048 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1829 23:16:15.640836 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 23:16:15.647341 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 23:16:15.650652 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1832 23:16:15.654056 0 10 4 | B1->B0 | 2e2e 2f2f | 0 1 | (0 0) (1 0)
1833 23:16:15.660784 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1834 23:16:15.664245 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 23:16:15.667519 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 23:16:15.674413 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 23:16:15.677710 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 23:16:15.681401 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 23:16:15.687763 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1840 23:16:15.690723 0 11 4 | B1->B0 | 3b3b 3030 | 0 0 | (0 0) (0 0)
1841 23:16:15.694458 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1842 23:16:15.701161 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1843 23:16:15.704248 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1844 23:16:15.707700 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 23:16:15.714049 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 23:16:15.717535 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 23:16:15.721007 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1848 23:16:15.724156 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1849 23:16:15.730935 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1850 23:16:15.734070 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1851 23:16:15.737431 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 23:16:15.744348 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 23:16:15.747551 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 23:16:15.750694 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 23:16:15.757555 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 23:16:15.760938 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 23:16:15.764054 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 23:16:15.771323 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 23:16:15.774335 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 23:16:15.777658 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 23:16:15.784254 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 23:16:15.787861 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 23:16:15.791054 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1864 23:16:15.797952 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1865 23:16:15.798515 Total UI for P1: 0, mck2ui 16
1866 23:16:15.800779 best dqsien dly found for B1: ( 0, 14, 0)
1867 23:16:15.807831 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1868 23:16:15.810793 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 23:16:15.814729 Total UI for P1: 0, mck2ui 16
1870 23:16:15.817409 best dqsien dly found for B0: ( 0, 14, 6)
1871 23:16:15.820744 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1872 23:16:15.824226 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1873 23:16:15.824777
1874 23:16:15.827329 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1875 23:16:15.830923 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1876 23:16:15.834065 [Gating] SW calibration Done
1877 23:16:15.834626 ==
1878 23:16:15.837533 Dram Type= 6, Freq= 0, CH_1, rank 1
1879 23:16:15.844083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1880 23:16:15.844544 ==
1881 23:16:15.844971 RX Vref Scan: 0
1882 23:16:15.845324
1883 23:16:15.847335 RX Vref 0 -> 0, step: 1
1884 23:16:15.847897
1885 23:16:15.850620 RX Delay -130 -> 252, step: 16
1886 23:16:15.854062 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1887 23:16:15.857659 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1888 23:16:15.861181 iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208
1889 23:16:15.867467 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1890 23:16:15.870798 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1891 23:16:15.873995 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1892 23:16:15.877160 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1893 23:16:15.880685 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1894 23:16:15.884276 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1895 23:16:15.890806 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1896 23:16:15.894194 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1897 23:16:15.897636 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1898 23:16:15.901196 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1899 23:16:15.903970 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1900 23:16:15.910726 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1901 23:16:15.914407 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1902 23:16:15.914964 ==
1903 23:16:15.917285 Dram Type= 6, Freq= 0, CH_1, rank 1
1904 23:16:15.920829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1905 23:16:15.921289 ==
1906 23:16:15.924378 DQS Delay:
1907 23:16:15.924928 DQS0 = 0, DQS1 = 0
1908 23:16:15.925295 DQM Delay:
1909 23:16:15.927760 DQM0 = 94, DQM1 = 91
1910 23:16:15.928311 DQ Delay:
1911 23:16:15.931003 DQ0 =101, DQ1 =85, DQ2 =85, DQ3 =85
1912 23:16:15.933897 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1913 23:16:15.937751 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1914 23:16:15.940805 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1915 23:16:15.941267
1916 23:16:15.941677
1917 23:16:15.944265 ==
1918 23:16:15.944820 Dram Type= 6, Freq= 0, CH_1, rank 1
1919 23:16:15.951098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1920 23:16:15.951587 ==
1921 23:16:15.951957
1922 23:16:15.952290
1923 23:16:15.952610 TX Vref Scan disable
1924 23:16:15.954485 == TX Byte 0 ==
1925 23:16:15.958512 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1926 23:16:15.961655 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1927 23:16:15.964892 == TX Byte 1 ==
1928 23:16:15.967995 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1929 23:16:15.971463 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1930 23:16:15.974966 ==
1931 23:16:15.977946 Dram Type= 6, Freq= 0, CH_1, rank 1
1932 23:16:15.981712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1933 23:16:15.982267 ==
1934 23:16:15.994202 TX Vref=22, minBit 1, minWin=26, winSum=443
1935 23:16:15.997433 TX Vref=24, minBit 0, minWin=27, winSum=445
1936 23:16:16.001116 TX Vref=26, minBit 0, minWin=27, winSum=446
1937 23:16:16.004193 TX Vref=28, minBit 1, minWin=27, winSum=450
1938 23:16:16.007554 TX Vref=30, minBit 2, minWin=27, winSum=449
1939 23:16:16.010945 TX Vref=32, minBit 1, minWin=27, winSum=447
1940 23:16:16.017642 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1941 23:16:16.018191
1942 23:16:16.020585 Final TX Range 1 Vref 28
1943 23:16:16.021043
1944 23:16:16.021401 ==
1945 23:16:16.024134 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 23:16:16.027793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 23:16:16.028351 ==
1948 23:16:16.028718
1949 23:16:16.029051
1950 23:16:16.031012 TX Vref Scan disable
1951 23:16:16.034135 == TX Byte 0 ==
1952 23:16:16.037443 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1953 23:16:16.041051 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1954 23:16:16.044272 == TX Byte 1 ==
1955 23:16:16.047868 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1956 23:16:16.050971 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1957 23:16:16.051427
1958 23:16:16.054089 [DATLAT]
1959 23:16:16.054569 Freq=800, CH1 RK1
1960 23:16:16.054933
1961 23:16:16.058178 DATLAT Default: 0xa
1962 23:16:16.058740 0, 0xFFFF, sum = 0
1963 23:16:16.060929 1, 0xFFFF, sum = 0
1964 23:16:16.061497 2, 0xFFFF, sum = 0
1965 23:16:16.064567 3, 0xFFFF, sum = 0
1966 23:16:16.065135 4, 0xFFFF, sum = 0
1967 23:16:16.067885 5, 0xFFFF, sum = 0
1968 23:16:16.068459 6, 0xFFFF, sum = 0
1969 23:16:16.071436 7, 0xFFFF, sum = 0
1970 23:16:16.072000 8, 0xFFFF, sum = 0
1971 23:16:16.074633 9, 0x0, sum = 1
1972 23:16:16.075095 10, 0x0, sum = 2
1973 23:16:16.078228 11, 0x0, sum = 3
1974 23:16:16.078792 12, 0x0, sum = 4
1975 23:16:16.081255 best_step = 10
1976 23:16:16.081745
1977 23:16:16.082106 ==
1978 23:16:16.083995 Dram Type= 6, Freq= 0, CH_1, rank 1
1979 23:16:16.087752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1980 23:16:16.088211 ==
1981 23:16:16.090656 RX Vref Scan: 0
1982 23:16:16.091112
1983 23:16:16.091473 RX Vref 0 -> 0, step: 1
1984 23:16:16.091810
1985 23:16:16.094179 RX Delay -79 -> 252, step: 8
1986 23:16:16.101212 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
1987 23:16:16.104262 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
1988 23:16:16.107988 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
1989 23:16:16.111350 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
1990 23:16:16.114570 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
1991 23:16:16.117391 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
1992 23:16:16.123985 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
1993 23:16:16.127711 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
1994 23:16:16.131009 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
1995 23:16:16.133778 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
1996 23:16:16.137473 iDelay=209, Bit 10, Center 92 (-7 ~ 192) 200
1997 23:16:16.143768 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
1998 23:16:16.147254 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
1999 23:16:16.150381 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2000 23:16:16.153999 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2001 23:16:16.157855 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2002 23:16:16.158509 ==
2003 23:16:16.161008 Dram Type= 6, Freq= 0, CH_1, rank 1
2004 23:16:16.167446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2005 23:16:16.168004 ==
2006 23:16:16.168372 DQS Delay:
2007 23:16:16.171214 DQS0 = 0, DQS1 = 0
2008 23:16:16.171772 DQM Delay:
2009 23:16:16.172139 DQM0 = 97, DQM1 = 90
2010 23:16:16.173843 DQ Delay:
2011 23:16:16.177468 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2012 23:16:16.180864 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2013 23:16:16.184656 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2014 23:16:16.187539 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2015 23:16:16.187998
2016 23:16:16.188359
2017 23:16:16.194122 [DQSOSCAuto] RK1, (LSB)MR18= 0x410b, (MSB)MR19= 0x606, tDQSOscB0 = 407 ps tDQSOscB1 = 393 ps
2018 23:16:16.197382 CH1 RK1: MR19=606, MR18=410B
2019 23:16:16.204445 CH1_RK1: MR19=0x606, MR18=0x410B, DQSOSC=393, MR23=63, INC=95, DEC=63
2020 23:16:16.207965 [RxdqsGatingPostProcess] freq 800
2021 23:16:16.211200 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2022 23:16:16.214041 Pre-setting of DQS Precalculation
2023 23:16:16.220689 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2024 23:16:16.227742 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2025 23:16:16.234399 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2026 23:16:16.234951
2027 23:16:16.235314
2028 23:16:16.237329 [Calibration Summary] 1600 Mbps
2029 23:16:16.237811 CH 0, Rank 0
2030 23:16:16.240849 SW Impedance : PASS
2031 23:16:16.244300 DUTY Scan : NO K
2032 23:16:16.244755 ZQ Calibration : PASS
2033 23:16:16.247816 Jitter Meter : NO K
2034 23:16:16.250725 CBT Training : PASS
2035 23:16:16.251180 Write leveling : PASS
2036 23:16:16.254198 RX DQS gating : PASS
2037 23:16:16.258068 RX DQ/DQS(RDDQC) : PASS
2038 23:16:16.258573 TX DQ/DQS : PASS
2039 23:16:16.261017 RX DATLAT : PASS
2040 23:16:16.261609 RX DQ/DQS(Engine): PASS
2041 23:16:16.264566 TX OE : NO K
2042 23:16:16.265022 All Pass.
2043 23:16:16.265380
2044 23:16:16.268153 CH 0, Rank 1
2045 23:16:16.268719 SW Impedance : PASS
2046 23:16:16.271231 DUTY Scan : NO K
2047 23:16:16.274554 ZQ Calibration : PASS
2048 23:16:16.275010 Jitter Meter : NO K
2049 23:16:16.278172 CBT Training : PASS
2050 23:16:16.281043 Write leveling : PASS
2051 23:16:16.281501 RX DQS gating : PASS
2052 23:16:16.284601 RX DQ/DQS(RDDQC) : PASS
2053 23:16:16.287891 TX DQ/DQS : PASS
2054 23:16:16.288453 RX DATLAT : PASS
2055 23:16:16.291041 RX DQ/DQS(Engine): PASS
2056 23:16:16.294211 TX OE : NO K
2057 23:16:16.294666 All Pass.
2058 23:16:16.295027
2059 23:16:16.295355 CH 1, Rank 0
2060 23:16:16.298038 SW Impedance : PASS
2061 23:16:16.300954 DUTY Scan : NO K
2062 23:16:16.301409 ZQ Calibration : PASS
2063 23:16:16.304405 Jitter Meter : NO K
2064 23:16:16.307736 CBT Training : PASS
2065 23:16:16.308290 Write leveling : PASS
2066 23:16:16.311483 RX DQS gating : PASS
2067 23:16:16.312043 RX DQ/DQS(RDDQC) : PASS
2068 23:16:16.314122 TX DQ/DQS : PASS
2069 23:16:16.317379 RX DATLAT : PASS
2070 23:16:16.317868 RX DQ/DQS(Engine): PASS
2071 23:16:16.321281 TX OE : NO K
2072 23:16:16.321905 All Pass.
2073 23:16:16.322274
2074 23:16:16.324303 CH 1, Rank 1
2075 23:16:16.324755 SW Impedance : PASS
2076 23:16:16.327949 DUTY Scan : NO K
2077 23:16:16.330952 ZQ Calibration : PASS
2078 23:16:16.331512 Jitter Meter : NO K
2079 23:16:16.334071 CBT Training : PASS
2080 23:16:16.337769 Write leveling : PASS
2081 23:16:16.338328 RX DQS gating : PASS
2082 23:16:16.341175 RX DQ/DQS(RDDQC) : PASS
2083 23:16:16.344399 TX DQ/DQS : PASS
2084 23:16:16.344956 RX DATLAT : PASS
2085 23:16:16.347865 RX DQ/DQS(Engine): PASS
2086 23:16:16.351696 TX OE : NO K
2087 23:16:16.352285 All Pass.
2088 23:16:16.352652
2089 23:16:16.352991 DramC Write-DBI off
2090 23:16:16.354032 PER_BANK_REFRESH: Hybrid Mode
2091 23:16:16.357295 TX_TRACKING: ON
2092 23:16:16.361183 [GetDramInforAfterCalByMRR] Vendor 6.
2093 23:16:16.364216 [GetDramInforAfterCalByMRR] Revision 606.
2094 23:16:16.367673 [GetDramInforAfterCalByMRR] Revision 2 0.
2095 23:16:16.368226 MR0 0x3b3b
2096 23:16:16.370675 MR8 0x5151
2097 23:16:16.374033 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2098 23:16:16.374493
2099 23:16:16.374854 MR0 0x3b3b
2100 23:16:16.375189 MR8 0x5151
2101 23:16:16.377425 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 23:16:16.377913
2103 23:16:16.387554 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2104 23:16:16.390855 [FAST_K] Save calibration result to emmc
2105 23:16:16.394415 [FAST_K] Save calibration result to emmc
2106 23:16:16.397443 dram_init: config_dvfs: 1
2107 23:16:16.400803 dramc_set_vcore_voltage set vcore to 662500
2108 23:16:16.404234 Read voltage for 1200, 2
2109 23:16:16.404692 Vio18 = 0
2110 23:16:16.407925 Vcore = 662500
2111 23:16:16.408477 Vdram = 0
2112 23:16:16.408842 Vddq = 0
2113 23:16:16.409179 Vmddr = 0
2114 23:16:16.414839 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2115 23:16:16.417435 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2116 23:16:16.421245 MEM_TYPE=3, freq_sel=15
2117 23:16:16.424673 sv_algorithm_assistance_LP4_1600
2118 23:16:16.427750 ============ PULL DRAM RESETB DOWN ============
2119 23:16:16.431360 ========== PULL DRAM RESETB DOWN end =========
2120 23:16:16.438114 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2121 23:16:16.441376 ===================================
2122 23:16:16.444677 LPDDR4 DRAM CONFIGURATION
2123 23:16:16.447903 ===================================
2124 23:16:16.448468 EX_ROW_EN[0] = 0x0
2125 23:16:16.450893 EX_ROW_EN[1] = 0x0
2126 23:16:16.451348 LP4Y_EN = 0x0
2127 23:16:16.454180 WORK_FSP = 0x0
2128 23:16:16.454634 WL = 0x4
2129 23:16:16.457839 RL = 0x4
2130 23:16:16.458294 BL = 0x2
2131 23:16:16.460862 RPST = 0x0
2132 23:16:16.461315 RD_PRE = 0x0
2133 23:16:16.464555 WR_PRE = 0x1
2134 23:16:16.465013 WR_PST = 0x0
2135 23:16:16.467683 DBI_WR = 0x0
2136 23:16:16.468137 DBI_RD = 0x0
2137 23:16:16.471095 OTF = 0x1
2138 23:16:16.474223 ===================================
2139 23:16:16.477728 ===================================
2140 23:16:16.478144 ANA top config
2141 23:16:16.481336 ===================================
2142 23:16:16.484490 DLL_ASYNC_EN = 0
2143 23:16:16.487891 ALL_SLAVE_EN = 0
2144 23:16:16.491707 NEW_RANK_MODE = 1
2145 23:16:16.492125 DLL_IDLE_MODE = 1
2146 23:16:16.494250 LP45_APHY_COMB_EN = 1
2147 23:16:16.497660 TX_ODT_DIS = 1
2148 23:16:16.501406 NEW_8X_MODE = 1
2149 23:16:16.504360 ===================================
2150 23:16:16.507940 ===================================
2151 23:16:16.512082 data_rate = 2400
2152 23:16:16.512648 CKR = 1
2153 23:16:16.514767 DQ_P2S_RATIO = 8
2154 23:16:16.518304 ===================================
2155 23:16:16.521536 CA_P2S_RATIO = 8
2156 23:16:16.525055 DQ_CA_OPEN = 0
2157 23:16:16.528449 DQ_SEMI_OPEN = 0
2158 23:16:16.529009 CA_SEMI_OPEN = 0
2159 23:16:16.531413 CA_FULL_RATE = 0
2160 23:16:16.534702 DQ_CKDIV4_EN = 0
2161 23:16:16.538268 CA_CKDIV4_EN = 0
2162 23:16:16.541467 CA_PREDIV_EN = 0
2163 23:16:16.544766 PH8_DLY = 17
2164 23:16:16.545333 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2165 23:16:16.548437 DQ_AAMCK_DIV = 4
2166 23:16:16.551292 CA_AAMCK_DIV = 4
2167 23:16:16.554648 CA_ADMCK_DIV = 4
2168 23:16:16.558300 DQ_TRACK_CA_EN = 0
2169 23:16:16.561688 CA_PICK = 1200
2170 23:16:16.564889 CA_MCKIO = 1200
2171 23:16:16.565345 MCKIO_SEMI = 0
2172 23:16:16.568048 PLL_FREQ = 2366
2173 23:16:16.571531 DQ_UI_PI_RATIO = 32
2174 23:16:16.574919 CA_UI_PI_RATIO = 0
2175 23:16:16.577996 ===================================
2176 23:16:16.581315 ===================================
2177 23:16:16.585114 memory_type:LPDDR4
2178 23:16:16.585716 GP_NUM : 10
2179 23:16:16.588385 SRAM_EN : 1
2180 23:16:16.588955 MD32_EN : 0
2181 23:16:16.591251 ===================================
2182 23:16:16.594839 [ANA_INIT] >>>>>>>>>>>>>>
2183 23:16:16.598095 <<<<<< [CONFIGURE PHASE]: ANA_TX
2184 23:16:16.601408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2185 23:16:16.604943 ===================================
2186 23:16:16.608769 data_rate = 2400,PCW = 0X5b00
2187 23:16:16.611759 ===================================
2188 23:16:16.615004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2189 23:16:16.618313 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2190 23:16:16.625148 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2191 23:16:16.628267 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2192 23:16:16.635233 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2193 23:16:16.638344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2194 23:16:16.638802 [ANA_INIT] flow start
2195 23:16:16.641824 [ANA_INIT] PLL >>>>>>>>
2196 23:16:16.644670 [ANA_INIT] PLL <<<<<<<<
2197 23:16:16.645122 [ANA_INIT] MIDPI >>>>>>>>
2198 23:16:16.648373 [ANA_INIT] MIDPI <<<<<<<<
2199 23:16:16.651616 [ANA_INIT] DLL >>>>>>>>
2200 23:16:16.652072 [ANA_INIT] DLL <<<<<<<<
2201 23:16:16.654987 [ANA_INIT] flow end
2202 23:16:16.658002 ============ LP4 DIFF to SE enter ============
2203 23:16:16.661981 ============ LP4 DIFF to SE exit ============
2204 23:16:16.665399 [ANA_INIT] <<<<<<<<<<<<<
2205 23:16:16.668112 [Flow] Enable top DCM control >>>>>
2206 23:16:16.671960 [Flow] Enable top DCM control <<<<<
2207 23:16:16.674850 Enable DLL master slave shuffle
2208 23:16:16.681811 ==============================================================
2209 23:16:16.682373 Gating Mode config
2210 23:16:16.687951 ==============================================================
2211 23:16:16.688500 Config description:
2212 23:16:16.698429 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2213 23:16:16.705279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2214 23:16:16.711945 SELPH_MODE 0: By rank 1: By Phase
2215 23:16:16.714872 ==============================================================
2216 23:16:16.718524 GAT_TRACK_EN = 1
2217 23:16:16.721531 RX_GATING_MODE = 2
2218 23:16:16.724997 RX_GATING_TRACK_MODE = 2
2219 23:16:16.728076 SELPH_MODE = 1
2220 23:16:16.731755 PICG_EARLY_EN = 1
2221 23:16:16.735175 VALID_LAT_VALUE = 1
2222 23:16:16.738073 ==============================================================
2223 23:16:16.741572 Enter into Gating configuration >>>>
2224 23:16:16.744690 Exit from Gating configuration <<<<
2225 23:16:16.749114 Enter into DVFS_PRE_config >>>>>
2226 23:16:16.762221 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2227 23:16:16.764538 Exit from DVFS_PRE_config <<<<<
2228 23:16:16.768227 Enter into PICG configuration >>>>
2229 23:16:16.771845 Exit from PICG configuration <<<<
2230 23:16:16.772400 [RX_INPUT] configuration >>>>>
2231 23:16:16.774558 [RX_INPUT] configuration <<<<<
2232 23:16:16.781249 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2233 23:16:16.784964 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2234 23:16:16.791546 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2235 23:16:16.797995 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2236 23:16:16.804975 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 23:16:16.812094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 23:16:16.815338 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2239 23:16:16.818620 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2240 23:16:16.821977 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2241 23:16:16.828325 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2242 23:16:16.831788 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2243 23:16:16.834855 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2244 23:16:16.838294 ===================================
2245 23:16:16.841748 LPDDR4 DRAM CONFIGURATION
2246 23:16:16.845167 ===================================
2247 23:16:16.848103 EX_ROW_EN[0] = 0x0
2248 23:16:16.848580 EX_ROW_EN[1] = 0x0
2249 23:16:16.851328 LP4Y_EN = 0x0
2250 23:16:16.851783 WORK_FSP = 0x0
2251 23:16:16.854606 WL = 0x4
2252 23:16:16.855056 RL = 0x4
2253 23:16:16.857991 BL = 0x2
2254 23:16:16.858444 RPST = 0x0
2255 23:16:16.861501 RD_PRE = 0x0
2256 23:16:16.861990 WR_PRE = 0x1
2257 23:16:16.864943 WR_PST = 0x0
2258 23:16:16.865394 DBI_WR = 0x0
2259 23:16:16.868315 DBI_RD = 0x0
2260 23:16:16.868768 OTF = 0x1
2261 23:16:16.871594 ===================================
2262 23:16:16.874635 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2263 23:16:16.881274 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2264 23:16:16.884712 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2265 23:16:16.888066 ===================================
2266 23:16:16.891411 LPDDR4 DRAM CONFIGURATION
2267 23:16:16.894828 ===================================
2268 23:16:16.895287 EX_ROW_EN[0] = 0x10
2269 23:16:16.898552 EX_ROW_EN[1] = 0x0
2270 23:16:16.901851 LP4Y_EN = 0x0
2271 23:16:16.902396 WORK_FSP = 0x0
2272 23:16:16.904576 WL = 0x4
2273 23:16:16.905031 RL = 0x4
2274 23:16:16.908068 BL = 0x2
2275 23:16:16.908618 RPST = 0x0
2276 23:16:16.911628 RD_PRE = 0x0
2277 23:16:16.912179 WR_PRE = 0x1
2278 23:16:16.915204 WR_PST = 0x0
2279 23:16:16.915805 DBI_WR = 0x0
2280 23:16:16.918083 DBI_RD = 0x0
2281 23:16:16.918542 OTF = 0x1
2282 23:16:16.921525 ===================================
2283 23:16:16.927769 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2284 23:16:16.928308 ==
2285 23:16:16.931496 Dram Type= 6, Freq= 0, CH_0, rank 0
2286 23:16:16.934641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2287 23:16:16.935214 ==
2288 23:16:16.938155 [Duty_Offset_Calibration]
2289 23:16:16.941163 B0:2 B1:1 CA:1
2290 23:16:16.941646
2291 23:16:16.944531 [DutyScan_Calibration_Flow] k_type=0
2292 23:16:16.952546
2293 23:16:16.952996 ==CLK 0==
2294 23:16:16.955845 Final CLK duty delay cell = 0
2295 23:16:16.959209 [0] MAX Duty = 5187%(X100), DQS PI = 24
2296 23:16:16.962785 [0] MIN Duty = 4875%(X100), DQS PI = 0
2297 23:16:16.963234 [0] AVG Duty = 5031%(X100)
2298 23:16:16.966346
2299 23:16:16.966753 CH0 CLK Duty spec in!! Max-Min= 312%
2300 23:16:16.972487 [DutyScan_Calibration_Flow] ====Done====
2301 23:16:16.972878
2302 23:16:16.975530 [DutyScan_Calibration_Flow] k_type=1
2303 23:16:16.991165
2304 23:16:16.991551 ==DQS 0 ==
2305 23:16:16.994573 Final DQS duty delay cell = -4
2306 23:16:16.997801 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2307 23:16:17.001911 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2308 23:16:17.004923 [-4] AVG Duty = 4953%(X100)
2309 23:16:17.005299
2310 23:16:17.005617 ==DQS 1 ==
2311 23:16:17.007889 Final DQS duty delay cell = 0
2312 23:16:17.011148 [0] MAX Duty = 5156%(X100), DQS PI = 0
2313 23:16:17.014671 [0] MIN Duty = 5000%(X100), DQS PI = 32
2314 23:16:17.018045 [0] AVG Duty = 5078%(X100)
2315 23:16:17.018604
2316 23:16:17.021278 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2317 23:16:17.021866
2318 23:16:17.024903 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2319 23:16:17.027884 [DutyScan_Calibration_Flow] ====Done====
2320 23:16:17.028353
2321 23:16:17.031124 [DutyScan_Calibration_Flow] k_type=3
2322 23:16:17.048202
2323 23:16:17.048747 ==DQM 0 ==
2324 23:16:17.051082 Final DQM duty delay cell = 0
2325 23:16:17.054805 [0] MAX Duty = 5156%(X100), DQS PI = 30
2326 23:16:17.058199 [0] MIN Duty = 4938%(X100), DQS PI = 0
2327 23:16:17.058648 [0] AVG Duty = 5047%(X100)
2328 23:16:17.061893
2329 23:16:17.062447 ==DQM 1 ==
2330 23:16:17.065239 Final DQM duty delay cell = 0
2331 23:16:17.068320 [0] MAX Duty = 5093%(X100), DQS PI = 0
2332 23:16:17.071599 [0] MIN Duty = 5031%(X100), DQS PI = 16
2333 23:16:17.072181 [0] AVG Duty = 5062%(X100)
2334 23:16:17.072540
2335 23:16:17.077923 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2336 23:16:17.078380
2337 23:16:17.081753 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2338 23:16:17.084827 [DutyScan_Calibration_Flow] ====Done====
2339 23:16:17.085380
2340 23:16:17.087703 [DutyScan_Calibration_Flow] k_type=2
2341 23:16:17.104391
2342 23:16:17.104951 ==DQ 0 ==
2343 23:16:17.107798 Final DQ duty delay cell = 0
2344 23:16:17.110975 [0] MAX Duty = 5031%(X100), DQS PI = 26
2345 23:16:17.114454 [0] MIN Duty = 4875%(X100), DQS PI = 62
2346 23:16:17.115007 [0] AVG Duty = 4953%(X100)
2347 23:16:17.117993
2348 23:16:17.118548 ==DQ 1 ==
2349 23:16:17.120606 Final DQ duty delay cell = 0
2350 23:16:17.124670 [0] MAX Duty = 5093%(X100), DQS PI = 10
2351 23:16:17.127887 [0] MIN Duty = 4938%(X100), DQS PI = 36
2352 23:16:17.128445 [0] AVG Duty = 5015%(X100)
2353 23:16:17.128806
2354 23:16:17.131072 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2355 23:16:17.134355
2356 23:16:17.137826 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2357 23:16:17.141051 [DutyScan_Calibration_Flow] ====Done====
2358 23:16:17.141662 ==
2359 23:16:17.144305 Dram Type= 6, Freq= 0, CH_1, rank 0
2360 23:16:17.147860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2361 23:16:17.148317 ==
2362 23:16:17.150949 [Duty_Offset_Calibration]
2363 23:16:17.151400 B0:1 B1:0 CA:0
2364 23:16:17.151753
2365 23:16:17.154285 [DutyScan_Calibration_Flow] k_type=0
2366 23:16:17.163942
2367 23:16:17.164501 ==CLK 0==
2368 23:16:17.166805 Final CLK duty delay cell = -4
2369 23:16:17.170160 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2370 23:16:17.173342 [-4] MIN Duty = 4875%(X100), DQS PI = 52
2371 23:16:17.176661 [-4] AVG Duty = 4953%(X100)
2372 23:16:17.177112
2373 23:16:17.179985 CH1 CLK Duty spec in!! Max-Min= 156%
2374 23:16:17.183311 [DutyScan_Calibration_Flow] ====Done====
2375 23:16:17.183764
2376 23:16:17.187061 [DutyScan_Calibration_Flow] k_type=1
2377 23:16:17.203546
2378 23:16:17.204117 ==DQS 0 ==
2379 23:16:17.207070 Final DQS duty delay cell = 0
2380 23:16:17.210183 [0] MAX Duty = 5094%(X100), DQS PI = 24
2381 23:16:17.213869 [0] MIN Duty = 4875%(X100), DQS PI = 0
2382 23:16:17.214422 [0] AVG Duty = 4984%(X100)
2383 23:16:17.214779
2384 23:16:17.216790 ==DQS 1 ==
2385 23:16:17.220906 Final DQS duty delay cell = 0
2386 23:16:17.223896 [0] MAX Duty = 5187%(X100), DQS PI = 18
2387 23:16:17.226614 [0] MIN Duty = 4969%(X100), DQS PI = 8
2388 23:16:17.227069 [0] AVG Duty = 5078%(X100)
2389 23:16:17.227426
2390 23:16:17.230543 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2391 23:16:17.233606
2392 23:16:17.236880 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2393 23:16:17.240457 [DutyScan_Calibration_Flow] ====Done====
2394 23:16:17.241012
2395 23:16:17.243659 [DutyScan_Calibration_Flow] k_type=3
2396 23:16:17.259918
2397 23:16:17.260500 ==DQM 0 ==
2398 23:16:17.263324 Final DQM duty delay cell = 0
2399 23:16:17.266609 [0] MAX Duty = 5156%(X100), DQS PI = 6
2400 23:16:17.270241 [0] MIN Duty = 5031%(X100), DQS PI = 0
2401 23:16:17.270699 [0] AVG Duty = 5093%(X100)
2402 23:16:17.271060
2403 23:16:17.273233 ==DQM 1 ==
2404 23:16:17.276759 Final DQM duty delay cell = 0
2405 23:16:17.280087 [0] MAX Duty = 5031%(X100), DQS PI = 16
2406 23:16:17.283078 [0] MIN Duty = 4907%(X100), DQS PI = 34
2407 23:16:17.283533 [0] AVG Duty = 4969%(X100)
2408 23:16:17.283894
2409 23:16:17.289870 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2410 23:16:17.290430
2411 23:16:17.293302 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2412 23:16:17.296468 [DutyScan_Calibration_Flow] ====Done====
2413 23:16:17.296920
2414 23:16:17.300128 [DutyScan_Calibration_Flow] k_type=2
2415 23:16:17.315915
2416 23:16:17.316515 ==DQ 0 ==
2417 23:16:17.319203 Final DQ duty delay cell = -4
2418 23:16:17.322452 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2419 23:16:17.325749 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2420 23:16:17.326317 [-4] AVG Duty = 5000%(X100)
2421 23:16:17.328921
2422 23:16:17.329372 ==DQ 1 ==
2423 23:16:17.332258 Final DQ duty delay cell = 0
2424 23:16:17.335813 [0] MAX Duty = 5125%(X100), DQS PI = 20
2425 23:16:17.339277 [0] MIN Duty = 4969%(X100), DQS PI = 12
2426 23:16:17.339837 [0] AVG Duty = 5047%(X100)
2427 23:16:17.340199
2428 23:16:17.342753 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2429 23:16:17.346152
2430 23:16:17.349207 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2431 23:16:17.352582 [DutyScan_Calibration_Flow] ====Done====
2432 23:16:17.355369 nWR fixed to 30
2433 23:16:17.355828 [ModeRegInit_LP4] CH0 RK0
2434 23:16:17.358950 [ModeRegInit_LP4] CH0 RK1
2435 23:16:17.362149 [ModeRegInit_LP4] CH1 RK0
2436 23:16:17.362606 [ModeRegInit_LP4] CH1 RK1
2437 23:16:17.365761 match AC timing 7
2438 23:16:17.369105 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2439 23:16:17.372356 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2440 23:16:17.379463 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2441 23:16:17.382844 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2442 23:16:17.389107 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2443 23:16:17.389716 ==
2444 23:16:17.392304 Dram Type= 6, Freq= 0, CH_0, rank 0
2445 23:16:17.395607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2446 23:16:17.396149 ==
2447 23:16:17.402222 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2448 23:16:17.406063 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2449 23:16:17.415948 [CA 0] Center 39 (8~70) winsize 63
2450 23:16:17.419594 [CA 1] Center 39 (8~70) winsize 63
2451 23:16:17.422942 [CA 2] Center 35 (5~66) winsize 62
2452 23:16:17.425822 [CA 3] Center 34 (4~65) winsize 62
2453 23:16:17.429447 [CA 4] Center 33 (3~64) winsize 62
2454 23:16:17.432430 [CA 5] Center 32 (3~62) winsize 60
2455 23:16:17.432985
2456 23:16:17.436015 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2457 23:16:17.436578
2458 23:16:17.439392 [CATrainingPosCal] consider 1 rank data
2459 23:16:17.442939 u2DelayCellTimex100 = 270/100 ps
2460 23:16:17.446215 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2461 23:16:17.449053 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2462 23:16:17.455474 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2463 23:16:17.459026 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2464 23:16:17.462390 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2465 23:16:17.466211 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2466 23:16:17.466827
2467 23:16:17.469173 CA PerBit enable=1, Macro0, CA PI delay=32
2468 23:16:17.469777
2469 23:16:17.472926 [CBTSetCACLKResult] CA Dly = 32
2470 23:16:17.473485 CS Dly: 6 (0~37)
2471 23:16:17.473897 ==
2472 23:16:17.475961 Dram Type= 6, Freq= 0, CH_0, rank 1
2473 23:16:17.482592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2474 23:16:17.483098 ==
2475 23:16:17.485903 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2476 23:16:17.492361 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2477 23:16:17.501478 [CA 0] Center 38 (8~69) winsize 62
2478 23:16:17.504702 [CA 1] Center 38 (8~69) winsize 62
2479 23:16:17.507868 [CA 2] Center 35 (4~66) winsize 63
2480 23:16:17.511155 [CA 3] Center 34 (4~65) winsize 62
2481 23:16:17.515062 [CA 4] Center 33 (3~64) winsize 62
2482 23:16:17.518107 [CA 5] Center 32 (3~62) winsize 60
2483 23:16:17.518558
2484 23:16:17.521489 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2485 23:16:17.521995
2486 23:16:17.524825 [CATrainingPosCal] consider 2 rank data
2487 23:16:17.528141 u2DelayCellTimex100 = 270/100 ps
2488 23:16:17.531892 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2489 23:16:17.534599 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2490 23:16:17.541711 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2491 23:16:17.545183 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2492 23:16:17.548516 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2493 23:16:17.551504 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2494 23:16:17.551960
2495 23:16:17.554794 CA PerBit enable=1, Macro0, CA PI delay=32
2496 23:16:17.555250
2497 23:16:17.558461 [CBTSetCACLKResult] CA Dly = 32
2498 23:16:17.558916 CS Dly: 6 (0~38)
2499 23:16:17.559275
2500 23:16:17.561550 ----->DramcWriteLeveling(PI) begin...
2501 23:16:17.562061 ==
2502 23:16:17.565141 Dram Type= 6, Freq= 0, CH_0, rank 0
2503 23:16:17.571510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2504 23:16:17.571970 ==
2505 23:16:17.575501 Write leveling (Byte 0): 33 => 33
2506 23:16:17.578337 Write leveling (Byte 1): 28 => 28
2507 23:16:17.578886 DramcWriteLeveling(PI) end<-----
2508 23:16:17.581881
2509 23:16:17.582426 ==
2510 23:16:17.584863 Dram Type= 6, Freq= 0, CH_0, rank 0
2511 23:16:17.588209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2512 23:16:17.588763 ==
2513 23:16:17.592340 [Gating] SW mode calibration
2514 23:16:17.598636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2515 23:16:17.601713 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2516 23:16:17.608668 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2517 23:16:17.611842 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2518 23:16:17.615201 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2519 23:16:17.621928 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2520 23:16:17.625050 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 23:16:17.628359 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 23:16:17.635288 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 23:16:17.638324 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2524 23:16:17.641967 1 0 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
2525 23:16:17.648320 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2526 23:16:17.651380 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2527 23:16:17.654805 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2528 23:16:17.661619 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 23:16:17.664989 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 23:16:17.668366 1 0 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)
2531 23:16:17.671355 1 0 28 | B1->B0 | 2a2a 4545 | 0 0 | (0 0) (0 0)
2532 23:16:17.678474 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
2533 23:16:17.681924 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2534 23:16:17.685502 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2535 23:16:17.692337 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2536 23:16:17.695426 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 23:16:17.698290 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 23:16:17.705012 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2539 23:16:17.708480 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2540 23:16:17.711857 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2541 23:16:17.718502 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2542 23:16:17.721731 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2543 23:16:17.724878 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2544 23:16:17.732091 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 23:16:17.735504 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 23:16:17.738484 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 23:16:17.745675 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 23:16:17.748900 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 23:16:17.752359 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 23:16:17.755581 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 23:16:17.761642 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 23:16:17.765440 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 23:16:17.768658 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 23:16:17.775499 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 23:16:17.778704 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2556 23:16:17.781956 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2557 23:16:17.785236 Total UI for P1: 0, mck2ui 16
2558 23:16:17.788371 best dqsien dly found for B0: ( 1, 3, 28)
2559 23:16:17.795494 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 23:16:17.796041 Total UI for P1: 0, mck2ui 16
2561 23:16:17.801998 best dqsien dly found for B1: ( 1, 4, 0)
2562 23:16:17.805549 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2563 23:16:17.808747 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2564 23:16:17.809313
2565 23:16:17.812624 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2566 23:16:17.815708 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2567 23:16:17.818554 [Gating] SW calibration Done
2568 23:16:17.819019 ==
2569 23:16:17.822281 Dram Type= 6, Freq= 0, CH_0, rank 0
2570 23:16:17.825486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2571 23:16:17.826087 ==
2572 23:16:17.829086 RX Vref Scan: 0
2573 23:16:17.829702
2574 23:16:17.830076 RX Vref 0 -> 0, step: 1
2575 23:16:17.830420
2576 23:16:17.832233 RX Delay -40 -> 252, step: 8
2577 23:16:17.835533 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2578 23:16:17.841814 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2579 23:16:17.845536 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2580 23:16:17.848729 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2581 23:16:17.852333 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2582 23:16:17.855358 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2583 23:16:17.858579 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2584 23:16:17.865465 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2585 23:16:17.868865 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2586 23:16:17.872298 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2587 23:16:17.875841 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2588 23:16:17.878750 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2589 23:16:17.885109 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2590 23:16:17.888958 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2591 23:16:17.892001 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2592 23:16:17.895539 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2593 23:16:17.896002 ==
2594 23:16:17.898575 Dram Type= 6, Freq= 0, CH_0, rank 0
2595 23:16:17.905252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2596 23:16:17.905754 ==
2597 23:16:17.906126 DQS Delay:
2598 23:16:17.908839 DQS0 = 0, DQS1 = 0
2599 23:16:17.909404 DQM Delay:
2600 23:16:17.909823 DQM0 = 121, DQM1 = 113
2601 23:16:17.912552 DQ Delay:
2602 23:16:17.915467 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2603 23:16:17.918328 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2604 23:16:17.922454 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2605 23:16:17.925828 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2606 23:16:17.926386
2607 23:16:17.926756
2608 23:16:17.927092 ==
2609 23:16:17.929210 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 23:16:17.932920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 23:16:17.935803 ==
2612 23:16:17.936373
2613 23:16:17.936742
2614 23:16:17.937081 TX Vref Scan disable
2615 23:16:17.938487 == TX Byte 0 ==
2616 23:16:17.942010 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2617 23:16:17.945563 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2618 23:16:17.948906 == TX Byte 1 ==
2619 23:16:17.951813 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2620 23:16:17.955235 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2621 23:16:17.955691 ==
2622 23:16:17.959006 Dram Type= 6, Freq= 0, CH_0, rank 0
2623 23:16:17.965018 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2624 23:16:17.965480 ==
2625 23:16:17.976871 TX Vref=22, minBit 0, minWin=24, winSum=404
2626 23:16:17.979891 TX Vref=24, minBit 0, minWin=25, winSum=412
2627 23:16:17.983602 TX Vref=26, minBit 4, minWin=25, winSum=417
2628 23:16:17.986253 TX Vref=28, minBit 13, minWin=25, winSum=421
2629 23:16:17.989650 TX Vref=30, minBit 0, minWin=26, winSum=422
2630 23:16:17.996323 TX Vref=32, minBit 10, minWin=25, winSum=420
2631 23:16:17.999938 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 30
2632 23:16:18.000499
2633 23:16:18.003613 Final TX Range 1 Vref 30
2634 23:16:18.004259
2635 23:16:18.004635 ==
2636 23:16:18.006597 Dram Type= 6, Freq= 0, CH_0, rank 0
2637 23:16:18.009905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2638 23:16:18.010366 ==
2639 23:16:18.010729
2640 23:16:18.013369
2641 23:16:18.013965 TX Vref Scan disable
2642 23:16:18.016806 == TX Byte 0 ==
2643 23:16:18.019837 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2644 23:16:18.023183 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2645 23:16:18.026748 == TX Byte 1 ==
2646 23:16:18.029739 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2647 23:16:18.033177 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2648 23:16:18.033836
2649 23:16:18.036828 [DATLAT]
2650 23:16:18.037375 Freq=1200, CH0 RK0
2651 23:16:18.037795
2652 23:16:18.040408 DATLAT Default: 0xd
2653 23:16:18.040960 0, 0xFFFF, sum = 0
2654 23:16:18.043641 1, 0xFFFF, sum = 0
2655 23:16:18.044197 2, 0xFFFF, sum = 0
2656 23:16:18.046547 3, 0xFFFF, sum = 0
2657 23:16:18.047007 4, 0xFFFF, sum = 0
2658 23:16:18.050005 5, 0xFFFF, sum = 0
2659 23:16:18.050792 6, 0xFFFF, sum = 0
2660 23:16:18.053347 7, 0xFFFF, sum = 0
2661 23:16:18.053979 8, 0xFFFF, sum = 0
2662 23:16:18.056628 9, 0xFFFF, sum = 0
2663 23:16:18.059879 10, 0xFFFF, sum = 0
2664 23:16:18.060323 11, 0xFFFF, sum = 0
2665 23:16:18.063396 12, 0x0, sum = 1
2666 23:16:18.063862 13, 0x0, sum = 2
2667 23:16:18.064232 14, 0x0, sum = 3
2668 23:16:18.066382 15, 0x0, sum = 4
2669 23:16:18.066845 best_step = 13
2670 23:16:18.067210
2671 23:16:18.069805 ==
2672 23:16:18.070266 Dram Type= 6, Freq= 0, CH_0, rank 0
2673 23:16:18.076725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2674 23:16:18.077292 ==
2675 23:16:18.077729 RX Vref Scan: 1
2676 23:16:18.078088
2677 23:16:18.079801 Set Vref Range= 32 -> 127
2678 23:16:18.080366
2679 23:16:18.083102 RX Vref 32 -> 127, step: 1
2680 23:16:18.083623
2681 23:16:18.086357 RX Delay -13 -> 252, step: 4
2682 23:16:18.086817
2683 23:16:18.089967 Set Vref, RX VrefLevel [Byte0]: 32
2684 23:16:18.093386 [Byte1]: 32
2685 23:16:18.093988
2686 23:16:18.096385 Set Vref, RX VrefLevel [Byte0]: 33
2687 23:16:18.100333 [Byte1]: 33
2688 23:16:18.100916
2689 23:16:18.103153 Set Vref, RX VrefLevel [Byte0]: 34
2690 23:16:18.106162 [Byte1]: 34
2691 23:16:18.110616
2692 23:16:18.111181 Set Vref, RX VrefLevel [Byte0]: 35
2693 23:16:18.113757 [Byte1]: 35
2694 23:16:18.118874
2695 23:16:18.119580 Set Vref, RX VrefLevel [Byte0]: 36
2696 23:16:18.121977 [Byte1]: 36
2697 23:16:18.126307
2698 23:16:18.126863 Set Vref, RX VrefLevel [Byte0]: 37
2699 23:16:18.129811 [Byte1]: 37
2700 23:16:18.134055
2701 23:16:18.134517 Set Vref, RX VrefLevel [Byte0]: 38
2702 23:16:18.137984 [Byte1]: 38
2703 23:16:18.142225
2704 23:16:18.142785 Set Vref, RX VrefLevel [Byte0]: 39
2705 23:16:18.145760 [Byte1]: 39
2706 23:16:18.149987
2707 23:16:18.150668 Set Vref, RX VrefLevel [Byte0]: 40
2708 23:16:18.153378 [Byte1]: 40
2709 23:16:18.157815
2710 23:16:18.158437 Set Vref, RX VrefLevel [Byte0]: 41
2711 23:16:18.164107 [Byte1]: 41
2712 23:16:18.164647
2713 23:16:18.167965 Set Vref, RX VrefLevel [Byte0]: 42
2714 23:16:18.171532 [Byte1]: 42
2715 23:16:18.171991
2716 23:16:18.174835 Set Vref, RX VrefLevel [Byte0]: 43
2717 23:16:18.177935 [Byte1]: 43
2718 23:16:18.181449
2719 23:16:18.181942 Set Vref, RX VrefLevel [Byte0]: 44
2720 23:16:18.185213 [Byte1]: 44
2721 23:16:18.189709
2722 23:16:18.190272 Set Vref, RX VrefLevel [Byte0]: 45
2723 23:16:18.193091 [Byte1]: 45
2724 23:16:18.197796
2725 23:16:18.198378 Set Vref, RX VrefLevel [Byte0]: 46
2726 23:16:18.200966 [Byte1]: 46
2727 23:16:18.205079
2728 23:16:18.205540 Set Vref, RX VrefLevel [Byte0]: 47
2729 23:16:18.208342 [Byte1]: 47
2730 23:16:18.213750
2731 23:16:18.214329 Set Vref, RX VrefLevel [Byte0]: 48
2732 23:16:18.216377 [Byte1]: 48
2733 23:16:18.221275
2734 23:16:18.221895 Set Vref, RX VrefLevel [Byte0]: 49
2735 23:16:18.224425 [Byte1]: 49
2736 23:16:18.229087
2737 23:16:18.229545 Set Vref, RX VrefLevel [Byte0]: 50
2738 23:16:18.232177 [Byte1]: 50
2739 23:16:18.237312
2740 23:16:18.237935 Set Vref, RX VrefLevel [Byte0]: 51
2741 23:16:18.240071 [Byte1]: 51
2742 23:16:18.244906
2743 23:16:18.245484 Set Vref, RX VrefLevel [Byte0]: 52
2744 23:16:18.248336 [Byte1]: 52
2745 23:16:18.252167
2746 23:16:18.252629 Set Vref, RX VrefLevel [Byte0]: 53
2747 23:16:18.256575 [Byte1]: 53
2748 23:16:18.260524
2749 23:16:18.260986 Set Vref, RX VrefLevel [Byte0]: 54
2750 23:16:18.264021 [Byte1]: 54
2751 23:16:18.268565
2752 23:16:18.269118 Set Vref, RX VrefLevel [Byte0]: 55
2753 23:16:18.271897 [Byte1]: 55
2754 23:16:18.276388
2755 23:16:18.276973 Set Vref, RX VrefLevel [Byte0]: 56
2756 23:16:18.279589 [Byte1]: 56
2757 23:16:18.284470
2758 23:16:18.285033 Set Vref, RX VrefLevel [Byte0]: 57
2759 23:16:18.287440 [Byte1]: 57
2760 23:16:18.292771
2761 23:16:18.293338 Set Vref, RX VrefLevel [Byte0]: 58
2762 23:16:18.295837 [Byte1]: 58
2763 23:16:18.300320
2764 23:16:18.300881 Set Vref, RX VrefLevel [Byte0]: 59
2765 23:16:18.303065 [Byte1]: 59
2766 23:16:18.307833
2767 23:16:18.308409 Set Vref, RX VrefLevel [Byte0]: 60
2768 23:16:18.311454 [Byte1]: 60
2769 23:16:18.316057
2770 23:16:18.316627 Set Vref, RX VrefLevel [Byte0]: 61
2771 23:16:18.319118 [Byte1]: 61
2772 23:16:18.324188
2773 23:16:18.324766 Set Vref, RX VrefLevel [Byte0]: 62
2774 23:16:18.327519 [Byte1]: 62
2775 23:16:18.331823
2776 23:16:18.332481 Set Vref, RX VrefLevel [Byte0]: 63
2777 23:16:18.335098 [Byte1]: 63
2778 23:16:18.339526
2779 23:16:18.340091 Set Vref, RX VrefLevel [Byte0]: 64
2780 23:16:18.342792 [Byte1]: 64
2781 23:16:18.347334
2782 23:16:18.347909 Set Vref, RX VrefLevel [Byte0]: 65
2783 23:16:18.350716 [Byte1]: 65
2784 23:16:18.355447
2785 23:16:18.355909 Set Vref, RX VrefLevel [Byte0]: 66
2786 23:16:18.358204 [Byte1]: 66
2787 23:16:18.362773
2788 23:16:18.363248 Set Vref, RX VrefLevel [Byte0]: 67
2789 23:16:18.366772 [Byte1]: 67
2790 23:16:18.370800
2791 23:16:18.371397 Set Vref, RX VrefLevel [Byte0]: 68
2792 23:16:18.374069 [Byte1]: 68
2793 23:16:18.378856
2794 23:16:18.379361 Final RX Vref Byte 0 = 57 to rank0
2795 23:16:18.382137 Final RX Vref Byte 1 = 49 to rank0
2796 23:16:18.385750 Final RX Vref Byte 0 = 57 to rank1
2797 23:16:18.389031 Final RX Vref Byte 1 = 49 to rank1==
2798 23:16:18.392413 Dram Type= 6, Freq= 0, CH_0, rank 0
2799 23:16:18.398833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2800 23:16:18.399567 ==
2801 23:16:18.399956 DQS Delay:
2802 23:16:18.400298 DQS0 = 0, DQS1 = 0
2803 23:16:18.402579 DQM Delay:
2804 23:16:18.403054 DQM0 = 120, DQM1 = 112
2805 23:16:18.405541 DQ Delay:
2806 23:16:18.409163 DQ0 =118, DQ1 =120, DQ2 =120, DQ3 =118
2807 23:16:18.412928 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2808 23:16:18.416172 DQ8 =100, DQ9 =100, DQ10 =112, DQ11 =106
2809 23:16:18.418900 DQ12 =118, DQ13 =116, DQ14 =124, DQ15 =122
2810 23:16:18.419363
2811 23:16:18.419728
2812 23:16:18.425838 [DQSOSCAuto] RK0, (LSB)MR18= 0x130c, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
2813 23:16:18.428985 CH0 RK0: MR19=404, MR18=130C
2814 23:16:18.435601 CH0_RK0: MR19=0x404, MR18=0x130C, DQSOSC=402, MR23=63, INC=40, DEC=27
2815 23:16:18.436168
2816 23:16:18.439141 ----->DramcWriteLeveling(PI) begin...
2817 23:16:18.439790 ==
2818 23:16:18.442324 Dram Type= 6, Freq= 0, CH_0, rank 1
2819 23:16:18.445900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 23:16:18.449245 ==
2821 23:16:18.449846 Write leveling (Byte 0): 36 => 36
2822 23:16:18.452500 Write leveling (Byte 1): 30 => 30
2823 23:16:18.455512 DramcWriteLeveling(PI) end<-----
2824 23:16:18.455982
2825 23:16:18.456348 ==
2826 23:16:18.458781 Dram Type= 6, Freq= 0, CH_0, rank 1
2827 23:16:18.465518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2828 23:16:18.466135 ==
2829 23:16:18.468640 [Gating] SW mode calibration
2830 23:16:18.475540 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2831 23:16:18.478810 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2832 23:16:18.485541 0 15 0 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)
2833 23:16:18.489000 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2834 23:16:18.492570 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2835 23:16:18.495732 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2836 23:16:18.502136 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2837 23:16:18.505544 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2838 23:16:18.508850 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2839 23:16:18.515558 0 15 28 | B1->B0 | 3232 2c2c | 1 0 | (0 1) (0 0)
2840 23:16:18.518674 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2841 23:16:18.522093 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2842 23:16:18.528601 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2843 23:16:18.531993 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2844 23:16:18.535351 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2845 23:16:18.541922 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2846 23:16:18.545340 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2847 23:16:18.549067 1 0 28 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (1 1)
2848 23:16:18.555153 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2849 23:16:18.558515 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2850 23:16:18.562067 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2851 23:16:18.569068 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2852 23:16:18.572108 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2853 23:16:18.575685 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2854 23:16:18.581995 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 23:16:18.585755 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2856 23:16:18.589191 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2857 23:16:18.592296 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2858 23:16:18.599104 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2859 23:16:18.602534 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2860 23:16:18.605908 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2861 23:16:18.612146 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2862 23:16:18.615902 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 23:16:18.618757 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 23:16:18.625456 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 23:16:18.629092 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 23:16:18.632420 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 23:16:18.638936 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 23:16:18.642441 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 23:16:18.646072 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 23:16:18.652342 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 23:16:18.655452 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2872 23:16:18.659336 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2873 23:16:18.665741 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 23:16:18.666300 Total UI for P1: 0, mck2ui 16
2875 23:16:18.668680 best dqsien dly found for B0: ( 1, 3, 30)
2876 23:16:18.672406 Total UI for P1: 0, mck2ui 16
2877 23:16:18.675522 best dqsien dly found for B1: ( 1, 3, 30)
2878 23:16:18.678721 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2879 23:16:18.685824 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2880 23:16:18.686372
2881 23:16:18.689277 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2882 23:16:18.692070 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2883 23:16:18.695795 [Gating] SW calibration Done
2884 23:16:18.696366 ==
2885 23:16:18.698419 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 23:16:18.702048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 23:16:18.702605 ==
2888 23:16:18.705190 RX Vref Scan: 0
2889 23:16:18.705739
2890 23:16:18.706134 RX Vref 0 -> 0, step: 1
2891 23:16:18.706483
2892 23:16:18.708776 RX Delay -40 -> 252, step: 8
2893 23:16:18.711578 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2894 23:16:18.715475 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2895 23:16:18.721602 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2896 23:16:18.725115 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2897 23:16:18.728203 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2898 23:16:18.731728 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2899 23:16:18.735279 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2900 23:16:18.741625 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2901 23:16:18.744956 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2902 23:16:18.748286 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2903 23:16:18.751650 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2904 23:16:18.754720 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2905 23:16:18.761455 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2906 23:16:18.765005 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2907 23:16:18.768602 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2908 23:16:18.771611 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2909 23:16:18.771768 ==
2910 23:16:18.774884 Dram Type= 6, Freq= 0, CH_0, rank 1
2911 23:16:18.782093 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2912 23:16:18.782261 ==
2913 23:16:18.782404 DQS Delay:
2914 23:16:18.784734 DQS0 = 0, DQS1 = 0
2915 23:16:18.784892 DQM Delay:
2916 23:16:18.785017 DQM0 = 122, DQM1 = 113
2917 23:16:18.788031 DQ Delay:
2918 23:16:18.791728 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2919 23:16:18.794684 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2920 23:16:18.797921 DQ8 =103, DQ9 =103, DQ10 =111, DQ11 =107
2921 23:16:18.801308 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2922 23:16:18.801466
2923 23:16:18.801604
2924 23:16:18.801721 ==
2925 23:16:18.804611 Dram Type= 6, Freq= 0, CH_0, rank 1
2926 23:16:18.808101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2927 23:16:18.811415 ==
2928 23:16:18.811575
2929 23:16:18.811699
2930 23:16:18.811814 TX Vref Scan disable
2931 23:16:18.814957 == TX Byte 0 ==
2932 23:16:18.818217 Update DQ dly =856 (3 ,2, 24) DQ OEN =(2 ,7)
2933 23:16:18.821587 Update DQM dly =856 (3 ,2, 24) DQM OEN =(2 ,7)
2934 23:16:18.825108 == TX Byte 1 ==
2935 23:16:18.828515 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2936 23:16:18.831828 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2937 23:16:18.834752 ==
2938 23:16:18.834999 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 23:16:18.841169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 23:16:18.841343 ==
2941 23:16:18.852889 TX Vref=22, minBit 5, minWin=24, winSum=410
2942 23:16:18.856790 TX Vref=24, minBit 10, minWin=25, winSum=417
2943 23:16:18.860018 TX Vref=26, minBit 4, minWin=26, winSum=427
2944 23:16:18.863468 TX Vref=28, minBit 12, minWin=25, winSum=425
2945 23:16:18.866142 TX Vref=30, minBit 3, minWin=26, winSum=425
2946 23:16:18.873348 TX Vref=32, minBit 10, minWin=25, winSum=424
2947 23:16:18.876104 [TxChooseVref] Worse bit 4, Min win 26, Win sum 427, Final Vref 26
2948 23:16:18.876262
2949 23:16:18.879483 Final TX Range 1 Vref 26
2950 23:16:18.879639
2951 23:16:18.879762 ==
2952 23:16:18.882812 Dram Type= 6, Freq= 0, CH_0, rank 1
2953 23:16:18.886126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2954 23:16:18.889551 ==
2955 23:16:18.889797
2956 23:16:18.889963
2957 23:16:18.890117 TX Vref Scan disable
2958 23:16:18.893032 == TX Byte 0 ==
2959 23:16:18.896595 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2960 23:16:18.899769 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2961 23:16:18.903159 == TX Byte 1 ==
2962 23:16:18.906352 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2963 23:16:18.909551 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2964 23:16:18.912958
2965 23:16:18.913209 [DATLAT]
2966 23:16:18.913409 Freq=1200, CH0 RK1
2967 23:16:18.913626
2968 23:16:18.916577 DATLAT Default: 0xd
2969 23:16:18.916829 0, 0xFFFF, sum = 0
2970 23:16:18.919825 1, 0xFFFF, sum = 0
2971 23:16:18.920081 2, 0xFFFF, sum = 0
2972 23:16:18.923107 3, 0xFFFF, sum = 0
2973 23:16:18.923362 4, 0xFFFF, sum = 0
2974 23:16:18.926338 5, 0xFFFF, sum = 0
2975 23:16:18.926595 6, 0xFFFF, sum = 0
2976 23:16:18.930156 7, 0xFFFF, sum = 0
2977 23:16:18.930358 8, 0xFFFF, sum = 0
2978 23:16:18.933050 9, 0xFFFF, sum = 0
2979 23:16:18.936366 10, 0xFFFF, sum = 0
2980 23:16:18.936533 11, 0xFFFF, sum = 0
2981 23:16:18.939858 12, 0x0, sum = 1
2982 23:16:18.940017 13, 0x0, sum = 2
2983 23:16:18.940186 14, 0x0, sum = 3
2984 23:16:18.943161 15, 0x0, sum = 4
2985 23:16:18.943285 best_step = 13
2986 23:16:18.943381
2987 23:16:18.946357 ==
2988 23:16:18.946479 Dram Type= 6, Freq= 0, CH_0, rank 1
2989 23:16:18.952835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2990 23:16:18.952940 ==
2991 23:16:18.953018 RX Vref Scan: 0
2992 23:16:18.953089
2993 23:16:18.956324 RX Vref 0 -> 0, step: 1
2994 23:16:18.956423
2995 23:16:18.959836 RX Delay -13 -> 252, step: 4
2996 23:16:18.963221 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
2997 23:16:18.966828 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
2998 23:16:18.973049 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
2999 23:16:18.976528 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3000 23:16:18.979883 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3001 23:16:18.983280 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3002 23:16:18.986908 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3003 23:16:18.993366 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3004 23:16:18.996377 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3005 23:16:18.999775 iDelay=195, Bit 9, Center 98 (35 ~ 162) 128
3006 23:16:19.003220 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3007 23:16:19.006883 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3008 23:16:19.013566 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3009 23:16:19.016399 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3010 23:16:19.019736 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3011 23:16:19.023630 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3012 23:16:19.023712 ==
3013 23:16:19.027031 Dram Type= 6, Freq= 0, CH_0, rank 1
3014 23:16:19.033054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3015 23:16:19.033142 ==
3016 23:16:19.033212 DQS Delay:
3017 23:16:19.033275 DQS0 = 0, DQS1 = 0
3018 23:16:19.036449 DQM Delay:
3019 23:16:19.036536 DQM0 = 120, DQM1 = 110
3020 23:16:19.039820 DQ Delay:
3021 23:16:19.043302 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
3022 23:16:19.046794 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3023 23:16:19.049991 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3024 23:16:19.053234 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3025 23:16:19.053327
3026 23:16:19.053401
3027 23:16:19.059901 [DQSOSCAuto] RK1, (LSB)MR18= 0xfef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 404 ps
3028 23:16:19.063538 CH0 RK1: MR19=403, MR18=FEF
3029 23:16:19.070005 CH0_RK1: MR19=0x403, MR18=0xFEF, DQSOSC=404, MR23=63, INC=40, DEC=26
3030 23:16:19.073174 [RxdqsGatingPostProcess] freq 1200
3031 23:16:19.080275 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3032 23:16:19.080386 best DQS0 dly(2T, 0.5T) = (0, 11)
3033 23:16:19.083874 best DQS1 dly(2T, 0.5T) = (0, 12)
3034 23:16:19.087069 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3035 23:16:19.090605 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3036 23:16:19.094059 best DQS0 dly(2T, 0.5T) = (0, 11)
3037 23:16:19.097235 best DQS1 dly(2T, 0.5T) = (0, 11)
3038 23:16:19.100566 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3039 23:16:19.103545 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3040 23:16:19.106844 Pre-setting of DQS Precalculation
3041 23:16:19.110241 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3042 23:16:19.110377 ==
3043 23:16:19.113847 Dram Type= 6, Freq= 0, CH_1, rank 0
3044 23:16:19.120416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3045 23:16:19.120569 ==
3046 23:16:19.123539 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3047 23:16:19.130045 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3048 23:16:19.139439 [CA 0] Center 37 (7~67) winsize 61
3049 23:16:19.142514 [CA 1] Center 37 (7~68) winsize 62
3050 23:16:19.146160 [CA 2] Center 35 (5~65) winsize 61
3051 23:16:19.149696 [CA 3] Center 34 (4~65) winsize 62
3052 23:16:19.153428 [CA 4] Center 34 (4~64) winsize 61
3053 23:16:19.156212 [CA 5] Center 33 (3~63) winsize 61
3054 23:16:19.156655
3055 23:16:19.159710 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3056 23:16:19.160130
3057 23:16:19.163054 [CATrainingPosCal] consider 1 rank data
3058 23:16:19.166497 u2DelayCellTimex100 = 270/100 ps
3059 23:16:19.169784 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3060 23:16:19.173108 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3061 23:16:19.176306 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3062 23:16:19.182848 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3063 23:16:19.186060 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3064 23:16:19.189464 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3065 23:16:19.189820
3066 23:16:19.193014 CA PerBit enable=1, Macro0, CA PI delay=33
3067 23:16:19.193240
3068 23:16:19.196061 [CBTSetCACLKResult] CA Dly = 33
3069 23:16:19.196286 CS Dly: 7 (0~38)
3070 23:16:19.196463 ==
3071 23:16:19.199405 Dram Type= 6, Freq= 0, CH_1, rank 1
3072 23:16:19.206073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 23:16:19.206230 ==
3074 23:16:19.209515 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3075 23:16:19.215681 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3076 23:16:19.224776 [CA 0] Center 37 (7~68) winsize 62
3077 23:16:19.227987 [CA 1] Center 37 (7~68) winsize 62
3078 23:16:19.231351 [CA 2] Center 35 (5~65) winsize 61
3079 23:16:19.234777 [CA 3] Center 34 (4~65) winsize 62
3080 23:16:19.238708 [CA 4] Center 34 (4~65) winsize 62
3081 23:16:19.241438 [CA 5] Center 34 (4~64) winsize 61
3082 23:16:19.241545
3083 23:16:19.244802 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3084 23:16:19.244883
3085 23:16:19.248967 [CATrainingPosCal] consider 2 rank data
3086 23:16:19.252007 u2DelayCellTimex100 = 270/100 ps
3087 23:16:19.254987 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3088 23:16:19.258694 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3089 23:16:19.261982 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3090 23:16:19.269034 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3091 23:16:19.272173 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3092 23:16:19.275251 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3093 23:16:19.275666
3094 23:16:19.278424 CA PerBit enable=1, Macro0, CA PI delay=33
3095 23:16:19.278836
3096 23:16:19.282073 [CBTSetCACLKResult] CA Dly = 33
3097 23:16:19.282485 CS Dly: 8 (0~41)
3098 23:16:19.282816
3099 23:16:19.285198 ----->DramcWriteLeveling(PI) begin...
3100 23:16:19.288574 ==
3101 23:16:19.288984 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 23:16:19.295315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 23:16:19.295728 ==
3104 23:16:19.298477 Write leveling (Byte 0): 28 => 28
3105 23:16:19.302119 Write leveling (Byte 1): 28 => 28
3106 23:16:19.302532 DramcWriteLeveling(PI) end<-----
3107 23:16:19.305320
3108 23:16:19.305777 ==
3109 23:16:19.308389 Dram Type= 6, Freq= 0, CH_1, rank 0
3110 23:16:19.312195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3111 23:16:19.312610 ==
3112 23:16:19.315339 [Gating] SW mode calibration
3113 23:16:19.321888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3114 23:16:19.325016 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3115 23:16:19.331520 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3116 23:16:19.335066 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3117 23:16:19.338478 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3118 23:16:19.345418 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3119 23:16:19.348574 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3120 23:16:19.351957 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3121 23:16:19.358427 0 15 24 | B1->B0 | 3131 2c2c | 0 1 | (0 0) (1 1)
3122 23:16:19.362148 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
3123 23:16:19.364988 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3124 23:16:19.371522 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3125 23:16:19.375344 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3126 23:16:19.378824 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3127 23:16:19.381695 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3128 23:16:19.388694 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3129 23:16:19.392708 1 0 24 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)
3130 23:16:19.395452 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3131 23:16:19.402259 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3132 23:16:19.405415 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3133 23:16:19.409078 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3134 23:16:19.415538 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3135 23:16:19.418804 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3136 23:16:19.422028 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 23:16:19.429208 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3138 23:16:19.432206 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3139 23:16:19.435747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3140 23:16:19.442122 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3141 23:16:19.445818 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3142 23:16:19.448822 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3143 23:16:19.455393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3144 23:16:19.458779 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 23:16:19.462155 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 23:16:19.465323 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 23:16:19.472062 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 23:16:19.475296 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 23:16:19.478942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 23:16:19.485851 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 23:16:19.489169 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 23:16:19.492101 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 23:16:19.499027 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3154 23:16:19.502405 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3155 23:16:19.505875 Total UI for P1: 0, mck2ui 16
3156 23:16:19.508848 best dqsien dly found for B1: ( 1, 3, 24)
3157 23:16:19.512035 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 23:16:19.515420 Total UI for P1: 0, mck2ui 16
3159 23:16:19.518583 best dqsien dly found for B0: ( 1, 3, 26)
3160 23:16:19.522070 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3161 23:16:19.525348 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3162 23:16:19.525454
3163 23:16:19.532467 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3164 23:16:19.535592 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3165 23:16:19.535731 [Gating] SW calibration Done
3166 23:16:19.538792 ==
3167 23:16:19.542216 Dram Type= 6, Freq= 0, CH_1, rank 0
3168 23:16:19.545165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3169 23:16:19.545312 ==
3170 23:16:19.545401 RX Vref Scan: 0
3171 23:16:19.545471
3172 23:16:19.548369 RX Vref 0 -> 0, step: 1
3173 23:16:19.548456
3174 23:16:19.552040 RX Delay -40 -> 252, step: 8
3175 23:16:19.555126 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3176 23:16:19.558283 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3177 23:16:19.564971 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3178 23:16:19.568372 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3179 23:16:19.571557 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3180 23:16:19.575185 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3181 23:16:19.578362 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3182 23:16:19.581679 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3183 23:16:19.588587 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3184 23:16:19.592160 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3185 23:16:19.595384 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3186 23:16:19.598730 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3187 23:16:19.605419 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3188 23:16:19.609126 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3189 23:16:19.611823 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3190 23:16:19.615500 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3191 23:16:19.616023 ==
3192 23:16:19.618786 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 23:16:19.622188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 23:16:19.625952 ==
3195 23:16:19.626475 DQS Delay:
3196 23:16:19.626835 DQS0 = 0, DQS1 = 0
3197 23:16:19.628555 DQM Delay:
3198 23:16:19.629010 DQM0 = 120, DQM1 = 117
3199 23:16:19.631731 DQ Delay:
3200 23:16:19.635363 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3201 23:16:19.638847 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3202 23:16:19.642243 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3203 23:16:19.645427 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3204 23:16:19.646141
3205 23:16:19.646750
3206 23:16:19.647328 ==
3207 23:16:19.648562 Dram Type= 6, Freq= 0, CH_1, rank 0
3208 23:16:19.652104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3209 23:16:19.652564 ==
3210 23:16:19.652927
3211 23:16:19.655310
3212 23:16:19.655764 TX Vref Scan disable
3213 23:16:19.658320 == TX Byte 0 ==
3214 23:16:19.661743 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3215 23:16:19.665233 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3216 23:16:19.668765 == TX Byte 1 ==
3217 23:16:19.672420 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3218 23:16:19.675346 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3219 23:16:19.675804 ==
3220 23:16:19.679038 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 23:16:19.684864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 23:16:19.685407 ==
3223 23:16:19.695453 TX Vref=22, minBit 9, minWin=24, winSum=412
3224 23:16:19.698784 TX Vref=24, minBit 9, minWin=24, winSum=414
3225 23:16:19.702192 TX Vref=26, minBit 1, minWin=25, winSum=419
3226 23:16:19.705394 TX Vref=28, minBit 1, minWin=25, winSum=427
3227 23:16:19.708963 TX Vref=30, minBit 9, minWin=26, winSum=431
3228 23:16:19.712358 TX Vref=32, minBit 9, minWin=26, winSum=432
3229 23:16:19.718987 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 32
3230 23:16:19.719560
3231 23:16:19.722445 Final TX Range 1 Vref 32
3232 23:16:19.723129
3233 23:16:19.723504 ==
3234 23:16:19.725262 Dram Type= 6, Freq= 0, CH_1, rank 0
3235 23:16:19.728935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3236 23:16:19.729709 ==
3237 23:16:19.730262
3238 23:16:19.730746
3239 23:16:19.732877 TX Vref Scan disable
3240 23:16:19.736098 == TX Byte 0 ==
3241 23:16:19.739269 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3242 23:16:19.742171 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3243 23:16:19.745419 == TX Byte 1 ==
3244 23:16:19.749054 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3245 23:16:19.752291 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3246 23:16:19.752745
3247 23:16:19.755637 [DATLAT]
3248 23:16:19.756089 Freq=1200, CH1 RK0
3249 23:16:19.756446
3250 23:16:19.759028 DATLAT Default: 0xd
3251 23:16:19.759481 0, 0xFFFF, sum = 0
3252 23:16:19.762310 1, 0xFFFF, sum = 0
3253 23:16:19.762772 2, 0xFFFF, sum = 0
3254 23:16:19.765225 3, 0xFFFF, sum = 0
3255 23:16:19.765725 4, 0xFFFF, sum = 0
3256 23:16:19.769252 5, 0xFFFF, sum = 0
3257 23:16:19.769863 6, 0xFFFF, sum = 0
3258 23:16:19.772478 7, 0xFFFF, sum = 0
3259 23:16:19.773026 8, 0xFFFF, sum = 0
3260 23:16:19.775387 9, 0xFFFF, sum = 0
3261 23:16:19.775848 10, 0xFFFF, sum = 0
3262 23:16:19.779392 11, 0xFFFF, sum = 0
3263 23:16:19.779992 12, 0x0, sum = 1
3264 23:16:19.782122 13, 0x0, sum = 2
3265 23:16:19.782587 14, 0x0, sum = 3
3266 23:16:19.785735 15, 0x0, sum = 4
3267 23:16:19.786197 best_step = 13
3268 23:16:19.786592
3269 23:16:19.786952 ==
3270 23:16:19.788933 Dram Type= 6, Freq= 0, CH_1, rank 0
3271 23:16:19.795364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3272 23:16:19.795821 ==
3273 23:16:19.796232 RX Vref Scan: 1
3274 23:16:19.796603
3275 23:16:19.798802 Set Vref Range= 32 -> 127
3276 23:16:19.799268
3277 23:16:19.802744 RX Vref 32 -> 127, step: 1
3278 23:16:19.803303
3279 23:16:19.805384 RX Delay -5 -> 252, step: 4
3280 23:16:19.805849
3281 23:16:19.806178 Set Vref, RX VrefLevel [Byte0]: 32
3282 23:16:19.808494 [Byte1]: 32
3283 23:16:19.813630
3284 23:16:19.814186 Set Vref, RX VrefLevel [Byte0]: 33
3285 23:16:19.816794 [Byte1]: 33
3286 23:16:19.821693
3287 23:16:19.822159 Set Vref, RX VrefLevel [Byte0]: 34
3288 23:16:19.824860 [Byte1]: 34
3289 23:16:19.829393
3290 23:16:19.829914 Set Vref, RX VrefLevel [Byte0]: 35
3291 23:16:19.832811 [Byte1]: 35
3292 23:16:19.836749
3293 23:16:19.837299 Set Vref, RX VrefLevel [Byte0]: 36
3294 23:16:19.840208 [Byte1]: 36
3295 23:16:19.844899
3296 23:16:19.845305 Set Vref, RX VrefLevel [Byte0]: 37
3297 23:16:19.848098 [Byte1]: 37
3298 23:16:19.852727
3299 23:16:19.853133 Set Vref, RX VrefLevel [Byte0]: 38
3300 23:16:19.855800 [Byte1]: 38
3301 23:16:19.860383
3302 23:16:19.860857 Set Vref, RX VrefLevel [Byte0]: 39
3303 23:16:19.864111 [Byte1]: 39
3304 23:16:19.868630
3305 23:16:19.869036 Set Vref, RX VrefLevel [Byte0]: 40
3306 23:16:19.871722 [Byte1]: 40
3307 23:16:19.876106
3308 23:16:19.876511 Set Vref, RX VrefLevel [Byte0]: 41
3309 23:16:19.879776 [Byte1]: 41
3310 23:16:19.884101
3311 23:16:19.884509 Set Vref, RX VrefLevel [Byte0]: 42
3312 23:16:19.887854 [Byte1]: 42
3313 23:16:19.892289
3314 23:16:19.892818 Set Vref, RX VrefLevel [Byte0]: 43
3315 23:16:19.895349 [Byte1]: 43
3316 23:16:19.900047
3317 23:16:19.900559 Set Vref, RX VrefLevel [Byte0]: 44
3318 23:16:19.903176 [Byte1]: 44
3319 23:16:19.908056
3320 23:16:19.908614 Set Vref, RX VrefLevel [Byte0]: 45
3321 23:16:19.910820 [Byte1]: 45
3322 23:16:19.915682
3323 23:16:19.916239 Set Vref, RX VrefLevel [Byte0]: 46
3324 23:16:19.918864 [Byte1]: 46
3325 23:16:19.923201
3326 23:16:19.923759 Set Vref, RX VrefLevel [Byte0]: 47
3327 23:16:19.926704 [Byte1]: 47
3328 23:16:19.931213
3329 23:16:19.931658 Set Vref, RX VrefLevel [Byte0]: 48
3330 23:16:19.934481 [Byte1]: 48
3331 23:16:19.939140
3332 23:16:19.939545 Set Vref, RX VrefLevel [Byte0]: 49
3333 23:16:19.942602 [Byte1]: 49
3334 23:16:19.947233
3335 23:16:19.947739 Set Vref, RX VrefLevel [Byte0]: 50
3336 23:16:19.950452 [Byte1]: 50
3337 23:16:19.954631
3338 23:16:19.955194 Set Vref, RX VrefLevel [Byte0]: 51
3339 23:16:19.957953 [Byte1]: 51
3340 23:16:19.962423
3341 23:16:19.962872 Set Vref, RX VrefLevel [Byte0]: 52
3342 23:16:19.965796 [Byte1]: 52
3343 23:16:19.970463
3344 23:16:19.970913 Set Vref, RX VrefLevel [Byte0]: 53
3345 23:16:19.973892 [Byte1]: 53
3346 23:16:19.978027
3347 23:16:19.978430 Set Vref, RX VrefLevel [Byte0]: 54
3348 23:16:19.981484 [Byte1]: 54
3349 23:16:19.986433
3350 23:16:19.986834 Set Vref, RX VrefLevel [Byte0]: 55
3351 23:16:19.989554 [Byte1]: 55
3352 23:16:19.994209
3353 23:16:19.994664 Set Vref, RX VrefLevel [Byte0]: 56
3354 23:16:19.997445 [Byte1]: 56
3355 23:16:20.001907
3356 23:16:20.002311 Set Vref, RX VrefLevel [Byte0]: 57
3357 23:16:20.005374 [Byte1]: 57
3358 23:16:20.009785
3359 23:16:20.010314 Set Vref, RX VrefLevel [Byte0]: 58
3360 23:16:20.013053 [Byte1]: 58
3361 23:16:20.017688
3362 23:16:20.018240 Set Vref, RX VrefLevel [Byte0]: 59
3363 23:16:20.021004 [Byte1]: 59
3364 23:16:20.025541
3365 23:16:20.026137 Set Vref, RX VrefLevel [Byte0]: 60
3366 23:16:20.029136 [Byte1]: 60
3367 23:16:20.033467
3368 23:16:20.034068 Set Vref, RX VrefLevel [Byte0]: 61
3369 23:16:20.036653 [Byte1]: 61
3370 23:16:20.041637
3371 23:16:20.042192 Set Vref, RX VrefLevel [Byte0]: 62
3372 23:16:20.044708 [Byte1]: 62
3373 23:16:20.049362
3374 23:16:20.050037 Set Vref, RX VrefLevel [Byte0]: 63
3375 23:16:20.052366 [Byte1]: 63
3376 23:16:20.056979
3377 23:16:20.057427 Set Vref, RX VrefLevel [Byte0]: 64
3378 23:16:20.059970 [Byte1]: 64
3379 23:16:20.065217
3380 23:16:20.065840 Set Vref, RX VrefLevel [Byte0]: 65
3381 23:16:20.067978 [Byte1]: 65
3382 23:16:20.072474
3383 23:16:20.073086 Set Vref, RX VrefLevel [Byte0]: 66
3384 23:16:20.075647 [Byte1]: 66
3385 23:16:20.080552
3386 23:16:20.081118 Set Vref, RX VrefLevel [Byte0]: 67
3387 23:16:20.083993 [Byte1]: 67
3388 23:16:20.088316
3389 23:16:20.088870 Set Vref, RX VrefLevel [Byte0]: 68
3390 23:16:20.091570 [Byte1]: 68
3391 23:16:20.096606
3392 23:16:20.097158 Set Vref, RX VrefLevel [Byte0]: 69
3393 23:16:20.099388 [Byte1]: 69
3394 23:16:20.103946
3395 23:16:20.104394 Final RX Vref Byte 0 = 57 to rank0
3396 23:16:20.107395 Final RX Vref Byte 1 = 48 to rank0
3397 23:16:20.110751 Final RX Vref Byte 0 = 57 to rank1
3398 23:16:20.113894 Final RX Vref Byte 1 = 48 to rank1==
3399 23:16:20.117696 Dram Type= 6, Freq= 0, CH_1, rank 0
3400 23:16:20.124280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3401 23:16:20.124837 ==
3402 23:16:20.125201 DQS Delay:
3403 23:16:20.125539 DQS0 = 0, DQS1 = 0
3404 23:16:20.127366 DQM Delay:
3405 23:16:20.127814 DQM0 = 120, DQM1 = 116
3406 23:16:20.131210 DQ Delay:
3407 23:16:20.134365 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3408 23:16:20.137665 DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120
3409 23:16:20.140955 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3410 23:16:20.144248 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3411 23:16:20.144804
3412 23:16:20.145164
3413 23:16:20.150952 [DQSOSCAuto] RK0, (LSB)MR18= 0xfc0f, (MSB)MR19= 0x304, tDQSOscB0 = 404 ps tDQSOscB1 = 411 ps
3414 23:16:20.154024 CH1 RK0: MR19=304, MR18=FC0F
3415 23:16:20.160862 CH1_RK0: MR19=0x304, MR18=0xFC0F, DQSOSC=404, MR23=63, INC=40, DEC=26
3416 23:16:20.161316
3417 23:16:20.164101 ----->DramcWriteLeveling(PI) begin...
3418 23:16:20.164560 ==
3419 23:16:20.167085 Dram Type= 6, Freq= 0, CH_1, rank 1
3420 23:16:20.170963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3421 23:16:20.171420 ==
3422 23:16:20.174255 Write leveling (Byte 0): 26 => 26
3423 23:16:20.177701 Write leveling (Byte 1): 29 => 29
3424 23:16:20.181358 DramcWriteLeveling(PI) end<-----
3425 23:16:20.181931
3426 23:16:20.182297 ==
3427 23:16:20.184074 Dram Type= 6, Freq= 0, CH_1, rank 1
3428 23:16:20.188274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3429 23:16:20.190920 ==
3430 23:16:20.191368 [Gating] SW mode calibration
3431 23:16:20.200943 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3432 23:16:20.204252 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3433 23:16:20.207404 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 23:16:20.213991 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 23:16:20.217899 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 23:16:20.221095 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 23:16:20.227877 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 23:16:20.231012 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 23:16:20.234228 0 15 24 | B1->B0 | 2e2e 3333 | 0 1 | (1 0) (1 0)
3440 23:16:20.241014 0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
3441 23:16:20.244312 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 23:16:20.247395 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 23:16:20.254431 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 23:16:20.257701 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 23:16:20.261147 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 23:16:20.264568 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 23:16:20.271291 1 0 24 | B1->B0 | 3d3d 2626 | 1 0 | (1 1) (0 0)
3448 23:16:20.274413 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 23:16:20.277722 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 23:16:20.284550 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 23:16:20.287608 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 23:16:20.291048 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 23:16:20.297659 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 23:16:20.300958 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3455 23:16:20.304631 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3456 23:16:20.310695 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3457 23:16:20.313987 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 23:16:20.317289 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 23:16:20.324134 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 23:16:20.328039 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 23:16:20.331032 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 23:16:20.337405 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 23:16:20.340577 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 23:16:20.343955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 23:16:20.350816 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 23:16:20.354048 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 23:16:20.357776 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 23:16:20.364102 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 23:16:20.367624 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 23:16:20.370647 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3471 23:16:20.377096 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3472 23:16:20.380519 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3473 23:16:20.383793 Total UI for P1: 0, mck2ui 16
3474 23:16:20.387379 best dqsien dly found for B1: ( 1, 3, 22)
3475 23:16:20.390783 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 23:16:20.394093 Total UI for P1: 0, mck2ui 16
3477 23:16:20.397315 best dqsien dly found for B0: ( 1, 3, 26)
3478 23:16:20.400514 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3479 23:16:20.404136 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3480 23:16:20.404713
3481 23:16:20.407187 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3482 23:16:20.413865 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3483 23:16:20.414437 [Gating] SW calibration Done
3484 23:16:20.414808 ==
3485 23:16:20.416765 Dram Type= 6, Freq= 0, CH_1, rank 1
3486 23:16:20.423961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3487 23:16:20.424489 ==
3488 23:16:20.424857 RX Vref Scan: 0
3489 23:16:20.425193
3490 23:16:20.427546 RX Vref 0 -> 0, step: 1
3491 23:16:20.428130
3492 23:16:20.430079 RX Delay -40 -> 252, step: 8
3493 23:16:20.433693 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3494 23:16:20.437056 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3495 23:16:20.440298 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3496 23:16:20.447293 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3497 23:16:20.450327 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3498 23:16:20.453570 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3499 23:16:20.457072 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3500 23:16:20.460358 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3501 23:16:20.466902 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3502 23:16:20.470199 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3503 23:16:20.473515 iDelay=200, Bit 10, Center 119 (56 ~ 183) 128
3504 23:16:20.477053 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3505 23:16:20.480395 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3506 23:16:20.486949 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3507 23:16:20.489958 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3508 23:16:20.493373 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3509 23:16:20.493821 ==
3510 23:16:20.497020 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 23:16:20.500194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 23:16:20.500610 ==
3513 23:16:20.503574 DQS Delay:
3514 23:16:20.504026 DQS0 = 0, DQS1 = 0
3515 23:16:20.506761 DQM Delay:
3516 23:16:20.507221 DQM0 = 120, DQM1 = 119
3517 23:16:20.507552 DQ Delay:
3518 23:16:20.513699 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3519 23:16:20.516948 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =123
3520 23:16:20.520291 DQ8 =107, DQ9 =107, DQ10 =119, DQ11 =115
3521 23:16:20.523489 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3522 23:16:20.523946
3523 23:16:20.524306
3524 23:16:20.524636 ==
3525 23:16:20.527047 Dram Type= 6, Freq= 0, CH_1, rank 1
3526 23:16:20.529895 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3527 23:16:20.530317 ==
3528 23:16:20.530648
3529 23:16:20.530952
3530 23:16:20.533545 TX Vref Scan disable
3531 23:16:20.536563 == TX Byte 0 ==
3532 23:16:20.539900 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3533 23:16:20.543522 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3534 23:16:20.546769 == TX Byte 1 ==
3535 23:16:20.549978 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3536 23:16:20.553346 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3537 23:16:20.553907 ==
3538 23:16:20.556412 Dram Type= 6, Freq= 0, CH_1, rank 1
3539 23:16:20.562952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3540 23:16:20.563502 ==
3541 23:16:20.573445 TX Vref=22, minBit 9, minWin=25, winSum=421
3542 23:16:20.576776 TX Vref=24, minBit 2, minWin=26, winSum=426
3543 23:16:20.580158 TX Vref=26, minBit 10, minWin=25, winSum=427
3544 23:16:20.583362 TX Vref=28, minBit 2, minWin=26, winSum=432
3545 23:16:20.586795 TX Vref=30, minBit 9, minWin=26, winSum=438
3546 23:16:20.593162 TX Vref=32, minBit 11, minWin=26, winSum=434
3547 23:16:20.596444 [TxChooseVref] Worse bit 9, Min win 26, Win sum 438, Final Vref 30
3548 23:16:20.597218
3549 23:16:20.599887 Final TX Range 1 Vref 30
3550 23:16:20.600490
3551 23:16:20.601002 ==
3552 23:16:20.603198 Dram Type= 6, Freq= 0, CH_1, rank 1
3553 23:16:20.606490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3554 23:16:20.610256 ==
3555 23:16:20.610779
3556 23:16:20.611108
3557 23:16:20.611409 TX Vref Scan disable
3558 23:16:20.613407 == TX Byte 0 ==
3559 23:16:20.616797 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3560 23:16:20.623392 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3561 23:16:20.623904 == TX Byte 1 ==
3562 23:16:20.626349 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3563 23:16:20.632910 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3564 23:16:20.633422
3565 23:16:20.633789 [DATLAT]
3566 23:16:20.634094 Freq=1200, CH1 RK1
3567 23:16:20.634387
3568 23:16:20.636674 DATLAT Default: 0xd
3569 23:16:20.637192 0, 0xFFFF, sum = 0
3570 23:16:20.640024 1, 0xFFFF, sum = 0
3571 23:16:20.643541 2, 0xFFFF, sum = 0
3572 23:16:20.644057 3, 0xFFFF, sum = 0
3573 23:16:20.646668 4, 0xFFFF, sum = 0
3574 23:16:20.647185 5, 0xFFFF, sum = 0
3575 23:16:20.650040 6, 0xFFFF, sum = 0
3576 23:16:20.650555 7, 0xFFFF, sum = 0
3577 23:16:20.653025 8, 0xFFFF, sum = 0
3578 23:16:20.653443 9, 0xFFFF, sum = 0
3579 23:16:20.656820 10, 0xFFFF, sum = 0
3580 23:16:20.657337 11, 0xFFFF, sum = 0
3581 23:16:20.659619 12, 0x0, sum = 1
3582 23:16:20.660031 13, 0x0, sum = 2
3583 23:16:20.663052 14, 0x0, sum = 3
3584 23:16:20.663467 15, 0x0, sum = 4
3585 23:16:20.666317 best_step = 13
3586 23:16:20.666724
3587 23:16:20.667045 ==
3588 23:16:20.669811 Dram Type= 6, Freq= 0, CH_1, rank 1
3589 23:16:20.673081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3590 23:16:20.673492 ==
3591 23:16:20.673860 RX Vref Scan: 0
3592 23:16:20.675998
3593 23:16:20.676407 RX Vref 0 -> 0, step: 1
3594 23:16:20.676729
3595 23:16:20.679832 RX Delay -5 -> 252, step: 4
3596 23:16:20.682707 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3597 23:16:20.689677 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3598 23:16:20.693202 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3599 23:16:20.695927 iDelay=195, Bit 3, Center 116 (59 ~ 174) 116
3600 23:16:20.699705 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3601 23:16:20.702948 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3602 23:16:20.709645 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3603 23:16:20.712734 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3604 23:16:20.715913 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3605 23:16:20.719433 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3606 23:16:20.722596 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3607 23:16:20.728911 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3608 23:16:20.732770 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3609 23:16:20.735721 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3610 23:16:20.739136 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3611 23:16:20.745810 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3612 23:16:20.746264 ==
3613 23:16:20.749084 Dram Type= 6, Freq= 0, CH_1, rank 1
3614 23:16:20.752411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3615 23:16:20.752909 ==
3616 23:16:20.753270 DQS Delay:
3617 23:16:20.755789 DQS0 = 0, DQS1 = 0
3618 23:16:20.756271 DQM Delay:
3619 23:16:20.759056 DQM0 = 120, DQM1 = 117
3620 23:16:20.759564 DQ Delay:
3621 23:16:20.762182 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3622 23:16:20.765284 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3623 23:16:20.768610 DQ8 =106, DQ9 =106, DQ10 =116, DQ11 =110
3624 23:16:20.772492 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3625 23:16:20.773074
3626 23:16:20.773441
3627 23:16:20.782559 [DQSOSCAuto] RK1, (LSB)MR18= 0xeec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3628 23:16:20.785553 CH1 RK1: MR19=403, MR18=EEC
3629 23:16:20.789166 CH1_RK1: MR19=0x403, MR18=0xEEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3630 23:16:20.791842 [RxdqsGatingPostProcess] freq 1200
3631 23:16:20.798757 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3632 23:16:20.802419 best DQS0 dly(2T, 0.5T) = (0, 11)
3633 23:16:20.805522 best DQS1 dly(2T, 0.5T) = (0, 11)
3634 23:16:20.808843 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3635 23:16:20.811925 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3636 23:16:20.815196 best DQS0 dly(2T, 0.5T) = (0, 11)
3637 23:16:20.818842 best DQS1 dly(2T, 0.5T) = (0, 11)
3638 23:16:20.822163 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3639 23:16:20.825479 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3640 23:16:20.828755 Pre-setting of DQS Precalculation
3641 23:16:20.832105 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3642 23:16:20.838647 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3643 23:16:20.845320 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3644 23:16:20.848664
3645 23:16:20.849202
3646 23:16:20.849667 [Calibration Summary] 2400 Mbps
3647 23:16:20.851547 CH 0, Rank 0
3648 23:16:20.852011 SW Impedance : PASS
3649 23:16:20.855040 DUTY Scan : NO K
3650 23:16:20.858310 ZQ Calibration : PASS
3651 23:16:20.858762 Jitter Meter : NO K
3652 23:16:20.861528 CBT Training : PASS
3653 23:16:20.865007 Write leveling : PASS
3654 23:16:20.865486 RX DQS gating : PASS
3655 23:16:20.868933 RX DQ/DQS(RDDQC) : PASS
3656 23:16:20.871661 TX DQ/DQS : PASS
3657 23:16:20.872124 RX DATLAT : PASS
3658 23:16:20.874906 RX DQ/DQS(Engine): PASS
3659 23:16:20.878238 TX OE : NO K
3660 23:16:20.878793 All Pass.
3661 23:16:20.879163
3662 23:16:20.879492 CH 0, Rank 1
3663 23:16:20.881484 SW Impedance : PASS
3664 23:16:20.885004 DUTY Scan : NO K
3665 23:16:20.885668 ZQ Calibration : PASS
3666 23:16:20.888674 Jitter Meter : NO K
3667 23:16:20.892208 CBT Training : PASS
3668 23:16:20.892820 Write leveling : PASS
3669 23:16:20.895091 RX DQS gating : PASS
3670 23:16:20.895705 RX DQ/DQS(RDDQC) : PASS
3671 23:16:20.898506 TX DQ/DQS : PASS
3672 23:16:20.901683 RX DATLAT : PASS
3673 23:16:20.902248 RX DQ/DQS(Engine): PASS
3674 23:16:20.905381 TX OE : NO K
3675 23:16:20.905969 All Pass.
3676 23:16:20.906332
3677 23:16:20.908614 CH 1, Rank 0
3678 23:16:20.909170 SW Impedance : PASS
3679 23:16:20.911904 DUTY Scan : NO K
3680 23:16:20.915180 ZQ Calibration : PASS
3681 23:16:20.915659 Jitter Meter : NO K
3682 23:16:20.918582 CBT Training : PASS
3683 23:16:20.921879 Write leveling : PASS
3684 23:16:20.922595 RX DQS gating : PASS
3685 23:16:20.925118 RX DQ/DQS(RDDQC) : PASS
3686 23:16:20.928091 TX DQ/DQS : PASS
3687 23:16:20.928807 RX DATLAT : PASS
3688 23:16:20.931432 RX DQ/DQS(Engine): PASS
3689 23:16:20.934770 TX OE : NO K
3690 23:16:20.935306 All Pass.
3691 23:16:20.935819
3692 23:16:20.936201 CH 1, Rank 1
3693 23:16:20.938246 SW Impedance : PASS
3694 23:16:20.941425 DUTY Scan : NO K
3695 23:16:20.942024 ZQ Calibration : PASS
3696 23:16:20.944907 Jitter Meter : NO K
3697 23:16:20.945473 CBT Training : PASS
3698 23:16:20.947952 Write leveling : PASS
3699 23:16:20.951420 RX DQS gating : PASS
3700 23:16:20.951906 RX DQ/DQS(RDDQC) : PASS
3701 23:16:20.954984 TX DQ/DQS : PASS
3702 23:16:20.958098 RX DATLAT : PASS
3703 23:16:20.958567 RX DQ/DQS(Engine): PASS
3704 23:16:20.961217 TX OE : NO K
3705 23:16:20.961747 All Pass.
3706 23:16:20.962154
3707 23:16:20.964617 DramC Write-DBI off
3708 23:16:20.968388 PER_BANK_REFRESH: Hybrid Mode
3709 23:16:20.968933 TX_TRACKING: ON
3710 23:16:20.978239 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3711 23:16:20.981631 [FAST_K] Save calibration result to emmc
3712 23:16:20.984986 dramc_set_vcore_voltage set vcore to 650000
3713 23:16:20.988429 Read voltage for 600, 5
3714 23:16:20.988960 Vio18 = 0
3715 23:16:20.989393 Vcore = 650000
3716 23:16:20.991454 Vdram = 0
3717 23:16:20.991985 Vddq = 0
3718 23:16:20.992363 Vmddr = 0
3719 23:16:20.997818 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3720 23:16:21.001281 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3721 23:16:21.004686 MEM_TYPE=3, freq_sel=19
3722 23:16:21.007929 sv_algorithm_assistance_LP4_1600
3723 23:16:21.011435 ============ PULL DRAM RESETB DOWN ============
3724 23:16:21.014482 ========== PULL DRAM RESETB DOWN end =========
3725 23:16:21.021419 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3726 23:16:21.024696 ===================================
3727 23:16:21.027620 LPDDR4 DRAM CONFIGURATION
3728 23:16:21.030945 ===================================
3729 23:16:21.031488 EX_ROW_EN[0] = 0x0
3730 23:16:21.034480 EX_ROW_EN[1] = 0x0
3731 23:16:21.034894 LP4Y_EN = 0x0
3732 23:16:21.037636 WORK_FSP = 0x0
3733 23:16:21.038050 WL = 0x2
3734 23:16:21.040864 RL = 0x2
3735 23:16:21.041374 BL = 0x2
3736 23:16:21.044632 RPST = 0x0
3737 23:16:21.045051 RD_PRE = 0x0
3738 23:16:21.047164 WR_PRE = 0x1
3739 23:16:21.047576 WR_PST = 0x0
3740 23:16:21.051217 DBI_WR = 0x0
3741 23:16:21.054092 DBI_RD = 0x0
3742 23:16:21.054564 OTF = 0x1
3743 23:16:21.057316 ===================================
3744 23:16:21.060907 ===================================
3745 23:16:21.061417 ANA top config
3746 23:16:21.063755 ===================================
3747 23:16:21.067170 DLL_ASYNC_EN = 0
3748 23:16:21.070330 ALL_SLAVE_EN = 1
3749 23:16:21.073745 NEW_RANK_MODE = 1
3750 23:16:21.076874 DLL_IDLE_MODE = 1
3751 23:16:21.077302 LP45_APHY_COMB_EN = 1
3752 23:16:21.080577 TX_ODT_DIS = 1
3753 23:16:21.083784 NEW_8X_MODE = 1
3754 23:16:21.087144 ===================================
3755 23:16:21.090265 ===================================
3756 23:16:21.093422 data_rate = 1200
3757 23:16:21.097487 CKR = 1
3758 23:16:21.098073 DQ_P2S_RATIO = 8
3759 23:16:21.100336 ===================================
3760 23:16:21.103491 CA_P2S_RATIO = 8
3761 23:16:21.106730 DQ_CA_OPEN = 0
3762 23:16:21.110430 DQ_SEMI_OPEN = 0
3763 23:16:21.113949 CA_SEMI_OPEN = 0
3764 23:16:21.117048 CA_FULL_RATE = 0
3765 23:16:21.117475 DQ_CKDIV4_EN = 1
3766 23:16:21.120954 CA_CKDIV4_EN = 1
3767 23:16:21.123514 CA_PREDIV_EN = 0
3768 23:16:21.127698 PH8_DLY = 0
3769 23:16:21.130762 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3770 23:16:21.133839 DQ_AAMCK_DIV = 4
3771 23:16:21.134304 CA_AAMCK_DIV = 4
3772 23:16:21.136908 CA_ADMCK_DIV = 4
3773 23:16:21.140581 DQ_TRACK_CA_EN = 0
3774 23:16:21.143985 CA_PICK = 600
3775 23:16:21.147374 CA_MCKIO = 600
3776 23:16:21.150565 MCKIO_SEMI = 0
3777 23:16:21.153243 PLL_FREQ = 2288
3778 23:16:21.153863 DQ_UI_PI_RATIO = 32
3779 23:16:21.156594 CA_UI_PI_RATIO = 0
3780 23:16:21.160163 ===================================
3781 23:16:21.163651 ===================================
3782 23:16:21.166851 memory_type:LPDDR4
3783 23:16:21.170424 GP_NUM : 10
3784 23:16:21.170878 SRAM_EN : 1
3785 23:16:21.173346 MD32_EN : 0
3786 23:16:21.176592 ===================================
3787 23:16:21.179992 [ANA_INIT] >>>>>>>>>>>>>>
3788 23:16:21.180590 <<<<<< [CONFIGURE PHASE]: ANA_TX
3789 23:16:21.183474 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3790 23:16:21.186821 ===================================
3791 23:16:21.190239 data_rate = 1200,PCW = 0X5800
3792 23:16:21.193296 ===================================
3793 23:16:21.197029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3794 23:16:21.203411 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3795 23:16:21.209912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 23:16:21.213494 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3797 23:16:21.216880 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3798 23:16:21.220215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3799 23:16:21.223693 [ANA_INIT] flow start
3800 23:16:21.224237 [ANA_INIT] PLL >>>>>>>>
3801 23:16:21.226857 [ANA_INIT] PLL <<<<<<<<
3802 23:16:21.230443 [ANA_INIT] MIDPI >>>>>>>>
3803 23:16:21.230974 [ANA_INIT] MIDPI <<<<<<<<
3804 23:16:21.233337 [ANA_INIT] DLL >>>>>>>>
3805 23:16:21.236657 [ANA_INIT] flow end
3806 23:16:21.240363 ============ LP4 DIFF to SE enter ============
3807 23:16:21.243139 ============ LP4 DIFF to SE exit ============
3808 23:16:21.246504 [ANA_INIT] <<<<<<<<<<<<<
3809 23:16:21.250055 [Flow] Enable top DCM control >>>>>
3810 23:16:21.252986 [Flow] Enable top DCM control <<<<<
3811 23:16:21.256538 Enable DLL master slave shuffle
3812 23:16:21.259892 ==============================================================
3813 23:16:21.262706 Gating Mode config
3814 23:16:21.269643 ==============================================================
3815 23:16:21.270071 Config description:
3816 23:16:21.280035 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3817 23:16:21.286484 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3818 23:16:21.289838 SELPH_MODE 0: By rank 1: By Phase
3819 23:16:21.296416 ==============================================================
3820 23:16:21.300038 GAT_TRACK_EN = 1
3821 23:16:21.302948 RX_GATING_MODE = 2
3822 23:16:21.306837 RX_GATING_TRACK_MODE = 2
3823 23:16:21.309708 SELPH_MODE = 1
3824 23:16:21.313136 PICG_EARLY_EN = 1
3825 23:16:21.316041 VALID_LAT_VALUE = 1
3826 23:16:21.319853 ==============================================================
3827 23:16:21.322989 Enter into Gating configuration >>>>
3828 23:16:21.326087 Exit from Gating configuration <<<<
3829 23:16:21.329377 Enter into DVFS_PRE_config >>>>>
3830 23:16:21.342786 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3831 23:16:21.343370 Exit from DVFS_PRE_config <<<<<
3832 23:16:21.346832 Enter into PICG configuration >>>>
3833 23:16:21.349463 Exit from PICG configuration <<<<
3834 23:16:21.352641 [RX_INPUT] configuration >>>>>
3835 23:16:21.356105 [RX_INPUT] configuration <<<<<
3836 23:16:21.362744 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3837 23:16:21.366110 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3838 23:16:21.372917 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 23:16:21.379614 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 23:16:21.386772 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 23:16:21.392721 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 23:16:21.395945 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3843 23:16:21.399819 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3844 23:16:21.402567 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3845 23:16:21.409325 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3846 23:16:21.412542 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3847 23:16:21.416038 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3848 23:16:21.419644 ===================================
3849 23:16:21.422668 LPDDR4 DRAM CONFIGURATION
3850 23:16:21.425989 ===================================
3851 23:16:21.426460 EX_ROW_EN[0] = 0x0
3852 23:16:21.429429 EX_ROW_EN[1] = 0x0
3853 23:16:21.432709 LP4Y_EN = 0x0
3854 23:16:21.433128 WORK_FSP = 0x0
3855 23:16:21.436175 WL = 0x2
3856 23:16:21.436715 RL = 0x2
3857 23:16:21.439660 BL = 0x2
3858 23:16:21.440232 RPST = 0x0
3859 23:16:21.443140 RD_PRE = 0x0
3860 23:16:21.443737 WR_PRE = 0x1
3861 23:16:21.446527 WR_PST = 0x0
3862 23:16:21.447100 DBI_WR = 0x0
3863 23:16:21.449324 DBI_RD = 0x0
3864 23:16:21.449828 OTF = 0x1
3865 23:16:21.452756 ===================================
3866 23:16:21.455997 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3867 23:16:21.462605 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3868 23:16:21.466093 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3869 23:16:21.468777 ===================================
3870 23:16:21.472595 LPDDR4 DRAM CONFIGURATION
3871 23:16:21.475376 ===================================
3872 23:16:21.475850 EX_ROW_EN[0] = 0x10
3873 23:16:21.478969 EX_ROW_EN[1] = 0x0
3874 23:16:21.482248 LP4Y_EN = 0x0
3875 23:16:21.482808 WORK_FSP = 0x0
3876 23:16:21.485270 WL = 0x2
3877 23:16:21.485771 RL = 0x2
3878 23:16:21.488744 BL = 0x2
3879 23:16:21.489209 RPST = 0x0
3880 23:16:21.492097 RD_PRE = 0x0
3881 23:16:21.492568 WR_PRE = 0x1
3882 23:16:21.495188 WR_PST = 0x0
3883 23:16:21.495659 DBI_WR = 0x0
3884 23:16:21.499025 DBI_RD = 0x0
3885 23:16:21.499517 OTF = 0x1
3886 23:16:21.501663 ===================================
3887 23:16:21.508538 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3888 23:16:21.513064 nWR fixed to 30
3889 23:16:21.516080 [ModeRegInit_LP4] CH0 RK0
3890 23:16:21.516505 [ModeRegInit_LP4] CH0 RK1
3891 23:16:21.519695 [ModeRegInit_LP4] CH1 RK0
3892 23:16:21.522925 [ModeRegInit_LP4] CH1 RK1
3893 23:16:21.523451 match AC timing 17
3894 23:16:21.529747 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3895 23:16:21.532706 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3896 23:16:21.536142 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3897 23:16:21.542914 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3898 23:16:21.545936 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3899 23:16:21.546360 ==
3900 23:16:21.549544 Dram Type= 6, Freq= 0, CH_0, rank 0
3901 23:16:21.552776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3902 23:16:21.553192 ==
3903 23:16:21.559306 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3904 23:16:21.565943 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3905 23:16:21.569405 [CA 0] Center 35 (5~66) winsize 62
3906 23:16:21.572788 [CA 1] Center 36 (5~67) winsize 63
3907 23:16:21.576124 [CA 2] Center 33 (3~64) winsize 62
3908 23:16:21.579003 [CA 3] Center 33 (2~64) winsize 63
3909 23:16:21.583225 [CA 4] Center 33 (2~64) winsize 63
3910 23:16:21.586213 [CA 5] Center 32 (2~63) winsize 62
3911 23:16:21.586648
3912 23:16:21.589177 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3913 23:16:21.589622
3914 23:16:21.592661 [CATrainingPosCal] consider 1 rank data
3915 23:16:21.595814 u2DelayCellTimex100 = 270/100 ps
3916 23:16:21.599173 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3917 23:16:21.602594 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3918 23:16:21.605930 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3919 23:16:21.609389 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3920 23:16:21.612635 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3921 23:16:21.618837 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3922 23:16:21.619565
3923 23:16:21.622678 CA PerBit enable=1, Macro0, CA PI delay=32
3924 23:16:21.623398
3925 23:16:21.625902 [CBTSetCACLKResult] CA Dly = 32
3926 23:16:21.626624 CS Dly: 4 (0~35)
3927 23:16:21.627282 ==
3928 23:16:21.628902 Dram Type= 6, Freq= 0, CH_0, rank 1
3929 23:16:21.632449 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3930 23:16:21.635479 ==
3931 23:16:21.638979 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3932 23:16:21.645300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3933 23:16:21.648812 [CA 0] Center 35 (5~66) winsize 62
3934 23:16:21.651958 [CA 1] Center 35 (5~66) winsize 62
3935 23:16:21.655532 [CA 2] Center 34 (3~65) winsize 63
3936 23:16:21.658820 [CA 3] Center 33 (3~64) winsize 62
3937 23:16:21.662046 [CA 4] Center 33 (2~64) winsize 63
3938 23:16:21.665547 [CA 5] Center 32 (2~63) winsize 62
3939 23:16:21.665786
3940 23:16:21.668735 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3941 23:16:21.668956
3942 23:16:21.672344 [CATrainingPosCal] consider 2 rank data
3943 23:16:21.675238 u2DelayCellTimex100 = 270/100 ps
3944 23:16:21.678695 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3945 23:16:21.682200 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3946 23:16:21.685883 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3947 23:16:21.688788 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
3948 23:16:21.695555 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3949 23:16:21.699111 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3950 23:16:21.699667
3951 23:16:21.702154 CA PerBit enable=1, Macro0, CA PI delay=32
3952 23:16:21.702617
3953 23:16:21.705718 [CBTSetCACLKResult] CA Dly = 32
3954 23:16:21.706281 CS Dly: 4 (0~35)
3955 23:16:21.706653
3956 23:16:21.708887 ----->DramcWriteLeveling(PI) begin...
3957 23:16:21.709352 ==
3958 23:16:21.711861 Dram Type= 6, Freq= 0, CH_0, rank 0
3959 23:16:21.718834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3960 23:16:21.719440 ==
3961 23:16:21.721940 Write leveling (Byte 0): 34 => 34
3962 23:16:21.725769 Write leveling (Byte 1): 31 => 31
3963 23:16:21.726364 DramcWriteLeveling(PI) end<-----
3964 23:16:21.726736
3965 23:16:21.728953 ==
3966 23:16:21.732160 Dram Type= 6, Freq= 0, CH_0, rank 0
3967 23:16:21.735521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3968 23:16:21.735990 ==
3969 23:16:21.738544 [Gating] SW mode calibration
3970 23:16:21.745531 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3971 23:16:21.748558 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3972 23:16:21.755206 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3973 23:16:21.758858 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 23:16:21.761879 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 23:16:21.768895 0 9 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (1 0)
3976 23:16:21.771948 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
3977 23:16:21.775320 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 23:16:21.782125 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 23:16:21.785616 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 23:16:21.788622 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 23:16:21.792228 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 23:16:21.798816 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 23:16:21.802119 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
3984 23:16:21.805351 0 10 16 | B1->B0 | 3434 4646 | 0 0 | (1 1) (0 0)
3985 23:16:21.812438 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 23:16:21.815331 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 23:16:21.818451 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 23:16:21.825067 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 23:16:21.828238 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 23:16:21.831956 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 23:16:21.838846 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 23:16:21.841814 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3993 23:16:21.845142 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 23:16:21.851643 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 23:16:21.854848 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 23:16:21.858397 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 23:16:21.865338 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 23:16:21.868313 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 23:16:21.871927 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 23:16:21.878322 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 23:16:21.881685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 23:16:21.885144 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 23:16:21.892040 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 23:16:21.894798 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 23:16:21.898306 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 23:16:21.905189 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 23:16:21.908223 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4008 23:16:21.911633 Total UI for P1: 0, mck2ui 16
4009 23:16:21.915113 best dqsien dly found for B0: ( 0, 13, 10)
4010 23:16:21.918741 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4011 23:16:21.921668 Total UI for P1: 0, mck2ui 16
4012 23:16:21.924671 best dqsien dly found for B1: ( 0, 13, 14)
4013 23:16:21.928190 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4014 23:16:21.931821 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4015 23:16:21.932382
4016 23:16:21.938341 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4017 23:16:21.941775 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4018 23:16:21.942332 [Gating] SW calibration Done
4019 23:16:21.944671 ==
4020 23:16:21.945227 Dram Type= 6, Freq= 0, CH_0, rank 0
4021 23:16:21.951301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4022 23:16:21.951848 ==
4023 23:16:21.952214 RX Vref Scan: 0
4024 23:16:21.952555
4025 23:16:21.954772 RX Vref 0 -> 0, step: 1
4026 23:16:21.955250
4027 23:16:21.957968 RX Delay -230 -> 252, step: 16
4028 23:16:21.961269 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4029 23:16:21.964987 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4030 23:16:21.971546 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4031 23:16:21.974947 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4032 23:16:21.977910 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4033 23:16:21.981154 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4034 23:16:21.984397 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4035 23:16:21.991263 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4036 23:16:21.994308 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4037 23:16:21.997760 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4038 23:16:22.001154 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4039 23:16:22.007871 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4040 23:16:22.011411 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4041 23:16:22.014317 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4042 23:16:22.018134 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4043 23:16:22.024555 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4044 23:16:22.025116 ==
4045 23:16:22.027912 Dram Type= 6, Freq= 0, CH_0, rank 0
4046 23:16:22.031347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4047 23:16:22.031905 ==
4048 23:16:22.032278 DQS Delay:
4049 23:16:22.034360 DQS0 = 0, DQS1 = 0
4050 23:16:22.034851 DQM Delay:
4051 23:16:22.037923 DQM0 = 49, DQM1 = 44
4052 23:16:22.038483 DQ Delay:
4053 23:16:22.040977 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4054 23:16:22.044538 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4055 23:16:22.047870 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =41
4056 23:16:22.051405 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4057 23:16:22.051961
4058 23:16:22.052330
4059 23:16:22.052664 ==
4060 23:16:22.054230 Dram Type= 6, Freq= 0, CH_0, rank 0
4061 23:16:22.057787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 23:16:22.058255 ==
4063 23:16:22.058614
4064 23:16:22.058947
4065 23:16:22.060835 TX Vref Scan disable
4066 23:16:22.064224 == TX Byte 0 ==
4067 23:16:22.067596 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4068 23:16:22.070953 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4069 23:16:22.074347 == TX Byte 1 ==
4070 23:16:22.077720 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4071 23:16:22.080978 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4072 23:16:22.081442 ==
4073 23:16:22.084691 Dram Type= 6, Freq= 0, CH_0, rank 0
4074 23:16:22.090826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4075 23:16:22.091497 ==
4076 23:16:22.091876
4077 23:16:22.092211
4078 23:16:22.092532 TX Vref Scan disable
4079 23:16:22.095017 == TX Byte 0 ==
4080 23:16:22.098933 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4081 23:16:22.105357 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4082 23:16:22.105879 == TX Byte 1 ==
4083 23:16:22.108624 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4084 23:16:22.115199 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4085 23:16:22.115678
4086 23:16:22.116043 [DATLAT]
4087 23:16:22.116381 Freq=600, CH0 RK0
4088 23:16:22.116711
4089 23:16:22.118412 DATLAT Default: 0x9
4090 23:16:22.118883 0, 0xFFFF, sum = 0
4091 23:16:22.121680 1, 0xFFFF, sum = 0
4092 23:16:22.122105 2, 0xFFFF, sum = 0
4093 23:16:22.125166 3, 0xFFFF, sum = 0
4094 23:16:22.128528 4, 0xFFFF, sum = 0
4095 23:16:22.129055 5, 0xFFFF, sum = 0
4096 23:16:22.131646 6, 0xFFFF, sum = 0
4097 23:16:22.132148 7, 0xFFFF, sum = 0
4098 23:16:22.134917 8, 0x0, sum = 1
4099 23:16:22.135383 9, 0x0, sum = 2
4100 23:16:22.135753 10, 0x0, sum = 3
4101 23:16:22.138315 11, 0x0, sum = 4
4102 23:16:22.138735 best_step = 9
4103 23:16:22.139063
4104 23:16:22.139369 ==
4105 23:16:22.141336 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 23:16:22.148110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 23:16:22.148794 ==
4108 23:16:22.149144 RX Vref Scan: 1
4109 23:16:22.149458
4110 23:16:22.151694 RX Vref 0 -> 0, step: 1
4111 23:16:22.152106
4112 23:16:22.154731 RX Delay -179 -> 252, step: 8
4113 23:16:22.155142
4114 23:16:22.158259 Set Vref, RX VrefLevel [Byte0]: 57
4115 23:16:22.161290 [Byte1]: 49
4116 23:16:22.161745
4117 23:16:22.165432 Final RX Vref Byte 0 = 57 to rank0
4118 23:16:22.168081 Final RX Vref Byte 1 = 49 to rank0
4119 23:16:22.171474 Final RX Vref Byte 0 = 57 to rank1
4120 23:16:22.174904 Final RX Vref Byte 1 = 49 to rank1==
4121 23:16:22.178343 Dram Type= 6, Freq= 0, CH_0, rank 0
4122 23:16:22.181782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4123 23:16:22.182241 ==
4124 23:16:22.185422 DQS Delay:
4125 23:16:22.186010 DQS0 = 0, DQS1 = 0
4126 23:16:22.186373 DQM Delay:
4127 23:16:22.188041 DQM0 = 52, DQM1 = 46
4128 23:16:22.188507 DQ Delay:
4129 23:16:22.191705 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4130 23:16:22.194666 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4131 23:16:22.198223 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4132 23:16:22.201677 DQ12 =52, DQ13 =56, DQ14 =56, DQ15 =52
4133 23:16:22.202198
4134 23:16:22.202556
4135 23:16:22.211670 [DQSOSCAuto] RK0, (LSB)MR18= 0x6a5d, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps
4136 23:16:22.215141 CH0 RK0: MR19=808, MR18=6A5D
4137 23:16:22.218773 CH0_RK0: MR19=0x808, MR18=0x6A5D, DQSOSC=389, MR23=63, INC=173, DEC=115
4138 23:16:22.221113
4139 23:16:22.224545 ----->DramcWriteLeveling(PI) begin...
4140 23:16:22.225101 ==
4141 23:16:22.228414 Dram Type= 6, Freq= 0, CH_0, rank 1
4142 23:16:22.231380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4143 23:16:22.231937 ==
4144 23:16:22.234408 Write leveling (Byte 0): 34 => 34
4145 23:16:22.238128 Write leveling (Byte 1): 33 => 33
4146 23:16:22.240897 DramcWriteLeveling(PI) end<-----
4147 23:16:22.241352
4148 23:16:22.241763 ==
4149 23:16:22.244700 Dram Type= 6, Freq= 0, CH_0, rank 1
4150 23:16:22.248095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4151 23:16:22.248641 ==
4152 23:16:22.251571 [Gating] SW mode calibration
4153 23:16:22.257860 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4154 23:16:22.264776 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4155 23:16:22.267844 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 23:16:22.271267 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 23:16:22.277855 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 23:16:22.280892 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
4159 23:16:22.284494 0 9 16 | B1->B0 | 2c2c 2626 | 1 0 | (1 0) (0 0)
4160 23:16:22.291288 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 23:16:22.294547 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 23:16:22.297754 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 23:16:22.301159 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 23:16:22.308039 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 23:16:22.311328 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 23:16:22.314673 0 10 12 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
4167 23:16:22.321159 0 10 16 | B1->B0 | 3d3d 4343 | 0 0 | (1 1) (0 0)
4168 23:16:22.324622 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 23:16:22.327496 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 23:16:22.334407 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 23:16:22.337732 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 23:16:22.341322 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 23:16:22.347725 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 23:16:22.350961 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 23:16:22.354163 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 23:16:22.361013 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 23:16:22.363894 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 23:16:22.367390 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 23:16:22.374140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 23:16:22.377995 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 23:16:22.380955 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 23:16:22.387345 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 23:16:22.391108 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 23:16:22.393952 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 23:16:22.400919 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 23:16:22.404082 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 23:16:22.407437 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 23:16:22.410708 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 23:16:22.417685 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 23:16:22.420996 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4191 23:16:22.424413 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 23:16:22.427926 Total UI for P1: 0, mck2ui 16
4193 23:16:22.430649 best dqsien dly found for B0: ( 0, 13, 12)
4194 23:16:22.434166 Total UI for P1: 0, mck2ui 16
4195 23:16:22.437315 best dqsien dly found for B1: ( 0, 13, 14)
4196 23:16:22.440496 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4197 23:16:22.447309 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4198 23:16:22.447872
4199 23:16:22.450606 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4200 23:16:22.453956 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4201 23:16:22.457169 [Gating] SW calibration Done
4202 23:16:22.457674 ==
4203 23:16:22.460561 Dram Type= 6, Freq= 0, CH_0, rank 1
4204 23:16:22.464050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4205 23:16:22.464628 ==
4206 23:16:22.467345 RX Vref Scan: 0
4207 23:16:22.467801
4208 23:16:22.468161 RX Vref 0 -> 0, step: 1
4209 23:16:22.468495
4210 23:16:22.470993 RX Delay -230 -> 252, step: 16
4211 23:16:22.474175 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4212 23:16:22.480697 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4213 23:16:22.484477 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4214 23:16:22.487469 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4215 23:16:22.490902 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4216 23:16:22.493934 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4217 23:16:22.500584 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4218 23:16:22.503924 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4219 23:16:22.507653 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4220 23:16:22.510350 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4221 23:16:22.517002 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4222 23:16:22.520666 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4223 23:16:22.524427 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4224 23:16:22.527233 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4225 23:16:22.533959 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4226 23:16:22.537466 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4227 23:16:22.538079 ==
4228 23:16:22.540750 Dram Type= 6, Freq= 0, CH_0, rank 1
4229 23:16:22.543831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4230 23:16:22.544341 ==
4231 23:16:22.544713 DQS Delay:
4232 23:16:22.547153 DQS0 = 0, DQS1 = 0
4233 23:16:22.547895 DQM Delay:
4234 23:16:22.550210 DQM0 = 53, DQM1 = 43
4235 23:16:22.550665 DQ Delay:
4236 23:16:22.553906 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4237 23:16:22.557023 DQ4 =57, DQ5 =41, DQ6 =65, DQ7 =65
4238 23:16:22.560315 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4239 23:16:22.563817 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4240 23:16:22.564277
4241 23:16:22.564636
4242 23:16:22.564970 ==
4243 23:16:22.567164 Dram Type= 6, Freq= 0, CH_0, rank 1
4244 23:16:22.570447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4245 23:16:22.573746 ==
4246 23:16:22.574199
4247 23:16:22.574558
4248 23:16:22.574892 TX Vref Scan disable
4249 23:16:22.576854 == TX Byte 0 ==
4250 23:16:22.580758 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4251 23:16:22.583496 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4252 23:16:22.587392 == TX Byte 1 ==
4253 23:16:22.590299 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4254 23:16:22.593412 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4255 23:16:22.597139 ==
4256 23:16:22.600129 Dram Type= 6, Freq= 0, CH_0, rank 1
4257 23:16:22.603497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4258 23:16:22.603912 ==
4259 23:16:22.604239
4260 23:16:22.604590
4261 23:16:22.606859 TX Vref Scan disable
4262 23:16:22.607271 == TX Byte 0 ==
4263 23:16:22.613639 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4264 23:16:22.616811 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4265 23:16:22.617225 == TX Byte 1 ==
4266 23:16:22.624010 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4267 23:16:22.626746 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4268 23:16:22.627160
4269 23:16:22.627485 [DATLAT]
4270 23:16:22.630199 Freq=600, CH0 RK1
4271 23:16:22.630618
4272 23:16:22.630943 DATLAT Default: 0x9
4273 23:16:22.633222 0, 0xFFFF, sum = 0
4274 23:16:22.633665 1, 0xFFFF, sum = 0
4275 23:16:22.636804 2, 0xFFFF, sum = 0
4276 23:16:22.640151 3, 0xFFFF, sum = 0
4277 23:16:22.640661 4, 0xFFFF, sum = 0
4278 23:16:22.643432 5, 0xFFFF, sum = 0
4279 23:16:22.643971 6, 0xFFFF, sum = 0
4280 23:16:22.646533 7, 0xFFFF, sum = 0
4281 23:16:22.647181 8, 0x0, sum = 1
4282 23:16:22.647633 9, 0x0, sum = 2
4283 23:16:22.649906 10, 0x0, sum = 3
4284 23:16:22.650317 11, 0x0, sum = 4
4285 23:16:22.653445 best_step = 9
4286 23:16:22.653902
4287 23:16:22.654228 ==
4288 23:16:22.656682 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 23:16:22.659989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 23:16:22.660400 ==
4291 23:16:22.663181 RX Vref Scan: 0
4292 23:16:22.663592
4293 23:16:22.663911 RX Vref 0 -> 0, step: 1
4294 23:16:22.664212
4295 23:16:22.666449 RX Delay -163 -> 252, step: 8
4296 23:16:22.673515 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4297 23:16:22.677087 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4298 23:16:22.680250 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4299 23:16:22.683553 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4300 23:16:22.687110 iDelay=205, Bit 4, Center 52 (-91 ~ 196) 288
4301 23:16:22.694223 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4302 23:16:22.697129 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4303 23:16:22.700482 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4304 23:16:22.704250 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4305 23:16:22.707156 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4306 23:16:22.713718 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4307 23:16:22.717059 iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288
4308 23:16:22.720380 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4309 23:16:22.723499 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4310 23:16:22.730271 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4311 23:16:22.733499 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4312 23:16:22.734110 ==
4313 23:16:22.737056 Dram Type= 6, Freq= 0, CH_0, rank 1
4314 23:16:22.740434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 23:16:22.740968 ==
4316 23:16:22.744008 DQS Delay:
4317 23:16:22.744514 DQS0 = 0, DQS1 = 0
4318 23:16:22.744951 DQM Delay:
4319 23:16:22.746793 DQM0 = 53, DQM1 = 45
4320 23:16:22.747203 DQ Delay:
4321 23:16:22.750107 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4322 23:16:22.753500 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4323 23:16:22.756735 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4324 23:16:22.760084 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4325 23:16:22.760497
4326 23:16:22.760821
4327 23:16:22.769957 [DQSOSCAuto] RK1, (LSB)MR18= 0x6323, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4328 23:16:22.770376 CH0 RK1: MR19=808, MR18=6323
4329 23:16:22.776398 CH0_RK1: MR19=0x808, MR18=0x6323, DQSOSC=391, MR23=63, INC=171, DEC=114
4330 23:16:22.779554 [RxdqsGatingPostProcess] freq 600
4331 23:16:22.786548 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4332 23:16:22.790183 Pre-setting of DQS Precalculation
4333 23:16:22.793333 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4334 23:16:22.793785 ==
4335 23:16:22.796666 Dram Type= 6, Freq= 0, CH_1, rank 0
4336 23:16:22.803441 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4337 23:16:22.804010 ==
4338 23:16:22.806255 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4339 23:16:22.813206 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4340 23:16:22.816646 [CA 0] Center 36 (5~67) winsize 63
4341 23:16:22.820139 [CA 1] Center 36 (5~67) winsize 63
4342 23:16:22.823545 [CA 2] Center 34 (4~65) winsize 62
4343 23:16:22.826844 [CA 3] Center 34 (4~65) winsize 62
4344 23:16:22.830443 [CA 4] Center 34 (4~65) winsize 62
4345 23:16:22.833273 [CA 5] Center 33 (3~64) winsize 62
4346 23:16:22.833800
4347 23:16:22.836144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4348 23:16:22.836629
4349 23:16:22.839978 [CATrainingPosCal] consider 1 rank data
4350 23:16:22.843104 u2DelayCellTimex100 = 270/100 ps
4351 23:16:22.846697 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4352 23:16:22.849799 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4353 23:16:22.856674 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4354 23:16:22.859704 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4355 23:16:22.862626 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4356 23:16:22.866378 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4357 23:16:22.866835
4358 23:16:22.869229 CA PerBit enable=1, Macro0, CA PI delay=33
4359 23:16:22.869752
4360 23:16:22.873226 [CBTSetCACLKResult] CA Dly = 33
4361 23:16:22.873863 CS Dly: 5 (0~36)
4362 23:16:22.874240 ==
4363 23:16:22.876216 Dram Type= 6, Freq= 0, CH_1, rank 1
4364 23:16:22.883101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 23:16:22.883623 ==
4366 23:16:22.886106 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4367 23:16:22.893087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4368 23:16:22.896543 [CA 0] Center 36 (5~67) winsize 63
4369 23:16:22.900135 [CA 1] Center 36 (5~67) winsize 63
4370 23:16:22.903743 [CA 2] Center 35 (4~66) winsize 63
4371 23:16:22.906340 [CA 3] Center 34 (4~65) winsize 62
4372 23:16:22.910159 [CA 4] Center 35 (4~66) winsize 63
4373 23:16:22.913573 [CA 5] Center 34 (3~65) winsize 63
4374 23:16:22.914199
4375 23:16:22.916647 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4376 23:16:22.917101
4377 23:16:22.919461 [CATrainingPosCal] consider 2 rank data
4378 23:16:22.923555 u2DelayCellTimex100 = 270/100 ps
4379 23:16:22.926131 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4380 23:16:22.929555 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4381 23:16:22.936084 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4382 23:16:22.939697 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4383 23:16:22.943037 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 23:16:22.946664 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4385 23:16:22.947235
4386 23:16:22.949946 CA PerBit enable=1, Macro0, CA PI delay=33
4387 23:16:22.950408
4388 23:16:22.952856 [CBTSetCACLKResult] CA Dly = 33
4389 23:16:22.953315 CS Dly: 5 (0~37)
4390 23:16:22.953739
4391 23:16:22.956671 ----->DramcWriteLeveling(PI) begin...
4392 23:16:22.959332 ==
4393 23:16:22.962879 Dram Type= 6, Freq= 0, CH_1, rank 0
4394 23:16:22.966345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4395 23:16:22.966812 ==
4396 23:16:22.969637 Write leveling (Byte 0): 32 => 32
4397 23:16:22.973446 Write leveling (Byte 1): 30 => 30
4398 23:16:22.976359 DramcWriteLeveling(PI) end<-----
4399 23:16:22.976821
4400 23:16:22.977180 ==
4401 23:16:22.979630 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 23:16:22.982742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 23:16:22.983328 ==
4404 23:16:22.986075 [Gating] SW mode calibration
4405 23:16:22.992910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4406 23:16:22.996108 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4407 23:16:23.003078 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 23:16:23.006585 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 23:16:23.009531 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4410 23:16:23.016344 0 9 12 | B1->B0 | 2e2e 2e2e | 0 0 | (1 0) (1 0)
4411 23:16:23.019721 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 23:16:23.023360 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 23:16:23.029725 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 23:16:23.032788 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 23:16:23.036666 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 23:16:23.043355 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 23:16:23.045940 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4418 23:16:23.049467 0 10 12 | B1->B0 | 3333 3a3a | 0 0 | (0 0) (0 0)
4419 23:16:23.056208 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 23:16:23.059581 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 23:16:23.062688 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 23:16:23.069620 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 23:16:23.072963 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 23:16:23.076145 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 23:16:23.082699 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 23:16:23.086216 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4427 23:16:23.089830 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 23:16:23.092727 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 23:16:23.099699 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 23:16:23.103067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 23:16:23.109152 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 23:16:23.112404 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 23:16:23.115900 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 23:16:23.119427 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 23:16:23.126081 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 23:16:23.129354 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 23:16:23.135925 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 23:16:23.139248 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 23:16:23.141973 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 23:16:23.145820 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 23:16:23.152287 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 23:16:23.155813 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4443 23:16:23.158918 Total UI for P1: 0, mck2ui 16
4444 23:16:23.162184 best dqsien dly found for B1: ( 0, 13, 10)
4445 23:16:23.165430 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4446 23:16:23.168718 Total UI for P1: 0, mck2ui 16
4447 23:16:23.171833 best dqsien dly found for B0: ( 0, 13, 12)
4448 23:16:23.175167 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4449 23:16:23.181861 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4450 23:16:23.182314
4451 23:16:23.185218 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4452 23:16:23.188438 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4453 23:16:23.191745 [Gating] SW calibration Done
4454 23:16:23.192152 ==
4455 23:16:23.195306 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 23:16:23.198743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 23:16:23.199317 ==
4458 23:16:23.201370 RX Vref Scan: 0
4459 23:16:23.201835
4460 23:16:23.202159 RX Vref 0 -> 0, step: 1
4461 23:16:23.202463
4462 23:16:23.204662 RX Delay -230 -> 252, step: 16
4463 23:16:23.208158 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4464 23:16:23.214963 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4465 23:16:23.218106 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4466 23:16:23.221680 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4467 23:16:23.225274 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4468 23:16:23.231619 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4469 23:16:23.234782 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4470 23:16:23.238228 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4471 23:16:23.241179 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4472 23:16:23.244921 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4473 23:16:23.252148 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4474 23:16:23.254970 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4475 23:16:23.258293 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4476 23:16:23.261730 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4477 23:16:23.268578 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4478 23:16:23.271759 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4479 23:16:23.272218 ==
4480 23:16:23.274892 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 23:16:23.277962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 23:16:23.278379 ==
4483 23:16:23.281194 DQS Delay:
4484 23:16:23.281635 DQS0 = 0, DQS1 = 0
4485 23:16:23.281972 DQM Delay:
4486 23:16:23.285208 DQM0 = 50, DQM1 = 46
4487 23:16:23.285776 DQ Delay:
4488 23:16:23.287731 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4489 23:16:23.291145 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4490 23:16:23.294385 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4491 23:16:23.297777 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4492 23:16:23.298192
4493 23:16:23.298541
4494 23:16:23.298945 ==
4495 23:16:23.301319 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 23:16:23.308474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 23:16:23.309026 ==
4498 23:16:23.309361
4499 23:16:23.309717
4500 23:16:23.310015 TX Vref Scan disable
4501 23:16:23.311595 == TX Byte 0 ==
4502 23:16:23.315143 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4503 23:16:23.318590 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4504 23:16:23.321947 == TX Byte 1 ==
4505 23:16:23.325306 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4506 23:16:23.331589 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4507 23:16:23.332131 ==
4508 23:16:23.334939 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 23:16:23.338296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 23:16:23.338856 ==
4511 23:16:23.339199
4512 23:16:23.339500
4513 23:16:23.341217 TX Vref Scan disable
4514 23:16:23.344613 == TX Byte 0 ==
4515 23:16:23.348323 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4516 23:16:23.351538 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4517 23:16:23.355145 == TX Byte 1 ==
4518 23:16:23.357982 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4519 23:16:23.361495 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4520 23:16:23.362176
4521 23:16:23.362513 [DATLAT]
4522 23:16:23.364829 Freq=600, CH1 RK0
4523 23:16:23.365463
4524 23:16:23.365862 DATLAT Default: 0x9
4525 23:16:23.368272 0, 0xFFFF, sum = 0
4526 23:16:23.371469 1, 0xFFFF, sum = 0
4527 23:16:23.371889 2, 0xFFFF, sum = 0
4528 23:16:23.374990 3, 0xFFFF, sum = 0
4529 23:16:23.375523 4, 0xFFFF, sum = 0
4530 23:16:23.377980 5, 0xFFFF, sum = 0
4531 23:16:23.378460 6, 0xFFFF, sum = 0
4532 23:16:23.381110 7, 0xFFFF, sum = 0
4533 23:16:23.381709 8, 0x0, sum = 1
4534 23:16:23.384511 9, 0x0, sum = 2
4535 23:16:23.384971 10, 0x0, sum = 3
4536 23:16:23.385305 11, 0x0, sum = 4
4537 23:16:23.388135 best_step = 9
4538 23:16:23.388637
4539 23:16:23.388963 ==
4540 23:16:23.391159 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 23:16:23.394542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 23:16:23.394971 ==
4543 23:16:23.397642 RX Vref Scan: 1
4544 23:16:23.398072
4545 23:16:23.398398 RX Vref 0 -> 0, step: 1
4546 23:16:23.401172
4547 23:16:23.401743 RX Delay -163 -> 252, step: 8
4548 23:16:23.402085
4549 23:16:23.404525 Set Vref, RX VrefLevel [Byte0]: 57
4550 23:16:23.407552 [Byte1]: 48
4551 23:16:23.412250
4552 23:16:23.412747 Final RX Vref Byte 0 = 57 to rank0
4553 23:16:23.415597 Final RX Vref Byte 1 = 48 to rank0
4554 23:16:23.418893 Final RX Vref Byte 0 = 57 to rank1
4555 23:16:23.422199 Final RX Vref Byte 1 = 48 to rank1==
4556 23:16:23.425392 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 23:16:23.432216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 23:16:23.432746 ==
4559 23:16:23.433111 DQS Delay:
4560 23:16:23.433448 DQS0 = 0, DQS1 = 0
4561 23:16:23.435346 DQM Delay:
4562 23:16:23.435801 DQM0 = 49, DQM1 = 45
4563 23:16:23.438719 DQ Delay:
4564 23:16:23.442296 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4565 23:16:23.442754 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4566 23:16:23.445378 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =40
4567 23:16:23.448925 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4568 23:16:23.452278
4569 23:16:23.452728
4570 23:16:23.458546 [DQSOSCAuto] RK0, (LSB)MR18= 0x466b, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4571 23:16:23.462648 CH1 RK0: MR19=808, MR18=466B
4572 23:16:23.468619 CH1_RK0: MR19=0x808, MR18=0x466B, DQSOSC=389, MR23=63, INC=173, DEC=115
4573 23:16:23.469081
4574 23:16:23.471733 ----->DramcWriteLeveling(PI) begin...
4575 23:16:23.472200 ==
4576 23:16:23.475022 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 23:16:23.478579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 23:16:23.479043 ==
4579 23:16:23.481759 Write leveling (Byte 0): 29 => 29
4580 23:16:23.485068 Write leveling (Byte 1): 32 => 32
4581 23:16:23.488568 DramcWriteLeveling(PI) end<-----
4582 23:16:23.489093
4583 23:16:23.489456 ==
4584 23:16:23.491878 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 23:16:23.495270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 23:16:23.495732 ==
4587 23:16:23.498313 [Gating] SW mode calibration
4588 23:16:23.504949 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 23:16:23.511727 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 23:16:23.515567 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 23:16:23.518158 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 23:16:23.525052 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 23:16:23.528281 0 9 12 | B1->B0 | 2e2e 3030 | 1 1 | (1 0) (1 0)
4594 23:16:23.531633 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 23:16:23.538356 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 23:16:23.541565 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 23:16:23.545037 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 23:16:23.551890 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 23:16:23.554778 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 23:16:23.558257 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 23:16:23.564806 0 10 12 | B1->B0 | 3636 3737 | 0 0 | (0 0) (0 0)
4602 23:16:23.568228 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4603 23:16:23.571455 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 23:16:23.578165 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 23:16:23.581326 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 23:16:23.584971 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 23:16:23.591739 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 23:16:23.594865 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 23:16:23.598012 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4610 23:16:23.604497 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 23:16:23.607909 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 23:16:23.611286 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 23:16:23.617749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 23:16:23.621026 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 23:16:23.624702 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 23:16:23.630995 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 23:16:23.634425 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 23:16:23.637767 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 23:16:23.644685 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 23:16:23.647896 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 23:16:23.651613 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 23:16:23.657516 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 23:16:23.660698 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 23:16:23.664579 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4625 23:16:23.670837 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4626 23:16:23.674331 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4627 23:16:23.677252 Total UI for P1: 0, mck2ui 16
4628 23:16:23.680726 best dqsien dly found for B0: ( 0, 13, 10)
4629 23:16:23.684078 Total UI for P1: 0, mck2ui 16
4630 23:16:23.687347 best dqsien dly found for B1: ( 0, 13, 12)
4631 23:16:23.690690 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4632 23:16:23.694140 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4633 23:16:23.694552
4634 23:16:23.697675 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 23:16:23.701127 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4636 23:16:23.704110 [Gating] SW calibration Done
4637 23:16:23.704520 ==
4638 23:16:23.707364 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 23:16:23.710968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 23:16:23.711382 ==
4641 23:16:23.713996 RX Vref Scan: 0
4642 23:16:23.714404
4643 23:16:23.717269 RX Vref 0 -> 0, step: 1
4644 23:16:23.717716
4645 23:16:23.718051 RX Delay -230 -> 252, step: 16
4646 23:16:23.723858 iDelay=218, Bit 0, Center 65 (-86 ~ 217) 304
4647 23:16:23.727498 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4648 23:16:23.730664 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4649 23:16:23.734382 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4650 23:16:23.740901 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4651 23:16:23.743893 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4652 23:16:23.747315 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4653 23:16:23.750508 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4654 23:16:23.754052 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4655 23:16:23.760608 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4656 23:16:23.763774 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4657 23:16:23.767159 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4658 23:16:23.770688 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4659 23:16:23.777277 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4660 23:16:23.780473 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4661 23:16:23.783851 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4662 23:16:23.784311 ==
4663 23:16:23.787215 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 23:16:23.790221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 23:16:23.793481 ==
4666 23:16:23.794009 DQS Delay:
4667 23:16:23.794368 DQS0 = 0, DQS1 = 0
4668 23:16:23.797257 DQM Delay:
4669 23:16:23.797767 DQM0 = 52, DQM1 = 47
4670 23:16:23.800489 DQ Delay:
4671 23:16:23.801042 DQ0 =65, DQ1 =41, DQ2 =33, DQ3 =49
4672 23:16:23.803591 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4673 23:16:23.807214 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4674 23:16:23.810235 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =65
4675 23:16:23.810689
4676 23:16:23.811044
4677 23:16:23.813916 ==
4678 23:16:23.817325 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 23:16:23.820423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 23:16:23.820969 ==
4681 23:16:23.821333
4682 23:16:23.821707
4683 23:16:23.823836 TX Vref Scan disable
4684 23:16:23.824390 == TX Byte 0 ==
4685 23:16:23.830161 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4686 23:16:23.833728 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4687 23:16:23.834279 == TX Byte 1 ==
4688 23:16:23.840825 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4689 23:16:23.844314 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4690 23:16:23.844768 ==
4691 23:16:23.846859 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 23:16:23.850591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 23:16:23.851048 ==
4694 23:16:23.851406
4695 23:16:23.851734
4696 23:16:23.853499 TX Vref Scan disable
4697 23:16:23.857208 == TX Byte 0 ==
4698 23:16:23.860259 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4699 23:16:23.863333 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4700 23:16:23.866822 == TX Byte 1 ==
4701 23:16:23.870493 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4702 23:16:23.873497 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4703 23:16:23.873999
4704 23:16:23.876918 [DATLAT]
4705 23:16:23.877443 Freq=600, CH1 RK1
4706 23:16:23.877870
4707 23:16:23.880057 DATLAT Default: 0x9
4708 23:16:23.880517 0, 0xFFFF, sum = 0
4709 23:16:23.883778 1, 0xFFFF, sum = 0
4710 23:16:23.884242 2, 0xFFFF, sum = 0
4711 23:16:23.886611 3, 0xFFFF, sum = 0
4712 23:16:23.887081 4, 0xFFFF, sum = 0
4713 23:16:23.890018 5, 0xFFFF, sum = 0
4714 23:16:23.890479 6, 0xFFFF, sum = 0
4715 23:16:23.893143 7, 0xFFFF, sum = 0
4716 23:16:23.893626 8, 0x0, sum = 1
4717 23:16:23.896740 9, 0x0, sum = 2
4718 23:16:23.897203 10, 0x0, sum = 3
4719 23:16:23.900226 11, 0x0, sum = 4
4720 23:16:23.900645 best_step = 9
4721 23:16:23.900976
4722 23:16:23.901281 ==
4723 23:16:23.903337 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 23:16:23.906714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 23:16:23.909687 ==
4726 23:16:23.910104 RX Vref Scan: 0
4727 23:16:23.910434
4728 23:16:23.913213 RX Vref 0 -> 0, step: 1
4729 23:16:23.913666
4730 23:16:23.916545 RX Delay -163 -> 252, step: 8
4731 23:16:23.919935 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4732 23:16:23.923454 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4733 23:16:23.930037 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4734 23:16:23.932999 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4735 23:16:23.936768 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4736 23:16:23.940231 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4737 23:16:23.942812 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4738 23:16:23.949893 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4739 23:16:23.953264 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4740 23:16:23.956462 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4741 23:16:23.959739 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4742 23:16:23.966506 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4743 23:16:23.969717 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4744 23:16:23.972851 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4745 23:16:23.976648 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4746 23:16:23.979736 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4747 23:16:23.980223 ==
4748 23:16:23.982776 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 23:16:23.989352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 23:16:23.989888 ==
4751 23:16:23.990434 DQS Delay:
4752 23:16:23.993039 DQS0 = 0, DQS1 = 0
4753 23:16:23.993656 DQM Delay:
4754 23:16:23.995970 DQM0 = 48, DQM1 = 46
4755 23:16:23.996425 DQ Delay:
4756 23:16:23.999482 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4757 23:16:24.003077 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4758 23:16:24.006138 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4759 23:16:24.009317 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4760 23:16:24.009926
4761 23:16:24.010298
4762 23:16:24.015873 [DQSOSCAuto] RK1, (LSB)MR18= 0x6a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4763 23:16:24.019056 CH1 RK1: MR19=808, MR18=6A21
4764 23:16:24.026409 CH1_RK1: MR19=0x808, MR18=0x6A21, DQSOSC=389, MR23=63, INC=173, DEC=115
4765 23:16:24.029308 [RxdqsGatingPostProcess] freq 600
4766 23:16:24.036050 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 23:16:24.036611 Pre-setting of DQS Precalculation
4768 23:16:24.042686 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 23:16:24.049474 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 23:16:24.055761 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 23:16:24.056325
4772 23:16:24.056693
4773 23:16:24.059072 [Calibration Summary] 1200 Mbps
4774 23:16:24.062328 CH 0, Rank 0
4775 23:16:24.062786 SW Impedance : PASS
4776 23:16:24.065895 DUTY Scan : NO K
4777 23:16:24.069187 ZQ Calibration : PASS
4778 23:16:24.069806 Jitter Meter : NO K
4779 23:16:24.072447 CBT Training : PASS
4780 23:16:24.073012 Write leveling : PASS
4781 23:16:24.076139 RX DQS gating : PASS
4782 23:16:24.078908 RX DQ/DQS(RDDQC) : PASS
4783 23:16:24.079366 TX DQ/DQS : PASS
4784 23:16:24.081916 RX DATLAT : PASS
4785 23:16:24.085425 RX DQ/DQS(Engine): PASS
4786 23:16:24.086003 TX OE : NO K
4787 23:16:24.088672 All Pass.
4788 23:16:24.089130
4789 23:16:24.089492 CH 0, Rank 1
4790 23:16:24.092667 SW Impedance : PASS
4791 23:16:24.093220 DUTY Scan : NO K
4792 23:16:24.095868 ZQ Calibration : PASS
4793 23:16:24.099150 Jitter Meter : NO K
4794 23:16:24.099712 CBT Training : PASS
4795 23:16:24.102252 Write leveling : PASS
4796 23:16:24.105873 RX DQS gating : PASS
4797 23:16:24.106417 RX DQ/DQS(RDDQC) : PASS
4798 23:16:24.109081 TX DQ/DQS : PASS
4799 23:16:24.112182 RX DATLAT : PASS
4800 23:16:24.112738 RX DQ/DQS(Engine): PASS
4801 23:16:24.115948 TX OE : NO K
4802 23:16:24.116481 All Pass.
4803 23:16:24.116921
4804 23:16:24.118873 CH 1, Rank 0
4805 23:16:24.119333 SW Impedance : PASS
4806 23:16:24.121943 DUTY Scan : NO K
4807 23:16:24.122401 ZQ Calibration : PASS
4808 23:16:24.125486 Jitter Meter : NO K
4809 23:16:24.128737 CBT Training : PASS
4810 23:16:24.129218 Write leveling : PASS
4811 23:16:24.132268 RX DQS gating : PASS
4812 23:16:24.135543 RX DQ/DQS(RDDQC) : PASS
4813 23:16:24.136115 TX DQ/DQS : PASS
4814 23:16:24.138632 RX DATLAT : PASS
4815 23:16:24.142502 RX DQ/DQS(Engine): PASS
4816 23:16:24.143053 TX OE : NO K
4817 23:16:24.145455 All Pass.
4818 23:16:24.146078
4819 23:16:24.146445 CH 1, Rank 1
4820 23:16:24.148795 SW Impedance : PASS
4821 23:16:24.149247 DUTY Scan : NO K
4822 23:16:24.152019 ZQ Calibration : PASS
4823 23:16:24.155402 Jitter Meter : NO K
4824 23:16:24.156199 CBT Training : PASS
4825 23:16:24.158611 Write leveling : PASS
4826 23:16:24.161630 RX DQS gating : PASS
4827 23:16:24.162118 RX DQ/DQS(RDDQC) : PASS
4828 23:16:24.164962 TX DQ/DQS : PASS
4829 23:16:24.168533 RX DATLAT : PASS
4830 23:16:24.169101 RX DQ/DQS(Engine): PASS
4831 23:16:24.171744 TX OE : NO K
4832 23:16:24.172350 All Pass.
4833 23:16:24.172725
4834 23:16:24.175149 DramC Write-DBI off
4835 23:16:24.178920 PER_BANK_REFRESH: Hybrid Mode
4836 23:16:24.179396 TX_TRACKING: ON
4837 23:16:24.188950 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 23:16:24.192202 [FAST_K] Save calibration result to emmc
4839 23:16:24.195433 dramc_set_vcore_voltage set vcore to 662500
4840 23:16:24.195895 Read voltage for 933, 3
4841 23:16:24.198737 Vio18 = 0
4842 23:16:24.199197 Vcore = 662500
4843 23:16:24.199559 Vdram = 0
4844 23:16:24.201688 Vddq = 0
4845 23:16:24.202149 Vmddr = 0
4846 23:16:24.208615 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 23:16:24.211945 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 23:16:24.214861 MEM_TYPE=3, freq_sel=17
4849 23:16:24.218292 sv_algorithm_assistance_LP4_1600
4850 23:16:24.221679 ============ PULL DRAM RESETB DOWN ============
4851 23:16:24.224697 ========== PULL DRAM RESETB DOWN end =========
4852 23:16:24.231775 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 23:16:24.235345 ===================================
4854 23:16:24.235917 LPDDR4 DRAM CONFIGURATION
4855 23:16:24.237902 ===================================
4856 23:16:24.241399 EX_ROW_EN[0] = 0x0
4857 23:16:24.244880 EX_ROW_EN[1] = 0x0
4858 23:16:24.245450 LP4Y_EN = 0x0
4859 23:16:24.248071 WORK_FSP = 0x0
4860 23:16:24.248643 WL = 0x3
4861 23:16:24.251379 RL = 0x3
4862 23:16:24.251799 BL = 0x2
4863 23:16:24.254714 RPST = 0x0
4864 23:16:24.255173 RD_PRE = 0x0
4865 23:16:24.258194 WR_PRE = 0x1
4866 23:16:24.258651 WR_PST = 0x0
4867 23:16:24.261071 DBI_WR = 0x0
4868 23:16:24.261509 DBI_RD = 0x0
4869 23:16:24.264789 OTF = 0x1
4870 23:16:24.268225 ===================================
4871 23:16:24.271341 ===================================
4872 23:16:24.271802 ANA top config
4873 23:16:24.274661 ===================================
4874 23:16:24.277991 DLL_ASYNC_EN = 0
4875 23:16:24.281348 ALL_SLAVE_EN = 1
4876 23:16:24.282055 NEW_RANK_MODE = 1
4877 23:16:24.284650 DLL_IDLE_MODE = 1
4878 23:16:24.288411 LP45_APHY_COMB_EN = 1
4879 23:16:24.292005 TX_ODT_DIS = 1
4880 23:16:24.295488 NEW_8X_MODE = 1
4881 23:16:24.298305 ===================================
4882 23:16:24.301293 ===================================
4883 23:16:24.301800 data_rate = 1866
4884 23:16:24.304614 CKR = 1
4885 23:16:24.308433 DQ_P2S_RATIO = 8
4886 23:16:24.311652 ===================================
4887 23:16:24.314900 CA_P2S_RATIO = 8
4888 23:16:24.317794 DQ_CA_OPEN = 0
4889 23:16:24.321140 DQ_SEMI_OPEN = 0
4890 23:16:24.321743 CA_SEMI_OPEN = 0
4891 23:16:24.324707 CA_FULL_RATE = 0
4892 23:16:24.328261 DQ_CKDIV4_EN = 1
4893 23:16:24.331533 CA_CKDIV4_EN = 1
4894 23:16:24.334476 CA_PREDIV_EN = 0
4895 23:16:24.337952 PH8_DLY = 0
4896 23:16:24.338437 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 23:16:24.341231 DQ_AAMCK_DIV = 4
4898 23:16:24.344960 CA_AAMCK_DIV = 4
4899 23:16:24.347715 CA_ADMCK_DIV = 4
4900 23:16:24.351052 DQ_TRACK_CA_EN = 0
4901 23:16:24.354709 CA_PICK = 933
4902 23:16:24.355264 CA_MCKIO = 933
4903 23:16:24.357823 MCKIO_SEMI = 0
4904 23:16:24.360853 PLL_FREQ = 3732
4905 23:16:24.364360 DQ_UI_PI_RATIO = 32
4906 23:16:24.367850 CA_UI_PI_RATIO = 0
4907 23:16:24.370910 ===================================
4908 23:16:24.374129 ===================================
4909 23:16:24.377934 memory_type:LPDDR4
4910 23:16:24.378489 GP_NUM : 10
4911 23:16:24.380781 SRAM_EN : 1
4912 23:16:24.381238 MD32_EN : 0
4913 23:16:24.384424 ===================================
4914 23:16:24.387988 [ANA_INIT] >>>>>>>>>>>>>>
4915 23:16:24.390677 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 23:16:24.394086 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 23:16:24.397554 ===================================
4918 23:16:24.401407 data_rate = 1866,PCW = 0X8f00
4919 23:16:24.404422 ===================================
4920 23:16:24.408112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 23:16:24.414520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 23:16:24.417791 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 23:16:24.424361 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 23:16:24.427930 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 23:16:24.431221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 23:16:24.431782 [ANA_INIT] flow start
4927 23:16:24.434257 [ANA_INIT] PLL >>>>>>>>
4928 23:16:24.437443 [ANA_INIT] PLL <<<<<<<<
4929 23:16:24.438100 [ANA_INIT] MIDPI >>>>>>>>
4930 23:16:24.440890 [ANA_INIT] MIDPI <<<<<<<<
4931 23:16:24.444344 [ANA_INIT] DLL >>>>>>>>
4932 23:16:24.444805 [ANA_INIT] flow end
4933 23:16:24.451094 ============ LP4 DIFF to SE enter ============
4934 23:16:24.454591 ============ LP4 DIFF to SE exit ============
4935 23:16:24.455137 [ANA_INIT] <<<<<<<<<<<<<
4936 23:16:24.457356 [Flow] Enable top DCM control >>>>>
4937 23:16:24.460713 [Flow] Enable top DCM control <<<<<
4938 23:16:24.464214 Enable DLL master slave shuffle
4939 23:16:24.470568 ==============================================================
4940 23:16:24.474243 Gating Mode config
4941 23:16:24.477500 ==============================================================
4942 23:16:24.481435 Config description:
4943 23:16:24.490727 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 23:16:24.497404 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 23:16:24.500943 SELPH_MODE 0: By rank 1: By Phase
4946 23:16:24.507653 ==============================================================
4947 23:16:24.510588 GAT_TRACK_EN = 1
4948 23:16:24.513897 RX_GATING_MODE = 2
4949 23:16:24.517530 RX_GATING_TRACK_MODE = 2
4950 23:16:24.518230 SELPH_MODE = 1
4951 23:16:24.520475 PICG_EARLY_EN = 1
4952 23:16:24.523731 VALID_LAT_VALUE = 1
4953 23:16:24.530393 ==============================================================
4954 23:16:24.534059 Enter into Gating configuration >>>>
4955 23:16:24.537001 Exit from Gating configuration <<<<
4956 23:16:24.540645 Enter into DVFS_PRE_config >>>>>
4957 23:16:24.550126 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 23:16:24.554011 Exit from DVFS_PRE_config <<<<<
4959 23:16:24.557299 Enter into PICG configuration >>>>
4960 23:16:24.560257 Exit from PICG configuration <<<<
4961 23:16:24.563377 [RX_INPUT] configuration >>>>>
4962 23:16:24.567156 [RX_INPUT] configuration <<<<<
4963 23:16:24.570408 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 23:16:24.576955 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 23:16:24.583315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 23:16:24.590071 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 23:16:24.596641 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 23:16:24.600083 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 23:16:24.606462 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 23:16:24.609913 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 23:16:24.613599 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 23:16:24.616416 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 23:16:24.619902 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 23:16:24.626732 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 23:16:24.629510 ===================================
4976 23:16:24.633051 LPDDR4 DRAM CONFIGURATION
4977 23:16:24.636570 ===================================
4978 23:16:24.636751 EX_ROW_EN[0] = 0x0
4979 23:16:24.639259 EX_ROW_EN[1] = 0x0
4980 23:16:24.639408 LP4Y_EN = 0x0
4981 23:16:24.643004 WORK_FSP = 0x0
4982 23:16:24.643133 WL = 0x3
4983 23:16:24.646132 RL = 0x3
4984 23:16:24.646261 BL = 0x2
4985 23:16:24.649260 RPST = 0x0
4986 23:16:24.649373 RD_PRE = 0x0
4987 23:16:24.653307 WR_PRE = 0x1
4988 23:16:24.653409 WR_PST = 0x0
4989 23:16:24.655833 DBI_WR = 0x0
4990 23:16:24.655937 DBI_RD = 0x0
4991 23:16:24.659387 OTF = 0x1
4992 23:16:24.662907 ===================================
4993 23:16:24.665855 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 23:16:24.669121 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 23:16:24.675802 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 23:16:24.679215 ===================================
4997 23:16:24.679298 LPDDR4 DRAM CONFIGURATION
4998 23:16:24.682626 ===================================
4999 23:16:24.686665 EX_ROW_EN[0] = 0x10
5000 23:16:24.689435 EX_ROW_EN[1] = 0x0
5001 23:16:24.689542 LP4Y_EN = 0x0
5002 23:16:24.692824 WORK_FSP = 0x0
5003 23:16:24.692906 WL = 0x3
5004 23:16:24.696243 RL = 0x3
5005 23:16:24.696327 BL = 0x2
5006 23:16:24.699370 RPST = 0x0
5007 23:16:24.699452 RD_PRE = 0x0
5008 23:16:24.702777 WR_PRE = 0x1
5009 23:16:24.702856 WR_PST = 0x0
5010 23:16:24.706022 DBI_WR = 0x0
5011 23:16:24.706105 DBI_RD = 0x0
5012 23:16:24.709093 OTF = 0x1
5013 23:16:24.713061 ===================================
5014 23:16:24.719348 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 23:16:24.722593 nWR fixed to 30
5016 23:16:24.725926 [ModeRegInit_LP4] CH0 RK0
5017 23:16:24.726007 [ModeRegInit_LP4] CH0 RK1
5018 23:16:24.729288 [ModeRegInit_LP4] CH1 RK0
5019 23:16:24.732808 [ModeRegInit_LP4] CH1 RK1
5020 23:16:24.732889 match AC timing 9
5021 23:16:24.739530 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 23:16:24.742505 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 23:16:24.745572 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 23:16:24.752678 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 23:16:24.755739 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 23:16:24.755820 ==
5027 23:16:24.758881 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 23:16:24.762131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 23:16:24.762211 ==
5030 23:16:24.768825 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 23:16:24.775450 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5032 23:16:24.778908 [CA 0] Center 37 (6~68) winsize 63
5033 23:16:24.782382 [CA 1] Center 37 (7~68) winsize 62
5034 23:16:24.785509 [CA 2] Center 34 (4~65) winsize 62
5035 23:16:24.789283 [CA 3] Center 34 (3~65) winsize 63
5036 23:16:24.792725 [CA 4] Center 33 (3~64) winsize 62
5037 23:16:24.795473 [CA 5] Center 32 (2~62) winsize 61
5038 23:16:24.795561
5039 23:16:24.799375 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5040 23:16:24.799467
5041 23:16:24.802000 [CATrainingPosCal] consider 1 rank data
5042 23:16:24.805711 u2DelayCellTimex100 = 270/100 ps
5043 23:16:24.808687 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5044 23:16:24.812110 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 23:16:24.815490 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5046 23:16:24.818985 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5047 23:16:24.822454 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5048 23:16:24.825934 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5049 23:16:24.826054
5050 23:16:24.832373 CA PerBit enable=1, Macro0, CA PI delay=32
5051 23:16:24.832508
5052 23:16:24.832613 [CBTSetCACLKResult] CA Dly = 32
5053 23:16:24.835354 CS Dly: 5 (0~36)
5054 23:16:24.835485 ==
5055 23:16:24.838848 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 23:16:24.842391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 23:16:24.842523 ==
5058 23:16:24.848842 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 23:16:24.855881 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5060 23:16:24.859380 [CA 0] Center 37 (6~68) winsize 63
5061 23:16:24.862639 [CA 1] Center 37 (7~68) winsize 62
5062 23:16:24.866121 [CA 2] Center 34 (4~65) winsize 62
5063 23:16:24.869565 [CA 3] Center 34 (3~65) winsize 63
5064 23:16:24.872609 [CA 4] Center 33 (3~63) winsize 61
5065 23:16:24.876190 [CA 5] Center 32 (2~63) winsize 62
5066 23:16:24.876600
5067 23:16:24.879264 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5068 23:16:24.879554
5069 23:16:24.882398 [CATrainingPosCal] consider 2 rank data
5070 23:16:24.885810 u2DelayCellTimex100 = 270/100 ps
5071 23:16:24.889353 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5072 23:16:24.892195 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 23:16:24.895276 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5074 23:16:24.898881 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5075 23:16:24.902074 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5076 23:16:24.905189 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5077 23:16:24.908770
5078 23:16:24.912363 CA PerBit enable=1, Macro0, CA PI delay=32
5079 23:16:24.912464
5080 23:16:24.915169 [CBTSetCACLKResult] CA Dly = 32
5081 23:16:24.915295 CS Dly: 5 (0~37)
5082 23:16:24.915404
5083 23:16:24.918416 ----->DramcWriteLeveling(PI) begin...
5084 23:16:24.918500 ==
5085 23:16:24.921719 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 23:16:24.925188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 23:16:24.928198 ==
5088 23:16:24.928281 Write leveling (Byte 0): 34 => 34
5089 23:16:24.931567 Write leveling (Byte 1): 30 => 30
5090 23:16:24.934989 DramcWriteLeveling(PI) end<-----
5091 23:16:24.935097
5092 23:16:24.935192 ==
5093 23:16:24.938368 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 23:16:24.945233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 23:16:24.945354 ==
5096 23:16:24.945457 [Gating] SW mode calibration
5097 23:16:24.955052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 23:16:24.958441 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 23:16:24.965123 0 14 0 | B1->B0 | 2626 3434 | 1 1 | (0 0) (1 1)
5100 23:16:24.968826 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5101 23:16:24.971557 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 23:16:24.975174 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 23:16:24.981513 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 23:16:24.984995 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 23:16:24.988184 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
5106 23:16:24.994744 0 14 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
5107 23:16:24.997981 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
5108 23:16:25.001348 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 23:16:25.008026 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 23:16:25.011773 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 23:16:25.014604 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 23:16:25.021564 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 23:16:25.024766 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 23:16:25.028089 0 15 28 | B1->B0 | 2424 3535 | 0 0 | (0 0) (0 0)
5115 23:16:25.034758 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5116 23:16:25.038049 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 23:16:25.041299 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 23:16:25.048428 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 23:16:25.051484 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 23:16:25.054501 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 23:16:25.061160 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 23:16:25.064643 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5123 23:16:25.067821 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5124 23:16:25.074353 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5125 23:16:25.077719 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 23:16:25.081066 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 23:16:25.087697 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 23:16:25.091167 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 23:16:25.094344 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 23:16:25.101146 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 23:16:25.104474 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 23:16:25.107975 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 23:16:25.114042 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 23:16:25.117442 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 23:16:25.120916 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 23:16:25.127404 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 23:16:25.130858 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 23:16:25.134231 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5139 23:16:25.137229 Total UI for P1: 0, mck2ui 16
5140 23:16:25.141379 best dqsien dly found for B0: ( 1, 2, 24)
5141 23:16:25.143982 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5142 23:16:25.150706 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5143 23:16:25.154202 Total UI for P1: 0, mck2ui 16
5144 23:16:25.157147 best dqsien dly found for B1: ( 1, 2, 30)
5145 23:16:25.160780 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5146 23:16:25.163853 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5147 23:16:25.163962
5148 23:16:25.167284 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5149 23:16:25.170618 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5150 23:16:25.174229 [Gating] SW calibration Done
5151 23:16:25.174319 ==
5152 23:16:25.177158 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 23:16:25.180559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 23:16:25.180640 ==
5155 23:16:25.183843 RX Vref Scan: 0
5156 23:16:25.183924
5157 23:16:25.186998 RX Vref 0 -> 0, step: 1
5158 23:16:25.187081
5159 23:16:25.187146 RX Delay -80 -> 252, step: 8
5160 23:16:25.193774 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5161 23:16:25.197030 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5162 23:16:25.200640 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5163 23:16:25.203898 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5164 23:16:25.207160 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5165 23:16:25.210972 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5166 23:16:25.217460 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5167 23:16:25.220655 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5168 23:16:25.224092 iDelay=208, Bit 8, Center 83 (0 ~ 167) 168
5169 23:16:25.227212 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5170 23:16:25.230549 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5171 23:16:25.233654 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5172 23:16:25.240728 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5173 23:16:25.243909 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5174 23:16:25.247329 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5175 23:16:25.250659 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5176 23:16:25.251145 ==
5177 23:16:25.254052 Dram Type= 6, Freq= 0, CH_0, rank 0
5178 23:16:25.257457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5179 23:16:25.260528 ==
5180 23:16:25.261055 DQS Delay:
5181 23:16:25.261409 DQS0 = 0, DQS1 = 0
5182 23:16:25.263861 DQM Delay:
5183 23:16:25.264326 DQM0 = 104, DQM1 = 94
5184 23:16:25.267608 DQ Delay:
5185 23:16:25.270556 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5186 23:16:25.273686 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5187 23:16:25.277608 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5188 23:16:25.280519 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5189 23:16:25.280936
5190 23:16:25.281264
5191 23:16:25.281573 ==
5192 23:16:25.284167 Dram Type= 6, Freq= 0, CH_0, rank 0
5193 23:16:25.287513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5194 23:16:25.287934 ==
5195 23:16:25.288266
5196 23:16:25.288577
5197 23:16:25.290571 TX Vref Scan disable
5198 23:16:25.290988 == TX Byte 0 ==
5199 23:16:25.297187 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5200 23:16:25.300503 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5201 23:16:25.300926 == TX Byte 1 ==
5202 23:16:25.307027 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5203 23:16:25.310135 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5204 23:16:25.310666 ==
5205 23:16:25.313645 Dram Type= 6, Freq= 0, CH_0, rank 0
5206 23:16:25.316685 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5207 23:16:25.317109 ==
5208 23:16:25.317442
5209 23:16:25.320470
5210 23:16:25.320883 TX Vref Scan disable
5211 23:16:25.323410 == TX Byte 0 ==
5212 23:16:25.327104 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5213 23:16:25.330157 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5214 23:16:25.333304 == TX Byte 1 ==
5215 23:16:25.336920 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5216 23:16:25.343647 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5217 23:16:25.344065
5218 23:16:25.344397 [DATLAT]
5219 23:16:25.344705 Freq=933, CH0 RK0
5220 23:16:25.345005
5221 23:16:25.346667 DATLAT Default: 0xd
5222 23:16:25.347083 0, 0xFFFF, sum = 0
5223 23:16:25.350238 1, 0xFFFF, sum = 0
5224 23:16:25.350735 2, 0xFFFF, sum = 0
5225 23:16:25.353698 3, 0xFFFF, sum = 0
5226 23:16:25.356858 4, 0xFFFF, sum = 0
5227 23:16:25.357393 5, 0xFFFF, sum = 0
5228 23:16:25.359962 6, 0xFFFF, sum = 0
5229 23:16:25.360386 7, 0xFFFF, sum = 0
5230 23:16:25.363255 8, 0xFFFF, sum = 0
5231 23:16:25.363694 9, 0xFFFF, sum = 0
5232 23:16:25.366740 10, 0x0, sum = 1
5233 23:16:25.367176 11, 0x0, sum = 2
5234 23:16:25.369933 12, 0x0, sum = 3
5235 23:16:25.370355 13, 0x0, sum = 4
5236 23:16:25.370690 best_step = 11
5237 23:16:25.370996
5238 23:16:25.373427 ==
5239 23:16:25.376543 Dram Type= 6, Freq= 0, CH_0, rank 0
5240 23:16:25.380074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5241 23:16:25.380494 ==
5242 23:16:25.380824 RX Vref Scan: 1
5243 23:16:25.381129
5244 23:16:25.382959 RX Vref 0 -> 0, step: 1
5245 23:16:25.383379
5246 23:16:25.386357 RX Delay -45 -> 252, step: 4
5247 23:16:25.386779
5248 23:16:25.389296 Set Vref, RX VrefLevel [Byte0]: 57
5249 23:16:25.393118 [Byte1]: 49
5250 23:16:25.393662
5251 23:16:25.396326 Final RX Vref Byte 0 = 57 to rank0
5252 23:16:25.399787 Final RX Vref Byte 1 = 49 to rank0
5253 23:16:25.402723 Final RX Vref Byte 0 = 57 to rank1
5254 23:16:25.406052 Final RX Vref Byte 1 = 49 to rank1==
5255 23:16:25.409511 Dram Type= 6, Freq= 0, CH_0, rank 0
5256 23:16:25.412945 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5257 23:16:25.416090 ==
5258 23:16:25.416507 DQS Delay:
5259 23:16:25.416840 DQS0 = 0, DQS1 = 0
5260 23:16:25.419458 DQM Delay:
5261 23:16:25.419892 DQM0 = 104, DQM1 = 94
5262 23:16:25.422757 DQ Delay:
5263 23:16:25.425846 DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102
5264 23:16:25.429719 DQ4 =106, DQ5 =96, DQ6 =110, DQ7 =110
5265 23:16:25.432835 DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =88
5266 23:16:25.436079 DQ12 =100, DQ13 =98, DQ14 =104, DQ15 =102
5267 23:16:25.436498
5268 23:16:25.436828
5269 23:16:25.442512 [DQSOSCAuto] RK0, (LSB)MR18= 0x2e26, (MSB)MR19= 0x505, tDQSOscB0 = 409 ps tDQSOscB1 = 407 ps
5270 23:16:25.445909 CH0 RK0: MR19=505, MR18=2E26
5271 23:16:25.452689 CH0_RK0: MR19=0x505, MR18=0x2E26, DQSOSC=407, MR23=63, INC=65, DEC=43
5272 23:16:25.453182
5273 23:16:25.456016 ----->DramcWriteLeveling(PI) begin...
5274 23:16:25.456518 ==
5275 23:16:25.459179 Dram Type= 6, Freq= 0, CH_0, rank 1
5276 23:16:25.462773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 23:16:25.463272 ==
5278 23:16:25.465715 Write leveling (Byte 0): 32 => 32
5279 23:16:25.469355 Write leveling (Byte 1): 29 => 29
5280 23:16:25.472557 DramcWriteLeveling(PI) end<-----
5281 23:16:25.472974
5282 23:16:25.473300 ==
5283 23:16:25.475996 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 23:16:25.478956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 23:16:25.482205 ==
5286 23:16:25.482624 [Gating] SW mode calibration
5287 23:16:25.492750 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5288 23:16:25.496004 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5289 23:16:25.499189 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5290 23:16:25.505951 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5291 23:16:25.509300 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 23:16:25.512798 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 23:16:25.518756 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 23:16:25.522691 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 23:16:25.525649 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5296 23:16:25.532553 0 14 28 | B1->B0 | 2c2c 2a2a | 0 0 | (0 0) (0 0)
5297 23:16:25.535830 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5298 23:16:25.538937 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5299 23:16:25.545637 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 23:16:25.548978 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 23:16:25.552558 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 23:16:25.559220 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 23:16:25.562324 0 15 24 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
5304 23:16:25.566040 0 15 28 | B1->B0 | 4343 3e3e | 0 0 | (0 0) (0 0)
5305 23:16:25.572048 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5306 23:16:25.575298 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5307 23:16:25.578848 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 23:16:25.585047 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 23:16:25.588643 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 23:16:25.592269 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 23:16:25.595294 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 23:16:25.602319 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5313 23:16:25.605565 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5314 23:16:25.608561 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 23:16:25.615895 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 23:16:25.619330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 23:16:25.621994 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 23:16:25.628739 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 23:16:25.632036 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 23:16:25.635352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 23:16:25.641747 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 23:16:25.645265 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 23:16:25.648486 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 23:16:25.655068 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 23:16:25.658329 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 23:16:25.661646 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 23:16:25.668165 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 23:16:25.671907 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5329 23:16:25.674998 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5330 23:16:25.678434 Total UI for P1: 0, mck2ui 16
5331 23:16:25.681665 best dqsien dly found for B0: ( 1, 2, 28)
5332 23:16:25.685015 Total UI for P1: 0, mck2ui 16
5333 23:16:25.687959 best dqsien dly found for B1: ( 1, 2, 28)
5334 23:16:25.691349 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5335 23:16:25.694862 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5336 23:16:25.695283
5337 23:16:25.701771 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5338 23:16:25.704953 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5339 23:16:25.705446 [Gating] SW calibration Done
5340 23:16:25.708076 ==
5341 23:16:25.711098 Dram Type= 6, Freq= 0, CH_0, rank 1
5342 23:16:25.714558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5343 23:16:25.714976 ==
5344 23:16:25.715301 RX Vref Scan: 0
5345 23:16:25.715610
5346 23:16:25.717709 RX Vref 0 -> 0, step: 1
5347 23:16:25.718128
5348 23:16:25.721167 RX Delay -80 -> 252, step: 8
5349 23:16:25.724489 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5350 23:16:25.727884 iDelay=208, Bit 1, Center 111 (24 ~ 199) 176
5351 23:16:25.731436 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5352 23:16:25.738178 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5353 23:16:25.741039 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5354 23:16:25.744431 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5355 23:16:25.747901 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5356 23:16:25.751225 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5357 23:16:25.758301 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5358 23:16:25.761270 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5359 23:16:25.764309 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5360 23:16:25.767758 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5361 23:16:25.771138 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5362 23:16:25.774592 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5363 23:16:25.781302 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5364 23:16:25.784280 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5365 23:16:25.784833 ==
5366 23:16:25.787467 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 23:16:25.790913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 23:16:25.791375 ==
5369 23:16:25.791736 DQS Delay:
5370 23:16:25.794340 DQS0 = 0, DQS1 = 0
5371 23:16:25.794799 DQM Delay:
5372 23:16:25.797623 DQM0 = 106, DQM1 = 93
5373 23:16:25.798087 DQ Delay:
5374 23:16:25.800819 DQ0 =103, DQ1 =111, DQ2 =103, DQ3 =99
5375 23:16:25.804575 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5376 23:16:25.807864 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5377 23:16:25.810847 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5378 23:16:25.811262
5379 23:16:25.811592
5380 23:16:25.811896 ==
5381 23:16:25.814283 Dram Type= 6, Freq= 0, CH_0, rank 1
5382 23:16:25.820442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 23:16:25.820888 ==
5384 23:16:25.821218
5385 23:16:25.821522
5386 23:16:25.821890 TX Vref Scan disable
5387 23:16:25.824706 == TX Byte 0 ==
5388 23:16:25.828144 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5389 23:16:25.834249 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5390 23:16:25.834779 == TX Byte 1 ==
5391 23:16:25.837561 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5392 23:16:25.844292 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5393 23:16:25.844819 ==
5394 23:16:25.847757 Dram Type= 6, Freq= 0, CH_0, rank 1
5395 23:16:25.850771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5396 23:16:25.851302 ==
5397 23:16:25.851660
5398 23:16:25.851989
5399 23:16:25.854041 TX Vref Scan disable
5400 23:16:25.854511 == TX Byte 0 ==
5401 23:16:25.860879 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5402 23:16:25.864137 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5403 23:16:25.864636 == TX Byte 1 ==
5404 23:16:25.871107 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5405 23:16:25.873901 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5406 23:16:25.874442
5407 23:16:25.874905 [DATLAT]
5408 23:16:25.877332 Freq=933, CH0 RK1
5409 23:16:25.877775
5410 23:16:25.878104 DATLAT Default: 0xb
5411 23:16:25.880547 0, 0xFFFF, sum = 0
5412 23:16:25.880970 1, 0xFFFF, sum = 0
5413 23:16:25.884164 2, 0xFFFF, sum = 0
5414 23:16:25.884577 3, 0xFFFF, sum = 0
5415 23:16:25.887423 4, 0xFFFF, sum = 0
5416 23:16:25.887855 5, 0xFFFF, sum = 0
5417 23:16:25.891001 6, 0xFFFF, sum = 0
5418 23:16:25.893833 7, 0xFFFF, sum = 0
5419 23:16:25.894259 8, 0xFFFF, sum = 0
5420 23:16:25.897559 9, 0xFFFF, sum = 0
5421 23:16:25.898035 10, 0x0, sum = 1
5422 23:16:25.900840 11, 0x0, sum = 2
5423 23:16:25.901262 12, 0x0, sum = 3
5424 23:16:25.901776 13, 0x0, sum = 4
5425 23:16:25.903852 best_step = 11
5426 23:16:25.904268
5427 23:16:25.904600 ==
5428 23:16:25.907188 Dram Type= 6, Freq= 0, CH_0, rank 1
5429 23:16:25.910572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5430 23:16:25.910994 ==
5431 23:16:25.914327 RX Vref Scan: 0
5432 23:16:25.914745
5433 23:16:25.915075 RX Vref 0 -> 0, step: 1
5434 23:16:25.917746
5435 23:16:25.918161 RX Delay -53 -> 252, step: 4
5436 23:16:25.924585 iDelay=199, Bit 0, Center 104 (15 ~ 194) 180
5437 23:16:25.928210 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5438 23:16:25.931979 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5439 23:16:25.934633 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5440 23:16:25.938438 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5441 23:16:25.944955 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5442 23:16:25.948080 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5443 23:16:25.951215 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5444 23:16:25.954475 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5445 23:16:25.958141 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5446 23:16:25.961493 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5447 23:16:25.967728 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5448 23:16:25.971140 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5449 23:16:25.974554 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5450 23:16:25.978083 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5451 23:16:25.981487 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5452 23:16:25.984698 ==
5453 23:16:25.988152 Dram Type= 6, Freq= 0, CH_0, rank 1
5454 23:16:25.991052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5455 23:16:25.991472 ==
5456 23:16:25.991805 DQS Delay:
5457 23:16:25.994487 DQS0 = 0, DQS1 = 0
5458 23:16:25.994906 DQM Delay:
5459 23:16:25.997846 DQM0 = 105, DQM1 = 94
5460 23:16:25.998265 DQ Delay:
5461 23:16:26.001171 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5462 23:16:26.004616 DQ4 =106, DQ5 =98, DQ6 =112, DQ7 =112
5463 23:16:26.007437 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5464 23:16:26.010660 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5465 23:16:26.011082
5466 23:16:26.011415
5467 23:16:26.020947 [DQSOSCAuto] RK1, (LSB)MR18= 0x24fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 410 ps
5468 23:16:26.021432 CH0 RK1: MR19=504, MR18=24FD
5469 23:16:26.027630 CH0_RK1: MR19=0x504, MR18=0x24FD, DQSOSC=410, MR23=63, INC=64, DEC=42
5470 23:16:26.030614 [RxdqsGatingPostProcess] freq 933
5471 23:16:26.037391 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5472 23:16:26.041190 best DQS0 dly(2T, 0.5T) = (0, 10)
5473 23:16:26.044644 best DQS1 dly(2T, 0.5T) = (0, 10)
5474 23:16:26.047103 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5475 23:16:26.050542 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5476 23:16:26.054091 best DQS0 dly(2T, 0.5T) = (0, 10)
5477 23:16:26.057530 best DQS1 dly(2T, 0.5T) = (0, 10)
5478 23:16:26.060747 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5479 23:16:26.063626 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5480 23:16:26.064048 Pre-setting of DQS Precalculation
5481 23:16:26.070690 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5482 23:16:26.071180 ==
5483 23:16:26.073640 Dram Type= 6, Freq= 0, CH_1, rank 0
5484 23:16:26.077152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5485 23:16:26.077628 ==
5486 23:16:26.083957 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5487 23:16:26.090137 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5488 23:16:26.093512 [CA 0] Center 36 (6~67) winsize 62
5489 23:16:26.097075 [CA 1] Center 36 (6~67) winsize 62
5490 23:16:26.100569 [CA 2] Center 34 (4~65) winsize 62
5491 23:16:26.103979 [CA 3] Center 34 (4~65) winsize 62
5492 23:16:26.107157 [CA 4] Center 34 (4~64) winsize 61
5493 23:16:26.110368 [CA 5] Center 33 (3~64) winsize 62
5494 23:16:26.110787
5495 23:16:26.113556 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5496 23:16:26.114007
5497 23:16:26.116795 [CATrainingPosCal] consider 1 rank data
5498 23:16:26.120284 u2DelayCellTimex100 = 270/100 ps
5499 23:16:26.123343 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5500 23:16:26.126839 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5501 23:16:26.130089 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5502 23:16:26.133484 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5503 23:16:26.136676 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5504 23:16:26.140262 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 23:16:26.140801
5506 23:16:26.146626 CA PerBit enable=1, Macro0, CA PI delay=33
5507 23:16:26.147060
5508 23:16:26.150247 [CBTSetCACLKResult] CA Dly = 33
5509 23:16:26.150684 CS Dly: 6 (0~37)
5510 23:16:26.151029 ==
5511 23:16:26.153571 Dram Type= 6, Freq= 0, CH_1, rank 1
5512 23:16:26.156790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 23:16:26.157221 ==
5514 23:16:26.163334 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5515 23:16:26.170134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5516 23:16:26.173336 [CA 0] Center 37 (6~68) winsize 63
5517 23:16:26.176797 [CA 1] Center 37 (6~68) winsize 63
5518 23:16:26.180151 [CA 2] Center 35 (4~66) winsize 63
5519 23:16:26.183184 [CA 3] Center 34 (4~65) winsize 62
5520 23:16:26.187156 [CA 4] Center 34 (4~65) winsize 62
5521 23:16:26.190198 [CA 5] Center 34 (4~64) winsize 61
5522 23:16:26.190621
5523 23:16:26.193417 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5524 23:16:26.193883
5525 23:16:26.196550 [CATrainingPosCal] consider 2 rank data
5526 23:16:26.199958 u2DelayCellTimex100 = 270/100 ps
5527 23:16:26.203460 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5528 23:16:26.206808 CA1 delay=36 (6~67),Diff = 2 PI (12 cell)
5529 23:16:26.210178 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
5530 23:16:26.213029 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5531 23:16:26.216876 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5532 23:16:26.220153 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5533 23:16:26.223413
5534 23:16:26.226401 CA PerBit enable=1, Macro0, CA PI delay=34
5535 23:16:26.226836
5536 23:16:26.230002 [CBTSetCACLKResult] CA Dly = 34
5537 23:16:26.230501 CS Dly: 7 (0~40)
5538 23:16:26.230840
5539 23:16:26.233468 ----->DramcWriteLeveling(PI) begin...
5540 23:16:26.234020 ==
5541 23:16:26.236291 Dram Type= 6, Freq= 0, CH_1, rank 0
5542 23:16:26.239825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5543 23:16:26.243185 ==
5544 23:16:26.243676 Write leveling (Byte 0): 24 => 24
5545 23:16:26.246669 Write leveling (Byte 1): 24 => 24
5546 23:16:26.250200 DramcWriteLeveling(PI) end<-----
5547 23:16:26.250703
5548 23:16:26.251036 ==
5549 23:16:26.253065 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 23:16:26.259908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 23:16:26.260394 ==
5552 23:16:26.260733 [Gating] SW mode calibration
5553 23:16:26.269638 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5554 23:16:26.272921 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5555 23:16:26.279893 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5556 23:16:26.282951 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5557 23:16:26.286276 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 23:16:26.289691 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 23:16:26.296420 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 23:16:26.299920 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 23:16:26.302928 0 14 24 | B1->B0 | 3333 2f2f | 1 0 | (0 1) (0 1)
5562 23:16:26.309387 0 14 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
5563 23:16:26.312964 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5564 23:16:26.316683 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5565 23:16:26.322791 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5566 23:16:26.326639 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 23:16:26.329572 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 23:16:26.336425 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 23:16:26.339375 0 15 24 | B1->B0 | 2424 3434 | 0 0 | (0 0) (0 0)
5570 23:16:26.343047 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5571 23:16:26.349723 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5572 23:16:26.352747 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5573 23:16:26.356174 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 23:16:26.363055 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 23:16:26.366562 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 23:16:26.369668 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 23:16:26.376217 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5578 23:16:26.379586 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5579 23:16:26.383202 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5580 23:16:26.389638 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5581 23:16:26.392811 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 23:16:26.395926 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 23:16:26.402437 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 23:16:26.405848 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 23:16:26.409293 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 23:16:26.412841 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 23:16:26.419622 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 23:16:26.422731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 23:16:26.425905 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 23:16:26.432317 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 23:16:26.435935 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 23:16:26.439531 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 23:16:26.445655 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5594 23:16:26.448955 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5595 23:16:26.452479 Total UI for P1: 0, mck2ui 16
5596 23:16:26.455851 best dqsien dly found for B0: ( 1, 2, 24)
5597 23:16:26.459203 Total UI for P1: 0, mck2ui 16
5598 23:16:26.462540 best dqsien dly found for B1: ( 1, 2, 24)
5599 23:16:26.466070 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5600 23:16:26.468956 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5601 23:16:26.469369
5602 23:16:26.472443 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5603 23:16:26.478686 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5604 23:16:26.479167 [Gating] SW calibration Done
5605 23:16:26.479501 ==
5606 23:16:26.482212 Dram Type= 6, Freq= 0, CH_1, rank 0
5607 23:16:26.489290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5608 23:16:26.489821 ==
5609 23:16:26.490158 RX Vref Scan: 0
5610 23:16:26.490467
5611 23:16:26.491982 RX Vref 0 -> 0, step: 1
5612 23:16:26.492437
5613 23:16:26.495674 RX Delay -80 -> 252, step: 8
5614 23:16:26.498714 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5615 23:16:26.502364 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5616 23:16:26.505197 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5617 23:16:26.508941 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5618 23:16:26.515346 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5619 23:16:26.518524 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5620 23:16:26.522094 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5621 23:16:26.525194 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5622 23:16:26.528365 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5623 23:16:26.531887 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5624 23:16:26.539010 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5625 23:16:26.541972 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5626 23:16:26.545452 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5627 23:16:26.548834 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5628 23:16:26.552137 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5629 23:16:26.558496 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5630 23:16:26.559083 ==
5631 23:16:26.562285 Dram Type= 6, Freq= 0, CH_1, rank 0
5632 23:16:26.565258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 23:16:26.565832 ==
5634 23:16:26.566222 DQS Delay:
5635 23:16:26.568865 DQS0 = 0, DQS1 = 0
5636 23:16:26.569531 DQM Delay:
5637 23:16:26.572525 DQM0 = 102, DQM1 = 98
5638 23:16:26.573194 DQ Delay:
5639 23:16:26.575030 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5640 23:16:26.578398 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5641 23:16:26.582037 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5642 23:16:26.584986 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5643 23:16:26.585448
5644 23:16:26.585972
5645 23:16:26.586333 ==
5646 23:16:26.588553 Dram Type= 6, Freq= 0, CH_1, rank 0
5647 23:16:26.594689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5648 23:16:26.595115 ==
5649 23:16:26.595450
5650 23:16:26.595849
5651 23:16:26.596171 TX Vref Scan disable
5652 23:16:26.598413 == TX Byte 0 ==
5653 23:16:26.601958 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5654 23:16:26.608047 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5655 23:16:26.608509 == TX Byte 1 ==
5656 23:16:26.611699 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5657 23:16:26.617900 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5658 23:16:26.618326 ==
5659 23:16:26.621642 Dram Type= 6, Freq= 0, CH_1, rank 0
5660 23:16:26.624775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5661 23:16:26.625200 ==
5662 23:16:26.625764
5663 23:16:26.626149
5664 23:16:26.627982 TX Vref Scan disable
5665 23:16:26.628400 == TX Byte 0 ==
5666 23:16:26.635157 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5667 23:16:26.638302 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5668 23:16:26.638727 == TX Byte 1 ==
5669 23:16:26.645185 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5670 23:16:26.648401 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5671 23:16:26.648925
5672 23:16:26.649259 [DATLAT]
5673 23:16:26.651653 Freq=933, CH1 RK0
5674 23:16:26.652177
5675 23:16:26.652513 DATLAT Default: 0xd
5676 23:16:26.654910 0, 0xFFFF, sum = 0
5677 23:16:26.655463 1, 0xFFFF, sum = 0
5678 23:16:26.658574 2, 0xFFFF, sum = 0
5679 23:16:26.659104 3, 0xFFFF, sum = 0
5680 23:16:26.661731 4, 0xFFFF, sum = 0
5681 23:16:26.664789 5, 0xFFFF, sum = 0
5682 23:16:26.665234 6, 0xFFFF, sum = 0
5683 23:16:26.668034 7, 0xFFFF, sum = 0
5684 23:16:26.668457 8, 0xFFFF, sum = 0
5685 23:16:26.671343 9, 0xFFFF, sum = 0
5686 23:16:26.671766 10, 0x0, sum = 1
5687 23:16:26.674283 11, 0x0, sum = 2
5688 23:16:26.674709 12, 0x0, sum = 3
5689 23:16:26.675047 13, 0x0, sum = 4
5690 23:16:26.677613 best_step = 11
5691 23:16:26.678142
5692 23:16:26.678500 ==
5693 23:16:26.681411 Dram Type= 6, Freq= 0, CH_1, rank 0
5694 23:16:26.684758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5695 23:16:26.685182 ==
5696 23:16:26.687493 RX Vref Scan: 1
5697 23:16:26.687997
5698 23:16:26.690897 RX Vref 0 -> 0, step: 1
5699 23:16:26.691314
5700 23:16:26.691644 RX Delay -45 -> 252, step: 4
5701 23:16:26.691962
5702 23:16:26.694279 Set Vref, RX VrefLevel [Byte0]: 57
5703 23:16:26.697629 [Byte1]: 48
5704 23:16:26.701924
5705 23:16:26.702340 Final RX Vref Byte 0 = 57 to rank0
5706 23:16:26.705732 Final RX Vref Byte 1 = 48 to rank0
5707 23:16:26.708928 Final RX Vref Byte 0 = 57 to rank1
5708 23:16:26.712410 Final RX Vref Byte 1 = 48 to rank1==
5709 23:16:26.715463 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 23:16:26.722548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 23:16:26.723070 ==
5712 23:16:26.723407 DQS Delay:
5713 23:16:26.723720 DQS0 = 0, DQS1 = 0
5714 23:16:26.725413 DQM Delay:
5715 23:16:26.725990 DQM0 = 104, DQM1 = 99
5716 23:16:26.728924 DQ Delay:
5717 23:16:26.732302 DQ0 =106, DQ1 =98, DQ2 =96, DQ3 =102
5718 23:16:26.735341 DQ4 =102, DQ5 =114, DQ6 =114, DQ7 =104
5719 23:16:26.738673 DQ8 =88, DQ9 =88, DQ10 =98, DQ11 =92
5720 23:16:26.742477 DQ12 =108, DQ13 =106, DQ14 =108, DQ15 =110
5721 23:16:26.743009
5722 23:16:26.743343
5723 23:16:26.748880 [DQSOSCAuto] RK0, (LSB)MR18= 0x182f, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
5724 23:16:26.751946 CH1 RK0: MR19=505, MR18=182F
5725 23:16:26.758845 CH1_RK0: MR19=0x505, MR18=0x182F, DQSOSC=407, MR23=63, INC=65, DEC=43
5726 23:16:26.759382
5727 23:16:26.762256 ----->DramcWriteLeveling(PI) begin...
5728 23:16:26.762687 ==
5729 23:16:26.765213 Dram Type= 6, Freq= 0, CH_1, rank 1
5730 23:16:26.768386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 23:16:26.768811 ==
5732 23:16:26.772054 Write leveling (Byte 0): 29 => 29
5733 23:16:26.775434 Write leveling (Byte 1): 31 => 31
5734 23:16:26.778536 DramcWriteLeveling(PI) end<-----
5735 23:16:26.779047
5736 23:16:26.779388 ==
5737 23:16:26.781973 Dram Type= 6, Freq= 0, CH_1, rank 1
5738 23:16:26.785289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 23:16:26.789135 ==
5740 23:16:26.789552 [Gating] SW mode calibration
5741 23:16:26.799010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5742 23:16:26.802003 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5743 23:16:26.805240 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5744 23:16:26.812097 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5745 23:16:26.815397 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5746 23:16:26.818678 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 23:16:26.825257 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 23:16:26.828743 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 23:16:26.832037 0 14 24 | B1->B0 | 2e2e 3232 | 0 0 | (0 1) (0 0)
5750 23:16:26.838343 0 14 28 | B1->B0 | 2323 2424 | 0 1 | (1 0) (1 0)
5751 23:16:26.841964 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5752 23:16:26.844900 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5753 23:16:26.851650 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5754 23:16:26.855380 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5755 23:16:26.858720 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 23:16:26.864869 0 15 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5757 23:16:26.868239 0 15 24 | B1->B0 | 3535 2828 | 1 0 | (0 0) (0 0)
5758 23:16:26.871750 0 15 28 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)
5759 23:16:26.878363 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5760 23:16:26.881635 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5761 23:16:26.884718 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5762 23:16:26.891613 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5763 23:16:26.895147 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 23:16:26.898289 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 23:16:26.905082 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 23:16:26.908039 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5767 23:16:26.911655 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5768 23:16:26.914783 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5769 23:16:26.921568 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 23:16:26.924377 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 23:16:26.928666 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 23:16:26.934820 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 23:16:26.938395 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 23:16:26.941505 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 23:16:26.948230 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 23:16:26.951731 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 23:16:26.955120 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 23:16:26.961216 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 23:16:26.964998 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 23:16:26.967520 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 23:16:26.974368 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 23:16:26.977834 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5783 23:16:26.981301 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5784 23:16:26.984852 Total UI for P1: 0, mck2ui 16
5785 23:16:26.987608 best dqsien dly found for B0: ( 1, 2, 28)
5786 23:16:26.991008 Total UI for P1: 0, mck2ui 16
5787 23:16:26.994079 best dqsien dly found for B1: ( 1, 2, 28)
5788 23:16:26.997650 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5789 23:16:27.000855 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5790 23:16:27.001342
5791 23:16:27.007912 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5792 23:16:27.010895 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5793 23:16:27.014135 [Gating] SW calibration Done
5794 23:16:27.014561 ==
5795 23:16:27.017470 Dram Type= 6, Freq= 0, CH_1, rank 1
5796 23:16:27.021035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5797 23:16:27.021545 ==
5798 23:16:27.021939 RX Vref Scan: 0
5799 23:16:27.022432
5800 23:16:27.024502 RX Vref 0 -> 0, step: 1
5801 23:16:27.024919
5802 23:16:27.027661 RX Delay -80 -> 252, step: 8
5803 23:16:27.031175 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5804 23:16:27.034279 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5805 23:16:27.037500 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5806 23:16:27.044072 iDelay=208, Bit 3, Center 95 (8 ~ 183) 176
5807 23:16:27.047499 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5808 23:16:27.050541 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5809 23:16:27.054225 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5810 23:16:27.057106 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5811 23:16:27.060537 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5812 23:16:27.067167 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5813 23:16:27.070677 iDelay=208, Bit 10, Center 103 (16 ~ 191) 176
5814 23:16:27.074069 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5815 23:16:27.077669 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5816 23:16:27.080414 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5817 23:16:27.087036 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5818 23:16:27.090808 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5819 23:16:27.091359 ==
5820 23:16:27.093703 Dram Type= 6, Freq= 0, CH_1, rank 1
5821 23:16:27.096799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5822 23:16:27.097274 ==
5823 23:16:27.100942 DQS Delay:
5824 23:16:27.101517 DQS0 = 0, DQS1 = 0
5825 23:16:27.102053 DQM Delay:
5826 23:16:27.103630 DQM0 = 102, DQM1 = 99
5827 23:16:27.104102 DQ Delay:
5828 23:16:27.107177 DQ0 =111, DQ1 =99, DQ2 =91, DQ3 =95
5829 23:16:27.110245 DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =99
5830 23:16:27.113916 DQ8 =87, DQ9 =91, DQ10 =103, DQ11 =91
5831 23:16:27.117248 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5832 23:16:27.117888
5833 23:16:27.120575
5834 23:16:27.121138 ==
5835 23:16:27.123822 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 23:16:27.127092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 23:16:27.127663 ==
5838 23:16:27.128150
5839 23:16:27.128601
5840 23:16:27.130172 TX Vref Scan disable
5841 23:16:27.130643 == TX Byte 0 ==
5842 23:16:27.137191 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5843 23:16:27.140383 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5844 23:16:27.140965 == TX Byte 1 ==
5845 23:16:27.146744 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5846 23:16:27.150200 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5847 23:16:27.150767 ==
5848 23:16:27.153645 Dram Type= 6, Freq= 0, CH_1, rank 1
5849 23:16:27.157024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5850 23:16:27.157623 ==
5851 23:16:27.157999
5852 23:16:27.158333
5853 23:16:27.159927 TX Vref Scan disable
5854 23:16:27.163566 == TX Byte 0 ==
5855 23:16:27.167035 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5856 23:16:27.169880 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5857 23:16:27.173668 == TX Byte 1 ==
5858 23:16:27.177345 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5859 23:16:27.180346 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5860 23:16:27.180805
5861 23:16:27.183289 [DATLAT]
5862 23:16:27.183742 Freq=933, CH1 RK1
5863 23:16:27.184102
5864 23:16:27.187368 DATLAT Default: 0xb
5865 23:16:27.187922 0, 0xFFFF, sum = 0
5866 23:16:27.190040 1, 0xFFFF, sum = 0
5867 23:16:27.190597 2, 0xFFFF, sum = 0
5868 23:16:27.193243 3, 0xFFFF, sum = 0
5869 23:16:27.193753 4, 0xFFFF, sum = 0
5870 23:16:27.196753 5, 0xFFFF, sum = 0
5871 23:16:27.197247 6, 0xFFFF, sum = 0
5872 23:16:27.200135 7, 0xFFFF, sum = 0
5873 23:16:27.200737 8, 0xFFFF, sum = 0
5874 23:16:27.203110 9, 0xFFFF, sum = 0
5875 23:16:27.203569 10, 0x0, sum = 1
5876 23:16:27.206755 11, 0x0, sum = 2
5877 23:16:27.207213 12, 0x0, sum = 3
5878 23:16:27.210189 13, 0x0, sum = 4
5879 23:16:27.210645 best_step = 11
5880 23:16:27.210998
5881 23:16:27.211314 ==
5882 23:16:27.213635 Dram Type= 6, Freq= 0, CH_1, rank 1
5883 23:16:27.216444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5884 23:16:27.219929 ==
5885 23:16:27.220353 RX Vref Scan: 0
5886 23:16:27.220678
5887 23:16:27.223440 RX Vref 0 -> 0, step: 1
5888 23:16:27.223974
5889 23:16:27.226710 RX Delay -45 -> 252, step: 4
5890 23:16:27.229670 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5891 23:16:27.233502 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5892 23:16:27.239999 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5893 23:16:27.242867 iDelay=203, Bit 3, Center 98 (19 ~ 178) 160
5894 23:16:27.246454 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5895 23:16:27.249755 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5896 23:16:27.253089 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5897 23:16:27.256498 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5898 23:16:27.263570 iDelay=203, Bit 8, Center 92 (11 ~ 174) 164
5899 23:16:27.266028 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5900 23:16:27.270041 iDelay=203, Bit 10, Center 100 (19 ~ 182) 164
5901 23:16:27.273199 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5902 23:16:27.276370 iDelay=203, Bit 12, Center 108 (19 ~ 198) 180
5903 23:16:27.283318 iDelay=203, Bit 13, Center 108 (27 ~ 190) 164
5904 23:16:27.286236 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5905 23:16:27.289873 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5906 23:16:27.290328 ==
5907 23:16:27.292930 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 23:16:27.296193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 23:16:27.296650 ==
5910 23:16:27.299852 DQS Delay:
5911 23:16:27.300361 DQS0 = 0, DQS1 = 0
5912 23:16:27.303261 DQM Delay:
5913 23:16:27.303667 DQM0 = 105, DQM1 = 100
5914 23:16:27.306426 DQ Delay:
5915 23:16:27.309736 DQ0 =110, DQ1 =102, DQ2 =94, DQ3 =98
5916 23:16:27.312933 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
5917 23:16:27.315963 DQ8 =92, DQ9 =88, DQ10 =100, DQ11 =94
5918 23:16:27.319557 DQ12 =108, DQ13 =108, DQ14 =106, DQ15 =110
5919 23:16:27.320071
5920 23:16:27.320395
5921 23:16:27.326554 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
5922 23:16:27.329822 CH1 RK1: MR19=505, MR18=2C00
5923 23:16:27.336076 CH1_RK1: MR19=0x505, MR18=0x2C00, DQSOSC=408, MR23=63, INC=65, DEC=43
5924 23:16:27.339344 [RxdqsGatingPostProcess] freq 933
5925 23:16:27.342628 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5926 23:16:27.346288 best DQS0 dly(2T, 0.5T) = (0, 10)
5927 23:16:27.349688 best DQS1 dly(2T, 0.5T) = (0, 10)
5928 23:16:27.352879 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5929 23:16:27.356360 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5930 23:16:27.359417 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 23:16:27.362525 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 23:16:27.365784 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 23:16:27.369361 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 23:16:27.372581 Pre-setting of DQS Precalculation
5935 23:16:27.375673 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5936 23:16:27.385981 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5937 23:16:27.392425 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5938 23:16:27.392934
5939 23:16:27.393262
5940 23:16:27.396156 [Calibration Summary] 1866 Mbps
5941 23:16:27.396807 CH 0, Rank 0
5942 23:16:27.399225 SW Impedance : PASS
5943 23:16:27.399677 DUTY Scan : NO K
5944 23:16:27.402775 ZQ Calibration : PASS
5945 23:16:27.406573 Jitter Meter : NO K
5946 23:16:27.407125 CBT Training : PASS
5947 23:16:27.409889 Write leveling : PASS
5948 23:16:27.412856 RX DQS gating : PASS
5949 23:16:27.413406 RX DQ/DQS(RDDQC) : PASS
5950 23:16:27.415809 TX DQ/DQS : PASS
5951 23:16:27.419460 RX DATLAT : PASS
5952 23:16:27.420014 RX DQ/DQS(Engine): PASS
5953 23:16:27.422578 TX OE : NO K
5954 23:16:27.423031 All Pass.
5955 23:16:27.423387
5956 23:16:27.426041 CH 0, Rank 1
5957 23:16:27.426493 SW Impedance : PASS
5958 23:16:27.429306 DUTY Scan : NO K
5959 23:16:27.432954 ZQ Calibration : PASS
5960 23:16:27.433515 Jitter Meter : NO K
5961 23:16:27.435805 CBT Training : PASS
5962 23:16:27.436258 Write leveling : PASS
5963 23:16:27.439146 RX DQS gating : PASS
5964 23:16:27.442317 RX DQ/DQS(RDDQC) : PASS
5965 23:16:27.442866 TX DQ/DQS : PASS
5966 23:16:27.445937 RX DATLAT : PASS
5967 23:16:27.449411 RX DQ/DQS(Engine): PASS
5968 23:16:27.450135 TX OE : NO K
5969 23:16:27.452882 All Pass.
5970 23:16:27.453431
5971 23:16:27.453837 CH 1, Rank 0
5972 23:16:27.456084 SW Impedance : PASS
5973 23:16:27.456534 DUTY Scan : NO K
5974 23:16:27.458715 ZQ Calibration : PASS
5975 23:16:27.462284 Jitter Meter : NO K
5976 23:16:27.462788 CBT Training : PASS
5977 23:16:27.465700 Write leveling : PASS
5978 23:16:27.469312 RX DQS gating : PASS
5979 23:16:27.469765 RX DQ/DQS(RDDQC) : PASS
5980 23:16:27.472112 TX DQ/DQS : PASS
5981 23:16:27.475577 RX DATLAT : PASS
5982 23:16:27.476084 RX DQ/DQS(Engine): PASS
5983 23:16:27.478774 TX OE : NO K
5984 23:16:27.479184 All Pass.
5985 23:16:27.479574
5986 23:16:27.482045 CH 1, Rank 1
5987 23:16:27.482552 SW Impedance : PASS
5988 23:16:27.485216 DUTY Scan : NO K
5989 23:16:27.488810 ZQ Calibration : PASS
5990 23:16:27.489317 Jitter Meter : NO K
5991 23:16:27.492089 CBT Training : PASS
5992 23:16:27.495581 Write leveling : PASS
5993 23:16:27.496111 RX DQS gating : PASS
5994 23:16:27.498609 RX DQ/DQS(RDDQC) : PASS
5995 23:16:27.499026 TX DQ/DQS : PASS
5996 23:16:27.502076 RX DATLAT : PASS
5997 23:16:27.505869 RX DQ/DQS(Engine): PASS
5998 23:16:27.506433 TX OE : NO K
5999 23:16:27.508531 All Pass.
6000 23:16:27.508979
6001 23:16:27.509344 DramC Write-DBI off
6002 23:16:27.511810 PER_BANK_REFRESH: Hybrid Mode
6003 23:16:27.515089 TX_TRACKING: ON
6004 23:16:27.521947 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6005 23:16:27.525284 [FAST_K] Save calibration result to emmc
6006 23:16:27.528568 dramc_set_vcore_voltage set vcore to 650000
6007 23:16:27.532195 Read voltage for 400, 6
6008 23:16:27.532709 Vio18 = 0
6009 23:16:27.535417 Vcore = 650000
6010 23:16:27.535933 Vdram = 0
6011 23:16:27.536262 Vddq = 0
6012 23:16:27.538448 Vmddr = 0
6013 23:16:27.541988 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6014 23:16:27.548350 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6015 23:16:27.548903 MEM_TYPE=3, freq_sel=20
6016 23:16:27.551879 sv_algorithm_assistance_LP4_800
6017 23:16:27.558470 ============ PULL DRAM RESETB DOWN ============
6018 23:16:27.562036 ========== PULL DRAM RESETB DOWN end =========
6019 23:16:27.565293 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6020 23:16:27.568778 ===================================
6021 23:16:27.571972 LPDDR4 DRAM CONFIGURATION
6022 23:16:27.575214 ===================================
6023 23:16:27.578671 EX_ROW_EN[0] = 0x0
6024 23:16:27.579221 EX_ROW_EN[1] = 0x0
6025 23:16:27.582071 LP4Y_EN = 0x0
6026 23:16:27.582524 WORK_FSP = 0x0
6027 23:16:27.585316 WL = 0x2
6028 23:16:27.585923 RL = 0x2
6029 23:16:27.588095 BL = 0x2
6030 23:16:27.588546 RPST = 0x0
6031 23:16:27.591334 RD_PRE = 0x0
6032 23:16:27.591785 WR_PRE = 0x1
6033 23:16:27.594934 WR_PST = 0x0
6034 23:16:27.595384 DBI_WR = 0x0
6035 23:16:27.598218 DBI_RD = 0x0
6036 23:16:27.598748 OTF = 0x1
6037 23:16:27.601915 ===================================
6038 23:16:27.604782 ===================================
6039 23:16:27.608224 ANA top config
6040 23:16:27.611925 ===================================
6041 23:16:27.612458 DLL_ASYNC_EN = 0
6042 23:16:27.615258 ALL_SLAVE_EN = 1
6043 23:16:27.618067 NEW_RANK_MODE = 1
6044 23:16:27.621785 DLL_IDLE_MODE = 1
6045 23:16:27.625042 LP45_APHY_COMB_EN = 1
6046 23:16:27.625521 TX_ODT_DIS = 1
6047 23:16:27.628734 NEW_8X_MODE = 1
6048 23:16:27.631648 ===================================
6049 23:16:27.635467 ===================================
6050 23:16:27.638893 data_rate = 800
6051 23:16:27.641881 CKR = 1
6052 23:16:27.645341 DQ_P2S_RATIO = 4
6053 23:16:27.648168 ===================================
6054 23:16:27.651623 CA_P2S_RATIO = 4
6055 23:16:27.652143 DQ_CA_OPEN = 0
6056 23:16:27.654416 DQ_SEMI_OPEN = 1
6057 23:16:27.658213 CA_SEMI_OPEN = 1
6058 23:16:27.661399 CA_FULL_RATE = 0
6059 23:16:27.664704 DQ_CKDIV4_EN = 0
6060 23:16:27.667889 CA_CKDIV4_EN = 1
6061 23:16:27.668300 CA_PREDIV_EN = 0
6062 23:16:27.670947 PH8_DLY = 0
6063 23:16:27.674813 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6064 23:16:27.677967 DQ_AAMCK_DIV = 0
6065 23:16:27.681074 CA_AAMCK_DIV = 0
6066 23:16:27.684445 CA_ADMCK_DIV = 4
6067 23:16:27.684853 DQ_TRACK_CA_EN = 0
6068 23:16:27.687501 CA_PICK = 800
6069 23:16:27.691139 CA_MCKIO = 400
6070 23:16:27.694142 MCKIO_SEMI = 400
6071 23:16:27.697824 PLL_FREQ = 3016
6072 23:16:27.701128 DQ_UI_PI_RATIO = 32
6073 23:16:27.704275 CA_UI_PI_RATIO = 32
6074 23:16:27.707927 ===================================
6075 23:16:27.711293 ===================================
6076 23:16:27.711813 memory_type:LPDDR4
6077 23:16:27.714221 GP_NUM : 10
6078 23:16:27.718043 SRAM_EN : 1
6079 23:16:27.718453 MD32_EN : 0
6080 23:16:27.720745 ===================================
6081 23:16:27.724456 [ANA_INIT] >>>>>>>>>>>>>>
6082 23:16:27.727382 <<<<<< [CONFIGURE PHASE]: ANA_TX
6083 23:16:27.730861 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6084 23:16:27.734085 ===================================
6085 23:16:27.737322 data_rate = 800,PCW = 0X7400
6086 23:16:27.741126 ===================================
6087 23:16:27.744385 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6088 23:16:27.748169 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6089 23:16:27.760845 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6090 23:16:27.764597 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6091 23:16:27.767386 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6092 23:16:27.770799 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6093 23:16:27.774663 [ANA_INIT] flow start
6094 23:16:27.775204 [ANA_INIT] PLL >>>>>>>>
6095 23:16:27.777107 [ANA_INIT] PLL <<<<<<<<
6096 23:16:27.780239 [ANA_INIT] MIDPI >>>>>>>>
6097 23:16:27.783764 [ANA_INIT] MIDPI <<<<<<<<
6098 23:16:27.784410 [ANA_INIT] DLL >>>>>>>>
6099 23:16:27.786961 [ANA_INIT] flow end
6100 23:16:27.790158 ============ LP4 DIFF to SE enter ============
6101 23:16:27.793931 ============ LP4 DIFF to SE exit ============
6102 23:16:27.797434 [ANA_INIT] <<<<<<<<<<<<<
6103 23:16:27.800149 [Flow] Enable top DCM control >>>>>
6104 23:16:27.803758 [Flow] Enable top DCM control <<<<<
6105 23:16:27.806982 Enable DLL master slave shuffle
6106 23:16:27.813484 ==============================================================
6107 23:16:27.813938 Gating Mode config
6108 23:16:27.820681 ==============================================================
6109 23:16:27.821174 Config description:
6110 23:16:27.830153 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6111 23:16:27.837359 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6112 23:16:27.843739 SELPH_MODE 0: By rank 1: By Phase
6113 23:16:27.846772 ==============================================================
6114 23:16:27.850003 GAT_TRACK_EN = 0
6115 23:16:27.853345 RX_GATING_MODE = 2
6116 23:16:27.857106 RX_GATING_TRACK_MODE = 2
6117 23:16:27.860377 SELPH_MODE = 1
6118 23:16:27.863570 PICG_EARLY_EN = 1
6119 23:16:27.866825 VALID_LAT_VALUE = 1
6120 23:16:27.869863 ==============================================================
6121 23:16:27.876804 Enter into Gating configuration >>>>
6122 23:16:27.877351 Exit from Gating configuration <<<<
6123 23:16:27.879927 Enter into DVFS_PRE_config >>>>>
6124 23:16:27.893215 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6125 23:16:27.896612 Exit from DVFS_PRE_config <<<<<
6126 23:16:27.899945 Enter into PICG configuration >>>>
6127 23:16:27.903340 Exit from PICG configuration <<<<
6128 23:16:27.903749 [RX_INPUT] configuration >>>>>
6129 23:16:27.906900 [RX_INPUT] configuration <<<<<
6130 23:16:27.913122 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6131 23:16:27.916552 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6132 23:16:27.923137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6133 23:16:27.929924 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6134 23:16:27.936415 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 23:16:27.942890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 23:16:27.946360 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6137 23:16:27.949323 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6138 23:16:27.955951 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6139 23:16:27.959115 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6140 23:16:27.962352 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6141 23:16:27.965739 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6142 23:16:27.969391 ===================================
6143 23:16:27.972438 LPDDR4 DRAM CONFIGURATION
6144 23:16:27.975623 ===================================
6145 23:16:27.979161 EX_ROW_EN[0] = 0x0
6146 23:16:27.979240 EX_ROW_EN[1] = 0x0
6147 23:16:27.982645 LP4Y_EN = 0x0
6148 23:16:27.982724 WORK_FSP = 0x0
6149 23:16:27.985883 WL = 0x2
6150 23:16:27.985963 RL = 0x2
6151 23:16:27.989088 BL = 0x2
6152 23:16:27.989168 RPST = 0x0
6153 23:16:27.992323 RD_PRE = 0x0
6154 23:16:27.992403 WR_PRE = 0x1
6155 23:16:27.995754 WR_PST = 0x0
6156 23:16:27.998892 DBI_WR = 0x0
6157 23:16:27.998997 DBI_RD = 0x0
6158 23:16:28.002144 OTF = 0x1
6159 23:16:28.005570 ===================================
6160 23:16:28.008905 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6161 23:16:28.012292 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6162 23:16:28.015939 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6163 23:16:28.019045 ===================================
6164 23:16:28.022067 LPDDR4 DRAM CONFIGURATION
6165 23:16:28.025911 ===================================
6166 23:16:28.028891 EX_ROW_EN[0] = 0x10
6167 23:16:28.028963 EX_ROW_EN[1] = 0x0
6168 23:16:28.032198 LP4Y_EN = 0x0
6169 23:16:28.032294 WORK_FSP = 0x0
6170 23:16:28.035632 WL = 0x2
6171 23:16:28.035727 RL = 0x2
6172 23:16:28.038868 BL = 0x2
6173 23:16:28.038938 RPST = 0x0
6174 23:16:28.042328 RD_PRE = 0x0
6175 23:16:28.042430 WR_PRE = 0x1
6176 23:16:28.045982 WR_PST = 0x0
6177 23:16:28.046077 DBI_WR = 0x0
6178 23:16:28.048711 DBI_RD = 0x0
6179 23:16:28.048804 OTF = 0x1
6180 23:16:28.051950 ===================================
6181 23:16:28.058944 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6182 23:16:28.063452 nWR fixed to 30
6183 23:16:28.066892 [ModeRegInit_LP4] CH0 RK0
6184 23:16:28.066989 [ModeRegInit_LP4] CH0 RK1
6185 23:16:28.070212 [ModeRegInit_LP4] CH1 RK0
6186 23:16:28.073781 [ModeRegInit_LP4] CH1 RK1
6187 23:16:28.073877 match AC timing 19
6188 23:16:28.080161 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6189 23:16:28.084013 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6190 23:16:28.086940 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6191 23:16:28.093500 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6192 23:16:28.097200 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6193 23:16:28.097280 ==
6194 23:16:28.100155 Dram Type= 6, Freq= 0, CH_0, rank 0
6195 23:16:28.103515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6196 23:16:28.103597 ==
6197 23:16:28.110389 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6198 23:16:28.117019 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6199 23:16:28.120121 [CA 0] Center 36 (8~64) winsize 57
6200 23:16:28.123421 [CA 1] Center 36 (8~64) winsize 57
6201 23:16:28.126728 [CA 2] Center 36 (8~64) winsize 57
6202 23:16:28.129804 [CA 3] Center 36 (8~64) winsize 57
6203 23:16:28.129883 [CA 4] Center 36 (8~64) winsize 57
6204 23:16:28.133251 [CA 5] Center 36 (8~64) winsize 57
6205 23:16:28.133347
6206 23:16:28.140140 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6207 23:16:28.140238
6208 23:16:28.143199 [CATrainingPosCal] consider 1 rank data
6209 23:16:28.146514 u2DelayCellTimex100 = 270/100 ps
6210 23:16:28.150175 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6211 23:16:28.153766 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6212 23:16:28.156840 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 23:16:28.160066 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 23:16:28.163424 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 23:16:28.166397 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 23:16:28.166468
6217 23:16:28.169543 CA PerBit enable=1, Macro0, CA PI delay=36
6218 23:16:28.169648
6219 23:16:28.173213 [CBTSetCACLKResult] CA Dly = 36
6220 23:16:28.176253 CS Dly: 1 (0~32)
6221 23:16:28.176353 ==
6222 23:16:28.179899 Dram Type= 6, Freq= 0, CH_0, rank 1
6223 23:16:28.182905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6224 23:16:28.182978 ==
6225 23:16:28.189682 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6226 23:16:28.193419 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6227 23:16:28.196340 [CA 0] Center 36 (8~64) winsize 57
6228 23:16:28.199851 [CA 1] Center 36 (8~64) winsize 57
6229 23:16:28.203249 [CA 2] Center 36 (8~64) winsize 57
6230 23:16:28.206642 [CA 3] Center 36 (8~64) winsize 57
6231 23:16:28.209462 [CA 4] Center 36 (8~64) winsize 57
6232 23:16:28.213431 [CA 5] Center 36 (8~64) winsize 57
6233 23:16:28.213533
6234 23:16:28.216383 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6235 23:16:28.216479
6236 23:16:28.219435 [CATrainingPosCal] consider 2 rank data
6237 23:16:28.222889 u2DelayCellTimex100 = 270/100 ps
6238 23:16:28.226099 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6239 23:16:28.229542 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6240 23:16:28.235934 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 23:16:28.239391 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 23:16:28.243062 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 23:16:28.246476 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 23:16:28.246549
6245 23:16:28.249802 CA PerBit enable=1, Macro0, CA PI delay=36
6246 23:16:28.249874
6247 23:16:28.252556 [CBTSetCACLKResult] CA Dly = 36
6248 23:16:28.252651 CS Dly: 1 (0~32)
6249 23:16:28.252738
6250 23:16:28.255899 ----->DramcWriteLeveling(PI) begin...
6251 23:16:28.259185 ==
6252 23:16:28.263090 Dram Type= 6, Freq= 0, CH_0, rank 0
6253 23:16:28.266243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6254 23:16:28.266315 ==
6255 23:16:28.269610 Write leveling (Byte 0): 40 => 8
6256 23:16:28.272498 Write leveling (Byte 1): 40 => 8
6257 23:16:28.276145 DramcWriteLeveling(PI) end<-----
6258 23:16:28.276223
6259 23:16:28.276283 ==
6260 23:16:28.279310 Dram Type= 6, Freq= 0, CH_0, rank 0
6261 23:16:28.282640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6262 23:16:28.282718 ==
6263 23:16:28.286145 [Gating] SW mode calibration
6264 23:16:28.292526 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6265 23:16:28.296168 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6266 23:16:28.302478 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6267 23:16:28.305983 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6268 23:16:28.309472 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6269 23:16:28.316136 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
6270 23:16:28.319187 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6271 23:16:28.322724 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6272 23:16:28.329460 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 23:16:28.332709 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 23:16:28.336013 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6275 23:16:28.339228 Total UI for P1: 0, mck2ui 16
6276 23:16:28.342427 best dqsien dly found for B0: ( 0, 14, 24)
6277 23:16:28.345671 Total UI for P1: 0, mck2ui 16
6278 23:16:28.349280 best dqsien dly found for B1: ( 0, 14, 24)
6279 23:16:28.352308 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6280 23:16:28.355609 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6281 23:16:28.359062
6282 23:16:28.362254 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6283 23:16:28.365712 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6284 23:16:28.368931 [Gating] SW calibration Done
6285 23:16:28.369010 ==
6286 23:16:28.372117 Dram Type= 6, Freq= 0, CH_0, rank 0
6287 23:16:28.375580 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6288 23:16:28.375666 ==
6289 23:16:28.378980 RX Vref Scan: 0
6290 23:16:28.379092
6291 23:16:28.379184 RX Vref 0 -> 0, step: 1
6292 23:16:28.379271
6293 23:16:28.381930 RX Delay -410 -> 252, step: 16
6294 23:16:28.385252 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6295 23:16:28.392121 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6296 23:16:28.395543 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6297 23:16:28.398707 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6298 23:16:28.401792 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6299 23:16:28.408363 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6300 23:16:28.411927 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6301 23:16:28.415299 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6302 23:16:28.418370 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6303 23:16:28.425234 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6304 23:16:28.428921 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6305 23:16:28.431678 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6306 23:16:28.434997 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6307 23:16:28.441583 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6308 23:16:28.444972 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6309 23:16:28.448435 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6310 23:16:28.448513 ==
6311 23:16:28.451548 Dram Type= 6, Freq= 0, CH_0, rank 0
6312 23:16:28.458513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6313 23:16:28.458592 ==
6314 23:16:28.458654 DQS Delay:
6315 23:16:28.461712 DQS0 = 27, DQS1 = 35
6316 23:16:28.461790 DQM Delay:
6317 23:16:28.461854 DQM0 = 10, DQM1 = 11
6318 23:16:28.465341 DQ Delay:
6319 23:16:28.468551 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6320 23:16:28.468634 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6321 23:16:28.471505 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6322 23:16:28.474783 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6323 23:16:28.474862
6324 23:16:28.474923
6325 23:16:28.478642 ==
6326 23:16:28.481626 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 23:16:28.484966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 23:16:28.485058 ==
6329 23:16:28.485124
6330 23:16:28.485182
6331 23:16:28.488353 TX Vref Scan disable
6332 23:16:28.488458 == TX Byte 0 ==
6333 23:16:28.491786 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6334 23:16:28.498053 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6335 23:16:28.498129 == TX Byte 1 ==
6336 23:16:28.501558 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 23:16:28.508265 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 23:16:28.508365 ==
6339 23:16:28.511674 Dram Type= 6, Freq= 0, CH_0, rank 0
6340 23:16:28.515014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6341 23:16:28.515120 ==
6342 23:16:28.515207
6343 23:16:28.515291
6344 23:16:28.518051 TX Vref Scan disable
6345 23:16:28.518120 == TX Byte 0 ==
6346 23:16:28.521565 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 23:16:28.528457 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 23:16:28.528564 == TX Byte 1 ==
6349 23:16:28.531563 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 23:16:28.538244 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 23:16:28.538317
6352 23:16:28.538376 [DATLAT]
6353 23:16:28.538433 Freq=400, CH0 RK0
6354 23:16:28.538550
6355 23:16:28.541401 DATLAT Default: 0xf
6356 23:16:28.541496 0, 0xFFFF, sum = 0
6357 23:16:28.544708 1, 0xFFFF, sum = 0
6358 23:16:28.548130 2, 0xFFFF, sum = 0
6359 23:16:28.548228 3, 0xFFFF, sum = 0
6360 23:16:28.551502 4, 0xFFFF, sum = 0
6361 23:16:28.551577 5, 0xFFFF, sum = 0
6362 23:16:28.554751 6, 0xFFFF, sum = 0
6363 23:16:28.554855 7, 0xFFFF, sum = 0
6364 23:16:28.558351 8, 0xFFFF, sum = 0
6365 23:16:28.558456 9, 0xFFFF, sum = 0
6366 23:16:28.561332 10, 0xFFFF, sum = 0
6367 23:16:28.561431 11, 0xFFFF, sum = 0
6368 23:16:28.564496 12, 0xFFFF, sum = 0
6369 23:16:28.564592 13, 0x0, sum = 1
6370 23:16:28.568060 14, 0x0, sum = 2
6371 23:16:28.568141 15, 0x0, sum = 3
6372 23:16:28.571671 16, 0x0, sum = 4
6373 23:16:28.571745 best_step = 14
6374 23:16:28.571819
6375 23:16:28.571877 ==
6376 23:16:28.574684 Dram Type= 6, Freq= 0, CH_0, rank 0
6377 23:16:28.578173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6378 23:16:28.581527 ==
6379 23:16:28.581669 RX Vref Scan: 1
6380 23:16:28.581757
6381 23:16:28.584589 RX Vref 0 -> 0, step: 1
6382 23:16:28.584657
6383 23:16:28.587925 RX Delay -311 -> 252, step: 8
6384 23:16:28.587991
6385 23:16:28.591113 Set Vref, RX VrefLevel [Byte0]: 57
6386 23:16:28.594331 [Byte1]: 49
6387 23:16:28.594409
6388 23:16:28.598138 Final RX Vref Byte 0 = 57 to rank0
6389 23:16:28.601163 Final RX Vref Byte 1 = 49 to rank0
6390 23:16:28.604612 Final RX Vref Byte 0 = 57 to rank1
6391 23:16:28.608070 Final RX Vref Byte 1 = 49 to rank1==
6392 23:16:28.611028 Dram Type= 6, Freq= 0, CH_0, rank 0
6393 23:16:28.614281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6394 23:16:28.614363 ==
6395 23:16:28.617915 DQS Delay:
6396 23:16:28.617993 DQS0 = 28, DQS1 = 36
6397 23:16:28.620954 DQM Delay:
6398 23:16:28.621032 DQM0 = 10, DQM1 = 13
6399 23:16:28.621094 DQ Delay:
6400 23:16:28.624415 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6401 23:16:28.627508 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6402 23:16:28.630896 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6403 23:16:28.634277 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6404 23:16:28.634356
6405 23:16:28.634419
6406 23:16:28.644270 [DQSOSCAuto] RK0, (LSB)MR18= 0xc4b1, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6407 23:16:28.647392 CH0 RK0: MR19=C0C, MR18=C4B1
6408 23:16:28.650803 CH0_RK0: MR19=0xC0C, MR18=0xC4B1, DQSOSC=385, MR23=63, INC=398, DEC=265
6409 23:16:28.654050 ==
6410 23:16:28.654129 Dram Type= 6, Freq= 0, CH_0, rank 1
6411 23:16:28.660808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6412 23:16:28.660888 ==
6413 23:16:28.664523 [Gating] SW mode calibration
6414 23:16:28.671008 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6415 23:16:28.674330 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6416 23:16:28.680802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6417 23:16:28.684065 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6418 23:16:28.687325 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6419 23:16:28.694019 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6420 23:16:28.697336 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6421 23:16:28.700423 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6422 23:16:28.706959 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 23:16:28.710379 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 23:16:28.713835 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6425 23:16:28.717151 Total UI for P1: 0, mck2ui 16
6426 23:16:28.720382 best dqsien dly found for B0: ( 0, 14, 24)
6427 23:16:28.723688 Total UI for P1: 0, mck2ui 16
6428 23:16:28.727039 best dqsien dly found for B1: ( 0, 14, 24)
6429 23:16:28.730464 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6430 23:16:28.733800 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6431 23:16:28.733880
6432 23:16:28.740558 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6433 23:16:28.743957 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6434 23:16:28.744036 [Gating] SW calibration Done
6435 23:16:28.746952 ==
6436 23:16:28.747031 Dram Type= 6, Freq= 0, CH_0, rank 1
6437 23:16:28.753765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 23:16:28.753849 ==
6439 23:16:28.753912 RX Vref Scan: 0
6440 23:16:28.753971
6441 23:16:28.756993 RX Vref 0 -> 0, step: 1
6442 23:16:28.757072
6443 23:16:28.760602 RX Delay -410 -> 252, step: 16
6444 23:16:28.763715 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6445 23:16:28.767389 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6446 23:16:28.773857 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6447 23:16:28.777462 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6448 23:16:28.780429 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6449 23:16:28.783851 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6450 23:16:28.790702 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6451 23:16:28.793983 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6452 23:16:28.797411 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6453 23:16:28.800337 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6454 23:16:28.806752 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6455 23:16:28.810364 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6456 23:16:28.813750 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6457 23:16:28.816683 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6458 23:16:28.823360 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6459 23:16:28.826629 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6460 23:16:28.826745 ==
6461 23:16:28.829776 Dram Type= 6, Freq= 0, CH_0, rank 1
6462 23:16:28.833571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 23:16:28.833668 ==
6464 23:16:28.836371 DQS Delay:
6465 23:16:28.836476 DQS0 = 19, DQS1 = 35
6466 23:16:28.839683 DQM Delay:
6467 23:16:28.839788 DQM0 = 5, DQM1 = 12
6468 23:16:28.839876 DQ Delay:
6469 23:16:28.843192 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6470 23:16:28.846814 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6471 23:16:28.849856 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6472 23:16:28.852981 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6473 23:16:28.853093
6474 23:16:28.853227
6475 23:16:28.853313 ==
6476 23:16:28.856368 Dram Type= 6, Freq= 0, CH_0, rank 1
6477 23:16:28.863181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6478 23:16:28.863259 ==
6479 23:16:28.863321
6480 23:16:28.863378
6481 23:16:28.863434 TX Vref Scan disable
6482 23:16:28.866003 == TX Byte 0 ==
6483 23:16:28.869418 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6484 23:16:28.872892 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6485 23:16:28.876150 == TX Byte 1 ==
6486 23:16:28.879802 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6487 23:16:28.882678 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6488 23:16:28.882765 ==
6489 23:16:28.886047 Dram Type= 6, Freq= 0, CH_0, rank 1
6490 23:16:28.892433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6491 23:16:28.892516 ==
6492 23:16:28.892580
6493 23:16:28.892639
6494 23:16:28.892695 TX Vref Scan disable
6495 23:16:28.895996 == TX Byte 0 ==
6496 23:16:28.899203 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6497 23:16:28.902586 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6498 23:16:28.905869 == TX Byte 1 ==
6499 23:16:28.909334 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6500 23:16:28.912749 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6501 23:16:28.912861
6502 23:16:28.915630 [DATLAT]
6503 23:16:28.915702 Freq=400, CH0 RK1
6504 23:16:28.915789
6505 23:16:28.919855 DATLAT Default: 0xe
6506 23:16:28.919952 0, 0xFFFF, sum = 0
6507 23:16:28.922525 1, 0xFFFF, sum = 0
6508 23:16:28.922607 2, 0xFFFF, sum = 0
6509 23:16:28.925796 3, 0xFFFF, sum = 0
6510 23:16:28.925869 4, 0xFFFF, sum = 0
6511 23:16:28.929113 5, 0xFFFF, sum = 0
6512 23:16:28.929215 6, 0xFFFF, sum = 0
6513 23:16:28.932686 7, 0xFFFF, sum = 0
6514 23:16:28.932759 8, 0xFFFF, sum = 0
6515 23:16:28.935828 9, 0xFFFF, sum = 0
6516 23:16:28.939520 10, 0xFFFF, sum = 0
6517 23:16:28.939601 11, 0xFFFF, sum = 0
6518 23:16:28.942505 12, 0xFFFF, sum = 0
6519 23:16:28.942586 13, 0x0, sum = 1
6520 23:16:28.945788 14, 0x0, sum = 2
6521 23:16:28.945869 15, 0x0, sum = 3
6522 23:16:28.945932 16, 0x0, sum = 4
6523 23:16:28.949156 best_step = 14
6524 23:16:28.949268
6525 23:16:28.949358 ==
6526 23:16:28.952512 Dram Type= 6, Freq= 0, CH_0, rank 1
6527 23:16:28.955803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6528 23:16:28.955879 ==
6529 23:16:28.959075 RX Vref Scan: 0
6530 23:16:28.959175
6531 23:16:28.962486 RX Vref 0 -> 0, step: 1
6532 23:16:28.962583
6533 23:16:28.962671 RX Delay -311 -> 252, step: 8
6534 23:16:28.971241 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6535 23:16:28.974208 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6536 23:16:28.977715 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6537 23:16:28.983898 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6538 23:16:28.987182 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6539 23:16:28.990556 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6540 23:16:28.993683 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6541 23:16:28.997131 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6542 23:16:29.004070 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6543 23:16:29.007183 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6544 23:16:29.010397 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6545 23:16:29.017063 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6546 23:16:29.020582 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6547 23:16:29.023956 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6548 23:16:29.027067 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6549 23:16:29.033873 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6550 23:16:29.033953 ==
6551 23:16:29.037013 Dram Type= 6, Freq= 0, CH_0, rank 1
6552 23:16:29.040418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6553 23:16:29.040516 ==
6554 23:16:29.040604 DQS Delay:
6555 23:16:29.043719 DQS0 = 24, DQS1 = 32
6556 23:16:29.043789 DQM Delay:
6557 23:16:29.047035 DQM0 = 7, DQM1 = 9
6558 23:16:29.047107 DQ Delay:
6559 23:16:29.050583 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6560 23:16:29.053715 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6561 23:16:29.056908 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6562 23:16:29.060305 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6563 23:16:29.060378
6564 23:16:29.060439
6565 23:16:29.066968 [DQSOSCAuto] RK1, (LSB)MR18= 0xb555, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6566 23:16:29.070128 CH0 RK1: MR19=C0C, MR18=B555
6567 23:16:29.076954 CH0_RK1: MR19=0xC0C, MR18=0xB555, DQSOSC=387, MR23=63, INC=394, DEC=262
6568 23:16:29.080511 [RxdqsGatingPostProcess] freq 400
6569 23:16:29.083869 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6570 23:16:29.087346 best DQS0 dly(2T, 0.5T) = (0, 10)
6571 23:16:29.090740 best DQS1 dly(2T, 0.5T) = (0, 10)
6572 23:16:29.093848 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6573 23:16:29.096849 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6574 23:16:29.100202 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 23:16:29.103969 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 23:16:29.106870 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 23:16:29.110283 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 23:16:29.113356 Pre-setting of DQS Precalculation
6579 23:16:29.116636 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6580 23:16:29.120375 ==
6581 23:16:29.120456 Dram Type= 6, Freq= 0, CH_1, rank 0
6582 23:16:29.126638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 23:16:29.126718 ==
6584 23:16:29.130188 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6585 23:16:29.136761 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6586 23:16:29.140173 [CA 0] Center 36 (8~64) winsize 57
6587 23:16:29.143481 [CA 1] Center 36 (8~64) winsize 57
6588 23:16:29.147041 [CA 2] Center 36 (8~64) winsize 57
6589 23:16:29.150185 [CA 3] Center 36 (8~64) winsize 57
6590 23:16:29.153204 [CA 4] Center 36 (8~64) winsize 57
6591 23:16:29.156579 [CA 5] Center 36 (8~64) winsize 57
6592 23:16:29.156659
6593 23:16:29.160248 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6594 23:16:29.160327
6595 23:16:29.163373 [CATrainingPosCal] consider 1 rank data
6596 23:16:29.166745 u2DelayCellTimex100 = 270/100 ps
6597 23:16:29.170108 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6598 23:16:29.173086 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6599 23:16:29.176435 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 23:16:29.179751 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 23:16:29.183088 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 23:16:29.189906 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 23:16:29.189986
6604 23:16:29.193250 CA PerBit enable=1, Macro0, CA PI delay=36
6605 23:16:29.193329
6606 23:16:29.196343 [CBTSetCACLKResult] CA Dly = 36
6607 23:16:29.196422 CS Dly: 1 (0~32)
6608 23:16:29.196485 ==
6609 23:16:29.199588 Dram Type= 6, Freq= 0, CH_1, rank 1
6610 23:16:29.203440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 23:16:29.207114 ==
6612 23:16:29.209528 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6613 23:16:29.216396 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6614 23:16:29.220074 [CA 0] Center 36 (8~64) winsize 57
6615 23:16:29.223174 [CA 1] Center 36 (8~64) winsize 57
6616 23:16:29.226511 [CA 2] Center 36 (8~64) winsize 57
6617 23:16:29.229728 [CA 3] Center 36 (8~64) winsize 57
6618 23:16:29.233375 [CA 4] Center 36 (8~64) winsize 57
6619 23:16:29.236626 [CA 5] Center 36 (8~64) winsize 57
6620 23:16:29.236706
6621 23:16:29.239530 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6622 23:16:29.239610
6623 23:16:29.243003 [CATrainingPosCal] consider 2 rank data
6624 23:16:29.246268 u2DelayCellTimex100 = 270/100 ps
6625 23:16:29.249688 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6626 23:16:29.253278 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6627 23:16:29.256461 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 23:16:29.259778 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 23:16:29.262940 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 23:16:29.266153 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 23:16:29.266232
6632 23:16:29.270222 CA PerBit enable=1, Macro0, CA PI delay=36
6633 23:16:29.270302
6634 23:16:29.272792 [CBTSetCACLKResult] CA Dly = 36
6635 23:16:29.276223 CS Dly: 1 (0~32)
6636 23:16:29.276302
6637 23:16:29.279489 ----->DramcWriteLeveling(PI) begin...
6638 23:16:29.279571 ==
6639 23:16:29.283370 Dram Type= 6, Freq= 0, CH_1, rank 0
6640 23:16:29.286173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6641 23:16:29.286336 ==
6642 23:16:29.289338 Write leveling (Byte 0): 40 => 8
6643 23:16:29.292966 Write leveling (Byte 1): 40 => 8
6644 23:16:29.296135 DramcWriteLeveling(PI) end<-----
6645 23:16:29.296215
6646 23:16:29.296277 ==
6647 23:16:29.299870 Dram Type= 6, Freq= 0, CH_1, rank 0
6648 23:16:29.302792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6649 23:16:29.302873 ==
6650 23:16:29.306638 [Gating] SW mode calibration
6651 23:16:29.312961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6652 23:16:29.319699 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6653 23:16:29.323049 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6654 23:16:29.329683 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6655 23:16:29.333133 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6656 23:16:29.336112 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6657 23:16:29.339612 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6658 23:16:29.346218 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6659 23:16:29.349461 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 23:16:29.352787 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 23:16:29.359341 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6662 23:16:29.363037 Total UI for P1: 0, mck2ui 16
6663 23:16:29.365701 best dqsien dly found for B0: ( 0, 14, 24)
6664 23:16:29.369473 Total UI for P1: 0, mck2ui 16
6665 23:16:29.372402 best dqsien dly found for B1: ( 0, 14, 24)
6666 23:16:29.375859 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6667 23:16:29.379525 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6668 23:16:29.379620
6669 23:16:29.382464 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6670 23:16:29.385856 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6671 23:16:29.389246 [Gating] SW calibration Done
6672 23:16:29.389314 ==
6673 23:16:29.392552 Dram Type= 6, Freq= 0, CH_1, rank 0
6674 23:16:29.395904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6675 23:16:29.395983 ==
6676 23:16:29.398938 RX Vref Scan: 0
6677 23:16:29.399017
6678 23:16:29.402573 RX Vref 0 -> 0, step: 1
6679 23:16:29.402654
6680 23:16:29.402718 RX Delay -410 -> 252, step: 16
6681 23:16:29.409063 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6682 23:16:29.412738 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6683 23:16:29.415858 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6684 23:16:29.419420 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6685 23:16:29.425730 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6686 23:16:29.429382 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6687 23:16:29.432732 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6688 23:16:29.435805 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6689 23:16:29.442771 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6690 23:16:29.445766 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6691 23:16:29.449064 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6692 23:16:29.452399 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6693 23:16:29.458858 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6694 23:16:29.462578 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6695 23:16:29.465781 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6696 23:16:29.472195 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6697 23:16:29.472276 ==
6698 23:16:29.475466 Dram Type= 6, Freq= 0, CH_1, rank 0
6699 23:16:29.478774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6700 23:16:29.478865 ==
6701 23:16:29.478929 DQS Delay:
6702 23:16:29.482364 DQS0 = 27, DQS1 = 35
6703 23:16:29.482444 DQM Delay:
6704 23:16:29.485375 DQM0 = 10, DQM1 = 13
6705 23:16:29.485456 DQ Delay:
6706 23:16:29.489231 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6707 23:16:29.492337 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6708 23:16:29.495265 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6709 23:16:29.498532 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6710 23:16:29.498620
6711 23:16:29.498688
6712 23:16:29.498747 ==
6713 23:16:29.501964 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 23:16:29.505425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 23:16:29.505530 ==
6716 23:16:29.505663
6717 23:16:29.505750
6718 23:16:29.508901 TX Vref Scan disable
6719 23:16:29.508996 == TX Byte 0 ==
6720 23:16:29.515234 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6721 23:16:29.518762 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6722 23:16:29.518844 == TX Byte 1 ==
6723 23:16:29.525321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 23:16:29.528737 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 23:16:29.528819 ==
6726 23:16:29.532106 Dram Type= 6, Freq= 0, CH_1, rank 0
6727 23:16:29.535293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6728 23:16:29.535375 ==
6729 23:16:29.535440
6730 23:16:29.535499
6731 23:16:29.538717 TX Vref Scan disable
6732 23:16:29.538798 == TX Byte 0 ==
6733 23:16:29.545714 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 23:16:29.548886 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 23:16:29.548967 == TX Byte 1 ==
6736 23:16:29.555342 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 23:16:29.558731 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 23:16:29.558813
6739 23:16:29.558877 [DATLAT]
6740 23:16:29.561705 Freq=400, CH1 RK0
6741 23:16:29.561786
6742 23:16:29.561850 DATLAT Default: 0xf
6743 23:16:29.564963 0, 0xFFFF, sum = 0
6744 23:16:29.565045 1, 0xFFFF, sum = 0
6745 23:16:29.568509 2, 0xFFFF, sum = 0
6746 23:16:29.568591 3, 0xFFFF, sum = 0
6747 23:16:29.571818 4, 0xFFFF, sum = 0
6748 23:16:29.571901 5, 0xFFFF, sum = 0
6749 23:16:29.575080 6, 0xFFFF, sum = 0
6750 23:16:29.575162 7, 0xFFFF, sum = 0
6751 23:16:29.578347 8, 0xFFFF, sum = 0
6752 23:16:29.582054 9, 0xFFFF, sum = 0
6753 23:16:29.582136 10, 0xFFFF, sum = 0
6754 23:16:29.585060 11, 0xFFFF, sum = 0
6755 23:16:29.585142 12, 0xFFFF, sum = 0
6756 23:16:29.588278 13, 0x0, sum = 1
6757 23:16:29.588360 14, 0x0, sum = 2
6758 23:16:29.592206 15, 0x0, sum = 3
6759 23:16:29.592288 16, 0x0, sum = 4
6760 23:16:29.592354 best_step = 14
6761 23:16:29.592414
6762 23:16:29.595362 ==
6763 23:16:29.598740 Dram Type= 6, Freq= 0, CH_1, rank 0
6764 23:16:29.601865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6765 23:16:29.601947 ==
6766 23:16:29.602011 RX Vref Scan: 1
6767 23:16:29.602070
6768 23:16:29.604987 RX Vref 0 -> 0, step: 1
6769 23:16:29.605067
6770 23:16:29.608177 RX Delay -311 -> 252, step: 8
6771 23:16:29.608259
6772 23:16:29.611441 Set Vref, RX VrefLevel [Byte0]: 57
6773 23:16:29.614948 [Byte1]: 48
6774 23:16:29.618779
6775 23:16:29.618859 Final RX Vref Byte 0 = 57 to rank0
6776 23:16:29.622092 Final RX Vref Byte 1 = 48 to rank0
6777 23:16:29.625000 Final RX Vref Byte 0 = 57 to rank1
6778 23:16:29.628403 Final RX Vref Byte 1 = 48 to rank1==
6779 23:16:29.631741 Dram Type= 6, Freq= 0, CH_1, rank 0
6780 23:16:29.638329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6781 23:16:29.638409 ==
6782 23:16:29.638472 DQS Delay:
6783 23:16:29.641872 DQS0 = 28, DQS1 = 32
6784 23:16:29.641951 DQM Delay:
6785 23:16:29.642014 DQM0 = 9, DQM1 = 12
6786 23:16:29.645271 DQ Delay:
6787 23:16:29.645349 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6788 23:16:29.648543 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6789 23:16:29.651548 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =4
6790 23:16:29.654922 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =24
6791 23:16:29.655002
6792 23:16:29.655077
6793 23:16:29.664958 [DQSOSCAuto] RK0, (LSB)MR18= 0x91c9, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6794 23:16:29.668523 CH1 RK0: MR19=C0C, MR18=91C9
6795 23:16:29.675362 CH1_RK0: MR19=0xC0C, MR18=0x91C9, DQSOSC=384, MR23=63, INC=400, DEC=267
6796 23:16:29.675437 ==
6797 23:16:29.678171 Dram Type= 6, Freq= 0, CH_1, rank 1
6798 23:16:29.681794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6799 23:16:29.681891 ==
6800 23:16:29.684983 [Gating] SW mode calibration
6801 23:16:29.691569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6802 23:16:29.694664 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6803 23:16:29.701454 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6804 23:16:29.704962 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6805 23:16:29.708465 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6806 23:16:29.714921 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6807 23:16:29.718377 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6808 23:16:29.721247 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6809 23:16:29.727849 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 23:16:29.731151 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 23:16:29.734669 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6812 23:16:29.737929 Total UI for P1: 0, mck2ui 16
6813 23:16:29.741066 best dqsien dly found for B0: ( 0, 14, 24)
6814 23:16:29.744511 Total UI for P1: 0, mck2ui 16
6815 23:16:29.747912 best dqsien dly found for B1: ( 0, 14, 24)
6816 23:16:29.751404 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6817 23:16:29.754290 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6818 23:16:29.757702
6819 23:16:29.761302 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6820 23:16:29.764623 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6821 23:16:29.767778 [Gating] SW calibration Done
6822 23:16:29.767858 ==
6823 23:16:29.771180 Dram Type= 6, Freq= 0, CH_1, rank 1
6824 23:16:29.774681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 23:16:29.774788 ==
6826 23:16:29.774883 RX Vref Scan: 0
6827 23:16:29.774960
6828 23:16:29.777832 RX Vref 0 -> 0, step: 1
6829 23:16:29.777911
6830 23:16:29.780967 RX Delay -410 -> 252, step: 16
6831 23:16:29.784320 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6832 23:16:29.790945 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6833 23:16:29.794414 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6834 23:16:29.798133 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6835 23:16:29.801375 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6836 23:16:29.804799 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6837 23:16:29.811037 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6838 23:16:29.814402 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6839 23:16:29.817559 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6840 23:16:29.821579 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6841 23:16:29.828156 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6842 23:16:29.831191 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6843 23:16:29.834556 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6844 23:16:29.837942 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6845 23:16:29.844689 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6846 23:16:29.848245 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6847 23:16:29.848324 ==
6848 23:16:29.851264 Dram Type= 6, Freq= 0, CH_1, rank 1
6849 23:16:29.854654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 23:16:29.854734 ==
6851 23:16:29.857814 DQS Delay:
6852 23:16:29.857922 DQS0 = 27, DQS1 = 35
6853 23:16:29.861251 DQM Delay:
6854 23:16:29.861349 DQM0 = 12, DQM1 = 13
6855 23:16:29.861437 DQ Delay:
6856 23:16:29.864541 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6857 23:16:29.867851 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6858 23:16:29.871276 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6859 23:16:29.874905 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6860 23:16:29.875010
6861 23:16:29.875095
6862 23:16:29.875155 ==
6863 23:16:29.878064 Dram Type= 6, Freq= 0, CH_1, rank 1
6864 23:16:29.884444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6865 23:16:29.884525 ==
6866 23:16:29.884587
6867 23:16:29.884645
6868 23:16:29.884701 TX Vref Scan disable
6869 23:16:29.887748 == TX Byte 0 ==
6870 23:16:29.891432 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6871 23:16:29.894305 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6872 23:16:29.897666 == TX Byte 1 ==
6873 23:16:29.901169 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6874 23:16:29.904394 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6875 23:16:29.904475 ==
6876 23:16:29.907757 Dram Type= 6, Freq= 0, CH_1, rank 1
6877 23:16:29.914903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6878 23:16:29.914984 ==
6879 23:16:29.915047
6880 23:16:29.915105
6881 23:16:29.915161 TX Vref Scan disable
6882 23:16:29.917475 == TX Byte 0 ==
6883 23:16:29.921304 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6884 23:16:29.924267 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6885 23:16:29.927725 == TX Byte 1 ==
6886 23:16:29.930638 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6887 23:16:29.934141 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6888 23:16:29.934221
6889 23:16:29.937337 [DATLAT]
6890 23:16:29.937416 Freq=400, CH1 RK1
6891 23:16:29.937479
6892 23:16:29.940893 DATLAT Default: 0xe
6893 23:16:29.940971 0, 0xFFFF, sum = 0
6894 23:16:29.944109 1, 0xFFFF, sum = 0
6895 23:16:29.944190 2, 0xFFFF, sum = 0
6896 23:16:29.947533 3, 0xFFFF, sum = 0
6897 23:16:29.947613 4, 0xFFFF, sum = 0
6898 23:16:29.951091 5, 0xFFFF, sum = 0
6899 23:16:29.951171 6, 0xFFFF, sum = 0
6900 23:16:29.954182 7, 0xFFFF, sum = 0
6901 23:16:29.954263 8, 0xFFFF, sum = 0
6902 23:16:29.957503 9, 0xFFFF, sum = 0
6903 23:16:29.957588 10, 0xFFFF, sum = 0
6904 23:16:29.960895 11, 0xFFFF, sum = 0
6905 23:16:29.964450 12, 0xFFFF, sum = 0
6906 23:16:29.964530 13, 0x0, sum = 1
6907 23:16:29.964594 14, 0x0, sum = 2
6908 23:16:29.967528 15, 0x0, sum = 3
6909 23:16:29.967608 16, 0x0, sum = 4
6910 23:16:29.970876 best_step = 14
6911 23:16:29.970956
6912 23:16:29.971018 ==
6913 23:16:29.974349 Dram Type= 6, Freq= 0, CH_1, rank 1
6914 23:16:29.977611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6915 23:16:29.977705 ==
6916 23:16:29.981132 RX Vref Scan: 0
6917 23:16:29.981211
6918 23:16:29.981273 RX Vref 0 -> 0, step: 1
6919 23:16:29.983779
6920 23:16:29.983859 RX Delay -311 -> 252, step: 8
6921 23:16:29.992412 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6922 23:16:29.995443 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6923 23:16:29.998960 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6924 23:16:30.002460 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6925 23:16:30.009305 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6926 23:16:30.012691 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6927 23:16:30.015922 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6928 23:16:30.018955 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6929 23:16:30.025515 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6930 23:16:30.028964 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6931 23:16:30.032815 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6932 23:16:30.036164 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6933 23:16:30.042148 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6934 23:16:30.045556 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6935 23:16:30.048961 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6936 23:16:30.052398 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6937 23:16:30.055877 ==
6938 23:16:30.055959 Dram Type= 6, Freq= 0, CH_1, rank 1
6939 23:16:30.062309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6940 23:16:30.062409 ==
6941 23:16:30.062502 DQS Delay:
6942 23:16:30.065856 DQS0 = 32, DQS1 = 32
6943 23:16:30.065935 DQM Delay:
6944 23:16:30.069196 DQM0 = 15, DQM1 = 11
6945 23:16:30.069275 DQ Delay:
6946 23:16:30.072625 DQ0 =20, DQ1 =12, DQ2 =0, DQ3 =12
6947 23:16:30.076161 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =16
6948 23:16:30.079276 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6949 23:16:30.082727 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6950 23:16:30.082813
6951 23:16:30.082876
6952 23:16:30.088904 [DQSOSCAuto] RK1, (LSB)MR18= 0xc456, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps
6953 23:16:30.092693 CH1 RK1: MR19=C0C, MR18=C456
6954 23:16:30.098773 CH1_RK1: MR19=0xC0C, MR18=0xC456, DQSOSC=385, MR23=63, INC=398, DEC=265
6955 23:16:30.102360 [RxdqsGatingPostProcess] freq 400
6956 23:16:30.105408 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6957 23:16:30.108845 best DQS0 dly(2T, 0.5T) = (0, 10)
6958 23:16:30.112259 best DQS1 dly(2T, 0.5T) = (0, 10)
6959 23:16:30.115589 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6960 23:16:30.118641 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6961 23:16:30.122559 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 23:16:30.125509 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 23:16:30.128526 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 23:16:30.131883 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 23:16:30.135311 Pre-setting of DQS Precalculation
6966 23:16:30.138927 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6967 23:16:30.148971 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6968 23:16:30.155229 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6969 23:16:30.155311
6970 23:16:30.155374
6971 23:16:30.158704 [Calibration Summary] 800 Mbps
6972 23:16:30.158785 CH 0, Rank 0
6973 23:16:30.162190 SW Impedance : PASS
6974 23:16:30.162272 DUTY Scan : NO K
6975 23:16:30.164906 ZQ Calibration : PASS
6976 23:16:30.168344 Jitter Meter : NO K
6977 23:16:30.168424 CBT Training : PASS
6978 23:16:30.171585 Write leveling : PASS
6979 23:16:30.175128 RX DQS gating : PASS
6980 23:16:30.175208 RX DQ/DQS(RDDQC) : PASS
6981 23:16:30.178549 TX DQ/DQS : PASS
6982 23:16:30.181861 RX DATLAT : PASS
6983 23:16:30.181941 RX DQ/DQS(Engine): PASS
6984 23:16:30.185156 TX OE : NO K
6985 23:16:30.185241 All Pass.
6986 23:16:30.185305
6987 23:16:30.188867 CH 0, Rank 1
6988 23:16:30.188948 SW Impedance : PASS
6989 23:16:30.191996 DUTY Scan : NO K
6990 23:16:30.195279 ZQ Calibration : PASS
6991 23:16:30.195359 Jitter Meter : NO K
6992 23:16:30.198612 CBT Training : PASS
6993 23:16:30.201863 Write leveling : NO K
6994 23:16:30.201942 RX DQS gating : PASS
6995 23:16:30.205109 RX DQ/DQS(RDDQC) : PASS
6996 23:16:30.205188 TX DQ/DQS : PASS
6997 23:16:30.208674 RX DATLAT : PASS
6998 23:16:30.211934 RX DQ/DQS(Engine): PASS
6999 23:16:30.212014 TX OE : NO K
7000 23:16:30.215279 All Pass.
7001 23:16:30.215358
7002 23:16:30.215421 CH 1, Rank 0
7003 23:16:30.218808 SW Impedance : PASS
7004 23:16:30.218887 DUTY Scan : NO K
7005 23:16:30.221573 ZQ Calibration : PASS
7006 23:16:30.224881 Jitter Meter : NO K
7007 23:16:30.224960 CBT Training : PASS
7008 23:16:30.228375 Write leveling : PASS
7009 23:16:30.231706 RX DQS gating : PASS
7010 23:16:30.231787 RX DQ/DQS(RDDQC) : PASS
7011 23:16:30.235236 TX DQ/DQS : PASS
7012 23:16:30.238377 RX DATLAT : PASS
7013 23:16:30.238458 RX DQ/DQS(Engine): PASS
7014 23:16:30.241280 TX OE : NO K
7015 23:16:30.241362 All Pass.
7016 23:16:30.241426
7017 23:16:30.244827 CH 1, Rank 1
7018 23:16:30.244912 SW Impedance : PASS
7019 23:16:30.248111 DUTY Scan : NO K
7020 23:16:30.251289 ZQ Calibration : PASS
7021 23:16:30.251366 Jitter Meter : NO K
7022 23:16:30.254388 CBT Training : PASS
7023 23:16:30.257930 Write leveling : NO K
7024 23:16:30.258009 RX DQS gating : PASS
7025 23:16:30.262394 RX DQ/DQS(RDDQC) : PASS
7026 23:16:30.262468 TX DQ/DQS : PASS
7027 23:16:30.265271 RX DATLAT : PASS
7028 23:16:30.267785 RX DQ/DQS(Engine): PASS
7029 23:16:30.267857 TX OE : NO K
7030 23:16:30.271359 All Pass.
7031 23:16:30.271487
7032 23:16:30.271612 DramC Write-DBI off
7033 23:16:30.274416 PER_BANK_REFRESH: Hybrid Mode
7034 23:16:30.277924 TX_TRACKING: ON
7035 23:16:30.284570 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7036 23:16:30.287960 [FAST_K] Save calibration result to emmc
7037 23:16:30.291063 dramc_set_vcore_voltage set vcore to 725000
7038 23:16:30.294796 Read voltage for 1600, 0
7039 23:16:30.294872 Vio18 = 0
7040 23:16:30.297733 Vcore = 725000
7041 23:16:30.297808 Vdram = 0
7042 23:16:30.297870 Vddq = 0
7043 23:16:30.300977 Vmddr = 0
7044 23:16:30.304269 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7045 23:16:30.311318 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7046 23:16:30.311403 MEM_TYPE=3, freq_sel=13
7047 23:16:30.314487 sv_algorithm_assistance_LP4_3733
7048 23:16:30.320944 ============ PULL DRAM RESETB DOWN ============
7049 23:16:30.324513 ========== PULL DRAM RESETB DOWN end =========
7050 23:16:30.328160 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7051 23:16:30.331152 ===================================
7052 23:16:30.334406 LPDDR4 DRAM CONFIGURATION
7053 23:16:30.337988 ===================================
7054 23:16:30.340840 EX_ROW_EN[0] = 0x0
7055 23:16:30.340911 EX_ROW_EN[1] = 0x0
7056 23:16:30.344348 LP4Y_EN = 0x0
7057 23:16:30.344444 WORK_FSP = 0x1
7058 23:16:30.347459 WL = 0x5
7059 23:16:30.347530 RL = 0x5
7060 23:16:30.351023 BL = 0x2
7061 23:16:30.351100 RPST = 0x0
7062 23:16:30.354332 RD_PRE = 0x0
7063 23:16:30.354418 WR_PRE = 0x1
7064 23:16:30.357502 WR_PST = 0x1
7065 23:16:30.357622 DBI_WR = 0x0
7066 23:16:30.360778 DBI_RD = 0x0
7067 23:16:30.360848 OTF = 0x1
7068 23:16:30.364049 ===================================
7069 23:16:30.367423 ===================================
7070 23:16:30.370483 ANA top config
7071 23:16:30.374087 ===================================
7072 23:16:30.377454 DLL_ASYNC_EN = 0
7073 23:16:30.377550 ALL_SLAVE_EN = 0
7074 23:16:30.380361 NEW_RANK_MODE = 1
7075 23:16:30.384192 DLL_IDLE_MODE = 1
7076 23:16:30.387504 LP45_APHY_COMB_EN = 1
7077 23:16:30.390496 TX_ODT_DIS = 0
7078 23:16:30.390593 NEW_8X_MODE = 1
7079 23:16:30.393900 ===================================
7080 23:16:30.397174 ===================================
7081 23:16:30.400587 data_rate = 3200
7082 23:16:30.404094 CKR = 1
7083 23:16:30.407152 DQ_P2S_RATIO = 8
7084 23:16:30.410404 ===================================
7085 23:16:30.413834 CA_P2S_RATIO = 8
7086 23:16:30.413917 DQ_CA_OPEN = 0
7087 23:16:30.417114 DQ_SEMI_OPEN = 0
7088 23:16:30.420595 CA_SEMI_OPEN = 0
7089 23:16:30.423821 CA_FULL_RATE = 0
7090 23:16:30.427429 DQ_CKDIV4_EN = 0
7091 23:16:30.430398 CA_CKDIV4_EN = 0
7092 23:16:30.430475 CA_PREDIV_EN = 0
7093 23:16:30.433957 PH8_DLY = 12
7094 23:16:30.436809 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7095 23:16:30.440534 DQ_AAMCK_DIV = 4
7096 23:16:30.443372 CA_AAMCK_DIV = 4
7097 23:16:30.447244 CA_ADMCK_DIV = 4
7098 23:16:30.447317 DQ_TRACK_CA_EN = 0
7099 23:16:30.450419 CA_PICK = 1600
7100 23:16:30.453967 CA_MCKIO = 1600
7101 23:16:30.457226 MCKIO_SEMI = 0
7102 23:16:30.460456 PLL_FREQ = 3068
7103 23:16:30.464065 DQ_UI_PI_RATIO = 32
7104 23:16:30.466805 CA_UI_PI_RATIO = 0
7105 23:16:30.470469 ===================================
7106 23:16:30.473674 ===================================
7107 23:16:30.473751 memory_type:LPDDR4
7108 23:16:30.476966 GP_NUM : 10
7109 23:16:30.480365 SRAM_EN : 1
7110 23:16:30.480436 MD32_EN : 0
7111 23:16:30.483754 ===================================
7112 23:16:30.486587 [ANA_INIT] >>>>>>>>>>>>>>
7113 23:16:30.489955 <<<<<< [CONFIGURE PHASE]: ANA_TX
7114 23:16:30.493525 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7115 23:16:30.496580 ===================================
7116 23:16:30.500002 data_rate = 3200,PCW = 0X7600
7117 23:16:30.503307 ===================================
7118 23:16:30.506937 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7119 23:16:30.510077 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7120 23:16:30.516798 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7121 23:16:30.520075 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7122 23:16:30.523238 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7123 23:16:30.526777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7124 23:16:30.529796 [ANA_INIT] flow start
7125 23:16:30.533500 [ANA_INIT] PLL >>>>>>>>
7126 23:16:30.533605 [ANA_INIT] PLL <<<<<<<<
7127 23:16:30.536818 [ANA_INIT] MIDPI >>>>>>>>
7128 23:16:30.540034 [ANA_INIT] MIDPI <<<<<<<<
7129 23:16:30.543357 [ANA_INIT] DLL >>>>>>>>
7130 23:16:30.543431 [ANA_INIT] DLL <<<<<<<<
7131 23:16:30.546878 [ANA_INIT] flow end
7132 23:16:30.550241 ============ LP4 DIFF to SE enter ============
7133 23:16:30.553640 ============ LP4 DIFF to SE exit ============
7134 23:16:30.556802 [ANA_INIT] <<<<<<<<<<<<<
7135 23:16:30.560175 [Flow] Enable top DCM control >>>>>
7136 23:16:30.563602 [Flow] Enable top DCM control <<<<<
7137 23:16:30.567163 Enable DLL master slave shuffle
7138 23:16:30.570211 ==============================================================
7139 23:16:30.573497 Gating Mode config
7140 23:16:30.580212 ==============================================================
7141 23:16:30.580296 Config description:
7142 23:16:30.589804 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7143 23:16:30.596488 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7144 23:16:30.603874 SELPH_MODE 0: By rank 1: By Phase
7145 23:16:30.606803 ==============================================================
7146 23:16:30.609925 GAT_TRACK_EN = 1
7147 23:16:30.613493 RX_GATING_MODE = 2
7148 23:16:30.616870 RX_GATING_TRACK_MODE = 2
7149 23:16:30.620379 SELPH_MODE = 1
7150 23:16:30.623069 PICG_EARLY_EN = 1
7151 23:16:30.626656 VALID_LAT_VALUE = 1
7152 23:16:30.629530 ==============================================================
7153 23:16:30.632969 Enter into Gating configuration >>>>
7154 23:16:30.636223 Exit from Gating configuration <<<<
7155 23:16:30.639739 Enter into DVFS_PRE_config >>>>>
7156 23:16:30.652910 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7157 23:16:30.656416 Exit from DVFS_PRE_config <<<<<
7158 23:16:30.659421 Enter into PICG configuration >>>>
7159 23:16:30.659501 Exit from PICG configuration <<<<
7160 23:16:30.662642 [RX_INPUT] configuration >>>>>
7161 23:16:30.666229 [RX_INPUT] configuration <<<<<
7162 23:16:30.673092 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7163 23:16:30.676481 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7164 23:16:30.683094 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7165 23:16:30.689695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7166 23:16:30.695861 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 23:16:30.702779 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 23:16:30.706353 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7169 23:16:30.709712 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7170 23:16:30.712879 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7171 23:16:30.719159 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7172 23:16:30.722404 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7173 23:16:30.725962 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7174 23:16:30.729432 ===================================
7175 23:16:30.732542 LPDDR4 DRAM CONFIGURATION
7176 23:16:30.735958 ===================================
7177 23:16:30.739243 EX_ROW_EN[0] = 0x0
7178 23:16:30.739324 EX_ROW_EN[1] = 0x0
7179 23:16:30.742537 LP4Y_EN = 0x0
7180 23:16:30.742617 WORK_FSP = 0x1
7181 23:16:30.745993 WL = 0x5
7182 23:16:30.746074 RL = 0x5
7183 23:16:30.749084 BL = 0x2
7184 23:16:30.749164 RPST = 0x0
7185 23:16:30.752513 RD_PRE = 0x0
7186 23:16:30.752593 WR_PRE = 0x1
7187 23:16:30.755654 WR_PST = 0x1
7188 23:16:30.755733 DBI_WR = 0x0
7189 23:16:30.759164 DBI_RD = 0x0
7190 23:16:30.759244 OTF = 0x1
7191 23:16:30.762870 ===================================
7192 23:16:30.769045 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7193 23:16:30.772488 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7194 23:16:30.775763 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7195 23:16:30.779000 ===================================
7196 23:16:30.782244 LPDDR4 DRAM CONFIGURATION
7197 23:16:30.785680 ===================================
7198 23:16:30.789064 EX_ROW_EN[0] = 0x10
7199 23:16:30.789144 EX_ROW_EN[1] = 0x0
7200 23:16:30.792276 LP4Y_EN = 0x0
7201 23:16:30.792370 WORK_FSP = 0x1
7202 23:16:30.795818 WL = 0x5
7203 23:16:30.795899 RL = 0x5
7204 23:16:30.798987 BL = 0x2
7205 23:16:30.799067 RPST = 0x0
7206 23:16:30.802348 RD_PRE = 0x0
7207 23:16:30.802428 WR_PRE = 0x1
7208 23:16:30.805242 WR_PST = 0x1
7209 23:16:30.805331 DBI_WR = 0x0
7210 23:16:30.808600 DBI_RD = 0x0
7211 23:16:30.808680 OTF = 0x1
7212 23:16:30.812047 ===================================
7213 23:16:30.818931 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7214 23:16:30.819011 ==
7215 23:16:30.822133 Dram Type= 6, Freq= 0, CH_0, rank 0
7216 23:16:30.828633 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7217 23:16:30.828714 ==
7218 23:16:30.828778 [Duty_Offset_Calibration]
7219 23:16:30.832003 B0:2 B1:1 CA:1
7220 23:16:30.832083
7221 23:16:30.835410 [DutyScan_Calibration_Flow] k_type=0
7222 23:16:30.844799
7223 23:16:30.844879 ==CLK 0==
7224 23:16:30.847582 Final CLK duty delay cell = 0
7225 23:16:30.851411 [0] MAX Duty = 5156%(X100), DQS PI = 22
7226 23:16:30.854853 [0] MIN Duty = 4907%(X100), DQS PI = 0
7227 23:16:30.854934 [0] AVG Duty = 5031%(X100)
7228 23:16:30.857486
7229 23:16:30.860861 CH0 CLK Duty spec in!! Max-Min= 249%
7230 23:16:30.864650 [DutyScan_Calibration_Flow] ====Done====
7231 23:16:30.864731
7232 23:16:30.867575 [DutyScan_Calibration_Flow] k_type=1
7233 23:16:30.883495
7234 23:16:30.883581 ==DQS 0 ==
7235 23:16:30.887099 Final DQS duty delay cell = -4
7236 23:16:30.890391 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7237 23:16:30.893755 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7238 23:16:30.896770 [-4] AVG Duty = 4906%(X100)
7239 23:16:30.896850
7240 23:16:30.896913 ==DQS 1 ==
7241 23:16:30.900091 Final DQS duty delay cell = 0
7242 23:16:30.903813 [0] MAX Duty = 5187%(X100), DQS PI = 20
7243 23:16:30.906685 [0] MIN Duty = 5031%(X100), DQS PI = 52
7244 23:16:30.910053 [0] AVG Duty = 5109%(X100)
7245 23:16:30.910125
7246 23:16:30.913450 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7247 23:16:30.913541
7248 23:16:30.916834 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7249 23:16:30.920469 [DutyScan_Calibration_Flow] ====Done====
7250 23:16:30.920541
7251 23:16:30.923354 [DutyScan_Calibration_Flow] k_type=3
7252 23:16:30.940161
7253 23:16:30.940235 ==DQM 0 ==
7254 23:16:30.943802 Final DQM duty delay cell = 0
7255 23:16:30.946688 [0] MAX Duty = 5187%(X100), DQS PI = 32
7256 23:16:30.950229 [0] MIN Duty = 4907%(X100), DQS PI = 54
7257 23:16:30.953344 [0] AVG Duty = 5047%(X100)
7258 23:16:30.953415
7259 23:16:30.953478 ==DQM 1 ==
7260 23:16:30.957137 Final DQM duty delay cell = -4
7261 23:16:30.960276 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7262 23:16:30.963708 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7263 23:16:30.967091 [-4] AVG Duty = 4891%(X100)
7264 23:16:30.967161
7265 23:16:30.970017 CH0 DQM 0 Duty spec in!! Max-Min= 280%
7266 23:16:30.970100
7267 23:16:30.973311 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7268 23:16:30.976939 [DutyScan_Calibration_Flow] ====Done====
7269 23:16:30.977013
7270 23:16:30.979831 [DutyScan_Calibration_Flow] k_type=2
7271 23:16:30.997981
7272 23:16:30.998062 ==DQ 0 ==
7273 23:16:31.001467 Final DQ duty delay cell = 0
7274 23:16:31.004587 [0] MAX Duty = 5062%(X100), DQS PI = 26
7275 23:16:31.008153 [0] MIN Duty = 4907%(X100), DQS PI = 0
7276 23:16:31.008227 [0] AVG Duty = 4984%(X100)
7277 23:16:31.010799
7278 23:16:31.010869 ==DQ 1 ==
7279 23:16:31.014061 Final DQ duty delay cell = 0
7280 23:16:31.017716 [0] MAX Duty = 5156%(X100), DQS PI = 22
7281 23:16:31.021182 [0] MIN Duty = 4907%(X100), DQS PI = 34
7282 23:16:31.021254 [0] AVG Duty = 5031%(X100)
7283 23:16:31.021318
7284 23:16:31.027653 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7285 23:16:31.027727
7286 23:16:31.030723 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7287 23:16:31.033994 [DutyScan_Calibration_Flow] ====Done====
7288 23:16:31.034090 ==
7289 23:16:31.037285 Dram Type= 6, Freq= 0, CH_1, rank 0
7290 23:16:31.040783 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 23:16:31.040855 ==
7292 23:16:31.044049 [Duty_Offset_Calibration]
7293 23:16:31.044122 B0:1 B1:0 CA:0
7294 23:16:31.044182
7295 23:16:31.047867 [DutyScan_Calibration_Flow] k_type=0
7296 23:16:31.057246
7297 23:16:31.057319 ==CLK 0==
7298 23:16:31.060403 Final CLK duty delay cell = -4
7299 23:16:31.063683 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7300 23:16:31.067089 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7301 23:16:31.070558 [-4] AVG Duty = 4906%(X100)
7302 23:16:31.070653
7303 23:16:31.073850 CH1 CLK Duty spec in!! Max-Min= 125%
7304 23:16:31.077393 [DutyScan_Calibration_Flow] ====Done====
7305 23:16:31.077464
7306 23:16:31.080118 [DutyScan_Calibration_Flow] k_type=1
7307 23:16:31.097330
7308 23:16:31.097407 ==DQS 0 ==
7309 23:16:31.100286 Final DQS duty delay cell = 0
7310 23:16:31.103819 [0] MAX Duty = 5094%(X100), DQS PI = 18
7311 23:16:31.107132 [0] MIN Duty = 4844%(X100), DQS PI = 48
7312 23:16:31.110399 [0] AVG Duty = 4969%(X100)
7313 23:16:31.110472
7314 23:16:31.110532 ==DQS 1 ==
7315 23:16:31.113893 Final DQS duty delay cell = 0
7316 23:16:31.117027 [0] MAX Duty = 5249%(X100), DQS PI = 16
7317 23:16:31.120432 [0] MIN Duty = 4969%(X100), DQS PI = 6
7318 23:16:31.123862 [0] AVG Duty = 5109%(X100)
7319 23:16:31.123933
7320 23:16:31.127474 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7321 23:16:31.127547
7322 23:16:31.130848 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7323 23:16:31.133782 [DutyScan_Calibration_Flow] ====Done====
7324 23:16:31.133852
7325 23:16:31.136766 [DutyScan_Calibration_Flow] k_type=3
7326 23:16:31.154132
7327 23:16:31.154205 ==DQM 0 ==
7328 23:16:31.157531 Final DQM duty delay cell = 0
7329 23:16:31.161142 [0] MAX Duty = 5187%(X100), DQS PI = 10
7330 23:16:31.164216 [0] MIN Duty = 4969%(X100), DQS PI = 46
7331 23:16:31.167159 [0] AVG Duty = 5078%(X100)
7332 23:16:31.167229
7333 23:16:31.167287 ==DQM 1 ==
7334 23:16:31.170474 Final DQM duty delay cell = 0
7335 23:16:31.174230 [0] MAX Duty = 5062%(X100), DQS PI = 14
7336 23:16:31.177724 [0] MIN Duty = 4907%(X100), DQS PI = 32
7337 23:16:31.180958 [0] AVG Duty = 4984%(X100)
7338 23:16:31.181032
7339 23:16:31.183770 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7340 23:16:31.183840
7341 23:16:31.187583 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7342 23:16:31.190901 [DutyScan_Calibration_Flow] ====Done====
7343 23:16:31.190975
7344 23:16:31.194265 [DutyScan_Calibration_Flow] k_type=2
7345 23:16:31.209971
7346 23:16:31.210048 ==DQ 0 ==
7347 23:16:31.213381 Final DQ duty delay cell = -4
7348 23:16:31.216784 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7349 23:16:31.220423 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7350 23:16:31.223438 [-4] AVG Duty = 4968%(X100)
7351 23:16:31.223510
7352 23:16:31.223574 ==DQ 1 ==
7353 23:16:31.226960 Final DQ duty delay cell = 0
7354 23:16:31.230270 [0] MAX Duty = 5156%(X100), DQS PI = 18
7355 23:16:31.233154 [0] MIN Duty = 4938%(X100), DQS PI = 8
7356 23:16:31.236500 [0] AVG Duty = 5047%(X100)
7357 23:16:31.236574
7358 23:16:31.239831 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7359 23:16:31.239900
7360 23:16:31.243222 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7361 23:16:31.246528 [DutyScan_Calibration_Flow] ====Done====
7362 23:16:31.249966 nWR fixed to 30
7363 23:16:31.253372 [ModeRegInit_LP4] CH0 RK0
7364 23:16:31.253445 [ModeRegInit_LP4] CH0 RK1
7365 23:16:31.256490 [ModeRegInit_LP4] CH1 RK0
7366 23:16:31.259897 [ModeRegInit_LP4] CH1 RK1
7367 23:16:31.259967 match AC timing 5
7368 23:16:31.266960 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7369 23:16:31.270202 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7370 23:16:31.273002 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7371 23:16:31.280066 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7372 23:16:31.282927 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7373 23:16:31.283026 [MiockJmeterHQA]
7374 23:16:31.283118
7375 23:16:31.286152 [DramcMiockJmeter] u1RxGatingPI = 0
7376 23:16:31.289613 0 : 4252, 4027
7377 23:16:31.289703 4 : 4255, 4029
7378 23:16:31.293064 8 : 4254, 4029
7379 23:16:31.293166 12 : 4255, 4029
7380 23:16:31.296332 16 : 4257, 4029
7381 23:16:31.296404 20 : 4252, 4027
7382 23:16:31.296464 24 : 4253, 4026
7383 23:16:31.299395 28 : 4363, 4137
7384 23:16:31.299470 32 : 4362, 4137
7385 23:16:31.302869 36 : 4363, 4137
7386 23:16:31.302967 40 : 4252, 4027
7387 23:16:31.305994 44 : 4255, 4029
7388 23:16:31.306066 48 : 4252, 4027
7389 23:16:31.306126 52 : 4366, 4140
7390 23:16:31.309799 56 : 4360, 4138
7391 23:16:31.309897 60 : 4360, 4138
7392 23:16:31.312879 64 : 4252, 4026
7393 23:16:31.313012 68 : 4250, 4027
7394 23:16:31.316241 72 : 4250, 4027
7395 23:16:31.316322 76 : 4250, 4026
7396 23:16:31.319283 80 : 4361, 4137
7397 23:16:31.319364 84 : 4250, 4025
7398 23:16:31.319428 88 : 4250, 62
7399 23:16:31.323026 92 : 4249, 0
7400 23:16:31.323107 96 : 4365, 0
7401 23:16:31.326356 100 : 4253, 0
7402 23:16:31.326438 104 : 4361, 0
7403 23:16:31.326503 108 : 4252, 0
7404 23:16:31.329373 112 : 4252, 0
7405 23:16:31.329453 116 : 4361, 0
7406 23:16:31.329517 120 : 4250, 0
7407 23:16:31.332990 124 : 4249, 0
7408 23:16:31.333071 128 : 4250, 0
7409 23:16:31.336372 132 : 4255, 0
7410 23:16:31.336452 136 : 4360, 0
7411 23:16:31.336516 140 : 4250, 0
7412 23:16:31.339255 144 : 4361, 0
7413 23:16:31.339336 148 : 4250, 0
7414 23:16:31.342780 152 : 4249, 0
7415 23:16:31.342861 156 : 4361, 0
7416 23:16:31.342925 160 : 4250, 0
7417 23:16:31.346135 164 : 4250, 0
7418 23:16:31.346216 168 : 4250, 0
7419 23:16:31.349238 172 : 4253, 0
7420 23:16:31.349319 176 : 4250, 0
7421 23:16:31.349383 180 : 4250, 0
7422 23:16:31.352593 184 : 4255, 0
7423 23:16:31.352673 188 : 4360, 0
7424 23:16:31.352738 192 : 4250, 0
7425 23:16:31.356290 196 : 4361, 0
7426 23:16:31.356370 200 : 4250, 0
7427 23:16:31.359354 204 : 4252, 1398
7428 23:16:31.359435 208 : 4249, 4011
7429 23:16:31.362838 212 : 4252, 4029
7430 23:16:31.362973 216 : 4250, 4026
7431 23:16:31.366204 220 : 4360, 4138
7432 23:16:31.366285 224 : 4360, 4138
7433 23:16:31.369022 228 : 4250, 4026
7434 23:16:31.369103 232 : 4361, 4137
7435 23:16:31.369167 236 : 4250, 4027
7436 23:16:31.372450 240 : 4253, 4029
7437 23:16:31.372531 244 : 4250, 4026
7438 23:16:31.375866 248 : 4363, 4140
7439 23:16:31.375947 252 : 4250, 4027
7440 23:16:31.379225 256 : 4250, 4027
7441 23:16:31.379306 260 : 4360, 4137
7442 23:16:31.382434 264 : 4250, 4027
7443 23:16:31.382515 268 : 4250, 4027
7444 23:16:31.385912 272 : 4360, 4138
7445 23:16:31.385993 276 : 4361, 4138
7446 23:16:31.389301 280 : 4250, 4027
7447 23:16:31.389381 284 : 4250, 4026
7448 23:16:31.392632 288 : 4253, 4029
7449 23:16:31.392713 292 : 4250, 4027
7450 23:16:31.395972 296 : 4250, 4026
7451 23:16:31.396053 300 : 4363, 4140
7452 23:16:31.396118 304 : 4253, 4029
7453 23:16:31.399047 308 : 4250, 3943
7454 23:16:31.399128 312 : 4363, 1794
7455 23:16:31.399193
7456 23:16:31.402184 MIOCK jitter meter ch=0
7457 23:16:31.402263
7458 23:16:31.405583 1T = (312-88) = 224 dly cells
7459 23:16:31.412464 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7460 23:16:31.412547 ==
7461 23:16:31.415539 Dram Type= 6, Freq= 0, CH_0, rank 0
7462 23:16:31.418740 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7463 23:16:31.418826 ==
7464 23:16:31.425244 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7465 23:16:31.428612 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7466 23:16:31.431934 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7467 23:16:31.438634 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7468 23:16:31.447831 [CA 0] Center 42 (12~73) winsize 62
7469 23:16:31.450851 [CA 1] Center 42 (12~73) winsize 62
7470 23:16:31.454668 [CA 2] Center 38 (8~68) winsize 61
7471 23:16:31.457904 [CA 3] Center 37 (7~67) winsize 61
7472 23:16:31.460815 [CA 4] Center 36 (6~66) winsize 61
7473 23:16:31.464200 [CA 5] Center 35 (6~64) winsize 59
7474 23:16:31.464280
7475 23:16:31.467432 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7476 23:16:31.467512
7477 23:16:31.470667 [CATrainingPosCal] consider 1 rank data
7478 23:16:31.474467 u2DelayCellTimex100 = 290/100 ps
7479 23:16:31.480727 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7480 23:16:31.484053 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7481 23:16:31.487337 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7482 23:16:31.490684 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7483 23:16:31.494328 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7484 23:16:31.497543 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7485 23:16:31.497630
7486 23:16:31.500538 CA PerBit enable=1, Macro0, CA PI delay=35
7487 23:16:31.500618
7488 23:16:31.503762 [CBTSetCACLKResult] CA Dly = 35
7489 23:16:31.507014 CS Dly: 9 (0~40)
7490 23:16:31.510493 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7491 23:16:31.514041 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7492 23:16:31.514122 ==
7493 23:16:31.516989 Dram Type= 6, Freq= 0, CH_0, rank 1
7494 23:16:31.524107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7495 23:16:31.524190 ==
7496 23:16:31.527118 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7497 23:16:31.530278 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7498 23:16:31.536742 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7499 23:16:31.543788 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7500 23:16:31.550840 [CA 0] Center 42 (12~73) winsize 62
7501 23:16:31.554576 [CA 1] Center 42 (12~73) winsize 62
7502 23:16:31.557782 [CA 2] Center 38 (8~68) winsize 61
7503 23:16:31.560934 [CA 3] Center 37 (8~67) winsize 60
7504 23:16:31.564721 [CA 4] Center 36 (6~66) winsize 61
7505 23:16:31.567657 [CA 5] Center 35 (5~65) winsize 61
7506 23:16:31.567738
7507 23:16:31.570736 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7508 23:16:31.570818
7509 23:16:31.574163 [CATrainingPosCal] consider 2 rank data
7510 23:16:31.577356 u2DelayCellTimex100 = 290/100 ps
7511 23:16:31.580784 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7512 23:16:31.587445 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7513 23:16:31.590809 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7514 23:16:31.594299 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7515 23:16:31.597653 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7516 23:16:31.600839 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7517 23:16:31.600919
7518 23:16:31.603909 CA PerBit enable=1, Macro0, CA PI delay=35
7519 23:16:31.603990
7520 23:16:31.607322 [CBTSetCACLKResult] CA Dly = 35
7521 23:16:31.610733 CS Dly: 10 (0~42)
7522 23:16:31.613949 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7523 23:16:31.617057 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7524 23:16:31.617138
7525 23:16:31.620647 ----->DramcWriteLeveling(PI) begin...
7526 23:16:31.620729 ==
7527 23:16:31.624194 Dram Type= 6, Freq= 0, CH_0, rank 0
7528 23:16:31.630879 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7529 23:16:31.630961 ==
7530 23:16:31.633804 Write leveling (Byte 0): 35 => 35
7531 23:16:31.633885 Write leveling (Byte 1): 28 => 28
7532 23:16:31.636981 DramcWriteLeveling(PI) end<-----
7533 23:16:31.637061
7534 23:16:31.640760 ==
7535 23:16:31.643885 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 23:16:31.646935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 23:16:31.647016 ==
7538 23:16:31.650751 [Gating] SW mode calibration
7539 23:16:31.656777 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7540 23:16:31.660190 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7541 23:16:31.667258 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7542 23:16:31.670016 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7543 23:16:31.673626 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7544 23:16:31.680525 1 4 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (1 1)
7545 23:16:31.683365 1 4 16 | B1->B0 | 2323 3736 | 0 1 | (0 0) (1 1)
7546 23:16:31.687104 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7547 23:16:31.693580 1 4 24 | B1->B0 | 3434 3939 | 1 0 | (1 1) (0 0)
7548 23:16:31.696924 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7549 23:16:31.700249 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7550 23:16:31.707057 1 5 4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (1 1)
7551 23:16:31.709962 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
7552 23:16:31.713838 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
7553 23:16:31.719907 1 5 16 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
7554 23:16:31.723212 1 5 20 | B1->B0 | 2626 2423 | 0 1 | (0 0) (0 0)
7555 23:16:31.726882 1 5 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7556 23:16:31.733934 1 5 28 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
7557 23:16:31.736566 1 6 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
7558 23:16:31.739993 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7559 23:16:31.743445 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
7560 23:16:31.750109 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7561 23:16:31.753324 1 6 16 | B1->B0 | 2727 4645 | 0 1 | (0 0) (0 0)
7562 23:16:31.756541 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7563 23:16:31.763072 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7564 23:16:31.766338 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7565 23:16:31.769657 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7566 23:16:31.776728 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7567 23:16:31.780055 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7568 23:16:31.783183 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7569 23:16:31.790233 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7570 23:16:31.792853 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7571 23:16:31.796182 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7572 23:16:31.802807 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7573 23:16:31.806055 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7574 23:16:31.809429 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7575 23:16:31.816461 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7576 23:16:31.819786 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 23:16:31.822768 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 23:16:31.829696 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 23:16:31.833065 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 23:16:31.836029 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 23:16:31.843279 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 23:16:31.846123 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 23:16:31.849526 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7584 23:16:31.856344 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7585 23:16:31.859391 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7586 23:16:31.863022 Total UI for P1: 0, mck2ui 16
7587 23:16:31.866336 best dqsien dly found for B0: ( 1, 9, 10)
7588 23:16:31.869264 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7589 23:16:31.875812 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 23:16:31.875893 Total UI for P1: 0, mck2ui 16
7591 23:16:31.882406 best dqsien dly found for B1: ( 1, 9, 18)
7592 23:16:31.885701 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7593 23:16:31.889157 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7594 23:16:31.889238
7595 23:16:31.892293 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7596 23:16:31.896521 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7597 23:16:31.899097 [Gating] SW calibration Done
7598 23:16:31.899178 ==
7599 23:16:31.902350 Dram Type= 6, Freq= 0, CH_0, rank 0
7600 23:16:31.906173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7601 23:16:31.906256 ==
7602 23:16:31.909479 RX Vref Scan: 0
7603 23:16:31.909562
7604 23:16:31.909652 RX Vref 0 -> 0, step: 1
7605 23:16:31.909712
7606 23:16:31.912494 RX Delay 0 -> 252, step: 8
7607 23:16:31.915809 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7608 23:16:31.922362 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7609 23:16:31.925585 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7610 23:16:31.929126 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
7611 23:16:31.932281 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7612 23:16:31.935670 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7613 23:16:31.939145 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7614 23:16:31.945468 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7615 23:16:31.948956 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7616 23:16:31.952528 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7617 23:16:31.955397 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7618 23:16:31.958953 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7619 23:16:31.965532 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7620 23:16:31.968772 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7621 23:16:31.972083 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7622 23:16:31.975247 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7623 23:16:31.975328 ==
7624 23:16:31.978927 Dram Type= 6, Freq= 0, CH_0, rank 0
7625 23:16:31.985344 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7626 23:16:31.985427 ==
7627 23:16:31.985491 DQS Delay:
7628 23:16:31.988959 DQS0 = 0, DQS1 = 0
7629 23:16:31.989039 DQM Delay:
7630 23:16:31.992054 DQM0 = 136, DQM1 = 131
7631 23:16:31.992135 DQ Delay:
7632 23:16:31.995480 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135
7633 23:16:31.998456 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7634 23:16:32.001838 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7635 23:16:32.005094 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7636 23:16:32.005175
7637 23:16:32.005238
7638 23:16:32.005297 ==
7639 23:16:32.008812 Dram Type= 6, Freq= 0, CH_0, rank 0
7640 23:16:32.015525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7641 23:16:32.015607 ==
7642 23:16:32.015671
7643 23:16:32.015729
7644 23:16:32.015786 TX Vref Scan disable
7645 23:16:32.018429 == TX Byte 0 ==
7646 23:16:32.021936 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7647 23:16:32.025612 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7648 23:16:32.028631 == TX Byte 1 ==
7649 23:16:32.031966 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7650 23:16:32.035400 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7651 23:16:32.038942 ==
7652 23:16:32.042022 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 23:16:32.045022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 23:16:32.045103 ==
7655 23:16:32.057121
7656 23:16:32.060173 TX Vref early break, caculate TX vref
7657 23:16:32.064164 TX Vref=16, minBit 7, minWin=22, winSum=376
7658 23:16:32.066933 TX Vref=18, minBit 7, minWin=22, winSum=382
7659 23:16:32.070584 TX Vref=20, minBit 0, minWin=24, winSum=396
7660 23:16:32.073982 TX Vref=22, minBit 0, minWin=24, winSum=409
7661 23:16:32.076717 TX Vref=24, minBit 0, minWin=25, winSum=416
7662 23:16:32.083403 TX Vref=26, minBit 7, minWin=25, winSum=426
7663 23:16:32.086638 TX Vref=28, minBit 2, minWin=25, winSum=424
7664 23:16:32.090327 TX Vref=30, minBit 1, minWin=24, winSum=413
7665 23:16:32.093834 TX Vref=32, minBit 0, minWin=24, winSum=403
7666 23:16:32.100441 [TxChooseVref] Worse bit 7, Min win 25, Win sum 426, Final Vref 26
7667 23:16:32.100522
7668 23:16:32.103737 Final TX Range 0 Vref 26
7669 23:16:32.103818
7670 23:16:32.103882 ==
7671 23:16:32.107109 Dram Type= 6, Freq= 0, CH_0, rank 0
7672 23:16:32.109953 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7673 23:16:32.110036 ==
7674 23:16:32.110099
7675 23:16:32.110159
7676 23:16:32.113212 TX Vref Scan disable
7677 23:16:32.117128 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7678 23:16:32.119946 == TX Byte 0 ==
7679 23:16:32.123419 u2DelayCellOfst[0]=10 cells (3 PI)
7680 23:16:32.126733 u2DelayCellOfst[1]=13 cells (4 PI)
7681 23:16:32.130223 u2DelayCellOfst[2]=10 cells (3 PI)
7682 23:16:32.133715 u2DelayCellOfst[3]=6 cells (2 PI)
7683 23:16:32.136502 u2DelayCellOfst[4]=6 cells (2 PI)
7684 23:16:32.136582 u2DelayCellOfst[5]=0 cells (0 PI)
7685 23:16:32.139835 u2DelayCellOfst[6]=16 cells (5 PI)
7686 23:16:32.142992 u2DelayCellOfst[7]=13 cells (4 PI)
7687 23:16:32.150104 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7688 23:16:32.153011 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7689 23:16:32.153092 == TX Byte 1 ==
7690 23:16:32.156645 u2DelayCellOfst[8]=0 cells (0 PI)
7691 23:16:32.159707 u2DelayCellOfst[9]=0 cells (0 PI)
7692 23:16:32.162964 u2DelayCellOfst[10]=10 cells (3 PI)
7693 23:16:32.166235 u2DelayCellOfst[11]=6 cells (2 PI)
7694 23:16:32.169701 u2DelayCellOfst[12]=13 cells (4 PI)
7695 23:16:32.172939 u2DelayCellOfst[13]=10 cells (3 PI)
7696 23:16:32.176653 u2DelayCellOfst[14]=16 cells (5 PI)
7697 23:16:32.179406 u2DelayCellOfst[15]=13 cells (4 PI)
7698 23:16:32.182861 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7699 23:16:32.189471 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7700 23:16:32.189553 DramC Write-DBI on
7701 23:16:32.189628 ==
7702 23:16:32.192905 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 23:16:32.196052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 23:16:32.196133 ==
7705 23:16:32.199249
7706 23:16:32.199330
7707 23:16:32.199393 TX Vref Scan disable
7708 23:16:32.202929 == TX Byte 0 ==
7709 23:16:32.206324 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7710 23:16:32.209489 == TX Byte 1 ==
7711 23:16:32.213175 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7712 23:16:32.213257 DramC Write-DBI off
7713 23:16:32.216118
7714 23:16:32.216198 [DATLAT]
7715 23:16:32.216262 Freq=1600, CH0 RK0
7716 23:16:32.216321
7717 23:16:32.219444 DATLAT Default: 0xf
7718 23:16:32.219527 0, 0xFFFF, sum = 0
7719 23:16:32.222565 1, 0xFFFF, sum = 0
7720 23:16:32.222647 2, 0xFFFF, sum = 0
7721 23:16:32.225857 3, 0xFFFF, sum = 0
7722 23:16:32.229187 4, 0xFFFF, sum = 0
7723 23:16:32.229269 5, 0xFFFF, sum = 0
7724 23:16:32.232643 6, 0xFFFF, sum = 0
7725 23:16:32.232725 7, 0xFFFF, sum = 0
7726 23:16:32.235706 8, 0xFFFF, sum = 0
7727 23:16:32.235788 9, 0xFFFF, sum = 0
7728 23:16:32.239478 10, 0xFFFF, sum = 0
7729 23:16:32.239559 11, 0xFFFF, sum = 0
7730 23:16:32.242335 12, 0xFFFF, sum = 0
7731 23:16:32.242417 13, 0xFFFF, sum = 0
7732 23:16:32.245762 14, 0x0, sum = 1
7733 23:16:32.245844 15, 0x0, sum = 2
7734 23:16:32.249300 16, 0x0, sum = 3
7735 23:16:32.249381 17, 0x0, sum = 4
7736 23:16:32.253054 best_step = 15
7737 23:16:32.253134
7738 23:16:32.253199 ==
7739 23:16:32.255991 Dram Type= 6, Freq= 0, CH_0, rank 0
7740 23:16:32.259723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7741 23:16:32.259809 ==
7742 23:16:32.259874 RX Vref Scan: 1
7743 23:16:32.259933
7744 23:16:32.262851 Set Vref Range= 24 -> 127
7745 23:16:32.262932
7746 23:16:32.265770 RX Vref 24 -> 127, step: 1
7747 23:16:32.265850
7748 23:16:32.269201 RX Delay 27 -> 252, step: 4
7749 23:16:32.269281
7750 23:16:32.272607 Set Vref, RX VrefLevel [Byte0]: 24
7751 23:16:32.275949 [Byte1]: 24
7752 23:16:32.276030
7753 23:16:32.278935 Set Vref, RX VrefLevel [Byte0]: 25
7754 23:16:32.282736 [Byte1]: 25
7755 23:16:32.282816
7756 23:16:32.285859 Set Vref, RX VrefLevel [Byte0]: 26
7757 23:16:32.289085 [Byte1]: 26
7758 23:16:32.293091
7759 23:16:32.293172 Set Vref, RX VrefLevel [Byte0]: 27
7760 23:16:32.296082 [Byte1]: 27
7761 23:16:32.300040
7762 23:16:32.300121 Set Vref, RX VrefLevel [Byte0]: 28
7763 23:16:32.303849 [Byte1]: 28
7764 23:16:32.308070
7765 23:16:32.308165 Set Vref, RX VrefLevel [Byte0]: 29
7766 23:16:32.311104 [Byte1]: 29
7767 23:16:32.315302
7768 23:16:32.315382 Set Vref, RX VrefLevel [Byte0]: 30
7769 23:16:32.318726 [Byte1]: 30
7770 23:16:32.322861
7771 23:16:32.322942 Set Vref, RX VrefLevel [Byte0]: 31
7772 23:16:32.326118 [Byte1]: 31
7773 23:16:32.330524
7774 23:16:32.330604 Set Vref, RX VrefLevel [Byte0]: 32
7775 23:16:32.333905 [Byte1]: 32
7776 23:16:32.338132
7777 23:16:32.338212 Set Vref, RX VrefLevel [Byte0]: 33
7778 23:16:32.341198 [Byte1]: 33
7779 23:16:32.345535
7780 23:16:32.345622 Set Vref, RX VrefLevel [Byte0]: 34
7781 23:16:32.348837 [Byte1]: 34
7782 23:16:32.353096
7783 23:16:32.353176 Set Vref, RX VrefLevel [Byte0]: 35
7784 23:16:32.356273 [Byte1]: 35
7785 23:16:32.360784
7786 23:16:32.360865 Set Vref, RX VrefLevel [Byte0]: 36
7787 23:16:32.364010 [Byte1]: 36
7788 23:16:32.368646
7789 23:16:32.368726 Set Vref, RX VrefLevel [Byte0]: 37
7790 23:16:32.371263 [Byte1]: 37
7791 23:16:32.375686
7792 23:16:32.375766 Set Vref, RX VrefLevel [Byte0]: 38
7793 23:16:32.379038 [Byte1]: 38
7794 23:16:32.383020
7795 23:16:32.383101 Set Vref, RX VrefLevel [Byte0]: 39
7796 23:16:32.386638 [Byte1]: 39
7797 23:16:32.390689
7798 23:16:32.390769 Set Vref, RX VrefLevel [Byte0]: 40
7799 23:16:32.393735 [Byte1]: 40
7800 23:16:32.398402
7801 23:16:32.398483 Set Vref, RX VrefLevel [Byte0]: 41
7802 23:16:32.401485 [Byte1]: 41
7803 23:16:32.405841
7804 23:16:32.405921 Set Vref, RX VrefLevel [Byte0]: 42
7805 23:16:32.409319 [Byte1]: 42
7806 23:16:32.413700
7807 23:16:32.413783 Set Vref, RX VrefLevel [Byte0]: 43
7808 23:16:32.416545 [Byte1]: 43
7809 23:16:32.420610
7810 23:16:32.420691 Set Vref, RX VrefLevel [Byte0]: 44
7811 23:16:32.424217 [Byte1]: 44
7812 23:16:32.428700
7813 23:16:32.428785 Set Vref, RX VrefLevel [Byte0]: 45
7814 23:16:32.431838 [Byte1]: 45
7815 23:16:32.435657
7816 23:16:32.435737 Set Vref, RX VrefLevel [Byte0]: 46
7817 23:16:32.439372 [Byte1]: 46
7818 23:16:32.443447
7819 23:16:32.443527 Set Vref, RX VrefLevel [Byte0]: 47
7820 23:16:32.446598 [Byte1]: 47
7821 23:16:32.451427
7822 23:16:32.451508 Set Vref, RX VrefLevel [Byte0]: 48
7823 23:16:32.454586 [Byte1]: 48
7824 23:16:32.458582
7825 23:16:32.458663 Set Vref, RX VrefLevel [Byte0]: 49
7826 23:16:32.461480 [Byte1]: 49
7827 23:16:32.465816
7828 23:16:32.465896 Set Vref, RX VrefLevel [Byte0]: 50
7829 23:16:32.469261 [Byte1]: 50
7830 23:16:32.473416
7831 23:16:32.473495 Set Vref, RX VrefLevel [Byte0]: 51
7832 23:16:32.476666 [Byte1]: 51
7833 23:16:32.480849
7834 23:16:32.480930 Set Vref, RX VrefLevel [Byte0]: 52
7835 23:16:32.484280 [Byte1]: 52
7836 23:16:32.488998
7837 23:16:32.489078 Set Vref, RX VrefLevel [Byte0]: 53
7838 23:16:32.492166 [Byte1]: 53
7839 23:16:32.495980
7840 23:16:32.496060 Set Vref, RX VrefLevel [Byte0]: 54
7841 23:16:32.499611 [Byte1]: 54
7842 23:16:32.503645
7843 23:16:32.503730 Set Vref, RX VrefLevel [Byte0]: 55
7844 23:16:32.508017 [Byte1]: 55
7845 23:16:32.511047
7846 23:16:32.511128 Set Vref, RX VrefLevel [Byte0]: 56
7847 23:16:32.514472 [Byte1]: 56
7848 23:16:32.518961
7849 23:16:32.519042 Set Vref, RX VrefLevel [Byte0]: 57
7850 23:16:32.522124 [Byte1]: 57
7851 23:16:32.526513
7852 23:16:32.526594 Set Vref, RX VrefLevel [Byte0]: 58
7853 23:16:32.529349 [Byte1]: 58
7854 23:16:32.534143
7855 23:16:32.534238 Set Vref, RX VrefLevel [Byte0]: 59
7856 23:16:32.537509 [Byte1]: 59
7857 23:16:32.541807
7858 23:16:32.541887 Set Vref, RX VrefLevel [Byte0]: 60
7859 23:16:32.544878 [Byte1]: 60
7860 23:16:32.548890
7861 23:16:32.548971 Set Vref, RX VrefLevel [Byte0]: 61
7862 23:16:32.552316 [Byte1]: 61
7863 23:16:32.556342
7864 23:16:32.556423 Set Vref, RX VrefLevel [Byte0]: 62
7865 23:16:32.559827 [Byte1]: 62
7866 23:16:32.563789
7867 23:16:32.563869 Set Vref, RX VrefLevel [Byte0]: 63
7868 23:16:32.567290 [Byte1]: 63
7869 23:16:32.571952
7870 23:16:32.572032 Set Vref, RX VrefLevel [Byte0]: 64
7871 23:16:32.574866 [Byte1]: 64
7872 23:16:32.579253
7873 23:16:32.579334 Set Vref, RX VrefLevel [Byte0]: 65
7874 23:16:32.582735 [Byte1]: 65
7875 23:16:32.586618
7876 23:16:32.586705 Set Vref, RX VrefLevel [Byte0]: 66
7877 23:16:32.590169 [Byte1]: 66
7878 23:16:32.594106
7879 23:16:32.594186 Set Vref, RX VrefLevel [Byte0]: 67
7880 23:16:32.597621 [Byte1]: 67
7881 23:16:32.601877
7882 23:16:32.601958 Set Vref, RX VrefLevel [Byte0]: 68
7883 23:16:32.604889 [Byte1]: 68
7884 23:16:32.608953
7885 23:16:32.609033 Set Vref, RX VrefLevel [Byte0]: 69
7886 23:16:32.612337 [Byte1]: 69
7887 23:16:32.616763
7888 23:16:32.616843 Set Vref, RX VrefLevel [Byte0]: 70
7889 23:16:32.619718 [Byte1]: 70
7890 23:16:32.624019
7891 23:16:32.624100 Set Vref, RX VrefLevel [Byte0]: 71
7892 23:16:32.627462 [Byte1]: 71
7893 23:16:32.631728
7894 23:16:32.631808 Set Vref, RX VrefLevel [Byte0]: 72
7895 23:16:32.635053 [Byte1]: 72
7896 23:16:32.639204
7897 23:16:32.639284 Final RX Vref Byte 0 = 58 to rank0
7898 23:16:32.642585 Final RX Vref Byte 1 = 63 to rank0
7899 23:16:32.646114 Final RX Vref Byte 0 = 58 to rank1
7900 23:16:32.649313 Final RX Vref Byte 1 = 63 to rank1==
7901 23:16:32.652498 Dram Type= 6, Freq= 0, CH_0, rank 0
7902 23:16:32.659090 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7903 23:16:32.659171 ==
7904 23:16:32.659236 DQS Delay:
7905 23:16:32.659294 DQS0 = 0, DQS1 = 0
7906 23:16:32.662361 DQM Delay:
7907 23:16:32.662441 DQM0 = 134, DQM1 = 128
7908 23:16:32.665777 DQ Delay:
7909 23:16:32.669211 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7910 23:16:32.672695 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =138
7911 23:16:32.675647 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120
7912 23:16:32.678935 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7913 23:16:32.679016
7914 23:16:32.679080
7915 23:16:32.679138
7916 23:16:32.683024 [DramC_TX_OE_Calibration] TA2
7917 23:16:32.685978 Original DQ_B0 (3 6) =30, OEN = 27
7918 23:16:32.689114 Original DQ_B1 (3 6) =30, OEN = 27
7919 23:16:32.692544 24, 0x0, End_B0=24 End_B1=24
7920 23:16:32.692626 25, 0x0, End_B0=25 End_B1=25
7921 23:16:32.695979 26, 0x0, End_B0=26 End_B1=26
7922 23:16:32.699262 27, 0x0, End_B0=27 End_B1=27
7923 23:16:32.702395 28, 0x0, End_B0=28 End_B1=28
7924 23:16:32.705541 29, 0x0, End_B0=29 End_B1=29
7925 23:16:32.705662 30, 0x0, End_B0=30 End_B1=30
7926 23:16:32.709050 31, 0x4141, End_B0=30 End_B1=30
7927 23:16:32.712142 Byte0 end_step=30 best_step=27
7928 23:16:32.715476 Byte1 end_step=30 best_step=27
7929 23:16:32.718696 Byte0 TX OE(2T, 0.5T) = (3, 3)
7930 23:16:32.722056 Byte1 TX OE(2T, 0.5T) = (3, 3)
7931 23:16:32.722136
7932 23:16:32.722200
7933 23:16:32.728988 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
7934 23:16:32.732022 CH0 RK0: MR19=303, MR18=2521
7935 23:16:32.738747 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
7936 23:16:32.738829
7937 23:16:32.742092 ----->DramcWriteLeveling(PI) begin...
7938 23:16:32.742174 ==
7939 23:16:32.745488 Dram Type= 6, Freq= 0, CH_0, rank 1
7940 23:16:32.748630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7941 23:16:32.748712 ==
7942 23:16:32.752276 Write leveling (Byte 0): 35 => 35
7943 23:16:32.755441 Write leveling (Byte 1): 28 => 28
7944 23:16:32.758811 DramcWriteLeveling(PI) end<-----
7945 23:16:32.758894
7946 23:16:32.758958 ==
7947 23:16:32.762289 Dram Type= 6, Freq= 0, CH_0, rank 1
7948 23:16:32.765825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7949 23:16:32.765931 ==
7950 23:16:32.769180 [Gating] SW mode calibration
7951 23:16:32.775235 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7952 23:16:32.782268 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7953 23:16:32.785097 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7954 23:16:32.788880 1 4 4 | B1->B0 | 2323 2222 | 0 1 | (0 0) (0 0)
7955 23:16:32.795768 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7956 23:16:32.798776 1 4 12 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7957 23:16:32.801969 1 4 16 | B1->B0 | 3030 3535 | 1 1 | (1 1) (0 0)
7958 23:16:32.808801 1 4 20 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
7959 23:16:32.811754 1 4 24 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
7960 23:16:32.815079 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
7961 23:16:32.821724 1 5 0 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
7962 23:16:32.825227 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
7963 23:16:32.828850 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7964 23:16:32.834983 1 5 12 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
7965 23:16:32.838234 1 5 16 | B1->B0 | 2d2d 2626 | 0 0 | (1 0) (1 0)
7966 23:16:32.841728 1 5 20 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7967 23:16:32.848515 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7968 23:16:32.851929 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7969 23:16:32.855035 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7970 23:16:32.861973 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7971 23:16:32.865054 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
7972 23:16:32.868525 1 6 12 | B1->B0 | 2424 3333 | 0 0 | (0 0) (0 0)
7973 23:16:32.875078 1 6 16 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
7974 23:16:32.878228 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7975 23:16:32.881441 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7976 23:16:32.888429 1 6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
7977 23:16:32.891524 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7978 23:16:32.895040 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7979 23:16:32.901635 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7980 23:16:32.904928 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7981 23:16:32.908405 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
7982 23:16:32.914964 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7983 23:16:32.918243 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7984 23:16:32.921763 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7985 23:16:32.924923 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7986 23:16:32.931514 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7987 23:16:32.934700 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7988 23:16:32.938019 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7989 23:16:32.944489 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7990 23:16:32.947779 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7991 23:16:32.950992 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7992 23:16:32.957940 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7993 23:16:32.961028 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7994 23:16:32.964843 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7995 23:16:32.971486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7996 23:16:32.974308 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7997 23:16:32.977666 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7998 23:16:32.984253 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 23:16:32.987611 Total UI for P1: 0, mck2ui 16
8000 23:16:32.990805 best dqsien dly found for B0: ( 1, 9, 12)
8001 23:16:32.994418 Total UI for P1: 0, mck2ui 16
8002 23:16:32.997453 best dqsien dly found for B1: ( 1, 9, 12)
8003 23:16:33.000782 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8004 23:16:33.004279 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8005 23:16:33.004360
8006 23:16:33.007680 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8007 23:16:33.010983 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8008 23:16:33.014254 [Gating] SW calibration Done
8009 23:16:33.014334 ==
8010 23:16:33.017251 Dram Type= 6, Freq= 0, CH_0, rank 1
8011 23:16:33.020657 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8012 23:16:33.020738 ==
8013 23:16:33.024240 RX Vref Scan: 0
8014 23:16:33.024321
8015 23:16:33.027457 RX Vref 0 -> 0, step: 1
8016 23:16:33.027537
8017 23:16:33.027600 RX Delay 0 -> 252, step: 8
8018 23:16:33.033974 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8019 23:16:33.037191 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8020 23:16:33.040730 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8021 23:16:33.044461 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8022 23:16:33.047446 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8023 23:16:33.050750 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8024 23:16:33.057385 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8025 23:16:33.060953 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8026 23:16:33.063868 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8027 23:16:33.067282 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8028 23:16:33.070845 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8029 23:16:33.077337 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8030 23:16:33.080426 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8031 23:16:33.083964 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
8032 23:16:33.087317 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8033 23:16:33.093849 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8034 23:16:33.093956 ==
8035 23:16:33.096937 Dram Type= 6, Freq= 0, CH_0, rank 1
8036 23:16:33.100880 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8037 23:16:33.100962 ==
8038 23:16:33.101026 DQS Delay:
8039 23:16:33.104059 DQS0 = 0, DQS1 = 0
8040 23:16:33.104139 DQM Delay:
8041 23:16:33.107418 DQM0 = 137, DQM1 = 130
8042 23:16:33.107499 DQ Delay:
8043 23:16:33.110356 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8044 23:16:33.113711 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8045 23:16:33.116956 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =119
8046 23:16:33.120218 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8047 23:16:33.120299
8048 23:16:33.120362
8049 23:16:33.123583 ==
8050 23:16:33.126738 Dram Type= 6, Freq= 0, CH_0, rank 1
8051 23:16:33.130299 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8052 23:16:33.130380 ==
8053 23:16:33.130445
8054 23:16:33.130503
8055 23:16:33.133279 TX Vref Scan disable
8056 23:16:33.133359 == TX Byte 0 ==
8057 23:16:33.136644 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8058 23:16:33.144087 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8059 23:16:33.144169 == TX Byte 1 ==
8060 23:16:33.150694 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8061 23:16:33.153515 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8062 23:16:33.153621 ==
8063 23:16:33.156780 Dram Type= 6, Freq= 0, CH_0, rank 1
8064 23:16:33.160235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8065 23:16:33.160317 ==
8066 23:16:33.173985
8067 23:16:33.177408 TX Vref early break, caculate TX vref
8068 23:16:33.180824 TX Vref=16, minBit 1, minWin=23, winSum=385
8069 23:16:33.184276 TX Vref=18, minBit 1, minWin=22, winSum=392
8070 23:16:33.187654 TX Vref=20, minBit 1, minWin=24, winSum=405
8071 23:16:33.191126 TX Vref=22, minBit 1, minWin=24, winSum=413
8072 23:16:33.193747 TX Vref=24, minBit 1, minWin=24, winSum=419
8073 23:16:33.200728 TX Vref=26, minBit 1, minWin=25, winSum=429
8074 23:16:33.203982 TX Vref=28, minBit 1, minWin=26, winSum=425
8075 23:16:33.207217 TX Vref=30, minBit 0, minWin=25, winSum=418
8076 23:16:33.210690 TX Vref=32, minBit 0, minWin=25, winSum=411
8077 23:16:33.213966 TX Vref=34, minBit 1, minWin=23, winSum=401
8078 23:16:33.220919 [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 28
8079 23:16:33.221031
8080 23:16:33.224315 Final TX Range 0 Vref 28
8081 23:16:33.224389
8082 23:16:33.224451 ==
8083 23:16:33.227891 Dram Type= 6, Freq= 0, CH_0, rank 1
8084 23:16:33.231007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8085 23:16:33.231078 ==
8086 23:16:33.231159
8087 23:16:33.231218
8088 23:16:33.234082 TX Vref Scan disable
8089 23:16:33.240988 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8090 23:16:33.241085 == TX Byte 0 ==
8091 23:16:33.244162 u2DelayCellOfst[0]=13 cells (4 PI)
8092 23:16:33.247464 u2DelayCellOfst[1]=16 cells (5 PI)
8093 23:16:33.250744 u2DelayCellOfst[2]=10 cells (3 PI)
8094 23:16:33.254241 u2DelayCellOfst[3]=10 cells (3 PI)
8095 23:16:33.257218 u2DelayCellOfst[4]=10 cells (3 PI)
8096 23:16:33.260820 u2DelayCellOfst[5]=0 cells (0 PI)
8097 23:16:33.264152 u2DelayCellOfst[6]=13 cells (4 PI)
8098 23:16:33.264234 u2DelayCellOfst[7]=16 cells (5 PI)
8099 23:16:33.270401 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8100 23:16:33.274059 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8101 23:16:33.274140 == TX Byte 1 ==
8102 23:16:33.277239 u2DelayCellOfst[8]=3 cells (1 PI)
8103 23:16:33.280264 u2DelayCellOfst[9]=0 cells (0 PI)
8104 23:16:33.283616 u2DelayCellOfst[10]=6 cells (2 PI)
8105 23:16:33.287431 u2DelayCellOfst[11]=3 cells (1 PI)
8106 23:16:33.290986 u2DelayCellOfst[12]=13 cells (4 PI)
8107 23:16:33.293698 u2DelayCellOfst[13]=13 cells (4 PI)
8108 23:16:33.297508 u2DelayCellOfst[14]=13 cells (4 PI)
8109 23:16:33.301008 u2DelayCellOfst[15]=10 cells (3 PI)
8110 23:16:33.303623 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8111 23:16:33.310507 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8112 23:16:33.310589 DramC Write-DBI on
8113 23:16:33.310653 ==
8114 23:16:33.313901 Dram Type= 6, Freq= 0, CH_0, rank 1
8115 23:16:33.316935 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8116 23:16:33.317017 ==
8117 23:16:33.320192
8118 23:16:33.320272
8119 23:16:33.320335 TX Vref Scan disable
8120 23:16:33.323720 == TX Byte 0 ==
8121 23:16:33.326876 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8122 23:16:33.330632 == TX Byte 1 ==
8123 23:16:33.333741 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8124 23:16:33.336898 DramC Write-DBI off
8125 23:16:33.336978
8126 23:16:33.337041 [DATLAT]
8127 23:16:33.337100 Freq=1600, CH0 RK1
8128 23:16:33.337158
8129 23:16:33.340204 DATLAT Default: 0xf
8130 23:16:33.340284 0, 0xFFFF, sum = 0
8131 23:16:33.343855 1, 0xFFFF, sum = 0
8132 23:16:33.347228 2, 0xFFFF, sum = 0
8133 23:16:33.347310 3, 0xFFFF, sum = 0
8134 23:16:33.350212 4, 0xFFFF, sum = 0
8135 23:16:33.350294 5, 0xFFFF, sum = 0
8136 23:16:33.353599 6, 0xFFFF, sum = 0
8137 23:16:33.353681 7, 0xFFFF, sum = 0
8138 23:16:33.356697 8, 0xFFFF, sum = 0
8139 23:16:33.356779 9, 0xFFFF, sum = 0
8140 23:16:33.359934 10, 0xFFFF, sum = 0
8141 23:16:33.360016 11, 0xFFFF, sum = 0
8142 23:16:33.363760 12, 0xFFFF, sum = 0
8143 23:16:33.363842 13, 0xFFFF, sum = 0
8144 23:16:33.366873 14, 0x0, sum = 1
8145 23:16:33.366954 15, 0x0, sum = 2
8146 23:16:33.370155 16, 0x0, sum = 3
8147 23:16:33.370237 17, 0x0, sum = 4
8148 23:16:33.373442 best_step = 15
8149 23:16:33.373523
8150 23:16:33.373610 ==
8151 23:16:33.377137 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 23:16:33.379755 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 23:16:33.379836 ==
8154 23:16:33.383387 RX Vref Scan: 0
8155 23:16:33.383468
8156 23:16:33.383532 RX Vref 0 -> 0, step: 1
8157 23:16:33.383591
8158 23:16:33.386887 RX Delay 19 -> 252, step: 4
8159 23:16:33.389954 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8160 23:16:33.396503 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8161 23:16:33.400019 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8162 23:16:33.403536 iDelay=191, Bit 3, Center 132 (79 ~ 186) 108
8163 23:16:33.406994 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8164 23:16:33.410105 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8165 23:16:33.416818 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8166 23:16:33.419730 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8167 23:16:33.423463 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8168 23:16:33.426827 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8169 23:16:33.430007 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8170 23:16:33.436628 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8171 23:16:33.439830 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8172 23:16:33.443131 iDelay=191, Bit 13, Center 132 (83 ~ 182) 100
8173 23:16:33.446732 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8174 23:16:33.449567 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8175 23:16:33.453446 ==
8176 23:16:33.453527 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 23:16:33.460270 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 23:16:33.460351 ==
8179 23:16:33.460415 DQS Delay:
8180 23:16:33.463139 DQS0 = 0, DQS1 = 0
8181 23:16:33.463220 DQM Delay:
8182 23:16:33.466661 DQM0 = 134, DQM1 = 126
8183 23:16:33.466741 DQ Delay:
8184 23:16:33.469691 DQ0 =134, DQ1 =138, DQ2 =132, DQ3 =132
8185 23:16:33.472990 DQ4 =136, DQ5 =124, DQ6 =140, DQ7 =140
8186 23:16:33.476706 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8187 23:16:33.479990 DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134
8188 23:16:33.480071
8189 23:16:33.480135
8190 23:16:33.480193
8191 23:16:33.483354 [DramC_TX_OE_Calibration] TA2
8192 23:16:33.486722 Original DQ_B0 (3 6) =30, OEN = 27
8193 23:16:33.490080 Original DQ_B1 (3 6) =30, OEN = 27
8194 23:16:33.493069 24, 0x0, End_B0=24 End_B1=24
8195 23:16:33.496971 25, 0x0, End_B0=25 End_B1=25
8196 23:16:33.497053 26, 0x0, End_B0=26 End_B1=26
8197 23:16:33.500344 27, 0x0, End_B0=27 End_B1=27
8198 23:16:33.503204 28, 0x0, End_B0=28 End_B1=28
8199 23:16:33.506503 29, 0x0, End_B0=29 End_B1=29
8200 23:16:33.506586 30, 0x0, End_B0=30 End_B1=30
8201 23:16:33.509827 31, 0x4141, End_B0=30 End_B1=30
8202 23:16:33.513054 Byte0 end_step=30 best_step=27
8203 23:16:33.516770 Byte1 end_step=30 best_step=27
8204 23:16:33.519888 Byte0 TX OE(2T, 0.5T) = (3, 3)
8205 23:16:33.523330 Byte1 TX OE(2T, 0.5T) = (3, 3)
8206 23:16:33.523410
8207 23:16:33.523474
8208 23:16:33.529821 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8209 23:16:33.533391 CH0 RK1: MR19=303, MR18=220A
8210 23:16:33.539785 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8211 23:16:33.543249 [RxdqsGatingPostProcess] freq 1600
8212 23:16:33.546173 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8213 23:16:33.549912 best DQS0 dly(2T, 0.5T) = (1, 1)
8214 23:16:33.552854 best DQS1 dly(2T, 0.5T) = (1, 1)
8215 23:16:33.556529 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8216 23:16:33.559866 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8217 23:16:33.563353 best DQS0 dly(2T, 0.5T) = (1, 1)
8218 23:16:33.566118 best DQS1 dly(2T, 0.5T) = (1, 1)
8219 23:16:33.569830 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8220 23:16:33.572830 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8221 23:16:33.576405 Pre-setting of DQS Precalculation
8222 23:16:33.580084 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8223 23:16:33.580165 ==
8224 23:16:33.583296 Dram Type= 6, Freq= 0, CH_1, rank 0
8225 23:16:33.586646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8226 23:16:33.589963 ==
8227 23:16:33.592858 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8228 23:16:33.596579 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8229 23:16:33.603113 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8230 23:16:33.606946 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8231 23:16:33.616892 [CA 0] Center 41 (12~71) winsize 60
8232 23:16:33.620283 [CA 1] Center 41 (12~71) winsize 60
8233 23:16:33.623049 [CA 2] Center 38 (9~68) winsize 60
8234 23:16:33.626417 [CA 3] Center 37 (8~66) winsize 59
8235 23:16:33.629972 [CA 4] Center 38 (9~67) winsize 59
8236 23:16:33.633139 [CA 5] Center 36 (7~66) winsize 60
8237 23:16:33.633219
8238 23:16:33.636555 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8239 23:16:33.636636
8240 23:16:33.639825 [CATrainingPosCal] consider 1 rank data
8241 23:16:33.643219 u2DelayCellTimex100 = 290/100 ps
8242 23:16:33.646682 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8243 23:16:33.652826 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8244 23:16:33.656070 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8245 23:16:33.659829 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8246 23:16:33.662946 CA4 delay=38 (9~67),Diff = 2 PI (6 cell)
8247 23:16:33.666269 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8248 23:16:33.666350
8249 23:16:33.669487 CA PerBit enable=1, Macro0, CA PI delay=36
8250 23:16:33.669568
8251 23:16:33.672582 [CBTSetCACLKResult] CA Dly = 36
8252 23:16:33.676519 CS Dly: 10 (0~41)
8253 23:16:33.679376 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8254 23:16:33.683036 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8255 23:16:33.683117 ==
8256 23:16:33.686091 Dram Type= 6, Freq= 0, CH_1, rank 1
8257 23:16:33.689529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8258 23:16:33.692760 ==
8259 23:16:33.695878 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8260 23:16:33.699146 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8261 23:16:33.705757 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8262 23:16:33.712835 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8263 23:16:33.719783 [CA 0] Center 42 (12~72) winsize 61
8264 23:16:33.723250 [CA 1] Center 42 (13~72) winsize 60
8265 23:16:33.726647 [CA 2] Center 38 (9~68) winsize 60
8266 23:16:33.729935 [CA 3] Center 38 (9~68) winsize 60
8267 23:16:33.733263 [CA 4] Center 39 (9~69) winsize 61
8268 23:16:33.736233 [CA 5] Center 37 (8~67) winsize 60
8269 23:16:33.736324
8270 23:16:33.739890 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8271 23:16:33.739971
8272 23:16:33.743083 [CATrainingPosCal] consider 2 rank data
8273 23:16:33.746680 u2DelayCellTimex100 = 290/100 ps
8274 23:16:33.749821 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8275 23:16:33.756486 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8276 23:16:33.759990 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8277 23:16:33.763175 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8278 23:16:33.766193 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8279 23:16:33.769505 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8280 23:16:33.769591
8281 23:16:33.772996 CA PerBit enable=1, Macro0, CA PI delay=37
8282 23:16:33.773076
8283 23:16:33.776491 [CBTSetCACLKResult] CA Dly = 37
8284 23:16:33.779529 CS Dly: 11 (0~44)
8285 23:16:33.783258 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8286 23:16:33.786151 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8287 23:16:33.786232
8288 23:16:33.789830 ----->DramcWriteLeveling(PI) begin...
8289 23:16:33.789913 ==
8290 23:16:33.792859 Dram Type= 6, Freq= 0, CH_1, rank 0
8291 23:16:33.796491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8292 23:16:33.799331 ==
8293 23:16:33.802941 Write leveling (Byte 0): 24 => 24
8294 23:16:33.803023 Write leveling (Byte 1): 26 => 26
8295 23:16:33.806201 DramcWriteLeveling(PI) end<-----
8296 23:16:33.806282
8297 23:16:33.806345 ==
8298 23:16:33.809381 Dram Type= 6, Freq= 0, CH_1, rank 0
8299 23:16:33.816028 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8300 23:16:33.816110 ==
8301 23:16:33.819300 [Gating] SW mode calibration
8302 23:16:33.826301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8303 23:16:33.829712 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8304 23:16:33.836211 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8305 23:16:33.839354 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8306 23:16:33.842680 1 4 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8307 23:16:33.848999 1 4 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
8308 23:16:33.852711 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8309 23:16:33.856032 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8310 23:16:33.862308 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8311 23:16:33.865808 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8312 23:16:33.869166 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8313 23:16:33.872688 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8314 23:16:33.879321 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
8315 23:16:33.882846 1 5 12 | B1->B0 | 2727 2323 | 0 0 | (1 0) (1 0)
8316 23:16:33.886239 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8317 23:16:33.892516 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8318 23:16:33.895887 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8319 23:16:33.899363 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 23:16:33.905848 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 23:16:33.908992 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 23:16:33.912533 1 6 8 | B1->B0 | 2424 3a3a | 0 0 | (0 0) (0 0)
8323 23:16:33.919068 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8324 23:16:33.922108 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8325 23:16:33.925347 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8326 23:16:33.932073 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8327 23:16:33.935365 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8328 23:16:33.938744 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8329 23:16:33.945272 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8330 23:16:33.948663 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8331 23:16:33.952161 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8332 23:16:33.958772 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8333 23:16:33.961521 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8334 23:16:33.964947 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8335 23:16:33.971712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8336 23:16:33.975063 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8337 23:16:33.977929 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8338 23:16:33.984733 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8339 23:16:33.988404 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8340 23:16:33.991513 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8341 23:16:33.998058 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8342 23:16:34.001250 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8343 23:16:34.004724 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8344 23:16:34.010901 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8345 23:16:34.014304 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8346 23:16:34.017764 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8347 23:16:34.024433 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8348 23:16:34.028213 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 23:16:34.031227 Total UI for P1: 0, mck2ui 16
8350 23:16:34.034263 best dqsien dly found for B0: ( 1, 9, 12)
8351 23:16:34.037758 Total UI for P1: 0, mck2ui 16
8352 23:16:34.040912 best dqsien dly found for B1: ( 1, 9, 12)
8353 23:16:34.044360 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8354 23:16:34.047900 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8355 23:16:34.047980
8356 23:16:34.051213 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8357 23:16:34.054300 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8358 23:16:34.057869 [Gating] SW calibration Done
8359 23:16:34.057950 ==
8360 23:16:34.061420 Dram Type= 6, Freq= 0, CH_1, rank 0
8361 23:16:34.064491 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8362 23:16:34.067715 ==
8363 23:16:34.067794 RX Vref Scan: 0
8364 23:16:34.067858
8365 23:16:34.071354 RX Vref 0 -> 0, step: 1
8366 23:16:34.071435
8367 23:16:34.071498 RX Delay 0 -> 252, step: 8
8368 23:16:34.077962 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8369 23:16:34.081515 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8370 23:16:34.084750 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8371 23:16:34.087707 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8372 23:16:34.091038 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8373 23:16:34.097936 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8374 23:16:34.101131 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8375 23:16:34.104406 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8376 23:16:34.107768 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8377 23:16:34.111075 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8378 23:16:34.118052 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8379 23:16:34.121157 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8380 23:16:34.124474 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8381 23:16:34.127704 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8382 23:16:34.131074 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8383 23:16:34.137835 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8384 23:16:34.137917 ==
8385 23:16:34.141081 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 23:16:34.144425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 23:16:34.144507 ==
8388 23:16:34.144572 DQS Delay:
8389 23:16:34.147667 DQS0 = 0, DQS1 = 0
8390 23:16:34.147748 DQM Delay:
8391 23:16:34.151224 DQM0 = 136, DQM1 = 132
8392 23:16:34.151305 DQ Delay:
8393 23:16:34.154275 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8394 23:16:34.157627 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8395 23:16:34.161189 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8396 23:16:34.164422 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8397 23:16:34.164503
8398 23:16:34.167652
8399 23:16:34.167732 ==
8400 23:16:34.171301 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 23:16:34.174196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 23:16:34.174277 ==
8403 23:16:34.174341
8404 23:16:34.174399
8405 23:16:34.177632 TX Vref Scan disable
8406 23:16:34.177741 == TX Byte 0 ==
8407 23:16:34.184331 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8408 23:16:34.187322 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8409 23:16:34.187428 == TX Byte 1 ==
8410 23:16:34.194388 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8411 23:16:34.197709 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8412 23:16:34.197790 ==
8413 23:16:34.201187 Dram Type= 6, Freq= 0, CH_1, rank 0
8414 23:16:34.204139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8415 23:16:34.204220 ==
8416 23:16:34.217255
8417 23:16:34.220542 TX Vref early break, caculate TX vref
8418 23:16:34.223848 TX Vref=16, minBit 0, minWin=23, winSum=380
8419 23:16:34.227156 TX Vref=18, minBit 1, minWin=23, winSum=392
8420 23:16:34.230894 TX Vref=20, minBit 1, minWin=24, winSum=404
8421 23:16:34.233818 TX Vref=22, minBit 0, minWin=25, winSum=410
8422 23:16:34.237327 TX Vref=24, minBit 0, minWin=25, winSum=418
8423 23:16:34.243690 TX Vref=26, minBit 0, minWin=25, winSum=427
8424 23:16:34.247075 TX Vref=28, minBit 0, minWin=26, winSum=432
8425 23:16:34.250725 TX Vref=30, minBit 6, minWin=25, winSum=425
8426 23:16:34.253513 TX Vref=32, minBit 0, minWin=24, winSum=415
8427 23:16:34.257159 TX Vref=34, minBit 0, minWin=24, winSum=407
8428 23:16:34.264110 [TxChooseVref] Worse bit 0, Min win 26, Win sum 432, Final Vref 28
8429 23:16:34.264192
8430 23:16:34.267162 Final TX Range 0 Vref 28
8431 23:16:34.267242
8432 23:16:34.267306 ==
8433 23:16:34.270182 Dram Type= 6, Freq= 0, CH_1, rank 0
8434 23:16:34.273465 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8435 23:16:34.273546 ==
8436 23:16:34.273654
8437 23:16:34.273715
8438 23:16:34.277164 TX Vref Scan disable
8439 23:16:34.283493 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8440 23:16:34.283574 == TX Byte 0 ==
8441 23:16:34.286785 u2DelayCellOfst[0]=16 cells (5 PI)
8442 23:16:34.290261 u2DelayCellOfst[1]=10 cells (3 PI)
8443 23:16:34.293499 u2DelayCellOfst[2]=0 cells (0 PI)
8444 23:16:34.296709 u2DelayCellOfst[3]=6 cells (2 PI)
8445 23:16:34.300671 u2DelayCellOfst[4]=10 cells (3 PI)
8446 23:16:34.303412 u2DelayCellOfst[5]=16 cells (5 PI)
8447 23:16:34.306885 u2DelayCellOfst[6]=16 cells (5 PI)
8448 23:16:34.306965 u2DelayCellOfst[7]=6 cells (2 PI)
8449 23:16:34.313493 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8450 23:16:34.316969 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8451 23:16:34.317051 == TX Byte 1 ==
8452 23:16:34.320383 u2DelayCellOfst[8]=0 cells (0 PI)
8453 23:16:34.323782 u2DelayCellOfst[9]=3 cells (1 PI)
8454 23:16:34.326748 u2DelayCellOfst[10]=13 cells (4 PI)
8455 23:16:34.330331 u2DelayCellOfst[11]=3 cells (1 PI)
8456 23:16:34.333331 u2DelayCellOfst[12]=16 cells (5 PI)
8457 23:16:34.336848 u2DelayCellOfst[13]=16 cells (5 PI)
8458 23:16:34.340154 u2DelayCellOfst[14]=16 cells (5 PI)
8459 23:16:34.343605 u2DelayCellOfst[15]=16 cells (5 PI)
8460 23:16:34.346853 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8461 23:16:34.353357 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8462 23:16:34.353439 DramC Write-DBI on
8463 23:16:34.353503 ==
8464 23:16:34.356710 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 23:16:34.359840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 23:16:34.359922 ==
8467 23:16:34.363471
8468 23:16:34.363551
8469 23:16:34.363614 TX Vref Scan disable
8470 23:16:34.366654 == TX Byte 0 ==
8471 23:16:34.370011 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8472 23:16:34.373810 == TX Byte 1 ==
8473 23:16:34.376813 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8474 23:16:34.376894 DramC Write-DBI off
8475 23:16:34.376958
8476 23:16:34.380179 [DATLAT]
8477 23:16:34.380259 Freq=1600, CH1 RK0
8478 23:16:34.380324
8479 23:16:34.383487 DATLAT Default: 0xf
8480 23:16:34.383568 0, 0xFFFF, sum = 0
8481 23:16:34.386754 1, 0xFFFF, sum = 0
8482 23:16:34.386836 2, 0xFFFF, sum = 0
8483 23:16:34.389926 3, 0xFFFF, sum = 0
8484 23:16:34.390011 4, 0xFFFF, sum = 0
8485 23:16:34.393334 5, 0xFFFF, sum = 0
8486 23:16:34.396608 6, 0xFFFF, sum = 0
8487 23:16:34.396721 7, 0xFFFF, sum = 0
8488 23:16:34.399804 8, 0xFFFF, sum = 0
8489 23:16:34.399886 9, 0xFFFF, sum = 0
8490 23:16:34.403278 10, 0xFFFF, sum = 0
8491 23:16:34.403360 11, 0xFFFF, sum = 0
8492 23:16:34.406853 12, 0xFFFF, sum = 0
8493 23:16:34.406934 13, 0xFFFF, sum = 0
8494 23:16:34.409782 14, 0x0, sum = 1
8495 23:16:34.409864 15, 0x0, sum = 2
8496 23:16:34.413326 16, 0x0, sum = 3
8497 23:16:34.413407 17, 0x0, sum = 4
8498 23:16:34.416828 best_step = 15
8499 23:16:34.416909
8500 23:16:34.416984 ==
8501 23:16:34.420331 Dram Type= 6, Freq= 0, CH_1, rank 0
8502 23:16:34.423255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8503 23:16:34.423336 ==
8504 23:16:34.423400 RX Vref Scan: 1
8505 23:16:34.423459
8506 23:16:34.426926 Set Vref Range= 24 -> 127
8507 23:16:34.427006
8508 23:16:34.430214 RX Vref 24 -> 127, step: 1
8509 23:16:34.430295
8510 23:16:34.432800 RX Delay 27 -> 252, step: 4
8511 23:16:34.432881
8512 23:16:34.436503 Set Vref, RX VrefLevel [Byte0]: 24
8513 23:16:34.439776 [Byte1]: 24
8514 23:16:34.439857
8515 23:16:34.443159 Set Vref, RX VrefLevel [Byte0]: 25
8516 23:16:34.446441 [Byte1]: 25
8517 23:16:34.446522
8518 23:16:34.450037 Set Vref, RX VrefLevel [Byte0]: 26
8519 23:16:34.452742 [Byte1]: 26
8520 23:16:34.456593
8521 23:16:34.456674 Set Vref, RX VrefLevel [Byte0]: 27
8522 23:16:34.459741 [Byte1]: 27
8523 23:16:34.464197
8524 23:16:34.464277 Set Vref, RX VrefLevel [Byte0]: 28
8525 23:16:34.467898 [Byte1]: 28
8526 23:16:34.471674
8527 23:16:34.471758 Set Vref, RX VrefLevel [Byte0]: 29
8528 23:16:34.474984 [Byte1]: 29
8529 23:16:34.479057
8530 23:16:34.479137 Set Vref, RX VrefLevel [Byte0]: 30
8531 23:16:34.482494 [Byte1]: 30
8532 23:16:34.486814
8533 23:16:34.486894 Set Vref, RX VrefLevel [Byte0]: 31
8534 23:16:34.489969 [Byte1]: 31
8535 23:16:34.494147
8536 23:16:34.494228 Set Vref, RX VrefLevel [Byte0]: 32
8537 23:16:34.497621 [Byte1]: 32
8538 23:16:34.502190
8539 23:16:34.502270 Set Vref, RX VrefLevel [Byte0]: 33
8540 23:16:34.505142 [Byte1]: 33
8541 23:16:34.509456
8542 23:16:34.509536 Set Vref, RX VrefLevel [Byte0]: 34
8543 23:16:34.512832 [Byte1]: 34
8544 23:16:34.516670
8545 23:16:34.516750 Set Vref, RX VrefLevel [Byte0]: 35
8546 23:16:34.520240 [Byte1]: 35
8547 23:16:34.524521
8548 23:16:34.524601 Set Vref, RX VrefLevel [Byte0]: 36
8549 23:16:34.527675 [Byte1]: 36
8550 23:16:34.531833
8551 23:16:34.531914 Set Vref, RX VrefLevel [Byte0]: 37
8552 23:16:34.535690 [Byte1]: 37
8553 23:16:34.539525
8554 23:16:34.539605 Set Vref, RX VrefLevel [Byte0]: 38
8555 23:16:34.542621 [Byte1]: 38
8556 23:16:34.547385
8557 23:16:34.547466 Set Vref, RX VrefLevel [Byte0]: 39
8558 23:16:34.550217 [Byte1]: 39
8559 23:16:34.554708
8560 23:16:34.554788 Set Vref, RX VrefLevel [Byte0]: 40
8561 23:16:34.558101 [Byte1]: 40
8562 23:16:34.561965
8563 23:16:34.562045 Set Vref, RX VrefLevel [Byte0]: 41
8564 23:16:34.565762 [Byte1]: 41
8565 23:16:34.569761
8566 23:16:34.569841 Set Vref, RX VrefLevel [Byte0]: 42
8567 23:16:34.572873 [Byte1]: 42
8568 23:16:34.577051
8569 23:16:34.577131 Set Vref, RX VrefLevel [Byte0]: 43
8570 23:16:34.580307 [Byte1]: 43
8571 23:16:34.584710
8572 23:16:34.584791 Set Vref, RX VrefLevel [Byte0]: 44
8573 23:16:34.588042 [Byte1]: 44
8574 23:16:34.592391
8575 23:16:34.592471 Set Vref, RX VrefLevel [Byte0]: 45
8576 23:16:34.595520 [Byte1]: 45
8577 23:16:34.599579
8578 23:16:34.599659 Set Vref, RX VrefLevel [Byte0]: 46
8579 23:16:34.603132 [Byte1]: 46
8580 23:16:34.607408
8581 23:16:34.607489 Set Vref, RX VrefLevel [Byte0]: 47
8582 23:16:34.610977 [Byte1]: 47
8583 23:16:34.614693
8584 23:16:34.614773 Set Vref, RX VrefLevel [Byte0]: 48
8585 23:16:34.617887 [Byte1]: 48
8586 23:16:34.622570
8587 23:16:34.622650 Set Vref, RX VrefLevel [Byte0]: 49
8588 23:16:34.625852 [Byte1]: 49
8589 23:16:34.630165
8590 23:16:34.630249 Set Vref, RX VrefLevel [Byte0]: 50
8591 23:16:34.633219 [Byte1]: 50
8592 23:16:34.637458
8593 23:16:34.637562 Set Vref, RX VrefLevel [Byte0]: 51
8594 23:16:34.640557 [Byte1]: 51
8595 23:16:34.644913
8596 23:16:34.645019 Set Vref, RX VrefLevel [Byte0]: 52
8597 23:16:34.648318 [Byte1]: 52
8598 23:16:34.652380
8599 23:16:34.652451 Set Vref, RX VrefLevel [Byte0]: 53
8600 23:16:34.655675 [Byte1]: 53
8601 23:16:34.659867
8602 23:16:34.659962 Set Vref, RX VrefLevel [Byte0]: 54
8603 23:16:34.663146 [Byte1]: 54
8604 23:16:34.667557
8605 23:16:34.667651 Set Vref, RX VrefLevel [Byte0]: 55
8606 23:16:34.671029 [Byte1]: 55
8607 23:16:34.675129
8608 23:16:34.675235 Set Vref, RX VrefLevel [Byte0]: 56
8609 23:16:34.678257 [Byte1]: 56
8610 23:16:34.682338
8611 23:16:34.682432 Set Vref, RX VrefLevel [Byte0]: 57
8612 23:16:34.685869 [Byte1]: 57
8613 23:16:34.690284
8614 23:16:34.690382 Set Vref, RX VrefLevel [Byte0]: 58
8615 23:16:34.693685 [Byte1]: 58
8616 23:16:34.697950
8617 23:16:34.698051 Set Vref, RX VrefLevel [Byte0]: 59
8618 23:16:34.700775 [Byte1]: 59
8619 23:16:34.705222
8620 23:16:34.705320 Set Vref, RX VrefLevel [Byte0]: 60
8621 23:16:34.708925 [Byte1]: 60
8622 23:16:34.712695
8623 23:16:34.712770 Set Vref, RX VrefLevel [Byte0]: 61
8624 23:16:34.716093 [Byte1]: 61
8625 23:16:34.720254
8626 23:16:34.720351 Set Vref, RX VrefLevel [Byte0]: 62
8627 23:16:34.723997 [Byte1]: 62
8628 23:16:34.728039
8629 23:16:34.728132 Set Vref, RX VrefLevel [Byte0]: 63
8630 23:16:34.731290 [Byte1]: 63
8631 23:16:34.735496
8632 23:16:34.735595 Set Vref, RX VrefLevel [Byte0]: 64
8633 23:16:34.739054 [Byte1]: 64
8634 23:16:34.743029
8635 23:16:34.743099 Set Vref, RX VrefLevel [Byte0]: 65
8636 23:16:34.746194 [Byte1]: 65
8637 23:16:34.750279
8638 23:16:34.750373 Set Vref, RX VrefLevel [Byte0]: 66
8639 23:16:34.753773 [Byte1]: 66
8640 23:16:34.757802
8641 23:16:34.757869 Set Vref, RX VrefLevel [Byte0]: 67
8642 23:16:34.761905 [Byte1]: 67
8643 23:16:34.765586
8644 23:16:34.765671 Set Vref, RX VrefLevel [Byte0]: 68
8645 23:16:34.768924 [Byte1]: 68
8646 23:16:34.772852
8647 23:16:34.772955 Set Vref, RX VrefLevel [Byte0]: 69
8648 23:16:34.776375 [Byte1]: 69
8649 23:16:34.780533
8650 23:16:34.780629 Set Vref, RX VrefLevel [Byte0]: 70
8651 23:16:34.784022 [Byte1]: 70
8652 23:16:34.787926
8653 23:16:34.788025 Set Vref, RX VrefLevel [Byte0]: 71
8654 23:16:34.791498 [Byte1]: 71
8655 23:16:34.795977
8656 23:16:34.796084 Set Vref, RX VrefLevel [Byte0]: 72
8657 23:16:34.799038 [Byte1]: 72
8658 23:16:34.803130
8659 23:16:34.803203 Set Vref, RX VrefLevel [Byte0]: 73
8660 23:16:34.806272 [Byte1]: 73
8661 23:16:34.810935
8662 23:16:34.811034 Set Vref, RX VrefLevel [Byte0]: 74
8663 23:16:34.813949 [Byte1]: 74
8664 23:16:34.817917
8665 23:16:34.817988 Set Vref, RX VrefLevel [Byte0]: 75
8666 23:16:34.821711 [Byte1]: 75
8667 23:16:34.825736
8668 23:16:34.825805 Set Vref, RX VrefLevel [Byte0]: 76
8669 23:16:34.829268 [Byte1]: 76
8670 23:16:34.833172
8671 23:16:34.833241 Set Vref, RX VrefLevel [Byte0]: 77
8672 23:16:34.836662 [Byte1]: 77
8673 23:16:34.841015
8674 23:16:34.841107 Final RX Vref Byte 0 = 59 to rank0
8675 23:16:34.844257 Final RX Vref Byte 1 = 57 to rank0
8676 23:16:34.847337 Final RX Vref Byte 0 = 59 to rank1
8677 23:16:34.850668 Final RX Vref Byte 1 = 57 to rank1==
8678 23:16:34.854111 Dram Type= 6, Freq= 0, CH_1, rank 0
8679 23:16:34.860443 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8680 23:16:34.860537 ==
8681 23:16:34.860622 DQS Delay:
8682 23:16:34.860681 DQS0 = 0, DQS1 = 0
8683 23:16:34.864149 DQM Delay:
8684 23:16:34.864213 DQM0 = 134, DQM1 = 131
8685 23:16:34.867174 DQ Delay:
8686 23:16:34.870824 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8687 23:16:34.873817 DQ4 =134, DQ5 =144, DQ6 =144, DQ7 =132
8688 23:16:34.877339 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8689 23:16:34.880185 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8690 23:16:34.880253
8691 23:16:34.880315
8692 23:16:34.880374
8693 23:16:34.883614 [DramC_TX_OE_Calibration] TA2
8694 23:16:34.887361 Original DQ_B0 (3 6) =30, OEN = 27
8695 23:16:34.890413 Original DQ_B1 (3 6) =30, OEN = 27
8696 23:16:34.893803 24, 0x0, End_B0=24 End_B1=24
8697 23:16:34.893876 25, 0x0, End_B0=25 End_B1=25
8698 23:16:34.897026 26, 0x0, End_B0=26 End_B1=26
8699 23:16:34.900222 27, 0x0, End_B0=27 End_B1=27
8700 23:16:34.903745 28, 0x0, End_B0=28 End_B1=28
8701 23:16:34.906951 29, 0x0, End_B0=29 End_B1=29
8702 23:16:34.907025 30, 0x0, End_B0=30 End_B1=30
8703 23:16:34.910584 31, 0x4141, End_B0=30 End_B1=30
8704 23:16:34.913729 Byte0 end_step=30 best_step=27
8705 23:16:34.916969 Byte1 end_step=30 best_step=27
8706 23:16:34.920463 Byte0 TX OE(2T, 0.5T) = (3, 3)
8707 23:16:34.923736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8708 23:16:34.923806
8709 23:16:34.923865
8710 23:16:34.930235 [DQSOSCAuto] RK0, (LSB)MR18= 0x1826, (MSB)MR19= 0x303, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
8711 23:16:34.933512 CH1 RK0: MR19=303, MR18=1826
8712 23:16:34.940306 CH1_RK0: MR19=0x303, MR18=0x1826, DQSOSC=390, MR23=63, INC=24, DEC=16
8713 23:16:34.940404
8714 23:16:34.943867 ----->DramcWriteLeveling(PI) begin...
8715 23:16:34.943934 ==
8716 23:16:34.946803 Dram Type= 6, Freq= 0, CH_1, rank 1
8717 23:16:34.950360 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8718 23:16:34.950426 ==
8719 23:16:34.953438 Write leveling (Byte 0): 26 => 26
8720 23:16:34.956842 Write leveling (Byte 1): 27 => 27
8721 23:16:34.960139 DramcWriteLeveling(PI) end<-----
8722 23:16:34.960234
8723 23:16:34.960320 ==
8724 23:16:34.963601 Dram Type= 6, Freq= 0, CH_1, rank 1
8725 23:16:34.966764 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8726 23:16:34.966837 ==
8727 23:16:34.970310 [Gating] SW mode calibration
8728 23:16:34.976570 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8729 23:16:34.983214 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8730 23:16:34.986721 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8731 23:16:34.993141 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8732 23:16:34.996683 1 4 8 | B1->B0 | 2c2c 2323 | 1 0 | (1 1) (0 0)
8733 23:16:34.999874 1 4 12 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 1)
8734 23:16:35.003407 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 23:16:35.010444 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 23:16:35.014013 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 23:16:35.016597 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 23:16:35.023302 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8739 23:16:35.026830 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8740 23:16:35.030080 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 0)
8741 23:16:35.036899 1 5 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 0)
8742 23:16:35.039815 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 23:16:35.043320 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 23:16:35.050039 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 23:16:35.053394 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8746 23:16:35.056572 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8747 23:16:35.063505 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8748 23:16:35.066923 1 6 8 | B1->B0 | 3a3a 2323 | 1 0 | (0 0) (0 0)
8749 23:16:35.070182 1 6 12 | B1->B0 | 4646 4343 | 0 1 | (0 0) (0 0)
8750 23:16:35.076448 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 23:16:35.079816 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 23:16:35.083158 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 23:16:35.089967 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8754 23:16:35.093193 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8755 23:16:35.096414 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 23:16:35.103398 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8757 23:16:35.106281 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8758 23:16:35.109995 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8759 23:16:35.116729 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 23:16:35.120052 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 23:16:35.123051 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 23:16:35.126574 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 23:16:35.132815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 23:16:35.136582 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 23:16:35.139823 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 23:16:35.146223 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 23:16:35.149479 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 23:16:35.153002 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 23:16:35.160023 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 23:16:35.162960 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 23:16:35.166064 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8772 23:16:35.172971 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8773 23:16:35.176376 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8774 23:16:35.179383 Total UI for P1: 0, mck2ui 16
8775 23:16:35.183041 best dqsien dly found for B1: ( 1, 9, 6)
8776 23:16:35.186598 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 23:16:35.189757 Total UI for P1: 0, mck2ui 16
8778 23:16:35.193248 best dqsien dly found for B0: ( 1, 9, 12)
8779 23:16:35.196467 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8780 23:16:35.199930 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8781 23:16:35.200003
8782 23:16:35.203612 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8783 23:16:35.209399 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8784 23:16:35.209495 [Gating] SW calibration Done
8785 23:16:35.209619 ==
8786 23:16:35.213324 Dram Type= 6, Freq= 0, CH_1, rank 1
8787 23:16:35.219590 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8788 23:16:35.219675 ==
8789 23:16:35.219739 RX Vref Scan: 0
8790 23:16:35.219798
8791 23:16:35.223019 RX Vref 0 -> 0, step: 1
8792 23:16:35.223100
8793 23:16:35.226415 RX Delay 0 -> 252, step: 8
8794 23:16:35.229967 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8795 23:16:35.232657 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8796 23:16:35.236026 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8797 23:16:35.242854 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8798 23:16:35.246236 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8799 23:16:35.249323 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8800 23:16:35.252941 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8801 23:16:35.256099 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8802 23:16:35.262641 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8803 23:16:35.266131 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8804 23:16:35.269163 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8805 23:16:35.272824 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8806 23:16:35.275736 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8807 23:16:35.282551 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8808 23:16:35.285819 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8809 23:16:35.288797 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8810 23:16:35.288903 ==
8811 23:16:35.292304 Dram Type= 6, Freq= 0, CH_1, rank 1
8812 23:16:35.295674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8813 23:16:35.298931 ==
8814 23:16:35.299004 DQS Delay:
8815 23:16:35.299064 DQS0 = 0, DQS1 = 0
8816 23:16:35.302237 DQM Delay:
8817 23:16:35.302305 DQM0 = 136, DQM1 = 133
8818 23:16:35.305581 DQ Delay:
8819 23:16:35.308903 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8820 23:16:35.311920 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8821 23:16:35.315616 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8822 23:16:35.318998 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8823 23:16:35.319071
8824 23:16:35.319151
8825 23:16:35.319209 ==
8826 23:16:35.321659 Dram Type= 6, Freq= 0, CH_1, rank 1
8827 23:16:35.325117 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8828 23:16:35.328659 ==
8829 23:16:35.328755
8830 23:16:35.328844
8831 23:16:35.328930 TX Vref Scan disable
8832 23:16:35.332353 == TX Byte 0 ==
8833 23:16:35.335575 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8834 23:16:35.338414 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8835 23:16:35.341727 == TX Byte 1 ==
8836 23:16:35.345583 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8837 23:16:35.348636 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8838 23:16:35.348708 ==
8839 23:16:35.351667 Dram Type= 6, Freq= 0, CH_1, rank 1
8840 23:16:35.358179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8841 23:16:35.358263 ==
8842 23:16:35.370095
8843 23:16:35.373431 TX Vref early break, caculate TX vref
8844 23:16:35.376889 TX Vref=16, minBit 0, minWin=23, winSum=381
8845 23:16:35.379810 TX Vref=18, minBit 6, minWin=23, winSum=393
8846 23:16:35.383332 TX Vref=20, minBit 1, minWin=24, winSum=403
8847 23:16:35.386636 TX Vref=22, minBit 0, minWin=24, winSum=411
8848 23:16:35.390103 TX Vref=24, minBit 0, minWin=25, winSum=422
8849 23:16:35.396489 TX Vref=26, minBit 0, minWin=25, winSum=425
8850 23:16:35.399827 TX Vref=28, minBit 0, minWin=26, winSum=430
8851 23:16:35.403800 TX Vref=30, minBit 0, minWin=25, winSum=418
8852 23:16:35.406327 TX Vref=32, minBit 1, minWin=25, winSum=415
8853 23:16:35.410198 TX Vref=34, minBit 0, minWin=24, winSum=406
8854 23:16:35.416802 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8855 23:16:35.416901
8856 23:16:35.420018 Final TX Range 0 Vref 28
8857 23:16:35.420100
8858 23:16:35.420164 ==
8859 23:16:35.423355 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 23:16:35.426593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 23:16:35.426675 ==
8862 23:16:35.426739
8863 23:16:35.426798
8864 23:16:35.430124 TX Vref Scan disable
8865 23:16:35.436238 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8866 23:16:35.436319 == TX Byte 0 ==
8867 23:16:35.439577 u2DelayCellOfst[0]=16 cells (5 PI)
8868 23:16:35.443307 u2DelayCellOfst[1]=13 cells (4 PI)
8869 23:16:35.446217 u2DelayCellOfst[2]=0 cells (0 PI)
8870 23:16:35.449595 u2DelayCellOfst[3]=6 cells (2 PI)
8871 23:16:35.453002 u2DelayCellOfst[4]=10 cells (3 PI)
8872 23:16:35.456774 u2DelayCellOfst[5]=16 cells (5 PI)
8873 23:16:35.459853 u2DelayCellOfst[6]=16 cells (5 PI)
8874 23:16:35.459934 u2DelayCellOfst[7]=6 cells (2 PI)
8875 23:16:35.466803 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8876 23:16:35.469752 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 23:16:35.469832 == TX Byte 1 ==
8878 23:16:35.473561 u2DelayCellOfst[8]=0 cells (0 PI)
8879 23:16:35.476496 u2DelayCellOfst[9]=3 cells (1 PI)
8880 23:16:35.479717 u2DelayCellOfst[10]=10 cells (3 PI)
8881 23:16:35.482871 u2DelayCellOfst[11]=3 cells (1 PI)
8882 23:16:35.486347 u2DelayCellOfst[12]=16 cells (5 PI)
8883 23:16:35.489472 u2DelayCellOfst[13]=13 cells (4 PI)
8884 23:16:35.492746 u2DelayCellOfst[14]=16 cells (5 PI)
8885 23:16:35.496448 u2DelayCellOfst[15]=16 cells (5 PI)
8886 23:16:35.499580 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8887 23:16:35.506064 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 23:16:35.506145 DramC Write-DBI on
8889 23:16:35.506208 ==
8890 23:16:35.509511 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 23:16:35.513104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 23:16:35.516338 ==
8893 23:16:35.516438
8894 23:16:35.516527
8895 23:16:35.516614 TX Vref Scan disable
8896 23:16:35.519479 == TX Byte 0 ==
8897 23:16:35.522716 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8898 23:16:35.525593 == TX Byte 1 ==
8899 23:16:35.529457 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8900 23:16:35.532292 DramC Write-DBI off
8901 23:16:35.532390
8902 23:16:35.532478 [DATLAT]
8903 23:16:35.532575 Freq=1600, CH1 RK1
8904 23:16:35.532660
8905 23:16:35.535721 DATLAT Default: 0xf
8906 23:16:35.539137 0, 0xFFFF, sum = 0
8907 23:16:35.539241 1, 0xFFFF, sum = 0
8908 23:16:35.542275 2, 0xFFFF, sum = 0
8909 23:16:35.542348 3, 0xFFFF, sum = 0
8910 23:16:35.545877 4, 0xFFFF, sum = 0
8911 23:16:35.545977 5, 0xFFFF, sum = 0
8912 23:16:35.549399 6, 0xFFFF, sum = 0
8913 23:16:35.549499 7, 0xFFFF, sum = 0
8914 23:16:35.552893 8, 0xFFFF, sum = 0
8915 23:16:35.552993 9, 0xFFFF, sum = 0
8916 23:16:35.555698 10, 0xFFFF, sum = 0
8917 23:16:35.555797 11, 0xFFFF, sum = 0
8918 23:16:35.559222 12, 0xFFFF, sum = 0
8919 23:16:35.559329 13, 0xFFFF, sum = 0
8920 23:16:35.562578 14, 0x0, sum = 1
8921 23:16:35.562651 15, 0x0, sum = 2
8922 23:16:35.565656 16, 0x0, sum = 3
8923 23:16:35.565725 17, 0x0, sum = 4
8924 23:16:35.568993 best_step = 15
8925 23:16:35.569063
8926 23:16:35.569123 ==
8927 23:16:35.572522 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 23:16:35.575689 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 23:16:35.575791 ==
8930 23:16:35.575887 RX Vref Scan: 0
8931 23:16:35.579371
8932 23:16:35.579443 RX Vref 0 -> 0, step: 1
8933 23:16:35.579503
8934 23:16:35.582713 RX Delay 19 -> 252, step: 4
8935 23:16:35.585954 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
8936 23:16:35.592518 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
8937 23:16:35.595941 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
8938 23:16:35.599100 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
8939 23:16:35.602422 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
8940 23:16:35.605773 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
8941 23:16:35.609012 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
8942 23:16:35.615452 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
8943 23:16:35.619168 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
8944 23:16:35.622510 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8945 23:16:35.625612 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
8946 23:16:35.628817 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
8947 23:16:35.635747 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
8948 23:16:35.639106 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8949 23:16:35.642166 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
8950 23:16:35.645773 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
8951 23:16:35.645848 ==
8952 23:16:35.648848 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 23:16:35.655322 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 23:16:35.655402 ==
8955 23:16:35.655465 DQS Delay:
8956 23:16:35.658744 DQS0 = 0, DQS1 = 0
8957 23:16:35.658810 DQM Delay:
8958 23:16:35.662146 DQM0 = 134, DQM1 = 130
8959 23:16:35.662216 DQ Delay:
8960 23:16:35.665740 DQ0 =138, DQ1 =132, DQ2 =122, DQ3 =130
8961 23:16:35.668560 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
8962 23:16:35.671683 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
8963 23:16:35.675087 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
8964 23:16:35.675157
8965 23:16:35.675216
8966 23:16:35.675282
8967 23:16:35.678468 [DramC_TX_OE_Calibration] TA2
8968 23:16:35.681899 Original DQ_B0 (3 6) =30, OEN = 27
8969 23:16:35.685398 Original DQ_B1 (3 6) =30, OEN = 27
8970 23:16:35.688520 24, 0x0, End_B0=24 End_B1=24
8971 23:16:35.692186 25, 0x0, End_B0=25 End_B1=25
8972 23:16:35.692290 26, 0x0, End_B0=26 End_B1=26
8973 23:16:35.695521 27, 0x0, End_B0=27 End_B1=27
8974 23:16:35.698437 28, 0x0, End_B0=28 End_B1=28
8975 23:16:35.701894 29, 0x0, End_B0=29 End_B1=29
8976 23:16:35.701975 30, 0x0, End_B0=30 End_B1=30
8977 23:16:35.705421 31, 0x4141, End_B0=30 End_B1=30
8978 23:16:35.708259 Byte0 end_step=30 best_step=27
8979 23:16:35.711678 Byte1 end_step=30 best_step=27
8980 23:16:35.715123 Byte0 TX OE(2T, 0.5T) = (3, 3)
8981 23:16:35.718887 Byte1 TX OE(2T, 0.5T) = (3, 3)
8982 23:16:35.718969
8983 23:16:35.719032
8984 23:16:35.725056 [DQSOSCAuto] RK1, (LSB)MR18= 0x2107, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
8985 23:16:35.728322 CH1 RK1: MR19=303, MR18=2107
8986 23:16:35.735214 CH1_RK1: MR19=0x303, MR18=0x2107, DQSOSC=393, MR23=63, INC=23, DEC=15
8987 23:16:35.738280 [RxdqsGatingPostProcess] freq 1600
8988 23:16:35.741993 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8989 23:16:35.745008 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 23:16:35.748521 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 23:16:35.751764 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 23:16:35.755128 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 23:16:35.758475 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 23:16:35.761566 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 23:16:35.765092 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 23:16:35.768297 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 23:16:35.771686 Pre-setting of DQS Precalculation
8998 23:16:35.774895 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8999 23:16:35.782186 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9000 23:16:35.791495 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9001 23:16:35.791578
9002 23:16:35.791642
9003 23:16:35.794944 [Calibration Summary] 3200 Mbps
9004 23:16:35.795024 CH 0, Rank 0
9005 23:16:35.798402 SW Impedance : PASS
9006 23:16:35.798483 DUTY Scan : NO K
9007 23:16:35.801479 ZQ Calibration : PASS
9008 23:16:35.804756 Jitter Meter : NO K
9009 23:16:35.804836 CBT Training : PASS
9010 23:16:35.808094 Write leveling : PASS
9011 23:16:35.808175 RX DQS gating : PASS
9012 23:16:35.811540 RX DQ/DQS(RDDQC) : PASS
9013 23:16:35.814919 TX DQ/DQS : PASS
9014 23:16:35.815001 RX DATLAT : PASS
9015 23:16:35.818322 RX DQ/DQS(Engine): PASS
9016 23:16:35.821600 TX OE : PASS
9017 23:16:35.821694 All Pass.
9018 23:16:35.821759
9019 23:16:35.821817 CH 0, Rank 1
9020 23:16:35.824798 SW Impedance : PASS
9021 23:16:35.827964 DUTY Scan : NO K
9022 23:16:35.828045 ZQ Calibration : PASS
9023 23:16:35.831420 Jitter Meter : NO K
9024 23:16:35.835014 CBT Training : PASS
9025 23:16:35.835094 Write leveling : PASS
9026 23:16:35.838660 RX DQS gating : PASS
9027 23:16:35.841807 RX DQ/DQS(RDDQC) : PASS
9028 23:16:35.841888 TX DQ/DQS : PASS
9029 23:16:35.844942 RX DATLAT : PASS
9030 23:16:35.848363 RX DQ/DQS(Engine): PASS
9031 23:16:35.848444 TX OE : PASS
9032 23:16:35.848508 All Pass.
9033 23:16:35.848568
9034 23:16:35.851401 CH 1, Rank 0
9035 23:16:35.851482 SW Impedance : PASS
9036 23:16:35.854571 DUTY Scan : NO K
9037 23:16:35.857995 ZQ Calibration : PASS
9038 23:16:35.858077 Jitter Meter : NO K
9039 23:16:35.861702 CBT Training : PASS
9040 23:16:35.864712 Write leveling : PASS
9041 23:16:35.864793 RX DQS gating : PASS
9042 23:16:35.868011 RX DQ/DQS(RDDQC) : PASS
9043 23:16:35.871468 TX DQ/DQS : PASS
9044 23:16:35.871549 RX DATLAT : PASS
9045 23:16:35.874760 RX DQ/DQS(Engine): PASS
9046 23:16:35.878160 TX OE : PASS
9047 23:16:35.878241 All Pass.
9048 23:16:35.878305
9049 23:16:35.878365 CH 1, Rank 1
9050 23:16:35.881584 SW Impedance : PASS
9051 23:16:35.884879 DUTY Scan : NO K
9052 23:16:35.884960 ZQ Calibration : PASS
9053 23:16:35.887737 Jitter Meter : NO K
9054 23:16:35.891012 CBT Training : PASS
9055 23:16:35.891093 Write leveling : PASS
9056 23:16:35.894334 RX DQS gating : PASS
9057 23:16:35.898141 RX DQ/DQS(RDDQC) : PASS
9058 23:16:35.898222 TX DQ/DQS : PASS
9059 23:16:35.901036 RX DATLAT : PASS
9060 23:16:35.904652 RX DQ/DQS(Engine): PASS
9061 23:16:35.904732 TX OE : PASS
9062 23:16:35.904797 All Pass.
9063 23:16:35.904857
9064 23:16:35.908009 DramC Write-DBI on
9065 23:16:35.911464 PER_BANK_REFRESH: Hybrid Mode
9066 23:16:35.911538 TX_TRACKING: ON
9067 23:16:35.920922 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9068 23:16:35.927972 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9069 23:16:35.937770 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 23:16:35.941536 [FAST_K] Save calibration result to emmc
9071 23:16:35.941627 sync common calibartion params.
9072 23:16:35.944264 sync cbt_mode0:1, 1:1
9073 23:16:35.947502 dram_init: ddr_geometry: 2
9074 23:16:35.950748 dram_init: ddr_geometry: 2
9075 23:16:35.950829 dram_init: ddr_geometry: 2
9076 23:16:35.954211 0:dram_rank_size:100000000
9077 23:16:35.957389 1:dram_rank_size:100000000
9078 23:16:35.961631 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9079 23:16:35.963981 DFS_SHUFFLE_HW_MODE: ON
9080 23:16:35.967639 dramc_set_vcore_voltage set vcore to 725000
9081 23:16:35.971006 Read voltage for 1600, 0
9082 23:16:35.971087 Vio18 = 0
9083 23:16:35.973998 Vcore = 725000
9084 23:16:35.974078 Vdram = 0
9085 23:16:35.974141 Vddq = 0
9086 23:16:35.974200 Vmddr = 0
9087 23:16:35.977397 switch to 3200 Mbps bootup
9088 23:16:35.980586 [DramcRunTimeConfig]
9089 23:16:35.980666 PHYPLL
9090 23:16:35.983872 DPM_CONTROL_AFTERK: ON
9091 23:16:35.983953 PER_BANK_REFRESH: ON
9092 23:16:35.987313 REFRESH_OVERHEAD_REDUCTION: ON
9093 23:16:35.990756 CMD_PICG_NEW_MODE: OFF
9094 23:16:35.990850 XRTWTW_NEW_MODE: ON
9095 23:16:35.994024 XRTRTR_NEW_MODE: ON
9096 23:16:35.994104 TX_TRACKING: ON
9097 23:16:35.997168 RDSEL_TRACKING: OFF
9098 23:16:36.000674 DQS Precalculation for DVFS: ON
9099 23:16:36.000755 RX_TRACKING: OFF
9100 23:16:36.003775 HW_GATING DBG: ON
9101 23:16:36.003856 ZQCS_ENABLE_LP4: ON
9102 23:16:36.007121 RX_PICG_NEW_MODE: ON
9103 23:16:36.007202 TX_PICG_NEW_MODE: ON
9104 23:16:36.010562 ENABLE_RX_DCM_DPHY: ON
9105 23:16:36.013903 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9106 23:16:36.017400 DUMMY_READ_FOR_TRACKING: OFF
9107 23:16:36.017500 !!! SPM_CONTROL_AFTERK: OFF
9108 23:16:36.020336 !!! SPM could not control APHY
9109 23:16:36.023696 IMPEDANCE_TRACKING: ON
9110 23:16:36.023765 TEMP_SENSOR: ON
9111 23:16:36.027116 HW_SAVE_FOR_SR: OFF
9112 23:16:36.030609 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9113 23:16:36.033808 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9114 23:16:36.033881 Read ODT Tracking: ON
9115 23:16:36.037250 Refresh Rate DeBounce: ON
9116 23:16:36.040527 DFS_NO_QUEUE_FLUSH: ON
9117 23:16:36.043692 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9118 23:16:36.043777 ENABLE_DFS_RUNTIME_MRW: OFF
9119 23:16:36.047140 DDR_RESERVE_NEW_MODE: ON
9120 23:16:36.050177 MR_CBT_SWITCH_FREQ: ON
9121 23:16:36.050276 =========================
9122 23:16:36.070406 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9123 23:16:36.073969 dram_init: ddr_geometry: 2
9124 23:16:36.092194 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9125 23:16:36.095688 dram_init: dram init end (result: 0)
9126 23:16:36.101874 DRAM-K: Full calibration passed in 24428 msecs
9127 23:16:36.105468 MRC: failed to locate region type 0.
9128 23:16:36.105588 DRAM rank0 size:0x100000000,
9129 23:16:36.108849 DRAM rank1 size=0x100000000
9130 23:16:36.118765 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9131 23:16:36.125514 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9132 23:16:36.132151 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9133 23:16:36.138744 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9134 23:16:36.141574 DRAM rank0 size:0x100000000,
9135 23:16:36.144922 DRAM rank1 size=0x100000000
9136 23:16:36.145002 CBMEM:
9137 23:16:36.148295 IMD: root @ 0xfffff000 254 entries.
9138 23:16:36.151499 IMD: root @ 0xffffec00 62 entries.
9139 23:16:36.155063 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9140 23:16:36.158248 WARNING: RO_VPD is uninitialized or empty.
9141 23:16:36.165005 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9142 23:16:36.171960 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9143 23:16:36.185067 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9144 23:16:36.196335 BS: romstage times (exec / console): total (unknown) / 23966 ms
9145 23:16:36.196417
9146 23:16:36.196481
9147 23:16:36.206060 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9148 23:16:36.209809 ARM64: Exception handlers installed.
9149 23:16:36.212541 ARM64: Testing exception
9150 23:16:36.216241 ARM64: Done test exception
9151 23:16:36.216322 Enumerating buses...
9152 23:16:36.219278 Show all devs... Before device enumeration.
9153 23:16:36.222749 Root Device: enabled 1
9154 23:16:36.226466 CPU_CLUSTER: 0: enabled 1
9155 23:16:36.226545 CPU: 00: enabled 1
9156 23:16:36.229545 Compare with tree...
9157 23:16:36.229672 Root Device: enabled 1
9158 23:16:36.232958 CPU_CLUSTER: 0: enabled 1
9159 23:16:36.236237 CPU: 00: enabled 1
9160 23:16:36.236316 Root Device scanning...
9161 23:16:36.239602 scan_static_bus for Root Device
9162 23:16:36.242813 CPU_CLUSTER: 0 enabled
9163 23:16:36.245914 scan_static_bus for Root Device done
9164 23:16:36.249097 scan_bus: bus Root Device finished in 8 msecs
9165 23:16:36.249196 done
9166 23:16:36.256051 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9167 23:16:36.259434 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9168 23:16:36.266194 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9169 23:16:36.269423 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9170 23:16:36.272950 Allocating resources...
9171 23:16:36.273047 Reading resources...
9172 23:16:36.279391 Root Device read_resources bus 0 link: 0
9173 23:16:36.279491 DRAM rank0 size:0x100000000,
9174 23:16:36.282878 DRAM rank1 size=0x100000000
9175 23:16:36.286172 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9176 23:16:36.289493 CPU: 00 missing read_resources
9177 23:16:36.292406 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9178 23:16:36.299018 Root Device read_resources bus 0 link: 0 done
9179 23:16:36.299100 Done reading resources.
9180 23:16:36.305694 Show resources in subtree (Root Device)...After reading.
9181 23:16:36.309459 Root Device child on link 0 CPU_CLUSTER: 0
9182 23:16:36.312810 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 23:16:36.322808 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 23:16:36.322890 CPU: 00
9185 23:16:36.325551 Root Device assign_resources, bus 0 link: 0
9186 23:16:36.329358 CPU_CLUSTER: 0 missing set_resources
9187 23:16:36.332415 Root Device assign_resources, bus 0 link: 0 done
9188 23:16:36.335718 Done setting resources.
9189 23:16:36.342336 Show resources in subtree (Root Device)...After assigning values.
9190 23:16:36.345975 Root Device child on link 0 CPU_CLUSTER: 0
9191 23:16:36.348912 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 23:16:36.358852 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 23:16:36.358955 CPU: 00
9194 23:16:36.362203 Done allocating resources.
9195 23:16:36.365564 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9196 23:16:36.368952 Enabling resources...
9197 23:16:36.369046 done.
9198 23:16:36.375676 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9199 23:16:36.375774 Initializing devices...
9200 23:16:36.378927 Root Device init
9201 23:16:36.378997 init hardware done!
9202 23:16:36.382323 0x00000018: ctrlr->caps
9203 23:16:36.385375 52.000 MHz: ctrlr->f_max
9204 23:16:36.385466 0.400 MHz: ctrlr->f_min
9205 23:16:36.388736 0x40ff8080: ctrlr->voltages
9206 23:16:36.388833 sclk: 390625
9207 23:16:36.392034 Bus Width = 1
9208 23:16:36.392105 sclk: 390625
9209 23:16:36.395128 Bus Width = 1
9210 23:16:36.395198 Early init status = 3
9211 23:16:36.401819 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9212 23:16:36.405340 in-header: 03 fc 00 00 01 00 00 00
9213 23:16:36.405439 in-data: 00
9214 23:16:36.411970 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9215 23:16:36.415040 in-header: 03 fd 00 00 00 00 00 00
9216 23:16:36.418330 in-data:
9217 23:16:36.421727 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9218 23:16:36.424965 in-header: 03 fc 00 00 01 00 00 00
9219 23:16:36.428563 in-data: 00
9220 23:16:36.431838 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9221 23:16:36.436224 in-header: 03 fd 00 00 00 00 00 00
9222 23:16:36.439351 in-data:
9223 23:16:36.442868 [SSUSB] Setting up USB HOST controller...
9224 23:16:36.445790 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9225 23:16:36.449572 [SSUSB] phy power-on done.
9226 23:16:36.452933 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9227 23:16:36.459576 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9228 23:16:36.462657 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9229 23:16:36.469121 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9230 23:16:36.475705 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9231 23:16:36.482783 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9232 23:16:36.488901 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9233 23:16:36.496150 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9234 23:16:36.499443 SPM: binary array size = 0x9dc
9235 23:16:36.502624 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9236 23:16:36.508961 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9237 23:16:36.515608 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9238 23:16:36.522166 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9239 23:16:36.525479 configure_display: Starting display init
9240 23:16:36.559510 anx7625_power_on_init: Init interface.
9241 23:16:36.562772 anx7625_disable_pd_protocol: Disabled PD feature.
9242 23:16:36.565744 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9243 23:16:36.593961 anx7625_start_dp_work: Secure OCM version=00
9244 23:16:36.596950 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9245 23:16:36.611788 sp_tx_get_edid_block: EDID Block = 1
9246 23:16:36.714978 Extracted contents:
9247 23:16:36.717709 header: 00 ff ff ff ff ff ff 00
9248 23:16:36.720945 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9249 23:16:36.724507 version: 01 04
9250 23:16:36.728108 basic params: 95 1f 11 78 0a
9251 23:16:36.731112 chroma info: 76 90 94 55 54 90 27 21 50 54
9252 23:16:36.734465 established: 00 00 00
9253 23:16:36.741129 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9254 23:16:36.744607 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9255 23:16:36.751120 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9256 23:16:36.757439 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9257 23:16:36.764195 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9258 23:16:36.767541 extensions: 00
9259 23:16:36.767620 checksum: fb
9260 23:16:36.767684
9261 23:16:36.770913 Manufacturer: IVO Model 57d Serial Number 0
9262 23:16:36.774416 Made week 0 of 2020
9263 23:16:36.774495 EDID version: 1.4
9264 23:16:36.777842 Digital display
9265 23:16:36.781164 6 bits per primary color channel
9266 23:16:36.781250 DisplayPort interface
9267 23:16:36.784400 Maximum image size: 31 cm x 17 cm
9268 23:16:36.787617 Gamma: 220%
9269 23:16:36.787689 Check DPMS levels
9270 23:16:36.791402 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9271 23:16:36.793894 First detailed timing is preferred timing
9272 23:16:36.797709 Established timings supported:
9273 23:16:36.800859 Standard timings supported:
9274 23:16:36.804101 Detailed timings
9275 23:16:36.807200 Hex of detail: 383680a07038204018303c0035ae10000019
9276 23:16:36.810559 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9277 23:16:36.817498 0780 0798 07c8 0820 hborder 0
9278 23:16:36.820723 0438 043b 0447 0458 vborder 0
9279 23:16:36.823827 -hsync -vsync
9280 23:16:36.823925 Did detailed timing
9281 23:16:36.827793 Hex of detail: 000000000000000000000000000000000000
9282 23:16:36.830673 Manufacturer-specified data, tag 0
9283 23:16:36.837389 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9284 23:16:36.837463 ASCII string: InfoVision
9285 23:16:36.844127 Hex of detail: 000000fe00523134304e574635205248200a
9286 23:16:36.847606 ASCII string: R140NWF5 RH
9287 23:16:36.847675 Checksum
9288 23:16:36.847741 Checksum: 0xfb (valid)
9289 23:16:36.853974 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9290 23:16:36.857298 DSI data_rate: 832800000 bps
9291 23:16:36.860621 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9292 23:16:36.867116 anx7625_parse_edid: pixelclock(138800).
9293 23:16:36.870759 hactive(1920), hsync(48), hfp(24), hbp(88)
9294 23:16:36.873669 vactive(1080), vsync(12), vfp(3), vbp(17)
9295 23:16:36.877439 anx7625_dsi_config: config dsi.
9296 23:16:36.883918 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9297 23:16:36.896676 anx7625_dsi_config: success to config DSI
9298 23:16:36.899769 anx7625_dp_start: MIPI phy setup OK.
9299 23:16:36.903026 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9300 23:16:36.906503 mtk_ddp_mode_set invalid vrefresh 60
9301 23:16:36.910001 main_disp_path_setup
9302 23:16:36.910099 ovl_layer_smi_id_en
9303 23:16:36.913329 ovl_layer_smi_id_en
9304 23:16:36.913428 ccorr_config
9305 23:16:36.913518 aal_config
9306 23:16:36.916491 gamma_config
9307 23:16:36.916592 postmask_config
9308 23:16:36.920052 dither_config
9309 23:16:36.923413 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9310 23:16:36.929751 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9311 23:16:36.933298 Root Device init finished in 551 msecs
9312 23:16:36.933394 CPU_CLUSTER: 0 init
9313 23:16:36.943528 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9314 23:16:36.946495 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9315 23:16:36.949856 APU_MBOX 0x190000b0 = 0x10001
9316 23:16:36.953659 APU_MBOX 0x190001b0 = 0x10001
9317 23:16:36.956415 APU_MBOX 0x190005b0 = 0x10001
9318 23:16:36.959877 APU_MBOX 0x190006b0 = 0x10001
9319 23:16:36.963390 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9320 23:16:36.975690 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9321 23:16:36.987929 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9322 23:16:36.994600 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9323 23:16:37.006032 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9324 23:16:37.015583 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9325 23:16:37.019093 CPU_CLUSTER: 0 init finished in 81 msecs
9326 23:16:37.022213 Devices initialized
9327 23:16:37.025189 Show all devs... After init.
9328 23:16:37.025289 Root Device: enabled 1
9329 23:16:37.028298 CPU_CLUSTER: 0: enabled 1
9330 23:16:37.031818 CPU: 00: enabled 1
9331 23:16:37.035076 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9332 23:16:37.038545 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9333 23:16:37.041778 ELOG: NV offset 0x57f000 size 0x1000
9334 23:16:37.048675 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9335 23:16:37.054959 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9336 23:16:37.058278 ELOG: Event(17) added with size 13 at 2023-12-03 23:14:22 UTC
9337 23:16:37.065057 out: cmd=0x121: 03 db 21 01 00 00 00 00
9338 23:16:37.068210 in-header: 03 f9 00 00 2c 00 00 00
9339 23:16:37.078409 in-data: 66 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 23:16:37.084964 ELOG: Event(A1) added with size 10 at 2023-12-03 23:14:22 UTC
9341 23:16:37.091570 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9342 23:16:37.098376 ELOG: Event(A0) added with size 9 at 2023-12-03 23:14:22 UTC
9343 23:16:37.101192 elog_add_boot_reason: Logged dev mode boot
9344 23:16:37.107788 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9345 23:16:37.107891 Finalize devices...
9346 23:16:37.111111 Devices finalized
9347 23:16:37.115016 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9348 23:16:37.117953 Writing coreboot table at 0xffe64000
9349 23:16:37.121272 0. 000000000010a000-0000000000113fff: RAMSTAGE
9350 23:16:37.124302 1. 0000000040000000-00000000400fffff: RAM
9351 23:16:37.131269 2. 0000000040100000-000000004032afff: RAMSTAGE
9352 23:16:37.134227 3. 000000004032b000-00000000545fffff: RAM
9353 23:16:37.137685 4. 0000000054600000-000000005465ffff: BL31
9354 23:16:37.141315 5. 0000000054660000-00000000ffe63fff: RAM
9355 23:16:37.147337 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9356 23:16:37.151208 7. 0000000100000000-000000023fffffff: RAM
9357 23:16:37.154117 Passing 5 GPIOs to payload:
9358 23:16:37.157358 NAME | PORT | POLARITY | VALUE
9359 23:16:37.164148 EC in RW | 0x000000aa | low | undefined
9360 23:16:37.167348 EC interrupt | 0x00000005 | low | undefined
9361 23:16:37.170996 TPM interrupt | 0x000000ab | high | undefined
9362 23:16:37.177512 SD card detect | 0x00000011 | high | undefined
9363 23:16:37.180948 speaker enable | 0x00000093 | high | undefined
9364 23:16:37.184127 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9365 23:16:37.187557 in-header: 03 f9 00 00 02 00 00 00
9366 23:16:37.190928 in-data: 02 00
9367 23:16:37.194073 ADC[4]: Raw value=904726 ID=7
9368 23:16:37.194147 ADC[3]: Raw value=213810 ID=1
9369 23:16:37.197533 RAM Code: 0x71
9370 23:16:37.200305 ADC[6]: Raw value=75701 ID=0
9371 23:16:37.200400 ADC[5]: Raw value=213072 ID=1
9372 23:16:37.203689 SKU Code: 0x1
9373 23:16:37.207068 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9374 23:16:37.210845 coreboot table: 964 bytes.
9375 23:16:37.214089 IMD ROOT 0. 0xfffff000 0x00001000
9376 23:16:37.216950 IMD SMALL 1. 0xffffe000 0x00001000
9377 23:16:37.220346 RO MCACHE 2. 0xffffc000 0x00001104
9378 23:16:37.224034 CONSOLE 3. 0xfff7c000 0x00080000
9379 23:16:37.227360 FMAP 4. 0xfff7b000 0x00000452
9380 23:16:37.230547 TIME STAMP 5. 0xfff7a000 0x00000910
9381 23:16:37.234087 VBOOT WORK 6. 0xfff66000 0x00014000
9382 23:16:37.237378 RAMOOPS 7. 0xffe66000 0x00100000
9383 23:16:37.240432 COREBOOT 8. 0xffe64000 0x00002000
9384 23:16:37.243528 IMD small region:
9385 23:16:37.247052 IMD ROOT 0. 0xffffec00 0x00000400
9386 23:16:37.250673 VPD 1. 0xffffeb80 0x0000006c
9387 23:16:37.253800 MMC STATUS 2. 0xffffeb60 0x00000004
9388 23:16:37.257062 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9389 23:16:37.260248 Probing TPM: done!
9390 23:16:37.264455 Connected to device vid:did:rid of 1ae0:0028:00
9391 23:16:37.274034 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9392 23:16:37.277436 Initialized TPM device CR50 revision 0
9393 23:16:37.281519 Checking cr50 for pending updates
9394 23:16:37.285171 Reading cr50 TPM mode
9395 23:16:37.294388 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9396 23:16:37.300587 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9397 23:16:37.340717 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9398 23:16:37.343675 Checking segment from ROM address 0x40100000
9399 23:16:37.346993 Checking segment from ROM address 0x4010001c
9400 23:16:37.353990 Loading segment from ROM address 0x40100000
9401 23:16:37.354068 code (compression=0)
9402 23:16:37.363652 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9403 23:16:37.370410 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9404 23:16:37.370488 it's not compressed!
9405 23:16:37.377463 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9406 23:16:37.380991 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9407 23:16:37.400780 Loading segment from ROM address 0x4010001c
9408 23:16:37.400864 Entry Point 0x80000000
9409 23:16:37.404442 Loaded segments
9410 23:16:37.407792 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9411 23:16:37.414186 Jumping to boot code at 0x80000000(0xffe64000)
9412 23:16:37.420860 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9413 23:16:37.427498 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9414 23:16:37.435873 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9415 23:16:37.438761 Checking segment from ROM address 0x40100000
9416 23:16:37.442052 Checking segment from ROM address 0x4010001c
9417 23:16:37.445250 Loading segment from ROM address 0x40100000
9418 23:16:37.448840 code (compression=1)
9419 23:16:37.455589 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9420 23:16:37.465245 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9421 23:16:37.465347 using LZMA
9422 23:16:37.473477 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9423 23:16:37.480224 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9424 23:16:37.483739 Loading segment from ROM address 0x4010001c
9425 23:16:37.483814 Entry Point 0x54601000
9426 23:16:37.486959 Loaded segments
9427 23:16:37.490532 NOTICE: MT8192 bl31_setup
9428 23:16:37.497608 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9429 23:16:37.500850 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9430 23:16:37.506922 WARNING: region 0:
9431 23:16:37.507331 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 23:16:37.507420 WARNING: region 1:
9433 23:16:37.514121 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9434 23:16:37.514202 WARNING: region 2:
9435 23:16:37.520991 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9436 23:16:37.524502 WARNING: region 3:
9437 23:16:37.527709 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 23:16:37.531175 WARNING: region 4:
9439 23:16:37.534493 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 23:16:37.537484 WARNING: region 5:
9441 23:16:37.540816 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 23:16:37.544665 WARNING: region 6:
9443 23:16:37.547607 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 23:16:37.547683 WARNING: region 7:
9445 23:16:37.554004 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 23:16:37.560559 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9447 23:16:37.564554 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9448 23:16:37.567477 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9449 23:16:37.573972 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9450 23:16:37.577809 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9451 23:16:37.580730 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9452 23:16:37.587187 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9453 23:16:37.590800 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9454 23:16:37.594075 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9455 23:16:37.600976 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9456 23:16:37.604213 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9457 23:16:37.610565 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9458 23:16:37.613896 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9459 23:16:37.617775 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9460 23:16:37.624055 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9461 23:16:37.627611 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9462 23:16:37.630682 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9463 23:16:37.637824 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9464 23:16:37.640677 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9465 23:16:37.644074 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9466 23:16:37.651380 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9467 23:16:37.654246 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9468 23:16:37.661365 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9469 23:16:37.664184 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9470 23:16:37.667462 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9471 23:16:37.674376 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9472 23:16:37.678060 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9473 23:16:37.684166 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9474 23:16:37.687761 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9475 23:16:37.691359 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9476 23:16:37.697716 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9477 23:16:37.701074 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9478 23:16:37.704185 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9479 23:16:37.711234 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9480 23:16:37.714266 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9481 23:16:37.717694 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9482 23:16:37.720946 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9483 23:16:37.727655 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9484 23:16:37.731124 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9485 23:16:37.734519 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9486 23:16:37.737583 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9487 23:16:37.744516 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9488 23:16:37.747616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9489 23:16:37.751012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9490 23:16:37.754268 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9491 23:16:37.760918 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9492 23:16:37.764017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9493 23:16:37.767430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9494 23:16:37.774155 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9495 23:16:37.777331 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9496 23:16:37.781261 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9497 23:16:37.787680 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9498 23:16:37.790901 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9499 23:16:37.797723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9500 23:16:37.801017 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9501 23:16:37.807836 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9502 23:16:37.811024 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9503 23:16:37.814443 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9504 23:16:37.821059 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9505 23:16:37.824324 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9506 23:16:37.830814 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9507 23:16:37.834585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9508 23:16:37.840827 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9509 23:16:37.844074 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9510 23:16:37.850831 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9511 23:16:37.854152 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9512 23:16:37.857870 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9513 23:16:37.864220 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9514 23:16:37.867631 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9515 23:16:37.874513 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9516 23:16:37.877444 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9517 23:16:37.880852 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9518 23:16:37.887814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9519 23:16:37.891436 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9520 23:16:37.897221 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9521 23:16:37.900793 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9522 23:16:37.907499 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9523 23:16:37.910865 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9524 23:16:37.917938 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9525 23:16:37.920797 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9526 23:16:37.924507 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9527 23:16:37.931016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9528 23:16:37.934086 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9529 23:16:37.941340 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9530 23:16:37.943960 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9531 23:16:37.950674 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9532 23:16:37.954636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9533 23:16:37.957394 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9534 23:16:37.964024 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9535 23:16:37.967264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9536 23:16:37.974399 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9537 23:16:37.977691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9538 23:16:37.984315 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9539 23:16:37.987645 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9540 23:16:37.991034 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9541 23:16:37.997502 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9542 23:16:38.001472 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9543 23:16:38.004619 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9544 23:16:38.010856 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9545 23:16:38.014201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9546 23:16:38.017943 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9547 23:16:38.024048 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9548 23:16:38.028099 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9549 23:16:38.030832 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9550 23:16:38.037944 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9551 23:16:38.040794 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9552 23:16:38.047386 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9553 23:16:38.050879 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9554 23:16:38.054211 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9555 23:16:38.060496 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9556 23:16:38.064029 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9557 23:16:38.070863 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9558 23:16:38.073997 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9559 23:16:38.077930 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9560 23:16:38.084288 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9561 23:16:38.087554 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9562 23:16:38.090779 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9563 23:16:38.097537 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9564 23:16:38.100950 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9565 23:16:38.104055 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9566 23:16:38.107588 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9567 23:16:38.114127 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9568 23:16:38.117672 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9569 23:16:38.121007 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9570 23:16:38.127447 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9571 23:16:38.130798 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9572 23:16:38.134378 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9573 23:16:38.140499 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9574 23:16:38.144031 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9575 23:16:38.151210 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9576 23:16:38.154198 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9577 23:16:38.157288 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9578 23:16:38.164188 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9579 23:16:38.167496 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9580 23:16:38.173952 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9581 23:16:38.177283 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9582 23:16:38.180612 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9583 23:16:38.187443 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9584 23:16:38.190684 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9585 23:16:38.193879 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9586 23:16:38.200486 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9587 23:16:38.204204 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9588 23:16:38.210470 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9589 23:16:38.213983 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9590 23:16:38.217260 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9591 23:16:38.223794 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9592 23:16:38.227096 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9593 23:16:38.233969 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9594 23:16:38.237409 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9595 23:16:38.240417 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9596 23:16:38.247181 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9597 23:16:38.250820 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9598 23:16:38.253803 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9599 23:16:38.260710 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9600 23:16:38.264030 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9601 23:16:38.270656 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9602 23:16:38.274011 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9603 23:16:38.277393 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9604 23:16:38.284308 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9605 23:16:38.287604 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9606 23:16:38.291075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9607 23:16:38.297394 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9608 23:16:38.300653 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9609 23:16:38.307496 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9610 23:16:38.310597 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9611 23:16:38.314128 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9612 23:16:38.320544 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9613 23:16:38.323802 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9614 23:16:38.330756 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9615 23:16:38.333740 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9616 23:16:38.337222 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9617 23:16:38.344043 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9618 23:16:38.347215 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9619 23:16:38.353706 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9620 23:16:38.357190 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9621 23:16:38.360724 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9622 23:16:38.367342 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9623 23:16:38.370713 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9624 23:16:38.377484 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9625 23:16:38.380616 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9626 23:16:38.383610 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9627 23:16:38.390216 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9628 23:16:38.393698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9629 23:16:38.400407 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9630 23:16:38.403301 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9631 23:16:38.406702 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9632 23:16:38.413357 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9633 23:16:38.417018 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9634 23:16:38.420219 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9635 23:16:38.426716 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9636 23:16:38.430185 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9637 23:16:38.436777 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9638 23:16:38.440354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9639 23:16:38.446440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9640 23:16:38.450169 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9641 23:16:38.453193 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9642 23:16:38.460159 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9643 23:16:38.463215 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9644 23:16:38.470074 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9645 23:16:38.473278 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9646 23:16:38.476371 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9647 23:16:38.483183 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9648 23:16:38.486650 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9649 23:16:38.493139 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9650 23:16:38.496486 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9651 23:16:38.502750 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9652 23:16:38.506141 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9653 23:16:38.509455 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9654 23:16:38.516003 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9655 23:16:38.519522 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9656 23:16:38.526606 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9657 23:16:38.529488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9658 23:16:38.536291 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9659 23:16:38.539343 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9660 23:16:38.542832 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9661 23:16:38.549432 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9662 23:16:38.552893 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9663 23:16:38.559232 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9664 23:16:38.562915 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9665 23:16:38.565805 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9666 23:16:38.573074 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9667 23:16:38.576063 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9668 23:16:38.582509 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9669 23:16:38.585800 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9670 23:16:38.592537 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9671 23:16:38.595611 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9672 23:16:38.599765 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9673 23:16:38.605843 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9674 23:16:38.608930 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9675 23:16:38.612472 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9676 23:16:38.619136 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9677 23:16:38.622311 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9678 23:16:38.625695 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9679 23:16:38.628999 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9680 23:16:38.635818 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9681 23:16:38.639219 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9682 23:16:38.645321 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9683 23:16:38.648910 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9684 23:16:38.652011 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9685 23:16:38.658852 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9686 23:16:38.662223 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9687 23:16:38.665579 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9688 23:16:38.671883 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9689 23:16:38.675390 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9690 23:16:38.678744 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9691 23:16:38.685911 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9692 23:16:38.688793 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9693 23:16:38.695562 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9694 23:16:38.699150 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9695 23:16:38.701885 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9696 23:16:38.708717 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9697 23:16:38.712344 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9698 23:16:38.715402 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9699 23:16:38.722019 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9700 23:16:38.725714 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9701 23:16:38.728946 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9702 23:16:38.735217 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9703 23:16:38.738730 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9704 23:16:38.742213 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9705 23:16:38.748319 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9706 23:16:38.751653 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9707 23:16:38.758733 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9708 23:16:38.761672 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9709 23:16:38.765185 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9710 23:16:38.771965 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9711 23:16:38.774744 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9712 23:16:38.778722 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9713 23:16:38.784896 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9714 23:16:38.788649 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9715 23:16:38.791702 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9716 23:16:38.798199 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9717 23:16:38.801917 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9718 23:16:38.805040 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9719 23:16:38.808339 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9720 23:16:38.811639 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9721 23:16:38.818160 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9722 23:16:38.821693 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9723 23:16:38.824786 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9724 23:16:38.828142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9725 23:16:38.834746 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9726 23:16:38.838551 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9727 23:16:38.841430 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9728 23:16:38.848065 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9729 23:16:38.851330 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9730 23:16:38.858164 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9731 23:16:38.861470 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9732 23:16:38.864725 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9733 23:16:38.871275 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9734 23:16:38.874667 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9735 23:16:38.881631 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9736 23:16:38.884939 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9737 23:16:38.888224 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9738 23:16:38.894863 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9739 23:16:38.897985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9740 23:16:38.904477 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9741 23:16:38.908207 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9742 23:16:38.914461 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9743 23:16:38.917920 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9744 23:16:38.921269 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9745 23:16:38.927904 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9746 23:16:38.931680 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9747 23:16:38.937989 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9748 23:16:38.941066 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9749 23:16:38.944290 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9750 23:16:38.951419 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9751 23:16:38.954829 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9752 23:16:38.958223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9753 23:16:38.964722 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9754 23:16:38.967740 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9755 23:16:38.974276 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9756 23:16:38.977764 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9757 23:16:38.984377 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9758 23:16:38.987948 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9759 23:16:38.990839 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9760 23:16:38.997750 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9761 23:16:39.001187 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9762 23:16:39.007642 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9763 23:16:39.010936 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9764 23:16:39.014261 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9765 23:16:39.021144 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9766 23:16:39.024415 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9767 23:16:39.030835 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9768 23:16:39.034113 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9769 23:16:39.037244 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9770 23:16:39.043991 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9771 23:16:39.047439 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9772 23:16:39.053882 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9773 23:16:39.057529 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9774 23:16:39.063808 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9775 23:16:39.067208 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9776 23:16:39.070840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9777 23:16:39.077310 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9778 23:16:39.080616 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9779 23:16:39.087450 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9780 23:16:39.090441 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9781 23:16:39.093797 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9782 23:16:39.100284 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9783 23:16:39.103956 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9784 23:16:39.110470 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9785 23:16:39.114048 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9786 23:16:39.117167 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9787 23:16:39.123528 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9788 23:16:39.127148 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9789 23:16:39.134142 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9790 23:16:39.136774 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9791 23:16:39.140113 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9792 23:16:39.146983 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9793 23:16:39.149966 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9794 23:16:39.157015 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9795 23:16:39.159955 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9796 23:16:39.167193 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9797 23:16:39.169905 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9798 23:16:39.173445 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9799 23:16:39.179888 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9800 23:16:39.183195 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9801 23:16:39.189755 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9802 23:16:39.193345 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9803 23:16:39.199693 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9804 23:16:39.203507 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9805 23:16:39.206836 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9806 23:16:39.213501 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9807 23:16:39.216661 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9808 23:16:39.223481 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9809 23:16:39.226495 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9810 23:16:39.232807 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9811 23:16:39.236832 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9812 23:16:39.239705 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9813 23:16:39.246476 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9814 23:16:39.249936 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9815 23:16:39.256298 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9816 23:16:39.259479 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9817 23:16:39.266568 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9818 23:16:39.270152 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9819 23:16:39.273073 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9820 23:16:39.279973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9821 23:16:39.283152 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9822 23:16:39.289692 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9823 23:16:39.293392 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9824 23:16:39.300131 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9825 23:16:39.303175 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9826 23:16:39.309307 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9827 23:16:39.312883 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9828 23:16:39.316571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9829 23:16:39.323054 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9830 23:16:39.326367 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9831 23:16:39.333100 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9832 23:16:39.336035 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9833 23:16:39.342859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9834 23:16:39.346757 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9835 23:16:39.353428 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9836 23:16:39.356313 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9837 23:16:39.359652 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9838 23:16:39.366261 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9839 23:16:39.369842 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9840 23:16:39.376746 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9841 23:16:39.379428 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9842 23:16:39.385914 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9843 23:16:39.389640 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9844 23:16:39.392916 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9845 23:16:39.399356 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9846 23:16:39.402706 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9847 23:16:39.409505 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9848 23:16:39.412786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9849 23:16:39.415969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9850 23:16:39.422341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9851 23:16:39.426217 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9852 23:16:39.432200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9853 23:16:39.436108 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9854 23:16:39.442926 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9855 23:16:39.446145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9856 23:16:39.452237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9857 23:16:39.455863 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9858 23:16:39.462878 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9859 23:16:39.465719 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9860 23:16:39.472559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9861 23:16:39.476091 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9862 23:16:39.482153 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9863 23:16:39.485370 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9864 23:16:39.492572 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9865 23:16:39.495358 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9866 23:16:39.502464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9867 23:16:39.505535 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9868 23:16:39.512396 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9869 23:16:39.515447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9870 23:16:39.522191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9871 23:16:39.525629 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9872 23:16:39.532044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9873 23:16:39.535328 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9874 23:16:39.542190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9875 23:16:39.545727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9876 23:16:39.552446 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9877 23:16:39.555890 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9878 23:16:39.562440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9879 23:16:39.565254 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9880 23:16:39.568922 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9881 23:16:39.572191 INFO: [APUAPC] vio 0
9882 23:16:39.575512 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9883 23:16:39.582426 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9884 23:16:39.585597 INFO: [APUAPC] D0_APC_0: 0x400510
9885 23:16:39.588952 INFO: [APUAPC] D0_APC_1: 0x0
9886 23:16:39.592195 INFO: [APUAPC] D0_APC_2: 0x1540
9887 23:16:39.592749 INFO: [APUAPC] D0_APC_3: 0x0
9888 23:16:39.595631 INFO: [APUAPC] D1_APC_0: 0xffffffff
9889 23:16:39.598574 INFO: [APUAPC] D1_APC_1: 0xffffffff
9890 23:16:39.602313 INFO: [APUAPC] D1_APC_2: 0x3fffff
9891 23:16:39.605843 INFO: [APUAPC] D1_APC_3: 0x0
9892 23:16:39.608709 INFO: [APUAPC] D2_APC_0: 0xffffffff
9893 23:16:39.612380 INFO: [APUAPC] D2_APC_1: 0xffffffff
9894 23:16:39.615166 INFO: [APUAPC] D2_APC_2: 0x3fffff
9895 23:16:39.618623 INFO: [APUAPC] D2_APC_3: 0x0
9896 23:16:39.622070 INFO: [APUAPC] D3_APC_0: 0xffffffff
9897 23:16:39.625258 INFO: [APUAPC] D3_APC_1: 0xffffffff
9898 23:16:39.628451 INFO: [APUAPC] D3_APC_2: 0x3fffff
9899 23:16:39.632120 INFO: [APUAPC] D3_APC_3: 0x0
9900 23:16:39.635049 INFO: [APUAPC] D4_APC_0: 0xffffffff
9901 23:16:39.638196 INFO: [APUAPC] D4_APC_1: 0xffffffff
9902 23:16:39.641956 INFO: [APUAPC] D4_APC_2: 0x3fffff
9903 23:16:39.645304 INFO: [APUAPC] D4_APC_3: 0x0
9904 23:16:39.648569 INFO: [APUAPC] D5_APC_0: 0xffffffff
9905 23:16:39.651816 INFO: [APUAPC] D5_APC_1: 0xffffffff
9906 23:16:39.655184 INFO: [APUAPC] D5_APC_2: 0x3fffff
9907 23:16:39.658568 INFO: [APUAPC] D5_APC_3: 0x0
9908 23:16:39.661676 INFO: [APUAPC] D6_APC_0: 0xffffffff
9909 23:16:39.665343 INFO: [APUAPC] D6_APC_1: 0xffffffff
9910 23:16:39.669102 INFO: [APUAPC] D6_APC_2: 0x3fffff
9911 23:16:39.671898 INFO: [APUAPC] D6_APC_3: 0x0
9912 23:16:39.675367 INFO: [APUAPC] D7_APC_0: 0xffffffff
9913 23:16:39.678589 INFO: [APUAPC] D7_APC_1: 0xffffffff
9914 23:16:39.681957 INFO: [APUAPC] D7_APC_2: 0x3fffff
9915 23:16:39.685457 INFO: [APUAPC] D7_APC_3: 0x0
9916 23:16:39.688587 INFO: [APUAPC] D8_APC_0: 0xffffffff
9917 23:16:39.691793 INFO: [APUAPC] D8_APC_1: 0xffffffff
9918 23:16:39.695179 INFO: [APUAPC] D8_APC_2: 0x3fffff
9919 23:16:39.698672 INFO: [APUAPC] D8_APC_3: 0x0
9920 23:16:39.701625 INFO: [APUAPC] D9_APC_0: 0xffffffff
9921 23:16:39.705082 INFO: [APUAPC] D9_APC_1: 0xffffffff
9922 23:16:39.708421 INFO: [APUAPC] D9_APC_2: 0x3fffff
9923 23:16:39.711567 INFO: [APUAPC] D9_APC_3: 0x0
9924 23:16:39.714768 INFO: [APUAPC] D10_APC_0: 0xffffffff
9925 23:16:39.718237 INFO: [APUAPC] D10_APC_1: 0xffffffff
9926 23:16:39.721710 INFO: [APUAPC] D10_APC_2: 0x3fffff
9927 23:16:39.724813 INFO: [APUAPC] D10_APC_3: 0x0
9928 23:16:39.728049 INFO: [APUAPC] D11_APC_0: 0xffffffff
9929 23:16:39.731392 INFO: [APUAPC] D11_APC_1: 0xffffffff
9930 23:16:39.734508 INFO: [APUAPC] D11_APC_2: 0x3fffff
9931 23:16:39.737690 INFO: [APUAPC] D11_APC_3: 0x0
9932 23:16:39.741571 INFO: [APUAPC] D12_APC_0: 0xffffffff
9933 23:16:39.744781 INFO: [APUAPC] D12_APC_1: 0xffffffff
9934 23:16:39.747726 INFO: [APUAPC] D12_APC_2: 0x3fffff
9935 23:16:39.751247 INFO: [APUAPC] D12_APC_3: 0x0
9936 23:16:39.754349 INFO: [APUAPC] D13_APC_0: 0xffffffff
9937 23:16:39.758236 INFO: [APUAPC] D13_APC_1: 0xffffffff
9938 23:16:39.761255 INFO: [APUAPC] D13_APC_2: 0x3fffff
9939 23:16:39.764207 INFO: [APUAPC] D13_APC_3: 0x0
9940 23:16:39.767677 INFO: [APUAPC] D14_APC_0: 0xffffffff
9941 23:16:39.770715 INFO: [APUAPC] D14_APC_1: 0xffffffff
9942 23:16:39.774254 INFO: [APUAPC] D14_APC_2: 0x3fffff
9943 23:16:39.777869 INFO: [APUAPC] D14_APC_3: 0x0
9944 23:16:39.780592 INFO: [APUAPC] D15_APC_0: 0xffffffff
9945 23:16:39.784113 INFO: [APUAPC] D15_APC_1: 0xffffffff
9946 23:16:39.787597 INFO: [APUAPC] D15_APC_2: 0x3fffff
9947 23:16:39.791104 INFO: [APUAPC] D15_APC_3: 0x0
9948 23:16:39.794510 INFO: [APUAPC] APC_CON: 0x4
9949 23:16:39.797470 INFO: [NOCDAPC] D0_APC_0: 0x0
9950 23:16:39.800600 INFO: [NOCDAPC] D0_APC_1: 0x0
9951 23:16:39.804152 INFO: [NOCDAPC] D1_APC_0: 0x0
9952 23:16:39.804716 INFO: [NOCDAPC] D1_APC_1: 0xfff
9953 23:16:39.807398 INFO: [NOCDAPC] D2_APC_0: 0x0
9954 23:16:39.811034 INFO: [NOCDAPC] D2_APC_1: 0xfff
9955 23:16:39.813896 INFO: [NOCDAPC] D3_APC_0: 0x0
9956 23:16:39.817204 INFO: [NOCDAPC] D3_APC_1: 0xfff
9957 23:16:39.820548 INFO: [NOCDAPC] D4_APC_0: 0x0
9958 23:16:39.823998 INFO: [NOCDAPC] D4_APC_1: 0xfff
9959 23:16:39.827007 INFO: [NOCDAPC] D5_APC_0: 0x0
9960 23:16:39.830162 INFO: [NOCDAPC] D5_APC_1: 0xfff
9961 23:16:39.834020 INFO: [NOCDAPC] D6_APC_0: 0x0
9962 23:16:39.836992 INFO: [NOCDAPC] D6_APC_1: 0xfff
9963 23:16:39.837550 INFO: [NOCDAPC] D7_APC_0: 0x0
9964 23:16:39.840078 INFO: [NOCDAPC] D7_APC_1: 0xfff
9965 23:16:39.844018 INFO: [NOCDAPC] D8_APC_0: 0x0
9966 23:16:39.847074 INFO: [NOCDAPC] D8_APC_1: 0xfff
9967 23:16:39.850032 INFO: [NOCDAPC] D9_APC_0: 0x0
9968 23:16:39.853739 INFO: [NOCDAPC] D9_APC_1: 0xfff
9969 23:16:39.857302 INFO: [NOCDAPC] D10_APC_0: 0x0
9970 23:16:39.860455 INFO: [NOCDAPC] D10_APC_1: 0xfff
9971 23:16:39.863628 INFO: [NOCDAPC] D11_APC_0: 0x0
9972 23:16:39.867117 INFO: [NOCDAPC] D11_APC_1: 0xfff
9973 23:16:39.870163 INFO: [NOCDAPC] D12_APC_0: 0x0
9974 23:16:39.873413 INFO: [NOCDAPC] D12_APC_1: 0xfff
9975 23:16:39.876776 INFO: [NOCDAPC] D13_APC_0: 0x0
9976 23:16:39.879961 INFO: [NOCDAPC] D13_APC_1: 0xfff
9977 23:16:39.880418 INFO: [NOCDAPC] D14_APC_0: 0x0
9978 23:16:39.883085 INFO: [NOCDAPC] D14_APC_1: 0xfff
9979 23:16:39.886477 INFO: [NOCDAPC] D15_APC_0: 0x0
9980 23:16:39.889907 INFO: [NOCDAPC] D15_APC_1: 0xfff
9981 23:16:39.893340 INFO: [NOCDAPC] APC_CON: 0x4
9982 23:16:39.896552 INFO: [APUAPC] set_apusys_apc done
9983 23:16:39.899764 INFO: [DEVAPC] devapc_init done
9984 23:16:39.903362 INFO: GICv3 without legacy support detected.
9985 23:16:39.910056 INFO: ARM GICv3 driver initialized in EL3
9986 23:16:39.913616 INFO: Maximum SPI INTID supported: 639
9987 23:16:39.916334 INFO: BL31: Initializing runtime services
9988 23:16:39.923461 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9989 23:16:39.924151 INFO: SPM: enable CPC mode
9990 23:16:39.929566 INFO: mcdi ready for mcusys-off-idle and system suspend
9991 23:16:39.933026 INFO: BL31: Preparing for EL3 exit to normal world
9992 23:16:39.939517 INFO: Entry point address = 0x80000000
9993 23:16:39.939977 INFO: SPSR = 0x8
9994 23:16:39.945926
9995 23:16:39.946376
9996 23:16:39.946728
9997 23:16:39.949355 Starting depthcharge on Spherion...
9998 23:16:39.949869
9999 23:16:39.950233 Wipe memory regions:
10000 23:16:39.950568
10001 23:16:39.953490 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10002 23:16:39.954115 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10003 23:16:39.954564 Setting prompt string to ['asurada:']
10004 23:16:39.954982 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10005 23:16:39.955688 [0x00000040000000, 0x00000054600000)
10006 23:16:40.074891
10007 23:16:40.075440 [0x00000054660000, 0x00000080000000)
10008 23:16:40.335844
10009 23:16:40.336395 [0x000000821a7280, 0x000000ffe64000)
10010 23:16:41.080242
10011 23:16:41.080988 [0x00000100000000, 0x00000240000000)
10012 23:16:42.970233
10013 23:16:42.973338 Initializing XHCI USB controller at 0x11200000.
10014 23:16:44.011564
10015 23:16:44.014592 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10016 23:16:44.015049
10017 23:16:44.015407
10018 23:16:44.015739
10019 23:16:44.016527 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 23:16:44.117801 asurada: tftpboot 192.168.201.1 12172418/tftp-deploy-1y2kapwx/kernel/image.itb 12172418/tftp-deploy-1y2kapwx/kernel/cmdline
10022 23:16:44.118398 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 23:16:44.118954 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10024 23:16:44.124072 tftpboot 192.168.201.1 12172418/tftp-deploy-1y2kapwx/kernel/image.ittp-deploy-1y2kapwx/kernel/cmdline
10025 23:16:44.124636
10026 23:16:44.124998 Waiting for link
10027 23:16:44.284641
10028 23:16:44.285190 R8152: Initializing
10029 23:16:44.285553
10030 23:16:44.287547 Version 9 (ocp_data = 6010)
10031 23:16:44.288030
10032 23:16:44.290790 R8152: Done initializing
10033 23:16:44.291401
10034 23:16:44.291832 Adding net device
10035 23:16:46.159761
10036 23:16:46.160303 done.
10037 23:16:46.160733
10038 23:16:46.161145 MAC: 00:e0:4c:78:7a:aa
10039 23:16:46.161522
10040 23:16:46.162893 Sending DHCP discover... done.
10041 23:16:46.163345
10042 23:16:46.166105 Waiting for reply... done.
10043 23:16:46.166597
10044 23:16:46.169510 Sending DHCP request... done.
10045 23:16:46.170015
10046 23:16:46.170386 Waiting for reply... done.
10047 23:16:46.170735
10048 23:16:46.173352 My ip is 192.168.201.12
10049 23:16:46.173905
10050 23:16:46.176583 The DHCP server ip is 192.168.201.1
10051 23:16:46.177146
10052 23:16:46.179567 TFTP server IP predefined by user: 192.168.201.1
10053 23:16:46.180029
10054 23:16:46.186788 Bootfile predefined by user: 12172418/tftp-deploy-1y2kapwx/kernel/image.itb
10055 23:16:46.187427
10056 23:16:46.189669 Sending tftp read request... done.
10057 23:16:46.190137
10058 23:16:46.193042 Waiting for the transfer...
10059 23:16:46.193522
10060 23:16:46.591643 00000000 ################################################################
10061 23:16:46.592211
10062 23:16:46.893134 00080000 ################################################################
10063 23:16:46.893279
10064 23:16:47.208841 00100000 ################################################################
10065 23:16:47.209011
10066 23:16:47.523384 00180000 ################################################################
10067 23:16:47.523533
10068 23:16:47.838489 00200000 ################################################################
10069 23:16:47.838623
10070 23:16:48.143466 00280000 ################################################################
10071 23:16:48.143608
10072 23:16:48.439434 00300000 ################################################################
10073 23:16:48.439585
10074 23:16:48.713138 00380000 ################################################################
10075 23:16:48.713372
10076 23:16:48.982067 00400000 ################################################################
10077 23:16:48.982193
10078 23:16:49.252453 00480000 ################################################################
10079 23:16:49.252586
10080 23:16:49.534139 00500000 ################################################################
10081 23:16:49.534269
10082 23:16:49.795532 00580000 ################################################################
10083 23:16:49.795674
10084 23:16:50.066212 00600000 ################################################################
10085 23:16:50.066364
10086 23:16:50.340964 00680000 ################################################################
10087 23:16:50.341116
10088 23:16:50.594910 00700000 ################################################################
10089 23:16:50.595065
10090 23:16:50.853354 00780000 ################################################################
10091 23:16:50.853539
10092 23:16:51.124626 00800000 ################################################################
10093 23:16:51.124786
10094 23:16:51.398298 00880000 ################################################################
10095 23:16:51.398441
10096 23:16:51.675475 00900000 ################################################################
10097 23:16:51.675645
10098 23:16:51.963676 00980000 ################################################################
10099 23:16:51.963843
10100 23:16:52.253615 00a00000 ################################################################
10101 23:16:52.253749
10102 23:16:52.527368 00a80000 ################################################################
10103 23:16:52.527502
10104 23:16:52.815354 00b00000 ################################################################
10105 23:16:52.815503
10106 23:16:53.086617 00b80000 ################################################################
10107 23:16:53.086759
10108 23:16:53.387800 00c00000 ################################################################
10109 23:16:53.387932
10110 23:16:53.685719 00c80000 ################################################################
10111 23:16:53.685858
10112 23:16:53.959839 00d00000 ################################################################
10113 23:16:53.960004
10114 23:16:54.254520 00d80000 ################################################################
10115 23:16:54.254663
10116 23:16:54.544134 00e00000 ################################################################
10117 23:16:54.544296
10118 23:16:54.857683 00e80000 ################################################################
10119 23:16:54.857851
10120 23:16:55.136622 00f00000 ################################################################
10121 23:16:55.136752
10122 23:16:55.423489 00f80000 ################################################################
10123 23:16:55.423621
10124 23:16:55.716374 01000000 ################################################################
10125 23:16:55.716506
10126 23:16:56.004624 01080000 ################################################################
10127 23:16:56.004775
10128 23:16:56.298661 01100000 ################################################################
10129 23:16:56.298807
10130 23:16:56.591264 01180000 ################################################################
10131 23:16:56.591405
10132 23:16:56.874960 01200000 ################################################################
10133 23:16:56.875111
10134 23:16:57.164385 01280000 ################################################################
10135 23:16:57.164519
10136 23:16:57.466364 01300000 ################################################################
10137 23:16:57.466507
10138 23:16:57.769149 01380000 ################################################################
10139 23:16:57.769286
10140 23:16:58.053744 01400000 ################################################################
10141 23:16:58.053885
10142 23:16:58.348117 01480000 ################################################################
10143 23:16:58.348255
10144 23:16:58.649368 01500000 ################################################################
10145 23:16:58.649506
10146 23:16:58.946474 01580000 ################################################################
10147 23:16:58.946612
10148 23:16:59.210757 01600000 ################################################################
10149 23:16:59.210902
10150 23:16:59.477433 01680000 ################################################################
10151 23:16:59.477600
10152 23:16:59.759374 01700000 ################################################################
10153 23:16:59.759515
10154 23:17:00.055345 01780000 ################################################################
10155 23:17:00.055487
10156 23:17:00.349523 01800000 ################################################################
10157 23:17:00.349670
10158 23:17:00.646721 01880000 ################################################################
10159 23:17:00.646864
10160 23:17:00.948405 01900000 ################################################################
10161 23:17:00.948550
10162 23:17:01.248343 01980000 ################################################################
10163 23:17:01.248485
10164 23:17:01.540053 01a00000 ################################################################
10165 23:17:01.540195
10166 23:17:01.827650 01a80000 ################################################################
10167 23:17:01.827792
10168 23:17:02.109114 01b00000 ################################################################
10169 23:17:02.109253
10170 23:17:02.371266 01b80000 ################################################################
10171 23:17:02.371402
10172 23:17:02.739840 01c00000 ################################################################
10173 23:17:02.740338
10174 23:17:03.134470 01c80000 ################################################################
10175 23:17:03.134970
10176 23:17:03.524129 01d00000 ################################################################
10177 23:17:03.524630
10178 23:17:03.968020 01d80000 ################################################################
10179 23:17:03.968528
10180 23:17:04.375513 01e00000 ################################################################
10181 23:17:04.376033
10182 23:17:04.782683 01e80000 ################################################################
10183 23:17:04.783180
10184 23:17:05.176625 01f00000 ################################################################
10185 23:17:05.177123
10186 23:17:05.483045 01f80000 ################################################################
10187 23:17:05.483192
10188 23:17:05.773924 02000000 ################################################################
10189 23:17:05.774059
10190 23:17:06.067389 02080000 ################################################################
10191 23:17:06.067555
10192 23:17:06.397654 02100000 ################################################################
10193 23:17:06.398171
10194 23:17:06.801502 02180000 ################################################################
10195 23:17:06.802063
10196 23:17:07.205746 02200000 ################################################################
10197 23:17:07.206239
10198 23:17:07.598049 02280000 ################################################################
10199 23:17:07.598538
10200 23:17:08.015814 02300000 ################################################################
10201 23:17:08.016318
10202 23:17:08.381185 02380000 ################################################################
10203 23:17:08.381349
10204 23:17:08.773464 02400000 ################################################################
10205 23:17:08.774028
10206 23:17:09.208870 02480000 ################################################################
10207 23:17:09.209374
10208 23:17:09.620122 02500000 ################################################################
10209 23:17:09.620746
10210 23:17:10.015167 02580000 ################################################################
10211 23:17:10.015310
10212 23:17:10.314416 02600000 ################################################################
10213 23:17:10.314551
10214 23:17:10.616603 02680000 ################################################################
10215 23:17:10.616783
10216 23:17:10.914955 02700000 ################################################################
10217 23:17:10.915093
10218 23:17:11.241921 02780000 ################################################################
10219 23:17:11.242428
10220 23:17:11.619741 02800000 ################################################################
10221 23:17:11.619887
10222 23:17:11.918209 02880000 ################################################################
10223 23:17:11.918833
10224 23:17:12.307414 02900000 ################################################################
10225 23:17:12.307933
10226 23:17:12.719902 02980000 ################################################################
10227 23:17:12.720551
10228 23:17:13.141869 02a00000 ################################################################
10229 23:17:13.142480
10230 23:17:13.567014 02a80000 ################################################################
10231 23:17:13.567521
10232 23:17:13.995704 02b00000 ################################################################
10233 23:17:13.996213
10234 23:17:14.414749 02b80000 ################################################################
10235 23:17:14.415415
10236 23:17:14.833446 02c00000 ################################################################
10237 23:17:14.834019
10238 23:17:15.270166 02c80000 ################################################################
10239 23:17:15.270887
10240 23:17:15.683648 02d00000 ################################################################
10241 23:17:15.684201
10242 23:17:16.078354 02d80000 ################################################################
10243 23:17:16.078998
10244 23:17:16.483262 02e00000 ################################################################
10245 23:17:16.483809
10246 23:17:16.880069 02e80000 ################################################################
10247 23:17:16.880732
10248 23:17:17.279554 02f00000 ################################################################
10249 23:17:17.280089
10250 23:17:17.672550 02f80000 ################################################################
10251 23:17:17.673079
10252 23:17:18.071577 03000000 ################################################################
10253 23:17:18.072103
10254 23:17:18.504916 03080000 ################################################################
10255 23:17:18.505451
10256 23:17:18.933766 03100000 ################################################################
10257 23:17:18.934290
10258 23:17:19.342620 03180000 ################################################################
10259 23:17:19.343138
10260 23:17:19.732801 03200000 ################################################################
10261 23:17:19.733302
10262 23:17:20.164259 03280000 ################################################################
10263 23:17:20.164771
10264 23:17:20.561456 03300000 ################################################################
10265 23:17:20.561998
10266 23:17:20.965010 03380000 ################################################################
10267 23:17:20.965541
10268 23:17:21.363180 03400000 ################################################################
10269 23:17:21.363860
10270 23:17:21.684786 03480000 ################################################################
10271 23:17:21.685330
10272 23:17:22.080182 03500000 ################################################################
10273 23:17:22.080901
10274 23:17:22.376521 03580000 ################################################################
10275 23:17:22.376684
10276 23:17:22.677913 03600000 ################################################################
10277 23:17:22.678323
10278 23:17:23.062399 03680000 ################################################################
10279 23:17:23.062943
10280 23:17:23.480551 03700000 ################################################################
10281 23:17:23.481126
10282 23:17:23.816327 03780000 ####################################################### done.
10283 23:17:23.816823
10284 23:17:23.820070 The bootfile was 58641198 bytes long.
10285 23:17:23.820508
10286 23:17:23.823166 Sending tftp read request... done.
10287 23:17:23.823583
10288 23:17:23.826204 Waiting for the transfer...
10289 23:17:23.826663
10290 23:17:23.829271 00000000 # done.
10291 23:17:23.829738
10292 23:17:23.836364 Command line loaded dynamically from TFTP file: 12172418/tftp-deploy-1y2kapwx/kernel/cmdline
10293 23:17:23.837056
10294 23:17:23.849662 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10295 23:17:23.850159
10296 23:17:23.853138 Loading FIT.
10297 23:17:23.853550
10298 23:17:23.856451 Image ramdisk-1 has 47542540 bytes.
10299 23:17:23.856863
10300 23:17:23.857191 Image fdt-1 has 47278 bytes.
10301 23:17:23.857497
10302 23:17:23.859311 Image kernel-1 has 11049348 bytes.
10303 23:17:23.859725
10304 23:17:23.869742 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10305 23:17:23.870264
10306 23:17:23.886425 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10307 23:17:23.886995
10308 23:17:23.892685 Choosing best match conf-1 for compat google,spherion-rev2.
10309 23:17:23.896734
10310 23:17:23.901404 Connected to device vid:did:rid of 1ae0:0028:00
10311 23:17:23.909803
10312 23:17:23.913016 tpm_get_response: command 0x17b, return code 0x0
10313 23:17:23.913534
10314 23:17:23.915723 ec_init: CrosEC protocol v3 supported (256, 248)
10315 23:17:23.920942
10316 23:17:23.924032 tpm_cleanup: add release locality here.
10317 23:17:23.924546
10318 23:17:23.924881 Shutting down all USB controllers.
10319 23:17:23.927192
10320 23:17:23.927604 Removing current net device
10321 23:17:23.927934
10322 23:17:23.934098 Exiting depthcharge with code 4 at timestamp: 73232571
10323 23:17:23.934610
10324 23:17:23.936975 LZMA decompressing kernel-1 to 0x821a6718
10325 23:17:23.937393
10326 23:17:23.940909 LZMA decompressing kernel-1 to 0x40000000
10327 23:17:25.328558
10328 23:17:25.329115 jumping to kernel
10329 23:17:25.331207 end: 2.2.4 bootloader-commands (duration 00:00:45) [common]
10330 23:17:25.331730 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10331 23:17:25.332141 Setting prompt string to ['Linux version [0-9]']
10332 23:17:25.332519 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10333 23:17:25.332903 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10334 23:17:25.410272
10335 23:17:25.413878 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10336 23:17:25.417900 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10337 23:17:25.418497 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10338 23:17:25.418894 Setting prompt string to []
10339 23:17:25.419315 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10340 23:17:25.419707 Using line separator: #'\n'#
10341 23:17:25.420042 No login prompt set.
10342 23:17:25.420378 Parsing kernel messages
10343 23:17:25.420685 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10344 23:17:25.421253 [login-action] Waiting for messages, (timeout 00:03:40)
10345 23:17:25.437116 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10346 23:17:25.440196 [ 0.000000] random: crng init done
10347 23:17:25.447051 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10348 23:17:25.450080 [ 0.000000] efi: UEFI not found.
10349 23:17:25.456885 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10350 23:17:25.467211 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10351 23:17:25.473705 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10352 23:17:25.483573 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10353 23:17:25.490020 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10354 23:17:25.496750 [ 0.000000] printk: bootconsole [mtk8250] enabled
10355 23:17:25.503259 [ 0.000000] NUMA: No NUMA configuration found
10356 23:17:25.510071 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10357 23:17:25.513244 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10358 23:17:25.516640 [ 0.000000] Zone ranges:
10359 23:17:25.523589 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10360 23:17:25.526638 [ 0.000000] DMA32 empty
10361 23:17:25.533232 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10362 23:17:25.537300 [ 0.000000] Movable zone start for each node
10363 23:17:25.539734 [ 0.000000] Early memory node ranges
10364 23:17:25.546339 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10365 23:17:25.553376 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10366 23:17:25.559519 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10367 23:17:25.566349 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10368 23:17:25.569976 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10369 23:17:25.579496 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10370 23:17:25.635661 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10371 23:17:25.642514 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10372 23:17:25.649199 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10373 23:17:25.651918 [ 0.000000] psci: probing for conduit method from DT.
10374 23:17:25.659075 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10375 23:17:25.662434 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10376 23:17:25.665449 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10377 23:17:25.672177 [ 0.000000] psci: SMC Calling Convention v1.2
10378 23:17:25.678787 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10379 23:17:25.682310 [ 0.000000] Detected VIPT I-cache on CPU0
10380 23:17:25.688643 [ 0.000000] CPU features: detected: GIC system register CPU interface
10381 23:17:25.695326 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10382 23:17:25.702350 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10383 23:17:25.709179 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10384 23:17:25.715886 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10385 23:17:25.722184 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10386 23:17:25.729178 [ 0.000000] alternatives: applying boot alternatives
10387 23:17:25.732320 [ 0.000000] Fallback order for Node 0: 0
10388 23:17:25.738769 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10389 23:17:25.742151 [ 0.000000] Policy zone: Normal
10390 23:17:25.758312 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10391 23:17:25.768230 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10392 23:17:25.779515 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10393 23:17:25.789350 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10394 23:17:25.796018 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10395 23:17:25.798825 <6>[ 0.000000] software IO TLB: area num 8.
10396 23:17:25.855722 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10397 23:17:26.005416 <6>[ 0.000000] Memory: 7923128K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 429640K reserved, 32768K cma-reserved)
10398 23:17:26.011675 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10399 23:17:26.018180 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10400 23:17:26.021544 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10401 23:17:26.028665 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10402 23:17:26.035291 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10403 23:17:26.038112 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10404 23:17:26.048817 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10405 23:17:26.054926 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10406 23:17:26.058183 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10407 23:17:26.065741 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10408 23:17:26.069184 <6>[ 0.000000] GICv3: 608 SPIs implemented
10409 23:17:26.075846 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10410 23:17:26.079317 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10411 23:17:26.082228 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10412 23:17:26.092602 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10413 23:17:26.102262 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10414 23:17:26.115403 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10415 23:17:26.121846 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10416 23:17:26.131855 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10417 23:17:26.145373 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10418 23:17:26.151616 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10419 23:17:26.158099 <6>[ 0.009183] Console: colour dummy device 80x25
10420 23:17:26.168002 <6>[ 0.013928] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10421 23:17:26.174639 <6>[ 0.024371] pid_max: default: 32768 minimum: 301
10422 23:17:26.177910 <6>[ 0.029235] LSM: Security Framework initializing
10423 23:17:26.184291 <6>[ 0.034203] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10424 23:17:26.194390 <6>[ 0.042066] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10425 23:17:26.204282 <6>[ 0.051514] cblist_init_generic: Setting adjustable number of callback queues.
10426 23:17:26.208225 <6>[ 0.059001] cblist_init_generic: Setting shift to 3 and lim to 1.
10427 23:17:26.217982 <6>[ 0.065378] cblist_init_generic: Setting adjustable number of callback queues.
10428 23:17:26.224702 <6>[ 0.072806] cblist_init_generic: Setting shift to 3 and lim to 1.
10429 23:17:26.227958 <6>[ 0.079246] rcu: Hierarchical SRCU implementation.
10430 23:17:26.234796 <6>[ 0.079248] rcu: Max phase no-delay instances is 1000.
10431 23:17:26.241101 <6>[ 0.079272] printk: bootconsole [mtk8250] printing thread started
10432 23:17:26.247767 <6>[ 0.097597] EFI services will not be available.
10433 23:17:26.250989 <6>[ 0.097795] smp: Bringing up secondary CPUs ...
10434 23:17:26.254486 <6>[ 0.098108] Detected VIPT I-cache on CPU1
10435 23:17:26.264443 <6>[ 0.098175] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10436 23:17:26.271413 <6>[ 0.098207] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10437 23:17:26.279952 <6>[ 0.126058] Detected VIPT I-cache on CPU2
10438 23:17:26.286108 <6>[ 0.126106] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10439 23:17:26.292974 <6>[ 0.126121] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10440 23:17:26.299297 <6>[ 0.126377] Detected VIPT I-cache on CPU3
10441 23:17:26.306152 <6>[ 0.126425] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10442 23:17:26.313067 <6>[ 0.126438] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10443 23:17:26.316010 <6>[ 0.126747] CPU features: detected: Spectre-v4
10444 23:17:26.323029 <6>[ 0.126752] CPU features: detected: Spectre-BHB
10445 23:17:26.326207 <6>[ 0.126757] Detected PIPT I-cache on CPU4
10446 23:17:26.332814 <6>[ 0.126813] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10447 23:17:26.339744 <6>[ 0.126830] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10448 23:17:26.345812 <6>[ 0.127125] Detected PIPT I-cache on CPU5
10449 23:17:26.352565 <6>[ 0.127185] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10450 23:17:26.358978 <6>[ 0.127202] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10451 23:17:26.362551 <6>[ 0.127476] Detected PIPT I-cache on CPU6
10452 23:17:26.371901 <6>[ 0.127538] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10453 23:17:26.378648 <6>[ 0.127554] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10454 23:17:26.382286 <6>[ 0.127842] Detected PIPT I-cache on CPU7
10455 23:17:26.388573 <6>[ 0.127906] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10456 23:17:26.395392 <6>[ 0.127922] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10457 23:17:26.398710 <6>[ 0.127967] smp: Brought up 1 node, 8 CPUs
10458 23:17:26.405687 <6>[ 0.127972] SMP: Total of 8 processors activated.
10459 23:17:26.411917 <6>[ 0.127975] CPU features: detected: 32-bit EL0 Support
10460 23:17:26.418553 <6>[ 0.127977] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10461 23:17:26.425016 <6>[ 0.127979] CPU features: detected: Common not Private translations
10462 23:17:26.431534 <6>[ 0.127981] CPU features: detected: CRC32 instructions
10463 23:17:26.438501 <6>[ 0.127983] CPU features: detected: RCpc load-acquire (LDAPR)
10464 23:17:26.441416 <6>[ 0.127985] CPU features: detected: LSE atomic instructions
10465 23:17:26.448255 <6>[ 0.127986] CPU features: detected: Privileged Access Never
10466 23:17:26.454966 <6>[ 0.127988] CPU features: detected: RAS Extension Support
10467 23:17:26.461406 <6>[ 0.127991] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10468 23:17:26.464353 <6>[ 0.128058] CPU: All CPU(s) started at EL2
10469 23:17:26.471189 <6>[ 0.128059] alternatives: applying system-wide alternatives
10470 23:17:26.474355 <6>[ 0.141137] devtmpfs: initialized
10471 23:17:26.484104 <6>[ 0.147364] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10472 23:17:26.506989 ��egistered PF_INET protocol family
10473 23:17:26.513754 <6>[ 0.3<64500] printk: console [ttyS0] printing thread started
10474 23:17:26.520409 6>[ <6>[ 0.364519] printk: console [ttyS0] enabled
10475 23:17:26.526410 0.228671] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10476 23:17:26.534306 <6>[ 0.364523] printk: bootconsole [mtk8250] disabled
10477 23:17:26.541221 <6>[ 0.382609] printk: bootconsole [mtk8250] printing thread stopped
10478 23:17:26.544442 <6>[ 0.383893] SuperH (H)SCI(F) driver initialized
10479 23:17:26.551368 <6>[ 0.384375] msm_serial: driver initialized
10480 23:17:26.557410 <6>[ 0.389009] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10481 23:17:26.567068 <6>[ 0.389037] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10482 23:17:26.573723 <6>[ 0.389066] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10483 23:17:26.593961 <6>[ 0.389096] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10484 23:17:26.602271 <6>[ 0.389117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10485 23:17:26.602849 <6>[ 0.389145] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10486 23:17:26.619553 <6>[ 0.389173] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10487 23:17:26.620109 <6>[ 0.389300] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10488 23:17:26.634040 <6>[ 0.389330] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10489 23:17:26.634624 <6>[ 0.400215] loop: module loaded
10490 23:17:26.643410 <6>[ 0.402783] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10491 23:17:26.646887 <4>[ 0.419715] mtk-pmic-keys: Failed to locate of_node [id: -1]
10492 23:17:26.647465 <6>[ 0.420686] megasas: 07.719.03.00-rc1
10493 23:17:26.653753 <6>[ 0.432759] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10494 23:17:26.656564 <6>[ 0.432873] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10495 23:17:26.663272 <6>[ 0.444949] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10496 23:17:26.676211 <6>[ 0.497943] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10497 23:17:28.414121 <6>[ 2.261474] Freeing initrd memory: 46424K
10498 23:17:28.420501 <6>[ 2.267705] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10499 23:17:28.424137 <6>[ 2.272601] tun: Universal TUN/TAP device driver, 1.6
10500 23:17:28.427100 <6>[ 2.273369] thunder_xcv, ver 1.0
10501 23:17:28.430732 <6>[ 2.273392] thunder_bgx, ver 1.0
10502 23:17:28.434384 <6>[ 2.273408] nicpf, ver 1.0
10503 23:17:28.444200 <6>[ 2.274463] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10504 23:17:28.446961 <6>[ 2.274466] hns3: Copyright (c) 2017 Huawei Corporation.
10505 23:17:28.450528 <6>[ 2.274499] hclge is initializing
10506 23:17:28.457230 <6>[ 2.274513] e1000: Intel(R) PRO/1000 Network Driver
10507 23:17:28.464382 <6>[ 2.274515] e1000: Copyright (c) 1999-2006 Intel Corporation.
10508 23:17:28.467635 <6>[ 2.274532] e1000e: Intel(R) PRO/1000 Network Driver
10509 23:17:28.475039 <6>[ 2.274534] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10510 23:17:28.478141 <6>[ 2.274549] igb: Intel(R) Gigabit Ethernet Network Driver
10511 23:17:28.484913 <6>[ 2.274551] igb: Copyright (c) 2007-2014 Intel Corporation.
10512 23:17:28.491728 <6>[ 2.274575] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10513 23:17:28.498809 <6>[ 2.274577] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10514 23:17:28.501709 <6>[ 2.274871] sky2: driver version 1.30
10515 23:17:28.508783 <6>[ 2.275931] VFIO - User Level meta-driver version: 0.3
10516 23:17:28.512366 <6>[ 2.278800] usbcore: registered new interface driver usb-storage
10517 23:17:28.518354 <6>[ 2.278982] usbcore: registered new device driver onboard-usb-hub
10518 23:17:28.525387 <6>[ 2.281778] mt6397-rtc mt6359-rtc: registered as rtc0
10519 23:17:28.535220 <6>[ 2.281928] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:15:14 UTC (1701645314)
10520 23:17:28.538489 <6>[ 2.282546] i2c_dev: i2c /dev entries driver
10521 23:17:28.545350 <6>[ 2.289763] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10522 23:17:28.551683 <6>[ 2.304761] cpu cpu0: EM: created perf domain
10523 23:17:28.554890 <6>[ 2.305093] cpu cpu4: EM: created perf domain
10524 23:17:28.561718 <6>[ 2.307877] sdhci: Secure Digital Host Controller Interface driver
10525 23:17:28.568501 <6>[ 2.307878] sdhci: Copyright(c) Pierre Ossman
10526 23:17:28.572148 <6>[ 2.308223] Synopsys Designware Multimedia Card Interface Driver
10527 23:17:28.578137 <6>[ 2.308582] sdhci-pltfm: SDHCI platform and OF driver helper
10528 23:17:28.584554 <6>[ 2.312868] ledtrig-cpu: registered to indicate activity on CPUs
10529 23:17:28.587857 <6>[ 2.313581] mmc0: CQHCI version 5.10
10530 23:17:28.594244 <6>[ 2.313809] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10531 23:17:28.601200 <6>[ 2.314103] usbcore: registered new interface driver usbhid
10532 23:17:28.604449 <6>[ 2.314105] usbhid: USB HID core driver
10533 23:17:28.611438 <6>[ 2.314225] spi_master spi0: will run message pump with realtime priority
10534 23:17:28.625130 <6>[ 2.345262] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10535 23:17:28.637687 <6>[ 2.348421] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10536 23:17:28.644416 <6>[ 2.349700] cros-ec-spi spi0.0: Chrome EC device registered
10537 23:17:28.654603 <6>[ 2.362503] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10538 23:17:28.657781 <6>[ 2.363439] NET: Registered PF_PACKET protocol family
10539 23:17:28.664406 <6>[ 2.363507] 9pnet: Installing 9P2000 support
10540 23:17:28.667999 <5>[ 2.363543] Key type dns_resolver registered
10541 23:17:28.674342 <6>[ 2.364030] registered taskstats version 1
10542 23:17:28.677664 <5>[ 2.364046] Loading compiled-in X.509 certificates
10543 23:17:28.687770 <4>[ 2.378511] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 23:17:28.697447 <4>[ 2.378760] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 23:17:28.704353 <3>[ 2.378781] debugfs: File 'uA_load' in directory '/' already present!
10546 23:17:28.710559 <3>[ 2.378789] debugfs: File 'min_uV' in directory '/' already present!
10547 23:17:28.717147 <3>[ 2.378793] debugfs: File 'max_uV' in directory '/' already present!
10548 23:17:28.727406 <3>[ 2.378797] debugfs: File 'constraint_flags' in directory '/' already present!
10549 23:17:28.733661 <3>[ 2.382233] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10550 23:17:28.740582 <6>[ 2.393612] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10551 23:17:28.747225 <6>[ 2.394238] xhci-mtk 11200000.usb: xHCI Host Controller
10552 23:17:28.753660 <6>[ 2.394254] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10553 23:17:28.763528 <6>[ 2.394470] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10554 23:17:28.769923 <6>[ 2.394520] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10555 23:17:28.773874 <6>[ 2.394611] xhci-mtk 11200000.usb: xHCI Host Controller
10556 23:17:28.783493 <6>[ 2.394618] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10557 23:17:28.789825 <6>[ 2.394630] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10558 23:17:28.793255 <6>[ 2.395109] hub 1-0:1.0: USB hub found
10559 23:17:28.796521 <6>[ 2.395139] hub 1-0:1.0: 1 port detected
10560 23:17:28.806424 <6>[ 2.395421] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10561 23:17:28.809664 <6>[ 2.395797] hub 2-0:1.0: USB hub found
10562 23:17:28.813121 <6>[ 2.395818] hub 2-0:1.0: 1 port detected
10563 23:17:28.820398 <6>[ 2.398966] mtk-msdc 11f70000.mmc: Got CD GPIO
10564 23:17:28.822965 <6>[ 2.407701] mmc0: Command Queue Engine enabled
10565 23:17:28.829743 <6>[ 2.407716] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10566 23:17:28.836092 <6>[ 2.408345] mmcblk0: mmc0:0001 DA4128 116 GiB
10567 23:17:28.839876 <6>[ 2.412049] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10568 23:17:28.846266 <6>[ 2.413232] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10569 23:17:28.853001 <6>[ 2.414137] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10570 23:17:28.859416 <6>[ 2.414449] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10571 23:17:28.865838 <6>[ 2.414457] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10572 23:17:28.876018 <4>[ 2.414686] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10573 23:17:28.882805 <6>[ 2.414858] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10574 23:17:28.889385 <6>[ 2.415318] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10575 23:17:28.898971 <6>[ 2.415321] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10576 23:17:28.906076 <6>[ 2.415434] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10577 23:17:28.915863 <6>[ 2.415444] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10578 23:17:28.921953 <6>[ 2.415448] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10579 23:17:28.932132 <6>[ 2.415454] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10580 23:17:28.938789 <6>[ 2.417022] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10581 23:17:28.948900 <6>[ 2.417040] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10582 23:17:28.955458 <6>[ 2.417046] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10583 23:17:28.965189 <6>[ 2.417053] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10584 23:17:28.972032 <6>[ 2.417059] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10585 23:17:28.981971 <6>[ 2.417065] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10586 23:17:28.988693 <6>[ 2.417072] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10587 23:17:28.998080 <6>[ 2.417078] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10588 23:17:29.004593 <6>[ 2.417084] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10589 23:17:29.015087 <6>[ 2.417090] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10590 23:17:29.021568 <6>[ 2.417096] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10591 23:17:29.031487 <6>[ 2.417102] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10592 23:17:29.037809 <6>[ 2.417109] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10593 23:17:29.048103 <6>[ 2.417115] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10594 23:17:29.058190 <6>[ 2.417121] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10595 23:17:29.064186 <6>[ 2.417676] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10596 23:17:29.071176 <6>[ 2.418519] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10597 23:17:29.074149 <6>[ 2.419066] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10598 23:17:29.084456 <6>[ 2.419681] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10599 23:17:29.090805 <6>[ 2.420315] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10600 23:17:29.097362 <6>[ 2.420507] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10601 23:17:29.107360 <6>[ 2.420521] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10602 23:17:29.117064 <6>[ 2.420526] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10603 23:17:29.127354 <6>[ 2.420532] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10604 23:17:29.136903 <6>[ 2.420537] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10605 23:17:29.143591 <6>[ 2.420542] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10606 23:17:29.153445 <6>[ 2.420548] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10607 23:17:29.163229 <6>[ 2.420556] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10608 23:17:29.173349 <6>[ 2.420561] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10609 23:17:29.182923 <6>[ 2.420568] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10610 23:17:29.193279 <6>[ 2.420573] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10611 23:17:29.203305 <6>[ 2.421038] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10612 23:17:29.209269 <6>[ 2.825539] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10613 23:17:29.212867 <6>[ 2.985632] hub 1-1:1.0: USB hub found
10614 23:17:29.216516 <6>[ 2.985987] hub 1-1:1.0: 4 ports detected
10615 23:17:29.220024 <6>[ 2.989313] hub 1-1:1.0: USB hub found
10616 23:17:29.225894 <6>[ 2.989642] hub 1-1:1.0: 4 ports detected
10617 23:17:29.265296 <6>[ 3.109622] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10618 23:17:29.286137 <6>[ 3.133813] hub 2-1:1.0: USB hub found
10619 23:17:29.289002 <6>[ 3.134239] hub 2-1:1.0: 3 ports detected
10620 23:17:29.292502 <6>[ 3.137231] hub 2-1:1.0: USB hub found
10621 23:17:29.295802 <6>[ 3.137595] hub 2-1:1.0: 3 ports detected
10622 23:17:29.457774 <6>[ 3.301497] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10623 23:17:29.578265 <6>[ 3.428957] hub 1-1.4:1.0: USB hub found
10624 23:17:29.581325 <6>[ 3.429316] hub 1-1.4:1.0: 2 ports detected
10625 23:17:29.584484 <6>[ 3.432644] hub 1-1.4:1.0: USB hub found
10626 23:17:29.591055 <6>[ 3.432975] hub 1-1.4:1.0: 2 ports detected
10627 23:17:29.661317 <6>[ 3.505793] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10628 23:17:29.877558 <6>[ 3.721651] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10629 23:17:30.061164 <6>[ 3.905657] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10630 23:17:40.869758 <6>[ 14.722655] ALSA device list:
10631 23:17:40.875995 <6>[ 14.722678] No soundcards found.
10632 23:17:40.879318 <6>[ 14.727138] Freeing unused kernel memory: 8448K
10633 23:17:40.882920 <6>[ 14.727226] Run /init as init process
10634 23:17:40.908776 <6>[ 14.757883] NET: Registered PF_INET6 protocol family
10635 23:17:40.911769 <6>[ 14.759002] Segment Routing with IPv6
10636 23:17:40.915592
10637 23:17:40.922051 Welcome to [1mDebian GNU/Linu<6>[ 14.759017] In-situ OAM (IOAM) with IPv6
10638 23:17:40.945756 x 11 (bullseye)<30>[ 14.770855] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10639 23:17:40.946344 [0m!
10640 23:17:40.946707
10641 23:17:40.951941 <30>[ 14.771419] systemd[1]: Detected architecture arm64.
10642 23:17:40.964474 <30>[ 14.813827] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10643 23:17:41.124355 <30>[ 14.971162] systemd[1]: Queued start job for default target Graphical Interface.
10644 23:17:41.169489 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.018216] systemd[1]: Created slice system-getty.slice.
10645 23:17:41.172451 m-getty.slice[0m.
10646 23:17:41.196581 [[0;32m OK [0m] Created slice [0;1;39msyste<30>[ 15.042356] systemd[1]: Created slice system-modprobe.slice.
10647 23:17:41.197155 m-modprobe.slice[0m.
10648 23:17:41.221554 [[0;32m OK [0m] Created slic<30>[ 15.070671] systemd[1]: Created slice system-serial\x2dgetty.slice.
10649 23:17:41.228159 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10650 23:17:41.248203 [[0;32m OK [0m] Created slice [0;1;39mUser <30>[ 15.094157] systemd[1]: Created slice User and Session Slice.
10651 23:17:41.248774 and Session Slice[0m.
10652 23:17:41.273266 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 15.118476] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10653 23:17:41.275805 ssword …ts to Console Directory Watch[0m.
10654 23:17:41.300348 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 15.146402] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10655 23:17:41.304107 sword R…uests to Wall Directory Watch[0m.
10656 23:17:41.331800 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 15.174180] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10657 23:17:41.338106 <30>[ 15.174439] systemd[1]: Reached target Local Encrypted Volumes.
10658 23:17:41.340956 l Encrypted Volumes[0m.
10659 23:17:41.360484 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 15.210204] systemd[1]: Reached target Paths.
10660 23:17:41.360633 s[0m.
10661 23:17:41.383148 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 15.229653] systemd[1]: Reached target Remote File Systems.
10662 23:17:41.383371 te File Systems[0m.
10663 23:17:41.400001 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 15.249611] systemd[1]: Reached target Slices.
10664 23:17:41.400368 es[0m.
10665 23:17:41.420302 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 15.269661] systemd[1]: Reached target Swap.
10666 23:17:41.420867 [0m.
10667 23:17:41.444413 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 15.290134] systemd[1]: Listening on initctl Compatibility Named Pipe.
10668 23:17:41.447802 l Compatibility Named Pipe[0m.
10669 23:17:41.465974 [[0;32m OK [0m] Listening on<30>[ 15.315132] systemd[1]: Listening on Journal Audit Socket.
10670 23:17:41.469386 [0;1;39mJournal Audit Socket[0m.
10671 23:17:41.492021 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 15.338160] systemd[1]: Listening on Journal Socket (/dev/log).
10672 23:17:41.492664 l Socket (/dev/log)[0m.
10673 23:17:41.513598 [[0;32m OK [0m] Listening on<30>[ 15.362881] systemd[1]: Listening on Journal Socket.
10674 23:17:41.517009 [0;1;39mJournal Socket[0m.
10675 23:17:41.537457 [[0;32m OK [0m] Listening on [0;1;39mNetwor<30>[ 15.382351] systemd[1]: Listening on Network Service Netlink Socket.
10676 23:17:41.539331 k Service Netlink Socket[0m.
10677 23:17:41.556394 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 15.406190] systemd[1]: Listening on udev Control Socket.
10678 23:17:41.560488 ontrol Socket[0m.
10679 23:17:41.581396 [[0;32m OK [0m] Listening on<30>[ 15.430721] systemd[1]: Listening on udev Kernel Socket.
10680 23:17:41.584854 [0;1;39mudev Kernel Socket[0m.
10681 23:17:41.644354 Mounting [0;1;39mHuge Pages File Syste<30>[ 15.489868] systemd[1]: Mounting Huge Pages File System...
10682 23:17:41.644916 m[0m...
10683 23:17:41.663461 Mountin<30>[ 15.512845] systemd[1]: Mounting POSIX Message Queue File System...
10684 23:17:41.666304 g [0;1;39mPOSIX Message Queue File System[0m...
10685 23:17:41.688086 Mountin<30>[ 15.536973] systemd[1]: Mounting Kernel Debug File System...
10686 23:17:41.690577 g [0;1;39mKernel Debug File System[0m...
10687 23:17:41.711835 <30>[ 15.557795] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10688 23:17:41.725172 Starting [0;1;39mCreate list of st…o<30>[ 15.561768] systemd[1]: Starting Create list of static device nodes for the current kernel...
10689 23:17:41.728382 des for the current kernel[0m...
10690 23:17:41.767970 Starting [0;1;39mLoad Kernel Module co<30>[ 15.613857] systemd[1]: Starting Load Kernel Module configfs...
10691 23:17:41.768554 nfigfs[0m...
10692 23:17:41.792418 Starting [0;1;39mLoad Kernel Module dr<30>[ 15.641439] systemd[1]: Starting Load Kernel Module drm...
10693 23:17:41.795670 m[0m...
10694 23:17:41.815763 <30>[ 15.661787] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10695 23:17:41.829264 Starting [0;1;39mJourn<30>[ 15.678552] systemd[1]: Starting Journal Service...
10696 23:17:41.829884 al Service[0m...
10697 23:17:41.851015 Startin<30>[ 15.700354] systemd[1]: Starting Load Kernel Modules...
10698 23:17:41.854442 g [0;1;39mLoad Kernel Modules[0m...
10699 23:17:41.877536 Starting [0;1;39mRemou<30>[ 15.726865] systemd[1]: Starting Remount Root and Kernel File Systems...
10700 23:17:41.884220 nt Root and Kernel File Systems[0m...
10701 23:17:41.907528 Startin<30>[ 15.756840] systemd[1]: Starting Coldplug All udev Devices...
10702 23:17:41.910617 g [0;1;39mColdplug All udev Devices[0m...
10703 23:17:41.936518 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 15.785779] systemd[1]: Started Journal Service.
10704 23:17:41.939293 vice[0m.
10705 23:17:41.956360 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10706 23:17:41.974247 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10707 23:17:41.994699 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10708 23:17:42.017684 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10709 23:17:42.038998 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10710 23:17:42.059683 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10711 23:17:42.082357 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10712 23:17:42.107329 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10713 23:17:42.124785 See 'systemctl status systemd-remount-fs.service' for details.
10714 23:17:42.192730 Mounting [0;1;39mKernel Configuration File System[0m...
10715 23:17:42.217513 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10716 23:17:42.244586 <46>[ 16.089721] systemd-journald[191]: Received client request to flush runtime journal.
10717 23:17:42.251084 Starting [0;1;39mLoad/Save Random Seed[0m...
10718 23:17:42.274058 Starting [0;1;39mApply Kernel Variables[0m...
10719 23:17:42.294294 Starting [0;1;39mCreate System Users[0m...
10720 23:17:42.315896 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10721 23:17:42.338134 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10722 23:17:42.361968 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10723 23:17:42.373833 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10724 23:17:42.390296 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10725 23:17:42.410119 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10726 23:17:42.453509 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10727 23:17:42.481167 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10728 23:17:42.493338 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10729 23:17:42.512839 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10730 23:17:42.554168 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10731 23:17:42.578199 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10732 23:17:42.601699 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10733 23:17:42.622879 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10734 23:17:42.679499 Starting [0;1;39mNetwork Service[0m...
10735 23:17:42.715186 Starting [0;1;39mNetwork Time Synchronization[0m...
10736 23:17:42.738376 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10737 23:17:42.786723 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10738 23:17:42.799699 <6>[ 16.646732] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10739 23:17:42.807742 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10740 23:17:42.816536 <6>[ 16.666727] remoteproc remoteproc0: scp is available
10741 23:17:42.823595 <6>[ 16.666805] remoteproc remoteproc0: powering up scp
10742 23:17:42.829398 <6>[ 16.666812] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10743 23:17:42.836112 <6>[ 16.666840] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10744 23:17:42.842715 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10745 23:17:42.864099 <6>[ 16.712943] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10746 23:17:42.870331 <6>[ 16.713012] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10747 23:17:42.880369 <6>[ 16.713020] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10748 23:17:42.886846 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10749 23:17:42.903702 <3>[ 16.752899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10750 23:17:42.910055 <3>[ 16.752963] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 23:17:42.920357 <3>[ 16.752982] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10752 23:17:42.927258 <3>[ 16.765942] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10753 23:17:42.936945 <3>[ 16.765968] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 23:17:42.943449 <3>[ 16.765977] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10755 23:17:42.953292 <3>[ 16.765991] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 23:17:42.960375 <3>[ 16.766000] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10757 23:17:42.970290 <3>[ 16.769019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 23:17:42.979656 [[0;32m OK [<3>[ 16.778820] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10759 23:17:42.986257 <3>[ 16.778836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10760 23:17:42.993184 <3>[ 16.778841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10761 23:17:43.002913 <6>[ 16.792373] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10762 23:17:43.009387 <6>[ 16.793903] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10763 23:17:43.016792 <6>[ 16.793929] remoteproc remoteproc0: remote processor scp is now up
10764 23:17:43.026373 0m] Created slic<3>[ 16.794183] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10765 23:17:43.033296 <3>[ 16.794198] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10766 23:17:43.043446 <3>[ 16.794201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10767 23:17:43.050647 <3>[ 16.794206] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10768 23:17:43.057304 <3>[ 16.794209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10769 23:17:43.067655 <3>[ 16.810844] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10770 23:17:43.070532 e [0;1;39msyste<6>[ 16.813231] mc: Linux media interface: v0.10
10771 23:17:43.081188 <4>[ 16.848905] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10772 23:17:43.087717 <6>[ 16.857011] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10773 23:17:43.090884 <6>[ 16.857039] pci_bus 0000:00: root bus resource [bus 00-ff]
10774 23:17:43.097704 <4>[ 16.857041] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10775 23:17:43.107822 m-systemd\x2dbac<6>[ 16.857050] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10776 23:17:43.118349 <6>[ 16.857058] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10777 23:17:43.125192 klight.slice[0m<6>[ 16.857110] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10778 23:17:43.125762 .
10779 23:17:43.131945 <6>[ 16.857125] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10780 23:17:43.138361 <6>[ 16.857203] pci 0000:00:00.0: supports D1 D2
10781 23:17:43.145079 <6>[ 16.857207] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10782 23:17:43.151994 <6>[ 16.864023] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10783 23:17:43.162324 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 16.869742] videodev: Linux video capture interface: v2.00
10784 23:17:43.169194 em Time Set[0m.<6>[ 16.884494] usbcore: registered new interface driver r8152
10785 23:17:43.169806
10786 23:17:43.178877 <6>[ 16.884753] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10787 23:17:43.184881 <6>[ 16.884910] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10788 23:17:43.194806 [[0;32m OK [0m] Reached target [0;1;39mSyst<6>[ 16.884946] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10789 23:17:43.204802 em Time Synchron<6>[ 16.884972] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10790 23:17:43.205371 ized[0m.
10791 23:17:43.214921 <6>[ 16.884987] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10792 23:17:43.218137 <6>[ 16.885180] pci 0000:01:00.0: supports D1 D2
10793 23:17:43.224810 <6>[ 16.885186] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10794 23:17:43.234638 <4>[ 16.888731] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10795 23:17:43.238308 <4>[ 16.888731] Fallback method does not support PEC.
10796 23:17:43.248966 <6>[ 16.902088] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10797 23:17:43.256328 <6>[ 16.904972] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10798 23:17:43.263753 <6>[ 16.905032] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10799 23:17:43.270228 <6>[ 16.905037] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10800 23:17:43.280584 <6>[ 16.905047] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10801 23:17:43.287479 <6>[ 16.905060] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10802 23:17:43.294457 <6>[ 16.905073] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10803 23:17:43.301209 <6>[ 16.905086] pci 0000:00:00.0: PCI bridge to [bus 01]
10804 23:17:43.308642 <6>[ 16.905092] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10805 23:17:43.318219 <3>[ 16.907451] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10806 23:17:43.325827 <6>[ 16.908375] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10807 23:17:43.332342 <6>[ 16.911113] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10808 23:17:43.343415 <3>[ 16.940576] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10809 23:17:43.346175 <6>[ 16.940987] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10810 23:17:43.352881 <6>[ 16.941183] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10811 23:17:43.363510 <6>[ 16.967371] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10812 23:17:43.370322 <3>[ 16.972946] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10813 23:17:43.377082 <6>[ 16.991959] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10814 23:17:43.387557 <3>[ 17.010407] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10815 23:17:43.390913 <6>[ 17.037739] Bluetooth: Core ver 2.22
10816 23:17:43.397199 <6>[ 17.038156] NET: Registered PF_BLUETOOTH protocol family
10817 23:17:43.404677 <6>[ 17.038160] Bluetooth: HCI device and connection manager initialized
10818 23:17:43.408254 <6>[ 17.038173] Bluetooth: HCI socket layer initialized
10819 23:17:43.414406 <6>[ 17.038197] Bluetooth: L2CAP socket layer initialized
10820 23:17:43.418084 <6>[ 17.038211] Bluetooth: SCO socket layer initialized
10821 23:17:43.424702 <6>[ 17.046033] r8152 2-1.3:1.0: load rtl8153b-2 v1 10/23/19 successfully
10822 23:17:43.431303 <6>[ 17.052467] usbcore: registered new interface driver cdc_ether
10823 23:17:43.437616 <6>[ 17.054690] usbcore: registered new interface driver r8153_ecm
10824 23:17:43.444686 <5>[ 17.073730] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10825 23:17:43.451686 <5>[ 17.086826] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10826 23:17:43.461394 <4>[ 17.086888] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10827 23:17:43.468038 <6>[ 17.086896] cfg80211: failed to load regulatory.db
10828 23:17:43.470952 <6>[ 17.096708] r8152 2-1.3:1.0 eth0: v1.12.13
10829 23:17:43.477533 <6>[ 17.097882] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10830 23:17:43.487203 <6>[ 17.099144] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10831 23:17:43.497406 <6>[ 17.100573] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10832 23:17:43.504498 <6>[ 17.100693] usbcore: registered new interface driver uvcvideo
10833 23:17:43.513990 <6>[ 17.100842] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10834 23:17:43.521102 <3>[ 17.112586] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 23:17:43.530732 <3>[ 17.113104] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10836 23:17:43.544087 Startin<4>[ 17.117083] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10837 23:17:43.550289 g [0;1;39mLoad/<3>[ 17.117099] Bluetooth: hci0: Failed to load firmware file (-2)
10838 23:17:43.557182 <3>[ 17.117102] Bluetooth: hci0: Failed to set up firmware (-2)
10839 23:17:43.567051 <4>[ 17.117105] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10840 23:17:43.573789 <6>[ 17.117513] usbcore: registered new interface driver btusb
10841 23:17:43.577453 <6>[ 17.121254] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10842 23:17:43.587181 <3>[ 17.121571] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10843 23:17:43.596309 <3>[ 17.140326] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10844 23:17:43.603694 <6>[ 17.146152] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10845 23:17:43.610145 <3>[ 17.163483] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10846 23:17:43.620017 <3>[ 17.184849] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10847 23:17:43.626696 <6>[ 17.457568] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10848 23:17:43.633284 <6>[ 17.457701] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10849 23:17:43.639764 <6>[ 17.477544] mt7921e 0000:01:00.0: ASIC revision: 79610010
10850 23:17:43.643294 Save Screen …of leds:white:kbd_backlight[0m...
10851 23:17:43.667192 Starting [0;1;39mNetwork Name Resolution[0m...
10852 23:17:43.686143 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10853 23:17:43.730714 <4>[ 17.574811] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10854 23:17:43.773908 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10855 23:17:43.838935 <4>[ 17.683601] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10856 23:17:43.845704 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10857 23:17:43.860488 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10858 23:17:43.879810 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10859 23:17:43.892499 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10860 23:17:43.912618 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10861 23:17:43.933226 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10862 23:17:43.947262 <4>[ 17.791941] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10863 23:17:43.953970 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10864 23:17:43.972769 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10865 23:17:43.989360 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10866 23:17:44.009021 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10867 23:17:44.032831 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10868 23:17:44.055084 <4>[ 17.899845] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 23:17:44.085401 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10870 23:17:44.114555 Starting [0;1;39mUser Login Management[0m...
10871 23:17:44.133515 Starting [0;1;39mPermit User Sessions[0m...
10872 23:17:44.168389 [[0;32m OK [0m] Finished [0<4>[ 18.011221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10873 23:17:44.172092 ;1;39mPermit User Sessions[0m.
10874 23:17:44.191071 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10875 23:17:44.209415 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10876 23:17:44.225057 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10877 23:17:44.244970 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10878 23:17:44.276516 [[0;32m OK [0m] Started [0;<4>[ 18.120526] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10879 23:17:44.279472 1;39mUser Login Management[0m.
10880 23:17:44.286657 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10881 23:17:44.306899 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10882 23:17:44.325218 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10883 23:17:44.383682 <4>[ 18.227953] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10884 23:17:44.394162 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10885 23:17:44.424114 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10886 23:17:44.439139
10887 23:17:44.439710
10888 23:17:44.442537 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10889 23:17:44.443017
10890 23:17:44.445799 debian-bullseye-arm64 login: root (automatic login)
10891 23:17:44.446280
10892 23:17:44.446766
10893 23:17:44.463393 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10894 23:17:44.464079
10895 23:17:44.470087 The programs included with the Debian GNU/Linux system are free software;
10896 23:17:44.476783 the exact distribution terms for each program are described in the
10897 23:17:44.493290 individual files in /usr/share/doc/*/copyrigh<4>[ 18.336841] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10898 23:17:44.493879 t.
10899 23:17:44.494228
10900 23:17:44.496331 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10901 23:17:44.499465 permitted by applicable law.
10902 23:17:44.500820 Matched prompt #10: / #
10904 23:17:44.501891 Setting prompt string to ['/ #']
10905 23:17:44.502326 end: 2.2.5.1 login-action (duration 00:00:19) [common]
10907 23:17:44.503284 end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10908 23:17:44.503717 start: 2.2.6 expect-shell-connection (timeout 00:03:21) [common]
10909 23:17:44.504057 Setting prompt string to ['/ #']
10910 23:17:44.504363 Forcing a shell prompt, looking for ['/ #']
10912 23:17:44.555244 / #
10913 23:17:44.555886 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10914 23:17:44.556357 Waiting using forced prompt support (timeout 00:02:30)
10915 23:17:44.561703
10916 23:17:44.562656 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10917 23:17:44.563179 start: 2.2.7 export-device-env (timeout 00:03:21) [common]
10918 23:17:44.563674 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10919 23:17:44.564138 end: 2.2 depthcharge-retry (duration 00:01:39) [common]
10920 23:17:44.564647 end: 2 depthcharge-action (duration 00:01:39) [common]
10921 23:17:44.565118 start: 3 lava-test-retry (timeout 00:05:00) [common]
10922 23:17:44.565610 start: 3.1 lava-test-shell (timeout 00:05:00) [common]
10923 23:17:44.566032 Using namespace: common
10925 23:17:44.667554 / # #
10926 23:17:44.668208 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:05:00)
10927 23:17:44.668804 <4>[ 18.447864] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 23:17:44.674502 #
10929 23:17:44.675386 Using /lava-12172418
10931 23:17:44.776578 / # export SHELL=/bin/sh
10932 23:17:44.777522 <4>[ 18.556087] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10933 23:17:44.783101 export SHELL=/bin/sh
10935 23:17:44.884762 / # . /lava-12172418/environment
10936 23:17:44.885525 <3>[ 18.662010] mt7921e 0000:01:00.0: hardware init failed
10937 23:17:44.885966 . /lava-12172418/environment<6>[ 18.721050] IPv6: ADDRCONF(NETDEV_CHANGE): enx00e04c787aaa: link becomes ready
10938 23:17:44.886323 <6>[ 18.721789] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10939 23:17:44.890878
10941 23:17:44.992601 / # /lava-12172418/bin/lava-test-runner /lava-12172418/0
10942 23:17:44.993224 Test shell timeout: 10s (minimum of the action and connection timeout)
10943 23:17:44.999170 /lava-12172418/bin/lava-test-runner /lava-12172418/0
10944 23:17:45.022311 + export TESTRUN_ID=0_cros-ec
10945 23:17:45.029179 +<8>[ 18.880512] <LAVA_SIGNAL_STARTRUN 0_cros-ec 12172418_1.5.2.3.1>
10946 23:17:45.030074 Received signal: <STARTRUN> 0_cros-ec 12172418_1.5.2.3.1
10947 23:17:45.030489 Starting test lava.0_cros-ec (12172418_1.5.2.3.1)
10948 23:17:45.030938 Skipping test definition patterns.
10949 23:17:45.032574 cd /lava-12172418/0/tests/0_cros-ec
10950 23:17:45.035749 + cat uuid
10951 23:17:45.036306 + UUID=12172418_1.5.2.3.1
10952 23:17:45.036683 + set +x
10953 23:17:45.042420 + python3 -m cros.runners.lava_runner -v
10954 23:17:45.423808 test_cros_ec_accel_iio_abi (cros.tests.cros_ec_accel.TestCrosECAccel)
10955 23:17:45.430033 Checks the cros-ec accelerometer IIO ABI. ... skipped 'No cros-ec-accel found'
10956 23:17:45.430634
10957 23:17:45.436866 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip
10959 23:17:45.439947 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_abi RESULT=skip>
10960 23:17:45.446717 test_cros_ec_accel_iio_data_is_valid (cros.tests.cros_ec_accel.TestCrosECAccel)
10961 23:17:45.453118 Validates accelerometer data by computing the magnitude. If the ... skipped 'No accelerometer found'
10962 23:17:45.453703
10963 23:17:45.460119 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8
10964 23:17:45.460735 Test case results without result (probably a sign of an incorrect parsing pattern being used): {'test_case_id': 'test_cros_ec_accel_iio_data_is_<8', 'result': 'unknown'}
10965 23:17:45.466730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_accel_iio_data_is_<8>[ 19.316569] <LAVA_SIGNAL_ENDRUN 0_cros-ec 12172418_1.5.2.3.1>
10966 23:17:45.467581 Received signal: <ENDRUN> 0_cros-ec 12172418_1.5.2.3.1
10967 23:17:45.468026 Ending use of test pattern.
10968 23:17:45.468377 Ending test lava.0_cros-ec (12172418_1.5.2.3.1), duration 0.44
10970 23:17:45.469991 valid RESULT=skip>
10971 23:17:45.472908 test_cros_ec_gyro_iio_abi (cros.tests.cros_ec_gyro.TestCrosECGyro)
10972 23:17:45.479592 Checks the cros-ec gyroscope IIO ABI. ... skipped 'No cros-ec-gyro found'
10973 23:17:45.480162
10974 23:17:45.486276 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip>
10975 23:17:45.487082 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_gyro_iio_abi RESULT=skip
10977 23:17:45.493000 test_cros_ec_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10978 23:17:45.496148 Checks the standard ABI for the main Embedded Controller. ... ok
10979 23:17:45.500008
10980 23:17:45.503074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_abi RESULT=pass>
10981 23:17:45.503878 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_abi RESULT=pass
10983 23:17:45.509392 test_cros_ec_chardev (cros.tests.cros_ec_mcu.TestCrosECMCU)
10984 23:17:45.512487 Checks the main Embedded controller character device. ... ok
10985 23:17:45.516441
10986 23:17:45.519152 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_chardev RESULT=pass>
10987 23:17:45.519823 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_chardev RESULT=pass
10989 23:17:45.526347 test_cros_ec_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
10990 23:17:45.532691 Checks basic comunication with the main Embedded controller. ... ok
10991 23:17:45.533107
10992 23:17:45.539440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_hello RESULT=pass>
10993 23:17:45.540230 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_hello RESULT=pass
10995 23:17:45.542488 test_cros_fp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
10996 23:17:45.549845 Checks the standard ABI for the Fingerprint EC. ... skipped 'MCU cros_fp not supported'
10997 23:17:45.550360
10998 23:17:45.556472 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_abi RESULT=skip>
10999 23:17:45.557320 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_abi RESULT=skip
11001 23:17:45.562616 test_cros_fp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11002 23:17:45.569512 Checks basic comunication with the fingerprint controller. ... skipped 'MCU cros_fp not found'
11003 23:17:45.570073
11004 23:17:45.575790 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_hello RESULT=skip>
11005 23:17:45.576599 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_hello RESULT=skip
11007 23:17:45.582758 test_cros_fp_reboot (cros.tests.cros_ec_mcu.TestCrosECMCU)
11008 23:17:45.589214 Test reboot command on Fingerprint MCU. ... skipped 'MCU cros_fp not found'
11009 23:17:45.589781
11010 23:17:45.592375 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_fp_reboot RESULT=skip>
11011 23:17:45.593156 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_fp_reboot RESULT=skip
11013 23:17:45.599268 test_cros_pd_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11014 23:17:45.605880 Checks the standard ABI for the Power Delivery EC. ... skipped 'MCU cros_pd not supported'
11015 23:17:45.606394
11016 23:17:45.612464 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_abi RESULT=skip>
11017 23:17:45.613249 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_abi RESULT=skip
11019 23:17:45.618920 test_cros_pd_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11020 23:17:45.625417 Checks basic comunication with the power delivery controller. ... skipped 'MCU cros_pd not found'
11021 23:17:45.626007
11022 23:17:45.632310 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_pd_hello RESULT=skip>
11023 23:17:45.633152 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_pd_hello RESULT=skip
11025 23:17:45.638547 test_cros_tp_abi (cros.tests.cros_ec_mcu.TestCrosECMCU)
11026 23:17:45.645644 Checks the standard ABI for the Touchpad EC. ... skipped 'MCU cros_tp not supported'
11027 23:17:45.646219
11028 23:17:45.652101 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_abi RESULT=skip>
11029 23:17:45.652939 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_abi RESULT=skip
11031 23:17:45.655232 test_cros_tp_hello (cros.tests.cros_ec_mcu.TestCrosECMCU)
11032 23:17:45.665228 Checks basic comunication with the touchpad controller. ... skipped 'MCU cros_tp not found'
11033 23:17:45.665829
11034 23:17:45.668743 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_tp_hello RESULT=skip
11036 23:17:45.671817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_tp_hello RESULT=skip>
11037 23:17:45.675221 test_cros_ec_pwm_backlight (cros.tests.cros_ec_pwm.TestCrosECPWM)
11038 23:17:45.685370 Check that the backlight is connected to a pwm of the EC and that ... skipped 'No backlight pwm found'
11039 23:17:45.685975
11040 23:17:45.692158 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip>
11041 23:17:45.692995 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_pwm_backlight RESULT=skip
11043 23:17:45.698199 test_cros_ec_battery_abi (cros.tests.cros_ec_power.TestCrosECPower)
11044 23:17:45.701508 Check the cros battery ABI. ... skipped 'No BAT found'
11045 23:17:45.702038
11046 23:17:45.708128 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip>
11047 23:17:45.708960 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_battery_abi RESULT=skip
11049 23:17:45.714824 test_cros_ec_usbpd_charger_abi (cros.tests.cros_ec_power.TestCrosECPower)
11050 23:17:45.721323 Check the cros USBPD charger ABI. ... skipped 'No CROS_USBPD_CHARGER found'
11051 23:17:45.721907
11052 23:17:45.728387 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip>
11053 23:17:45.729221 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_usbpd_charger_abi RESULT=skip
11055 23:17:45.734507 test_cros_ec_rtc_abi (cros.tests.cros_ec_rtc.TestCrosECRTC)
11056 23:17:45.741487 Check the cros RTC ABI. ... skipped 'EC_FEATURE_RTC not supported, skipping'
11057 23:17:45.742092
11058 23:17:45.747727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip>
11059 23:17:45.748545 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_rtc_abi RESULT=skip
11061 23:17:45.754774 test_cros_ec_extcon_usbc_abi (cros.tests.cros_ec_extcon.TestCrosECextcon)
11062 23:17:45.761387 Checks the cros-ec extcon ABI. ... skipped 'No extcon device found'
11063 23:17:45.762001
11064 23:17:45.767419 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip>
11065 23:17:45.767965
11066 23:17:45.768601 Received signal: <TESTCASE> TEST_CASE_ID=test_cros_ec_extcon_usbc_abi RESULT=skip
11068 23:17:45.774375 ----------------------------------------------------------------------
11069 23:17:45.774922 Ran 18 tests in 0.006s
11070 23:17:45.777898
11071 23:17:45.778353 OK (skipped=15)
11072 23:17:45.778719 + set +x
11073 23:17:45.781304 <LAVA_TEST_RUNNER EXIT>
11074 23:17:45.782167 ok: lava_test_shell seems to have completed
11075 23:17:45.783112 test_cros_ec_abi: pass
test_cros_ec_accel_iio_abi: skip
test_cros_ec_battery_abi: skip
test_cros_ec_chardev: pass
test_cros_ec_extcon_usbc_abi: skip
test_cros_ec_gyro_iio_abi: skip
test_cros_ec_hello: pass
test_cros_ec_pwm_backlight: skip
test_cros_ec_rtc_abi: skip
test_cros_ec_usbpd_charger_abi: skip
test_cros_fp_abi: skip
test_cros_fp_hello: skip
test_cros_fp_reboot: skip
test_cros_pd_abi: skip
test_cros_pd_hello: skip
test_cros_tp_abi: skip
test_cros_tp_hello: skip
11076 23:17:45.783611 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11077 23:17:45.784065 end: 3 lava-test-retry (duration 00:00:01) [common]
11078 23:17:45.784549 start: 4 finalize (timeout 00:07:59) [common]
11079 23:17:45.785028 start: 4.1 power-off (timeout 00:00:30) [common]
11080 23:17:45.785875 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11081 23:17:45.903246 >> Command sent successfully.
11082 23:17:45.906639 Returned 0 in 0 seconds
11083 23:17:46.007674 end: 4.1 power-off (duration 00:00:00) [common]
11085 23:17:46.009443 start: 4.2 read-feedback (timeout 00:07:58) [common]
11086 23:17:46.010804 Listened to connection for namespace 'common' for up to 1s
11087 23:17:47.011411 Finalising connection for namespace 'common'
11088 23:17:47.012088 Disconnecting from shell: Finalise
11089 23:17:47.012491 / #
11090 23:17:47.113503 end: 4.2 read-feedback (duration 00:00:01) [common]
11091 23:17:47.114217 end: 4 finalize (duration 00:00:01) [common]
11092 23:17:47.114802 Cleaning after the job
11093 23:17:47.115323 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/ramdisk
11094 23:17:47.144584 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/kernel
11095 23:17:47.163268 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/dtb
11096 23:17:47.163567 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172418/tftp-deploy-1y2kapwx/modules
11097 23:17:47.173665 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172418
11098 23:17:47.292307 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172418
11099 23:17:47.292490 Job finished correctly