Boot log: mt8192-asurada-spherion-r0

    1 23:05:42.883753  lava-dispatcher, installed at version: 2023.10
    2 23:05:42.883992  start: 0 validate
    3 23:05:42.884143  Start time: 2023-12-03 23:05:42.884134+00:00 (UTC)
    4 23:05:42.884285  Using caching service: 'http://localhost/cache/?uri=%s'
    5 23:05:42.884439  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 23:05:43.151279  Using caching service: 'http://localhost/cache/?uri=%s'
    7 23:05:43.151451  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 23:05:43.423647  Using caching service: 'http://localhost/cache/?uri=%s'
    9 23:05:43.423838  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 23:05:43.680911  Using caching service: 'http://localhost/cache/?uri=%s'
   11 23:05:43.681101  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 23:05:43.953501  validate duration: 1.07
   14 23:05:43.954710  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 23:05:43.955353  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 23:05:43.955783  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 23:05:43.956323  Not decompressing ramdisk as can be used compressed.
   18 23:05:43.956787  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
   19 23:05:43.957104  saving as /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/ramdisk/rootfs.cpio.gz
   20 23:05:43.957417  total size: 43284872 (41 MB)
   21 23:05:43.963083  progress   0 % (0 MB)
   22 23:05:43.993886  progress   5 % (2 MB)
   23 23:05:44.008532  progress  10 % (4 MB)
   24 23:05:44.020776  progress  15 % (6 MB)
   25 23:05:44.032272  progress  20 % (8 MB)
   26 23:05:44.043517  progress  25 % (10 MB)
   27 23:05:44.055139  progress  30 % (12 MB)
   28 23:05:44.067550  progress  35 % (14 MB)
   29 23:05:44.079464  progress  40 % (16 MB)
   30 23:05:44.091177  progress  45 % (18 MB)
   31 23:05:44.102747  progress  50 % (20 MB)
   32 23:05:44.114566  progress  55 % (22 MB)
   33 23:05:44.126457  progress  60 % (24 MB)
   34 23:05:44.139369  progress  65 % (26 MB)
   35 23:05:44.150893  progress  70 % (28 MB)
   36 23:05:44.162843  progress  75 % (30 MB)
   37 23:05:44.175147  progress  80 % (33 MB)
   38 23:05:44.188573  progress  85 % (35 MB)
   39 23:05:44.200597  progress  90 % (37 MB)
   40 23:05:44.212010  progress  95 % (39 MB)
   41 23:05:44.223650  progress 100 % (41 MB)
   42 23:05:44.223920  41 MB downloaded in 0.27 s (154.88 MB/s)
   43 23:05:44.224101  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 23:05:44.224357  end: 1.1 download-retry (duration 00:00:00) [common]
   46 23:05:44.224453  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 23:05:44.224560  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 23:05:44.224727  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 23:05:44.224827  saving as /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/kernel/Image
   50 23:05:44.224917  total size: 49172992 (46 MB)
   51 23:05:44.225023  No compression specified
   52 23:05:44.226420  progress   0 % (0 MB)
   53 23:05:44.239777  progress   5 % (2 MB)
   54 23:05:44.253030  progress  10 % (4 MB)
   55 23:05:44.266186  progress  15 % (7 MB)
   56 23:05:44.279816  progress  20 % (9 MB)
   57 23:05:44.293356  progress  25 % (11 MB)
   58 23:05:44.306963  progress  30 % (14 MB)
   59 23:05:44.320874  progress  35 % (16 MB)
   60 23:05:44.334670  progress  40 % (18 MB)
   61 23:05:44.348038  progress  45 % (21 MB)
   62 23:05:44.361454  progress  50 % (23 MB)
   63 23:05:44.375884  progress  55 % (25 MB)
   64 23:05:44.390849  progress  60 % (28 MB)
   65 23:05:44.405339  progress  65 % (30 MB)
   66 23:05:44.418944  progress  70 % (32 MB)
   67 23:05:44.432659  progress  75 % (35 MB)
   68 23:05:44.446011  progress  80 % (37 MB)
   69 23:05:44.459881  progress  85 % (39 MB)
   70 23:05:44.474151  progress  90 % (42 MB)
   71 23:05:44.487531  progress  95 % (44 MB)
   72 23:05:44.500878  progress 100 % (46 MB)
   73 23:05:44.501107  46 MB downloaded in 0.28 s (169.80 MB/s)
   74 23:05:44.501283  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 23:05:44.501710  end: 1.2 download-retry (duration 00:00:00) [common]
   77 23:05:44.501845  start: 1.3 download-retry (timeout 00:09:59) [common]
   78 23:05:44.501962  start: 1.3.1 http-download (timeout 00:09:59) [common]
   79 23:05:44.502099  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 23:05:44.502169  saving as /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/dtb/mt8192-asurada-spherion-r0.dtb
   81 23:05:44.502231  total size: 47278 (0 MB)
   82 23:05:44.502292  No compression specified
   83 23:05:44.503497  progress  69 % (0 MB)
   84 23:05:44.503788  progress 100 % (0 MB)
   85 23:05:44.503947  0 MB downloaded in 0.00 s (26.32 MB/s)
   86 23:05:44.504070  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 23:05:44.504285  end: 1.3 download-retry (duration 00:00:00) [common]
   89 23:05:44.504396  start: 1.4 download-retry (timeout 00:09:59) [common]
   90 23:05:44.504517  start: 1.4.1 http-download (timeout 00:09:59) [common]
   91 23:05:44.504715  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 23:05:44.504792  saving as /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/modules/modules.tar
   93 23:05:44.504861  total size: 8614132 (8 MB)
   94 23:05:44.504955  Using unxz to decompress xz
   95 23:05:44.509702  progress   0 % (0 MB)
   96 23:05:44.532308  progress   5 % (0 MB)
   97 23:05:44.556551  progress  10 % (0 MB)
   98 23:05:44.581842  progress  15 % (1 MB)
   99 23:05:44.609368  progress  20 % (1 MB)
  100 23:05:44.635309  progress  25 % (2 MB)
  101 23:05:44.663427  progress  30 % (2 MB)
  102 23:05:44.692456  progress  35 % (2 MB)
  103 23:05:44.718748  progress  40 % (3 MB)
  104 23:05:44.746182  progress  45 % (3 MB)
  105 23:05:44.773026  progress  50 % (4 MB)
  106 23:05:44.799107  progress  55 % (4 MB)
  107 23:05:44.825626  progress  60 % (4 MB)
  108 23:05:44.853439  progress  65 % (5 MB)
  109 23:05:44.882031  progress  70 % (5 MB)
  110 23:05:44.906669  progress  75 % (6 MB)
  111 23:05:44.935649  progress  80 % (6 MB)
  112 23:05:44.962756  progress  85 % (7 MB)
  113 23:05:44.988840  progress  90 % (7 MB)
  114 23:05:45.019787  progress  95 % (7 MB)
  115 23:05:45.049694  progress 100 % (8 MB)
  116 23:05:45.056077  8 MB downloaded in 0.55 s (14.90 MB/s)
  117 23:05:45.056337  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 23:05:45.056598  end: 1.4 download-retry (duration 00:00:01) [common]
  120 23:05:45.056692  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 23:05:45.056792  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 23:05:45.056872  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 23:05:45.056956  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 23:05:45.057185  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3
  125 23:05:45.057327  makedir: /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin
  126 23:05:45.057435  makedir: /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/tests
  127 23:05:45.057536  makedir: /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/results
  128 23:05:45.057701  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-add-keys
  129 23:05:45.057861  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-add-sources
  130 23:05:45.058000  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-background-process-start
  131 23:05:45.058226  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-background-process-stop
  132 23:05:45.058361  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-common-functions
  133 23:05:45.058492  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-echo-ipv4
  134 23:05:45.058638  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-install-packages
  135 23:05:45.058785  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-installed-packages
  136 23:05:45.058932  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-os-build
  137 23:05:45.059079  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-probe-channel
  138 23:05:45.059225  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-probe-ip
  139 23:05:45.059373  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-target-ip
  140 23:05:45.059522  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-target-mac
  141 23:05:45.059696  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-target-storage
  142 23:05:45.059919  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-case
  143 23:05:45.060121  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-event
  144 23:05:45.060273  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-feedback
  145 23:05:45.060447  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-raise
  146 23:05:45.060633  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-reference
  147 23:05:45.060785  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-runner
  148 23:05:45.060916  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-set
  149 23:05:45.061047  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-test-shell
  150 23:05:45.061180  Updating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-install-packages (oe)
  151 23:05:45.061336  Updating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/bin/lava-installed-packages (oe)
  152 23:05:45.061479  Creating /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/environment
  153 23:05:45.061620  LAVA metadata
  154 23:05:45.061697  - LAVA_JOB_ID=12172395
  155 23:05:45.061764  - LAVA_DISPATCHER_IP=192.168.201.1
  156 23:05:45.061871  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 23:05:45.061939  skipped lava-vland-overlay
  158 23:05:45.062014  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 23:05:45.062094  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 23:05:45.062163  skipped lava-multinode-overlay
  161 23:05:45.062249  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 23:05:45.062337  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 23:05:45.062418  Loading test definitions
  164 23:05:45.062512  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
  165 23:05:45.062589  Using /lava-12172395 at stage 0
  166 23:05:45.062909  uuid=12172395_1.5.2.3.1 testdef=None
  167 23:05:45.062998  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 23:05:45.063113  start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
  169 23:05:45.063657  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 23:05:45.063878  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
  172 23:05:45.064506  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 23:05:45.064749  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
  175 23:05:45.065408  runner path: /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/0/tests/0_igt-gpu-panfrost test_uuid 12172395_1.5.2.3.1
  176 23:05:45.065610  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 23:05:45.065856  Creating lava-test-runner.conf files
  179 23:05:45.065939  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172395/lava-overlay-obgifsa3/lava-12172395/0 for stage 0
  180 23:05:45.066057  - 0_igt-gpu-panfrost
  181 23:05:45.066198  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 23:05:45.066321  start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
  183 23:05:45.073855  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 23:05:45.073999  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
  185 23:05:45.074107  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 23:05:45.074196  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 23:05:45.074289  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
  188 23:05:46.498251  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 23:05:46.498634  start: 1.5.4 extract-modules (timeout 00:09:57) [common]
  190 23:05:46.498744  extracting modules file /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172395/extract-overlay-ramdisk-k08_kdsj/ramdisk
  191 23:05:46.742406  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 23:05:46.742600  start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
  193 23:05:46.742696  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172395/compress-overlay-5unl3tp1/overlay-1.5.2.4.tar.gz to ramdisk
  194 23:05:46.742768  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172395/compress-overlay-5unl3tp1/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172395/extract-overlay-ramdisk-k08_kdsj/ramdisk
  195 23:05:46.750260  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 23:05:46.750380  start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
  197 23:05:46.750473  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 23:05:46.750561  start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
  199 23:05:46.750642  Building ramdisk /var/lib/lava/dispatcher/tmp/12172395/extract-overlay-ramdisk-k08_kdsj/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172395/extract-overlay-ramdisk-k08_kdsj/ramdisk
  200 23:05:47.797846  >> 369994 blocks

  201 23:05:53.597601  rename /var/lib/lava/dispatcher/tmp/12172395/extract-overlay-ramdisk-k08_kdsj/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/ramdisk/ramdisk.cpio.gz
  202 23:05:53.598088  end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
  203 23:05:53.598243  start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
  204 23:05:53.598380  start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
  205 23:05:53.598525  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/kernel/Image'
  206 23:06:06.171303  Returned 0 in 12 seconds
  207 23:06:06.271945  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/kernel/image.itb
  208 23:06:07.083826  output: FIT description: Kernel Image image with one or more FDT blobs
  209 23:06:07.084202  output: Created:         Sun Dec  3 23:06:06 2023
  210 23:06:07.084291  output:  Image 0 (kernel-1)
  211 23:06:07.084373  output:   Description:  
  212 23:06:07.084467  output:   Created:      Sun Dec  3 23:06:06 2023
  213 23:06:07.084560  output:   Type:         Kernel Image
  214 23:06:07.084651  output:   Compression:  lzma compressed
  215 23:06:07.084740  output:   Data Size:    11049348 Bytes = 10790.38 KiB = 10.54 MiB
  216 23:06:07.084810  output:   Architecture: AArch64
  217 23:06:07.084887  output:   OS:           Linux
  218 23:06:07.084973  output:   Load Address: 0x00000000
  219 23:06:07.085059  output:   Entry Point:  0x00000000
  220 23:06:07.085144  output:   Hash algo:    crc32
  221 23:06:07.085226  output:   Hash value:   c85ea8f0
  222 23:06:07.085310  output:  Image 1 (fdt-1)
  223 23:06:07.085394  output:   Description:  mt8192-asurada-spherion-r0
  224 23:06:07.085477  output:   Created:      Sun Dec  3 23:06:06 2023
  225 23:06:07.085563  output:   Type:         Flat Device Tree
  226 23:06:07.085666  output:   Compression:  uncompressed
  227 23:06:07.085721  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  228 23:06:07.085775  output:   Architecture: AArch64
  229 23:06:07.085828  output:   Hash algo:    crc32
  230 23:06:07.085881  output:   Hash value:   cc4352de
  231 23:06:07.085934  output:  Image 2 (ramdisk-1)
  232 23:06:07.085987  output:   Description:  unavailable
  233 23:06:07.086040  output:   Created:      Sun Dec  3 23:06:06 2023
  234 23:06:07.086093  output:   Type:         RAMDisk Image
  235 23:06:07.086145  output:   Compression:  Unknown Compression
  236 23:06:07.086198  output:   Data Size:    56438347 Bytes = 55115.57 KiB = 53.82 MiB
  237 23:06:07.086252  output:   Architecture: AArch64
  238 23:06:07.086305  output:   OS:           Linux
  239 23:06:07.086359  output:   Load Address: unavailable
  240 23:06:07.086421  output:   Entry Point:  unavailable
  241 23:06:07.086477  output:   Hash algo:    crc32
  242 23:06:07.086530  output:   Hash value:   99818260
  243 23:06:07.086582  output:  Default Configuration: 'conf-1'
  244 23:06:07.086635  output:  Configuration 0 (conf-1)
  245 23:06:07.086687  output:   Description:  mt8192-asurada-spherion-r0
  246 23:06:07.086740  output:   Kernel:       kernel-1
  247 23:06:07.086792  output:   Init Ramdisk: ramdisk-1
  248 23:06:07.086844  output:   FDT:          fdt-1
  249 23:06:07.086896  output:   Loadables:    kernel-1
  250 23:06:07.086958  output: 
  251 23:06:07.087166  end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
  252 23:06:07.087264  end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
  253 23:06:07.087368  end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
  254 23:06:07.087464  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
  255 23:06:07.087546  No LXC device requested
  256 23:06:07.087628  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 23:06:07.087713  start: 1.7 deploy-device-env (timeout 00:09:37) [common]
  258 23:06:07.087793  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 23:06:07.087875  Checking files for TFTP limit of 4294967296 bytes.
  260 23:06:07.088547  end: 1 tftp-deploy (duration 00:00:23) [common]
  261 23:06:07.088685  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 23:06:07.088804  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 23:06:07.088965  substitutions:
  264 23:06:07.089054  - {DTB}: 12172395/tftp-deploy-usgu8x7g/dtb/mt8192-asurada-spherion-r0.dtb
  265 23:06:07.089151  - {INITRD}: 12172395/tftp-deploy-usgu8x7g/ramdisk/ramdisk.cpio.gz
  266 23:06:07.089239  - {KERNEL}: 12172395/tftp-deploy-usgu8x7g/kernel/Image
  267 23:06:07.089326  - {LAVA_MAC}: None
  268 23:06:07.089411  - {PRESEED_CONFIG}: None
  269 23:06:07.089495  - {PRESEED_LOCAL}: None
  270 23:06:07.089602  - {RAMDISK}: 12172395/tftp-deploy-usgu8x7g/ramdisk/ramdisk.cpio.gz
  271 23:06:07.089690  - {ROOT_PART}: None
  272 23:06:07.089747  - {ROOT}: None
  273 23:06:07.089802  - {SERVER_IP}: 192.168.201.1
  274 23:06:07.089867  - {TEE}: None
  275 23:06:07.089926  Parsed boot commands:
  276 23:06:07.089982  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 23:06:07.090163  Parsed boot commands: tftpboot 192.168.201.1 12172395/tftp-deploy-usgu8x7g/kernel/image.itb 12172395/tftp-deploy-usgu8x7g/kernel/cmdline 
  278 23:06:07.090254  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 23:06:07.090342  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 23:06:07.090437  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 23:06:07.090519  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 23:06:07.090589  Not connected, no need to disconnect.
  283 23:06:07.090662  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 23:06:07.090741  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 23:06:07.090810  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
  286 23:06:07.095074  Setting prompt string to ['lava-test: # ']
  287 23:06:07.095497  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 23:06:07.095603  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 23:06:07.095704  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 23:06:07.095819  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 23:06:07.096179  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
  292 23:06:12.230534  >> Command sent successfully.

  293 23:06:12.232966  Returned 0 in 5 seconds
  294 23:06:12.333342  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 23:06:12.333662  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 23:06:12.333821  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 23:06:12.333916  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 23:06:12.333985  Changing prompt to 'Starting depthcharge on Spherion...'
  300 23:06:12.334053  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 23:06:12.334323  [Enter `^Ec?' for help]

  302 23:06:12.505924  

  303 23:06:12.506098  

  304 23:06:12.506171  F0: 102B 0000

  305 23:06:12.506237  

  306 23:06:12.506298  F3: 1001 0000 [0200]

  307 23:06:12.509429  

  308 23:06:12.509516  F3: 1001 0000

  309 23:06:12.509608  

  310 23:06:12.509714  F7: 102D 0000

  311 23:06:12.509773  

  312 23:06:12.512373  F1: 0000 0000

  313 23:06:12.512456  

  314 23:06:12.512522  V0: 0000 0000 [0001]

  315 23:06:12.512586  

  316 23:06:12.516093  00: 0007 8000

  317 23:06:12.516180  

  318 23:06:12.516246  01: 0000 0000

  319 23:06:12.516309  

  320 23:06:12.519726  BP: 0C00 0209 [0000]

  321 23:06:12.519809  

  322 23:06:12.519874  G0: 1182 0000

  323 23:06:12.519935  

  324 23:06:12.522740  EC: 0000 0021 [4000]

  325 23:06:12.522823  

  326 23:06:12.522888  S7: 0000 0000 [0000]

  327 23:06:12.522949  

  328 23:06:12.526322  CC: 0000 0000 [0001]

  329 23:06:12.526404  

  330 23:06:12.526469  T0: 0000 0040 [010F]

  331 23:06:12.526533  

  332 23:06:12.529237  Jump to BL

  333 23:06:12.529320  

  334 23:06:12.553244  

  335 23:06:12.553333  

  336 23:06:12.553400  

  337 23:06:12.560345  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 23:06:12.564321  ARM64: Exception handlers installed.

  339 23:06:12.567707  ARM64: Testing exception

  340 23:06:12.571207  ARM64: Done test exception

  341 23:06:12.577907  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 23:06:12.588368  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 23:06:12.594850  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 23:06:12.604598  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 23:06:12.611621  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 23:06:12.618021  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 23:06:12.629967  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 23:06:12.636615  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 23:06:12.656232  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 23:06:12.659208  WDT: Last reset was cold boot

  351 23:06:12.662864  SPI1(PAD0) initialized at 2873684 Hz

  352 23:06:12.665811  SPI5(PAD0) initialized at 992727 Hz

  353 23:06:12.669239  VBOOT: Loading verstage.

  354 23:06:12.676119  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 23:06:12.679068  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 23:06:12.682848  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 23:06:12.686189  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 23:06:12.693225  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 23:06:12.700053  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 23:06:12.710933  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  361 23:06:12.711024  

  362 23:06:12.711112  

  363 23:06:12.721530  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 23:06:12.724944  ARM64: Exception handlers installed.

  365 23:06:12.728517  ARM64: Testing exception

  366 23:06:12.728603  ARM64: Done test exception

  367 23:06:12.731758  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 23:06:12.738611  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 23:06:12.752086  Probing TPM: . done!

  370 23:06:12.752171  TPM ready after 0 ms

  371 23:06:12.759019  Connected to device vid:did:rid of 1ae0:0028:00

  372 23:06:12.765653  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  373 23:06:12.826377  Initialized TPM device CR50 revision 0

  374 23:06:12.836762  tlcl_send_startup: Startup return code is 0

  375 23:06:12.836857  TPM: setup succeeded

  376 23:06:12.847890  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 23:06:12.857270  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 23:06:12.871059  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 23:06:12.878103  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 23:06:12.881180  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 23:06:12.888803  in-header: 03 07 00 00 08 00 00 00 

  382 23:06:12.888966  in-data: aa e4 47 04 13 02 00 00 

  383 23:06:12.892344  Chrome EC: UHEPI supported

  384 23:06:12.899617  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 23:06:12.903865  in-header: 03 95 00 00 08 00 00 00 

  386 23:06:12.907454  in-data: 18 20 20 08 00 00 00 00 

  387 23:06:12.907538  Phase 1

  388 23:06:12.911043  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 23:06:12.918594  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 23:06:12.922596  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 23:06:12.926062  Recovery requested (1009000e)

  392 23:06:12.933880  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 23:06:12.939574  tlcl_extend: response is 0

  394 23:06:12.948965  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 23:06:12.954600  tlcl_extend: response is 0

  396 23:06:12.961946  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 23:06:12.981150  read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps

  398 23:06:12.988326  BS: bootblock times (exec / console): total (unknown) / 148 ms

  399 23:06:12.988412  

  400 23:06:12.988477  

  401 23:06:12.997846  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 23:06:13.001377  ARM64: Exception handlers installed.

  403 23:06:13.004967  ARM64: Testing exception

  404 23:06:13.005051  ARM64: Done test exception

  405 23:06:13.026908  pmic_efuse_setting: Set efuses in 11 msecs

  406 23:06:13.030362  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 23:06:13.036806  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 23:06:13.040213  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 23:06:13.047527  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 23:06:13.051636  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 23:06:13.055051  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 23:06:13.058634  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 23:06:13.065995  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 23:06:13.069945  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 23:06:13.073324  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 23:06:13.081089  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 23:06:13.085165  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 23:06:13.088656  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 23:06:13.091909  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 23:06:13.099407  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 23:06:13.103621  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 23:06:13.110818  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 23:06:13.115036  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 23:06:13.122705  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 23:06:13.129678  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 23:06:13.133878  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 23:06:13.137331  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 23:06:13.144553  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 23:06:13.148648  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 23:06:13.155947  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 23:06:13.159410  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 23:06:13.167049  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 23:06:13.171161  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 23:06:13.174386  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 23:06:13.181884  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 23:06:13.185441  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 23:06:13.193104  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 23:06:13.196259  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 23:06:13.200090  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 23:06:13.207655  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 23:06:13.211298  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 23:06:13.214922  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 23:06:13.222358  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 23:06:13.226178  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 23:06:13.229956  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 23:06:13.233385  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 23:06:13.241305  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 23:06:13.244747  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 23:06:13.248269  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 23:06:13.251770  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 23:06:13.255377  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 23:06:13.259456  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 23:06:13.266617  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 23:06:13.269966  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 23:06:13.273605  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 23:06:13.277696  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 23:06:13.281032  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 23:06:13.288226  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 23:06:13.299757  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 23:06:13.303239  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 23:06:13.310305  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 23:06:13.321014  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 23:06:13.325030  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 23:06:13.329201  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 23:06:13.332510  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 23:06:13.340587  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0

  467 23:06:13.343734  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 23:06:13.352485  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  469 23:06:13.355446  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 23:06:13.364977  [RTC]rtc_get_frequency_meter,154: input=15, output=758

  471 23:06:13.374586  [RTC]rtc_get_frequency_meter,154: input=23, output=942

  472 23:06:13.383577  [RTC]rtc_get_frequency_meter,154: input=19, output=850

  473 23:06:13.393436  [RTC]rtc_get_frequency_meter,154: input=17, output=804

  474 23:06:13.403156  [RTC]rtc_get_frequency_meter,154: input=16, output=782

  475 23:06:13.412119  [RTC]rtc_get_frequency_meter,154: input=16, output=782

  476 23:06:13.421613  [RTC]rtc_get_frequency_meter,154: input=17, output=804

  477 23:06:13.425208  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  478 23:06:13.432991  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70

  479 23:06:13.436611  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  480 23:06:13.439968  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  481 23:06:13.443529  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  482 23:06:13.448260  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  483 23:06:13.451112  ADC[4]: Raw value=906203 ID=7

  484 23:06:13.454895  ADC[3]: Raw value=213441 ID=1

  485 23:06:13.454982  RAM Code: 0x71

  486 23:06:13.458890  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  487 23:06:13.462698  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  488 23:06:13.474284  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  489 23:06:13.477870  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  490 23:06:13.480735  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  491 23:06:13.485490  in-header: 03 07 00 00 08 00 00 00 

  492 23:06:13.489340  in-data: aa e4 47 04 13 02 00 00 

  493 23:06:13.492588  Chrome EC: UHEPI supported

  494 23:06:13.499997  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  495 23:06:13.503642  in-header: 03 95 00 00 08 00 00 00 

  496 23:06:13.507289  in-data: 18 20 20 08 00 00 00 00 

  497 23:06:13.510892  MRC: failed to locate region type 0.

  498 23:06:13.514784  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  499 23:06:13.518353  DRAM-K: Running full calibration

  500 23:06:13.526219  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  501 23:06:13.526303  header.status = 0x0

  502 23:06:13.529678  header.version = 0x6 (expected: 0x6)

  503 23:06:13.533071  header.size = 0xd00 (expected: 0xd00)

  504 23:06:13.537339  header.flags = 0x0

  505 23:06:13.540348  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  506 23:06:13.559367  read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps

  507 23:06:13.567055  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  508 23:06:13.567141  dram_init: ddr_geometry: 2

  509 23:06:13.571211  [EMI] MDL number = 2

  510 23:06:13.571294  [EMI] Get MDL freq = 0

  511 23:06:13.575222  dram_init: ddr_type: 0

  512 23:06:13.578983  is_discrete_lpddr4: 1

  513 23:06:13.579066  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  514 23:06:13.579173  

  515 23:06:13.579246  

  516 23:06:13.582636  [Bian_co] ETT version 0.0.0.1

  517 23:06:13.586131   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  518 23:06:13.586214  

  519 23:06:13.593767  dramc_set_vcore_voltage set vcore to 650000

  520 23:06:13.593854  Read voltage for 800, 4

  521 23:06:13.593926  Vio18 = 0

  522 23:06:13.597722  Vcore = 650000

  523 23:06:13.597823  Vdram = 0

  524 23:06:13.597917  Vddq = 0

  525 23:06:13.598005  Vmddr = 0

  526 23:06:13.601642  dram_init: config_dvfs: 1

  527 23:06:13.605616  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  528 23:06:13.613507  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  529 23:06:13.617050  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  530 23:06:13.620602  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  531 23:06:13.624900  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  532 23:06:13.628430  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  533 23:06:13.628538  MEM_TYPE=3, freq_sel=18

  534 23:06:13.632109  sv_algorithm_assistance_LP4_1600 

  535 23:06:13.635621  ============ PULL DRAM RESETB DOWN ============

  536 23:06:13.641841  ========== PULL DRAM RESETB DOWN end =========

  537 23:06:13.645406  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  538 23:06:13.648965  =================================== 

  539 23:06:13.652535  LPDDR4 DRAM CONFIGURATION

  540 23:06:13.652643  =================================== 

  541 23:06:13.656136  EX_ROW_EN[0]    = 0x0

  542 23:06:13.659940  EX_ROW_EN[1]    = 0x0

  543 23:06:13.660013  LP4Y_EN      = 0x0

  544 23:06:13.660097  WORK_FSP     = 0x0

  545 23:06:13.663750  WL           = 0x2

  546 23:06:13.663880  RL           = 0x2

  547 23:06:13.667381  BL           = 0x2

  548 23:06:13.667492  RPST         = 0x0

  549 23:06:13.671163  RD_PRE       = 0x0

  550 23:06:13.671268  WR_PRE       = 0x1

  551 23:06:13.674822  WR_PST       = 0x0

  552 23:06:13.674945  DBI_WR       = 0x0

  553 23:06:13.677935  DBI_RD       = 0x0

  554 23:06:13.678046  OTF          = 0x1

  555 23:06:13.680928  =================================== 

  556 23:06:13.684491  =================================== 

  557 23:06:13.687983  ANA top config

  558 23:06:13.691058  =================================== 

  559 23:06:13.691160  DLL_ASYNC_EN            =  0

  560 23:06:13.693962  ALL_SLAVE_EN            =  1

  561 23:06:13.697839  NEW_RANK_MODE           =  1

  562 23:06:13.700866  DLL_IDLE_MODE           =  1

  563 23:06:13.704471  LP45_APHY_COMB_EN       =  1

  564 23:06:13.704547  TX_ODT_DIS              =  1

  565 23:06:13.707690  NEW_8X_MODE             =  1

  566 23:06:13.711454  =================================== 

  567 23:06:13.715042  =================================== 

  568 23:06:13.718502  data_rate                  = 1600

  569 23:06:13.721734  CKR                        = 1

  570 23:06:13.721806  DQ_P2S_RATIO               = 8

  571 23:06:13.724856  =================================== 

  572 23:06:13.728407  CA_P2S_RATIO               = 8

  573 23:06:13.731590  DQ_CA_OPEN                 = 0

  574 23:06:13.735137  DQ_SEMI_OPEN               = 0

  575 23:06:13.738266  CA_SEMI_OPEN               = 0

  576 23:06:13.741776  CA_FULL_RATE               = 0

  577 23:06:13.741851  DQ_CKDIV4_EN               = 1

  578 23:06:13.745015  CA_CKDIV4_EN               = 1

  579 23:06:13.748517  CA_PREDIV_EN               = 0

  580 23:06:13.751620  PH8_DLY                    = 0

  581 23:06:13.755009  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  582 23:06:13.755081  DQ_AAMCK_DIV               = 4

  583 23:06:13.758593  CA_AAMCK_DIV               = 4

  584 23:06:13.762167  CA_ADMCK_DIV               = 4

  585 23:06:13.765113  DQ_TRACK_CA_EN             = 0

  586 23:06:13.768664  CA_PICK                    = 800

  587 23:06:13.772311  CA_MCKIO                   = 800

  588 23:06:13.775958  MCKIO_SEMI                 = 0

  589 23:06:13.776033  PLL_FREQ                   = 3068

  590 23:06:13.779554  DQ_UI_PI_RATIO             = 32

  591 23:06:13.783644  CA_UI_PI_RATIO             = 0

  592 23:06:13.786775  =================================== 

  593 23:06:13.790317  =================================== 

  594 23:06:13.790428  memory_type:LPDDR4         

  595 23:06:13.794607  GP_NUM     : 10       

  596 23:06:13.794683  SRAM_EN    : 1       

  597 23:06:13.798198  MD32_EN    : 0       

  598 23:06:13.801785  =================================== 

  599 23:06:13.801871  [ANA_INIT] >>>>>>>>>>>>>> 

  600 23:06:13.805342  <<<<<< [CONFIGURE PHASE]: ANA_TX

  601 23:06:13.809419  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  602 23:06:13.812725  =================================== 

  603 23:06:13.816202  data_rate = 1600,PCW = 0X7600

  604 23:06:13.819291  =================================== 

  605 23:06:13.822769  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  606 23:06:13.826384  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  607 23:06:13.832810  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  608 23:06:13.836451  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  609 23:06:13.839914  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  610 23:06:13.843053  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  611 23:06:13.846178  [ANA_INIT] flow start 

  612 23:06:13.849758  [ANA_INIT] PLL >>>>>>>> 

  613 23:06:13.849872  [ANA_INIT] PLL <<<<<<<< 

  614 23:06:13.852990  [ANA_INIT] MIDPI >>>>>>>> 

  615 23:06:13.856248  [ANA_INIT] MIDPI <<<<<<<< 

  616 23:06:13.859730  [ANA_INIT] DLL >>>>>>>> 

  617 23:06:13.859803  [ANA_INIT] flow end 

  618 23:06:13.862979  ============ LP4 DIFF to SE enter ============

  619 23:06:13.869664  ============ LP4 DIFF to SE exit  ============

  620 23:06:13.869778  [ANA_INIT] <<<<<<<<<<<<< 

  621 23:06:13.873286  [Flow] Enable top DCM control >>>>> 

  622 23:06:13.876655  [Flow] Enable top DCM control <<<<< 

  623 23:06:13.879612  Enable DLL master slave shuffle 

  624 23:06:13.886767  ============================================================== 

  625 23:06:13.886852  Gating Mode config

  626 23:06:13.893480  ============================================================== 

  627 23:06:13.893563  Config description: 

  628 23:06:13.903516  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  629 23:06:13.910029  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  630 23:06:13.916623  SELPH_MODE            0: By rank         1: By Phase 

  631 23:06:13.919913  ============================================================== 

  632 23:06:13.923265  GAT_TRACK_EN                 =  1

  633 23:06:13.926603  RX_GATING_MODE               =  2

  634 23:06:13.930032  RX_GATING_TRACK_MODE         =  2

  635 23:06:13.933565  SELPH_MODE                   =  1

  636 23:06:13.936467  PICG_EARLY_EN                =  1

  637 23:06:13.939996  VALID_LAT_VALUE              =  1

  638 23:06:13.946577  ============================================================== 

  639 23:06:13.950613  Enter into Gating configuration >>>> 

  640 23:06:13.953304  Exit from Gating configuration <<<< 

  641 23:06:13.953389  Enter into  DVFS_PRE_config >>>>> 

  642 23:06:13.966749  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  643 23:06:13.969965  Exit from  DVFS_PRE_config <<<<< 

  644 23:06:13.973110  Enter into PICG configuration >>>> 

  645 23:06:13.976588  Exit from PICG configuration <<<< 

  646 23:06:13.976668  [RX_INPUT] configuration >>>>> 

  647 23:06:13.979834  [RX_INPUT] configuration <<<<< 

  648 23:06:13.986505  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  649 23:06:13.990105  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  650 23:06:13.996477  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  651 23:06:14.003481  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  652 23:06:14.010276  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  653 23:06:14.016822  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  654 23:06:14.020183  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  655 23:06:14.023238  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  656 23:06:14.026732  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  657 23:06:14.033313  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  658 23:06:14.036523  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  659 23:06:14.040002  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  660 23:06:14.043323  =================================== 

  661 23:06:14.046984  LPDDR4 DRAM CONFIGURATION

  662 23:06:14.049997  =================================== 

  663 23:06:14.053425  EX_ROW_EN[0]    = 0x0

  664 23:06:14.053508  EX_ROW_EN[1]    = 0x0

  665 23:06:14.056325  LP4Y_EN      = 0x0

  666 23:06:14.056408  WORK_FSP     = 0x0

  667 23:06:14.059662  WL           = 0x2

  668 23:06:14.059744  RL           = 0x2

  669 23:06:14.063275  BL           = 0x2

  670 23:06:14.063358  RPST         = 0x0

  671 23:06:14.066828  RD_PRE       = 0x0

  672 23:06:14.066911  WR_PRE       = 0x1

  673 23:06:14.069718  WR_PST       = 0x0

  674 23:06:14.069800  DBI_WR       = 0x0

  675 23:06:14.073254  DBI_RD       = 0x0

  676 23:06:14.073337  OTF          = 0x1

  677 23:06:14.076778  =================================== 

  678 23:06:14.082992  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  679 23:06:14.086493  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  680 23:06:14.089804  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  681 23:06:14.093097  =================================== 

  682 23:06:14.096397  LPDDR4 DRAM CONFIGURATION

  683 23:06:14.099895  =================================== 

  684 23:06:14.099979  EX_ROW_EN[0]    = 0x10

  685 23:06:14.102960  EX_ROW_EN[1]    = 0x0

  686 23:06:14.106293  LP4Y_EN      = 0x0

  687 23:06:14.106376  WORK_FSP     = 0x0

  688 23:06:14.109925  WL           = 0x2

  689 23:06:14.110044  RL           = 0x2

  690 23:06:14.112976  BL           = 0x2

  691 23:06:14.113058  RPST         = 0x0

  692 23:06:14.116416  RD_PRE       = 0x0

  693 23:06:14.116499  WR_PRE       = 0x1

  694 23:06:14.119383  WR_PST       = 0x0

  695 23:06:14.119467  DBI_WR       = 0x0

  696 23:06:14.123031  DBI_RD       = 0x0

  697 23:06:14.123114  OTF          = 0x1

  698 23:06:14.126620  =================================== 

  699 23:06:14.132570  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  700 23:06:14.137343  nWR fixed to 40

  701 23:06:14.141008  [ModeRegInit_LP4] CH0 RK0

  702 23:06:14.141092  [ModeRegInit_LP4] CH0 RK1

  703 23:06:14.144354  [ModeRegInit_LP4] CH1 RK0

  704 23:06:14.147412  [ModeRegInit_LP4] CH1 RK1

  705 23:06:14.147495  match AC timing 13

  706 23:06:14.154279  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  707 23:06:14.157621  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  708 23:06:14.160968  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  709 23:06:14.167403  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  710 23:06:14.170850  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  711 23:06:14.170933  [EMI DOE] emi_dcm 0

  712 23:06:14.177499  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  713 23:06:14.177616  ==

  714 23:06:14.181004  Dram Type= 6, Freq= 0, CH_0, rank 0

  715 23:06:14.184004  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  716 23:06:14.184103  ==

  717 23:06:14.190827  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  718 23:06:14.197159  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  719 23:06:14.204778  [CA 0] Center 36 (6~67) winsize 62

  720 23:06:14.208213  [CA 1] Center 36 (6~67) winsize 62

  721 23:06:14.211244  [CA 2] Center 34 (4~65) winsize 62

  722 23:06:14.214909  [CA 3] Center 33 (3~64) winsize 62

  723 23:06:14.218326  [CA 4] Center 33 (3~64) winsize 62

  724 23:06:14.221853  [CA 5] Center 32 (3~62) winsize 60

  725 23:06:14.221936  

  726 23:06:14.224996  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  727 23:06:14.225079  

  728 23:06:14.228304  [CATrainingPosCal] consider 1 rank data

  729 23:06:14.231885  u2DelayCellTimex100 = 270/100 ps

  730 23:06:14.234854  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  731 23:06:14.238521  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  732 23:06:14.242142  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  733 23:06:14.248594  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  734 23:06:14.251626  CA4 delay=33 (3~64),Diff = 1 PI (7 cell)

  735 23:06:14.255187  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  736 23:06:14.255270  

  737 23:06:14.258589  CA PerBit enable=1, Macro0, CA PI delay=32

  738 23:06:14.258672  

  739 23:06:14.261750  [CBTSetCACLKResult] CA Dly = 32

  740 23:06:14.261833  CS Dly: 4 (0~35)

  741 23:06:14.261898  ==

  742 23:06:14.265428  Dram Type= 6, Freq= 0, CH_0, rank 1

  743 23:06:14.271600  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  744 23:06:14.271685  ==

  745 23:06:14.275039  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  746 23:06:14.281849  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  747 23:06:14.290912  [CA 0] Center 36 (6~67) winsize 62

  748 23:06:14.294344  [CA 1] Center 36 (6~67) winsize 62

  749 23:06:14.297914  [CA 2] Center 34 (4~65) winsize 62

  750 23:06:14.300897  [CA 3] Center 33 (3~64) winsize 62

  751 23:06:14.304411  [CA 4] Center 32 (2~63) winsize 62

  752 23:06:14.307861  [CA 5] Center 32 (2~63) winsize 62

  753 23:06:14.307944  

  754 23:06:14.311431  [CmdBusTrainingLP45] Vref(ca) range 1: 32

  755 23:06:14.311514  

  756 23:06:14.314235  [CATrainingPosCal] consider 2 rank data

  757 23:06:14.317876  u2DelayCellTimex100 = 270/100 ps

  758 23:06:14.321446  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  759 23:06:14.324694  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  760 23:06:14.331155  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  761 23:06:14.334770  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  762 23:06:14.338083  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  763 23:06:14.341098  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

  764 23:06:14.341210  

  765 23:06:14.344935  CA PerBit enable=1, Macro0, CA PI delay=32

  766 23:06:14.345040  

  767 23:06:14.348409  [CBTSetCACLKResult] CA Dly = 32

  768 23:06:14.348493  CS Dly: 5 (0~37)

  769 23:06:14.348558  

  770 23:06:14.351310  ----->DramcWriteLeveling(PI) begin...

  771 23:06:14.351389  ==

  772 23:06:14.355641  Dram Type= 6, Freq= 0, CH_0, rank 0

  773 23:06:14.359185  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  774 23:06:14.359259  ==

  775 23:06:14.362674  Write leveling (Byte 0): 31 => 31

  776 23:06:14.366791  Write leveling (Byte 1): 31 => 31

  777 23:06:14.370230  DramcWriteLeveling(PI) end<-----

  778 23:06:14.370332  

  779 23:06:14.370434  ==

  780 23:06:14.374122  Dram Type= 6, Freq= 0, CH_0, rank 0

  781 23:06:14.377058  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  782 23:06:14.377132  ==

  783 23:06:14.380485  [Gating] SW mode calibration

  784 23:06:14.388014  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  785 23:06:14.390962  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  786 23:06:14.397884   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  787 23:06:14.400929   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  788 23:06:14.404578   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  789 23:06:14.411181   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  790 23:06:14.414198   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 23:06:14.417642   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 23:06:14.424167   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 23:06:14.427813   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 23:06:14.431427   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 23:06:14.438036   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 23:06:14.440879   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 23:06:14.444149   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 23:06:14.451061   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 23:06:14.454215   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 23:06:14.458020   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 23:06:14.464152   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 23:06:14.467872   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 23:06:14.471342   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  804 23:06:14.474357   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

  805 23:06:14.481302   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  806 23:06:14.484357   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 23:06:14.488097   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 23:06:14.494376   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 23:06:14.497729   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 23:06:14.501087   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 23:06:14.508027   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 23:06:14.511246   0  9  8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)

  813 23:06:14.514679   0  9 12 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)

  814 23:06:14.521150   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  815 23:06:14.524678   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  816 23:06:14.527680   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  817 23:06:14.534643   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 23:06:14.538090   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 23:06:14.541109   0 10  4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

  820 23:06:14.547656   0 10  8 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)

  821 23:06:14.551017   0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

  822 23:06:14.554488   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  823 23:06:14.557774   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  824 23:06:14.564562   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  825 23:06:14.567921   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 23:06:14.571386   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 23:06:14.578038   0 11  4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)

  828 23:06:14.581568   0 11  8 | B1->B0 | 2e2e 3a3a | 0 1 | (0 0) (0 0)

  829 23:06:14.585095   0 11 12 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)

  830 23:06:14.591423   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  831 23:06:14.594897   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  832 23:06:14.597905   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  833 23:06:14.604889   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 23:06:14.608425   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 23:06:14.611990   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  836 23:06:14.614809   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

  837 23:06:14.621676   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

  838 23:06:14.624787   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 23:06:14.628427   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 23:06:14.634870   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 23:06:14.638303   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 23:06:14.641376   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 23:06:14.648477   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 23:06:14.651345   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 23:06:14.654819   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 23:06:14.661187   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 23:06:14.664821   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 23:06:14.668304   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 23:06:14.674606   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 23:06:14.678053   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 23:06:14.681547   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  852 23:06:14.688115   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

  853 23:06:14.691675   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  854 23:06:14.694973  Total UI for P1: 0, mck2ui 16

  855 23:06:14.698398  best dqsien dly found for B0: ( 0, 14,  6)

  856 23:06:14.701880   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  857 23:06:14.704781  Total UI for P1: 0, mck2ui 16

  858 23:06:14.709123  best dqsien dly found for B1: ( 0, 14, 12)

  859 23:06:14.712823  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  860 23:06:14.715642  best DQS1 dly(MCK, UI, PI) = (0, 14, 12)

  861 23:06:14.715713  

  862 23:06:14.719083  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  863 23:06:14.722694  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)

  864 23:06:14.725727  [Gating] SW calibration Done

  865 23:06:14.725796  ==

  866 23:06:14.729153  Dram Type= 6, Freq= 0, CH_0, rank 0

  867 23:06:14.732581  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  868 23:06:14.732681  ==

  869 23:06:14.735915  RX Vref Scan: 0

  870 23:06:14.735987  

  871 23:06:14.738999  RX Vref 0 -> 0, step: 1

  872 23:06:14.739079  

  873 23:06:14.739141  RX Delay -130 -> 252, step: 16

  874 23:06:14.745928  iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240

  875 23:06:14.749473  iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224

  876 23:06:14.752427  iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240

  877 23:06:14.756144  iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240

  878 23:06:14.758994  iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224

  879 23:06:14.765882  iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224

  880 23:06:14.769419  iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208

  881 23:06:14.772393  iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224

  882 23:06:14.775917  iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224

  883 23:06:14.779222  iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224

  884 23:06:14.785779  iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224

  885 23:06:14.789437  iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224

  886 23:06:14.792982  iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224

  887 23:06:14.795904  iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224

  888 23:06:14.799494  iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224

  889 23:06:14.806223  iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240

  890 23:06:14.806300  ==

  891 23:06:14.809122  Dram Type= 6, Freq= 0, CH_0, rank 0

  892 23:06:14.812716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  893 23:06:14.812787  ==

  894 23:06:14.812848  DQS Delay:

  895 23:06:14.816292  DQS0 = 0, DQS1 = 0

  896 23:06:14.816365  DQM Delay:

  897 23:06:14.819724  DQM0 = 89, DQM1 = 84

  898 23:06:14.819793  DQ Delay:

  899 23:06:14.822903  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85

  900 23:06:14.825868  DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93

  901 23:06:14.829373  DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77

  902 23:06:14.832844  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85

  903 23:06:14.832912  

  904 23:06:14.832975  

  905 23:06:14.833033  ==

  906 23:06:14.835791  Dram Type= 6, Freq= 0, CH_0, rank 0

  907 23:06:14.839390  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  908 23:06:14.839462  ==

  909 23:06:14.839523  

  910 23:06:14.842968  

  911 23:06:14.843037  	TX Vref Scan disable

  912 23:06:14.845954   == TX Byte 0 ==

  913 23:06:14.849547  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  914 23:06:14.852826  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  915 23:06:14.856303   == TX Byte 1 ==

  916 23:06:14.859828  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  917 23:06:14.862975  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  918 23:06:14.863044  ==

  919 23:06:14.866164  Dram Type= 6, Freq= 0, CH_0, rank 0

  920 23:06:14.869676  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  921 23:06:14.873108  ==

  922 23:06:14.884144  TX Vref=22, minBit 7, minWin=27, winSum=445

  923 23:06:14.887410  TX Vref=24, minBit 0, minWin=28, winSum=454

  924 23:06:14.890784  TX Vref=26, minBit 8, minWin=27, winSum=453

  925 23:06:14.894068  TX Vref=28, minBit 0, minWin=28, winSum=455

  926 23:06:14.897609  TX Vref=30, minBit 8, minWin=28, winSum=459

  927 23:06:14.901200  TX Vref=32, minBit 10, minWin=27, winSum=454

  928 23:06:14.907711  [TxChooseVref] Worse bit 8, Min win 28, Win sum 459, Final Vref 30

  929 23:06:14.907810  

  930 23:06:14.910708  Final TX Range 1 Vref 30

  931 23:06:14.910782  

  932 23:06:14.910843  ==

  933 23:06:14.914260  Dram Type= 6, Freq= 0, CH_0, rank 0

  934 23:06:14.917457  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  935 23:06:14.917553  ==

  936 23:06:14.917670  

  937 23:06:14.920907  

  938 23:06:14.920979  	TX Vref Scan disable

  939 23:06:14.923891   == TX Byte 0 ==

  940 23:06:14.927762  Update DQ  dly =582 (2 ,1, 38)  DQ  OEN =(1 ,6)

  941 23:06:14.930785  Update DQM dly =582 (2 ,1, 38)  DQM OEN =(1 ,6)

  942 23:06:14.934359   == TX Byte 1 ==

  943 23:06:14.937320  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  944 23:06:14.940916  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  945 23:06:14.944537  

  946 23:06:14.944604  [DATLAT]

  947 23:06:14.944663  Freq=800, CH0 RK0

  948 23:06:14.944720  

  949 23:06:14.947430  DATLAT Default: 0xa

  950 23:06:14.947501  0, 0xFFFF, sum = 0

  951 23:06:14.950969  1, 0xFFFF, sum = 0

  952 23:06:14.951047  2, 0xFFFF, sum = 0

  953 23:06:14.954519  3, 0xFFFF, sum = 0

  954 23:06:14.954594  4, 0xFFFF, sum = 0

  955 23:06:14.957664  5, 0xFFFF, sum = 0

  956 23:06:14.957733  6, 0xFFFF, sum = 0

  957 23:06:14.960974  7, 0xFFFF, sum = 0

  958 23:06:14.964476  8, 0xFFFF, sum = 0

  959 23:06:14.964544  9, 0x0, sum = 1

  960 23:06:14.964603  10, 0x0, sum = 2

  961 23:06:14.967539  11, 0x0, sum = 3

  962 23:06:14.967605  12, 0x0, sum = 4

  963 23:06:14.970985  best_step = 10

  964 23:06:14.971053  

  965 23:06:14.971110  ==

  966 23:06:14.974297  Dram Type= 6, Freq= 0, CH_0, rank 0

  967 23:06:14.977530  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  968 23:06:14.977650  ==

  969 23:06:14.980970  RX Vref Scan: 1

  970 23:06:14.981042  

  971 23:06:14.981106  Set Vref Range= 32 -> 127

  972 23:06:14.981164  

  973 23:06:14.984611  RX Vref 32 -> 127, step: 1

  974 23:06:14.984685  

  975 23:06:14.987487  RX Delay -79 -> 252, step: 8

  976 23:06:14.987560  

  977 23:06:14.990982  Set Vref, RX VrefLevel [Byte0]: 32

  978 23:06:14.994323                           [Byte1]: 32

  979 23:06:14.994391  

  980 23:06:14.997612  Set Vref, RX VrefLevel [Byte0]: 33

  981 23:06:15.000963                           [Byte1]: 33

  982 23:06:15.004527  

  983 23:06:15.004597  Set Vref, RX VrefLevel [Byte0]: 34

  984 23:06:15.007597                           [Byte1]: 34

  985 23:06:15.011759  

  986 23:06:15.011833  Set Vref, RX VrefLevel [Byte0]: 35

  987 23:06:15.015431                           [Byte1]: 35

  988 23:06:15.019478  

  989 23:06:15.019551  Set Vref, RX VrefLevel [Byte0]: 36

  990 23:06:15.022909                           [Byte1]: 36

  991 23:06:15.027572  

  992 23:06:15.027650  Set Vref, RX VrefLevel [Byte0]: 37

  993 23:06:15.030183                           [Byte1]: 37

  994 23:06:15.034505  

  995 23:06:15.034588  Set Vref, RX VrefLevel [Byte0]: 38

  996 23:06:15.038134                           [Byte1]: 38

  997 23:06:15.042951  

  998 23:06:15.043033  Set Vref, RX VrefLevel [Byte0]: 39

  999 23:06:15.045843                           [Byte1]: 39

 1000 23:06:15.050070  

 1001 23:06:15.050152  Set Vref, RX VrefLevel [Byte0]: 40

 1002 23:06:15.053721                           [Byte1]: 40

 1003 23:06:15.057192  

 1004 23:06:15.057295  Set Vref, RX VrefLevel [Byte0]: 41

 1005 23:06:15.060698                           [Byte1]: 41

 1006 23:06:15.064783  

 1007 23:06:15.064853  Set Vref, RX VrefLevel [Byte0]: 42

 1008 23:06:15.068173                           [Byte1]: 42

 1009 23:06:15.072256  

 1010 23:06:15.072351  Set Vref, RX VrefLevel [Byte0]: 43

 1011 23:06:15.075362                           [Byte1]: 43

 1012 23:06:15.079495  

 1013 23:06:15.079595  Set Vref, RX VrefLevel [Byte0]: 44

 1014 23:06:15.083085                           [Byte1]: 44

 1015 23:06:15.087528  

 1016 23:06:15.087623  Set Vref, RX VrefLevel [Byte0]: 45

 1017 23:06:15.090760                           [Byte1]: 45

 1018 23:06:15.094660  

 1019 23:06:15.094733  Set Vref, RX VrefLevel [Byte0]: 46

 1020 23:06:15.098078                           [Byte1]: 46

 1021 23:06:15.102575  

 1022 23:06:15.102657  Set Vref, RX VrefLevel [Byte0]: 47

 1023 23:06:15.105635                           [Byte1]: 47

 1024 23:06:15.110112  

 1025 23:06:15.110198  Set Vref, RX VrefLevel [Byte0]: 48

 1026 23:06:15.113519                           [Byte1]: 48

 1027 23:06:15.117307  

 1028 23:06:15.117387  Set Vref, RX VrefLevel [Byte0]: 49

 1029 23:06:15.120786                           [Byte1]: 49

 1030 23:06:15.124955  

 1031 23:06:15.125041  Set Vref, RX VrefLevel [Byte0]: 50

 1032 23:06:15.128458                           [Byte1]: 50

 1033 23:06:15.132685  

 1034 23:06:15.132766  Set Vref, RX VrefLevel [Byte0]: 51

 1035 23:06:15.136148                           [Byte1]: 51

 1036 23:06:15.140299  

 1037 23:06:15.140380  Set Vref, RX VrefLevel [Byte0]: 52

 1038 23:06:15.143729                           [Byte1]: 52

 1039 23:06:15.147838  

 1040 23:06:15.147918  Set Vref, RX VrefLevel [Byte0]: 53

 1041 23:06:15.150934                           [Byte1]: 53

 1042 23:06:15.155133  

 1043 23:06:15.155212  Set Vref, RX VrefLevel [Byte0]: 54

 1044 23:06:15.158886                           [Byte1]: 54

 1045 23:06:15.162998  

 1046 23:06:15.163078  Set Vref, RX VrefLevel [Byte0]: 55

 1047 23:06:15.166088                           [Byte1]: 55

 1048 23:06:15.170509  

 1049 23:06:15.170589  Set Vref, RX VrefLevel [Byte0]: 56

 1050 23:06:15.173905                           [Byte1]: 56

 1051 23:06:15.177994  

 1052 23:06:15.178074  Set Vref, RX VrefLevel [Byte0]: 57

 1053 23:06:15.181512                           [Byte1]: 57

 1054 23:06:15.185879  

 1055 23:06:15.185960  Set Vref, RX VrefLevel [Byte0]: 58

 1056 23:06:15.188882                           [Byte1]: 58

 1057 23:06:15.193034  

 1058 23:06:15.193114  Set Vref, RX VrefLevel [Byte0]: 59

 1059 23:06:15.196633                           [Byte1]: 59

 1060 23:06:15.200680  

 1061 23:06:15.200760  Set Vref, RX VrefLevel [Byte0]: 60

 1062 23:06:15.204046                           [Byte1]: 60

 1063 23:06:15.207946  

 1064 23:06:15.208025  Set Vref, RX VrefLevel [Byte0]: 61

 1065 23:06:15.211487                           [Byte1]: 61

 1066 23:06:15.215642  

 1067 23:06:15.215723  Set Vref, RX VrefLevel [Byte0]: 62

 1068 23:06:15.219003                           [Byte1]: 62

 1069 23:06:15.223181  

 1070 23:06:15.223262  Set Vref, RX VrefLevel [Byte0]: 63

 1071 23:06:15.226541                           [Byte1]: 63

 1072 23:06:15.230768  

 1073 23:06:15.230863  Set Vref, RX VrefLevel [Byte0]: 64

 1074 23:06:15.234094                           [Byte1]: 64

 1075 23:06:15.238527  

 1076 23:06:15.238608  Set Vref, RX VrefLevel [Byte0]: 65

 1077 23:06:15.241796                           [Byte1]: 65

 1078 23:06:15.245780  

 1079 23:06:15.245861  Set Vref, RX VrefLevel [Byte0]: 66

 1080 23:06:15.249113                           [Byte1]: 66

 1081 23:06:15.253650  

 1082 23:06:15.253731  Set Vref, RX VrefLevel [Byte0]: 67

 1083 23:06:15.257083                           [Byte1]: 67

 1084 23:06:15.261171  

 1085 23:06:15.261251  Set Vref, RX VrefLevel [Byte0]: 68

 1086 23:06:15.264233                           [Byte1]: 68

 1087 23:06:15.268339  

 1088 23:06:15.268419  Set Vref, RX VrefLevel [Byte0]: 69

 1089 23:06:15.271856                           [Byte1]: 69

 1090 23:06:15.275785  

 1091 23:06:15.275865  Set Vref, RX VrefLevel [Byte0]: 70

 1092 23:06:15.279280                           [Byte1]: 70

 1093 23:06:15.283666  

 1094 23:06:15.283751  Set Vref, RX VrefLevel [Byte0]: 71

 1095 23:06:15.286682                           [Byte1]: 71

 1096 23:06:15.291336  

 1097 23:06:15.291416  Set Vref, RX VrefLevel [Byte0]: 72

 1098 23:06:15.294399                           [Byte1]: 72

 1099 23:06:15.298472  

 1100 23:06:15.298552  Set Vref, RX VrefLevel [Byte0]: 73

 1101 23:06:15.302061                           [Byte1]: 73

 1102 23:06:15.306223  

 1103 23:06:15.306303  Set Vref, RX VrefLevel [Byte0]: 74

 1104 23:06:15.309758                           [Byte1]: 74

 1105 23:06:15.313594  

 1106 23:06:15.313689  Set Vref, RX VrefLevel [Byte0]: 75

 1107 23:06:15.316966                           [Byte1]: 75

 1108 23:06:15.321439  

 1109 23:06:15.321541  Set Vref, RX VrefLevel [Byte0]: 76

 1110 23:06:15.324832                           [Byte1]: 76

 1111 23:06:15.328975  

 1112 23:06:15.329056  Final RX Vref Byte 0 = 58 to rank0

 1113 23:06:15.332434  Final RX Vref Byte 1 = 62 to rank0

 1114 23:06:15.335828  Final RX Vref Byte 0 = 58 to rank1

 1115 23:06:15.338829  Final RX Vref Byte 1 = 62 to rank1==

 1116 23:06:15.342304  Dram Type= 6, Freq= 0, CH_0, rank 0

 1117 23:06:15.349111  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1118 23:06:15.349193  ==

 1119 23:06:15.349257  DQS Delay:

 1120 23:06:15.349316  DQS0 = 0, DQS1 = 0

 1121 23:06:15.352104  DQM Delay:

 1122 23:06:15.352184  DQM0 = 92, DQM1 = 84

 1123 23:06:15.355337  DQ Delay:

 1124 23:06:15.358863  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1125 23:06:15.362345  DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100

 1126 23:06:15.362426  DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76

 1127 23:06:15.368914  DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92

 1128 23:06:15.368995  

 1129 23:06:15.369057  

 1130 23:06:15.375818  [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 1131 23:06:15.378890  CH0 RK0: MR19=606, MR18=4B41

 1132 23:06:15.385705  CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64

 1133 23:06:15.385789  

 1134 23:06:15.389289  ----->DramcWriteLeveling(PI) begin...

 1135 23:06:15.389385  ==

 1136 23:06:15.392275  Dram Type= 6, Freq= 0, CH_0, rank 1

 1137 23:06:15.395861  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1138 23:06:15.395942  ==

 1139 23:06:15.398724  Write leveling (Byte 0): 35 => 35

 1140 23:06:15.402217  Write leveling (Byte 1): 29 => 29

 1141 23:06:15.405917  DramcWriteLeveling(PI) end<-----

 1142 23:06:15.405997  

 1143 23:06:15.406060  ==

 1144 23:06:15.408886  Dram Type= 6, Freq= 0, CH_0, rank 1

 1145 23:06:15.412568  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1146 23:06:15.412650  ==

 1147 23:06:15.415358  [Gating] SW mode calibration

 1148 23:06:15.422431  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1149 23:06:15.469693  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1150 23:06:15.469788   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1151 23:06:15.470042   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1152 23:06:15.470110   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1153 23:06:15.470815   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1154 23:06:15.471080   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1155 23:06:15.471155   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1156 23:06:15.471217   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1157 23:06:15.471287   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1158 23:06:15.471361   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1159 23:06:15.513751   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1160 23:06:15.513839   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1161 23:06:15.514130   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1162 23:06:15.514223   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1163 23:06:15.514300   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 23:06:15.514389   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 23:06:15.514476   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 23:06:15.514592   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 23:06:15.514880   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1168 23:06:15.515436   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1169 23:06:15.557877   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1170 23:06:15.557968   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 23:06:15.558219   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 23:06:15.558287   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 23:06:15.558358   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 23:06:15.558604   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 23:06:15.558684   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1176 23:06:15.558757   0  9  8 | B1->B0 | 2d2d 2727 | 1 1 | (1 1) (1 1)

 1177 23:06:15.559015   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1178 23:06:15.559115   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1179 23:06:15.568431   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1180 23:06:15.568612   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1181 23:06:15.571428   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1182 23:06:15.575070   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1183 23:06:15.578042   0 10  4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1184 23:06:15.581391   0 10  8 | B1->B0 | 2b2b 2828 | 0 0 | (0 1) (0 0)

 1185 23:06:15.584750   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1186 23:06:15.591871   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1187 23:06:15.595022   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1188 23:06:15.599129   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1189 23:06:15.602179   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1190 23:06:15.609487   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1191 23:06:15.613851   0 11  4 | B1->B0 | 2727 2525 | 1 0 | (0 0) (0 0)

 1192 23:06:15.616815   0 11  8 | B1->B0 | 3d3d 3a3a | 0 1 | (0 0) (0 0)

 1193 23:06:15.620352   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1194 23:06:15.627538   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1195 23:06:15.631161   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1196 23:06:15.633976   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1197 23:06:15.637317   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1198 23:06:15.644149   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1199 23:06:15.647593   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1200 23:06:15.651159   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1201 23:06:15.657762   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1202 23:06:15.660942   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1203 23:06:15.664242   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1204 23:06:15.670819   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1205 23:06:15.674242   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1206 23:06:15.677714   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1207 23:06:15.684194   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1208 23:06:15.687651   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1209 23:06:15.691183   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1210 23:06:15.697467   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 23:06:15.700974   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 23:06:15.704643   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 23:06:15.710621   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1214 23:06:15.714304   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1215 23:06:15.717432   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1216 23:06:15.721160   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1217 23:06:15.727661   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1218 23:06:15.731221  Total UI for P1: 0, mck2ui 16

 1219 23:06:15.734101  best dqsien dly found for B0: ( 0, 14,  6)

 1220 23:06:15.734182  Total UI for P1: 0, mck2ui 16

 1221 23:06:15.741213  best dqsien dly found for B1: ( 0, 14,  6)

 1222 23:06:15.744598  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

 1223 23:06:15.747811  best DQS1 dly(MCK, UI, PI) = (0, 14, 6)

 1224 23:06:15.747892  

 1225 23:06:15.751229  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1226 23:06:15.754091  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)

 1227 23:06:15.757740  [Gating] SW calibration Done

 1228 23:06:15.757821  ==

 1229 23:06:15.761254  Dram Type= 6, Freq= 0, CH_0, rank 1

 1230 23:06:15.764235  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1231 23:06:15.764317  ==

 1232 23:06:15.767647  RX Vref Scan: 0

 1233 23:06:15.767736  

 1234 23:06:15.767804  RX Vref 0 -> 0, step: 1

 1235 23:06:15.767863  

 1236 23:06:15.771010  RX Delay -130 -> 252, step: 16

 1237 23:06:15.774298  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1238 23:06:15.781319  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1239 23:06:15.784251  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1240 23:06:15.787890  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1241 23:06:15.791299  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1242 23:06:15.794263  iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240

 1243 23:06:15.800986  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1244 23:06:15.804404  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1245 23:06:15.807848  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1246 23:06:15.811392  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1247 23:06:15.814824  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1248 23:06:15.820948  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1249 23:06:15.824460  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1250 23:06:15.827859  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1251 23:06:15.831164  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1252 23:06:15.834499  iDelay=222, Bit 15, Center 85 (-18 ~ 189) 208

 1253 23:06:15.837971  ==

 1254 23:06:15.838052  Dram Type= 6, Freq= 0, CH_0, rank 1

 1255 23:06:15.844873  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1256 23:06:15.844955  ==

 1257 23:06:15.845019  DQS Delay:

 1258 23:06:15.847807  DQS0 = 0, DQS1 = 0

 1259 23:06:15.847888  DQM Delay:

 1260 23:06:15.851181  DQM0 = 91, DQM1 = 82

 1261 23:06:15.851262  DQ Delay:

 1262 23:06:15.854446  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

 1263 23:06:15.857634  DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101

 1264 23:06:15.861271  DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77

 1265 23:06:15.864567  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85

 1266 23:06:15.864648  

 1267 23:06:15.864711  

 1268 23:06:15.864770  ==

 1269 23:06:15.868008  Dram Type= 6, Freq= 0, CH_0, rank 1

 1270 23:06:15.871118  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1271 23:06:15.871199  ==

 1272 23:06:15.871264  

 1273 23:06:15.871323  

 1274 23:06:15.874751  	TX Vref Scan disable

 1275 23:06:15.878114   == TX Byte 0 ==

 1276 23:06:15.881791  Update DQ  dly =586 (2 ,2, 10)  DQ  OEN =(1 ,7)

 1277 23:06:15.884511  Update DQM dly =586 (2 ,2, 10)  DQM OEN =(1 ,7)

 1278 23:06:15.888387   == TX Byte 1 ==

 1279 23:06:15.891342  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1280 23:06:15.894908  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1281 23:06:15.894989  ==

 1282 23:06:15.898329  Dram Type= 6, Freq= 0, CH_0, rank 1

 1283 23:06:15.901847  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1284 23:06:15.901928  ==

 1285 23:06:15.916186  TX Vref=22, minBit 8, minWin=27, winSum=446

 1286 23:06:15.919782  TX Vref=24, minBit 1, minWin=28, winSum=452

 1287 23:06:15.923334  TX Vref=26, minBit 1, minWin=28, winSum=455

 1288 23:06:15.926378  TX Vref=28, minBit 1, minWin=28, winSum=457

 1289 23:06:15.929916  TX Vref=30, minBit 4, minWin=28, winSum=457

 1290 23:06:15.932943  TX Vref=32, minBit 2, minWin=28, winSum=453

 1291 23:06:15.939412  [TxChooseVref] Worse bit 1, Min win 28, Win sum 457, Final Vref 28

 1292 23:06:15.939493  

 1293 23:06:15.942821  Final TX Range 1 Vref 28

 1294 23:06:15.942903  

 1295 23:06:15.942966  ==

 1296 23:06:15.946707  Dram Type= 6, Freq= 0, CH_0, rank 1

 1297 23:06:15.949756  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1298 23:06:15.949837  ==

 1299 23:06:15.949901  

 1300 23:06:15.949959  

 1301 23:06:15.952817  	TX Vref Scan disable

 1302 23:06:15.956514   == TX Byte 0 ==

 1303 23:06:15.959846  Update DQ  dly =586 (2 ,2, 10)  DQ  OEN =(1 ,7)

 1304 23:06:15.963098  Update DQM dly =586 (2 ,2, 10)  DQM OEN =(1 ,7)

 1305 23:06:15.966440   == TX Byte 1 ==

 1306 23:06:15.969451  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1307 23:06:15.973025  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1308 23:06:15.976612  

 1309 23:06:15.976693  [DATLAT]

 1310 23:06:15.976755  Freq=800, CH0 RK1

 1311 23:06:15.976814  

 1312 23:06:15.979436  DATLAT Default: 0xa

 1313 23:06:15.979515  0, 0xFFFF, sum = 0

 1314 23:06:15.982976  1, 0xFFFF, sum = 0

 1315 23:06:15.983057  2, 0xFFFF, sum = 0

 1316 23:06:15.986642  3, 0xFFFF, sum = 0

 1317 23:06:15.986724  4, 0xFFFF, sum = 0

 1318 23:06:15.989473  5, 0xFFFF, sum = 0

 1319 23:06:15.989558  6, 0xFFFF, sum = 0

 1320 23:06:15.993044  7, 0xFFFF, sum = 0

 1321 23:06:15.996285  8, 0xFFFF, sum = 0

 1322 23:06:15.996367  9, 0x0, sum = 1

 1323 23:06:15.996431  10, 0x0, sum = 2

 1324 23:06:15.999763  11, 0x0, sum = 3

 1325 23:06:15.999844  12, 0x0, sum = 4

 1326 23:06:16.003031  best_step = 10

 1327 23:06:16.003111  

 1328 23:06:16.003173  ==

 1329 23:06:16.006518  Dram Type= 6, Freq= 0, CH_0, rank 1

 1330 23:06:16.009884  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1331 23:06:16.009965  ==

 1332 23:06:16.012793  RX Vref Scan: 0

 1333 23:06:16.012872  

 1334 23:06:16.012935  RX Vref 0 -> 0, step: 1

 1335 23:06:16.012993  

 1336 23:06:16.016147  RX Delay -79 -> 252, step: 8

 1337 23:06:16.023107  iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224

 1338 23:06:16.026711  iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208

 1339 23:06:16.029433  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1340 23:06:16.033048  iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224

 1341 23:06:16.036696  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1342 23:06:16.043180  iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224

 1343 23:06:16.046228  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1344 23:06:16.049663  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1345 23:06:16.053309  iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216

 1346 23:06:16.056382  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1347 23:06:16.062969  iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216

 1348 23:06:16.066576  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1349 23:06:16.069513  iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216

 1350 23:06:16.072864  iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208

 1351 23:06:16.076096  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1352 23:06:16.083375  iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216

 1353 23:06:16.083456  ==

 1354 23:06:16.086223  Dram Type= 6, Freq= 0, CH_0, rank 1

 1355 23:06:16.089793  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1356 23:06:16.089875  ==

 1357 23:06:16.089940  DQS Delay:

 1358 23:06:16.092753  DQS0 = 0, DQS1 = 0

 1359 23:06:16.092833  DQM Delay:

 1360 23:06:16.096373  DQM0 = 92, DQM1 = 84

 1361 23:06:16.096454  DQ Delay:

 1362 23:06:16.099937  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1363 23:06:16.102735  DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100

 1364 23:06:16.106233  DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76

 1365 23:06:16.109685  DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92

 1366 23:06:16.109766  

 1367 23:06:16.109830  

 1368 23:06:16.116642  [DQSOSCAuto] RK1, (LSB)MR18= 0x3f10, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 1369 23:06:16.119528  CH0 RK1: MR19=606, MR18=3F10

 1370 23:06:16.126355  CH0_RK1: MR19=0x606, MR18=0x3F10, DQSOSC=393, MR23=63, INC=95, DEC=63

 1371 23:06:16.129906  [RxdqsGatingPostProcess] freq 800

 1372 23:06:16.136441  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1373 23:06:16.139462  Pre-setting of DQS Precalculation

 1374 23:06:16.142889  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1375 23:06:16.142971  ==

 1376 23:06:16.146420  Dram Type= 6, Freq= 0, CH_1, rank 0

 1377 23:06:16.149913  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1378 23:06:16.149994  ==

 1379 23:06:16.156622  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1380 23:06:16.163002  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1381 23:06:16.171239  [CA 0] Center 36 (6~67) winsize 62

 1382 23:06:16.174559  [CA 1] Center 36 (6~67) winsize 62

 1383 23:06:16.177696  [CA 2] Center 35 (5~66) winsize 62

 1384 23:06:16.181351  [CA 3] Center 34 (4~65) winsize 62

 1385 23:06:16.184634  [CA 4] Center 35 (5~65) winsize 61

 1386 23:06:16.187649  [CA 5] Center 34 (4~64) winsize 61

 1387 23:06:16.187733  

 1388 23:06:16.191232  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1389 23:06:16.191355  

 1390 23:06:16.194924  [CATrainingPosCal] consider 1 rank data

 1391 23:06:16.197955  u2DelayCellTimex100 = 270/100 ps

 1392 23:06:16.201617  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1393 23:06:16.204933  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1394 23:06:16.207965  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1395 23:06:16.214479  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1396 23:06:16.217969  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1397 23:06:16.221177  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1398 23:06:16.221258  

 1399 23:06:16.224525  CA PerBit enable=1, Macro0, CA PI delay=34

 1400 23:06:16.224607  

 1401 23:06:16.227808  [CBTSetCACLKResult] CA Dly = 34

 1402 23:06:16.227889  CS Dly: 6 (0~37)

 1403 23:06:16.227955  ==

 1404 23:06:16.231673  Dram Type= 6, Freq= 0, CH_1, rank 1

 1405 23:06:16.238288  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1406 23:06:16.238373  ==

 1407 23:06:16.241120  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1408 23:06:16.248218  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1409 23:06:16.257301  [CA 0] Center 36 (6~67) winsize 62

 1410 23:06:16.260817  [CA 1] Center 37 (6~68) winsize 63

 1411 23:06:16.264587  [CA 2] Center 35 (4~66) winsize 63

 1412 23:06:16.268131  [CA 3] Center 34 (4~65) winsize 62

 1413 23:06:16.272195  [CA 4] Center 35 (4~66) winsize 63

 1414 23:06:16.275883  [CA 5] Center 34 (4~65) winsize 62

 1415 23:06:16.275965  

 1416 23:06:16.279472  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1417 23:06:16.279553  

 1418 23:06:16.282974  [CATrainingPosCal] consider 2 rank data

 1419 23:06:16.287149  u2DelayCellTimex100 = 270/100 ps

 1420 23:06:16.287231  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1421 23:06:16.294434  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1422 23:06:16.294516  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1423 23:06:16.298207  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1424 23:06:16.301740  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1425 23:06:16.307928  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1426 23:06:16.308011  

 1427 23:06:16.311490  CA PerBit enable=1, Macro0, CA PI delay=34

 1428 23:06:16.311573  

 1429 23:06:16.314793  [CBTSetCACLKResult] CA Dly = 34

 1430 23:06:16.314869  CS Dly: 6 (0~38)

 1431 23:06:16.314933  

 1432 23:06:16.318611  ----->DramcWriteLeveling(PI) begin...

 1433 23:06:16.318684  ==

 1434 23:06:16.321385  Dram Type= 6, Freq= 0, CH_1, rank 0

 1435 23:06:16.324940  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1436 23:06:16.328522  ==

 1437 23:06:16.328592  Write leveling (Byte 0): 28 => 28

 1438 23:06:16.331764  Write leveling (Byte 1): 26 => 26

 1439 23:06:16.335056  DramcWriteLeveling(PI) end<-----

 1440 23:06:16.335131  

 1441 23:06:16.335194  ==

 1442 23:06:16.338365  Dram Type= 6, Freq= 0, CH_1, rank 0

 1443 23:06:16.344941  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1444 23:06:16.345017  ==

 1445 23:06:16.345080  [Gating] SW mode calibration

 1446 23:06:16.354904  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1447 23:06:16.358495  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1448 23:06:16.361493   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1449 23:06:16.368671   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1450 23:06:16.371701   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1451 23:06:16.375314   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1452 23:06:16.381822   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1453 23:06:16.384843   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1454 23:06:16.388560   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1455 23:06:16.395242   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1456 23:06:16.398279   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1457 23:06:16.401513   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1458 23:06:16.408578   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1459 23:06:16.411847   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1460 23:06:16.415101   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 23:06:16.421884   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 23:06:16.425195   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 23:06:16.428188   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 23:06:16.435032   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1465 23:06:16.438383   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)

 1466 23:06:16.441977   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 23:06:16.444907   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 23:06:16.451733   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 23:06:16.455084   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 23:06:16.458700   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 23:06:16.465075   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 23:06:16.468714   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 23:06:16.471613   0  9  4 | B1->B0 | 2323 2626 | 1 1 | (1 1) (1 1)

 1474 23:06:16.478776   0  9  8 | B1->B0 | 2f2f 3434 | 1 0 | (1 1) (0 0)

 1475 23:06:16.481628   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1476 23:06:16.485244   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1477 23:06:16.491807   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1478 23:06:16.495427   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1479 23:06:16.498356   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1480 23:06:16.505511   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 1481 23:06:16.508500   0 10  4 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 0)

 1482 23:06:16.512127   0 10  8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (1 0)

 1483 23:06:16.515528   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1484 23:06:16.522548   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1485 23:06:16.525514   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1486 23:06:16.529033   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1487 23:06:16.535169   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1488 23:06:16.538879   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1489 23:06:16.542043   0 11  4 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)

 1490 23:06:16.548945   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1491 23:06:16.552137   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1492 23:06:16.555310   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1493 23:06:16.562026   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1494 23:06:16.565812   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1495 23:06:16.568953   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1496 23:06:16.575392   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1497 23:06:16.578781   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1498 23:06:16.582467   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1499 23:06:16.589076   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1500 23:06:16.592168   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1501 23:06:16.595664   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1502 23:06:16.599243   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1503 23:06:16.605884   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1504 23:06:16.608727   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1505 23:06:16.612402   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1506 23:06:16.619026   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 23:06:16.622319   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 23:06:16.625883   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 23:06:16.632380   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 23:06:16.635372   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 23:06:16.638914   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 23:06:16.645512   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1513 23:06:16.649161   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 1514 23:06:16.652124  Total UI for P1: 0, mck2ui 16

 1515 23:06:16.655882  best dqsien dly found for B0: ( 0, 14,  2)

 1516 23:06:16.659037   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1517 23:06:16.662239  Total UI for P1: 0, mck2ui 16

 1518 23:06:16.665825  best dqsien dly found for B1: ( 0, 14,  2)

 1519 23:06:16.669321  best DQS0 dly(MCK, UI, PI) = (0, 14, 2)

 1520 23:06:16.672621  best DQS1 dly(MCK, UI, PI) = (0, 14, 2)

 1521 23:06:16.672703  

 1522 23:06:16.675648  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1523 23:06:16.682696  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)

 1524 23:06:16.682778  [Gating] SW calibration Done

 1525 23:06:16.682843  ==

 1526 23:06:16.685856  Dram Type= 6, Freq= 0, CH_1, rank 0

 1527 23:06:16.692506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1528 23:06:16.692590  ==

 1529 23:06:16.692655  RX Vref Scan: 0

 1530 23:06:16.692716  

 1531 23:06:16.695630  RX Vref 0 -> 0, step: 1

 1532 23:06:16.695706  

 1533 23:06:16.698854  RX Delay -130 -> 252, step: 16

 1534 23:06:16.702468  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1535 23:06:16.706110  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1536 23:06:16.709003  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1537 23:06:16.712669  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1538 23:06:16.719201  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1539 23:06:16.722723  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1540 23:06:16.725840  iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224

 1541 23:06:16.729320  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1542 23:06:16.732745  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1543 23:06:16.739400  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1544 23:06:16.742360  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1545 23:06:16.745956  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1546 23:06:16.749566  iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208

 1547 23:06:16.752693  iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208

 1548 23:06:16.759271  iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208

 1549 23:06:16.762788  iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208

 1550 23:06:16.762870  ==

 1551 23:06:16.766023  Dram Type= 6, Freq= 0, CH_1, rank 0

 1552 23:06:16.769025  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1553 23:06:16.769107  ==

 1554 23:06:16.772503  DQS Delay:

 1555 23:06:16.772584  DQS0 = 0, DQS1 = 0

 1556 23:06:16.772649  DQM Delay:

 1557 23:06:16.775739  DQM0 = 94, DQM1 = 91

 1558 23:06:16.775820  DQ Delay:

 1559 23:06:16.779393  DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93

 1560 23:06:16.782695  DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93

 1561 23:06:16.785934  DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85

 1562 23:06:16.789617  DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101

 1563 23:06:16.789699  

 1564 23:06:16.789763  

 1565 23:06:16.792326  ==

 1566 23:06:16.792407  Dram Type= 6, Freq= 0, CH_1, rank 0

 1567 23:06:16.799604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1568 23:06:16.799687  ==

 1569 23:06:16.799752  

 1570 23:06:16.799812  

 1571 23:06:16.799870  	TX Vref Scan disable

 1572 23:06:16.803353   == TX Byte 0 ==

 1573 23:06:16.806432  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1574 23:06:16.809634  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1575 23:06:16.813099   == TX Byte 1 ==

 1576 23:06:16.816291  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1577 23:06:16.820058  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1578 23:06:16.823067  ==

 1579 23:06:16.826696  Dram Type= 6, Freq= 0, CH_1, rank 0

 1580 23:06:16.829565  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1581 23:06:16.829687  ==

 1582 23:06:16.842957  TX Vref=22, minBit 3, minWin=26, winSum=439

 1583 23:06:16.846560  TX Vref=24, minBit 0, minWin=27, winSum=445

 1584 23:06:16.850058  TX Vref=26, minBit 3, minWin=26, winSum=445

 1585 23:06:16.853755  TX Vref=28, minBit 1, minWin=27, winSum=446

 1586 23:06:16.856712  TX Vref=30, minBit 2, minWin=27, winSum=450

 1587 23:06:16.860337  TX Vref=32, minBit 0, minWin=27, winSum=446

 1588 23:06:16.866710  [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 30

 1589 23:06:16.866792  

 1590 23:06:16.870059  Final TX Range 1 Vref 30

 1591 23:06:16.870141  

 1592 23:06:16.870205  ==

 1593 23:06:16.873640  Dram Type= 6, Freq= 0, CH_1, rank 0

 1594 23:06:16.876732  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1595 23:06:16.876815  ==

 1596 23:06:16.876879  

 1597 23:06:16.876939  

 1598 23:06:16.880289  	TX Vref Scan disable

 1599 23:06:16.883463   == TX Byte 0 ==

 1600 23:06:16.886793  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1601 23:06:16.890041  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1602 23:06:16.893520   == TX Byte 1 ==

 1603 23:06:16.896648  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1604 23:06:16.900252  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1605 23:06:16.900334  

 1606 23:06:16.900398  [DATLAT]

 1607 23:06:16.903734  Freq=800, CH1 RK0

 1608 23:06:16.903816  

 1609 23:06:16.906762  DATLAT Default: 0xa

 1610 23:06:16.906844  0, 0xFFFF, sum = 0

 1611 23:06:16.910153  1, 0xFFFF, sum = 0

 1612 23:06:16.910236  2, 0xFFFF, sum = 0

 1613 23:06:16.913499  3, 0xFFFF, sum = 0

 1614 23:06:16.913589  4, 0xFFFF, sum = 0

 1615 23:06:16.916854  5, 0xFFFF, sum = 0

 1616 23:06:16.916936  6, 0xFFFF, sum = 0

 1617 23:06:16.920241  7, 0xFFFF, sum = 0

 1618 23:06:16.920317  8, 0xFFFF, sum = 0

 1619 23:06:16.923793  9, 0x0, sum = 1

 1620 23:06:16.923865  10, 0x0, sum = 2

 1621 23:06:16.927115  11, 0x0, sum = 3

 1622 23:06:16.927185  12, 0x0, sum = 4

 1623 23:06:16.927246  best_step = 10

 1624 23:06:16.927302  

 1625 23:06:16.930204  ==

 1626 23:06:16.933722  Dram Type= 6, Freq= 0, CH_1, rank 0

 1627 23:06:16.936757  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1628 23:06:16.936831  ==

 1629 23:06:16.936892  RX Vref Scan: 1

 1630 23:06:16.936951  

 1631 23:06:16.940130  Set Vref Range= 32 -> 127

 1632 23:06:16.940200  

 1633 23:06:16.943623  RX Vref 32 -> 127, step: 1

 1634 23:06:16.943696  

 1635 23:06:16.947045  RX Delay -79 -> 252, step: 8

 1636 23:06:16.947118  

 1637 23:06:16.949986  Set Vref, RX VrefLevel [Byte0]: 32

 1638 23:06:16.953435                           [Byte1]: 32

 1639 23:06:16.953508  

 1640 23:06:16.956966  Set Vref, RX VrefLevel [Byte0]: 33

 1641 23:06:16.960047                           [Byte1]: 33

 1642 23:06:16.960115  

 1643 23:06:16.963789  Set Vref, RX VrefLevel [Byte0]: 34

 1644 23:06:16.966586                           [Byte1]: 34

 1645 23:06:16.970146  

 1646 23:06:16.970214  Set Vref, RX VrefLevel [Byte0]: 35

 1647 23:06:16.973563                           [Byte1]: 35

 1648 23:06:16.977569  

 1649 23:06:16.977650  Set Vref, RX VrefLevel [Byte0]: 36

 1650 23:06:16.981266                           [Byte1]: 36

 1651 23:06:16.985446  

 1652 23:06:16.985516  Set Vref, RX VrefLevel [Byte0]: 37

 1653 23:06:16.988310                           [Byte1]: 37

 1654 23:06:16.992540  

 1655 23:06:16.992609  Set Vref, RX VrefLevel [Byte0]: 38

 1656 23:06:16.995841                           [Byte1]: 38

 1657 23:06:17.000210  

 1658 23:06:17.000281  Set Vref, RX VrefLevel [Byte0]: 39

 1659 23:06:17.003755                           [Byte1]: 39

 1660 23:06:17.007847  

 1661 23:06:17.007923  Set Vref, RX VrefLevel [Byte0]: 40

 1662 23:06:17.011078                           [Byte1]: 40

 1663 23:06:17.015151  

 1664 23:06:17.015224  Set Vref, RX VrefLevel [Byte0]: 41

 1665 23:06:17.018711                           [Byte1]: 41

 1666 23:06:17.022885  

 1667 23:06:17.022961  Set Vref, RX VrefLevel [Byte0]: 42

 1668 23:06:17.026101                           [Byte1]: 42

 1669 23:06:17.030694  

 1670 23:06:17.030768  Set Vref, RX VrefLevel [Byte0]: 43

 1671 23:06:17.033545                           [Byte1]: 43

 1672 23:06:17.038303  

 1673 23:06:17.038377  Set Vref, RX VrefLevel [Byte0]: 44

 1674 23:06:17.041500                           [Byte1]: 44

 1675 23:06:17.045294  

 1676 23:06:17.045367  Set Vref, RX VrefLevel [Byte0]: 45

 1677 23:06:17.048663                           [Byte1]: 45

 1678 23:06:17.053224  

 1679 23:06:17.053301  Set Vref, RX VrefLevel [Byte0]: 46

 1680 23:06:17.056360                           [Byte1]: 46

 1681 23:06:17.060849  

 1682 23:06:17.060922  Set Vref, RX VrefLevel [Byte0]: 47

 1683 23:06:17.063749                           [Byte1]: 47

 1684 23:06:17.068453  

 1685 23:06:17.068532  Set Vref, RX VrefLevel [Byte0]: 48

 1686 23:06:17.071598                           [Byte1]: 48

 1687 23:06:17.075602  

 1688 23:06:17.075675  Set Vref, RX VrefLevel [Byte0]: 49

 1689 23:06:17.079091                           [Byte1]: 49

 1690 23:06:17.083268  

 1691 23:06:17.083367  Set Vref, RX VrefLevel [Byte0]: 50

 1692 23:06:17.086891                           [Byte1]: 50

 1693 23:06:17.091121  

 1694 23:06:17.091196  Set Vref, RX VrefLevel [Byte0]: 51

 1695 23:06:17.094070                           [Byte1]: 51

 1696 23:06:17.098192  

 1697 23:06:17.098269  Set Vref, RX VrefLevel [Byte0]: 52

 1698 23:06:17.101673                           [Byte1]: 52

 1699 23:06:17.105839  

 1700 23:06:17.105915  Set Vref, RX VrefLevel [Byte0]: 53

 1701 23:06:17.109394                           [Byte1]: 53

 1702 23:06:17.113389  

 1703 23:06:17.113467  Set Vref, RX VrefLevel [Byte0]: 54

 1704 23:06:17.116850                           [Byte1]: 54

 1705 23:06:17.121040  

 1706 23:06:17.121114  Set Vref, RX VrefLevel [Byte0]: 55

 1707 23:06:17.124698                           [Byte1]: 55

 1708 23:06:17.128410  

 1709 23:06:17.128493  Set Vref, RX VrefLevel [Byte0]: 56

 1710 23:06:17.131876                           [Byte1]: 56

 1711 23:06:17.135895  

 1712 23:06:17.135975  Set Vref, RX VrefLevel [Byte0]: 57

 1713 23:06:17.139526                           [Byte1]: 57

 1714 23:06:17.143639  

 1715 23:06:17.143719  Set Vref, RX VrefLevel [Byte0]: 58

 1716 23:06:17.147206                           [Byte1]: 58

 1717 23:06:17.151169  

 1718 23:06:17.151250  Set Vref, RX VrefLevel [Byte0]: 59

 1719 23:06:17.154327                           [Byte1]: 59

 1720 23:06:17.158655  

 1721 23:06:17.158736  Set Vref, RX VrefLevel [Byte0]: 60

 1722 23:06:17.162252                           [Byte1]: 60

 1723 23:06:17.166794  

 1724 23:06:17.166876  Set Vref, RX VrefLevel [Byte0]: 61

 1725 23:06:17.169898                           [Byte1]: 61

 1726 23:06:17.174110  

 1727 23:06:17.174191  Set Vref, RX VrefLevel [Byte0]: 62

 1728 23:06:17.177490                           [Byte1]: 62

 1729 23:06:17.181460  

 1730 23:06:17.181558  Set Vref, RX VrefLevel [Byte0]: 63

 1731 23:06:17.185044                           [Byte1]: 63

 1732 23:06:17.189141  

 1733 23:06:17.189222  Set Vref, RX VrefLevel [Byte0]: 64

 1734 23:06:17.192074                           [Byte1]: 64

 1735 23:06:17.196816  

 1736 23:06:17.196897  Set Vref, RX VrefLevel [Byte0]: 65

 1737 23:06:17.199723                           [Byte1]: 65

 1738 23:06:17.203852  

 1739 23:06:17.203934  Set Vref, RX VrefLevel [Byte0]: 66

 1740 23:06:17.207518                           [Byte1]: 66

 1741 23:06:17.211442  

 1742 23:06:17.211522  Set Vref, RX VrefLevel [Byte0]: 67

 1743 23:06:17.215102                           [Byte1]: 67

 1744 23:06:17.219334  

 1745 23:06:17.219415  Set Vref, RX VrefLevel [Byte0]: 68

 1746 23:06:17.222747                           [Byte1]: 68

 1747 23:06:17.226668  

 1748 23:06:17.226749  Set Vref, RX VrefLevel [Byte0]: 69

 1749 23:06:17.229976                           [Byte1]: 69

 1750 23:06:17.234440  

 1751 23:06:17.234522  Set Vref, RX VrefLevel [Byte0]: 70

 1752 23:06:17.237682                           [Byte1]: 70

 1753 23:06:17.241684  

 1754 23:06:17.241765  Final RX Vref Byte 0 = 58 to rank0

 1755 23:06:17.244881  Final RX Vref Byte 1 = 57 to rank0

 1756 23:06:17.248500  Final RX Vref Byte 0 = 58 to rank1

 1757 23:06:17.251522  Final RX Vref Byte 1 = 57 to rank1==

 1758 23:06:17.255064  Dram Type= 6, Freq= 0, CH_1, rank 0

 1759 23:06:17.261885  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1760 23:06:17.261967  ==

 1761 23:06:17.262045  DQS Delay:

 1762 23:06:17.262108  DQS0 = 0, DQS1 = 0

 1763 23:06:17.265435  DQM Delay:

 1764 23:06:17.265516  DQM0 = 95, DQM1 = 91

 1765 23:06:17.268727  DQ Delay:

 1766 23:06:17.272268  DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88

 1767 23:06:17.275110  DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =92

 1768 23:06:17.278258  DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84

 1769 23:06:17.281601  DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =100

 1770 23:06:17.281682  

 1771 23:06:17.281746  

 1772 23:06:17.288757  [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 1773 23:06:17.291874  CH1 RK0: MR19=606, MR18=304C

 1774 23:06:17.298363  CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64

 1775 23:06:17.298445  

 1776 23:06:17.302005  ----->DramcWriteLeveling(PI) begin...

 1777 23:06:17.302088  ==

 1778 23:06:17.304929  Dram Type= 6, Freq= 0, CH_1, rank 1

 1779 23:06:17.308493  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1780 23:06:17.308574  ==

 1781 23:06:17.311997  Write leveling (Byte 0): 27 => 27

 1782 23:06:17.315412  Write leveling (Byte 1): 27 => 27

 1783 23:06:17.318996  DramcWriteLeveling(PI) end<-----

 1784 23:06:17.319078  

 1785 23:06:17.319142  ==

 1786 23:06:17.322038  Dram Type= 6, Freq= 0, CH_1, rank 1

 1787 23:06:17.325574  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1788 23:06:17.325664  ==

 1789 23:06:17.328558  [Gating] SW mode calibration

 1790 23:06:17.335609  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1791 23:06:17.342019  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1792 23:06:17.345317   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1793 23:06:17.349155   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1794 23:06:17.355226   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1795 23:06:17.358844   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1796 23:06:17.362275   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1797 23:06:17.368793   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1798 23:06:17.372342   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1799 23:06:17.375350   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1800 23:06:17.381967   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1801 23:06:17.385447   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1802 23:06:17.388916   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1803 23:06:17.395238   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1804 23:06:17.398791   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1805 23:06:17.402402   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1806 23:06:17.405373   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1807 23:06:17.412374   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1808 23:06:17.415886   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1809 23:06:17.418708   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1810 23:06:17.425827   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1811 23:06:17.429234   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1812 23:06:17.432195   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1813 23:06:17.438756   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1814 23:06:17.442073   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1815 23:06:17.445695   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1816 23:06:17.452328   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1817 23:06:17.455713   0  9  4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)

 1818 23:06:17.458897   0  9  8 | B1->B0 | 3434 3131 | 1 0 | (1 1) (1 1)

 1819 23:06:17.465782   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1820 23:06:17.469018   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1821 23:06:17.472694   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1822 23:06:17.478901   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1823 23:06:17.482627   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1824 23:06:17.486080   0 10  0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 1825 23:06:17.488905   0 10  4 | B1->B0 | 2e2e 3131 | 0 1 | (0 0) (0 1)

 1826 23:06:17.495460   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 23:06:17.498881   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1828 23:06:17.502051   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1829 23:06:17.508694   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1830 23:06:17.512184   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1831 23:06:17.515726   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1832 23:06:17.522179   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 23:06:17.525464   0 11  4 | B1->B0 | 3d3d 2d2d | 0 0 | (0 0) (0 0)

 1834 23:06:17.529017   0 11  8 | B1->B0 | 4646 4242 | 0 0 | (0 0) (0 0)

 1835 23:06:17.535560   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1836 23:06:17.539131   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1837 23:06:17.542680   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1838 23:06:17.549633   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1839 23:06:17.552618   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1840 23:06:17.556141   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1841 23:06:17.559562   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1842 23:06:17.566223   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 1843 23:06:17.569150   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1844 23:06:17.572636   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1845 23:06:17.579163   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1846 23:06:17.582559   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1847 23:06:17.586295   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1848 23:06:17.592805   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1849 23:06:17.596343   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1850 23:06:17.599282   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1851 23:06:17.606364   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1852 23:06:17.609486   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1853 23:06:17.612836   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1854 23:06:17.619277   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1855 23:06:17.622719   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1856 23:06:17.626282   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1857 23:06:17.629672   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 1858 23:06:17.635998   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 1859 23:06:17.639747  Total UI for P1: 0, mck2ui 16

 1860 23:06:17.642885  best dqsien dly found for B1: ( 0, 14,  4)

 1861 23:06:17.645900   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1862 23:06:17.649304  Total UI for P1: 0, mck2ui 16

 1863 23:06:17.652813  best dqsien dly found for B0: ( 0, 14,  8)

 1864 23:06:17.656398  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1865 23:06:17.659434  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1866 23:06:17.659508  

 1867 23:06:17.662778  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1868 23:06:17.666374  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1869 23:06:17.669704  [Gating] SW calibration Done

 1870 23:06:17.669774  ==

 1871 23:06:17.673033  Dram Type= 6, Freq= 0, CH_1, rank 1

 1872 23:06:17.676383  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1873 23:06:17.679774  ==

 1874 23:06:17.679853  RX Vref Scan: 0

 1875 23:06:17.679916  

 1876 23:06:17.683225  RX Vref 0 -> 0, step: 1

 1877 23:06:17.683295  

 1878 23:06:17.686140  RX Delay -130 -> 252, step: 16

 1879 23:06:17.689795  iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208

 1880 23:06:17.693258  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1881 23:06:17.696275  iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224

 1882 23:06:17.699670  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1883 23:06:17.706384  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1884 23:06:17.709960  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1885 23:06:17.712895  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1886 23:06:17.716279  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1887 23:06:17.719736  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1888 23:06:17.723344  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1889 23:06:17.729521  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1890 23:06:17.732862  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1891 23:06:17.736636  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1892 23:06:17.740047  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1893 23:06:17.743539  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1894 23:06:17.749901  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1895 23:06:17.749974  ==

 1896 23:06:17.753515  Dram Type= 6, Freq= 0, CH_1, rank 1

 1897 23:06:17.756962  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1898 23:06:17.757036  ==

 1899 23:06:17.757099  DQS Delay:

 1900 23:06:17.759851  DQS0 = 0, DQS1 = 0

 1901 23:06:17.759935  DQM Delay:

 1902 23:06:17.763530  DQM0 = 92, DQM1 = 88

 1903 23:06:17.763608  DQ Delay:

 1904 23:06:17.766489  DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85

 1905 23:06:17.769955  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1906 23:06:17.773459  DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85

 1907 23:06:17.776855  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1908 23:06:17.776932  

 1909 23:06:17.777001  

 1910 23:06:17.777062  ==

 1911 23:06:17.780590  Dram Type= 6, Freq= 0, CH_1, rank 1

 1912 23:06:17.783415  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1913 23:06:17.786851  ==

 1914 23:06:17.786925  

 1915 23:06:17.786994  

 1916 23:06:17.787055  	TX Vref Scan disable

 1917 23:06:17.789913   == TX Byte 0 ==

 1918 23:06:17.793341  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1919 23:06:17.796706  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1920 23:06:17.800031   == TX Byte 1 ==

 1921 23:06:17.803090  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1922 23:06:17.806568  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1923 23:06:17.806651  ==

 1924 23:06:17.809935  Dram Type= 6, Freq= 0, CH_1, rank 1

 1925 23:06:17.816702  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1926 23:06:17.816779  ==

 1927 23:06:17.828855  TX Vref=22, minBit 2, minWin=26, winSum=439

 1928 23:06:17.831864  TX Vref=24, minBit 3, minWin=26, winSum=444

 1929 23:06:17.835214  TX Vref=26, minBit 2, minWin=26, winSum=447

 1930 23:06:17.838741  TX Vref=28, minBit 3, minWin=26, winSum=448

 1931 23:06:17.842117  TX Vref=30, minBit 1, minWin=27, winSum=452

 1932 23:06:17.845229  TX Vref=32, minBit 0, minWin=27, winSum=446

 1933 23:06:17.851963  [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30

 1934 23:06:17.852062  

 1935 23:06:17.855658  Final TX Range 1 Vref 30

 1936 23:06:17.855739  

 1937 23:06:17.855803  ==

 1938 23:06:17.858947  Dram Type= 6, Freq= 0, CH_1, rank 1

 1939 23:06:17.862463  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1940 23:06:17.862543  ==

 1941 23:06:17.862607  

 1942 23:06:17.862665  

 1943 23:06:17.865323  	TX Vref Scan disable

 1944 23:06:17.869005   == TX Byte 0 ==

 1945 23:06:17.871965  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1946 23:06:17.875482  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1947 23:06:17.879075   == TX Byte 1 ==

 1948 23:06:17.882067  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 1949 23:06:17.885357  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 1950 23:06:17.885437  

 1951 23:06:17.888906  [DATLAT]

 1952 23:06:17.888986  Freq=800, CH1 RK1

 1953 23:06:17.889049  

 1954 23:06:17.892141  DATLAT Default: 0xa

 1955 23:06:17.892221  0, 0xFFFF, sum = 0

 1956 23:06:17.895748  1, 0xFFFF, sum = 0

 1957 23:06:17.895829  2, 0xFFFF, sum = 0

 1958 23:06:17.899458  3, 0xFFFF, sum = 0

 1959 23:06:17.899539  4, 0xFFFF, sum = 0

 1960 23:06:17.902299  5, 0xFFFF, sum = 0

 1961 23:06:17.902408  6, 0xFFFF, sum = 0

 1962 23:06:17.905820  7, 0xFFFF, sum = 0

 1963 23:06:17.905901  8, 0xFFFF, sum = 0

 1964 23:06:17.908877  9, 0x0, sum = 1

 1965 23:06:17.908958  10, 0x0, sum = 2

 1966 23:06:17.912147  11, 0x0, sum = 3

 1967 23:06:17.912228  12, 0x0, sum = 4

 1968 23:06:17.915489  best_step = 10

 1969 23:06:17.915568  

 1970 23:06:17.915631  ==

 1971 23:06:17.918675  Dram Type= 6, Freq= 0, CH_1, rank 1

 1972 23:06:17.922420  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1973 23:06:17.922501  ==

 1974 23:06:17.925785  RX Vref Scan: 0

 1975 23:06:17.925866  

 1976 23:06:17.925930  RX Vref 0 -> 0, step: 1

 1977 23:06:17.925990  

 1978 23:06:17.928780  RX Delay -79 -> 252, step: 8

 1979 23:06:17.935958  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 1980 23:06:17.938973  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 1981 23:06:17.942397  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 1982 23:06:17.945793  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 1983 23:06:17.948752  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 1984 23:06:17.952279  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 1985 23:06:17.958605  iDelay=209, Bit 6, Center 108 (9 ~ 208) 200

 1986 23:06:17.961908  iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208

 1987 23:06:17.965466  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 1988 23:06:17.968618  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 1989 23:06:17.972055  iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208

 1990 23:06:17.979213  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 1991 23:06:17.982218  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 1992 23:06:17.985187  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 1993 23:06:17.988647  iDelay=209, Bit 14, Center 104 (9 ~ 200) 192

 1994 23:06:17.992152  iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216

 1995 23:06:17.995829  ==

 1996 23:06:17.995910  Dram Type= 6, Freq= 0, CH_1, rank 1

 1997 23:06:18.001960  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1998 23:06:18.002042  ==

 1999 23:06:18.002107  DQS Delay:

 2000 23:06:18.005481  DQS0 = 0, DQS1 = 0

 2001 23:06:18.005562  DQM Delay:

 2002 23:06:18.005677  DQM0 = 97, DQM1 = 92

 2003 23:06:18.008902  DQ Delay:

 2004 23:06:18.012047  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2005 23:06:18.015490  DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96

 2006 23:06:18.018897  DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88

 2007 23:06:18.022539  DQ12 =100, DQ13 =96, DQ14 =104, DQ15 =100

 2008 23:06:18.022619  

 2009 23:06:18.022683  

 2010 23:06:18.028839  [DQSOSCAuto] RK1, (LSB)MR18= 0x420c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps

 2011 23:06:18.032207  CH1 RK1: MR19=606, MR18=420C

 2012 23:06:18.039206  CH1_RK1: MR19=0x606, MR18=0x420C, DQSOSC=393, MR23=63, INC=95, DEC=63

 2013 23:06:18.042500  [RxdqsGatingPostProcess] freq 800

 2014 23:06:18.045455  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2015 23:06:18.048911  Pre-setting of DQS Precalculation

 2016 23:06:18.055848  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2017 23:06:18.062617  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2018 23:06:18.069118  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2019 23:06:18.069209  

 2020 23:06:18.069273  

 2021 23:06:18.072496  [Calibration Summary] 1600 Mbps

 2022 23:06:18.075832  CH 0, Rank 0

 2023 23:06:18.075914  SW Impedance     : PASS

 2024 23:06:18.078849  DUTY Scan        : NO K

 2025 23:06:18.078931  ZQ Calibration   : PASS

 2026 23:06:18.082363  Jitter Meter     : NO K

 2027 23:06:18.085302  CBT Training     : PASS

 2028 23:06:18.085383  Write leveling   : PASS

 2029 23:06:18.088724  RX DQS gating    : PASS

 2030 23:06:18.092198  RX DQ/DQS(RDDQC) : PASS

 2031 23:06:18.092279  TX DQ/DQS        : PASS

 2032 23:06:18.095643  RX DATLAT        : PASS

 2033 23:06:18.099385  RX DQ/DQS(Engine): PASS

 2034 23:06:18.099468  TX OE            : NO K

 2035 23:06:18.102193  All Pass.

 2036 23:06:18.102275  

 2037 23:06:18.102338  CH 0, Rank 1

 2038 23:06:18.105479  SW Impedance     : PASS

 2039 23:06:18.105583  DUTY Scan        : NO K

 2040 23:06:18.108913  ZQ Calibration   : PASS

 2041 23:06:18.112460  Jitter Meter     : NO K

 2042 23:06:18.112542  CBT Training     : PASS

 2043 23:06:18.115532  Write leveling   : PASS

 2044 23:06:18.118907  RX DQS gating    : PASS

 2045 23:06:18.118989  RX DQ/DQS(RDDQC) : PASS

 2046 23:06:18.122392  TX DQ/DQS        : PASS

 2047 23:06:18.122474  RX DATLAT        : PASS

 2048 23:06:18.125561  RX DQ/DQS(Engine): PASS

 2049 23:06:18.129263  TX OE            : NO K

 2050 23:06:18.129344  All Pass.

 2051 23:06:18.129409  

 2052 23:06:18.129468  CH 1, Rank 0

 2053 23:06:18.132156  SW Impedance     : PASS

 2054 23:06:18.135774  DUTY Scan        : NO K

 2055 23:06:18.135877  ZQ Calibration   : PASS

 2056 23:06:18.138863  Jitter Meter     : NO K

 2057 23:06:18.142449  CBT Training     : PASS

 2058 23:06:18.142531  Write leveling   : PASS

 2059 23:06:18.145763  RX DQS gating    : PASS

 2060 23:06:18.149147  RX DQ/DQS(RDDQC) : PASS

 2061 23:06:18.149229  TX DQ/DQS        : PASS

 2062 23:06:18.152242  RX DATLAT        : PASS

 2063 23:06:18.152324  RX DQ/DQS(Engine): PASS

 2064 23:06:18.155883  TX OE            : NO K

 2065 23:06:18.155964  All Pass.

 2066 23:06:18.156029  

 2067 23:06:18.159040  CH 1, Rank 1

 2068 23:06:18.159121  SW Impedance     : PASS

 2069 23:06:18.162546  DUTY Scan        : NO K

 2070 23:06:18.165495  ZQ Calibration   : PASS

 2071 23:06:18.165585  Jitter Meter     : NO K

 2072 23:06:18.169028  CBT Training     : PASS

 2073 23:06:18.172106  Write leveling   : PASS

 2074 23:06:18.172187  RX DQS gating    : PASS

 2075 23:06:18.175485  RX DQ/DQS(RDDQC) : PASS

 2076 23:06:18.178954  TX DQ/DQS        : PASS

 2077 23:06:18.179037  RX DATLAT        : PASS

 2078 23:06:18.182616  RX DQ/DQS(Engine): PASS

 2079 23:06:18.185803  TX OE            : NO K

 2080 23:06:18.185884  All Pass.

 2081 23:06:18.185949  

 2082 23:06:18.189206  DramC Write-DBI off

 2083 23:06:18.189287  	PER_BANK_REFRESH: Hybrid Mode

 2084 23:06:18.192433  TX_TRACKING: ON

 2085 23:06:18.195558  [GetDramInforAfterCalByMRR] Vendor 6.

 2086 23:06:18.198798  [GetDramInforAfterCalByMRR] Revision 606.

 2087 23:06:18.202442  [GetDramInforAfterCalByMRR] Revision 2 0.

 2088 23:06:18.202523  MR0 0x3b3b

 2089 23:06:18.206066  MR8 0x5151

 2090 23:06:18.209122  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2091 23:06:18.209228  

 2092 23:06:18.209325  MR0 0x3b3b

 2093 23:06:18.209411  MR8 0x5151

 2094 23:06:18.212306  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2095 23:06:18.215714  

 2096 23:06:18.222777  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2097 23:06:18.225581  [FAST_K] Save calibration result to emmc

 2098 23:06:18.229134  [FAST_K] Save calibration result to emmc

 2099 23:06:18.232173  dram_init: config_dvfs: 1

 2100 23:06:18.235615  dramc_set_vcore_voltage set vcore to 662500

 2101 23:06:18.239208  Read voltage for 1200, 2

 2102 23:06:18.239290  Vio18 = 0

 2103 23:06:18.242309  Vcore = 662500

 2104 23:06:18.242390  Vdram = 0

 2105 23:06:18.242454  Vddq = 0

 2106 23:06:18.242514  Vmddr = 0

 2107 23:06:18.248935  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2108 23:06:18.255831  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2109 23:06:18.255913  MEM_TYPE=3, freq_sel=15

 2110 23:06:18.259321  sv_algorithm_assistance_LP4_1600 

 2111 23:06:18.262213  ============ PULL DRAM RESETB DOWN ============

 2112 23:06:18.268871  ========== PULL DRAM RESETB DOWN end =========

 2113 23:06:18.272414  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2114 23:06:18.275609  =================================== 

 2115 23:06:18.278878  LPDDR4 DRAM CONFIGURATION

 2116 23:06:18.282523  =================================== 

 2117 23:06:18.282605  EX_ROW_EN[0]    = 0x0

 2118 23:06:18.285975  EX_ROW_EN[1]    = 0x0

 2119 23:06:18.286057  LP4Y_EN      = 0x0

 2120 23:06:18.289027  WORK_FSP     = 0x0

 2121 23:06:18.289108  WL           = 0x4

 2122 23:06:18.292361  RL           = 0x4

 2123 23:06:18.292442  BL           = 0x2

 2124 23:06:18.296076  RPST         = 0x0

 2125 23:06:18.296157  RD_PRE       = 0x0

 2126 23:06:18.299305  WR_PRE       = 0x1

 2127 23:06:18.299386  WR_PST       = 0x0

 2128 23:06:18.302632  DBI_WR       = 0x0

 2129 23:06:18.302714  DBI_RD       = 0x0

 2130 23:06:18.305631  OTF          = 0x1

 2131 23:06:18.309088  =================================== 

 2132 23:06:18.312290  =================================== 

 2133 23:06:18.312371  ANA top config

 2134 23:06:18.315804  =================================== 

 2135 23:06:18.319315  DLL_ASYNC_EN            =  0

 2136 23:06:18.322249  ALL_SLAVE_EN            =  0

 2137 23:06:18.326013  NEW_RANK_MODE           =  1

 2138 23:06:18.326096  DLL_IDLE_MODE           =  1

 2139 23:06:18.329293  LP45_APHY_COMB_EN       =  1

 2140 23:06:18.332273  TX_ODT_DIS              =  1

 2141 23:06:18.335974  NEW_8X_MODE             =  1

 2142 23:06:18.339004  =================================== 

 2143 23:06:18.342307  =================================== 

 2144 23:06:18.345843  data_rate                  = 2400

 2145 23:06:18.345928  CKR                        = 1

 2146 23:06:18.348946  DQ_P2S_RATIO               = 8

 2147 23:06:18.352419  =================================== 

 2148 23:06:18.356062  CA_P2S_RATIO               = 8

 2149 23:06:18.359400  DQ_CA_OPEN                 = 0

 2150 23:06:18.362302  DQ_SEMI_OPEN               = 0

 2151 23:06:18.365869  CA_SEMI_OPEN               = 0

 2152 23:06:18.365951  CA_FULL_RATE               = 0

 2153 23:06:18.369459  DQ_CKDIV4_EN               = 0

 2154 23:06:18.372561  CA_CKDIV4_EN               = 0

 2155 23:06:18.375924  CA_PREDIV_EN               = 0

 2156 23:06:18.378980  PH8_DLY                    = 17

 2157 23:06:18.382467  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2158 23:06:18.382548  DQ_AAMCK_DIV               = 4

 2159 23:06:18.385714  CA_AAMCK_DIV               = 4

 2160 23:06:18.388939  CA_ADMCK_DIV               = 4

 2161 23:06:18.392370  DQ_TRACK_CA_EN             = 0

 2162 23:06:18.395911  CA_PICK                    = 1200

 2163 23:06:18.399245  CA_MCKIO                   = 1200

 2164 23:06:18.402820  MCKIO_SEMI                 = 0

 2165 23:06:18.402901  PLL_FREQ                   = 2366

 2166 23:06:18.405711  DQ_UI_PI_RATIO             = 32

 2167 23:06:18.409117  CA_UI_PI_RATIO             = 0

 2168 23:06:18.412488  =================================== 

 2169 23:06:18.415839  =================================== 

 2170 23:06:18.419400  memory_type:LPDDR4         

 2171 23:06:18.419480  GP_NUM     : 10       

 2172 23:06:18.422119  SRAM_EN    : 1       

 2173 23:06:18.425615  MD32_EN    : 0       

 2174 23:06:18.429214  =================================== 

 2175 23:06:18.429296  [ANA_INIT] >>>>>>>>>>>>>> 

 2176 23:06:18.432975  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2177 23:06:18.435911  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2178 23:06:18.438925  =================================== 

 2179 23:06:18.442656  data_rate = 2400,PCW = 0X5b00

 2180 23:06:18.445874  =================================== 

 2181 23:06:18.448878  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2182 23:06:18.456116  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2183 23:06:18.459084  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2184 23:06:18.465899  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2185 23:06:18.468971  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2186 23:06:18.472558  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2187 23:06:18.472640  [ANA_INIT] flow start 

 2188 23:06:18.475591  [ANA_INIT] PLL >>>>>>>> 

 2189 23:06:18.479163  [ANA_INIT] PLL <<<<<<<< 

 2190 23:06:18.482366  [ANA_INIT] MIDPI >>>>>>>> 

 2191 23:06:18.482448  [ANA_INIT] MIDPI <<<<<<<< 

 2192 23:06:18.485731  [ANA_INIT] DLL >>>>>>>> 

 2193 23:06:18.488857  [ANA_INIT] DLL <<<<<<<< 

 2194 23:06:18.488938  [ANA_INIT] flow end 

 2195 23:06:18.492417  ============ LP4 DIFF to SE enter ============

 2196 23:06:18.498817  ============ LP4 DIFF to SE exit  ============

 2197 23:06:18.498900  [ANA_INIT] <<<<<<<<<<<<< 

 2198 23:06:18.502575  [Flow] Enable top DCM control >>>>> 

 2199 23:06:18.506065  [Flow] Enable top DCM control <<<<< 

 2200 23:06:18.508912  Enable DLL master slave shuffle 

 2201 23:06:18.516033  ============================================================== 

 2202 23:06:18.516115  Gating Mode config

 2203 23:06:18.522626  ============================================================== 

 2204 23:06:18.525641  Config description: 

 2205 23:06:18.532296  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2206 23:06:18.539197  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2207 23:06:18.545766  SELPH_MODE            0: By rank         1: By Phase 

 2208 23:06:18.552394  ============================================================== 

 2209 23:06:18.552476  GAT_TRACK_EN                 =  1

 2210 23:06:18.555929  RX_GATING_MODE               =  2

 2211 23:06:18.559441  RX_GATING_TRACK_MODE         =  2

 2212 23:06:18.562414  SELPH_MODE                   =  1

 2213 23:06:18.565776  PICG_EARLY_EN                =  1

 2214 23:06:18.569126  VALID_LAT_VALUE              =  1

 2215 23:06:18.575685  ============================================================== 

 2216 23:06:18.579378  Enter into Gating configuration >>>> 

 2217 23:06:18.583075  Exit from Gating configuration <<<< 

 2218 23:06:18.585945  Enter into  DVFS_PRE_config >>>>> 

 2219 23:06:18.595896  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2220 23:06:18.599415  Exit from  DVFS_PRE_config <<<<< 

 2221 23:06:18.602365  Enter into PICG configuration >>>> 

 2222 23:06:18.606149  Exit from PICG configuration <<<< 

 2223 23:06:18.606230  [RX_INPUT] configuration >>>>> 

 2224 23:06:18.609154  [RX_INPUT] configuration <<<<< 

 2225 23:06:18.616036  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2226 23:06:18.619524  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2227 23:06:18.626012  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2228 23:06:18.632871  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2229 23:06:18.639075  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2230 23:06:18.645880  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2231 23:06:18.649404  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2232 23:06:18.652805  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2233 23:06:18.659101  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2234 23:06:18.662665  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2235 23:06:18.665865  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2236 23:06:18.669447  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2237 23:06:18.673051  =================================== 

 2238 23:06:18.675820  LPDDR4 DRAM CONFIGURATION

 2239 23:06:18.679348  =================================== 

 2240 23:06:18.682993  EX_ROW_EN[0]    = 0x0

 2241 23:06:18.683074  EX_ROW_EN[1]    = 0x0

 2242 23:06:18.685916  LP4Y_EN      = 0x0

 2243 23:06:18.685997  WORK_FSP     = 0x0

 2244 23:06:18.689474  WL           = 0x4

 2245 23:06:18.689554  RL           = 0x4

 2246 23:06:18.692363  BL           = 0x2

 2247 23:06:18.692444  RPST         = 0x0

 2248 23:06:18.696171  RD_PRE       = 0x0

 2249 23:06:18.696252  WR_PRE       = 0x1

 2250 23:06:18.699084  WR_PST       = 0x0

 2251 23:06:18.699165  DBI_WR       = 0x0

 2252 23:06:18.702753  DBI_RD       = 0x0

 2253 23:06:18.702833  OTF          = 0x1

 2254 23:06:18.706158  =================================== 

 2255 23:06:18.712799  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2256 23:06:18.715825  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2257 23:06:18.719244  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2258 23:06:18.722805  =================================== 

 2259 23:06:18.726399  LPDDR4 DRAM CONFIGURATION

 2260 23:06:18.729755  =================================== 

 2261 23:06:18.729836  EX_ROW_EN[0]    = 0x10

 2262 23:06:18.732954  EX_ROW_EN[1]    = 0x0

 2263 23:06:18.735996  LP4Y_EN      = 0x0

 2264 23:06:18.736077  WORK_FSP     = 0x0

 2265 23:06:18.739538  WL           = 0x4

 2266 23:06:18.739619  RL           = 0x4

 2267 23:06:18.743177  BL           = 0x2

 2268 23:06:18.743258  RPST         = 0x0

 2269 23:06:18.746025  RD_PRE       = 0x0

 2270 23:06:18.746106  WR_PRE       = 0x1

 2271 23:06:18.749552  WR_PST       = 0x0

 2272 23:06:18.749676  DBI_WR       = 0x0

 2273 23:06:18.752783  DBI_RD       = 0x0

 2274 23:06:18.752863  OTF          = 0x1

 2275 23:06:18.756226  =================================== 

 2276 23:06:18.762734  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2277 23:06:18.762816  ==

 2278 23:06:18.766039  Dram Type= 6, Freq= 0, CH_0, rank 0

 2279 23:06:18.769456  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2280 23:06:18.773044  ==

 2281 23:06:18.773124  [Duty_Offset_Calibration]

 2282 23:06:18.776134  	B0:2	B1:1	CA:1

 2283 23:06:18.776215  

 2284 23:06:18.779709  [DutyScan_Calibration_Flow] k_type=0

 2285 23:06:18.787633  

 2286 23:06:18.787715  ==CLK 0==

 2287 23:06:18.791106  Final CLK duty delay cell = 0

 2288 23:06:18.794708  [0] MAX Duty = 5218%(X100), DQS PI = 24

 2289 23:06:18.797775  [0] MIN Duty = 4875%(X100), DQS PI = 0

 2290 23:06:18.797856  [0] AVG Duty = 5046%(X100)

 2291 23:06:18.797920  

 2292 23:06:18.801362  CH0 CLK Duty spec in!! Max-Min= 343%

 2293 23:06:18.807868  [DutyScan_Calibration_Flow] ====Done====

 2294 23:06:18.807950  

 2295 23:06:18.811239  [DutyScan_Calibration_Flow] k_type=1

 2296 23:06:18.825990  

 2297 23:06:18.826074  ==DQS 0 ==

 2298 23:06:18.829757  Final DQS duty delay cell = -4

 2299 23:06:18.833126  [-4] MAX Duty = 5124%(X100), DQS PI = 24

 2300 23:06:18.836169  [-4] MIN Duty = 4751%(X100), DQS PI = 0

 2301 23:06:18.839587  [-4] AVG Duty = 4937%(X100)

 2302 23:06:18.839667  

 2303 23:06:18.839730  ==DQS 1 ==

 2304 23:06:18.842821  Final DQS duty delay cell = 0

 2305 23:06:18.846192  [0] MAX Duty = 5156%(X100), DQS PI = 0

 2306 23:06:18.849823  [0] MIN Duty = 5000%(X100), DQS PI = 34

 2307 23:06:18.852819  [0] AVG Duty = 5078%(X100)

 2308 23:06:18.852899  

 2309 23:06:18.856268  CH0 DQS 0 Duty spec in!! Max-Min= 373%

 2310 23:06:18.856348  

 2311 23:06:18.859822  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 2312 23:06:18.863194  [DutyScan_Calibration_Flow] ====Done====

 2313 23:06:18.863288  

 2314 23:06:18.866140  [DutyScan_Calibration_Flow] k_type=3

 2315 23:06:18.883100  

 2316 23:06:18.883180  ==DQM 0 ==

 2317 23:06:18.886242  Final DQM duty delay cell = 0

 2318 23:06:18.889846  [0] MAX Duty = 5156%(X100), DQS PI = 30

 2319 23:06:18.893150  [0] MIN Duty = 4906%(X100), DQS PI = 58

 2320 23:06:18.893230  [0] AVG Duty = 5031%(X100)

 2321 23:06:18.896903  

 2322 23:06:18.896982  ==DQM 1 ==

 2323 23:06:18.900193  Final DQM duty delay cell = 0

 2324 23:06:18.903390  [0] MAX Duty = 5093%(X100), DQS PI = 0

 2325 23:06:18.906838  [0] MIN Duty = 5031%(X100), DQS PI = 18

 2326 23:06:18.906922  [0] AVG Duty = 5062%(X100)

 2327 23:06:18.907011  

 2328 23:06:18.910023  CH0 DQM 0 Duty spec in!! Max-Min= 250%

 2329 23:06:18.910103  

 2330 23:06:18.917119  CH0 DQM 1 Duty spec in!! Max-Min= 62%

 2331 23:06:18.919960  [DutyScan_Calibration_Flow] ====Done====

 2332 23:06:18.920040  

 2333 23:06:18.923117  [DutyScan_Calibration_Flow] k_type=2

 2334 23:06:18.939521  

 2335 23:06:18.939629  ==DQ 0 ==

 2336 23:06:18.943050  Final DQ duty delay cell = 0

 2337 23:06:18.946137  [0] MAX Duty = 5062%(X100), DQS PI = 32

 2338 23:06:18.949568  [0] MIN Duty = 4906%(X100), DQS PI = 0

 2339 23:06:18.949687  [0] AVG Duty = 4984%(X100)

 2340 23:06:18.949751  

 2341 23:06:18.953073  ==DQ 1 ==

 2342 23:06:18.955942  Final DQ duty delay cell = 0

 2343 23:06:18.959503  [0] MAX Duty = 5093%(X100), DQS PI = 24

 2344 23:06:18.962581  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2345 23:06:18.962662  [0] AVG Duty = 5000%(X100)

 2346 23:06:18.962729  

 2347 23:06:18.965906  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 2348 23:06:18.965987  

 2349 23:06:18.969210  CH0 DQ 1 Duty spec in!! Max-Min= 186%

 2350 23:06:18.976326  [DutyScan_Calibration_Flow] ====Done====

 2351 23:06:18.976407  ==

 2352 23:06:18.979666  Dram Type= 6, Freq= 0, CH_1, rank 0

 2353 23:06:18.983018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2354 23:06:18.983106  ==

 2355 23:06:18.986054  [Duty_Offset_Calibration]

 2356 23:06:18.986134  	B0:1	B1:0	CA:0

 2357 23:06:18.986198  

 2358 23:06:18.989573  [DutyScan_Calibration_Flow] k_type=0

 2359 23:06:18.998772  

 2360 23:06:18.998868  ==CLK 0==

 2361 23:06:19.001770  Final CLK duty delay cell = -4

 2362 23:06:19.005291  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2363 23:06:19.008834  [-4] MIN Duty = 4875%(X100), DQS PI = 52

 2364 23:06:19.012094  [-4] AVG Duty = 4953%(X100)

 2365 23:06:19.012181  

 2366 23:06:19.015447  CH1 CLK Duty spec in!! Max-Min= 156%

 2367 23:06:19.018706  [DutyScan_Calibration_Flow] ====Done====

 2368 23:06:19.018812  

 2369 23:06:19.021773  [DutyScan_Calibration_Flow] k_type=1

 2370 23:06:19.038751  

 2371 23:06:19.038832  ==DQS 0 ==

 2372 23:06:19.041747  Final DQS duty delay cell = 0

 2373 23:06:19.045240  [0] MAX Duty = 5094%(X100), DQS PI = 22

 2374 23:06:19.048134  [0] MIN Duty = 4844%(X100), DQS PI = 0

 2375 23:06:19.048215  [0] AVG Duty = 4969%(X100)

 2376 23:06:19.051735  

 2377 23:06:19.051815  ==DQS 1 ==

 2378 23:06:19.055052  Final DQS duty delay cell = 0

 2379 23:06:19.058457  [0] MAX Duty = 5187%(X100), DQS PI = 20

 2380 23:06:19.061453  [0] MIN Duty = 4938%(X100), DQS PI = 12

 2381 23:06:19.065074  [0] AVG Duty = 5062%(X100)

 2382 23:06:19.065154  

 2383 23:06:19.068076  CH1 DQS 0 Duty spec in!! Max-Min= 250%

 2384 23:06:19.068167  

 2385 23:06:19.071574  CH1 DQS 1 Duty spec in!! Max-Min= 249%

 2386 23:06:19.075061  [DutyScan_Calibration_Flow] ====Done====

 2387 23:06:19.075142  

 2388 23:06:19.078064  [DutyScan_Calibration_Flow] k_type=3

 2389 23:06:19.095277  

 2390 23:06:19.095358  ==DQM 0 ==

 2391 23:06:19.098754  Final DQM duty delay cell = 0

 2392 23:06:19.101688  [0] MAX Duty = 5156%(X100), DQS PI = 8

 2393 23:06:19.104873  [0] MIN Duty = 5031%(X100), DQS PI = 0

 2394 23:06:19.104959  [0] AVG Duty = 5093%(X100)

 2395 23:06:19.105045  

 2396 23:06:19.108546  ==DQM 1 ==

 2397 23:06:19.111689  Final DQM duty delay cell = 0

 2398 23:06:19.115179  [0] MAX Duty = 5031%(X100), DQS PI = 16

 2399 23:06:19.118721  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2400 23:06:19.118808  [0] AVG Duty = 4969%(X100)

 2401 23:06:19.118895  

 2402 23:06:19.125098  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 2403 23:06:19.125182  

 2404 23:06:19.128421  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2405 23:06:19.131706  [DutyScan_Calibration_Flow] ====Done====

 2406 23:06:19.131789  

 2407 23:06:19.135178  [DutyScan_Calibration_Flow] k_type=2

 2408 23:06:19.151012  

 2409 23:06:19.151100  ==DQ 0 ==

 2410 23:06:19.154024  Final DQ duty delay cell = -4

 2411 23:06:19.157523  [-4] MAX Duty = 5062%(X100), DQS PI = 8

 2412 23:06:19.160407  [-4] MIN Duty = 4938%(X100), DQS PI = 0

 2413 23:06:19.163840  [-4] AVG Duty = 5000%(X100)

 2414 23:06:19.163922  

 2415 23:06:19.163985  ==DQ 1 ==

 2416 23:06:19.167171  Final DQ duty delay cell = 0

 2417 23:06:19.170921  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2418 23:06:19.173910  [0] MIN Duty = 4969%(X100), DQS PI = 12

 2419 23:06:19.177436  [0] AVG Duty = 5047%(X100)

 2420 23:06:19.177542  

 2421 23:06:19.180455  CH1 DQ 0 Duty spec in!! Max-Min= 124%

 2422 23:06:19.180553  

 2423 23:06:19.183990  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2424 23:06:19.187016  [DutyScan_Calibration_Flow] ====Done====

 2425 23:06:19.190371  nWR fixed to 30

 2426 23:06:19.193770  [ModeRegInit_LP4] CH0 RK0

 2427 23:06:19.193866  [ModeRegInit_LP4] CH0 RK1

 2428 23:06:19.196691  [ModeRegInit_LP4] CH1 RK0

 2429 23:06:19.199996  [ModeRegInit_LP4] CH1 RK1

 2430 23:06:19.200123  match AC timing 7

 2431 23:06:19.207146  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2432 23:06:19.210165  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2433 23:06:19.213434  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2434 23:06:19.220203  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2435 23:06:19.223653  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2436 23:06:19.223791  ==

 2437 23:06:19.227015  Dram Type= 6, Freq= 0, CH_0, rank 0

 2438 23:06:19.230066  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2439 23:06:19.230197  ==

 2440 23:06:19.237100  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2441 23:06:19.243902  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2442 23:06:19.250851  [CA 0] Center 39 (8~70) winsize 63

 2443 23:06:19.254370  [CA 1] Center 39 (8~70) winsize 63

 2444 23:06:19.257259  [CA 2] Center 35 (5~66) winsize 62

 2445 23:06:19.260862  [CA 3] Center 34 (4~65) winsize 62

 2446 23:06:19.264456  [CA 4] Center 33 (3~64) winsize 62

 2447 23:06:19.267327  [CA 5] Center 32 (3~62) winsize 60

 2448 23:06:19.267427  

 2449 23:06:19.270923  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2450 23:06:19.271019  

 2451 23:06:19.274355  [CATrainingPosCal] consider 1 rank data

 2452 23:06:19.277755  u2DelayCellTimex100 = 270/100 ps

 2453 23:06:19.280805  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2454 23:06:19.284243  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2455 23:06:19.291020  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2456 23:06:19.294046  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2457 23:06:19.297780  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2458 23:06:19.301117  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2459 23:06:19.301257  

 2460 23:06:19.304107  CA PerBit enable=1, Macro0, CA PI delay=32

 2461 23:06:19.304248  

 2462 23:06:19.307530  [CBTSetCACLKResult] CA Dly = 32

 2463 23:06:19.307638  CS Dly: 6 (0~37)

 2464 23:06:19.307736  ==

 2465 23:06:19.310996  Dram Type= 6, Freq= 0, CH_0, rank 1

 2466 23:06:19.317619  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2467 23:06:19.317747  ==

 2468 23:06:19.320782  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2469 23:06:19.327689  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37

 2470 23:06:19.336563  [CA 0] Center 38 (8~69) winsize 62

 2471 23:06:19.339892  [CA 1] Center 38 (8~69) winsize 62

 2472 23:06:19.343152  [CA 2] Center 35 (5~66) winsize 62

 2473 23:06:19.346766  [CA 3] Center 34 (4~65) winsize 62

 2474 23:06:19.349935  [CA 4] Center 33 (3~64) winsize 62

 2475 23:06:19.353408  [CA 5] Center 32 (2~62) winsize 61

 2476 23:06:19.353536  

 2477 23:06:19.357043  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2478 23:06:19.357182  

 2479 23:06:19.359930  [CATrainingPosCal] consider 2 rank data

 2480 23:06:19.363287  u2DelayCellTimex100 = 270/100 ps

 2481 23:06:19.366809  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2482 23:06:19.369912  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2483 23:06:19.376895  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2484 23:06:19.379896  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2485 23:06:19.383360  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2486 23:06:19.386954  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2487 23:06:19.387032  

 2488 23:06:19.390019  CA PerBit enable=1, Macro0, CA PI delay=32

 2489 23:06:19.390142  

 2490 23:06:19.393413  [CBTSetCACLKResult] CA Dly = 32

 2491 23:06:19.393513  CS Dly: 6 (0~38)

 2492 23:06:19.393636  

 2493 23:06:19.396699  ----->DramcWriteLeveling(PI) begin...

 2494 23:06:19.396781  ==

 2495 23:06:19.400057  Dram Type= 6, Freq= 0, CH_0, rank 0

 2496 23:06:19.407233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2497 23:06:19.407315  ==

 2498 23:06:19.409989  Write leveling (Byte 0): 34 => 34

 2499 23:06:19.413656  Write leveling (Byte 1): 30 => 30

 2500 23:06:19.413745  DramcWriteLeveling(PI) end<-----

 2501 23:06:19.416623  

 2502 23:06:19.416728  ==

 2503 23:06:19.420011  Dram Type= 6, Freq= 0, CH_0, rank 0

 2504 23:06:19.423672  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2505 23:06:19.423753  ==

 2506 23:06:19.426896  [Gating] SW mode calibration

 2507 23:06:19.433805  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2508 23:06:19.436725  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2509 23:06:19.443507   0 15  0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)

 2510 23:06:19.446784   0 15  4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 2511 23:06:19.450053   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2512 23:06:19.456902   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2513 23:06:19.460341   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2514 23:06:19.463468   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2515 23:06:19.469971   0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 2516 23:06:19.473471   0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)

 2517 23:06:19.477154   1  0  0 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)

 2518 23:06:19.483507   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2519 23:06:19.487030   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2520 23:06:19.490602   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2521 23:06:19.496624   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2522 23:06:19.500054   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2523 23:06:19.503460   1  0 24 | B1->B0 | 2323 3030 | 0 1 | (0 0) (0 0)

 2524 23:06:19.506894   1  0 28 | B1->B0 | 2525 4545 | 0 0 | (0 0) (0 0)

 2525 23:06:19.513694   1  1  0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)

 2526 23:06:19.516998   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2527 23:06:19.520283   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2528 23:06:19.526901   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2529 23:06:19.530391   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2530 23:06:19.533816   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2531 23:06:19.540073   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2532 23:06:19.543464   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2533 23:06:19.547048   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2534 23:06:19.553468   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2535 23:06:19.557065   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2536 23:06:19.560516   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2537 23:06:19.566726   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2538 23:06:19.570236   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2539 23:06:19.573679   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2540 23:06:19.580332   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2541 23:06:19.583864   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2542 23:06:19.586733   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2543 23:06:19.590341   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2544 23:06:19.597175   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2545 23:06:19.600318   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2546 23:06:19.603913   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2547 23:06:19.610175   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2548 23:06:19.613776   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2549 23:06:19.617065   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2550 23:06:19.623815   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2551 23:06:19.623950  Total UI for P1: 0, mck2ui 16

 2552 23:06:19.630109  best dqsien dly found for B0: ( 1,  3, 30)

 2553 23:06:19.630191  Total UI for P1: 0, mck2ui 16

 2554 23:06:19.636973  best dqsien dly found for B1: ( 1,  4,  0)

 2555 23:06:19.640440  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2556 23:06:19.643663  best DQS1 dly(MCK, UI, PI) = (1, 4, 0)

 2557 23:06:19.643743  

 2558 23:06:19.647057  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2559 23:06:19.650593  best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)

 2560 23:06:19.653474  [Gating] SW calibration Done

 2561 23:06:19.653555  ==

 2562 23:06:19.657205  Dram Type= 6, Freq= 0, CH_0, rank 0

 2563 23:06:19.660215  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2564 23:06:19.660296  ==

 2565 23:06:19.663873  RX Vref Scan: 0

 2566 23:06:19.663953  

 2567 23:06:19.664017  RX Vref 0 -> 0, step: 1

 2568 23:06:19.664076  

 2569 23:06:19.667363  RX Delay -40 -> 252, step: 8

 2570 23:06:19.670208  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2571 23:06:19.676955  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2572 23:06:19.680482  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2573 23:06:19.683885  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2574 23:06:19.687514  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2575 23:06:19.690459  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2576 23:06:19.694138  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2577 23:06:19.700476  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2578 23:06:19.703990  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2579 23:06:19.707498  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2580 23:06:19.710358  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2581 23:06:19.713953  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2582 23:06:19.720593  iDelay=200, Bit 12, Center 119 (48 ~ 191) 144

 2583 23:06:19.724226  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2584 23:06:19.727525  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2585 23:06:19.730442  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 2586 23:06:19.730526  ==

 2587 23:06:19.733998  Dram Type= 6, Freq= 0, CH_0, rank 0

 2588 23:06:19.740600  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2589 23:06:19.740690  ==

 2590 23:06:19.740776  DQS Delay:

 2591 23:06:19.740857  DQS0 = 0, DQS1 = 0

 2592 23:06:19.743889  DQM Delay:

 2593 23:06:19.743973  DQM0 = 121, DQM1 = 113

 2594 23:06:19.747181  DQ Delay:

 2595 23:06:19.751053  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2596 23:06:19.753962  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2597 23:06:19.757393  DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107

 2598 23:06:19.760947  DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119

 2599 23:06:19.761032  

 2600 23:06:19.761117  

 2601 23:06:19.761198  ==

 2602 23:06:19.764127  Dram Type= 6, Freq= 0, CH_0, rank 0

 2603 23:06:19.767315  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2604 23:06:19.767400  ==

 2605 23:06:19.767485  

 2606 23:06:19.770825  

 2607 23:06:19.770908  	TX Vref Scan disable

 2608 23:06:19.774310   == TX Byte 0 ==

 2609 23:06:19.777735  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2610 23:06:19.780620  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2611 23:06:19.784110   == TX Byte 1 ==

 2612 23:06:19.787844  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2613 23:06:19.790703  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2614 23:06:19.790787  ==

 2615 23:06:19.794196  Dram Type= 6, Freq= 0, CH_0, rank 0

 2616 23:06:19.800830  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2617 23:06:19.800916  ==

 2618 23:06:19.811502  TX Vref=22, minBit 5, minWin=24, winSum=407

 2619 23:06:19.814509  TX Vref=24, minBit 0, minWin=25, winSum=413

 2620 23:06:19.818174  TX Vref=26, minBit 7, minWin=25, winSum=417

 2621 23:06:19.821604  TX Vref=28, minBit 0, minWin=26, winSum=427

 2622 23:06:19.824930  TX Vref=30, minBit 1, minWin=26, winSum=425

 2623 23:06:19.828130  TX Vref=32, minBit 0, minWin=26, winSum=422

 2624 23:06:19.835267  [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28

 2625 23:06:19.835383  

 2626 23:06:19.838210  Final TX Range 1 Vref 28

 2627 23:06:19.838292  

 2628 23:06:19.838357  ==

 2629 23:06:19.841321  Dram Type= 6, Freq= 0, CH_0, rank 0

 2630 23:06:19.844689  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2631 23:06:19.844770  ==

 2632 23:06:19.844833  

 2633 23:06:19.844892  

 2634 23:06:19.848381  	TX Vref Scan disable

 2635 23:06:19.851653   == TX Byte 0 ==

 2636 23:06:19.854619  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2637 23:06:19.858211  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2638 23:06:19.861639   == TX Byte 1 ==

 2639 23:06:19.864624  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2640 23:06:19.867923  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2641 23:06:19.868008  

 2642 23:06:19.871559  [DATLAT]

 2643 23:06:19.871643  Freq=1200, CH0 RK0

 2644 23:06:19.871730  

 2645 23:06:19.875066  DATLAT Default: 0xd

 2646 23:06:19.875150  0, 0xFFFF, sum = 0

 2647 23:06:19.878336  1, 0xFFFF, sum = 0

 2648 23:06:19.878422  2, 0xFFFF, sum = 0

 2649 23:06:19.881465  3, 0xFFFF, sum = 0

 2650 23:06:19.881550  4, 0xFFFF, sum = 0

 2651 23:06:19.885151  5, 0xFFFF, sum = 0

 2652 23:06:19.885237  6, 0xFFFF, sum = 0

 2653 23:06:19.888081  7, 0xFFFF, sum = 0

 2654 23:06:19.888166  8, 0xFFFF, sum = 0

 2655 23:06:19.891487  9, 0xFFFF, sum = 0

 2656 23:06:19.891573  10, 0xFFFF, sum = 0

 2657 23:06:19.894866  11, 0xFFFF, sum = 0

 2658 23:06:19.894952  12, 0x0, sum = 1

 2659 23:06:19.898051  13, 0x0, sum = 2

 2660 23:06:19.898137  14, 0x0, sum = 3

 2661 23:06:19.901634  15, 0x0, sum = 4

 2662 23:06:19.901719  best_step = 13

 2663 23:06:19.901805  

 2664 23:06:19.901886  ==

 2665 23:06:19.905126  Dram Type= 6, Freq= 0, CH_0, rank 0

 2666 23:06:19.911724  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2667 23:06:19.911809  ==

 2668 23:06:19.911894  RX Vref Scan: 1

 2669 23:06:19.911976  

 2670 23:06:19.915055  Set Vref Range= 32 -> 127

 2671 23:06:19.915140  

 2672 23:06:19.918165  RX Vref 32 -> 127, step: 1

 2673 23:06:19.918249  

 2674 23:06:19.921836  RX Delay -13 -> 252, step: 4

 2675 23:06:19.921920  

 2676 23:06:19.924664  Set Vref, RX VrefLevel [Byte0]: 32

 2677 23:06:19.927984                           [Byte1]: 32

 2678 23:06:19.928068  

 2679 23:06:19.931566  Set Vref, RX VrefLevel [Byte0]: 33

 2680 23:06:19.935078                           [Byte1]: 33

 2681 23:06:19.935163  

 2682 23:06:19.938146  Set Vref, RX VrefLevel [Byte0]: 34

 2683 23:06:19.941490                           [Byte1]: 34

 2684 23:06:19.945131  

 2685 23:06:19.945212  Set Vref, RX VrefLevel [Byte0]: 35

 2686 23:06:19.948838                           [Byte1]: 35

 2687 23:06:19.953677  

 2688 23:06:19.953757  Set Vref, RX VrefLevel [Byte0]: 36

 2689 23:06:19.956415                           [Byte1]: 36

 2690 23:06:19.961204  

 2691 23:06:19.961284  Set Vref, RX VrefLevel [Byte0]: 37

 2692 23:06:19.964487                           [Byte1]: 37

 2693 23:06:19.968836  

 2694 23:06:19.968916  Set Vref, RX VrefLevel [Byte0]: 38

 2695 23:06:19.972218                           [Byte1]: 38

 2696 23:06:19.977131  

 2697 23:06:19.977212  Set Vref, RX VrefLevel [Byte0]: 39

 2698 23:06:19.980392                           [Byte1]: 39

 2699 23:06:19.984876  

 2700 23:06:19.984956  Set Vref, RX VrefLevel [Byte0]: 40

 2701 23:06:19.988051                           [Byte1]: 40

 2702 23:06:19.992986  

 2703 23:06:19.993090  Set Vref, RX VrefLevel [Byte0]: 41

 2704 23:06:19.996010                           [Byte1]: 41

 2705 23:06:20.000471  

 2706 23:06:20.000551  Set Vref, RX VrefLevel [Byte0]: 42

 2707 23:06:20.004037                           [Byte1]: 42

 2708 23:06:20.008578  

 2709 23:06:20.008657  Set Vref, RX VrefLevel [Byte0]: 43

 2710 23:06:20.012023                           [Byte1]: 43

 2711 23:06:20.016797  

 2712 23:06:20.016877  Set Vref, RX VrefLevel [Byte0]: 44

 2713 23:06:20.020064                           [Byte1]: 44

 2714 23:06:20.024171  

 2715 23:06:20.024251  Set Vref, RX VrefLevel [Byte0]: 45

 2716 23:06:20.027765                           [Byte1]: 45

 2717 23:06:20.032541  

 2718 23:06:20.032621  Set Vref, RX VrefLevel [Byte0]: 46

 2719 23:06:20.035255                           [Byte1]: 46

 2720 23:06:20.039999  

 2721 23:06:20.040079  Set Vref, RX VrefLevel [Byte0]: 47

 2722 23:06:20.043427                           [Byte1]: 47

 2723 23:06:20.048302  

 2724 23:06:20.048384  Set Vref, RX VrefLevel [Byte0]: 48

 2725 23:06:20.051193                           [Byte1]: 48

 2726 23:06:20.055925  

 2727 23:06:20.056006  Set Vref, RX VrefLevel [Byte0]: 49

 2728 23:06:20.058965                           [Byte1]: 49

 2729 23:06:20.063983  

 2730 23:06:20.064067  Set Vref, RX VrefLevel [Byte0]: 50

 2731 23:06:20.067212                           [Byte1]: 50

 2732 23:06:20.071773  

 2733 23:06:20.071853  Set Vref, RX VrefLevel [Byte0]: 51

 2734 23:06:20.075316                           [Byte1]: 51

 2735 23:06:20.079374  

 2736 23:06:20.079453  Set Vref, RX VrefLevel [Byte0]: 52

 2737 23:06:20.082958                           [Byte1]: 52

 2738 23:06:20.087325  

 2739 23:06:20.087405  Set Vref, RX VrefLevel [Byte0]: 53

 2740 23:06:20.090391                           [Byte1]: 53

 2741 23:06:20.095355  

 2742 23:06:20.095435  Set Vref, RX VrefLevel [Byte0]: 54

 2743 23:06:20.098506                           [Byte1]: 54

 2744 23:06:20.103207  

 2745 23:06:20.103287  Set Vref, RX VrefLevel [Byte0]: 55

 2746 23:06:20.106750                           [Byte1]: 55

 2747 23:06:20.111264  

 2748 23:06:20.111344  Set Vref, RX VrefLevel [Byte0]: 56

 2749 23:06:20.114099                           [Byte1]: 56

 2750 23:06:20.119224  

 2751 23:06:20.119304  Set Vref, RX VrefLevel [Byte0]: 57

 2752 23:06:20.122376                           [Byte1]: 57

 2753 23:06:20.126823  

 2754 23:06:20.126903  Set Vref, RX VrefLevel [Byte0]: 58

 2755 23:06:20.130021                           [Byte1]: 58

 2756 23:06:20.134639  

 2757 23:06:20.134722  Set Vref, RX VrefLevel [Byte0]: 59

 2758 23:06:20.138267                           [Byte1]: 59

 2759 23:06:20.142675  

 2760 23:06:20.142755  Set Vref, RX VrefLevel [Byte0]: 60

 2761 23:06:20.146191                           [Byte1]: 60

 2762 23:06:20.150412  

 2763 23:06:20.150492  Set Vref, RX VrefLevel [Byte0]: 61

 2764 23:06:20.153953                           [Byte1]: 61

 2765 23:06:20.158689  

 2766 23:06:20.158768  Set Vref, RX VrefLevel [Byte0]: 62

 2767 23:06:20.161739                           [Byte1]: 62

 2768 23:06:20.166413  

 2769 23:06:20.166493  Set Vref, RX VrefLevel [Byte0]: 63

 2770 23:06:20.170060                           [Byte1]: 63

 2771 23:06:20.174307  

 2772 23:06:20.174387  Set Vref, RX VrefLevel [Byte0]: 64

 2773 23:06:20.177866                           [Byte1]: 64

 2774 23:06:20.181899  

 2775 23:06:20.181980  Set Vref, RX VrefLevel [Byte0]: 65

 2776 23:06:20.185391                           [Byte1]: 65

 2777 23:06:20.190120  

 2778 23:06:20.190200  Set Vref, RX VrefLevel [Byte0]: 66

 2779 23:06:20.193406                           [Byte1]: 66

 2780 23:06:20.197794  

 2781 23:06:20.197874  Set Vref, RX VrefLevel [Byte0]: 67

 2782 23:06:20.201289                           [Byte1]: 67

 2783 23:06:20.206004  

 2784 23:06:20.206083  Set Vref, RX VrefLevel [Byte0]: 68

 2785 23:06:20.208823                           [Byte1]: 68

 2786 23:06:20.213493  

 2787 23:06:20.213636  Set Vref, RX VrefLevel [Byte0]: 69

 2788 23:06:20.217069                           [Byte1]: 69

 2789 23:06:20.221305  

 2790 23:06:20.221385  Set Vref, RX VrefLevel [Byte0]: 70

 2791 23:06:20.224753                           [Byte1]: 70

 2792 23:06:20.229734  

 2793 23:06:20.229818  Final RX Vref Byte 0 = 53 to rank0

 2794 23:06:20.233119  Final RX Vref Byte 1 = 46 to rank0

 2795 23:06:20.235853  Final RX Vref Byte 0 = 53 to rank1

 2796 23:06:20.239716  Final RX Vref Byte 1 = 46 to rank1==

 2797 23:06:20.243178  Dram Type= 6, Freq= 0, CH_0, rank 0

 2798 23:06:20.246127  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2799 23:06:20.249486  ==

 2800 23:06:20.249590  DQS Delay:

 2801 23:06:20.249671  DQS0 = 0, DQS1 = 0

 2802 23:06:20.253049  DQM Delay:

 2803 23:06:20.253130  DQM0 = 121, DQM1 = 110

 2804 23:06:20.256017  DQ Delay:

 2805 23:06:20.259693  DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118

 2806 23:06:20.262698  DQ4 =124, DQ5 =112, DQ6 =126, DQ7 =128

 2807 23:06:20.266209  DQ8 =96, DQ9 =100, DQ10 =112, DQ11 =102

 2808 23:06:20.269764  DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =118

 2809 23:06:20.269844  

 2810 23:06:20.269907  

 2811 23:06:20.276454  [DQSOSCAuto] RK0, (LSB)MR18= 0x140d, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps

 2812 23:06:20.279782  CH0 RK0: MR19=404, MR18=140D

 2813 23:06:20.286267  CH0_RK0: MR19=0x404, MR18=0x140D, DQSOSC=402, MR23=63, INC=40, DEC=27

 2814 23:06:20.286348  

 2815 23:06:20.289762  ----->DramcWriteLeveling(PI) begin...

 2816 23:06:20.289844  ==

 2817 23:06:20.292696  Dram Type= 6, Freq= 0, CH_0, rank 1

 2818 23:06:20.296198  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2819 23:06:20.299670  ==

 2820 23:06:20.299750  Write leveling (Byte 0): 34 => 34

 2821 23:06:20.302923  Write leveling (Byte 1): 30 => 30

 2822 23:06:20.305841  DramcWriteLeveling(PI) end<-----

 2823 23:06:20.305922  

 2824 23:06:20.306017  ==

 2825 23:06:20.309354  Dram Type= 6, Freq= 0, CH_0, rank 1

 2826 23:06:20.316018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2827 23:06:20.316099  ==

 2828 23:06:20.316163  [Gating] SW mode calibration

 2829 23:06:20.326097  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2830 23:06:20.329281  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2831 23:06:20.332858   0 15  0 | B1->B0 | 3030 3030 | 1 1 | (0 0) (0 0)

 2832 23:06:20.339407   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2833 23:06:20.343237   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2834 23:06:20.346510   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2835 23:06:20.352784   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2836 23:06:20.356176   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2837 23:06:20.359354   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2838 23:06:20.366385   0 15 28 | B1->B0 | 3232 2d2d | 1 0 | (1 0) (1 0)

 2839 23:06:20.369478   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 2840 23:06:20.373083   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2841 23:06:20.379718   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2842 23:06:20.383212   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2843 23:06:20.386194   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2844 23:06:20.393095   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2845 23:06:20.396458   1  0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2846 23:06:20.399939   1  0 28 | B1->B0 | 3939 3b3b | 0 0 | (0 0) (0 0)

 2847 23:06:20.406259   1  1  0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 2848 23:06:20.409395   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2849 23:06:20.413203   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2850 23:06:20.416204   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2851 23:06:20.423071   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2852 23:06:20.426164   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2853 23:06:20.429979   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2854 23:06:20.436109   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 2855 23:06:20.439520   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 2856 23:06:20.442948   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2857 23:06:20.450012   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2858 23:06:20.453217   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2859 23:06:20.456506   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2860 23:06:20.463026   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2861 23:06:20.466299   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2862 23:06:20.469903   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2863 23:06:20.476197   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2864 23:06:20.479986   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2865 23:06:20.482838   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2866 23:06:20.486418   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2867 23:06:20.493080   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2868 23:06:20.496608   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2869 23:06:20.499668   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2870 23:06:20.506601   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2871 23:06:20.509712   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 2872 23:06:20.513106  Total UI for P1: 0, mck2ui 16

 2873 23:06:20.516678  best dqsien dly found for B1: ( 1,  3, 28)

 2874 23:06:20.520217   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2875 23:06:20.523284  Total UI for P1: 0, mck2ui 16

 2876 23:06:20.526910  best dqsien dly found for B0: ( 1,  3, 30)

 2877 23:06:20.529950  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2878 23:06:20.533472  best DQS1 dly(MCK, UI, PI) = (1, 3, 28)

 2879 23:06:20.533553  

 2880 23:06:20.539948  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2881 23:06:20.543388  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)

 2882 23:06:20.543469  [Gating] SW calibration Done

 2883 23:06:20.547007  ==

 2884 23:06:20.547147  Dram Type= 6, Freq= 0, CH_0, rank 1

 2885 23:06:20.553550  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2886 23:06:20.553681  ==

 2887 23:06:20.553746  RX Vref Scan: 0

 2888 23:06:20.553806  

 2889 23:06:20.556807  RX Vref 0 -> 0, step: 1

 2890 23:06:20.556903  

 2891 23:06:20.560174  RX Delay -40 -> 252, step: 8

 2892 23:06:20.563123  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2893 23:06:20.566637  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 2894 23:06:20.570356  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2895 23:06:20.576657  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2896 23:06:20.580247  iDelay=200, Bit 4, Center 127 (56 ~ 199) 144

 2897 23:06:20.583265  iDelay=200, Bit 5, Center 119 (48 ~ 191) 144

 2898 23:06:20.587037  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2899 23:06:20.590133  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2900 23:06:20.596893  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2901 23:06:20.599840  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 2902 23:06:20.603390  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2903 23:06:20.606441  iDelay=200, Bit 11, Center 103 (32 ~ 175) 144

 2904 23:06:20.609897  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2905 23:06:20.616595  iDelay=200, Bit 13, Center 119 (48 ~ 191) 144

 2906 23:06:20.620252  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2907 23:06:20.623302  iDelay=200, Bit 15, Center 119 (56 ~ 183) 128

 2908 23:06:20.623384  ==

 2909 23:06:20.626318  Dram Type= 6, Freq= 0, CH_0, rank 1

 2910 23:06:20.629930  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2911 23:06:20.630012  ==

 2912 23:06:20.633560  DQS Delay:

 2913 23:06:20.633680  DQS0 = 0, DQS1 = 0

 2914 23:06:20.637165  DQM Delay:

 2915 23:06:20.637245  DQM0 = 122, DQM1 = 111

 2916 23:06:20.637309  DQ Delay:

 2917 23:06:20.639905  DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119

 2918 23:06:20.643503  DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127

 2919 23:06:20.650006  DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103

 2920 23:06:20.653395  DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119

 2921 23:06:20.653476  

 2922 23:06:20.653538  

 2923 23:06:20.653640  ==

 2924 23:06:20.656913  Dram Type= 6, Freq= 0, CH_0, rank 1

 2925 23:06:20.659973  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2926 23:06:20.660054  ==

 2927 23:06:20.660118  

 2928 23:06:20.660177  

 2929 23:06:20.663386  	TX Vref Scan disable

 2930 23:06:20.663466   == TX Byte 0 ==

 2931 23:06:20.670070  Update DQ  dly =854 (3 ,2, 22)  DQ  OEN =(2 ,7)

 2932 23:06:20.673437  Update DQM dly =854 (3 ,2, 22)  DQM OEN =(2 ,7)

 2933 23:06:20.673517   == TX Byte 1 ==

 2934 23:06:20.680198  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2935 23:06:20.683900  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2936 23:06:20.683981  ==

 2937 23:06:20.686841  Dram Type= 6, Freq= 0, CH_0, rank 1

 2938 23:06:20.690301  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2939 23:06:20.690383  ==

 2940 23:06:20.703476  TX Vref=22, minBit 5, minWin=24, winSum=411

 2941 23:06:20.706574  TX Vref=24, minBit 2, minWin=25, winSum=412

 2942 23:06:20.710190  TX Vref=26, minBit 3, minWin=25, winSum=420

 2943 23:06:20.713243  TX Vref=28, minBit 12, minWin=25, winSum=421

 2944 23:06:20.716774  TX Vref=30, minBit 1, minWin=26, winSum=425

 2945 23:06:20.720344  TX Vref=32, minBit 0, minWin=26, winSum=425

 2946 23:06:20.726556  [TxChooseVref] Worse bit 1, Min win 26, Win sum 425, Final Vref 30

 2947 23:06:20.726639  

 2948 23:06:20.730014  Final TX Range 1 Vref 30

 2949 23:06:20.730096  

 2950 23:06:20.730159  ==

 2951 23:06:20.733500  Dram Type= 6, Freq= 0, CH_0, rank 1

 2952 23:06:20.736527  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2953 23:06:20.736608  ==

 2954 23:06:20.736672  

 2955 23:06:20.740078  

 2956 23:06:20.740158  	TX Vref Scan disable

 2957 23:06:20.743799   == TX Byte 0 ==

 2958 23:06:20.746707  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2959 23:06:20.750312  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2960 23:06:20.753380   == TX Byte 1 ==

 2961 23:06:20.756891  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 2962 23:06:20.760362  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 2963 23:06:20.760443  

 2964 23:06:20.763462  [DATLAT]

 2965 23:06:20.763542  Freq=1200, CH0 RK1

 2966 23:06:20.763614  

 2967 23:06:20.766953  DATLAT Default: 0xd

 2968 23:06:20.767033  0, 0xFFFF, sum = 0

 2969 23:06:20.769989  1, 0xFFFF, sum = 0

 2970 23:06:20.770071  2, 0xFFFF, sum = 0

 2971 23:06:20.773481  3, 0xFFFF, sum = 0

 2972 23:06:20.773563  4, 0xFFFF, sum = 0

 2973 23:06:20.776853  5, 0xFFFF, sum = 0

 2974 23:06:20.776934  6, 0xFFFF, sum = 0

 2975 23:06:20.780429  7, 0xFFFF, sum = 0

 2976 23:06:20.783621  8, 0xFFFF, sum = 0

 2977 23:06:20.783703  9, 0xFFFF, sum = 0

 2978 23:06:20.786515  10, 0xFFFF, sum = 0

 2979 23:06:20.786597  11, 0xFFFF, sum = 0

 2980 23:06:20.790078  12, 0x0, sum = 1

 2981 23:06:20.790160  13, 0x0, sum = 2

 2982 23:06:20.793731  14, 0x0, sum = 3

 2983 23:06:20.793845  15, 0x0, sum = 4

 2984 23:06:20.793910  best_step = 13

 2985 23:06:20.793969  

 2986 23:06:20.796687  ==

 2987 23:06:20.800337  Dram Type= 6, Freq= 0, CH_0, rank 1

 2988 23:06:20.803769  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2989 23:06:20.803850  ==

 2990 23:06:20.803914  RX Vref Scan: 0

 2991 23:06:20.803972  

 2992 23:06:20.806854  RX Vref 0 -> 0, step: 1

 2993 23:06:20.806934  

 2994 23:06:20.810522  RX Delay -13 -> 252, step: 4

 2995 23:06:20.813454  iDelay=195, Bit 0, Center 118 (51 ~ 186) 136

 2996 23:06:20.816789  iDelay=195, Bit 1, Center 122 (55 ~ 190) 136

 2997 23:06:20.823789  iDelay=195, Bit 2, Center 118 (51 ~ 186) 136

 2998 23:06:20.826748  iDelay=195, Bit 3, Center 118 (51 ~ 186) 136

 2999 23:06:20.830316  iDelay=195, Bit 4, Center 122 (55 ~ 190) 136

 3000 23:06:20.833788  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3001 23:06:20.837021  iDelay=195, Bit 6, Center 126 (63 ~ 190) 128

 3002 23:06:20.843767  iDelay=195, Bit 7, Center 128 (63 ~ 194) 132

 3003 23:06:20.847194  iDelay=195, Bit 8, Center 100 (35 ~ 166) 132

 3004 23:06:20.850260  iDelay=195, Bit 9, Center 96 (31 ~ 162) 132

 3005 23:06:20.853742  iDelay=195, Bit 10, Center 110 (47 ~ 174) 128

 3006 23:06:20.857127  iDelay=195, Bit 11, Center 100 (35 ~ 166) 132

 3007 23:06:20.863760  iDelay=195, Bit 12, Center 114 (51 ~ 178) 128

 3008 23:06:20.867145  iDelay=195, Bit 13, Center 116 (55 ~ 178) 124

 3009 23:06:20.870269  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3010 23:06:20.873912  iDelay=195, Bit 15, Center 118 (55 ~ 182) 128

 3011 23:06:20.873993  ==

 3012 23:06:20.876883  Dram Type= 6, Freq= 0, CH_0, rank 1

 3013 23:06:20.880338  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3014 23:06:20.883731  ==

 3015 23:06:20.883811  DQS Delay:

 3016 23:06:20.883875  DQS0 = 0, DQS1 = 0

 3017 23:06:20.887141  DQM Delay:

 3018 23:06:20.887221  DQM0 = 121, DQM1 = 109

 3019 23:06:20.890431  DQ Delay:

 3020 23:06:20.893787  DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118

 3021 23:06:20.897372  DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =128

 3022 23:06:20.900828  DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =100

 3023 23:06:20.903949  DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =118

 3024 23:06:20.904029  

 3025 23:06:20.904092  

 3026 23:06:20.911058  [DQSOSCAuto] RK1, (LSB)MR18= 0xdef, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 405 ps

 3027 23:06:20.913890  CH0 RK1: MR19=403, MR18=DEF

 3028 23:06:20.920706  CH0_RK1: MR19=0x403, MR18=0xDEF, DQSOSC=405, MR23=63, INC=39, DEC=26

 3029 23:06:20.924139  [RxdqsGatingPostProcess] freq 1200

 3030 23:06:20.927384  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3031 23:06:20.930891  best DQS0 dly(2T, 0.5T) = (0, 11)

 3032 23:06:20.933936  best DQS1 dly(2T, 0.5T) = (0, 12)

 3033 23:06:20.937484  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3034 23:06:20.940699  best DQS1 P1 dly(2T, 0.5T) = (1, 0)

 3035 23:06:20.944043  best DQS0 dly(2T, 0.5T) = (0, 11)

 3036 23:06:20.947089  best DQS1 dly(2T, 0.5T) = (0, 11)

 3037 23:06:20.950502  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3038 23:06:20.954083  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3039 23:06:20.957699  Pre-setting of DQS Precalculation

 3040 23:06:20.960758  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3041 23:06:20.960839  ==

 3042 23:06:20.964219  Dram Type= 6, Freq= 0, CH_1, rank 0

 3043 23:06:20.970604  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3044 23:06:20.970685  ==

 3045 23:06:20.974174  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3046 23:06:20.980571  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3047 23:06:20.989712  [CA 0] Center 37 (7~68) winsize 62

 3048 23:06:20.992670  [CA 1] Center 37 (7~68) winsize 62

 3049 23:06:20.996284  [CA 2] Center 35 (5~65) winsize 61

 3050 23:06:20.999634  [CA 3] Center 34 (4~64) winsize 61

 3051 23:06:21.003082  [CA 4] Center 34 (4~64) winsize 61

 3052 23:06:21.005872  [CA 5] Center 33 (3~63) winsize 61

 3053 23:06:21.005953  

 3054 23:06:21.009457  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3055 23:06:21.009537  

 3056 23:06:21.013134  [CATrainingPosCal] consider 1 rank data

 3057 23:06:21.015995  u2DelayCellTimex100 = 270/100 ps

 3058 23:06:21.019512  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3059 23:06:21.022472  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3060 23:06:21.029490  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3061 23:06:21.032458  CA3 delay=34 (4~64),Diff = 1 PI (4 cell)

 3062 23:06:21.036109  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3063 23:06:21.039484  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3064 23:06:21.039564  

 3065 23:06:21.042815  CA PerBit enable=1, Macro0, CA PI delay=33

 3066 23:06:21.042896  

 3067 23:06:21.046192  [CBTSetCACLKResult] CA Dly = 33

 3068 23:06:21.046274  CS Dly: 8 (0~39)

 3069 23:06:21.046338  ==

 3070 23:06:21.049658  Dram Type= 6, Freq= 0, CH_1, rank 1

 3071 23:06:21.056270  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3072 23:06:21.056351  ==

 3073 23:06:21.059787  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3074 23:06:21.065913  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3075 23:06:21.075074  [CA 0] Center 37 (7~68) winsize 62

 3076 23:06:21.078810  [CA 1] Center 37 (7~68) winsize 62

 3077 23:06:21.081552  [CA 2] Center 35 (5~65) winsize 61

 3078 23:06:21.085081  [CA 3] Center 35 (5~65) winsize 61

 3079 23:06:21.088556  [CA 4] Center 34 (4~65) winsize 62

 3080 23:06:21.092105  [CA 5] Center 34 (4~64) winsize 61

 3081 23:06:21.092185  

 3082 23:06:21.095064  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3083 23:06:21.095145  

 3084 23:06:21.098379  [CATrainingPosCal] consider 2 rank data

 3085 23:06:21.101914  u2DelayCellTimex100 = 270/100 ps

 3086 23:06:21.105177  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3087 23:06:21.108654  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3088 23:06:21.114885  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3089 23:06:21.118416  CA3 delay=34 (5~64),Diff = 1 PI (4 cell)

 3090 23:06:21.121945  CA4 delay=34 (4~64),Diff = 1 PI (4 cell)

 3091 23:06:21.124915  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3092 23:06:21.124995  

 3093 23:06:21.128678  CA PerBit enable=1, Macro0, CA PI delay=33

 3094 23:06:21.128758  

 3095 23:06:21.131659  [CBTSetCACLKResult] CA Dly = 33

 3096 23:06:21.131738  CS Dly: 8 (0~40)

 3097 23:06:21.131803  

 3098 23:06:21.135191  ----->DramcWriteLeveling(PI) begin...

 3099 23:06:21.138772  ==

 3100 23:06:21.138856  Dram Type= 6, Freq= 0, CH_1, rank 0

 3101 23:06:21.145452  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3102 23:06:21.145534  ==

 3103 23:06:21.148587  Write leveling (Byte 0): 27 => 27

 3104 23:06:21.151673  Write leveling (Byte 1): 27 => 27

 3105 23:06:21.155174  DramcWriteLeveling(PI) end<-----

 3106 23:06:21.155255  

 3107 23:06:21.155319  ==

 3108 23:06:21.158205  Dram Type= 6, Freq= 0, CH_1, rank 0

 3109 23:06:21.161779  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3110 23:06:21.161860  ==

 3111 23:06:21.165156  [Gating] SW mode calibration

 3112 23:06:21.171581  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3113 23:06:21.175097  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3114 23:06:21.181961   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3115 23:06:21.184822   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3116 23:06:21.188248   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3117 23:06:21.195047   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3118 23:06:21.198502   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3119 23:06:21.201556   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3120 23:06:21.208295   0 15 24 | B1->B0 | 3434 2e2e | 1 0 | (1 0) (0 0)

 3121 23:06:21.211566   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 3122 23:06:21.215058   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3123 23:06:21.221423   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3124 23:06:21.224859   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3125 23:06:21.228460   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3126 23:06:21.234872   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3127 23:06:21.238612   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3128 23:06:21.241608   1  0 24 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)

 3129 23:06:21.248655   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3130 23:06:21.252258   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3131 23:06:21.255146   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3132 23:06:21.258589   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3133 23:06:21.265213   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3134 23:06:21.268663   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3135 23:06:21.271503   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3136 23:06:21.278733   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3137 23:06:21.282281   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3138 23:06:21.285365   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3139 23:06:21.292092   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3140 23:06:21.295686   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3141 23:06:21.299181   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3142 23:06:21.305384   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3143 23:06:21.308600   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3144 23:06:21.311977   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3145 23:06:21.318677   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3146 23:06:21.321917   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3147 23:06:21.325399   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3148 23:06:21.332251   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3149 23:06:21.335753   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3150 23:06:21.338865   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3151 23:06:21.342262   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3152 23:06:21.348713   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3153 23:06:21.352383   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3154 23:06:21.355475   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3155 23:06:21.358753  Total UI for P1: 0, mck2ui 16

 3156 23:06:21.362439  best dqsien dly found for B0: ( 1,  3, 26)

 3157 23:06:21.365364  Total UI for P1: 0, mck2ui 16

 3158 23:06:21.369088  best dqsien dly found for B1: ( 1,  3, 26)

 3159 23:06:21.372513  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3160 23:06:21.375410  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3161 23:06:21.375491  

 3162 23:06:21.382301  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3163 23:06:21.385311  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3164 23:06:21.385391  [Gating] SW calibration Done

 3165 23:06:21.388909  ==

 3166 23:06:21.391962  Dram Type= 6, Freq= 0, CH_1, rank 0

 3167 23:06:21.395296  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3168 23:06:21.395377  ==

 3169 23:06:21.395440  RX Vref Scan: 0

 3170 23:06:21.395501  

 3171 23:06:21.398904  RX Vref 0 -> 0, step: 1

 3172 23:06:21.398984  

 3173 23:06:21.402088  RX Delay -40 -> 252, step: 8

 3174 23:06:21.405109  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3175 23:06:21.408631  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3176 23:06:21.415201  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3177 23:06:21.418696  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3178 23:06:21.421754  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3179 23:06:21.425559  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3180 23:06:21.428831  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3181 23:06:21.432223  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3182 23:06:21.438593  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3183 23:06:21.441869  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3184 23:06:21.445687  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3185 23:06:21.448635  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3186 23:06:21.451974  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3187 23:06:21.458709  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3188 23:06:21.462105  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3189 23:06:21.465765  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3190 23:06:21.465845  ==

 3191 23:06:21.468793  Dram Type= 6, Freq= 0, CH_1, rank 0

 3192 23:06:21.472271  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3193 23:06:21.472352  ==

 3194 23:06:21.475970  DQS Delay:

 3195 23:06:21.476051  DQS0 = 0, DQS1 = 0

 3196 23:06:21.478838  DQM Delay:

 3197 23:06:21.478919  DQM0 = 120, DQM1 = 116

 3198 23:06:21.478982  DQ Delay:

 3199 23:06:21.485810  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3200 23:06:21.489311  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123

 3201 23:06:21.492137  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3202 23:06:21.495689  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3203 23:06:21.495770  

 3204 23:06:21.495833  

 3205 23:06:21.495891  ==

 3206 23:06:21.498725  Dram Type= 6, Freq= 0, CH_1, rank 0

 3207 23:06:21.502352  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3208 23:06:21.502433  ==

 3209 23:06:21.502497  

 3210 23:06:21.502556  

 3211 23:06:21.505935  	TX Vref Scan disable

 3212 23:06:21.508860   == TX Byte 0 ==

 3213 23:06:21.512504  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3214 23:06:21.515766  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3215 23:06:21.519220   == TX Byte 1 ==

 3216 23:06:21.522182  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3217 23:06:21.525665  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3218 23:06:21.525746  ==

 3219 23:06:21.529058  Dram Type= 6, Freq= 0, CH_1, rank 0

 3220 23:06:21.532651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3221 23:06:21.532732  ==

 3222 23:06:21.545300  TX Vref=22, minBit 9, minWin=24, winSum=408

 3223 23:06:21.548394  TX Vref=24, minBit 9, minWin=25, winSum=419

 3224 23:06:21.551808  TX Vref=26, minBit 9, minWin=25, winSum=420

 3225 23:06:21.555129  TX Vref=28, minBit 9, minWin=25, winSum=425

 3226 23:06:21.558566  TX Vref=30, minBit 1, minWin=26, winSum=429

 3227 23:06:21.561725  TX Vref=32, minBit 9, minWin=26, winSum=430

 3228 23:06:21.568454  [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 32

 3229 23:06:21.568534  

 3230 23:06:21.571629  Final TX Range 1 Vref 32

 3231 23:06:21.571701  

 3232 23:06:21.571761  ==

 3233 23:06:21.575297  Dram Type= 6, Freq= 0, CH_1, rank 0

 3234 23:06:21.578386  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3235 23:06:21.578468  ==

 3236 23:06:21.582127  

 3237 23:06:21.582208  

 3238 23:06:21.582271  	TX Vref Scan disable

 3239 23:06:21.585187   == TX Byte 0 ==

 3240 23:06:21.588644  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3241 23:06:21.591856  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3242 23:06:21.595383   == TX Byte 1 ==

 3243 23:06:21.598663  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3244 23:06:21.601970  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3245 23:06:21.602072  

 3246 23:06:21.605038  [DATLAT]

 3247 23:06:21.605110  Freq=1200, CH1 RK0

 3248 23:06:21.605172  

 3249 23:06:21.608857  DATLAT Default: 0xd

 3250 23:06:21.608961  0, 0xFFFF, sum = 0

 3251 23:06:21.612045  1, 0xFFFF, sum = 0

 3252 23:06:21.612144  2, 0xFFFF, sum = 0

 3253 23:06:21.614984  3, 0xFFFF, sum = 0

 3254 23:06:21.615072  4, 0xFFFF, sum = 0

 3255 23:06:21.618633  5, 0xFFFF, sum = 0

 3256 23:06:21.618735  6, 0xFFFF, sum = 0

 3257 23:06:21.621715  7, 0xFFFF, sum = 0

 3258 23:06:21.621791  8, 0xFFFF, sum = 0

 3259 23:06:21.625027  9, 0xFFFF, sum = 0

 3260 23:06:21.628572  10, 0xFFFF, sum = 0

 3261 23:06:21.628678  11, 0xFFFF, sum = 0

 3262 23:06:21.631774  12, 0x0, sum = 1

 3263 23:06:21.631874  13, 0x0, sum = 2

 3264 23:06:21.631965  14, 0x0, sum = 3

 3265 23:06:21.635531  15, 0x0, sum = 4

 3266 23:06:21.635636  best_step = 13

 3267 23:06:21.635724  

 3268 23:06:21.638402  ==

 3269 23:06:21.638485  Dram Type= 6, Freq= 0, CH_1, rank 0

 3270 23:06:21.645071  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3271 23:06:21.645191  ==

 3272 23:06:21.645285  RX Vref Scan: 1

 3273 23:06:21.645374  

 3274 23:06:21.648355  Set Vref Range= 32 -> 127

 3275 23:06:21.648527  

 3276 23:06:21.651679  RX Vref 32 -> 127, step: 1

 3277 23:06:21.651791  

 3278 23:06:21.655410  RX Delay -5 -> 252, step: 4

 3279 23:06:21.655492  

 3280 23:06:21.658565  Set Vref, RX VrefLevel [Byte0]: 32

 3281 23:06:21.661542                           [Byte1]: 32

 3282 23:06:21.661658  

 3283 23:06:21.665041  Set Vref, RX VrefLevel [Byte0]: 33

 3284 23:06:21.668283                           [Byte1]: 33

 3285 23:06:21.668361  

 3286 23:06:21.671668  Set Vref, RX VrefLevel [Byte0]: 34

 3287 23:06:21.675321                           [Byte1]: 34

 3288 23:06:21.679194  

 3289 23:06:21.679298  Set Vref, RX VrefLevel [Byte0]: 35

 3290 23:06:21.682179                           [Byte1]: 35

 3291 23:06:21.686694  

 3292 23:06:21.686798  Set Vref, RX VrefLevel [Byte0]: 36

 3293 23:06:21.690486                           [Byte1]: 36

 3294 23:06:21.694654  

 3295 23:06:21.694736  Set Vref, RX VrefLevel [Byte0]: 37

 3296 23:06:21.698280                           [Byte1]: 37

 3297 23:06:21.702810  

 3298 23:06:21.702916  Set Vref, RX VrefLevel [Byte0]: 38

 3299 23:06:21.705783                           [Byte1]: 38

 3300 23:06:21.710129  

 3301 23:06:21.710201  Set Vref, RX VrefLevel [Byte0]: 39

 3302 23:06:21.713840                           [Byte1]: 39

 3303 23:06:21.718072  

 3304 23:06:21.718171  Set Vref, RX VrefLevel [Byte0]: 40

 3305 23:06:21.721267                           [Byte1]: 40

 3306 23:06:21.726077  

 3307 23:06:21.726149  Set Vref, RX VrefLevel [Byte0]: 41

 3308 23:06:21.729572                           [Byte1]: 41

 3309 23:06:21.733919  

 3310 23:06:21.734003  Set Vref, RX VrefLevel [Byte0]: 42

 3311 23:06:21.737222                           [Byte1]: 42

 3312 23:06:21.741560  

 3313 23:06:21.741659  Set Vref, RX VrefLevel [Byte0]: 43

 3314 23:06:21.745329                           [Byte1]: 43

 3315 23:06:21.749323  

 3316 23:06:21.749421  Set Vref, RX VrefLevel [Byte0]: 44

 3317 23:06:21.753002                           [Byte1]: 44

 3318 23:06:21.757769  

 3319 23:06:21.757842  Set Vref, RX VrefLevel [Byte0]: 45

 3320 23:06:21.760911                           [Byte1]: 45

 3321 23:06:21.765196  

 3322 23:06:21.765294  Set Vref, RX VrefLevel [Byte0]: 46

 3323 23:06:21.768548                           [Byte1]: 46

 3324 23:06:21.773316  

 3325 23:06:21.773416  Set Vref, RX VrefLevel [Byte0]: 47

 3326 23:06:21.776329                           [Byte1]: 47

 3327 23:06:21.781102  

 3328 23:06:21.781205  Set Vref, RX VrefLevel [Byte0]: 48

 3329 23:06:21.784720                           [Byte1]: 48

 3330 23:06:21.789278  

 3331 23:06:21.789379  Set Vref, RX VrefLevel [Byte0]: 49

 3332 23:06:21.792169                           [Byte1]: 49

 3333 23:06:21.796935  

 3334 23:06:21.797042  Set Vref, RX VrefLevel [Byte0]: 50

 3335 23:06:21.799997                           [Byte1]: 50

 3336 23:06:21.804835  

 3337 23:06:21.804944  Set Vref, RX VrefLevel [Byte0]: 51

 3338 23:06:21.807838                           [Byte1]: 51

 3339 23:06:21.812636  

 3340 23:06:21.812742  Set Vref, RX VrefLevel [Byte0]: 52

 3341 23:06:21.815766                           [Byte1]: 52

 3342 23:06:21.820145  

 3343 23:06:21.820246  Set Vref, RX VrefLevel [Byte0]: 53

 3344 23:06:21.823778                           [Byte1]: 53

 3345 23:06:21.828090  

 3346 23:06:21.828187  Set Vref, RX VrefLevel [Byte0]: 54

 3347 23:06:21.831841                           [Byte1]: 54

 3348 23:06:21.836250  

 3349 23:06:21.836347  Set Vref, RX VrefLevel [Byte0]: 55

 3350 23:06:21.839557                           [Byte1]: 55

 3351 23:06:21.843680  

 3352 23:06:21.843780  Set Vref, RX VrefLevel [Byte0]: 56

 3353 23:06:21.847120                           [Byte1]: 56

 3354 23:06:21.851875  

 3355 23:06:21.851973  Set Vref, RX VrefLevel [Byte0]: 57

 3356 23:06:21.854833                           [Byte1]: 57

 3357 23:06:21.859518  

 3358 23:06:21.859625  Set Vref, RX VrefLevel [Byte0]: 58

 3359 23:06:21.863111                           [Byte1]: 58

 3360 23:06:21.867343  

 3361 23:06:21.867444  Set Vref, RX VrefLevel [Byte0]: 59

 3362 23:06:21.870821                           [Byte1]: 59

 3363 23:06:21.875300  

 3364 23:06:21.875400  Set Vref, RX VrefLevel [Byte0]: 60

 3365 23:06:21.878291                           [Byte1]: 60

 3366 23:06:21.883354  

 3367 23:06:21.883456  Set Vref, RX VrefLevel [Byte0]: 61

 3368 23:06:21.886428                           [Byte1]: 61

 3369 23:06:21.891194  

 3370 23:06:21.891267  Set Vref, RX VrefLevel [Byte0]: 62

 3371 23:06:21.894222                           [Byte1]: 62

 3372 23:06:21.898718  

 3373 23:06:21.898793  Set Vref, RX VrefLevel [Byte0]: 63

 3374 23:06:21.902050                           [Byte1]: 63

 3375 23:06:21.906604  

 3376 23:06:21.906676  Set Vref, RX VrefLevel [Byte0]: 64

 3377 23:06:21.909886                           [Byte1]: 64

 3378 23:06:21.914560  

 3379 23:06:21.914634  Set Vref, RX VrefLevel [Byte0]: 65

 3380 23:06:21.917566                           [Byte1]: 65

 3381 23:06:21.922279  

 3382 23:06:21.922353  Set Vref, RX VrefLevel [Byte0]: 66

 3383 23:06:21.925880                           [Byte1]: 66

 3384 23:06:21.930094  

 3385 23:06:21.930161  Set Vref, RX VrefLevel [Byte0]: 67

 3386 23:06:21.933529                           [Byte1]: 67

 3387 23:06:21.938290  

 3388 23:06:21.938390  Final RX Vref Byte 0 = 53 to rank0

 3389 23:06:21.941141  Final RX Vref Byte 1 = 51 to rank0

 3390 23:06:21.944643  Final RX Vref Byte 0 = 53 to rank1

 3391 23:06:21.947856  Final RX Vref Byte 1 = 51 to rank1==

 3392 23:06:21.951134  Dram Type= 6, Freq= 0, CH_1, rank 0

 3393 23:06:21.957994  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3394 23:06:21.958076  ==

 3395 23:06:21.958143  DQS Delay:

 3396 23:06:21.958202  DQS0 = 0, DQS1 = 0

 3397 23:06:21.961677  DQM Delay:

 3398 23:06:21.961746  DQM0 = 120, DQM1 = 117

 3399 23:06:21.964691  DQ Delay:

 3400 23:06:21.968156  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116

 3401 23:06:21.971734  DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120

 3402 23:06:21.974767  DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =110

 3403 23:06:21.978340  DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126

 3404 23:06:21.978418  

 3405 23:06:21.978505  

 3406 23:06:21.984961  [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps

 3407 23:06:21.987834  CH1 RK0: MR19=404, MR18=215

 3408 23:06:21.994963  CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27

 3409 23:06:21.995044  

 3410 23:06:21.998221  ----->DramcWriteLeveling(PI) begin...

 3411 23:06:21.998321  ==

 3412 23:06:22.001143  Dram Type= 6, Freq= 0, CH_1, rank 1

 3413 23:06:22.004961  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3414 23:06:22.005059  ==

 3415 23:06:22.007893  Write leveling (Byte 0): 25 => 25

 3416 23:06:22.011344  Write leveling (Byte 1): 30 => 30

 3417 23:06:22.014693  DramcWriteLeveling(PI) end<-----

 3418 23:06:22.014766  

 3419 23:06:22.014832  ==

 3420 23:06:22.018480  Dram Type= 6, Freq= 0, CH_1, rank 1

 3421 23:06:22.024971  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3422 23:06:22.025055  ==

 3423 23:06:22.025132  [Gating] SW mode calibration

 3424 23:06:22.035013  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3425 23:06:22.037962  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3426 23:06:22.041496   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3427 23:06:22.048460   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3428 23:06:22.051485   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3429 23:06:22.054941   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3430 23:06:22.061414   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3431 23:06:22.065045   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 3432 23:06:22.068410   0 15 24 | B1->B0 | 2d2d 3434 | 0 1 | (0 1) (0 1)

 3433 23:06:22.075031   0 15 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)

 3434 23:06:22.078014   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3435 23:06:22.081468   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3436 23:06:22.088093   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3437 23:06:22.091835   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3438 23:06:22.094800   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3439 23:06:22.098039   1  0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 3440 23:06:22.104971   1  0 24 | B1->B0 | 4242 2c2c | 0 1 | (1 1) (0 0)

 3441 23:06:22.108622   1  0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 3442 23:06:22.111644   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3443 23:06:22.118099   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3444 23:06:22.122272   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3445 23:06:22.124850   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3446 23:06:22.131624   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3447 23:06:22.134759   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3448 23:06:22.138313   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3449 23:06:22.145111   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3450 23:06:22.148376   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3451 23:06:22.151648   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3452 23:06:22.158758   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3453 23:06:22.161628   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3454 23:06:22.165238   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3455 23:06:22.171719   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3456 23:06:22.174814   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3457 23:06:22.178178   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3458 23:06:22.181913   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3459 23:06:22.188345   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3460 23:06:22.192061   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3461 23:06:22.195057   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3462 23:06:22.201666   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3463 23:06:22.204894   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3464 23:06:22.208276   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3465 23:06:22.214643   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3466 23:06:22.218215  Total UI for P1: 0, mck2ui 16

 3467 23:06:22.221426  best dqsien dly found for B1: ( 1,  3, 22)

 3468 23:06:22.224932   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3469 23:06:22.228289  Total UI for P1: 0, mck2ui 16

 3470 23:06:22.231856  best dqsien dly found for B0: ( 1,  3, 26)

 3471 23:06:22.234827  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 3472 23:06:22.238466  best DQS1 dly(MCK, UI, PI) = (1, 3, 22)

 3473 23:06:22.238566  

 3474 23:06:22.241292  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3475 23:06:22.245147  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)

 3476 23:06:22.248507  [Gating] SW calibration Done

 3477 23:06:22.248589  ==

 3478 23:06:22.251667  Dram Type= 6, Freq= 0, CH_1, rank 1

 3479 23:06:22.255059  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3480 23:06:22.258256  ==

 3481 23:06:22.258336  RX Vref Scan: 0

 3482 23:06:22.258416  

 3483 23:06:22.261412  RX Vref 0 -> 0, step: 1

 3484 23:06:22.261503  

 3485 23:06:22.264920  RX Delay -40 -> 252, step: 8

 3486 23:06:22.268453  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3487 23:06:22.271414  iDelay=200, Bit 1, Center 119 (48 ~ 191) 144

 3488 23:06:22.275220  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3489 23:06:22.278212  iDelay=200, Bit 3, Center 119 (56 ~ 183) 128

 3490 23:06:22.285180  iDelay=200, Bit 4, Center 119 (56 ~ 183) 128

 3491 23:06:22.288610  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3492 23:06:22.291622  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3493 23:06:22.294847  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3494 23:06:22.298629  iDelay=200, Bit 8, Center 107 (40 ~ 175) 136

 3495 23:06:22.301880  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3496 23:06:22.308476  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3497 23:06:22.312170  iDelay=200, Bit 11, Center 115 (48 ~ 183) 136

 3498 23:06:22.315350  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3499 23:06:22.318397  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3500 23:06:22.325220  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3501 23:06:22.328253  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3502 23:06:22.328359  ==

 3503 23:06:22.331918  Dram Type= 6, Freq= 0, CH_1, rank 1

 3504 23:06:22.334829  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3505 23:06:22.334912  ==

 3506 23:06:22.334972  DQS Delay:

 3507 23:06:22.338443  DQS0 = 0, DQS1 = 0

 3508 23:06:22.338548  DQM Delay:

 3509 23:06:22.341642  DQM0 = 121, DQM1 = 118

 3510 23:06:22.341715  DQ Delay:

 3511 23:06:22.345280  DQ0 =123, DQ1 =119, DQ2 =107, DQ3 =119

 3512 23:06:22.348319  DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123

 3513 23:06:22.351486  DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115

 3514 23:06:22.355077  DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123

 3515 23:06:22.355155  

 3516 23:06:22.358588  

 3517 23:06:22.358697  ==

 3518 23:06:22.362180  Dram Type= 6, Freq= 0, CH_1, rank 1

 3519 23:06:22.365227  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3520 23:06:22.365332  ==

 3521 23:06:22.365443  

 3522 23:06:22.365531  

 3523 23:06:22.368813  	TX Vref Scan disable

 3524 23:06:22.368909   == TX Byte 0 ==

 3525 23:06:22.375154  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3526 23:06:22.378357  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3527 23:06:22.378443   == TX Byte 1 ==

 3528 23:06:22.384915  Update DQ  dly =846 (3 ,2, 14)  DQ  OEN =(2 ,7)

 3529 23:06:22.388443  Update DQM dly =846 (3 ,2, 14)  DQM OEN =(2 ,7)

 3530 23:06:22.388542  ==

 3531 23:06:22.391452  Dram Type= 6, Freq= 0, CH_1, rank 1

 3532 23:06:22.394728  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3533 23:06:22.394797  ==

 3534 23:06:22.407309  TX Vref=22, minBit 9, minWin=25, winSum=422

 3535 23:06:22.411006  TX Vref=24, minBit 9, minWin=25, winSum=422

 3536 23:06:22.414347  TX Vref=26, minBit 0, minWin=26, winSum=430

 3537 23:06:22.417448  TX Vref=28, minBit 8, minWin=26, winSum=431

 3538 23:06:22.420866  TX Vref=30, minBit 10, minWin=26, winSum=434

 3539 23:06:22.427441  TX Vref=32, minBit 9, minWin=26, winSum=434

 3540 23:06:22.430847  [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30

 3541 23:06:22.430921  

 3542 23:06:22.433832  Final TX Range 1 Vref 30

 3543 23:06:22.433928  

 3544 23:06:22.434015  ==

 3545 23:06:22.437351  Dram Type= 6, Freq= 0, CH_1, rank 1

 3546 23:06:22.440839  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3547 23:06:22.443825  ==

 3548 23:06:22.443905  

 3549 23:06:22.443968  

 3550 23:06:22.444026  	TX Vref Scan disable

 3551 23:06:22.447428   == TX Byte 0 ==

 3552 23:06:22.451102  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 3553 23:06:22.457395  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 3554 23:06:22.457475   == TX Byte 1 ==

 3555 23:06:22.460447  Update DQ  dly =847 (3 ,2, 15)  DQ  OEN =(2 ,7)

 3556 23:06:22.467338  Update DQM dly =847 (3 ,2, 15)  DQM OEN =(2 ,7)

 3557 23:06:22.467419  

 3558 23:06:22.467484  [DATLAT]

 3559 23:06:22.467542  Freq=1200, CH1 RK1

 3560 23:06:22.467600  

 3561 23:06:22.470780  DATLAT Default: 0xd

 3562 23:06:22.470853  0, 0xFFFF, sum = 0

 3563 23:06:22.473732  1, 0xFFFF, sum = 0

 3564 23:06:22.477199  2, 0xFFFF, sum = 0

 3565 23:06:22.477300  3, 0xFFFF, sum = 0

 3566 23:06:22.480186  4, 0xFFFF, sum = 0

 3567 23:06:22.480285  5, 0xFFFF, sum = 0

 3568 23:06:22.483797  6, 0xFFFF, sum = 0

 3569 23:06:22.483873  7, 0xFFFF, sum = 0

 3570 23:06:22.487439  8, 0xFFFF, sum = 0

 3571 23:06:22.487509  9, 0xFFFF, sum = 0

 3572 23:06:22.490232  10, 0xFFFF, sum = 0

 3573 23:06:22.490308  11, 0xFFFF, sum = 0

 3574 23:06:22.493930  12, 0x0, sum = 1

 3575 23:06:22.494004  13, 0x0, sum = 2

 3576 23:06:22.497079  14, 0x0, sum = 3

 3577 23:06:22.497181  15, 0x0, sum = 4

 3578 23:06:22.499985  best_step = 13

 3579 23:06:22.500080  

 3580 23:06:22.500170  ==

 3581 23:06:22.503382  Dram Type= 6, Freq= 0, CH_1, rank 1

 3582 23:06:22.506958  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3583 23:06:22.507030  ==

 3584 23:06:22.507090  RX Vref Scan: 0

 3585 23:06:22.510099  

 3586 23:06:22.510196  RX Vref 0 -> 0, step: 1

 3587 23:06:22.510282  

 3588 23:06:22.513220  RX Delay -5 -> 252, step: 4

 3589 23:06:22.519891  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3590 23:06:22.523406  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3591 23:06:22.526347  iDelay=195, Bit 2, Center 110 (51 ~ 170) 120

 3592 23:06:22.529983  iDelay=195, Bit 3, Center 118 (59 ~ 178) 120

 3593 23:06:22.532923  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3594 23:06:22.539914  iDelay=195, Bit 5, Center 132 (71 ~ 194) 124

 3595 23:06:22.542933  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3596 23:06:22.546588  iDelay=195, Bit 7, Center 120 (59 ~ 182) 124

 3597 23:06:22.549476  iDelay=195, Bit 8, Center 106 (47 ~ 166) 120

 3598 23:06:22.553139  iDelay=195, Bit 9, Center 108 (47 ~ 170) 124

 3599 23:06:22.559862  iDelay=195, Bit 10, Center 116 (55 ~ 178) 124

 3600 23:06:22.562680  iDelay=195, Bit 11, Center 112 (51 ~ 174) 124

 3601 23:06:22.566238  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3602 23:06:22.569326  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3603 23:06:22.572919  iDelay=195, Bit 14, Center 122 (63 ~ 182) 120

 3604 23:06:22.579648  iDelay=195, Bit 15, Center 128 (67 ~ 190) 124

 3605 23:06:22.579746  ==

 3606 23:06:22.582835  Dram Type= 6, Freq= 0, CH_1, rank 1

 3607 23:06:22.586286  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3608 23:06:22.586391  ==

 3609 23:06:22.586482  DQS Delay:

 3610 23:06:22.589415  DQS0 = 0, DQS1 = 0

 3611 23:06:22.589509  DQM Delay:

 3612 23:06:22.592667  DQM0 = 120, DQM1 = 117

 3613 23:06:22.592763  DQ Delay:

 3614 23:06:22.596256  DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118

 3615 23:06:22.599821  DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120

 3616 23:06:22.602841  DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112

 3617 23:06:22.605784  DQ12 =126, DQ13 =124, DQ14 =122, DQ15 =128

 3618 23:06:22.609171  

 3619 23:06:22.609277  

 3620 23:06:22.616308  [DQSOSCAuto] RK1, (LSB)MR18= 0x11ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps

 3621 23:06:22.619140  CH1 RK1: MR19=403, MR18=11EE

 3622 23:06:22.626264  CH1_RK1: MR19=0x403, MR18=0x11EE, DQSOSC=403, MR23=63, INC=40, DEC=26

 3623 23:06:22.629432  [RxdqsGatingPostProcess] freq 1200

 3624 23:06:22.632521  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3625 23:06:22.635961  best DQS0 dly(2T, 0.5T) = (0, 11)

 3626 23:06:22.639188  best DQS1 dly(2T, 0.5T) = (0, 11)

 3627 23:06:22.642618  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3628 23:06:22.646056  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3629 23:06:22.649192  best DQS0 dly(2T, 0.5T) = (0, 11)

 3630 23:06:22.652614  best DQS1 dly(2T, 0.5T) = (0, 11)

 3631 23:06:22.655999  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3632 23:06:22.659325  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3633 23:06:22.662829  Pre-setting of DQS Precalculation

 3634 23:06:22.665877  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3635 23:06:22.672950  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3636 23:06:22.682744  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3637 23:06:22.682827  

 3638 23:06:22.682892  

 3639 23:06:22.682952  [Calibration Summary] 2400 Mbps

 3640 23:06:22.685958  CH 0, Rank 0

 3641 23:06:22.686039  SW Impedance     : PASS

 3642 23:06:22.689449  DUTY Scan        : NO K

 3643 23:06:22.693040  ZQ Calibration   : PASS

 3644 23:06:22.693136  Jitter Meter     : NO K

 3645 23:06:22.696025  CBT Training     : PASS

 3646 23:06:22.699785  Write leveling   : PASS

 3647 23:06:22.699961  RX DQS gating    : PASS

 3648 23:06:22.702939  RX DQ/DQS(RDDQC) : PASS

 3649 23:06:22.705866  TX DQ/DQS        : PASS

 3650 23:06:22.706069  RX DATLAT        : PASS

 3651 23:06:22.709341  RX DQ/DQS(Engine): PASS

 3652 23:06:22.712724  TX OE            : NO K

 3653 23:06:22.712914  All Pass.

 3654 23:06:22.713040  

 3655 23:06:22.713147  CH 0, Rank 1

 3656 23:06:22.716234  SW Impedance     : PASS

 3657 23:06:22.719452  DUTY Scan        : NO K

 3658 23:06:22.719685  ZQ Calibration   : PASS

 3659 23:06:22.722763  Jitter Meter     : NO K

 3660 23:06:22.725804  CBT Training     : PASS

 3661 23:06:22.725979  Write leveling   : PASS

 3662 23:06:22.729728  RX DQS gating    : PASS

 3663 23:06:22.732801  RX DQ/DQS(RDDQC) : PASS

 3664 23:06:22.733125  TX DQ/DQS        : PASS

 3665 23:06:22.736384  RX DATLAT        : PASS

 3666 23:06:22.736755  RX DQ/DQS(Engine): PASS

 3667 23:06:22.739894  TX OE            : NO K

 3668 23:06:22.740305  All Pass.

 3669 23:06:22.740555  

 3670 23:06:22.742634  CH 1, Rank 0

 3671 23:06:22.743017  SW Impedance     : PASS

 3672 23:06:22.746082  DUTY Scan        : NO K

 3673 23:06:22.749260  ZQ Calibration   : PASS

 3674 23:06:22.749774  Jitter Meter     : NO K

 3675 23:06:22.752427  CBT Training     : PASS

 3676 23:06:22.755772  Write leveling   : PASS

 3677 23:06:22.756193  RX DQS gating    : PASS

 3678 23:06:22.759143  RX DQ/DQS(RDDQC) : PASS

 3679 23:06:22.762687  TX DQ/DQS        : PASS

 3680 23:06:22.763103  RX DATLAT        : PASS

 3681 23:06:22.766142  RX DQ/DQS(Engine): PASS

 3682 23:06:22.769336  TX OE            : NO K

 3683 23:06:22.769797  All Pass.

 3684 23:06:22.770142  

 3685 23:06:22.770579  CH 1, Rank 1

 3686 23:06:22.772502  SW Impedance     : PASS

 3687 23:06:22.775981  DUTY Scan        : NO K

 3688 23:06:22.776409  ZQ Calibration   : PASS

 3689 23:06:22.779344  Jitter Meter     : NO K

 3690 23:06:22.782566  CBT Training     : PASS

 3691 23:06:22.782984  Write leveling   : PASS

 3692 23:06:22.785692  RX DQS gating    : PASS

 3693 23:06:22.789352  RX DQ/DQS(RDDQC) : PASS

 3694 23:06:22.789820  TX DQ/DQS        : PASS

 3695 23:06:22.792345  RX DATLAT        : PASS

 3696 23:06:22.792762  RX DQ/DQS(Engine): PASS

 3697 23:06:22.795907  TX OE            : NO K

 3698 23:06:22.796351  All Pass.

 3699 23:06:22.796693  

 3700 23:06:22.799823  DramC Write-DBI off

 3701 23:06:22.802530  	PER_BANK_REFRESH: Hybrid Mode

 3702 23:06:22.802960  TX_TRACKING: ON

 3703 23:06:22.812708  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3704 23:06:22.815996  [FAST_K] Save calibration result to emmc

 3705 23:06:22.819387  dramc_set_vcore_voltage set vcore to 650000

 3706 23:06:22.822621  Read voltage for 600, 5

 3707 23:06:22.823085  Vio18 = 0

 3708 23:06:22.825771  Vcore = 650000

 3709 23:06:22.826257  Vdram = 0

 3710 23:06:22.826765  Vddq = 0

 3711 23:06:22.827227  Vmddr = 0

 3712 23:06:22.832742  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3713 23:06:22.836045  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3714 23:06:22.839389  MEM_TYPE=3, freq_sel=19

 3715 23:06:22.842224  sv_algorithm_assistance_LP4_1600 

 3716 23:06:22.845509  ============ PULL DRAM RESETB DOWN ============

 3717 23:06:22.851945  ========== PULL DRAM RESETB DOWN end =========

 3718 23:06:22.855389  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3719 23:06:22.858985  =================================== 

 3720 23:06:22.862027  LPDDR4 DRAM CONFIGURATION

 3721 23:06:22.865815  =================================== 

 3722 23:06:22.866263  EX_ROW_EN[0]    = 0x0

 3723 23:06:22.868832  EX_ROW_EN[1]    = 0x0

 3724 23:06:22.869289  LP4Y_EN      = 0x0

 3725 23:06:22.872473  WORK_FSP     = 0x0

 3726 23:06:22.872998  WL           = 0x2

 3727 23:06:22.875522  RL           = 0x2

 3728 23:06:22.875977  BL           = 0x2

 3729 23:06:22.878824  RPST         = 0x0

 3730 23:06:22.879301  RD_PRE       = 0x0

 3731 23:06:22.882221  WR_PRE       = 0x1

 3732 23:06:22.882765  WR_PST       = 0x0

 3733 23:06:22.885260  DBI_WR       = 0x0

 3734 23:06:22.888569  DBI_RD       = 0x0

 3735 23:06:22.889035  OTF          = 0x1

 3736 23:06:22.892015  =================================== 

 3737 23:06:22.895593  =================================== 

 3738 23:06:22.896030  ANA top config

 3739 23:06:22.898860  =================================== 

 3740 23:06:22.902061  DLL_ASYNC_EN            =  0

 3741 23:06:22.905396  ALL_SLAVE_EN            =  1

 3742 23:06:22.909041  NEW_RANK_MODE           =  1

 3743 23:06:22.912293  DLL_IDLE_MODE           =  1

 3744 23:06:22.912705  LP45_APHY_COMB_EN       =  1

 3745 23:06:22.915927  TX_ODT_DIS              =  1

 3746 23:06:22.919091  NEW_8X_MODE             =  1

 3747 23:06:22.922228  =================================== 

 3748 23:06:22.925301  =================================== 

 3749 23:06:22.928843  data_rate                  = 1200

 3750 23:06:22.932244  CKR                        = 1

 3751 23:06:22.932755  DQ_P2S_RATIO               = 8

 3752 23:06:22.935896  =================================== 

 3753 23:06:22.938582  CA_P2S_RATIO               = 8

 3754 23:06:22.942100  DQ_CA_OPEN                 = 0

 3755 23:06:22.945683  DQ_SEMI_OPEN               = 0

 3756 23:06:22.948641  CA_SEMI_OPEN               = 0

 3757 23:06:22.952177  CA_FULL_RATE               = 0

 3758 23:06:22.952600  DQ_CKDIV4_EN               = 1

 3759 23:06:22.955747  CA_CKDIV4_EN               = 1

 3760 23:06:22.958614  CA_PREDIV_EN               = 0

 3761 23:06:22.962102  PH8_DLY                    = 0

 3762 23:06:22.965642  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3763 23:06:22.968789  DQ_AAMCK_DIV               = 4

 3764 23:06:22.969302  CA_AAMCK_DIV               = 4

 3765 23:06:22.972386  CA_ADMCK_DIV               = 4

 3766 23:06:22.975224  DQ_TRACK_CA_EN             = 0

 3767 23:06:22.978714  CA_PICK                    = 600

 3768 23:06:22.981689  CA_MCKIO                   = 600

 3769 23:06:22.985132  MCKIO_SEMI                 = 0

 3770 23:06:22.989037  PLL_FREQ                   = 2288

 3771 23:06:22.989571  DQ_UI_PI_RATIO             = 32

 3772 23:06:22.992039  CA_UI_PI_RATIO             = 0

 3773 23:06:22.995737  =================================== 

 3774 23:06:22.998297  =================================== 

 3775 23:06:23.002101  memory_type:LPDDR4         

 3776 23:06:23.005249  GP_NUM     : 10       

 3777 23:06:23.005880  SRAM_EN    : 1       

 3778 23:06:23.008144  MD32_EN    : 0       

 3779 23:06:23.012119  =================================== 

 3780 23:06:23.014970  [ANA_INIT] >>>>>>>>>>>>>> 

 3781 23:06:23.015435  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3782 23:06:23.018499  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3783 23:06:23.021982  =================================== 

 3784 23:06:23.024683  data_rate = 1200,PCW = 0X5800

 3785 23:06:23.028375  =================================== 

 3786 23:06:23.031861  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3787 23:06:23.038223  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3788 23:06:23.044710  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3789 23:06:23.047834  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3790 23:06:23.051274  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3791 23:06:23.054895  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3792 23:06:23.057783  [ANA_INIT] flow start 

 3793 23:06:23.058264  [ANA_INIT] PLL >>>>>>>> 

 3794 23:06:23.061377  [ANA_INIT] PLL <<<<<<<< 

 3795 23:06:23.065297  [ANA_INIT] MIDPI >>>>>>>> 

 3796 23:06:23.065895  [ANA_INIT] MIDPI <<<<<<<< 

 3797 23:06:23.068279  [ANA_INIT] DLL >>>>>>>> 

 3798 23:06:23.071427  [ANA_INIT] flow end 

 3799 23:06:23.074311  ============ LP4 DIFF to SE enter ============

 3800 23:06:23.078072  ============ LP4 DIFF to SE exit  ============

 3801 23:06:23.080990  [ANA_INIT] <<<<<<<<<<<<< 

 3802 23:06:23.084895  [Flow] Enable top DCM control >>>>> 

 3803 23:06:23.087909  [Flow] Enable top DCM control <<<<< 

 3804 23:06:23.090897  Enable DLL master slave shuffle 

 3805 23:06:23.094727  ============================================================== 

 3806 23:06:23.097564  Gating Mode config

 3807 23:06:23.105067  ============================================================== 

 3808 23:06:23.105667  Config description: 

 3809 23:06:23.114166  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3810 23:06:23.121567  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3811 23:06:23.127950  SELPH_MODE            0: By rank         1: By Phase 

 3812 23:06:23.131102  ============================================================== 

 3813 23:06:23.134322  GAT_TRACK_EN                 =  1

 3814 23:06:23.137363  RX_GATING_MODE               =  2

 3815 23:06:23.141196  RX_GATING_TRACK_MODE         =  2

 3816 23:06:23.144466  SELPH_MODE                   =  1

 3817 23:06:23.147599  PICG_EARLY_EN                =  1

 3818 23:06:23.150717  VALID_LAT_VALUE              =  1

 3819 23:06:23.154607  ============================================================== 

 3820 23:06:23.157671  Enter into Gating configuration >>>> 

 3821 23:06:23.160792  Exit from Gating configuration <<<< 

 3822 23:06:23.164357  Enter into  DVFS_PRE_config >>>>> 

 3823 23:06:23.177409  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3824 23:06:23.180738  Exit from  DVFS_PRE_config <<<<< 

 3825 23:06:23.181165  Enter into PICG configuration >>>> 

 3826 23:06:23.184643  Exit from PICG configuration <<<< 

 3827 23:06:23.187163  [RX_INPUT] configuration >>>>> 

 3828 23:06:23.190860  [RX_INPUT] configuration <<<<< 

 3829 23:06:23.197411  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3830 23:06:23.200846  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3831 23:06:23.207341  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3832 23:06:23.213915  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3833 23:06:23.220736  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3834 23:06:23.227144  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3835 23:06:23.230531  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3836 23:06:23.234550  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3837 23:06:23.237491  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3838 23:06:23.243985  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3839 23:06:23.247256  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3840 23:06:23.250217  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3841 23:06:23.253839  =================================== 

 3842 23:06:23.257271  LPDDR4 DRAM CONFIGURATION

 3843 23:06:23.260770  =================================== 

 3844 23:06:23.264298  EX_ROW_EN[0]    = 0x0

 3845 23:06:23.264718  EX_ROW_EN[1]    = 0x0

 3846 23:06:23.267228  LP4Y_EN      = 0x0

 3847 23:06:23.267757  WORK_FSP     = 0x0

 3848 23:06:23.270307  WL           = 0x2

 3849 23:06:23.270791  RL           = 0x2

 3850 23:06:23.273685  BL           = 0x2

 3851 23:06:23.274106  RPST         = 0x0

 3852 23:06:23.277449  RD_PRE       = 0x0

 3853 23:06:23.278039  WR_PRE       = 0x1

 3854 23:06:23.280080  WR_PST       = 0x0

 3855 23:06:23.280500  DBI_WR       = 0x0

 3856 23:06:23.283968  DBI_RD       = 0x0

 3857 23:06:23.284384  OTF          = 0x1

 3858 23:06:23.287424  =================================== 

 3859 23:06:23.293859  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3860 23:06:23.297265  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3861 23:06:23.300659  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3862 23:06:23.304075  =================================== 

 3863 23:06:23.307013  LPDDR4 DRAM CONFIGURATION

 3864 23:06:23.310741  =================================== 

 3865 23:06:23.311306  EX_ROW_EN[0]    = 0x10

 3866 23:06:23.313522  EX_ROW_EN[1]    = 0x0

 3867 23:06:23.317280  LP4Y_EN      = 0x0

 3868 23:06:23.317897  WORK_FSP     = 0x0

 3869 23:06:23.320748  WL           = 0x2

 3870 23:06:23.321309  RL           = 0x2

 3871 23:06:23.323804  BL           = 0x2

 3872 23:06:23.324385  RPST         = 0x0

 3873 23:06:23.327217  RD_PRE       = 0x0

 3874 23:06:23.327844  WR_PRE       = 0x1

 3875 23:06:23.330099  WR_PST       = 0x0

 3876 23:06:23.330560  DBI_WR       = 0x0

 3877 23:06:23.333555  DBI_RD       = 0x0

 3878 23:06:23.334158  OTF          = 0x1

 3879 23:06:23.337018  =================================== 

 3880 23:06:23.343656  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3881 23:06:23.347620  nWR fixed to 30

 3882 23:06:23.351244  [ModeRegInit_LP4] CH0 RK0

 3883 23:06:23.351710  [ModeRegInit_LP4] CH0 RK1

 3884 23:06:23.354367  [ModeRegInit_LP4] CH1 RK0

 3885 23:06:23.357824  [ModeRegInit_LP4] CH1 RK1

 3886 23:06:23.358337  match AC timing 17

 3887 23:06:23.364507  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3888 23:06:23.367842  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3889 23:06:23.371205  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3890 23:06:23.378084  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3891 23:06:23.380921  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3892 23:06:23.381494  ==

 3893 23:06:23.384158  Dram Type= 6, Freq= 0, CH_0, rank 0

 3894 23:06:23.387716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3895 23:06:23.388288  ==

 3896 23:06:23.394561  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3897 23:06:23.400895  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3898 23:06:23.404270  [CA 0] Center 35 (5~66) winsize 62

 3899 23:06:23.407461  [CA 1] Center 35 (5~66) winsize 62

 3900 23:06:23.410499  [CA 2] Center 33 (3~64) winsize 62

 3901 23:06:23.414258  [CA 3] Center 33 (2~64) winsize 63

 3902 23:06:23.417650  [CA 4] Center 33 (2~64) winsize 63

 3903 23:06:23.421001  [CA 5] Center 32 (2~63) winsize 62

 3904 23:06:23.421564  

 3905 23:06:23.424407  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3906 23:06:23.424973  

 3907 23:06:23.427093  [CATrainingPosCal] consider 1 rank data

 3908 23:06:23.430832  u2DelayCellTimex100 = 270/100 ps

 3909 23:06:23.434509  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3910 23:06:23.437251  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3911 23:06:23.440988  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3912 23:06:23.443884  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3913 23:06:23.447294  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3914 23:06:23.453646  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3915 23:06:23.454119  

 3916 23:06:23.457251  CA PerBit enable=1, Macro0, CA PI delay=32

 3917 23:06:23.457848  

 3918 23:06:23.460887  [CBTSetCACLKResult] CA Dly = 32

 3919 23:06:23.461441  CS Dly: 4 (0~35)

 3920 23:06:23.461872  ==

 3921 23:06:23.463919  Dram Type= 6, Freq= 0, CH_0, rank 1

 3922 23:06:23.467301  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3923 23:06:23.470620  ==

 3924 23:06:23.473468  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3925 23:06:23.480066  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3926 23:06:23.483606  [CA 0] Center 35 (5~66) winsize 62

 3927 23:06:23.486894  [CA 1] Center 35 (5~66) winsize 62

 3928 23:06:23.490465  [CA 2] Center 33 (3~64) winsize 62

 3929 23:06:23.494088  [CA 3] Center 33 (2~64) winsize 63

 3930 23:06:23.496603  [CA 4] Center 33 (2~64) winsize 63

 3931 23:06:23.500815  [CA 5] Center 32 (2~63) winsize 62

 3932 23:06:23.501327  

 3933 23:06:23.503365  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3934 23:06:23.503779  

 3935 23:06:23.506648  [CATrainingPosCal] consider 2 rank data

 3936 23:06:23.510573  u2DelayCellTimex100 = 270/100 ps

 3937 23:06:23.513272  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3938 23:06:23.517060  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3939 23:06:23.520310  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3940 23:06:23.526686  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3941 23:06:23.530338  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3942 23:06:23.533628  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3943 23:06:23.534197  

 3944 23:06:23.536835  CA PerBit enable=1, Macro0, CA PI delay=32

 3945 23:06:23.537251  

 3946 23:06:23.540361  [CBTSetCACLKResult] CA Dly = 32

 3947 23:06:23.540827  CS Dly: 4 (0~36)

 3948 23:06:23.541161  

 3949 23:06:23.543356  ----->DramcWriteLeveling(PI) begin...

 3950 23:06:23.543777  ==

 3951 23:06:23.546998  Dram Type= 6, Freq= 0, CH_0, rank 0

 3952 23:06:23.553343  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3953 23:06:23.553796  ==

 3954 23:06:23.557185  Write leveling (Byte 0): 35 => 35

 3955 23:06:23.559846  Write leveling (Byte 1): 31 => 31

 3956 23:06:23.560268  DramcWriteLeveling(PI) end<-----

 3957 23:06:23.563816  

 3958 23:06:23.564338  ==

 3959 23:06:23.566428  Dram Type= 6, Freq= 0, CH_0, rank 0

 3960 23:06:23.569865  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3961 23:06:23.570283  ==

 3962 23:06:23.573117  [Gating] SW mode calibration

 3963 23:06:23.580028  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3964 23:06:23.583176  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3965 23:06:23.589832   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3966 23:06:23.593529   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3967 23:06:23.596431   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3968 23:06:23.603565   0  9 12 | B1->B0 | 3434 2828 | 1 1 | (1 1) (1 1)

 3969 23:06:23.606263   0  9 16 | B1->B0 | 3030 2323 | 0 0 | (0 0) (0 0)

 3970 23:06:23.609653   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3971 23:06:23.616361   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3972 23:06:23.619442   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3973 23:06:23.623374   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3974 23:06:23.629472   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3975 23:06:23.633016   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 3976 23:06:23.636294   0 10 12 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)

 3977 23:06:23.643123   0 10 16 | B1->B0 | 3434 4646 | 0 0 | (0 0) (0 0)

 3978 23:06:23.646305   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3979 23:06:23.649441   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3980 23:06:23.656096   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3981 23:06:23.659369   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3982 23:06:23.662754   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3983 23:06:23.669813   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3984 23:06:23.672911   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3985 23:06:23.676336   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3986 23:06:23.682771   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3987 23:06:23.686139   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3988 23:06:23.689918   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3989 23:06:23.696434   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3990 23:06:23.699026   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3991 23:06:23.702813   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3992 23:06:23.709242   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3993 23:06:23.712397   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3994 23:06:23.716093   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3995 23:06:23.722224   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3996 23:06:23.725761   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3997 23:06:23.729101   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3998 23:06:23.732403   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3999 23:06:23.738941   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4000 23:06:23.742263   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4001 23:06:23.746129  Total UI for P1: 0, mck2ui 16

 4002 23:06:23.749241  best dqsien dly found for B0: ( 0, 13, 10)

 4003 23:06:23.752538   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4004 23:06:23.755553  Total UI for P1: 0, mck2ui 16

 4005 23:06:23.759030  best dqsien dly found for B1: ( 0, 13, 14)

 4006 23:06:23.761955  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4007 23:06:23.769023  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4008 23:06:23.769572  

 4009 23:06:23.772498  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4010 23:06:23.775572  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4011 23:06:23.778927  [Gating] SW calibration Done

 4012 23:06:23.779386  ==

 4013 23:06:23.782041  Dram Type= 6, Freq= 0, CH_0, rank 0

 4014 23:06:23.785421  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4015 23:06:23.786048  ==

 4016 23:06:23.786437  RX Vref Scan: 0

 4017 23:06:23.788986  

 4018 23:06:23.789533  RX Vref 0 -> 0, step: 1

 4019 23:06:23.789944  

 4020 23:06:23.792076  RX Delay -230 -> 252, step: 16

 4021 23:06:23.795340  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4022 23:06:23.802593  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4023 23:06:23.805443  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4024 23:06:23.808910  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4025 23:06:23.811964  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4026 23:06:23.815621  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4027 23:06:23.822056  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4028 23:06:23.825368  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4029 23:06:23.828371  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4030 23:06:23.831856  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4031 23:06:23.838498  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4032 23:06:23.841927  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4033 23:06:23.844979  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4034 23:06:23.848503  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4035 23:06:23.855059  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4036 23:06:23.858655  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4037 23:06:23.859091  ==

 4038 23:06:23.861965  Dram Type= 6, Freq= 0, CH_0, rank 0

 4039 23:06:23.865314  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4040 23:06:23.865876  ==

 4041 23:06:23.868507  DQS Delay:

 4042 23:06:23.869031  DQS0 = 0, DQS1 = 0

 4043 23:06:23.869373  DQM Delay:

 4044 23:06:23.871767  DQM0 = 52, DQM1 = 46

 4045 23:06:23.872186  DQ Delay:

 4046 23:06:23.875084  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49

 4047 23:06:23.878436  DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57

 4048 23:06:23.881717  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4049 23:06:23.885338  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57

 4050 23:06:23.885810  

 4051 23:06:23.886145  

 4052 23:06:23.886452  ==

 4053 23:06:23.888308  Dram Type= 6, Freq= 0, CH_0, rank 0

 4054 23:06:23.894615  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4055 23:06:23.895126  ==

 4056 23:06:23.895458  

 4057 23:06:23.895769  

 4058 23:06:23.896062  	TX Vref Scan disable

 4059 23:06:23.898613   == TX Byte 0 ==

 4060 23:06:23.901784  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 4061 23:06:23.908701  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 4062 23:06:23.909262   == TX Byte 1 ==

 4063 23:06:23.911484  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4064 23:06:23.918597  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4065 23:06:23.919020  ==

 4066 23:06:23.921567  Dram Type= 6, Freq= 0, CH_0, rank 0

 4067 23:06:23.924700  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4068 23:06:23.925123  ==

 4069 23:06:23.925454  

 4070 23:06:23.925805  

 4071 23:06:23.928122  	TX Vref Scan disable

 4072 23:06:23.931640   == TX Byte 0 ==

 4073 23:06:23.935069  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4074 23:06:23.938355  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4075 23:06:23.941322   == TX Byte 1 ==

 4076 23:06:23.944742  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4077 23:06:23.952707  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4078 23:06:23.953307  

 4079 23:06:23.953704  [DATLAT]

 4080 23:06:23.954026  Freq=600, CH0 RK0

 4081 23:06:23.954351  

 4082 23:06:23.954990  DATLAT Default: 0x9

 4083 23:06:23.955313  0, 0xFFFF, sum = 0

 4084 23:06:23.958229  1, 0xFFFF, sum = 0

 4085 23:06:23.958654  2, 0xFFFF, sum = 0

 4086 23:06:23.961126  3, 0xFFFF, sum = 0

 4087 23:06:23.961551  4, 0xFFFF, sum = 0

 4088 23:06:23.964794  5, 0xFFFF, sum = 0

 4089 23:06:23.965294  6, 0xFFFF, sum = 0

 4090 23:06:23.968145  7, 0xFFFF, sum = 0

 4091 23:06:23.968664  8, 0x0, sum = 1

 4092 23:06:23.971141  9, 0x0, sum = 2

 4093 23:06:23.971570  10, 0x0, sum = 3

 4094 23:06:23.971909  11, 0x0, sum = 4

 4095 23:06:23.974632  best_step = 9

 4096 23:06:23.975076  

 4097 23:06:23.975416  ==

 4098 23:06:23.977780  Dram Type= 6, Freq= 0, CH_0, rank 0

 4099 23:06:23.981137  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4100 23:06:23.981746  ==

 4101 23:06:23.984395  RX Vref Scan: 1

 4102 23:06:23.984811  

 4103 23:06:23.985144  RX Vref 0 -> 0, step: 1

 4104 23:06:23.987546  

 4105 23:06:23.987963  RX Delay -163 -> 252, step: 8

 4106 23:06:23.988294  

 4107 23:06:23.991743  Set Vref, RX VrefLevel [Byte0]: 53

 4108 23:06:23.994195                           [Byte1]: 46

 4109 23:06:23.998577  

 4110 23:06:23.999008  Final RX Vref Byte 0 = 53 to rank0

 4111 23:06:24.002097  Final RX Vref Byte 1 = 46 to rank0

 4112 23:06:24.005717  Final RX Vref Byte 0 = 53 to rank1

 4113 23:06:24.009062  Final RX Vref Byte 1 = 46 to rank1==

 4114 23:06:24.012213  Dram Type= 6, Freq= 0, CH_0, rank 0

 4115 23:06:24.018782  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4116 23:06:24.019207  ==

 4117 23:06:24.019541  DQS Delay:

 4118 23:06:24.019850  DQS0 = 0, DQS1 = 0

 4119 23:06:24.021871  DQM Delay:

 4120 23:06:24.022290  DQM0 = 52, DQM1 = 45

 4121 23:06:24.025461  DQ Delay:

 4122 23:06:24.029113  DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48

 4123 23:06:24.032104  DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56

 4124 23:06:24.035376  DQ8 =36, DQ9 =32, DQ10 =48, DQ11 =40

 4125 23:06:24.038492  DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52

 4126 23:06:24.038973  

 4127 23:06:24.039309  

 4128 23:06:24.045186  [DQSOSCAuto] RK0, (LSB)MR18= 0x6b5e, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 389 ps

 4129 23:06:24.048683  CH0 RK0: MR19=808, MR18=6B5E

 4130 23:06:24.055362  CH0_RK0: MR19=0x808, MR18=0x6B5E, DQSOSC=389, MR23=63, INC=173, DEC=115

 4131 23:06:24.055789  

 4132 23:06:24.058501  ----->DramcWriteLeveling(PI) begin...

 4133 23:06:24.058927  ==

 4134 23:06:24.061781  Dram Type= 6, Freq= 0, CH_0, rank 1

 4135 23:06:24.065440  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4136 23:06:24.065997  ==

 4137 23:06:24.068915  Write leveling (Byte 0): 33 => 33

 4138 23:06:24.072139  Write leveling (Byte 1): 33 => 33

 4139 23:06:24.075768  DramcWriteLeveling(PI) end<-----

 4140 23:06:24.076294  

 4141 23:06:24.076629  ==

 4142 23:06:24.078467  Dram Type= 6, Freq= 0, CH_0, rank 1

 4143 23:06:24.082123  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4144 23:06:24.082542  ==

 4145 23:06:24.085077  [Gating] SW mode calibration

 4146 23:06:24.092088  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4147 23:06:24.098317  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4148 23:06:24.101789   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4149 23:06:24.105481   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4150 23:06:24.111916   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4151 23:06:24.115330   0  9 12 | B1->B0 | 3434 3434 | 0 1 | (0 1) (0 1)

 4152 23:06:24.118819   0  9 16 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 0)

 4153 23:06:24.125366   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4154 23:06:24.128152   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4155 23:06:24.131706   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4156 23:06:24.138341   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4157 23:06:24.141705   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4158 23:06:24.145375   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4159 23:06:24.151863   0 10 12 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)

 4160 23:06:24.155087   0 10 16 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (0 0)

 4161 23:06:24.158503   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4162 23:06:24.164912   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4163 23:06:24.168574   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4164 23:06:24.171298   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4165 23:06:24.178486   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4166 23:06:24.181140   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4167 23:06:24.184994   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4168 23:06:24.191754   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 4169 23:06:24.195037   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4170 23:06:24.198053   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4171 23:06:24.204849   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4172 23:06:24.207904   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4173 23:06:24.211749   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4174 23:06:24.217688   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4175 23:06:24.221079   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4176 23:06:24.224322   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4177 23:06:24.231145   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4178 23:06:24.234627   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4179 23:06:24.237882   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4180 23:06:24.244528   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4181 23:06:24.247922   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4182 23:06:24.251483   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 4183 23:06:24.258184   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4184 23:06:24.258607  Total UI for P1: 0, mck2ui 16

 4185 23:06:24.261114  best dqsien dly found for B0: ( 0, 13,  8)

 4186 23:06:24.267693   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4187 23:06:24.271014  Total UI for P1: 0, mck2ui 16

 4188 23:06:24.274399  best dqsien dly found for B1: ( 0, 13, 12)

 4189 23:06:24.277893  best DQS0 dly(MCK, UI, PI) = (0, 13, 8)

 4190 23:06:24.281217  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4191 23:06:24.281956  

 4192 23:06:24.284881  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)

 4193 23:06:24.287650  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4194 23:06:24.291007  [Gating] SW calibration Done

 4195 23:06:24.291426  ==

 4196 23:06:24.295056  Dram Type= 6, Freq= 0, CH_0, rank 1

 4197 23:06:24.297532  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4198 23:06:24.297996  ==

 4199 23:06:24.301425  RX Vref Scan: 0

 4200 23:06:24.301982  

 4201 23:06:24.304334  RX Vref 0 -> 0, step: 1

 4202 23:06:24.304752  

 4203 23:06:24.305082  RX Delay -230 -> 252, step: 16

 4204 23:06:24.310778  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4205 23:06:24.314221  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4206 23:06:24.317545  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4207 23:06:24.320894  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4208 23:06:24.327385  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4209 23:06:24.330805  iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320

 4210 23:06:24.334165  iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304

 4211 23:06:24.337808  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4212 23:06:24.341114  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4213 23:06:24.347287  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4214 23:06:24.350768  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4215 23:06:24.354134  iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304

 4216 23:06:24.357704  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4217 23:06:24.363810  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4218 23:06:24.367882  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4219 23:06:24.370562  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4220 23:06:24.370991  ==

 4221 23:06:24.374155  Dram Type= 6, Freq= 0, CH_0, rank 1

 4222 23:06:24.377506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4223 23:06:24.380472  ==

 4224 23:06:24.380887  DQS Delay:

 4225 23:06:24.381217  DQS0 = 0, DQS1 = 0

 4226 23:06:24.383897  DQM Delay:

 4227 23:06:24.384311  DQM0 = 50, DQM1 = 43

 4228 23:06:24.387284  DQ Delay:

 4229 23:06:24.387701  DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49

 4230 23:06:24.390587  DQ4 =57, DQ5 =41, DQ6 =49, DQ7 =57

 4231 23:06:24.393729  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33

 4232 23:06:24.397335  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4233 23:06:24.397797  

 4234 23:06:24.400252  

 4235 23:06:24.400661  ==

 4236 23:06:24.403899  Dram Type= 6, Freq= 0, CH_0, rank 1

 4237 23:06:24.406936  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4238 23:06:24.407357  ==

 4239 23:06:24.407691  

 4240 23:06:24.407995  

 4241 23:06:24.410549  	TX Vref Scan disable

 4242 23:06:24.411046   == TX Byte 0 ==

 4243 23:06:24.417229  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4244 23:06:24.420228  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4245 23:06:24.420643   == TX Byte 1 ==

 4246 23:06:24.427099  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4247 23:06:24.430251  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4248 23:06:24.430670  ==

 4249 23:06:24.433887  Dram Type= 6, Freq= 0, CH_0, rank 1

 4250 23:06:24.437252  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4251 23:06:24.437789  ==

 4252 23:06:24.438126  

 4253 23:06:24.438432  

 4254 23:06:24.440110  	TX Vref Scan disable

 4255 23:06:24.443640   == TX Byte 0 ==

 4256 23:06:24.446849  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 4257 23:06:24.450257  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 4258 23:06:24.453745   == TX Byte 1 ==

 4259 23:06:24.456542  Update DQ  dly =577 (2 ,1, 33)  DQ  OEN =(1 ,6)

 4260 23:06:24.460651  Update DQM dly =577 (2 ,1, 33)  DQM OEN =(1 ,6)

 4261 23:06:24.461168  

 4262 23:06:24.463686  [DATLAT]

 4263 23:06:24.464098  Freq=600, CH0 RK1

 4264 23:06:24.464425  

 4265 23:06:24.466670  DATLAT Default: 0x9

 4266 23:06:24.467086  0, 0xFFFF, sum = 0

 4267 23:06:24.470262  1, 0xFFFF, sum = 0

 4268 23:06:24.470679  2, 0xFFFF, sum = 0

 4269 23:06:24.473250  3, 0xFFFF, sum = 0

 4270 23:06:24.473701  4, 0xFFFF, sum = 0

 4271 23:06:24.476689  5, 0xFFFF, sum = 0

 4272 23:06:24.477108  6, 0xFFFF, sum = 0

 4273 23:06:24.480400  7, 0xFFFF, sum = 0

 4274 23:06:24.480815  8, 0x0, sum = 1

 4275 23:06:24.483438  9, 0x0, sum = 2

 4276 23:06:24.483923  10, 0x0, sum = 3

 4277 23:06:24.486500  11, 0x0, sum = 4

 4278 23:06:24.486914  best_step = 9

 4279 23:06:24.487237  

 4280 23:06:24.487536  ==

 4281 23:06:24.490093  Dram Type= 6, Freq= 0, CH_0, rank 1

 4282 23:06:24.496922  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4283 23:06:24.497435  ==

 4284 23:06:24.497824  RX Vref Scan: 0

 4285 23:06:24.498136  

 4286 23:06:24.499966  RX Vref 0 -> 0, step: 1

 4287 23:06:24.500377  

 4288 23:06:24.503692  RX Delay -163 -> 252, step: 8

 4289 23:06:24.506681  iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288

 4290 23:06:24.509714  iDelay=197, Bit 1, Center 56 (-83 ~ 196) 280

 4291 23:06:24.516175  iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288

 4292 23:06:24.519726  iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288

 4293 23:06:24.523439  iDelay=197, Bit 4, Center 56 (-83 ~ 196) 280

 4294 23:06:24.526478  iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288

 4295 23:06:24.530170  iDelay=197, Bit 6, Center 60 (-75 ~ 196) 272

 4296 23:06:24.536584  iDelay=197, Bit 7, Center 60 (-75 ~ 196) 272

 4297 23:06:24.539812  iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288

 4298 23:06:24.543093  iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288

 4299 23:06:24.546671  iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280

 4300 23:06:24.549541  iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280

 4301 23:06:24.556405  iDelay=197, Bit 12, Center 48 (-91 ~ 188) 280

 4302 23:06:24.559929  iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288

 4303 23:06:24.563440  iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280

 4304 23:06:24.566342  iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288

 4305 23:06:24.566756  ==

 4306 23:06:24.569897  Dram Type= 6, Freq= 0, CH_0, rank 1

 4307 23:06:24.576635  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4308 23:06:24.577049  ==

 4309 23:06:24.577391  DQS Delay:

 4310 23:06:24.579759  DQS0 = 0, DQS1 = 0

 4311 23:06:24.580167  DQM Delay:

 4312 23:06:24.580493  DQM0 = 54, DQM1 = 46

 4313 23:06:24.583224  DQ Delay:

 4314 23:06:24.586201  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4315 23:06:24.589910  DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60

 4316 23:06:24.593090  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40

 4317 23:06:24.596008  DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52

 4318 23:06:24.596418  

 4319 23:06:24.596742  

 4320 23:06:24.603120  [DQSOSCAuto] RK1, (LSB)MR18= 0x6020, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps

 4321 23:06:24.606435  CH0 RK1: MR19=808, MR18=6020

 4322 23:06:24.612883  CH0_RK1: MR19=0x808, MR18=0x6020, DQSOSC=391, MR23=63, INC=171, DEC=114

 4323 23:06:24.616435  [RxdqsGatingPostProcess] freq 600

 4324 23:06:24.619560  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4325 23:06:24.622874  Pre-setting of DQS Precalculation

 4326 23:06:24.629267  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4327 23:06:24.629861  ==

 4328 23:06:24.633016  Dram Type= 6, Freq= 0, CH_1, rank 0

 4329 23:06:24.635897  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4330 23:06:24.636419  ==

 4331 23:06:24.642320  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4332 23:06:24.649562  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 4333 23:06:24.652400  [CA 0] Center 35 (5~66) winsize 62

 4334 23:06:24.655840  [CA 1] Center 35 (5~66) winsize 62

 4335 23:06:24.659148  [CA 2] Center 34 (4~65) winsize 62

 4336 23:06:24.662518  [CA 3] Center 34 (4~65) winsize 62

 4337 23:06:24.665889  [CA 4] Center 34 (4~65) winsize 62

 4338 23:06:24.669244  [CA 5] Center 33 (3~64) winsize 62

 4339 23:06:24.669861  

 4340 23:06:24.672081  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 4341 23:06:24.672651  

 4342 23:06:24.675771  [CATrainingPosCal] consider 1 rank data

 4343 23:06:24.678790  u2DelayCellTimex100 = 270/100 ps

 4344 23:06:24.682159  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4345 23:06:24.685663  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4346 23:06:24.688745  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4347 23:06:24.692219  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 4348 23:06:24.695718  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4349 23:06:24.699440  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4350 23:06:24.699865  

 4351 23:06:24.705901  CA PerBit enable=1, Macro0, CA PI delay=33

 4352 23:06:24.706314  

 4353 23:06:24.706642  [CBTSetCACLKResult] CA Dly = 33

 4354 23:06:24.708952  CS Dly: 6 (0~37)

 4355 23:06:24.709365  ==

 4356 23:06:24.712426  Dram Type= 6, Freq= 0, CH_1, rank 1

 4357 23:06:24.715644  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4358 23:06:24.716205  ==

 4359 23:06:24.722008  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4360 23:06:24.729155  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4361 23:06:24.732231  [CA 0] Center 36 (5~67) winsize 63

 4362 23:06:24.735817  [CA 1] Center 36 (5~67) winsize 63

 4363 23:06:24.738671  [CA 2] Center 34 (4~65) winsize 62

 4364 23:06:24.742213  [CA 3] Center 34 (4~65) winsize 62

 4365 23:06:24.745931  [CA 4] Center 34 (4~65) winsize 62

 4366 23:06:24.748826  [CA 5] Center 34 (3~65) winsize 63

 4367 23:06:24.749255  

 4368 23:06:24.752432  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4369 23:06:24.752843  

 4370 23:06:24.755292  [CATrainingPosCal] consider 2 rank data

 4371 23:06:24.758523  u2DelayCellTimex100 = 270/100 ps

 4372 23:06:24.761961  CA0 delay=35 (5~66),Diff = 2 PI (19 cell)

 4373 23:06:24.765496  CA1 delay=35 (5~66),Diff = 2 PI (19 cell)

 4374 23:06:24.768509  CA2 delay=34 (4~65),Diff = 1 PI (9 cell)

 4375 23:06:24.772092  CA3 delay=34 (4~65),Diff = 1 PI (9 cell)

 4376 23:06:24.775503  CA4 delay=34 (4~65),Diff = 1 PI (9 cell)

 4377 23:06:24.778646  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 4378 23:06:24.782030  

 4379 23:06:24.785675  CA PerBit enable=1, Macro0, CA PI delay=33

 4380 23:06:24.786090  

 4381 23:06:24.788538  [CBTSetCACLKResult] CA Dly = 33

 4382 23:06:24.788972  CS Dly: 7 (0~39)

 4383 23:06:24.789298  

 4384 23:06:24.792129  ----->DramcWriteLeveling(PI) begin...

 4385 23:06:24.792548  ==

 4386 23:06:24.795211  Dram Type= 6, Freq= 0, CH_1, rank 0

 4387 23:06:24.798870  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4388 23:06:24.801899  ==

 4389 23:06:24.802309  Write leveling (Byte 0): 29 => 29

 4390 23:06:24.805357  Write leveling (Byte 1): 30 => 30

 4391 23:06:24.808868  DramcWriteLeveling(PI) end<-----

 4392 23:06:24.809275  

 4393 23:06:24.809643  ==

 4394 23:06:24.812089  Dram Type= 6, Freq= 0, CH_1, rank 0

 4395 23:06:24.818862  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4396 23:06:24.819278  ==

 4397 23:06:24.819605  [Gating] SW mode calibration

 4398 23:06:24.828414  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4399 23:06:24.831924  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4400 23:06:24.835026   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4401 23:06:24.841728   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4402 23:06:24.845404   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 4403 23:06:24.848281   0  9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)

 4404 23:06:24.854894   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4405 23:06:24.858391   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4406 23:06:24.861406   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4407 23:06:24.868168   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4408 23:06:24.871408   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4409 23:06:24.874864   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4410 23:06:24.881514   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4411 23:06:24.884772   0 10 12 | B1->B0 | 3a3a 3737 | 0 0 | (0 0) (1 1)

 4412 23:06:24.887979   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4413 23:06:24.894728   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4414 23:06:24.898414   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4415 23:06:24.901693   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4416 23:06:24.908051   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4417 23:06:24.911382   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4418 23:06:24.914401   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4419 23:06:24.921636   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4420 23:06:24.924900   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4421 23:06:24.927901   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4422 23:06:24.934577   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4423 23:06:24.938071   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4424 23:06:24.941449   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4425 23:06:24.948056   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4426 23:06:24.951050   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4427 23:06:24.954554   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4428 23:06:24.961258   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4429 23:06:24.964351   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4430 23:06:24.967689   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4431 23:06:24.974678   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4432 23:06:24.977660   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4433 23:06:24.981329   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4434 23:06:24.988081   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4435 23:06:24.991494   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 4436 23:06:24.994396   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4437 23:06:24.998443  Total UI for P1: 0, mck2ui 16

 4438 23:06:25.001805  best dqsien dly found for B0: ( 0, 13, 10)

 4439 23:06:25.004581  Total UI for P1: 0, mck2ui 16

 4440 23:06:25.007891  best dqsien dly found for B1: ( 0, 13, 10)

 4441 23:06:25.011791  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4442 23:06:25.014484  best DQS1 dly(MCK, UI, PI) = (0, 13, 10)

 4443 23:06:25.014904  

 4444 23:06:25.018153  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4445 23:06:25.021100  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4446 23:06:25.024587  [Gating] SW calibration Done

 4447 23:06:25.025003  ==

 4448 23:06:25.027917  Dram Type= 6, Freq= 0, CH_1, rank 0

 4449 23:06:25.034740  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4450 23:06:25.035193  ==

 4451 23:06:25.035530  RX Vref Scan: 0

 4452 23:06:25.036035  

 4453 23:06:25.037773  RX Vref 0 -> 0, step: 1

 4454 23:06:25.038190  

 4455 23:06:25.041310  RX Delay -230 -> 252, step: 16

 4456 23:06:25.044285  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4457 23:06:25.048193  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4458 23:06:25.051211  iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320

 4459 23:06:25.057619  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4460 23:06:25.060677  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4461 23:06:25.064410  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4462 23:06:25.067912  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4463 23:06:25.074298  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4464 23:06:25.077717  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4465 23:06:25.080969  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4466 23:06:25.084180  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4467 23:06:25.087899  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4468 23:06:25.094132  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4469 23:06:25.097894  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4470 23:06:25.101021  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4471 23:06:25.104246  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4472 23:06:25.108022  ==

 4473 23:06:25.110604  Dram Type= 6, Freq= 0, CH_1, rank 0

 4474 23:06:25.113862  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4475 23:06:25.114281  ==

 4476 23:06:25.114612  DQS Delay:

 4477 23:06:25.117489  DQS0 = 0, DQS1 = 0

 4478 23:06:25.118063  DQM Delay:

 4479 23:06:25.120904  DQM0 = 47, DQM1 = 46

 4480 23:06:25.121407  DQ Delay:

 4481 23:06:25.124306  DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =41

 4482 23:06:25.127470  DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41

 4483 23:06:25.130548  DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41

 4484 23:06:25.134200  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4485 23:06:25.134707  

 4486 23:06:25.135038  

 4487 23:06:25.135376  ==

 4488 23:06:25.137483  Dram Type= 6, Freq= 0, CH_1, rank 0

 4489 23:06:25.140829  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4490 23:06:25.141256  ==

 4491 23:06:25.141626  

 4492 23:06:25.141946  

 4493 23:06:25.144414  	TX Vref Scan disable

 4494 23:06:25.147366   == TX Byte 0 ==

 4495 23:06:25.150934  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4496 23:06:25.153775  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4497 23:06:25.157572   == TX Byte 1 ==

 4498 23:06:25.160653  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4499 23:06:25.164269  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4500 23:06:25.164790  ==

 4501 23:06:25.166976  Dram Type= 6, Freq= 0, CH_1, rank 0

 4502 23:06:25.170509  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4503 23:06:25.173666  ==

 4504 23:06:25.174082  

 4505 23:06:25.174414  

 4506 23:06:25.174719  	TX Vref Scan disable

 4507 23:06:25.178054   == TX Byte 0 ==

 4508 23:06:25.181467  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4509 23:06:25.187684  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4510 23:06:25.188102   == TX Byte 1 ==

 4511 23:06:25.191277  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4512 23:06:25.197959  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4513 23:06:25.198469  

 4514 23:06:25.198821  [DATLAT]

 4515 23:06:25.199130  Freq=600, CH1 RK0

 4516 23:06:25.199430  

 4517 23:06:25.200958  DATLAT Default: 0x9

 4518 23:06:25.201371  0, 0xFFFF, sum = 0

 4519 23:06:25.204499  1, 0xFFFF, sum = 0

 4520 23:06:25.204962  2, 0xFFFF, sum = 0

 4521 23:06:25.208308  3, 0xFFFF, sum = 0

 4522 23:06:25.208866  4, 0xFFFF, sum = 0

 4523 23:06:25.211141  5, 0xFFFF, sum = 0

 4524 23:06:25.214703  6, 0xFFFF, sum = 0

 4525 23:06:25.215139  7, 0xFFFF, sum = 0

 4526 23:06:25.215507  8, 0x0, sum = 1

 4527 23:06:25.217623  9, 0x0, sum = 2

 4528 23:06:25.218074  10, 0x0, sum = 3

 4529 23:06:25.221181  11, 0x0, sum = 4

 4530 23:06:25.221657  best_step = 9

 4531 23:06:25.222016  

 4532 23:06:25.222325  ==

 4533 23:06:25.224675  Dram Type= 6, Freq= 0, CH_1, rank 0

 4534 23:06:25.230810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4535 23:06:25.231285  ==

 4536 23:06:25.231637  RX Vref Scan: 1

 4537 23:06:25.231978  

 4538 23:06:25.234559  RX Vref 0 -> 0, step: 1

 4539 23:06:25.234997  

 4540 23:06:25.237681  RX Delay -163 -> 252, step: 8

 4541 23:06:25.238114  

 4542 23:06:25.240809  Set Vref, RX VrefLevel [Byte0]: 53

 4543 23:06:25.244227                           [Byte1]: 51

 4544 23:06:25.244643  

 4545 23:06:25.247595  Final RX Vref Byte 0 = 53 to rank0

 4546 23:06:25.251443  Final RX Vref Byte 1 = 51 to rank0

 4547 23:06:25.254373  Final RX Vref Byte 0 = 53 to rank1

 4548 23:06:25.258067  Final RX Vref Byte 1 = 51 to rank1==

 4549 23:06:25.261011  Dram Type= 6, Freq= 0, CH_1, rank 0

 4550 23:06:25.264959  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4551 23:06:25.265503  ==

 4552 23:06:25.267605  DQS Delay:

 4553 23:06:25.268012  DQS0 = 0, DQS1 = 0

 4554 23:06:25.268351  DQM Delay:

 4555 23:06:25.271309  DQM0 = 47, DQM1 = 45

 4556 23:06:25.271721  DQ Delay:

 4557 23:06:25.274283  DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =44

 4558 23:06:25.277893  DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48

 4559 23:06:25.281253  DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36

 4560 23:06:25.284294  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56

 4561 23:06:25.284709  

 4562 23:06:25.285034  

 4563 23:06:25.294977  [DQSOSCAuto] RK0, (LSB)MR18= 0x4268, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 4564 23:06:25.295529  CH1 RK0: MR19=808, MR18=4268

 4565 23:06:25.300900  CH1_RK0: MR19=0x808, MR18=0x4268, DQSOSC=390, MR23=63, INC=172, DEC=114

 4566 23:06:25.301310  

 4567 23:06:25.304407  ----->DramcWriteLeveling(PI) begin...

 4568 23:06:25.304824  ==

 4569 23:06:25.307744  Dram Type= 6, Freq= 0, CH_1, rank 1

 4570 23:06:25.314531  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4571 23:06:25.315074  ==

 4572 23:06:25.317888  Write leveling (Byte 0): 30 => 30

 4573 23:06:25.320862  Write leveling (Byte 1): 30 => 30

 4574 23:06:25.324734  DramcWriteLeveling(PI) end<-----

 4575 23:06:25.325269  

 4576 23:06:25.325637  ==

 4577 23:06:25.327693  Dram Type= 6, Freq= 0, CH_1, rank 1

 4578 23:06:25.330825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4579 23:06:25.331247  ==

 4580 23:06:25.334140  [Gating] SW mode calibration

 4581 23:06:25.340905  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4582 23:06:25.344231  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4583 23:06:25.350664   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4584 23:06:25.353780   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4585 23:06:25.357537   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4586 23:06:25.363868   0  9 12 | B1->B0 | 2f2f 2d2d | 0 0 | (1 1) (0 1)

 4587 23:06:25.367317   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4588 23:06:25.370326   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4589 23:06:25.376932   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4590 23:06:25.380452   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4591 23:06:25.383960   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4592 23:06:25.390083   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4593 23:06:25.393624   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4594 23:06:25.396854   0 10 12 | B1->B0 | 3838 3434 | 0 0 | (0 0) (0 0)

 4595 23:06:25.403474   0 10 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 4596 23:06:25.407459   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4597 23:06:25.410654   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4598 23:06:25.416912   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4599 23:06:25.420438   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4600 23:06:25.424074   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4601 23:06:25.430556   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4602 23:06:25.433624   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

 4603 23:06:25.436956   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4604 23:06:25.443486   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4605 23:06:25.447077   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4606 23:06:25.450518   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4607 23:06:25.457129   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4608 23:06:25.460383   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4609 23:06:25.463668   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4610 23:06:25.470112   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4611 23:06:25.473384   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4612 23:06:25.477018   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4613 23:06:25.483824   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4614 23:06:25.486551   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4615 23:06:25.490290   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4616 23:06:25.493351   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4617 23:06:25.500288   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4618 23:06:25.503516   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4619 23:06:25.507101   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4620 23:06:25.510132  Total UI for P1: 0, mck2ui 16

 4621 23:06:25.513274  best dqsien dly found for B0: ( 0, 13, 14)

 4622 23:06:25.516738  Total UI for P1: 0, mck2ui 16

 4623 23:06:25.520005  best dqsien dly found for B1: ( 0, 13, 14)

 4624 23:06:25.523351  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4625 23:06:25.529708  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4626 23:06:25.530126  

 4627 23:06:25.533386  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4628 23:06:25.536602  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4629 23:06:25.540116  [Gating] SW calibration Done

 4630 23:06:25.540659  ==

 4631 23:06:25.543188  Dram Type= 6, Freq= 0, CH_1, rank 1

 4632 23:06:25.546862  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4633 23:06:25.547376  ==

 4634 23:06:25.547722  RX Vref Scan: 0

 4635 23:06:25.549809  

 4636 23:06:25.550237  RX Vref 0 -> 0, step: 1

 4637 23:06:25.550678  

 4638 23:06:25.553563  RX Delay -230 -> 252, step: 16

 4639 23:06:25.556561  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4640 23:06:25.563120  iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320

 4641 23:06:25.566583  iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304

 4642 23:06:25.570155  iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320

 4643 23:06:25.573132  iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320

 4644 23:06:25.576594  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4645 23:06:25.583707  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4646 23:06:25.586588  iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320

 4647 23:06:25.589949  iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304

 4648 23:06:25.592984  iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320

 4649 23:06:25.600243  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4650 23:06:25.603065  iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320

 4651 23:06:25.606186  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4652 23:06:25.609790  iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320

 4653 23:06:25.616102  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4654 23:06:25.619336  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4655 23:06:25.619753  ==

 4656 23:06:25.623267  Dram Type= 6, Freq= 0, CH_1, rank 1

 4657 23:06:25.626154  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4658 23:06:25.626571  ==

 4659 23:06:25.629722  DQS Delay:

 4660 23:06:25.630219  DQS0 = 0, DQS1 = 0

 4661 23:06:25.630564  DQM Delay:

 4662 23:06:25.632640  DQM0 = 46, DQM1 = 48

 4663 23:06:25.633046  DQ Delay:

 4664 23:06:25.636017  DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41

 4665 23:06:25.639434  DQ4 =41, DQ5 =65, DQ6 =57, DQ7 =41

 4666 23:06:25.642695  DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41

 4667 23:06:25.645870  DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57

 4668 23:06:25.646284  

 4669 23:06:25.646609  

 4670 23:06:25.646912  ==

 4671 23:06:25.649355  Dram Type= 6, Freq= 0, CH_1, rank 1

 4672 23:06:25.652754  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4673 23:06:25.656373  ==

 4674 23:06:25.656788  

 4675 23:06:25.657261  

 4676 23:06:25.657800  	TX Vref Scan disable

 4677 23:06:25.659214   == TX Byte 0 ==

 4678 23:06:25.662580  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 4679 23:06:25.669064  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 4680 23:06:25.669476   == TX Byte 1 ==

 4681 23:06:25.672715  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4682 23:06:25.679220  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4683 23:06:25.679634  ==

 4684 23:06:25.682673  Dram Type= 6, Freq= 0, CH_1, rank 1

 4685 23:06:25.686291  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4686 23:06:25.686760  ==

 4687 23:06:25.687105  

 4688 23:06:25.687413  

 4689 23:06:25.689322  	TX Vref Scan disable

 4690 23:06:25.689765   == TX Byte 0 ==

 4691 23:06:25.695865  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4692 23:06:25.699598  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4693 23:06:25.700119   == TX Byte 1 ==

 4694 23:06:25.706069  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4695 23:06:25.709318  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4696 23:06:25.709773  

 4697 23:06:25.710160  [DATLAT]

 4698 23:06:25.712937  Freq=600, CH1 RK1

 4699 23:06:25.713351  

 4700 23:06:25.713712  DATLAT Default: 0x9

 4701 23:06:25.716469  0, 0xFFFF, sum = 0

 4702 23:06:25.716890  1, 0xFFFF, sum = 0

 4703 23:06:25.719362  2, 0xFFFF, sum = 0

 4704 23:06:25.719776  3, 0xFFFF, sum = 0

 4705 23:06:25.723137  4, 0xFFFF, sum = 0

 4706 23:06:25.723653  5, 0xFFFF, sum = 0

 4707 23:06:25.726331  6, 0xFFFF, sum = 0

 4708 23:06:25.729724  7, 0xFFFF, sum = 0

 4709 23:06:25.730271  8, 0x0, sum = 1

 4710 23:06:25.730614  9, 0x0, sum = 2

 4711 23:06:25.733342  10, 0x0, sum = 3

 4712 23:06:25.733913  11, 0x0, sum = 4

 4713 23:06:25.736259  best_step = 9

 4714 23:06:25.736773  

 4715 23:06:25.737130  ==

 4716 23:06:25.739510  Dram Type= 6, Freq= 0, CH_1, rank 1

 4717 23:06:25.742531  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4718 23:06:25.742947  ==

 4719 23:06:25.746034  RX Vref Scan: 0

 4720 23:06:25.746445  

 4721 23:06:25.746774  RX Vref 0 -> 0, step: 1

 4722 23:06:25.747083  

 4723 23:06:25.749303  RX Delay -163 -> 252, step: 8

 4724 23:06:25.756512  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4725 23:06:25.759571  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4726 23:06:25.762891  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4727 23:06:25.766232  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4728 23:06:25.773158  iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288

 4729 23:06:25.776478  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4730 23:06:25.779607  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4731 23:06:25.783517  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4732 23:06:25.786200  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4733 23:06:25.793613  iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288

 4734 23:06:25.796245  iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296

 4735 23:06:25.800050  iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296

 4736 23:06:25.802961  iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304

 4737 23:06:25.806062  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4738 23:06:25.812640  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4739 23:06:25.816468  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4740 23:06:25.816882  ==

 4741 23:06:25.819285  Dram Type= 6, Freq= 0, CH_1, rank 1

 4742 23:06:25.823078  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4743 23:06:25.823621  ==

 4744 23:06:25.826324  DQS Delay:

 4745 23:06:25.826737  DQS0 = 0, DQS1 = 0

 4746 23:06:25.827063  DQM Delay:

 4747 23:06:25.829458  DQM0 = 48, DQM1 = 45

 4748 23:06:25.829920  DQ Delay:

 4749 23:06:25.833261  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4750 23:06:25.836474  DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48

 4751 23:06:25.839465  DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40

 4752 23:06:25.842940  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52

 4753 23:06:25.843354  

 4754 23:06:25.843680  

 4755 23:06:25.852672  [DQSOSCAuto] RK1, (LSB)MR18= 0x641c, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps

 4756 23:06:25.853104  CH1 RK1: MR19=808, MR18=641C

 4757 23:06:25.859310  CH1_RK1: MR19=0x808, MR18=0x641C, DQSOSC=391, MR23=63, INC=171, DEC=114

 4758 23:06:25.862578  [RxdqsGatingPostProcess] freq 600

 4759 23:06:25.869273  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4760 23:06:25.872660  Pre-setting of DQS Precalculation

 4761 23:06:25.875748  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4762 23:06:25.882481  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4763 23:06:25.893082  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4764 23:06:25.893670  

 4765 23:06:25.894007  

 4766 23:06:25.896543  [Calibration Summary] 1200 Mbps

 4767 23:06:25.897102  CH 0, Rank 0

 4768 23:06:25.899073  SW Impedance     : PASS

 4769 23:06:25.899566  DUTY Scan        : NO K

 4770 23:06:25.902682  ZQ Calibration   : PASS

 4771 23:06:25.905694  Jitter Meter     : NO K

 4772 23:06:25.906145  CBT Training     : PASS

 4773 23:06:25.909366  Write leveling   : PASS

 4774 23:06:25.910007  RX DQS gating    : PASS

 4775 23:06:25.912872  RX DQ/DQS(RDDQC) : PASS

 4776 23:06:25.915937  TX DQ/DQS        : PASS

 4777 23:06:25.916486  RX DATLAT        : PASS

 4778 23:06:25.918812  RX DQ/DQS(Engine): PASS

 4779 23:06:25.922184  TX OE            : NO K

 4780 23:06:25.922712  All Pass.

 4781 23:06:25.923188  

 4782 23:06:25.923586  CH 0, Rank 1

 4783 23:06:25.925870  SW Impedance     : PASS

 4784 23:06:25.929089  DUTY Scan        : NO K

 4785 23:06:25.929701  ZQ Calibration   : PASS

 4786 23:06:25.932594  Jitter Meter     : NO K

 4787 23:06:25.935936  CBT Training     : PASS

 4788 23:06:25.936470  Write leveling   : PASS

 4789 23:06:25.939127  RX DQS gating    : PASS

 4790 23:06:25.942403  RX DQ/DQS(RDDQC) : PASS

 4791 23:06:25.942928  TX DQ/DQS        : PASS

 4792 23:06:25.945622  RX DATLAT        : PASS

 4793 23:06:25.949250  RX DQ/DQS(Engine): PASS

 4794 23:06:25.949910  TX OE            : NO K

 4795 23:06:25.952613  All Pass.

 4796 23:06:25.953260  

 4797 23:06:25.953647  CH 1, Rank 0

 4798 23:06:25.955486  SW Impedance     : PASS

 4799 23:06:25.956009  DUTY Scan        : NO K

 4800 23:06:25.958807  ZQ Calibration   : PASS

 4801 23:06:25.962271  Jitter Meter     : NO K

 4802 23:06:25.962767  CBT Training     : PASS

 4803 23:06:25.965803  Write leveling   : PASS

 4804 23:06:25.966417  RX DQS gating    : PASS

 4805 23:06:25.968993  RX DQ/DQS(RDDQC) : PASS

 4806 23:06:25.971814  TX DQ/DQS        : PASS

 4807 23:06:25.972363  RX DATLAT        : PASS

 4808 23:06:25.975196  RX DQ/DQS(Engine): PASS

 4809 23:06:25.978752  TX OE            : NO K

 4810 23:06:25.979190  All Pass.

 4811 23:06:25.979622  

 4812 23:06:25.979932  CH 1, Rank 1

 4813 23:06:25.982000  SW Impedance     : PASS

 4814 23:06:25.985645  DUTY Scan        : NO K

 4815 23:06:25.986142  ZQ Calibration   : PASS

 4816 23:06:25.988616  Jitter Meter     : NO K

 4817 23:06:25.992095  CBT Training     : PASS

 4818 23:06:25.992581  Write leveling   : PASS

 4819 23:06:25.995360  RX DQS gating    : PASS

 4820 23:06:25.999190  RX DQ/DQS(RDDQC) : PASS

 4821 23:06:25.999749  TX DQ/DQS        : PASS

 4822 23:06:26.002184  RX DATLAT        : PASS

 4823 23:06:26.005267  RX DQ/DQS(Engine): PASS

 4824 23:06:26.005823  TX OE            : NO K

 4825 23:06:26.006169  All Pass.

 4826 23:06:26.008570  

 4827 23:06:26.009028  DramC Write-DBI off

 4828 23:06:26.012324  	PER_BANK_REFRESH: Hybrid Mode

 4829 23:06:26.012852  TX_TRACKING: ON

 4830 23:06:26.021976  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4831 23:06:26.025661  [FAST_K] Save calibration result to emmc

 4832 23:06:26.028874  dramc_set_vcore_voltage set vcore to 662500

 4833 23:06:26.032198  Read voltage for 933, 3

 4834 23:06:26.032613  Vio18 = 0

 4835 23:06:26.035333  Vcore = 662500

 4836 23:06:26.035846  Vdram = 0

 4837 23:06:26.036180  Vddq = 0

 4838 23:06:26.036487  Vmddr = 0

 4839 23:06:26.042115  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4840 23:06:26.045226  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4841 23:06:26.049020  MEM_TYPE=3, freq_sel=17

 4842 23:06:26.052275  sv_algorithm_assistance_LP4_1600 

 4843 23:06:26.055273  ============ PULL DRAM RESETB DOWN ============

 4844 23:06:26.061693  ========== PULL DRAM RESETB DOWN end =========

 4845 23:06:26.065281  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4846 23:06:26.068397  =================================== 

 4847 23:06:26.071942  LPDDR4 DRAM CONFIGURATION

 4848 23:06:26.075741  =================================== 

 4849 23:06:26.076289  EX_ROW_EN[0]    = 0x0

 4850 23:06:26.078903  EX_ROW_EN[1]    = 0x0

 4851 23:06:26.079486  LP4Y_EN      = 0x0

 4852 23:06:26.081986  WORK_FSP     = 0x0

 4853 23:06:26.082399  WL           = 0x3

 4854 23:06:26.085556  RL           = 0x3

 4855 23:06:26.086010  BL           = 0x2

 4856 23:06:26.088962  RPST         = 0x0

 4857 23:06:26.089375  RD_PRE       = 0x0

 4858 23:06:26.092054  WR_PRE       = 0x1

 4859 23:06:26.092467  WR_PST       = 0x0

 4860 23:06:26.095426  DBI_WR       = 0x0

 4861 23:06:26.095942  DBI_RD       = 0x0

 4862 23:06:26.098504  OTF          = 0x1

 4863 23:06:26.102620  =================================== 

 4864 23:06:26.105327  =================================== 

 4865 23:06:26.105795  ANA top config

 4866 23:06:26.108873  =================================== 

 4867 23:06:26.112199  DLL_ASYNC_EN            =  0

 4868 23:06:26.115395  ALL_SLAVE_EN            =  1

 4869 23:06:26.118561  NEW_RANK_MODE           =  1

 4870 23:06:26.121540  DLL_IDLE_MODE           =  1

 4871 23:06:26.122076  LP45_APHY_COMB_EN       =  1

 4872 23:06:26.124968  TX_ODT_DIS              =  1

 4873 23:06:26.128170  NEW_8X_MODE             =  1

 4874 23:06:26.131904  =================================== 

 4875 23:06:26.134842  =================================== 

 4876 23:06:26.138670  data_rate                  = 1866

 4877 23:06:26.141914  CKR                        = 1

 4878 23:06:26.142471  DQ_P2S_RATIO               = 8

 4879 23:06:26.145190  =================================== 

 4880 23:06:26.148171  CA_P2S_RATIO               = 8

 4881 23:06:26.151659  DQ_CA_OPEN                 = 0

 4882 23:06:26.154722  DQ_SEMI_OPEN               = 0

 4883 23:06:26.158314  CA_SEMI_OPEN               = 0

 4884 23:06:26.161678  CA_FULL_RATE               = 0

 4885 23:06:26.162100  DQ_CKDIV4_EN               = 1

 4886 23:06:26.164817  CA_CKDIV4_EN               = 1

 4887 23:06:26.167858  CA_PREDIV_EN               = 0

 4888 23:06:26.171627  PH8_DLY                    = 0

 4889 23:06:26.174614  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4890 23:06:26.178255  DQ_AAMCK_DIV               = 4

 4891 23:06:26.178670  CA_AAMCK_DIV               = 4

 4892 23:06:26.181159  CA_ADMCK_DIV               = 4

 4893 23:06:26.184664  DQ_TRACK_CA_EN             = 0

 4894 23:06:26.187868  CA_PICK                    = 933

 4895 23:06:26.191551  CA_MCKIO                   = 933

 4896 23:06:26.194469  MCKIO_SEMI                 = 0

 4897 23:06:26.198265  PLL_FREQ                   = 3732

 4898 23:06:26.198751  DQ_UI_PI_RATIO             = 32

 4899 23:06:26.201214  CA_UI_PI_RATIO             = 0

 4900 23:06:26.204589  =================================== 

 4901 23:06:26.207650  =================================== 

 4902 23:06:26.211229  memory_type:LPDDR4         

 4903 23:06:26.214097  GP_NUM     : 10       

 4904 23:06:26.214509  SRAM_EN    : 1       

 4905 23:06:26.217820  MD32_EN    : 0       

 4906 23:06:26.220739  =================================== 

 4907 23:06:26.224545  [ANA_INIT] >>>>>>>>>>>>>> 

 4908 23:06:26.225055  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4909 23:06:26.227596  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4910 23:06:26.230752  =================================== 

 4911 23:06:26.234086  data_rate = 1866,PCW = 0X8f00

 4912 23:06:26.237349  =================================== 

 4913 23:06:26.240948  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4914 23:06:26.247383  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4915 23:06:26.254083  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4916 23:06:26.257214  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4917 23:06:26.260716  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4918 23:06:26.263953  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4919 23:06:26.267163  [ANA_INIT] flow start 

 4920 23:06:26.267580  [ANA_INIT] PLL >>>>>>>> 

 4921 23:06:26.270699  [ANA_INIT] PLL <<<<<<<< 

 4922 23:06:26.273932  [ANA_INIT] MIDPI >>>>>>>> 

 4923 23:06:26.277140  [ANA_INIT] MIDPI <<<<<<<< 

 4924 23:06:26.277551  [ANA_INIT] DLL >>>>>>>> 

 4925 23:06:26.280704  [ANA_INIT] flow end 

 4926 23:06:26.284119  ============ LP4 DIFF to SE enter ============

 4927 23:06:26.287245  ============ LP4 DIFF to SE exit  ============

 4928 23:06:26.290836  [ANA_INIT] <<<<<<<<<<<<< 

 4929 23:06:26.293631  [Flow] Enable top DCM control >>>>> 

 4930 23:06:26.297137  [Flow] Enable top DCM control <<<<< 

 4931 23:06:26.300496  Enable DLL master slave shuffle 

 4932 23:06:26.307184  ============================================================== 

 4933 23:06:26.307792  Gating Mode config

 4934 23:06:26.313836  ============================================================== 

 4935 23:06:26.314437  Config description: 

 4936 23:06:26.323983  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4937 23:06:26.330377  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4938 23:06:26.337192  SELPH_MODE            0: By rank         1: By Phase 

 4939 23:06:26.340745  ============================================================== 

 4940 23:06:26.343270  GAT_TRACK_EN                 =  1

 4941 23:06:26.347167  RX_GATING_MODE               =  2

 4942 23:06:26.350012  RX_GATING_TRACK_MODE         =  2

 4943 23:06:26.353287  SELPH_MODE                   =  1

 4944 23:06:26.356787  PICG_EARLY_EN                =  1

 4945 23:06:26.359934  VALID_LAT_VALUE              =  1

 4946 23:06:26.363282  ============================================================== 

 4947 23:06:26.366541  Enter into Gating configuration >>>> 

 4948 23:06:26.370428  Exit from Gating configuration <<<< 

 4949 23:06:26.373094  Enter into  DVFS_PRE_config >>>>> 

 4950 23:06:26.386533  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4951 23:06:26.389965  Exit from  DVFS_PRE_config <<<<< 

 4952 23:06:26.393243  Enter into PICG configuration >>>> 

 4953 23:06:26.396507  Exit from PICG configuration <<<< 

 4954 23:06:26.396939  [RX_INPUT] configuration >>>>> 

 4955 23:06:26.399917  [RX_INPUT] configuration <<<<< 

 4956 23:06:26.407080  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4957 23:06:26.410135  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4958 23:06:26.416890  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4959 23:06:26.423320  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4960 23:06:26.430251  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4961 23:06:26.436598  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4962 23:06:26.440443  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4963 23:06:26.443091  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4964 23:06:26.449631  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4965 23:06:26.453130  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4966 23:06:26.456368  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4967 23:06:26.459900  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4968 23:06:26.462974  =================================== 

 4969 23:06:26.466385  LPDDR4 DRAM CONFIGURATION

 4970 23:06:26.469739  =================================== 

 4971 23:06:26.473228  EX_ROW_EN[0]    = 0x0

 4972 23:06:26.473703  EX_ROW_EN[1]    = 0x0

 4973 23:06:26.476476  LP4Y_EN      = 0x0

 4974 23:06:26.477020  WORK_FSP     = 0x0

 4975 23:06:26.479532  WL           = 0x3

 4976 23:06:26.479967  RL           = 0x3

 4977 23:06:26.483435  BL           = 0x2

 4978 23:06:26.484019  RPST         = 0x0

 4979 23:06:26.486465  RD_PRE       = 0x0

 4980 23:06:26.486900  WR_PRE       = 0x1

 4981 23:06:26.489960  WR_PST       = 0x0

 4982 23:06:26.490395  DBI_WR       = 0x0

 4983 23:06:26.492881  DBI_RD       = 0x0

 4984 23:06:26.493314  OTF          = 0x1

 4985 23:06:26.496188  =================================== 

 4986 23:06:26.502812  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 4987 23:06:26.506087  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 4988 23:06:26.509661  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4989 23:06:26.513044  =================================== 

 4990 23:06:26.516307  LPDDR4 DRAM CONFIGURATION

 4991 23:06:26.519282  =================================== 

 4992 23:06:26.522537  EX_ROW_EN[0]    = 0x10

 4993 23:06:26.522977  EX_ROW_EN[1]    = 0x0

 4994 23:06:26.526178  LP4Y_EN      = 0x0

 4995 23:06:26.526605  WORK_FSP     = 0x0

 4996 23:06:26.529550  WL           = 0x3

 4997 23:06:26.530006  RL           = 0x3

 4998 23:06:26.532760  BL           = 0x2

 4999 23:06:26.533180  RPST         = 0x0

 5000 23:06:26.536558  RD_PRE       = 0x0

 5001 23:06:26.537144  WR_PRE       = 0x1

 5002 23:06:26.540347  WR_PST       = 0x0

 5003 23:06:26.541057  DBI_WR       = 0x0

 5004 23:06:26.542955  DBI_RD       = 0x0

 5005 23:06:26.543387  OTF          = 0x1

 5006 23:06:26.546528  =================================== 

 5007 23:06:26.552776  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5008 23:06:26.557346  nWR fixed to 30

 5009 23:06:26.560774  [ModeRegInit_LP4] CH0 RK0

 5010 23:06:26.561267  [ModeRegInit_LP4] CH0 RK1

 5011 23:06:26.564312  [ModeRegInit_LP4] CH1 RK0

 5012 23:06:26.567225  [ModeRegInit_LP4] CH1 RK1

 5013 23:06:26.567641  match AC timing 9

 5014 23:06:26.573974  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5015 23:06:26.577400  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5016 23:06:26.580770  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5017 23:06:26.587591  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5018 23:06:26.590582  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5019 23:06:26.591006  ==

 5020 23:06:26.593870  Dram Type= 6, Freq= 0, CH_0, rank 0

 5021 23:06:26.597152  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5022 23:06:26.597570  ==

 5023 23:06:26.603815  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5024 23:06:26.610746  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5025 23:06:26.614160  [CA 0] Center 37 (7~68) winsize 62

 5026 23:06:26.616934  [CA 1] Center 37 (7~68) winsize 62

 5027 23:06:26.620547  [CA 2] Center 34 (4~65) winsize 62

 5028 23:06:26.623839  [CA 3] Center 34 (3~65) winsize 63

 5029 23:06:26.627019  [CA 4] Center 33 (3~64) winsize 62

 5030 23:06:26.630901  [CA 5] Center 32 (2~62) winsize 61

 5031 23:06:26.631387  

 5032 23:06:26.633873  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5033 23:06:26.634318  

 5034 23:06:26.636998  [CATrainingPosCal] consider 1 rank data

 5035 23:06:26.640414  u2DelayCellTimex100 = 270/100 ps

 5036 23:06:26.643825  CA0 delay=37 (7~68),Diff = 5 PI (31 cell)

 5037 23:06:26.647304  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5038 23:06:26.650304  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5039 23:06:26.654087  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5040 23:06:26.656886  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5041 23:06:26.660555  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5042 23:06:26.663927  

 5043 23:06:26.666844  CA PerBit enable=1, Macro0, CA PI delay=32

 5044 23:06:26.667265  

 5045 23:06:26.670487  [CBTSetCACLKResult] CA Dly = 32

 5046 23:06:26.670920  CS Dly: 5 (0~36)

 5047 23:06:26.671257  ==

 5048 23:06:26.673424  Dram Type= 6, Freq= 0, CH_0, rank 1

 5049 23:06:26.677231  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5050 23:06:26.677928  ==

 5051 23:06:26.683602  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5052 23:06:26.690062  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5053 23:06:26.693760  [CA 0] Center 37 (6~68) winsize 63

 5054 23:06:26.696760  [CA 1] Center 37 (6~68) winsize 63

 5055 23:06:26.700233  [CA 2] Center 34 (4~65) winsize 62

 5056 23:06:26.703566  [CA 3] Center 34 (4~65) winsize 62

 5057 23:06:26.706750  [CA 4] Center 32 (2~63) winsize 62

 5058 23:06:26.710238  [CA 5] Center 32 (2~63) winsize 62

 5059 23:06:26.710897  

 5060 23:06:26.713680  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5061 23:06:26.714260  

 5062 23:06:26.716767  [CATrainingPosCal] consider 2 rank data

 5063 23:06:26.720020  u2DelayCellTimex100 = 270/100 ps

 5064 23:06:26.723666  CA0 delay=37 (7~68),Diff = 5 PI (31 cell)

 5065 23:06:26.726977  CA1 delay=37 (7~68),Diff = 5 PI (31 cell)

 5066 23:06:26.730502  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5067 23:06:26.733356  CA3 delay=34 (4~65),Diff = 2 PI (12 cell)

 5068 23:06:26.739906  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5069 23:06:26.743219  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5070 23:06:26.743765  

 5071 23:06:26.746751  CA PerBit enable=1, Macro0, CA PI delay=32

 5072 23:06:26.747166  

 5073 23:06:26.750142  [CBTSetCACLKResult] CA Dly = 32

 5074 23:06:26.750555  CS Dly: 5 (0~37)

 5075 23:06:26.750883  

 5076 23:06:26.753663  ----->DramcWriteLeveling(PI) begin...

 5077 23:06:26.754089  ==

 5078 23:06:26.756819  Dram Type= 6, Freq= 0, CH_0, rank 0

 5079 23:06:26.763329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5080 23:06:26.763750  ==

 5081 23:06:26.766619  Write leveling (Byte 0): 31 => 31

 5082 23:06:26.767050  Write leveling (Byte 1): 29 => 29

 5083 23:06:26.770178  DramcWriteLeveling(PI) end<-----

 5084 23:06:26.770594  

 5085 23:06:26.773135  ==

 5086 23:06:26.773566  Dram Type= 6, Freq= 0, CH_0, rank 0

 5087 23:06:26.779720  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5088 23:06:26.780205  ==

 5089 23:06:26.783320  [Gating] SW mode calibration

 5090 23:06:26.789928  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5091 23:06:26.793175  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5092 23:06:26.799600   0 14  0 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)

 5093 23:06:26.803044   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5094 23:06:26.806739   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5095 23:06:26.813324   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5096 23:06:26.816183   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5097 23:06:26.819710   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5098 23:06:26.826397   0 14 24 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)

 5099 23:06:26.829476   0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 1) (1 0)

 5100 23:06:26.832589   0 15  0 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)

 5101 23:06:26.839336   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5102 23:06:26.842775   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5103 23:06:26.845948   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5104 23:06:26.852817   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5105 23:06:26.856160   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5106 23:06:26.859608   0 15 24 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 5107 23:06:26.866225   0 15 28 | B1->B0 | 2828 3737 | 0 0 | (0 0) (1 1)

 5108 23:06:26.869558   1  0  0 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)

 5109 23:06:26.873076   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5110 23:06:26.876314   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5111 23:06:26.882571   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5112 23:06:26.886060   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5113 23:06:26.889505   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5114 23:06:26.895935   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5115 23:06:26.899247   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5116 23:06:26.902991   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5117 23:06:26.909448   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5118 23:06:26.912310   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5119 23:06:26.915951   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5120 23:06:26.922562   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5121 23:06:26.926139   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5122 23:06:26.929173   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5123 23:06:26.935694   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5124 23:06:26.938966   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5125 23:06:26.942670   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5126 23:06:26.948994   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5127 23:06:26.952371   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5128 23:06:26.955856   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5129 23:06:26.962287   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5130 23:06:26.965911   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5131 23:06:26.968715   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5132 23:06:26.975064   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5133 23:06:26.978574  Total UI for P1: 0, mck2ui 16

 5134 23:06:26.982013  best dqsien dly found for B0: ( 1,  2, 28)

 5135 23:06:26.985619   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5136 23:06:26.988419  Total UI for P1: 0, mck2ui 16

 5137 23:06:26.992361  best dqsien dly found for B1: ( 1,  3,  0)

 5138 23:06:26.994928  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5139 23:06:26.998692  best DQS1 dly(MCK, UI, PI) = (1, 3, 0)

 5140 23:06:26.999129  

 5141 23:06:27.001560  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5142 23:06:27.005124  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)

 5143 23:06:27.008734  [Gating] SW calibration Done

 5144 23:06:27.009111  ==

 5145 23:06:27.011714  Dram Type= 6, Freq= 0, CH_0, rank 0

 5146 23:06:27.015313  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5147 23:06:27.018303  ==

 5148 23:06:27.018717  RX Vref Scan: 0

 5149 23:06:27.019046  

 5150 23:06:27.021872  RX Vref 0 -> 0, step: 1

 5151 23:06:27.022288  

 5152 23:06:27.024930  RX Delay -80 -> 252, step: 8

 5153 23:06:27.028852  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5154 23:06:27.031739  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5155 23:06:27.035180  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5156 23:06:27.038786  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5157 23:06:27.041513  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5158 23:06:27.048160  iDelay=208, Bit 5, Center 91 (0 ~ 183) 184

 5159 23:06:27.051751  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5160 23:06:27.054814  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5161 23:06:27.058456  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5162 23:06:27.061672  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5163 23:06:27.065112  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5164 23:06:27.071761  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5165 23:06:27.074741  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5166 23:06:27.078251  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5167 23:06:27.081529  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5168 23:06:27.084680  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5169 23:06:27.085215  ==

 5170 23:06:27.088007  Dram Type= 6, Freq= 0, CH_0, rank 0

 5171 23:06:27.095229  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5172 23:06:27.095813  ==

 5173 23:06:27.096151  DQS Delay:

 5174 23:06:27.097767  DQS0 = 0, DQS1 = 0

 5175 23:06:27.098187  DQM Delay:

 5176 23:06:27.101264  DQM0 = 105, DQM1 = 93

 5177 23:06:27.101774  DQ Delay:

 5178 23:06:27.104441  DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99

 5179 23:06:27.107893  DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115

 5180 23:06:27.111407  DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87

 5181 23:06:27.114622  DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99

 5182 23:06:27.115101  

 5183 23:06:27.115445  

 5184 23:06:27.115754  ==

 5185 23:06:27.117935  Dram Type= 6, Freq= 0, CH_0, rank 0

 5186 23:06:27.121238  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5187 23:06:27.121707  ==

 5188 23:06:27.122151  

 5189 23:06:27.122476  

 5190 23:06:27.124479  	TX Vref Scan disable

 5191 23:06:27.127966   == TX Byte 0 ==

 5192 23:06:27.131226  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5193 23:06:27.134636  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5194 23:06:27.138016   == TX Byte 1 ==

 5195 23:06:27.141344  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5196 23:06:27.144466  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5197 23:06:27.145035  ==

 5198 23:06:27.147966  Dram Type= 6, Freq= 0, CH_0, rank 0

 5199 23:06:27.154483  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5200 23:06:27.154987  ==

 5201 23:06:27.155342  

 5202 23:06:27.155653  

 5203 23:06:27.155952  	TX Vref Scan disable

 5204 23:06:27.158046   == TX Byte 0 ==

 5205 23:06:27.161687  Update DQ  dly =714 (2 ,6, 10)  DQ  OEN =(2 ,3)

 5206 23:06:27.165200  Update DQM dly =714 (2 ,6, 10)  DQM OEN =(2 ,3)

 5207 23:06:27.168331   == TX Byte 1 ==

 5208 23:06:27.171853  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5209 23:06:27.174851  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5210 23:06:27.178410  

 5211 23:06:27.178829  [DATLAT]

 5212 23:06:27.179158  Freq=933, CH0 RK0

 5213 23:06:27.179471  

 5214 23:06:27.181487  DATLAT Default: 0xd

 5215 23:06:27.181952  0, 0xFFFF, sum = 0

 5216 23:06:27.185214  1, 0xFFFF, sum = 0

 5217 23:06:27.185810  2, 0xFFFF, sum = 0

 5218 23:06:27.188504  3, 0xFFFF, sum = 0

 5219 23:06:27.189020  4, 0xFFFF, sum = 0

 5220 23:06:27.191374  5, 0xFFFF, sum = 0

 5221 23:06:27.191805  6, 0xFFFF, sum = 0

 5222 23:06:27.194995  7, 0xFFFF, sum = 0

 5223 23:06:27.198043  8, 0xFFFF, sum = 0

 5224 23:06:27.198514  9, 0xFFFF, sum = 0

 5225 23:06:27.201342  10, 0x0, sum = 1

 5226 23:06:27.201825  11, 0x0, sum = 2

 5227 23:06:27.202171  12, 0x0, sum = 3

 5228 23:06:27.204875  13, 0x0, sum = 4

 5229 23:06:27.205389  best_step = 11

 5230 23:06:27.205782  

 5231 23:06:27.206101  ==

 5232 23:06:27.208377  Dram Type= 6, Freq= 0, CH_0, rank 0

 5233 23:06:27.214949  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5234 23:06:27.215457  ==

 5235 23:06:27.215798  RX Vref Scan: 1

 5236 23:06:27.216110  

 5237 23:06:27.218363  RX Vref 0 -> 0, step: 1

 5238 23:06:27.218879  

 5239 23:06:27.221339  RX Delay -53 -> 252, step: 4

 5240 23:06:27.221824  

 5241 23:06:27.224877  Set Vref, RX VrefLevel [Byte0]: 53

 5242 23:06:27.228377                           [Byte1]: 46

 5243 23:06:27.228798  

 5244 23:06:27.231772  Final RX Vref Byte 0 = 53 to rank0

 5245 23:06:27.234847  Final RX Vref Byte 1 = 46 to rank0

 5246 23:06:27.238155  Final RX Vref Byte 0 = 53 to rank1

 5247 23:06:27.241534  Final RX Vref Byte 1 = 46 to rank1==

 5248 23:06:27.244850  Dram Type= 6, Freq= 0, CH_0, rank 0

 5249 23:06:27.248364  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5250 23:06:27.248786  ==

 5251 23:06:27.251653  DQS Delay:

 5252 23:06:27.252205  DQS0 = 0, DQS1 = 0

 5253 23:06:27.254806  DQM Delay:

 5254 23:06:27.255224  DQM0 = 104, DQM1 = 95

 5255 23:06:27.255558  DQ Delay:

 5256 23:06:27.258258  DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =104

 5257 23:06:27.261261  DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110

 5258 23:06:27.264838  DQ8 =84, DQ9 =86, DQ10 =96, DQ11 =90

 5259 23:06:27.271377  DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102

 5260 23:06:27.271800  

 5261 23:06:27.272129  

 5262 23:06:27.277885  [DQSOSCAuto] RK0, (LSB)MR18= 0x2c24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps

 5263 23:06:27.281530  CH0 RK0: MR19=505, MR18=2C24

 5264 23:06:27.288348  CH0_RK0: MR19=0x505, MR18=0x2C24, DQSOSC=408, MR23=63, INC=65, DEC=43

 5265 23:06:27.288865  

 5266 23:06:27.291154  ----->DramcWriteLeveling(PI) begin...

 5267 23:06:27.291728  ==

 5268 23:06:27.294512  Dram Type= 6, Freq= 0, CH_0, rank 1

 5269 23:06:27.298306  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5270 23:06:27.298827  ==

 5271 23:06:27.301103  Write leveling (Byte 0): 34 => 34

 5272 23:06:27.304861  Write leveling (Byte 1): 26 => 26

 5273 23:06:27.307520  DramcWriteLeveling(PI) end<-----

 5274 23:06:27.307932  

 5275 23:06:27.308255  ==

 5276 23:06:27.311146  Dram Type= 6, Freq= 0, CH_0, rank 1

 5277 23:06:27.314337  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5278 23:06:27.314754  ==

 5279 23:06:27.317984  [Gating] SW mode calibration

 5280 23:06:27.324549  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5281 23:06:27.331399  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5282 23:06:27.334492   0 14  0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)

 5283 23:06:27.341055   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5284 23:06:27.344481   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5285 23:06:27.347440   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5286 23:06:27.354053   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5287 23:06:27.357442   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5288 23:06:27.361112   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5289 23:06:27.367742   0 14 28 | B1->B0 | 2a2a 2929 | 0 0 | (0 0) (0 1)

 5290 23:06:27.370742   0 15  0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)

 5291 23:06:27.373920   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5292 23:06:27.380474   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5293 23:06:27.383891   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5294 23:06:27.386984   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5295 23:06:27.393696   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5296 23:06:27.397205   0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 5297 23:06:27.400851   0 15 28 | B1->B0 | 3434 3737 | 0 1 | (0 0) (0 0)

 5298 23:06:27.404077   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5299 23:06:27.410347   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5300 23:06:27.414178   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5301 23:06:27.417111   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5302 23:06:27.424071   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5303 23:06:27.427332   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5304 23:06:27.430669   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5305 23:06:27.437100   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5306 23:06:27.440820   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5307 23:06:27.443675   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5308 23:06:27.450172   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5309 23:06:27.453722   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5310 23:06:27.457146   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5311 23:06:27.463890   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5312 23:06:27.466910   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5313 23:06:27.470187   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5314 23:06:27.476761   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5315 23:06:27.480054   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5316 23:06:27.483289   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5317 23:06:27.490186   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5318 23:06:27.493095   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5319 23:06:27.496463   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5320 23:06:27.503055   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5321 23:06:27.506229   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5322 23:06:27.509567   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5323 23:06:27.513425  Total UI for P1: 0, mck2ui 16

 5324 23:06:27.516588  best dqsien dly found for B0: ( 1,  2, 28)

 5325 23:06:27.519525  Total UI for P1: 0, mck2ui 16

 5326 23:06:27.522956  best dqsien dly found for B1: ( 1,  2, 28)

 5327 23:06:27.526126  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5328 23:06:27.529547  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5329 23:06:27.530026  

 5330 23:06:27.536154  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5331 23:06:27.539910  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5332 23:06:27.540427  [Gating] SW calibration Done

 5333 23:06:27.543019  ==

 5334 23:06:27.546192  Dram Type= 6, Freq= 0, CH_0, rank 1

 5335 23:06:27.549306  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5336 23:06:27.549775  ==

 5337 23:06:27.550120  RX Vref Scan: 0

 5338 23:06:27.550430  

 5339 23:06:27.552888  RX Vref 0 -> 0, step: 1

 5340 23:06:27.553303  

 5341 23:06:27.556441  RX Delay -80 -> 252, step: 8

 5342 23:06:27.559430  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5343 23:06:27.563095  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5344 23:06:27.565984  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5345 23:06:27.573203  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5346 23:06:27.576473  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5347 23:06:27.579756  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5348 23:06:27.583200  iDelay=208, Bit 6, Center 111 (24 ~ 199) 176

 5349 23:06:27.586429  iDelay=208, Bit 7, Center 111 (16 ~ 207) 192

 5350 23:06:27.589662  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5351 23:06:27.596347  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5352 23:06:27.599821  iDelay=208, Bit 10, Center 91 (0 ~ 183) 184

 5353 23:06:27.602739  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5354 23:06:27.606442  iDelay=208, Bit 12, Center 95 (8 ~ 183) 176

 5355 23:06:27.609070  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5356 23:06:27.612716  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5357 23:06:27.619557  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5358 23:06:27.620097  ==

 5359 23:06:27.622523  Dram Type= 6, Freq= 0, CH_0, rank 1

 5360 23:06:27.626297  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5361 23:06:27.626852  ==

 5362 23:06:27.627224  DQS Delay:

 5363 23:06:27.629149  DQS0 = 0, DQS1 = 0

 5364 23:06:27.629667  DQM Delay:

 5365 23:06:27.633003  DQM0 = 104, DQM1 = 93

 5366 23:06:27.633561  DQ Delay:

 5367 23:06:27.635980  DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99

 5368 23:06:27.639722  DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =111

 5369 23:06:27.642829  DQ8 =87, DQ9 =87, DQ10 =91, DQ11 =87

 5370 23:06:27.646108  DQ12 =95, DQ13 =99, DQ14 =99, DQ15 =99

 5371 23:06:27.646585  

 5372 23:06:27.646962  

 5373 23:06:27.647352  ==

 5374 23:06:27.648975  Dram Type= 6, Freq= 0, CH_0, rank 1

 5375 23:06:27.652575  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5376 23:06:27.656183  ==

 5377 23:06:27.656745  

 5378 23:06:27.657110  

 5379 23:06:27.657450  	TX Vref Scan disable

 5380 23:06:27.659228   == TX Byte 0 ==

 5381 23:06:27.662848  Update DQ  dly =719 (2 ,6, 15)  DQ  OEN =(2 ,3)

 5382 23:06:27.669283  Update DQM dly =719 (2 ,6, 15)  DQM OEN =(2 ,3)

 5383 23:06:27.669882   == TX Byte 1 ==

 5384 23:06:27.672600  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5385 23:06:27.678813  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5386 23:06:27.679355  ==

 5387 23:06:27.682294  Dram Type= 6, Freq= 0, CH_0, rank 1

 5388 23:06:27.685837  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5389 23:06:27.686321  ==

 5390 23:06:27.686744  

 5391 23:06:27.687088  

 5392 23:06:27.688707  	TX Vref Scan disable

 5393 23:06:27.689124   == TX Byte 0 ==

 5394 23:06:27.695252  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5395 23:06:27.698765  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5396 23:06:27.699229   == TX Byte 1 ==

 5397 23:06:27.705485  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5398 23:06:27.708576  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5399 23:06:27.709077  

 5400 23:06:27.709416  [DATLAT]

 5401 23:06:27.712045  Freq=933, CH0 RK1

 5402 23:06:27.712552  

 5403 23:06:27.712886  DATLAT Default: 0xb

 5404 23:06:27.715583  0, 0xFFFF, sum = 0

 5405 23:06:27.716028  1, 0xFFFF, sum = 0

 5406 23:06:27.718776  2, 0xFFFF, sum = 0

 5407 23:06:27.719298  3, 0xFFFF, sum = 0

 5408 23:06:27.722315  4, 0xFFFF, sum = 0

 5409 23:06:27.725752  5, 0xFFFF, sum = 0

 5410 23:06:27.726281  6, 0xFFFF, sum = 0

 5411 23:06:27.729323  7, 0xFFFF, sum = 0

 5412 23:06:27.729903  8, 0xFFFF, sum = 0

 5413 23:06:27.732665  9, 0xFFFF, sum = 0

 5414 23:06:27.733204  10, 0x0, sum = 1

 5415 23:06:27.735485  11, 0x0, sum = 2

 5416 23:06:27.735912  12, 0x0, sum = 3

 5417 23:06:27.736340  13, 0x0, sum = 4

 5418 23:06:27.739204  best_step = 11

 5419 23:06:27.739718  

 5420 23:06:27.740052  ==

 5421 23:06:27.742544  Dram Type= 6, Freq= 0, CH_0, rank 1

 5422 23:06:27.745460  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5423 23:06:27.746047  ==

 5424 23:06:27.749126  RX Vref Scan: 0

 5425 23:06:27.749649  

 5426 23:06:27.750162  RX Vref 0 -> 0, step: 1

 5427 23:06:27.752775  

 5428 23:06:27.753288  RX Delay -45 -> 252, step: 4

 5429 23:06:27.759794  iDelay=195, Bit 0, Center 102 (15 ~ 190) 176

 5430 23:06:27.762722  iDelay=195, Bit 1, Center 106 (19 ~ 194) 176

 5431 23:06:27.766091  iDelay=195, Bit 2, Center 102 (15 ~ 190) 176

 5432 23:06:27.769482  iDelay=195, Bit 3, Center 102 (15 ~ 190) 176

 5433 23:06:27.772926  iDelay=195, Bit 4, Center 106 (19 ~ 194) 176

 5434 23:06:27.778913  iDelay=195, Bit 5, Center 98 (11 ~ 186) 176

 5435 23:06:27.782422  iDelay=195, Bit 6, Center 108 (23 ~ 194) 172

 5436 23:06:27.785977  iDelay=195, Bit 7, Center 110 (27 ~ 194) 168

 5437 23:06:27.789784  iDelay=195, Bit 8, Center 82 (-1 ~ 166) 168

 5438 23:06:27.792701  iDelay=195, Bit 9, Center 82 (-1 ~ 166) 168

 5439 23:06:27.799313  iDelay=195, Bit 10, Center 96 (15 ~ 178) 164

 5440 23:06:27.802663  iDelay=195, Bit 11, Center 88 (7 ~ 170) 164

 5441 23:06:27.806012  iDelay=195, Bit 12, Center 100 (19 ~ 182) 164

 5442 23:06:27.809108  iDelay=195, Bit 13, Center 100 (19 ~ 182) 164

 5443 23:06:27.812682  iDelay=195, Bit 14, Center 102 (19 ~ 186) 168

 5444 23:06:27.819412  iDelay=195, Bit 15, Center 100 (15 ~ 186) 172

 5445 23:06:27.819994  ==

 5446 23:06:27.822528  Dram Type= 6, Freq= 0, CH_0, rank 1

 5447 23:06:27.825738  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5448 23:06:27.826293  ==

 5449 23:06:27.826662  DQS Delay:

 5450 23:06:27.829046  DQS0 = 0, DQS1 = 0

 5451 23:06:27.829508  DQM Delay:

 5452 23:06:27.832397  DQM0 = 104, DQM1 = 93

 5453 23:06:27.832950  DQ Delay:

 5454 23:06:27.835484  DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102

 5455 23:06:27.839104  DQ4 =106, DQ5 =98, DQ6 =108, DQ7 =110

 5456 23:06:27.842104  DQ8 =82, DQ9 =82, DQ10 =96, DQ11 =88

 5457 23:06:27.845143  DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =100

 5458 23:06:27.845818  

 5459 23:06:27.846206  

 5460 23:06:27.855489  [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps

 5461 23:06:27.858515  CH0 RK1: MR19=505, MR18=2700

 5462 23:06:27.862016  CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43

 5463 23:06:27.865472  [RxdqsGatingPostProcess] freq 933

 5464 23:06:27.872006  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5465 23:06:27.875561  best DQS0 dly(2T, 0.5T) = (0, 10)

 5466 23:06:27.879010  best DQS1 dly(2T, 0.5T) = (0, 11)

 5467 23:06:27.882471  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5468 23:06:27.885364  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 5469 23:06:27.888639  best DQS0 dly(2T, 0.5T) = (0, 10)

 5470 23:06:27.891705  best DQS1 dly(2T, 0.5T) = (0, 10)

 5471 23:06:27.895377  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5472 23:06:27.898551  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5473 23:06:27.902074  Pre-setting of DQS Precalculation

 5474 23:06:27.905339  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5475 23:06:27.905909  ==

 5476 23:06:27.908918  Dram Type= 6, Freq= 0, CH_1, rank 0

 5477 23:06:27.912345  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5478 23:06:27.912861  ==

 5479 23:06:27.918575  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5480 23:06:27.925484  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5481 23:06:27.928881  [CA 0] Center 36 (6~67) winsize 62

 5482 23:06:27.932250  [CA 1] Center 37 (6~68) winsize 63

 5483 23:06:27.935384  [CA 2] Center 34 (4~65) winsize 62

 5484 23:06:27.938928  [CA 3] Center 34 (4~64) winsize 61

 5485 23:06:27.941790  [CA 4] Center 34 (4~64) winsize 61

 5486 23:06:27.945083  [CA 5] Center 33 (3~64) winsize 62

 5487 23:06:27.945650  

 5488 23:06:27.948441  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5489 23:06:27.948862  

 5490 23:06:27.951859  [CATrainingPosCal] consider 1 rank data

 5491 23:06:27.954936  u2DelayCellTimex100 = 270/100 ps

 5492 23:06:27.958302  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5493 23:06:27.961919  CA1 delay=37 (6~68),Diff = 4 PI (24 cell)

 5494 23:06:27.964936  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5495 23:06:27.968389  CA3 delay=34 (4~64),Diff = 1 PI (6 cell)

 5496 23:06:27.971586  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5497 23:06:27.978243  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5498 23:06:27.978877  

 5499 23:06:27.981524  CA PerBit enable=1, Macro0, CA PI delay=33

 5500 23:06:27.982068  

 5501 23:06:27.985342  [CBTSetCACLKResult] CA Dly = 33

 5502 23:06:27.985964  CS Dly: 7 (0~38)

 5503 23:06:27.986335  ==

 5504 23:06:27.988846  Dram Type= 6, Freq= 0, CH_1, rank 1

 5505 23:06:27.991649  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5506 23:06:27.992110  ==

 5507 23:06:27.998517  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5508 23:06:28.005183  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5509 23:06:28.008819  [CA 0] Center 37 (6~68) winsize 63

 5510 23:06:28.011856  [CA 1] Center 37 (6~68) winsize 63

 5511 23:06:28.014978  [CA 2] Center 35 (5~66) winsize 62

 5512 23:06:28.018629  [CA 3] Center 34 (4~65) winsize 62

 5513 23:06:28.021850  [CA 4] Center 34 (4~65) winsize 62

 5514 23:06:28.024745  [CA 5] Center 33 (3~64) winsize 62

 5515 23:06:28.025221  

 5516 23:06:28.028352  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5517 23:06:28.028880  

 5518 23:06:28.031648  [CATrainingPosCal] consider 2 rank data

 5519 23:06:28.035145  u2DelayCellTimex100 = 270/100 ps

 5520 23:06:28.038537  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5521 23:06:28.041783  CA1 delay=37 (6~68),Diff = 4 PI (24 cell)

 5522 23:06:28.044715  CA2 delay=35 (5~65),Diff = 2 PI (12 cell)

 5523 23:06:28.048084  CA3 delay=34 (4~64),Diff = 1 PI (6 cell)

 5524 23:06:28.051476  CA4 delay=34 (4~64),Diff = 1 PI (6 cell)

 5525 23:06:28.058063  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5526 23:06:28.058484  

 5527 23:06:28.061555  CA PerBit enable=1, Macro0, CA PI delay=33

 5528 23:06:28.062028  

 5529 23:06:28.065048  [CBTSetCACLKResult] CA Dly = 33

 5530 23:06:28.065561  CS Dly: 8 (0~40)

 5531 23:06:28.066005  

 5532 23:06:28.068526  ----->DramcWriteLeveling(PI) begin...

 5533 23:06:28.069050  ==

 5534 23:06:28.072010  Dram Type= 6, Freq= 0, CH_1, rank 0

 5535 23:06:28.075184  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5536 23:06:28.078495  ==

 5537 23:06:28.079014  Write leveling (Byte 0): 28 => 28

 5538 23:06:28.081825  Write leveling (Byte 1): 29 => 29

 5539 23:06:28.084906  DramcWriteLeveling(PI) end<-----

 5540 23:06:28.085456  

 5541 23:06:28.085908  ==

 5542 23:06:28.088970  Dram Type= 6, Freq= 0, CH_1, rank 0

 5543 23:06:28.095003  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5544 23:06:28.095515  ==

 5545 23:06:28.098709  [Gating] SW mode calibration

 5546 23:06:28.104926  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5547 23:06:28.108313  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5548 23:06:28.115239   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5549 23:06:28.118436   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5550 23:06:28.121363   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5551 23:06:28.128236   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5552 23:06:28.131612   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5553 23:06:28.135149   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5554 23:06:28.141730   0 14 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)

 5555 23:06:28.144416   0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)

 5556 23:06:28.148010   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5557 23:06:28.151471   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5558 23:06:28.158239   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5559 23:06:28.161647   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5560 23:06:28.164371   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5561 23:06:28.171366   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5562 23:06:28.174624   0 15 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

 5563 23:06:28.178016   0 15 28 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)

 5564 23:06:28.185140   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5565 23:06:28.187814   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5566 23:06:28.191299   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5567 23:06:28.198267   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5568 23:06:28.201273   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5569 23:06:28.204382   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5570 23:06:28.211286   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5571 23:06:28.214310   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5572 23:06:28.217828   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5573 23:06:28.224572   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5574 23:06:28.227374   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5575 23:06:28.230730   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5576 23:06:28.237679   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5577 23:06:28.241023   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5578 23:06:28.244750   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5579 23:06:28.250801   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5580 23:06:28.254295   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5581 23:06:28.257431   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5582 23:06:28.264625   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5583 23:06:28.267316   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5584 23:06:28.270724   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5585 23:06:28.277256   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5586 23:06:28.281104   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5587 23:06:28.284157   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 5588 23:06:28.287575  Total UI for P1: 0, mck2ui 16

 5589 23:06:28.290981  best dqsien dly found for B1: ( 1,  2, 24)

 5590 23:06:28.293933   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5591 23:06:28.297391  Total UI for P1: 0, mck2ui 16

 5592 23:06:28.300691  best dqsien dly found for B0: ( 1,  2, 26)

 5593 23:06:28.304258  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5594 23:06:28.310752  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5595 23:06:28.311265  

 5596 23:06:28.314149  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5597 23:06:28.317776  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5598 23:06:28.320716  [Gating] SW calibration Done

 5599 23:06:28.321271  ==

 5600 23:06:28.324109  Dram Type= 6, Freq= 0, CH_1, rank 0

 5601 23:06:28.327462  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5602 23:06:28.327976  ==

 5603 23:06:28.328306  RX Vref Scan: 0

 5604 23:06:28.330527  

 5605 23:06:28.330938  RX Vref 0 -> 0, step: 1

 5606 23:06:28.331267  

 5607 23:06:28.334090  RX Delay -80 -> 252, step: 8

 5608 23:06:28.336970  iDelay=208, Bit 0, Center 111 (24 ~ 199) 176

 5609 23:06:28.340435  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5610 23:06:28.347260  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5611 23:06:28.350262  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5612 23:06:28.353646  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5613 23:06:28.357255  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5614 23:06:28.360514  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5615 23:06:28.363655  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5616 23:06:28.370481  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5617 23:06:28.373554  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5618 23:06:28.376702  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5619 23:06:28.380740  iDelay=208, Bit 11, Center 95 (8 ~ 183) 176

 5620 23:06:28.383639  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5621 23:06:28.387175  iDelay=208, Bit 13, Center 107 (24 ~ 191) 168

 5622 23:06:28.393526  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5623 23:06:28.397093  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5624 23:06:28.397613  ==

 5625 23:06:28.400071  Dram Type= 6, Freq= 0, CH_1, rank 0

 5626 23:06:28.403829  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5627 23:06:28.404395  ==

 5628 23:06:28.407339  DQS Delay:

 5629 23:06:28.407893  DQS0 = 0, DQS1 = 0

 5630 23:06:28.408257  DQM Delay:

 5631 23:06:28.410005  DQM0 = 103, DQM1 = 99

 5632 23:06:28.410465  DQ Delay:

 5633 23:06:28.413769  DQ0 =111, DQ1 =95, DQ2 =91, DQ3 =99

 5634 23:06:28.416737  DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103

 5635 23:06:28.420350  DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95

 5636 23:06:28.423473  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5637 23:06:28.426671  

 5638 23:06:28.427223  

 5639 23:06:28.427588  ==

 5640 23:06:28.430344  Dram Type= 6, Freq= 0, CH_1, rank 0

 5641 23:06:28.433448  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5642 23:06:28.434042  ==

 5643 23:06:28.434413  

 5644 23:06:28.434743  

 5645 23:06:28.436745  	TX Vref Scan disable

 5646 23:06:28.437297   == TX Byte 0 ==

 5647 23:06:28.443067  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5648 23:06:28.446663  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5649 23:06:28.447414   == TX Byte 1 ==

 5650 23:06:28.453503  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5651 23:06:28.456523  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5652 23:06:28.456978  ==

 5653 23:06:28.460198  Dram Type= 6, Freq= 0, CH_1, rank 0

 5654 23:06:28.463311  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5655 23:06:28.463772  ==

 5656 23:06:28.464133  

 5657 23:06:28.464465  

 5658 23:06:28.466531  	TX Vref Scan disable

 5659 23:06:28.469859   == TX Byte 0 ==

 5660 23:06:28.473377  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5661 23:06:28.476348  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5662 23:06:28.480086   == TX Byte 1 ==

 5663 23:06:28.483085  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5664 23:06:28.486259  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5665 23:06:28.486719  

 5666 23:06:28.489777  [DATLAT]

 5667 23:06:28.490208  Freq=933, CH1 RK0

 5668 23:06:28.490539  

 5669 23:06:28.492976  DATLAT Default: 0xd

 5670 23:06:28.493484  0, 0xFFFF, sum = 0

 5671 23:06:28.496848  1, 0xFFFF, sum = 0

 5672 23:06:28.497392  2, 0xFFFF, sum = 0

 5673 23:06:28.499766  3, 0xFFFF, sum = 0

 5674 23:06:28.500280  4, 0xFFFF, sum = 0

 5675 23:06:28.503333  5, 0xFFFF, sum = 0

 5676 23:06:28.503870  6, 0xFFFF, sum = 0

 5677 23:06:28.506871  7, 0xFFFF, sum = 0

 5678 23:06:28.507433  8, 0xFFFF, sum = 0

 5679 23:06:28.510072  9, 0xFFFF, sum = 0

 5680 23:06:28.510634  10, 0x0, sum = 1

 5681 23:06:28.513049  11, 0x0, sum = 2

 5682 23:06:28.513655  12, 0x0, sum = 3

 5683 23:06:28.516605  13, 0x0, sum = 4

 5684 23:06:28.517194  best_step = 11

 5685 23:06:28.517640  

 5686 23:06:28.518005  ==

 5687 23:06:28.520016  Dram Type= 6, Freq= 0, CH_1, rank 0

 5688 23:06:28.526404  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5689 23:06:28.526963  ==

 5690 23:06:28.527326  RX Vref Scan: 1

 5691 23:06:28.527664  

 5692 23:06:28.529849  RX Vref 0 -> 0, step: 1

 5693 23:06:28.530403  

 5694 23:06:28.532922  RX Delay -45 -> 252, step: 4

 5695 23:06:28.533475  

 5696 23:06:28.536421  Set Vref, RX VrefLevel [Byte0]: 53

 5697 23:06:28.539959                           [Byte1]: 51

 5698 23:06:28.540530  

 5699 23:06:28.542863  Final RX Vref Byte 0 = 53 to rank0

 5700 23:06:28.546589  Final RX Vref Byte 1 = 51 to rank0

 5701 23:06:28.550044  Final RX Vref Byte 0 = 53 to rank1

 5702 23:06:28.552595  Final RX Vref Byte 1 = 51 to rank1==

 5703 23:06:28.556021  Dram Type= 6, Freq= 0, CH_1, rank 0

 5704 23:06:28.559788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5705 23:06:28.560380  ==

 5706 23:06:28.563051  DQS Delay:

 5707 23:06:28.563505  DQS0 = 0, DQS1 = 0

 5708 23:06:28.563862  DQM Delay:

 5709 23:06:28.565926  DQM0 = 103, DQM1 = 99

 5710 23:06:28.566381  DQ Delay:

 5711 23:06:28.569761  DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =100

 5712 23:06:28.573100  DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102

 5713 23:06:28.576236  DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92

 5714 23:06:28.579777  DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106

 5715 23:06:28.582446  

 5716 23:06:28.582898  

 5717 23:06:28.589666  [DQSOSCAuto] RK0, (LSB)MR18= 0x162e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps

 5718 23:06:28.592412  CH1 RK0: MR19=505, MR18=162E

 5719 23:06:28.599428  CH1_RK0: MR19=0x505, MR18=0x162E, DQSOSC=407, MR23=63, INC=65, DEC=43

 5720 23:06:28.599943  

 5721 23:06:28.602763  ----->DramcWriteLeveling(PI) begin...

 5722 23:06:28.603288  ==

 5723 23:06:28.605707  Dram Type= 6, Freq= 0, CH_1, rank 1

 5724 23:06:28.609192  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5725 23:06:28.609638  ==

 5726 23:06:28.612352  Write leveling (Byte 0): 26 => 26

 5727 23:06:28.616112  Write leveling (Byte 1): 27 => 27

 5728 23:06:28.619401  DramcWriteLeveling(PI) end<-----

 5729 23:06:28.619815  

 5730 23:06:28.620139  ==

 5731 23:06:28.622261  Dram Type= 6, Freq= 0, CH_1, rank 1

 5732 23:06:28.625716  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5733 23:06:28.626229  ==

 5734 23:06:28.628945  [Gating] SW mode calibration

 5735 23:06:28.635897  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5736 23:06:28.642295  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5737 23:06:28.645569   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5738 23:06:28.651788   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5739 23:06:28.655284   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5740 23:06:28.658755   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5741 23:06:28.662521   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5742 23:06:28.668914   0 14 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 5743 23:06:28.672582   0 14 24 | B1->B0 | 2d2d 2f2f | 1 1 | (1 0) (1 0)

 5744 23:06:28.675049   0 14 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 5745 23:06:28.682166   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 5746 23:06:28.685762   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5747 23:06:28.688560   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5748 23:06:28.695701   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5749 23:06:28.698695   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5750 23:06:28.702031   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5751 23:06:28.709167   0 15 24 | B1->B0 | 3737 2c2c | 0 0 | (0 0) (1 1)

 5752 23:06:28.711708   0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)

 5753 23:06:28.715193   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5754 23:06:28.721867   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5755 23:06:28.725169   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5756 23:06:28.728797   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5757 23:06:28.735194   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5758 23:06:28.738515   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5759 23:06:28.741927   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5760 23:06:28.748507   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5761 23:06:28.751823   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5762 23:06:28.755188   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5763 23:06:28.762041   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5764 23:06:28.765115   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5765 23:06:28.768558   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5766 23:06:28.775501   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5767 23:06:28.778215   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5768 23:06:28.781662   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5769 23:06:28.788455   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5770 23:06:28.791842   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5771 23:06:28.795310   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5772 23:06:28.798272   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5773 23:06:28.804952   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5774 23:06:28.808467   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5775 23:06:28.811418   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5776 23:06:28.818488   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5777 23:06:28.821657   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5778 23:06:28.824785  Total UI for P1: 0, mck2ui 16

 5779 23:06:28.828342  best dqsien dly found for B0: ( 1,  2, 26)

 5780 23:06:28.831703  Total UI for P1: 0, mck2ui 16

 5781 23:06:28.835036  best dqsien dly found for B1: ( 1,  2, 26)

 5782 23:06:28.838161  best DQS0 dly(MCK, UI, PI) = (1, 2, 26)

 5783 23:06:28.841517  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5784 23:06:28.842131  

 5785 23:06:28.844994  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5786 23:06:28.848227  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5787 23:06:28.851266  [Gating] SW calibration Done

 5788 23:06:28.851722  ==

 5789 23:06:28.854940  Dram Type= 6, Freq= 0, CH_1, rank 1

 5790 23:06:28.861751  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5791 23:06:28.862302  ==

 5792 23:06:28.862663  RX Vref Scan: 0

 5793 23:06:28.863000  

 5794 23:06:28.865129  RX Vref 0 -> 0, step: 1

 5795 23:06:28.865745  

 5796 23:06:28.867780  RX Delay -80 -> 252, step: 8

 5797 23:06:28.871594  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5798 23:06:28.874539  iDelay=208, Bit 1, Center 103 (16 ~ 191) 176

 5799 23:06:28.877959  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5800 23:06:28.881376  iDelay=208, Bit 3, Center 103 (16 ~ 191) 176

 5801 23:06:28.887745  iDelay=208, Bit 4, Center 95 (8 ~ 183) 176

 5802 23:06:28.891268  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5803 23:06:28.894233  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5804 23:06:28.897879  iDelay=208, Bit 7, Center 103 (16 ~ 191) 176

 5805 23:06:28.900965  iDelay=208, Bit 8, Center 91 (0 ~ 183) 184

 5806 23:06:28.907969  iDelay=208, Bit 9, Center 91 (0 ~ 183) 184

 5807 23:06:28.910861  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5808 23:06:28.914525  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5809 23:06:28.917470  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5810 23:06:28.920924  iDelay=208, Bit 13, Center 103 (16 ~ 191) 176

 5811 23:06:28.927266  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5812 23:06:28.930982  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5813 23:06:28.931537  ==

 5814 23:06:28.934076  Dram Type= 6, Freq= 0, CH_1, rank 1

 5815 23:06:28.937411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5816 23:06:28.938003  ==

 5817 23:06:28.940788  DQS Delay:

 5818 23:06:28.941340  DQS0 = 0, DQS1 = 0

 5819 23:06:28.941762  DQM Delay:

 5820 23:06:28.944369  DQM0 = 104, DQM1 = 99

 5821 23:06:28.944919  DQ Delay:

 5822 23:06:28.947305  DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103

 5823 23:06:28.950435  DQ4 =95, DQ5 =115, DQ6 =115, DQ7 =103

 5824 23:06:28.954119  DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91

 5825 23:06:28.957138  DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107

 5826 23:06:28.957641  

 5827 23:06:28.958016  

 5828 23:06:28.960900  ==

 5829 23:06:28.963673  Dram Type= 6, Freq= 0, CH_1, rank 1

 5830 23:06:28.967382  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5831 23:06:28.967944  ==

 5832 23:06:28.968304  

 5833 23:06:28.968637  

 5834 23:06:28.970639  	TX Vref Scan disable

 5835 23:06:28.971094   == TX Byte 0 ==

 5836 23:06:28.974007  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5837 23:06:28.980984  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5838 23:06:28.981535   == TX Byte 1 ==

 5839 23:06:28.984052  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5840 23:06:28.990405  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5841 23:06:28.990965  ==

 5842 23:06:28.993991  Dram Type= 6, Freq= 0, CH_1, rank 1

 5843 23:06:28.997209  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5844 23:06:28.998007  ==

 5845 23:06:28.998397  

 5846 23:06:28.998868  

 5847 23:06:29.000630  	TX Vref Scan disable

 5848 23:06:29.004057   == TX Byte 0 ==

 5849 23:06:29.007555  Update DQ  dly =710 (2 ,5, 38)  DQ  OEN =(2 ,2)

 5850 23:06:29.010474  Update DQM dly =710 (2 ,5, 38)  DQM OEN =(2 ,2)

 5851 23:06:29.014052   == TX Byte 1 ==

 5852 23:06:29.017189  Update DQ  dly =708 (2 ,5, 36)  DQ  OEN =(2 ,2)

 5853 23:06:29.020580  Update DQM dly =708 (2 ,5, 36)  DQM OEN =(2 ,2)

 5854 23:06:29.021134  

 5855 23:06:29.021496  [DATLAT]

 5856 23:06:29.024325  Freq=933, CH1 RK1

 5857 23:06:29.024881  

 5858 23:06:29.027014  DATLAT Default: 0xb

 5859 23:06:29.027470  0, 0xFFFF, sum = 0

 5860 23:06:29.030176  1, 0xFFFF, sum = 0

 5861 23:06:29.030661  2, 0xFFFF, sum = 0

 5862 23:06:29.034064  3, 0xFFFF, sum = 0

 5863 23:06:29.034622  4, 0xFFFF, sum = 0

 5864 23:06:29.037457  5, 0xFFFF, sum = 0

 5865 23:06:29.038181  6, 0xFFFF, sum = 0

 5866 23:06:29.040430  7, 0xFFFF, sum = 0

 5867 23:06:29.040944  8, 0xFFFF, sum = 0

 5868 23:06:29.043678  9, 0xFFFF, sum = 0

 5869 23:06:29.044455  10, 0x0, sum = 1

 5870 23:06:29.047108  11, 0x0, sum = 2

 5871 23:06:29.047713  12, 0x0, sum = 3

 5872 23:06:29.049923  13, 0x0, sum = 4

 5873 23:06:29.050423  best_step = 11

 5874 23:06:29.050782  

 5875 23:06:29.051410  ==

 5876 23:06:29.053668  Dram Type= 6, Freq= 0, CH_1, rank 1

 5877 23:06:29.056842  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5878 23:06:29.059960  ==

 5879 23:06:29.060636  RX Vref Scan: 0

 5880 23:06:29.061152  

 5881 23:06:29.063368  RX Vref 0 -> 0, step: 1

 5882 23:06:29.063977  

 5883 23:06:29.064506  RX Delay -45 -> 252, step: 4

 5884 23:06:29.071001  iDelay=203, Bit 0, Center 108 (27 ~ 190) 164

 5885 23:06:29.074524  iDelay=203, Bit 1, Center 100 (19 ~ 182) 164

 5886 23:06:29.078020  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5887 23:06:29.081238  iDelay=203, Bit 3, Center 100 (19 ~ 182) 164

 5888 23:06:29.085005  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5889 23:06:29.091411  iDelay=203, Bit 5, Center 118 (35 ~ 202) 168

 5890 23:06:29.094804  iDelay=203, Bit 6, Center 114 (31 ~ 198) 168

 5891 23:06:29.098178  iDelay=203, Bit 7, Center 102 (19 ~ 186) 168

 5892 23:06:29.101551  iDelay=203, Bit 8, Center 92 (11 ~ 174) 164

 5893 23:06:29.105159  iDelay=203, Bit 9, Center 90 (7 ~ 174) 168

 5894 23:06:29.111720  iDelay=203, Bit 10, Center 100 (15 ~ 186) 172

 5895 23:06:29.114841  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5896 23:06:29.118264  iDelay=203, Bit 12, Center 108 (19 ~ 198) 180

 5897 23:06:29.121952  iDelay=203, Bit 13, Center 104 (19 ~ 190) 172

 5898 23:06:29.124859  iDelay=203, Bit 14, Center 102 (19 ~ 186) 168

 5899 23:06:29.131430  iDelay=203, Bit 15, Center 108 (23 ~ 194) 172

 5900 23:06:29.131993  ==

 5901 23:06:29.134905  Dram Type= 6, Freq= 0, CH_1, rank 1

 5902 23:06:29.138636  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5903 23:06:29.139199  ==

 5904 23:06:29.139565  DQS Delay:

 5905 23:06:29.141501  DQS0 = 0, DQS1 = 0

 5906 23:06:29.142095  DQM Delay:

 5907 23:06:29.144890  DQM0 = 104, DQM1 = 99

 5908 23:06:29.145349  DQ Delay:

 5909 23:06:29.148073  DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100

 5910 23:06:29.151239  DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102

 5911 23:06:29.155159  DQ8 =92, DQ9 =90, DQ10 =100, DQ11 =94

 5912 23:06:29.157745  DQ12 =108, DQ13 =104, DQ14 =102, DQ15 =108

 5913 23:06:29.158205  

 5914 23:06:29.158566  

 5915 23:06:29.168032  [DQSOSCAuto] RK1, (LSB)MR18= 0x2d00, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 407 ps

 5916 23:06:29.171472  CH1 RK1: MR19=505, MR18=2D00

 5917 23:06:29.174154  CH1_RK1: MR19=0x505, MR18=0x2D00, DQSOSC=407, MR23=63, INC=65, DEC=43

 5918 23:06:29.177866  [RxdqsGatingPostProcess] freq 933

 5919 23:06:29.184331  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5920 23:06:29.187655  best DQS0 dly(2T, 0.5T) = (0, 10)

 5921 23:06:29.191092  best DQS1 dly(2T, 0.5T) = (0, 10)

 5922 23:06:29.194602  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5923 23:06:29.197456  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5924 23:06:29.201259  best DQS0 dly(2T, 0.5T) = (0, 10)

 5925 23:06:29.204628  best DQS1 dly(2T, 0.5T) = (0, 10)

 5926 23:06:29.207592  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5927 23:06:29.211172  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5928 23:06:29.211586  Pre-setting of DQS Precalculation

 5929 23:06:29.218180  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5930 23:06:29.224675  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5931 23:06:29.231029  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5932 23:06:29.231478  

 5933 23:06:29.231806  

 5934 23:06:29.234951  [Calibration Summary] 1866 Mbps

 5935 23:06:29.238001  CH 0, Rank 0

 5936 23:06:29.238527  SW Impedance     : PASS

 5937 23:06:29.241400  DUTY Scan        : NO K

 5938 23:06:29.244500  ZQ Calibration   : PASS

 5939 23:06:29.245020  Jitter Meter     : NO K

 5940 23:06:29.248201  CBT Training     : PASS

 5941 23:06:29.248738  Write leveling   : PASS

 5942 23:06:29.251261  RX DQS gating    : PASS

 5943 23:06:29.254233  RX DQ/DQS(RDDQC) : PASS

 5944 23:06:29.254647  TX DQ/DQS        : PASS

 5945 23:06:29.257822  RX DATLAT        : PASS

 5946 23:06:29.261398  RX DQ/DQS(Engine): PASS

 5947 23:06:29.262010  TX OE            : NO K

 5948 23:06:29.264797  All Pass.

 5949 23:06:29.265343  

 5950 23:06:29.265756  CH 0, Rank 1

 5951 23:06:29.268274  SW Impedance     : PASS

 5952 23:06:29.268835  DUTY Scan        : NO K

 5953 23:06:29.270826  ZQ Calibration   : PASS

 5954 23:06:29.274264  Jitter Meter     : NO K

 5955 23:06:29.274681  CBT Training     : PASS

 5956 23:06:29.277386  Write leveling   : PASS

 5957 23:06:29.281020  RX DQS gating    : PASS

 5958 23:06:29.281541  RX DQ/DQS(RDDQC) : PASS

 5959 23:06:29.284573  TX DQ/DQS        : PASS

 5960 23:06:29.287790  RX DATLAT        : PASS

 5961 23:06:29.288218  RX DQ/DQS(Engine): PASS

 5962 23:06:29.291034  TX OE            : NO K

 5963 23:06:29.291455  All Pass.

 5964 23:06:29.291967  

 5965 23:06:29.294237  CH 1, Rank 0

 5966 23:06:29.294652  SW Impedance     : PASS

 5967 23:06:29.297467  DUTY Scan        : NO K

 5968 23:06:29.300861  ZQ Calibration   : PASS

 5969 23:06:29.301281  Jitter Meter     : NO K

 5970 23:06:29.304331  CBT Training     : PASS

 5971 23:06:29.304853  Write leveling   : PASS

 5972 23:06:29.308008  RX DQS gating    : PASS

 5973 23:06:29.310617  RX DQ/DQS(RDDQC) : PASS

 5974 23:06:29.311035  TX DQ/DQS        : PASS

 5975 23:06:29.314257  RX DATLAT        : PASS

 5976 23:06:29.317523  RX DQ/DQS(Engine): PASS

 5977 23:06:29.318220  TX OE            : NO K

 5978 23:06:29.320968  All Pass.

 5979 23:06:29.321489  

 5980 23:06:29.321893  CH 1, Rank 1

 5981 23:06:29.324674  SW Impedance     : PASS

 5982 23:06:29.325206  DUTY Scan        : NO K

 5983 23:06:29.327437  ZQ Calibration   : PASS

 5984 23:06:29.330626  Jitter Meter     : NO K

 5985 23:06:29.331147  CBT Training     : PASS

 5986 23:06:29.334167  Write leveling   : PASS

 5987 23:06:29.337679  RX DQS gating    : PASS

 5988 23:06:29.338198  RX DQ/DQS(RDDQC) : PASS

 5989 23:06:29.340843  TX DQ/DQS        : PASS

 5990 23:06:29.344126  RX DATLAT        : PASS

 5991 23:06:29.344645  RX DQ/DQS(Engine): PASS

 5992 23:06:29.347842  TX OE            : NO K

 5993 23:06:29.348368  All Pass.

 5994 23:06:29.348702  

 5995 23:06:29.350454  DramC Write-DBI off

 5996 23:06:29.353990  	PER_BANK_REFRESH: Hybrid Mode

 5997 23:06:29.354407  TX_TRACKING: ON

 5998 23:06:29.363557  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 5999 23:06:29.367405  [FAST_K] Save calibration result to emmc

 6000 23:06:29.370453  dramc_set_vcore_voltage set vcore to 650000

 6001 23:06:29.374171  Read voltage for 400, 6

 6002 23:06:29.374690  Vio18 = 0

 6003 23:06:29.375027  Vcore = 650000

 6004 23:06:29.377145  Vdram = 0

 6005 23:06:29.377705  Vddq = 0

 6006 23:06:29.378060  Vmddr = 0

 6007 23:06:29.383665  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6008 23:06:29.386886  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6009 23:06:29.390092  MEM_TYPE=3, freq_sel=20

 6010 23:06:29.393797  sv_algorithm_assistance_LP4_800 

 6011 23:06:29.396663  ============ PULL DRAM RESETB DOWN ============

 6012 23:06:29.400246  ========== PULL DRAM RESETB DOWN end =========

 6013 23:06:29.406686  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6014 23:06:29.410233  =================================== 

 6015 23:06:29.410832  LPDDR4 DRAM CONFIGURATION

 6016 23:06:29.413339  =================================== 

 6017 23:06:29.417033  EX_ROW_EN[0]    = 0x0

 6018 23:06:29.420403  EX_ROW_EN[1]    = 0x0

 6019 23:06:29.420966  LP4Y_EN      = 0x0

 6020 23:06:29.423417  WORK_FSP     = 0x0

 6021 23:06:29.423875  WL           = 0x2

 6022 23:06:29.427435  RL           = 0x2

 6023 23:06:29.428059  BL           = 0x2

 6024 23:06:29.430004  RPST         = 0x0

 6025 23:06:29.430458  RD_PRE       = 0x0

 6026 23:06:29.433816  WR_PRE       = 0x1

 6027 23:06:29.434329  WR_PST       = 0x0

 6028 23:06:29.436858  DBI_WR       = 0x0

 6029 23:06:29.437414  DBI_RD       = 0x0

 6030 23:06:29.440289  OTF          = 0x1

 6031 23:06:29.443260  =================================== 

 6032 23:06:29.446551  =================================== 

 6033 23:06:29.447217  ANA top config

 6034 23:06:29.449879  =================================== 

 6035 23:06:29.453407  DLL_ASYNC_EN            =  0

 6036 23:06:29.456463  ALL_SLAVE_EN            =  1

 6037 23:06:29.460170  NEW_RANK_MODE           =  1

 6038 23:06:29.460630  DLL_IDLE_MODE           =  1

 6039 23:06:29.462977  LP45_APHY_COMB_EN       =  1

 6040 23:06:29.466470  TX_ODT_DIS              =  1

 6041 23:06:29.470248  NEW_8X_MODE             =  1

 6042 23:06:29.473298  =================================== 

 6043 23:06:29.476321  =================================== 

 6044 23:06:29.480096  data_rate                  =  800

 6045 23:06:29.480626  CKR                        = 1

 6046 23:06:29.482796  DQ_P2S_RATIO               = 4

 6047 23:06:29.486397  =================================== 

 6048 23:06:29.489895  CA_P2S_RATIO               = 4

 6049 23:06:29.492846  DQ_CA_OPEN                 = 0

 6050 23:06:29.496189  DQ_SEMI_OPEN               = 1

 6051 23:06:29.499943  CA_SEMI_OPEN               = 1

 6052 23:06:29.500512  CA_FULL_RATE               = 0

 6053 23:06:29.503126  DQ_CKDIV4_EN               = 0

 6054 23:06:29.506659  CA_CKDIV4_EN               = 1

 6055 23:06:29.509958  CA_PREDIV_EN               = 0

 6056 23:06:29.512620  PH8_DLY                    = 0

 6057 23:06:29.516068  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6058 23:06:29.516477  DQ_AAMCK_DIV               = 0

 6059 23:06:29.519909  CA_AAMCK_DIV               = 0

 6060 23:06:29.522854  CA_ADMCK_DIV               = 4

 6061 23:06:29.526070  DQ_TRACK_CA_EN             = 0

 6062 23:06:29.530003  CA_PICK                    = 800

 6063 23:06:29.533006  CA_MCKIO                   = 400

 6064 23:06:29.533525  MCKIO_SEMI                 = 400

 6065 23:06:29.536276  PLL_FREQ                   = 3016

 6066 23:06:29.539504  DQ_UI_PI_RATIO             = 32

 6067 23:06:29.543255  CA_UI_PI_RATIO             = 32

 6068 23:06:29.546669  =================================== 

 6069 23:06:29.549750  =================================== 

 6070 23:06:29.552967  memory_type:LPDDR4         

 6071 23:06:29.553382  GP_NUM     : 10       

 6072 23:06:29.556478  SRAM_EN    : 1       

 6073 23:06:29.559455  MD32_EN    : 0       

 6074 23:06:29.562859  =================================== 

 6075 23:06:29.563271  [ANA_INIT] >>>>>>>>>>>>>> 

 6076 23:06:29.566247  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6077 23:06:29.569964  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6078 23:06:29.572813  =================================== 

 6079 23:06:29.576548  data_rate = 800,PCW = 0X7400

 6080 23:06:29.579210  =================================== 

 6081 23:06:29.582757  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6082 23:06:29.589317  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6083 23:06:29.599456  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6084 23:06:29.605923  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6085 23:06:29.609410  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6086 23:06:29.612662  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6087 23:06:29.613240  [ANA_INIT] flow start 

 6088 23:06:29.616435  [ANA_INIT] PLL >>>>>>>> 

 6089 23:06:29.619737  [ANA_INIT] PLL <<<<<<<< 

 6090 23:06:29.620356  [ANA_INIT] MIDPI >>>>>>>> 

 6091 23:06:29.622952  [ANA_INIT] MIDPI <<<<<<<< 

 6092 23:06:29.625723  [ANA_INIT] DLL >>>>>>>> 

 6093 23:06:29.626328  [ANA_INIT] flow end 

 6094 23:06:29.632284  ============ LP4 DIFF to SE enter ============

 6095 23:06:29.635954  ============ LP4 DIFF to SE exit  ============

 6096 23:06:29.636439  [ANA_INIT] <<<<<<<<<<<<< 

 6097 23:06:29.639260  [Flow] Enable top DCM control >>>>> 

 6098 23:06:29.642834  [Flow] Enable top DCM control <<<<< 

 6099 23:06:29.646026  Enable DLL master slave shuffle 

 6100 23:06:29.652521  ============================================================== 

 6101 23:06:29.653067  Gating Mode config

 6102 23:06:29.659013  ============================================================== 

 6103 23:06:29.662475  Config description: 

 6104 23:06:29.672513  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6105 23:06:29.679221  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6106 23:06:29.682696  SELPH_MODE            0: By rank         1: By Phase 

 6107 23:06:29.689434  ============================================================== 

 6108 23:06:29.692246  GAT_TRACK_EN                 =  0

 6109 23:06:29.695826  RX_GATING_MODE               =  2

 6110 23:06:29.696239  RX_GATING_TRACK_MODE         =  2

 6111 23:06:29.698804  SELPH_MODE                   =  1

 6112 23:06:29.702653  PICG_EARLY_EN                =  1

 6113 23:06:29.705571  VALID_LAT_VALUE              =  1

 6114 23:06:29.712485  ============================================================== 

 6115 23:06:29.716061  Enter into Gating configuration >>>> 

 6116 23:06:29.719185  Exit from Gating configuration <<<< 

 6117 23:06:29.722098  Enter into  DVFS_PRE_config >>>>> 

 6118 23:06:29.732392  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6119 23:06:29.736001  Exit from  DVFS_PRE_config <<<<< 

 6120 23:06:29.739067  Enter into PICG configuration >>>> 

 6121 23:06:29.742438  Exit from PICG configuration <<<< 

 6122 23:06:29.745710  [RX_INPUT] configuration >>>>> 

 6123 23:06:29.748612  [RX_INPUT] configuration <<<<< 

 6124 23:06:29.751970  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6125 23:06:29.758838  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6126 23:06:29.765468  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6127 23:06:29.771807  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6128 23:06:29.775154  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6129 23:06:29.781694  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6130 23:06:29.788451  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6131 23:06:29.792168  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6132 23:06:29.795170  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6133 23:06:29.798470  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6134 23:06:29.805026  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6135 23:06:29.808290  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6136 23:06:29.811643  =================================== 

 6137 23:06:29.815288  LPDDR4 DRAM CONFIGURATION

 6138 23:06:29.818510  =================================== 

 6139 23:06:29.819074  EX_ROW_EN[0]    = 0x0

 6140 23:06:29.821693  EX_ROW_EN[1]    = 0x0

 6141 23:06:29.822168  LP4Y_EN      = 0x0

 6142 23:06:29.824751  WORK_FSP     = 0x0

 6143 23:06:29.825305  WL           = 0x2

 6144 23:06:29.828410  RL           = 0x2

 6145 23:06:29.829055  BL           = 0x2

 6146 23:06:29.831562  RPST         = 0x0

 6147 23:06:29.832119  RD_PRE       = 0x0

 6148 23:06:29.834508  WR_PRE       = 0x1

 6149 23:06:29.835092  WR_PST       = 0x0

 6150 23:06:29.838188  DBI_WR       = 0x0

 6151 23:06:29.841766  DBI_RD       = 0x0

 6152 23:06:29.842324  OTF          = 0x1

 6153 23:06:29.844871  =================================== 

 6154 23:06:29.848381  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6155 23:06:29.851472  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6156 23:06:29.858137  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6157 23:06:29.861044  =================================== 

 6158 23:06:29.864309  LPDDR4 DRAM CONFIGURATION

 6159 23:06:29.868188  =================================== 

 6160 23:06:29.868740  EX_ROW_EN[0]    = 0x10

 6161 23:06:29.870990  EX_ROW_EN[1]    = 0x0

 6162 23:06:29.871445  LP4Y_EN      = 0x0

 6163 23:06:29.874729  WORK_FSP     = 0x0

 6164 23:06:29.875241  WL           = 0x2

 6165 23:06:29.878500  RL           = 0x2

 6166 23:06:29.879057  BL           = 0x2

 6167 23:06:29.881304  RPST         = 0x0

 6168 23:06:29.881895  RD_PRE       = 0x0

 6169 23:06:29.884951  WR_PRE       = 0x1

 6170 23:06:29.885523  WR_PST       = 0x0

 6171 23:06:29.887949  DBI_WR       = 0x0

 6172 23:06:29.888503  DBI_RD       = 0x0

 6173 23:06:29.891172  OTF          = 0x1

 6174 23:06:29.894654  =================================== 

 6175 23:06:29.901204  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6176 23:06:29.904992  nWR fixed to 30

 6177 23:06:29.908280  [ModeRegInit_LP4] CH0 RK0

 6178 23:06:29.908880  [ModeRegInit_LP4] CH0 RK1

 6179 23:06:29.911466  [ModeRegInit_LP4] CH1 RK0

 6180 23:06:29.914357  [ModeRegInit_LP4] CH1 RK1

 6181 23:06:29.914813  match AC timing 19

 6182 23:06:29.920998  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6183 23:06:29.924488  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6184 23:06:29.927870  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6185 23:06:29.934250  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6186 23:06:29.937967  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6187 23:06:29.938472  ==

 6188 23:06:29.941209  Dram Type= 6, Freq= 0, CH_0, rank 0

 6189 23:06:29.944360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6190 23:06:29.944775  ==

 6191 23:06:29.950695  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6192 23:06:29.957467  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6193 23:06:29.961076  [CA 0] Center 36 (8~64) winsize 57

 6194 23:06:29.964703  [CA 1] Center 36 (8~64) winsize 57

 6195 23:06:29.967446  [CA 2] Center 36 (8~64) winsize 57

 6196 23:06:29.967859  [CA 3] Center 36 (8~64) winsize 57

 6197 23:06:29.971273  [CA 4] Center 36 (8~64) winsize 57

 6198 23:06:29.974130  [CA 5] Center 36 (8~64) winsize 57

 6199 23:06:29.974561  

 6200 23:06:29.977658  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6201 23:06:29.978032  

 6202 23:06:29.984133  [CATrainingPosCal] consider 1 rank data

 6203 23:06:29.984631  u2DelayCellTimex100 = 270/100 ps

 6204 23:06:29.988297  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6205 23:06:29.994316  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6206 23:06:29.997471  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6207 23:06:30.000779  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6208 23:06:30.004657  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6209 23:06:30.007379  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6210 23:06:30.007797  

 6211 23:06:30.011171  CA PerBit enable=1, Macro0, CA PI delay=36

 6212 23:06:30.011686  

 6213 23:06:30.014509  [CBTSetCACLKResult] CA Dly = 36

 6214 23:06:30.017313  CS Dly: 1 (0~32)

 6215 23:06:30.017765  ==

 6216 23:06:30.020788  Dram Type= 6, Freq= 0, CH_0, rank 1

 6217 23:06:30.023855  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6218 23:06:30.024268  ==

 6219 23:06:30.030775  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6220 23:06:30.034081  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6221 23:06:30.037676  [CA 0] Center 36 (8~64) winsize 57

 6222 23:06:30.040809  [CA 1] Center 36 (8~64) winsize 57

 6223 23:06:30.044427  [CA 2] Center 36 (8~64) winsize 57

 6224 23:06:30.047340  [CA 3] Center 36 (8~64) winsize 57

 6225 23:06:30.050786  [CA 4] Center 36 (8~64) winsize 57

 6226 23:06:30.054231  [CA 5] Center 36 (8~64) winsize 57

 6227 23:06:30.054726  

 6228 23:06:30.057925  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6229 23:06:30.058580  

 6230 23:06:30.060813  [CATrainingPosCal] consider 2 rank data

 6231 23:06:30.064033  u2DelayCellTimex100 = 270/100 ps

 6232 23:06:30.067251  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6233 23:06:30.070548  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6234 23:06:30.073931  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6235 23:06:30.080395  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6236 23:06:30.083930  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6237 23:06:30.087045  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6238 23:06:30.087706  

 6239 23:06:30.090571  CA PerBit enable=1, Macro0, CA PI delay=36

 6240 23:06:30.091130  

 6241 23:06:30.093668  [CBTSetCACLKResult] CA Dly = 36

 6242 23:06:30.094381  CS Dly: 1 (0~32)

 6243 23:06:30.094970  

 6244 23:06:30.097311  ----->DramcWriteLeveling(PI) begin...

 6245 23:06:30.097780  ==

 6246 23:06:30.100413  Dram Type= 6, Freq= 0, CH_0, rank 0

 6247 23:06:30.107069  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6248 23:06:30.107633  ==

 6249 23:06:30.110688  Write leveling (Byte 0): 40 => 8

 6250 23:06:30.113485  Write leveling (Byte 1): 40 => 8

 6251 23:06:30.113973  DramcWriteLeveling(PI) end<-----

 6252 23:06:30.114405  

 6253 23:06:30.116845  ==

 6254 23:06:30.120257  Dram Type= 6, Freq= 0, CH_0, rank 0

 6255 23:06:30.124283  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6256 23:06:30.124833  ==

 6257 23:06:30.126927  [Gating] SW mode calibration

 6258 23:06:30.133608  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6259 23:06:30.137467  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6260 23:06:30.143639   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6261 23:06:30.146864   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6262 23:06:30.150487   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6263 23:06:30.156870   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6264 23:06:30.160305   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6265 23:06:30.163836   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6266 23:06:30.170823   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6267 23:06:30.173488   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6268 23:06:30.176624   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6269 23:06:30.180253  Total UI for P1: 0, mck2ui 16

 6270 23:06:30.183639  best dqsien dly found for B0: ( 0, 14, 24)

 6271 23:06:30.186549  Total UI for P1: 0, mck2ui 16

 6272 23:06:30.190083  best dqsien dly found for B1: ( 0, 14, 24)

 6273 23:06:30.193155  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6274 23:06:30.196696  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6275 23:06:30.197120  

 6276 23:06:30.203449  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6277 23:06:30.206470  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6278 23:06:30.209913  [Gating] SW calibration Done

 6279 23:06:30.210328  ==

 6280 23:06:30.213269  Dram Type= 6, Freq= 0, CH_0, rank 0

 6281 23:06:30.216685  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6282 23:06:30.217166  ==

 6283 23:06:30.217498  RX Vref Scan: 0

 6284 23:06:30.217855  

 6285 23:06:30.220071  RX Vref 0 -> 0, step: 1

 6286 23:06:30.220577  

 6287 23:06:30.222812  RX Delay -410 -> 252, step: 16

 6288 23:06:30.226199  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6289 23:06:30.232907  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6290 23:06:30.236492  iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480

 6291 23:06:30.239608  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6292 23:06:30.243072  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6293 23:06:30.249659  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6294 23:06:30.252493  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6295 23:06:30.256107  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6296 23:06:30.259561  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6297 23:06:30.262638  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6298 23:06:30.269275  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6299 23:06:30.272731  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6300 23:06:30.276088  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6301 23:06:30.282253  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6302 23:06:30.285737  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6303 23:06:30.288996  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6304 23:06:30.289502  ==

 6305 23:06:30.292624  Dram Type= 6, Freq= 0, CH_0, rank 0

 6306 23:06:30.295771  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6307 23:06:30.298971  ==

 6308 23:06:30.299481  DQS Delay:

 6309 23:06:30.299928  DQS0 = 27, DQS1 = 35

 6310 23:06:30.302370  DQM Delay:

 6311 23:06:30.302779  DQM0 = 10, DQM1 = 11

 6312 23:06:30.305892  DQ Delay:

 6313 23:06:30.306302  DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8

 6314 23:06:30.309498  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =24

 6315 23:06:30.312363  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6316 23:06:30.316156  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6317 23:06:30.316598  

 6318 23:06:30.316921  

 6319 23:06:30.319247  ==

 6320 23:06:30.319758  Dram Type= 6, Freq= 0, CH_0, rank 0

 6321 23:06:30.326151  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6322 23:06:30.326628  ==

 6323 23:06:30.326957  

 6324 23:06:30.327254  

 6325 23:06:30.329047  	TX Vref Scan disable

 6326 23:06:30.329455   == TX Byte 0 ==

 6327 23:06:30.332779  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6328 23:06:30.338896  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6329 23:06:30.339395   == TX Byte 1 ==

 6330 23:06:30.342606  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6331 23:06:30.345736  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6332 23:06:30.349391  ==

 6333 23:06:30.352534  Dram Type= 6, Freq= 0, CH_0, rank 0

 6334 23:06:30.355585  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6335 23:06:30.355994  ==

 6336 23:06:30.356315  

 6337 23:06:30.356614  

 6338 23:06:30.359154  	TX Vref Scan disable

 6339 23:06:30.359563   == TX Byte 0 ==

 6340 23:06:30.362131  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6341 23:06:30.369507  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6342 23:06:30.370060   == TX Byte 1 ==

 6343 23:06:30.372425  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6344 23:06:30.375719  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6345 23:06:30.379076  

 6346 23:06:30.379629  [DATLAT]

 6347 23:06:30.379964  Freq=400, CH0 RK0

 6348 23:06:30.380268  

 6349 23:06:30.382467  DATLAT Default: 0xf

 6350 23:06:30.382877  0, 0xFFFF, sum = 0

 6351 23:06:30.385650  1, 0xFFFF, sum = 0

 6352 23:06:30.386068  2, 0xFFFF, sum = 0

 6353 23:06:30.388964  3, 0xFFFF, sum = 0

 6354 23:06:30.389377  4, 0xFFFF, sum = 0

 6355 23:06:30.392202  5, 0xFFFF, sum = 0

 6356 23:06:30.395554  6, 0xFFFF, sum = 0

 6357 23:06:30.395972  7, 0xFFFF, sum = 0

 6358 23:06:30.399057  8, 0xFFFF, sum = 0

 6359 23:06:30.399477  9, 0xFFFF, sum = 0

 6360 23:06:30.402218  10, 0xFFFF, sum = 0

 6361 23:06:30.402713  11, 0xFFFF, sum = 0

 6362 23:06:30.405271  12, 0xFFFF, sum = 0

 6363 23:06:30.405722  13, 0x0, sum = 1

 6364 23:06:30.408744  14, 0x0, sum = 2

 6365 23:06:30.409157  15, 0x0, sum = 3

 6366 23:06:30.412119  16, 0x0, sum = 4

 6367 23:06:30.412536  best_step = 14

 6368 23:06:30.412857  

 6369 23:06:30.413158  ==

 6370 23:06:30.415674  Dram Type= 6, Freq= 0, CH_0, rank 0

 6371 23:06:30.418917  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6372 23:06:30.419432  ==

 6373 23:06:30.422291  RX Vref Scan: 1

 6374 23:06:30.422702  

 6375 23:06:30.425526  RX Vref 0 -> 0, step: 1

 6376 23:06:30.425998  

 6377 23:06:30.426345  RX Delay -311 -> 252, step: 8

 6378 23:06:30.428717  

 6379 23:06:30.429278  Set Vref, RX VrefLevel [Byte0]: 53

 6380 23:06:30.432182                           [Byte1]: 46

 6381 23:06:30.437626  

 6382 23:06:30.438147  Final RX Vref Byte 0 = 53 to rank0

 6383 23:06:30.441378  Final RX Vref Byte 1 = 46 to rank0

 6384 23:06:30.444234  Final RX Vref Byte 0 = 53 to rank1

 6385 23:06:30.447904  Final RX Vref Byte 1 = 46 to rank1==

 6386 23:06:30.450493  Dram Type= 6, Freq= 0, CH_0, rank 0

 6387 23:06:30.457509  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6388 23:06:30.458077  ==

 6389 23:06:30.458415  DQS Delay:

 6390 23:06:30.460927  DQS0 = 28, DQS1 = 36

 6391 23:06:30.461339  DQM Delay:

 6392 23:06:30.461697  DQM0 = 11, DQM1 = 12

 6393 23:06:30.463838  DQ Delay:

 6394 23:06:30.467876  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8

 6395 23:06:30.468405  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6396 23:06:30.471329  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4

 6397 23:06:30.474213  DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20

 6398 23:06:30.474728  

 6399 23:06:30.475061  

 6400 23:06:30.484069  [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps

 6401 23:06:30.487388  CH0 RK0: MR19=C0C, MR18=C8B5

 6402 23:06:30.494376  CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265

 6403 23:06:30.494793  ==

 6404 23:06:30.497572  Dram Type= 6, Freq= 0, CH_0, rank 1

 6405 23:06:30.501082  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6406 23:06:30.501507  ==

 6407 23:06:30.504253  [Gating] SW mode calibration

 6408 23:06:30.510968  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6409 23:06:30.513853  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6410 23:06:30.520877   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6411 23:06:30.524343   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6412 23:06:30.527250   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6413 23:06:30.534294   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6414 23:06:30.537332   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6415 23:06:30.541035   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6416 23:06:30.547558   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6417 23:06:30.550460   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6418 23:06:30.553683   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6419 23:06:30.557533  Total UI for P1: 0, mck2ui 16

 6420 23:06:30.560411  best dqsien dly found for B0: ( 0, 14, 24)

 6421 23:06:30.564133  Total UI for P1: 0, mck2ui 16

 6422 23:06:30.567080  best dqsien dly found for B1: ( 0, 14, 24)

 6423 23:06:30.570846  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6424 23:06:30.574306  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6425 23:06:30.574806  

 6426 23:06:30.580691  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6427 23:06:30.583912  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6428 23:06:30.587583  [Gating] SW calibration Done

 6429 23:06:30.588107  ==

 6430 23:06:30.590973  Dram Type= 6, Freq= 0, CH_0, rank 1

 6431 23:06:30.593763  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6432 23:06:30.594180  ==

 6433 23:06:30.594508  RX Vref Scan: 0

 6434 23:06:30.594809  

 6435 23:06:30.597352  RX Vref 0 -> 0, step: 1

 6436 23:06:30.597828  

 6437 23:06:30.600552  RX Delay -410 -> 252, step: 16

 6438 23:06:30.603605  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6439 23:06:30.610475  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6440 23:06:30.613779  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6441 23:06:30.617074  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6442 23:06:30.620457  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6443 23:06:30.626968  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6444 23:06:30.630321  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6445 23:06:30.633877  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6446 23:06:30.636749  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6447 23:06:30.640261  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6448 23:06:30.646835  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6449 23:06:30.650400  iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448

 6450 23:06:30.653753  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6451 23:06:30.660384  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6452 23:06:30.663834  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6453 23:06:30.666843  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6454 23:06:30.667253  ==

 6455 23:06:30.669946  Dram Type= 6, Freq= 0, CH_0, rank 1

 6456 23:06:30.674075  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6457 23:06:30.674700  ==

 6458 23:06:30.676982  DQS Delay:

 6459 23:06:30.677497  DQS0 = 27, DQS1 = 35

 6460 23:06:30.680383  DQM Delay:

 6461 23:06:30.680793  DQM0 = 12, DQM1 = 12

 6462 23:06:30.683705  DQ Delay:

 6463 23:06:30.684221  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6464 23:06:30.686901  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6465 23:06:30.690445  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6466 23:06:30.693545  DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16

 6467 23:06:30.693997  

 6468 23:06:30.694326  

 6469 23:06:30.694626  ==

 6470 23:06:30.697071  Dram Type= 6, Freq= 0, CH_0, rank 1

 6471 23:06:30.703237  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6472 23:06:30.703733  ==

 6473 23:06:30.704066  

 6474 23:06:30.704373  

 6475 23:06:30.704663  	TX Vref Scan disable

 6476 23:06:30.707116   == TX Byte 0 ==

 6477 23:06:30.710299  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6478 23:06:30.713146  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6479 23:06:30.716676   == TX Byte 1 ==

 6480 23:06:30.720582  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6481 23:06:30.723274  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6482 23:06:30.726572  ==

 6483 23:06:30.726987  Dram Type= 6, Freq= 0, CH_0, rank 1

 6484 23:06:30.733105  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6485 23:06:30.733679  ==

 6486 23:06:30.734020  

 6487 23:06:30.734325  

 6488 23:06:30.736538  	TX Vref Scan disable

 6489 23:06:30.736946   == TX Byte 0 ==

 6490 23:06:30.739917  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6491 23:06:30.743702  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6492 23:06:30.746685   == TX Byte 1 ==

 6493 23:06:30.750061  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6494 23:06:30.753090  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6495 23:06:30.753503  

 6496 23:06:30.756685  [DATLAT]

 6497 23:06:30.757096  Freq=400, CH0 RK1

 6498 23:06:30.757421  

 6499 23:06:30.759727  DATLAT Default: 0xe

 6500 23:06:30.760137  0, 0xFFFF, sum = 0

 6501 23:06:30.763388  1, 0xFFFF, sum = 0

 6502 23:06:30.763806  2, 0xFFFF, sum = 0

 6503 23:06:30.766250  3, 0xFFFF, sum = 0

 6504 23:06:30.766667  4, 0xFFFF, sum = 0

 6505 23:06:30.769927  5, 0xFFFF, sum = 0

 6506 23:06:30.770450  6, 0xFFFF, sum = 0

 6507 23:06:30.773219  7, 0xFFFF, sum = 0

 6508 23:06:30.776714  8, 0xFFFF, sum = 0

 6509 23:06:30.777210  9, 0xFFFF, sum = 0

 6510 23:06:30.779999  10, 0xFFFF, sum = 0

 6511 23:06:30.780600  11, 0xFFFF, sum = 0

 6512 23:06:30.783353  12, 0xFFFF, sum = 0

 6513 23:06:30.783845  13, 0x0, sum = 1

 6514 23:06:30.786527  14, 0x0, sum = 2

 6515 23:06:30.787172  15, 0x0, sum = 3

 6516 23:06:30.789735  16, 0x0, sum = 4

 6517 23:06:30.790158  best_step = 14

 6518 23:06:30.790487  

 6519 23:06:30.790794  ==

 6520 23:06:30.792615  Dram Type= 6, Freq= 0, CH_0, rank 1

 6521 23:06:30.796479  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6522 23:06:30.797022  ==

 6523 23:06:30.799848  RX Vref Scan: 0

 6524 23:06:30.800262  

 6525 23:06:30.802706  RX Vref 0 -> 0, step: 1

 6526 23:06:30.803114  

 6527 23:06:30.803564  RX Delay -311 -> 252, step: 8

 6528 23:06:30.811558  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6529 23:06:30.814989  iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448

 6530 23:06:30.818110  iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456

 6531 23:06:30.821740  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6532 23:06:30.827975  iDelay=217, Bit 4, Center -8 (-231 ~ 216) 448

 6533 23:06:30.831353  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6534 23:06:30.835109  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6535 23:06:30.838775  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6536 23:06:30.844712  iDelay=217, Bit 8, Center -32 (-247 ~ 184) 432

 6537 23:06:30.848589  iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440

 6538 23:06:30.851640  iDelay=217, Bit 10, Center -24 (-239 ~ 192) 432

 6539 23:06:30.854636  iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440

 6540 23:06:30.861356  iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432

 6541 23:06:30.865005  iDelay=217, Bit 13, Center -16 (-231 ~ 200) 432

 6542 23:06:30.868265  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6543 23:06:30.874412  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6544 23:06:30.874954  ==

 6545 23:06:30.878012  Dram Type= 6, Freq= 0, CH_0, rank 1

 6546 23:06:30.881528  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6547 23:06:30.882022  ==

 6548 23:06:30.882385  DQS Delay:

 6549 23:06:30.884538  DQS0 = 24, DQS1 = 36

 6550 23:06:30.885126  DQM Delay:

 6551 23:06:30.887911  DQM0 = 9, DQM1 = 13

 6552 23:06:30.888367  DQ Delay:

 6553 23:06:30.891358  DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8

 6554 23:06:30.894337  DQ4 =16, DQ5 =0, DQ6 =12, DQ7 =16

 6555 23:06:30.897540  DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =8

 6556 23:06:30.901032  DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20

 6557 23:06:30.901451  

 6558 23:06:30.901951  

 6559 23:06:30.908005  [DQSOSCAuto] RK1, (LSB)MR18= 0xbd5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps

 6560 23:06:30.911208  CH0 RK1: MR19=C0C, MR18=BD5D

 6561 23:06:30.917754  CH0_RK1: MR19=0xC0C, MR18=0xBD5D, DQSOSC=386, MR23=63, INC=396, DEC=264

 6562 23:06:30.921158  [RxdqsGatingPostProcess] freq 400

 6563 23:06:30.924886  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6564 23:06:30.927917  best DQS0 dly(2T, 0.5T) = (0, 10)

 6565 23:06:30.931392  best DQS1 dly(2T, 0.5T) = (0, 10)

 6566 23:06:30.934428  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6567 23:06:30.937870  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6568 23:06:30.941427  best DQS0 dly(2T, 0.5T) = (0, 10)

 6569 23:06:30.944225  best DQS1 dly(2T, 0.5T) = (0, 10)

 6570 23:06:30.948131  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6571 23:06:30.950938  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6572 23:06:30.954239  Pre-setting of DQS Precalculation

 6573 23:06:30.957654  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6574 23:06:30.961182  ==

 6575 23:06:30.961786  Dram Type= 6, Freq= 0, CH_1, rank 0

 6576 23:06:30.967527  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6577 23:06:30.968072  ==

 6578 23:06:30.971021  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6579 23:06:30.977628  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6580 23:06:30.981226  [CA 0] Center 36 (8~64) winsize 57

 6581 23:06:30.984157  [CA 1] Center 36 (8~64) winsize 57

 6582 23:06:30.987484  [CA 2] Center 36 (8~64) winsize 57

 6583 23:06:30.990315  [CA 3] Center 36 (8~64) winsize 57

 6584 23:06:30.993910  [CA 4] Center 36 (8~64) winsize 57

 6585 23:06:30.997340  [CA 5] Center 36 (8~64) winsize 57

 6586 23:06:30.997826  

 6587 23:06:31.000662  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6588 23:06:31.001213  

 6589 23:06:31.003849  [CATrainingPosCal] consider 1 rank data

 6590 23:06:31.007474  u2DelayCellTimex100 = 270/100 ps

 6591 23:06:31.010730  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6592 23:06:31.013857  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6593 23:06:31.017154  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6594 23:06:31.020577  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6595 23:06:31.026837  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6596 23:06:31.030433  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6597 23:06:31.030894  

 6598 23:06:31.034257  CA PerBit enable=1, Macro0, CA PI delay=36

 6599 23:06:31.034821  

 6600 23:06:31.037011  [CBTSetCACLKResult] CA Dly = 36

 6601 23:06:31.037467  CS Dly: 1 (0~32)

 6602 23:06:31.037869  ==

 6603 23:06:31.040905  Dram Type= 6, Freq= 0, CH_1, rank 1

 6604 23:06:31.047411  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6605 23:06:31.047985  ==

 6606 23:06:31.050068  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6607 23:06:31.056872  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6608 23:06:31.060643  [CA 0] Center 36 (8~64) winsize 57

 6609 23:06:31.063770  [CA 1] Center 36 (8~64) winsize 57

 6610 23:06:31.066988  [CA 2] Center 36 (8~64) winsize 57

 6611 23:06:31.070384  [CA 3] Center 36 (8~64) winsize 57

 6612 23:06:31.073397  [CA 4] Center 36 (8~64) winsize 57

 6613 23:06:31.076789  [CA 5] Center 36 (8~64) winsize 57

 6614 23:06:31.077240  

 6615 23:06:31.080303  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6616 23:06:31.080865  

 6617 23:06:31.084051  [CATrainingPosCal] consider 2 rank data

 6618 23:06:31.087212  u2DelayCellTimex100 = 270/100 ps

 6619 23:06:31.090289  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6620 23:06:31.093666  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6621 23:06:31.097653  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6622 23:06:31.100244  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6623 23:06:31.103588  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6624 23:06:31.106616  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6625 23:06:31.107028  

 6626 23:06:31.113265  CA PerBit enable=1, Macro0, CA PI delay=36

 6627 23:06:31.114040  

 6628 23:06:31.114540  [CBTSetCACLKResult] CA Dly = 36

 6629 23:06:31.116764  CS Dly: 1 (0~32)

 6630 23:06:31.117299  

 6631 23:06:31.120169  ----->DramcWriteLeveling(PI) begin...

 6632 23:06:31.120717  ==

 6633 23:06:31.123180  Dram Type= 6, Freq= 0, CH_1, rank 0

 6634 23:06:31.126731  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6635 23:06:31.127368  ==

 6636 23:06:31.129970  Write leveling (Byte 0): 40 => 8

 6637 23:06:31.133538  Write leveling (Byte 1): 40 => 8

 6638 23:06:31.136939  DramcWriteLeveling(PI) end<-----

 6639 23:06:31.137352  

 6640 23:06:31.137733  ==

 6641 23:06:31.140146  Dram Type= 6, Freq= 0, CH_1, rank 0

 6642 23:06:31.143699  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6643 23:06:31.144216  ==

 6644 23:06:31.146819  [Gating] SW mode calibration

 6645 23:06:31.153349  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6646 23:06:31.160283  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6647 23:06:31.162846   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6648 23:06:31.169681   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6649 23:06:31.173305   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6650 23:06:31.176484   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6651 23:06:31.182783   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6652 23:06:31.186301   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6653 23:06:31.189489   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6654 23:06:31.196254   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6655 23:06:31.199588   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6656 23:06:31.203049  Total UI for P1: 0, mck2ui 16

 6657 23:06:31.206431  best dqsien dly found for B0: ( 0, 14, 24)

 6658 23:06:31.209767  Total UI for P1: 0, mck2ui 16

 6659 23:06:31.213228  best dqsien dly found for B1: ( 0, 14, 24)

 6660 23:06:31.216120  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6661 23:06:31.219981  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6662 23:06:31.220495  

 6663 23:06:31.222816  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6664 23:06:31.226256  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6665 23:06:31.229723  [Gating] SW calibration Done

 6666 23:06:31.230135  ==

 6667 23:06:31.232664  Dram Type= 6, Freq= 0, CH_1, rank 0

 6668 23:06:31.236171  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6669 23:06:31.239468  ==

 6670 23:06:31.239879  RX Vref Scan: 0

 6671 23:06:31.240207  

 6672 23:06:31.242757  RX Vref 0 -> 0, step: 1

 6673 23:06:31.243170  

 6674 23:06:31.246391  RX Delay -410 -> 252, step: 16

 6675 23:06:31.249315  iDelay=230, Bit 0, Center -3 (-234 ~ 229) 464

 6676 23:06:31.252424  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6677 23:06:31.256178  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6678 23:06:31.262355  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6679 23:06:31.266020  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6680 23:06:31.269634  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6681 23:06:31.272300  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6682 23:06:31.279801  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6683 23:06:31.282276  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6684 23:06:31.286283  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6685 23:06:31.289265  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6686 23:06:31.295702  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6687 23:06:31.298828  iDelay=230, Bit 12, Center -3 (-234 ~ 229) 464

 6688 23:06:31.302118  iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448

 6689 23:06:31.305879  iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448

 6690 23:06:31.312459  iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464

 6691 23:06:31.312939  ==

 6692 23:06:31.315423  Dram Type= 6, Freq= 0, CH_1, rank 0

 6693 23:06:31.319044  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6694 23:06:31.319458  ==

 6695 23:06:31.319784  DQS Delay:

 6696 23:06:31.322582  DQS0 = 35, DQS1 = 35

 6697 23:06:31.322991  DQM Delay:

 6698 23:06:31.325622  DQM0 = 20, DQM1 = 17

 6699 23:06:31.326041  DQ Delay:

 6700 23:06:31.328807  DQ0 =32, DQ1 =16, DQ2 =0, DQ3 =16

 6701 23:06:31.332219  DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16

 6702 23:06:31.335336  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6703 23:06:31.338960  DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32

 6704 23:06:31.339465  

 6705 23:06:31.339790  

 6706 23:06:31.340090  ==

 6707 23:06:31.342176  Dram Type= 6, Freq= 0, CH_1, rank 0

 6708 23:06:31.345562  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6709 23:06:31.346019  ==

 6710 23:06:31.348624  

 6711 23:06:31.349100  

 6712 23:06:31.349421  	TX Vref Scan disable

 6713 23:06:31.352102   == TX Byte 0 ==

 6714 23:06:31.355522  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6715 23:06:31.358539  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6716 23:06:31.362065   == TX Byte 1 ==

 6717 23:06:31.365170  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6718 23:06:31.368291  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6719 23:06:31.368856  ==

 6720 23:06:31.372229  Dram Type= 6, Freq= 0, CH_1, rank 0

 6721 23:06:31.375140  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6722 23:06:31.378454  ==

 6723 23:06:31.378863  

 6724 23:06:31.379187  

 6725 23:06:31.379486  	TX Vref Scan disable

 6726 23:06:31.381698   == TX Byte 0 ==

 6727 23:06:31.385181  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6728 23:06:31.388388  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6729 23:06:31.391614   == TX Byte 1 ==

 6730 23:06:31.394991  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6731 23:06:31.398520  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6732 23:06:31.398932  

 6733 23:06:31.399257  [DATLAT]

 6734 23:06:31.401953  Freq=400, CH1 RK0

 6735 23:06:31.402363  

 6736 23:06:31.405010  DATLAT Default: 0xf

 6737 23:06:31.405442  0, 0xFFFF, sum = 0

 6738 23:06:31.408726  1, 0xFFFF, sum = 0

 6739 23:06:31.409276  2, 0xFFFF, sum = 0

 6740 23:06:31.411806  3, 0xFFFF, sum = 0

 6741 23:06:31.412508  4, 0xFFFF, sum = 0

 6742 23:06:31.415148  5, 0xFFFF, sum = 0

 6743 23:06:31.415714  6, 0xFFFF, sum = 0

 6744 23:06:31.418528  7, 0xFFFF, sum = 0

 6745 23:06:31.418966  8, 0xFFFF, sum = 0

 6746 23:06:31.421405  9, 0xFFFF, sum = 0

 6747 23:06:31.421889  10, 0xFFFF, sum = 0

 6748 23:06:31.425258  11, 0xFFFF, sum = 0

 6749 23:06:31.425841  12, 0xFFFF, sum = 0

 6750 23:06:31.428404  13, 0x0, sum = 1

 6751 23:06:31.428840  14, 0x0, sum = 2

 6752 23:06:31.432155  15, 0x0, sum = 3

 6753 23:06:31.432721  16, 0x0, sum = 4

 6754 23:06:31.435148  best_step = 14

 6755 23:06:31.435691  

 6756 23:06:31.436145  ==

 6757 23:06:31.438647  Dram Type= 6, Freq= 0, CH_1, rank 0

 6758 23:06:31.441666  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6759 23:06:31.442238  ==

 6760 23:06:31.445083  RX Vref Scan: 1

 6761 23:06:31.445687  

 6762 23:06:31.446144  RX Vref 0 -> 0, step: 1

 6763 23:06:31.446562  

 6764 23:06:31.448475  RX Delay -311 -> 252, step: 8

 6765 23:06:31.448904  

 6766 23:06:31.452154  Set Vref, RX VrefLevel [Byte0]: 53

 6767 23:06:31.454783                           [Byte1]: 51

 6768 23:06:31.459805  

 6769 23:06:31.460344  Final RX Vref Byte 0 = 53 to rank0

 6770 23:06:31.463143  Final RX Vref Byte 1 = 51 to rank0

 6771 23:06:31.466251  Final RX Vref Byte 0 = 53 to rank1

 6772 23:06:31.469040  Final RX Vref Byte 1 = 51 to rank1==

 6773 23:06:31.472802  Dram Type= 6, Freq= 0, CH_1, rank 0

 6774 23:06:31.479141  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6775 23:06:31.479646  ==

 6776 23:06:31.479976  DQS Delay:

 6777 23:06:31.480284  DQS0 = 32, DQS1 = 32

 6778 23:06:31.482710  DQM Delay:

 6779 23:06:31.483122  DQM0 = 13, DQM1 = 11

 6780 23:06:31.486077  DQ Delay:

 6781 23:06:31.489419  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12

 6782 23:06:31.489864  DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12

 6783 23:06:31.492483  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4

 6784 23:06:31.495911  DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24

 6785 23:06:31.496324  

 6786 23:06:31.496645  

 6787 23:06:31.505979  [DQSOSCAuto] RK0, (LSB)MR18= 0x8fc8, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 391 ps

 6788 23:06:31.509372  CH1 RK0: MR19=C0C, MR18=8FC8

 6789 23:06:31.516131  CH1_RK0: MR19=0xC0C, MR18=0x8FC8, DQSOSC=385, MR23=63, INC=398, DEC=265

 6790 23:06:31.516643  ==

 6791 23:06:31.519373  Dram Type= 6, Freq= 0, CH_1, rank 1

 6792 23:06:31.523026  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6793 23:06:31.523585  ==

 6794 23:06:31.526480  [Gating] SW mode calibration

 6795 23:06:31.533326  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6796 23:06:31.536081  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6797 23:06:31.542666   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6798 23:06:31.546313   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6799 23:06:31.549989   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6800 23:06:31.556553   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6801 23:06:31.559672   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6802 23:06:31.562612   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6803 23:06:31.569514   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6804 23:06:31.572742   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6805 23:06:31.576079   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6806 23:06:31.579155  Total UI for P1: 0, mck2ui 16

 6807 23:06:31.582700  best dqsien dly found for B0: ( 0, 14, 24)

 6808 23:06:31.586070  Total UI for P1: 0, mck2ui 16

 6809 23:06:31.589543  best dqsien dly found for B1: ( 0, 14, 24)

 6810 23:06:31.592527  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6811 23:06:31.596227  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6812 23:06:31.596791  

 6813 23:06:31.602778  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6814 23:06:31.605732  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6815 23:06:31.606188  [Gating] SW calibration Done

 6816 23:06:31.609255  ==

 6817 23:06:31.612557  Dram Type= 6, Freq= 0, CH_1, rank 1

 6818 23:06:31.615788  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6819 23:06:31.616249  ==

 6820 23:06:31.616607  RX Vref Scan: 0

 6821 23:06:31.616939  

 6822 23:06:31.619245  RX Vref 0 -> 0, step: 1

 6823 23:06:31.619701  

 6824 23:06:31.622872  RX Delay -410 -> 252, step: 16

 6825 23:06:31.626210  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6826 23:06:31.629014  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6827 23:06:31.635929  iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448

 6828 23:06:31.639535  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6829 23:06:31.642619  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6830 23:06:31.646131  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6831 23:06:31.652768  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6832 23:06:31.655709  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6833 23:06:31.659561  iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448

 6834 23:06:31.662411  iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448

 6835 23:06:31.669156  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6836 23:06:31.672474  iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464

 6837 23:06:31.675949  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6838 23:06:31.679423  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6839 23:06:31.685513  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6840 23:06:31.689287  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6841 23:06:31.689795  ==

 6842 23:06:31.692301  Dram Type= 6, Freq= 0, CH_1, rank 1

 6843 23:06:31.695885  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6844 23:06:31.696356  ==

 6845 23:06:31.699510  DQS Delay:

 6846 23:06:31.699941  DQS0 = 27, DQS1 = 27

 6847 23:06:31.702395  DQM Delay:

 6848 23:06:31.702809  DQM0 = 11, DQM1 = 8

 6849 23:06:31.703138  DQ Delay:

 6850 23:06:31.705845  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8

 6851 23:06:31.709830  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6852 23:06:31.712560  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8

 6853 23:06:31.716331  DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =16

 6854 23:06:31.716852  

 6855 23:06:31.717181  

 6856 23:06:31.717482  ==

 6857 23:06:31.719337  Dram Type= 6, Freq= 0, CH_1, rank 1

 6858 23:06:31.723023  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6859 23:06:31.723541  ==

 6860 23:06:31.725706  

 6861 23:06:31.726133  

 6862 23:06:31.726456  	TX Vref Scan disable

 6863 23:06:31.729455   == TX Byte 0 ==

 6864 23:06:31.732360  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6865 23:06:31.735839  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6866 23:06:31.739487   == TX Byte 1 ==

 6867 23:06:31.742420  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6868 23:06:31.745452  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6869 23:06:31.745921  ==

 6870 23:06:31.749172  Dram Type= 6, Freq= 0, CH_1, rank 1

 6871 23:06:31.752317  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6872 23:06:31.755480  ==

 6873 23:06:31.755891  

 6874 23:06:31.756215  

 6875 23:06:31.756515  	TX Vref Scan disable

 6876 23:06:31.759105   == TX Byte 0 ==

 6877 23:06:31.762262  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6878 23:06:31.765829  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6879 23:06:31.768935   == TX Byte 1 ==

 6880 23:06:31.772350  Update DQ  dly =582 (4 ,2, 6)  DQ  OEN =(3 ,3)

 6881 23:06:31.775329  Update DQM dly =582 (4 ,2, 6)  DQM OEN =(3 ,3)

 6882 23:06:31.775743  

 6883 23:06:31.776064  [DATLAT]

 6884 23:06:31.778777  Freq=400, CH1 RK1

 6885 23:06:31.779262  

 6886 23:06:31.782173  DATLAT Default: 0xe

 6887 23:06:31.782584  0, 0xFFFF, sum = 0

 6888 23:06:31.785927  1, 0xFFFF, sum = 0

 6889 23:06:31.786437  2, 0xFFFF, sum = 0

 6890 23:06:31.788729  3, 0xFFFF, sum = 0

 6891 23:06:31.789146  4, 0xFFFF, sum = 0

 6892 23:06:31.792073  5, 0xFFFF, sum = 0

 6893 23:06:31.792494  6, 0xFFFF, sum = 0

 6894 23:06:31.795596  7, 0xFFFF, sum = 0

 6895 23:06:31.796049  8, 0xFFFF, sum = 0

 6896 23:06:31.799107  9, 0xFFFF, sum = 0

 6897 23:06:31.799541  10, 0xFFFF, sum = 0

 6898 23:06:31.802088  11, 0xFFFF, sum = 0

 6899 23:06:31.802524  12, 0xFFFF, sum = 0

 6900 23:06:31.805772  13, 0x0, sum = 1

 6901 23:06:31.806381  14, 0x0, sum = 2

 6902 23:06:31.808835  15, 0x0, sum = 3

 6903 23:06:31.809379  16, 0x0, sum = 4

 6904 23:06:31.811823  best_step = 14

 6905 23:06:31.812248  

 6906 23:06:31.812680  ==

 6907 23:06:31.815552  Dram Type= 6, Freq= 0, CH_1, rank 1

 6908 23:06:31.818485  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6909 23:06:31.818928  ==

 6910 23:06:31.822294  RX Vref Scan: 0

 6911 23:06:31.822823  

 6912 23:06:31.823300  RX Vref 0 -> 0, step: 1

 6913 23:06:31.823697  

 6914 23:06:31.824900  RX Delay -295 -> 252, step: 8

 6915 23:06:31.832834  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6916 23:06:31.836240  iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448

 6917 23:06:31.839740  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6918 23:06:31.842734  iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448

 6919 23:06:31.849727  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6920 23:06:31.852791  iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440

 6921 23:06:31.856074  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6922 23:06:31.859431  iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440

 6923 23:06:31.866357  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6924 23:06:31.869273  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6925 23:06:31.872482  iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456

 6926 23:06:31.876281  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 6927 23:06:31.882593  iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456

 6928 23:06:31.886298  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6929 23:06:31.889271  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6930 23:06:31.896059  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 6931 23:06:31.896520  ==

 6932 23:06:31.899123  Dram Type= 6, Freq= 0, CH_1, rank 1

 6933 23:06:31.902477  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6934 23:06:31.902938  ==

 6935 23:06:31.903302  DQS Delay:

 6936 23:06:31.906046  DQS0 = 28, DQS1 = 36

 6937 23:06:31.906567  DQM Delay:

 6938 23:06:31.908970  DQM0 = 10, DQM1 = 14

 6939 23:06:31.909424  DQ Delay:

 6940 23:06:31.912720  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4

 6941 23:06:31.916069  DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8

 6942 23:06:31.919452  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8

 6943 23:06:31.922620  DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24

 6944 23:06:31.923156  

 6945 23:06:31.923521  

 6946 23:06:31.929388  [DQSOSCAuto] RK1, (LSB)MR18= 0xc355, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps

 6947 23:06:31.932802  CH1 RK1: MR19=C0C, MR18=C355

 6948 23:06:31.939196  CH1_RK1: MR19=0xC0C, MR18=0xC355, DQSOSC=385, MR23=63, INC=398, DEC=265

 6949 23:06:31.942131  [RxdqsGatingPostProcess] freq 400

 6950 23:06:31.949415  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6951 23:06:31.950036  best DQS0 dly(2T, 0.5T) = (0, 10)

 6952 23:06:31.952199  best DQS1 dly(2T, 0.5T) = (0, 10)

 6953 23:06:31.955868  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6954 23:06:31.958631  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6955 23:06:31.962411  best DQS0 dly(2T, 0.5T) = (0, 10)

 6956 23:06:31.965494  best DQS1 dly(2T, 0.5T) = (0, 10)

 6957 23:06:31.968448  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6958 23:06:31.972378  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6959 23:06:31.975442  Pre-setting of DQS Precalculation

 6960 23:06:31.982091  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6961 23:06:31.988819  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6962 23:06:31.994943  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6963 23:06:31.995492  

 6964 23:06:31.995866  

 6965 23:06:31.998938  [Calibration Summary] 800 Mbps

 6966 23:06:31.999512  CH 0, Rank 0

 6967 23:06:32.002138  SW Impedance     : PASS

 6968 23:06:32.005104  DUTY Scan        : NO K

 6969 23:06:32.005711  ZQ Calibration   : PASS

 6970 23:06:32.008855  Jitter Meter     : NO K

 6971 23:06:32.011642  CBT Training     : PASS

 6972 23:06:32.012219  Write leveling   : PASS

 6973 23:06:32.014991  RX DQS gating    : PASS

 6974 23:06:32.015447  RX DQ/DQS(RDDQC) : PASS

 6975 23:06:32.018284  TX DQ/DQS        : PASS

 6976 23:06:32.021760  RX DATLAT        : PASS

 6977 23:06:32.022217  RX DQ/DQS(Engine): PASS

 6978 23:06:32.025229  TX OE            : NO K

 6979 23:06:32.025733  All Pass.

 6980 23:06:32.026097  

 6981 23:06:32.028313  CH 0, Rank 1

 6982 23:06:32.028861  SW Impedance     : PASS

 6983 23:06:32.031732  DUTY Scan        : NO K

 6984 23:06:32.035016  ZQ Calibration   : PASS

 6985 23:06:32.035574  Jitter Meter     : NO K

 6986 23:06:32.038449  CBT Training     : PASS

 6987 23:06:32.041727  Write leveling   : NO K

 6988 23:06:32.042278  RX DQS gating    : PASS

 6989 23:06:32.044839  RX DQ/DQS(RDDQC) : PASS

 6990 23:06:32.047995  TX DQ/DQS        : PASS

 6991 23:06:32.048478  RX DATLAT        : PASS

 6992 23:06:32.051327  RX DQ/DQS(Engine): PASS

 6993 23:06:32.054733  TX OE            : NO K

 6994 23:06:32.055194  All Pass.

 6995 23:06:32.055552  

 6996 23:06:32.055884  CH 1, Rank 0

 6997 23:06:32.058376  SW Impedance     : PASS

 6998 23:06:32.061391  DUTY Scan        : NO K

 6999 23:06:32.062011  ZQ Calibration   : PASS

 7000 23:06:32.064954  Jitter Meter     : NO K

 7001 23:06:32.068213  CBT Training     : PASS

 7002 23:06:32.068671  Write leveling   : PASS

 7003 23:06:32.070912  RX DQS gating    : PASS

 7004 23:06:32.071379  RX DQ/DQS(RDDQC) : PASS

 7005 23:06:32.074538  TX DQ/DQS        : PASS

 7006 23:06:32.077852  RX DATLAT        : PASS

 7007 23:06:32.078330  RX DQ/DQS(Engine): PASS

 7008 23:06:32.081003  TX OE            : NO K

 7009 23:06:32.081461  All Pass.

 7010 23:06:32.081880  

 7011 23:06:32.084565  CH 1, Rank 1

 7012 23:06:32.085034  SW Impedance     : PASS

 7013 23:06:32.087969  DUTY Scan        : NO K

 7014 23:06:32.091245  ZQ Calibration   : PASS

 7015 23:06:32.091755  Jitter Meter     : NO K

 7016 23:06:32.094542  CBT Training     : PASS

 7017 23:06:32.097691  Write leveling   : NO K

 7018 23:06:32.098192  RX DQS gating    : PASS

 7019 23:06:32.101126  RX DQ/DQS(RDDQC) : PASS

 7020 23:06:32.104194  TX DQ/DQS        : PASS

 7021 23:06:32.104607  RX DATLAT        : PASS

 7022 23:06:32.107396  RX DQ/DQS(Engine): PASS

 7023 23:06:32.110985  TX OE            : NO K

 7024 23:06:32.111497  All Pass.

 7025 23:06:32.111826  

 7026 23:06:32.112219  DramC Write-DBI off

 7027 23:06:32.114324  	PER_BANK_REFRESH: Hybrid Mode

 7028 23:06:32.117551  TX_TRACKING: ON

 7029 23:06:32.124133  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7030 23:06:32.127426  [FAST_K] Save calibration result to emmc

 7031 23:06:32.134069  dramc_set_vcore_voltage set vcore to 725000

 7032 23:06:32.134544  Read voltage for 1600, 0

 7033 23:06:32.137465  Vio18 = 0

 7034 23:06:32.137938  Vcore = 725000

 7035 23:06:32.138390  Vdram = 0

 7036 23:06:32.140518  Vddq = 0

 7037 23:06:32.140931  Vmddr = 0

 7038 23:06:32.144130  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7039 23:06:32.150705  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7040 23:06:32.154277  MEM_TYPE=3, freq_sel=13

 7041 23:06:32.157534  sv_algorithm_assistance_LP4_3733 

 7042 23:06:32.160183  ============ PULL DRAM RESETB DOWN ============

 7043 23:06:32.163680  ========== PULL DRAM RESETB DOWN end =========

 7044 23:06:32.170413  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7045 23:06:32.170831  =================================== 

 7046 23:06:32.173857  LPDDR4 DRAM CONFIGURATION

 7047 23:06:32.177421  =================================== 

 7048 23:06:32.181054  EX_ROW_EN[0]    = 0x0

 7049 23:06:32.181572  EX_ROW_EN[1]    = 0x0

 7050 23:06:32.184486  LP4Y_EN      = 0x0

 7051 23:06:32.185001  WORK_FSP     = 0x1

 7052 23:06:32.187712  WL           = 0x5

 7053 23:06:32.188227  RL           = 0x5

 7054 23:06:32.190943  BL           = 0x2

 7055 23:06:32.191476  RPST         = 0x0

 7056 23:06:32.193964  RD_PRE       = 0x0

 7057 23:06:32.194384  WR_PRE       = 0x1

 7058 23:06:32.197457  WR_PST       = 0x1

 7059 23:06:32.200705  DBI_WR       = 0x0

 7060 23:06:32.201219  DBI_RD       = 0x0

 7061 23:06:32.204025  OTF          = 0x1

 7062 23:06:32.206927  =================================== 

 7063 23:06:32.210373  =================================== 

 7064 23:06:32.210786  ANA top config

 7065 23:06:32.213883  =================================== 

 7066 23:06:32.217834  DLL_ASYNC_EN            =  0

 7067 23:06:32.218344  ALL_SLAVE_EN            =  0

 7068 23:06:32.220472  NEW_RANK_MODE           =  1

 7069 23:06:32.224292  DLL_IDLE_MODE           =  1

 7070 23:06:32.227237  LP45_APHY_COMB_EN       =  1

 7071 23:06:32.230375  TX_ODT_DIS              =  0

 7072 23:06:32.230787  NEW_8X_MODE             =  1

 7073 23:06:32.233490  =================================== 

 7074 23:06:32.237138  =================================== 

 7075 23:06:32.240287  data_rate                  = 3200

 7076 23:06:32.243808  CKR                        = 1

 7077 23:06:32.246869  DQ_P2S_RATIO               = 8

 7078 23:06:32.250167  =================================== 

 7079 23:06:32.253483  CA_P2S_RATIO               = 8

 7080 23:06:32.256800  DQ_CA_OPEN                 = 0

 7081 23:06:32.257184  DQ_SEMI_OPEN               = 0

 7082 23:06:32.260507  CA_SEMI_OPEN               = 0

 7083 23:06:32.263282  CA_FULL_RATE               = 0

 7084 23:06:32.267402  DQ_CKDIV4_EN               = 0

 7085 23:06:32.270399  CA_CKDIV4_EN               = 0

 7086 23:06:32.273975  CA_PREDIV_EN               = 0

 7087 23:06:32.274392  PH8_DLY                    = 12

 7088 23:06:32.277192  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7089 23:06:32.280660  DQ_AAMCK_DIV               = 4

 7090 23:06:32.283785  CA_AAMCK_DIV               = 4

 7091 23:06:32.286873  CA_ADMCK_DIV               = 4

 7092 23:06:32.290124  DQ_TRACK_CA_EN             = 0

 7093 23:06:32.293706  CA_PICK                    = 1600

 7094 23:06:32.294260  CA_MCKIO                   = 1600

 7095 23:06:32.296803  MCKIO_SEMI                 = 0

 7096 23:06:32.300355  PLL_FREQ                   = 3068

 7097 23:06:32.303326  DQ_UI_PI_RATIO             = 32

 7098 23:06:32.306582  CA_UI_PI_RATIO             = 0

 7099 23:06:32.310207  =================================== 

 7100 23:06:32.313200  =================================== 

 7101 23:06:32.317089  memory_type:LPDDR4         

 7102 23:06:32.317692  GP_NUM     : 10       

 7103 23:06:32.320005  SRAM_EN    : 1       

 7104 23:06:32.320609  MD32_EN    : 0       

 7105 23:06:32.323706  =================================== 

 7106 23:06:32.327023  [ANA_INIT] >>>>>>>>>>>>>> 

 7107 23:06:32.329874  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7108 23:06:32.333427  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7109 23:06:32.336383  =================================== 

 7110 23:06:32.340089  data_rate = 3200,PCW = 0X7600

 7111 23:06:32.343556  =================================== 

 7112 23:06:32.346478  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7113 23:06:32.353158  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7114 23:06:32.356053  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7115 23:06:32.363043  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7116 23:06:32.365882  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7117 23:06:32.369657  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7118 23:06:32.370134  [ANA_INIT] flow start 

 7119 23:06:32.372962  [ANA_INIT] PLL >>>>>>>> 

 7120 23:06:32.376301  [ANA_INIT] PLL <<<<<<<< 

 7121 23:06:32.376757  [ANA_INIT] MIDPI >>>>>>>> 

 7122 23:06:32.379290  [ANA_INIT] MIDPI <<<<<<<< 

 7123 23:06:32.382728  [ANA_INIT] DLL >>>>>>>> 

 7124 23:06:32.383181  [ANA_INIT] DLL <<<<<<<< 

 7125 23:06:32.386125  [ANA_INIT] flow end 

 7126 23:06:32.389889  ============ LP4 DIFF to SE enter ============

 7127 23:06:32.392952  ============ LP4 DIFF to SE exit  ============

 7128 23:06:32.396307  [ANA_INIT] <<<<<<<<<<<<< 

 7129 23:06:32.400120  [Flow] Enable top DCM control >>>>> 

 7130 23:06:32.402842  [Flow] Enable top DCM control <<<<< 

 7131 23:06:32.406047  Enable DLL master slave shuffle 

 7132 23:06:32.413255  ============================================================== 

 7133 23:06:32.413893  Gating Mode config

 7134 23:06:32.419578  ============================================================== 

 7135 23:06:32.422767  Config description: 

 7136 23:06:32.429953  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7137 23:06:32.436483  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7138 23:06:32.442971  SELPH_MODE            0: By rank         1: By Phase 

 7139 23:06:32.449398  ============================================================== 

 7140 23:06:32.450042  GAT_TRACK_EN                 =  1

 7141 23:06:32.452822  RX_GATING_MODE               =  2

 7142 23:06:32.456002  RX_GATING_TRACK_MODE         =  2

 7143 23:06:32.459655  SELPH_MODE                   =  1

 7144 23:06:32.462654  PICG_EARLY_EN                =  1

 7145 23:06:32.466007  VALID_LAT_VALUE              =  1

 7146 23:06:32.472727  ============================================================== 

 7147 23:06:32.476223  Enter into Gating configuration >>>> 

 7148 23:06:32.479447  Exit from Gating configuration <<<< 

 7149 23:06:32.482655  Enter into  DVFS_PRE_config >>>>> 

 7150 23:06:32.492563  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7151 23:06:32.496153  Exit from  DVFS_PRE_config <<<<< 

 7152 23:06:32.499098  Enter into PICG configuration >>>> 

 7153 23:06:32.502458  Exit from PICG configuration <<<< 

 7154 23:06:32.505451  [RX_INPUT] configuration >>>>> 

 7155 23:06:32.505963  [RX_INPUT] configuration <<<<< 

 7156 23:06:32.512456  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7157 23:06:32.518828  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7158 23:06:32.522603  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7159 23:06:32.529338  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7160 23:06:32.535531  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7161 23:06:32.542263  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7162 23:06:32.545752  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7163 23:06:32.549640  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7164 23:06:32.555797  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7165 23:06:32.558649  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7166 23:06:32.562375  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7167 23:06:32.569353  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7168 23:06:32.572192  =================================== 

 7169 23:06:32.572749  LPDDR4 DRAM CONFIGURATION

 7170 23:06:32.575951  =================================== 

 7171 23:06:32.579124  EX_ROW_EN[0]    = 0x0

 7172 23:06:32.579676  EX_ROW_EN[1]    = 0x0

 7173 23:06:32.582486  LP4Y_EN      = 0x0

 7174 23:06:32.582944  WORK_FSP     = 0x1

 7175 23:06:32.585416  WL           = 0x5

 7176 23:06:32.585905  RL           = 0x5

 7177 23:06:32.589001  BL           = 0x2

 7178 23:06:32.589659  RPST         = 0x0

 7179 23:06:32.592074  RD_PRE       = 0x0

 7180 23:06:32.596028  WR_PRE       = 0x1

 7181 23:06:32.596591  WR_PST       = 0x1

 7182 23:06:32.598803  DBI_WR       = 0x0

 7183 23:06:32.599260  DBI_RD       = 0x0

 7184 23:06:32.602226  OTF          = 0x1

 7185 23:06:32.605529  =================================== 

 7186 23:06:32.608436  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7187 23:06:32.612620  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7188 23:06:32.615442  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7189 23:06:32.618508  =================================== 

 7190 23:06:32.622242  LPDDR4 DRAM CONFIGURATION

 7191 23:06:32.625699  =================================== 

 7192 23:06:32.628891  EX_ROW_EN[0]    = 0x10

 7193 23:06:32.629440  EX_ROW_EN[1]    = 0x0

 7194 23:06:32.632298  LP4Y_EN      = 0x0

 7195 23:06:32.632860  WORK_FSP     = 0x1

 7196 23:06:32.635356  WL           = 0x5

 7197 23:06:32.635814  RL           = 0x5

 7198 23:06:32.638601  BL           = 0x2

 7199 23:06:32.639063  RPST         = 0x0

 7200 23:06:32.642475  RD_PRE       = 0x0

 7201 23:06:32.642935  WR_PRE       = 0x1

 7202 23:06:32.645502  WR_PST       = 0x1

 7203 23:06:32.646019  DBI_WR       = 0x0

 7204 23:06:32.649446  DBI_RD       = 0x0

 7205 23:06:32.650044  OTF          = 0x1

 7206 23:06:32.652204  =================================== 

 7207 23:06:32.658716  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7208 23:06:32.659273  ==

 7209 23:06:32.662280  Dram Type= 6, Freq= 0, CH_0, rank 0

 7210 23:06:32.668868  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7211 23:06:32.669428  ==

 7212 23:06:32.669862  [Duty_Offset_Calibration]

 7213 23:06:32.671555  	B0:2	B1:1	CA:1

 7214 23:06:32.672008  

 7215 23:06:32.674894  [DutyScan_Calibration_Flow] k_type=0

 7216 23:06:32.684917  

 7217 23:06:32.685460  ==CLK 0==

 7218 23:06:32.688055  Final CLK duty delay cell = 0

 7219 23:06:32.692041  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7220 23:06:32.694810  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7221 23:06:32.695271  [0] AVG Duty = 5031%(X100)

 7222 23:06:32.698301  

 7223 23:06:32.701701  CH0 CLK Duty spec in!! Max-Min= 249%

 7224 23:06:32.704680  [DutyScan_Calibration_Flow] ====Done====

 7225 23:06:32.705136  

 7226 23:06:32.708061  [DutyScan_Calibration_Flow] k_type=1

 7227 23:06:32.724205  

 7228 23:06:32.724776  ==DQS 0 ==

 7229 23:06:32.727062  Final DQS duty delay cell = -4

 7230 23:06:32.730523  [-4] MAX Duty = 5125%(X100), DQS PI = 26

 7231 23:06:32.733639  [-4] MIN Duty = 4657%(X100), DQS PI = 0

 7232 23:06:32.737204  [-4] AVG Duty = 4891%(X100)

 7233 23:06:32.737698  

 7234 23:06:32.738065  ==DQS 1 ==

 7235 23:06:32.740714  Final DQS duty delay cell = 0

 7236 23:06:32.743919  [0] MAX Duty = 5187%(X100), DQS PI = 4

 7237 23:06:32.747381  [0] MIN Duty = 5062%(X100), DQS PI = 30

 7238 23:06:32.750471  [0] AVG Duty = 5124%(X100)

 7239 23:06:32.750936  

 7240 23:06:32.753903  CH0 DQS 0 Duty spec in!! Max-Min= 468%

 7241 23:06:32.754364  

 7242 23:06:32.756745  CH0 DQS 1 Duty spec in!! Max-Min= 125%

 7243 23:06:32.760479  [DutyScan_Calibration_Flow] ====Done====

 7244 23:06:32.760921  

 7245 23:06:32.763470  [DutyScan_Calibration_Flow] k_type=3

 7246 23:06:32.781271  

 7247 23:06:32.781830  ==DQM 0 ==

 7248 23:06:32.784594  Final DQM duty delay cell = 0

 7249 23:06:32.788013  [0] MAX Duty = 5187%(X100), DQS PI = 26

 7250 23:06:32.790829  [0] MIN Duty = 4907%(X100), DQS PI = 56

 7251 23:06:32.794405  [0] AVG Duty = 5047%(X100)

 7252 23:06:32.794816  

 7253 23:06:32.795144  ==DQM 1 ==

 7254 23:06:32.797544  Final DQM duty delay cell = 0

 7255 23:06:32.800921  [0] MAX Duty = 5187%(X100), DQS PI = 6

 7256 23:06:32.804669  [0] MIN Duty = 5062%(X100), DQS PI = 14

 7257 23:06:32.808299  [0] AVG Duty = 5124%(X100)

 7258 23:06:32.808985  

 7259 23:06:32.810981  CH0 DQM 0 Duty spec in!! Max-Min= 280%

 7260 23:06:32.811532  

 7261 23:06:32.814582  CH0 DQM 1 Duty spec in!! Max-Min= 125%

 7262 23:06:32.817705  [DutyScan_Calibration_Flow] ====Done====

 7263 23:06:32.818165  

 7264 23:06:32.821306  [DutyScan_Calibration_Flow] k_type=2

 7265 23:06:32.838251  

 7266 23:06:32.838794  ==DQ 0 ==

 7267 23:06:32.841824  Final DQ duty delay cell = 0

 7268 23:06:32.844816  [0] MAX Duty = 5062%(X100), DQS PI = 24

 7269 23:06:32.848272  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7270 23:06:32.848826  [0] AVG Duty = 4984%(X100)

 7271 23:06:32.852065  

 7272 23:06:32.852524  ==DQ 1 ==

 7273 23:06:32.854911  Final DQ duty delay cell = 0

 7274 23:06:32.858296  [0] MAX Duty = 5093%(X100), DQS PI = 6

 7275 23:06:32.861463  [0] MIN Duty = 4907%(X100), DQS PI = 34

 7276 23:06:32.862084  [0] AVG Duty = 5000%(X100)

 7277 23:06:32.862462  

 7278 23:06:32.864673  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7279 23:06:32.867858  

 7280 23:06:32.871551  CH0 DQ 1 Duty spec in!! Max-Min= 186%

 7281 23:06:32.874678  [DutyScan_Calibration_Flow] ====Done====

 7282 23:06:32.875243  ==

 7283 23:06:32.878146  Dram Type= 6, Freq= 0, CH_1, rank 0

 7284 23:06:32.881686  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7285 23:06:32.882151  ==

 7286 23:06:32.884855  [Duty_Offset_Calibration]

 7287 23:06:32.885326  	B0:1	B1:0	CA:0

 7288 23:06:32.885758  

 7289 23:06:32.888062  [DutyScan_Calibration_Flow] k_type=0

 7290 23:06:32.897438  

 7291 23:06:32.898024  ==CLK 0==

 7292 23:06:32.900913  Final CLK duty delay cell = -4

 7293 23:06:32.904315  [-4] MAX Duty = 4969%(X100), DQS PI = 22

 7294 23:06:32.907194  [-4] MIN Duty = 4844%(X100), DQS PI = 50

 7295 23:06:32.910641  [-4] AVG Duty = 4906%(X100)

 7296 23:06:32.911053  

 7297 23:06:32.914251  CH1 CLK Duty spec in!! Max-Min= 125%

 7298 23:06:32.917231  [DutyScan_Calibration_Flow] ====Done====

 7299 23:06:32.917692  

 7300 23:06:32.920874  [DutyScan_Calibration_Flow] k_type=1

 7301 23:06:32.937547  

 7302 23:06:32.938106  ==DQS 0 ==

 7303 23:06:32.941051  Final DQS duty delay cell = 0

 7304 23:06:32.944331  [0] MAX Duty = 5094%(X100), DQS PI = 12

 7305 23:06:32.947740  [0] MIN Duty = 4844%(X100), DQS PI = 48

 7306 23:06:32.950812  [0] AVG Duty = 4969%(X100)

 7307 23:06:32.951272  

 7308 23:06:32.951630  ==DQS 1 ==

 7309 23:06:32.954019  Final DQS duty delay cell = 0

 7310 23:06:32.957724  [0] MAX Duty = 5249%(X100), DQS PI = 16

 7311 23:06:32.960987  [0] MIN Duty = 4969%(X100), DQS PI = 8

 7312 23:06:32.964114  [0] AVG Duty = 5109%(X100)

 7313 23:06:32.964610  

 7314 23:06:32.967573  CH1 DQS 0 Duty spec in!! Max-Min= 250%

 7315 23:06:32.967987  

 7316 23:06:32.970762  CH1 DQS 1 Duty spec in!! Max-Min= 280%

 7317 23:06:32.974207  [DutyScan_Calibration_Flow] ====Done====

 7318 23:06:32.974714  

 7319 23:06:32.977465  [DutyScan_Calibration_Flow] k_type=3

 7320 23:06:32.994383  

 7321 23:06:32.994962  ==DQM 0 ==

 7322 23:06:32.997695  Final DQM duty delay cell = 0

 7323 23:06:33.001432  [0] MAX Duty = 5218%(X100), DQS PI = 18

 7324 23:06:33.004602  [0] MIN Duty = 4969%(X100), DQS PI = 48

 7325 23:06:33.005087  [0] AVG Duty = 5093%(X100)

 7326 23:06:33.007690  

 7327 23:06:33.008096  ==DQM 1 ==

 7328 23:06:33.011587  Final DQM duty delay cell = 0

 7329 23:06:33.014573  [0] MAX Duty = 5062%(X100), DQS PI = 14

 7330 23:06:33.018038  [0] MIN Duty = 4907%(X100), DQS PI = 52

 7331 23:06:33.021101  [0] AVG Duty = 4984%(X100)

 7332 23:06:33.021689  

 7333 23:06:33.024495  CH1 DQM 0 Duty spec in!! Max-Min= 249%

 7334 23:06:33.024946  

 7335 23:06:33.027789  CH1 DQM 1 Duty spec in!! Max-Min= 155%

 7336 23:06:33.031116  [DutyScan_Calibration_Flow] ====Done====

 7337 23:06:33.031672  

 7338 23:06:33.034958  [DutyScan_Calibration_Flow] k_type=2

 7339 23:06:33.050877  

 7340 23:06:33.051414  ==DQ 0 ==

 7341 23:06:33.053946  Final DQ duty delay cell = -4

 7342 23:06:33.057695  [-4] MAX Duty = 5062%(X100), DQS PI = 12

 7343 23:06:33.060774  [-4] MIN Duty = 4875%(X100), DQS PI = 46

 7344 23:06:33.064139  [-4] AVG Duty = 4968%(X100)

 7345 23:06:33.064594  

 7346 23:06:33.064950  ==DQ 1 ==

 7347 23:06:33.067587  Final DQ duty delay cell = 0

 7348 23:06:33.070756  [0] MAX Duty = 5124%(X100), DQS PI = 16

 7349 23:06:33.074639  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7350 23:06:33.075195  [0] AVG Duty = 5031%(X100)

 7351 23:06:33.075559  

 7352 23:06:33.080998  CH1 DQ 0 Duty spec in!! Max-Min= 187%

 7353 23:06:33.081570  

 7354 23:06:33.084004  CH1 DQ 1 Duty spec in!! Max-Min= 186%

 7355 23:06:33.087322  [DutyScan_Calibration_Flow] ====Done====

 7356 23:06:33.090758  nWR fixed to 30

 7357 23:06:33.091214  [ModeRegInit_LP4] CH0 RK0

 7358 23:06:33.094179  [ModeRegInit_LP4] CH0 RK1

 7359 23:06:33.097979  [ModeRegInit_LP4] CH1 RK0

 7360 23:06:33.100625  [ModeRegInit_LP4] CH1 RK1

 7361 23:06:33.101125  match AC timing 5

 7362 23:06:33.104003  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7363 23:06:33.110606  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7364 23:06:33.113922  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7365 23:06:33.120699  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7366 23:06:33.124107  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7367 23:06:33.124637  [MiockJmeterHQA]

 7368 23:06:33.124997  

 7369 23:06:33.127614  [DramcMiockJmeter] u1RxGatingPI = 0

 7370 23:06:33.130787  0 : 4255, 4026

 7371 23:06:33.131358  4 : 4365, 4140

 7372 23:06:33.131725  8 : 4253, 4027

 7373 23:06:33.133869  12 : 4252, 4027

 7374 23:06:33.134435  16 : 4252, 4027

 7375 23:06:33.137463  20 : 4252, 4027

 7376 23:06:33.137948  24 : 4363, 4137

 7377 23:06:33.140887  28 : 4255, 4029

 7378 23:06:33.141447  32 : 4255, 4029

 7379 23:06:33.144365  36 : 4252, 4027

 7380 23:06:33.144924  40 : 4253, 4027

 7381 23:06:33.145290  44 : 4253, 4026

 7382 23:06:33.147887  48 : 4363, 4137

 7383 23:06:33.148452  52 : 4363, 4137

 7384 23:06:33.150477  56 : 4252, 4027

 7385 23:06:33.150943  60 : 4253, 4026

 7386 23:06:33.154652  64 : 4252, 4027

 7387 23:06:33.155204  68 : 4253, 4027

 7388 23:06:33.155573  72 : 4254, 4029

 7389 23:06:33.157498  76 : 4361, 4138

 7390 23:06:33.158092  80 : 4250, 4027

 7391 23:06:33.160715  84 : 4361, 4136

 7392 23:06:33.161181  88 : 4250, 120

 7393 23:06:33.163776  92 : 4253, 0

 7394 23:06:33.164232  96 : 4250, 0

 7395 23:06:33.164594  100 : 4361, 0

 7396 23:06:33.167117  104 : 4360, 0

 7397 23:06:33.167816  108 : 4363, 0

 7398 23:06:33.170189  112 : 4250, 0

 7399 23:06:33.170753  116 : 4250, 0

 7400 23:06:33.171353  120 : 4250, 0

 7401 23:06:33.173688  124 : 4253, 0

 7402 23:06:33.174163  128 : 4250, 0

 7403 23:06:33.174553  132 : 4250, 0

 7404 23:06:33.177244  136 : 4253, 0

 7405 23:06:33.177722  140 : 4364, 0

 7406 23:06:33.180165  144 : 4255, 0

 7407 23:06:33.180584  148 : 4249, 0

 7408 23:06:33.180915  152 : 4250, 0

 7409 23:06:33.184144  156 : 4360, 0

 7410 23:06:33.184564  160 : 4360, 0

 7411 23:06:33.187032  164 : 4250, 0

 7412 23:06:33.187452  168 : 4250, 0

 7413 23:06:33.187783  172 : 4250, 0

 7414 23:06:33.190428  176 : 4252, 0

 7415 23:06:33.190844  180 : 4250, 0

 7416 23:06:33.193491  184 : 4250, 0

 7417 23:06:33.193945  188 : 4252, 0

 7418 23:06:33.194285  192 : 4361, 0

 7419 23:06:33.196949  196 : 4250, 0

 7420 23:06:33.197530  200 : 4250, 0

 7421 23:06:33.200236  204 : 4252, 1372

 7422 23:06:33.200654  208 : 4253, 3976

 7423 23:06:33.201017  212 : 4249, 4027

 7424 23:06:33.204277  216 : 4255, 4029

 7425 23:06:33.204713  220 : 4361, 4137

 7426 23:06:33.206945  224 : 4252, 4030

 7427 23:06:33.207368  228 : 4361, 4138

 7428 23:06:33.210499  232 : 4361, 4138

 7429 23:06:33.210924  236 : 4250, 4026

 7430 23:06:33.213950  240 : 4250, 4026

 7431 23:06:33.214475  244 : 4361, 4137

 7432 23:06:33.216863  248 : 4255, 4029

 7433 23:06:33.217282  252 : 4252, 4027

 7434 23:06:33.220598  256 : 4255, 4029

 7435 23:06:33.221144  260 : 4253, 4029

 7436 23:06:33.224289  264 : 4255, 4029

 7437 23:06:33.224814  268 : 4252, 4027

 7438 23:06:33.225151  272 : 4361, 4137

 7439 23:06:33.227190  276 : 4250, 4026

 7440 23:06:33.227714  280 : 4361, 4138

 7441 23:06:33.230490  284 : 4361, 4138

 7442 23:06:33.230910  288 : 4250, 4026

 7443 23:06:33.233658  292 : 4250, 4027

 7444 23:06:33.234083  296 : 4361, 4137

 7445 23:06:33.236980  300 : 4250, 4027

 7446 23:06:33.237414  304 : 4249, 4027

 7447 23:06:33.240125  308 : 4250, 3950

 7448 23:06:33.240565  312 : 4252, 2215

 7449 23:06:33.244031  316 : 4250, 3

 7450 23:06:33.244582  

 7451 23:06:33.245022  	MIOCK jitter meter	ch=0

 7452 23:06:33.245340  

 7453 23:06:33.246958  1T = (316-88) = 228 dly cells

 7454 23:06:33.253708  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps

 7455 23:06:33.254234  ==

 7456 23:06:33.257268  Dram Type= 6, Freq= 0, CH_0, rank 0

 7457 23:06:33.260269  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7458 23:06:33.260682  ==

 7459 23:06:33.266767  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7460 23:06:33.269825  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7461 23:06:33.273866  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7462 23:06:33.280293  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7463 23:06:33.290095  [CA 0] Center 43 (12~74) winsize 63

 7464 23:06:33.293200  [CA 1] Center 43 (13~74) winsize 62

 7465 23:06:33.296851  [CA 2] Center 38 (9~68) winsize 60

 7466 23:06:33.300162  [CA 3] Center 38 (8~68) winsize 61

 7467 23:06:33.302682  [CA 4] Center 37 (7~67) winsize 61

 7468 23:06:33.306477  [CA 5] Center 36 (7~65) winsize 59

 7469 23:06:33.306934  

 7470 23:06:33.310099  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 7471 23:06:33.310656  

 7472 23:06:33.313143  [CATrainingPosCal] consider 1 rank data

 7473 23:06:33.316567  u2DelayCellTimex100 = 285/100 ps

 7474 23:06:33.319969  CA0 delay=43 (12~74),Diff = 7 PI (23 cell)

 7475 23:06:33.326549  CA1 delay=43 (13~74),Diff = 7 PI (23 cell)

 7476 23:06:33.329721  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 7477 23:06:33.333116  CA3 delay=38 (8~68),Diff = 2 PI (6 cell)

 7478 23:06:33.335771  CA4 delay=37 (7~67),Diff = 1 PI (3 cell)

 7479 23:06:33.339888  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7480 23:06:33.340455  

 7481 23:06:33.342608  CA PerBit enable=1, Macro0, CA PI delay=36

 7482 23:06:33.343072  

 7483 23:06:33.346160  [CBTSetCACLKResult] CA Dly = 36

 7484 23:06:33.349267  CS Dly: 9 (0~40)

 7485 23:06:33.352689  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7486 23:06:33.356127  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7487 23:06:33.356679  ==

 7488 23:06:33.359248  Dram Type= 6, Freq= 0, CH_0, rank 1

 7489 23:06:33.362315  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7490 23:06:33.365967  ==

 7491 23:06:33.369957  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7492 23:06:33.372807  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7493 23:06:33.378976  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7494 23:06:33.382565  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7495 23:06:33.393205  [CA 0] Center 43 (13~73) winsize 61

 7496 23:06:33.396950  [CA 1] Center 42 (12~73) winsize 62

 7497 23:06:33.400058  [CA 2] Center 38 (8~68) winsize 61

 7498 23:06:33.402885  [CA 3] Center 38 (8~68) winsize 61

 7499 23:06:33.406424  [CA 4] Center 36 (6~66) winsize 61

 7500 23:06:33.409686  [CA 5] Center 35 (6~65) winsize 60

 7501 23:06:33.410176  

 7502 23:06:33.412619  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7503 23:06:33.413093  

 7504 23:06:33.416735  [CATrainingPosCal] consider 2 rank data

 7505 23:06:33.419276  u2DelayCellTimex100 = 285/100 ps

 7506 23:06:33.422799  CA0 delay=43 (13~73),Diff = 7 PI (23 cell)

 7507 23:06:33.429316  CA1 delay=43 (13~73),Diff = 7 PI (23 cell)

 7508 23:06:33.432532  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 7509 23:06:33.435967  CA3 delay=38 (8~68),Diff = 2 PI (6 cell)

 7510 23:06:33.439502  CA4 delay=36 (7~66),Diff = 0 PI (0 cell)

 7511 23:06:33.443107  CA5 delay=36 (7~65),Diff = 0 PI (0 cell)

 7512 23:06:33.443737  

 7513 23:06:33.445729  CA PerBit enable=1, Macro0, CA PI delay=36

 7514 23:06:33.446141  

 7515 23:06:33.449402  [CBTSetCACLKResult] CA Dly = 36

 7516 23:06:33.452448  CS Dly: 10 (0~42)

 7517 23:06:33.455986  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7518 23:06:33.459197  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7519 23:06:33.459613  

 7520 23:06:33.462990  ----->DramcWriteLeveling(PI) begin...

 7521 23:06:33.463515  ==

 7522 23:06:33.465623  Dram Type= 6, Freq= 0, CH_0, rank 0

 7523 23:06:33.469415  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7524 23:06:33.472494  ==

 7525 23:06:33.472930  Write leveling (Byte 0): 35 => 35

 7526 23:06:33.475629  Write leveling (Byte 1): 28 => 28

 7527 23:06:33.479116  DramcWriteLeveling(PI) end<-----

 7528 23:06:33.479531  

 7529 23:06:33.479860  ==

 7530 23:06:33.482337  Dram Type= 6, Freq= 0, CH_0, rank 0

 7531 23:06:33.489709  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7532 23:06:33.490265  ==

 7533 23:06:33.490636  [Gating] SW mode calibration

 7534 23:06:33.499400  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7535 23:06:33.502343  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7536 23:06:33.509611   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7537 23:06:33.512503   1  4  4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)

 7538 23:06:33.515826   1  4  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7539 23:06:33.522235   1  4 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (0 0)

 7540 23:06:33.526273   1  4 16 | B1->B0 | 2424 3535 | 1 0 | (1 1) (1 1)

 7541 23:06:33.529036   1  4 20 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)

 7542 23:06:33.532610   1  4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)

 7543 23:06:33.539281   1  4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (0 0)

 7544 23:06:33.542493   1  5  0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)

 7545 23:06:33.545486   1  5  4 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)

 7546 23:06:33.552308   1  5  8 | B1->B0 | 3434 3130 | 1 1 | (1 1) (1 0)

 7547 23:06:33.555233   1  5 12 | B1->B0 | 3434 2928 | 1 1 | (1 1) (0 0)

 7548 23:06:33.558823   1  5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)

 7549 23:06:33.565647   1  5 20 | B1->B0 | 2727 2524 | 0 1 | (1 0) (0 0)

 7550 23:06:33.568994   1  5 24 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)

 7551 23:06:33.571935   1  5 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 7552 23:06:33.578974   1  6  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7553 23:06:33.581892   1  6  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7554 23:06:33.585380   1  6  8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)

 7555 23:06:33.592319   1  6 12 | B1->B0 | 2323 4342 | 0 1 | (0 0) (0 0)

 7556 23:06:33.595623   1  6 16 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)

 7557 23:06:33.598579   1  6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 7558 23:06:33.605227   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7559 23:06:33.609254   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7560 23:06:33.612176   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7561 23:06:33.618679   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7562 23:06:33.621683   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7563 23:06:33.625365   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7564 23:06:33.632071   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 7565 23:06:33.635430   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7566 23:06:33.638460   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7567 23:06:33.645429   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7568 23:06:33.648882   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7569 23:06:33.651962   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7570 23:06:33.658326   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7571 23:06:33.661728   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7572 23:06:33.664945   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7573 23:06:33.671691   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7574 23:06:33.675032   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7575 23:06:33.678540   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7576 23:06:33.684681   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7577 23:06:33.688330   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7578 23:06:33.691375   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7579 23:06:33.694838   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7580 23:06:33.701513   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7581 23:06:33.705045  Total UI for P1: 0, mck2ui 16

 7582 23:06:33.708430  best dqsien dly found for B0: ( 1,  9, 10)

 7583 23:06:33.711343   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7584 23:06:33.714685  Total UI for P1: 0, mck2ui 16

 7585 23:06:33.718171  best dqsien dly found for B1: ( 1,  9, 16)

 7586 23:06:33.721678  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7587 23:06:33.725025  best DQS1 dly(MCK, UI, PI) = (1, 9, 16)

 7588 23:06:33.725487  

 7589 23:06:33.728378  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7590 23:06:33.734543  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)

 7591 23:06:33.735088  [Gating] SW calibration Done

 7592 23:06:33.735458  ==

 7593 23:06:33.738046  Dram Type= 6, Freq= 0, CH_0, rank 0

 7594 23:06:33.744957  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7595 23:06:33.745520  ==

 7596 23:06:33.745999  RX Vref Scan: 0

 7597 23:06:33.746353  

 7598 23:06:33.748382  RX Vref 0 -> 0, step: 1

 7599 23:06:33.748935  

 7600 23:06:33.751529  RX Delay 0 -> 252, step: 8

 7601 23:06:33.755148  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7602 23:06:33.758185  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7603 23:06:33.761427  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7604 23:06:33.764708  iDelay=200, Bit 3, Center 131 (80 ~ 183) 104

 7605 23:06:33.771328  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7606 23:06:33.774627  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7607 23:06:33.777977  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7608 23:06:33.781377  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7609 23:06:33.784744  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7610 23:06:33.791431  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 7611 23:06:33.794772  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7612 23:06:33.797904  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7613 23:06:33.801287  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 7614 23:06:33.804264  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 7615 23:06:33.811141  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7616 23:06:33.814129  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7617 23:06:33.814565  ==

 7618 23:06:33.817699  Dram Type= 6, Freq= 0, CH_0, rank 0

 7619 23:06:33.821019  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7620 23:06:33.821540  ==

 7621 23:06:33.824593  DQS Delay:

 7622 23:06:33.825099  DQS0 = 0, DQS1 = 0

 7623 23:06:33.825436  DQM Delay:

 7624 23:06:33.827719  DQM0 = 136, DQM1 = 131

 7625 23:06:33.828141  DQ Delay:

 7626 23:06:33.831225  DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131

 7627 23:06:33.834217  DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143

 7628 23:06:33.837694  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123

 7629 23:06:33.844841  DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135

 7630 23:06:33.845352  

 7631 23:06:33.845731  

 7632 23:06:33.846047  ==

 7633 23:06:33.847819  Dram Type= 6, Freq= 0, CH_0, rank 0

 7634 23:06:33.851382  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7635 23:06:33.851896  ==

 7636 23:06:33.852231  

 7637 23:06:33.852540  

 7638 23:06:33.854064  	TX Vref Scan disable

 7639 23:06:33.854484   == TX Byte 0 ==

 7640 23:06:33.861086  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 7641 23:06:33.864386  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7642 23:06:33.864908   == TX Byte 1 ==

 7643 23:06:33.871139  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 7644 23:06:33.873879  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 7645 23:06:33.874352  ==

 7646 23:06:33.877314  Dram Type= 6, Freq= 0, CH_0, rank 0

 7647 23:06:33.881048  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7648 23:06:33.881563  ==

 7649 23:06:33.895921  

 7650 23:06:33.898920  TX Vref early break, caculate TX vref

 7651 23:06:33.902524  TX Vref=16, minBit 7, minWin=22, winSum=379

 7652 23:06:33.905803  TX Vref=18, minBit 6, minWin=23, winSum=390

 7653 23:06:33.909538  TX Vref=20, minBit 7, minWin=23, winSum=400

 7654 23:06:33.912121  TX Vref=22, minBit 0, minWin=24, winSum=408

 7655 23:06:33.915802  TX Vref=24, minBit 7, minWin=25, winSum=420

 7656 23:06:33.921904  TX Vref=26, minBit 2, minWin=25, winSum=421

 7657 23:06:33.925069  TX Vref=28, minBit 1, minWin=25, winSum=422

 7658 23:06:33.928696  TX Vref=30, minBit 2, minWin=24, winSum=414

 7659 23:06:33.931936  TX Vref=32, minBit 6, minWin=23, winSum=402

 7660 23:06:33.935597  TX Vref=34, minBit 0, minWin=23, winSum=393

 7661 23:06:33.942149  [TxChooseVref] Worse bit 1, Min win 25, Win sum 422, Final Vref 28

 7662 23:06:33.942923  

 7663 23:06:33.945078  Final TX Range 0 Vref 28

 7664 23:06:33.945501  

 7665 23:06:33.945895  ==

 7666 23:06:33.948787  Dram Type= 6, Freq= 0, CH_0, rank 0

 7667 23:06:33.952171  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7668 23:06:33.952679  ==

 7669 23:06:33.953018  

 7670 23:06:33.953344  

 7671 23:06:33.955652  	TX Vref Scan disable

 7672 23:06:33.961795  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 7673 23:06:33.962223   == TX Byte 0 ==

 7674 23:06:33.965402  u2DelayCellOfst[0]=10 cells (3 PI)

 7675 23:06:33.969023  u2DelayCellOfst[1]=13 cells (4 PI)

 7676 23:06:33.972077  u2DelayCellOfst[2]=10 cells (3 PI)

 7677 23:06:33.975067  u2DelayCellOfst[3]=10 cells (3 PI)

 7678 23:06:33.978794  u2DelayCellOfst[4]=6 cells (2 PI)

 7679 23:06:33.982345  u2DelayCellOfst[5]=0 cells (0 PI)

 7680 23:06:33.985202  u2DelayCellOfst[6]=17 cells (5 PI)

 7681 23:06:33.985660  u2DelayCellOfst[7]=17 cells (5 PI)

 7682 23:06:33.992053  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7683 23:06:33.995693  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7684 23:06:33.996213   == TX Byte 1 ==

 7685 23:06:33.999194  u2DelayCellOfst[8]=0 cells (0 PI)

 7686 23:06:34.002256  u2DelayCellOfst[9]=0 cells (0 PI)

 7687 23:06:34.005190  u2DelayCellOfst[10]=6 cells (2 PI)

 7688 23:06:34.008825  u2DelayCellOfst[11]=0 cells (0 PI)

 7689 23:06:34.011791  u2DelayCellOfst[12]=10 cells (3 PI)

 7690 23:06:34.015349  u2DelayCellOfst[13]=6 cells (2 PI)

 7691 23:06:34.018682  u2DelayCellOfst[14]=13 cells (4 PI)

 7692 23:06:34.022366  u2DelayCellOfst[15]=10 cells (3 PI)

 7693 23:06:34.025324  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7694 23:06:34.028992  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7695 23:06:34.032423  DramC Write-DBI on

 7696 23:06:34.032837  ==

 7697 23:06:34.035977  Dram Type= 6, Freq= 0, CH_0, rank 0

 7698 23:06:34.038704  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7699 23:06:34.039130  ==

 7700 23:06:34.039463  

 7701 23:06:34.039765  

 7702 23:06:34.042154  	TX Vref Scan disable

 7703 23:06:34.045334   == TX Byte 0 ==

 7704 23:06:34.048876  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 7705 23:06:34.052410   == TX Byte 1 ==

 7706 23:06:34.055872  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 7707 23:06:34.056387  DramC Write-DBI off

 7708 23:06:34.056723  

 7709 23:06:34.058426  [DATLAT]

 7710 23:06:34.058840  Freq=1600, CH0 RK0

 7711 23:06:34.059169  

 7712 23:06:34.061641  DATLAT Default: 0xf

 7713 23:06:34.062059  0, 0xFFFF, sum = 0

 7714 23:06:34.065449  1, 0xFFFF, sum = 0

 7715 23:06:34.066019  2, 0xFFFF, sum = 0

 7716 23:06:34.068478  3, 0xFFFF, sum = 0

 7717 23:06:34.068902  4, 0xFFFF, sum = 0

 7718 23:06:34.072192  5, 0xFFFF, sum = 0

 7719 23:06:34.072617  6, 0xFFFF, sum = 0

 7720 23:06:34.075381  7, 0xFFFF, sum = 0

 7721 23:06:34.075883  8, 0xFFFF, sum = 0

 7722 23:06:34.078714  9, 0xFFFF, sum = 0

 7723 23:06:34.081808  10, 0xFFFF, sum = 0

 7724 23:06:34.082326  11, 0xFFFF, sum = 0

 7725 23:06:34.085223  12, 0xFFFF, sum = 0

 7726 23:06:34.085702  13, 0xFFFF, sum = 0

 7727 23:06:34.088736  14, 0x0, sum = 1

 7728 23:06:34.089256  15, 0x0, sum = 2

 7729 23:06:34.091835  16, 0x0, sum = 3

 7730 23:06:34.092256  17, 0x0, sum = 4

 7731 23:06:34.092592  best_step = 15

 7732 23:06:34.095500  

 7733 23:06:34.096011  ==

 7734 23:06:34.098305  Dram Type= 6, Freq= 0, CH_0, rank 0

 7735 23:06:34.102065  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7736 23:06:34.102594  ==

 7737 23:06:34.102934  RX Vref Scan: 1

 7738 23:06:34.103246  

 7739 23:06:34.105544  Set Vref Range= 24 -> 127

 7740 23:06:34.106024  

 7741 23:06:34.108252  RX Vref 24 -> 127, step: 1

 7742 23:06:34.108668  

 7743 23:06:34.111946  RX Delay 27 -> 252, step: 4

 7744 23:06:34.112415  

 7745 23:06:34.114988  Set Vref, RX VrefLevel [Byte0]: 24

 7746 23:06:34.118116                           [Byte1]: 24

 7747 23:06:34.118531  

 7748 23:06:34.121724  Set Vref, RX VrefLevel [Byte0]: 25

 7749 23:06:34.125146                           [Byte1]: 25

 7750 23:06:34.125715  

 7751 23:06:34.128292  Set Vref, RX VrefLevel [Byte0]: 26

 7752 23:06:34.131844                           [Byte1]: 26

 7753 23:06:34.135107  

 7754 23:06:34.135524  Set Vref, RX VrefLevel [Byte0]: 27

 7755 23:06:34.138311                           [Byte1]: 27

 7756 23:06:34.142542  

 7757 23:06:34.142999  Set Vref, RX VrefLevel [Byte0]: 28

 7758 23:06:34.146134                           [Byte1]: 28

 7759 23:06:34.149985  

 7760 23:06:34.150400  Set Vref, RX VrefLevel [Byte0]: 29

 7761 23:06:34.153423                           [Byte1]: 29

 7762 23:06:34.157537  

 7763 23:06:34.158096  Set Vref, RX VrefLevel [Byte0]: 30

 7764 23:06:34.161088                           [Byte1]: 30

 7765 23:06:34.165312  

 7766 23:06:34.165877  Set Vref, RX VrefLevel [Byte0]: 31

 7767 23:06:34.168381                           [Byte1]: 31

 7768 23:06:34.172445  

 7769 23:06:34.173033  Set Vref, RX VrefLevel [Byte0]: 32

 7770 23:06:34.175877                           [Byte1]: 32

 7771 23:06:34.179994  

 7772 23:06:34.180508  Set Vref, RX VrefLevel [Byte0]: 33

 7773 23:06:34.183466                           [Byte1]: 33

 7774 23:06:34.187821  

 7775 23:06:34.188268  Set Vref, RX VrefLevel [Byte0]: 34

 7776 23:06:34.191158                           [Byte1]: 34

 7777 23:06:34.195342  

 7778 23:06:34.195915  Set Vref, RX VrefLevel [Byte0]: 35

 7779 23:06:34.198272                           [Byte1]: 35

 7780 23:06:34.202529  

 7781 23:06:34.202949  Set Vref, RX VrefLevel [Byte0]: 36

 7782 23:06:34.206031                           [Byte1]: 36

 7783 23:06:34.210428  

 7784 23:06:34.210941  Set Vref, RX VrefLevel [Byte0]: 37

 7785 23:06:34.213844                           [Byte1]: 37

 7786 23:06:34.217884  

 7787 23:06:34.218299  Set Vref, RX VrefLevel [Byte0]: 38

 7788 23:06:34.221454                           [Byte1]: 38

 7789 23:06:34.225714  

 7790 23:06:34.226127  Set Vref, RX VrefLevel [Byte0]: 39

 7791 23:06:34.228970                           [Byte1]: 39

 7792 23:06:34.233236  

 7793 23:06:34.233810  Set Vref, RX VrefLevel [Byte0]: 40

 7794 23:06:34.236071                           [Byte1]: 40

 7795 23:06:34.240655  

 7796 23:06:34.241204  Set Vref, RX VrefLevel [Byte0]: 41

 7797 23:06:34.243841                           [Byte1]: 41

 7798 23:06:34.248151  

 7799 23:06:34.248672  Set Vref, RX VrefLevel [Byte0]: 42

 7800 23:06:34.251594                           [Byte1]: 42

 7801 23:06:34.255392  

 7802 23:06:34.255802  Set Vref, RX VrefLevel [Byte0]: 43

 7803 23:06:34.258997                           [Byte1]: 43

 7804 23:06:34.262904  

 7805 23:06:34.263320  Set Vref, RX VrefLevel [Byte0]: 44

 7806 23:06:34.266415                           [Byte1]: 44

 7807 23:06:34.270395  

 7808 23:06:34.270814  Set Vref, RX VrefLevel [Byte0]: 45

 7809 23:06:34.273649                           [Byte1]: 45

 7810 23:06:34.278702  

 7811 23:06:34.279223  Set Vref, RX VrefLevel [Byte0]: 46

 7812 23:06:34.281722                           [Byte1]: 46

 7813 23:06:34.285670  

 7814 23:06:34.286095  Set Vref, RX VrefLevel [Byte0]: 47

 7815 23:06:34.289368                           [Byte1]: 47

 7816 23:06:34.293478  

 7817 23:06:34.294062  Set Vref, RX VrefLevel [Byte0]: 48

 7818 23:06:34.296305                           [Byte1]: 48

 7819 23:06:34.300827  

 7820 23:06:34.301348  Set Vref, RX VrefLevel [Byte0]: 49

 7821 23:06:34.304008                           [Byte1]: 49

 7822 23:06:34.308461  

 7823 23:06:34.309049  Set Vref, RX VrefLevel [Byte0]: 50

 7824 23:06:34.311846                           [Byte1]: 50

 7825 23:06:34.315912  

 7826 23:06:34.316569  Set Vref, RX VrefLevel [Byte0]: 51

 7827 23:06:34.319321                           [Byte1]: 51

 7828 23:06:34.323615  

 7829 23:06:34.324134  Set Vref, RX VrefLevel [Byte0]: 52

 7830 23:06:34.326576                           [Byte1]: 52

 7831 23:06:34.330911  

 7832 23:06:34.331433  Set Vref, RX VrefLevel [Byte0]: 53

 7833 23:06:34.334122                           [Byte1]: 53

 7834 23:06:34.338443  

 7835 23:06:34.338965  Set Vref, RX VrefLevel [Byte0]: 54

 7836 23:06:34.342307                           [Byte1]: 54

 7837 23:06:34.346598  

 7838 23:06:34.347124  Set Vref, RX VrefLevel [Byte0]: 55

 7839 23:06:34.349377                           [Byte1]: 55

 7840 23:06:34.353362  

 7841 23:06:34.353928  Set Vref, RX VrefLevel [Byte0]: 56

 7842 23:06:34.356795                           [Byte1]: 56

 7843 23:06:34.361425  

 7844 23:06:34.362163  Set Vref, RX VrefLevel [Byte0]: 57

 7845 23:06:34.364321                           [Byte1]: 57

 7846 23:06:34.368301  

 7847 23:06:34.368781  Set Vref, RX VrefLevel [Byte0]: 58

 7848 23:06:34.371564                           [Byte1]: 58

 7849 23:06:34.376176  

 7850 23:06:34.376595  Set Vref, RX VrefLevel [Byte0]: 59

 7851 23:06:34.379351                           [Byte1]: 59

 7852 23:06:34.384013  

 7853 23:06:34.384546  Set Vref, RX VrefLevel [Byte0]: 60

 7854 23:06:34.387598                           [Byte1]: 60

 7855 23:06:34.391624  

 7856 23:06:34.392147  Set Vref, RX VrefLevel [Byte0]: 61

 7857 23:06:34.394662                           [Byte1]: 61

 7858 23:06:34.398477  

 7859 23:06:34.398904  Set Vref, RX VrefLevel [Byte0]: 62

 7860 23:06:34.402272                           [Byte1]: 62

 7861 23:06:34.406527  

 7862 23:06:34.407071  Set Vref, RX VrefLevel [Byte0]: 63

 7863 23:06:34.409445                           [Byte1]: 63

 7864 23:06:34.413543  

 7865 23:06:34.414004  Set Vref, RX VrefLevel [Byte0]: 64

 7866 23:06:34.417100                           [Byte1]: 64

 7867 23:06:34.421450  

 7868 23:06:34.422035  Set Vref, RX VrefLevel [Byte0]: 65

 7869 23:06:34.424771                           [Byte1]: 65

 7870 23:06:34.429044  

 7871 23:06:34.429668  Set Vref, RX VrefLevel [Byte0]: 66

 7872 23:06:34.432080                           [Byte1]: 66

 7873 23:06:34.436148  

 7874 23:06:34.436666  Set Vref, RX VrefLevel [Byte0]: 67

 7875 23:06:34.439630                           [Byte1]: 67

 7876 23:06:34.443752  

 7877 23:06:34.444304  Set Vref, RX VrefLevel [Byte0]: 68

 7878 23:06:34.447658                           [Byte1]: 68

 7879 23:06:34.451772  

 7880 23:06:34.452284  Set Vref, RX VrefLevel [Byte0]: 69

 7881 23:06:34.454434                           [Byte1]: 69

 7882 23:06:34.459407  

 7883 23:06:34.459924  Set Vref, RX VrefLevel [Byte0]: 70

 7884 23:06:34.462388                           [Byte1]: 70

 7885 23:06:34.467010  

 7886 23:06:34.467529  Set Vref, RX VrefLevel [Byte0]: 71

 7887 23:06:34.469525                           [Byte1]: 71

 7888 23:06:34.474509  

 7889 23:06:34.475038  Set Vref, RX VrefLevel [Byte0]: 72

 7890 23:06:34.477315                           [Byte1]: 72

 7891 23:06:34.481987  

 7892 23:06:34.482543  Set Vref, RX VrefLevel [Byte0]: 73

 7893 23:06:34.485205                           [Byte1]: 73

 7894 23:06:34.489278  

 7895 23:06:34.489901  Final RX Vref Byte 0 = 56 to rank0

 7896 23:06:34.492506  Final RX Vref Byte 1 = 65 to rank0

 7897 23:06:34.495458  Final RX Vref Byte 0 = 56 to rank1

 7898 23:06:34.499335  Final RX Vref Byte 1 = 65 to rank1==

 7899 23:06:34.502222  Dram Type= 6, Freq= 0, CH_0, rank 0

 7900 23:06:34.509121  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7901 23:06:34.509885  ==

 7902 23:06:34.510245  DQS Delay:

 7903 23:06:34.510560  DQS0 = 0, DQS1 = 0

 7904 23:06:34.512054  DQM Delay:

 7905 23:06:34.512470  DQM0 = 133, DQM1 = 128

 7906 23:06:34.516067  DQ Delay:

 7907 23:06:34.518764  DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130

 7908 23:06:34.522375  DQ4 =132, DQ5 =124, DQ6 =138, DQ7 =138

 7909 23:06:34.525390  DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =120

 7910 23:06:34.529222  DQ12 =132, DQ13 =132, DQ14 =140, DQ15 =136

 7911 23:06:34.529788  

 7912 23:06:34.530123  

 7913 23:06:34.530426  

 7914 23:06:34.531865  [DramC_TX_OE_Calibration] TA2

 7915 23:06:34.535517  Original DQ_B0 (3 6) =30, OEN = 27

 7916 23:06:34.539292  Original DQ_B1 (3 6) =30, OEN = 27

 7917 23:06:34.541706  24, 0x0, End_B0=24 End_B1=24

 7918 23:06:34.542245  25, 0x0, End_B0=25 End_B1=25

 7919 23:06:34.545082  26, 0x0, End_B0=26 End_B1=26

 7920 23:06:34.548377  27, 0x0, End_B0=27 End_B1=27

 7921 23:06:34.552406  28, 0x0, End_B0=28 End_B1=28

 7922 23:06:34.555949  29, 0x0, End_B0=29 End_B1=29

 7923 23:06:34.556483  30, 0x0, End_B0=30 End_B1=30

 7924 23:06:34.558235  31, 0x4141, End_B0=30 End_B1=30

 7925 23:06:34.561852  Byte0 end_step=30  best_step=27

 7926 23:06:34.564877  Byte1 end_step=30  best_step=27

 7927 23:06:34.568127  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7928 23:06:34.571573  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7929 23:06:34.572045  

 7930 23:06:34.572378  

 7931 23:06:34.578589  [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 7932 23:06:34.581860  CH0 RK0: MR19=303, MR18=2521

 7933 23:06:34.588781  CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16

 7934 23:06:34.589309  

 7935 23:06:34.591779  ----->DramcWriteLeveling(PI) begin...

 7936 23:06:34.592204  ==

 7937 23:06:34.595250  Dram Type= 6, Freq= 0, CH_0, rank 1

 7938 23:06:34.598648  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7939 23:06:34.599077  ==

 7940 23:06:34.601523  Write leveling (Byte 0): 34 => 34

 7941 23:06:34.605358  Write leveling (Byte 1): 29 => 29

 7942 23:06:34.608113  DramcWriteLeveling(PI) end<-----

 7943 23:06:34.608533  

 7944 23:06:34.608862  ==

 7945 23:06:34.612072  Dram Type= 6, Freq= 0, CH_0, rank 1

 7946 23:06:34.615575  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7947 23:06:34.616120  ==

 7948 23:06:34.618219  [Gating] SW mode calibration

 7949 23:06:34.625056  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7950 23:06:34.631636  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7951 23:06:34.634906   1  4  0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)

 7952 23:06:34.641440   1  4  4 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)

 7953 23:06:34.644814   1  4  8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)

 7954 23:06:34.648670   1  4 12 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7955 23:06:34.651730   1  4 16 | B1->B0 | 2d2d 3535 | 0 1 | (0 0) (1 1)

 7956 23:06:34.658460   1  4 20 | B1->B0 | 3434 3c3b | 1 1 | (1 1) (1 1)

 7957 23:06:34.661783   1  4 24 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)

 7958 23:06:34.664644   1  4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)

 7959 23:06:34.671627   1  5  0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (1 1)

 7960 23:06:34.675338   1  5  4 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)

 7961 23:06:34.678485   1  5  8 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)

 7962 23:06:34.684887   1  5 12 | B1->B0 | 3434 3636 | 1 1 | (1 1) (1 0)

 7963 23:06:34.688486   1  5 16 | B1->B0 | 2e2e 2c2c | 0 0 | (0 0) (0 0)

 7964 23:06:34.691853   1  5 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 7965 23:06:34.698089   1  5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7966 23:06:34.701224   1  5 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)

 7967 23:06:34.704475   1  6  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7968 23:06:34.711066   1  6  4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 7969 23:06:34.714872   1  6  8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 7970 23:06:34.717887   1  6 12 | B1->B0 | 2626 3434 | 0 0 | (0 0) (0 0)

 7971 23:06:34.724667   1  6 16 | B1->B0 | 4545 4645 | 0 1 | (0 0) (0 0)

 7972 23:06:34.728184   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7973 23:06:34.731344   1  6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7974 23:06:34.738016   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7975 23:06:34.740735   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7976 23:06:34.744638   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7977 23:06:34.751234   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7978 23:06:34.754758   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 7979 23:06:34.757663   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 7980 23:06:34.764329   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7981 23:06:34.767972   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7982 23:06:34.770633   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7983 23:06:34.777476   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7984 23:06:34.781142   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7985 23:06:34.784433   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7986 23:06:34.791283   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7987 23:06:34.794898   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7988 23:06:34.797753   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7989 23:06:34.804295   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7990 23:06:34.807328   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7991 23:06:34.810823   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7992 23:06:34.817370   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7993 23:06:34.820406   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 7994 23:06:34.824018   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 7995 23:06:34.827337   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7996 23:06:34.830301  Total UI for P1: 0, mck2ui 16

 7997 23:06:34.834147  best dqsien dly found for B0: ( 1,  9, 10)

 7998 23:06:34.837259  Total UI for P1: 0, mck2ui 16

 7999 23:06:34.841090  best dqsien dly found for B1: ( 1,  9, 10)

 8000 23:06:34.844205  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8001 23:06:34.847579  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8002 23:06:34.851168  

 8003 23:06:34.854139  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8004 23:06:34.857768  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8005 23:06:34.860953  [Gating] SW calibration Done

 8006 23:06:34.861373  ==

 8007 23:06:34.863757  Dram Type= 6, Freq= 0, CH_0, rank 1

 8008 23:06:34.867338  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8009 23:06:34.867765  ==

 8010 23:06:34.868139  RX Vref Scan: 0

 8011 23:06:34.870546  

 8012 23:06:34.870962  RX Vref 0 -> 0, step: 1

 8013 23:06:34.871296  

 8014 23:06:34.873544  RX Delay 0 -> 252, step: 8

 8015 23:06:34.877190  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8016 23:06:34.881160  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8017 23:06:34.887518  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8018 23:06:34.891232  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8019 23:06:34.893904  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8020 23:06:34.897738  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8021 23:06:34.900758  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8022 23:06:34.907313  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8023 23:06:34.910641  iDelay=200, Bit 8, Center 123 (72 ~ 175) 104

 8024 23:06:34.913699  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8025 23:06:34.917365  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8026 23:06:34.920695  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8027 23:06:34.927348  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8028 23:06:34.930492  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 8029 23:06:34.933808  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8030 23:06:34.937085  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8031 23:06:34.937695  ==

 8032 23:06:34.940689  Dram Type= 6, Freq= 0, CH_0, rank 1

 8033 23:06:34.947605  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8034 23:06:34.948185  ==

 8035 23:06:34.948568  DQS Delay:

 8036 23:06:34.948906  DQS0 = 0, DQS1 = 0

 8037 23:06:34.950365  DQM Delay:

 8038 23:06:34.950823  DQM0 = 137, DQM1 = 131

 8039 23:06:34.953663  DQ Delay:

 8040 23:06:34.957047  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8041 23:06:34.960676  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8042 23:06:34.963626  DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123

 8043 23:06:34.967253  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139

 8044 23:06:34.967766  

 8045 23:06:34.968091  

 8046 23:06:34.968438  ==

 8047 23:06:34.970360  Dram Type= 6, Freq= 0, CH_0, rank 1

 8048 23:06:34.973891  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8049 23:06:34.974479  ==

 8050 23:06:34.977248  

 8051 23:06:34.977699  

 8052 23:06:34.978031  	TX Vref Scan disable

 8053 23:06:34.980462   == TX Byte 0 ==

 8054 23:06:34.983780  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 8055 23:06:34.987205  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 8056 23:06:34.990138   == TX Byte 1 ==

 8057 23:06:34.993758  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8058 23:06:34.996937  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8059 23:06:34.997455  ==

 8060 23:06:35.000460  Dram Type= 6, Freq= 0, CH_0, rank 1

 8061 23:06:35.006854  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8062 23:06:35.007362  ==

 8063 23:06:35.019412  

 8064 23:06:35.022905  TX Vref early break, caculate TX vref

 8065 23:06:35.026667  TX Vref=16, minBit 3, minWin=23, winSum=390

 8066 23:06:35.029239  TX Vref=18, minBit 1, minWin=23, winSum=397

 8067 23:06:35.032607  TX Vref=20, minBit 0, minWin=24, winSum=406

 8068 23:06:35.035763  TX Vref=22, minBit 1, minWin=24, winSum=413

 8069 23:06:35.039231  TX Vref=24, minBit 0, minWin=25, winSum=417

 8070 23:06:35.045776  TX Vref=26, minBit 1, minWin=26, winSum=431

 8071 23:06:35.049347  TX Vref=28, minBit 1, minWin=25, winSum=425

 8072 23:06:35.052811  TX Vref=30, minBit 0, minWin=25, winSum=419

 8073 23:06:35.056020  TX Vref=32, minBit 0, minWin=25, winSum=413

 8074 23:06:35.059367  TX Vref=34, minBit 7, minWin=24, winSum=400

 8075 23:06:35.066349  [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 26

 8076 23:06:35.066914  

 8077 23:06:35.069423  Final TX Range 0 Vref 26

 8078 23:06:35.069980  

 8079 23:06:35.070352  ==

 8080 23:06:35.072758  Dram Type= 6, Freq= 0, CH_0, rank 1

 8081 23:06:35.075902  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8082 23:06:35.076435  ==

 8083 23:06:35.076777  

 8084 23:06:35.077181  

 8085 23:06:35.079508  	TX Vref Scan disable

 8086 23:06:35.085987  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8087 23:06:35.086542   == TX Byte 0 ==

 8088 23:06:35.089130  u2DelayCellOfst[0]=10 cells (3 PI)

 8089 23:06:35.092223  u2DelayCellOfst[1]=13 cells (4 PI)

 8090 23:06:35.095959  u2DelayCellOfst[2]=6 cells (2 PI)

 8091 23:06:35.099435  u2DelayCellOfst[3]=6 cells (2 PI)

 8092 23:06:35.102100  u2DelayCellOfst[4]=3 cells (1 PI)

 8093 23:06:35.106059  u2DelayCellOfst[5]=0 cells (0 PI)

 8094 23:06:35.108952  u2DelayCellOfst[6]=10 cells (3 PI)

 8095 23:06:35.109496  u2DelayCellOfst[7]=13 cells (4 PI)

 8096 23:06:35.115903  Update DQ  dly =990 (3 ,6, 30)  DQ  OEN =(3 ,3)

 8097 23:06:35.119197  Update DQM dly =992 (3 ,6, 32)  DQM OEN =(3 ,3)

 8098 23:06:35.119622   == TX Byte 1 ==

 8099 23:06:35.122115  u2DelayCellOfst[8]=0 cells (0 PI)

 8100 23:06:35.126064  u2DelayCellOfst[9]=0 cells (0 PI)

 8101 23:06:35.129079  u2DelayCellOfst[10]=6 cells (2 PI)

 8102 23:06:35.132701  u2DelayCellOfst[11]=3 cells (1 PI)

 8103 23:06:35.135553  u2DelayCellOfst[12]=10 cells (3 PI)

 8104 23:06:35.138591  u2DelayCellOfst[13]=13 cells (4 PI)

 8105 23:06:35.142603  u2DelayCellOfst[14]=17 cells (5 PI)

 8106 23:06:35.145883  u2DelayCellOfst[15]=10 cells (3 PI)

 8107 23:06:35.149138  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8108 23:06:35.155420  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8109 23:06:35.155936  DramC Write-DBI on

 8110 23:06:35.156272  ==

 8111 23:06:35.158547  Dram Type= 6, Freq= 0, CH_0, rank 1

 8112 23:06:35.162102  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8113 23:06:35.162527  ==

 8114 23:06:35.165088  

 8115 23:06:35.165503  

 8116 23:06:35.165886  	TX Vref Scan disable

 8117 23:06:35.168714   == TX Byte 0 ==

 8118 23:06:35.172313  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 8119 23:06:35.175515   == TX Byte 1 ==

 8120 23:06:35.178944  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8121 23:06:35.182214  DramC Write-DBI off

 8122 23:06:35.182629  

 8123 23:06:35.182956  [DATLAT]

 8124 23:06:35.183261  Freq=1600, CH0 RK1

 8125 23:06:35.183561  

 8126 23:06:35.185149  DATLAT Default: 0xf

 8127 23:06:35.185561  0, 0xFFFF, sum = 0

 8128 23:06:35.188385  1, 0xFFFF, sum = 0

 8129 23:06:35.191909  2, 0xFFFF, sum = 0

 8130 23:06:35.192442  3, 0xFFFF, sum = 0

 8131 23:06:35.195284  4, 0xFFFF, sum = 0

 8132 23:06:35.195705  5, 0xFFFF, sum = 0

 8133 23:06:35.198202  6, 0xFFFF, sum = 0

 8134 23:06:35.198624  7, 0xFFFF, sum = 0

 8135 23:06:35.201743  8, 0xFFFF, sum = 0

 8136 23:06:35.202297  9, 0xFFFF, sum = 0

 8137 23:06:35.205192  10, 0xFFFF, sum = 0

 8138 23:06:35.205657  11, 0xFFFF, sum = 0

 8139 23:06:35.207990  12, 0xFFFF, sum = 0

 8140 23:06:35.208559  13, 0xFFFF, sum = 0

 8141 23:06:35.211798  14, 0x0, sum = 1

 8142 23:06:35.212335  15, 0x0, sum = 2

 8143 23:06:35.215117  16, 0x0, sum = 3

 8144 23:06:35.215552  17, 0x0, sum = 4

 8145 23:06:35.218213  best_step = 15

 8146 23:06:35.218627  

 8147 23:06:35.218956  ==

 8148 23:06:35.221641  Dram Type= 6, Freq= 0, CH_0, rank 1

 8149 23:06:35.225141  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8150 23:06:35.225560  ==

 8151 23:06:35.228126  RX Vref Scan: 0

 8152 23:06:35.228860  

 8153 23:06:35.229457  RX Vref 0 -> 0, step: 1

 8154 23:06:35.229879  

 8155 23:06:35.231707  RX Delay 19 -> 252, step: 4

 8156 23:06:35.234567  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8157 23:06:35.241710  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8158 23:06:35.244838  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8159 23:06:35.248062  iDelay=191, Bit 3, Center 134 (83 ~ 186) 104

 8160 23:06:35.251300  iDelay=191, Bit 4, Center 134 (83 ~ 186) 104

 8161 23:06:35.254787  iDelay=191, Bit 5, Center 124 (71 ~ 178) 108

 8162 23:06:35.261728  iDelay=191, Bit 6, Center 138 (87 ~ 190) 104

 8163 23:06:35.264823  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8164 23:06:35.268354  iDelay=191, Bit 8, Center 120 (71 ~ 170) 100

 8165 23:06:35.271099  iDelay=191, Bit 9, Center 116 (67 ~ 166) 100

 8166 23:06:35.274786  iDelay=191, Bit 10, Center 126 (75 ~ 178) 104

 8167 23:06:35.281547  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8168 23:06:35.285116  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8169 23:06:35.288449  iDelay=191, Bit 13, Center 132 (83 ~ 182) 100

 8170 23:06:35.291580  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8171 23:06:35.295107  iDelay=191, Bit 15, Center 134 (87 ~ 182) 96

 8172 23:06:35.298140  ==

 8173 23:06:35.301531  Dram Type= 6, Freq= 0, CH_0, rank 1

 8174 23:06:35.305111  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8175 23:06:35.305728  ==

 8176 23:06:35.306103  DQS Delay:

 8177 23:06:35.308099  DQS0 = 0, DQS1 = 0

 8178 23:06:35.308652  DQM Delay:

 8179 23:06:35.310995  DQM0 = 134, DQM1 = 126

 8180 23:06:35.311450  DQ Delay:

 8181 23:06:35.314262  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134

 8182 23:06:35.317900  DQ4 =134, DQ5 =124, DQ6 =138, DQ7 =140

 8183 23:06:35.321111  DQ8 =120, DQ9 =116, DQ10 =126, DQ11 =118

 8184 23:06:35.324329  DQ12 =134, DQ13 =132, DQ14 =134, DQ15 =134

 8185 23:06:35.324744  

 8186 23:06:35.325069  

 8187 23:06:35.325374  

 8188 23:06:35.327641  [DramC_TX_OE_Calibration] TA2

 8189 23:06:35.331352  Original DQ_B0 (3 6) =30, OEN = 27

 8190 23:06:35.334705  Original DQ_B1 (3 6) =30, OEN = 27

 8191 23:06:35.337675  24, 0x0, End_B0=24 End_B1=24

 8192 23:06:35.341260  25, 0x0, End_B0=25 End_B1=25

 8193 23:06:35.341868  26, 0x0, End_B0=26 End_B1=26

 8194 23:06:35.344654  27, 0x0, End_B0=27 End_B1=27

 8195 23:06:35.347567  28, 0x0, End_B0=28 End_B1=28

 8196 23:06:35.350913  29, 0x0, End_B0=29 End_B1=29

 8197 23:06:35.354242  30, 0x0, End_B0=30 End_B1=30

 8198 23:06:35.354758  31, 0x4141, End_B0=30 End_B1=30

 8199 23:06:35.357741  Byte0 end_step=30  best_step=27

 8200 23:06:35.360961  Byte1 end_step=30  best_step=27

 8201 23:06:35.364499  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8202 23:06:35.367987  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8203 23:06:35.368543  

 8204 23:06:35.368903  

 8205 23:06:35.374504  [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps

 8206 23:06:35.377372  CH0 RK1: MR19=303, MR18=2008

 8207 23:06:35.383820  CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15

 8208 23:06:35.387568  [RxdqsGatingPostProcess] freq 1600

 8209 23:06:35.394295  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8210 23:06:35.394915  best DQS0 dly(2T, 0.5T) = (1, 1)

 8211 23:06:35.397108  best DQS1 dly(2T, 0.5T) = (1, 1)

 8212 23:06:35.400956  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8213 23:06:35.404451  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8214 23:06:35.407792  best DQS0 dly(2T, 0.5T) = (1, 1)

 8215 23:06:35.410423  best DQS1 dly(2T, 0.5T) = (1, 1)

 8216 23:06:35.414217  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8217 23:06:35.417439  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8218 23:06:35.420913  Pre-setting of DQS Precalculation

 8219 23:06:35.424323  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8220 23:06:35.424874  ==

 8221 23:06:35.427051  Dram Type= 6, Freq= 0, CH_1, rank 0

 8222 23:06:35.434203  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8223 23:06:35.434664  ==

 8224 23:06:35.437336  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8225 23:06:35.444073  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8226 23:06:35.447607  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8227 23:06:35.454061  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8228 23:06:35.461445  [CA 0] Center 42 (13~72) winsize 60

 8229 23:06:35.465088  [CA 1] Center 42 (13~72) winsize 60

 8230 23:06:35.468651  [CA 2] Center 39 (9~69) winsize 61

 8231 23:06:35.471451  [CA 3] Center 38 (9~67) winsize 59

 8232 23:06:35.474783  [CA 4] Center 39 (10~68) winsize 59

 8233 23:06:35.478225  [CA 5] Center 37 (8~67) winsize 60

 8234 23:06:35.478798  

 8235 23:06:35.481720  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8236 23:06:35.482272  

 8237 23:06:35.485006  [CATrainingPosCal] consider 1 rank data

 8238 23:06:35.488496  u2DelayCellTimex100 = 285/100 ps

 8239 23:06:35.494571  CA0 delay=42 (13~72),Diff = 5 PI (17 cell)

 8240 23:06:35.498359  CA1 delay=42 (13~72),Diff = 5 PI (17 cell)

 8241 23:06:35.501532  CA2 delay=39 (9~69),Diff = 2 PI (6 cell)

 8242 23:06:35.504808  CA3 delay=38 (9~67),Diff = 1 PI (3 cell)

 8243 23:06:35.508226  CA4 delay=39 (10~68),Diff = 2 PI (6 cell)

 8244 23:06:35.511456  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8245 23:06:35.511915  

 8246 23:06:35.514494  CA PerBit enable=1, Macro0, CA PI delay=37

 8247 23:06:35.514951  

 8248 23:06:35.518329  [CBTSetCACLKResult] CA Dly = 37

 8249 23:06:35.521264  CS Dly: 11 (0~42)

 8250 23:06:35.524757  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8251 23:06:35.528576  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8252 23:06:35.529133  ==

 8253 23:06:35.531533  Dram Type= 6, Freq= 0, CH_1, rank 1

 8254 23:06:35.535161  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8255 23:06:35.538536  ==

 8256 23:06:35.541511  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8257 23:06:35.544961  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8258 23:06:35.551646  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8259 23:06:35.554968  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8260 23:06:35.565259  [CA 0] Center 42 (12~72) winsize 61

 8261 23:06:35.568620  [CA 1] Center 42 (13~71) winsize 59

 8262 23:06:35.571558  [CA 2] Center 38 (9~68) winsize 60

 8263 23:06:35.574956  [CA 3] Center 37 (8~67) winsize 60

 8264 23:06:35.578357  [CA 4] Center 38 (8~68) winsize 61

 8265 23:06:35.581573  [CA 5] Center 37 (8~67) winsize 60

 8266 23:06:35.582183  

 8267 23:06:35.585223  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 8268 23:06:35.585830  

 8269 23:06:35.588581  [CATrainingPosCal] consider 2 rank data

 8270 23:06:35.591369  u2DelayCellTimex100 = 285/100 ps

 8271 23:06:35.594851  CA0 delay=42 (13~72),Diff = 5 PI (17 cell)

 8272 23:06:35.601496  CA1 delay=42 (13~71),Diff = 5 PI (17 cell)

 8273 23:06:35.604866  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8274 23:06:35.608250  CA3 delay=38 (9~67),Diff = 1 PI (3 cell)

 8275 23:06:35.611702  CA4 delay=39 (10~68),Diff = 2 PI (6 cell)

 8276 23:06:35.615080  CA5 delay=37 (8~67),Diff = 0 PI (0 cell)

 8277 23:06:35.615641  

 8278 23:06:35.618837  CA PerBit enable=1, Macro0, CA PI delay=37

 8279 23:06:35.619397  

 8280 23:06:35.621763  [CBTSetCACLKResult] CA Dly = 37

 8281 23:06:35.625044  CS Dly: 12 (0~44)

 8282 23:06:35.628650  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8283 23:06:35.631997  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8284 23:06:35.632548  

 8285 23:06:35.634931  ----->DramcWriteLeveling(PI) begin...

 8286 23:06:35.635493  ==

 8287 23:06:35.638476  Dram Type= 6, Freq= 0, CH_1, rank 0

 8288 23:06:35.641752  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8289 23:06:35.645335  ==

 8290 23:06:35.645932  Write leveling (Byte 0): 26 => 26

 8291 23:06:35.648049  Write leveling (Byte 1): 28 => 28

 8292 23:06:35.651177  DramcWriteLeveling(PI) end<-----

 8293 23:06:35.651628  

 8294 23:06:35.651982  ==

 8295 23:06:35.654734  Dram Type= 6, Freq= 0, CH_1, rank 0

 8296 23:06:35.661293  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8297 23:06:35.661766  ==

 8298 23:06:35.662107  [Gating] SW mode calibration

 8299 23:06:35.671556  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8300 23:06:35.674512  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8301 23:06:35.681282   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8302 23:06:35.684630   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8303 23:06:35.688210   1  4  8 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)

 8304 23:06:35.691756   1  4 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)

 8305 23:06:35.698165   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8306 23:06:35.701616   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8307 23:06:35.704409   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8308 23:06:35.711388   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8309 23:06:35.714398   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8310 23:06:35.717681   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8311 23:06:35.724335   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)

 8312 23:06:35.728447   1  5 12 | B1->B0 | 2424 2323 | 0 0 | (0 1) (1 0)

 8313 23:06:35.731371   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 8314 23:06:35.737819   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8315 23:06:35.741481   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8316 23:06:35.744420   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8317 23:06:35.751095   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8318 23:06:35.754447   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8319 23:06:35.758002   1  6  8 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (0 0)

 8320 23:06:35.764369   1  6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8321 23:06:35.768020   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8322 23:06:35.771331   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8323 23:06:35.778320   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8324 23:06:35.781120   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8325 23:06:35.784397   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8326 23:06:35.791090   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8327 23:06:35.794423   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8328 23:06:35.797664   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8329 23:06:35.803964   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8330 23:06:35.807729   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8331 23:06:35.810785   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8332 23:06:35.817421   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8333 23:06:35.821309   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8334 23:06:35.824594   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8335 23:06:35.830754   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8336 23:06:35.834621   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8337 23:06:35.837339   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8338 23:06:35.843679   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8339 23:06:35.847290   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8340 23:06:35.850609   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8341 23:06:35.854197   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8342 23:06:35.860394   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8343 23:06:35.864066   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8344 23:06:35.866914   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8345 23:06:35.873824   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8346 23:06:35.877275  Total UI for P1: 0, mck2ui 16

 8347 23:06:35.880755  best dqsien dly found for B0: ( 1,  9, 12)

 8348 23:06:35.883757  Total UI for P1: 0, mck2ui 16

 8349 23:06:35.887117  best dqsien dly found for B1: ( 1,  9, 10)

 8350 23:06:35.890455  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8351 23:06:35.893227  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8352 23:06:35.893733  

 8353 23:06:35.896543  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8354 23:06:35.900286  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8355 23:06:35.904051  [Gating] SW calibration Done

 8356 23:06:35.904600  ==

 8357 23:06:35.906663  Dram Type= 6, Freq= 0, CH_1, rank 0

 8358 23:06:35.910404  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8359 23:06:35.910959  ==

 8360 23:06:35.913977  RX Vref Scan: 0

 8361 23:06:35.914536  

 8362 23:06:35.916700  RX Vref 0 -> 0, step: 1

 8363 23:06:35.917265  

 8364 23:06:35.917688  RX Delay 0 -> 252, step: 8

 8365 23:06:35.923464  iDelay=200, Bit 0, Center 143 (96 ~ 191) 96

 8366 23:06:35.926405  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8367 23:06:35.930012  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8368 23:06:35.933516  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8369 23:06:35.936641  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8370 23:06:35.943244  iDelay=200, Bit 5, Center 151 (104 ~ 199) 96

 8371 23:06:35.946803  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8372 23:06:35.949614  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8373 23:06:35.953226  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8374 23:06:35.956856  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8375 23:06:35.963181  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8376 23:06:35.966365  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8377 23:06:35.969697  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8378 23:06:35.972993  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8379 23:06:35.976558  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8380 23:06:35.982818  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8381 23:06:35.983413  ==

 8382 23:06:35.986466  Dram Type= 6, Freq= 0, CH_1, rank 0

 8383 23:06:35.989679  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8384 23:06:35.990247  ==

 8385 23:06:35.990608  DQS Delay:

 8386 23:06:35.993194  DQS0 = 0, DQS1 = 0

 8387 23:06:35.993796  DQM Delay:

 8388 23:06:35.996314  DQM0 = 137, DQM1 = 132

 8389 23:06:35.996786  DQ Delay:

 8390 23:06:35.999520  DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135

 8391 23:06:36.002681  DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135

 8392 23:06:36.005978  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127

 8393 23:06:36.009766  DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139

 8394 23:06:36.012535  

 8395 23:06:36.012985  

 8396 23:06:36.013338  ==

 8397 23:06:36.016163  Dram Type= 6, Freq= 0, CH_1, rank 0

 8398 23:06:36.019444  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8399 23:06:36.020009  ==

 8400 23:06:36.020370  

 8401 23:06:36.020702  

 8402 23:06:36.022827  	TX Vref Scan disable

 8403 23:06:36.023385   == TX Byte 0 ==

 8404 23:06:36.029552  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8405 23:06:36.033023  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8406 23:06:36.033726   == TX Byte 1 ==

 8407 23:06:36.039461  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8408 23:06:36.042337  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8409 23:06:36.042811  ==

 8410 23:06:36.046010  Dram Type= 6, Freq= 0, CH_1, rank 0

 8411 23:06:36.049432  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8412 23:06:36.050004  ==

 8413 23:06:36.063820  

 8414 23:06:36.066683  TX Vref early break, caculate TX vref

 8415 23:06:36.070631  TX Vref=16, minBit 0, minWin=23, winSum=375

 8416 23:06:36.073448  TX Vref=18, minBit 1, minWin=23, winSum=382

 8417 23:06:36.077093  TX Vref=20, minBit 0, minWin=24, winSum=399

 8418 23:06:36.080336  TX Vref=22, minBit 0, minWin=24, winSum=404

 8419 23:06:36.083298  TX Vref=24, minBit 0, minWin=25, winSum=413

 8420 23:06:36.089913  TX Vref=26, minBit 0, minWin=25, winSum=425

 8421 23:06:36.093830  TX Vref=28, minBit 0, minWin=25, winSum=423

 8422 23:06:36.096663  TX Vref=30, minBit 0, minWin=25, winSum=421

 8423 23:06:36.100071  TX Vref=32, minBit 0, minWin=24, winSum=411

 8424 23:06:36.103435  TX Vref=34, minBit 0, minWin=24, winSum=403

 8425 23:06:36.106841  TX Vref=36, minBit 0, minWin=23, winSum=388

 8426 23:06:36.113444  [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26

 8427 23:06:36.113931  

 8428 23:06:36.116742  Final TX Range 0 Vref 26

 8429 23:06:36.117346  

 8430 23:06:36.117738  ==

 8431 23:06:36.119832  Dram Type= 6, Freq= 0, CH_1, rank 0

 8432 23:06:36.123589  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8433 23:06:36.124106  ==

 8434 23:06:36.124440  

 8435 23:06:36.124740  

 8436 23:06:36.127307  	TX Vref Scan disable

 8437 23:06:36.133886  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8438 23:06:36.134405   == TX Byte 0 ==

 8439 23:06:36.136696  u2DelayCellOfst[0]=17 cells (5 PI)

 8440 23:06:36.140393  u2DelayCellOfst[1]=10 cells (3 PI)

 8441 23:06:36.143652  u2DelayCellOfst[2]=0 cells (0 PI)

 8442 23:06:36.146520  u2DelayCellOfst[3]=6 cells (2 PI)

 8443 23:06:36.150530  u2DelayCellOfst[4]=6 cells (2 PI)

 8444 23:06:36.153769  u2DelayCellOfst[5]=17 cells (5 PI)

 8445 23:06:36.157399  u2DelayCellOfst[6]=17 cells (5 PI)

 8446 23:06:36.157962  u2DelayCellOfst[7]=3 cells (1 PI)

 8447 23:06:36.163869  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8448 23:06:36.166631  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8449 23:06:36.170562   == TX Byte 1 ==

 8450 23:06:36.171084  u2DelayCellOfst[8]=0 cells (0 PI)

 8451 23:06:36.174177  u2DelayCellOfst[9]=3 cells (1 PI)

 8452 23:06:36.176868  u2DelayCellOfst[10]=13 cells (4 PI)

 8453 23:06:36.179817  u2DelayCellOfst[11]=3 cells (1 PI)

 8454 23:06:36.183737  u2DelayCellOfst[12]=13 cells (4 PI)

 8455 23:06:36.187126  u2DelayCellOfst[13]=17 cells (5 PI)

 8456 23:06:36.189988  u2DelayCellOfst[14]=17 cells (5 PI)

 8457 23:06:36.193459  u2DelayCellOfst[15]=17 cells (5 PI)

 8458 23:06:36.196789  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8459 23:06:36.203610  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8460 23:06:36.204165  DramC Write-DBI on

 8461 23:06:36.204533  ==

 8462 23:06:36.206255  Dram Type= 6, Freq= 0, CH_1, rank 0

 8463 23:06:36.210271  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8464 23:06:36.213015  ==

 8465 23:06:36.213489  

 8466 23:06:36.213935  

 8467 23:06:36.214274  	TX Vref Scan disable

 8468 23:06:36.216640   == TX Byte 0 ==

 8469 23:06:36.220051  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8470 23:06:36.223746   == TX Byte 1 ==

 8471 23:06:36.226324  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8472 23:06:36.230095  DramC Write-DBI off

 8473 23:06:36.230654  

 8474 23:06:36.231014  [DATLAT]

 8475 23:06:36.231349  Freq=1600, CH1 RK0

 8476 23:06:36.231670  

 8477 23:06:36.233377  DATLAT Default: 0xf

 8478 23:06:36.233893  0, 0xFFFF, sum = 0

 8479 23:06:36.236499  1, 0xFFFF, sum = 0

 8480 23:06:36.237059  2, 0xFFFF, sum = 0

 8481 23:06:36.239949  3, 0xFFFF, sum = 0

 8482 23:06:36.242873  4, 0xFFFF, sum = 0

 8483 23:06:36.243369  5, 0xFFFF, sum = 0

 8484 23:06:36.246697  6, 0xFFFF, sum = 0

 8485 23:06:36.247412  7, 0xFFFF, sum = 0

 8486 23:06:36.249659  8, 0xFFFF, sum = 0

 8487 23:06:36.250151  9, 0xFFFF, sum = 0

 8488 23:06:36.252850  10, 0xFFFF, sum = 0

 8489 23:06:36.253272  11, 0xFFFF, sum = 0

 8490 23:06:36.256217  12, 0xFFFF, sum = 0

 8491 23:06:36.257041  13, 0xFFFF, sum = 0

 8492 23:06:36.259334  14, 0x0, sum = 1

 8493 23:06:36.259803  15, 0x0, sum = 2

 8494 23:06:36.263221  16, 0x0, sum = 3

 8495 23:06:36.263836  17, 0x0, sum = 4

 8496 23:06:36.266124  best_step = 15

 8497 23:06:36.266714  

 8498 23:06:36.267266  ==

 8499 23:06:36.269493  Dram Type= 6, Freq= 0, CH_1, rank 0

 8500 23:06:36.273262  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8501 23:06:36.273876  ==

 8502 23:06:36.276206  RX Vref Scan: 1

 8503 23:06:36.276748  

 8504 23:06:36.277218  Set Vref Range= 24 -> 127

 8505 23:06:36.277698  

 8506 23:06:36.279666  RX Vref 24 -> 127, step: 1

 8507 23:06:36.280081  

 8508 23:06:36.282731  RX Delay 27 -> 252, step: 4

 8509 23:06:36.283147  

 8510 23:06:36.286395  Set Vref, RX VrefLevel [Byte0]: 24

 8511 23:06:36.289320                           [Byte1]: 24

 8512 23:06:36.289835  

 8513 23:06:36.293051  Set Vref, RX VrefLevel [Byte0]: 25

 8514 23:06:36.296154                           [Byte1]: 25

 8515 23:06:36.296569  

 8516 23:06:36.299556  Set Vref, RX VrefLevel [Byte0]: 26

 8517 23:06:36.303007                           [Byte1]: 26

 8518 23:06:36.306568  

 8519 23:06:36.307081  Set Vref, RX VrefLevel [Byte0]: 27

 8520 23:06:36.310148                           [Byte1]: 27

 8521 23:06:36.314511  

 8522 23:06:36.314957  Set Vref, RX VrefLevel [Byte0]: 28

 8523 23:06:36.317436                           [Byte1]: 28

 8524 23:06:36.321928  

 8525 23:06:36.322429  Set Vref, RX VrefLevel [Byte0]: 29

 8526 23:06:36.324892                           [Byte1]: 29

 8527 23:06:36.329297  

 8528 23:06:36.329872  Set Vref, RX VrefLevel [Byte0]: 30

 8529 23:06:36.332849                           [Byte1]: 30

 8530 23:06:36.337120  

 8531 23:06:36.337681  Set Vref, RX VrefLevel [Byte0]: 31

 8532 23:06:36.340123                           [Byte1]: 31

 8533 23:06:36.344860  

 8534 23:06:36.345372  Set Vref, RX VrefLevel [Byte0]: 32

 8535 23:06:36.347811                           [Byte1]: 32

 8536 23:06:36.351578  

 8537 23:06:36.351990  Set Vref, RX VrefLevel [Byte0]: 33

 8538 23:06:36.355302                           [Byte1]: 33

 8539 23:06:36.359760  

 8540 23:06:36.360273  Set Vref, RX VrefLevel [Byte0]: 34

 8541 23:06:36.362471                           [Byte1]: 34

 8542 23:06:36.366921  

 8543 23:06:36.367375  Set Vref, RX VrefLevel [Byte0]: 35

 8544 23:06:36.370404                           [Byte1]: 35

 8545 23:06:36.374358  

 8546 23:06:36.374890  Set Vref, RX VrefLevel [Byte0]: 36

 8547 23:06:36.377734                           [Byte1]: 36

 8548 23:06:36.381987  

 8549 23:06:36.382445  Set Vref, RX VrefLevel [Byte0]: 37

 8550 23:06:36.385232                           [Byte1]: 37

 8551 23:06:36.389735  

 8552 23:06:36.390277  Set Vref, RX VrefLevel [Byte0]: 38

 8553 23:06:36.392841                           [Byte1]: 38

 8554 23:06:36.396766  

 8555 23:06:36.397266  Set Vref, RX VrefLevel [Byte0]: 39

 8556 23:06:36.400317                           [Byte1]: 39

 8557 23:06:36.404750  

 8558 23:06:36.405260  Set Vref, RX VrefLevel [Byte0]: 40

 8559 23:06:36.408290                           [Byte1]: 40

 8560 23:06:36.412554  

 8561 23:06:36.413140  Set Vref, RX VrefLevel [Byte0]: 41

 8562 23:06:36.415224                           [Byte1]: 41

 8563 23:06:36.419811  

 8564 23:06:36.420265  Set Vref, RX VrefLevel [Byte0]: 42

 8565 23:06:36.423492                           [Byte1]: 42

 8566 23:06:36.427223  

 8567 23:06:36.427680  Set Vref, RX VrefLevel [Byte0]: 43

 8568 23:06:36.430598                           [Byte1]: 43

 8569 23:06:36.435038  

 8570 23:06:36.435587  Set Vref, RX VrefLevel [Byte0]: 44

 8571 23:06:36.438528                           [Byte1]: 44

 8572 23:06:36.442607  

 8573 23:06:36.443158  Set Vref, RX VrefLevel [Byte0]: 45

 8574 23:06:36.445531                           [Byte1]: 45

 8575 23:06:36.449772  

 8576 23:06:36.450319  Set Vref, RX VrefLevel [Byte0]: 46

 8577 23:06:36.456507                           [Byte1]: 46

 8578 23:06:36.457057  

 8579 23:06:36.459601  Set Vref, RX VrefLevel [Byte0]: 47

 8580 23:06:36.462820                           [Byte1]: 47

 8581 23:06:36.463293  

 8582 23:06:36.466375  Set Vref, RX VrefLevel [Byte0]: 48

 8583 23:06:36.469955                           [Byte1]: 48

 8584 23:06:36.470521  

 8585 23:06:36.472612  Set Vref, RX VrefLevel [Byte0]: 49

 8586 23:06:36.476289                           [Byte1]: 49

 8587 23:06:36.479983  

 8588 23:06:36.480532  Set Vref, RX VrefLevel [Byte0]: 50

 8589 23:06:36.483358                           [Byte1]: 50

 8590 23:06:36.487843  

 8591 23:06:36.488392  Set Vref, RX VrefLevel [Byte0]: 51

 8592 23:06:36.491099                           [Byte1]: 51

 8593 23:06:36.495223  

 8594 23:06:36.495782  Set Vref, RX VrefLevel [Byte0]: 52

 8595 23:06:36.498270                           [Byte1]: 52

 8596 23:06:36.502563  

 8597 23:06:36.503111  Set Vref, RX VrefLevel [Byte0]: 53

 8598 23:06:36.505986                           [Byte1]: 53

 8599 23:06:36.510268  

 8600 23:06:36.510813  Set Vref, RX VrefLevel [Byte0]: 54

 8601 23:06:36.513204                           [Byte1]: 54

 8602 23:06:36.517523  

 8603 23:06:36.518244  Set Vref, RX VrefLevel [Byte0]: 55

 8604 23:06:36.520867                           [Byte1]: 55

 8605 23:06:36.525242  

 8606 23:06:36.525917  Set Vref, RX VrefLevel [Byte0]: 56

 8607 23:06:36.528497                           [Byte1]: 56

 8608 23:06:36.532841  

 8609 23:06:36.533392  Set Vref, RX VrefLevel [Byte0]: 57

 8610 23:06:36.536083                           [Byte1]: 57

 8611 23:06:36.540735  

 8612 23:06:36.541285  Set Vref, RX VrefLevel [Byte0]: 58

 8613 23:06:36.543421                           [Byte1]: 58

 8614 23:06:36.547776  

 8615 23:06:36.548330  Set Vref, RX VrefLevel [Byte0]: 59

 8616 23:06:36.551421                           [Byte1]: 59

 8617 23:06:36.555808  

 8618 23:06:36.556363  Set Vref, RX VrefLevel [Byte0]: 60

 8619 23:06:36.558539                           [Byte1]: 60

 8620 23:06:36.562660  

 8621 23:06:36.563212  Set Vref, RX VrefLevel [Byte0]: 61

 8622 23:06:36.566413                           [Byte1]: 61

 8623 23:06:36.570434  

 8624 23:06:36.570990  Set Vref, RX VrefLevel [Byte0]: 62

 8625 23:06:36.574013                           [Byte1]: 62

 8626 23:06:36.577813  

 8627 23:06:36.578362  Set Vref, RX VrefLevel [Byte0]: 63

 8628 23:06:36.581667                           [Byte1]: 63

 8629 23:06:36.585649  

 8630 23:06:36.586226  Set Vref, RX VrefLevel [Byte0]: 64

 8631 23:06:36.589063                           [Byte1]: 64

 8632 23:06:36.593310  

 8633 23:06:36.593907  Set Vref, RX VrefLevel [Byte0]: 65

 8634 23:06:36.596361                           [Byte1]: 65

 8635 23:06:36.600505  

 8636 23:06:36.601053  Set Vref, RX VrefLevel [Byte0]: 66

 8637 23:06:36.604162                           [Byte1]: 66

 8638 23:06:36.608212  

 8639 23:06:36.608779  Set Vref, RX VrefLevel [Byte0]: 67

 8640 23:06:36.611835                           [Byte1]: 67

 8641 23:06:36.615917  

 8642 23:06:36.616463  Set Vref, RX VrefLevel [Byte0]: 68

 8643 23:06:36.618707                           [Byte1]: 68

 8644 23:06:36.622884  

 8645 23:06:36.623431  Set Vref, RX VrefLevel [Byte0]: 69

 8646 23:06:36.626298                           [Byte1]: 69

 8647 23:06:36.630550  

 8648 23:06:36.631109  Set Vref, RX VrefLevel [Byte0]: 70

 8649 23:06:36.633831                           [Byte1]: 70

 8650 23:06:36.638214  

 8651 23:06:36.638705  Set Vref, RX VrefLevel [Byte0]: 71

 8652 23:06:36.641459                           [Byte1]: 71

 8653 23:06:36.645656  

 8654 23:06:36.646117  Set Vref, RX VrefLevel [Byte0]: 72

 8655 23:06:36.649069                           [Byte1]: 72

 8656 23:06:36.653329  

 8657 23:06:36.653952  Set Vref, RX VrefLevel [Byte0]: 73

 8658 23:06:36.656554                           [Byte1]: 73

 8659 23:06:36.661125  

 8660 23:06:36.661715  Final RX Vref Byte 0 = 60 to rank0

 8661 23:06:36.663844  Final RX Vref Byte 1 = 58 to rank0

 8662 23:06:36.667346  Final RX Vref Byte 0 = 60 to rank1

 8663 23:06:36.670931  Final RX Vref Byte 1 = 58 to rank1==

 8664 23:06:36.674364  Dram Type= 6, Freq= 0, CH_1, rank 0

 8665 23:06:36.681191  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8666 23:06:36.681850  ==

 8667 23:06:36.682234  DQS Delay:

 8668 23:06:36.682574  DQS0 = 0, DQS1 = 0

 8669 23:06:36.684251  DQM Delay:

 8670 23:06:36.684708  DQM0 = 134, DQM1 = 131

 8671 23:06:36.687515  DQ Delay:

 8672 23:06:36.691249  DQ0 =140, DQ1 =130, DQ2 =120, DQ3 =130

 8673 23:06:36.694216  DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132

 8674 23:06:36.697266  DQ8 =118, DQ9 =122, DQ10 =132, DQ11 =122

 8675 23:06:36.700560  DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140

 8676 23:06:36.701106  

 8677 23:06:36.701472  

 8678 23:06:36.701860  

 8679 23:06:36.704201  [DramC_TX_OE_Calibration] TA2

 8680 23:06:36.706940  Original DQ_B0 (3 6) =30, OEN = 27

 8681 23:06:36.710682  Original DQ_B1 (3 6) =30, OEN = 27

 8682 23:06:36.713964  24, 0x0, End_B0=24 End_B1=24

 8683 23:06:36.714432  25, 0x0, End_B0=25 End_B1=25

 8684 23:06:36.717085  26, 0x0, End_B0=26 End_B1=26

 8685 23:06:36.720798  27, 0x0, End_B0=27 End_B1=27

 8686 23:06:36.723777  28, 0x0, End_B0=28 End_B1=28

 8687 23:06:36.727305  29, 0x0, End_B0=29 End_B1=29

 8688 23:06:36.727868  30, 0x0, End_B0=30 End_B1=30

 8689 23:06:36.730213  31, 0x4141, End_B0=30 End_B1=30

 8690 23:06:36.734029  Byte0 end_step=30  best_step=27

 8691 23:06:36.737043  Byte1 end_step=30  best_step=27

 8692 23:06:36.740622  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8693 23:06:36.743991  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8694 23:06:36.744548  

 8695 23:06:36.744911  

 8696 23:06:36.750242  [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 8697 23:06:36.753786  CH1 RK0: MR19=303, MR18=1624

 8698 23:06:36.760505  CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16

 8699 23:06:36.761065  

 8700 23:06:36.763363  ----->DramcWriteLeveling(PI) begin...

 8701 23:06:36.763829  ==

 8702 23:06:36.766522  Dram Type= 6, Freq= 0, CH_1, rank 1

 8703 23:06:36.770325  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8704 23:06:36.770786  ==

 8705 23:06:36.773346  Write leveling (Byte 0): 25 => 25

 8706 23:06:36.776909  Write leveling (Byte 1): 29 => 29

 8707 23:06:36.780071  DramcWriteLeveling(PI) end<-----

 8708 23:06:36.780566  

 8709 23:06:36.780929  ==

 8710 23:06:36.783395  Dram Type= 6, Freq= 0, CH_1, rank 1

 8711 23:06:36.786583  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8712 23:06:36.787046  ==

 8713 23:06:36.789690  [Gating] SW mode calibration

 8714 23:06:36.796702  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8715 23:06:36.803132  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8716 23:06:36.806448   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8717 23:06:36.812964   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8718 23:06:36.816819   1  4  8 | B1->B0 | 2626 2323 | 0 0 | (1 1) (0 0)

 8719 23:06:36.819540   1  4 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 1)

 8720 23:06:36.823052   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8721 23:06:36.830081   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8722 23:06:36.833071   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8723 23:06:36.836680   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8724 23:06:36.842962   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8725 23:06:36.846281   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8726 23:06:36.849421   1  5  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 8727 23:06:36.856760   1  5 12 | B1->B0 | 2424 3030 | 0 1 | (0 0) (1 0)

 8728 23:06:36.859706   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8729 23:06:36.863216   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8730 23:06:36.869987   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8731 23:06:36.872973   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8732 23:06:36.876280   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8733 23:06:36.883071   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8734 23:06:36.885974   1  6  8 | B1->B0 | 3939 2323 | 1 0 | (0 0) (0 0)

 8735 23:06:36.889502   1  6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)

 8736 23:06:36.896633   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8737 23:06:36.899645   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8738 23:06:36.902552   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8739 23:06:36.909147   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8740 23:06:36.912555   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8741 23:06:36.915759   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8742 23:06:36.922829   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8743 23:06:36.926280   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8744 23:06:36.929292   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8745 23:06:36.935882   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8746 23:06:36.939660   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8747 23:06:36.942604   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8748 23:06:36.949516   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8749 23:06:36.952885   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8750 23:06:36.956430   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8751 23:06:36.962851   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8752 23:06:36.966340   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8753 23:06:36.969425   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8754 23:06:36.972872   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8755 23:06:36.979119   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8756 23:06:36.982493   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8757 23:06:36.985969   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 8758 23:06:36.992743   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8759 23:06:36.995635   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8760 23:06:36.999249  Total UI for P1: 0, mck2ui 16

 8761 23:06:37.002816  best dqsien dly found for B1: ( 1,  9,  6)

 8762 23:06:37.005752   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8763 23:06:37.012604   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8764 23:06:37.013147  Total UI for P1: 0, mck2ui 16

 8765 23:06:37.019369  best dqsien dly found for B0: ( 1,  9, 12)

 8766 23:06:37.022335  best DQS0 dly(MCK, UI, PI) = (1, 9, 12)

 8767 23:06:37.025795  best DQS1 dly(MCK, UI, PI) = (1, 9, 6)

 8768 23:06:37.026261  

 8769 23:06:37.029679  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)

 8770 23:06:37.032286  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)

 8771 23:06:37.036086  [Gating] SW calibration Done

 8772 23:06:37.036635  ==

 8773 23:06:37.039077  Dram Type= 6, Freq= 0, CH_1, rank 1

 8774 23:06:37.042657  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8775 23:06:37.043144  ==

 8776 23:06:37.045505  RX Vref Scan: 0

 8777 23:06:37.046013  

 8778 23:06:37.046380  RX Vref 0 -> 0, step: 1

 8779 23:06:37.046743  

 8780 23:06:37.049454  RX Delay 0 -> 252, step: 8

 8781 23:06:37.052897  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8782 23:06:37.059142  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8783 23:06:37.062501  iDelay=208, Bit 2, Center 123 (72 ~ 175) 104

 8784 23:06:37.065566  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8785 23:06:37.068765  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8786 23:06:37.072308  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8787 23:06:37.079059  iDelay=208, Bit 6, Center 143 (88 ~ 199) 112

 8788 23:06:37.082715  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8789 23:06:37.085691  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8790 23:06:37.089675  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8791 23:06:37.092118  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8792 23:06:37.099143  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8793 23:06:37.102141  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8794 23:06:37.105666  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8795 23:06:37.109244  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8796 23:06:37.112808  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8797 23:06:37.115519  ==

 8798 23:06:37.118907  Dram Type= 6, Freq= 0, CH_1, rank 1

 8799 23:06:37.122424  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8800 23:06:37.122980  ==

 8801 23:06:37.123347  DQS Delay:

 8802 23:06:37.125448  DQS0 = 0, DQS1 = 0

 8803 23:06:37.125951  DQM Delay:

 8804 23:06:37.129219  DQM0 = 136, DQM1 = 133

 8805 23:06:37.129826  DQ Delay:

 8806 23:06:37.131788  DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131

 8807 23:06:37.135545  DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135

 8808 23:06:37.138598  DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127

 8809 23:06:37.142329  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8810 23:06:37.142952  

 8811 23:06:37.143326  

 8812 23:06:37.143663  ==

 8813 23:06:37.145205  Dram Type= 6, Freq= 0, CH_1, rank 1

 8814 23:06:37.152540  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8815 23:06:37.153101  ==

 8816 23:06:37.153470  

 8817 23:06:37.153879  

 8818 23:06:37.154213  	TX Vref Scan disable

 8819 23:06:37.155806   == TX Byte 0 ==

 8820 23:06:37.158904  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8821 23:06:37.165676  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8822 23:06:37.166215   == TX Byte 1 ==

 8823 23:06:37.168821  Update DQ  dly =984 (3 ,6, 24)  DQ  OEN =(3 ,3)

 8824 23:06:37.175457  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8825 23:06:37.175998  ==

 8826 23:06:37.178696  Dram Type= 6, Freq= 0, CH_1, rank 1

 8827 23:06:37.182210  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8828 23:06:37.182692  ==

 8829 23:06:37.194842  

 8830 23:06:37.197806  TX Vref early break, caculate TX vref

 8831 23:06:37.201077  TX Vref=16, minBit 0, minWin=23, winSum=386

 8832 23:06:37.204504  TX Vref=18, minBit 0, minWin=23, winSum=391

 8833 23:06:37.207874  TX Vref=20, minBit 0, minWin=23, winSum=398

 8834 23:06:37.211353  TX Vref=22, minBit 0, minWin=25, winSum=409

 8835 23:06:37.214688  TX Vref=24, minBit 0, minWin=25, winSum=421

 8836 23:06:37.221337  TX Vref=26, minBit 0, minWin=25, winSum=423

 8837 23:06:37.225009  TX Vref=28, minBit 1, minWin=25, winSum=427

 8838 23:06:37.228300  TX Vref=30, minBit 1, minWin=25, winSum=423

 8839 23:06:37.231358  TX Vref=32, minBit 6, minWin=24, winSum=412

 8840 23:06:37.234809  TX Vref=34, minBit 0, minWin=24, winSum=402

 8841 23:06:37.241388  [TxChooseVref] Worse bit 1, Min win 25, Win sum 427, Final Vref 28

 8842 23:06:37.242005  

 8843 23:06:37.244666  Final TX Range 0 Vref 28

 8844 23:06:37.245234  

 8845 23:06:37.245652  ==

 8846 23:06:37.248054  Dram Type= 6, Freq= 0, CH_1, rank 1

 8847 23:06:37.251525  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8848 23:06:37.252007  ==

 8849 23:06:37.252377  

 8850 23:06:37.252718  

 8851 23:06:37.254573  	TX Vref Scan disable

 8852 23:06:37.261534  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps

 8853 23:06:37.262150   == TX Byte 0 ==

 8854 23:06:37.265033  u2DelayCellOfst[0]=17 cells (5 PI)

 8855 23:06:37.267722  u2DelayCellOfst[1]=10 cells (3 PI)

 8856 23:06:37.271493  u2DelayCellOfst[2]=0 cells (0 PI)

 8857 23:06:37.274764  u2DelayCellOfst[3]=6 cells (2 PI)

 8858 23:06:37.278189  u2DelayCellOfst[4]=10 cells (3 PI)

 8859 23:06:37.281472  u2DelayCellOfst[5]=17 cells (5 PI)

 8860 23:06:37.281994  u2DelayCellOfst[6]=17 cells (5 PI)

 8861 23:06:37.284241  u2DelayCellOfst[7]=6 cells (2 PI)

 8862 23:06:37.290996  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8863 23:06:37.294563  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8864 23:06:37.295017   == TX Byte 1 ==

 8865 23:06:37.297683  u2DelayCellOfst[8]=0 cells (0 PI)

 8866 23:06:37.301062  u2DelayCellOfst[9]=3 cells (1 PI)

 8867 23:06:37.304107  u2DelayCellOfst[10]=10 cells (3 PI)

 8868 23:06:37.307427  u2DelayCellOfst[11]=6 cells (2 PI)

 8869 23:06:37.310779  u2DelayCellOfst[12]=13 cells (4 PI)

 8870 23:06:37.314398  u2DelayCellOfst[13]=17 cells (5 PI)

 8871 23:06:37.317946  u2DelayCellOfst[14]=17 cells (5 PI)

 8872 23:06:37.320985  u2DelayCellOfst[15]=17 cells (5 PI)

 8873 23:06:37.324526  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8874 23:06:37.331035  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8875 23:06:37.331555  DramC Write-DBI on

 8876 23:06:37.331884  ==

 8877 23:06:37.334199  Dram Type= 6, Freq= 0, CH_1, rank 1

 8878 23:06:37.336987  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8879 23:06:37.341045  ==

 8880 23:06:37.341560  

 8881 23:06:37.341997  

 8882 23:06:37.342302  	TX Vref Scan disable

 8883 23:06:37.344235   == TX Byte 0 ==

 8884 23:06:37.347105  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8885 23:06:37.350840   == TX Byte 1 ==

 8886 23:06:37.354385  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8887 23:06:37.357609  DramC Write-DBI off

 8888 23:06:37.358143  

 8889 23:06:37.358474  [DATLAT]

 8890 23:06:37.358774  Freq=1600, CH1 RK1

 8891 23:06:37.359065  

 8892 23:06:37.360219  DATLAT Default: 0xf

 8893 23:06:37.364148  0, 0xFFFF, sum = 0

 8894 23:06:37.364667  1, 0xFFFF, sum = 0

 8895 23:06:37.367078  2, 0xFFFF, sum = 0

 8896 23:06:37.367604  3, 0xFFFF, sum = 0

 8897 23:06:37.370640  4, 0xFFFF, sum = 0

 8898 23:06:37.371160  5, 0xFFFF, sum = 0

 8899 23:06:37.373456  6, 0xFFFF, sum = 0

 8900 23:06:37.374033  7, 0xFFFF, sum = 0

 8901 23:06:37.377264  8, 0xFFFF, sum = 0

 8902 23:06:37.377835  9, 0xFFFF, sum = 0

 8903 23:06:37.380306  10, 0xFFFF, sum = 0

 8904 23:06:37.380826  11, 0xFFFF, sum = 0

 8905 23:06:37.383534  12, 0xFFFF, sum = 0

 8906 23:06:37.383951  13, 0xFFFF, sum = 0

 8907 23:06:37.387368  14, 0x0, sum = 1

 8908 23:06:37.387892  15, 0x0, sum = 2

 8909 23:06:37.390240  16, 0x0, sum = 3

 8910 23:06:37.390761  17, 0x0, sum = 4

 8911 23:06:37.393527  best_step = 15

 8912 23:06:37.393987  

 8913 23:06:37.394316  ==

 8914 23:06:37.397227  Dram Type= 6, Freq= 0, CH_1, rank 1

 8915 23:06:37.400732  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8916 23:06:37.401257  ==

 8917 23:06:37.403452  RX Vref Scan: 0

 8918 23:06:37.403864  

 8919 23:06:37.404187  RX Vref 0 -> 0, step: 1

 8920 23:06:37.404490  

 8921 23:06:37.406376  RX Delay 19 -> 252, step: 4

 8922 23:06:37.413220  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 8923 23:06:37.417021  iDelay=195, Bit 1, Center 130 (79 ~ 182) 104

 8924 23:06:37.419907  iDelay=195, Bit 2, Center 122 (71 ~ 174) 104

 8925 23:06:37.423373  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8926 23:06:37.426328  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 8927 23:06:37.429801  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8928 23:06:37.436650  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 8929 23:06:37.439700  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 8930 23:06:37.443112  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 8931 23:06:37.446828  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 8932 23:06:37.449852  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 8933 23:06:37.456417  iDelay=195, Bit 11, Center 124 (71 ~ 178) 108

 8934 23:06:37.459489  iDelay=195, Bit 12, Center 140 (87 ~ 194) 108

 8935 23:06:37.463050  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 8936 23:06:37.466478  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 8937 23:06:37.472824  iDelay=195, Bit 15, Center 140 (91 ~ 190) 100

 8938 23:06:37.473248  ==

 8939 23:06:37.475937  Dram Type= 6, Freq= 0, CH_1, rank 1

 8940 23:06:37.479714  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8941 23:06:37.480235  ==

 8942 23:06:37.480565  DQS Delay:

 8943 23:06:37.483166  DQS0 = 0, DQS1 = 0

 8944 23:06:37.483576  DQM Delay:

 8945 23:06:37.486474  DQM0 = 134, DQM1 = 130

 8946 23:06:37.486985  DQ Delay:

 8947 23:06:37.489450  DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130

 8948 23:06:37.492760  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 8949 23:06:37.496383  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124

 8950 23:06:37.499356  DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140

 8951 23:06:37.499769  

 8952 23:06:37.500091  

 8953 23:06:37.500391  

 8954 23:06:37.503083  [DramC_TX_OE_Calibration] TA2

 8955 23:06:37.506072  Original DQ_B0 (3 6) =30, OEN = 27

 8956 23:06:37.509735  Original DQ_B1 (3 6) =30, OEN = 27

 8957 23:06:37.513044  24, 0x0, End_B0=24 End_B1=24

 8958 23:06:37.516034  25, 0x0, End_B0=25 End_B1=25

 8959 23:06:37.516455  26, 0x0, End_B0=26 End_B1=26

 8960 23:06:37.519591  27, 0x0, End_B0=27 End_B1=27

 8961 23:06:37.522801  28, 0x0, End_B0=28 End_B1=28

 8962 23:06:37.526018  29, 0x0, End_B0=29 End_B1=29

 8963 23:06:37.529737  30, 0x0, End_B0=30 End_B1=30

 8964 23:06:37.530255  31, 0x4141, End_B0=30 End_B1=30

 8965 23:06:37.532687  Byte0 end_step=30  best_step=27

 8966 23:06:37.536108  Byte1 end_step=30  best_step=27

 8967 23:06:37.539520  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8968 23:06:37.542213  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8969 23:06:37.542633  

 8970 23:06:37.542957  

 8971 23:06:37.549191  [DQSOSCAuto] RK1, (LSB)MR18= 0x1f05, (MSB)MR19= 0x303, tDQSOscB0 = 407 ps tDQSOscB1 = 394 ps

 8972 23:06:37.552605  CH1 RK1: MR19=303, MR18=1F05

 8973 23:06:37.559368  CH1_RK1: MR19=0x303, MR18=0x1F05, DQSOSC=394, MR23=63, INC=23, DEC=15

 8974 23:06:37.562181  [RxdqsGatingPostProcess] freq 1600

 8975 23:06:37.568926  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8976 23:06:37.572273  best DQS0 dly(2T, 0.5T) = (1, 1)

 8977 23:06:37.572791  best DQS1 dly(2T, 0.5T) = (1, 1)

 8978 23:06:37.575780  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8979 23:06:37.579531  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8980 23:06:37.582601  best DQS0 dly(2T, 0.5T) = (1, 1)

 8981 23:06:37.585996  best DQS1 dly(2T, 0.5T) = (1, 1)

 8982 23:06:37.589218  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8983 23:06:37.592592  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8984 23:06:37.595504  Pre-setting of DQS Precalculation

 8985 23:06:37.599169  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8986 23:06:37.609450  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 8987 23:06:37.615817  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 8988 23:06:37.616389  

 8989 23:06:37.616753  

 8990 23:06:37.619472  [Calibration Summary] 3200 Mbps

 8991 23:06:37.620033  CH 0, Rank 0

 8992 23:06:37.622678  SW Impedance     : PASS

 8993 23:06:37.623137  DUTY Scan        : NO K

 8994 23:06:37.625597  ZQ Calibration   : PASS

 8995 23:06:37.629079  Jitter Meter     : NO K

 8996 23:06:37.629537  CBT Training     : PASS

 8997 23:06:37.632818  Write leveling   : PASS

 8998 23:06:37.635892  RX DQS gating    : PASS

 8999 23:06:37.636608  RX DQ/DQS(RDDQC) : PASS

 9000 23:06:37.639280  TX DQ/DQS        : PASS

 9001 23:06:37.642291  RX DATLAT        : PASS

 9002 23:06:37.642912  RX DQ/DQS(Engine): PASS

 9003 23:06:37.645647  TX OE            : PASS

 9004 23:06:37.646195  All Pass.

 9005 23:06:37.646563  

 9006 23:06:37.649371  CH 0, Rank 1

 9007 23:06:37.649994  SW Impedance     : PASS

 9008 23:06:37.652085  DUTY Scan        : NO K

 9009 23:06:37.656023  ZQ Calibration   : PASS

 9010 23:06:37.656582  Jitter Meter     : NO K

 9011 23:06:37.658993  CBT Training     : PASS

 9012 23:06:37.659542  Write leveling   : PASS

 9013 23:06:37.662406  RX DQS gating    : PASS

 9014 23:06:37.665764  RX DQ/DQS(RDDQC) : PASS

 9015 23:06:37.666317  TX DQ/DQS        : PASS

 9016 23:06:37.669073  RX DATLAT        : PASS

 9017 23:06:37.672468  RX DQ/DQS(Engine): PASS

 9018 23:06:37.673017  TX OE            : PASS

 9019 23:06:37.675123  All Pass.

 9020 23:06:37.675578  

 9021 23:06:37.675939  CH 1, Rank 0

 9022 23:06:37.678843  SW Impedance     : PASS

 9023 23:06:37.679398  DUTY Scan        : NO K

 9024 23:06:37.682625  ZQ Calibration   : PASS

 9025 23:06:37.685442  Jitter Meter     : NO K

 9026 23:06:37.686027  CBT Training     : PASS

 9027 23:06:37.688803  Write leveling   : PASS

 9028 23:06:37.692465  RX DQS gating    : PASS

 9029 23:06:37.693044  RX DQ/DQS(RDDQC) : PASS

 9030 23:06:37.695735  TX DQ/DQS        : PASS

 9031 23:06:37.698765  RX DATLAT        : PASS

 9032 23:06:37.699338  RX DQ/DQS(Engine): PASS

 9033 23:06:37.702390  TX OE            : PASS

 9034 23:06:37.702852  All Pass.

 9035 23:06:37.703213  

 9036 23:06:37.705505  CH 1, Rank 1

 9037 23:06:37.706011  SW Impedance     : PASS

 9038 23:06:37.708885  DUTY Scan        : NO K

 9039 23:06:37.709494  ZQ Calibration   : PASS

 9040 23:06:37.711926  Jitter Meter     : NO K

 9041 23:06:37.715271  CBT Training     : PASS

 9042 23:06:37.715727  Write leveling   : PASS

 9043 23:06:37.718591  RX DQS gating    : PASS

 9044 23:06:37.722137  RX DQ/DQS(RDDQC) : PASS

 9045 23:06:37.722582  TX DQ/DQS        : PASS

 9046 23:06:37.725313  RX DATLAT        : PASS

 9047 23:06:37.728468  RX DQ/DQS(Engine): PASS

 9048 23:06:37.728881  TX OE            : PASS

 9049 23:06:37.732377  All Pass.

 9050 23:06:37.732890  

 9051 23:06:37.733215  DramC Write-DBI on

 9052 23:06:37.735036  	PER_BANK_REFRESH: Hybrid Mode

 9053 23:06:37.735452  TX_TRACKING: ON

 9054 23:06:37.744974  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9055 23:06:37.755568  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9056 23:06:37.761974  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9057 23:06:37.765411  [FAST_K] Save calibration result to emmc

 9058 23:06:37.768753  sync common calibartion params.

 9059 23:06:37.769274  sync cbt_mode0:1, 1:1

 9060 23:06:37.772526  dram_init: ddr_geometry: 2

 9061 23:06:37.775066  dram_init: ddr_geometry: 2

 9062 23:06:37.775528  dram_init: ddr_geometry: 2

 9063 23:06:37.778784  0:dram_rank_size:100000000

 9064 23:06:37.782264  1:dram_rank_size:100000000

 9065 23:06:37.788706  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9066 23:06:37.789267  DFS_SHUFFLE_HW_MODE: ON

 9067 23:06:37.791992  dramc_set_vcore_voltage set vcore to 725000

 9068 23:06:37.795534  Read voltage for 1600, 0

 9069 23:06:37.795999  Vio18 = 0

 9070 23:06:37.798486  Vcore = 725000

 9071 23:06:37.798944  Vdram = 0

 9072 23:06:37.799303  Vddq = 0

 9073 23:06:37.801677  Vmddr = 0

 9074 23:06:37.802137  switch to 3200 Mbps bootup

 9075 23:06:37.805011  [DramcRunTimeConfig]

 9076 23:06:37.805670  PHYPLL

 9077 23:06:37.808983  DPM_CONTROL_AFTERK: ON

 9078 23:06:37.809539  PER_BANK_REFRESH: ON

 9079 23:06:37.811822  REFRESH_OVERHEAD_REDUCTION: ON

 9080 23:06:37.814859  CMD_PICG_NEW_MODE: OFF

 9081 23:06:37.815463  XRTWTW_NEW_MODE: ON

 9082 23:06:37.818217  XRTRTR_NEW_MODE: ON

 9083 23:06:37.818672  TX_TRACKING: ON

 9084 23:06:37.821571  RDSEL_TRACKING: OFF

 9085 23:06:37.825011  DQS Precalculation for DVFS: ON

 9086 23:06:37.825423  RX_TRACKING: OFF

 9087 23:06:37.828632  HW_GATING DBG: ON

 9088 23:06:37.829144  ZQCS_ENABLE_LP4: ON

 9089 23:06:37.831938  RX_PICG_NEW_MODE: ON

 9090 23:06:37.832454  TX_PICG_NEW_MODE: ON

 9091 23:06:37.835104  ENABLE_RX_DCM_DPHY: ON

 9092 23:06:37.838116  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9093 23:06:37.841441  DUMMY_READ_FOR_TRACKING: OFF

 9094 23:06:37.842086  !!! SPM_CONTROL_AFTERK: OFF

 9095 23:06:37.844858  !!! SPM could not control APHY

 9096 23:06:37.848798  IMPEDANCE_TRACKING: ON

 9097 23:06:37.849212  TEMP_SENSOR: ON

 9098 23:06:37.851746  HW_SAVE_FOR_SR: OFF

 9099 23:06:37.854562  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9100 23:06:37.858093  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9101 23:06:37.858505  Read ODT Tracking: ON

 9102 23:06:37.861344  Refresh Rate DeBounce: ON

 9103 23:06:37.864942  DFS_NO_QUEUE_FLUSH: ON

 9104 23:06:37.867750  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9105 23:06:37.868211  ENABLE_DFS_RUNTIME_MRW: OFF

 9106 23:06:37.871474  DDR_RESERVE_NEW_MODE: ON

 9107 23:06:37.874811  MR_CBT_SWITCH_FREQ: ON

 9108 23:06:37.875198  =========================

 9109 23:06:37.895003  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9110 23:06:37.898319  dram_init: ddr_geometry: 2

 9111 23:06:37.916941  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9112 23:06:37.919644  dram_init: dram init end (result: 0)

 9113 23:06:37.926696  DRAM-K: Full calibration passed in 24395 msecs

 9114 23:06:37.929743  MRC: failed to locate region type 0.

 9115 23:06:37.930295  DRAM rank0 size:0x100000000,

 9116 23:06:37.933471  DRAM rank1 size=0x100000000

 9117 23:06:37.943877  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9118 23:06:37.950084  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9119 23:06:37.956595  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9120 23:06:37.963297  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9121 23:06:37.966832  DRAM rank0 size:0x100000000,

 9122 23:06:37.969643  DRAM rank1 size=0x100000000

 9123 23:06:37.970119  CBMEM:

 9124 23:06:37.973011  IMD: root @ 0xfffff000 254 entries.

 9125 23:06:37.976590  IMD: root @ 0xffffec00 62 entries.

 9126 23:06:37.980108  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9127 23:06:37.983547  WARNING: RO_VPD is uninitialized or empty.

 9128 23:06:37.990005  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9129 23:06:37.996711  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9130 23:06:38.010012  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9131 23:06:38.021254  BS: romstage times (exec / console): total (unknown) / 23938 ms

 9132 23:06:38.021896  

 9133 23:06:38.022393  

 9134 23:06:38.031236  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9135 23:06:38.034441  ARM64: Exception handlers installed.

 9136 23:06:38.037319  ARM64: Testing exception

 9137 23:06:38.041150  ARM64: Done test exception

 9138 23:06:38.041764  Enumerating buses...

 9139 23:06:38.044516  Show all devs... Before device enumeration.

 9140 23:06:38.047565  Root Device: enabled 1

 9141 23:06:38.051076  CPU_CLUSTER: 0: enabled 1

 9142 23:06:38.051596  CPU: 00: enabled 1

 9143 23:06:38.054089  Compare with tree...

 9144 23:06:38.054660  Root Device: enabled 1

 9145 23:06:38.057656   CPU_CLUSTER: 0: enabled 1

 9146 23:06:38.061426    CPU: 00: enabled 1

 9147 23:06:38.062067  Root Device scanning...

 9148 23:06:38.064266  scan_static_bus for Root Device

 9149 23:06:38.067749  CPU_CLUSTER: 0 enabled

 9150 23:06:38.070442  scan_static_bus for Root Device done

 9151 23:06:38.074073  scan_bus: bus Root Device finished in 8 msecs

 9152 23:06:38.074643  done

 9153 23:06:38.080473  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9154 23:06:38.083743  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9155 23:06:38.091074  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9156 23:06:38.093960  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9157 23:06:38.097311  Allocating resources...

 9158 23:06:38.100701  Reading resources...

 9159 23:06:38.103727  Root Device read_resources bus 0 link: 0

 9160 23:06:38.104296  DRAM rank0 size:0x100000000,

 9161 23:06:38.107389  DRAM rank1 size=0x100000000

 9162 23:06:38.110455  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9163 23:06:38.113707  CPU: 00 missing read_resources

 9164 23:06:38.117672  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9165 23:06:38.123916  Root Device read_resources bus 0 link: 0 done

 9166 23:06:38.124452  Done reading resources.

 9167 23:06:38.130668  Show resources in subtree (Root Device)...After reading.

 9168 23:06:38.134143   Root Device child on link 0 CPU_CLUSTER: 0

 9169 23:06:38.136758    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9170 23:06:38.147004    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9171 23:06:38.147570     CPU: 00

 9172 23:06:38.150358  Root Device assign_resources, bus 0 link: 0

 9173 23:06:38.153678  CPU_CLUSTER: 0 missing set_resources

 9174 23:06:38.157099  Root Device assign_resources, bus 0 link: 0 done

 9175 23:06:38.160740  Done setting resources.

 9176 23:06:38.166789  Show resources in subtree (Root Device)...After assigning values.

 9177 23:06:38.170384   Root Device child on link 0 CPU_CLUSTER: 0

 9178 23:06:38.174098    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9179 23:06:38.183367    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9180 23:06:38.183983     CPU: 00

 9181 23:06:38.187113  Done allocating resources.

 9182 23:06:38.190102  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9183 23:06:38.193421  Enabling resources...

 9184 23:06:38.193930  done.

 9185 23:06:38.200569  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9186 23:06:38.201144  Initializing devices...

 9187 23:06:38.203608  Root Device init

 9188 23:06:38.204218  init hardware done!

 9189 23:06:38.207021  0x00000018: ctrlr->caps

 9190 23:06:38.209899  52.000 MHz: ctrlr->f_max

 9191 23:06:38.210380  0.400 MHz: ctrlr->f_min

 9192 23:06:38.213562  0x40ff8080: ctrlr->voltages

 9193 23:06:38.214046  sclk: 390625

 9194 23:06:38.216674  Bus Width = 1

 9195 23:06:38.217100  sclk: 390625

 9196 23:06:38.219728  Bus Width = 1

 9197 23:06:38.220155  Early init status = 3

 9198 23:06:38.226325  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9199 23:06:38.229797  in-header: 03 fc 00 00 01 00 00 00 

 9200 23:06:38.230311  in-data: 00 

 9201 23:06:38.236840  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9202 23:06:38.239861  in-header: 03 fd 00 00 00 00 00 00 

 9203 23:06:38.243266  in-data: 

 9204 23:06:38.246127  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9205 23:06:38.250239  in-header: 03 fc 00 00 01 00 00 00 

 9206 23:06:38.253737  in-data: 00 

 9207 23:06:38.257232  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9208 23:06:38.262557  in-header: 03 fd 00 00 00 00 00 00 

 9209 23:06:38.265759  in-data: 

 9210 23:06:38.268762  [SSUSB] Setting up USB HOST controller...

 9211 23:06:38.272615  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9212 23:06:38.275324  [SSUSB] phy power-on done.

 9213 23:06:38.279134  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9214 23:06:38.285735  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9215 23:06:38.289025  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9216 23:06:38.295702  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9217 23:06:38.302126  read SPI 0x50eb0 0x2ad3: 1173 us, 9346 KB/s, 74.768 Mbps

 9218 23:06:38.308521  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9219 23:06:38.315365  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9220 23:06:38.322124  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9221 23:06:38.325219  SPM: binary array size = 0x9dc

 9222 23:06:38.328685  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9223 23:06:38.335066  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9224 23:06:38.342126  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9225 23:06:38.345493  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9226 23:06:38.352239  configure_display: Starting display init

 9227 23:06:38.386026  anx7625_power_on_init: Init interface.

 9228 23:06:38.388943  anx7625_disable_pd_protocol: Disabled PD feature.

 9229 23:06:38.392642  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9230 23:06:38.419754  anx7625_start_dp_work: Secure OCM version=00

 9231 23:06:38.422978  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9232 23:06:38.438433  sp_tx_get_edid_block: EDID Block = 1

 9233 23:06:38.540616  Extracted contents:

 9234 23:06:38.544175  header:          00 ff ff ff ff ff ff 00

 9235 23:06:38.547842  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9236 23:06:38.550390  version:         01 04

 9237 23:06:38.553906  basic params:    95 1f 11 78 0a

 9238 23:06:38.557533  chroma info:     76 90 94 55 54 90 27 21 50 54

 9239 23:06:38.560540  established:     00 00 00

 9240 23:06:38.567070  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9241 23:06:38.570769  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9242 23:06:38.577238  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9243 23:06:38.584237  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9244 23:06:38.590492  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9245 23:06:38.594114  extensions:      00

 9246 23:06:38.594747  checksum:        fb

 9247 23:06:38.595233  

 9248 23:06:38.597357  Manufacturer: IVO Model 57d Serial Number 0

 9249 23:06:38.600559  Made week 0 of 2020

 9250 23:06:38.601130  EDID version: 1.4

 9251 23:06:38.604067  Digital display

 9252 23:06:38.607578  6 bits per primary color channel

 9253 23:06:38.608160  DisplayPort interface

 9254 23:06:38.610548  Maximum image size: 31 cm x 17 cm

 9255 23:06:38.614334  Gamma: 220%

 9256 23:06:38.614906  Check DPMS levels

 9257 23:06:38.616929  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9258 23:06:38.620859  First detailed timing is preferred timing

 9259 23:06:38.623552  Established timings supported:

 9260 23:06:38.627291  Standard timings supported:

 9261 23:06:38.627862  Detailed timings

 9262 23:06:38.633442  Hex of detail: 383680a07038204018303c0035ae10000019

 9263 23:06:38.636962  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9264 23:06:38.643904                 0780 0798 07c8 0820 hborder 0

 9265 23:06:38.647187                 0438 043b 0447 0458 vborder 0

 9266 23:06:38.650431                 -hsync -vsync

 9267 23:06:38.650877  Did detailed timing

 9268 23:06:38.653409  Hex of detail: 000000000000000000000000000000000000

 9269 23:06:38.657329  Manufacturer-specified data, tag 0

 9270 23:06:38.663757  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9271 23:06:38.664286  ASCII string: InfoVision

 9272 23:06:38.670408  Hex of detail: 000000fe00523134304e574635205248200a

 9273 23:06:38.673291  ASCII string: R140NWF5 RH 

 9274 23:06:38.673757  Checksum

 9275 23:06:38.674193  Checksum: 0xfb (valid)

 9276 23:06:38.680501  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9277 23:06:38.683802  DSI data_rate: 832800000 bps

 9278 23:06:38.686786  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9279 23:06:38.693665  anx7625_parse_edid: pixelclock(138800).

 9280 23:06:38.696885   hactive(1920), hsync(48), hfp(24), hbp(88)

 9281 23:06:38.700171   vactive(1080), vsync(12), vfp(3), vbp(17)

 9282 23:06:38.703746  anx7625_dsi_config: config dsi.

 9283 23:06:38.709862  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9284 23:06:38.722948  anx7625_dsi_config: success to config DSI

 9285 23:06:38.726157  anx7625_dp_start: MIPI phy setup OK.

 9286 23:06:38.729770  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9287 23:06:38.732524  mtk_ddp_mode_set invalid vrefresh 60

 9288 23:06:38.736087  main_disp_path_setup

 9289 23:06:38.736666  ovl_layer_smi_id_en

 9290 23:06:38.739392  ovl_layer_smi_id_en

 9291 23:06:38.739865  ccorr_config

 9292 23:06:38.740341  aal_config

 9293 23:06:38.742796  gamma_config

 9294 23:06:38.743381  postmask_config

 9295 23:06:38.745859  dither_config

 9296 23:06:38.749212  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9297 23:06:38.755583                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9298 23:06:38.759184  Root Device init finished in 553 msecs

 9299 23:06:38.762143  CPU_CLUSTER: 0 init

 9300 23:06:38.769077  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9301 23:06:38.771868  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9302 23:06:38.775581  APU_MBOX 0x190000b0 = 0x10001

 9303 23:06:38.778694  APU_MBOX 0x190001b0 = 0x10001

 9304 23:06:38.781992  APU_MBOX 0x190005b0 = 0x10001

 9305 23:06:38.785605  APU_MBOX 0x190006b0 = 0x10001

 9306 23:06:38.789027  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9307 23:06:38.801274  read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps

 9308 23:06:38.814444  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9309 23:06:38.821021  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9310 23:06:38.832549  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9311 23:06:38.841602  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9312 23:06:38.845170  CPU_CLUSTER: 0 init finished in 81 msecs

 9313 23:06:38.848129  Devices initialized

 9314 23:06:38.851497  Show all devs... After init.

 9315 23:06:38.851952  Root Device: enabled 1

 9316 23:06:38.855207  CPU_CLUSTER: 0: enabled 1

 9317 23:06:38.857935  CPU: 00: enabled 1

 9318 23:06:38.861608  BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms

 9319 23:06:38.865279  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9320 23:06:38.868014  ELOG: NV offset 0x57f000 size 0x1000

 9321 23:06:38.874600  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9322 23:06:38.881536  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9323 23:06:38.885180  ELOG: Event(17) added with size 13 at 2023-12-03 23:04:25 UTC

 9324 23:06:38.891578  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9325 23:06:38.894565  in-header: 03 1b 00 00 2c 00 00 00 

 9326 23:06:38.904799  in-data: 44 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9327 23:06:38.910943  ELOG: Event(A1) added with size 10 at 2023-12-03 23:04:25 UTC

 9328 23:06:38.918029  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9329 23:06:38.924508  ELOG: Event(A0) added with size 9 at 2023-12-03 23:04:25 UTC

 9330 23:06:38.927702  elog_add_boot_reason: Logged dev mode boot

 9331 23:06:38.934379  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9332 23:06:38.934859  Finalize devices...

 9333 23:06:38.937715  Devices finalized

 9334 23:06:38.941100  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9335 23:06:38.944331  Writing coreboot table at 0xffe64000

 9336 23:06:38.947294   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9337 23:06:38.951332   1. 0000000040000000-00000000400fffff: RAM

 9338 23:06:38.957293   2. 0000000040100000-000000004032afff: RAMSTAGE

 9339 23:06:38.960872   3. 000000004032b000-00000000545fffff: RAM

 9340 23:06:38.964824   4. 0000000054600000-000000005465ffff: BL31

 9341 23:06:38.967592   5. 0000000054660000-00000000ffe63fff: RAM

 9342 23:06:38.974432   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9343 23:06:38.977513   7. 0000000100000000-000000023fffffff: RAM

 9344 23:06:38.981188  Passing 5 GPIOs to payload:

 9345 23:06:38.984527              NAME |       PORT | POLARITY |     VALUE

 9346 23:06:38.987408          EC in RW | 0x000000aa |      low | undefined

 9347 23:06:38.994746      EC interrupt | 0x00000005 |      low | undefined

 9348 23:06:38.997697     TPM interrupt | 0x000000ab |     high | undefined

 9349 23:06:39.003891    SD card detect | 0x00000011 |     high | undefined

 9350 23:06:39.007725    speaker enable | 0x00000093 |     high | undefined

 9351 23:06:39.010763  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9352 23:06:39.014287  in-header: 03 f9 00 00 02 00 00 00 

 9353 23:06:39.017753  in-data: 02 00 

 9354 23:06:39.018232  ADC[4]: Raw value=904357 ID=7

 9355 23:06:39.020523  ADC[3]: Raw value=213441 ID=1

 9356 23:06:39.024282  RAM Code: 0x71

 9357 23:06:39.024759  ADC[6]: Raw value=75701 ID=0

 9358 23:06:39.027065  ADC[5]: Raw value=213072 ID=1

 9359 23:06:39.030671  SKU Code: 0x1

 9360 23:06:39.034332  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c

 9361 23:06:39.037475  coreboot table: 964 bytes.

 9362 23:06:39.040851  IMD ROOT    0. 0xfffff000 0x00001000

 9363 23:06:39.044107  IMD SMALL   1. 0xffffe000 0x00001000

 9364 23:06:39.047131  RO MCACHE   2. 0xffffc000 0x00001104

 9365 23:06:39.050961  CONSOLE     3. 0xfff7c000 0x00080000

 9366 23:06:39.053985  FMAP        4. 0xfff7b000 0x00000452

 9367 23:06:39.057696  TIME STAMP  5. 0xfff7a000 0x00000910

 9368 23:06:39.060344  VBOOT WORK  6. 0xfff66000 0x00014000

 9369 23:06:39.063947  RAMOOPS     7. 0xffe66000 0x00100000

 9370 23:06:39.066999  COREBOOT    8. 0xffe64000 0x00002000

 9371 23:06:39.067473  IMD small region:

 9372 23:06:39.074034    IMD ROOT    0. 0xffffec00 0x00000400

 9373 23:06:39.077096    VPD         1. 0xffffeb80 0x0000006c

 9374 23:06:39.080494    MMC STATUS  2. 0xffffeb60 0x00000004

 9375 23:06:39.083367  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9376 23:06:39.086728  Probing TPM:  done!

 9377 23:06:39.090065  Connected to device vid:did:rid of 1ae0:0028:00

 9378 23:06:39.100977  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9379 23:06:39.104164  Initialized TPM device CR50 revision 0

 9380 23:06:39.108060  Checking cr50 for pending updates

 9381 23:06:39.111811  Reading cr50 TPM mode

 9382 23:06:39.120665  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9383 23:06:39.126824  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9384 23:06:39.166818  read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps

 9385 23:06:39.170454  Checking segment from ROM address 0x40100000

 9386 23:06:39.173895  Checking segment from ROM address 0x4010001c

 9387 23:06:39.180505  Loading segment from ROM address 0x40100000

 9388 23:06:39.181079    code (compression=0)

 9389 23:06:39.186913    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9390 23:06:39.197000  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9391 23:06:39.197573  it's not compressed!

 9392 23:06:39.203816  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9393 23:06:39.206971  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9394 23:06:39.227196  Loading segment from ROM address 0x4010001c

 9395 23:06:39.227751    Entry Point 0x80000000

 9396 23:06:39.230907  Loaded segments

 9397 23:06:39.234275  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9398 23:06:39.241030  Jumping to boot code at 0x80000000(0xffe64000)

 9399 23:06:39.247486  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9400 23:06:39.253789  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9401 23:06:39.261618  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9402 23:06:39.265530  Checking segment from ROM address 0x40100000

 9403 23:06:39.268456  Checking segment from ROM address 0x4010001c

 9404 23:06:39.275487  Loading segment from ROM address 0x40100000

 9405 23:06:39.276065    code (compression=1)

 9406 23:06:39.282260    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9407 23:06:39.291537  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9408 23:06:39.292101  using LZMA

 9409 23:06:39.300496  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9410 23:06:39.307309  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9411 23:06:39.309843  Loading segment from ROM address 0x4010001c

 9412 23:06:39.310317    Entry Point 0x54601000

 9413 23:06:39.313353  Loaded segments

 9414 23:06:39.316369  NOTICE:  MT8192 bl31_setup

 9415 23:06:39.323525  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9416 23:06:39.327224  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9417 23:06:39.330419  WARNING: region 0:

 9418 23:06:39.333570  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9419 23:06:39.334183  WARNING: region 1:

 9420 23:06:39.340595  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9421 23:06:39.343787  WARNING: region 2:

 9422 23:06:39.346709  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9423 23:06:39.350242  WARNING: region 3:

 9424 23:06:39.353543  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9425 23:06:39.356829  WARNING: region 4:

 9426 23:06:39.363615  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9427 23:06:39.364178  WARNING: region 5:

 9428 23:06:39.366910  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9429 23:06:39.370276  WARNING: region 6:

 9430 23:06:39.373317  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9431 23:06:39.373762  WARNING: region 7:

 9432 23:06:39.380949  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9433 23:06:39.387457  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9434 23:06:39.390276  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9435 23:06:39.394224  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9436 23:06:39.400635  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9437 23:06:39.404132  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9438 23:06:39.407103  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9439 23:06:39.414388  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9440 23:06:39.417441  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9441 23:06:39.423509  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9442 23:06:39.427008  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9443 23:06:39.430210  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9444 23:06:39.436771  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9445 23:06:39.440341  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9446 23:06:39.443253  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9447 23:06:39.450260  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9448 23:06:39.453520  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9449 23:06:39.460263  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9450 23:06:39.463793  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9451 23:06:39.466722  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9452 23:06:39.473338  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9453 23:06:39.476986  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9454 23:06:39.480426  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9455 23:06:39.486821  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9456 23:06:39.490524  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9457 23:06:39.497215  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9458 23:06:39.500065  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9459 23:06:39.503527  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9460 23:06:39.510082  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9461 23:06:39.513801  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9462 23:06:39.520407  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9463 23:06:39.523636  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9464 23:06:39.527247  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9465 23:06:39.533805  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9466 23:06:39.537377  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9467 23:06:39.540038  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9468 23:06:39.543401  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9469 23:06:39.550005  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9470 23:06:39.553415  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9471 23:06:39.556689  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9472 23:06:39.560233  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9473 23:06:39.563512  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9474 23:06:39.570300  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9475 23:06:39.573488  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9476 23:06:39.577189  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9477 23:06:39.580359  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9478 23:06:39.586828  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9479 23:06:39.590260  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9480 23:06:39.593804  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9481 23:06:39.599823  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9482 23:06:39.603546  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9483 23:06:39.609998  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9484 23:06:39.613730  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9485 23:06:39.616752  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9486 23:06:39.623429  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9487 23:06:39.627060  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9488 23:06:39.633948  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9489 23:06:39.636909  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9490 23:06:39.640644  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9491 23:06:39.647399  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9492 23:06:39.650418  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9493 23:06:39.657158  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9494 23:06:39.660658  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9495 23:06:39.667444  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9496 23:06:39.670590  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9497 23:06:39.673689  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9498 23:06:39.680523  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9499 23:06:39.683660  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9500 23:06:39.691017  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9501 23:06:39.694075  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9502 23:06:39.700456  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9503 23:06:39.704121  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9504 23:06:39.707347  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9505 23:06:39.714333  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9506 23:06:39.717540  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9507 23:06:39.724021  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9508 23:06:39.727321  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9509 23:06:39.734272  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9510 23:06:39.737304  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9511 23:06:39.740928  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9512 23:06:39.747719  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9513 23:06:39.750757  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9514 23:06:39.757621  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9515 23:06:39.760489  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9516 23:06:39.767421  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9517 23:06:39.770773  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9518 23:06:39.774030  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9519 23:06:39.781010  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9520 23:06:39.784168  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9521 23:06:39.791030  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9522 23:06:39.794189  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9523 23:06:39.800855  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9524 23:06:39.804195  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9525 23:06:39.807419  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9526 23:06:39.813942  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9527 23:06:39.817676  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9528 23:06:39.824393  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9529 23:06:39.827506  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9530 23:06:39.831162  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9531 23:06:39.834488  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9532 23:06:39.841442  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9533 23:06:39.845025  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9534 23:06:39.847826  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9535 23:06:39.855086  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9536 23:06:39.858060  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9537 23:06:39.861549  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9538 23:06:39.868615  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9539 23:06:39.872029  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9540 23:06:39.878324  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9541 23:06:39.881495  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9542 23:06:39.884916  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9543 23:06:39.891477  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9544 23:06:39.894975  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9545 23:06:39.901656  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9546 23:06:39.905040  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9547 23:06:39.907991  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9548 23:06:39.914729  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9549 23:06:39.917906  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9550 23:06:39.921213  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9551 23:06:39.927724  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9552 23:06:39.931467  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9553 23:06:39.934324  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9554 23:06:39.937951  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9555 23:06:39.944775  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9556 23:06:39.947749  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9557 23:06:39.951793  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9558 23:06:39.957703  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9559 23:06:39.961087  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9560 23:06:39.964634  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9561 23:06:39.971401  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9562 23:06:39.974896  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9563 23:06:39.978148  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9564 23:06:39.984710  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9565 23:06:39.987830  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9566 23:06:39.994939  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9567 23:06:39.998107  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9568 23:06:40.001223  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9569 23:06:40.008140  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9570 23:06:40.011524  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9571 23:06:40.018409  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9572 23:06:40.021339  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9573 23:06:40.024903  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9574 23:06:40.031451  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9575 23:06:40.035098  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9576 23:06:40.041801  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9577 23:06:40.044864  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9578 23:06:40.048579  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9579 23:06:40.055158  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9580 23:06:40.058554  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9581 23:06:40.065572  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9582 23:06:40.068494  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9583 23:06:40.071687  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9584 23:06:40.078349  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9585 23:06:40.082165  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9586 23:06:40.084747  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9587 23:06:40.091820  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9588 23:06:40.095171  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9589 23:06:40.101959  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9590 23:06:40.105455  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9591 23:06:40.108278  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9592 23:06:40.115441  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9593 23:06:40.118284  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9594 23:06:40.125043  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9595 23:06:40.128245  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9596 23:06:40.131722  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9597 23:06:40.138125  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9598 23:06:40.141479  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9599 23:06:40.144566  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9600 23:06:40.151458  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9601 23:06:40.154875  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9602 23:06:40.161672  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9603 23:06:40.165177  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9604 23:06:40.168349  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9605 23:06:40.174637  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9606 23:06:40.178334  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9607 23:06:40.185016  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9608 23:06:40.188626  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9609 23:06:40.191479  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9610 23:06:40.197949  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9611 23:06:40.201505  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9612 23:06:40.207999  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9613 23:06:40.211858  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9614 23:06:40.214413  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9615 23:06:40.221118  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9616 23:06:40.224732  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9617 23:06:40.230896  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9618 23:06:40.234468  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9619 23:06:40.237545  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9620 23:06:40.244582  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9621 23:06:40.247801  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9622 23:06:40.254425  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9623 23:06:40.258221  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9624 23:06:40.260966  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9625 23:06:40.267731  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9626 23:06:40.270499  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9627 23:06:40.277336  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9628 23:06:40.280671  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9629 23:06:40.284532  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9630 23:06:40.290558  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9631 23:06:40.294377  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9632 23:06:40.300615  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9633 23:06:40.304286  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9634 23:06:40.311059  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9635 23:06:40.314267  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9636 23:06:40.317800  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9637 23:06:40.324444  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9638 23:06:40.327581  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9639 23:06:40.334245  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9640 23:06:40.337684  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9641 23:06:40.340642  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9642 23:06:40.347923  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9643 23:06:40.350806  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9644 23:06:40.357935  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9645 23:06:40.361097  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9646 23:06:40.364729  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9647 23:06:40.370868  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9648 23:06:40.374322  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9649 23:06:40.380950  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9650 23:06:40.384322  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9651 23:06:40.390980  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9652 23:06:40.394081  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9653 23:06:40.397465  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9654 23:06:40.404359  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9655 23:06:40.407614  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9656 23:06:40.414201  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9657 23:06:40.417624  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9658 23:06:40.420782  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9659 23:06:40.427927  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9660 23:06:40.430736  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9661 23:06:40.438142  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9662 23:06:40.441440  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9663 23:06:40.444585  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9664 23:06:40.448278  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9665 23:06:40.451068  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9666 23:06:40.458036  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9667 23:06:40.461348  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9668 23:06:40.464660  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9669 23:06:40.471299  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9670 23:06:40.474145  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9671 23:06:40.477854  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9672 23:06:40.484624  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9673 23:06:40.487687  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9674 23:06:40.494763  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9675 23:06:40.497312  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9676 23:06:40.500822  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9677 23:06:40.507816  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9678 23:06:40.510663  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9679 23:06:40.514458  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9680 23:06:40.520774  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9681 23:06:40.524619  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9682 23:06:40.527541  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9683 23:06:40.534041  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9684 23:06:40.537716  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9685 23:06:40.544685  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9686 23:06:40.547273  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9687 23:06:40.550688  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9688 23:06:40.557326  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9689 23:06:40.561036  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9690 23:06:40.564371  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9691 23:06:40.570794  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9692 23:06:40.574082  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9693 23:06:40.580619  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9694 23:06:40.584678  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9695 23:06:40.587419  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9696 23:06:40.593941  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9697 23:06:40.597608  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9698 23:06:40.601054  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9699 23:06:40.607204  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9700 23:06:40.611065  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9701 23:06:40.613825  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9702 23:06:40.620459  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9703 23:06:40.623854  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9704 23:06:40.627226  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9705 23:06:40.630951  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9706 23:06:40.633965  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9707 23:06:40.640446  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9708 23:06:40.643481  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9709 23:06:40.647317  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9710 23:06:40.650259  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9711 23:06:40.657234  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9712 23:06:40.660106  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9713 23:06:40.663418  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9714 23:06:40.670467  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9715 23:06:40.673329  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9716 23:06:40.676779  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9717 23:06:40.683251  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9718 23:06:40.686885  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9719 23:06:40.693690  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9720 23:06:40.696762  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9721 23:06:40.703217  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9722 23:06:40.706529  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9723 23:06:40.710086  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9724 23:06:40.716561  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9725 23:06:40.719703  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9726 23:06:40.726389  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9727 23:06:40.729545  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9728 23:06:40.735979  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9729 23:06:40.739414  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9730 23:06:40.742734  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9731 23:06:40.749390  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9732 23:06:40.752754  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9733 23:06:40.756245  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9734 23:06:40.763183  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9735 23:06:40.766305  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9736 23:06:40.772551  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9737 23:06:40.776258  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9738 23:06:40.779844  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9739 23:06:40.786072  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9740 23:06:40.789008  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9741 23:06:40.795732  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9742 23:06:40.798991  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9743 23:06:40.805864  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9744 23:06:40.809461  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9745 23:06:40.812573  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9746 23:06:40.819291  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9747 23:06:40.822414  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9748 23:06:40.829167  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9749 23:06:40.832135  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9750 23:06:40.835271  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9751 23:06:40.841897  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9752 23:06:40.845270  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9753 23:06:40.851825  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9754 23:06:40.855709  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9755 23:06:40.859308  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9756 23:06:40.865474  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9757 23:06:40.869224  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9758 23:06:40.875837  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9759 23:06:40.879095  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9760 23:06:40.885675  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9761 23:06:40.889432  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9762 23:06:40.892835  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9763 23:06:40.899415  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9764 23:06:40.902741  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9765 23:06:40.909063  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9766 23:06:40.912818  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9767 23:06:40.915809  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9768 23:06:40.922323  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9769 23:06:40.925795  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9770 23:06:40.929049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9771 23:06:40.935852  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9772 23:06:40.939431  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9773 23:06:40.945786  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9774 23:06:40.948757  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9775 23:06:40.955787  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9776 23:06:40.958677  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9777 23:06:40.964961  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9778 23:06:40.968830  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9779 23:06:40.971916  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9780 23:06:40.978383  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9781 23:06:40.981413  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9782 23:06:40.988186  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9783 23:06:40.991838  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9784 23:06:40.995127  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9785 23:06:41.001724  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9786 23:06:41.004721  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9787 23:06:41.012018  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9788 23:06:41.014916  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9789 23:06:41.021138  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9790 23:06:41.024782  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9791 23:06:41.027630  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9792 23:06:41.034644  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9793 23:06:41.037834  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9794 23:06:41.044349  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9795 23:06:41.047577  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9796 23:06:41.054309  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9797 23:06:41.057762  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9798 23:06:41.064109  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9799 23:06:41.067362  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9800 23:06:41.070991  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9801 23:06:41.077420  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9802 23:06:41.080888  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9803 23:06:41.087513  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9804 23:06:41.090836  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9805 23:06:41.097628  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9806 23:06:41.101135  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9807 23:06:41.104164  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9808 23:06:41.110981  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9809 23:06:41.113997  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9810 23:06:41.120929  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9811 23:06:41.123610  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9812 23:06:41.130398  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9813 23:06:41.133612  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9814 23:06:41.136814  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9815 23:06:41.143451  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9816 23:06:41.147177  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9817 23:06:41.153681  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9818 23:06:41.156661  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9819 23:06:41.163645  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9820 23:06:41.166746  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9821 23:06:41.169936  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9822 23:06:41.176798  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9823 23:06:41.180161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9824 23:06:41.186664  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9825 23:06:41.190403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9826 23:06:41.197103  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9827 23:06:41.200188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9828 23:06:41.203379  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9829 23:06:41.210575  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9830 23:06:41.213671  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9831 23:06:41.220282  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9832 23:06:41.223956  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9833 23:06:41.230350  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9834 23:06:41.233846  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9835 23:06:41.236908  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9836 23:06:41.243747  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9837 23:06:41.246747  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9838 23:06:41.253696  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9839 23:06:41.257368  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9840 23:06:41.263662  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9841 23:06:41.266820  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9842 23:06:41.273517  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9843 23:06:41.277087  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9844 23:06:41.283922  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9845 23:06:41.286799  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9846 23:06:41.293994  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9847 23:06:41.297337  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9848 23:06:41.300595  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9849 23:06:41.307268  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9850 23:06:41.310374  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9851 23:06:41.317129  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9852 23:06:41.320442  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9853 23:06:41.327008  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9854 23:06:41.329941  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9855 23:06:41.337059  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9856 23:06:41.340625  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9857 23:06:41.347131  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9858 23:06:41.350704  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9859 23:06:41.357329  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9860 23:06:41.360725  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9861 23:06:41.367442  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9862 23:06:41.370506  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9863 23:06:41.376929  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9864 23:06:41.380708  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9865 23:06:41.387053  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9866 23:06:41.390597  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9867 23:06:41.396822  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9868 23:06:41.397322  INFO:    [APUAPC] vio 0

 9869 23:06:41.403631  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9870 23:06:41.407185  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9871 23:06:41.410147  INFO:    [APUAPC] D0_APC_0: 0x400510

 9872 23:06:41.413517  INFO:    [APUAPC] D0_APC_1: 0x0

 9873 23:06:41.416589  INFO:    [APUAPC] D0_APC_2: 0x1540

 9874 23:06:41.419722  INFO:    [APUAPC] D0_APC_3: 0x0

 9875 23:06:41.423108  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9876 23:06:41.426479  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9877 23:06:41.429452  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9878 23:06:41.432878  INFO:    [APUAPC] D1_APC_3: 0x0

 9879 23:06:41.436307  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9880 23:06:41.439688  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9881 23:06:41.443217  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9882 23:06:41.446350  INFO:    [APUAPC] D2_APC_3: 0x0

 9883 23:06:41.449481  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9884 23:06:41.453021  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9885 23:06:41.456281  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9886 23:06:41.459885  INFO:    [APUAPC] D3_APC_3: 0x0

 9887 23:06:41.462989  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9888 23:06:41.466093  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9889 23:06:41.469335  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9890 23:06:41.472726  INFO:    [APUAPC] D4_APC_3: 0x0

 9891 23:06:41.476271  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9892 23:06:41.479428  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9893 23:06:41.482433  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9894 23:06:41.483011  INFO:    [APUAPC] D5_APC_3: 0x0

 9895 23:06:41.486357  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9896 23:06:41.492745  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9897 23:06:41.495656  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9898 23:06:41.496083  INFO:    [APUAPC] D6_APC_3: 0x0

 9899 23:06:41.499292  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9900 23:06:41.502495  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9901 23:06:41.505432  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9902 23:06:41.509175  INFO:    [APUAPC] D7_APC_3: 0x0

 9903 23:06:41.512334  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9904 23:06:41.515782  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9905 23:06:41.518812  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9906 23:06:41.522502  INFO:    [APUAPC] D8_APC_3: 0x0

 9907 23:06:41.525361  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9908 23:06:41.528751  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9909 23:06:41.532294  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9910 23:06:41.535927  INFO:    [APUAPC] D9_APC_3: 0x0

 9911 23:06:41.538694  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9912 23:06:41.542110  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9913 23:06:41.545817  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9914 23:06:41.548849  INFO:    [APUAPC] D10_APC_3: 0x0

 9915 23:06:41.551919  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9916 23:06:41.555710  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9917 23:06:41.558886  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9918 23:06:41.562048  INFO:    [APUAPC] D11_APC_3: 0x0

 9919 23:06:41.565724  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9920 23:06:41.568954  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9921 23:06:41.572361  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9922 23:06:41.575514  INFO:    [APUAPC] D12_APC_3: 0x0

 9923 23:06:41.579042  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9924 23:06:41.582413  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9925 23:06:41.585448  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9926 23:06:41.589009  INFO:    [APUAPC] D13_APC_3: 0x0

 9927 23:06:41.592121  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9928 23:06:41.595602  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9929 23:06:41.598623  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9930 23:06:41.602296  INFO:    [APUAPC] D14_APC_3: 0x0

 9931 23:06:41.605511  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9932 23:06:41.608635  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9933 23:06:41.612238  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9934 23:06:41.615255  INFO:    [APUAPC] D15_APC_3: 0x0

 9935 23:06:41.618866  INFO:    [APUAPC] APC_CON: 0x4

 9936 23:06:41.621974  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9937 23:06:41.625353  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9938 23:06:41.628836  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9939 23:06:41.632429  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9940 23:06:41.636022  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9941 23:06:41.638932  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9942 23:06:41.639477  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9943 23:06:41.642118  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9944 23:06:41.645425  INFO:    [NOCDAPC] D4_APC_0: 0x0

 9945 23:06:41.648944  INFO:    [NOCDAPC] D4_APC_1: 0xfff

 9946 23:06:41.652043  INFO:    [NOCDAPC] D5_APC_0: 0x0

 9947 23:06:41.655543  INFO:    [NOCDAPC] D5_APC_1: 0xfff

 9948 23:06:41.658520  INFO:    [NOCDAPC] D6_APC_0: 0x0

 9949 23:06:41.662554  INFO:    [NOCDAPC] D6_APC_1: 0xfff

 9950 23:06:41.665423  INFO:    [NOCDAPC] D7_APC_0: 0x0

 9951 23:06:41.668994  INFO:    [NOCDAPC] D7_APC_1: 0xfff

 9952 23:06:41.672079  INFO:    [NOCDAPC] D8_APC_0: 0x0

 9953 23:06:41.672610  INFO:    [NOCDAPC] D8_APC_1: 0xfff

 9954 23:06:41.675385  INFO:    [NOCDAPC] D9_APC_0: 0x0

 9955 23:06:41.678425  INFO:    [NOCDAPC] D9_APC_1: 0xfff

 9956 23:06:41.682254  INFO:    [NOCDAPC] D10_APC_0: 0x0

 9957 23:06:41.685804  INFO:    [NOCDAPC] D10_APC_1: 0xfff

 9958 23:06:41.688732  INFO:    [NOCDAPC] D11_APC_0: 0x0

 9959 23:06:41.691535  INFO:    [NOCDAPC] D11_APC_1: 0xfff

 9960 23:06:41.695298  INFO:    [NOCDAPC] D12_APC_0: 0x0

 9961 23:06:41.698378  INFO:    [NOCDAPC] D12_APC_1: 0xfff

 9962 23:06:41.701748  INFO:    [NOCDAPC] D13_APC_0: 0x0

 9963 23:06:41.705314  INFO:    [NOCDAPC] D13_APC_1: 0xfff

 9964 23:06:41.708878  INFO:    [NOCDAPC] D14_APC_0: 0x0

 9965 23:06:41.712039  INFO:    [NOCDAPC] D14_APC_1: 0xfff

 9966 23:06:41.715243  INFO:    [NOCDAPC] D15_APC_0: 0x0

 9967 23:06:41.718540  INFO:    [NOCDAPC] D15_APC_1: 0xfff

 9968 23:06:41.719128  INFO:    [NOCDAPC] APC_CON: 0x4

 9969 23:06:41.721713  INFO:    [APUAPC] set_apusys_apc done

 9970 23:06:41.724929  INFO:    [DEVAPC] devapc_init done

 9971 23:06:41.731576  INFO:    GICv3 without legacy support detected.

 9972 23:06:41.735552  INFO:    ARM GICv3 driver initialized in EL3

 9973 23:06:41.738271  INFO:    Maximum SPI INTID supported: 639

 9974 23:06:41.742058  INFO:    BL31: Initializing runtime services

 9975 23:06:41.747900  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

 9976 23:06:41.751530  INFO:    SPM: enable CPC mode

 9977 23:06:41.754814  INFO:    mcdi ready for mcusys-off-idle and system suspend

 9978 23:06:41.761184  INFO:    BL31: Preparing for EL3 exit to normal world

 9979 23:06:41.764759  INFO:    Entry point address = 0x80000000

 9980 23:06:41.765224  INFO:    SPSR = 0x8

 9981 23:06:41.772266  

 9982 23:06:41.772826  

 9983 23:06:41.773303  

 9984 23:06:41.775011  Starting depthcharge on Spherion...

 9985 23:06:41.775473  

 9986 23:06:41.775835  Wipe memory regions:

 9987 23:06:41.776244  

 9988 23:06:41.779087  end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
 9989 23:06:41.779650  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
 9990 23:06:41.780083  Setting prompt string to ['asurada:']
 9991 23:06:41.780492  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
 9992 23:06:41.781201  	[0x00000040000000, 0x00000054600000)

 9993 23:06:41.900728  

 9994 23:06:41.901238  	[0x00000054660000, 0x00000080000000)

 9995 23:06:42.161070  

 9996 23:06:42.161650  	[0x000000821a7280, 0x000000ffe64000)

 9997 23:06:42.905560  

 9998 23:06:42.906185  	[0x00000100000000, 0x00000240000000)

 9999 23:06:44.796208  

10000 23:06:44.799782  Initializing XHCI USB controller at 0x11200000.

10001 23:06:45.837699  

10002 23:06:45.841169  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10003 23:06:45.841697  

10004 23:06:45.842188  

10005 23:06:45.842649  

10006 23:06:45.843573  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10008 23:06:45.945106  asurada: tftpboot 192.168.201.1 12172395/tftp-deploy-usgu8x7g/kernel/image.itb 12172395/tftp-deploy-usgu8x7g/kernel/cmdline 

10009 23:06:45.945885  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10010 23:06:45.946293  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10011 23:06:45.951005  tftpboot 192.168.201.1 12172395/tftp-deploy-usgu8x7g/kernel/image.ittp-deploy-usgu8x7g/kernel/cmdline 

10012 23:06:45.951436  

10013 23:06:45.951769  Waiting for link

10014 23:06:46.111349  

10015 23:06:46.111873  R8152: Initializing

10016 23:06:46.112319  

10017 23:06:46.114611  Version 9 (ocp_data = 6010)

10018 23:06:46.114994  

10019 23:06:46.118095  R8152: Done initializing

10020 23:06:46.118538  

10021 23:06:46.118900  Adding net device

10022 23:06:48.059912  

10023 23:06:48.060396  done.

10024 23:06:48.060731  

10025 23:06:48.061043  MAC: 00:e0:4c:78:7a:aa

10026 23:06:48.061497  

10027 23:06:48.062464  Sending DHCP discover... done.

10028 23:06:48.063158  

10029 23:06:48.066089  Waiting for reply... done.

10030 23:06:48.066593  

10031 23:06:48.069349  Sending DHCP request... done.

10032 23:06:48.069821  

10033 23:06:48.072512  Waiting for reply... done.

10034 23:06:48.073058  

10035 23:06:48.073562  My ip is 192.168.201.12

10036 23:06:48.074028  

10037 23:06:48.076281  The DHCP server ip is 192.168.201.1

10038 23:06:48.076708  

10039 23:06:48.082683  TFTP server IP predefined by user: 192.168.201.1

10040 23:06:48.083105  

10041 23:06:48.088989  Bootfile predefined by user: 12172395/tftp-deploy-usgu8x7g/kernel/image.itb

10042 23:06:48.089408  

10043 23:06:48.092874  Sending tftp read request... done.

10044 23:06:48.093397  

10045 23:06:48.098544  Waiting for the transfer... 

10046 23:06:48.098943  

10047 23:06:48.372067  00000000 ################################################################

10048 23:06:48.372194  

10049 23:06:48.623998  00080000 ################################################################

10050 23:06:48.624159  

10051 23:06:48.878732  00100000 ################################################################

10052 23:06:48.878867  

10053 23:06:49.139799  00180000 ################################################################

10054 23:06:49.139930  

10055 23:06:49.390548  00200000 ################################################################

10056 23:06:49.390678  

10057 23:06:49.665449  00280000 ################################################################

10058 23:06:49.665607  

10059 23:06:49.933514  00300000 ################################################################

10060 23:06:49.933691  

10061 23:06:50.184879  00380000 ################################################################

10062 23:06:50.185008  

10063 23:06:50.451475  00400000 ################################################################

10064 23:06:50.451607  

10065 23:06:50.719140  00480000 ################################################################

10066 23:06:50.719270  

10067 23:06:50.971864  00500000 ################################################################

10068 23:06:50.971999  

10069 23:06:51.222951  00580000 ################################################################

10070 23:06:51.223085  

10071 23:06:51.474230  00600000 ################################################################

10072 23:06:51.474357  

10073 23:06:51.762257  00680000 ################################################################

10074 23:06:51.762389  

10075 23:06:52.016317  00700000 ################################################################

10076 23:06:52.016443  

10077 23:06:52.268585  00780000 ################################################################

10078 23:06:52.268718  

10079 23:06:52.524593  00800000 ################################################################

10080 23:06:52.524720  

10081 23:06:52.776687  00880000 ################################################################

10082 23:06:52.776824  

10083 23:06:53.045357  00900000 ################################################################

10084 23:06:53.045493  

10085 23:06:53.318203  00980000 ################################################################

10086 23:06:53.318329  

10087 23:06:53.568630  00a00000 ################################################################

10088 23:06:53.568766  

10089 23:06:53.819881  00a80000 ################################################################

10090 23:06:53.820094  

10091 23:06:54.071080  00b00000 ################################################################

10092 23:06:54.071211  

10093 23:06:54.341766  00b80000 ################################################################

10094 23:06:54.341895  

10095 23:06:54.591696  00c00000 ################################################################

10096 23:06:54.591825  

10097 23:06:54.851113  00c80000 ################################################################

10098 23:06:54.851291  

10099 23:06:55.104905  00d00000 ################################################################

10100 23:06:55.105041  

10101 23:06:55.366581  00d80000 ################################################################

10102 23:06:55.366716  

10103 23:06:55.616385  00e00000 ################################################################

10104 23:06:55.616540  

10105 23:06:55.879533  00e80000 ################################################################

10106 23:06:55.879670  

10107 23:06:56.159860  00f00000 ################################################################

10108 23:06:56.160025  

10109 23:06:56.423228  00f80000 ################################################################

10110 23:06:56.423353  

10111 23:06:56.673719  01000000 ################################################################

10112 23:06:56.673872  

10113 23:06:56.933747  01080000 ################################################################

10114 23:06:56.933874  

10115 23:06:57.207146  01100000 ################################################################

10116 23:06:57.207279  

10117 23:06:57.466226  01180000 ################################################################

10118 23:06:57.466367  

10119 23:06:57.716860  01200000 ################################################################

10120 23:06:57.717017  

10121 23:06:57.966434  01280000 ################################################################

10122 23:06:57.966564  

10123 23:06:58.216959  01300000 ################################################################

10124 23:06:58.217092  

10125 23:06:58.467249  01380000 ################################################################

10126 23:06:58.467389  

10127 23:06:58.722420  01400000 ################################################################

10128 23:06:58.722548  

10129 23:06:58.986631  01480000 ################################################################

10130 23:06:58.986764  

10131 23:06:59.240790  01500000 ################################################################

10132 23:06:59.240950  

10133 23:06:59.498458  01580000 ################################################################

10134 23:06:59.498611  

10135 23:06:59.756526  01600000 ################################################################

10136 23:06:59.756660  

10137 23:07:00.007024  01680000 ################################################################

10138 23:07:00.007180  

10139 23:07:00.257058  01700000 ################################################################

10140 23:07:00.257189  

10141 23:07:00.508845  01780000 ################################################################

10142 23:07:00.508979  

10143 23:07:00.759077  01800000 ################################################################

10144 23:07:00.759266  

10145 23:07:01.008836  01880000 ################################################################

10146 23:07:01.008971  

10147 23:07:01.259984  01900000 ################################################################

10148 23:07:01.260115  

10149 23:07:01.510383  01980000 ################################################################

10150 23:07:01.510546  

10151 23:07:01.761271  01a00000 ################################################################

10152 23:07:01.761401  

10153 23:07:02.013928  01a80000 ################################################################

10154 23:07:02.014058  

10155 23:07:02.264081  01b00000 ################################################################

10156 23:07:02.264209  

10157 23:07:02.513432  01b80000 ################################################################

10158 23:07:02.513615  

10159 23:07:02.766326  01c00000 ################################################################

10160 23:07:02.766486  

10161 23:07:03.017778  01c80000 ################################################################

10162 23:07:03.017910  

10163 23:07:03.266183  01d00000 ################################################################

10164 23:07:03.266321  

10165 23:07:03.549150  01d80000 ################################################################

10166 23:07:03.549307  

10167 23:07:03.834464  01e00000 ################################################################

10168 23:07:03.834636  

10169 23:07:04.108490  01e80000 ################################################################

10170 23:07:04.108623  

10171 23:07:04.391003  01f00000 ################################################################

10172 23:07:04.391174  

10173 23:07:04.660459  01f80000 ################################################################

10174 23:07:04.660602  

10175 23:07:04.919327  02000000 ################################################################

10176 23:07:04.919486  

10177 23:07:05.180465  02080000 ################################################################

10178 23:07:05.180597  

10179 23:07:05.439156  02100000 ################################################################

10180 23:07:05.439291  

10181 23:07:05.701795  02180000 ################################################################

10182 23:07:05.701929  

10183 23:07:05.967450  02200000 ################################################################

10184 23:07:05.967604  

10185 23:07:06.227262  02280000 ################################################################

10186 23:07:06.227393  

10187 23:07:06.494716  02300000 ################################################################

10188 23:07:06.494882  

10189 23:07:06.756329  02380000 ################################################################

10190 23:07:06.756463  

10191 23:07:07.010118  02400000 ################################################################

10192 23:07:07.010283  

10193 23:07:07.265107  02480000 ################################################################

10194 23:07:07.265236  

10195 23:07:07.530885  02500000 ################################################################

10196 23:07:07.531019  

10197 23:07:07.781820  02580000 ################################################################

10198 23:07:07.781951  

10199 23:07:08.049075  02600000 ################################################################

10200 23:07:08.049202  

10201 23:07:08.336014  02680000 ################################################################

10202 23:07:08.336179  

10203 23:07:08.585499  02700000 ################################################################

10204 23:07:08.585664  

10205 23:07:08.836327  02780000 ################################################################

10206 23:07:08.836463  

10207 23:07:09.091464  02800000 ################################################################

10208 23:07:09.091619  

10209 23:07:09.343925  02880000 ################################################################

10210 23:07:09.344062  

10211 23:07:09.597917  02900000 ################################################################

10212 23:07:09.598047  

10213 23:07:09.849264  02980000 ################################################################

10214 23:07:09.849401  

10215 23:07:10.100118  02a00000 ################################################################

10216 23:07:10.100294  

10217 23:07:10.349842  02a80000 ################################################################

10218 23:07:10.349981  

10219 23:07:10.603300  02b00000 ################################################################

10220 23:07:10.603479  

10221 23:07:10.854215  02b80000 ################################################################

10222 23:07:10.854348  

10223 23:07:11.113024  02c00000 ################################################################

10224 23:07:11.113154  

10225 23:07:11.366111  02c80000 ################################################################

10226 23:07:11.366298  

10227 23:07:11.623094  02d00000 ################################################################

10228 23:07:11.623238  

10229 23:07:11.902746  02d80000 ################################################################

10230 23:07:11.902905  

10231 23:07:12.157517  02e00000 ################################################################

10232 23:07:12.157686  

10233 23:07:12.418009  02e80000 ################################################################

10234 23:07:12.418186  

10235 23:07:12.705768  02f00000 ################################################################

10236 23:07:12.705927  

10237 23:07:13.002929  02f80000 ################################################################

10238 23:07:13.003070  

10239 23:07:13.269262  03000000 ################################################################

10240 23:07:13.269400  

10241 23:07:13.552877  03080000 ################################################################

10242 23:07:13.553019  

10243 23:07:13.845760  03100000 ################################################################

10244 23:07:13.845903  

10245 23:07:14.139073  03180000 ################################################################

10246 23:07:14.139217  

10247 23:07:14.433596  03200000 ################################################################

10248 23:07:14.433756  

10249 23:07:14.724582  03280000 ################################################################

10250 23:07:14.724725  

10251 23:07:15.024007  03300000 ################################################################

10252 23:07:15.024180  

10253 23:07:15.323338  03380000 ################################################################

10254 23:07:15.323482  

10255 23:07:15.623634  03400000 ################################################################

10256 23:07:15.623804  

10257 23:07:15.923300  03480000 ################################################################

10258 23:07:15.923464  

10259 23:07:16.219065  03500000 ################################################################

10260 23:07:16.219232  

10261 23:07:16.516484  03580000 ################################################################

10262 23:07:16.516661  

10263 23:07:16.810251  03600000 ################################################################

10264 23:07:16.810418  

10265 23:07:17.108985  03680000 ################################################################

10266 23:07:17.109136  

10267 23:07:17.403486  03700000 ################################################################

10268 23:07:17.403657  

10269 23:07:17.681381  03780000 ################################################################

10270 23:07:17.681519  

10271 23:07:17.952212  03800000 ################################################################

10272 23:07:17.952383  

10273 23:07:18.212516  03880000 ################################################################

10274 23:07:18.212738  

10275 23:07:18.465955  03900000 ################################################################

10276 23:07:18.466116  

10277 23:07:18.755936  03980000 ################################################################

10278 23:07:18.756078  

10279 23:07:19.037723  03a00000 ################################################################

10280 23:07:19.037865  

10281 23:07:19.329606  03a80000 ################################################################

10282 23:07:19.329743  

10283 23:07:19.630341  03b00000 ################################################################

10284 23:07:19.630482  

10285 23:07:19.925753  03b80000 ################################################################

10286 23:07:19.925894  

10287 23:07:20.215775  03c00000 ################################################################

10288 23:07:20.215914  

10289 23:07:20.509276  03c80000 ################################################################

10290 23:07:20.509413  

10291 23:07:20.805300  03d00000 ################################################################

10292 23:07:20.805442  

10293 23:07:21.104228  03d80000 ################################################################

10294 23:07:21.104370  

10295 23:07:21.403002  03e00000 ################################################################

10296 23:07:21.403144  

10297 23:07:21.696561  03e80000 ################################################################

10298 23:07:21.696704  

10299 23:07:21.994596  03f00000 ################################################################

10300 23:07:21.994730  

10301 23:07:22.294902  03f80000 ################################################################

10302 23:07:22.295045  

10303 23:07:22.535930  04000000 ##################################################### done.

10304 23:07:22.536066  

10305 23:07:22.539317  The bootfile was 67537006 bytes long.

10306 23:07:22.539408  

10307 23:07:22.543004  Sending tftp read request... done.

10308 23:07:22.543094  

10309 23:07:22.546348  Waiting for the transfer... 

10310 23:07:22.546443  

10311 23:07:22.546518  00000000 # done.

10312 23:07:22.546590  

10313 23:07:22.556623  Command line loaded dynamically from TFTP file: 12172395/tftp-deploy-usgu8x7g/kernel/cmdline

10314 23:07:22.557051  

10315 23:07:22.569703  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10316 23:07:22.570211  

10317 23:07:22.570546  Loading FIT.

10318 23:07:22.570854  

10319 23:07:22.572882  Image ramdisk-1 has 56438347 bytes.

10320 23:07:22.573302  

10321 23:07:22.576673  Image fdt-1 has 47278 bytes.

10322 23:07:22.577191  

10323 23:07:22.579903  Image kernel-1 has 11049348 bytes.

10324 23:07:22.580327  

10325 23:07:22.587229  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10326 23:07:22.587748  

10327 23:07:22.606443  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10328 23:07:22.606970  

10329 23:07:22.609730  Choosing best match conf-1 for compat google,spherion-rev2.

10330 23:07:22.615002  

10331 23:07:22.620027  Connected to device vid:did:rid of 1ae0:0028:00

10332 23:07:22.627808  

10333 23:07:22.631061  tpm_get_response: command 0x17b, return code 0x0

10334 23:07:22.631485  

10335 23:07:22.634320  ec_init: CrosEC protocol v3 supported (256, 248)

10336 23:07:22.638386  

10337 23:07:22.641682  tpm_cleanup: add release locality here.

10338 23:07:22.642108  

10339 23:07:22.642509  Shutting down all USB controllers.

10340 23:07:22.646154  

10341 23:07:22.646818  Removing current net device

10342 23:07:22.647360  

10343 23:07:22.651892  Exiting depthcharge with code 4 at timestamp: 70094454

10344 23:07:22.652370  

10345 23:07:22.655798  LZMA decompressing kernel-1 to 0x821a6718

10346 23:07:22.656332  

10347 23:07:22.658506  LZMA decompressing kernel-1 to 0x40000000

10348 23:07:24.046579  

10349 23:07:24.047125  jumping to kernel

10350 23:07:24.049287  end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10351 23:07:24.049910  start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10352 23:07:24.050336  Setting prompt string to ['Linux version [0-9]']
10353 23:07:24.050712  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10354 23:07:24.051086  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10355 23:07:24.128762  

10356 23:07:24.131821  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10357 23:07:24.135437  start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10358 23:07:24.135943  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10359 23:07:24.136342  Setting prompt string to []
10360 23:07:24.136769  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10361 23:07:24.137174  Using line separator: #'\n'#
10362 23:07:24.137509  No login prompt set.
10363 23:07:24.137912  Parsing kernel messages
10364 23:07:24.138237  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10365 23:07:24.139064  [login-action] Waiting for messages, (timeout 00:03:43)
10366 23:07:24.155161  [    0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec  3 22:38:18 UTC 2023

10367 23:07:24.158196  [    0.000000] random: crng init done

10368 23:07:24.164681  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10369 23:07:24.168424  [    0.000000] efi: UEFI not found.

10370 23:07:24.175028  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10371 23:07:24.181669  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10372 23:07:24.191302  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10373 23:07:24.201065  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10374 23:07:24.208344  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10375 23:07:24.214445  [    0.000000] printk: bootconsole [mtk8250] enabled

10376 23:07:24.221301  [    0.000000] NUMA: No NUMA configuration found

10377 23:07:24.227849  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10378 23:07:24.231167  [    0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]

10379 23:07:24.234951  [    0.000000] Zone ranges:

10380 23:07:24.241373  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10381 23:07:24.244568  [    0.000000]   DMA32    empty

10382 23:07:24.251143  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10383 23:07:24.254700  [    0.000000] Movable zone start for each node

10384 23:07:24.258295  [    0.000000] Early memory node ranges

10385 23:07:24.264420  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10386 23:07:24.271735  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10387 23:07:24.277696  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10388 23:07:24.284418  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10389 23:07:24.287576  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10390 23:07:24.297640  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10391 23:07:24.353317  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10392 23:07:24.359971  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10393 23:07:24.366676  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10394 23:07:24.369972  [    0.000000] psci: probing for conduit method from DT.

10395 23:07:24.377094  [    0.000000] psci: PSCIv1.1 detected in firmware.

10396 23:07:24.380149  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10397 23:07:24.386476  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10398 23:07:24.389865  [    0.000000] psci: SMC Calling Convention v1.2

10399 23:07:24.396554  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10400 23:07:24.399965  [    0.000000] Detected VIPT I-cache on CPU0

10401 23:07:24.406236  [    0.000000] CPU features: detected: GIC system register CPU interface

10402 23:07:24.413293  [    0.000000] CPU features: detected: Virtualization Host Extensions

10403 23:07:24.419875  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10404 23:07:24.426227  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10405 23:07:24.432344  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10406 23:07:24.442224  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10407 23:07:24.446198  [    0.000000] alternatives: applying boot alternatives

10408 23:07:24.452831  [    0.000000] Fallback order for Node 0: 0 

10409 23:07:24.459235  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10410 23:07:24.462166  [    0.000000] Policy zone: Normal

10411 23:07:24.475941  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10412 23:07:24.485410  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10413 23:07:24.497797  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10414 23:07:24.507307  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10415 23:07:24.514242  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10416 23:07:24.517496  <6>[    0.000000] software IO TLB: area num 8.

10417 23:07:24.574189  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10418 23:07:24.722967  <6>[    0.000000] Memory: 7914440K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 438328K reserved, 32768K cma-reserved)

10419 23:07:24.729415  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10420 23:07:24.736157  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10421 23:07:24.739543  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10422 23:07:24.746131  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10423 23:07:24.752721  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10424 23:07:24.756307  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10425 23:07:24.766132  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10426 23:07:24.772623  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10427 23:07:24.775896  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10428 23:07:24.783995  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10429 23:07:24.787240  <6>[    0.000000] GICv3: 608 SPIs implemented

10430 23:07:24.793772  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10431 23:07:24.797304  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10432 23:07:24.800920  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10433 23:07:24.810430  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10434 23:07:24.820235  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10435 23:07:24.833880  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10436 23:07:24.840424  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10437 23:07:24.849708  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10438 23:07:24.862482  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10439 23:07:24.869002  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10440 23:07:24.875712  <6>[    0.009183] Console: colour dummy device 80x25

10441 23:07:24.885635  <6>[    0.013906] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10442 23:07:24.892468  <6>[    0.024413] pid_max: default: 32768 minimum: 301

10443 23:07:24.895776  <6>[    0.029285] LSM: Security Framework initializing

10444 23:07:24.902144  <6>[    0.034223] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10445 23:07:24.911971  <6>[    0.042036] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10446 23:07:24.918915  <6>[    0.051436] cblist_init_generic: Setting adjustable number of callback queues.

10447 23:07:24.925906  <6>[    0.058878] cblist_init_generic: Setting shift to 3 and lim to 1.

10448 23:07:24.935798  <6>[    0.065257] cblist_init_generic: Setting adjustable number of callback queues.

10449 23:07:24.938563  <6>[    0.072684] cblist_init_generic: Setting shift to 3 and lim to 1.

10450 23:07:24.945950  <6>[    0.079160] rcu: Hierarchical SRCU implementation.

10451 23:07:24.952057  <6>[    0.079162] rcu: 	Max phase no-delay instances is 1000.

10452 23:07:24.958851  <6>[    0.079186] printk: bootconsole [mtk8250] printing thread started

10453 23:07:24.966005  <6>[    0.097496] EFI services will not be available.

10454 23:07:24.968846  <6>[    0.097694] smp: Bringing up secondary CPUs ...

10455 23:07:24.972354  <6>[    0.098004] Detected VIPT I-cache on CPU1

10456 23:07:24.981725  <6>[    0.098073] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10457 23:07:24.988824  <6>[    0.098105] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10458 23:07:24.997741  <6>[    0.125975] Detected VIPT I-cache on CPU2

10459 23:07:25.004185  <6>[    0.126023] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10460 23:07:25.014144  <6>[    0.126040] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10461 23:07:25.016995  <6>[    0.126293] Detected VIPT I-cache on CPU3

10462 23:07:25.024044  <6>[    0.126339] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10463 23:07:25.030241  <6>[    0.126353] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10464 23:07:25.033781  <6>[    0.126662] CPU features: detected: Spectre-v4

10465 23:07:25.040666  <6>[    0.126669] CPU features: detected: Spectre-BHB

10466 23:07:25.043682  <6>[    0.126673] Detected PIPT I-cache on CPU4

10467 23:07:25.050491  <6>[    0.126731] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10468 23:07:25.057350  <6>[    0.126747] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10469 23:07:25.063690  <6>[    0.127041] Detected PIPT I-cache on CPU5

10470 23:07:25.070373  <6>[    0.127101] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10471 23:07:25.076757  <6>[    0.127118] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10472 23:07:25.080429  <6>[    0.127392] Detected PIPT I-cache on CPU6

10473 23:07:25.086960  <6>[    0.127456] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10474 23:07:25.093760  <6>[    0.127472] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10475 23:07:25.100247  <6>[    0.127764] Detected PIPT I-cache on CPU7

10476 23:07:25.106494  <6>[    0.127828] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10477 23:07:25.113371  <6>[    0.127844] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10478 23:07:25.116963  <6>[    0.127891] smp: Brought up 1 node, 8 CPUs

10479 23:07:25.123254  <6>[    0.127895] SMP: Total of 8 processors activated.

10480 23:07:25.126196  <6>[    0.127898] CPU features: detected: 32-bit EL0 Support

10481 23:07:25.136423  <6>[    0.127899] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10482 23:07:25.142826  <6>[    0.127902] CPU features: detected: Common not Private translations

10483 23:07:25.149355  <6>[    0.127904] CPU features: detected: CRC32 instructions

10484 23:07:25.155993  <6>[    0.127906] CPU features: detected: RCpc load-acquire (LDAPR)

10485 23:07:25.159711  <6>[    0.127908] CPU features: detected: LSE atomic instructions

10486 23:07:25.165914  <6>[    0.127909] CPU features: detected: Privileged Access Never

10487 23:07:25.172625  <6>[    0.127911] CPU features: detected: RAS Extension Support

10488 23:07:25.178943  <6>[    0.127914] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10489 23:07:25.182401  <6>[    0.127979] CPU: All CPU(s) started at EL2

10490 23:07:25.189284  <6>[    0.127981] alternatives: applying system-wide alternatives

10491 23:07:25.192305  <6>[    0.141058] devtmpfs: initialized

10492 23:07:25.202405  <6>[    0.147339] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10493 23:07:25.231363  ��U���ѕɕ��C}%9Q��ɽѽ����3�����5R�<6>[    0.<364533] printk: console [ttyS0] printing thread started

10494 23:07:25.237552  6<6>[    0.364576] printk: console [ttyS0] enabled

10495 23:07:25.244277  >[    0.228620] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)

10496 23:07:25.251586  <6>[    0.364580] printk: bootconsole [mtk8250] disabled

10497 23:07:25.258549  <6>[    0.382663] printk: bootconsole [mtk8250] printing thread stopped

10498 23:07:25.262029  <6>[    0.383964] SuperH (H)SCI(F) driver initialized

10499 23:07:25.268668  <6>[    0.384437] msm_serial: driver initialized

10500 23:07:25.274994  <6>[    0.389071] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10501 23:07:25.285006  <6>[    0.389098] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10502 23:07:25.291914  <6>[    0.389128] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10503 23:07:25.301646  <6>[    0.389157] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10504 23:07:25.320092  <6>[    0.389179] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10505 23:07:25.320663  <6>[    0.389206] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10506 23:07:25.336471  <6>[    0.389235] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10507 23:07:25.337885  <6>[    0.389348] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10508 23:07:25.350765  <6>[    0.389378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10509 23:07:25.357476  <6>[    0.400206] loop: module loaded

10510 23:07:25.358105  <6>[    0.402827] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10511 23:07:25.360703  <4>[    0.419838] mtk-pmic-keys: Failed to locate of_node [id: -1]

10512 23:07:25.364275  <6>[    0.420820] megasas: 07.719.03.00-rc1

10513 23:07:25.370575  <6>[    0.432648] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10514 23:07:25.377657  <6>[    0.432807] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10515 23:07:25.381078  <6>[    0.444823] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10516 23:07:25.393786  <6>[    0.498710] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10517 23:07:27.531263  <6>[    2.665135] Freeing initrd memory: 55112K

10518 23:07:27.539069  <6>[    2.671328] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10519 23:07:27.545634  <6>[    2.675997] tun: Universal TUN/TAP device driver, 1.6

10520 23:07:27.549033  <6>[    2.676749] thunder_xcv, ver 1.0

10521 23:07:27.552155  <6>[    2.676769] thunder_bgx, ver 1.0

10522 23:07:27.555492  <6>[    2.676783] nicpf, ver 1.0

10523 23:07:27.562058  <6>[    2.677840] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10524 23:07:27.568829  <6>[    2.677843] hns3: Copyright (c) 2017 Huawei Corporation.

10525 23:07:27.572395  <6>[    2.677872] hclge is initializing

10526 23:07:27.579636  <6>[    2.677888] e1000: Intel(R) PRO/1000 Network Driver

10527 23:07:27.582535  <6>[    2.677889] e1000: Copyright (c) 1999-2006 Intel Corporation.

10528 23:07:27.590236  <6>[    2.677907] e1000e: Intel(R) PRO/1000 Network Driver

10529 23:07:27.593972  <6>[    2.677908] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10530 23:07:27.600086  <6>[    2.677924] igb: Intel(R) Gigabit Ethernet Network Driver

10531 23:07:27.607400  <6>[    2.677926] igb: Copyright (c) 2007-2014 Intel Corporation.

10532 23:07:27.614293  <6>[    2.677939] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10533 23:07:27.618029  <6>[    2.677941] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10534 23:07:27.624122  <6>[    2.678234] sky2: driver version 1.30

10535 23:07:27.627621  <6>[    2.679299] VFIO - User Level meta-driver version: 0.3

10536 23:07:27.634164  <6>[    2.682121] usbcore: registered new interface driver usb-storage

10537 23:07:27.641121  <6>[    2.682303] usbcore: registered new device driver onboard-usb-hub

10538 23:07:27.647272  <6>[    2.685065] mt6397-rtc mt6359-rtc: registered as rtc0

10539 23:07:27.653697  <6>[    2.685218] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:05:13 UTC (1701644713)

10540 23:07:27.660659  <6>[    2.685833] i2c_dev: i2c /dev entries driver

10541 23:07:27.667671  <6>[    2.692955] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10542 23:07:27.674018  <6>[    2.707947] cpu cpu0: EM: created perf domain

10543 23:07:27.677080  <6>[    2.708250] cpu cpu4: EM: created perf domain

10544 23:07:27.683959  <6>[    2.711524] sdhci: Secure Digital Host Controller Interface driver

10545 23:07:27.687105  <6>[    2.711525] sdhci: Copyright(c) Pierre Ossman

10546 23:07:27.693989  <6>[    2.711890] Synopsys Designware Multimedia Card Interface Driver

10547 23:07:27.700263  <6>[    2.712254] sdhci-pltfm: SDHCI platform and OF driver helper

10548 23:07:27.707179  <6>[    2.716586] ledtrig-cpu: registered to indicate activity on CPUs

10549 23:07:27.710522  <6>[    2.716954] mmc0: CQHCI version 5.10

10550 23:07:27.717220  <6>[    2.717376] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10551 23:07:27.723492  <6>[    2.717653] usbcore: registered new interface driver usbhid

10552 23:07:27.726904  <6>[    2.717654] usbhid: USB HID core driver

10553 23:07:27.733399  <6>[    2.717770] spi_master spi0: will run message pump with realtime priority

10554 23:07:27.746593  <6>[    2.749600] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10555 23:07:27.759774  <6>[    2.751402] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10556 23:07:27.766644  <6>[    2.753520] cros-ec-spi spi0.0: Chrome EC device registered

10557 23:07:27.776529  <6>[    2.769967] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10558 23:07:27.780258  <6>[    2.772218] NET: Registered PF_PACKET protocol family

10559 23:07:27.786392  <6>[    2.772313] 9pnet: Installing 9P2000 support

10560 23:07:27.789818  <5>[    2.772351] Key type dns_resolver registered

10561 23:07:27.793027  <6>[    2.772718] registered taskstats version 1

10562 23:07:27.799274  <5>[    2.772737] Loading compiled-in X.509 certificates

10563 23:07:27.809269  <4>[    2.796120] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10564 23:07:27.819544  <4>[    2.796278] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10565 23:07:27.826044  <3>[    2.796288] debugfs: File 'uA_load' in directory '/' already present!

10566 23:07:27.832620  <3>[    2.796295] debugfs: File 'min_uV' in directory '/' already present!

10567 23:07:27.839303  <3>[    2.796298] debugfs: File 'max_uV' in directory '/' already present!

10568 23:07:27.845520  <3>[    2.796301] debugfs: File 'constraint_flags' in directory '/' already present!

10569 23:07:27.855595  <3>[    2.798742] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10570 23:07:27.862299  <6>[    2.806492] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10571 23:07:27.868774  <6>[    2.807161] xhci-mtk 11200000.usb: xHCI Host Controller

10572 23:07:27.875766  <6>[    2.807180] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10573 23:07:27.885254  <6>[    2.807390] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10574 23:07:27.892088  <6>[    2.807432] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10575 23:07:27.895382  <6>[    2.807506] xhci-mtk 11200000.usb: xHCI Host Controller

10576 23:07:27.901776  <6>[    2.807512] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10577 23:07:27.911881  <6>[    2.807518] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10578 23:07:27.915296  <6>[    2.808044] hub 1-0:1.0: USB hub found

10579 23:07:27.918553  <6>[    2.808063] hub 1-0:1.0: 1 port detected

10580 23:07:27.928566  <6>[    2.808244] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10581 23:07:27.931841  <6>[    2.808554] hub 2-0:1.0: USB hub found

10582 23:07:27.935242  <6>[    2.808571] hub 2-0:1.0: 1 port detected

10583 23:07:27.941812  <6>[    2.811571] mtk-msdc 11f70000.mmc: Got CD GPIO

10584 23:07:27.944989  <6>[    2.822376] mmc0: Command Queue Engine enabled

10585 23:07:27.951757  <6>[    2.822390] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10586 23:07:27.955235  <6>[    2.823020] mmcblk0: mmc0:0001 DA4128 116 GiB 

10587 23:07:27.965021  <6>[    2.825764] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10588 23:07:27.971901  <6>[    2.825772] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10589 23:07:27.981418  <4>[    2.825930] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10590 23:07:27.988203  <6>[    2.826504]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10591 23:07:27.995159  <6>[    2.826559] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10592 23:07:28.001609  <6>[    2.826563] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10593 23:07:28.011728  <6>[    2.826728] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10594 23:07:28.018073  <6>[    2.826743] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10595 23:07:28.028407  <6>[    2.826747] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10596 23:07:28.034708  <6>[    2.826752] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10597 23:07:28.041387  <6>[    2.828294] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10598 23:07:28.047978  <6>[    2.828668] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10599 23:07:28.057668  <6>[    2.828688] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10600 23:07:28.064738  <6>[    2.828695] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10601 23:07:28.074339  <6>[    2.828702] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10602 23:07:28.080909  <6>[    2.828708] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10603 23:07:28.090500  <6>[    2.828715] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10604 23:07:28.097838  <6>[    2.828721] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10605 23:07:28.107910  <6>[    2.828729] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10606 23:07:28.117636  <6>[    2.828737] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10607 23:07:28.123890  <6>[    2.828743] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10608 23:07:28.134007  <6>[    2.828750] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10609 23:07:28.140514  <6>[    2.828756] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10610 23:07:28.150437  <6>[    2.828763] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10611 23:07:28.156737  <6>[    2.828769] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10612 23:07:28.166811  <6>[    2.828775] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10613 23:07:28.170555  <6>[    2.829059] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10614 23:07:28.177211  <6>[    2.829489] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10615 23:07:28.183080  <6>[    2.829826] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10616 23:07:28.190477  <6>[    2.830431] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10617 23:07:28.196816  <6>[    2.830981] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10618 23:07:28.203532  <6>[    2.831595] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10619 23:07:28.209964  <6>[    2.832226] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10620 23:07:28.220119  <6>[    2.832408] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10621 23:07:28.229722  <6>[    2.832422] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10622 23:07:28.236329  <6>[    2.832427] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10623 23:07:28.246058  <6>[    2.832432] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10624 23:07:28.256032  <6>[    2.832438] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10625 23:07:28.266115  <6>[    2.832444] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10626 23:07:28.276579  <6>[    2.832449] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10627 23:07:28.282873  <6>[    2.832454] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10628 23:07:28.293141  <6>[    2.832458] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10629 23:07:28.302832  <6>[    2.832465] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10630 23:07:28.313298  <6>[    2.832470] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10631 23:07:28.322534  <6>[    2.832853] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10632 23:07:28.329093  <6>[    3.189669] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10633 23:07:28.333031  <6>[    3.216275] hub 2-1:1.0: USB hub found

10634 23:07:28.335946  <6>[    3.216622] hub 2-1:1.0: 3 ports detected

10635 23:07:28.343059  <6>[    3.219311] hub 2-1:1.0: USB hub found

10636 23:07:28.346256  <6>[    3.219669] hub 2-1:1.0: 3 ports detected

10637 23:07:28.352620  <6>[    3.337424] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10638 23:07:28.355850  <6>[    3.489486] hub 1-1:1.0: USB hub found

10639 23:07:28.359289  <6>[    3.489844] hub 1-1:1.0: 4 ports detected

10640 23:07:28.365988  <6>[    3.493077] hub 1-1:1.0: USB hub found

10641 23:07:28.368996  <6>[    3.493386] hub 1-1:1.0: 4 ports detected

10642 23:07:28.438785  <6>[    3.565629] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10643 23:07:28.678592  <6>[    3.805532] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10644 23:07:28.799750  <6>[    3.932892] hub 1-1.4:1.0: USB hub found

10645 23:07:28.802510  <6>[    3.933250] hub 1-1.4:1.0: 2 ports detected

10646 23:07:28.806048  <6>[    3.936930] hub 1-1.4:1.0: USB hub found

10647 23:07:28.812631  <6>[    3.937304] hub 1-1.4:1.0: 2 ports detected

10648 23:07:29.098589  <6>[    4.225552] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10649 23:07:29.282520  <6>[    4.409551] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10650 23:07:40.003340  <6>[   15.138570] ALSA device list:

10651 23:07:40.009910  <6>[   15.138592]   No soundcards found.

10652 23:07:40.012741  <6>[   15.142992] Freeing unused kernel memory: 8448K

10653 23:07:40.016211  <6>[   15.143139] Run /init as init process

10654 23:07:40.054163  <6>[   15.185311] NET: Registered PF_INET6 protocol family

10655 23:07:40.057717  <6>[   15.186334] Segment Routing with IPv6

10656 23:07:40.061061  

10657 23:07:40.067356  Welcome to Debian GNU/Linu<6>[   15.186352] In-situ OAM (IOAM) with IPv6

10658 23:07:40.091014  <30>[   15.198815] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10659 23:07:40.094206  <30>[   15.199282] systemd[1]: Detected architecture arm64.

10660 23:07:40.097417  x 11 (bullseye)!

10661 23:07:40.097980  

10662 23:07:40.113980  <30>[   15.245734] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10663 23:07:40.293154  <30>[   15.421792] systemd[1]: Queued start job for default target Graphical Interface.

10664 23:07:40.327142  [  OK  ] Created slic<30>[   15.458657] systemd[1]: Created slice system-getty.slice.

10665 23:07:40.330192  e system-getty.slice.

10666 23:07:40.354212  [  OK  ] Created slice syste<30>[   15.482442] systemd[1]: Created slice system-modprobe.slice.

10667 23:07:40.354780  m-modprobe.slice.

10668 23:07:40.376009  [  OK  ] Created slic<30>[   15.507167] systemd[1]: Created slice system-serial\x2dgetty.slice.

10669 23:07:40.382302  e system-serial\x2dgetty.slice.

10670 23:07:40.399996  [  OK  ] Created slic<30>[   15.531246] systemd[1]: Created slice User and Session Slice.

10671 23:07:40.403434  e User and Session Slice.

10672 23:07:40.426360  [  OK  ] Started Dispatch Pa<30>[   15.554344] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10673 23:07:40.429722  ssword …ts to Console Directory Watch.

10674 23:07:40.454260  [  OK  ] Started Forward Pas<30>[   15.582300] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10675 23:07:40.457336  sword R…uests to Wall Directory Watch.

10676 23:07:40.485101  [  OK  ] Reached target Loca<30>[   15.610082] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10677 23:07:40.494901  l Encrypted Volu<30>[   15.610365] systemd[1]: Reached target Local Encrypted Volumes.

10678 23:07:40.495461  mes.

10679 23:07:40.514087  [  OK  ] Reached target Path<30>[   15.645650] systemd[1]: Reached target Paths.

10680 23:07:40.514666  s.

10681 23:07:40.537685  [  OK  ] Reached target Remo<30>[   15.665553] systemd[1]: Reached target Remote File Systems.

10682 23:07:40.538486  te File Systems.

10683 23:07:40.553793  [  OK  ] Reached target Slic<30>[   15.685540] systemd[1]: Reached target Slices.

10684 23:07:40.554376  es.

10685 23:07:40.573701  [  OK  ] Reached target Swap<30>[   15.705551] systemd[1]: Reached target Swap.

10686 23:07:40.574278  .

10687 23:07:40.597750  [  OK  ] Listening on initct<30>[   15.725963] systemd[1]: Listening on initctl Compatibility Named Pipe.

10688 23:07:40.600682  l Compatibility Named Pipe.

10689 23:07:40.607386  [  OK  [<30>[   15.741058] systemd[1]: Listening on Journal Audit Socket.

10690 23:07:40.614077  0m] Listening on Journal Audit Socket.

10691 23:07:40.630785  [  OK  ] Listening on<30>[   15.762710] systemd[1]: Listening on Journal Socket (/dev/log).

10692 23:07:40.634471   Journal Socket (/dev/log).

10693 23:07:40.655417  [  OK  ] Listening on<30>[   15.786833] systemd[1]: Listening on Journal Socket.

10694 23:07:40.658247   Journal Socket.

10695 23:07:40.674108  [  OK  ] Listening on udev C<30>[   15.806104] systemd[1]: Listening on udev Control Socket.

10696 23:07:40.677507  ontrol Socket.

10697 23:07:40.699003  [  OK  ] Listening on<30>[   15.830561] systemd[1]: Listening on udev Kernel Socket.

10698 23:07:40.702448   udev Kernel Socket.

10699 23:07:40.761488           Mounting Huge Pages File Syste<30>[   15.889817] systemd[1]: Mounting Huge Pages File System...

10700 23:07:40.762130  m...

10701 23:07:40.780866           Mountin<30>[   15.912619] systemd[1]: Mounting POSIX Message Queue File System...

10702 23:07:40.783766  g POSIX Message Queue File System...

10703 23:07:40.803954           Mounting Kerne<30>[   15.935489] systemd[1]: Mounting Kernel Debug File System...

10704 23:07:40.807443  l Debug File System...

10705 23:07:40.832200           Startin<30>[   15.957844] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10706 23:07:40.842160  g Creat<30>[   15.960431] systemd[1]: Starting Create list of static device nodes for the current kernel...

10707 23:07:40.844936  e list of st…odes for the current kernel...

10708 23:07:40.869357           Starting Load Kernel Module co<30>[   15.997965] systemd[1]: Starting Load Kernel Module configfs...

10709 23:07:40.869956  nfigfs...

10710 23:07:40.893752           Starting Load Kernel Module dr<30>[   16.021819] systemd[1]: Starting Load Kernel Module drm...

10711 23:07:40.894329  m...

10712 23:07:40.913652  <30>[   16.041935] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10713 23:07:40.927425           Starting Journ<30>[   16.058735] systemd[1]: Starting Journal Service...

10714 23:07:40.927986  al Service...

10715 23:07:40.950663           Starting Load Kernel Modules[<30>[   16.082380] systemd[1]: Starting Load Kernel Modules...

10716 23:07:40.954324  0m...

10717 23:07:40.978163           Starting Remount Root and Kern<30>[   16.106001] systemd[1]: Starting Remount Root and Kernel File Systems...

10718 23:07:40.980992  el File Systems...

10719 23:07:40.998299  <30>[   16.133090] systemd[1]: Starting Coldplug All udev Devices...

10720 23:07:41.004662           Starting Coldplug All udev Devices...

10721 23:07:41.021571  [  OK  [<30>[   16.156655] systemd[1]: Started Journal Service.

10722 23:07:41.028180  0m] Started Journal Service.

10723 23:07:41.044464  [  OK  ] Mounted Huge Pages File System.

10724 23:07:41.063418  [  OK  ] Mounted POSIX Message Queue File System.

10725 23:07:41.079201  [  OK  ] Mounted Kernel Debug File System.

10726 23:07:41.099542  [  OK  ] Finished Create list of st… nodes for the current kernel.

10727 23:07:41.117045  [  OK  ] Finished Load Kernel Module configfs.

10728 23:07:41.137173  [  OK  ] Finished Load Kernel Module drm.

10729 23:07:41.157144  [  OK  ] Finished Load Kernel Modules.

10730 23:07:41.176519  [FAILED] Failed to start Remount Root and Kernel File Systems.

10731 23:07:41.190538  See 'systemctl status systemd-remount-fs.service' for details.

10732 23:07:41.230955           Mounting Kernel Configuration File System...

10733 23:07:41.250936           Starting Flush Journal to Persistent Storage...

10734 23:07:41.265667  <46>[   16.396062] systemd-journald[187]: Received client request to flush runtime journal.

10735 23:07:41.275683           Starting Load/Save Random Seed...

10736 23:07:41.295491           Starting Apply Kernel Variables...

10737 23:07:41.315328           Starting Create System Users...

10738 23:07:41.334152  [  OK  ] Finished Coldplug All udev Devices.

10739 23:07:41.350875  [  OK  ] Mounted Kernel Configuration File System.

10740 23:07:41.370704  [  OK  ] Finished Flush Journal to Persistent Storage.

10741 23:07:41.383611  [  OK  ] Finished Load/Save Random Seed.

10742 23:07:41.400115  [  OK  ] Finished Apply Kernel Variables.

10743 23:07:41.415922  [  OK  ] Finished Create System Users.

10744 23:07:41.455755           Starting Create Static Device Nodes in /dev...

10745 23:07:41.475894  [  OK  ] Finished Create Static Device Nodes in /dev.

10746 23:07:41.490676  [  OK  ] Reached target Local File Systems (Pre).

10747 23:07:41.507439  [  OK  ] Reached target Local File Systems.

10748 23:07:41.526516           Starting Create Volatile Files and Directories...

10749 23:07:41.550329           Starting Rule-based Manage…for Device Events and Files...

10750 23:07:41.573214  [  OK  ] Started Rule-based Manager for Device Events and Files.

10751 23:07:41.593267  [  OK  ] Finished Create Volatile Files and Directories.

10752 23:07:41.620211           Starting Network Time Synchronization...

10753 23:07:41.643656           Starting Update UTMP about System Boot/Shutdown...

10754 23:07:41.687009  [  OK  ] Started Network Time Synchronization.

10755 23:07:41.714320  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10756 23:07:41.725271  <6>[   16.855858] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10757 23:07:41.733292  <6>[   16.862396] remoteproc remoteproc0: scp is available

10758 23:07:41.739945  <6>[   16.862753] remoteproc remoteproc0: powering up scp

10759 23:07:41.746826  <6>[   16.862782] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10760 23:07:41.753738  <6>[   16.862885] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10761 23:07:41.760042  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10762 23:07:41.781407  [  OK  ] Reached target Syst<6>[   16.912797] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10763 23:07:41.791435  em Time Set.<6>[   16.912838] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10764 23:07:41.791998  

10765 23:07:41.801231  <6>[   16.912843] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10766 23:07:41.807518  <3>[   16.928505] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10767 23:07:41.818124  <3>[   16.928527] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10768 23:07:41.824475  <3>[   16.928535] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10769 23:07:41.837360  [  OK  ] Reached target Syst<3>[   16.952814] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10770 23:07:41.847277  em Time Synchron<3>[   16.952829] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10771 23:07:41.854334  <3>[   16.952832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10772 23:07:41.857457  ized.

10773 23:07:41.864185  <3>[   16.952837] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10774 23:07:41.870418  <3>[   16.952840] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10775 23:07:41.880725  <3>[   16.958024] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10776 23:07:41.887987  <3>[   16.968852] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10777 23:07:41.898574  <3>[   16.968876] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10778 23:07:41.904941  <3>[   16.968885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10779 23:07:41.911590  <3>[   16.982555] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10780 23:07:41.921732  <3>[   16.982580] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10781 23:07:41.928906  <3>[   16.982588] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10782 23:07:41.938265  <3>[   16.982598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10783 23:07:41.946250  <3>[   16.982606] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10784 23:07:41.952618  <6>[   16.987898] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10785 23:07:41.959063  <4>[   16.993529] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10786 23:07:41.969896  <6>[   16.995566] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10787 23:07:41.976755  <6>[   16.995570] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10788 23:07:41.983050  <6>[   16.995577] remoteproc remoteproc0: remote processor scp is now up

10789 23:07:41.990395  <3>[   17.005315] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10790 23:07:41.997513  <4>[   17.005395] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10791 23:07:42.007528  <4>[   17.011641] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10792 23:07:42.010539  <4>[   17.011641] Fallback method does not support PEC.

10793 23:07:42.020846  <3>[   17.030267] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10794 23:07:42.028096  <6>[   17.045861] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10795 23:07:42.031482  <6>[   17.045882] pci_bus 0000:00: root bus resource [bus 00-ff]

10796 23:07:42.038205  <6>[   17.045890] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10797 23:07:42.048716  <6>[   17.045895] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10798 23:07:42.056668  <6>[   17.045947] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10799 23:07:42.063322  <6>[   17.045987] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10800 23:07:42.066092  <6>[   17.046090] pci 0000:00:00.0: supports D1 D2

10801 23:07:42.073390  <6>[   17.046093] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10802 23:07:42.080138  <6>[   17.048185] mc: Linux media interface: v0.10

10803 23:07:42.087141  <3>[   17.061898] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10804 23:07:42.096824  <6>[   17.068258] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10805 23:07:42.103511  <6>[   17.068460] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10806 23:07:42.110478  <6>[   17.068495] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10807 23:07:42.117127  <6>[   17.068518] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10808 23:07:42.124249  <6>[   17.068536] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10809 23:07:42.127813  <6>[   17.068701] pci 0000:01:00.0: supports D1 D2

10810 23:07:42.138076  <6>[   17.068705] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10811 23:07:42.141239  <6>[   17.077418] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10812 23:07:42.151286  <6>[   17.077595] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10813 23:07:42.158347  <6>[   17.077605] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10814 23:07:42.165256  <6>[   17.077623] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10815 23:07:42.175191  <6>[   17.077640] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10816 23:07:42.182855  <6>[   17.077656] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10817 23:07:42.189617  <6>[   17.077675] pci 0000:00:00.0: PCI bridge to [bus 01]

10818 23:07:42.196074           Startin<6>[   17.077688] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10819 23:07:42.202926  <6>[   17.078127] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10820 23:07:42.209390  <6>[   17.078198] videodev: Linux video capture interface: v2.00

10821 23:07:42.216027  <6>[   17.080554] usbcore: registered new interface driver r8152

10822 23:07:42.222640  <6>[   17.083786] pcieport 0000:00:00.0: PME: Signaling with IRQ 282

10823 23:07:42.226025  <6>[   17.084045] pcieport 0000:00:00.0: AER: enabled with IRQ 282

10824 23:07:42.236067  <3>[   17.088537] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10825 23:07:42.246269  <3>[   17.110234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10826 23:07:42.252420  <6>[   17.120207] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10827 23:07:42.262454  <3>[   17.133810] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10828 23:07:42.272364  <6>[   17.161292] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10829 23:07:42.278893  <6>[   17.163193] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10830 23:07:42.288707  <6>[   17.165792] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10831 23:07:42.299153  <6>[   17.166090] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10832 23:07:42.305296  <6>[   17.169589] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10833 23:07:42.315744  <3>[   17.182322] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10834 23:07:42.322149  <3>[   17.184297] power_supply sbs-5-000b: driver failed to report `current_now' property: -6

10835 23:07:42.332387  <4>[   17.193137] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10836 23:07:42.338339  <4>[   17.193145] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10837 23:07:42.345385  <6>[   17.196450] usbcore: registered new interface driver cdc_ether

10838 23:07:42.355195  <3>[   17.199640] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10839 23:07:42.361666  <3>[   17.200440] power_supply sbs-5-000b: driver failed to report `capacity_level' property: -6

10840 23:07:42.371757  <5>[   17.207082] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10841 23:07:42.378172  <6>[   17.208475] usbcore: registered new interface driver r8153_ecm

10842 23:07:42.384862  <5>[   17.219059] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10843 23:07:42.391226  <4>[   17.219123] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10844 23:07:42.397899  <6>[   17.219130] cfg80211: failed to load regulatory.db

10845 23:07:42.401489  <6>[   17.219372] r8152 2-1.3:1.0 eth0: v1.12.13

10846 23:07:42.404966  <6>[   17.226081] Bluetooth: Core ver 2.22

10847 23:07:42.411189  <6>[   17.226143] NET: Registered PF_BLUETOOTH protocol family

10848 23:07:42.418113  <6>[   17.226145] Bluetooth: HCI device and connection manager initialized

10849 23:07:42.424848  <6>[   17.226161] Bluetooth: HCI socket layer initialized

10850 23:07:42.428026  <6>[   17.226166] Bluetooth: L2CAP socket layer initialized

10851 23:07:42.434309  <6>[   17.226178] Bluetooth: SCO socket layer initialized

10852 23:07:42.441325  <6>[   17.232076] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0

10853 23:07:42.448072  <6>[   17.238841] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10854 23:07:42.454199  <3>[   17.240139] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10855 23:07:42.467696  <6>[   17.240653] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10856 23:07:42.474545  <6>[   17.240884] usbcore: registered new interface driver uvcvideo

10857 23:07:42.480808  <6>[   17.277261] usbcore: registered new interface driver btusb

10858 23:07:42.491131  <4>[   17.278242] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10859 23:07:42.497638  <3>[   17.278260] Bluetooth: hci0: Failed to load firmware file (-2)

10860 23:07:42.500883  <3>[   17.278263] Bluetooth: hci0: Failed to set up firmware (-2)

10861 23:07:42.514018  <4>[   17.278267] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10862 23:07:42.520318  <6>[   17.291905] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10863 23:07:42.526862  <6>[   17.538329] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10864 23:07:42.533449  <6>[   17.538425] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10865 23:07:42.537040  <6>[   17.557441] mt7921e 0000:01:00.0: ASIC revision: 79610010

10866 23:07:42.550327  <4>[   17.652414] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10867 23:07:42.556575  g Load/Save Screen …of leds:white:kbd_backlight...

10868 23:07:42.578134  [  OK  ] Finished Load/Save Screen …s of leds:white:kbd_backlight.

10869 23:07:42.600647  [  OK  ] Found device /dev/ttyS0.

10870 23:07:42.632325  <4>[   17.759652] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10871 23:07:42.740553  <4>[   17.867198] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10872 23:07:42.751988  [  OK  ] Reached target Bluetooth.

10873 23:07:42.766337  [  OK  ] Reached target System Initialization.

10874 23:07:42.785766  [  OK  ] Started Discard unused blocks once a week.

10875 23:07:42.801222  [  OK  ] Started Daily Cleanup of Temporary Directories.

10876 23:07:42.814252  [  OK  ] Reached target Timers.

10877 23:07:42.834880  [  OK  ] Listening on D-Bus System Message Bus Socket.

10878 23:07:42.844870  <4>[   17.971902] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10879 23:07:42.851166  [  OK  ] Reached target Sockets.

10880 23:07:42.865616  [  OK  ] Reached target Basic System.

10881 23:07:42.885475  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10882 23:07:42.931628  [  OK  ] Started D-Bus System Message Bus.

10883 23:07:42.955926  <4>[   18.081985] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10884 23:07:42.976118           Starting User Login Management...

10885 23:07:42.994381           Starting Permit User Sessions...

10886 23:07:43.016147           Starting Load/Save RF Kill Switch Status...

10887 23:07:43.035072  [  OK  ] Started Load/Save RF Kill Switch Status.

10888 23:07:43.065665  [  OK  ] Finished [0<4>[   18.191697] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10889 23:07:43.068583  ;1;39mPermit User Sessions.

10890 23:07:43.087989  [  OK  ] Started User Login Management.

10891 23:07:43.135538  [  OK  ] Started Getty on tty1.

10892 23:07:43.177423  [  OK  ] Started Serial Gett<4>[   18.305135] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10893 23:07:43.180533  y on ttyS0.

10894 23:07:43.186930  [  OK  ] Reached target Login Prompts.

10895 23:07:43.207686  [  OK  ] Reached target Multi-User System.

10896 23:07:43.225901  [  OK  ] Reached target Graphical Interface.

10897 23:07:43.284748  <4>[   18.411881] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10898 23:07:43.296693           Starting Update UTMP about System Runlevel Changes...

10899 23:07:43.335350  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10900 23:07:43.396734  <4>[   18.524108] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10901 23:07:43.397311  

10902 23:07:43.397716  

10903 23:07:43.403432  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10904 23:07:43.404126  

10905 23:07:43.406526  debian-bullseye-arm64 login: root (automatic login)

10906 23:07:43.406981  

10907 23:07:43.407469  

10908 23:07:43.423122  Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec  3 22:38:18 UTC 2023 aarch64

10909 23:07:43.423780  

10910 23:07:43.430169  The programs included with the Debian GNU/Linux system are free software;

10911 23:07:43.436524  the exact distribution terms for each program are described in the

10912 23:07:43.439926  individual files in /usr/share/doc/*/copyright.

10913 23:07:43.440340  

10914 23:07:43.446397  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10915 23:07:43.449748  permitted by applicable law.

10916 23:07:43.451061  Matched prompt #10: / #
10918 23:07:43.452037  Setting prompt string to ['/ #']
10919 23:07:43.452454  end: 2.2.5.1 login-action (duration 00:00:19) [common]
10921 23:07:43.453386  end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10922 23:07:43.453858  start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10923 23:07:43.454201  Setting prompt string to ['/ #']
10924 23:07:43.454509  Forcing a shell prompt, looking for ['/ #']
10926 23:07:43.505370  / # 

10927 23:07:43.506070  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10928 23:07:43.506540  Waiting using forced prompt support (timeout 00:02:30)
10929 23:07:43.554092  <4>[   18.640208] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10930 23:07:43.554660  

10931 23:07:43.555517  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10932 23:07:43.556014  start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10933 23:07:43.556516  end: 2.2.7 export-device-env (duration 00:00:00) [common]
10934 23:07:43.556978  end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10935 23:07:43.557449  end: 2 depthcharge-action (duration 00:01:36) [common]
10936 23:07:43.557989  start: 3 lava-test-retry (timeout 00:08:00) [common]
10937 23:07:43.558470  start: 3.1 lava-test-shell (timeout 00:08:00) [common]
10938 23:07:43.558869  Using namespace: common
10940 23:07:43.660065  / # #

10941 23:07:43.660731  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10942 23:07:43.661292  <3>[   18.746073] mt7921e 0000:01:00.0: hardware init failed

10943 23:07:43.666020  #

10944 23:07:43.666777  Using /lava-12172395
10946 23:07:43.768243  / # export SHELL=/bin/sh

10947 23:07:43.774963  export SHELL=/bin/sh

10949 23:07:43.876667  / # . /lava-12172395/environment

10950 23:07:43.883338  . /lava-12172395/environment

10952 23:07:43.985238  / # /lava-12172395/bin/lava-test-runner /lava-12172395/0

10953 23:07:43.985925  Test shell timeout: 10s (minimum of the action and connection timeout)
10954 23:07:43.992019  /lava-12172395/bin/lava-test-runner /lava-12172395/0

10955 23:07:44.015775  + export TESTRUN_ID=0_igt-gpu-panfrost

10956 23:07:44.025877  + cd /lava-12172395/0/tests/0_igt-gpu-pa<8>[   19.153845] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 12172395_1.5.2.3.1>

10957 23:07:44.026455  nfrost

10958 23:07:44.026823  + cat uuid

10959 23:07:44.027455  Received signal: <STARTRUN> 0_igt-gpu-panfrost 12172395_1.5.2.3.1
10960 23:07:44.027826  Starting test lava.0_igt-gpu-panfrost (12172395_1.5.2.3.1)
10961 23:07:44.028268  Skipping test definition patterns.
10962 23:07:44.028799  + UUID=12172395_1.5.2.3.1

10963 23:07:44.029160  + set +x

10964 23:07:44.038929  + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit

10965 23:07:44.046040  <8>[   19.178997] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>

10966 23:07:44.046885  Received signal: <TESTSET> START panfrost_gem_new
10967 23:07:44.047292  Starting test_set panfrost_gem_new
10968 23:07:44.057284  IGT-Version: 1.2<14>[   19.192969] [IGT] panfrost_gem_new: executing

10969 23:07:44.067498  7.1-g621c2d3 (aarch64) (Linux: 6<14>[   19.199308] [IGT] panfrost_gem_new: exiting, ret=77

10970 23:07:44.074183  <8>[   19.203753] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>

10971 23:07:44.075040  Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
10973 23:07:44.077703  .1.64-cip10-rt5 aarch64)

10974 23:07:44.084390  Test requirement not m<14>[   19.215323] [IGT] panfrost_gem_new: executing

10975 23:07:44.087428  <14>[   19.217462] [IGT] panfrost_gem_new: exiting, ret=77

10976 23:07:44.097483  et in function d<8>[   19.227562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>

10977 23:07:44.098348  Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
10979 23:07:44.100823  rm_open_driver, file ../lib/drmtest.c:621:

10980 23:07:44.107278  Test requirement: !(<14>[   19.238940] [IGT] panfrost_gem_new: executing

10981 23:07:44.110818  <14>[   19.240930] [IGT] panfrost_gem_new: exiting, ret=77

10982 23:07:44.117488  <8>[   19.245800] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>

10983 23:07:44.118391  Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
10985 23:07:44.123631  <8>[   19.247107] <LAVA_SIGNAL_TESTSET STOP>

10986 23:07:44.124202  fd<0)

10987 23:07:44.124848  Received signal: <TESTSET> STOP
10988 23:07:44.125234  Closing test_set panfrost_gem_new
10989 23:07:44.127126  No known gpu found for chipset flags 0x32 (panfrost)

10990 23:07:44.130210  Last errno: 2, No such file or directory

10991 23:07:44.140027  Subtest gem-new-4096:<8>[   19.272971] <LAVA_SIGNAL_TESTSET START panfrost_get_param>

10992 23:07:44.140500   SKIP (0.000s)

10993 23:07:44.141219  Received signal: <TESTSET> START panfrost_get_param
10994 23:07:44.141643  Starting test_set panfrost_get_param
10995 23:07:44.150301  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[   19.284964] [IGT] panfrost_get_param: executing

10996 23:07:44.153762  x: 6.1.64-cip10-rt5 aarch64)

10997 23:07:44.160218  Test requirement n<14>[   19.290728] [IGT] panfrost_get_param: exiting, ret=77

10998 23:07:44.166656  ot met in functi<8>[   19.295214] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>

10999 23:07:44.167199  Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11001 23:07:44.172773  on drm_open_driv<14>[   19.308498] [IGT] panfrost_get_param: executing

11002 23:07:44.176052  er, file ../lib/drmtest.c:621:

11003 23:07:44.182959  Test requirement<14>[   19.314955] [IGT] panfrost_get_param: exiting, ret=77

11004 23:07:44.189384  <8>[   19.319595] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>

11005 23:07:44.189503  : !(fd<0)

11006 23:07:44.189791  Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11008 23:07:44.199645  No known gpu found fo<14>[   19.331750] [IGT] panfrost_get_param: executing

11009 23:07:44.199748  r chipset flags 0x32 (panfrost)

11010 23:07:44.206145  <14>[   19.339313] [IGT] panfrost_get_param: exiting, ret=77

11011 23:07:44.212634  <8>[   19.343580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>

11012 23:07:44.212892  Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11014 23:07:44.215705  <8>[   19.344836] <LAVA_SIGNAL_TESTSET STOP>

11015 23:07:44.215788  

11016 23:07:44.216023  Received signal: <TESTSET> STOP
11017 23:07:44.216092  Closing test_set panfrost_get_param
11018 23:07:44.222701  Last errno: 2, No such file or directory

11019 23:07:44.225750  Subtest gem-new-0: SKIP (0.000s)

11020 23:07:44.232806  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11021 23:07:44.239326  Test requirement <8>[   19.370136] <LAVA_SIGNAL_TESTSET START panfrost_prime>

11022 23:07:44.239585  Received signal: <TESTSET> START panfrost_prime
11023 23:07:44.239658  Starting test_set panfrost_prime
11024 23:07:44.242682  not met in function drm_open_driver, file ../lib/drmtest.c:621:

11025 23:07:44.249025  Test requiremen<14>[   19.382697] [IGT] panfrost_prime: executing

11026 23:07:44.249108  t: !(fd<0)

11027 23:07:44.255944  No k<14>[   19.384734] [IGT] panfrost_prime: exiting, ret=77

11028 23:07:44.262576  <8>[   19.389145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>

11029 23:07:44.262840  Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11031 23:07:44.265736  <8>[   19.390508] <LAVA_SIGNAL_TESTSET STOP>

11032 23:07:44.265990  Received signal: <TESTSET> STOP
11033 23:07:44.266062  Closing test_set panfrost_prime
11034 23:07:44.272239  nown gpu found for chipset flags 0x32 (panfrost)

11035 23:07:44.275660  Last errno: 2, No such file or directory

11036 23:07:44.282225  Subtest gem-new-<8>[   19.417226] <LAVA_SIGNAL_TESTSET START panfrost_submit>

11037 23:07:44.282481  Received signal: <TESTSET> START panfrost_submit
11038 23:07:44.282554  Starting test_set panfrost_submit
11039 23:07:44.285729  zeroed: SKIP (0.000s)

11040 23:07:44.292164  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11041 23:07:44.299027  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11042 23:07:44.305539  Test requirement: !(fd<0)<14>[   19.438575] [IGT] panfrost_submit: executing

11043 23:07:44.305634  

11044 23:07:44.315647  No known gpu found for chipset flags 0x32 (pan<14>[   19.446543] [IGT] panfrost_submit: exiting, ret=77

11045 23:07:44.322262  <8>[   19.451871] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>

11046 23:07:44.322351  frost)

11047 23:07:44.322590  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11049 23:07:44.328954  Last errno: 2, No such file or directory<14>[   19.464388] [IGT] panfrost_submit: executing

11050 23:07:44.329039  

11051 23:07:44.338660  Subtest base-params: SKIP <14>[   19.471470] [IGT] panfrost_submit: exiting, ret=77

11052 23:07:44.345732  <8>[   19.476690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>

11053 23:07:44.345991  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11055 23:07:44.348633  (0.000s)

11056 23:07:44.352129  IGT-Version: 1.27.<14>[   19.488645] [IGT] panfrost_submit: executing

11057 23:07:44.361887  1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aa<14>[   19.494686] [IGT] panfrost_submit: exiting, ret=77

11058 23:07:44.371911  <8>[   19.499141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>

11059 23:07:44.372005  rch64)

11060 23:07:44.372244  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11062 23:07:44.378661  Test req<14>[   19.512462] [IGT] panfrost_submit: executing

11063 23:07:44.385385  uirement not met in function drm_open_driver, fi<14>[   19.518519] [IGT] panfrost_submit: exiting, ret=77

11064 23:07:44.395228  <8>[   19.522806] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>

11065 23:07:44.395490  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11067 23:07:44.402285  le ../lib/drmtes<14>[   19.536449] [IGT] panfrost_submit: executing

11068 23:07:44.402370  t.c:621:

11069 23:07:44.405829  Test requirement: !(fd<0)

11070 23:07:44.408672  No known gp<14>[   19.542700] [IGT] panfrost_submit: exiting, ret=77

11071 23:07:44.418837  <8>[   19.547005] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>

11072 23:07:44.419099  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11074 23:07:44.422092  u found for chipset flags 0x32 (panfrost)

11075 23:07:44.425290  Last errno: 2, No such file or directory

11076 23:07:44.432279  Subtest get-bad-param: <14>[   19.567663] [IGT] panfrost_submit: executing

11077 23:07:44.435328  SKIP (0.000s)

11078 23:07:44.441999  IGT-Version: <14>[   19.575148] [IGT] panfrost_submit: exiting, ret=77

11079 23:07:44.448505  <8>[   19.580566] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>

11080 23:07:44.448802  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11082 23:07:44.455594  1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11083 23:07:44.465285  Test requirement not met in function drm_open_driver, file ../lib/d<14>[   19.600499] [IGT] panfrost_submit: executing

11084 23:07:44.465415  rmtest.c:621:

11085 23:07:44.472233  Test requirement:<14>[   19.607337] [IGT] panfrost_submit: exiting, ret=77

11086 23:07:44.479211  Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11088 23:07:44.482141  <8>[   19.612683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>

11089 23:07:44.482226   !(fd<0)

11090 23:07:44.485307  No known gpu found for chipset flags 0x32 (panfrost)

11091 23:07:44.488904  Last errno: 2, No such file or directory

11092 23:07:44.495203  Subtest get-bad-padding: SKIP (0.000s)

11093 23:07:44.502151  IGT-Version: 1.27.1-g621c2d3 (aarch64)<14>[   19.634812] [IGT] panfrost_submit: executing

11094 23:07:44.508715   (Linux: 6.1.64-cip10-rt5 aarch6<14>[   19.643226] [IGT] panfrost_submit: exiting, ret=77

11095 23:07:44.518581  <8>[   19.648602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>

11096 23:07:44.518665  4)

11097 23:07:44.518907  Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11099 23:07:44.525469  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11100 23:07:44.528302  Test requirement: !(fd<0)

11101 23:07:44.531651  No known gpu found for chipset flags 0x32 (panfrost)

11102 23:07:44.538151  Last errn<14>[   19.671308] [IGT] panfrost_submit: executing

11103 23:07:44.541447  o: 2, No such file or directory

11104 23:07:44.545049  Subtest gem<14>[   19.678838] [IGT] panfrost_submit: exiting, ret=77

11105 23:07:44.554549  <8>[   19.684035] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>

11106 23:07:44.554816  Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11108 23:07:44.558047  <8>[   19.685525] <LAVA_SIGNAL_TESTSET STOP>

11109 23:07:44.558303  Received signal: <TESTSET> STOP
11110 23:07:44.558377  Closing test_set panfrost_submit
11111 23:07:44.564809  <8>[   19.687919] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 12172395_1.5.2.3.1>

11112 23:07:44.565068  Received signal: <ENDRUN> 0_igt-gpu-panfrost 12172395_1.5.2.3.1
11113 23:07:44.565185  Ending use of test pattern.
11114 23:07:44.565308  Ending test lava.0_igt-gpu-panfrost (12172395_1.5.2.3.1), duration 0.54
11116 23:07:44.568050  -prime-import: SKIP (0.000s)

11117 23:07:44.574649  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11118 23:07:44.581732  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11119 23:07:44.584685  Test requirement: !(fd<0)

11120 23:07:44.588475  No known gpu found for chipset flags 0x32 (panfrost)

11121 23:07:44.591875  Last errno: 2, No such file or directory

11122 23:07:44.594931  Subtest pan-submit: SKIP (0.000s)

11123 23:07:44.601194  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11124 23:07:44.611640  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11125 23:07:44.611731  Test requirement: !(fd<0)

11126 23:07:44.618296  No known gpu found for chipset flags 0x32 (panfrost)

11127 23:07:44.621768  Last errno: 2, No such file or directory

11128 23:07:44.624915  Subtest pan-submit-error-no-jc: SKIP (0.000s)

11129 23:07:44.631284  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11130 23:07:44.638330  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11131 23:07:44.641217  Test requirement: !(fd<0)

11132 23:07:44.644744  No known gpu found for chipset flags 0x32 (panfrost)

11133 23:07:44.647634  Last errno: 2, No such file or directory

11134 23:07:44.654896  Subtest pan-submit-error-bad-in-syncs: SKIP (0.000s)

11135 23:07:44.661290  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11136 23:07:44.667886  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11137 23:07:44.671215  Test requirement: !(fd<0)

11138 23:07:44.674523  No known gpu found for chipset flags 0x32 (panfrost)

11139 23:07:44.678121  Last errno: 2, No such file or directory

11140 23:07:44.684204  Subtest pan-submit-error-bad-bo-handles: SKIP (0.000s)

11141 23:07:44.691029  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11142 23:07:44.697549  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11143 23:07:44.700976  Test requirement: !(fd<0)

11144 23:07:44.704486  No known gpu found for chipset flags 0x32 (panfrost)

11145 23:07:44.707403  Last errno: 2, No such file or directory

11146 23:07:44.714049  Subtest pan-submit-error-bad-requirements: SKIP (0.000s)

11147 23:07:44.721181  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11148 23:07:44.727597  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11149 23:07:44.730983  Test requirement: !(fd<0)

11150 23:07:44.734004  No known gpu found for chipset flags 0x32 (panfrost)

11151 23:07:44.737534  Last errno: 2, No such file or directory

11152 23:07:44.743950  Subtest pan-submit-error-bad-out-sync: SKIP (0.000s)

11153 23:07:44.750556  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11154 23:07:44.757307  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11155 23:07:44.760601  Test requirement: !(fd<0)

11156 23:07:44.764065  No known gpu found for chipset flags 0x32 (panfrost)

11157 23:07:44.767137  Last errno: 2, No such file or directory

11158 23:07:44.773620  Subtest pan-reset: SKIP (0.000s)

11159 23:07:44.776920  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11160 23:07:44.786625  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11161 23:07:44.786710  Test requirement: !(fd<0)

11162 23:07:44.793734  No known gpu found for chipset flags 0x32 (panfrost)

11163 23:07:44.796655  Last errno: 2, No such file or directory

11164 23:07:44.800214  Subtest pan-submit-and-close: SKIP (0.000s)

11165 23:07:44.806990  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11166 23:07:44.813362  Test requirement not met in function drm_open_driver, file ../lib/drmtest.c:621:

11167 23:07:44.816833  Test requirement: !(fd<0)

11168 23:07:44.819649  No known gpu found for chipset flags 0x32 (panfrost)

11169 23:07:44.826925  Last errno: 2, No such file or directory

11170 23:07:44.829734  Subtest pan-unhandled-pagefault: SKIP (0.000s)

11171 23:07:44.829819  + set +x

11172 23:07:44.833196  <LAVA_TEST_RUNNER EXIT>

11173 23:07:44.833459  ok: lava_test_shell seems to have completed
11174 23:07:44.833863  base-params:
  result: skip
  set: panfrost_get_param
gem-new-0:
  result: skip
  set: panfrost_gem_new
gem-new-4096:
  result: skip
  set: panfrost_gem_new
gem-new-zeroed:
  result: skip
  set: panfrost_gem_new
gem-prime-import:
  result: skip
  set: panfrost_prime
get-bad-padding:
  result: skip
  set: panfrost_get_param
get-bad-param:
  result: skip
  set: panfrost_get_param
pan-reset:
  result: skip
  set: panfrost_submit
pan-submit:
  result: skip
  set: panfrost_submit
pan-submit-and-close:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-bo-handles:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-in-syncs:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-out-sync:
  result: skip
  set: panfrost_submit
pan-submit-error-bad-requirements:
  result: skip
  set: panfrost_submit
pan-submit-error-no-jc:
  result: skip
  set: panfrost_submit
pan-unhandled-pagefault:
  result: skip
  set: panfrost_submit

11175 23:07:44.833969  end: 3.1 lava-test-shell (duration 00:00:01) [common]
11176 23:07:44.834058  end: 3 lava-test-retry (duration 00:00:01) [common]
11177 23:07:44.834147  start: 4 finalize (timeout 00:07:59) [common]
11178 23:07:44.834237  start: 4.1 power-off (timeout 00:00:30) [common]
11179 23:07:44.834392  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11180 23:07:44.914051  >> Command sent successfully.

11181 23:07:44.916691  Returned 0 in 0 seconds
11182 23:07:45.017094  end: 4.1 power-off (duration 00:00:00) [common]
11184 23:07:45.017420  start: 4.2 read-feedback (timeout 00:07:59) [common]
11185 23:07:45.017696  Listened to connection for namespace 'common' for up to 1s
11186 23:07:46.017694  Finalising connection for namespace 'common'
11187 23:07:46.017874  Disconnecting from shell: Finalise
11188 23:07:46.017959  / # 
11189 23:07:46.118304  end: 4.2 read-feedback (duration 00:00:01) [common]
11190 23:07:46.118498  end: 4 finalize (duration 00:00:01) [common]
11191 23:07:46.118612  Cleaning after the job
11192 23:07:46.118709  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/ramdisk
11193 23:07:46.126620  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/kernel
11194 23:07:46.135357  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/dtb
11195 23:07:46.135556  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172395/tftp-deploy-usgu8x7g/modules
11196 23:07:46.143090  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172395
11197 23:07:46.261110  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172395
11198 23:07:46.261287  Job finished correctly