Boot log: mt8192-asurada-spherion-r0

    1 23:27:43.793316  lava-dispatcher, installed at version: 2023.10
    2 23:27:43.793521  start: 0 validate
    3 23:27:43.793697  Start time: 2023-12-03 23:27:43.793689+00:00 (UTC)
    4 23:27:43.793823  Using caching service: 'http://localhost/cache/?uri=%s'
    5 23:27:43.793958  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230623.0%2Farm64%2Frootfs.cpio.gz exists
    6 23:27:44.074683  Using caching service: 'http://localhost/cache/?uri=%s'
    7 23:27:44.075684  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
    8 23:27:44.348932  Using caching service: 'http://localhost/cache/?uri=%s'
    9 23:27:44.349813  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
   10 23:27:44.618114  Using caching service: 'http://localhost/cache/?uri=%s'
   11 23:27:44.618335  Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
   12 23:27:44.886745  validate duration: 1.09
   14 23:27:44.887269  start: 1 tftp-deploy (timeout 00:10:00) [common]
   15 23:27:44.887454  start: 1.1 download-retry (timeout 00:10:00) [common]
   16 23:27:44.887626  start: 1.1.1 http-download (timeout 00:10:00) [common]
   17 23:27:44.887856  Not decompressing ramdisk as can be used compressed.
   18 23:27:44.888029  downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230623.0/arm64/rootfs.cpio.gz
   19 23:27:44.888166  saving as /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/ramdisk/rootfs.cpio.gz
   20 23:27:44.888300  total size: 43284872 (41 MB)
   21 23:27:44.890433  progress   0 % (0 MB)
   22 23:27:44.908949  progress   5 % (2 MB)
   23 23:27:44.924164  progress  10 % (4 MB)
   24 23:27:44.935558  progress  15 % (6 MB)
   25 23:27:44.947032  progress  20 % (8 MB)
   26 23:27:44.958312  progress  25 % (10 MB)
   27 23:27:44.969731  progress  30 % (12 MB)
   28 23:27:44.981107  progress  35 % (14 MB)
   29 23:27:44.992477  progress  40 % (16 MB)
   30 23:27:45.004062  progress  45 % (18 MB)
   31 23:27:45.015418  progress  50 % (20 MB)
   32 23:27:45.027116  progress  55 % (22 MB)
   33 23:27:45.039931  progress  60 % (24 MB)
   34 23:27:45.052017  progress  65 % (26 MB)
   35 23:27:45.063507  progress  70 % (28 MB)
   36 23:27:45.074925  progress  75 % (30 MB)
   37 23:27:45.086281  progress  80 % (33 MB)
   38 23:27:45.097550  progress  85 % (35 MB)
   39 23:27:45.108918  progress  90 % (37 MB)
   40 23:27:45.120238  progress  95 % (39 MB)
   41 23:27:45.131268  progress 100 % (41 MB)
   42 23:27:45.131521  41 MB downloaded in 0.24 s (169.72 MB/s)
   43 23:27:45.131679  end: 1.1.1 http-download (duration 00:00:00) [common]
   45 23:27:45.131929  end: 1.1 download-retry (duration 00:00:00) [common]
   46 23:27:45.132016  start: 1.2 download-retry (timeout 00:10:00) [common]
   47 23:27:45.132101  start: 1.2.1 http-download (timeout 00:10:00) [common]
   48 23:27:45.132239  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
   49 23:27:45.132313  saving as /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/kernel/Image
   50 23:27:45.132375  total size: 49172992 (46 MB)
   51 23:27:45.132437  No compression specified
   52 23:27:45.133524  progress   0 % (0 MB)
   53 23:27:45.146397  progress   5 % (2 MB)
   54 23:27:45.159200  progress  10 % (4 MB)
   55 23:27:45.172171  progress  15 % (7 MB)
   56 23:27:45.185019  progress  20 % (9 MB)
   57 23:27:45.197907  progress  25 % (11 MB)
   58 23:27:45.210660  progress  30 % (14 MB)
   59 23:27:45.223362  progress  35 % (16 MB)
   60 23:27:45.236107  progress  40 % (18 MB)
   61 23:27:45.248971  progress  45 % (21 MB)
   62 23:27:45.261700  progress  50 % (23 MB)
   63 23:27:45.274538  progress  55 % (25 MB)
   64 23:27:45.287464  progress  60 % (28 MB)
   65 23:27:45.300316  progress  65 % (30 MB)
   66 23:27:45.313048  progress  70 % (32 MB)
   67 23:27:45.325565  progress  75 % (35 MB)
   68 23:27:45.338172  progress  80 % (37 MB)
   69 23:27:45.350886  progress  85 % (39 MB)
   70 23:27:45.363970  progress  90 % (42 MB)
   71 23:27:45.376516  progress  95 % (44 MB)
   72 23:27:45.388953  progress 100 % (46 MB)
   73 23:27:45.389156  46 MB downloaded in 0.26 s (182.63 MB/s)
   74 23:27:45.389306  end: 1.2.1 http-download (duration 00:00:00) [common]
   76 23:27:45.389534  end: 1.2 download-retry (duration 00:00:00) [common]
   77 23:27:45.389695  start: 1.3 download-retry (timeout 00:09:59) [common]
   78 23:27:45.389783  start: 1.3.1 http-download (timeout 00:09:59) [common]
   79 23:27:45.389928  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
   80 23:27:45.389998  saving as /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/dtb/mt8192-asurada-spherion-r0.dtb
   81 23:27:45.390060  total size: 47278 (0 MB)
   82 23:27:45.390121  No compression specified
   83 23:27:45.391321  progress  69 % (0 MB)
   84 23:27:45.391595  progress 100 % (0 MB)
   85 23:27:45.391748  0 MB downloaded in 0.00 s (26.73 MB/s)
   86 23:27:45.391869  end: 1.3.1 http-download (duration 00:00:00) [common]
   88 23:27:45.392088  end: 1.3 download-retry (duration 00:00:00) [common]
   89 23:27:45.392172  start: 1.4 download-retry (timeout 00:09:59) [common]
   90 23:27:45.392253  start: 1.4.1 http-download (timeout 00:09:59) [common]
   91 23:27:45.392371  downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
   92 23:27:45.392439  saving as /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/modules/modules.tar
   93 23:27:45.392585  total size: 8614132 (8 MB)
   94 23:27:45.392666  Using unxz to decompress xz
   95 23:27:45.396938  progress   0 % (0 MB)
   96 23:27:45.417930  progress   5 % (0 MB)
   97 23:27:45.441412  progress  10 % (0 MB)
   98 23:27:45.464771  progress  15 % (1 MB)
   99 23:27:45.488347  progress  20 % (1 MB)
  100 23:27:45.512800  progress  25 % (2 MB)
  101 23:27:45.538211  progress  30 % (2 MB)
  102 23:27:45.564059  progress  35 % (2 MB)
  103 23:27:45.587266  progress  40 % (3 MB)
  104 23:27:45.611789  progress  45 % (3 MB)
  105 23:27:45.639439  progress  50 % (4 MB)
  106 23:27:45.663935  progress  55 % (4 MB)
  107 23:27:45.688551  progress  60 % (4 MB)
  108 23:27:45.713768  progress  65 % (5 MB)
  109 23:27:45.740782  progress  70 % (5 MB)
  110 23:27:45.764492  progress  75 % (6 MB)
  111 23:27:45.792209  progress  80 % (6 MB)
  112 23:27:45.817679  progress  85 % (7 MB)
  113 23:27:45.842712  progress  90 % (7 MB)
  114 23:27:45.872261  progress  95 % (7 MB)
  115 23:27:45.900526  progress 100 % (8 MB)
  116 23:27:45.906956  8 MB downloaded in 0.51 s (15.97 MB/s)
  117 23:27:45.907213  end: 1.4.1 http-download (duration 00:00:01) [common]
  119 23:27:45.907477  end: 1.4 download-retry (duration 00:00:01) [common]
  120 23:27:45.907570  start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
  121 23:27:45.907666  start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
  122 23:27:45.907748  end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
  123 23:27:45.907832  start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
  124 23:27:45.908066  [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q
  125 23:27:45.908201  makedir: /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin
  126 23:27:45.908309  makedir: /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/tests
  127 23:27:45.908409  makedir: /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/results
  128 23:27:45.908527  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-add-keys
  129 23:27:45.908681  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-add-sources
  130 23:27:45.908815  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-background-process-start
  131 23:27:45.908948  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-background-process-stop
  132 23:27:45.909167  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-common-functions
  133 23:27:45.909302  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-echo-ipv4
  134 23:27:45.909435  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-install-packages
  135 23:27:45.909562  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-installed-packages
  136 23:27:45.909732  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-os-build
  137 23:27:45.909859  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-probe-channel
  138 23:27:45.909990  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-probe-ip
  139 23:27:45.910121  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-target-ip
  140 23:27:45.910248  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-target-mac
  141 23:27:45.910374  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-target-storage
  142 23:27:45.910506  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-case
  143 23:27:45.910636  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-event
  144 23:27:45.910761  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-feedback
  145 23:27:45.910888  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-raise
  146 23:27:45.911043  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-reference
  147 23:27:45.911173  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-runner
  148 23:27:45.911300  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-set
  149 23:27:45.911431  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-test-shell
  150 23:27:45.911561  Updating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-install-packages (oe)
  151 23:27:45.911716  Updating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/bin/lava-installed-packages (oe)
  152 23:27:45.911848  Creating /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/environment
  153 23:27:45.911951  LAVA metadata
  154 23:27:45.912026  - LAVA_JOB_ID=12172428
  155 23:27:45.912091  - LAVA_DISPATCHER_IP=192.168.201.1
  156 23:27:45.912194  start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
  157 23:27:45.912262  skipped lava-vland-overlay
  158 23:27:45.912337  end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
  159 23:27:45.912418  start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
  160 23:27:45.912487  skipped lava-multinode-overlay
  161 23:27:45.912564  end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
  162 23:27:45.912649  start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
  163 23:27:45.912725  Loading test definitions
  164 23:27:45.912815  start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
  165 23:27:45.912890  Using /lava-12172428 at stage 0
  166 23:27:45.913197  uuid=12172428_1.5.2.3.1 testdef=None
  167 23:27:45.913285  end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
  168 23:27:45.913368  start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
  169 23:27:45.913944  end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
  171 23:27:45.914161  start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
  172 23:27:45.914780  end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
  174 23:27:45.915043  start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
  175 23:27:45.915809  runner path: /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/0/tests/0_igt-kms-mediatek test_uuid 12172428_1.5.2.3.1
  176 23:27:45.915968  end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
  178 23:27:45.916176  Creating lava-test-runner.conf files
  179 23:27:45.916238  Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172428/lava-overlay-dv19xp_q/lava-12172428/0 for stage 0
  180 23:27:45.916327  - 0_igt-kms-mediatek
  181 23:27:45.916425  end: 1.5.2.3 test-definition (duration 00:00:00) [common]
  182 23:27:45.916510  start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
  183 23:27:45.923251  end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
  184 23:27:45.923363  start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
  185 23:27:45.923449  end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
  186 23:27:45.923534  end: 1.5.2 lava-overlay (duration 00:00:00) [common]
  187 23:27:45.923625  start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
  188 23:27:47.320758  end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
  189 23:27:47.321149  start: 1.5.4 extract-modules (timeout 00:09:58) [common]
  190 23:27:47.321263  extracting modules file /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172428/extract-overlay-ramdisk-0_bwrhu4/ramdisk
  191 23:27:47.551351  end: 1.5.4 extract-modules (duration 00:00:00) [common]
  192 23:27:47.551528  start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
  193 23:27:47.551627  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172428/compress-overlay-1weps8ry/overlay-1.5.2.4.tar.gz to ramdisk
  194 23:27:47.551698  [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172428/compress-overlay-1weps8ry/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172428/extract-overlay-ramdisk-0_bwrhu4/ramdisk
  195 23:27:47.558194  end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
  196 23:27:47.558307  start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
  197 23:27:47.558397  end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
  198 23:27:47.558491  start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
  199 23:27:47.558567  Building ramdisk /var/lib/lava/dispatcher/tmp/12172428/extract-overlay-ramdisk-0_bwrhu4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172428/extract-overlay-ramdisk-0_bwrhu4/ramdisk
  200 23:27:48.796659  >> 369995 blocks

  201 23:27:54.851491  rename /var/lib/lava/dispatcher/tmp/12172428/extract-overlay-ramdisk-0_bwrhu4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/ramdisk/ramdisk.cpio.gz
  202 23:27:54.851973  end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
  203 23:27:54.852151  start: 1.5.8 prepare-kernel (timeout 00:09:50) [common]
  204 23:27:54.852303  start: 1.5.8.1 prepare-fit (timeout 00:09:50) [common]
  205 23:27:54.852459  Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/kernel/Image'
  206 23:28:06.967050  Returned 0 in 12 seconds
  207 23:28:07.068038  mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/kernel/image.itb
  208 23:28:08.042892  output: FIT description: Kernel Image image with one or more FDT blobs
  209 23:28:08.043275  output: Created:         Sun Dec  3 23:28:07 2023
  210 23:28:08.043357  output:  Image 0 (kernel-1)
  211 23:28:08.043426  output:   Description:  
  212 23:28:08.043488  output:   Created:      Sun Dec  3 23:28:07 2023
  213 23:28:08.043551  output:   Type:         Kernel Image
  214 23:28:08.043612  output:   Compression:  lzma compressed
  215 23:28:08.043670  output:   Data Size:    11049348 Bytes = 10790.38 KiB = 10.54 MiB
  216 23:28:08.043725  output:   Architecture: AArch64
  217 23:28:08.043782  output:   OS:           Linux
  218 23:28:08.043839  output:   Load Address: 0x00000000
  219 23:28:08.043892  output:   Entry Point:  0x00000000
  220 23:28:08.043947  output:   Hash algo:    crc32
  221 23:28:08.044004  output:   Hash value:   c85ea8f0
  222 23:28:08.044061  output:  Image 1 (fdt-1)
  223 23:28:08.044116  output:   Description:  mt8192-asurada-spherion-r0
  224 23:28:08.044169  output:   Created:      Sun Dec  3 23:28:07 2023
  225 23:28:08.044222  output:   Type:         Flat Device Tree
  226 23:28:08.044275  output:   Compression:  uncompressed
  227 23:28:08.044328  output:   Data Size:    47278 Bytes = 46.17 KiB = 0.05 MiB
  228 23:28:08.044381  output:   Architecture: AArch64
  229 23:28:08.044434  output:   Hash algo:    crc32
  230 23:28:08.044487  output:   Hash value:   cc4352de
  231 23:28:08.044540  output:  Image 2 (ramdisk-1)
  232 23:28:08.044592  output:   Description:  unavailable
  233 23:28:08.044645  output:   Created:      Sun Dec  3 23:28:07 2023
  234 23:28:08.044698  output:   Type:         RAMDisk Image
  235 23:28:08.044751  output:   Compression:  Unknown Compression
  236 23:28:08.044803  output:   Data Size:    56430611 Bytes = 55108.02 KiB = 53.82 MiB
  237 23:28:08.044856  output:   Architecture: AArch64
  238 23:28:08.044909  output:   OS:           Linux
  239 23:28:08.044962  output:   Load Address: unavailable
  240 23:28:08.045014  output:   Entry Point:  unavailable
  241 23:28:08.045066  output:   Hash algo:    crc32
  242 23:28:08.045118  output:   Hash value:   752cd256
  243 23:28:08.045171  output:  Default Configuration: 'conf-1'
  244 23:28:08.045223  output:  Configuration 0 (conf-1)
  245 23:28:08.045275  output:   Description:  mt8192-asurada-spherion-r0
  246 23:28:08.045328  output:   Kernel:       kernel-1
  247 23:28:08.045381  output:   Init Ramdisk: ramdisk-1
  248 23:28:08.045433  output:   FDT:          fdt-1
  249 23:28:08.045485  output:   Loadables:    kernel-1
  250 23:28:08.045537  output: 
  251 23:28:08.045786  end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
  252 23:28:08.045890  end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
  253 23:28:08.045994  end: 1.5 prepare-tftp-overlay (duration 00:00:22) [common]
  254 23:28:08.046090  start: 1.6 lxc-create-udev-rule-action (timeout 00:09:37) [common]
  255 23:28:08.046171  No LXC device requested
  256 23:28:08.046254  end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
  257 23:28:08.046342  start: 1.7 deploy-device-env (timeout 00:09:37) [common]
  258 23:28:08.046422  end: 1.7 deploy-device-env (duration 00:00:00) [common]
  259 23:28:08.046493  Checking files for TFTP limit of 4294967296 bytes.
  260 23:28:08.046987  end: 1 tftp-deploy (duration 00:00:23) [common]
  261 23:28:08.047089  start: 2 depthcharge-action (timeout 00:05:00) [common]
  262 23:28:08.047180  start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
  263 23:28:08.047303  substitutions:
  264 23:28:08.047369  - {DTB}: 12172428/tftp-deploy-um0a0hli/dtb/mt8192-asurada-spherion-r0.dtb
  265 23:28:08.047433  - {INITRD}: 12172428/tftp-deploy-um0a0hli/ramdisk/ramdisk.cpio.gz
  266 23:28:08.047492  - {KERNEL}: 12172428/tftp-deploy-um0a0hli/kernel/Image
  267 23:28:08.047549  - {LAVA_MAC}: None
  268 23:28:08.047605  - {PRESEED_CONFIG}: None
  269 23:28:08.047660  - {PRESEED_LOCAL}: None
  270 23:28:08.047714  - {RAMDISK}: 12172428/tftp-deploy-um0a0hli/ramdisk/ramdisk.cpio.gz
  271 23:28:08.047771  - {ROOT_PART}: None
  272 23:28:08.047826  - {ROOT}: None
  273 23:28:08.047881  - {SERVER_IP}: 192.168.201.1
  274 23:28:08.047935  - {TEE}: None
  275 23:28:08.047989  Parsed boot commands:
  276 23:28:08.048042  - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
  277 23:28:08.048225  Parsed boot commands: tftpboot 192.168.201.1 12172428/tftp-deploy-um0a0hli/kernel/image.itb 12172428/tftp-deploy-um0a0hli/kernel/cmdline 
  278 23:28:08.048313  end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
  279 23:28:08.048400  start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
  280 23:28:08.048497  start: 2.2.1 reset-connection (timeout 00:05:00) [common]
  281 23:28:08.048584  start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
  282 23:28:08.048655  Not connected, no need to disconnect.
  283 23:28:08.048729  end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
  284 23:28:08.048810  start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
  285 23:28:08.048875  [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
  286 23:28:08.052895  Setting prompt string to ['lava-test: # ']
  287 23:28:08.053369  end: 2.2.1.2 connect-device (duration 00:00:00) [common]
  288 23:28:08.053501  end: 2.2.1 reset-connection (duration 00:00:00) [common]
  289 23:28:08.053627  start: 2.2.2 reset-device (timeout 00:05:00) [common]
  290 23:28:08.053753  start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
  291 23:28:08.053982  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
  292 23:28:13.188535  >> Command sent successfully.

  293 23:28:13.190944  Returned 0 in 5 seconds
  294 23:28:13.291302  end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
  296 23:28:13.291746  end: 2.2.2 reset-device (duration 00:00:05) [common]
  297 23:28:13.291877  start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
  298 23:28:13.291993  Setting prompt string to 'Starting depthcharge on Spherion...'
  299 23:28:13.292087  Changing prompt to 'Starting depthcharge on Spherion...'
  300 23:28:13.292184  depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
  301 23:28:13.292547  [Enter `^Ec?' for help]

  302 23:28:13.464295  

  303 23:28:13.464488  

  304 23:28:13.464590  F0: 102B 0000

  305 23:28:13.464668  

  306 23:28:13.464729  F3: 1001 0000 [0200]

  307 23:28:13.467650  

  308 23:28:13.467758  F3: 1001 0000

  309 23:28:13.467853  

  310 23:28:13.467954  F7: 102D 0000

  311 23:28:13.468043  

  312 23:28:13.470766  F1: 0000 0000

  313 23:28:13.470868  

  314 23:28:13.470967  V0: 0000 0000 [0001]

  315 23:28:13.471061  

  316 23:28:13.474094  00: 0007 8000

  317 23:28:13.474177  

  318 23:28:13.474251  01: 0000 0000

  319 23:28:13.474314  

  320 23:28:13.477083  BP: 0C00 0209 [0000]

  321 23:28:13.477162  

  322 23:28:13.477228  G0: 1182 0000

  323 23:28:13.477289  

  324 23:28:13.480846  EC: 0000 0021 [4000]

  325 23:28:13.480964  

  326 23:28:13.481057  S7: 0000 0000 [0000]

  327 23:28:13.481147  

  328 23:28:13.484464  CC: 0000 0000 [0001]

  329 23:28:13.484566  

  330 23:28:13.484638  T0: 0000 0040 [010F]

  331 23:28:13.484700  

  332 23:28:13.484758  Jump to BL

  333 23:28:13.487840  

  334 23:28:13.511158  

  335 23:28:13.511275  

  336 23:28:13.511381  

  337 23:28:13.518362  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...

  338 23:28:13.521802  ARM64: Exception handlers installed.

  339 23:28:13.525436  ARM64: Testing exception

  340 23:28:13.528764  ARM64: Done test exception

  341 23:28:13.535304  Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000

  342 23:28:13.545450  Mapping address range [0x00000000:0x200000000) as     cacheable | read-write |     secure | device

  343 23:28:13.552249  Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000

  344 23:28:13.562297  Mapping address range [0x00100000:0x00120000) as     cacheable | read-write |     secure | normal

  345 23:28:13.569093  Backing address range [0x00000000:0x40000000) with new page table @0x0010f000

  346 23:28:13.575942  Backing address range [0x00000000:0x00200000) with new page table @0x00110000

  347 23:28:13.588029  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | normal

  348 23:28:13.594701  Backing address range [0x00200000:0x00400000) with new page table @0x00111000

  349 23:28:13.613554  Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write |     secure | normal

  350 23:28:13.616673  WDT: Last reset was cold boot

  351 23:28:13.620492  SPI1(PAD0) initialized at 2873684 Hz

  352 23:28:13.623911  SPI5(PAD0) initialized at 992727 Hz

  353 23:28:13.627132  VBOOT: Loading verstage.

  354 23:28:13.633914  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  355 23:28:13.637951  FMAP: Found "FLASH" version 1.1 at 0x20000.

  356 23:28:13.640627  FMAP: base = 0x0 size = 0x800000 #areas = 25

  357 23:28:13.643909  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  358 23:28:13.651496  CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes

  359 23:28:13.657559  CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150

  360 23:28:13.668670  read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps

  361 23:28:13.668760  

  362 23:28:13.668848  

  363 23:28:13.679399  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...

  364 23:28:13.682514  ARM64: Exception handlers installed.

  365 23:28:13.682601  ARM64: Testing exception

  366 23:28:13.686078  ARM64: Done test exception

  367 23:28:13.689511  FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)

  368 23:28:13.696317  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  369 23:28:13.709796  Probing TPM: . done!

  370 23:28:13.709883  TPM ready after 0 ms

  371 23:28:13.717023  Connected to device vid:did:rid of 1ae0:0028:00

  372 23:28:13.723316  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

  373 23:28:13.784189  Initialized TPM device CR50 revision 0

  374 23:28:13.793986  tlcl_send_startup: Startup return code is 0

  375 23:28:13.794089  TPM: setup succeeded

  376 23:28:13.805572  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0

  377 23:28:13.814715  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  378 23:28:13.826568  VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)

  379 23:28:13.836616  src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0

  380 23:28:13.840432  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  381 23:28:13.844216  in-header: 03 07 00 00 08 00 00 00 

  382 23:28:13.847764  in-data: aa e4 47 04 13 02 00 00 

  383 23:28:13.851387  Chrome EC: UHEPI supported

  384 23:28:13.854924  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  385 23:28:13.858983  in-header: 03 95 00 00 08 00 00 00 

  386 23:28:13.862874  in-data: 18 20 20 08 00 00 00 00 

  387 23:28:13.862988  Phase 1

  388 23:28:13.867141  FMAP: area GBB found @ 3f5000 (12032 bytes)

  389 23:28:13.874475  VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7

  390 23:28:13.878474  VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7

  391 23:28:13.882475  Recovery requested (1009000e)

  392 23:28:13.891769  TPM: Extending digest for VBOOT: boot mode into PCR 0

  393 23:28:13.897049  tlcl_extend: response is 0

  394 23:28:13.906443  TPM: Extending digest for VBOOT: GBB HWID into PCR 1

  395 23:28:13.912092  tlcl_extend: response is 0

  396 23:28:13.919237  CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c

  397 23:28:13.938897  read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps

  398 23:28:13.945716  BS: bootblock times (exec / console): total (unknown) / 148 ms

  399 23:28:13.945994  

  400 23:28:13.946197  

  401 23:28:13.955580  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...

  402 23:28:13.958932  ARM64: Exception handlers installed.

  403 23:28:13.962276  ARM64: Testing exception

  404 23:28:13.962385  ARM64: Done test exception

  405 23:28:13.984561  pmic_efuse_setting: Set efuses in 11 msecs

  406 23:28:13.987831  pmwrap_interface_init: Select PMIF_VLD_RDY

  407 23:28:13.994332  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a

  408 23:28:13.997698  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a

  409 23:28:14.005725  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a

  410 23:28:14.008922  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a

  411 23:28:14.012881  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a

  412 23:28:14.016427  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a

  413 23:28:14.023651  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a

  414 23:28:14.027916  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a

  415 23:28:14.031144  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c

  416 23:28:14.034993  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a

  417 23:28:14.042463  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a

  418 23:28:14.046758  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c

  419 23:28:14.050425  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c

  420 23:28:14.057536  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a

  421 23:28:14.061215  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a

  422 23:28:14.068673  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a

  423 23:28:14.072354  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a

  424 23:28:14.080615  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a

  425 23:28:14.083977  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a

  426 23:28:14.091793  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a

  427 23:28:14.095731  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c

  428 23:28:14.102962  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a

  429 23:28:14.107132  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a

  430 23:28:14.114391  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c

  431 23:28:14.118292  [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c

  432 23:28:14.125748  [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa

  433 23:28:14.129500  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92

  434 23:28:14.133096  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2

  435 23:28:14.140465  [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82

  436 23:28:14.144217  [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10

  437 23:28:14.148108  [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425

  438 23:28:14.154863  [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010

  439 23:28:14.159002  [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f

  440 23:28:14.162385  [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000

  441 23:28:14.169327  [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8

  442 23:28:14.173057  [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb

  443 23:28:14.180815  [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698

  444 23:28:14.184214  [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3

  445 23:28:14.188198  [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92

  446 23:28:14.192083  [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a

  447 23:28:14.195761  [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2

  448 23:28:14.203464  [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a

  449 23:28:14.207014  [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a

  450 23:28:14.210711  [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a

  451 23:28:14.213956  [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a

  452 23:28:14.217210  [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82

  453 23:28:14.221165  [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c

  454 23:28:14.228738  [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a

  455 23:28:14.232233  [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a

  456 23:28:14.236248  [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c

  457 23:28:14.239838  [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c

  458 23:28:14.246869  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248

  459 23:28:14.254503  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1

  460 23:28:14.261573  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  461 23:28:14.268852  [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248

  462 23:28:14.276535  [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0

  463 23:28:14.280031  [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0

  464 23:28:14.287793  [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  465 23:28:14.291357  [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1

  466 23:28:14.299099  [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1b

  467 23:28:14.302577  [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2

  468 23:28:14.306450  [RTC]rtc_osc_init,62: osc32con val = 0xde70

  469 23:28:14.313175  [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a

  470 23:28:14.321858  [RTC]rtc_get_frequency_meter,154: input=15, output=759

  471 23:28:14.331408  [RTC]rtc_get_frequency_meter,154: input=23, output=941

  472 23:28:14.341303  [RTC]rtc_get_frequency_meter,154: input=19, output=850

  473 23:28:14.350493  [RTC]rtc_get_frequency_meter,154: input=17, output=805

  474 23:28:14.359529  [RTC]rtc_get_frequency_meter,154: input=16, output=781

  475 23:28:14.369837  [RTC]rtc_get_frequency_meter,154: input=16, output=780

  476 23:28:14.379591  [RTC]rtc_get_frequency_meter,154: input=17, output=804

  477 23:28:14.383383  [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17

  478 23:28:14.386904  [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71

  479 23:28:14.390720  [RTC]rtc_boot_common,202: RTC_STATE_REBOOT

  480 23:28:14.398064  [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486

  481 23:28:14.401563  [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1

  482 23:28:14.405500  [RTC]rtc_bbpu_power_on,300: done BBPU=0x81

  483 23:28:14.408988  ADC[4]: Raw value=906203 ID=7

  484 23:28:14.409091  ADC[3]: Raw value=213810 ID=1

  485 23:28:14.412807  RAM Code: 0x71

  486 23:28:14.416730  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

  487 23:28:14.420007  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

  488 23:28:14.431907  CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014

  489 23:28:14.435236  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  490 23:28:14.438335  out: cmd=0xd: 03 f0 0d 00 00 00 00 00 

  491 23:28:14.442739  in-header: 03 07 00 00 08 00 00 00 

  492 23:28:14.446125  in-data: aa e4 47 04 13 02 00 00 

  493 23:28:14.449897  Chrome EC: UHEPI supported

  494 23:28:14.457153  out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00 

  495 23:28:14.461650  in-header: 03 95 00 00 08 00 00 00 

  496 23:28:14.461758  in-data: 18 20 20 08 00 00 00 00 

  497 23:28:14.465539  MRC: failed to locate region type 0.

  498 23:28:14.472920  DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)

  499 23:28:14.476929  DRAM-K: Running full calibration

  500 23:28:14.481128  DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE

  501 23:28:14.484476  header.status = 0x0

  502 23:28:14.488282  header.version = 0x6 (expected: 0x6)

  503 23:28:14.492170  header.size = 0xd00 (expected: 0xd00)

  504 23:28:14.492271  header.flags = 0x0

  505 23:28:14.499338  CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40

  506 23:28:14.516826  read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps

  507 23:28:14.523980  dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6

  508 23:28:14.524093  dram_init: ddr_geometry: 2

  509 23:28:14.527694  [EMI] MDL number = 2

  510 23:28:14.531235  [EMI] Get MDL freq = 0

  511 23:28:14.531337  dram_init: ddr_type: 0

  512 23:28:14.534966  is_discrete_lpddr4: 1

  513 23:28:14.538822  [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0

  514 23:28:14.538929  

  515 23:28:14.539023  

  516 23:28:14.539112  [Bian_co] ETT version 0.0.0.1

  517 23:28:14.545891   dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6

  518 23:28:14.545994  

  519 23:28:14.550192  dramc_set_vcore_voltage set vcore to 650000

  520 23:28:14.550275  Read voltage for 800, 4

  521 23:28:14.550341  Vio18 = 0

  522 23:28:14.553800  Vcore = 650000

  523 23:28:14.553900  Vdram = 0

  524 23:28:14.553991  Vddq = 0

  525 23:28:14.557200  Vmddr = 0

  526 23:28:14.557302  dram_init: config_dvfs: 1

  527 23:28:14.565060  [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0

  528 23:28:14.568589  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

  529 23:28:14.572523  [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9

  530 23:28:14.576095  freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9

  531 23:28:14.580529  [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9

  532 23:28:14.583770  freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9

  533 23:28:14.587877  MEM_TYPE=3, freq_sel=18

  534 23:28:14.587954  sv_algorithm_assistance_LP4_1600 

  535 23:28:14.594596  ============ PULL DRAM RESETB DOWN ============

  536 23:28:14.597856  ========== PULL DRAM RESETB DOWN end =========

  537 23:28:14.601198  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  538 23:28:14.604548  =================================== 

  539 23:28:14.607928  LPDDR4 DRAM CONFIGURATION

  540 23:28:14.611729  =================================== 

  541 23:28:14.611835  EX_ROW_EN[0]    = 0x0

  542 23:28:14.615647  EX_ROW_EN[1]    = 0x0

  543 23:28:14.615747  LP4Y_EN      = 0x0

  544 23:28:14.619166  WORK_FSP     = 0x0

  545 23:28:14.619238  WL           = 0x2

  546 23:28:14.622867  RL           = 0x2

  547 23:28:14.622965  BL           = 0x2

  548 23:28:14.626635  RPST         = 0x0

  549 23:28:14.626738  RD_PRE       = 0x0

  550 23:28:14.629981  WR_PRE       = 0x1

  551 23:28:14.630087  WR_PST       = 0x0

  552 23:28:14.633560  DBI_WR       = 0x0

  553 23:28:14.633698  DBI_RD       = 0x0

  554 23:28:14.636612  OTF          = 0x1

  555 23:28:14.640210  =================================== 

  556 23:28:14.643749  =================================== 

  557 23:28:14.643848  ANA top config

  558 23:28:14.646962  =================================== 

  559 23:28:14.650198  DLL_ASYNC_EN            =  0

  560 23:28:14.653713  ALL_SLAVE_EN            =  1

  561 23:28:14.653788  NEW_RANK_MODE           =  1

  562 23:28:14.656645  DLL_IDLE_MODE           =  1

  563 23:28:14.659985  LP45_APHY_COMB_EN       =  1

  564 23:28:14.663293  TX_ODT_DIS              =  1

  565 23:28:14.663366  NEW_8X_MODE             =  1

  566 23:28:14.667333  =================================== 

  567 23:28:14.670631  =================================== 

  568 23:28:14.673904  data_rate                  = 1600

  569 23:28:14.677252  CKR                        = 1

  570 23:28:14.680705  DQ_P2S_RATIO               = 8

  571 23:28:14.684213  =================================== 

  572 23:28:14.687433  CA_P2S_RATIO               = 8

  573 23:28:14.687538  DQ_CA_OPEN                 = 0

  574 23:28:14.690827  DQ_SEMI_OPEN               = 0

  575 23:28:14.694045  CA_SEMI_OPEN               = 0

  576 23:28:14.697439  CA_FULL_RATE               = 0

  577 23:28:14.700480  DQ_CKDIV4_EN               = 1

  578 23:28:14.700580  CA_CKDIV4_EN               = 1

  579 23:28:14.703834  CA_PREDIV_EN               = 0

  580 23:28:14.707248  PH8_DLY                    = 0

  581 23:28:14.710611  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

  582 23:28:14.714055  DQ_AAMCK_DIV               = 4

  583 23:28:14.717430  CA_AAMCK_DIV               = 4

  584 23:28:14.717532  CA_ADMCK_DIV               = 4

  585 23:28:14.720796  DQ_TRACK_CA_EN             = 0

  586 23:28:14.724321  CA_PICK                    = 800

  587 23:28:14.727526  CA_MCKIO                   = 800

  588 23:28:14.731079  MCKIO_SEMI                 = 0

  589 23:28:14.734555  PLL_FREQ                   = 3068

  590 23:28:14.734657  DQ_UI_PI_RATIO             = 32

  591 23:28:14.738502  CA_UI_PI_RATIO             = 0

  592 23:28:14.742314  =================================== 

  593 23:28:14.745538  =================================== 

  594 23:28:14.749260  memory_type:LPDDR4         

  595 23:28:14.749367  GP_NUM     : 10       

  596 23:28:14.753033  SRAM_EN    : 1       

  597 23:28:14.753144  MD32_EN    : 0       

  598 23:28:14.756908  =================================== 

  599 23:28:14.760581  [ANA_INIT] >>>>>>>>>>>>>> 

  600 23:28:14.764368  <<<<<< [CONFIGURE PHASE]: ANA_TX

  601 23:28:14.767623  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

  602 23:28:14.767727  =================================== 

  603 23:28:14.770938  data_rate = 1600,PCW = 0X7600

  604 23:28:14.774403  =================================== 

  605 23:28:14.777488  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

  606 23:28:14.784548  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  607 23:28:14.790941  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

  608 23:28:14.794416  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

  609 23:28:14.797677  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

  610 23:28:14.801035  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

  611 23:28:14.804518  [ANA_INIT] flow start 

  612 23:28:14.804627  [ANA_INIT] PLL >>>>>>>> 

  613 23:28:14.807741  [ANA_INIT] PLL <<<<<<<< 

  614 23:28:14.811250  [ANA_INIT] MIDPI >>>>>>>> 

  615 23:28:14.811357  [ANA_INIT] MIDPI <<<<<<<< 

  616 23:28:14.814692  [ANA_INIT] DLL >>>>>>>> 

  617 23:28:14.818092  [ANA_INIT] flow end 

  618 23:28:14.821123  ============ LP4 DIFF to SE enter ============

  619 23:28:14.824568  ============ LP4 DIFF to SE exit  ============

  620 23:28:14.828046  [ANA_INIT] <<<<<<<<<<<<< 

  621 23:28:14.831407  [Flow] Enable top DCM control >>>>> 

  622 23:28:14.834560  [Flow] Enable top DCM control <<<<< 

  623 23:28:14.837772  Enable DLL master slave shuffle 

  624 23:28:14.841098  ============================================================== 

  625 23:28:14.844474  Gating Mode config

  626 23:28:14.850908  ============================================================== 

  627 23:28:14.851012  Config description: 

  628 23:28:14.861457  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

  629 23:28:14.867841  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

  630 23:28:14.871285  SELPH_MODE            0: By rank         1: By Phase 

  631 23:28:14.877744  ============================================================== 

  632 23:28:14.881234  GAT_TRACK_EN                 =  1

  633 23:28:14.884714  RX_GATING_MODE               =  2

  634 23:28:14.888018  RX_GATING_TRACK_MODE         =  2

  635 23:28:14.891237  SELPH_MODE                   =  1

  636 23:28:14.895007  PICG_EARLY_EN                =  1

  637 23:28:14.895111  VALID_LAT_VALUE              =  1

  638 23:28:14.901451  ============================================================== 

  639 23:28:14.904855  Enter into Gating configuration >>>> 

  640 23:28:14.908127  Exit from Gating configuration <<<< 

  641 23:28:14.911040  Enter into  DVFS_PRE_config >>>>> 

  642 23:28:14.921151  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

  643 23:28:14.924535  Exit from  DVFS_PRE_config <<<<< 

  644 23:28:14.928515  Enter into PICG configuration >>>> 

  645 23:28:14.931308  Exit from PICG configuration <<<< 

  646 23:28:14.934617  [RX_INPUT] configuration >>>>> 

  647 23:28:14.937956  [RX_INPUT] configuration <<<<< 

  648 23:28:14.941311  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

  649 23:28:14.948040  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

  650 23:28:14.954529  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

  651 23:28:14.961394  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

  652 23:28:14.968048  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

  653 23:28:14.971654  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

  654 23:28:14.978291  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

  655 23:28:14.981722  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

  656 23:28:14.984355  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

  657 23:28:14.987888  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

  658 23:28:14.994461  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

  659 23:28:14.998039  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  660 23:28:15.001502  =================================== 

  661 23:28:15.004449  LPDDR4 DRAM CONFIGURATION

  662 23:28:15.008278  =================================== 

  663 23:28:15.008386  EX_ROW_EN[0]    = 0x0

  664 23:28:15.011328  EX_ROW_EN[1]    = 0x0

  665 23:28:15.011430  LP4Y_EN      = 0x0

  666 23:28:15.014659  WORK_FSP     = 0x0

  667 23:28:15.014765  WL           = 0x2

  668 23:28:15.017941  RL           = 0x2

  669 23:28:15.018043  BL           = 0x2

  670 23:28:15.021085  RPST         = 0x0

  671 23:28:15.021179  RD_PRE       = 0x0

  672 23:28:15.024304  WR_PRE       = 0x1

  673 23:28:15.024414  WR_PST       = 0x0

  674 23:28:15.027885  DBI_WR       = 0x0

  675 23:28:15.031239  DBI_RD       = 0x0

  676 23:28:15.031340  OTF          = 0x1

  677 23:28:15.034580  =================================== 

  678 23:28:15.037975  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

  679 23:28:15.041311  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

  680 23:28:15.047696  [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2

  681 23:28:15.053497  =================================== 

  682 23:28:15.054432  LPDDR4 DRAM CONFIGURATION

  683 23:28:15.054515  =================================== 

  684 23:28:15.057753  EX_ROW_EN[0]    = 0x10

  685 23:28:15.061529  EX_ROW_EN[1]    = 0x0

  686 23:28:15.061637  LP4Y_EN      = 0x0

  687 23:28:15.064363  WORK_FSP     = 0x0

  688 23:28:15.064446  WL           = 0x2

  689 23:28:15.067981  RL           = 0x2

  690 23:28:15.068090  BL           = 0x2

  691 23:28:15.071224  RPST         = 0x0

  692 23:28:15.071325  RD_PRE       = 0x0

  693 23:28:15.074677  WR_PRE       = 0x1

  694 23:28:15.074781  WR_PST       = 0x0

  695 23:28:15.077916  DBI_WR       = 0x0

  696 23:28:15.078017  DBI_RD       = 0x0

  697 23:28:15.081247  OTF          = 0x1

  698 23:28:15.084746  =================================== 

  699 23:28:15.091168  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

  700 23:28:15.094427  nWR fixed to 40

  701 23:28:15.097906  [ModeRegInit_LP4] CH0 RK0

  702 23:28:15.098009  [ModeRegInit_LP4] CH0 RK1

  703 23:28:15.101116  [ModeRegInit_LP4] CH1 RK0

  704 23:28:15.104248  [ModeRegInit_LP4] CH1 RK1

  705 23:28:15.104360  match AC timing 13

  706 23:28:15.111251  dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1

  707 23:28:15.114563  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

  708 23:28:15.118023  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

  709 23:28:15.121347  [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17

  710 23:28:15.127749  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

  711 23:28:15.127854  [EMI DOE] emi_dcm 0

  712 23:28:15.134713  [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600

  713 23:28:15.134819  ==

  714 23:28:15.138047  Dram Type= 6, Freq= 0, CH_0, rank 0

  715 23:28:15.141329  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  716 23:28:15.141436  ==

  717 23:28:15.148261  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  718 23:28:15.151623  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  719 23:28:15.161466  [CA 0] Center 36 (6~67) winsize 62

  720 23:28:15.164839  [CA 1] Center 36 (6~67) winsize 62

  721 23:28:15.168313  [CA 2] Center 34 (4~65) winsize 62

  722 23:28:15.171414  [CA 3] Center 33 (3~64) winsize 62

  723 23:28:15.175041  [CA 4] Center 33 (3~64) winsize 62

  724 23:28:15.178221  [CA 5] Center 32 (2~62) winsize 61

  725 23:28:15.178324  

  726 23:28:15.181283  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  727 23:28:15.181383  

  728 23:28:15.185098  [CATrainingPosCal] consider 1 rank data

  729 23:28:15.188449  u2DelayCellTimex100 = 270/100 ps

  730 23:28:15.191775  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  731 23:28:15.194971  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  732 23:28:15.201473  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  733 23:28:15.204816  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  734 23:28:15.208236  CA4 delay=33 (3~64),Diff = 1 PI (7 cell)

  735 23:28:15.211512  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

  736 23:28:15.211611  

  737 23:28:15.214863  CA PerBit enable=1, Macro0, CA PI delay=32

  738 23:28:15.214941  

  739 23:28:15.218352  [CBTSetCACLKResult] CA Dly = 32

  740 23:28:15.218444  CS Dly: 4 (0~35)

  741 23:28:15.218508  ==

  742 23:28:15.221851  Dram Type= 6, Freq= 0, CH_0, rank 1

  743 23:28:15.228330  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  744 23:28:15.228431  ==

  745 23:28:15.231499  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

  746 23:28:15.237965  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

  747 23:28:15.247670  [CA 0] Center 36 (6~67) winsize 62

  748 23:28:15.250823  [CA 1] Center 36 (6~67) winsize 62

  749 23:28:15.254642  [CA 2] Center 34 (4~65) winsize 62

  750 23:28:15.257760  [CA 3] Center 34 (3~65) winsize 63

  751 23:28:15.261178  [CA 4] Center 32 (2~63) winsize 62

  752 23:28:15.264326  [CA 5] Center 32 (2~63) winsize 62

  753 23:28:15.264448  

  754 23:28:15.267707  [CmdBusTrainingLP45] Vref(ca) range 1: 34

  755 23:28:15.267808  

  756 23:28:15.271427  [CATrainingPosCal] consider 2 rank data

  757 23:28:15.275085  u2DelayCellTimex100 = 270/100 ps

  758 23:28:15.277878  CA0 delay=36 (6~67),Diff = 4 PI (28 cell)

  759 23:28:15.281173  CA1 delay=36 (6~67),Diff = 4 PI (28 cell)

  760 23:28:15.287748  CA2 delay=34 (4~65),Diff = 2 PI (14 cell)

  761 23:28:15.291010  CA3 delay=33 (3~64),Diff = 1 PI (7 cell)

  762 23:28:15.294477  CA4 delay=33 (3~63),Diff = 1 PI (7 cell)

  763 23:28:15.298034  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

  764 23:28:15.298137  

  765 23:28:15.300967  CA PerBit enable=1, Macro0, CA PI delay=32

  766 23:28:15.301067  

  767 23:28:15.304699  [CBTSetCACLKResult] CA Dly = 32

  768 23:28:15.304801  CS Dly: 4 (0~36)

  769 23:28:15.304896  

  770 23:28:15.308145  ----->DramcWriteLeveling(PI) begin...

  771 23:28:15.311334  ==

  772 23:28:15.311427  Dram Type= 6, Freq= 0, CH_0, rank 0

  773 23:28:15.315810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  774 23:28:15.315920  ==

  775 23:28:15.319256  Write leveling (Byte 0): 33 => 33

  776 23:28:15.323152  Write leveling (Byte 1): 31 => 31

  777 23:28:15.326524  DramcWriteLeveling(PI) end<-----

  778 23:28:15.326608  

  779 23:28:15.326673  ==

  780 23:28:15.329692  Dram Type= 6, Freq= 0, CH_0, rank 0

  781 23:28:15.333110  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  782 23:28:15.333221  ==

  783 23:28:15.336291  [Gating] SW mode calibration

  784 23:28:15.344197  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

  785 23:28:15.350776  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

  786 23:28:15.353785   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

  787 23:28:15.357631   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)

  788 23:28:15.360932   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  789 23:28:15.367306   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  790 23:28:15.370556   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  791 23:28:15.373975   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  792 23:28:15.380698   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  793 23:28:15.384040   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  794 23:28:15.387235   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  795 23:28:15.393997   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  796 23:28:15.397730   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  797 23:28:15.401028   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  798 23:28:15.407294   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  799 23:28:15.410797   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  800 23:28:15.414359   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  801 23:28:15.420817   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  802 23:28:15.424072   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  803 23:28:15.427643   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)

  804 23:28:15.434546   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  805 23:28:15.437344   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

  806 23:28:15.440624   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  807 23:28:15.444311   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  808 23:28:15.451220   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  809 23:28:15.454085   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  810 23:28:15.457465   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  811 23:28:15.464205   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  812 23:28:15.467876   0  9  8 | B1->B0 | 2323 3232 | 1 1 | (1 1) (1 1)

  813 23:28:15.470532   0  9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)

  814 23:28:15.477223   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  815 23:28:15.480691   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  816 23:28:15.483856   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  817 23:28:15.490693   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  818 23:28:15.494452   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

  819 23:28:15.497739   0 10  4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

  820 23:28:15.503895   0 10  8 | B1->B0 | 3232 2626 | 1 0 | (1 1) (1 0)

  821 23:28:15.507635   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  822 23:28:15.511104   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  823 23:28:15.517450   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  824 23:28:15.520944   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  825 23:28:15.524074   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  826 23:28:15.530878   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

  827 23:28:15.534207   0 11  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

  828 23:28:15.537751   0 11  8 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)

  829 23:28:15.540665   0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)

  830 23:28:15.547382   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  831 23:28:15.551270   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  832 23:28:15.554120   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  833 23:28:15.560935   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  834 23:28:15.564472   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  835 23:28:15.567274   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

  836 23:28:15.574600   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

  837 23:28:15.577304   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  838 23:28:15.580782   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  839 23:28:15.587640   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  840 23:28:15.590766   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  841 23:28:15.594166   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  842 23:28:15.600810   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  843 23:28:15.604362   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  844 23:28:15.607635   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  845 23:28:15.614131   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  846 23:28:15.617406   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  847 23:28:15.621144   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  848 23:28:15.627798   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  849 23:28:15.631032   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  850 23:28:15.634194   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  851 23:28:15.637601   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

  852 23:28:15.644356   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)

  853 23:28:15.647493  Total UI for P1: 0, mck2ui 16

  854 23:28:15.650983  best dqsien dly found for B0: ( 0, 14,  6)

  855 23:28:15.654121   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

  856 23:28:15.658101   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

  857 23:28:15.661390  Total UI for P1: 0, mck2ui 16

  858 23:28:15.665322  best dqsien dly found for B1: ( 0, 14, 12)

  859 23:28:15.668778  best DQS0 dly(MCK, UI, PI) = (0, 14, 6)

  860 23:28:15.671854  best DQS1 dly(MCK, UI, PI) = (0, 14, 12)

  861 23:28:15.671957  

  862 23:28:15.675439  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)

  863 23:28:15.678288  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)

  864 23:28:15.681947  [Gating] SW calibration Done

  865 23:28:15.682049  ==

  866 23:28:15.685504  Dram Type= 6, Freq= 0, CH_0, rank 0

  867 23:28:15.691651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  868 23:28:15.691756  ==

  869 23:28:15.691850  RX Vref Scan: 0

  870 23:28:15.691939  

  871 23:28:15.695450  RX Vref 0 -> 0, step: 1

  872 23:28:15.695554  

  873 23:28:15.698778  RX Delay -130 -> 252, step: 16

  874 23:28:15.701784  iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240

  875 23:28:15.705274  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

  876 23:28:15.708867  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

  877 23:28:15.712195  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

  878 23:28:15.718895  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

  879 23:28:15.721939  iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224

  880 23:28:15.725893  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

  881 23:28:15.728836  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

  882 23:28:15.731808  iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240

  883 23:28:15.739199  iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240

  884 23:28:15.742008  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

  885 23:28:15.745391  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

  886 23:28:15.748728  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

  887 23:28:15.752573  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

  888 23:28:15.758578  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

  889 23:28:15.761833  iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240

  890 23:28:15.761912  ==

  891 23:28:15.765217  Dram Type= 6, Freq= 0, CH_0, rank 0

  892 23:28:15.769033  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  893 23:28:15.769138  ==

  894 23:28:15.772096  DQS Delay:

  895 23:28:15.772196  DQS0 = 0, DQS1 = 0

  896 23:28:15.772275  DQM Delay:

  897 23:28:15.775609  DQM0 = 89, DQM1 = 80

  898 23:28:15.775712  DQ Delay:

  899 23:28:15.778818  DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85

  900 23:28:15.781921  DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101

  901 23:28:15.785476  DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77

  902 23:28:15.788661  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85

  903 23:28:15.788761  

  904 23:28:15.788854  

  905 23:28:15.788942  ==

  906 23:28:15.792088  Dram Type= 6, Freq= 0, CH_0, rank 0

  907 23:28:15.798902  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  908 23:28:15.799001  ==

  909 23:28:15.799095  

  910 23:28:15.799183  

  911 23:28:15.799269  	TX Vref Scan disable

  912 23:28:15.802189   == TX Byte 0 ==

  913 23:28:15.805484  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  914 23:28:15.809344  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  915 23:28:15.812043   == TX Byte 1 ==

  916 23:28:15.815539  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  917 23:28:15.818882  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  918 23:28:15.822036  ==

  919 23:28:15.825354  Dram Type= 6, Freq= 0, CH_0, rank 0

  920 23:28:15.828813  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  921 23:28:15.828923  ==

  922 23:28:15.841350  TX Vref=22, minBit 10, minWin=27, winSum=448

  923 23:28:15.844344  TX Vref=24, minBit 9, minWin=27, winSum=453

  924 23:28:15.847748  TX Vref=26, minBit 10, minWin=27, winSum=455

  925 23:28:15.851281  TX Vref=28, minBit 8, minWin=28, winSum=458

  926 23:28:15.854674  TX Vref=30, minBit 8, minWin=28, winSum=458

  927 23:28:15.861464  TX Vref=32, minBit 0, minWin=28, winSum=457

  928 23:28:15.864908  [TxChooseVref] Worse bit 8, Min win 28, Win sum 458, Final Vref 28

  929 23:28:15.865010  

  930 23:28:15.867800  Final TX Range 1 Vref 28

  931 23:28:15.867926  

  932 23:28:15.868038  ==

  933 23:28:15.871616  Dram Type= 6, Freq= 0, CH_0, rank 0

  934 23:28:15.874653  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  935 23:28:15.874753  ==

  936 23:28:15.874845  

  937 23:28:15.877757  

  938 23:28:15.877857  	TX Vref Scan disable

  939 23:28:15.881196   == TX Byte 0 ==

  940 23:28:15.884831  Update DQ  dly =584 (2 ,1, 40)  DQ  OEN =(1 ,6)

  941 23:28:15.891578  Update DQM dly =584 (2 ,1, 40)  DQM OEN =(1 ,6)

  942 23:28:15.891682   == TX Byte 1 ==

  943 23:28:15.894843  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

  944 23:28:15.898272  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

  945 23:28:15.901687  

  946 23:28:15.901790  [DATLAT]

  947 23:28:15.901880  Freq=800, CH0 RK0

  948 23:28:15.901970  

  949 23:28:15.904893  DATLAT Default: 0xa

  950 23:28:15.904990  0, 0xFFFF, sum = 0

  951 23:28:15.908139  1, 0xFFFF, sum = 0

  952 23:28:15.908244  2, 0xFFFF, sum = 0

  953 23:28:15.911187  3, 0xFFFF, sum = 0

  954 23:28:15.911269  4, 0xFFFF, sum = 0

  955 23:28:15.914680  5, 0xFFFF, sum = 0

  956 23:28:15.917840  6, 0xFFFF, sum = 0

  957 23:28:15.917941  7, 0xFFFF, sum = 0

  958 23:28:15.921287  8, 0xFFFF, sum = 0

  959 23:28:15.921384  9, 0x0, sum = 1

  960 23:28:15.921477  10, 0x0, sum = 2

  961 23:28:15.924463  11, 0x0, sum = 3

  962 23:28:15.924560  12, 0x0, sum = 4

  963 23:28:15.927794  best_step = 10

  964 23:28:15.927895  

  965 23:28:15.927986  ==

  966 23:28:15.931413  Dram Type= 6, Freq= 0, CH_0, rank 0

  967 23:28:15.934550  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

  968 23:28:15.934623  ==

  969 23:28:15.937989  RX Vref Scan: 1

  970 23:28:15.938060  

  971 23:28:15.938149  Set Vref Range= 32 -> 127

  972 23:28:15.938237  

  973 23:28:15.941363  RX Vref 32 -> 127, step: 1

  974 23:28:15.941463  

  975 23:28:15.944758  RX Delay -95 -> 252, step: 8

  976 23:28:15.944856  

  977 23:28:15.948047  Set Vref, RX VrefLevel [Byte0]: 32

  978 23:28:15.951443                           [Byte1]: 32

  979 23:28:15.951541  

  980 23:28:15.954392  Set Vref, RX VrefLevel [Byte0]: 33

  981 23:28:15.957703                           [Byte1]: 33

  982 23:28:15.961913  

  983 23:28:15.962018  Set Vref, RX VrefLevel [Byte0]: 34

  984 23:28:15.964931                           [Byte1]: 34

  985 23:28:15.969322  

  986 23:28:15.969422  Set Vref, RX VrefLevel [Byte0]: 35

  987 23:28:15.972836                           [Byte1]: 35

  988 23:28:15.977524  

  989 23:28:15.977643  Set Vref, RX VrefLevel [Byte0]: 36

  990 23:28:15.980838                           [Byte1]: 36

  991 23:28:15.985206  

  992 23:28:15.985294  Set Vref, RX VrefLevel [Byte0]: 37

  993 23:28:15.988442                           [Byte1]: 37

  994 23:28:15.992986  

  995 23:28:15.993179  Set Vref, RX VrefLevel [Byte0]: 38

  996 23:28:15.995844                           [Byte1]: 38

  997 23:28:16.000287  

  998 23:28:16.000455  Set Vref, RX VrefLevel [Byte0]: 39

  999 23:28:16.003766                           [Byte1]: 39

 1000 23:28:16.007578  

 1001 23:28:16.007748  Set Vref, RX VrefLevel [Byte0]: 40

 1002 23:28:16.011209                           [Byte1]: 40

 1003 23:28:16.015268  

 1004 23:28:16.015491  Set Vref, RX VrefLevel [Byte0]: 41

 1005 23:28:16.018686                           [Byte1]: 41

 1006 23:28:16.022579  

 1007 23:28:16.022811  Set Vref, RX VrefLevel [Byte0]: 42

 1008 23:28:16.025918                           [Byte1]: 42

 1009 23:28:16.030199  

 1010 23:28:16.030414  Set Vref, RX VrefLevel [Byte0]: 43

 1011 23:28:16.033473                           [Byte1]: 43

 1012 23:28:16.037984  

 1013 23:28:16.038281  Set Vref, RX VrefLevel [Byte0]: 44

 1014 23:28:16.041474                           [Byte1]: 44

 1015 23:28:16.045615  

 1016 23:28:16.046037  Set Vref, RX VrefLevel [Byte0]: 45

 1017 23:28:16.048789                           [Byte1]: 45

 1018 23:28:16.053230  

 1019 23:28:16.053752  Set Vref, RX VrefLevel [Byte0]: 46

 1020 23:28:16.057084                           [Byte1]: 46

 1021 23:28:16.060974  

 1022 23:28:16.061394  Set Vref, RX VrefLevel [Byte0]: 47

 1023 23:28:16.064290                           [Byte1]: 47

 1024 23:28:16.068561  

 1025 23:28:16.068995  Set Vref, RX VrefLevel [Byte0]: 48

 1026 23:28:16.072042                           [Byte1]: 48

 1027 23:28:16.076064  

 1028 23:28:16.076476  Set Vref, RX VrefLevel [Byte0]: 49

 1029 23:28:16.079650                           [Byte1]: 49

 1030 23:28:16.083627  

 1031 23:28:16.084178  Set Vref, RX VrefLevel [Byte0]: 50

 1032 23:28:16.086989                           [Byte1]: 50

 1033 23:28:16.091317  

 1034 23:28:16.091916  Set Vref, RX VrefLevel [Byte0]: 51

 1035 23:28:16.094537                           [Byte1]: 51

 1036 23:28:16.098684  

 1037 23:28:16.099283  Set Vref, RX VrefLevel [Byte0]: 52

 1038 23:28:16.102605                           [Byte1]: 52

 1039 23:28:16.106591  

 1040 23:28:16.107004  Set Vref, RX VrefLevel [Byte0]: 53

 1041 23:28:16.109695                           [Byte1]: 53

 1042 23:28:16.113885  

 1043 23:28:16.114313  Set Vref, RX VrefLevel [Byte0]: 54

 1044 23:28:16.117240                           [Byte1]: 54

 1045 23:28:16.122184  

 1046 23:28:16.122705  Set Vref, RX VrefLevel [Byte0]: 55

 1047 23:28:16.124859                           [Byte1]: 55

 1048 23:28:16.129401  

 1049 23:28:16.129873  Set Vref, RX VrefLevel [Byte0]: 56

 1050 23:28:16.132825                           [Byte1]: 56

 1051 23:28:16.137020  

 1052 23:28:16.137477  Set Vref, RX VrefLevel [Byte0]: 57

 1053 23:28:16.140160                           [Byte1]: 57

 1054 23:28:16.144686  

 1055 23:28:16.145270  Set Vref, RX VrefLevel [Byte0]: 58

 1056 23:28:16.147497                           [Byte1]: 58

 1057 23:28:16.152037  

 1058 23:28:16.152610  Set Vref, RX VrefLevel [Byte0]: 59

 1059 23:28:16.155321                           [Byte1]: 59

 1060 23:28:16.159613  

 1061 23:28:16.160208  Set Vref, RX VrefLevel [Byte0]: 60

 1062 23:28:16.163151                           [Byte1]: 60

 1063 23:28:16.167117  

 1064 23:28:16.167697  Set Vref, RX VrefLevel [Byte0]: 61

 1065 23:28:16.170306                           [Byte1]: 61

 1066 23:28:16.175027  

 1067 23:28:16.175496  Set Vref, RX VrefLevel [Byte0]: 62

 1068 23:28:16.178323                           [Byte1]: 62

 1069 23:28:16.182267  

 1070 23:28:16.182886  Set Vref, RX VrefLevel [Byte0]: 63

 1071 23:28:16.185606                           [Byte1]: 63

 1072 23:28:16.189848  

 1073 23:28:16.190431  Set Vref, RX VrefLevel [Byte0]: 64

 1074 23:28:16.193622                           [Byte1]: 64

 1075 23:28:16.197618  

 1076 23:28:16.198174  Set Vref, RX VrefLevel [Byte0]: 65

 1077 23:28:16.201077                           [Byte1]: 65

 1078 23:28:16.205178  

 1079 23:28:16.205793  Set Vref, RX VrefLevel [Byte0]: 66

 1080 23:28:16.208190                           [Byte1]: 66

 1081 23:28:16.212882  

 1082 23:28:16.213482  Set Vref, RX VrefLevel [Byte0]: 67

 1083 23:28:16.216290                           [Byte1]: 67

 1084 23:28:16.220209  

 1085 23:28:16.220763  Set Vref, RX VrefLevel [Byte0]: 68

 1086 23:28:16.223566                           [Byte1]: 68

 1087 23:28:16.228075  

 1088 23:28:16.228658  Set Vref, RX VrefLevel [Byte0]: 69

 1089 23:28:16.231335                           [Byte1]: 69

 1090 23:28:16.235362  

 1091 23:28:16.235957  Set Vref, RX VrefLevel [Byte0]: 70

 1092 23:28:16.239518                           [Byte1]: 70

 1093 23:28:16.243192  

 1094 23:28:16.243707  Set Vref, RX VrefLevel [Byte0]: 71

 1095 23:28:16.246760                           [Byte1]: 71

 1096 23:28:16.250728  

 1097 23:28:16.251313  Set Vref, RX VrefLevel [Byte0]: 72

 1098 23:28:16.254031                           [Byte1]: 72

 1099 23:28:16.258371  

 1100 23:28:16.258974  Set Vref, RX VrefLevel [Byte0]: 73

 1101 23:28:16.261933                           [Byte1]: 73

 1102 23:28:16.266297  

 1103 23:28:16.266847  Set Vref, RX VrefLevel [Byte0]: 74

 1104 23:28:16.269223                           [Byte1]: 74

 1105 23:28:16.273472  

 1106 23:28:16.274077  Set Vref, RX VrefLevel [Byte0]: 75

 1107 23:28:16.276670                           [Byte1]: 75

 1108 23:28:16.281683  

 1109 23:28:16.282285  Set Vref, RX VrefLevel [Byte0]: 76

 1110 23:28:16.284430                           [Byte1]: 76

 1111 23:28:16.288555  

 1112 23:28:16.289114  Set Vref, RX VrefLevel [Byte0]: 77

 1113 23:28:16.292039                           [Byte1]: 77

 1114 23:28:16.296524  

 1115 23:28:16.297103  Set Vref, RX VrefLevel [Byte0]: 78

 1116 23:28:16.299460                           [Byte1]: 78

 1117 23:28:16.303921  

 1118 23:28:16.304458  Set Vref, RX VrefLevel [Byte0]: 79

 1119 23:28:16.307411                           [Byte1]: 79

 1120 23:28:16.311577  

 1121 23:28:16.312164  Final RX Vref Byte 0 = 58 to rank0

 1122 23:28:16.315008  Final RX Vref Byte 1 = 60 to rank0

 1123 23:28:16.318489  Final RX Vref Byte 0 = 58 to rank1

 1124 23:28:16.321801  Final RX Vref Byte 1 = 60 to rank1==

 1125 23:28:16.324903  Dram Type= 6, Freq= 0, CH_0, rank 0

 1126 23:28:16.328134  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1127 23:28:16.331591  ==

 1128 23:28:16.332200  DQS Delay:

 1129 23:28:16.332742  DQS0 = 0, DQS1 = 0

 1130 23:28:16.335136  DQM Delay:

 1131 23:28:16.335715  DQM0 = 92, DQM1 = 85

 1132 23:28:16.338521  DQ Delay:

 1133 23:28:16.341472  DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88

 1134 23:28:16.345463  DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100

 1135 23:28:16.346084  DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76

 1136 23:28:16.351469  DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92

 1137 23:28:16.351568  

 1138 23:28:16.351657  

 1139 23:28:16.357966  [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps

 1140 23:28:16.361265  CH0 RK0: MR19=606, MR18=4C43

 1141 23:28:16.368323  CH0_RK0: MR19=0x606, MR18=0x4C43, DQSOSC=390, MR23=63, INC=97, DEC=64

 1142 23:28:16.368431  

 1143 23:28:16.371204  ----->DramcWriteLeveling(PI) begin...

 1144 23:28:16.371276  ==

 1145 23:28:16.374581  Dram Type= 6, Freq= 0, CH_0, rank 1

 1146 23:28:16.378018  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1147 23:28:16.378115  ==

 1148 23:28:16.381611  Write leveling (Byte 0): 35 => 35

 1149 23:28:16.425191  Write leveling (Byte 1): 31 => 31

 1150 23:28:16.425328  DramcWriteLeveling(PI) end<-----

 1151 23:28:16.425423  

 1152 23:28:16.425514  ==

 1153 23:28:16.425828  Dram Type= 6, Freq= 0, CH_0, rank 1

 1154 23:28:16.426078  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1155 23:28:16.426145  ==

 1156 23:28:16.426205  [Gating] SW mode calibration

 1157 23:28:16.426894  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1158 23:28:16.426989  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1159 23:28:16.427379   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1160 23:28:16.428024   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1161 23:28:16.428405   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1162 23:28:16.469572   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1163 23:28:16.469742   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1164 23:28:16.470132   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1165 23:28:16.470719   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1166 23:28:16.471343   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1167 23:28:16.471651   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1168 23:28:16.471743   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1169 23:28:16.472016   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1170 23:28:16.472423   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1171 23:28:16.473072   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1172 23:28:16.513606   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1173 23:28:16.513716   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1174 23:28:16.513967   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1175 23:28:16.514046   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1176 23:28:16.514325   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1177 23:28:16.514600   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1178 23:28:16.514692   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1179 23:28:16.514790   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1180 23:28:16.514893   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1181 23:28:16.515167   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1182 23:28:16.530203   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1183 23:28:16.530280   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1184 23:28:16.530537   0  9  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1185 23:28:16.530630   0  9  8 | B1->B0 | 2e2e 2e2e | 0 1 | (0 0) (0 0)

 1186 23:28:16.533845   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1187 23:28:16.536884   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1188 23:28:16.543468   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1189 23:28:16.546835   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1190 23:28:16.550410   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1191 23:28:16.553699   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1192 23:28:16.561452   0 10  4 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)

 1193 23:28:16.565105   0 10  8 | B1->B0 | 2525 2727 | 0 0 | (1 1) (0 0)

 1194 23:28:16.568886   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1195 23:28:16.572337   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1196 23:28:16.579277   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1197 23:28:16.582732   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1198 23:28:16.585957   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1199 23:28:16.590193   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1200 23:28:16.596209   0 11  4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 1201 23:28:16.599539   0 11  8 | B1->B0 | 3939 3c3c | 1 0 | (0 0) (0 0)

 1202 23:28:16.602738   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1203 23:28:16.609852   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1204 23:28:16.613292   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1205 23:28:16.616025   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1206 23:28:16.619497   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1207 23:28:16.626559   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1208 23:28:16.629924   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1209 23:28:16.632880   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1210 23:28:16.639575   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1211 23:28:16.643285   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1212 23:28:16.646618   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1213 23:28:16.653141   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1214 23:28:16.656445   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1215 23:28:16.659752   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1216 23:28:16.666789   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1217 23:28:16.669469   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1218 23:28:16.673453   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1219 23:28:16.679903   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1220 23:28:16.683245   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1221 23:28:16.686414   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1222 23:28:16.693019   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1223 23:28:16.696346   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1224 23:28:16.699728   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1225 23:28:16.703004   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1226 23:28:16.709665   0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1227 23:28:16.713345  Total UI for P1: 0, mck2ui 16

 1228 23:28:16.716812  best dqsien dly found for B0: ( 0, 14,  8)

 1229 23:28:16.720183  Total UI for P1: 0, mck2ui 16

 1230 23:28:16.723427  best dqsien dly found for B1: ( 0, 14,  8)

 1231 23:28:16.726696  best DQS0 dly(MCK, UI, PI) = (0, 14, 8)

 1232 23:28:16.729846  best DQS1 dly(MCK, UI, PI) = (0, 14, 8)

 1233 23:28:16.729920  

 1234 23:28:16.733046  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1235 23:28:16.736946  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)

 1236 23:28:16.739955  [Gating] SW calibration Done

 1237 23:28:16.740037  ==

 1238 23:28:16.743415  Dram Type= 6, Freq= 0, CH_0, rank 1

 1239 23:28:16.746418  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1240 23:28:16.746516  ==

 1241 23:28:16.749689  RX Vref Scan: 0

 1242 23:28:16.749789  

 1243 23:28:16.749880  RX Vref 0 -> 0, step: 1

 1244 23:28:16.749967  

 1245 23:28:16.752949  RX Delay -130 -> 252, step: 16

 1246 23:28:16.756291  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1247 23:28:16.763315  iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224

 1248 23:28:16.766538  iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240

 1249 23:28:16.769815  iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240

 1250 23:28:16.773038  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1251 23:28:16.776292  iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240

 1252 23:28:16.782915  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1253 23:28:16.786208  iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240

 1254 23:28:16.789645  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1255 23:28:16.793128  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1256 23:28:16.796451  iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224

 1257 23:28:16.803160  iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224

 1258 23:28:16.806536  iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240

 1259 23:28:16.809663  iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240

 1260 23:28:16.813523  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1261 23:28:16.816581  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1262 23:28:16.819726  ==

 1263 23:28:16.823085  Dram Type= 6, Freq= 0, CH_0, rank 1

 1264 23:28:16.826752  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1265 23:28:16.826829  ==

 1266 23:28:16.826894  DQS Delay:

 1267 23:28:16.829733  DQS0 = 0, DQS1 = 0

 1268 23:28:16.829832  DQM Delay:

 1269 23:28:16.832955  DQM0 = 91, DQM1 = 83

 1270 23:28:16.833051  DQ Delay:

 1271 23:28:16.836452  DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85

 1272 23:28:16.839837  DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101

 1273 23:28:16.843216  DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77

 1274 23:28:16.846627  DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93

 1275 23:28:16.846737  

 1276 23:28:16.846830  

 1277 23:28:16.846929  ==

 1278 23:28:16.849974  Dram Type= 6, Freq= 0, CH_0, rank 1

 1279 23:28:16.853253  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1280 23:28:16.853352  ==

 1281 23:28:16.853444  

 1282 23:28:16.853528  

 1283 23:28:16.856786  	TX Vref Scan disable

 1284 23:28:16.860212   == TX Byte 0 ==

 1285 23:28:16.863152  Update DQ  dly =586 (2 ,2, 10)  DQ  OEN =(1 ,7)

 1286 23:28:16.866377  Update DQM dly =586 (2 ,2, 10)  DQM OEN =(1 ,7)

 1287 23:28:16.870334   == TX Byte 1 ==

 1288 23:28:16.873438  Update DQ  dly =581 (2 ,1, 37)  DQ  OEN =(1 ,6)

 1289 23:28:16.876781  Update DQM dly =581 (2 ,1, 37)  DQM OEN =(1 ,6)

 1290 23:28:16.876878  ==

 1291 23:28:16.880373  Dram Type= 6, Freq= 0, CH_0, rank 1

 1292 23:28:16.883302  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1293 23:28:16.883395  ==

 1294 23:28:16.898641  TX Vref=22, minBit 11, minWin=27, winSum=447

 1295 23:28:16.901599  TX Vref=24, minBit 8, minWin=27, winSum=450

 1296 23:28:16.904886  TX Vref=26, minBit 1, minWin=28, winSum=456

 1297 23:28:16.908633  TX Vref=28, minBit 1, minWin=28, winSum=458

 1298 23:28:16.911856  TX Vref=30, minBit 4, minWin=28, winSum=458

 1299 23:28:16.915454  TX Vref=32, minBit 1, minWin=28, winSum=455

 1300 23:28:16.922053  [TxChooseVref] Worse bit 1, Min win 28, Win sum 458, Final Vref 28

 1301 23:28:16.922154  

 1302 23:28:16.925187  Final TX Range 1 Vref 28

 1303 23:28:16.925286  

 1304 23:28:16.925373  ==

 1305 23:28:16.928347  Dram Type= 6, Freq= 0, CH_0, rank 1

 1306 23:28:16.931982  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1307 23:28:16.932081  ==

 1308 23:28:16.932173  

 1309 23:28:16.932259  

 1310 23:28:16.935022  	TX Vref Scan disable

 1311 23:28:16.938474   == TX Byte 0 ==

 1312 23:28:16.941969  Update DQ  dly =586 (2 ,2, 10)  DQ  OEN =(1 ,7)

 1313 23:28:16.944942  Update DQM dly =586 (2 ,2, 10)  DQM OEN =(1 ,7)

 1314 23:28:16.948743   == TX Byte 1 ==

 1315 23:28:16.951840  Update DQ  dly =580 (2 ,1, 36)  DQ  OEN =(1 ,6)

 1316 23:28:16.955189  Update DQM dly =580 (2 ,1, 36)  DQM OEN =(1 ,6)

 1317 23:28:16.958507  

 1318 23:28:16.958604  [DATLAT]

 1319 23:28:16.958697  Freq=800, CH0 RK1

 1320 23:28:16.958785  

 1321 23:28:16.961498  DATLAT Default: 0xa

 1322 23:28:16.961643  0, 0xFFFF, sum = 0

 1323 23:28:16.965413  1, 0xFFFF, sum = 0

 1324 23:28:16.965530  2, 0xFFFF, sum = 0

 1325 23:28:16.968876  3, 0xFFFF, sum = 0

 1326 23:28:16.968981  4, 0xFFFF, sum = 0

 1327 23:28:16.971659  5, 0xFFFF, sum = 0

 1328 23:28:16.971766  6, 0xFFFF, sum = 0

 1329 23:28:16.975161  7, 0xFFFF, sum = 0

 1330 23:28:16.975235  8, 0xFFFF, sum = 0

 1331 23:28:16.978748  9, 0x0, sum = 1

 1332 23:28:16.978832  10, 0x0, sum = 2

 1333 23:28:16.981856  11, 0x0, sum = 3

 1334 23:28:16.981957  12, 0x0, sum = 4

 1335 23:28:16.985494  best_step = 10

 1336 23:28:16.985633  

 1337 23:28:16.985698  ==

 1338 23:28:16.989034  Dram Type= 6, Freq= 0, CH_0, rank 1

 1339 23:28:16.991953  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1340 23:28:16.992050  ==

 1341 23:28:16.995156  RX Vref Scan: 0

 1342 23:28:16.995253  

 1343 23:28:16.995341  RX Vref 0 -> 0, step: 1

 1344 23:28:16.995429  

 1345 23:28:16.998440  RX Delay -79 -> 252, step: 8

 1346 23:28:17.004894  iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216

 1347 23:28:17.008677  iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208

 1348 23:28:17.011878  iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224

 1349 23:28:17.015051  iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224

 1350 23:28:17.018304  iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216

 1351 23:28:17.021671  iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224

 1352 23:28:17.028481  iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216

 1353 23:28:17.031606  iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216

 1354 23:28:17.035120  iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216

 1355 23:28:17.038538  iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208

 1356 23:28:17.041728  iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216

 1357 23:28:17.048279  iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216

 1358 23:28:17.051621  iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208

 1359 23:28:17.055647  iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216

 1360 23:28:17.058445  iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216

 1361 23:28:17.065532  iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224

 1362 23:28:17.065659  ==

 1363 23:28:17.068342  Dram Type= 6, Freq= 0, CH_0, rank 1

 1364 23:28:17.071915  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1365 23:28:17.071989  ==

 1366 23:28:17.072053  DQS Delay:

 1367 23:28:17.075360  DQS0 = 0, DQS1 = 0

 1368 23:28:17.075457  DQM Delay:

 1369 23:28:17.078483  DQM0 = 93, DQM1 = 82

 1370 23:28:17.078586  DQ Delay:

 1371 23:28:17.081674  DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88

 1372 23:28:17.085050  DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100

 1373 23:28:17.088776  DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76

 1374 23:28:17.091735  DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =88

 1375 23:28:17.091909  

 1376 23:28:17.092012  

 1377 23:28:17.098528  [DQSOSCAuto] RK1, (LSB)MR18= 0x4415, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps

 1378 23:28:17.101892  CH0 RK1: MR19=606, MR18=4415

 1379 23:28:17.108567  CH0_RK1: MR19=0x606, MR18=0x4415, DQSOSC=392, MR23=63, INC=96, DEC=64

 1380 23:28:17.111768  [RxdqsGatingPostProcess] freq 800

 1381 23:28:17.118239  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 1382 23:28:17.118323  Pre-setting of DQS Precalculation

 1383 23:28:17.124944  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 1384 23:28:17.125045  ==

 1385 23:28:17.128431  Dram Type= 6, Freq= 0, CH_1, rank 0

 1386 23:28:17.131885  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1387 23:28:17.131961  ==

 1388 23:28:17.138368  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1389 23:28:17.144997  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1390 23:28:17.153248  [CA 0] Center 36 (6~67) winsize 62

 1391 23:28:17.156763  [CA 1] Center 36 (6~67) winsize 62

 1392 23:28:17.160236  [CA 2] Center 35 (5~66) winsize 62

 1393 23:28:17.163662  [CA 3] Center 34 (4~65) winsize 62

 1394 23:28:17.166522  [CA 4] Center 35 (5~65) winsize 61

 1395 23:28:17.170052  [CA 5] Center 34 (4~64) winsize 61

 1396 23:28:17.170134  

 1397 23:28:17.173438  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1398 23:28:17.173519  

 1399 23:28:17.176948  [CATrainingPosCal] consider 1 rank data

 1400 23:28:17.180293  u2DelayCellTimex100 = 270/100 ps

 1401 23:28:17.183003  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1402 23:28:17.186787  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1403 23:28:17.193045  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1404 23:28:17.196736  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1405 23:28:17.199653  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1406 23:28:17.203395  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1407 23:28:17.203477  

 1408 23:28:17.206795  CA PerBit enable=1, Macro0, CA PI delay=34

 1409 23:28:17.206878  

 1410 23:28:17.210117  [CBTSetCACLKResult] CA Dly = 34

 1411 23:28:17.210199  CS Dly: 5 (0~36)

 1412 23:28:17.210264  ==

 1413 23:28:17.213362  Dram Type= 6, Freq= 0, CH_1, rank 1

 1414 23:28:17.220543  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1415 23:28:17.220638  ==

 1416 23:28:17.223961  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 1417 23:28:17.230846  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34

 1418 23:28:17.239839  [CA 0] Center 36 (6~67) winsize 62

 1419 23:28:17.243144  [CA 1] Center 36 (6~67) winsize 62

 1420 23:28:17.246868  [CA 2] Center 35 (5~66) winsize 62

 1421 23:28:17.250328  [CA 3] Center 34 (4~65) winsize 62

 1422 23:28:17.254172  [CA 4] Center 35 (5~66) winsize 62

 1423 23:28:17.257054  [CA 5] Center 34 (4~65) winsize 62

 1424 23:28:17.257150  

 1425 23:28:17.260802  [CmdBusTrainingLP45] Vref(ca) range 1: 34

 1426 23:28:17.260905  

 1427 23:28:17.263835  [CATrainingPosCal] consider 2 rank data

 1428 23:28:17.267518  u2DelayCellTimex100 = 270/100 ps

 1429 23:28:17.270516  CA0 delay=36 (6~67),Diff = 2 PI (14 cell)

 1430 23:28:17.273998  CA1 delay=36 (6~67),Diff = 2 PI (14 cell)

 1431 23:28:17.277326  CA2 delay=35 (5~66),Diff = 1 PI (7 cell)

 1432 23:28:17.280791  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 1433 23:28:17.283942  CA4 delay=35 (5~65),Diff = 1 PI (7 cell)

 1434 23:28:17.287690  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 1435 23:28:17.287790  

 1436 23:28:17.294287  CA PerBit enable=1, Macro0, CA PI delay=34

 1437 23:28:17.294379  

 1438 23:28:17.294442  [CBTSetCACLKResult] CA Dly = 34

 1439 23:28:17.297529  CS Dly: 6 (0~38)

 1440 23:28:17.297659  

 1441 23:28:17.300464  ----->DramcWriteLeveling(PI) begin...

 1442 23:28:17.300549  ==

 1443 23:28:17.304265  Dram Type= 6, Freq= 0, CH_1, rank 0

 1444 23:28:17.307631  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1445 23:28:17.307718  ==

 1446 23:28:17.310594  Write leveling (Byte 0): 28 => 28

 1447 23:28:17.314276  Write leveling (Byte 1): 28 => 28

 1448 23:28:17.317516  DramcWriteLeveling(PI) end<-----

 1449 23:28:17.317666  

 1450 23:28:17.317798  ==

 1451 23:28:17.320884  Dram Type= 6, Freq= 0, CH_1, rank 0

 1452 23:28:17.324143  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1453 23:28:17.327389  ==

 1454 23:28:17.327489  [Gating] SW mode calibration

 1455 23:28:17.337512  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1456 23:28:17.340956  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1457 23:28:17.343870   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)

 1458 23:28:17.350931   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1459 23:28:17.354199   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1460 23:28:17.358042   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1461 23:28:17.363885   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1462 23:28:17.367762   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1463 23:28:17.370895   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1464 23:28:17.377515   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1465 23:28:17.381208   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1466 23:28:17.384223   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1467 23:28:17.387740   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1468 23:28:17.394340   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1469 23:28:17.397743   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1470 23:28:17.400780   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1471 23:28:17.407590   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1472 23:28:17.411187   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1473 23:28:17.414193   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)

 1474 23:28:17.420667   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)

 1475 23:28:17.424116   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1476 23:28:17.427628   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1477 23:28:17.434245   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1478 23:28:17.437421   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1479 23:28:17.440832   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1480 23:28:17.447494   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1481 23:28:17.450836   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1482 23:28:17.454299   0  9  4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 1483 23:28:17.460942   0  9  8 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 1484 23:28:17.464320   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1485 23:28:17.467828   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1486 23:28:17.474658   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1487 23:28:17.478164   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1488 23:28:17.481235   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1489 23:28:17.484480   0 10  0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 1490 23:28:17.490624   0 10  4 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)

 1491 23:28:17.493976   0 10  8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)

 1492 23:28:17.497343   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1493 23:28:17.504038   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1494 23:28:17.507964   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1495 23:28:17.510914   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1496 23:28:17.517631   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1497 23:28:17.520685   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1498 23:28:17.524538   0 11  4 | B1->B0 | 2a2a 3333 | 0 0 | (0 0) (1 1)

 1499 23:28:17.531026   0 11  8 | B1->B0 | 4141 4646 | 1 0 | (1 1) (0 0)

 1500 23:28:17.534568   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1501 23:28:17.537811   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1502 23:28:17.544417   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1503 23:28:17.547894   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1504 23:28:17.550794   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1505 23:28:17.557459   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1506 23:28:17.561057   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1507 23:28:17.564149   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1508 23:28:17.567902   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1509 23:28:17.574626   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1510 23:28:17.577957   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1511 23:28:17.580810   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1512 23:28:17.587744   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1513 23:28:17.591339   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1514 23:28:17.594745   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1515 23:28:17.600911   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1516 23:28:17.604419   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1517 23:28:17.608200   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1518 23:28:17.614696   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1519 23:28:17.617883   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1520 23:28:17.621269   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1521 23:28:17.627802   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1522 23:28:17.631169   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1523 23:28:17.634803   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1524 23:28:17.637883  Total UI for P1: 0, mck2ui 16

 1525 23:28:17.641204  best dqsien dly found for B0: ( 0, 14,  4)

 1526 23:28:17.644660  Total UI for P1: 0, mck2ui 16

 1527 23:28:17.647971  best dqsien dly found for B1: ( 0, 14,  4)

 1528 23:28:17.651296  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1529 23:28:17.654838  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1530 23:28:17.654911  

 1531 23:28:17.658277  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1532 23:28:17.661059  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1533 23:28:17.664761  [Gating] SW calibration Done

 1534 23:28:17.664849  ==

 1535 23:28:17.668246  Dram Type= 6, Freq= 0, CH_1, rank 0

 1536 23:28:17.671362  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1537 23:28:17.675001  ==

 1538 23:28:17.675101  RX Vref Scan: 0

 1539 23:28:17.675181  

 1540 23:28:17.677856  RX Vref 0 -> 0, step: 1

 1541 23:28:17.677957  

 1542 23:28:17.681367  RX Delay -130 -> 252, step: 16

 1543 23:28:17.684847  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1544 23:28:17.688280  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1545 23:28:17.691129  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1546 23:28:17.695071  iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224

 1547 23:28:17.701123  iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224

 1548 23:28:17.704585  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1549 23:28:17.708689  iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224

 1550 23:28:17.711490  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1551 23:28:17.714612  iDelay=222, Bit 8, Center 85 (-18 ~ 189) 208

 1552 23:28:17.721688  iDelay=222, Bit 9, Center 85 (-18 ~ 189) 208

 1553 23:28:17.724838  iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208

 1554 23:28:17.728011  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1555 23:28:17.731444  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1556 23:28:17.734861  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1557 23:28:17.741385  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1558 23:28:17.744643  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1559 23:28:17.745218  ==

 1560 23:28:17.748434  Dram Type= 6, Freq= 0, CH_1, rank 0

 1561 23:28:17.751425  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1562 23:28:17.752070  ==

 1563 23:28:17.754948  DQS Delay:

 1564 23:28:17.755058  DQS0 = 0, DQS1 = 0

 1565 23:28:17.755188  DQM Delay:

 1566 23:28:17.757798  DQM0 = 93, DQM1 = 89

 1567 23:28:17.757879  DQ Delay:

 1568 23:28:17.760969  DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93

 1569 23:28:17.764490  DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93

 1570 23:28:17.767669  DQ8 =85, DQ9 =85, DQ10 =85, DQ11 =85

 1571 23:28:17.770962  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1572 23:28:17.771041  

 1573 23:28:17.771104  

 1574 23:28:17.771195  ==

 1575 23:28:17.774523  Dram Type= 6, Freq= 0, CH_1, rank 0

 1576 23:28:17.780984  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1577 23:28:17.781060  ==

 1578 23:28:17.781123  

 1579 23:28:17.781181  

 1580 23:28:17.781237  	TX Vref Scan disable

 1581 23:28:17.784575   == TX Byte 0 ==

 1582 23:28:17.788204  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1583 23:28:17.791744  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1584 23:28:17.794711   == TX Byte 1 ==

 1585 23:28:17.798346  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1586 23:28:17.801933  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1587 23:28:17.802006  ==

 1588 23:28:17.805070  Dram Type= 6, Freq= 0, CH_1, rank 0

 1589 23:28:17.811785  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1590 23:28:17.811887  ==

 1591 23:28:17.823573  TX Vref=22, minBit 0, minWin=26, winSum=434

 1592 23:28:17.826986  TX Vref=24, minBit 1, minWin=26, winSum=442

 1593 23:28:17.830278  TX Vref=26, minBit 3, minWin=26, winSum=442

 1594 23:28:17.833820  TX Vref=28, minBit 1, minWin=27, winSum=444

 1595 23:28:17.837287  TX Vref=30, minBit 0, minWin=27, winSum=449

 1596 23:28:17.840535  TX Vref=32, minBit 0, minWin=27, winSum=447

 1597 23:28:17.847213  [TxChooseVref] Worse bit 0, Min win 27, Win sum 449, Final Vref 30

 1598 23:28:17.847317  

 1599 23:28:17.850548  Final TX Range 1 Vref 30

 1600 23:28:17.850649  

 1601 23:28:17.850741  ==

 1602 23:28:17.853687  Dram Type= 6, Freq= 0, CH_1, rank 0

 1603 23:28:17.856894  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1604 23:28:17.856967  ==

 1605 23:28:17.857065  

 1606 23:28:17.860266  

 1607 23:28:17.860367  	TX Vref Scan disable

 1608 23:28:17.863406   == TX Byte 0 ==

 1609 23:28:17.866908  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 1610 23:28:17.870830  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 1611 23:28:17.873875   == TX Byte 1 ==

 1612 23:28:17.876937  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1613 23:28:17.880453  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1614 23:28:17.880554  

 1615 23:28:17.884064  [DATLAT]

 1616 23:28:17.884162  Freq=800, CH1 RK0

 1617 23:28:17.884262  

 1618 23:28:17.887352  DATLAT Default: 0xa

 1619 23:28:17.887457  0, 0xFFFF, sum = 0

 1620 23:28:17.891077  1, 0xFFFF, sum = 0

 1621 23:28:17.891187  2, 0xFFFF, sum = 0

 1622 23:28:17.893624  3, 0xFFFF, sum = 0

 1623 23:28:17.893708  4, 0xFFFF, sum = 0

 1624 23:28:17.897010  5, 0xFFFF, sum = 0

 1625 23:28:17.897113  6, 0xFFFF, sum = 0

 1626 23:28:17.900552  7, 0xFFFF, sum = 0

 1627 23:28:17.900661  8, 0xFFFF, sum = 0

 1628 23:28:17.903985  9, 0x0, sum = 1

 1629 23:28:17.904087  10, 0x0, sum = 2

 1630 23:28:17.907279  11, 0x0, sum = 3

 1631 23:28:17.907350  12, 0x0, sum = 4

 1632 23:28:17.910860  best_step = 10

 1633 23:28:17.910930  

 1634 23:28:17.910989  ==

 1635 23:28:17.914039  Dram Type= 6, Freq= 0, CH_1, rank 0

 1636 23:28:17.917496  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1637 23:28:17.917599  ==

 1638 23:28:17.920669  RX Vref Scan: 1

 1639 23:28:17.920742  

 1640 23:28:17.920801  Set Vref Range= 32 -> 127

 1641 23:28:17.920886  

 1642 23:28:17.923945  RX Vref 32 -> 127, step: 1

 1643 23:28:17.924058  

 1644 23:28:17.927483  RX Delay -63 -> 252, step: 8

 1645 23:28:17.927600  

 1646 23:28:17.930929  Set Vref, RX VrefLevel [Byte0]: 32

 1647 23:28:17.934141                           [Byte1]: 32

 1648 23:28:17.934251  

 1649 23:28:17.937318  Set Vref, RX VrefLevel [Byte0]: 33

 1650 23:28:17.940859                           [Byte1]: 33

 1651 23:28:17.940937  

 1652 23:28:17.943661  Set Vref, RX VrefLevel [Byte0]: 34

 1653 23:28:17.947369                           [Byte1]: 34

 1654 23:28:17.951127  

 1655 23:28:17.951225  Set Vref, RX VrefLevel [Byte0]: 35

 1656 23:28:17.954508                           [Byte1]: 35

 1657 23:28:17.958894  

 1658 23:28:17.958992  Set Vref, RX VrefLevel [Byte0]: 36

 1659 23:28:17.961724                           [Byte1]: 36

 1660 23:28:17.966132  

 1661 23:28:17.966205  Set Vref, RX VrefLevel [Byte0]: 37

 1662 23:28:17.969442                           [Byte1]: 37

 1663 23:28:17.973897  

 1664 23:28:17.973990  Set Vref, RX VrefLevel [Byte0]: 38

 1665 23:28:17.976831                           [Byte1]: 38

 1666 23:28:17.981199  

 1667 23:28:17.981298  Set Vref, RX VrefLevel [Byte0]: 39

 1668 23:28:17.984656                           [Byte1]: 39

 1669 23:28:17.988882  

 1670 23:28:17.988989  Set Vref, RX VrefLevel [Byte0]: 40

 1671 23:28:17.991717                           [Byte1]: 40

 1672 23:28:17.995933  

 1673 23:28:17.996036  Set Vref, RX VrefLevel [Byte0]: 41

 1674 23:28:17.999806                           [Byte1]: 41

 1675 23:28:18.003529  

 1676 23:28:18.003635  Set Vref, RX VrefLevel [Byte0]: 42

 1677 23:28:18.006857                           [Byte1]: 42

 1678 23:28:18.010940  

 1679 23:28:18.011044  Set Vref, RX VrefLevel [Byte0]: 43

 1680 23:28:18.014248                           [Byte1]: 43

 1681 23:28:18.018558  

 1682 23:28:18.018660  Set Vref, RX VrefLevel [Byte0]: 44

 1683 23:28:18.022231                           [Byte1]: 44

 1684 23:28:18.026090  

 1685 23:28:18.026168  Set Vref, RX VrefLevel [Byte0]: 45

 1686 23:28:18.029663                           [Byte1]: 45

 1687 23:28:18.033657  

 1688 23:28:18.033788  Set Vref, RX VrefLevel [Byte0]: 46

 1689 23:28:18.037054                           [Byte1]: 46

 1690 23:28:18.041308  

 1691 23:28:18.041409  Set Vref, RX VrefLevel [Byte0]: 47

 1692 23:28:18.044521                           [Byte1]: 47

 1693 23:28:18.048553  

 1694 23:28:18.048635  Set Vref, RX VrefLevel [Byte0]: 48

 1695 23:28:18.052005                           [Byte1]: 48

 1696 23:28:18.055943  

 1697 23:28:18.056050  Set Vref, RX VrefLevel [Byte0]: 49

 1698 23:28:18.059277                           [Byte1]: 49

 1699 23:28:18.063976  

 1700 23:28:18.064076  Set Vref, RX VrefLevel [Byte0]: 50

 1701 23:28:18.066898                           [Byte1]: 50

 1702 23:28:18.071073  

 1703 23:28:18.071180  Set Vref, RX VrefLevel [Byte0]: 51

 1704 23:28:18.074464                           [Byte1]: 51

 1705 23:28:18.078563  

 1706 23:28:18.078662  Set Vref, RX VrefLevel [Byte0]: 52

 1707 23:28:18.081780                           [Byte1]: 52

 1708 23:28:18.085941  

 1709 23:28:18.086014  Set Vref, RX VrefLevel [Byte0]: 53

 1710 23:28:18.089194                           [Byte1]: 53

 1711 23:28:18.093808  

 1712 23:28:18.093889  Set Vref, RX VrefLevel [Byte0]: 54

 1713 23:28:18.096654                           [Byte1]: 54

 1714 23:28:18.101172  

 1715 23:28:18.101273  Set Vref, RX VrefLevel [Byte0]: 55

 1716 23:28:18.104215                           [Byte1]: 55

 1717 23:28:18.108795  

 1718 23:28:18.108895  Set Vref, RX VrefLevel [Byte0]: 56

 1719 23:28:18.112030                           [Byte1]: 56

 1720 23:28:18.116061  

 1721 23:28:18.116164  Set Vref, RX VrefLevel [Byte0]: 57

 1722 23:28:18.119367                           [Byte1]: 57

 1723 23:28:18.123756  

 1724 23:28:18.123867  Set Vref, RX VrefLevel [Byte0]: 58

 1725 23:28:18.126749                           [Byte1]: 58

 1726 23:28:18.131014  

 1727 23:28:18.131086  Set Vref, RX VrefLevel [Byte0]: 59

 1728 23:28:18.134294                           [Byte1]: 59

 1729 23:28:18.138840  

 1730 23:28:18.138925  Set Vref, RX VrefLevel [Byte0]: 60

 1731 23:28:18.142190                           [Byte1]: 60

 1732 23:28:18.146137  

 1733 23:28:18.146236  Set Vref, RX VrefLevel [Byte0]: 61

 1734 23:28:18.149304                           [Byte1]: 61

 1735 23:28:18.153828  

 1736 23:28:18.153979  Set Vref, RX VrefLevel [Byte0]: 62

 1737 23:28:18.156787                           [Byte1]: 62

 1738 23:28:18.161253  

 1739 23:28:18.161711  Set Vref, RX VrefLevel [Byte0]: 63

 1740 23:28:18.164608                           [Byte1]: 63

 1741 23:28:18.168928  

 1742 23:28:18.169362  Set Vref, RX VrefLevel [Byte0]: 64

 1743 23:28:18.171995                           [Byte1]: 64

 1744 23:28:18.176748  

 1745 23:28:18.177250  Set Vref, RX VrefLevel [Byte0]: 65

 1746 23:28:18.180166                           [Byte1]: 65

 1747 23:28:18.183825  

 1748 23:28:18.184371  Set Vref, RX VrefLevel [Byte0]: 66

 1749 23:28:18.187205                           [Byte1]: 66

 1750 23:28:18.191927  

 1751 23:28:18.192388  Set Vref, RX VrefLevel [Byte0]: 67

 1752 23:28:18.194784                           [Byte1]: 67

 1753 23:28:18.198935  

 1754 23:28:18.199451  Set Vref, RX VrefLevel [Byte0]: 68

 1755 23:28:18.202795                           [Byte1]: 68

 1756 23:28:18.206638  

 1757 23:28:18.207045  Set Vref, RX VrefLevel [Byte0]: 69

 1758 23:28:18.209694                           [Byte1]: 69

 1759 23:28:18.214625  

 1760 23:28:18.215171  Set Vref, RX VrefLevel [Byte0]: 70

 1761 23:28:18.217211                           [Byte1]: 70

 1762 23:28:18.221918  

 1763 23:28:18.222357  Set Vref, RX VrefLevel [Byte0]: 71

 1764 23:28:18.224960                           [Byte1]: 71

 1765 23:28:18.229148  

 1766 23:28:18.229653  Set Vref, RX VrefLevel [Byte0]: 72

 1767 23:28:18.232424                           [Byte1]: 72

 1768 23:28:18.236673  

 1769 23:28:18.237087  Set Vref, RX VrefLevel [Byte0]: 73

 1770 23:28:18.239638                           [Byte1]: 73

 1771 23:28:18.243861  

 1772 23:28:18.244452  Set Vref, RX VrefLevel [Byte0]: 74

 1773 23:28:18.247072                           [Byte1]: 74

 1774 23:28:18.251269  

 1775 23:28:18.251681  Final RX Vref Byte 0 = 55 to rank0

 1776 23:28:18.254702  Final RX Vref Byte 1 = 55 to rank0

 1777 23:28:18.258262  Final RX Vref Byte 0 = 55 to rank1

 1778 23:28:18.261257  Final RX Vref Byte 1 = 55 to rank1==

 1779 23:28:18.264691  Dram Type= 6, Freq= 0, CH_1, rank 0

 1780 23:28:18.271821  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1781 23:28:18.272469  ==

 1782 23:28:18.272813  DQS Delay:

 1783 23:28:18.273122  DQS0 = 0, DQS1 = 0

 1784 23:28:18.274718  DQM Delay:

 1785 23:28:18.275129  DQM0 = 94, DQM1 = 90

 1786 23:28:18.278120  DQ Delay:

 1787 23:28:18.281543  DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88

 1788 23:28:18.284768  DQ4 =92, DQ5 =108, DQ6 =104, DQ7 =92

 1789 23:28:18.288232  DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84

 1790 23:28:18.291533  DQ12 =96, DQ13 =100, DQ14 =96, DQ15 =96

 1791 23:28:18.292060  

 1792 23:28:18.292395  

 1793 23:28:18.298231  [DQSOSCAuto] RK0, (LSB)MR18= 0x2c48, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps

 1794 23:28:18.301387  CH1 RK0: MR19=606, MR18=2C48

 1795 23:28:18.307967  CH1_RK0: MR19=0x606, MR18=0x2C48, DQSOSC=391, MR23=63, INC=96, DEC=64

 1796 23:28:18.308623  

 1797 23:28:18.311297  ----->DramcWriteLeveling(PI) begin...

 1798 23:28:18.311804  ==

 1799 23:28:18.314789  Dram Type= 6, Freq= 0, CH_1, rank 1

 1800 23:28:18.318127  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1801 23:28:18.318650  ==

 1802 23:28:18.321324  Write leveling (Byte 0): 26 => 26

 1803 23:28:18.324715  Write leveling (Byte 1): 26 => 26

 1804 23:28:18.327939  DramcWriteLeveling(PI) end<-----

 1805 23:28:18.328356  

 1806 23:28:18.328681  ==

 1807 23:28:18.331413  Dram Type= 6, Freq= 0, CH_1, rank 1

 1808 23:28:18.334717  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1809 23:28:18.335137  ==

 1810 23:28:18.338268  [Gating] SW mode calibration

 1811 23:28:18.344950  [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 1812 23:28:18.351567  RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)

 1813 23:28:18.354929   0  6  0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)

 1814 23:28:18.358188   0  6  4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)

 1815 23:28:18.365561   0  6  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1816 23:28:18.369019   0  6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1817 23:28:18.372311   0  6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1818 23:28:18.378067   0  6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1819 23:28:18.381393   0  6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1820 23:28:18.385205   0  6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1821 23:28:18.391773   0  7  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1822 23:28:18.394918   0  7  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1823 23:28:18.398050   0  7  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1824 23:28:18.404900   0  7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1825 23:28:18.408075   0  7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1826 23:28:18.412238   0  7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1827 23:28:18.415715   0  7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1828 23:28:18.422214   0  7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1829 23:28:18.425043   0  8  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1830 23:28:18.428805   0  8  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 1831 23:28:18.434981   0  8  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1832 23:28:18.438312   0  8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1833 23:28:18.441947   0  8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1834 23:28:18.448839   0  8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1835 23:28:18.451830   0  8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1836 23:28:18.455197   0  8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1837 23:28:18.461893   0  9  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1838 23:28:18.465224   0  9  4 | B1->B0 | 2828 2323 | 1 0 | (1 1) (0 0)

 1839 23:28:18.468753   0  9  8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 1840 23:28:18.475181   0  9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1841 23:28:18.478433   0  9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1842 23:28:18.481757   0  9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1843 23:28:18.488734   0  9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 1844 23:28:18.491742   0  9 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 1845 23:28:18.495496   0 10  0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)

 1846 23:28:18.498417   0 10  4 | B1->B0 | 2929 3030 | 0 0 | (0 0) (0 1)

 1847 23:28:18.505173   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1848 23:28:18.508488   0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1849 23:28:18.511916   0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1850 23:28:18.518286   0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1851 23:28:18.522008   0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1852 23:28:18.525233   0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 1853 23:28:18.532291   0 11  0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)

 1854 23:28:18.535179   0 11  4 | B1->B0 | 3636 2b2b | 0 0 | (0 0) (0 0)

 1855 23:28:18.538485   0 11  8 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)

 1856 23:28:18.545227   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1857 23:28:18.548683   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1858 23:28:18.551528   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1859 23:28:18.558235   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1860 23:28:18.561629   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1861 23:28:18.565338   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1862 23:28:18.571599   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 1863 23:28:18.575456   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1864 23:28:18.578983   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1865 23:28:18.582180   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1866 23:28:18.588326   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1867 23:28:18.592208   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1868 23:28:18.595401   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1869 23:28:18.602247   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1870 23:28:18.605463   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1871 23:28:18.609078   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1872 23:28:18.615487   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1873 23:28:18.619293   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1874 23:28:18.622155   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1875 23:28:18.628722   0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1876 23:28:18.632296   0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1877 23:28:18.635366   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 1878 23:28:18.642188   0 14  4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 1879 23:28:18.645487   0 14  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 1880 23:28:18.648928  Total UI for P1: 0, mck2ui 16

 1881 23:28:18.652194  best dqsien dly found for B0: ( 0, 14,  4)

 1882 23:28:18.655725  Total UI for P1: 0, mck2ui 16

 1883 23:28:18.658857  best dqsien dly found for B1: ( 0, 14,  4)

 1884 23:28:18.662431  best DQS0 dly(MCK, UI, PI) = (0, 14, 4)

 1885 23:28:18.665728  best DQS1 dly(MCK, UI, PI) = (0, 14, 4)

 1886 23:28:18.666211  

 1887 23:28:18.669022  best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1888 23:28:18.672239  best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)

 1889 23:28:18.675677  [Gating] SW calibration Done

 1890 23:28:18.676139  ==

 1891 23:28:18.679097  Dram Type= 6, Freq= 0, CH_1, rank 1

 1892 23:28:18.682177  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1893 23:28:18.682598  ==

 1894 23:28:18.685644  RX Vref Scan: 0

 1895 23:28:18.686063  

 1896 23:28:18.686391  RX Vref 0 -> 0, step: 1

 1897 23:28:18.688595  

 1898 23:28:18.689009  RX Delay -130 -> 252, step: 16

 1899 23:28:18.695415  iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224

 1900 23:28:18.699131  iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208

 1901 23:28:18.702200  iDelay=222, Bit 2, Center 85 (-18 ~ 189) 208

 1902 23:28:18.705434  iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208

 1903 23:28:18.709288  iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208

 1904 23:28:18.711995  iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224

 1905 23:28:18.718697  iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208

 1906 23:28:18.722387  iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224

 1907 23:28:18.725653  iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224

 1908 23:28:18.728939  iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224

 1909 23:28:18.732388  iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224

 1910 23:28:18.738945  iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208

 1911 23:28:18.742343  iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224

 1912 23:28:18.745656  iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224

 1913 23:28:18.749001  iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224

 1914 23:28:18.752420  iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224

 1915 23:28:18.755998  ==

 1916 23:28:18.756416  Dram Type= 6, Freq= 0, CH_1, rank 1

 1917 23:28:18.762593  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1918 23:28:18.763013  ==

 1919 23:28:18.763345  DQS Delay:

 1920 23:28:18.765656  DQS0 = 0, DQS1 = 0

 1921 23:28:18.766073  DQM Delay:

 1922 23:28:18.768900  DQM0 = 92, DQM1 = 88

 1923 23:28:18.769314  DQ Delay:

 1924 23:28:18.772283  DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85

 1925 23:28:18.775944  DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93

 1926 23:28:18.779104  DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85

 1927 23:28:18.782606  DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93

 1928 23:28:18.783245  

 1929 23:28:18.783757  

 1930 23:28:18.784374  ==

 1931 23:28:18.785967  Dram Type= 6, Freq= 0, CH_1, rank 1

 1932 23:28:18.788944  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1933 23:28:18.789676  ==

 1934 23:28:18.790244  

 1935 23:28:18.790732  

 1936 23:28:18.792288  	TX Vref Scan disable

 1937 23:28:18.795653   == TX Byte 0 ==

 1938 23:28:18.799004  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1939 23:28:18.802336  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1940 23:28:18.805872   == TX Byte 1 ==

 1941 23:28:18.809018  Update DQ  dly =576 (2 ,1, 32)  DQ  OEN =(1 ,6)

 1942 23:28:18.812704  Update DQM dly =576 (2 ,1, 32)  DQM OEN =(1 ,6)

 1943 23:28:18.813123  ==

 1944 23:28:18.815931  Dram Type= 6, Freq= 0, CH_1, rank 1

 1945 23:28:18.819147  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1946 23:28:18.822370  ==

 1947 23:28:18.833518  TX Vref=22, minBit 1, minWin=26, winSum=435

 1948 23:28:18.837054  TX Vref=24, minBit 0, minWin=27, winSum=442

 1949 23:28:18.840233  TX Vref=26, minBit 1, minWin=27, winSum=442

 1950 23:28:18.843314  TX Vref=28, minBit 1, minWin=27, winSum=447

 1951 23:28:18.847406  TX Vref=30, minBit 2, minWin=27, winSum=446

 1952 23:28:18.850570  TX Vref=32, minBit 2, minWin=27, winSum=446

 1953 23:28:18.857429  [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28

 1954 23:28:18.857899  

 1955 23:28:18.860445  Final TX Range 1 Vref 28

 1956 23:28:18.860868  

 1957 23:28:18.861202  ==

 1958 23:28:18.863639  Dram Type= 6, Freq= 0, CH_1, rank 1

 1959 23:28:18.866913  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1960 23:28:18.867424  ==

 1961 23:28:18.868048  

 1962 23:28:18.868622  

 1963 23:28:18.870334  	TX Vref Scan disable

 1964 23:28:18.873713   == TX Byte 0 ==

 1965 23:28:18.877310  Update DQ  dly =578 (2 ,1, 34)  DQ  OEN =(1 ,6)

 1966 23:28:18.880653  Update DQM dly =578 (2 ,1, 34)  DQM OEN =(1 ,6)

 1967 23:28:18.883685   == TX Byte 1 ==

 1968 23:28:18.887168  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 1969 23:28:18.890478  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 1970 23:28:18.890898  

 1971 23:28:18.893647  [DATLAT]

 1972 23:28:18.894061  Freq=800, CH1 RK1

 1973 23:28:18.894396  

 1974 23:28:18.896986  DATLAT Default: 0xa

 1975 23:28:18.897400  0, 0xFFFF, sum = 0

 1976 23:28:18.900326  1, 0xFFFF, sum = 0

 1977 23:28:18.900748  2, 0xFFFF, sum = 0

 1978 23:28:18.903393  3, 0xFFFF, sum = 0

 1979 23:28:18.903816  4, 0xFFFF, sum = 0

 1980 23:28:18.906692  5, 0xFFFF, sum = 0

 1981 23:28:18.907242  6, 0xFFFF, sum = 0

 1982 23:28:18.910280  7, 0xFFFF, sum = 0

 1983 23:28:18.913406  8, 0xFFFF, sum = 0

 1984 23:28:18.913867  9, 0x0, sum = 1

 1985 23:28:18.914209  10, 0x0, sum = 2

 1986 23:28:18.916767  11, 0x0, sum = 3

 1987 23:28:18.917188  12, 0x0, sum = 4

 1988 23:28:18.920549  best_step = 10

 1989 23:28:18.920964  

 1990 23:28:18.921296  ==

 1991 23:28:18.923478  Dram Type= 6, Freq= 0, CH_1, rank 1

 1992 23:28:18.926926  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 1993 23:28:18.927345  ==

 1994 23:28:18.930567  RX Vref Scan: 0

 1995 23:28:18.930985  

 1996 23:28:18.931319  RX Vref 0 -> 0, step: 1

 1997 23:28:18.931634  

 1998 23:28:18.933565  RX Delay -79 -> 252, step: 8

 1999 23:28:18.940294  iDelay=209, Bit 0, Center 104 (9 ~ 200) 192

 2000 23:28:18.943512  iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200

 2001 23:28:18.947109  iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200

 2002 23:28:18.950298  iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200

 2003 23:28:18.953711  iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200

 2004 23:28:18.956800  iDelay=209, Bit 5, Center 112 (17 ~ 208) 192

 2005 23:28:18.963500  iDelay=209, Bit 6, Center 108 (9 ~ 208) 200

 2006 23:28:18.967274  iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208

 2007 23:28:18.970434  iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208

 2008 23:28:18.973857  iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208

 2009 23:28:18.977259  iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208

 2010 23:28:18.984100  iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208

 2011 23:28:18.987284  iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216

 2012 23:28:18.990749  iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208

 2013 23:28:18.993818  iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208

 2014 23:28:18.997335  iDelay=209, Bit 15, Center 100 (-7 ~ 208) 216

 2015 23:28:18.997797  ==

 2016 23:28:19.000499  Dram Type= 6, Freq= 0, CH_1, rank 1

 2017 23:28:19.007305  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2018 23:28:19.007722  ==

 2019 23:28:19.008058  DQS Delay:

 2020 23:28:19.008368  DQS0 = 0, DQS1 = 0

 2021 23:28:19.010671  DQM Delay:

 2022 23:28:19.011085  DQM0 = 97, DQM1 = 92

 2023 23:28:19.013834  DQ Delay:

 2024 23:28:19.017080  DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92

 2025 23:28:19.020720  DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96

 2026 23:28:19.024342  DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88

 2027 23:28:19.027146  DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =100

 2028 23:28:19.027735  

 2029 23:28:19.028237  

 2030 23:28:19.034189  [DQSOSCAuto] RK1, (LSB)MR18= 0x450f, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps

 2031 23:28:19.037096  CH1 RK1: MR19=606, MR18=450F

 2032 23:28:19.043927  CH1_RK1: MR19=0x606, MR18=0x450F, DQSOSC=392, MR23=63, INC=96, DEC=64

 2033 23:28:19.047217  [RxdqsGatingPostProcess] freq 800

 2034 23:28:19.050609  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 2035 23:28:19.054341  Pre-setting of DQS Precalculation

 2036 23:28:19.060741  [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10

 2037 23:28:19.067364  sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4

 2038 23:28:19.073920  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 2039 23:28:19.074343  

 2040 23:28:19.074672  

 2041 23:28:19.077492  [Calibration Summary] 1600 Mbps

 2042 23:28:19.077940  CH 0, Rank 0

 2043 23:28:19.080772  SW Impedance     : PASS

 2044 23:28:19.083945  DUTY Scan        : NO K

 2045 23:28:19.084363  ZQ Calibration   : PASS

 2046 23:28:19.087262  Jitter Meter     : NO K

 2047 23:28:19.090665  CBT Training     : PASS

 2048 23:28:19.091080  Write leveling   : PASS

 2049 23:28:19.094034  RX DQS gating    : PASS

 2050 23:28:19.094452  RX DQ/DQS(RDDQC) : PASS

 2051 23:28:19.098148  TX DQ/DQS        : PASS

 2052 23:28:19.100690  RX DATLAT        : PASS

 2053 23:28:19.101384  RX DQ/DQS(Engine): PASS

 2054 23:28:19.104001  TX OE            : NO K

 2055 23:28:19.104425  All Pass.

 2056 23:28:19.104900  

 2057 23:28:19.107519  CH 0, Rank 1

 2058 23:28:19.108057  SW Impedance     : PASS

 2059 23:28:19.110648  DUTY Scan        : NO K

 2060 23:28:19.114299  ZQ Calibration   : PASS

 2061 23:28:19.114854  Jitter Meter     : NO K

 2062 23:28:19.117418  CBT Training     : PASS

 2063 23:28:19.121178  Write leveling   : PASS

 2064 23:28:19.121903  RX DQS gating    : PASS

 2065 23:28:19.124149  RX DQ/DQS(RDDQC) : PASS

 2066 23:28:19.127437  TX DQ/DQS        : PASS

 2067 23:28:19.127861  RX DATLAT        : PASS

 2068 23:28:19.130607  RX DQ/DQS(Engine): PASS

 2069 23:28:19.134559  TX OE            : NO K

 2070 23:28:19.134980  All Pass.

 2071 23:28:19.135310  

 2072 23:28:19.135617  CH 1, Rank 0

 2073 23:28:19.137366  SW Impedance     : PASS

 2074 23:28:19.141197  DUTY Scan        : NO K

 2075 23:28:19.141766  ZQ Calibration   : PASS

 2076 23:28:19.144379  Jitter Meter     : NO K

 2077 23:28:19.144798  CBT Training     : PASS

 2078 23:28:19.147590  Write leveling   : PASS

 2079 23:28:19.150722  RX DQS gating    : PASS

 2080 23:28:19.151343  RX DQ/DQS(RDDQC) : PASS

 2081 23:28:19.154006  TX DQ/DQS        : PASS

 2082 23:28:19.157228  RX DATLAT        : PASS

 2083 23:28:19.157883  RX DQ/DQS(Engine): PASS

 2084 23:28:19.160486  TX OE            : NO K

 2085 23:28:19.160976  All Pass.

 2086 23:28:19.161542  

 2087 23:28:19.163851  CH 1, Rank 1

 2088 23:28:19.164445  SW Impedance     : PASS

 2089 23:28:19.167428  DUTY Scan        : NO K

 2090 23:28:19.170878  ZQ Calibration   : PASS

 2091 23:28:19.171313  Jitter Meter     : NO K

 2092 23:28:19.174244  CBT Training     : PASS

 2093 23:28:19.177484  Write leveling   : PASS

 2094 23:28:19.178023  RX DQS gating    : PASS

 2095 23:28:19.180579  RX DQ/DQS(RDDQC) : PASS

 2096 23:28:19.184128  TX DQ/DQS        : PASS

 2097 23:28:19.184570  RX DATLAT        : PASS

 2098 23:28:19.187757  RX DQ/DQS(Engine): PASS

 2099 23:28:19.188196  TX OE            : NO K

 2100 23:28:19.190611  All Pass.

 2101 23:28:19.191048  

 2102 23:28:19.191502  DramC Write-DBI off

 2103 23:28:19.194563  	PER_BANK_REFRESH: Hybrid Mode

 2104 23:28:19.198123  TX_TRACKING: ON

 2105 23:28:19.200721  [GetDramInforAfterCalByMRR] Vendor 6.

 2106 23:28:19.204001  [GetDramInforAfterCalByMRR] Revision 606.

 2107 23:28:19.207464  [GetDramInforAfterCalByMRR] Revision 2 0.

 2108 23:28:19.207902  MR0 0x3b3b

 2109 23:28:19.208345  MR8 0x5151

 2110 23:28:19.214354  RK0, DieNum 2, Density 16Gb, RKsize 32Gb.

 2111 23:28:19.214795  

 2112 23:28:19.215235  MR0 0x3b3b

 2113 23:28:19.215654  MR8 0x5151

 2114 23:28:19.217683  RK1, DieNum 2, Density 16Gb, RKsize 32Gb.

 2115 23:28:19.218137  

 2116 23:28:19.227703  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 2117 23:28:19.231117  [FAST_K] Save calibration result to emmc

 2118 23:28:19.234553  [FAST_K] Save calibration result to emmc

 2119 23:28:19.237279  dram_init: config_dvfs: 1

 2120 23:28:19.241187  dramc_set_vcore_voltage set vcore to 662500

 2121 23:28:19.244538  Read voltage for 1200, 2

 2122 23:28:19.244964  Vio18 = 0

 2123 23:28:19.245344  Vcore = 662500

 2124 23:28:19.247980  Vdram = 0

 2125 23:28:19.248404  Vddq = 0

 2126 23:28:19.248735  Vmddr = 0

 2127 23:28:19.254398  [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0

 2128 23:28:19.257402  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 2129 23:28:19.261103  MEM_TYPE=3, freq_sel=15

 2130 23:28:19.264217  sv_algorithm_assistance_LP4_1600 

 2131 23:28:19.267665  ============ PULL DRAM RESETB DOWN ============

 2132 23:28:19.270897  ========== PULL DRAM RESETB DOWN end =========

 2133 23:28:19.277723  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2134 23:28:19.280870  =================================== 

 2135 23:28:19.280953  LPDDR4 DRAM CONFIGURATION

 2136 23:28:19.283734  =================================== 

 2137 23:28:19.287316  EX_ROW_EN[0]    = 0x0

 2138 23:28:19.290659  EX_ROW_EN[1]    = 0x0

 2139 23:28:19.290742  LP4Y_EN      = 0x0

 2140 23:28:19.293878  WORK_FSP     = 0x0

 2141 23:28:19.293961  WL           = 0x4

 2142 23:28:19.297048  RL           = 0x4

 2143 23:28:19.297130  BL           = 0x2

 2144 23:28:19.300662  RPST         = 0x0

 2145 23:28:19.300745  RD_PRE       = 0x0

 2146 23:28:19.304265  WR_PRE       = 0x1

 2147 23:28:19.304348  WR_PST       = 0x0

 2148 23:28:19.307305  DBI_WR       = 0x0

 2149 23:28:19.307388  DBI_RD       = 0x0

 2150 23:28:19.310852  OTF          = 0x1

 2151 23:28:19.314090  =================================== 

 2152 23:28:19.317437  =================================== 

 2153 23:28:19.317545  ANA top config

 2154 23:28:19.320734  =================================== 

 2155 23:28:19.324132  DLL_ASYNC_EN            =  0

 2156 23:28:19.327654  ALL_SLAVE_EN            =  0

 2157 23:28:19.330485  NEW_RANK_MODE           =  1

 2158 23:28:19.330568  DLL_IDLE_MODE           =  1

 2159 23:28:19.334039  LP45_APHY_COMB_EN       =  1

 2160 23:28:19.337108  TX_ODT_DIS              =  1

 2161 23:28:19.340913  NEW_8X_MODE             =  1

 2162 23:28:19.344315  =================================== 

 2163 23:28:19.347128  =================================== 

 2164 23:28:19.347211  data_rate                  = 2400

 2165 23:28:19.350698  CKR                        = 1

 2166 23:28:19.354052  DQ_P2S_RATIO               = 8

 2167 23:28:19.357396  =================================== 

 2168 23:28:19.360874  CA_P2S_RATIO               = 8

 2169 23:28:19.364278  DQ_CA_OPEN                 = 0

 2170 23:28:19.367370  DQ_SEMI_OPEN               = 0

 2171 23:28:19.367453  CA_SEMI_OPEN               = 0

 2172 23:28:19.370611  CA_FULL_RATE               = 0

 2173 23:28:19.374057  DQ_CKDIV4_EN               = 0

 2174 23:28:19.377107  CA_CKDIV4_EN               = 0

 2175 23:28:19.380416  CA_PREDIV_EN               = 0

 2176 23:28:19.383875  PH8_DLY                    = 17

 2177 23:28:19.383958  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 2178 23:28:19.387273  DQ_AAMCK_DIV               = 4

 2179 23:28:19.390680  CA_AAMCK_DIV               = 4

 2180 23:28:19.393753  CA_ADMCK_DIV               = 4

 2181 23:28:19.397151  DQ_TRACK_CA_EN             = 0

 2182 23:28:19.400358  CA_PICK                    = 1200

 2183 23:28:19.404032  CA_MCKIO                   = 1200

 2184 23:28:19.404113  MCKIO_SEMI                 = 0

 2185 23:28:19.407248  PLL_FREQ                   = 2366

 2186 23:28:19.410670  DQ_UI_PI_RATIO             = 32

 2187 23:28:19.413994  CA_UI_PI_RATIO             = 0

 2188 23:28:19.417379  =================================== 

 2189 23:28:19.420855  =================================== 

 2190 23:28:19.424094  memory_type:LPDDR4         

 2191 23:28:19.424176  GP_NUM     : 10       

 2192 23:28:19.427692  SRAM_EN    : 1       

 2193 23:28:19.427774  MD32_EN    : 0       

 2194 23:28:19.431264  =================================== 

 2195 23:28:19.434525  [ANA_INIT] >>>>>>>>>>>>>> 

 2196 23:28:19.437952  <<<<<< [CONFIGURE PHASE]: ANA_TX

 2197 23:28:19.440794  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 2198 23:28:19.444093  =================================== 

 2199 23:28:19.447644  data_rate = 2400,PCW = 0X5b00

 2200 23:28:19.451012  =================================== 

 2201 23:28:19.454083  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 2202 23:28:19.461064  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2203 23:28:19.464569  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 2204 23:28:19.471023  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 2205 23:28:19.473866  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 2206 23:28:19.477398  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 2207 23:28:19.477479  [ANA_INIT] flow start 

 2208 23:28:19.480693  [ANA_INIT] PLL >>>>>>>> 

 2209 23:28:19.484446  [ANA_INIT] PLL <<<<<<<< 

 2210 23:28:19.484526  [ANA_INIT] MIDPI >>>>>>>> 

 2211 23:28:19.487680  [ANA_INIT] MIDPI <<<<<<<< 

 2212 23:28:19.490633  [ANA_INIT] DLL >>>>>>>> 

 2213 23:28:19.490714  [ANA_INIT] DLL <<<<<<<< 

 2214 23:28:19.494276  [ANA_INIT] flow end 

 2215 23:28:19.497723  ============ LP4 DIFF to SE enter ============

 2216 23:28:19.500806  ============ LP4 DIFF to SE exit  ============

 2217 23:28:19.504267  [ANA_INIT] <<<<<<<<<<<<< 

 2218 23:28:19.507650  [Flow] Enable top DCM control >>>>> 

 2219 23:28:19.510486  [Flow] Enable top DCM control <<<<< 

 2220 23:28:19.514472  Enable DLL master slave shuffle 

 2221 23:28:19.520617  ============================================================== 

 2222 23:28:19.520699  Gating Mode config

 2223 23:28:19.527217  ============================================================== 

 2224 23:28:19.527300  Config description: 

 2225 23:28:19.537478  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 2226 23:28:19.544111  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 2227 23:28:19.551426  SELPH_MODE            0: By rank         1: By Phase 

 2228 23:28:19.554350  ============================================================== 

 2229 23:28:19.557802  GAT_TRACK_EN                 =  1

 2230 23:28:19.561066  RX_GATING_MODE               =  2

 2231 23:28:19.564506  RX_GATING_TRACK_MODE         =  2

 2232 23:28:19.567858  SELPH_MODE                   =  1

 2233 23:28:19.571303  PICG_EARLY_EN                =  1

 2234 23:28:19.574688  VALID_LAT_VALUE              =  1

 2235 23:28:19.577596  ============================================================== 

 2236 23:28:19.581198  Enter into Gating configuration >>>> 

 2237 23:28:19.584480  Exit from Gating configuration <<<< 

 2238 23:28:19.587431  Enter into  DVFS_PRE_config >>>>> 

 2239 23:28:19.601101  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 2240 23:28:19.604494  Exit from  DVFS_PRE_config <<<<< 

 2241 23:28:19.604579  Enter into PICG configuration >>>> 

 2242 23:28:19.607544  Exit from PICG configuration <<<< 

 2243 23:28:19.611402  [RX_INPUT] configuration >>>>> 

 2244 23:28:19.614599  [RX_INPUT] configuration <<<<< 

 2245 23:28:19.621320  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 2246 23:28:19.624673  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 2247 23:28:19.631247  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 2248 23:28:19.637899  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 2249 23:28:19.644485  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 2250 23:28:19.651241  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 2251 23:28:19.654505  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 2252 23:28:19.657749  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 2253 23:28:19.661350  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 2254 23:28:19.667796  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 2255 23:28:19.671214  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 2256 23:28:19.674777  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2257 23:28:19.677782  =================================== 

 2258 23:28:19.681352  LPDDR4 DRAM CONFIGURATION

 2259 23:28:19.684381  =================================== 

 2260 23:28:19.684467  EX_ROW_EN[0]    = 0x0

 2261 23:28:19.688341  EX_ROW_EN[1]    = 0x0

 2262 23:28:19.688426  LP4Y_EN      = 0x0

 2263 23:28:19.691342  WORK_FSP     = 0x0

 2264 23:28:19.694432  WL           = 0x4

 2265 23:28:19.694516  RL           = 0x4

 2266 23:28:19.697805  BL           = 0x2

 2267 23:28:19.697890  RPST         = 0x0

 2268 23:28:19.701263  RD_PRE       = 0x0

 2269 23:28:19.701347  WR_PRE       = 0x1

 2270 23:28:19.704718  WR_PST       = 0x0

 2271 23:28:19.704802  DBI_WR       = 0x0

 2272 23:28:19.708181  DBI_RD       = 0x0

 2273 23:28:19.708266  OTF          = 0x1

 2274 23:28:19.711265  =================================== 

 2275 23:28:19.714963  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 2276 23:28:19.721891  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 2277 23:28:19.724810  [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4

 2278 23:28:19.727693  =================================== 

 2279 23:28:19.731367  LPDDR4 DRAM CONFIGURATION

 2280 23:28:19.734456  =================================== 

 2281 23:28:19.734541  EX_ROW_EN[0]    = 0x10

 2282 23:28:19.738194  EX_ROW_EN[1]    = 0x0

 2283 23:28:19.738279  LP4Y_EN      = 0x0

 2284 23:28:19.741334  WORK_FSP     = 0x0

 2285 23:28:19.741419  WL           = 0x4

 2286 23:28:19.744380  RL           = 0x4

 2287 23:28:19.744465  BL           = 0x2

 2288 23:28:19.748069  RPST         = 0x0

 2289 23:28:19.748154  RD_PRE       = 0x0

 2290 23:28:19.751726  WR_PRE       = 0x1

 2291 23:28:19.751811  WR_PST       = 0x0

 2292 23:28:19.754464  DBI_WR       = 0x0

 2293 23:28:19.757897  DBI_RD       = 0x0

 2294 23:28:19.757981  OTF          = 0x1

 2295 23:28:19.761359  =================================== 

 2296 23:28:19.768013  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 2297 23:28:19.768095  ==

 2298 23:28:19.770935  Dram Type= 6, Freq= 0, CH_0, rank 0

 2299 23:28:19.774610  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2300 23:28:19.774692  ==

 2301 23:28:19.777627  [Duty_Offset_Calibration]

 2302 23:28:19.777708  	B0:2	B1:1	CA:1

 2303 23:28:19.777773  

 2304 23:28:19.781088  [DutyScan_Calibration_Flow] k_type=0

 2305 23:28:19.791789  

 2306 23:28:19.791870  ==CLK 0==

 2307 23:28:19.795356  Final CLK duty delay cell = 0

 2308 23:28:19.799007  [0] MAX Duty = 5187%(X100), DQS PI = 24

 2309 23:28:19.802093  [0] MIN Duty = 4844%(X100), DQS PI = 48

 2310 23:28:19.805241  [0] AVG Duty = 5015%(X100)

 2311 23:28:19.805323  

 2312 23:28:19.808564  CH0 CLK Duty spec in!! Max-Min= 343%

 2313 23:28:19.812002  [DutyScan_Calibration_Flow] ====Done====

 2314 23:28:19.812084  

 2315 23:28:19.815325  [DutyScan_Calibration_Flow] k_type=1

 2316 23:28:19.830689  

 2317 23:28:19.830771  ==DQS 0 ==

 2318 23:28:19.834041  Final DQS duty delay cell = -4

 2319 23:28:19.837141  [-4] MAX Duty = 5124%(X100), DQS PI = 24

 2320 23:28:19.840687  [-4] MIN Duty = 4782%(X100), DQS PI = 0

 2321 23:28:19.844313  [-4] AVG Duty = 4953%(X100)

 2322 23:28:19.844394  

 2323 23:28:19.844458  ==DQS 1 ==

 2324 23:28:19.847646  Final DQS duty delay cell = 0

 2325 23:28:19.850487  [0] MAX Duty = 5156%(X100), DQS PI = 14

 2326 23:28:19.854502  [0] MIN Duty = 5000%(X100), DQS PI = 36

 2327 23:28:19.857309  [0] AVG Duty = 5078%(X100)

 2328 23:28:19.857390  

 2329 23:28:19.860652  CH0 DQS 0 Duty spec in!! Max-Min= 342%

 2330 23:28:19.860733  

 2331 23:28:19.864079  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 2332 23:28:19.867384  [DutyScan_Calibration_Flow] ====Done====

 2333 23:28:19.867465  

 2334 23:28:19.870702  [DutyScan_Calibration_Flow] k_type=3

 2335 23:28:19.887442  

 2336 23:28:19.887525  ==DQM 0 ==

 2337 23:28:19.890583  Final DQM duty delay cell = 0

 2338 23:28:19.894508  [0] MAX Duty = 5156%(X100), DQS PI = 30

 2339 23:28:19.897585  [0] MIN Duty = 4875%(X100), DQS PI = 58

 2340 23:28:19.897667  [0] AVG Duty = 5015%(X100)

 2341 23:28:19.900746  

 2342 23:28:19.900827  ==DQM 1 ==

 2343 23:28:19.904056  Final DQM duty delay cell = 0

 2344 23:28:19.907485  [0] MAX Duty = 5124%(X100), DQS PI = 8

 2345 23:28:19.910862  [0] MIN Duty = 5031%(X100), DQS PI = 16

 2346 23:28:19.910971  [0] AVG Duty = 5077%(X100)

 2347 23:28:19.911074  

 2348 23:28:19.914404  CH0 DQM 0 Duty spec in!! Max-Min= 281%

 2349 23:28:19.917779  

 2350 23:28:19.921248  CH0 DQM 1 Duty spec in!! Max-Min= 93%

 2351 23:28:19.924876  [DutyScan_Calibration_Flow] ====Done====

 2352 23:28:19.924960  

 2353 23:28:19.927414  [DutyScan_Calibration_Flow] k_type=2

 2354 23:28:19.943810  

 2355 23:28:19.943894  ==DQ 0 ==

 2356 23:28:19.947185  Final DQ duty delay cell = 0

 2357 23:28:19.950498  [0] MAX Duty = 5031%(X100), DQS PI = 24

 2358 23:28:19.953853  [0] MIN Duty = 4875%(X100), DQS PI = 62

 2359 23:28:19.953939  [0] AVG Duty = 4953%(X100)

 2360 23:28:19.954024  

 2361 23:28:19.957602  ==DQ 1 ==

 2362 23:28:19.960627  Final DQ duty delay cell = 0

 2363 23:28:19.963851  [0] MAX Duty = 5093%(X100), DQS PI = 10

 2364 23:28:19.967216  [0] MIN Duty = 4907%(X100), DQS PI = 36

 2365 23:28:19.967299  [0] AVG Duty = 5000%(X100)

 2366 23:28:19.967435  

 2367 23:28:19.970576  CH0 DQ 0 Duty spec in!! Max-Min= 156%

 2368 23:28:19.970658  

 2369 23:28:19.977468  CH0 DQ 1 Duty spec in!! Max-Min= 186%

 2370 23:28:19.980336  [DutyScan_Calibration_Flow] ====Done====

 2371 23:28:19.980418  ==

 2372 23:28:19.983798  Dram Type= 6, Freq= 0, CH_1, rank 0

 2373 23:28:19.986780  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2374 23:28:19.986862  ==

 2375 23:28:19.990546  [Duty_Offset_Calibration]

 2376 23:28:19.990654  	B0:1	B1:0	CA:0

 2377 23:28:19.990747  

 2378 23:28:19.993324  [DutyScan_Calibration_Flow] k_type=0

 2379 23:28:20.003253  

 2380 23:28:20.003335  ==CLK 0==

 2381 23:28:20.006286  Final CLK duty delay cell = -4

 2382 23:28:20.010034  [-4] MAX Duty = 5031%(X100), DQS PI = 24

 2383 23:28:20.013148  [-4] MIN Duty = 4875%(X100), DQS PI = 50

 2384 23:28:20.016719  [-4] AVG Duty = 4953%(X100)

 2385 23:28:20.016801  

 2386 23:28:20.019703  CH1 CLK Duty spec in!! Max-Min= 156%

 2387 23:28:20.023248  [DutyScan_Calibration_Flow] ====Done====

 2388 23:28:20.023330  

 2389 23:28:20.026630  [DutyScan_Calibration_Flow] k_type=1

 2390 23:28:20.042786  

 2391 23:28:20.042868  ==DQS 0 ==

 2392 23:28:20.045896  Final DQS duty delay cell = 0

 2393 23:28:20.049531  [0] MAX Duty = 5094%(X100), DQS PI = 24

 2394 23:28:20.053034  [0] MIN Duty = 4844%(X100), DQS PI = 0

 2395 23:28:20.053117  [0] AVG Duty = 4969%(X100)

 2396 23:28:20.056051  

 2397 23:28:20.056158  ==DQS 1 ==

 2398 23:28:20.059474  Final DQS duty delay cell = 0

 2399 23:28:20.062686  [0] MAX Duty = 5156%(X100), DQS PI = 18

 2400 23:28:20.065879  [0] MIN Duty = 4969%(X100), DQS PI = 8

 2401 23:28:20.065960  [0] AVG Duty = 5062%(X100)

 2402 23:28:20.069405  

 2403 23:28:20.072701  CH1 DQS 0 Duty spec in!! Max-Min= 250%

 2404 23:28:20.072782  

 2405 23:28:20.076465  CH1 DQS 1 Duty spec in!! Max-Min= 187%

 2406 23:28:20.079506  [DutyScan_Calibration_Flow] ====Done====

 2407 23:28:20.079588  

 2408 23:28:20.082567  [DutyScan_Calibration_Flow] k_type=3

 2409 23:28:20.099265  

 2410 23:28:20.099346  ==DQM 0 ==

 2411 23:28:20.102492  Final DQM duty delay cell = 0

 2412 23:28:20.105981  [0] MAX Duty = 5156%(X100), DQS PI = 6

 2413 23:28:20.109065  [0] MIN Duty = 5031%(X100), DQS PI = 0

 2414 23:28:20.109154  [0] AVG Duty = 5093%(X100)

 2415 23:28:20.112512  

 2416 23:28:20.112593  ==DQM 1 ==

 2417 23:28:20.115790  Final DQM duty delay cell = 0

 2418 23:28:20.119458  [0] MAX Duty = 5031%(X100), DQS PI = 24

 2419 23:28:20.122444  [0] MIN Duty = 4907%(X100), DQS PI = 34

 2420 23:28:20.122525  [0] AVG Duty = 4969%(X100)

 2421 23:28:20.125879  

 2422 23:28:20.129524  CH1 DQM 0 Duty spec in!! Max-Min= 125%

 2423 23:28:20.129633  

 2424 23:28:20.132734  CH1 DQM 1 Duty spec in!! Max-Min= 124%

 2425 23:28:20.135956  [DutyScan_Calibration_Flow] ====Done====

 2426 23:28:20.136037  

 2427 23:28:20.139282  [DutyScan_Calibration_Flow] k_type=2

 2428 23:28:20.154972  

 2429 23:28:20.155056  ==DQ 0 ==

 2430 23:28:20.158235  Final DQ duty delay cell = -4

 2431 23:28:20.161907  [-4] MAX Duty = 5094%(X100), DQS PI = 10

 2432 23:28:20.165299  [-4] MIN Duty = 4906%(X100), DQS PI = 44

 2433 23:28:20.168098  [-4] AVG Duty = 5000%(X100)

 2434 23:28:20.168179  

 2435 23:28:20.168243  ==DQ 1 ==

 2436 23:28:20.171501  Final DQ duty delay cell = 0

 2437 23:28:20.175283  [0] MAX Duty = 5125%(X100), DQS PI = 20

 2438 23:28:20.178089  [0] MIN Duty = 4969%(X100), DQS PI = 12

 2439 23:28:20.178170  [0] AVG Duty = 5047%(X100)

 2440 23:28:20.181682  

 2441 23:28:20.184779  CH1 DQ 0 Duty spec in!! Max-Min= 188%

 2442 23:28:20.184860  

 2443 23:28:20.188384  CH1 DQ 1 Duty spec in!! Max-Min= 156%

 2444 23:28:20.191686  [DutyScan_Calibration_Flow] ====Done====

 2445 23:28:20.194857  nWR fixed to 30

 2446 23:28:20.194939  [ModeRegInit_LP4] CH0 RK0

 2447 23:28:20.198226  [ModeRegInit_LP4] CH0 RK1

 2448 23:28:20.201677  [ModeRegInit_LP4] CH1 RK0

 2449 23:28:20.205354  [ModeRegInit_LP4] CH1 RK1

 2450 23:28:20.205435  match AC timing 7

 2451 23:28:20.208286  dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1

 2452 23:28:20.214956  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 2453 23:28:20.218299  [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12

 2454 23:28:20.221548  [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25

 2455 23:28:20.228367  [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)

 2456 23:28:20.228449  ==

 2457 23:28:20.231743  Dram Type= 6, Freq= 0, CH_0, rank 0

 2458 23:28:20.235062  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2459 23:28:20.235144  ==

 2460 23:28:20.241686  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2461 23:28:20.247981  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2462 23:28:20.255465  [CA 0] Center 39 (8~70) winsize 63

 2463 23:28:20.258563  [CA 1] Center 39 (8~70) winsize 63

 2464 23:28:20.261961  [CA 2] Center 35 (5~66) winsize 62

 2465 23:28:20.265512  [CA 3] Center 34 (4~65) winsize 62

 2466 23:28:20.268815  [CA 4] Center 33 (3~64) winsize 62

 2467 23:28:20.272085  [CA 5] Center 32 (3~62) winsize 60

 2468 23:28:20.272166  

 2469 23:28:20.275378  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 2470 23:28:20.275460  

 2471 23:28:20.278809  [CATrainingPosCal] consider 1 rank data

 2472 23:28:20.282100  u2DelayCellTimex100 = 270/100 ps

 2473 23:28:20.285398  CA0 delay=39 (8~70),Diff = 7 PI (33 cell)

 2474 23:28:20.288516  CA1 delay=39 (8~70),Diff = 7 PI (33 cell)

 2475 23:28:20.295257  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2476 23:28:20.298471  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2477 23:28:20.302324  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2478 23:28:20.305518  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2479 23:28:20.305668  

 2480 23:28:20.308828  CA PerBit enable=1, Macro0, CA PI delay=32

 2481 23:28:20.308909  

 2482 23:28:20.312269  [CBTSetCACLKResult] CA Dly = 32

 2483 23:28:20.312351  CS Dly: 6 (0~37)

 2484 23:28:20.312415  ==

 2485 23:28:20.315312  Dram Type= 6, Freq= 0, CH_0, rank 1

 2486 23:28:20.322202  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2487 23:28:20.322284  ==

 2488 23:28:20.325495  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 2489 23:28:20.332345  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 2490 23:28:20.341046  [CA 0] Center 38 (8~69) winsize 62

 2491 23:28:20.344303  [CA 1] Center 38 (8~69) winsize 62

 2492 23:28:20.347704  [CA 2] Center 35 (5~66) winsize 62

 2493 23:28:20.350904  [CA 3] Center 34 (4~65) winsize 62

 2494 23:28:20.354414  [CA 4] Center 33 (3~64) winsize 62

 2495 23:28:20.357729  [CA 5] Center 32 (3~62) winsize 60

 2496 23:28:20.357811  

 2497 23:28:20.360888  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 2498 23:28:20.360970  

 2499 23:28:20.364265  [CATrainingPosCal] consider 2 rank data

 2500 23:28:20.367905  u2DelayCellTimex100 = 270/100 ps

 2501 23:28:20.370741  CA0 delay=38 (8~69),Diff = 6 PI (28 cell)

 2502 23:28:20.374470  CA1 delay=38 (8~69),Diff = 6 PI (28 cell)

 2503 23:28:20.380776  CA2 delay=35 (5~66),Diff = 3 PI (14 cell)

 2504 23:28:20.384193  CA3 delay=34 (4~65),Diff = 2 PI (9 cell)

 2505 23:28:20.387562  CA4 delay=33 (3~64),Diff = 1 PI (4 cell)

 2506 23:28:20.390950  CA5 delay=32 (3~62),Diff = 0 PI (0 cell)

 2507 23:28:20.391032  

 2508 23:28:20.394362  CA PerBit enable=1, Macro0, CA PI delay=32

 2509 23:28:20.394444  

 2510 23:28:20.397743  [CBTSetCACLKResult] CA Dly = 32

 2511 23:28:20.397825  CS Dly: 6 (0~38)

 2512 23:28:20.397889  

 2513 23:28:20.400979  ----->DramcWriteLeveling(PI) begin...

 2514 23:28:20.404144  ==

 2515 23:28:20.404230  Dram Type= 6, Freq= 0, CH_0, rank 0

 2516 23:28:20.410907  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2517 23:28:20.411000  ==

 2518 23:28:20.414146  Write leveling (Byte 0): 34 => 34

 2519 23:28:20.417854  Write leveling (Byte 1): 29 => 29

 2520 23:28:20.421042  DramcWriteLeveling(PI) end<-----

 2521 23:28:20.421140  

 2522 23:28:20.421234  ==

 2523 23:28:20.424542  Dram Type= 6, Freq= 0, CH_0, rank 0

 2524 23:28:20.427818  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2525 23:28:20.427929  ==

 2526 23:28:20.431340  [Gating] SW mode calibration

 2527 23:28:20.437832  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2528 23:28:20.441075  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2529 23:28:20.447729   0 15  0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)

 2530 23:28:20.450903   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2531 23:28:20.454355   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2532 23:28:20.460950   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2533 23:28:20.464848   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2534 23:28:20.468147   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2535 23:28:20.474462   0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)

 2536 23:28:20.477801   0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)

 2537 23:28:20.481059   1  0  0 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)

 2538 23:28:20.487888   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2539 23:28:20.491045   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2540 23:28:20.494449   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2541 23:28:20.501222   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2542 23:28:20.504810   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2543 23:28:20.507804   1  0 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)

 2544 23:28:20.511386   1  0 28 | B1->B0 | 2e2e 4646 | 0 0 | (1 1) (0 0)

 2545 23:28:20.517966   1  1  0 | B1->B0 | 3333 4545 | 0 0 | (0 0) (0 0)

 2546 23:28:20.521188   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2547 23:28:20.524253   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2548 23:28:20.531044   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2549 23:28:20.534526   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2550 23:28:20.538051   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2551 23:28:20.544536   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2552 23:28:20.547786   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 2553 23:28:20.551369   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2554 23:28:20.557956   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2555 23:28:20.561763   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2556 23:28:20.564934   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2557 23:28:20.571372   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2558 23:28:20.574562   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2559 23:28:20.578020   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2560 23:28:20.584619   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2561 23:28:20.588217   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2562 23:28:20.591117   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2563 23:28:20.594770   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2564 23:28:20.601330   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2565 23:28:20.604781   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2566 23:28:20.608166   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2567 23:28:20.614636   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 2568 23:28:20.617803   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2569 23:28:20.621115   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 2570 23:28:20.624457  Total UI for P1: 0, mck2ui 16

 2571 23:28:20.628268  best dqsien dly found for B0: ( 1,  3, 26)

 2572 23:28:20.634778   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2573 23:28:20.634862  Total UI for P1: 0, mck2ui 16

 2574 23:28:20.641129  best dqsien dly found for B1: ( 1,  3, 30)

 2575 23:28:20.644316  best DQS0 dly(MCK, UI, PI) = (1, 3, 26)

 2576 23:28:20.647782  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2577 23:28:20.647864  

 2578 23:28:20.651445  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)

 2579 23:28:20.654759  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2580 23:28:20.657914  [Gating] SW calibration Done

 2581 23:28:20.657996  ==

 2582 23:28:20.661377  Dram Type= 6, Freq= 0, CH_0, rank 0

 2583 23:28:20.664419  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2584 23:28:20.664502  ==

 2585 23:28:20.667919  RX Vref Scan: 0

 2586 23:28:20.668001  

 2587 23:28:20.668066  RX Vref 0 -> 0, step: 1

 2588 23:28:20.668127  

 2589 23:28:20.671053  RX Delay -40 -> 252, step: 8

 2590 23:28:20.674356  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2591 23:28:20.681447  iDelay=200, Bit 1, Center 123 (48 ~ 199) 152

 2592 23:28:20.684413  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2593 23:28:20.687898  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2594 23:28:20.691082  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 2595 23:28:20.694709  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2596 23:28:20.701854  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2597 23:28:20.704839  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2598 23:28:20.708399  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2599 23:28:20.711865  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 2600 23:28:20.714864  iDelay=200, Bit 10, Center 111 (48 ~ 175) 128

 2601 23:28:20.718344  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2602 23:28:20.725131  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2603 23:28:20.728538  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2604 23:28:20.731678  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2605 23:28:20.734886  iDelay=200, Bit 15, Center 119 (48 ~ 191) 144

 2606 23:28:20.734971  ==

 2607 23:28:20.738039  Dram Type= 6, Freq= 0, CH_0, rank 0

 2608 23:28:20.744983  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2609 23:28:20.745069  ==

 2610 23:28:20.745154  DQS Delay:

 2611 23:28:20.748549  DQS0 = 0, DQS1 = 0

 2612 23:28:20.748634  DQM Delay:

 2613 23:28:20.751300  DQM0 = 121, DQM1 = 113

 2614 23:28:20.751385  DQ Delay:

 2615 23:28:20.754843  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2616 23:28:20.758355  DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127

 2617 23:28:20.761371  DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107

 2618 23:28:20.764886  DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =119

 2619 23:28:20.764972  

 2620 23:28:20.765056  

 2621 23:28:20.765137  ==

 2622 23:28:20.768135  Dram Type= 6, Freq= 0, CH_0, rank 0

 2623 23:28:20.771281  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2624 23:28:20.774815  ==

 2625 23:28:20.774899  

 2626 23:28:20.774985  

 2627 23:28:20.775066  	TX Vref Scan disable

 2628 23:28:20.778095   == TX Byte 0 ==

 2629 23:28:20.781376  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2630 23:28:20.784839  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2631 23:28:20.788172   == TX Byte 1 ==

 2632 23:28:20.791503  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2633 23:28:20.795019  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2634 23:28:20.795103  ==

 2635 23:28:20.798107  Dram Type= 6, Freq= 0, CH_0, rank 0

 2636 23:28:20.804678  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2637 23:28:20.804763  ==

 2638 23:28:20.816074  TX Vref=22, minBit 0, minWin=25, winSum=407

 2639 23:28:20.819412  TX Vref=24, minBit 0, minWin=25, winSum=410

 2640 23:28:20.822957  TX Vref=26, minBit 7, minWin=25, winSum=419

 2641 23:28:20.826098  TX Vref=28, minBit 10, minWin=25, winSum=421

 2642 23:28:20.829352  TX Vref=30, minBit 12, minWin=25, winSum=420

 2643 23:28:20.835856  TX Vref=32, minBit 0, minWin=26, winSum=424

 2644 23:28:20.839222  [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 32

 2645 23:28:20.839308  

 2646 23:28:20.842476  Final TX Range 1 Vref 32

 2647 23:28:20.842561  

 2648 23:28:20.842663  ==

 2649 23:28:20.846365  Dram Type= 6, Freq= 0, CH_0, rank 0

 2650 23:28:20.849079  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2651 23:28:20.852439  ==

 2652 23:28:20.852524  

 2653 23:28:20.852609  

 2654 23:28:20.852707  	TX Vref Scan disable

 2655 23:28:20.855929   == TX Byte 0 ==

 2656 23:28:20.859287  Update DQ  dly =852 (3 ,2, 20)  DQ  OEN =(2 ,7)

 2657 23:28:20.863144  Update DQM dly =852 (3 ,2, 20)  DQM OEN =(2 ,7)

 2658 23:28:20.865810   == TX Byte 1 ==

 2659 23:28:20.869321  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 2660 23:28:20.872462  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 2661 23:28:20.875886  

 2662 23:28:20.875970  [DATLAT]

 2663 23:28:20.876055  Freq=1200, CH0 RK0

 2664 23:28:20.876136  

 2665 23:28:20.879145  DATLAT Default: 0xd

 2666 23:28:20.879229  0, 0xFFFF, sum = 0

 2667 23:28:20.882533  1, 0xFFFF, sum = 0

 2668 23:28:20.882619  2, 0xFFFF, sum = 0

 2669 23:28:20.886063  3, 0xFFFF, sum = 0

 2670 23:28:20.886149  4, 0xFFFF, sum = 0

 2671 23:28:20.889403  5, 0xFFFF, sum = 0

 2672 23:28:20.892745  6, 0xFFFF, sum = 0

 2673 23:28:20.892831  7, 0xFFFF, sum = 0

 2674 23:28:20.896129  8, 0xFFFF, sum = 0

 2675 23:28:20.896215  9, 0xFFFF, sum = 0

 2676 23:28:20.899593  10, 0xFFFF, sum = 0

 2677 23:28:20.899679  11, 0xFFFF, sum = 0

 2678 23:28:20.902481  12, 0x0, sum = 1

 2679 23:28:20.902567  13, 0x0, sum = 2

 2680 23:28:20.905780  14, 0x0, sum = 3

 2681 23:28:20.905866  15, 0x0, sum = 4

 2682 23:28:20.905952  best_step = 13

 2683 23:28:20.906033  

 2684 23:28:20.909256  ==

 2685 23:28:20.912463  Dram Type= 6, Freq= 0, CH_0, rank 0

 2686 23:28:20.916295  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2687 23:28:20.916380  ==

 2688 23:28:20.916466  RX Vref Scan: 1

 2689 23:28:20.916548  

 2690 23:28:20.919366  Set Vref Range= 32 -> 127

 2691 23:28:20.919450  

 2692 23:28:20.922629  RX Vref 32 -> 127, step: 1

 2693 23:28:20.922714  

 2694 23:28:20.926048  RX Delay -13 -> 252, step: 4

 2695 23:28:20.926133  

 2696 23:28:20.929430  Set Vref, RX VrefLevel [Byte0]: 32

 2697 23:28:20.932498                           [Byte1]: 32

 2698 23:28:20.932583  

 2699 23:28:20.935752  Set Vref, RX VrefLevel [Byte0]: 33

 2700 23:28:20.939150                           [Byte1]: 33

 2701 23:28:20.939235  

 2702 23:28:20.942562  Set Vref, RX VrefLevel [Byte0]: 34

 2703 23:28:20.945964                           [Byte1]: 34

 2704 23:28:20.950365  

 2705 23:28:20.950450  Set Vref, RX VrefLevel [Byte0]: 35

 2706 23:28:20.953538                           [Byte1]: 35

 2707 23:28:20.958350  

 2708 23:28:20.958434  Set Vref, RX VrefLevel [Byte0]: 36

 2709 23:28:20.961782                           [Byte1]: 36

 2710 23:28:20.965858  

 2711 23:28:20.965943  Set Vref, RX VrefLevel [Byte0]: 37

 2712 23:28:20.969563                           [Byte1]: 37

 2713 23:28:20.974010  

 2714 23:28:20.974095  Set Vref, RX VrefLevel [Byte0]: 38

 2715 23:28:20.977329                           [Byte1]: 38

 2716 23:28:20.981770  

 2717 23:28:20.981882  Set Vref, RX VrefLevel [Byte0]: 39

 2718 23:28:20.985141                           [Byte1]: 39

 2719 23:28:20.989709  

 2720 23:28:20.989804  Set Vref, RX VrefLevel [Byte0]: 40

 2721 23:28:20.993209                           [Byte1]: 40

 2722 23:28:20.997767  

 2723 23:28:20.997852  Set Vref, RX VrefLevel [Byte0]: 41

 2724 23:28:21.001231                           [Byte1]: 41

 2725 23:28:21.005637  

 2726 23:28:21.005722  Set Vref, RX VrefLevel [Byte0]: 42

 2727 23:28:21.009261                           [Byte1]: 42

 2728 23:28:21.013189  

 2729 23:28:21.013273  Set Vref, RX VrefLevel [Byte0]: 43

 2730 23:28:21.016738                           [Byte1]: 43

 2731 23:28:21.021550  

 2732 23:28:21.021673  Set Vref, RX VrefLevel [Byte0]: 44

 2733 23:28:21.024368                           [Byte1]: 44

 2734 23:28:21.029268  

 2735 23:28:21.029352  Set Vref, RX VrefLevel [Byte0]: 45

 2736 23:28:21.032771                           [Byte1]: 45

 2737 23:28:21.037048  

 2738 23:28:21.037133  Set Vref, RX VrefLevel [Byte0]: 46

 2739 23:28:21.041205                           [Byte1]: 46

 2740 23:28:21.045383  

 2741 23:28:21.045468  Set Vref, RX VrefLevel [Byte0]: 47

 2742 23:28:21.048006                           [Byte1]: 47

 2743 23:28:21.052760  

 2744 23:28:21.052844  Set Vref, RX VrefLevel [Byte0]: 48

 2745 23:28:21.056450                           [Byte1]: 48

 2746 23:28:21.060527  

 2747 23:28:21.060611  Set Vref, RX VrefLevel [Byte0]: 49

 2748 23:28:21.063891                           [Byte1]: 49

 2749 23:28:21.068348  

 2750 23:28:21.068432  Set Vref, RX VrefLevel [Byte0]: 50

 2751 23:28:21.071715                           [Byte1]: 50

 2752 23:28:21.076368  

 2753 23:28:21.076453  Set Vref, RX VrefLevel [Byte0]: 51

 2754 23:28:21.080068                           [Byte1]: 51

 2755 23:28:21.084230  

 2756 23:28:21.084315  Set Vref, RX VrefLevel [Byte0]: 52

 2757 23:28:21.087726                           [Byte1]: 52

 2758 23:28:21.092146  

 2759 23:28:21.092230  Set Vref, RX VrefLevel [Byte0]: 53

 2760 23:28:21.095671                           [Byte1]: 53

 2761 23:28:21.100226  

 2762 23:28:21.100311  Set Vref, RX VrefLevel [Byte0]: 54

 2763 23:28:21.103534                           [Byte1]: 54

 2764 23:28:21.108037  

 2765 23:28:21.108121  Set Vref, RX VrefLevel [Byte0]: 55

 2766 23:28:21.111414                           [Byte1]: 55

 2767 23:28:21.115919  

 2768 23:28:21.116003  Set Vref, RX VrefLevel [Byte0]: 56

 2769 23:28:21.119127                           [Byte1]: 56

 2770 23:28:21.123810  

 2771 23:28:21.123894  Set Vref, RX VrefLevel [Byte0]: 57

 2772 23:28:21.127510                           [Byte1]: 57

 2773 23:28:21.131514  

 2774 23:28:21.131598  Set Vref, RX VrefLevel [Byte0]: 58

 2775 23:28:21.134923                           [Byte1]: 58

 2776 23:28:21.139439  

 2777 23:28:21.139523  Set Vref, RX VrefLevel [Byte0]: 59

 2778 23:28:21.142794                           [Byte1]: 59

 2779 23:28:21.147491  

 2780 23:28:21.147574  Set Vref, RX VrefLevel [Byte0]: 60

 2781 23:28:21.150753                           [Byte1]: 60

 2782 23:28:21.155720  

 2783 23:28:21.155804  Set Vref, RX VrefLevel [Byte0]: 61

 2784 23:28:21.158994                           [Byte1]: 61

 2785 23:28:21.163427  

 2786 23:28:21.163512  Set Vref, RX VrefLevel [Byte0]: 62

 2787 23:28:21.166284                           [Byte1]: 62

 2788 23:28:21.170946  

 2789 23:28:21.171030  Set Vref, RX VrefLevel [Byte0]: 63

 2790 23:28:21.174326                           [Byte1]: 63

 2791 23:28:21.179024  

 2792 23:28:21.179108  Set Vref, RX VrefLevel [Byte0]: 64

 2793 23:28:21.182289                           [Byte1]: 64

 2794 23:28:21.186718  

 2795 23:28:21.186812  Set Vref, RX VrefLevel [Byte0]: 65

 2796 23:28:21.190390                           [Byte1]: 65

 2797 23:28:21.194643  

 2798 23:28:21.194728  Set Vref, RX VrefLevel [Byte0]: 66

 2799 23:28:21.198212                           [Byte1]: 66

 2800 23:28:21.202471  

 2801 23:28:21.202636  Set Vref, RX VrefLevel [Byte0]: 67

 2802 23:28:21.205842                           [Byte1]: 67

 2803 23:28:21.210800  

 2804 23:28:21.210881  Set Vref, RX VrefLevel [Byte0]: 68

 2805 23:28:21.214017                           [Byte1]: 68

 2806 23:28:21.218589  

 2807 23:28:21.218670  Set Vref, RX VrefLevel [Byte0]: 69

 2808 23:28:21.222027                           [Byte1]: 69

 2809 23:28:21.226088  

 2810 23:28:21.226169  Final RX Vref Byte 0 = 57 to rank0

 2811 23:28:21.229587  Final RX Vref Byte 1 = 55 to rank0

 2812 23:28:21.232796  Final RX Vref Byte 0 = 57 to rank1

 2813 23:28:21.236512  Final RX Vref Byte 1 = 55 to rank1==

 2814 23:28:21.239411  Dram Type= 6, Freq= 0, CH_0, rank 0

 2815 23:28:21.246173  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2816 23:28:21.246256  ==

 2817 23:28:21.246321  DQS Delay:

 2818 23:28:21.246381  DQS0 = 0, DQS1 = 0

 2819 23:28:21.250028  DQM Delay:

 2820 23:28:21.250109  DQM0 = 120, DQM1 = 113

 2821 23:28:21.253124  DQ Delay:

 2822 23:28:21.256435  DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =118

 2823 23:28:21.259994  DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126

 2824 23:28:21.262850  DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106

 2825 23:28:21.266227  DQ12 =120, DQ13 =118, DQ14 =126, DQ15 =122

 2826 23:28:21.266308  

 2827 23:28:21.266411  

 2828 23:28:21.272818  [DQSOSCAuto] RK0, (LSB)MR18= 0x120b, (MSB)MR19= 0x404, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps

 2829 23:28:21.276343  CH0 RK0: MR19=404, MR18=120B

 2830 23:28:21.283117  CH0_RK0: MR19=0x404, MR18=0x120B, DQSOSC=403, MR23=63, INC=40, DEC=26

 2831 23:28:21.283199  

 2832 23:28:21.286480  ----->DramcWriteLeveling(PI) begin...

 2833 23:28:21.286563  ==

 2834 23:28:21.289594  Dram Type= 6, Freq= 0, CH_0, rank 1

 2835 23:28:21.292737  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2836 23:28:21.296324  ==

 2837 23:28:21.296406  Write leveling (Byte 0): 34 => 34

 2838 23:28:21.299724  Write leveling (Byte 1): 28 => 28

 2839 23:28:21.302928  DramcWriteLeveling(PI) end<-----

 2840 23:28:21.303009  

 2841 23:28:21.303074  ==

 2842 23:28:21.306858  Dram Type= 6, Freq= 0, CH_0, rank 1

 2843 23:28:21.313445  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2844 23:28:21.313527  ==

 2845 23:28:21.313630  [Gating] SW mode calibration

 2846 23:28:21.323495  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 2847 23:28:21.326805  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 2848 23:28:21.330458   0 15  0 | B1->B0 | 3333 3030 | 1 0 | (1 1) (0 0)

 2849 23:28:21.336635   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2850 23:28:21.340474   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2851 23:28:21.343558   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2852 23:28:21.350376   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2853 23:28:21.353564   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2854 23:28:21.356719   0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 2855 23:28:21.363701   0 15 28 | B1->B0 | 2f2f 2e2e | 0 0 | (1 0) (1 0)

 2856 23:28:21.367046   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 2857 23:28:21.370236   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2858 23:28:21.376852   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2859 23:28:21.380217   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2860 23:28:21.383339   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2861 23:28:21.390182   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 2862 23:28:21.393544   1  0 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)

 2863 23:28:21.397116   1  0 28 | B1->B0 | 3f3f 3a39 | 0 1 | (0 0) (0 0)

 2864 23:28:21.400255   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2865 23:28:21.406974   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2866 23:28:21.409968   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2867 23:28:21.413783   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2868 23:28:21.419953   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2869 23:28:21.423812   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2870 23:28:21.427005   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2871 23:28:21.433735   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 2872 23:28:21.436650   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 2873 23:28:21.440249   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2874 23:28:21.447233   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2875 23:28:21.449916   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2876 23:28:21.453244   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2877 23:28:21.460301   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2878 23:28:21.463506   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2879 23:28:21.466726   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2880 23:28:21.473331   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2881 23:28:21.476629   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2882 23:28:21.480560   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2883 23:28:21.486613   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2884 23:28:21.489982   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2885 23:28:21.493237   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2886 23:28:21.496805   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 2887 23:28:21.503640   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2888 23:28:21.507034   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 2889 23:28:21.510347   1  4  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 2890 23:28:21.513700  Total UI for P1: 0, mck2ui 16

 2891 23:28:21.516770  best dqsien dly found for B0: ( 1,  3, 30)

 2892 23:28:21.520240  Total UI for P1: 0, mck2ui 16

 2893 23:28:21.523597  best dqsien dly found for B1: ( 1,  3, 30)

 2894 23:28:21.527309  best DQS0 dly(MCK, UI, PI) = (1, 3, 30)

 2895 23:28:21.530840  best DQS1 dly(MCK, UI, PI) = (1, 3, 30)

 2896 23:28:21.530926  

 2897 23:28:21.536733  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2898 23:28:21.540309  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)

 2899 23:28:21.540394  [Gating] SW calibration Done

 2900 23:28:21.543354  ==

 2901 23:28:21.546959  Dram Type= 6, Freq= 0, CH_0, rank 1

 2902 23:28:21.550697  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2903 23:28:21.550811  ==

 2904 23:28:21.550897  RX Vref Scan: 0

 2905 23:28:21.550979  

 2906 23:28:21.554036  RX Vref 0 -> 0, step: 1

 2907 23:28:21.554145  

 2908 23:28:21.557165  RX Delay -40 -> 252, step: 8

 2909 23:28:21.560636  iDelay=200, Bit 0, Center 119 (48 ~ 191) 144

 2910 23:28:21.563707  iDelay=200, Bit 1, Center 123 (56 ~ 191) 136

 2911 23:28:21.567104  iDelay=200, Bit 2, Center 119 (48 ~ 191) 144

 2912 23:28:21.573963  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 2913 23:28:21.577194  iDelay=200, Bit 4, Center 127 (56 ~ 199) 144

 2914 23:28:21.580438  iDelay=200, Bit 5, Center 115 (48 ~ 183) 136

 2915 23:28:21.583538  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 2916 23:28:21.587192  iDelay=200, Bit 7, Center 127 (56 ~ 199) 144

 2917 23:28:21.593499  iDelay=200, Bit 8, Center 99 (32 ~ 167) 136

 2918 23:28:21.597365  iDelay=200, Bit 9, Center 99 (32 ~ 167) 136

 2919 23:28:21.600469  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 2920 23:28:21.603711  iDelay=200, Bit 11, Center 107 (40 ~ 175) 136

 2921 23:28:21.607334  iDelay=200, Bit 12, Center 115 (48 ~ 183) 136

 2922 23:28:21.610911  iDelay=200, Bit 13, Center 123 (56 ~ 191) 136

 2923 23:28:21.617325  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 2924 23:28:21.620825  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 2925 23:28:21.620910  ==

 2926 23:28:21.624304  Dram Type= 6, Freq= 0, CH_0, rank 1

 2927 23:28:21.627258  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2928 23:28:21.627344  ==

 2929 23:28:21.630985  DQS Delay:

 2930 23:28:21.631105  DQS0 = 0, DQS1 = 0

 2931 23:28:21.631191  DQM Delay:

 2932 23:28:21.634292  DQM0 = 122, DQM1 = 113

 2933 23:28:21.634392  DQ Delay:

 2934 23:28:21.637149  DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119

 2935 23:28:21.640886  DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127

 2936 23:28:21.643714  DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107

 2937 23:28:21.650790  DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123

 2938 23:28:21.650876  

 2939 23:28:21.650961  

 2940 23:28:21.651041  ==

 2941 23:28:21.654062  Dram Type= 6, Freq= 0, CH_0, rank 1

 2942 23:28:21.657147  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2943 23:28:21.657233  ==

 2944 23:28:21.657318  

 2945 23:28:21.657398  

 2946 23:28:21.660851  	TX Vref Scan disable

 2947 23:28:21.660936   == TX Byte 0 ==

 2948 23:28:21.667272  Update DQ  dly =854 (3 ,2, 22)  DQ  OEN =(2 ,7)

 2949 23:28:21.670614  Update DQM dly =854 (3 ,2, 22)  DQM OEN =(2 ,7)

 2950 23:28:21.670699   == TX Byte 1 ==

 2951 23:28:21.677157  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 2952 23:28:21.680474  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 2953 23:28:21.680559  ==

 2954 23:28:21.683817  Dram Type= 6, Freq= 0, CH_0, rank 1

 2955 23:28:21.687513  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2956 23:28:21.687599  ==

 2957 23:28:21.700460  TX Vref=22, minBit 1, minWin=24, winSum=409

 2958 23:28:21.703896  TX Vref=24, minBit 3, minWin=25, winSum=416

 2959 23:28:21.707054  TX Vref=26, minBit 3, minWin=25, winSum=418

 2960 23:28:21.710616  TX Vref=28, minBit 4, minWin=25, winSum=422

 2961 23:28:21.713724  TX Vref=30, minBit 5, minWin=26, winSum=428

 2962 23:28:21.717835  TX Vref=32, minBit 5, minWin=25, winSum=417

 2963 23:28:21.723578  [TxChooseVref] Worse bit 5, Min win 26, Win sum 428, Final Vref 30

 2964 23:28:21.723664  

 2965 23:28:21.727475  Final TX Range 1 Vref 30

 2966 23:28:21.727559  

 2967 23:28:21.727645  ==

 2968 23:28:21.730770  Dram Type= 6, Freq= 0, CH_0, rank 1

 2969 23:28:21.733853  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 2970 23:28:21.733938  ==

 2971 23:28:21.734023  

 2972 23:28:21.737440  

 2973 23:28:21.737551  	TX Vref Scan disable

 2974 23:28:21.740431   == TX Byte 0 ==

 2975 23:28:21.743702  Update DQ  dly =853 (3 ,2, 21)  DQ  OEN =(2 ,7)

 2976 23:28:21.747103  Update DQM dly =853 (3 ,2, 21)  DQM OEN =(2 ,7)

 2977 23:28:21.750736   == TX Byte 1 ==

 2978 23:28:21.753808  Update DQ  dly =843 (3 ,2, 11)  DQ  OEN =(2 ,7)

 2979 23:28:21.757308  Update DQM dly =843 (3 ,2, 11)  DQM OEN =(2 ,7)

 2980 23:28:21.757393  

 2981 23:28:21.760453  [DATLAT]

 2982 23:28:21.760537  Freq=1200, CH0 RK1

 2983 23:28:21.760623  

 2984 23:28:21.763832  DATLAT Default: 0xd

 2985 23:28:21.763916  0, 0xFFFF, sum = 0

 2986 23:28:21.767406  1, 0xFFFF, sum = 0

 2987 23:28:21.767492  2, 0xFFFF, sum = 0

 2988 23:28:21.770829  3, 0xFFFF, sum = 0

 2989 23:28:21.770915  4, 0xFFFF, sum = 0

 2990 23:28:21.774259  5, 0xFFFF, sum = 0

 2991 23:28:21.774345  6, 0xFFFF, sum = 0

 2992 23:28:21.777391  7, 0xFFFF, sum = 0

 2993 23:28:21.777478  8, 0xFFFF, sum = 0

 2994 23:28:21.780352  9, 0xFFFF, sum = 0

 2995 23:28:21.783779  10, 0xFFFF, sum = 0

 2996 23:28:21.783865  11, 0xFFFF, sum = 0

 2997 23:28:21.787566  12, 0x0, sum = 1

 2998 23:28:21.787653  13, 0x0, sum = 2

 2999 23:28:21.787741  14, 0x0, sum = 3

 3000 23:28:21.790813  15, 0x0, sum = 4

 3001 23:28:21.790899  best_step = 13

 3002 23:28:21.790984  

 3003 23:28:21.794179  ==

 3004 23:28:21.794263  Dram Type= 6, Freq= 0, CH_0, rank 1

 3005 23:28:21.800507  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3006 23:28:21.800624  ==

 3007 23:28:21.800690  RX Vref Scan: 0

 3008 23:28:21.800779  

 3009 23:28:21.803807  RX Vref 0 -> 0, step: 1

 3010 23:28:21.803890  

 3011 23:28:21.807126  RX Delay -13 -> 252, step: 4

 3012 23:28:21.810424  iDelay=195, Bit 0, Center 120 (51 ~ 190) 140

 3013 23:28:21.813886  iDelay=195, Bit 1, Center 120 (55 ~ 186) 132

 3014 23:28:21.820566  iDelay=195, Bit 2, Center 118 (51 ~ 186) 136

 3015 23:28:21.823743  iDelay=195, Bit 3, Center 118 (51 ~ 186) 136

 3016 23:28:21.827125  iDelay=195, Bit 4, Center 122 (55 ~ 190) 136

 3017 23:28:21.830510  iDelay=195, Bit 5, Center 116 (51 ~ 182) 132

 3018 23:28:21.833796  iDelay=195, Bit 6, Center 126 (59 ~ 194) 136

 3019 23:28:21.840365  iDelay=195, Bit 7, Center 126 (59 ~ 194) 136

 3020 23:28:21.843839  iDelay=195, Bit 8, Center 102 (35 ~ 170) 136

 3021 23:28:21.847347  iDelay=195, Bit 9, Center 100 (35 ~ 166) 132

 3022 23:28:21.850794  iDelay=195, Bit 10, Center 112 (47 ~ 178) 132

 3023 23:28:21.853712  iDelay=195, Bit 11, Center 104 (39 ~ 170) 132

 3024 23:28:21.860311  iDelay=195, Bit 12, Center 118 (55 ~ 182) 128

 3025 23:28:21.863753  iDelay=195, Bit 13, Center 118 (55 ~ 182) 128

 3026 23:28:21.867508  iDelay=195, Bit 14, Center 122 (59 ~ 186) 128

 3027 23:28:21.870638  iDelay=195, Bit 15, Center 118 (55 ~ 182) 128

 3028 23:28:21.870720  ==

 3029 23:28:21.873734  Dram Type= 6, Freq= 0, CH_0, rank 1

 3030 23:28:21.880425  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3031 23:28:21.880512  ==

 3032 23:28:21.880578  DQS Delay:

 3033 23:28:21.884126  DQS0 = 0, DQS1 = 0

 3034 23:28:21.884208  DQM Delay:

 3035 23:28:21.884272  DQM0 = 120, DQM1 = 111

 3036 23:28:21.887504  DQ Delay:

 3037 23:28:21.890744  DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118

 3038 23:28:21.893915  DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126

 3039 23:28:21.897299  DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104

 3040 23:28:21.900615  DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118

 3041 23:28:21.900696  

 3042 23:28:21.900760  

 3043 23:28:21.907431  [DQSOSCAuto] RK1, (LSB)MR18= 0xff0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 404 ps

 3044 23:28:21.910842  CH0 RK1: MR19=403, MR18=FF0

 3045 23:28:21.917262  CH0_RK1: MR19=0x403, MR18=0xFF0, DQSOSC=404, MR23=63, INC=40, DEC=26

 3046 23:28:21.920963  [RxdqsGatingPostProcess] freq 1200

 3047 23:28:21.927120  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3048 23:28:21.930585  best DQS0 dly(2T, 0.5T) = (0, 11)

 3049 23:28:21.930668  best DQS1 dly(2T, 0.5T) = (0, 11)

 3050 23:28:21.933830  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3051 23:28:21.937390  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3052 23:28:21.940778  best DQS0 dly(2T, 0.5T) = (0, 11)

 3053 23:28:21.943939  best DQS1 dly(2T, 0.5T) = (0, 11)

 3054 23:28:21.947207  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3055 23:28:21.950770  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3056 23:28:21.954251  Pre-setting of DQS Precalculation

 3057 23:28:21.961008  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3058 23:28:21.961090  ==

 3059 23:28:21.963806  Dram Type= 6, Freq= 0, CH_1, rank 0

 3060 23:28:21.967495  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3061 23:28:21.967578  ==

 3062 23:28:21.974244  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3063 23:28:21.977573  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3064 23:28:21.987142  [CA 0] Center 37 (7~68) winsize 62

 3065 23:28:21.990202  [CA 1] Center 37 (7~68) winsize 62

 3066 23:28:21.993507  [CA 2] Center 35 (5~65) winsize 61

 3067 23:28:21.996835  [CA 3] Center 34 (5~64) winsize 60

 3068 23:28:22.000611  [CA 4] Center 34 (5~64) winsize 60

 3069 23:28:22.003750  [CA 5] Center 33 (3~63) winsize 61

 3070 23:28:22.003833  

 3071 23:28:22.007162  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3072 23:28:22.007245  

 3073 23:28:22.010137  [CATrainingPosCal] consider 1 rank data

 3074 23:28:22.013564  u2DelayCellTimex100 = 270/100 ps

 3075 23:28:22.016946  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3076 23:28:22.020813  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3077 23:28:22.026907  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3078 23:28:22.030152  CA3 delay=34 (5~64),Diff = 1 PI (4 cell)

 3079 23:28:22.033602  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3080 23:28:22.037093  CA5 delay=33 (3~63),Diff = 0 PI (0 cell)

 3081 23:28:22.037175  

 3082 23:28:22.040259  CA PerBit enable=1, Macro0, CA PI delay=33

 3083 23:28:22.040341  

 3084 23:28:22.043383  [CBTSetCACLKResult] CA Dly = 33

 3085 23:28:22.043466  CS Dly: 8 (0~39)

 3086 23:28:22.043531  ==

 3087 23:28:22.046599  Dram Type= 6, Freq= 0, CH_1, rank 1

 3088 23:28:22.053634  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3089 23:28:22.053719  ==

 3090 23:28:22.057228  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3091 23:28:22.063602  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39

 3092 23:28:22.072432  [CA 0] Center 37 (7~68) winsize 62

 3093 23:28:22.075576  [CA 1] Center 37 (7~68) winsize 62

 3094 23:28:22.078975  [CA 2] Center 35 (5~65) winsize 61

 3095 23:28:22.082289  [CA 3] Center 34 (4~65) winsize 62

 3096 23:28:22.086363  [CA 4] Center 34 (4~65) winsize 62

 3097 23:28:22.089361  [CA 5] Center 34 (4~64) winsize 61

 3098 23:28:22.089449  

 3099 23:28:22.092310  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3100 23:28:22.092418  

 3101 23:28:22.095682  [CATrainingPosCal] consider 2 rank data

 3102 23:28:22.098860  u2DelayCellTimex100 = 270/100 ps

 3103 23:28:22.102339  CA0 delay=37 (7~68),Diff = 4 PI (19 cell)

 3104 23:28:22.105634  CA1 delay=37 (7~68),Diff = 4 PI (19 cell)

 3105 23:28:22.112804  CA2 delay=35 (5~65),Diff = 2 PI (9 cell)

 3106 23:28:22.115813  CA3 delay=34 (5~64),Diff = 1 PI (4 cell)

 3107 23:28:22.119223  CA4 delay=34 (5~64),Diff = 1 PI (4 cell)

 3108 23:28:22.122195  CA5 delay=33 (4~63),Diff = 0 PI (0 cell)

 3109 23:28:22.122278  

 3110 23:28:22.125528  CA PerBit enable=1, Macro0, CA PI delay=33

 3111 23:28:22.125693  

 3112 23:28:22.128988  [CBTSetCACLKResult] CA Dly = 33

 3113 23:28:22.129070  CS Dly: 8 (0~40)

 3114 23:28:22.129135  

 3115 23:28:22.132990  ----->DramcWriteLeveling(PI) begin...

 3116 23:28:22.135583  ==

 3117 23:28:22.139048  Dram Type= 6, Freq= 0, CH_1, rank 0

 3118 23:28:22.142730  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3119 23:28:22.142813  ==

 3120 23:28:22.145798  Write leveling (Byte 0): 28 => 28

 3121 23:28:22.149199  Write leveling (Byte 1): 28 => 28

 3122 23:28:22.152265  DramcWriteLeveling(PI) end<-----

 3123 23:28:22.152346  

 3124 23:28:22.152410  ==

 3125 23:28:22.155904  Dram Type= 6, Freq= 0, CH_1, rank 0

 3126 23:28:22.158938  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3127 23:28:22.159020  ==

 3128 23:28:22.162282  [Gating] SW mode calibration

 3129 23:28:22.168931  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3130 23:28:22.172763  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3131 23:28:22.179464   0 15  0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)

 3132 23:28:22.182842   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3133 23:28:22.185698   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3134 23:28:22.192794   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3135 23:28:22.196094   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3136 23:28:22.199503   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3137 23:28:22.206045   0 15 24 | B1->B0 | 3232 2c2c | 0 0 | (0 0) (0 0)

 3138 23:28:22.209283   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)

 3139 23:28:22.212403   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3140 23:28:22.219063   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3141 23:28:22.222866   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3142 23:28:22.226065   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3143 23:28:22.232883   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3144 23:28:22.235769   1  0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3145 23:28:22.239339   1  0 24 | B1->B0 | 3434 4343 | 1 0 | (1 1) (0 0)

 3146 23:28:22.245929   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3147 23:28:22.249712   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3148 23:28:22.253287   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3149 23:28:22.256487   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3150 23:28:22.262973   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3151 23:28:22.265932   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3152 23:28:22.269233   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3153 23:28:22.276018   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3154 23:28:22.279178   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3155 23:28:22.282611   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3156 23:28:22.289862   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3157 23:28:22.293258   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3158 23:28:22.296378   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3159 23:28:22.303208   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3160 23:28:22.305923   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3161 23:28:22.309223   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3162 23:28:22.316427   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3163 23:28:22.319284   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3164 23:28:22.322742   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3165 23:28:22.326171   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3166 23:28:22.332771   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3167 23:28:22.336030   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3168 23:28:22.339427   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3169 23:28:22.345862   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 3170 23:28:22.349746   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 3171 23:28:22.352736  Total UI for P1: 0, mck2ui 16

 3172 23:28:22.356132  best dqsien dly found for B0: ( 1,  3, 24)

 3173 23:28:22.359749   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3174 23:28:22.362745  Total UI for P1: 0, mck2ui 16

 3175 23:28:22.366613  best dqsien dly found for B1: ( 1,  3, 26)

 3176 23:28:22.369253  best DQS0 dly(MCK, UI, PI) = (1, 3, 24)

 3177 23:28:22.373202  best DQS1 dly(MCK, UI, PI) = (1, 3, 26)

 3178 23:28:22.373284  

 3179 23:28:22.379390  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)

 3180 23:28:22.382567  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)

 3181 23:28:22.382649  [Gating] SW calibration Done

 3182 23:28:22.385859  ==

 3183 23:28:22.389515  Dram Type= 6, Freq= 0, CH_1, rank 0

 3184 23:28:22.392827  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3185 23:28:22.392921  ==

 3186 23:28:22.393017  RX Vref Scan: 0

 3187 23:28:22.393078  

 3188 23:28:22.395870  RX Vref 0 -> 0, step: 1

 3189 23:28:22.395969  

 3190 23:28:22.399420  RX Delay -40 -> 252, step: 8

 3191 23:28:22.402555  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3192 23:28:22.406277  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3193 23:28:22.409511  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3194 23:28:22.415938  iDelay=200, Bit 3, Center 119 (48 ~ 191) 144

 3195 23:28:22.419331  iDelay=200, Bit 4, Center 119 (48 ~ 191) 144

 3196 23:28:22.422830  iDelay=200, Bit 5, Center 127 (56 ~ 199) 144

 3197 23:28:22.426095  iDelay=200, Bit 6, Center 127 (56 ~ 199) 144

 3198 23:28:22.429333  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3199 23:28:22.436301  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3200 23:28:22.439294  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3201 23:28:22.442540  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3202 23:28:22.446399  iDelay=200, Bit 11, Center 111 (48 ~ 175) 128

 3203 23:28:22.449469  iDelay=200, Bit 12, Center 123 (56 ~ 191) 136

 3204 23:28:22.456266  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3205 23:28:22.459266  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3206 23:28:22.462723  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3207 23:28:22.462807  ==

 3208 23:28:22.465873  Dram Type= 6, Freq= 0, CH_1, rank 0

 3209 23:28:22.469493  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3210 23:28:22.472861  ==

 3211 23:28:22.472945  DQS Delay:

 3212 23:28:22.473011  DQS0 = 0, DQS1 = 0

 3213 23:28:22.476174  DQM Delay:

 3214 23:28:22.476255  DQM0 = 120, DQM1 = 116

 3215 23:28:22.479619  DQ Delay:

 3216 23:28:22.482810  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3217 23:28:22.486059  DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123

 3218 23:28:22.489455  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111

 3219 23:28:22.492908  DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123

 3220 23:28:22.493036  

 3221 23:28:22.493154  

 3222 23:28:22.493217  ==

 3223 23:28:22.496313  Dram Type= 6, Freq= 0, CH_1, rank 0

 3224 23:28:22.499543  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3225 23:28:22.499626  ==

 3226 23:28:22.499690  

 3227 23:28:22.499792  

 3228 23:28:22.502834  	TX Vref Scan disable

 3229 23:28:22.506095   == TX Byte 0 ==

 3230 23:28:22.509333  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3231 23:28:22.513037  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3232 23:28:22.516248   == TX Byte 1 ==

 3233 23:28:22.519655  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3234 23:28:22.522860  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3235 23:28:22.522942  ==

 3236 23:28:22.525878  Dram Type= 6, Freq= 0, CH_1, rank 0

 3237 23:28:22.529624  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3238 23:28:22.532613  ==

 3239 23:28:22.542525  TX Vref=22, minBit 1, minWin=25, winSum=412

 3240 23:28:22.546395  TX Vref=24, minBit 9, minWin=25, winSum=419

 3241 23:28:22.549118  TX Vref=26, minBit 9, minWin=25, winSum=419

 3242 23:28:22.552539  TX Vref=28, minBit 9, minWin=25, winSum=430

 3243 23:28:22.555933  TX Vref=30, minBit 1, minWin=26, winSum=429

 3244 23:28:22.559236  TX Vref=32, minBit 9, minWin=26, winSum=426

 3245 23:28:22.566000  [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 30

 3246 23:28:22.566082  

 3247 23:28:22.569412  Final TX Range 1 Vref 30

 3248 23:28:22.569495  

 3249 23:28:22.569582  ==

 3250 23:28:22.572837  Dram Type= 6, Freq= 0, CH_1, rank 0

 3251 23:28:22.575818  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3252 23:28:22.575900  ==

 3253 23:28:22.575965  

 3254 23:28:22.576024  

 3255 23:28:22.579267  	TX Vref Scan disable

 3256 23:28:22.582910   == TX Byte 0 ==

 3257 23:28:22.586050  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3258 23:28:22.589232  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3259 23:28:22.592877   == TX Byte 1 ==

 3260 23:28:22.596062  Update DQ  dly =845 (3 ,2, 13)  DQ  OEN =(2 ,7)

 3261 23:28:22.599304  Update DQM dly =845 (3 ,2, 13)  DQM OEN =(2 ,7)

 3262 23:28:22.599386  

 3263 23:28:22.602671  [DATLAT]

 3264 23:28:22.602752  Freq=1200, CH1 RK0

 3265 23:28:22.602818  

 3266 23:28:22.606100  DATLAT Default: 0xd

 3267 23:28:22.606181  0, 0xFFFF, sum = 0

 3268 23:28:22.609473  1, 0xFFFF, sum = 0

 3269 23:28:22.609580  2, 0xFFFF, sum = 0

 3270 23:28:22.612855  3, 0xFFFF, sum = 0

 3271 23:28:22.612938  4, 0xFFFF, sum = 0

 3272 23:28:22.615951  5, 0xFFFF, sum = 0

 3273 23:28:22.616034  6, 0xFFFF, sum = 0

 3274 23:28:22.619451  7, 0xFFFF, sum = 0

 3275 23:28:22.619534  8, 0xFFFF, sum = 0

 3276 23:28:22.623083  9, 0xFFFF, sum = 0

 3277 23:28:22.623166  10, 0xFFFF, sum = 0

 3278 23:28:22.625883  11, 0xFFFF, sum = 0

 3279 23:28:22.625966  12, 0x0, sum = 1

 3280 23:28:22.629639  13, 0x0, sum = 2

 3281 23:28:22.629723  14, 0x0, sum = 3

 3282 23:28:22.632593  15, 0x0, sum = 4

 3283 23:28:22.632676  best_step = 13

 3284 23:28:22.632740  

 3285 23:28:22.632830  ==

 3286 23:28:22.636082  Dram Type= 6, Freq= 0, CH_1, rank 0

 3287 23:28:22.642557  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3288 23:28:22.642644  ==

 3289 23:28:22.642739  RX Vref Scan: 1

 3290 23:28:22.642801  

 3291 23:28:22.646080  Set Vref Range= 32 -> 127

 3292 23:28:22.646161  

 3293 23:28:22.649487  RX Vref 32 -> 127, step: 1

 3294 23:28:22.649571  

 3295 23:28:22.652709  RX Delay -5 -> 252, step: 4

 3296 23:28:22.652790  

 3297 23:28:22.656000  Set Vref, RX VrefLevel [Byte0]: 32

 3298 23:28:22.659223                           [Byte1]: 32

 3299 23:28:22.659304  

 3300 23:28:22.662481  Set Vref, RX VrefLevel [Byte0]: 33

 3301 23:28:22.665746                           [Byte1]: 33

 3302 23:28:22.665828  

 3303 23:28:22.669073  Set Vref, RX VrefLevel [Byte0]: 34

 3304 23:28:22.672516                           [Byte1]: 34

 3305 23:28:22.676208  

 3306 23:28:22.676289  Set Vref, RX VrefLevel [Byte0]: 35

 3307 23:28:22.679616                           [Byte1]: 35

 3308 23:28:22.684017  

 3309 23:28:22.684098  Set Vref, RX VrefLevel [Byte0]: 36

 3310 23:28:22.687490                           [Byte1]: 36

 3311 23:28:22.692523  

 3312 23:28:22.692619  Set Vref, RX VrefLevel [Byte0]: 37

 3313 23:28:22.695283                           [Byte1]: 37

 3314 23:28:22.699822  

 3315 23:28:22.699904  Set Vref, RX VrefLevel [Byte0]: 38

 3316 23:28:22.703129                           [Byte1]: 38

 3317 23:28:22.707532  

 3318 23:28:22.707613  Set Vref, RX VrefLevel [Byte0]: 39

 3319 23:28:22.711023                           [Byte1]: 39

 3320 23:28:22.715742  

 3321 23:28:22.715823  Set Vref, RX VrefLevel [Byte0]: 40

 3322 23:28:22.718645                           [Byte1]: 40

 3323 23:28:22.723740  

 3324 23:28:22.723821  Set Vref, RX VrefLevel [Byte0]: 41

 3325 23:28:22.726728                           [Byte1]: 41

 3326 23:28:22.731712  

 3327 23:28:22.731794  Set Vref, RX VrefLevel [Byte0]: 42

 3328 23:28:22.734701                           [Byte1]: 42

 3329 23:28:22.739136  

 3330 23:28:22.739217  Set Vref, RX VrefLevel [Byte0]: 43

 3331 23:28:22.742539                           [Byte1]: 43

 3332 23:28:22.746901  

 3333 23:28:22.746983  Set Vref, RX VrefLevel [Byte0]: 44

 3334 23:28:22.750410                           [Byte1]: 44

 3335 23:28:22.755029  

 3336 23:28:22.755110  Set Vref, RX VrefLevel [Byte0]: 45

 3337 23:28:22.757934                           [Byte1]: 45

 3338 23:28:22.763135  

 3339 23:28:22.763216  Set Vref, RX VrefLevel [Byte0]: 46

 3340 23:28:22.766090                           [Byte1]: 46

 3341 23:28:22.770702  

 3342 23:28:22.770782  Set Vref, RX VrefLevel [Byte0]: 47

 3343 23:28:22.773934                           [Byte1]: 47

 3344 23:28:22.778371  

 3345 23:28:22.778457  Set Vref, RX VrefLevel [Byte0]: 48

 3346 23:28:22.781743                           [Byte1]: 48

 3347 23:28:22.786097  

 3348 23:28:22.786179  Set Vref, RX VrefLevel [Byte0]: 49

 3349 23:28:22.789290                           [Byte1]: 49

 3350 23:28:22.793929  

 3351 23:28:22.794028  Set Vref, RX VrefLevel [Byte0]: 50

 3352 23:28:22.797392                           [Byte1]: 50

 3353 23:28:22.801951  

 3354 23:28:22.802032  Set Vref, RX VrefLevel [Byte0]: 51

 3355 23:28:22.805127                           [Byte1]: 51

 3356 23:28:22.809713  

 3357 23:28:22.809794  Set Vref, RX VrefLevel [Byte0]: 52

 3358 23:28:22.813061                           [Byte1]: 52

 3359 23:28:22.817424  

 3360 23:28:22.817506  Set Vref, RX VrefLevel [Byte0]: 53

 3361 23:28:22.820905                           [Byte1]: 53

 3362 23:28:22.825350  

 3363 23:28:22.825432  Set Vref, RX VrefLevel [Byte0]: 54

 3364 23:28:22.828983                           [Byte1]: 54

 3365 23:28:22.833570  

 3366 23:28:22.833706  Set Vref, RX VrefLevel [Byte0]: 55

 3367 23:28:22.836687                           [Byte1]: 55

 3368 23:28:22.841342  

 3369 23:28:22.841425  Set Vref, RX VrefLevel [Byte0]: 56

 3370 23:28:22.844571                           [Byte1]: 56

 3371 23:28:22.849173  

 3372 23:28:22.849254  Set Vref, RX VrefLevel [Byte0]: 57

 3373 23:28:22.852572                           [Byte1]: 57

 3374 23:28:22.856991  

 3375 23:28:22.857072  Set Vref, RX VrefLevel [Byte0]: 58

 3376 23:28:22.860368                           [Byte1]: 58

 3377 23:28:22.865004  

 3378 23:28:22.865086  Set Vref, RX VrefLevel [Byte0]: 59

 3379 23:28:22.868078                           [Byte1]: 59

 3380 23:28:22.872426  

 3381 23:28:22.872507  Set Vref, RX VrefLevel [Byte0]: 60

 3382 23:28:22.875714                           [Byte1]: 60

 3383 23:28:22.880684  

 3384 23:28:22.880818  Set Vref, RX VrefLevel [Byte0]: 61

 3385 23:28:22.883870                           [Byte1]: 61

 3386 23:28:22.888556  

 3387 23:28:22.888637  Set Vref, RX VrefLevel [Byte0]: 62

 3388 23:28:22.891666                           [Byte1]: 62

 3389 23:28:22.896186  

 3390 23:28:22.896267  Set Vref, RX VrefLevel [Byte0]: 63

 3391 23:28:22.899659                           [Byte1]: 63

 3392 23:28:22.904074  

 3393 23:28:22.904156  Set Vref, RX VrefLevel [Byte0]: 64

 3394 23:28:22.906998                           [Byte1]: 64

 3395 23:28:22.911815  

 3396 23:28:22.911913  Set Vref, RX VrefLevel [Byte0]: 65

 3397 23:28:22.914955                           [Byte1]: 65

 3398 23:28:22.919394  

 3399 23:28:22.919476  Set Vref, RX VrefLevel [Byte0]: 66

 3400 23:28:22.922870                           [Byte1]: 66

 3401 23:28:22.927479  

 3402 23:28:22.927561  Set Vref, RX VrefLevel [Byte0]: 67

 3403 23:28:22.931052                           [Byte1]: 67

 3404 23:28:22.935656  

 3405 23:28:22.935737  Set Vref, RX VrefLevel [Byte0]: 68

 3406 23:28:22.938723                           [Byte1]: 68

 3407 23:28:22.943167  

 3408 23:28:22.943249  Final RX Vref Byte 0 = 53 to rank0

 3409 23:28:22.946707  Final RX Vref Byte 1 = 55 to rank0

 3410 23:28:22.950142  Final RX Vref Byte 0 = 53 to rank1

 3411 23:28:22.953103  Final RX Vref Byte 1 = 55 to rank1==

 3412 23:28:22.956512  Dram Type= 6, Freq= 0, CH_1, rank 0

 3413 23:28:22.963277  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3414 23:28:22.963360  ==

 3415 23:28:22.963426  DQS Delay:

 3416 23:28:22.963487  DQS0 = 0, DQS1 = 0

 3417 23:28:22.966625  DQM Delay:

 3418 23:28:22.966708  DQM0 = 120, DQM1 = 117

 3419 23:28:22.969771  DQ Delay:

 3420 23:28:22.973168  DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =116

 3421 23:28:22.976789  DQ4 =120, DQ5 =128, DQ6 =128, DQ7 =120

 3422 23:28:22.979929  DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112

 3423 23:28:22.983520  DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126

 3424 23:28:22.983602  

 3425 23:28:22.983666  

 3426 23:28:22.989851  [DQSOSCAuto] RK0, (LSB)MR18= 0xff11, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps

 3427 23:28:22.993317  CH1 RK0: MR19=304, MR18=FF11

 3428 23:28:22.999860  CH1_RK0: MR19=0x304, MR18=0xFF11, DQSOSC=403, MR23=63, INC=40, DEC=26

 3429 23:28:22.999942  

 3430 23:28:23.003358  ----->DramcWriteLeveling(PI) begin...

 3431 23:28:23.003442  ==

 3432 23:28:23.006480  Dram Type= 6, Freq= 0, CH_1, rank 1

 3433 23:28:23.010089  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3434 23:28:23.013263  ==

 3435 23:28:23.013345  Write leveling (Byte 0): 26 => 26

 3436 23:28:23.016594  Write leveling (Byte 1): 28 => 28

 3437 23:28:23.019980  DramcWriteLeveling(PI) end<-----

 3438 23:28:23.020062  

 3439 23:28:23.020127  ==

 3440 23:28:23.023394  Dram Type= 6, Freq= 0, CH_1, rank 1

 3441 23:28:23.030059  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3442 23:28:23.030207  ==

 3443 23:28:23.030347  [Gating] SW mode calibration

 3444 23:28:23.040241  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0

 3445 23:28:23.043271  RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)

 3446 23:28:23.046725   0 15  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3447 23:28:23.053317   0 15  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3448 23:28:23.056522   0 15  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3449 23:28:23.060580   0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3450 23:28:23.066987   0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3451 23:28:23.069875   0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)

 3452 23:28:23.073237   0 15 24 | B1->B0 | 2828 3232 | 1 1 | (1 0) (1 1)

 3453 23:28:23.079958   0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 3454 23:28:23.083551   1  0  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3455 23:28:23.086928   1  0  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3456 23:28:23.093251   1  0  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3457 23:28:23.096383   1  0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3458 23:28:23.100235   1  0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3459 23:28:23.106816   1  0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)

 3460 23:28:23.109724   1  0 24 | B1->B0 | 4040 2929 | 0 1 | (0 0) (0 0)

 3461 23:28:23.113012   1  0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)

 3462 23:28:23.119788   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3463 23:28:23.123539   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3464 23:28:23.126947   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3465 23:28:23.133316   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3466 23:28:23.136489   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3467 23:28:23.139923   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 3468 23:28:23.146637   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 3469 23:28:23.149981   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 3470 23:28:23.153438   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3471 23:28:23.156804   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3472 23:28:23.163007   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3473 23:28:23.166385   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3474 23:28:23.169613   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3475 23:28:23.176434   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3476 23:28:23.179991   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3477 23:28:23.183281   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3478 23:28:23.190318   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3479 23:28:23.193009   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3480 23:28:23.196215   1  3  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3481 23:28:23.203039   1  3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3482 23:28:23.206362   1  3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 3483 23:28:23.209834   1  3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 3484 23:28:23.216448   1  3 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 3485 23:28:23.216535  Total UI for P1: 0, mck2ui 16

 3486 23:28:23.222778  best dqsien dly found for B1: ( 1,  3, 20)

 3487 23:28:23.226102   1  3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 3488 23:28:23.229533   1  4  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3489 23:28:23.232917  Total UI for P1: 0, mck2ui 16

 3490 23:28:23.236229  best dqsien dly found for B0: ( 1,  3, 28)

 3491 23:28:23.239805  best DQS0 dly(MCK, UI, PI) = (1, 3, 28)

 3492 23:28:23.243144  best DQS1 dly(MCK, UI, PI) = (1, 3, 20)

 3493 23:28:23.243226  

 3494 23:28:23.249543  best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)

 3495 23:28:23.252859  best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 20)

 3496 23:28:23.252971  [Gating] SW calibration Done

 3497 23:28:23.256088  ==

 3498 23:28:23.259343  Dram Type= 6, Freq= 0, CH_1, rank 1

 3499 23:28:23.262809  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3500 23:28:23.262892  ==

 3501 23:28:23.263030  RX Vref Scan: 0

 3502 23:28:23.263178  

 3503 23:28:23.265923  RX Vref 0 -> 0, step: 1

 3504 23:28:23.266005  

 3505 23:28:23.269932  RX Delay -40 -> 252, step: 8

 3506 23:28:23.272660  iDelay=200, Bit 0, Center 123 (56 ~ 191) 136

 3507 23:28:23.276070  iDelay=200, Bit 1, Center 115 (48 ~ 183) 136

 3508 23:28:23.279547  iDelay=200, Bit 2, Center 107 (40 ~ 175) 136

 3509 23:28:23.286146  iDelay=200, Bit 3, Center 119 (56 ~ 183) 128

 3510 23:28:23.289527  iDelay=200, Bit 4, Center 119 (56 ~ 183) 128

 3511 23:28:23.293054  iDelay=200, Bit 5, Center 131 (64 ~ 199) 136

 3512 23:28:23.296336  iDelay=200, Bit 6, Center 131 (64 ~ 199) 136

 3513 23:28:23.299182  iDelay=200, Bit 7, Center 123 (56 ~ 191) 136

 3514 23:28:23.306122  iDelay=200, Bit 8, Center 103 (40 ~ 167) 128

 3515 23:28:23.309503  iDelay=200, Bit 9, Center 107 (40 ~ 175) 136

 3516 23:28:23.312798  iDelay=200, Bit 10, Center 115 (48 ~ 183) 136

 3517 23:28:23.316111  iDelay=200, Bit 11, Center 115 (48 ~ 183) 136

 3518 23:28:23.319641  iDelay=200, Bit 12, Center 127 (56 ~ 199) 144

 3519 23:28:23.325856  iDelay=200, Bit 13, Center 127 (64 ~ 191) 128

 3520 23:28:23.329243  iDelay=200, Bit 14, Center 123 (56 ~ 191) 136

 3521 23:28:23.332875  iDelay=200, Bit 15, Center 123 (56 ~ 191) 136

 3522 23:28:23.332958  ==

 3523 23:28:23.335911  Dram Type= 6, Freq= 0, CH_1, rank 1

 3524 23:28:23.339367  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3525 23:28:23.342564  ==

 3526 23:28:23.342646  DQS Delay:

 3527 23:28:23.342711  DQS0 = 0, DQS1 = 0

 3528 23:28:23.345743  DQM Delay:

 3529 23:28:23.345826  DQM0 = 121, DQM1 = 117

 3530 23:28:23.349256  DQ Delay:

 3531 23:28:23.352680  DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119

 3532 23:28:23.355863  DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123

 3533 23:28:23.359256  DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115

 3534 23:28:23.362807  DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123

 3535 23:28:23.362915  

 3536 23:28:23.363007  

 3537 23:28:23.363158  ==

 3538 23:28:23.365705  Dram Type= 6, Freq= 0, CH_1, rank 1

 3539 23:28:23.369140  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3540 23:28:23.369223  ==

 3541 23:28:23.369288  

 3542 23:28:23.372625  

 3543 23:28:23.372706  	TX Vref Scan disable

 3544 23:28:23.375970   == TX Byte 0 ==

 3545 23:28:23.379387  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3546 23:28:23.382731  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3547 23:28:23.385902   == TX Byte 1 ==

 3548 23:28:23.389339  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3549 23:28:23.392585  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3550 23:28:23.392667  ==

 3551 23:28:23.396453  Dram Type= 6, Freq= 0, CH_1, rank 1

 3552 23:28:23.399265  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3553 23:28:23.402579  ==

 3554 23:28:23.412500  TX Vref=22, minBit 9, minWin=25, winSum=420

 3555 23:28:23.416196  TX Vref=24, minBit 2, minWin=26, winSum=425

 3556 23:28:23.419324  TX Vref=26, minBit 2, minWin=26, winSum=430

 3557 23:28:23.422407  TX Vref=28, minBit 4, minWin=26, winSum=431

 3558 23:28:23.425764  TX Vref=30, minBit 9, minWin=26, winSum=434

 3559 23:28:23.432525  TX Vref=32, minBit 9, minWin=26, winSum=436

 3560 23:28:23.435746  [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32

 3561 23:28:23.435829  

 3562 23:28:23.439183  Final TX Range 1 Vref 32

 3563 23:28:23.439265  

 3564 23:28:23.439330  ==

 3565 23:28:23.442730  Dram Type= 6, Freq= 0, CH_1, rank 1

 3566 23:28:23.445757  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3567 23:28:23.445840  ==

 3568 23:28:23.449034  

 3569 23:28:23.449116  

 3570 23:28:23.449181  	TX Vref Scan disable

 3571 23:28:23.452114   == TX Byte 0 ==

 3572 23:28:23.455910  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3573 23:28:23.462475  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3574 23:28:23.462559   == TX Byte 1 ==

 3575 23:28:23.465729  Update DQ  dly =844 (3 ,2, 12)  DQ  OEN =(2 ,7)

 3576 23:28:23.472172  Update DQM dly =844 (3 ,2, 12)  DQM OEN =(2 ,7)

 3577 23:28:23.472254  

 3578 23:28:23.472318  [DATLAT]

 3579 23:28:23.472379  Freq=1200, CH1 RK1

 3580 23:28:23.472438  

 3581 23:28:23.475502  DATLAT Default: 0xd

 3582 23:28:23.475584  0, 0xFFFF, sum = 0

 3583 23:28:23.479042  1, 0xFFFF, sum = 0

 3584 23:28:23.482297  2, 0xFFFF, sum = 0

 3585 23:28:23.482381  3, 0xFFFF, sum = 0

 3586 23:28:23.485518  4, 0xFFFF, sum = 0

 3587 23:28:23.485629  5, 0xFFFF, sum = 0

 3588 23:28:23.488539  6, 0xFFFF, sum = 0

 3589 23:28:23.488623  7, 0xFFFF, sum = 0

 3590 23:28:23.492237  8, 0xFFFF, sum = 0

 3591 23:28:23.492321  9, 0xFFFF, sum = 0

 3592 23:28:23.495193  10, 0xFFFF, sum = 0

 3593 23:28:23.495276  11, 0xFFFF, sum = 0

 3594 23:28:23.499267  12, 0x0, sum = 1

 3595 23:28:23.499351  13, 0x0, sum = 2

 3596 23:28:23.501996  14, 0x0, sum = 3

 3597 23:28:23.502079  15, 0x0, sum = 4

 3598 23:28:23.505155  best_step = 13

 3599 23:28:23.505238  

 3600 23:28:23.505303  ==

 3601 23:28:23.508748  Dram Type= 6, Freq= 0, CH_1, rank 1

 3602 23:28:23.512142  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3603 23:28:23.512225  ==

 3604 23:28:23.512290  RX Vref Scan: 0

 3605 23:28:23.512351  

 3606 23:28:23.515399  RX Vref 0 -> 0, step: 1

 3607 23:28:23.515481  

 3608 23:28:23.518406  RX Delay -5 -> 252, step: 4

 3609 23:28:23.522222  iDelay=195, Bit 0, Center 122 (59 ~ 186) 128

 3610 23:28:23.528711  iDelay=195, Bit 1, Center 116 (55 ~ 178) 124

 3611 23:28:23.531955  iDelay=195, Bit 2, Center 110 (51 ~ 170) 120

 3612 23:28:23.535280  iDelay=195, Bit 3, Center 118 (59 ~ 178) 120

 3613 23:28:23.538634  iDelay=195, Bit 4, Center 116 (55 ~ 178) 124

 3614 23:28:23.541786  iDelay=195, Bit 5, Center 132 (71 ~ 194) 124

 3615 23:28:23.548491  iDelay=195, Bit 6, Center 130 (67 ~ 194) 128

 3616 23:28:23.551934  iDelay=195, Bit 7, Center 120 (59 ~ 182) 124

 3617 23:28:23.555173  iDelay=195, Bit 8, Center 106 (47 ~ 166) 120

 3618 23:28:23.558242  iDelay=195, Bit 9, Center 108 (47 ~ 170) 124

 3619 23:28:23.561805  iDelay=195, Bit 10, Center 118 (59 ~ 178) 120

 3620 23:28:23.568328  iDelay=195, Bit 11, Center 112 (51 ~ 174) 124

 3621 23:28:23.571785  iDelay=195, Bit 12, Center 126 (63 ~ 190) 128

 3622 23:28:23.575124  iDelay=195, Bit 13, Center 124 (67 ~ 182) 116

 3623 23:28:23.578208  iDelay=195, Bit 14, Center 124 (67 ~ 182) 116

 3624 23:28:23.584758  iDelay=195, Bit 15, Center 126 (67 ~ 186) 120

 3625 23:28:23.584841  ==

 3626 23:28:23.588274  Dram Type= 6, Freq= 0, CH_1, rank 1

 3627 23:28:23.591980  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3628 23:28:23.592062  ==

 3629 23:28:23.592128  DQS Delay:

 3630 23:28:23.594968  DQS0 = 0, DQS1 = 0

 3631 23:28:23.595050  DQM Delay:

 3632 23:28:23.598210  DQM0 = 120, DQM1 = 118

 3633 23:28:23.598292  DQ Delay:

 3634 23:28:23.601419  DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118

 3635 23:28:23.604788  DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120

 3636 23:28:23.608202  DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112

 3637 23:28:23.611231  DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126

 3638 23:28:23.611313  

 3639 23:28:23.611378  

 3640 23:28:23.621547  [DQSOSCAuto] RK1, (LSB)MR18= 0x10ee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 403 ps

 3641 23:28:23.624632  CH1 RK1: MR19=403, MR18=10EE

 3642 23:28:23.631187  CH1_RK1: MR19=0x403, MR18=0x10EE, DQSOSC=403, MR23=63, INC=40, DEC=26

 3643 23:28:23.631270  [RxdqsGatingPostProcess] freq 1200

 3644 23:28:23.637920  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 3645 23:28:23.641238  best DQS0 dly(2T, 0.5T) = (0, 11)

 3646 23:28:23.644661  best DQS1 dly(2T, 0.5T) = (0, 11)

 3647 23:28:23.647641  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3648 23:28:23.650972  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3649 23:28:23.654563  best DQS0 dly(2T, 0.5T) = (0, 11)

 3650 23:28:23.657833  best DQS1 dly(2T, 0.5T) = (0, 11)

 3651 23:28:23.661304  best DQS0 P1 dly(2T, 0.5T) = (0, 15)

 3652 23:28:23.664628  best DQS1 P1 dly(2T, 0.5T) = (0, 15)

 3653 23:28:23.667735  Pre-setting of DQS Precalculation

 3654 23:28:23.671070  [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13

 3655 23:28:23.677747  sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2

 3656 23:28:23.684625  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 3657 23:28:23.687867  

 3658 23:28:23.687951  

 3659 23:28:23.688037  [Calibration Summary] 2400 Mbps

 3660 23:28:23.691157  CH 0, Rank 0

 3661 23:28:23.691242  SW Impedance     : PASS

 3662 23:28:23.694310  DUTY Scan        : NO K

 3663 23:28:23.697793  ZQ Calibration   : PASS

 3664 23:28:23.697878  Jitter Meter     : NO K

 3665 23:28:23.701041  CBT Training     : PASS

 3666 23:28:23.704361  Write leveling   : PASS

 3667 23:28:23.704447  RX DQS gating    : PASS

 3668 23:28:23.707930  RX DQ/DQS(RDDQC) : PASS

 3669 23:28:23.711232  TX DQ/DQS        : PASS

 3670 23:28:23.711317  RX DATLAT        : PASS

 3671 23:28:23.714485  RX DQ/DQS(Engine): PASS

 3672 23:28:23.718075  TX OE            : NO K

 3673 23:28:23.718160  All Pass.

 3674 23:28:23.718246  

 3675 23:28:23.718326  CH 0, Rank 1

 3676 23:28:23.721108  SW Impedance     : PASS

 3677 23:28:23.724580  DUTY Scan        : NO K

 3678 23:28:23.724665  ZQ Calibration   : PASS

 3679 23:28:23.727716  Jitter Meter     : NO K

 3680 23:28:23.727801  CBT Training     : PASS

 3681 23:28:23.731255  Write leveling   : PASS

 3682 23:28:23.734737  RX DQS gating    : PASS

 3683 23:28:23.734822  RX DQ/DQS(RDDQC) : PASS

 3684 23:28:23.737927  TX DQ/DQS        : PASS

 3685 23:28:23.741132  RX DATLAT        : PASS

 3686 23:28:23.741216  RX DQ/DQS(Engine): PASS

 3687 23:28:23.744509  TX OE            : NO K

 3688 23:28:23.744595  All Pass.

 3689 23:28:23.744680  

 3690 23:28:23.747661  CH 1, Rank 0

 3691 23:28:23.747747  SW Impedance     : PASS

 3692 23:28:23.750704  DUTY Scan        : NO K

 3693 23:28:23.753999  ZQ Calibration   : PASS

 3694 23:28:23.754083  Jitter Meter     : NO K

 3695 23:28:23.757612  CBT Training     : PASS

 3696 23:28:23.760917  Write leveling   : PASS

 3697 23:28:23.761002  RX DQS gating    : PASS

 3698 23:28:23.764078  RX DQ/DQS(RDDQC) : PASS

 3699 23:28:23.767558  TX DQ/DQS        : PASS

 3700 23:28:23.767642  RX DATLAT        : PASS

 3701 23:28:23.771200  RX DQ/DQS(Engine): PASS

 3702 23:28:23.774500  TX OE            : NO K

 3703 23:28:23.774586  All Pass.

 3704 23:28:23.774672  

 3705 23:28:23.774753  CH 1, Rank 1

 3706 23:28:23.777570  SW Impedance     : PASS

 3707 23:28:23.780988  DUTY Scan        : NO K

 3708 23:28:23.781073  ZQ Calibration   : PASS

 3709 23:28:23.784287  Jitter Meter     : NO K

 3710 23:28:23.784371  CBT Training     : PASS

 3711 23:28:23.787661  Write leveling   : PASS

 3712 23:28:23.791013  RX DQS gating    : PASS

 3713 23:28:23.791098  RX DQ/DQS(RDDQC) : PASS

 3714 23:28:23.794317  TX DQ/DQS        : PASS

 3715 23:28:23.797696  RX DATLAT        : PASS

 3716 23:28:23.797781  RX DQ/DQS(Engine): PASS

 3717 23:28:23.800924  TX OE            : NO K

 3718 23:28:23.801008  All Pass.

 3719 23:28:23.801093  

 3720 23:28:23.804491  DramC Write-DBI off

 3721 23:28:23.807480  	PER_BANK_REFRESH: Hybrid Mode

 3722 23:28:23.807565  TX_TRACKING: ON

 3723 23:28:23.817638  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1

 3724 23:28:23.820841  [FAST_K] Save calibration result to emmc

 3725 23:28:23.824122  dramc_set_vcore_voltage set vcore to 650000

 3726 23:28:23.827378  Read voltage for 600, 5

 3727 23:28:23.827463  Vio18 = 0

 3728 23:28:23.827548  Vcore = 650000

 3729 23:28:23.830517  Vdram = 0

 3730 23:28:23.830601  Vddq = 0

 3731 23:28:23.830687  Vmddr = 0

 3732 23:28:23.837521  [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0

 3733 23:28:23.840715  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 3734 23:28:23.844008  MEM_TYPE=3, freq_sel=19

 3735 23:28:23.847002  sv_algorithm_assistance_LP4_1600 

 3736 23:28:23.850428  ============ PULL DRAM RESETB DOWN ============

 3737 23:28:23.853727  ========== PULL DRAM RESETB DOWN end =========

 3738 23:28:23.860376  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3739 23:28:23.863812  =================================== 

 3740 23:28:23.866935  LPDDR4 DRAM CONFIGURATION

 3741 23:28:23.870185  =================================== 

 3742 23:28:23.870271  EX_ROW_EN[0]    = 0x0

 3743 23:28:23.873642  EX_ROW_EN[1]    = 0x0

 3744 23:28:23.873727  LP4Y_EN      = 0x0

 3745 23:28:23.876909  WORK_FSP     = 0x0

 3746 23:28:23.876994  WL           = 0x2

 3747 23:28:23.879887  RL           = 0x2

 3748 23:28:23.879972  BL           = 0x2

 3749 23:28:23.883634  RPST         = 0x0

 3750 23:28:23.883718  RD_PRE       = 0x0

 3751 23:28:23.886956  WR_PRE       = 0x1

 3752 23:28:23.890059  WR_PST       = 0x0

 3753 23:28:23.890143  DBI_WR       = 0x0

 3754 23:28:23.893288  DBI_RD       = 0x0

 3755 23:28:23.893390  OTF          = 0x1

 3756 23:28:23.896540  =================================== 

 3757 23:28:23.899901  =================================== 

 3758 23:28:23.899986  ANA top config

 3759 23:28:23.902966  =================================== 

 3760 23:28:23.906512  DLL_ASYNC_EN            =  0

 3761 23:28:23.909885  ALL_SLAVE_EN            =  1

 3762 23:28:23.913469  NEW_RANK_MODE           =  1

 3763 23:28:23.916494  DLL_IDLE_MODE           =  1

 3764 23:28:23.916578  LP45_APHY_COMB_EN       =  1

 3765 23:28:23.920028  TX_ODT_DIS              =  1

 3766 23:28:23.923068  NEW_8X_MODE             =  1

 3767 23:28:23.926755  =================================== 

 3768 23:28:23.929783  =================================== 

 3769 23:28:23.933244  data_rate                  = 1200

 3770 23:28:23.936240  CKR                        = 1

 3771 23:28:23.936323  DQ_P2S_RATIO               = 8

 3772 23:28:23.939567  =================================== 

 3773 23:28:23.943259  CA_P2S_RATIO               = 8

 3774 23:28:23.946712  DQ_CA_OPEN                 = 0

 3775 23:28:23.949907  DQ_SEMI_OPEN               = 0

 3776 23:28:23.953612  CA_SEMI_OPEN               = 0

 3777 23:28:23.957127  CA_FULL_RATE               = 0

 3778 23:28:23.957211  DQ_CKDIV4_EN               = 1

 3779 23:28:23.959800  CA_CKDIV4_EN               = 1

 3780 23:28:23.963176  CA_PREDIV_EN               = 0

 3781 23:28:23.966449  PH8_DLY                    = 0

 3782 23:28:23.969554  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 3783 23:28:23.972731  DQ_AAMCK_DIV               = 4

 3784 23:28:23.972829  CA_AAMCK_DIV               = 4

 3785 23:28:23.976067  CA_ADMCK_DIV               = 4

 3786 23:28:23.979419  DQ_TRACK_CA_EN             = 0

 3787 23:28:23.982824  CA_PICK                    = 600

 3788 23:28:23.986151  CA_MCKIO                   = 600

 3789 23:28:23.989631  MCKIO_SEMI                 = 0

 3790 23:28:23.992942  PLL_FREQ                   = 2288

 3791 23:28:23.993027  DQ_UI_PI_RATIO             = 32

 3792 23:28:23.996812  CA_UI_PI_RATIO             = 0

 3793 23:28:23.999342  =================================== 

 3794 23:28:24.002659  =================================== 

 3795 23:28:24.006569  memory_type:LPDDR4         

 3796 23:28:24.009509  GP_NUM     : 10       

 3797 23:28:24.009629  SRAM_EN    : 1       

 3798 23:28:24.012925  MD32_EN    : 0       

 3799 23:28:24.016196  =================================== 

 3800 23:28:24.016281  [ANA_INIT] >>>>>>>>>>>>>> 

 3801 23:28:24.020039  <<<<<< [CONFIGURE PHASE]: ANA_TX

 3802 23:28:24.023102  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 3803 23:28:24.026231  =================================== 

 3804 23:28:24.029286  data_rate = 1200,PCW = 0X5800

 3805 23:28:24.032837  =================================== 

 3806 23:28:24.036331  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 3807 23:28:24.042970  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3808 23:28:24.049082  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 3809 23:28:24.052516  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 3810 23:28:24.055885  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 3811 23:28:24.059349  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 3812 23:28:24.062694  [ANA_INIT] flow start 

 3813 23:28:24.062797  [ANA_INIT] PLL >>>>>>>> 

 3814 23:28:24.065723  [ANA_INIT] PLL <<<<<<<< 

 3815 23:28:24.069436  [ANA_INIT] MIDPI >>>>>>>> 

 3816 23:28:24.069551  [ANA_INIT] MIDPI <<<<<<<< 

 3817 23:28:24.072676  [ANA_INIT] DLL >>>>>>>> 

 3818 23:28:24.075668  [ANA_INIT] flow end 

 3819 23:28:24.079236  ============ LP4 DIFF to SE enter ============

 3820 23:28:24.082561  ============ LP4 DIFF to SE exit  ============

 3821 23:28:24.086113  [ANA_INIT] <<<<<<<<<<<<< 

 3822 23:28:24.089208  [Flow] Enable top DCM control >>>>> 

 3823 23:28:24.092677  [Flow] Enable top DCM control <<<<< 

 3824 23:28:24.095554  Enable DLL master slave shuffle 

 3825 23:28:24.099183  ============================================================== 

 3826 23:28:24.102219  Gating Mode config

 3827 23:28:24.109277  ============================================================== 

 3828 23:28:24.109372  Config description: 

 3829 23:28:24.118924  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 3830 23:28:24.125734  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 3831 23:28:24.128846  SELPH_MODE            0: By rank         1: By Phase 

 3832 23:28:24.136197  ============================================================== 

 3833 23:28:24.138816  GAT_TRACK_EN                 =  1

 3834 23:28:24.142470  RX_GATING_MODE               =  2

 3835 23:28:24.145755  RX_GATING_TRACK_MODE         =  2

 3836 23:28:24.148950  SELPH_MODE                   =  1

 3837 23:28:24.152439  PICG_EARLY_EN                =  1

 3838 23:28:24.155678  VALID_LAT_VALUE              =  1

 3839 23:28:24.158916  ============================================================== 

 3840 23:28:24.162415  Enter into Gating configuration >>>> 

 3841 23:28:24.165826  Exit from Gating configuration <<<< 

 3842 23:28:24.169148  Enter into  DVFS_PRE_config >>>>> 

 3843 23:28:24.182117  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 3844 23:28:24.182206  Exit from  DVFS_PRE_config <<<<< 

 3845 23:28:24.185649  Enter into PICG configuration >>>> 

 3846 23:28:24.189105  Exit from PICG configuration <<<< 

 3847 23:28:24.192572  [RX_INPUT] configuration >>>>> 

 3848 23:28:24.195890  [RX_INPUT] configuration <<<<< 

 3849 23:28:24.202062  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 3850 23:28:24.205685  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 3851 23:28:24.212303  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 3852 23:28:24.219060  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 3853 23:28:24.225728  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 3854 23:28:24.232101  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 3855 23:28:24.235447  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 3856 23:28:24.238560  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 3857 23:28:24.241965  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 3858 23:28:24.248697  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 3859 23:28:24.252035  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 3860 23:28:24.255389  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3861 23:28:24.258662  =================================== 

 3862 23:28:24.261917  LPDDR4 DRAM CONFIGURATION

 3863 23:28:24.265314  =================================== 

 3864 23:28:24.265401  EX_ROW_EN[0]    = 0x0

 3865 23:28:24.268687  EX_ROW_EN[1]    = 0x0

 3866 23:28:24.272301  LP4Y_EN      = 0x0

 3867 23:28:24.272386  WORK_FSP     = 0x0

 3868 23:28:24.275189  WL           = 0x2

 3869 23:28:24.275274  RL           = 0x2

 3870 23:28:24.278932  BL           = 0x2

 3871 23:28:24.279017  RPST         = 0x0

 3872 23:28:24.281907  RD_PRE       = 0x0

 3873 23:28:24.281992  WR_PRE       = 0x1

 3874 23:28:24.285208  WR_PST       = 0x0

 3875 23:28:24.285293  DBI_WR       = 0x0

 3876 23:28:24.288258  DBI_RD       = 0x0

 3877 23:28:24.288343  OTF          = 0x1

 3878 23:28:24.291637  =================================== 

 3879 23:28:24.295524  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 3880 23:28:24.302014  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 3881 23:28:24.305432  [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2

 3882 23:28:24.308617  =================================== 

 3883 23:28:24.311663  LPDDR4 DRAM CONFIGURATION

 3884 23:28:24.314945  =================================== 

 3885 23:28:24.315030  EX_ROW_EN[0]    = 0x10

 3886 23:28:24.318424  EX_ROW_EN[1]    = 0x0

 3887 23:28:24.318508  LP4Y_EN      = 0x0

 3888 23:28:24.321757  WORK_FSP     = 0x0

 3889 23:28:24.324960  WL           = 0x2

 3890 23:28:24.325045  RL           = 0x2

 3891 23:28:24.328182  BL           = 0x2

 3892 23:28:24.328267  RPST         = 0x0

 3893 23:28:24.331446  RD_PRE       = 0x0

 3894 23:28:24.331530  WR_PRE       = 0x1

 3895 23:28:24.335029  WR_PST       = 0x0

 3896 23:28:24.335115  DBI_WR       = 0x0

 3897 23:28:24.338089  DBI_RD       = 0x0

 3898 23:28:24.338173  OTF          = 0x1

 3899 23:28:24.341450  =================================== 

 3900 23:28:24.348050  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 3901 23:28:24.352249  nWR fixed to 30

 3902 23:28:24.355533  [ModeRegInit_LP4] CH0 RK0

 3903 23:28:24.355618  [ModeRegInit_LP4] CH0 RK1

 3904 23:28:24.358785  [ModeRegInit_LP4] CH1 RK0

 3905 23:28:24.362053  [ModeRegInit_LP4] CH1 RK1

 3906 23:28:24.362137  match AC timing 17

 3907 23:28:24.368943  dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1

 3908 23:28:24.372108  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 3909 23:28:24.375711  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 3910 23:28:24.382219  [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17

 3911 23:28:24.385478  [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)

 3912 23:28:24.385553  ==

 3913 23:28:24.389015  Dram Type= 6, Freq= 0, CH_0, rank 0

 3914 23:28:24.392323  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3915 23:28:24.392405  ==

 3916 23:28:24.398630  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3917 23:28:24.405343  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 3918 23:28:24.408757  [CA 0] Center 35 (5~66) winsize 62

 3919 23:28:24.412225  [CA 1] Center 35 (5~66) winsize 62

 3920 23:28:24.415503  [CA 2] Center 33 (3~64) winsize 62

 3921 23:28:24.418359  [CA 3] Center 33 (2~64) winsize 63

 3922 23:28:24.422100  [CA 4] Center 33 (2~64) winsize 63

 3923 23:28:24.425280  [CA 5] Center 32 (2~63) winsize 62

 3924 23:28:24.425361  

 3925 23:28:24.428307  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 3926 23:28:24.428388  

 3927 23:28:24.431942  [CATrainingPosCal] consider 1 rank data

 3928 23:28:24.435261  u2DelayCellTimex100 = 270/100 ps

 3929 23:28:24.438595  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3930 23:28:24.441611  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3931 23:28:24.445424  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3932 23:28:24.448249  CA3 delay=33 (2~64),Diff = 1 PI (9 cell)

 3933 23:28:24.451972  CA4 delay=33 (2~64),Diff = 1 PI (9 cell)

 3934 23:28:24.458215  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3935 23:28:24.458297  

 3936 23:28:24.461494  CA PerBit enable=1, Macro0, CA PI delay=32

 3937 23:28:24.461598  

 3938 23:28:24.464940  [CBTSetCACLKResult] CA Dly = 32

 3939 23:28:24.465020  CS Dly: 4 (0~35)

 3940 23:28:24.465085  ==

 3941 23:28:24.468276  Dram Type= 6, Freq= 0, CH_0, rank 1

 3942 23:28:24.471739  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3943 23:28:24.471821  ==

 3944 23:28:24.478488  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 3945 23:28:24.485447  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 3946 23:28:24.488723  [CA 0] Center 35 (5~66) winsize 62

 3947 23:28:24.491621  [CA 1] Center 35 (5~66) winsize 62

 3948 23:28:24.494776  [CA 2] Center 34 (3~65) winsize 63

 3949 23:28:24.498181  [CA 3] Center 33 (3~64) winsize 62

 3950 23:28:24.501715  [CA 4] Center 32 (2~63) winsize 62

 3951 23:28:24.505066  [CA 5] Center 32 (2~63) winsize 62

 3952 23:28:24.505147  

 3953 23:28:24.508294  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 3954 23:28:24.508374  

 3955 23:28:24.511756  [CATrainingPosCal] consider 2 rank data

 3956 23:28:24.514925  u2DelayCellTimex100 = 270/100 ps

 3957 23:28:24.518013  CA0 delay=35 (5~66),Diff = 3 PI (28 cell)

 3958 23:28:24.521380  CA1 delay=35 (5~66),Diff = 3 PI (28 cell)

 3959 23:28:24.525309  CA2 delay=33 (3~64),Diff = 1 PI (9 cell)

 3960 23:28:24.531248  CA3 delay=33 (3~64),Diff = 1 PI (9 cell)

 3961 23:28:24.534771  CA4 delay=32 (2~63),Diff = 0 PI (0 cell)

 3962 23:28:24.537873  CA5 delay=32 (2~63),Diff = 0 PI (0 cell)

 3963 23:28:24.537954  

 3964 23:28:24.541551  CA PerBit enable=1, Macro0, CA PI delay=32

 3965 23:28:24.541672  

 3966 23:28:24.544437  [CBTSetCACLKResult] CA Dly = 32

 3967 23:28:24.544517  CS Dly: 4 (0~36)

 3968 23:28:24.544582  

 3969 23:28:24.548061  ----->DramcWriteLeveling(PI) begin...

 3970 23:28:24.548143  ==

 3971 23:28:24.551121  Dram Type= 6, Freq= 0, CH_0, rank 0

 3972 23:28:24.557825  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3973 23:28:24.557912  ==

 3974 23:28:24.560994  Write leveling (Byte 0): 34 => 34

 3975 23:28:24.564172  Write leveling (Byte 1): 31 => 31

 3976 23:28:24.564253  DramcWriteLeveling(PI) end<-----

 3977 23:28:24.567571  

 3978 23:28:24.567651  ==

 3979 23:28:24.570944  Dram Type= 6, Freq= 0, CH_0, rank 0

 3980 23:28:24.574266  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 3981 23:28:24.574348  ==

 3982 23:28:24.577698  [Gating] SW mode calibration

 3983 23:28:24.584234  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 3984 23:28:24.587485  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 3985 23:28:24.594126   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3986 23:28:24.597872   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3987 23:28:24.600818   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 3988 23:28:24.607598   0  9 12 | B1->B0 | 3434 3131 | 1 0 | (1 1) (0 0)

 3989 23:28:24.610834   0  9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)

 3990 23:28:24.614146   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3991 23:28:24.621195   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3992 23:28:24.624311   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3993 23:28:24.627700   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3994 23:28:24.633869   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 3995 23:28:24.637200   0 10  8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)

 3996 23:28:24.640859   0 10 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)

 3997 23:28:24.647658   0 10 16 | B1->B0 | 2f2f 4646 | 0 0 | (0 0) (0 0)

 3998 23:28:24.650712   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 3999 23:28:24.654482   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4000 23:28:24.660701   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4001 23:28:24.664160   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4002 23:28:24.667219   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4003 23:28:24.674014   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4004 23:28:24.677338   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4005 23:28:24.680637   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)

 4006 23:28:24.683950   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4007 23:28:24.690714   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4008 23:28:24.694106   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4009 23:28:24.697484   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4010 23:28:24.704035   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4011 23:28:24.707513   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4012 23:28:24.710938   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4013 23:28:24.717008   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4014 23:28:24.721022   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4015 23:28:24.724027   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4016 23:28:24.730686   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4017 23:28:24.733777   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4018 23:28:24.737204   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4019 23:28:24.744065   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4020 23:28:24.747261   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4021 23:28:24.750512   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4022 23:28:24.754059  Total UI for P1: 0, mck2ui 16

 4023 23:28:24.757292  best dqsien dly found for B0: ( 0, 13, 14)

 4024 23:28:24.763663   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4025 23:28:24.763747  Total UI for P1: 0, mck2ui 16

 4026 23:28:24.770375  best dqsien dly found for B1: ( 0, 13, 16)

 4027 23:28:24.773535  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4028 23:28:24.776765  best DQS1 dly(MCK, UI, PI) = (0, 13, 16)

 4029 23:28:24.776846  

 4030 23:28:24.780118  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4031 23:28:24.783418  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)

 4032 23:28:24.786829  [Gating] SW calibration Done

 4033 23:28:24.786910  ==

 4034 23:28:24.790479  Dram Type= 6, Freq= 0, CH_0, rank 0

 4035 23:28:24.793512  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4036 23:28:24.793647  ==

 4037 23:28:24.796899  RX Vref Scan: 0

 4038 23:28:24.796995  

 4039 23:28:24.797089  RX Vref 0 -> 0, step: 1

 4040 23:28:24.797164  

 4041 23:28:24.800184  RX Delay -230 -> 252, step: 16

 4042 23:28:24.807117  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4043 23:28:24.810020  iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320

 4044 23:28:24.813223  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4045 23:28:24.817187  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4046 23:28:24.820307  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4047 23:28:24.826961  iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304

 4048 23:28:24.829897  iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304

 4049 23:28:24.833758  iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304

 4050 23:28:24.837032  iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288

 4051 23:28:24.843438  iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304

 4052 23:28:24.846539  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4053 23:28:24.850109  iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304

 4054 23:28:24.854011  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4055 23:28:24.856822  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4056 23:28:24.863582  iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320

 4057 23:28:24.866669  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4058 23:28:24.866754  ==

 4059 23:28:24.869798  Dram Type= 6, Freq= 0, CH_0, rank 0

 4060 23:28:24.873194  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4061 23:28:24.873280  ==

 4062 23:28:24.876355  DQS Delay:

 4063 23:28:24.876440  DQS0 = 0, DQS1 = 0

 4064 23:28:24.879886  DQM Delay:

 4065 23:28:24.879972  DQM0 = 54, DQM1 = 48

 4066 23:28:24.880059  DQ Delay:

 4067 23:28:24.883130  DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =49

 4068 23:28:24.886725  DQ4 =49, DQ5 =49, DQ6 =65, DQ7 =65

 4069 23:28:24.890461  DQ8 =41, DQ9 =33, DQ10 =49, DQ11 =49

 4070 23:28:24.893381  DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57

 4071 23:28:24.893465  

 4072 23:28:24.893587  

 4073 23:28:24.893683  ==

 4074 23:28:24.896695  Dram Type= 6, Freq= 0, CH_0, rank 0

 4075 23:28:24.903595  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4076 23:28:24.903679  ==

 4077 23:28:24.903765  

 4078 23:28:24.903845  

 4079 23:28:24.903924  	TX Vref Scan disable

 4080 23:28:24.906853   == TX Byte 0 ==

 4081 23:28:24.910203  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4082 23:28:24.916840  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4083 23:28:24.916930   == TX Byte 1 ==

 4084 23:28:24.920438  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4085 23:28:24.926861  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4086 23:28:24.926973  ==

 4087 23:28:24.930213  Dram Type= 6, Freq= 0, CH_0, rank 0

 4088 23:28:24.933739  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4089 23:28:24.933838  ==

 4090 23:28:24.933939  

 4091 23:28:24.934038  

 4092 23:28:24.937182  	TX Vref Scan disable

 4093 23:28:24.940185   == TX Byte 0 ==

 4094 23:28:24.943670  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4095 23:28:24.947108  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4096 23:28:24.950433   == TX Byte 1 ==

 4097 23:28:24.953609  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4098 23:28:24.957144  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4099 23:28:24.957226  

 4100 23:28:24.957290  [DATLAT]

 4101 23:28:24.960647  Freq=600, CH0 RK0

 4102 23:28:24.960730  

 4103 23:28:24.960795  DATLAT Default: 0x9

 4104 23:28:24.964084  0, 0xFFFF, sum = 0

 4105 23:28:24.964167  1, 0xFFFF, sum = 0

 4106 23:28:24.967138  2, 0xFFFF, sum = 0

 4107 23:28:24.970346  3, 0xFFFF, sum = 0

 4108 23:28:24.970429  4, 0xFFFF, sum = 0

 4109 23:28:24.973803  5, 0xFFFF, sum = 0

 4110 23:28:24.973891  6, 0xFFFF, sum = 0

 4111 23:28:24.977178  7, 0xFFFF, sum = 0

 4112 23:28:24.977261  8, 0x0, sum = 1

 4113 23:28:24.977327  9, 0x0, sum = 2

 4114 23:28:24.980361  10, 0x0, sum = 3

 4115 23:28:24.980443  11, 0x0, sum = 4

 4116 23:28:24.983827  best_step = 9

 4117 23:28:24.983907  

 4118 23:28:24.983971  ==

 4119 23:28:24.987215  Dram Type= 6, Freq= 0, CH_0, rank 0

 4120 23:28:24.990345  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4121 23:28:24.990427  ==

 4122 23:28:24.993670  RX Vref Scan: 1

 4123 23:28:24.993811  

 4124 23:28:24.993909  RX Vref 0 -> 0, step: 1

 4125 23:28:24.993997  

 4126 23:28:24.996972  RX Delay -163 -> 252, step: 8

 4127 23:28:24.997067  

 4128 23:28:25.000213  Set Vref, RX VrefLevel [Byte0]: 57

 4129 23:28:25.003684                           [Byte1]: 55

 4130 23:28:25.007444  

 4131 23:28:25.007524  Final RX Vref Byte 0 = 57 to rank0

 4132 23:28:25.010893  Final RX Vref Byte 1 = 55 to rank0

 4133 23:28:25.014442  Final RX Vref Byte 0 = 57 to rank1

 4134 23:28:25.017755  Final RX Vref Byte 1 = 55 to rank1==

 4135 23:28:25.020934  Dram Type= 6, Freq= 0, CH_0, rank 0

 4136 23:28:25.027519  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4137 23:28:25.027600  ==

 4138 23:28:25.027665  DQS Delay:

 4139 23:28:25.027725  DQS0 = 0, DQS1 = 0

 4140 23:28:25.031157  DQM Delay:

 4141 23:28:25.031238  DQM0 = 53, DQM1 = 46

 4142 23:28:25.033936  DQ Delay:

 4143 23:28:25.037612  DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52

 4144 23:28:25.040758  DQ4 =52, DQ5 =48, DQ6 =60, DQ7 =60

 4145 23:28:25.040839  DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40

 4146 23:28:25.047281  DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52

 4147 23:28:25.047362  

 4148 23:28:25.047426  

 4149 23:28:25.054450  [DQSOSCAuto] RK0, (LSB)MR18= 0x6e62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps

 4150 23:28:25.056952  CH0 RK0: MR19=808, MR18=6E62

 4151 23:28:25.063827  CH0_RK0: MR19=0x808, MR18=0x6E62, DQSOSC=389, MR23=63, INC=173, DEC=115

 4152 23:28:25.063910  

 4153 23:28:25.067306  ----->DramcWriteLeveling(PI) begin...

 4154 23:28:25.067389  ==

 4155 23:28:25.070420  Dram Type= 6, Freq= 0, CH_0, rank 1

 4156 23:28:25.073771  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4157 23:28:25.073854  ==

 4158 23:28:25.077168  Write leveling (Byte 0): 34 => 34

 4159 23:28:25.080643  Write leveling (Byte 1): 31 => 31

 4160 23:28:25.084104  DramcWriteLeveling(PI) end<-----

 4161 23:28:25.084185  

 4162 23:28:25.084249  ==

 4163 23:28:25.086984  Dram Type= 6, Freq= 0, CH_0, rank 1

 4164 23:28:25.090574  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4165 23:28:25.090657  ==

 4166 23:28:25.093952  [Gating] SW mode calibration

 4167 23:28:25.100567  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4168 23:28:25.107127  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4169 23:28:25.110630   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4170 23:28:25.113716   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4171 23:28:25.120690   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4172 23:28:25.124076   0  9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)

 4173 23:28:25.127598   0  9 16 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)

 4174 23:28:25.133616   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4175 23:28:25.137123   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4176 23:28:25.140283   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4177 23:28:25.147153   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4178 23:28:25.150567   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4179 23:28:25.153543   0 10  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4180 23:28:25.160327   0 10 12 | B1->B0 | 2525 2b2b | 0 0 | (0 0) (0 0)

 4181 23:28:25.163583   0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)

 4182 23:28:25.167490   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4183 23:28:25.173473   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4184 23:28:25.177118   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4185 23:28:25.180391   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4186 23:28:25.186949   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4187 23:28:25.190017   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4188 23:28:25.193762   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4189 23:28:25.200089   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 4190 23:28:25.203580   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4191 23:28:25.206917   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4192 23:28:25.210581   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4193 23:28:25.217014   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4194 23:28:25.220511   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4195 23:28:25.223870   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4196 23:28:25.230118   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4197 23:28:25.233558   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4198 23:28:25.236978   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4199 23:28:25.243555   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4200 23:28:25.247261   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4201 23:28:25.250566   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4202 23:28:25.257310   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4203 23:28:25.260353   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4204 23:28:25.263774   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4205 23:28:25.266913  Total UI for P1: 0, mck2ui 16

 4206 23:28:25.270351  best dqsien dly found for B0: ( 0, 13, 10)

 4207 23:28:25.277064   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4208 23:28:25.280375   0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4209 23:28:25.283750  Total UI for P1: 0, mck2ui 16

 4210 23:28:25.287146  best dqsien dly found for B1: ( 0, 13, 14)

 4211 23:28:25.290190  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4212 23:28:25.293332  best DQS1 dly(MCK, UI, PI) = (0, 13, 14)

 4213 23:28:25.293416  

 4214 23:28:25.296991  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4215 23:28:25.300201  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4216 23:28:25.303419  [Gating] SW calibration Done

 4217 23:28:25.303504  ==

 4218 23:28:25.306430  Dram Type= 6, Freq= 0, CH_0, rank 1

 4219 23:28:25.313188  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4220 23:28:25.313273  ==

 4221 23:28:25.313359  RX Vref Scan: 0

 4222 23:28:25.313459  

 4223 23:28:25.316589  RX Vref 0 -> 0, step: 1

 4224 23:28:25.316674  

 4225 23:28:25.319654  RX Delay -230 -> 252, step: 16

 4226 23:28:25.323209  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4227 23:28:25.326281  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4228 23:28:25.330200  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4229 23:28:25.336151  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4230 23:28:25.339590  iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320

 4231 23:28:25.343263  iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304

 4232 23:28:25.346422  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4233 23:28:25.352901  iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320

 4234 23:28:25.356006  iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288

 4235 23:28:25.359761  iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320

 4236 23:28:25.363323  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4237 23:28:25.365981  iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288

 4238 23:28:25.373163  iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304

 4239 23:28:25.375926  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4240 23:28:25.379445  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4241 23:28:25.382583  iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304

 4242 23:28:25.386068  ==

 4243 23:28:25.389781  Dram Type= 6, Freq= 0, CH_0, rank 1

 4244 23:28:25.393007  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4245 23:28:25.393089  ==

 4246 23:28:25.393153  DQS Delay:

 4247 23:28:25.395888  DQS0 = 0, DQS1 = 0

 4248 23:28:25.395969  DQM Delay:

 4249 23:28:25.399181  DQM0 = 52, DQM1 = 44

 4250 23:28:25.399262  DQ Delay:

 4251 23:28:25.402511  DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49

 4252 23:28:25.405944  DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57

 4253 23:28:25.409552  DQ8 =41, DQ9 =25, DQ10 =49, DQ11 =41

 4254 23:28:25.412866  DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49

 4255 23:28:25.412947  

 4256 23:28:25.413013  

 4257 23:28:25.413073  ==

 4258 23:28:25.415711  Dram Type= 6, Freq= 0, CH_0, rank 1

 4259 23:28:25.418921  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4260 23:28:25.419001  ==

 4261 23:28:25.419066  

 4262 23:28:25.419125  

 4263 23:28:25.422284  	TX Vref Scan disable

 4264 23:28:25.425824   == TX Byte 0 ==

 4265 23:28:25.429018  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4266 23:28:25.432350  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4267 23:28:25.436038   == TX Byte 1 ==

 4268 23:28:25.439201  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4269 23:28:25.442564  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4270 23:28:25.442649  ==

 4271 23:28:25.445406  Dram Type= 6, Freq= 0, CH_0, rank 1

 4272 23:28:25.451879  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4273 23:28:25.451963  ==

 4274 23:28:25.452027  

 4275 23:28:25.452087  

 4276 23:28:25.452144  	TX Vref Scan disable

 4277 23:28:25.456933   == TX Byte 0 ==

 4278 23:28:25.459879  Update DQ  dly =579 (2 ,1, 35)  DQ  OEN =(1 ,6)

 4279 23:28:25.463408  Update DQM dly =579 (2 ,1, 35)  DQM OEN =(1 ,6)

 4280 23:28:25.466680   == TX Byte 1 ==

 4281 23:28:25.469765  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4282 23:28:25.476207  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4283 23:28:25.476288  

 4284 23:28:25.476352  [DATLAT]

 4285 23:28:25.476411  Freq=600, CH0 RK1

 4286 23:28:25.476469  

 4287 23:28:25.479829  DATLAT Default: 0x9

 4288 23:28:25.479910  0, 0xFFFF, sum = 0

 4289 23:28:25.482900  1, 0xFFFF, sum = 0

 4290 23:28:25.482982  2, 0xFFFF, sum = 0

 4291 23:28:25.486210  3, 0xFFFF, sum = 0

 4292 23:28:25.489701  4, 0xFFFF, sum = 0

 4293 23:28:25.489783  5, 0xFFFF, sum = 0

 4294 23:28:25.493219  6, 0xFFFF, sum = 0

 4295 23:28:25.493301  7, 0xFFFF, sum = 0

 4296 23:28:25.496522  8, 0x0, sum = 1

 4297 23:28:25.496604  9, 0x0, sum = 2

 4298 23:28:25.496669  10, 0x0, sum = 3

 4299 23:28:25.500029  11, 0x0, sum = 4

 4300 23:28:25.500111  best_step = 9

 4301 23:28:25.500174  

 4302 23:28:25.500234  ==

 4303 23:28:25.502949  Dram Type= 6, Freq= 0, CH_0, rank 1

 4304 23:28:25.509836  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4305 23:28:25.509917  ==

 4306 23:28:25.509981  RX Vref Scan: 0

 4307 23:28:25.510042  

 4308 23:28:25.513040  RX Vref 0 -> 0, step: 1

 4309 23:28:25.513121  

 4310 23:28:25.516037  RX Delay -179 -> 252, step: 8

 4311 23:28:25.519462  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4312 23:28:25.526032  iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280

 4313 23:28:25.529753  iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288

 4314 23:28:25.533303  iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288

 4315 23:28:25.536455  iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280

 4316 23:28:25.539381  iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280

 4317 23:28:25.546119  iDelay=205, Bit 6, Center 56 (-83 ~ 196) 280

 4318 23:28:25.549483  iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280

 4319 23:28:25.552756  iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288

 4320 23:28:25.556431  iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288

 4321 23:28:25.559559  iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280

 4322 23:28:25.566165  iDelay=205, Bit 11, Center 36 (-107 ~ 180) 288

 4323 23:28:25.569408  iDelay=205, Bit 12, Center 52 (-91 ~ 196) 288

 4324 23:28:25.572593  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4325 23:28:25.575885  iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280

 4326 23:28:25.582763  iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288

 4327 23:28:25.582871  ==

 4328 23:28:25.586133  Dram Type= 6, Freq= 0, CH_0, rank 1

 4329 23:28:25.589520  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4330 23:28:25.589624  ==

 4331 23:28:25.589690  DQS Delay:

 4332 23:28:25.592966  DQS0 = 0, DQS1 = 0

 4333 23:28:25.593046  DQM Delay:

 4334 23:28:25.595653  DQM0 = 54, DQM1 = 46

 4335 23:28:25.595732  DQ Delay:

 4336 23:28:25.599288  DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52

 4337 23:28:25.602466  DQ4 =56, DQ5 =48, DQ6 =56, DQ7 =64

 4338 23:28:25.605694  DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36

 4339 23:28:25.609289  DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52

 4340 23:28:25.609369  

 4341 23:28:25.609432  

 4342 23:28:25.615733  [DQSOSCAuto] RK1, (LSB)MR18= 0x5d1e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps

 4343 23:28:25.619049  CH0 RK1: MR19=808, MR18=5D1E

 4344 23:28:25.625898  CH0_RK1: MR19=0x808, MR18=0x5D1E, DQSOSC=392, MR23=63, INC=170, DEC=113

 4345 23:28:25.629088  [RxdqsGatingPostProcess] freq 600

 4346 23:28:25.635654  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4347 23:28:25.639790  Pre-setting of DQS Precalculation

 4348 23:28:25.642351  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4349 23:28:25.642433  ==

 4350 23:28:25.645754  Dram Type= 6, Freq= 0, CH_1, rank 0

 4351 23:28:25.649553  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4352 23:28:25.649662  ==

 4353 23:28:25.656017  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4354 23:28:25.662720  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4355 23:28:25.665746  [CA 0] Center 36 (5~67) winsize 63

 4356 23:28:25.669101  [CA 1] Center 36 (5~67) winsize 63

 4357 23:28:25.672984  [CA 2] Center 35 (4~66) winsize 63

 4358 23:28:25.675833  [CA 3] Center 34 (4~65) winsize 62

 4359 23:28:25.679513  [CA 4] Center 34 (4~65) winsize 62

 4360 23:28:25.682737  [CA 5] Center 34 (3~65) winsize 63

 4361 23:28:25.682847  

 4362 23:28:25.685925  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4363 23:28:25.686006  

 4364 23:28:25.689116  [CATrainingPosCal] consider 1 rank data

 4365 23:28:25.692658  u2DelayCellTimex100 = 270/100 ps

 4366 23:28:25.696203  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4367 23:28:25.699488  CA1 delay=36 (5~67),Diff = 2 PI (19 cell)

 4368 23:28:25.702849  CA2 delay=35 (4~66),Diff = 1 PI (9 cell)

 4369 23:28:25.705870  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4370 23:28:25.709177  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4371 23:28:25.712668  CA5 delay=34 (3~65),Diff = 0 PI (0 cell)

 4372 23:28:25.712748  

 4373 23:28:25.719183  CA PerBit enable=1, Macro0, CA PI delay=34

 4374 23:28:25.719264  

 4375 23:28:25.719328  [CBTSetCACLKResult] CA Dly = 34

 4376 23:28:25.722626  CS Dly: 6 (0~37)

 4377 23:28:25.722707  ==

 4378 23:28:25.726166  Dram Type= 6, Freq= 0, CH_1, rank 1

 4379 23:28:25.729233  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4380 23:28:25.729314  ==

 4381 23:28:25.735973  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 4382 23:28:25.742533  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 4383 23:28:25.745950  [CA 0] Center 36 (5~67) winsize 63

 4384 23:28:25.749293  [CA 1] Center 36 (6~67) winsize 62

 4385 23:28:25.752533  [CA 2] Center 35 (5~66) winsize 62

 4386 23:28:25.756133  [CA 3] Center 35 (4~66) winsize 63

 4387 23:28:25.759318  [CA 4] Center 35 (4~66) winsize 63

 4388 23:28:25.762425  [CA 5] Center 34 (4~65) winsize 62

 4389 23:28:25.762512  

 4390 23:28:25.765932  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 4391 23:28:25.766017  

 4392 23:28:25.769116  [CATrainingPosCal] consider 2 rank data

 4393 23:28:25.772389  u2DelayCellTimex100 = 270/100 ps

 4394 23:28:25.775343  CA0 delay=36 (5~67),Diff = 2 PI (19 cell)

 4395 23:28:25.779289  CA1 delay=36 (6~67),Diff = 2 PI (19 cell)

 4396 23:28:25.782297  CA2 delay=35 (5~66),Diff = 1 PI (9 cell)

 4397 23:28:25.785356  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 4398 23:28:25.788751  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 4399 23:28:25.795618  CA5 delay=34 (4~65),Diff = 0 PI (0 cell)

 4400 23:28:25.795700  

 4401 23:28:25.798766  CA PerBit enable=1, Macro0, CA PI delay=34

 4402 23:28:25.798849  

 4403 23:28:25.802289  [CBTSetCACLKResult] CA Dly = 34

 4404 23:28:25.802370  CS Dly: 6 (0~37)

 4405 23:28:25.802435  

 4406 23:28:25.805714  ----->DramcWriteLeveling(PI) begin...

 4407 23:28:25.805797  ==

 4408 23:28:25.808852  Dram Type= 6, Freq= 0, CH_1, rank 0

 4409 23:28:25.811927  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4410 23:28:25.815149  ==

 4411 23:28:25.815229  Write leveling (Byte 0): 29 => 29

 4412 23:28:25.818507  Write leveling (Byte 1): 29 => 29

 4413 23:28:25.821922  DramcWriteLeveling(PI) end<-----

 4414 23:28:25.822003  

 4415 23:28:25.822068  ==

 4416 23:28:25.825330  Dram Type= 6, Freq= 0, CH_1, rank 0

 4417 23:28:25.831779  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4418 23:28:25.831861  ==

 4419 23:28:25.835155  [Gating] SW mode calibration

 4420 23:28:25.841938  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4421 23:28:25.845022  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4422 23:28:25.851721   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4423 23:28:25.855197   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4424 23:28:25.858310   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)

 4425 23:28:25.865025   0  9 12 | B1->B0 | 3131 2c2c | 0 1 | (0 1) (1 0)

 4426 23:28:25.868808   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4427 23:28:25.871681   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4428 23:28:25.874990   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4429 23:28:25.881529   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4430 23:28:25.885083   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4431 23:28:25.888555   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4432 23:28:25.895043   0 10  8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 4433 23:28:25.898677   0 10 12 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)

 4434 23:28:25.901865   0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 4435 23:28:25.908816   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4436 23:28:25.912043   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4437 23:28:25.914962   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4438 23:28:25.922068   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4439 23:28:25.924837   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4440 23:28:25.928163   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4441 23:28:25.934839   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4442 23:28:25.938087   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4443 23:28:25.941729   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4444 23:28:25.948406   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4445 23:28:25.951566   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4446 23:28:25.954940   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4447 23:28:25.961719   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4448 23:28:25.964759   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4449 23:28:25.967880   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4450 23:28:25.974806   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4451 23:28:25.978166   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4452 23:28:25.981528   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4453 23:28:25.988177   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4454 23:28:25.991985   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4455 23:28:25.994783   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4456 23:28:26.001522   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4457 23:28:26.004797   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 4458 23:28:26.007746  Total UI for P1: 0, mck2ui 16

 4459 23:28:26.011591  best dqsien dly found for B0: ( 0, 13, 10)

 4460 23:28:26.014842   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4461 23:28:26.017710  Total UI for P1: 0, mck2ui 16

 4462 23:28:26.021155  best dqsien dly found for B1: ( 0, 13, 12)

 4463 23:28:26.024583  best DQS0 dly(MCK, UI, PI) = (0, 13, 10)

 4464 23:28:26.027998  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4465 23:28:26.028080  

 4466 23:28:26.031342  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)

 4467 23:28:26.037812  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4468 23:28:26.037895  [Gating] SW calibration Done

 4469 23:28:26.037961  ==

 4470 23:28:26.041265  Dram Type= 6, Freq= 0, CH_1, rank 0

 4471 23:28:26.047994  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4472 23:28:26.048078  ==

 4473 23:28:26.048143  RX Vref Scan: 0

 4474 23:28:26.048204  

 4475 23:28:26.051111  RX Vref 0 -> 0, step: 1

 4476 23:28:26.051193  

 4477 23:28:26.054545  RX Delay -230 -> 252, step: 16

 4478 23:28:26.057851  iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320

 4479 23:28:26.060922  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4480 23:28:26.064443  iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304

 4481 23:28:26.071073  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4482 23:28:26.074501  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4483 23:28:26.078104  iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320

 4484 23:28:26.080955  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4485 23:28:26.088054  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4486 23:28:26.091149  iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288

 4487 23:28:26.094399  iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288

 4488 23:28:26.097806  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4489 23:28:26.104434  iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304

 4490 23:28:26.107692  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4491 23:28:26.111039  iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304

 4492 23:28:26.114130  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4493 23:28:26.120456  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4494 23:28:26.120541  ==

 4495 23:28:26.124135  Dram Type= 6, Freq= 0, CH_1, rank 0

 4496 23:28:26.127479  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4497 23:28:26.127562  ==

 4498 23:28:26.127629  DQS Delay:

 4499 23:28:26.130757  DQS0 = 0, DQS1 = 0

 4500 23:28:26.130838  DQM Delay:

 4501 23:28:26.134230  DQM0 = 52, DQM1 = 49

 4502 23:28:26.134313  DQ Delay:

 4503 23:28:26.137081  DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49

 4504 23:28:26.140406  DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49

 4505 23:28:26.143795  DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49

 4506 23:28:26.147215  DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57

 4507 23:28:26.147324  

 4508 23:28:26.147417  

 4509 23:28:26.147506  ==

 4510 23:28:26.150446  Dram Type= 6, Freq= 0, CH_1, rank 0

 4511 23:28:26.153867  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4512 23:28:26.153950  ==

 4513 23:28:26.154015  

 4514 23:28:26.157072  

 4515 23:28:26.157154  	TX Vref Scan disable

 4516 23:28:26.160692   == TX Byte 0 ==

 4517 23:28:26.163925  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4518 23:28:26.167284  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4519 23:28:26.170489   == TX Byte 1 ==

 4520 23:28:26.173570  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4521 23:28:26.177223  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4522 23:28:26.177304  ==

 4523 23:28:26.180356  Dram Type= 6, Freq= 0, CH_1, rank 0

 4524 23:28:26.187057  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4525 23:28:26.187138  ==

 4526 23:28:26.187202  

 4527 23:28:26.187262  

 4528 23:28:26.187319  	TX Vref Scan disable

 4529 23:28:26.191626   == TX Byte 0 ==

 4530 23:28:26.194518  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4531 23:28:26.201120  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4532 23:28:26.201206   == TX Byte 1 ==

 4533 23:28:26.204421  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4534 23:28:26.211256  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4535 23:28:26.211337  

 4536 23:28:26.211401  [DATLAT]

 4537 23:28:26.211460  Freq=600, CH1 RK0

 4538 23:28:26.211518  

 4539 23:28:26.214458  DATLAT Default: 0x9

 4540 23:28:26.214539  0, 0xFFFF, sum = 0

 4541 23:28:26.217899  1, 0xFFFF, sum = 0

 4542 23:28:26.221032  2, 0xFFFF, sum = 0

 4543 23:28:26.221114  3, 0xFFFF, sum = 0

 4544 23:28:26.224470  4, 0xFFFF, sum = 0

 4545 23:28:26.224552  5, 0xFFFF, sum = 0

 4546 23:28:26.228118  6, 0xFFFF, sum = 0

 4547 23:28:26.228200  7, 0xFFFF, sum = 0

 4548 23:28:26.231493  8, 0x0, sum = 1

 4549 23:28:26.231576  9, 0x0, sum = 2

 4550 23:28:26.231641  10, 0x0, sum = 3

 4551 23:28:26.234289  11, 0x0, sum = 4

 4552 23:28:26.234371  best_step = 9

 4553 23:28:26.234435  

 4554 23:28:26.234495  ==

 4555 23:28:26.238057  Dram Type= 6, Freq= 0, CH_1, rank 0

 4556 23:28:26.244276  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4557 23:28:26.244357  ==

 4558 23:28:26.244422  RX Vref Scan: 1

 4559 23:28:26.244481  

 4560 23:28:26.247838  RX Vref 0 -> 0, step: 1

 4561 23:28:26.247919  

 4562 23:28:26.251172  RX Delay -147 -> 252, step: 8

 4563 23:28:26.251253  

 4564 23:28:26.254567  Set Vref, RX VrefLevel [Byte0]: 53

 4565 23:28:26.258123                           [Byte1]: 55

 4566 23:28:26.258204  

 4567 23:28:26.261077  Final RX Vref Byte 0 = 53 to rank0

 4568 23:28:26.264416  Final RX Vref Byte 1 = 55 to rank0

 4569 23:28:26.267779  Final RX Vref Byte 0 = 53 to rank1

 4570 23:28:26.270939  Final RX Vref Byte 1 = 55 to rank1==

 4571 23:28:26.274089  Dram Type= 6, Freq= 0, CH_1, rank 0

 4572 23:28:26.277518  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4573 23:28:26.277624  ==

 4574 23:28:26.281022  DQS Delay:

 4575 23:28:26.281103  DQS0 = 0, DQS1 = 0

 4576 23:28:26.281167  DQM Delay:

 4577 23:28:26.284553  DQM0 = 48, DQM1 = 44

 4578 23:28:26.284634  DQ Delay:

 4579 23:28:26.287481  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4580 23:28:26.290797  DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48

 4581 23:28:26.294490  DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36

 4582 23:28:26.297374  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52

 4583 23:28:26.297456  

 4584 23:28:26.297519  

 4585 23:28:26.307380  [DQSOSCAuto] RK0, (LSB)MR18= 0x4268, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps

 4586 23:28:26.310991  CH1 RK0: MR19=808, MR18=4268

 4587 23:28:26.314337  CH1_RK0: MR19=0x808, MR18=0x4268, DQSOSC=390, MR23=63, INC=172, DEC=114

 4588 23:28:26.317483  

 4589 23:28:26.320764  ----->DramcWriteLeveling(PI) begin...

 4590 23:28:26.320846  ==

 4591 23:28:26.324035  Dram Type= 6, Freq= 0, CH_1, rank 1

 4592 23:28:26.327549  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4593 23:28:26.327631  ==

 4594 23:28:26.330834  Write leveling (Byte 0): 29 => 29

 4595 23:28:26.334019  Write leveling (Byte 1): 29 => 29

 4596 23:28:26.337772  DramcWriteLeveling(PI) end<-----

 4597 23:28:26.337856  

 4598 23:28:26.337920  ==

 4599 23:28:26.340563  Dram Type= 6, Freq= 0, CH_1, rank 1

 4600 23:28:26.343900  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4601 23:28:26.343983  ==

 4602 23:28:26.347231  [Gating] SW mode calibration

 4603 23:28:26.353973  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0

 4604 23:28:26.360992  RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)

 4605 23:28:26.364695   0  9  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4606 23:28:26.368224   0  9  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4607 23:28:26.374220   0  9  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 4608 23:28:26.377525   0  9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (1 1)

 4609 23:28:26.380734   0  9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4610 23:28:26.384125   0  9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4611 23:28:26.391180   0  9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4612 23:28:26.394305   0  9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4613 23:28:26.397423   0 10  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4614 23:28:26.404288   0 10  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 4615 23:28:26.407477   0 10  8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 4616 23:28:26.411130   0 10 12 | B1->B0 | 3636 3838 | 0 1 | (0 0) (1 1)

 4617 23:28:26.417803   0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4618 23:28:26.421000   0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4619 23:28:26.424730   0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4620 23:28:26.431521   0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4621 23:28:26.434598   0 11  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4622 23:28:26.437558   0 11  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4623 23:28:26.444878   0 11  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 4624 23:28:26.448000   0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 4625 23:28:26.451430   0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4626 23:28:26.457735   0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4627 23:28:26.460624   0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4628 23:28:26.464054   0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4629 23:28:26.470819   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4630 23:28:26.474113   0 12  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4631 23:28:26.477458   0 12  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4632 23:28:26.484782   0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4633 23:28:26.487398   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4634 23:28:26.491126   0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4635 23:28:26.497380   0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4636 23:28:26.500404   0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4637 23:28:26.504214   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4638 23:28:26.510897   0 13  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4639 23:28:26.513778   0 13  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 4640 23:28:26.517149   0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)

 4641 23:28:26.520746   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 4642 23:28:26.524007  Total UI for P1: 0, mck2ui 16

 4643 23:28:26.527279  best dqsien dly found for B0: ( 0, 13, 14)

 4644 23:28:26.530687  Total UI for P1: 0, mck2ui 16

 4645 23:28:26.534102  best dqsien dly found for B1: ( 0, 13, 12)

 4646 23:28:26.537269  best DQS0 dly(MCK, UI, PI) = (0, 13, 14)

 4647 23:28:26.544363  best DQS1 dly(MCK, UI, PI) = (0, 13, 12)

 4648 23:28:26.544939  

 4649 23:28:26.547643  best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)

 4650 23:28:26.550711  best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)

 4651 23:28:26.553639  [Gating] SW calibration Done

 4652 23:28:26.554124  ==

 4653 23:28:26.557129  Dram Type= 6, Freq= 0, CH_1, rank 1

 4654 23:28:26.560573  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4655 23:28:26.561056  ==

 4656 23:28:26.564127  RX Vref Scan: 0

 4657 23:28:26.564606  

 4658 23:28:26.565088  RX Vref 0 -> 0, step: 1

 4659 23:28:26.565543  

 4660 23:28:26.567462  RX Delay -230 -> 252, step: 16

 4661 23:28:26.570247  iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304

 4662 23:28:26.576991  iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304

 4663 23:28:26.580805  iDelay=218, Bit 2, Center 41 (-102 ~ 185) 288

 4664 23:28:26.584125  iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304

 4665 23:28:26.586879  iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304

 4666 23:28:26.590229  iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304

 4667 23:28:26.597169  iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320

 4668 23:28:26.600300  iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304

 4669 23:28:26.603888  iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288

 4670 23:28:26.607601  iDelay=218, Bit 9, Center 49 (-102 ~ 201) 304

 4671 23:28:26.613513  iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304

 4672 23:28:26.616855  iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304

 4673 23:28:26.619892  iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320

 4674 23:28:26.623369  iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320

 4675 23:28:26.629952  iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304

 4676 23:28:26.633149  iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320

 4677 23:28:26.633807  ==

 4678 23:28:26.636597  Dram Type= 6, Freq= 0, CH_1, rank 1

 4679 23:28:26.639765  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4680 23:28:26.640341  ==

 4681 23:28:26.643299  DQS Delay:

 4682 23:28:26.643877  DQS0 = 0, DQS1 = 0

 4683 23:28:26.644398  DQM Delay:

 4684 23:28:26.646437  DQM0 = 51, DQM1 = 51

 4685 23:28:26.647017  DQ Delay:

 4686 23:28:26.649532  DQ0 =49, DQ1 =49, DQ2 =41, DQ3 =49

 4687 23:28:26.653308  DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49

 4688 23:28:26.656382  DQ8 =41, DQ9 =49, DQ10 =49, DQ11 =49

 4689 23:28:26.660027  DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57

 4690 23:28:26.660596  

 4691 23:28:26.661014  

 4692 23:28:26.661537  ==

 4693 23:28:26.663198  Dram Type= 6, Freq= 0, CH_1, rank 1

 4694 23:28:26.669767  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4695 23:28:26.670264  ==

 4696 23:28:26.670646  

 4697 23:28:26.670998  

 4698 23:28:26.671477  	TX Vref Scan disable

 4699 23:28:26.673335   == TX Byte 0 ==

 4700 23:28:26.676894  Update DQ  dly =575 (2 ,1, 31)  DQ  OEN =(1 ,6)

 4701 23:28:26.680141  Update DQM dly =575 (2 ,1, 31)  DQM OEN =(1 ,6)

 4702 23:28:26.683623   == TX Byte 1 ==

 4703 23:28:26.686475  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4704 23:28:26.693188  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4705 23:28:26.693797  ==

 4706 23:28:26.696721  Dram Type= 6, Freq= 0, CH_1, rank 1

 4707 23:28:26.699971  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4708 23:28:26.700502  ==

 4709 23:28:26.700974  

 4710 23:28:26.701501  

 4711 23:28:26.702965  	TX Vref Scan disable

 4712 23:28:26.706425   == TX Byte 0 ==

 4713 23:28:26.709629  Update DQ  dly =574 (2 ,1, 30)  DQ  OEN =(1 ,6)

 4714 23:28:26.712976  Update DQM dly =574 (2 ,1, 30)  DQM OEN =(1 ,6)

 4715 23:28:26.716398   == TX Byte 1 ==

 4716 23:28:26.719940  Update DQ  dly =573 (2 ,1, 29)  DQ  OEN =(1 ,6)

 4717 23:28:26.723307  Update DQM dly =573 (2 ,1, 29)  DQM OEN =(1 ,6)

 4718 23:28:26.723900  

 4719 23:28:26.724302  [DATLAT]

 4720 23:28:26.726767  Freq=600, CH1 RK1

 4721 23:28:26.727243  

 4722 23:28:26.727679  DATLAT Default: 0x9

 4723 23:28:26.729965  0, 0xFFFF, sum = 0

 4724 23:28:26.730423  1, 0xFFFF, sum = 0

 4725 23:28:26.733013  2, 0xFFFF, sum = 0

 4726 23:28:26.733643  3, 0xFFFF, sum = 0

 4727 23:28:26.736623  4, 0xFFFF, sum = 0

 4728 23:28:26.740152  5, 0xFFFF, sum = 0

 4729 23:28:26.740785  6, 0xFFFF, sum = 0

 4730 23:28:26.743421  7, 0xFFFF, sum = 0

 4731 23:28:26.743887  8, 0x0, sum = 1

 4732 23:28:26.744386  9, 0x0, sum = 2

 4733 23:28:26.746959  10, 0x0, sum = 3

 4734 23:28:26.747449  11, 0x0, sum = 4

 4735 23:28:26.749669  best_step = 9

 4736 23:28:26.750252  

 4737 23:28:26.750759  ==

 4738 23:28:26.753122  Dram Type= 6, Freq= 0, CH_1, rank 1

 4739 23:28:26.756586  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4740 23:28:26.757050  ==

 4741 23:28:26.760292  RX Vref Scan: 0

 4742 23:28:26.760874  

 4743 23:28:26.761384  RX Vref 0 -> 0, step: 1

 4744 23:28:26.761968  

 4745 23:28:26.763076  RX Delay -147 -> 252, step: 8

 4746 23:28:26.770064  iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288

 4747 23:28:26.773607  iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288

 4748 23:28:26.776720  iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288

 4749 23:28:26.779901  iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288

 4750 23:28:26.786820  iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288

 4751 23:28:26.789971  iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288

 4752 23:28:26.793631  iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288

 4753 23:28:26.796885  iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296

 4754 23:28:26.800281  iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296

 4755 23:28:26.806627  iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296

 4756 23:28:26.810301  iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296

 4757 23:28:26.813546  iDelay=205, Bit 11, Center 36 (-115 ~ 188) 304

 4758 23:28:26.816407  iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304

 4759 23:28:26.819778  iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288

 4760 23:28:26.826652  iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288

 4761 23:28:26.829987  iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296

 4762 23:28:26.830406  ==

 4763 23:28:26.833410  Dram Type= 6, Freq= 0, CH_1, rank 1

 4764 23:28:26.836675  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 4765 23:28:26.837100  ==

 4766 23:28:26.840027  DQS Delay:

 4767 23:28:26.840568  DQS0 = 0, DQS1 = 0

 4768 23:28:26.840914  DQM Delay:

 4769 23:28:26.843220  DQM0 = 48, DQM1 = 45

 4770 23:28:26.843639  DQ Delay:

 4771 23:28:26.846819  DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44

 4772 23:28:26.850078  DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48

 4773 23:28:26.853472  DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =36

 4774 23:28:26.856683  DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56

 4775 23:28:26.857101  

 4776 23:28:26.857431  

 4777 23:28:26.866705  [DQSOSCAuto] RK1, (LSB)MR18= 0x691f, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps

 4778 23:28:26.867131  CH1 RK1: MR19=808, MR18=691F

 4779 23:28:26.873006  CH1_RK1: MR19=0x808, MR18=0x691F, DQSOSC=390, MR23=63, INC=172, DEC=114

 4780 23:28:26.876470  [RxdqsGatingPostProcess] freq 600

 4781 23:28:26.882920  ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1

 4782 23:28:26.886499  Pre-setting of DQS Precalculation

 4783 23:28:26.889648  [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9

 4784 23:28:26.896566  sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5

 4785 23:28:26.906097  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 4786 23:28:26.906517  

 4787 23:28:26.906850  

 4788 23:28:26.909654  [Calibration Summary] 1200 Mbps

 4789 23:28:26.910080  CH 0, Rank 0

 4790 23:28:26.913250  SW Impedance     : PASS

 4791 23:28:26.913714  DUTY Scan        : NO K

 4792 23:28:26.916277  ZQ Calibration   : PASS

 4793 23:28:26.919621  Jitter Meter     : NO K

 4794 23:28:26.920039  CBT Training     : PASS

 4795 23:28:26.923079  Write leveling   : PASS

 4796 23:28:26.923499  RX DQS gating    : PASS

 4797 23:28:26.926551  RX DQ/DQS(RDDQC) : PASS

 4798 23:28:26.929320  TX DQ/DQS        : PASS

 4799 23:28:26.929767  RX DATLAT        : PASS

 4800 23:28:26.933096  RX DQ/DQS(Engine): PASS

 4801 23:28:26.935820  TX OE            : NO K

 4802 23:28:26.935902  All Pass.

 4803 23:28:26.935967  

 4804 23:28:26.936026  CH 0, Rank 1

 4805 23:28:26.938991  SW Impedance     : PASS

 4806 23:28:26.942296  DUTY Scan        : NO K

 4807 23:28:26.942378  ZQ Calibration   : PASS

 4808 23:28:26.945791  Jitter Meter     : NO K

 4809 23:28:26.949028  CBT Training     : PASS

 4810 23:28:26.949110  Write leveling   : PASS

 4811 23:28:26.952278  RX DQS gating    : PASS

 4812 23:28:26.956366  RX DQ/DQS(RDDQC) : PASS

 4813 23:28:26.956447  TX DQ/DQS        : PASS

 4814 23:28:26.958880  RX DATLAT        : PASS

 4815 23:28:26.962118  RX DQ/DQS(Engine): PASS

 4816 23:28:26.962199  TX OE            : NO K

 4817 23:28:26.962265  All Pass.

 4818 23:28:26.965532  

 4819 23:28:26.965655  CH 1, Rank 0

 4820 23:28:26.968861  SW Impedance     : PASS

 4821 23:28:26.968943  DUTY Scan        : NO K

 4822 23:28:26.972387  ZQ Calibration   : PASS

 4823 23:28:26.975671  Jitter Meter     : NO K

 4824 23:28:26.975753  CBT Training     : PASS

 4825 23:28:26.978874  Write leveling   : PASS

 4826 23:28:26.978957  RX DQS gating    : PASS

 4827 23:28:26.982387  RX DQ/DQS(RDDQC) : PASS

 4828 23:28:26.985855  TX DQ/DQS        : PASS

 4829 23:28:26.985937  RX DATLAT        : PASS

 4830 23:28:26.988890  RX DQ/DQS(Engine): PASS

 4831 23:28:26.992591  TX OE            : NO K

 4832 23:28:26.992673  All Pass.

 4833 23:28:26.992738  

 4834 23:28:26.992799  CH 1, Rank 1

 4835 23:28:26.995784  SW Impedance     : PASS

 4836 23:28:26.999173  DUTY Scan        : NO K

 4837 23:28:26.999255  ZQ Calibration   : PASS

 4838 23:28:27.002349  Jitter Meter     : NO K

 4839 23:28:27.006181  CBT Training     : PASS

 4840 23:28:27.006262  Write leveling   : PASS

 4841 23:28:27.008768  RX DQS gating    : PASS

 4842 23:28:27.012681  RX DQ/DQS(RDDQC) : PASS

 4843 23:28:27.012763  TX DQ/DQS        : PASS

 4844 23:28:27.015773  RX DATLAT        : PASS

 4845 23:28:27.019180  RX DQ/DQS(Engine): PASS

 4846 23:28:27.019261  TX OE            : NO K

 4847 23:28:27.019326  All Pass.

 4848 23:28:27.022067  

 4849 23:28:27.022148  DramC Write-DBI off

 4850 23:28:27.025422  	PER_BANK_REFRESH: Hybrid Mode

 4851 23:28:27.025503  TX_TRACKING: ON

 4852 23:28:27.035796  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1

 4853 23:28:27.038700  [FAST_K] Save calibration result to emmc

 4854 23:28:27.042140  dramc_set_vcore_voltage set vcore to 662500

 4855 23:28:27.045421  Read voltage for 933, 3

 4856 23:28:27.045529  Vio18 = 0

 4857 23:28:27.048988  Vcore = 662500

 4858 23:28:27.049069  Vdram = 0

 4859 23:28:27.049134  Vddq = 0

 4860 23:28:27.049194  Vmddr = 0

 4861 23:28:27.055485  [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0

 4862 23:28:27.058739  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 4863 23:28:27.062362  MEM_TYPE=3, freq_sel=17

 4864 23:28:27.065311  sv_algorithm_assistance_LP4_1600 

 4865 23:28:27.068660  ============ PULL DRAM RESETB DOWN ============

 4866 23:28:27.075518  ========== PULL DRAM RESETB DOWN end =========

 4867 23:28:27.078741  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4868 23:28:27.081869  =================================== 

 4869 23:28:27.085400  LPDDR4 DRAM CONFIGURATION

 4870 23:28:27.088398  =================================== 

 4871 23:28:27.088480  EX_ROW_EN[0]    = 0x0

 4872 23:28:27.091857  EX_ROW_EN[1]    = 0x0

 4873 23:28:27.091938  LP4Y_EN      = 0x0

 4874 23:28:27.095471  WORK_FSP     = 0x0

 4875 23:28:27.095553  WL           = 0x3

 4876 23:28:27.098404  RL           = 0x3

 4877 23:28:27.098486  BL           = 0x2

 4878 23:28:27.101560  RPST         = 0x0

 4879 23:28:27.104821  RD_PRE       = 0x0

 4880 23:28:27.104901  WR_PRE       = 0x1

 4881 23:28:27.108265  WR_PST       = 0x0

 4882 23:28:27.108346  DBI_WR       = 0x0

 4883 23:28:27.111817  DBI_RD       = 0x0

 4884 23:28:27.111898  OTF          = 0x1

 4885 23:28:27.115075  =================================== 

 4886 23:28:27.118157  =================================== 

 4887 23:28:27.121378  ANA top config

 4888 23:28:27.125021  =================================== 

 4889 23:28:27.125102  DLL_ASYNC_EN            =  0

 4890 23:28:27.128165  ALL_SLAVE_EN            =  1

 4891 23:28:27.131430  NEW_RANK_MODE           =  1

 4892 23:28:27.134715  DLL_IDLE_MODE           =  1

 4893 23:28:27.134796  LP45_APHY_COMB_EN       =  1

 4894 23:28:27.138554  TX_ODT_DIS              =  1

 4895 23:28:27.141571  NEW_8X_MODE             =  1

 4896 23:28:27.144893  =================================== 

 4897 23:28:27.148104  =================================== 

 4898 23:28:27.151541  data_rate                  = 1866

 4899 23:28:27.154696  CKR                        = 1

 4900 23:28:27.157984  DQ_P2S_RATIO               = 8

 4901 23:28:27.161216  =================================== 

 4902 23:28:27.161330  CA_P2S_RATIO               = 8

 4903 23:28:27.164771  DQ_CA_OPEN                 = 0

 4904 23:28:27.168193  DQ_SEMI_OPEN               = 0

 4905 23:28:27.171347  CA_SEMI_OPEN               = 0

 4906 23:28:27.174804  CA_FULL_RATE               = 0

 4907 23:28:27.174906  DQ_CKDIV4_EN               = 1

 4908 23:28:27.178165  CA_CKDIV4_EN               = 1

 4909 23:28:27.181598  CA_PREDIV_EN               = 0

 4910 23:28:27.184474  PH8_DLY                    = 0

 4911 23:28:27.187775  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 4912 23:28:27.191254  DQ_AAMCK_DIV               = 4

 4913 23:28:27.191335  CA_AAMCK_DIV               = 4

 4914 23:28:27.194756  CA_ADMCK_DIV               = 4

 4915 23:28:27.198468  DQ_TRACK_CA_EN             = 0

 4916 23:28:27.201285  CA_PICK                    = 933

 4917 23:28:27.204705  CA_MCKIO                   = 933

 4918 23:28:27.207689  MCKIO_SEMI                 = 0

 4919 23:28:27.210982  PLL_FREQ                   = 3732

 4920 23:28:27.211064  DQ_UI_PI_RATIO             = 32

 4921 23:28:27.214782  CA_UI_PI_RATIO             = 0

 4922 23:28:27.218324  =================================== 

 4923 23:28:27.221348  =================================== 

 4924 23:28:27.224168  memory_type:LPDDR4         

 4925 23:28:27.227651  GP_NUM     : 10       

 4926 23:28:27.227733  SRAM_EN    : 1       

 4927 23:28:27.230916  MD32_EN    : 0       

 4928 23:28:27.234407  =================================== 

 4929 23:28:27.237690  [ANA_INIT] >>>>>>>>>>>>>> 

 4930 23:28:27.241264  <<<<<< [CONFIGURE PHASE]: ANA_TX

 4931 23:28:27.244400  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 4932 23:28:27.247343  =================================== 

 4933 23:28:27.247425  data_rate = 1866,PCW = 0X8f00

 4934 23:28:27.250703  =================================== 

 4935 23:28:27.254197  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 4936 23:28:27.260719  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4937 23:28:27.267641  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 4938 23:28:27.270653  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 4939 23:28:27.274050  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 4940 23:28:27.277528  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 4941 23:28:27.280511  [ANA_INIT] flow start 

 4942 23:28:27.280593  [ANA_INIT] PLL >>>>>>>> 

 4943 23:28:27.284088  [ANA_INIT] PLL <<<<<<<< 

 4944 23:28:27.287651  [ANA_INIT] MIDPI >>>>>>>> 

 4945 23:28:27.290872  [ANA_INIT] MIDPI <<<<<<<< 

 4946 23:28:27.290954  [ANA_INIT] DLL >>>>>>>> 

 4947 23:28:27.293744  [ANA_INIT] flow end 

 4948 23:28:27.297094  ============ LP4 DIFF to SE enter ============

 4949 23:28:27.300509  ============ LP4 DIFF to SE exit  ============

 4950 23:28:27.303952  [ANA_INIT] <<<<<<<<<<<<< 

 4951 23:28:27.307354  [Flow] Enable top DCM control >>>>> 

 4952 23:28:27.310602  [Flow] Enable top DCM control <<<<< 

 4953 23:28:27.313908  Enable DLL master slave shuffle 

 4954 23:28:27.320579  ============================================================== 

 4955 23:28:27.320662  Gating Mode config

 4956 23:28:27.327091  ============================================================== 

 4957 23:28:27.327174  Config description: 

 4958 23:28:27.336799  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 4959 23:28:27.343449  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 4960 23:28:27.349965  SELPH_MODE            0: By rank         1: By Phase 

 4961 23:28:27.353818  ============================================================== 

 4962 23:28:27.356601  GAT_TRACK_EN                 =  1

 4963 23:28:27.359986  RX_GATING_MODE               =  2

 4964 23:28:27.363498  RX_GATING_TRACK_MODE         =  2

 4965 23:28:27.367103  SELPH_MODE                   =  1

 4966 23:28:27.370002  PICG_EARLY_EN                =  1

 4967 23:28:27.373396  VALID_LAT_VALUE              =  1

 4968 23:28:27.379680  ============================================================== 

 4969 23:28:27.383351  Enter into Gating configuration >>>> 

 4970 23:28:27.386552  Exit from Gating configuration <<<< 

 4971 23:28:27.389767  Enter into  DVFS_PRE_config >>>>> 

 4972 23:28:27.399853  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 4973 23:28:27.403247  Exit from  DVFS_PRE_config <<<<< 

 4974 23:28:27.406443  Enter into PICG configuration >>>> 

 4975 23:28:27.409958  Exit from PICG configuration <<<< 

 4976 23:28:27.413037  [RX_INPUT] configuration >>>>> 

 4977 23:28:27.413119  [RX_INPUT] configuration <<<<< 

 4978 23:28:27.419635  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 4979 23:28:27.426100  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 4980 23:28:27.429294  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 4981 23:28:27.436500  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 4982 23:28:27.442698  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 4983 23:28:27.449347  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 4984 23:28:27.452779  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 4985 23:28:27.456271  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 4986 23:28:27.462930  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 4987 23:28:27.465998  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 4988 23:28:27.469292  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 4989 23:28:27.475982  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 4990 23:28:27.479501  =================================== 

 4991 23:28:27.479585  LPDDR4 DRAM CONFIGURATION

 4992 23:28:27.482656  =================================== 

 4993 23:28:27.485909  EX_ROW_EN[0]    = 0x0

 4994 23:28:27.485990  EX_ROW_EN[1]    = 0x0

 4995 23:28:27.489472  LP4Y_EN      = 0x0

 4996 23:28:27.492596  WORK_FSP     = 0x0

 4997 23:28:27.492679  WL           = 0x3

 4998 23:28:27.495583  RL           = 0x3

 4999 23:28:27.495665  BL           = 0x2

 5000 23:28:27.499139  RPST         = 0x0

 5001 23:28:27.499222  RD_PRE       = 0x0

 5002 23:28:27.502909  WR_PRE       = 0x1

 5003 23:28:27.502991  WR_PST       = 0x0

 5004 23:28:27.505492  DBI_WR       = 0x0

 5005 23:28:27.505636  DBI_RD       = 0x0

 5006 23:28:27.508945  OTF          = 0x1

 5007 23:28:27.512128  =================================== 

 5008 23:28:27.515612  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 5009 23:28:27.518869  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 5010 23:28:27.522668  [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3

 5011 23:28:27.526008  =================================== 

 5012 23:28:27.528871  LPDDR4 DRAM CONFIGURATION

 5013 23:28:27.532221  =================================== 

 5014 23:28:27.535920  EX_ROW_EN[0]    = 0x10

 5015 23:28:27.536001  EX_ROW_EN[1]    = 0x0

 5016 23:28:27.538720  LP4Y_EN      = 0x0

 5017 23:28:27.538802  WORK_FSP     = 0x0

 5018 23:28:27.542522  WL           = 0x3

 5019 23:28:27.542605  RL           = 0x3

 5020 23:28:27.545763  BL           = 0x2

 5021 23:28:27.545845  RPST         = 0x0

 5022 23:28:27.548840  RD_PRE       = 0x0

 5023 23:28:27.552417  WR_PRE       = 0x1

 5024 23:28:27.552499  WR_PST       = 0x0

 5025 23:28:27.555601  DBI_WR       = 0x0

 5026 23:28:27.555683  DBI_RD       = 0x0

 5027 23:28:27.558635  OTF          = 0x1

 5028 23:28:27.562234  =================================== 

 5029 23:28:27.565346  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 5030 23:28:27.570836  nWR fixed to 30

 5031 23:28:27.574381  [ModeRegInit_LP4] CH0 RK0

 5032 23:28:27.574463  [ModeRegInit_LP4] CH0 RK1

 5033 23:28:27.577493  [ModeRegInit_LP4] CH1 RK0

 5034 23:28:27.580716  [ModeRegInit_LP4] CH1 RK1

 5035 23:28:27.580798  match AC timing 9

 5036 23:28:27.587273  dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1

 5037 23:28:27.590485  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 5038 23:28:27.593654  [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10

 5039 23:28:27.600689  [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21

 5040 23:28:27.603857  [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)

 5041 23:28:27.603955  ==

 5042 23:28:27.607328  Dram Type= 6, Freq= 0, CH_0, rank 0

 5043 23:28:27.610807  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5044 23:28:27.610893  ==

 5045 23:28:27.617334  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5046 23:28:27.623874  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 5047 23:28:27.627180  [CA 0] Center 37 (6~68) winsize 63

 5048 23:28:27.630159  [CA 1] Center 37 (6~68) winsize 63

 5049 23:28:27.633734  [CA 2] Center 34 (4~65) winsize 62

 5050 23:28:27.637083  [CA 3] Center 34 (3~65) winsize 63

 5051 23:28:27.640555  [CA 4] Center 33 (3~64) winsize 62

 5052 23:28:27.643650  [CA 5] Center 32 (2~62) winsize 61

 5053 23:28:27.643734  

 5054 23:28:27.646887  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 5055 23:28:27.646969  

 5056 23:28:27.650552  [CATrainingPosCal] consider 1 rank data

 5057 23:28:27.653791  u2DelayCellTimex100 = 270/100 ps

 5058 23:28:27.657146  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5059 23:28:27.660750  CA1 delay=37 (6~68),Diff = 5 PI (31 cell)

 5060 23:28:27.663424  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5061 23:28:27.666718  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5062 23:28:27.670142  CA4 delay=33 (3~64),Diff = 1 PI (6 cell)

 5063 23:28:27.676678  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5064 23:28:27.676760  

 5065 23:28:27.680036  CA PerBit enable=1, Macro0, CA PI delay=32

 5066 23:28:27.680118  

 5067 23:28:27.683462  [CBTSetCACLKResult] CA Dly = 32

 5068 23:28:27.683544  CS Dly: 5 (0~36)

 5069 23:28:27.683609  ==

 5070 23:28:27.686675  Dram Type= 6, Freq= 0, CH_0, rank 1

 5071 23:28:27.690156  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5072 23:28:27.693495  ==

 5073 23:28:27.696516  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5074 23:28:27.703267  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5075 23:28:27.706702  [CA 0] Center 37 (6~68) winsize 63

 5076 23:28:27.710164  [CA 1] Center 37 (6~68) winsize 63

 5077 23:28:27.713074  [CA 2] Center 34 (4~65) winsize 62

 5078 23:28:27.716645  [CA 3] Center 34 (3~65) winsize 63

 5079 23:28:27.719815  [CA 4] Center 32 (2~63) winsize 62

 5080 23:28:27.723079  [CA 5] Center 32 (2~62) winsize 61

 5081 23:28:27.723162  

 5082 23:28:27.726670  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5083 23:28:27.726752  

 5084 23:28:27.729556  [CATrainingPosCal] consider 2 rank data

 5085 23:28:27.733012  u2DelayCellTimex100 = 270/100 ps

 5086 23:28:27.736381  CA0 delay=37 (6~68),Diff = 5 PI (31 cell)

 5087 23:28:27.739641  CA1 delay=37 (6~68),Diff = 5 PI (31 cell)

 5088 23:28:27.743070  CA2 delay=34 (4~65),Diff = 2 PI (12 cell)

 5089 23:28:27.749536  CA3 delay=34 (3~65),Diff = 2 PI (12 cell)

 5090 23:28:27.753109  CA4 delay=33 (3~63),Diff = 1 PI (6 cell)

 5091 23:28:27.756608  CA5 delay=32 (2~62),Diff = 0 PI (0 cell)

 5092 23:28:27.756690  

 5093 23:28:27.759309  CA PerBit enable=1, Macro0, CA PI delay=32

 5094 23:28:27.759437  

 5095 23:28:27.763197  [CBTSetCACLKResult] CA Dly = 32

 5096 23:28:27.763282  CS Dly: 5 (0~37)

 5097 23:28:27.763414  

 5098 23:28:27.766213  ----->DramcWriteLeveling(PI) begin...

 5099 23:28:27.769486  ==

 5100 23:28:27.773270  Dram Type= 6, Freq= 0, CH_0, rank 0

 5101 23:28:27.775974  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5102 23:28:27.776057  ==

 5103 23:28:27.779324  Write leveling (Byte 0): 32 => 32

 5104 23:28:27.782541  Write leveling (Byte 1): 30 => 30

 5105 23:28:27.786133  DramcWriteLeveling(PI) end<-----

 5106 23:28:27.786214  

 5107 23:28:27.786279  ==

 5108 23:28:27.789385  Dram Type= 6, Freq= 0, CH_0, rank 0

 5109 23:28:27.792632  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5110 23:28:27.792714  ==

 5111 23:28:27.795928  [Gating] SW mode calibration

 5112 23:28:27.802742  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5113 23:28:27.809173  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5114 23:28:27.812582   0 14  0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)

 5115 23:28:27.815900   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5116 23:28:27.819454   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5117 23:28:27.826048   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5118 23:28:27.829336   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5119 23:28:27.832573   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5120 23:28:27.839494   0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)

 5121 23:28:27.842376   0 14 28 | B1->B0 | 3434 2727 | 0 0 | (0 0) (0 0)

 5122 23:28:27.846196   0 15  0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)

 5123 23:28:27.852643   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5124 23:28:27.855907   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5125 23:28:27.859000   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5126 23:28:27.865597   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5127 23:28:27.869359   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5128 23:28:27.872308   0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 5129 23:28:27.879277   0 15 28 | B1->B0 | 2424 3939 | 0 0 | (0 0) (0 0)

 5130 23:28:27.882219   1  0  0 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)

 5131 23:28:27.885707   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5132 23:28:27.892810   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5133 23:28:27.895563   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5134 23:28:27.898693   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5135 23:28:27.905520   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5136 23:28:27.909133   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5137 23:28:27.912529   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5138 23:28:27.918784   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5139 23:28:27.922731   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 5140 23:28:27.926232   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5141 23:28:27.928893   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5142 23:28:27.935652   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5143 23:28:27.939152   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5144 23:28:27.942383   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5145 23:28:27.949041   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5146 23:28:27.952662   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5147 23:28:27.955832   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5148 23:28:27.962444   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5149 23:28:27.966001   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5150 23:28:27.969072   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5151 23:28:27.975540   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5152 23:28:27.979123   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5153 23:28:27.982092   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5154 23:28:27.988687   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5155 23:28:27.988769  Total UI for P1: 0, mck2ui 16

 5156 23:28:27.995471  best dqsien dly found for B0: ( 1,  2, 28)

 5157 23:28:27.995554  Total UI for P1: 0, mck2ui 16

 5158 23:28:28.002071  best dqsien dly found for B1: ( 1,  2, 30)

 5159 23:28:28.005353  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5160 23:28:28.008767  best DQS1 dly(MCK, UI, PI) = (1, 2, 30)

 5161 23:28:28.008849  

 5162 23:28:28.012090  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5163 23:28:28.015568  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)

 5164 23:28:28.019017  [Gating] SW calibration Done

 5165 23:28:28.019099  ==

 5166 23:28:28.022195  Dram Type= 6, Freq= 0, CH_0, rank 0

 5167 23:28:28.025341  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5168 23:28:28.025423  ==

 5169 23:28:28.028958  RX Vref Scan: 0

 5170 23:28:28.029039  

 5171 23:28:28.029105  RX Vref 0 -> 0, step: 1

 5172 23:28:28.029166  

 5173 23:28:28.031927  RX Delay -80 -> 252, step: 8

 5174 23:28:28.035229  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5175 23:28:28.042014  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5176 23:28:28.045524  iDelay=208, Bit 2, Center 99 (8 ~ 191) 184

 5177 23:28:28.048787  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5178 23:28:28.052270  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5179 23:28:28.055625  iDelay=208, Bit 5, Center 95 (8 ~ 183) 176

 5180 23:28:28.058558  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5181 23:28:28.065184  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5182 23:28:28.068513  iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184

 5183 23:28:28.071879  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5184 23:28:28.075778  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5185 23:28:28.079025  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5186 23:28:28.081881  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5187 23:28:28.088504  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5188 23:28:28.091737  iDelay=208, Bit 14, Center 103 (8 ~ 199) 192

 5189 23:28:28.095034  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5190 23:28:28.095116  ==

 5191 23:28:28.098292  Dram Type= 6, Freq= 0, CH_0, rank 0

 5192 23:28:28.102057  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5193 23:28:28.102140  ==

 5194 23:28:28.105117  DQS Delay:

 5195 23:28:28.105198  DQS0 = 0, DQS1 = 0

 5196 23:28:28.108536  DQM Delay:

 5197 23:28:28.108618  DQM0 = 105, DQM1 = 94

 5198 23:28:28.108684  DQ Delay:

 5199 23:28:28.111727  DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99

 5200 23:28:28.115079  DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115

 5201 23:28:28.118336  DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87

 5202 23:28:28.124958  DQ12 =99, DQ13 =99, DQ14 =103, DQ15 =99

 5203 23:28:28.125040  

 5204 23:28:28.125105  

 5205 23:28:28.125165  ==

 5206 23:28:28.128103  Dram Type= 6, Freq= 0, CH_0, rank 0

 5207 23:28:28.131808  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5208 23:28:28.131890  ==

 5209 23:28:28.131955  

 5210 23:28:28.132016  

 5211 23:28:28.135295  	TX Vref Scan disable

 5212 23:28:28.135376   == TX Byte 0 ==

 5213 23:28:28.141452  Update DQ  dly =716 (2 ,6, 12)  DQ  OEN =(2 ,3)

 5214 23:28:28.145252  Update DQM dly =716 (2 ,6, 12)  DQM OEN =(2 ,3)

 5215 23:28:28.145335   == TX Byte 1 ==

 5216 23:28:28.151636  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5217 23:28:28.155054  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5218 23:28:28.155137  ==

 5219 23:28:28.158469  Dram Type= 6, Freq= 0, CH_0, rank 0

 5220 23:28:28.161492  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5221 23:28:28.161584  ==

 5222 23:28:28.161664  

 5223 23:28:28.161725  

 5224 23:28:28.164976  	TX Vref Scan disable

 5225 23:28:28.168414   == TX Byte 0 ==

 5226 23:28:28.171773  Update DQ  dly =715 (2 ,6, 11)  DQ  OEN =(2 ,3)

 5227 23:28:28.175155  Update DQM dly =715 (2 ,6, 11)  DQM OEN =(2 ,3)

 5228 23:28:28.178027   == TX Byte 1 ==

 5229 23:28:28.181828  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5230 23:28:28.184955  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5231 23:28:28.185037  

 5232 23:28:28.188364  [DATLAT]

 5233 23:28:28.188445  Freq=933, CH0 RK0

 5234 23:28:28.188509  

 5235 23:28:28.191607  DATLAT Default: 0xd

 5236 23:28:28.191688  0, 0xFFFF, sum = 0

 5237 23:28:28.194727  1, 0xFFFF, sum = 0

 5238 23:28:28.194810  2, 0xFFFF, sum = 0

 5239 23:28:28.198371  3, 0xFFFF, sum = 0

 5240 23:28:28.198464  4, 0xFFFF, sum = 0

 5241 23:28:28.201398  5, 0xFFFF, sum = 0

 5242 23:28:28.201482  6, 0xFFFF, sum = 0

 5243 23:28:28.204960  7, 0xFFFF, sum = 0

 5244 23:28:28.205042  8, 0xFFFF, sum = 0

 5245 23:28:28.208015  9, 0xFFFF, sum = 0

 5246 23:28:28.208130  10, 0x0, sum = 1

 5247 23:28:28.211390  11, 0x0, sum = 2

 5248 23:28:28.211475  12, 0x0, sum = 3

 5249 23:28:28.214660  13, 0x0, sum = 4

 5250 23:28:28.214742  best_step = 11

 5251 23:28:28.214806  

 5252 23:28:28.214866  ==

 5253 23:28:28.218246  Dram Type= 6, Freq= 0, CH_0, rank 0

 5254 23:28:28.225195  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5255 23:28:28.225277  ==

 5256 23:28:28.225341  RX Vref Scan: 1

 5257 23:28:28.225401  

 5258 23:28:28.227828  RX Vref 0 -> 0, step: 1

 5259 23:28:28.227910  

 5260 23:28:28.231287  RX Delay -53 -> 252, step: 4

 5261 23:28:28.231369  

 5262 23:28:28.234719  Set Vref, RX VrefLevel [Byte0]: 57

 5263 23:28:28.237969                           [Byte1]: 55

 5264 23:28:28.238050  

 5265 23:28:28.241465  Final RX Vref Byte 0 = 57 to rank0

 5266 23:28:28.244464  Final RX Vref Byte 1 = 55 to rank0

 5267 23:28:28.247886  Final RX Vref Byte 0 = 57 to rank1

 5268 23:28:28.251520  Final RX Vref Byte 1 = 55 to rank1==

 5269 23:28:28.254873  Dram Type= 6, Freq= 0, CH_0, rank 0

 5270 23:28:28.257879  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5271 23:28:28.257961  ==

 5272 23:28:28.261203  DQS Delay:

 5273 23:28:28.261284  DQS0 = 0, DQS1 = 0

 5274 23:28:28.261348  DQM Delay:

 5275 23:28:28.264605  DQM0 = 105, DQM1 = 97

 5276 23:28:28.264685  DQ Delay:

 5277 23:28:28.267648  DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102

 5278 23:28:28.270982  DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112

 5279 23:28:28.274715  DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92

 5280 23:28:28.278377  DQ12 =100, DQ13 =102, DQ14 =104, DQ15 =104

 5281 23:28:28.280928  

 5282 23:28:28.281008  

 5283 23:28:28.288054  [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps

 5284 23:28:28.291316  CH0 RK0: MR19=505, MR18=322A

 5285 23:28:28.297745  CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43

 5286 23:28:28.297827  

 5287 23:28:28.301502  ----->DramcWriteLeveling(PI) begin...

 5288 23:28:28.301627  ==

 5289 23:28:28.304954  Dram Type= 6, Freq= 0, CH_0, rank 1

 5290 23:28:28.307810  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5291 23:28:28.307892  ==

 5292 23:28:28.311073  Write leveling (Byte 0): 34 => 34

 5293 23:28:28.314281  Write leveling (Byte 1): 29 => 29

 5294 23:28:28.318068  DramcWriteLeveling(PI) end<-----

 5295 23:28:28.318171  

 5296 23:28:28.318266  ==

 5297 23:28:28.321009  Dram Type= 6, Freq= 0, CH_0, rank 1

 5298 23:28:28.324418  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5299 23:28:28.324500  ==

 5300 23:28:28.327411  [Gating] SW mode calibration

 5301 23:28:28.334770  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5302 23:28:28.340723  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5303 23:28:28.344062   0 14  0 | B1->B0 | 3434 3232 | 0 1 | (0 0) (1 1)

 5304 23:28:28.347520   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5305 23:28:28.354266   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5306 23:28:28.357648   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5307 23:28:28.360998   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5308 23:28:28.367692   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5309 23:28:28.370767   0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5310 23:28:28.374048   0 14 28 | B1->B0 | 2c2c 2d2d | 0 1 | (0 0) (0 1)

 5311 23:28:28.380610   0 15  0 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)

 5312 23:28:28.383781   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5313 23:28:28.387533   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5314 23:28:28.394021   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5315 23:28:28.397436   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5316 23:28:28.400636   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5317 23:28:28.407530   0 15 24 | B1->B0 | 2424 2424 | 0 0 | (1 1) (0 0)

 5318 23:28:28.410637   0 15 28 | B1->B0 | 3737 3333 | 0 0 | (0 0) (0 0)

 5319 23:28:28.414293   1  0  0 | B1->B0 | 4545 4545 | 0 0 | (0 0) (0 0)

 5320 23:28:28.420820   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5321 23:28:28.423692   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5322 23:28:28.427229   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5323 23:28:28.433740   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5324 23:28:28.437037   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5325 23:28:28.440456   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 5326 23:28:28.447287   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 5327 23:28:28.450621   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5328 23:28:28.453742   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5329 23:28:28.456925   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5330 23:28:28.463662   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5331 23:28:28.467155   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5332 23:28:28.470478   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5333 23:28:28.477425   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5334 23:28:28.480678   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5335 23:28:28.483788   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5336 23:28:28.490491   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5337 23:28:28.493728   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5338 23:28:28.497063   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5339 23:28:28.503880   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5340 23:28:28.506806   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5341 23:28:28.510246   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 5342 23:28:28.516860   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5343 23:28:28.520112   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 5344 23:28:28.523651  Total UI for P1: 0, mck2ui 16

 5345 23:28:28.527013  best dqsien dly found for B1: ( 1,  2, 28)

 5346 23:28:28.530130   1  3  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5347 23:28:28.533474  Total UI for P1: 0, mck2ui 16

 5348 23:28:28.536992  best dqsien dly found for B0: ( 1,  2, 28)

 5349 23:28:28.540341  best DQS0 dly(MCK, UI, PI) = (1, 2, 28)

 5350 23:28:28.543460  best DQS1 dly(MCK, UI, PI) = (1, 2, 28)

 5351 23:28:28.543542  

 5352 23:28:28.550442  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5353 23:28:28.553290  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)

 5354 23:28:28.553397  [Gating] SW calibration Done

 5355 23:28:28.556668  ==

 5356 23:28:28.559958  Dram Type= 6, Freq= 0, CH_0, rank 1

 5357 23:28:28.563268  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5358 23:28:28.563349  ==

 5359 23:28:28.563414  RX Vref Scan: 0

 5360 23:28:28.563473  

 5361 23:28:28.566994  RX Vref 0 -> 0, step: 1

 5362 23:28:28.567076  

 5363 23:28:28.570477  RX Delay -80 -> 252, step: 8

 5364 23:28:28.573258  iDelay=208, Bit 0, Center 103 (8 ~ 199) 192

 5365 23:28:28.576549  iDelay=208, Bit 1, Center 107 (16 ~ 199) 184

 5366 23:28:28.580191  iDelay=208, Bit 2, Center 103 (8 ~ 199) 192

 5367 23:28:28.586819  iDelay=208, Bit 3, Center 103 (8 ~ 199) 192

 5368 23:28:28.589946  iDelay=208, Bit 4, Center 107 (16 ~ 199) 184

 5369 23:28:28.593316  iDelay=208, Bit 5, Center 95 (0 ~ 191) 192

 5370 23:28:28.596849  iDelay=208, Bit 6, Center 111 (24 ~ 199) 176

 5371 23:28:28.599925  iDelay=208, Bit 7, Center 115 (24 ~ 207) 184

 5372 23:28:28.606300  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5373 23:28:28.609544  iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184

 5374 23:28:28.613081  iDelay=208, Bit 10, Center 95 (8 ~ 183) 176

 5375 23:28:28.616526  iDelay=208, Bit 11, Center 87 (0 ~ 175) 176

 5376 23:28:28.619846  iDelay=208, Bit 12, Center 99 (8 ~ 191) 184

 5377 23:28:28.623161  iDelay=208, Bit 13, Center 99 (8 ~ 191) 184

 5378 23:28:28.629823  iDelay=208, Bit 14, Center 99 (8 ~ 191) 184

 5379 23:28:28.633077  iDelay=208, Bit 15, Center 99 (8 ~ 191) 184

 5380 23:28:28.633157  ==

 5381 23:28:28.636484  Dram Type= 6, Freq= 0, CH_0, rank 1

 5382 23:28:28.639314  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5383 23:28:28.639391  ==

 5384 23:28:28.639472  DQS Delay:

 5385 23:28:28.642890  DQS0 = 0, DQS1 = 0

 5386 23:28:28.642973  DQM Delay:

 5387 23:28:28.646750  DQM0 = 105, DQM1 = 93

 5388 23:28:28.646825  DQ Delay:

 5389 23:28:28.649526  DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103

 5390 23:28:28.652853  DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115

 5391 23:28:28.656061  DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87

 5392 23:28:28.659430  DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99

 5393 23:28:28.659505  

 5394 23:28:28.659588  

 5395 23:28:28.659663  ==

 5396 23:28:28.662892  Dram Type= 6, Freq= 0, CH_0, rank 1

 5397 23:28:28.669680  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5398 23:28:28.669760  ==

 5399 23:28:28.669845  

 5400 23:28:28.669923  

 5401 23:28:28.672285  	TX Vref Scan disable

 5402 23:28:28.672361   == TX Byte 0 ==

 5403 23:28:28.675810  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5404 23:28:28.682656  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5405 23:28:28.682733   == TX Byte 1 ==

 5406 23:28:28.685662  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5407 23:28:28.692274  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5408 23:28:28.692352  ==

 5409 23:28:28.695482  Dram Type= 6, Freq= 0, CH_0, rank 1

 5410 23:28:28.699114  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5411 23:28:28.699189  ==

 5412 23:28:28.699272  

 5413 23:28:28.699351  

 5414 23:28:28.703052  	TX Vref Scan disable

 5415 23:28:28.705718   == TX Byte 0 ==

 5416 23:28:28.709041  Update DQ  dly =718 (2 ,6, 14)  DQ  OEN =(2 ,3)

 5417 23:28:28.712302  Update DQM dly =718 (2 ,6, 14)  DQM OEN =(2 ,3)

 5418 23:28:28.715437   == TX Byte 1 ==

 5419 23:28:28.719021  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5420 23:28:28.722563  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5421 23:28:28.722636  

 5422 23:28:28.725727  [DATLAT]

 5423 23:28:28.725802  Freq=933, CH0 RK1

 5424 23:28:28.725883  

 5425 23:28:28.729309  DATLAT Default: 0xb

 5426 23:28:28.729382  0, 0xFFFF, sum = 0

 5427 23:28:28.732072  1, 0xFFFF, sum = 0

 5428 23:28:28.732146  2, 0xFFFF, sum = 0

 5429 23:28:28.735510  3, 0xFFFF, sum = 0

 5430 23:28:28.735582  4, 0xFFFF, sum = 0

 5431 23:28:28.738681  5, 0xFFFF, sum = 0

 5432 23:28:28.738758  6, 0xFFFF, sum = 0

 5433 23:28:28.742409  7, 0xFFFF, sum = 0

 5434 23:28:28.742491  8, 0xFFFF, sum = 0

 5435 23:28:28.745412  9, 0xFFFF, sum = 0

 5436 23:28:28.745488  10, 0x0, sum = 1

 5437 23:28:28.748850  11, 0x0, sum = 2

 5438 23:28:28.748929  12, 0x0, sum = 3

 5439 23:28:28.752231  13, 0x0, sum = 4

 5440 23:28:28.752303  best_step = 11

 5441 23:28:28.752384  

 5442 23:28:28.752460  ==

 5443 23:28:28.755513  Dram Type= 6, Freq= 0, CH_0, rank 1

 5444 23:28:28.758902  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5445 23:28:28.762243  ==

 5446 23:28:28.762319  RX Vref Scan: 0

 5447 23:28:28.762382  

 5448 23:28:28.765597  RX Vref 0 -> 0, step: 1

 5449 23:28:28.765685  

 5450 23:28:28.768832  RX Delay -53 -> 252, step: 4

 5451 23:28:28.772261  iDelay=199, Bit 0, Center 102 (11 ~ 194) 184

 5452 23:28:28.775324  iDelay=199, Bit 1, Center 106 (23 ~ 190) 168

 5453 23:28:28.782215  iDelay=199, Bit 2, Center 102 (15 ~ 190) 176

 5454 23:28:28.785301  iDelay=199, Bit 3, Center 102 (15 ~ 190) 176

 5455 23:28:28.788522  iDelay=199, Bit 4, Center 106 (19 ~ 194) 176

 5456 23:28:28.792056  iDelay=199, Bit 5, Center 98 (11 ~ 186) 176

 5457 23:28:28.795205  iDelay=199, Bit 6, Center 110 (23 ~ 198) 176

 5458 23:28:28.798433  iDelay=199, Bit 7, Center 112 (27 ~ 198) 172

 5459 23:28:28.805146  iDelay=199, Bit 8, Center 86 (3 ~ 170) 168

 5460 23:28:28.808789  iDelay=199, Bit 9, Center 86 (3 ~ 170) 168

 5461 23:28:28.811779  iDelay=199, Bit 10, Center 96 (15 ~ 178) 164

 5462 23:28:28.815372  iDelay=199, Bit 11, Center 90 (7 ~ 174) 168

 5463 23:28:28.818780  iDelay=199, Bit 12, Center 102 (19 ~ 186) 168

 5464 23:28:28.825435  iDelay=199, Bit 13, Center 100 (15 ~ 186) 172

 5465 23:28:28.829035  iDelay=199, Bit 14, Center 104 (19 ~ 190) 172

 5466 23:28:28.832259  iDelay=199, Bit 15, Center 102 (19 ~ 186) 168

 5467 23:28:28.832340  ==

 5468 23:28:28.835662  Dram Type= 6, Freq= 0, CH_0, rank 1

 5469 23:28:28.838817  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5470 23:28:28.838911  ==

 5471 23:28:28.841720  DQS Delay:

 5472 23:28:28.841801  DQS0 = 0, DQS1 = 0

 5473 23:28:28.845279  DQM Delay:

 5474 23:28:28.845360  DQM0 = 104, DQM1 = 95

 5475 23:28:28.845425  DQ Delay:

 5476 23:28:28.848646  DQ0 =102, DQ1 =106, DQ2 =102, DQ3 =102

 5477 23:28:28.851718  DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112

 5478 23:28:28.855138  DQ8 =86, DQ9 =86, DQ10 =96, DQ11 =90

 5479 23:28:28.861677  DQ12 =102, DQ13 =100, DQ14 =104, DQ15 =102

 5480 23:28:28.861758  

 5481 23:28:28.861822  

 5482 23:28:28.868456  [DQSOSCAuto] RK1, (LSB)MR18= 0x2801, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 409 ps

 5483 23:28:28.871497  CH0 RK1: MR19=505, MR18=2801

 5484 23:28:28.877974  CH0_RK1: MR19=0x505, MR18=0x2801, DQSOSC=409, MR23=63, INC=64, DEC=43

 5485 23:28:28.881323  [RxdqsGatingPostProcess] freq 933

 5486 23:28:28.884894  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5487 23:28:28.888308  best DQS0 dly(2T, 0.5T) = (0, 10)

 5488 23:28:28.891489  best DQS1 dly(2T, 0.5T) = (0, 10)

 5489 23:28:28.894652  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5490 23:28:28.898226  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5491 23:28:28.901227  best DQS0 dly(2T, 0.5T) = (0, 10)

 5492 23:28:28.904710  best DQS1 dly(2T, 0.5T) = (0, 10)

 5493 23:28:28.908283  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5494 23:28:28.911153  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5495 23:28:28.914583  Pre-setting of DQS Precalculation

 5496 23:28:28.918096  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5497 23:28:28.921456  ==

 5498 23:28:28.924406  Dram Type= 6, Freq= 0, CH_1, rank 0

 5499 23:28:28.927651  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5500 23:28:28.927733  ==

 5501 23:28:28.930898  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5502 23:28:28.938056  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5503 23:28:28.941611  [CA 0] Center 36 (6~67) winsize 62

 5504 23:28:28.944981  [CA 1] Center 37 (6~68) winsize 63

 5505 23:28:28.947828  [CA 2] Center 34 (4~65) winsize 62

 5506 23:28:28.951679  [CA 3] Center 34 (4~65) winsize 62

 5507 23:28:28.954581  [CA 4] Center 34 (4~65) winsize 62

 5508 23:28:28.958091  [CA 5] Center 33 (3~64) winsize 62

 5509 23:28:28.958173  

 5510 23:28:28.961466  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5511 23:28:28.961548  

 5512 23:28:28.964733  [CATrainingPosCal] consider 1 rank data

 5513 23:28:28.967798  u2DelayCellTimex100 = 270/100 ps

 5514 23:28:28.971261  CA0 delay=36 (6~67),Diff = 3 PI (18 cell)

 5515 23:28:28.978313  CA1 delay=37 (6~68),Diff = 4 PI (24 cell)

 5516 23:28:28.981106  CA2 delay=34 (4~65),Diff = 1 PI (6 cell)

 5517 23:28:28.984575  CA3 delay=34 (4~65),Diff = 1 PI (6 cell)

 5518 23:28:28.987825  CA4 delay=34 (4~65),Diff = 1 PI (6 cell)

 5519 23:28:28.991131  CA5 delay=33 (3~64),Diff = 0 PI (0 cell)

 5520 23:28:28.991204  

 5521 23:28:28.994098  CA PerBit enable=1, Macro0, CA PI delay=33

 5522 23:28:28.994171  

 5523 23:28:28.997662  [CBTSetCACLKResult] CA Dly = 33

 5524 23:28:28.997734  CS Dly: 6 (0~37)

 5525 23:28:29.001005  ==

 5526 23:28:29.004400  Dram Type= 6, Freq= 0, CH_1, rank 1

 5527 23:28:29.007615  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5528 23:28:29.007694  ==

 5529 23:28:29.010832  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 5530 23:28:29.017883  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 5531 23:28:29.021121  [CA 0] Center 36 (6~67) winsize 62

 5532 23:28:29.024634  [CA 1] Center 37 (6~68) winsize 63

 5533 23:28:29.027892  [CA 2] Center 35 (4~66) winsize 63

 5534 23:28:29.031121  [CA 3] Center 34 (4~65) winsize 62

 5535 23:28:29.034339  [CA 4] Center 34 (4~65) winsize 62

 5536 23:28:29.037991  [CA 5] Center 34 (4~64) winsize 61

 5537 23:28:29.038065  

 5538 23:28:29.041177  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 5539 23:28:29.041248  

 5540 23:28:29.044446  [CATrainingPosCal] consider 2 rank data

 5541 23:28:29.047917  u2DelayCellTimex100 = 270/100 ps

 5542 23:28:29.051288  CA0 delay=36 (6~67),Diff = 2 PI (12 cell)

 5543 23:28:29.057526  CA1 delay=37 (6~68),Diff = 3 PI (18 cell)

 5544 23:28:29.061137  CA2 delay=34 (4~65),Diff = 0 PI (0 cell)

 5545 23:28:29.064427  CA3 delay=34 (4~65),Diff = 0 PI (0 cell)

 5546 23:28:29.067401  CA4 delay=34 (4~65),Diff = 0 PI (0 cell)

 5547 23:28:29.070877  CA5 delay=34 (4~64),Diff = 0 PI (0 cell)

 5548 23:28:29.070982  

 5549 23:28:29.074810  CA PerBit enable=1, Macro0, CA PI delay=34

 5550 23:28:29.074897  

 5551 23:28:29.077802  [CBTSetCACLKResult] CA Dly = 34

 5552 23:28:29.077873  CS Dly: 7 (0~40)

 5553 23:28:29.080746  

 5554 23:28:29.083980  ----->DramcWriteLeveling(PI) begin...

 5555 23:28:29.084055  ==

 5556 23:28:29.087404  Dram Type= 6, Freq= 0, CH_1, rank 0

 5557 23:28:29.091121  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5558 23:28:29.091200  ==

 5559 23:28:29.094512  Write leveling (Byte 0): 25 => 25

 5560 23:28:29.097422  Write leveling (Byte 1): 30 => 30

 5561 23:28:29.100937  DramcWriteLeveling(PI) end<-----

 5562 23:28:29.101018  

 5563 23:28:29.101081  ==

 5564 23:28:29.104256  Dram Type= 6, Freq= 0, CH_1, rank 0

 5565 23:28:29.107359  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5566 23:28:29.107437  ==

 5567 23:28:29.111300  [Gating] SW mode calibration

 5568 23:28:29.117590  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5569 23:28:29.123909  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5570 23:28:29.127299   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5571 23:28:29.130811   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5572 23:28:29.137378   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5573 23:28:29.140557   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5574 23:28:29.143816   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5575 23:28:29.150667   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5576 23:28:29.154056   0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (0 1) (0 1)

 5577 23:28:29.157324   0 14 28 | B1->B0 | 2a2a 2424 | 0 0 | (1 0) (0 0)

 5578 23:28:29.163923   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5579 23:28:29.167325   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5580 23:28:29.170488   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5581 23:28:29.177526   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5582 23:28:29.180329   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5583 23:28:29.184101   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5584 23:28:29.187011   0 15 24 | B1->B0 | 2424 3636 | 0 1 | (0 0) (0 0)

 5585 23:28:29.193830   0 15 28 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)

 5586 23:28:29.197041   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5587 23:28:29.200607   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5588 23:28:29.207375   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5589 23:28:29.211034   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5590 23:28:29.213951   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5591 23:28:29.220462   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5592 23:28:29.223810   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 5593 23:28:29.227209   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5594 23:28:29.233874   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5595 23:28:29.237580   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5596 23:28:29.240641   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5597 23:28:29.246937   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5598 23:28:29.250354   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5599 23:28:29.253546   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5600 23:28:29.260457   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5601 23:28:29.263728   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5602 23:28:29.266702   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5603 23:28:29.273468   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5604 23:28:29.276715   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5605 23:28:29.279829   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5606 23:28:29.286578   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5607 23:28:29.290009   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5608 23:28:29.293138   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5609 23:28:29.299768   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 5610 23:28:29.299853  Total UI for P1: 0, mck2ui 16

 5611 23:28:29.306182  best dqsien dly found for B0: ( 1,  2, 24)

 5612 23:28:29.309686   1  3  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5613 23:28:29.313062  Total UI for P1: 0, mck2ui 16

 5614 23:28:29.316426  best dqsien dly found for B1: ( 1,  2, 26)

 5615 23:28:29.319669  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5616 23:28:29.322777  best DQS1 dly(MCK, UI, PI) = (1, 2, 26)

 5617 23:28:29.322854  

 5618 23:28:29.326317  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5619 23:28:29.329433  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)

 5620 23:28:29.332769  [Gating] SW calibration Done

 5621 23:28:29.332842  ==

 5622 23:28:29.335994  Dram Type= 6, Freq= 0, CH_1, rank 0

 5623 23:28:29.339309  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5624 23:28:29.342708  ==

 5625 23:28:29.342784  RX Vref Scan: 0

 5626 23:28:29.342865  

 5627 23:28:29.346280  RX Vref 0 -> 0, step: 1

 5628 23:28:29.346360  

 5629 23:28:29.349493  RX Delay -80 -> 252, step: 8

 5630 23:28:29.353276  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5631 23:28:29.356205  iDelay=208, Bit 1, Center 95 (0 ~ 191) 192

 5632 23:28:29.359240  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5633 23:28:29.363084  iDelay=208, Bit 3, Center 99 (8 ~ 191) 184

 5634 23:28:29.366096  iDelay=208, Bit 4, Center 99 (8 ~ 191) 184

 5635 23:28:29.372459  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5636 23:28:29.376169  iDelay=208, Bit 6, Center 115 (24 ~ 207) 184

 5637 23:28:29.379208  iDelay=208, Bit 7, Center 103 (8 ~ 199) 192

 5638 23:28:29.382216  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5639 23:28:29.385816  iDelay=208, Bit 9, Center 87 (0 ~ 175) 176

 5640 23:28:29.389553  iDelay=208, Bit 10, Center 103 (16 ~ 191) 176

 5641 23:28:29.395426  iDelay=208, Bit 11, Center 95 (8 ~ 183) 176

 5642 23:28:29.398892  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5643 23:28:29.402299  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5644 23:28:29.405687  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5645 23:28:29.412278  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5646 23:28:29.412364  ==

 5647 23:28:29.415427  Dram Type= 6, Freq= 0, CH_1, rank 0

 5648 23:28:29.418919  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5649 23:28:29.418996  ==

 5650 23:28:29.419073  DQS Delay:

 5651 23:28:29.422563  DQS0 = 0, DQS1 = 0

 5652 23:28:29.422652  DQM Delay:

 5653 23:28:29.425703  DQM0 = 103, DQM1 = 99

 5654 23:28:29.425773  DQ Delay:

 5655 23:28:29.428834  DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99

 5656 23:28:29.432082  DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103

 5657 23:28:29.435499  DQ8 =87, DQ9 =87, DQ10 =103, DQ11 =95

 5658 23:28:29.438699  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5659 23:28:29.438771  

 5660 23:28:29.438840  

 5661 23:28:29.438899  ==

 5662 23:28:29.442444  Dram Type= 6, Freq= 0, CH_1, rank 0

 5663 23:28:29.448506  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5664 23:28:29.448617  ==

 5665 23:28:29.448708  

 5666 23:28:29.448806  

 5667 23:28:29.448891  	TX Vref Scan disable

 5668 23:28:29.452041   == TX Byte 0 ==

 5669 23:28:29.455232  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5670 23:28:29.461772  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5671 23:28:29.461849   == TX Byte 1 ==

 5672 23:28:29.465482  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5673 23:28:29.471920  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5674 23:28:29.471999  ==

 5675 23:28:29.475251  Dram Type= 6, Freq= 0, CH_1, rank 0

 5676 23:28:29.478360  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5677 23:28:29.478439  ==

 5678 23:28:29.478501  

 5679 23:28:29.478560  

 5680 23:28:29.481712  	TX Vref Scan disable

 5681 23:28:29.481784   == TX Byte 0 ==

 5682 23:28:29.488386  Update DQ  dly =709 (2 ,5, 37)  DQ  OEN =(2 ,2)

 5683 23:28:29.492182  Update DQM dly =709 (2 ,5, 37)  DQM OEN =(2 ,2)

 5684 23:28:29.492259   == TX Byte 1 ==

 5685 23:28:29.498278  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5686 23:28:29.501455  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5687 23:28:29.501561  

 5688 23:28:29.501680  [DATLAT]

 5689 23:28:29.504740  Freq=933, CH1 RK0

 5690 23:28:29.504813  

 5691 23:28:29.504894  DATLAT Default: 0xd

 5692 23:28:29.508268  0, 0xFFFF, sum = 0

 5693 23:28:29.508348  1, 0xFFFF, sum = 0

 5694 23:28:29.511795  2, 0xFFFF, sum = 0

 5695 23:28:29.515042  3, 0xFFFF, sum = 0

 5696 23:28:29.515118  4, 0xFFFF, sum = 0

 5697 23:28:29.518429  5, 0xFFFF, sum = 0

 5698 23:28:29.518503  6, 0xFFFF, sum = 0

 5699 23:28:29.521899  7, 0xFFFF, sum = 0

 5700 23:28:29.521976  8, 0xFFFF, sum = 0

 5701 23:28:29.524820  9, 0xFFFF, sum = 0

 5702 23:28:29.524894  10, 0x0, sum = 1

 5703 23:28:29.528196  11, 0x0, sum = 2

 5704 23:28:29.528277  12, 0x0, sum = 3

 5705 23:28:29.531436  13, 0x0, sum = 4

 5706 23:28:29.531536  best_step = 11

 5707 23:28:29.531638  

 5708 23:28:29.531725  ==

 5709 23:28:29.534774  Dram Type= 6, Freq= 0, CH_1, rank 0

 5710 23:28:29.537895  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5711 23:28:29.538001  ==

 5712 23:28:29.541222  RX Vref Scan: 1

 5713 23:28:29.541318  

 5714 23:28:29.544827  RX Vref 0 -> 0, step: 1

 5715 23:28:29.544906  

 5716 23:28:29.544979  RX Delay -45 -> 252, step: 4

 5717 23:28:29.545039  

 5718 23:28:29.548400  Set Vref, RX VrefLevel [Byte0]: 53

 5719 23:28:29.551566                           [Byte1]: 55

 5720 23:28:29.555658  

 5721 23:28:29.555765  Final RX Vref Byte 0 = 53 to rank0

 5722 23:28:29.559410  Final RX Vref Byte 1 = 55 to rank0

 5723 23:28:29.562579  Final RX Vref Byte 0 = 53 to rank1

 5724 23:28:29.566059  Final RX Vref Byte 1 = 55 to rank1==

 5725 23:28:29.568935  Dram Type= 6, Freq= 0, CH_1, rank 0

 5726 23:28:29.576115  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5727 23:28:29.576191  ==

 5728 23:28:29.576254  DQS Delay:

 5729 23:28:29.576323  DQS0 = 0, DQS1 = 0

 5730 23:28:29.579491  DQM Delay:

 5731 23:28:29.579566  DQM0 = 102, DQM1 = 100

 5732 23:28:29.582785  DQ Delay:

 5733 23:28:29.585530  DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98

 5734 23:28:29.588843  DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102

 5735 23:28:29.592267  DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =92

 5736 23:28:29.595456  DQ12 =104, DQ13 =108, DQ14 =108, DQ15 =108

 5737 23:28:29.595527  

 5738 23:28:29.595588  

 5739 23:28:29.602453  [DQSOSCAuto] RK0, (LSB)MR18= 0x172e, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps

 5740 23:28:29.605763  CH1 RK0: MR19=505, MR18=172E

 5741 23:28:29.612229  CH1_RK0: MR19=0x505, MR18=0x172E, DQSOSC=407, MR23=63, INC=65, DEC=43

 5742 23:28:29.612305  

 5743 23:28:29.615582  ----->DramcWriteLeveling(PI) begin...

 5744 23:28:29.615657  ==

 5745 23:28:29.619033  Dram Type= 6, Freq= 0, CH_1, rank 1

 5746 23:28:29.622436  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5747 23:28:29.622519  ==

 5748 23:28:29.625930  Write leveling (Byte 0): 28 => 28

 5749 23:28:29.628672  Write leveling (Byte 1): 29 => 29

 5750 23:28:29.632272  DramcWriteLeveling(PI) end<-----

 5751 23:28:29.632344  

 5752 23:28:29.632413  ==

 5753 23:28:29.635837  Dram Type= 6, Freq= 0, CH_1, rank 1

 5754 23:28:29.642251  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5755 23:28:29.642362  ==

 5756 23:28:29.642454  [Gating] SW mode calibration

 5757 23:28:29.652394  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0

 5758 23:28:29.655845  RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)

 5759 23:28:29.658547   0 14  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5760 23:28:29.665389   0 14  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5761 23:28:29.668562   0 14  8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5762 23:28:29.671776   0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5763 23:28:29.678761   0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5764 23:28:29.681804   0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 5765 23:28:29.685188   0 14 24 | B1->B0 | 2d2d 3333 | 1 1 | (1 0) (1 0)

 5766 23:28:29.691922   0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 5767 23:28:29.694944   0 15  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5768 23:28:29.698421   0 15  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5769 23:28:29.705251   0 15  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5770 23:28:29.708211   0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5771 23:28:29.711556   0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5772 23:28:29.718481   0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 5773 23:28:29.721527   0 15 24 | B1->B0 | 3333 2727 | 0 0 | (0 0) (0 0)

 5774 23:28:29.724903   0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)

 5775 23:28:29.731665   1  0  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5776 23:28:29.735093   1  0  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5777 23:28:29.738234   1  0  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5778 23:28:29.744791   1  0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5779 23:28:29.748256   1  0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5780 23:28:29.751577   1  0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5781 23:28:29.757992   1  0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5782 23:28:29.761328   1  0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5783 23:28:29.764887   1  1  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5784 23:28:29.771623   1  1  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5785 23:28:29.775271   1  1  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5786 23:28:29.777961   1  1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5787 23:28:29.784409   1  1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5788 23:28:29.788094   1  1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5789 23:28:29.791343   1  1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5790 23:28:29.798263   1  1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5791 23:28:29.801298   1  2  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5792 23:28:29.804709   1  2  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5793 23:28:29.811023   1  2  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5794 23:28:29.814309   1  2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5795 23:28:29.817525   1  2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5796 23:28:29.824230   1  2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 5797 23:28:29.827816   1  2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 5798 23:28:29.830940   1  2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 5799 23:28:29.834885  Total UI for P1: 0, mck2ui 16

 5800 23:28:29.837868  best dqsien dly found for B0: ( 1,  2, 24)

 5801 23:28:29.841021  Total UI for P1: 0, mck2ui 16

 5802 23:28:29.844483  best dqsien dly found for B1: ( 1,  2, 24)

 5803 23:28:29.847642  best DQS0 dly(MCK, UI, PI) = (1, 2, 24)

 5804 23:28:29.851080  best DQS1 dly(MCK, UI, PI) = (1, 2, 24)

 5805 23:28:29.851184  

 5806 23:28:29.854782  best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5807 23:28:29.861095  best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)

 5808 23:28:29.861173  [Gating] SW calibration Done

 5809 23:28:29.861236  ==

 5810 23:28:29.864483  Dram Type= 6, Freq= 0, CH_1, rank 1

 5811 23:28:29.871108  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5812 23:28:29.871193  ==

 5813 23:28:29.871270  RX Vref Scan: 0

 5814 23:28:29.871333  

 5815 23:28:29.874622  RX Vref 0 -> 0, step: 1

 5816 23:28:29.874709  

 5817 23:28:29.877672  RX Delay -80 -> 252, step: 8

 5818 23:28:29.881230  iDelay=208, Bit 0, Center 107 (16 ~ 199) 184

 5819 23:28:29.884277  iDelay=208, Bit 1, Center 103 (16 ~ 191) 176

 5820 23:28:29.887301  iDelay=208, Bit 2, Center 91 (0 ~ 183) 184

 5821 23:28:29.893921  iDelay=208, Bit 3, Center 103 (16 ~ 191) 176

 5822 23:28:29.897374  iDelay=208, Bit 4, Center 99 (16 ~ 183) 168

 5823 23:28:29.900676  iDelay=208, Bit 5, Center 115 (24 ~ 207) 184

 5824 23:28:29.904081  iDelay=208, Bit 6, Center 111 (16 ~ 207) 192

 5825 23:28:29.907372  iDelay=208, Bit 7, Center 103 (16 ~ 191) 176

 5826 23:28:29.910387  iDelay=208, Bit 8, Center 87 (0 ~ 175) 176

 5827 23:28:29.916999  iDelay=208, Bit 9, Center 91 (0 ~ 183) 184

 5828 23:28:29.920490  iDelay=208, Bit 10, Center 99 (8 ~ 191) 184

 5829 23:28:29.923861  iDelay=208, Bit 11, Center 91 (0 ~ 183) 184

 5830 23:28:29.927130  iDelay=208, Bit 12, Center 107 (16 ~ 199) 184

 5831 23:28:29.930889  iDelay=208, Bit 13, Center 107 (16 ~ 199) 184

 5832 23:28:29.937334  iDelay=208, Bit 14, Center 103 (16 ~ 191) 176

 5833 23:28:29.940352  iDelay=208, Bit 15, Center 107 (16 ~ 199) 184

 5834 23:28:29.940450  ==

 5835 23:28:29.944024  Dram Type= 6, Freq= 0, CH_1, rank 1

 5836 23:28:29.947075  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5837 23:28:29.947174  ==

 5838 23:28:29.950929  DQS Delay:

 5839 23:28:29.951043  DQS0 = 0, DQS1 = 0

 5840 23:28:29.951135  DQM Delay:

 5841 23:28:29.953511  DQM0 = 104, DQM1 = 99

 5842 23:28:29.953642  DQ Delay:

 5843 23:28:29.956868  DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103

 5844 23:28:29.960541  DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103

 5845 23:28:29.963502  DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91

 5846 23:28:29.967043  DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107

 5847 23:28:29.967147  

 5848 23:28:29.967247  

 5849 23:28:29.970256  ==

 5850 23:28:29.973641  Dram Type= 6, Freq= 0, CH_1, rank 1

 5851 23:28:29.977001  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5852 23:28:29.977121  ==

 5853 23:28:29.977227  

 5854 23:28:29.977323  

 5855 23:28:29.980124  	TX Vref Scan disable

 5856 23:28:29.980221   == TX Byte 0 ==

 5857 23:28:29.986842  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5858 23:28:29.990266  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5859 23:28:29.990355   == TX Byte 1 ==

 5860 23:28:29.996633  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5861 23:28:30.000487  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5862 23:28:30.000592  ==

 5863 23:28:30.003500  Dram Type= 6, Freq= 0, CH_1, rank 1

 5864 23:28:30.006976  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5865 23:28:30.007063  ==

 5866 23:28:30.007128  

 5867 23:28:30.007186  

 5868 23:28:30.010353  	TX Vref Scan disable

 5869 23:28:30.013708   == TX Byte 0 ==

 5870 23:28:30.016559  Update DQ  dly =712 (2 ,5, 40)  DQ  OEN =(2 ,2)

 5871 23:28:30.019835  Update DQM dly =712 (2 ,5, 40)  DQM OEN =(2 ,2)

 5872 23:28:30.023163   == TX Byte 1 ==

 5873 23:28:30.026695  Update DQ  dly =711 (2 ,5, 39)  DQ  OEN =(2 ,2)

 5874 23:28:30.030079  Update DQM dly =711 (2 ,5, 39)  DQM OEN =(2 ,2)

 5875 23:28:30.030151  

 5876 23:28:30.033147  [DATLAT]

 5877 23:28:30.033251  Freq=933, CH1 RK1

 5878 23:28:30.033342  

 5879 23:28:30.037006  DATLAT Default: 0xb

 5880 23:28:30.037077  0, 0xFFFF, sum = 0

 5881 23:28:30.040239  1, 0xFFFF, sum = 0

 5882 23:28:30.040309  2, 0xFFFF, sum = 0

 5883 23:28:30.043043  3, 0xFFFF, sum = 0

 5884 23:28:30.043152  4, 0xFFFF, sum = 0

 5885 23:28:30.046436  5, 0xFFFF, sum = 0

 5886 23:28:30.046511  6, 0xFFFF, sum = 0

 5887 23:28:30.049901  7, 0xFFFF, sum = 0

 5888 23:28:30.049974  8, 0xFFFF, sum = 0

 5889 23:28:30.053339  9, 0xFFFF, sum = 0

 5890 23:28:30.053455  10, 0x0, sum = 1

 5891 23:28:30.056720  11, 0x0, sum = 2

 5892 23:28:30.056798  12, 0x0, sum = 3

 5893 23:28:30.060020  13, 0x0, sum = 4

 5894 23:28:30.060095  best_step = 11

 5895 23:28:30.060168  

 5896 23:28:30.060227  ==

 5897 23:28:30.063267  Dram Type= 6, Freq= 0, CH_1, rank 1

 5898 23:28:30.066289  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5899 23:28:30.069799  ==

 5900 23:28:30.069873  RX Vref Scan: 0

 5901 23:28:30.069936  

 5902 23:28:30.073284  RX Vref 0 -> 0, step: 1

 5903 23:28:30.073381  

 5904 23:28:30.076355  RX Delay -45 -> 252, step: 4

 5905 23:28:30.079710  iDelay=203, Bit 0, Center 108 (27 ~ 190) 164

 5906 23:28:30.083072  iDelay=203, Bit 1, Center 98 (15 ~ 182) 168

 5907 23:28:30.089819  iDelay=203, Bit 2, Center 94 (11 ~ 178) 168

 5908 23:28:30.092894  iDelay=203, Bit 3, Center 100 (19 ~ 182) 164

 5909 23:28:30.096266  iDelay=203, Bit 4, Center 100 (19 ~ 182) 164

 5910 23:28:30.099489  iDelay=203, Bit 5, Center 118 (35 ~ 202) 168

 5911 23:28:30.103017  iDelay=203, Bit 6, Center 114 (31 ~ 198) 168

 5912 23:28:30.106330  iDelay=203, Bit 7, Center 102 (19 ~ 186) 168

 5913 23:28:30.112716  iDelay=203, Bit 8, Center 88 (3 ~ 174) 172

 5914 23:28:30.116497  iDelay=203, Bit 9, Center 86 (-1 ~ 174) 176

 5915 23:28:30.119455  iDelay=203, Bit 10, Center 102 (19 ~ 186) 168

 5916 23:28:30.123246  iDelay=203, Bit 11, Center 94 (11 ~ 178) 168

 5917 23:28:30.126559  iDelay=203, Bit 12, Center 108 (19 ~ 198) 180

 5918 23:28:30.133110  iDelay=203, Bit 13, Center 106 (23 ~ 190) 168

 5919 23:28:30.136531  iDelay=203, Bit 14, Center 106 (23 ~ 190) 168

 5920 23:28:30.139748  iDelay=203, Bit 15, Center 108 (23 ~ 194) 172

 5921 23:28:30.139821  ==

 5922 23:28:30.143154  Dram Type= 6, Freq= 0, CH_1, rank 1

 5923 23:28:30.146352  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1

 5924 23:28:30.146438  ==

 5925 23:28:30.149435  DQS Delay:

 5926 23:28:30.149531  DQS0 = 0, DQS1 = 0

 5927 23:28:30.152653  DQM Delay:

 5928 23:28:30.152750  DQM0 = 104, DQM1 = 99

 5929 23:28:30.156061  DQ Delay:

 5930 23:28:30.159785  DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =100

 5931 23:28:30.162762  DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102

 5932 23:28:30.166302  DQ8 =88, DQ9 =86, DQ10 =102, DQ11 =94

 5933 23:28:30.169361  DQ12 =108, DQ13 =106, DQ14 =106, DQ15 =108

 5934 23:28:30.169472  

 5935 23:28:30.169562  

 5936 23:28:30.175734  [DQSOSCAuto] RK1, (LSB)MR18= 0x29fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps

 5937 23:28:30.179333  CH1 RK1: MR19=504, MR18=29FD

 5938 23:28:30.186030  CH1_RK1: MR19=0x504, MR18=0x29FD, DQSOSC=408, MR23=63, INC=65, DEC=43

 5939 23:28:30.189198  [RxdqsGatingPostProcess] freq 933

 5940 23:28:30.195541  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2

 5941 23:28:30.195644  best DQS0 dly(2T, 0.5T) = (0, 10)

 5942 23:28:30.198884  best DQS1 dly(2T, 0.5T) = (0, 10)

 5943 23:28:30.202521  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5944 23:28:30.205805  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5945 23:28:30.209107  best DQS0 dly(2T, 0.5T) = (0, 10)

 5946 23:28:30.212342  best DQS1 dly(2T, 0.5T) = (0, 10)

 5947 23:28:30.215491  best DQS0 P1 dly(2T, 0.5T) = (0, 14)

 5948 23:28:30.219072  best DQS1 P1 dly(2T, 0.5T) = (0, 14)

 5949 23:28:30.222239  Pre-setting of DQS Precalculation

 5950 23:28:30.225763  [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11

 5951 23:28:30.235693  sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3

 5952 23:28:30.242509  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 5953 23:28:30.242611  

 5954 23:28:30.242701  

 5955 23:28:30.245762  [Calibration Summary] 1866 Mbps

 5956 23:28:30.245874  CH 0, Rank 0

 5957 23:28:30.248663  SW Impedance     : PASS

 5958 23:28:30.248737  DUTY Scan        : NO K

 5959 23:28:30.252032  ZQ Calibration   : PASS

 5960 23:28:30.255449  Jitter Meter     : NO K

 5961 23:28:30.255560  CBT Training     : PASS

 5962 23:28:30.258874  Write leveling   : PASS

 5963 23:28:30.262233  RX DQS gating    : PASS

 5964 23:28:30.262319  RX DQ/DQS(RDDQC) : PASS

 5965 23:28:30.265251  TX DQ/DQS        : PASS

 5966 23:28:30.268691  RX DATLAT        : PASS

 5967 23:28:30.268768  RX DQ/DQS(Engine): PASS

 5968 23:28:30.272117  TX OE            : NO K

 5969 23:28:30.272229  All Pass.

 5970 23:28:30.272319  

 5971 23:28:30.275405  CH 0, Rank 1

 5972 23:28:30.275508  SW Impedance     : PASS

 5973 23:28:30.278605  DUTY Scan        : NO K

 5974 23:28:30.282294  ZQ Calibration   : PASS

 5975 23:28:30.282379  Jitter Meter     : NO K

 5976 23:28:30.285501  CBT Training     : PASS

 5977 23:28:30.288931  Write leveling   : PASS

 5978 23:28:30.289003  RX DQS gating    : PASS

 5979 23:28:30.292027  RX DQ/DQS(RDDQC) : PASS

 5980 23:28:30.292097  TX DQ/DQS        : PASS

 5981 23:28:30.295324  RX DATLAT        : PASS

 5982 23:28:30.298774  RX DQ/DQS(Engine): PASS

 5983 23:28:30.298845  TX OE            : NO K

 5984 23:28:30.302319  All Pass.

 5985 23:28:30.302391  

 5986 23:28:30.302452  CH 1, Rank 0

 5987 23:28:30.305431  SW Impedance     : PASS

 5988 23:28:30.305499  DUTY Scan        : NO K

 5989 23:28:30.308938  ZQ Calibration   : PASS

 5990 23:28:30.312038  Jitter Meter     : NO K

 5991 23:28:30.312113  CBT Training     : PASS

 5992 23:28:30.315508  Write leveling   : PASS

 5993 23:28:30.318838  RX DQS gating    : PASS

 5994 23:28:30.318911  RX DQ/DQS(RDDQC) : PASS

 5995 23:28:30.321884  TX DQ/DQS        : PASS

 5996 23:28:30.325544  RX DATLAT        : PASS

 5997 23:28:30.325626  RX DQ/DQS(Engine): PASS

 5998 23:28:30.328991  TX OE            : NO K

 5999 23:28:30.329060  All Pass.

 6000 23:28:30.329120  

 6001 23:28:30.332101  CH 1, Rank 1

 6002 23:28:30.332167  SW Impedance     : PASS

 6003 23:28:30.335305  DUTY Scan        : NO K

 6004 23:28:30.338502  ZQ Calibration   : PASS

 6005 23:28:30.338571  Jitter Meter     : NO K

 6006 23:28:30.341904  CBT Training     : PASS

 6007 23:28:30.341969  Write leveling   : PASS

 6008 23:28:30.345238  RX DQS gating    : PASS

 6009 23:28:30.348705  RX DQ/DQS(RDDQC) : PASS

 6010 23:28:30.348778  TX DQ/DQS        : PASS

 6011 23:28:30.351988  RX DATLAT        : PASS

 6012 23:28:30.355528  RX DQ/DQS(Engine): PASS

 6013 23:28:30.355595  TX OE            : NO K

 6014 23:28:30.358719  All Pass.

 6015 23:28:30.358800  

 6016 23:28:30.358881  DramC Write-DBI off

 6017 23:28:30.361672  	PER_BANK_REFRESH: Hybrid Mode

 6018 23:28:30.365192  TX_TRACKING: ON

 6019 23:28:30.371955  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0

 6020 23:28:30.375475  [FAST_K] Save calibration result to emmc

 6021 23:28:30.378265  dramc_set_vcore_voltage set vcore to 650000

 6022 23:28:30.381535  Read voltage for 400, 6

 6023 23:28:30.381667  Vio18 = 0

 6024 23:28:30.385258  Vcore = 650000

 6025 23:28:30.385333  Vdram = 0

 6026 23:28:30.385396  Vddq = 0

 6027 23:28:30.388555  Vmddr = 0

 6028 23:28:30.392208  [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0

 6029 23:28:30.398508  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 6030 23:28:30.398580  MEM_TYPE=3, freq_sel=20

 6031 23:28:30.401979  sv_algorithm_assistance_LP4_800 

 6032 23:28:30.408231  ============ PULL DRAM RESETB DOWN ============

 6033 23:28:30.411532  ========== PULL DRAM RESETB DOWN end =========

 6034 23:28:30.415017  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6035 23:28:30.418169  =================================== 

 6036 23:28:30.422042  LPDDR4 DRAM CONFIGURATION

 6037 23:28:30.424810  =================================== 

 6038 23:28:30.428642  EX_ROW_EN[0]    = 0x0

 6039 23:28:30.428717  EX_ROW_EN[1]    = 0x0

 6040 23:28:30.431820  LP4Y_EN      = 0x0

 6041 23:28:30.431984  WORK_FSP     = 0x0

 6042 23:28:30.435282  WL           = 0x2

 6043 23:28:30.435414  RL           = 0x2

 6044 23:28:30.438723  BL           = 0x2

 6045 23:28:30.438878  RPST         = 0x0

 6046 23:28:30.441543  RD_PRE       = 0x0

 6047 23:28:30.441691  WR_PRE       = 0x1

 6048 23:28:30.445027  WR_PST       = 0x0

 6049 23:28:30.445206  DBI_WR       = 0x0

 6050 23:28:30.448580  DBI_RD       = 0x0

 6051 23:28:30.448771  OTF          = 0x1

 6052 23:28:30.451910  =================================== 

 6053 23:28:30.454977  =================================== 

 6054 23:28:30.458313  ANA top config

 6055 23:28:30.461949  =================================== 

 6056 23:28:30.462083  DLL_ASYNC_EN            =  0

 6057 23:28:30.465266  ALL_SLAVE_EN            =  1

 6058 23:28:30.468475  NEW_RANK_MODE           =  1

 6059 23:28:30.471822  DLL_IDLE_MODE           =  1

 6060 23:28:30.474933  LP45_APHY_COMB_EN       =  1

 6061 23:28:30.475222  TX_ODT_DIS              =  1

 6062 23:28:30.478307  NEW_8X_MODE             =  1

 6063 23:28:30.481916  =================================== 

 6064 23:28:30.485485  =================================== 

 6065 23:28:30.488779  data_rate                  =  800

 6066 23:28:30.491820  CKR                        = 1

 6067 23:28:30.495243  DQ_P2S_RATIO               = 4

 6068 23:28:30.498431  =================================== 

 6069 23:28:30.501702  CA_P2S_RATIO               = 4

 6070 23:28:30.502162  DQ_CA_OPEN                 = 0

 6071 23:28:30.505182  DQ_SEMI_OPEN               = 1

 6072 23:28:30.508534  CA_SEMI_OPEN               = 1

 6073 23:28:30.511715  CA_FULL_RATE               = 0

 6074 23:28:30.515080  DQ_CKDIV4_EN               = 0

 6075 23:28:30.518668  CA_CKDIV4_EN               = 1

 6076 23:28:30.519126  CA_PREDIV_EN               = 0

 6077 23:28:30.521700  PH8_DLY                    = 0

 6078 23:28:30.525167  SEMI_OPEN_CA_PICK_MCK_RATIO= 4

 6079 23:28:30.528597  DQ_AAMCK_DIV               = 0

 6080 23:28:30.531969  CA_AAMCK_DIV               = 0

 6081 23:28:30.534741  CA_ADMCK_DIV               = 4

 6082 23:28:30.535199  DQ_TRACK_CA_EN             = 0

 6083 23:28:30.537951  CA_PICK                    = 800

 6084 23:28:30.541263  CA_MCKIO                   = 400

 6085 23:28:30.545018  MCKIO_SEMI                 = 400

 6086 23:28:30.547879  PLL_FREQ                   = 3016

 6087 23:28:30.551307  DQ_UI_PI_RATIO             = 32

 6088 23:28:30.554617  CA_UI_PI_RATIO             = 32

 6089 23:28:30.557965  =================================== 

 6090 23:28:30.561011  =================================== 

 6091 23:28:30.561488  memory_type:LPDDR4         

 6092 23:28:30.564712  GP_NUM     : 10       

 6093 23:28:30.568044  SRAM_EN    : 1       

 6094 23:28:30.568579  MD32_EN    : 0       

 6095 23:28:30.571272  =================================== 

 6096 23:28:30.574508  [ANA_INIT] >>>>>>>>>>>>>> 

 6097 23:28:30.578033  <<<<<< [CONFIGURE PHASE]: ANA_TX

 6098 23:28:30.581334  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 6099 23:28:30.584210  =================================== 

 6100 23:28:30.587674  data_rate = 800,PCW = 0X7400

 6101 23:28:30.591461  =================================== 

 6102 23:28:30.594173  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 6103 23:28:30.597519  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6104 23:28:30.611125  WARN: tr->DQ_AAMCK_DIV=  0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 6105 23:28:30.614573  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 6106 23:28:30.617668  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 6107 23:28:30.620336  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 6108 23:28:30.623714  [ANA_INIT] flow start 

 6109 23:28:30.623799  [ANA_INIT] PLL >>>>>>>> 

 6110 23:28:30.627557  [ANA_INIT] PLL <<<<<<<< 

 6111 23:28:30.630533  [ANA_INIT] MIDPI >>>>>>>> 

 6112 23:28:30.633540  [ANA_INIT] MIDPI <<<<<<<< 

 6113 23:28:30.633664  [ANA_INIT] DLL >>>>>>>> 

 6114 23:28:30.637495  [ANA_INIT] flow end 

 6115 23:28:30.640463  ============ LP4 DIFF to SE enter ============

 6116 23:28:30.643482  ============ LP4 DIFF to SE exit  ============

 6117 23:28:30.646967  [ANA_INIT] <<<<<<<<<<<<< 

 6118 23:28:30.650694  [Flow] Enable top DCM control >>>>> 

 6119 23:28:30.653691  [Flow] Enable top DCM control <<<<< 

 6120 23:28:30.656767  Enable DLL master slave shuffle 

 6121 23:28:30.663706  ============================================================== 

 6122 23:28:30.663789  Gating Mode config

 6123 23:28:30.670230  ============================================================== 

 6124 23:28:30.670315  Config description: 

 6125 23:28:30.680109  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 6126 23:28:30.686920  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 6127 23:28:30.693373  SELPH_MODE            0: By rank         1: By Phase 

 6128 23:28:30.696632  ============================================================== 

 6129 23:28:30.699965  GAT_TRACK_EN                 =  0

 6130 23:28:30.703211  RX_GATING_MODE               =  2

 6131 23:28:30.706950  RX_GATING_TRACK_MODE         =  2

 6132 23:28:30.709914  SELPH_MODE                   =  1

 6133 23:28:30.713252  PICG_EARLY_EN                =  1

 6134 23:28:30.716680  VALID_LAT_VALUE              =  1

 6135 23:28:30.723029  ============================================================== 

 6136 23:28:30.726933  Enter into Gating configuration >>>> 

 6137 23:28:30.729956  Exit from Gating configuration <<<< 

 6138 23:28:30.730033  Enter into  DVFS_PRE_config >>>>> 

 6139 23:28:30.743185  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 6140 23:28:30.746656  Exit from  DVFS_PRE_config <<<<< 

 6141 23:28:30.749889  Enter into PICG configuration >>>> 

 6142 23:28:30.753196  Exit from PICG configuration <<<< 

 6143 23:28:30.753269  [RX_INPUT] configuration >>>>> 

 6144 23:28:30.756495  [RX_INPUT] configuration <<<<< 

 6145 23:28:30.762971  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 6146 23:28:30.766515  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 6147 23:28:30.773212  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 6148 23:28:30.779609  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 6149 23:28:30.786456  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 6150 23:28:30.793207  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 6151 23:28:30.796293  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 6152 23:28:30.800051  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 6153 23:28:30.806579  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 6154 23:28:30.809568  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 6155 23:28:30.812899  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 6156 23:28:30.816508  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6157 23:28:30.819377  =================================== 

 6158 23:28:30.822805  LPDDR4 DRAM CONFIGURATION

 6159 23:28:30.826035  =================================== 

 6160 23:28:30.829735  EX_ROW_EN[0]    = 0x0

 6161 23:28:30.829807  EX_ROW_EN[1]    = 0x0

 6162 23:28:30.832740  LP4Y_EN      = 0x0

 6163 23:28:30.832810  WORK_FSP     = 0x0

 6164 23:28:30.836036  WL           = 0x2

 6165 23:28:30.836104  RL           = 0x2

 6166 23:28:30.839721  BL           = 0x2

 6167 23:28:30.839792  RPST         = 0x0

 6168 23:28:30.843196  RD_PRE       = 0x0

 6169 23:28:30.843266  WR_PRE       = 0x1

 6170 23:28:30.846373  WR_PST       = 0x0

 6171 23:28:30.849613  DBI_WR       = 0x0

 6172 23:28:30.849700  DBI_RD       = 0x0

 6173 23:28:30.852626  OTF          = 0x1

 6174 23:28:30.856335  =================================== 

 6175 23:28:30.859662  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 6176 23:28:30.862765  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 6177 23:28:30.865955  [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2

 6178 23:28:30.869437  =================================== 

 6179 23:28:30.872351  LPDDR4 DRAM CONFIGURATION

 6180 23:28:30.875936  =================================== 

 6181 23:28:30.879277  EX_ROW_EN[0]    = 0x10

 6182 23:28:30.879350  EX_ROW_EN[1]    = 0x0

 6183 23:28:30.882659  LP4Y_EN      = 0x0

 6184 23:28:30.882729  WORK_FSP     = 0x0

 6185 23:28:30.886685  WL           = 0x2

 6186 23:28:30.886761  RL           = 0x2

 6187 23:28:30.888944  BL           = 0x2

 6188 23:28:30.889013  RPST         = 0x0

 6189 23:28:30.892689  RD_PRE       = 0x0

 6190 23:28:30.892759  WR_PRE       = 0x1

 6191 23:28:30.895937  WR_PST       = 0x0

 6192 23:28:30.896015  DBI_WR       = 0x0

 6193 23:28:30.899309  DBI_RD       = 0x0

 6194 23:28:30.899395  OTF          = 0x1

 6195 23:28:30.902521  =================================== 

 6196 23:28:30.909112  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 6197 23:28:30.914045  nWR fixed to 30

 6198 23:28:30.917514  [ModeRegInit_LP4] CH0 RK0

 6199 23:28:30.917653  [ModeRegInit_LP4] CH0 RK1

 6200 23:28:30.920518  [ModeRegInit_LP4] CH1 RK0

 6201 23:28:30.923877  [ModeRegInit_LP4] CH1 RK1

 6202 23:28:30.923950  match AC timing 19

 6203 23:28:30.930620  dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1

 6204 23:28:30.933822  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 6205 23:28:30.937172  [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8

 6206 23:28:30.943610  [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17

 6207 23:28:30.947394  [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)

 6208 23:28:30.947471  ==

 6209 23:28:30.950957  Dram Type= 6, Freq= 0, CH_0, rank 0

 6210 23:28:30.953913  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6211 23:28:30.954011  ==

 6212 23:28:30.960138  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6213 23:28:30.966987  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37

 6214 23:28:30.969923  [CA 0] Center 36 (8~64) winsize 57

 6215 23:28:30.973269  [CA 1] Center 36 (8~64) winsize 57

 6216 23:28:30.976675  [CA 2] Center 36 (8~64) winsize 57

 6217 23:28:30.980551  [CA 3] Center 36 (8~64) winsize 57

 6218 23:28:30.983458  [CA 4] Center 36 (8~64) winsize 57

 6219 23:28:30.983533  [CA 5] Center 36 (8~64) winsize 57

 6220 23:28:30.986694  

 6221 23:28:30.990236  [CmdBusTrainingLP45] Vref(ca) range 1: 37

 6222 23:28:30.990308  

 6223 23:28:30.993505  [CATrainingPosCal] consider 1 rank data

 6224 23:28:30.996839  u2DelayCellTimex100 = 270/100 ps

 6225 23:28:31.000288  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6226 23:28:31.003385  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6227 23:28:31.006453  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6228 23:28:31.009976  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6229 23:28:31.013327  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6230 23:28:31.017150  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6231 23:28:31.017226  

 6232 23:28:31.020186  CA PerBit enable=1, Macro0, CA PI delay=36

 6233 23:28:31.020286  

 6234 23:28:31.023278  [CBTSetCACLKResult] CA Dly = 36

 6235 23:28:31.026329  CS Dly: 1 (0~32)

 6236 23:28:31.026401  ==

 6237 23:28:31.029887  Dram Type= 6, Freq= 0, CH_0, rank 1

 6238 23:28:31.033404  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6239 23:28:31.033502  ==

 6240 23:28:31.039718  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6241 23:28:31.046255  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6242 23:28:31.049706  [CA 0] Center 36 (8~64) winsize 57

 6243 23:28:31.049783  [CA 1] Center 36 (8~64) winsize 57

 6244 23:28:31.053109  [CA 2] Center 36 (8~64) winsize 57

 6245 23:28:31.056307  [CA 3] Center 36 (8~64) winsize 57

 6246 23:28:31.059677  [CA 4] Center 36 (8~64) winsize 57

 6247 23:28:31.063386  [CA 5] Center 36 (8~64) winsize 57

 6248 23:28:31.063459  

 6249 23:28:31.067026  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6250 23:28:31.067124  

 6251 23:28:31.069703  [CATrainingPosCal] consider 2 rank data

 6252 23:28:31.072894  u2DelayCellTimex100 = 270/100 ps

 6253 23:28:31.076539  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6254 23:28:31.083167  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6255 23:28:31.086451  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6256 23:28:31.089500  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6257 23:28:31.092873  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6258 23:28:31.096004  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6259 23:28:31.096076  

 6260 23:28:31.099507  CA PerBit enable=1, Macro0, CA PI delay=36

 6261 23:28:31.099578  

 6262 23:28:31.102877  [CBTSetCACLKResult] CA Dly = 36

 6263 23:28:31.106234  CS Dly: 1 (0~32)

 6264 23:28:31.106314  

 6265 23:28:31.109426  ----->DramcWriteLeveling(PI) begin...

 6266 23:28:31.109525  ==

 6267 23:28:31.112644  Dram Type= 6, Freq= 0, CH_0, rank 0

 6268 23:28:31.116175  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6269 23:28:31.116256  ==

 6270 23:28:31.119595  Write leveling (Byte 0): 40 => 8

 6271 23:28:31.122791  Write leveling (Byte 1): 40 => 8

 6272 23:28:31.125849  DramcWriteLeveling(PI) end<-----

 6273 23:28:31.125931  

 6274 23:28:31.125993  ==

 6275 23:28:31.129199  Dram Type= 6, Freq= 0, CH_0, rank 0

 6276 23:28:31.132443  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6277 23:28:31.132519  ==

 6278 23:28:31.135962  [Gating] SW mode calibration

 6279 23:28:31.142544  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6280 23:28:31.149866  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6281 23:28:31.153000   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6282 23:28:31.156256   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6283 23:28:31.162529   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6284 23:28:31.166242   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6285 23:28:31.169391   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6286 23:28:31.175781   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6287 23:28:31.179003   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6288 23:28:31.182616   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6289 23:28:31.189264   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6290 23:28:31.189353  Total UI for P1: 0, mck2ui 16

 6291 23:28:31.192291  best dqsien dly found for B0: ( 0, 14, 24)

 6292 23:28:31.195545  Total UI for P1: 0, mck2ui 16

 6293 23:28:31.199057  best dqsien dly found for B1: ( 0, 14, 24)

 6294 23:28:31.202961  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6295 23:28:31.208770  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6296 23:28:31.208853  

 6297 23:28:31.212336  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6298 23:28:31.215499  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6299 23:28:31.219109  [Gating] SW calibration Done

 6300 23:28:31.219185  ==

 6301 23:28:31.222640  Dram Type= 6, Freq= 0, CH_0, rank 0

 6302 23:28:31.225709  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6303 23:28:31.225785  ==

 6304 23:28:31.228804  RX Vref Scan: 0

 6305 23:28:31.228887  

 6306 23:28:31.228949  RX Vref 0 -> 0, step: 1

 6307 23:28:31.229008  

 6308 23:28:31.232179  RX Delay -410 -> 252, step: 16

 6309 23:28:31.235562  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6310 23:28:31.242181  iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480

 6311 23:28:31.245597  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6312 23:28:31.248852  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6313 23:28:31.252298  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6314 23:28:31.258818  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6315 23:28:31.262260  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6316 23:28:31.265319  iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480

 6317 23:28:31.268799  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6318 23:28:31.275676  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6319 23:28:31.278959  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6320 23:28:31.282147  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6321 23:28:31.285485  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6322 23:28:31.292518  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6323 23:28:31.295731  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6324 23:28:31.298916  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6325 23:28:31.299005  ==

 6326 23:28:31.302318  Dram Type= 6, Freq= 0, CH_0, rank 0

 6327 23:28:31.308446  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6328 23:28:31.308524  ==

 6329 23:28:31.308597  DQS Delay:

 6330 23:28:31.312183  DQS0 = 27, DQS1 = 35

 6331 23:28:31.312290  DQM Delay:

 6332 23:28:31.312381  DQM0 = 10, DQM1 = 11

 6333 23:28:31.315564  DQ Delay:

 6334 23:28:31.318948  DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8

 6335 23:28:31.319023  DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16

 6336 23:28:31.321972  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6337 23:28:31.325115  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6338 23:28:31.325202  

 6339 23:28:31.329158  

 6340 23:28:31.329267  ==

 6341 23:28:31.332219  Dram Type= 6, Freq= 0, CH_0, rank 0

 6342 23:28:31.335352  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6343 23:28:31.335434  ==

 6344 23:28:31.335496  

 6345 23:28:31.335554  

 6346 23:28:31.338528  	TX Vref Scan disable

 6347 23:28:31.338596   == TX Byte 0 ==

 6348 23:28:31.342243  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6349 23:28:31.348749  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6350 23:28:31.348831   == TX Byte 1 ==

 6351 23:28:31.351899  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6352 23:28:31.358737  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6353 23:28:31.358820  ==

 6354 23:28:31.362206  Dram Type= 6, Freq= 0, CH_0, rank 0

 6355 23:28:31.365245  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6356 23:28:31.365326  ==

 6357 23:28:31.365407  

 6358 23:28:31.365528  

 6359 23:28:31.368251  	TX Vref Scan disable

 6360 23:28:31.368320   == TX Byte 0 ==

 6361 23:28:31.371638  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6362 23:28:31.378579  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6363 23:28:31.378654   == TX Byte 1 ==

 6364 23:28:31.381740  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6365 23:28:31.388325  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6366 23:28:31.388398  

 6367 23:28:31.388458  [DATLAT]

 6368 23:28:31.391799  Freq=400, CH0 RK0

 6369 23:28:31.391878  

 6370 23:28:31.391938  DATLAT Default: 0xf

 6371 23:28:31.394879  0, 0xFFFF, sum = 0

 6372 23:28:31.394952  1, 0xFFFF, sum = 0

 6373 23:28:31.397810  2, 0xFFFF, sum = 0

 6374 23:28:31.397918  3, 0xFFFF, sum = 0

 6375 23:28:31.401409  4, 0xFFFF, sum = 0

 6376 23:28:31.401520  5, 0xFFFF, sum = 0

 6377 23:28:31.404501  6, 0xFFFF, sum = 0

 6378 23:28:31.404600  7, 0xFFFF, sum = 0

 6379 23:28:31.408129  8, 0xFFFF, sum = 0

 6380 23:28:31.408202  9, 0xFFFF, sum = 0

 6381 23:28:31.411288  10, 0xFFFF, sum = 0

 6382 23:28:31.411373  11, 0xFFFF, sum = 0

 6383 23:28:31.414661  12, 0xFFFF, sum = 0

 6384 23:28:31.414731  13, 0x0, sum = 1

 6385 23:28:31.417927  14, 0x0, sum = 2

 6386 23:28:31.417998  15, 0x0, sum = 3

 6387 23:28:31.420997  16, 0x0, sum = 4

 6388 23:28:31.421069  best_step = 14

 6389 23:28:31.421137  

 6390 23:28:31.421195  ==

 6391 23:28:31.424389  Dram Type= 6, Freq= 0, CH_0, rank 0

 6392 23:28:31.431215  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6393 23:28:31.431299  ==

 6394 23:28:31.431362  RX Vref Scan: 1

 6395 23:28:31.431434  

 6396 23:28:31.434384  RX Vref 0 -> 0, step: 1

 6397 23:28:31.434462  

 6398 23:28:31.437611  RX Delay -311 -> 252, step: 8

 6399 23:28:31.437696  

 6400 23:28:31.441244  Set Vref, RX VrefLevel [Byte0]: 57

 6401 23:28:31.444739                           [Byte1]: 55

 6402 23:28:31.444812  

 6403 23:28:31.448008  Final RX Vref Byte 0 = 57 to rank0

 6404 23:28:31.450946  Final RX Vref Byte 1 = 55 to rank0

 6405 23:28:31.454437  Final RX Vref Byte 0 = 57 to rank1

 6406 23:28:31.457539  Final RX Vref Byte 1 = 55 to rank1==

 6407 23:28:31.461280  Dram Type= 6, Freq= 0, CH_0, rank 0

 6408 23:28:31.464641  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6409 23:28:31.464715  ==

 6410 23:28:31.468078  DQS Delay:

 6411 23:28:31.468161  DQS0 = 28, DQS1 = 36

 6412 23:28:31.471171  DQM Delay:

 6413 23:28:31.471251  DQM0 = 10, DQM1 = 13

 6414 23:28:31.474430  DQ Delay:

 6415 23:28:31.474501  DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8

 6416 23:28:31.478112  DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16

 6417 23:28:31.481201  DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4

 6418 23:28:31.484624  DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20

 6419 23:28:31.484694  

 6420 23:28:31.484764  

 6421 23:28:31.494434  [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps

 6422 23:28:31.497751  CH0 RK0: MR19=C0C, MR18=C8B5

 6423 23:28:31.500976  CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265

 6424 23:28:31.504238  ==

 6425 23:28:31.507623  Dram Type= 6, Freq= 0, CH_0, rank 1

 6426 23:28:31.511027  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6427 23:28:31.511101  ==

 6428 23:28:31.514586  [Gating] SW mode calibration

 6429 23:28:31.520969  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6430 23:28:31.524377  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6431 23:28:31.530884   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6432 23:28:31.534140   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6433 23:28:31.537808   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6434 23:28:31.544550   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6435 23:28:31.547715   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6436 23:28:31.551039   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6437 23:28:31.557412   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6438 23:28:31.560888   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6439 23:28:31.564370   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6440 23:28:31.567253  Total UI for P1: 0, mck2ui 16

 6441 23:28:31.570745  best dqsien dly found for B0: ( 0, 14, 24)

 6442 23:28:31.574076  Total UI for P1: 0, mck2ui 16

 6443 23:28:31.577655  best dqsien dly found for B1: ( 0, 14, 24)

 6444 23:28:31.581088  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6445 23:28:31.584749  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6446 23:28:31.584832  

 6447 23:28:31.590664  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6448 23:28:31.593838  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6449 23:28:31.593918  [Gating] SW calibration Done

 6450 23:28:31.597206  ==

 6451 23:28:31.600436  Dram Type= 6, Freq= 0, CH_0, rank 1

 6452 23:28:31.604095  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6453 23:28:31.604178  ==

 6454 23:28:31.604243  RX Vref Scan: 0

 6455 23:28:31.604313  

 6456 23:28:31.607114  RX Vref 0 -> 0, step: 1

 6457 23:28:31.607187  

 6458 23:28:31.610626  RX Delay -410 -> 252, step: 16

 6459 23:28:31.613736  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6460 23:28:31.617187  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6461 23:28:31.624159  iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464

 6462 23:28:31.627466  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6463 23:28:31.630671  iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480

 6464 23:28:31.634006  iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480

 6465 23:28:31.640273  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6466 23:28:31.643749  iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464

 6467 23:28:31.647136  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6468 23:28:31.650632  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6469 23:28:31.657070  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6470 23:28:31.660473  iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464

 6471 23:28:31.663363  iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464

 6472 23:28:31.670048  iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464

 6473 23:28:31.673260  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6474 23:28:31.677492  iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464

 6475 23:28:31.677646  ==

 6476 23:28:31.680092  Dram Type= 6, Freq= 0, CH_0, rank 1

 6477 23:28:31.683826  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6478 23:28:31.683903  ==

 6479 23:28:31.687008  DQS Delay:

 6480 23:28:31.687107  DQS0 = 27, DQS1 = 35

 6481 23:28:31.689939  DQM Delay:

 6482 23:28:31.690044  DQM0 = 12, DQM1 = 10

 6483 23:28:31.693780  DQ Delay:

 6484 23:28:31.693862  DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8

 6485 23:28:31.696904  DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24

 6486 23:28:31.700060  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0

 6487 23:28:31.703253  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16

 6488 23:28:31.703326  

 6489 23:28:31.703412  

 6490 23:28:31.703508  ==

 6491 23:28:31.706536  Dram Type= 6, Freq= 0, CH_0, rank 1

 6492 23:28:31.713279  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6493 23:28:31.713355  ==

 6494 23:28:31.713436  

 6495 23:28:31.713496  

 6496 23:28:31.713554  	TX Vref Scan disable

 6497 23:28:31.716861   == TX Byte 0 ==

 6498 23:28:31.720117  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6499 23:28:31.723442  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6500 23:28:31.726708   == TX Byte 1 ==

 6501 23:28:31.730059  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6502 23:28:31.733733  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6503 23:28:31.733804  ==

 6504 23:28:31.736370  Dram Type= 6, Freq= 0, CH_0, rank 1

 6505 23:28:31.743012  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6506 23:28:31.743118  ==

 6507 23:28:31.743210  

 6508 23:28:31.743295  

 6509 23:28:31.743392  	TX Vref Scan disable

 6510 23:28:31.746519   == TX Byte 0 ==

 6511 23:28:31.750136  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6512 23:28:31.753427  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6513 23:28:31.756409   == TX Byte 1 ==

 6514 23:28:31.759806  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6515 23:28:31.763294  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6516 23:28:31.763367  

 6517 23:28:31.766577  [DATLAT]

 6518 23:28:31.766648  Freq=400, CH0 RK1

 6519 23:28:31.766721  

 6520 23:28:31.769726  DATLAT Default: 0xe

 6521 23:28:31.769808  0, 0xFFFF, sum = 0

 6522 23:28:31.773449  1, 0xFFFF, sum = 0

 6523 23:28:31.773526  2, 0xFFFF, sum = 0

 6524 23:28:31.776687  3, 0xFFFF, sum = 0

 6525 23:28:31.776761  4, 0xFFFF, sum = 0

 6526 23:28:31.779871  5, 0xFFFF, sum = 0

 6527 23:28:31.779955  6, 0xFFFF, sum = 0

 6528 23:28:31.783194  7, 0xFFFF, sum = 0

 6529 23:28:31.783266  8, 0xFFFF, sum = 0

 6530 23:28:31.786223  9, 0xFFFF, sum = 0

 6531 23:28:31.789862  10, 0xFFFF, sum = 0

 6532 23:28:31.789952  11, 0xFFFF, sum = 0

 6533 23:28:31.792953  12, 0xFFFF, sum = 0

 6534 23:28:31.793034  13, 0x0, sum = 1

 6535 23:28:31.796614  14, 0x0, sum = 2

 6536 23:28:31.796698  15, 0x0, sum = 3

 6537 23:28:31.796762  16, 0x0, sum = 4

 6538 23:28:31.800073  best_step = 14

 6539 23:28:31.800150  

 6540 23:28:31.800213  ==

 6541 23:28:31.803572  Dram Type= 6, Freq= 0, CH_0, rank 1

 6542 23:28:31.806554  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6543 23:28:31.806635  ==

 6544 23:28:31.809550  RX Vref Scan: 0

 6545 23:28:31.809662  

 6546 23:28:31.809724  RX Vref 0 -> 0, step: 1

 6547 23:28:31.813467  

 6548 23:28:31.813539  RX Delay -311 -> 252, step: 8

 6549 23:28:31.821444  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6550 23:28:31.825171  iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440

 6551 23:28:31.828106  iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456

 6552 23:28:31.831488  iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448

 6553 23:28:31.837932  iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448

 6554 23:28:31.841268  iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448

 6555 23:28:31.844511  iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440

 6556 23:28:31.847759  iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448

 6557 23:28:31.854362  iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448

 6558 23:28:31.857523  iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448

 6559 23:28:31.861034  iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440

 6560 23:28:31.867662  iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448

 6561 23:28:31.871230  iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448

 6562 23:28:31.874377  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6563 23:28:31.877841  iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440

 6564 23:28:31.884439  iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448

 6565 23:28:31.884520  ==

 6566 23:28:31.887691  Dram Type= 6, Freq= 0, CH_0, rank 1

 6567 23:28:31.890928  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6568 23:28:31.891002  ==

 6569 23:28:31.891065  DQS Delay:

 6570 23:28:31.894454  DQS0 = 24, DQS1 = 32

 6571 23:28:31.894531  DQM Delay:

 6572 23:28:31.897783  DQM0 = 8, DQM1 = 10

 6573 23:28:31.897857  DQ Delay:

 6574 23:28:31.900892  DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8

 6575 23:28:31.904119  DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16

 6576 23:28:31.907377  DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0

 6577 23:28:31.911006  DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16

 6578 23:28:31.911078  

 6579 23:28:31.911140  

 6580 23:28:31.917972  [DQSOSCAuto] RK1, (LSB)MR18= 0xb252, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps

 6581 23:28:31.921135  CH0 RK1: MR19=C0C, MR18=B252

 6582 23:28:31.927362  CH0_RK1: MR19=0xC0C, MR18=0xB252, DQSOSC=387, MR23=63, INC=394, DEC=262

 6583 23:28:31.930555  [RxdqsGatingPostProcess] freq 400

 6584 23:28:31.937431  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6585 23:28:31.937507  best DQS0 dly(2T, 0.5T) = (0, 10)

 6586 23:28:31.940992  best DQS1 dly(2T, 0.5T) = (0, 10)

 6587 23:28:31.944412  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6588 23:28:31.947155  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6589 23:28:31.950948  best DQS0 dly(2T, 0.5T) = (0, 10)

 6590 23:28:31.954104  best DQS1 dly(2T, 0.5T) = (0, 10)

 6591 23:28:31.956991  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6592 23:28:31.960668  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6593 23:28:31.963889  Pre-setting of DQS Precalculation

 6594 23:28:31.970768  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6595 23:28:31.970843  ==

 6596 23:28:31.974122  Dram Type= 6, Freq= 0, CH_1, rank 0

 6597 23:28:31.977494  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6598 23:28:31.977627  ==

 6599 23:28:31.983813  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6600 23:28:31.987183  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6601 23:28:31.990822  [CA 0] Center 36 (8~64) winsize 57

 6602 23:28:31.994042  [CA 1] Center 36 (8~64) winsize 57

 6603 23:28:31.997136  [CA 2] Center 36 (8~64) winsize 57

 6604 23:28:32.000428  [CA 3] Center 36 (8~64) winsize 57

 6605 23:28:32.003934  [CA 4] Center 36 (8~64) winsize 57

 6606 23:28:32.007170  [CA 5] Center 36 (8~64) winsize 57

 6607 23:28:32.007247  

 6608 23:28:32.010429  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6609 23:28:32.010505  

 6610 23:28:32.013911  [CATrainingPosCal] consider 1 rank data

 6611 23:28:32.016779  u2DelayCellTimex100 = 270/100 ps

 6612 23:28:32.019955  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6613 23:28:32.023536  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6614 23:28:32.027083  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6615 23:28:32.033595  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6616 23:28:32.036854  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6617 23:28:32.040161  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6618 23:28:32.040234  

 6619 23:28:32.043497  CA PerBit enable=1, Macro0, CA PI delay=36

 6620 23:28:32.043569  

 6621 23:28:32.047056  [CBTSetCACLKResult] CA Dly = 36

 6622 23:28:32.047171  CS Dly: 1 (0~32)

 6623 23:28:32.047263  ==

 6624 23:28:32.050131  Dram Type= 6, Freq= 0, CH_1, rank 1

 6625 23:28:32.057088  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6626 23:28:32.057167  ==

 6627 23:28:32.060181  pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0

 6628 23:28:32.067139  u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35

 6629 23:28:32.070067  [CA 0] Center 36 (8~64) winsize 57

 6630 23:28:32.073841  [CA 1] Center 36 (8~64) winsize 57

 6631 23:28:32.076901  [CA 2] Center 36 (8~64) winsize 57

 6632 23:28:32.080314  [CA 3] Center 36 (8~64) winsize 57

 6633 23:28:32.083622  [CA 4] Center 36 (8~64) winsize 57

 6634 23:28:32.087212  [CA 5] Center 36 (8~64) winsize 57

 6635 23:28:32.087425  

 6636 23:28:32.090670  [CmdBusTrainingLP45] Vref(ca) range 1: 35

 6637 23:28:32.090874  

 6638 23:28:32.094098  [CATrainingPosCal] consider 2 rank data

 6639 23:28:32.097398  u2DelayCellTimex100 = 270/100 ps

 6640 23:28:32.100291  CA0 delay=36 (8~64),Diff = 0 PI (0 cell)

 6641 23:28:32.103689  CA1 delay=36 (8~64),Diff = 0 PI (0 cell)

 6642 23:28:32.106613  CA2 delay=36 (8~64),Diff = 0 PI (0 cell)

 6643 23:28:32.110662  CA3 delay=36 (8~64),Diff = 0 PI (0 cell)

 6644 23:28:32.113872  CA4 delay=36 (8~64),Diff = 0 PI (0 cell)

 6645 23:28:32.117195  CA5 delay=36 (8~64),Diff = 0 PI (0 cell)

 6646 23:28:32.117647  

 6647 23:28:32.123841  CA PerBit enable=1, Macro0, CA PI delay=36

 6648 23:28:32.124221  

 6649 23:28:32.124520  [CBTSetCACLKResult] CA Dly = 36

 6650 23:28:32.127535  CS Dly: 1 (0~32)

 6651 23:28:32.128092  

 6652 23:28:32.130307  ----->DramcWriteLeveling(PI) begin...

 6653 23:28:32.130813  ==

 6654 23:28:32.134029  Dram Type= 6, Freq= 0, CH_1, rank 0

 6655 23:28:32.137428  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6656 23:28:32.138030  ==

 6657 23:28:32.140034  Write leveling (Byte 0): 40 => 8

 6658 23:28:32.143693  Write leveling (Byte 1): 40 => 8

 6659 23:28:32.146916  DramcWriteLeveling(PI) end<-----

 6660 23:28:32.147493  

 6661 23:28:32.148018  ==

 6662 23:28:32.150162  Dram Type= 6, Freq= 0, CH_1, rank 0

 6663 23:28:32.153174  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6664 23:28:32.156955  ==

 6665 23:28:32.157412  [Gating] SW mode calibration

 6666 23:28:32.166912  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6667 23:28:32.169880  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6668 23:28:32.173100   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6669 23:28:32.179942   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6670 23:28:32.183009   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6671 23:28:32.186342   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6672 23:28:32.192997   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6673 23:28:32.196527   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6674 23:28:32.199752   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6675 23:28:32.206282   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6676 23:28:32.209640   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6677 23:28:32.213554  Total UI for P1: 0, mck2ui 16

 6678 23:28:32.216032  best dqsien dly found for B0: ( 0, 14, 24)

 6679 23:28:32.219498  Total UI for P1: 0, mck2ui 16

 6680 23:28:32.223176  best dqsien dly found for B1: ( 0, 14, 24)

 6681 23:28:32.226009  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6682 23:28:32.229394  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6683 23:28:32.229977  

 6684 23:28:32.232785  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6685 23:28:32.236296  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6686 23:28:32.239650  [Gating] SW calibration Done

 6687 23:28:32.240117  ==

 6688 23:28:32.243080  Dram Type= 6, Freq= 0, CH_1, rank 0

 6689 23:28:32.249683  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6690 23:28:32.250411  ==

 6691 23:28:32.250807  RX Vref Scan: 0

 6692 23:28:32.251145  

 6693 23:28:32.252895  RX Vref 0 -> 0, step: 1

 6694 23:28:32.253292  

 6695 23:28:32.256309  RX Delay -410 -> 252, step: 16

 6696 23:28:32.259591  iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480

 6697 23:28:32.262888  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6698 23:28:32.266250  iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464

 6699 23:28:32.272434  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6700 23:28:32.276110  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6701 23:28:32.279099  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6702 23:28:32.282977  iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480

 6703 23:28:32.289783  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6704 23:28:32.292860  iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464

 6705 23:28:32.296074  iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464

 6706 23:28:32.299022  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6707 23:28:32.305989  iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480

 6708 23:28:32.309895  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6709 23:28:32.312714  iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448

 6710 23:28:32.319174  iDelay=230, Bit 14, Center -11 (-250 ~ 229) 480

 6711 23:28:32.322976  iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464

 6712 23:28:32.323399  ==

 6713 23:28:32.325866  Dram Type= 6, Freq= 0, CH_1, rank 0

 6714 23:28:32.329370  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6715 23:28:32.329832  ==

 6716 23:28:32.330172  DQS Delay:

 6717 23:28:32.332513  DQS0 = 35, DQS1 = 35

 6718 23:28:32.332951  DQM Delay:

 6719 23:28:32.335958  DQM0 = 18, DQM1 = 16

 6720 23:28:32.336406  DQ Delay:

 6721 23:28:32.339164  DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16

 6722 23:28:32.342392  DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16

 6723 23:28:32.345780  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6724 23:28:32.349274  DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32

 6725 23:28:32.349824  

 6726 23:28:32.350299  

 6727 23:28:32.350756  ==

 6728 23:28:32.352712  Dram Type= 6, Freq= 0, CH_1, rank 0

 6729 23:28:32.356266  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6730 23:28:32.358953  ==

 6731 23:28:32.359415  

 6732 23:28:32.359938  

 6733 23:28:32.360394  	TX Vref Scan disable

 6734 23:28:32.362285   == TX Byte 0 ==

 6735 23:28:32.365438  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6736 23:28:32.368983  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6737 23:28:32.372421   == TX Byte 1 ==

 6738 23:28:32.375850  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6739 23:28:32.378755  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6740 23:28:32.379253  ==

 6741 23:28:32.382581  Dram Type= 6, Freq= 0, CH_1, rank 0

 6742 23:28:32.388854  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6743 23:28:32.389317  ==

 6744 23:28:32.389745  

 6745 23:28:32.390101  

 6746 23:28:32.390436  	TX Vref Scan disable

 6747 23:28:32.392462   == TX Byte 0 ==

 6748 23:28:32.395392  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6749 23:28:32.398573  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6750 23:28:32.402460   == TX Byte 1 ==

 6751 23:28:32.405496  Update DQ  dly =580 (4 ,2, 4)  DQ  OEN =(3 ,3)

 6752 23:28:32.409132  Update DQM dly =580 (4 ,2, 4)  DQM OEN =(3 ,3)

 6753 23:28:32.409789  

 6754 23:28:32.412195  [DATLAT]

 6755 23:28:32.412671  Freq=400, CH1 RK0

 6756 23:28:32.413101  

 6757 23:28:32.414986  DATLAT Default: 0xf

 6758 23:28:32.415057  0, 0xFFFF, sum = 0

 6759 23:28:32.418913  1, 0xFFFF, sum = 0

 6760 23:28:32.418992  2, 0xFFFF, sum = 0

 6761 23:28:32.421713  3, 0xFFFF, sum = 0

 6762 23:28:32.421800  4, 0xFFFF, sum = 0

 6763 23:28:32.425409  5, 0xFFFF, sum = 0

 6764 23:28:32.425492  6, 0xFFFF, sum = 0

 6765 23:28:32.428188  7, 0xFFFF, sum = 0

 6766 23:28:32.428268  8, 0xFFFF, sum = 0

 6767 23:28:32.431825  9, 0xFFFF, sum = 0

 6768 23:28:32.431908  10, 0xFFFF, sum = 0

 6769 23:28:32.435115  11, 0xFFFF, sum = 0

 6770 23:28:32.435185  12, 0xFFFF, sum = 0

 6771 23:28:32.438272  13, 0x0, sum = 1

 6772 23:28:32.438344  14, 0x0, sum = 2

 6773 23:28:32.441509  15, 0x0, sum = 3

 6774 23:28:32.441638  16, 0x0, sum = 4

 6775 23:28:32.444950  best_step = 14

 6776 23:28:32.445042  

 6777 23:28:32.445134  ==

 6778 23:28:32.448660  Dram Type= 6, Freq= 0, CH_1, rank 0

 6779 23:28:32.451888  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6780 23:28:32.451959  ==

 6781 23:28:32.455188  RX Vref Scan: 1

 6782 23:28:32.455270  

 6783 23:28:32.455332  RX Vref 0 -> 0, step: 1

 6784 23:28:32.455390  

 6785 23:28:32.458720  RX Delay -311 -> 252, step: 8

 6786 23:28:32.458794  

 6787 23:28:32.461541  Set Vref, RX VrefLevel [Byte0]: 53

 6788 23:28:32.464796                           [Byte1]: 55

 6789 23:28:32.469253  

 6790 23:28:32.469323  Final RX Vref Byte 0 = 53 to rank0

 6791 23:28:32.472532  Final RX Vref Byte 1 = 55 to rank0

 6792 23:28:32.475916  Final RX Vref Byte 0 = 53 to rank1

 6793 23:28:32.479510  Final RX Vref Byte 1 = 55 to rank1==

 6794 23:28:32.482810  Dram Type= 6, Freq= 0, CH_1, rank 0

 6795 23:28:32.489174  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6796 23:28:32.489252  ==

 6797 23:28:32.489317  DQS Delay:

 6798 23:28:32.493042  DQS0 = 32, DQS1 = 32

 6799 23:28:32.493112  DQM Delay:

 6800 23:28:32.493172  DQM0 = 13, DQM1 = 9

 6801 23:28:32.496263  DQ Delay:

 6802 23:28:32.499580  DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =16

 6803 23:28:32.499650  DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12

 6804 23:28:32.503013  DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0

 6805 23:28:32.506026  DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20

 6806 23:28:32.506100  

 6807 23:28:32.509445  

 6808 23:28:32.516245  [DQSOSCAuto] RK0, (LSB)MR18= 0x8bc4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps

 6809 23:28:32.519070  CH1 RK0: MR19=C0C, MR18=8BC4

 6810 23:28:32.526095  CH1_RK0: MR19=0xC0C, MR18=0x8BC4, DQSOSC=385, MR23=63, INC=398, DEC=265

 6811 23:28:32.526179  ==

 6812 23:28:32.529323  Dram Type= 6, Freq= 0, CH_1, rank 1

 6813 23:28:32.532739  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6814 23:28:32.532816  ==

 6815 23:28:32.536113  [Gating] SW mode calibration

 6816 23:28:32.542280  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1

 6817 23:28:32.549250  RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)

 6818 23:28:32.552874   0 11  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6819 23:28:32.555915   0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 6820 23:28:32.559209   0 12  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6821 23:28:32.565716   0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6822 23:28:32.569119   0 13  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6823 23:28:32.572393   0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6824 23:28:32.579550   0 14  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6825 23:28:32.582839   0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 6826 23:28:32.585840   0 15  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 6827 23:28:32.588978  Total UI for P1: 0, mck2ui 16

 6828 23:28:32.592508  best dqsien dly found for B0: ( 0, 14, 24)

 6829 23:28:32.595644  Total UI for P1: 0, mck2ui 16

 6830 23:28:32.599425  best dqsien dly found for B1: ( 0, 14, 24)

 6831 23:28:32.602585  best DQS0 dly(MCK, UI, PI) = (0, 14, 24)

 6832 23:28:32.605977  best DQS1 dly(MCK, UI, PI) = (0, 14, 24)

 6833 23:28:32.606051  

 6834 23:28:32.612727  best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6835 23:28:32.615701  best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)

 6836 23:28:32.619081  [Gating] SW calibration Done

 6837 23:28:32.619154  ==

 6838 23:28:32.622447  Dram Type= 6, Freq= 0, CH_1, rank 1

 6839 23:28:32.625773  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6840 23:28:32.625848  ==

 6841 23:28:32.625910  RX Vref Scan: 0

 6842 23:28:32.625968  

 6843 23:28:32.629083  RX Vref 0 -> 0, step: 1

 6844 23:28:32.629155  

 6845 23:28:32.632589  RX Delay -410 -> 252, step: 16

 6846 23:28:32.635578  iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464

 6847 23:28:32.642548  iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464

 6848 23:28:32.645869  iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448

 6849 23:28:32.649180  iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464

 6850 23:28:32.652644  iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464

 6851 23:28:32.655713  iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464

 6852 23:28:32.662486  iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464

 6853 23:28:32.665883  iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464

 6854 23:28:32.669207  iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448

 6855 23:28:32.672613  iDelay=230, Bit 9, Center -19 (-250 ~ 213) 464

 6856 23:28:32.678884  iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464

 6857 23:28:32.682311  iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464

 6858 23:28:32.685469  iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480

 6859 23:28:32.692406  iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480

 6860 23:28:32.696032  iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464

 6861 23:28:32.699282  iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480

 6862 23:28:32.699352  ==

 6863 23:28:32.702310  Dram Type= 6, Freq= 0, CH_1, rank 1

 6864 23:28:32.705484  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6865 23:28:32.705588  ==

 6866 23:28:32.708897  DQS Delay:

 6867 23:28:32.708977  DQS0 = 27, DQS1 = 27

 6868 23:28:32.712084  DQM Delay:

 6869 23:28:32.712157  DQM0 = 11, DQM1 = 10

 6870 23:28:32.715597  DQ Delay:

 6871 23:28:32.715669  DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8

 6872 23:28:32.719070  DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8

 6873 23:28:32.722064  DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8

 6874 23:28:32.725497  DQ12 =16, DQ13 =16, DQ14 =8, DQ15 =16

 6875 23:28:32.725612  

 6876 23:28:32.725693  

 6877 23:28:32.725751  ==

 6878 23:28:32.728583  Dram Type= 6, Freq= 0, CH_1, rank 1

 6879 23:28:32.735635  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6880 23:28:32.735708  ==

 6881 23:28:32.735770  

 6882 23:28:32.735828  

 6883 23:28:32.735888  	TX Vref Scan disable

 6884 23:28:32.738513   == TX Byte 0 ==

 6885 23:28:32.742185  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6886 23:28:32.745133  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6887 23:28:32.748653   == TX Byte 1 ==

 6888 23:28:32.751854  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6889 23:28:32.755350  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6890 23:28:32.755420  ==

 6891 23:28:32.758750  Dram Type= 6, Freq= 0, CH_1, rank 1

 6892 23:28:32.765513  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6893 23:28:32.765615  ==

 6894 23:28:32.765683  

 6895 23:28:32.765746  

 6896 23:28:32.765804  	TX Vref Scan disable

 6897 23:28:32.768716   == TX Byte 0 ==

 6898 23:28:32.771827  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6899 23:28:32.775128  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6900 23:28:32.778428   == TX Byte 1 ==

 6901 23:28:32.781959  Update DQ  dly =584 (4 ,2, 8)  DQ  OEN =(3 ,3)

 6902 23:28:32.785029  Update DQM dly =584 (4 ,2, 8)  DQM OEN =(3 ,3)

 6903 23:28:32.785101  

 6904 23:28:32.788654  [DATLAT]

 6905 23:28:32.788730  Freq=400, CH1 RK1

 6906 23:28:32.788792  

 6907 23:28:32.791750  DATLAT Default: 0xe

 6908 23:28:32.791823  0, 0xFFFF, sum = 0

 6909 23:28:32.794978  1, 0xFFFF, sum = 0

 6910 23:28:32.795048  2, 0xFFFF, sum = 0

 6911 23:28:32.798393  3, 0xFFFF, sum = 0

 6912 23:28:32.798483  4, 0xFFFF, sum = 0

 6913 23:28:32.801719  5, 0xFFFF, sum = 0

 6914 23:28:32.801793  6, 0xFFFF, sum = 0

 6915 23:28:32.805029  7, 0xFFFF, sum = 0

 6916 23:28:32.805107  8, 0xFFFF, sum = 0

 6917 23:28:32.808312  9, 0xFFFF, sum = 0

 6918 23:28:32.811447  10, 0xFFFF, sum = 0

 6919 23:28:32.811523  11, 0xFFFF, sum = 0

 6920 23:28:32.814979  12, 0xFFFF, sum = 0

 6921 23:28:32.815063  13, 0x0, sum = 1

 6922 23:28:32.818021  14, 0x0, sum = 2

 6923 23:28:32.818092  15, 0x0, sum = 3

 6924 23:28:32.821314  16, 0x0, sum = 4

 6925 23:28:32.821398  best_step = 14

 6926 23:28:32.821458  

 6927 23:28:32.821515  ==

 6928 23:28:32.824841  Dram Type= 6, Freq= 0, CH_1, rank 1

 6929 23:28:32.828267  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6930 23:28:32.828351  ==

 6931 23:28:32.831586  RX Vref Scan: 0

 6932 23:28:32.831659  

 6933 23:28:32.834490  RX Vref 0 -> 0, step: 1

 6934 23:28:32.834560  

 6935 23:28:32.834628  RX Delay -295 -> 252, step: 8

 6936 23:28:32.843065  iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448

 6937 23:28:32.846415  iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448

 6938 23:28:32.849685  iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440

 6939 23:28:32.852835  iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440

 6940 23:28:32.859405  iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440

 6941 23:28:32.863172  iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440

 6942 23:28:32.866433  iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448

 6943 23:28:32.869681  iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440

 6944 23:28:32.876294  iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456

 6945 23:28:32.879606  iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456

 6946 23:28:32.883016  iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456

 6947 23:28:32.886187  iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456

 6948 23:28:32.893167  iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456

 6949 23:28:32.896240  iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448

 6950 23:28:32.899708  iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448

 6951 23:28:32.906276  iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456

 6952 23:28:32.906359  ==

 6953 23:28:32.909563  Dram Type= 6, Freq= 0, CH_1, rank 1

 6954 23:28:32.912877  fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2

 6955 23:28:32.912960  ==

 6956 23:28:32.913025  DQS Delay:

 6957 23:28:32.916046  DQS0 = 28, DQS1 = 36

 6958 23:28:32.916124  DQM Delay:

 6959 23:28:32.919826  DQM0 = 10, DQM1 = 14

 6960 23:28:32.919903  DQ Delay:

 6961 23:28:32.922972  DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8

 6962 23:28:32.925869  DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8

 6963 23:28:32.929221  DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8

 6964 23:28:32.932528  DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24

 6965 23:28:32.932602  

 6966 23:28:32.932672  

 6967 23:28:32.939155  [DQSOSCAuto] RK1, (LSB)MR18= 0xc356, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 385 ps

 6968 23:28:32.942494  CH1 RK1: MR19=C0C, MR18=C356

 6969 23:28:32.949305  CH1_RK1: MR19=0xC0C, MR18=0xC356, DQSOSC=385, MR23=63, INC=398, DEC=265

 6970 23:28:32.952922  [RxdqsGatingPostProcess] freq 400

 6971 23:28:32.959031  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 6972 23:28:32.959105  best DQS0 dly(2T, 0.5T) = (0, 10)

 6973 23:28:32.962677  best DQS1 dly(2T, 0.5T) = (0, 10)

 6974 23:28:32.966081  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6975 23:28:32.969098  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6976 23:28:32.972525  best DQS0 dly(2T, 0.5T) = (0, 10)

 6977 23:28:32.975817  best DQS1 dly(2T, 0.5T) = (0, 10)

 6978 23:28:32.979263  best DQS0 P1 dly(2T, 0.5T) = (0, 12)

 6979 23:28:32.982517  best DQS1 P1 dly(2T, 0.5T) = (0, 12)

 6980 23:28:32.985949  Pre-setting of DQS Precalculation

 6981 23:28:32.988888  [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14

 6982 23:28:32.998956  sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6

 6983 23:28:33.005362  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 6984 23:28:33.005440  

 6985 23:28:33.005504  

 6986 23:28:33.009168  [Calibration Summary] 800 Mbps

 6987 23:28:33.009274  CH 0, Rank 0

 6988 23:28:33.012172  SW Impedance     : PASS

 6989 23:28:33.012243  DUTY Scan        : NO K

 6990 23:28:33.015422  ZQ Calibration   : PASS

 6991 23:28:33.018914  Jitter Meter     : NO K

 6992 23:28:33.018990  CBT Training     : PASS

 6993 23:28:33.022593  Write leveling   : PASS

 6994 23:28:33.025599  RX DQS gating    : PASS

 6995 23:28:33.025670  RX DQ/DQS(RDDQC) : PASS

 6996 23:28:33.028705  TX DQ/DQS        : PASS

 6997 23:28:33.032137  RX DATLAT        : PASS

 6998 23:28:33.032214  RX DQ/DQS(Engine): PASS

 6999 23:28:33.035681  TX OE            : NO K

 7000 23:28:33.035764  All Pass.

 7001 23:28:33.035827  

 7002 23:28:33.038865  CH 0, Rank 1

 7003 23:28:33.038943  SW Impedance     : PASS

 7004 23:28:33.042333  DUTY Scan        : NO K

 7005 23:28:33.045712  ZQ Calibration   : PASS

 7006 23:28:33.045782  Jitter Meter     : NO K

 7007 23:28:33.049044  CBT Training     : PASS

 7008 23:28:33.051968  Write leveling   : NO K

 7009 23:28:33.052043  RX DQS gating    : PASS

 7010 23:28:33.055299  RX DQ/DQS(RDDQC) : PASS

 7011 23:28:33.055369  TX DQ/DQS        : PASS

 7012 23:28:33.058767  RX DATLAT        : PASS

 7013 23:28:33.062075  RX DQ/DQS(Engine): PASS

 7014 23:28:33.062160  TX OE            : NO K

 7015 23:28:33.065395  All Pass.

 7016 23:28:33.065492  

 7017 23:28:33.065612  CH 1, Rank 0

 7018 23:28:33.068702  SW Impedance     : PASS

 7019 23:28:33.068781  DUTY Scan        : NO K

 7020 23:28:33.071939  ZQ Calibration   : PASS

 7021 23:28:33.074940  Jitter Meter     : NO K

 7022 23:28:33.075016  CBT Training     : PASS

 7023 23:28:33.078440  Write leveling   : PASS

 7024 23:28:33.081746  RX DQS gating    : PASS

 7025 23:28:33.081851  RX DQ/DQS(RDDQC) : PASS

 7026 23:28:33.085359  TX DQ/DQS        : PASS

 7027 23:28:33.088728  RX DATLAT        : PASS

 7028 23:28:33.088801  RX DQ/DQS(Engine): PASS

 7029 23:28:33.091671  TX OE            : NO K

 7030 23:28:33.091742  All Pass.

 7031 23:28:33.091805  

 7032 23:28:33.095410  CH 1, Rank 1

 7033 23:28:33.095484  SW Impedance     : PASS

 7034 23:28:33.098540  DUTY Scan        : NO K

 7035 23:28:33.101887  ZQ Calibration   : PASS

 7036 23:28:33.101959  Jitter Meter     : NO K

 7037 23:28:33.105038  CBT Training     : PASS

 7038 23:28:33.108639  Write leveling   : NO K

 7039 23:28:33.108720  RX DQS gating    : PASS

 7040 23:28:33.112400  RX DQ/DQS(RDDQC) : PASS

 7041 23:28:33.112477  TX DQ/DQS        : PASS

 7042 23:28:33.115279  RX DATLAT        : PASS

 7043 23:28:33.119200  RX DQ/DQS(Engine): PASS

 7044 23:28:33.119373  TX OE            : NO K

 7045 23:28:33.121742  All Pass.

 7046 23:28:33.121874  

 7047 23:28:33.121962  DramC Write-DBI off

 7048 23:28:33.125048  	PER_BANK_REFRESH: Hybrid Mode

 7049 23:28:33.128501  TX_TRACKING: ON

 7050 23:28:33.135182  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0

 7051 23:28:33.139116  [FAST_K] Save calibration result to emmc

 7052 23:28:33.141935  dramc_set_vcore_voltage set vcore to 725000

 7053 23:28:33.145229  Read voltage for 1600, 0

 7054 23:28:33.145464  Vio18 = 0

 7055 23:28:33.148746  Vcore = 725000

 7056 23:28:33.149005  Vdram = 0

 7057 23:28:33.149160  Vddq = 0

 7058 23:28:33.151677  Vmddr = 0

 7059 23:28:33.155036  [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0

 7060 23:28:33.161932  [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0

 7061 23:28:33.162170  MEM_TYPE=3, freq_sel=13

 7062 23:28:33.165447  sv_algorithm_assistance_LP4_3733 

 7063 23:28:33.172059  ============ PULL DRAM RESETB DOWN ============

 7064 23:28:33.175551  ========== PULL DRAM RESETB DOWN end =========

 7065 23:28:33.178553  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7066 23:28:33.182493  =================================== 

 7067 23:28:33.185560  LPDDR4 DRAM CONFIGURATION

 7068 23:28:33.188874  =================================== 

 7069 23:28:33.192287  EX_ROW_EN[0]    = 0x0

 7070 23:28:33.192843  EX_ROW_EN[1]    = 0x0

 7071 23:28:33.195579  LP4Y_EN      = 0x0

 7072 23:28:33.196136  WORK_FSP     = 0x1

 7073 23:28:33.198938  WL           = 0x5

 7074 23:28:33.199495  RL           = 0x5

 7075 23:28:33.202327  BL           = 0x2

 7076 23:28:33.202787  RPST         = 0x0

 7077 23:28:33.205315  RD_PRE       = 0x0

 7078 23:28:33.205808  WR_PRE       = 0x1

 7079 23:28:33.208551  WR_PST       = 0x1

 7080 23:28:33.209006  DBI_WR       = 0x0

 7081 23:28:33.212224  DBI_RD       = 0x0

 7082 23:28:33.212785  OTF          = 0x1

 7083 23:28:33.215127  =================================== 

 7084 23:28:33.218796  =================================== 

 7085 23:28:33.222324  ANA top config

 7086 23:28:33.225234  =================================== 

 7087 23:28:33.225717  DLL_ASYNC_EN            =  0

 7088 23:28:33.229199  ALL_SLAVE_EN            =  0

 7089 23:28:33.231914  NEW_RANK_MODE           =  1

 7090 23:28:33.235455  DLL_IDLE_MODE           =  1

 7091 23:28:33.239016  LP45_APHY_COMB_EN       =  1

 7092 23:28:33.239582  TX_ODT_DIS              =  0

 7093 23:28:33.242392  NEW_8X_MODE             =  1

 7094 23:28:33.245876  =================================== 

 7095 23:28:33.248951  =================================== 

 7096 23:28:33.252122  data_rate                  = 3200

 7097 23:28:33.255603  CKR                        = 1

 7098 23:28:33.258951  DQ_P2S_RATIO               = 8

 7099 23:28:33.262213  =================================== 

 7100 23:28:33.262670  CA_P2S_RATIO               = 8

 7101 23:28:33.265349  DQ_CA_OPEN                 = 0

 7102 23:28:33.269018  DQ_SEMI_OPEN               = 0

 7103 23:28:33.272308  CA_SEMI_OPEN               = 0

 7104 23:28:33.275357  CA_FULL_RATE               = 0

 7105 23:28:33.278836  DQ_CKDIV4_EN               = 0

 7106 23:28:33.279298  CA_CKDIV4_EN               = 0

 7107 23:28:33.282246  CA_PREDIV_EN               = 0

 7108 23:28:33.285369  PH8_DLY                    = 12

 7109 23:28:33.288501  SEMI_OPEN_CA_PICK_MCK_RATIO= 0

 7110 23:28:33.291526  DQ_AAMCK_DIV               = 4

 7111 23:28:33.294757  CA_AAMCK_DIV               = 4

 7112 23:28:33.294838  CA_ADMCK_DIV               = 4

 7113 23:28:33.298088  DQ_TRACK_CA_EN             = 0

 7114 23:28:33.301424  CA_PICK                    = 1600

 7115 23:28:33.304913  CA_MCKIO                   = 1600

 7116 23:28:33.308197  MCKIO_SEMI                 = 0

 7117 23:28:33.311253  PLL_FREQ                   = 3068

 7118 23:28:33.314727  DQ_UI_PI_RATIO             = 32

 7119 23:28:33.317982  CA_UI_PI_RATIO             = 0

 7120 23:28:33.320990  =================================== 

 7121 23:28:33.324617  =================================== 

 7122 23:28:33.324705  memory_type:LPDDR4         

 7123 23:28:33.328133  GP_NUM     : 10       

 7124 23:28:33.330837  SRAM_EN    : 1       

 7125 23:28:33.330912  MD32_EN    : 0       

 7126 23:28:33.334264  =================================== 

 7127 23:28:33.337737  [ANA_INIT] >>>>>>>>>>>>>> 

 7128 23:28:33.341220  <<<<<< [CONFIGURE PHASE]: ANA_TX

 7129 23:28:33.344569  >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL

 7130 23:28:33.347900  =================================== 

 7131 23:28:33.350787  data_rate = 3200,PCW = 0X7600

 7132 23:28:33.354836  =================================== 

 7133 23:28:33.357542  <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL

 7134 23:28:33.361054  >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7135 23:28:33.367701  <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration

 7136 23:28:33.370875  >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2

 7137 23:28:33.374556  >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL

 7138 23:28:33.377847  <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL

 7139 23:28:33.380884  [ANA_INIT] flow start 

 7140 23:28:33.384112  [ANA_INIT] PLL >>>>>>>> 

 7141 23:28:33.384210  [ANA_INIT] PLL <<<<<<<< 

 7142 23:28:33.387770  [ANA_INIT] MIDPI >>>>>>>> 

 7143 23:28:33.390547  [ANA_INIT] MIDPI <<<<<<<< 

 7144 23:28:33.390626  [ANA_INIT] DLL >>>>>>>> 

 7145 23:28:33.394227  [ANA_INIT] DLL <<<<<<<< 

 7146 23:28:33.397281  [ANA_INIT] flow end 

 7147 23:28:33.400496  ============ LP4 DIFF to SE enter ============

 7148 23:28:33.404235  ============ LP4 DIFF to SE exit  ============

 7149 23:28:33.407348  [ANA_INIT] <<<<<<<<<<<<< 

 7150 23:28:33.410851  [Flow] Enable top DCM control >>>>> 

 7151 23:28:33.414053  [Flow] Enable top DCM control <<<<< 

 7152 23:28:33.417147  Enable DLL master slave shuffle 

 7153 23:28:33.420406  ============================================================== 

 7154 23:28:33.424201  Gating Mode config

 7155 23:28:33.430529  ============================================================== 

 7156 23:28:33.430619  Config description: 

 7157 23:28:33.440415  RX_GATING_MODE        0: Pulse Mode      1: Burst Mode(8UI)        2: Burst Mode(7UI)  3: Original Burst Mode

 7158 23:28:33.447147  RX_GATING_TRACK_MODE  0: Valid DLY Mode  1: Valid Mode (-like) 2: FIFO mode

 7159 23:28:33.450507  SELPH_MODE            0: By rank         1: By Phase 

 7160 23:28:33.457258  ============================================================== 

 7161 23:28:33.460828  GAT_TRACK_EN                 =  1

 7162 23:28:33.463911  RX_GATING_MODE               =  2

 7163 23:28:33.467563  RX_GATING_TRACK_MODE         =  2

 7164 23:28:33.470730  SELPH_MODE                   =  1

 7165 23:28:33.474136  PICG_EARLY_EN                =  1

 7166 23:28:33.477246  VALID_LAT_VALUE              =  1

 7167 23:28:33.480468  ============================================================== 

 7168 23:28:33.483947  Enter into Gating configuration >>>> 

 7169 23:28:33.487351  Exit from Gating configuration <<<< 

 7170 23:28:33.490350  Enter into  DVFS_PRE_config >>>>> 

 7171 23:28:33.504015  Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL. 

 7172 23:28:33.504099  Exit from  DVFS_PRE_config <<<<< 

 7173 23:28:33.507278  Enter into PICG configuration >>>> 

 7174 23:28:33.510791  Exit from PICG configuration <<<< 

 7175 23:28:33.513952  [RX_INPUT] configuration >>>>> 

 7176 23:28:33.517179  [RX_INPUT] configuration <<<<< 

 7177 23:28:33.523983  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>

 7178 23:28:33.526856  [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<

 7179 23:28:33.533761  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>

 7180 23:28:33.540279  [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<

 7181 23:28:33.547237  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>

 7182 23:28:33.553564  [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<

 7183 23:28:33.556655  [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0 

 7184 23:28:33.560072  [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0 

 7185 23:28:33.563384  [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0 

 7186 23:28:33.569865  [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0 

 7187 23:28:33.573233  [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0 

 7188 23:28:33.576590  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7189 23:28:33.579824  =================================== 

 7190 23:28:33.583311  LPDDR4 DRAM CONFIGURATION

 7191 23:28:33.587042  =================================== 

 7192 23:28:33.589938  EX_ROW_EN[0]    = 0x0

 7193 23:28:33.590008  EX_ROW_EN[1]    = 0x0

 7194 23:28:33.593171  LP4Y_EN      = 0x0

 7195 23:28:33.593241  WORK_FSP     = 0x1

 7196 23:28:33.596649  WL           = 0x5

 7197 23:28:33.596718  RL           = 0x5

 7198 23:28:33.600042  BL           = 0x2

 7199 23:28:33.600111  RPST         = 0x0

 7200 23:28:33.603270  RD_PRE       = 0x0

 7201 23:28:33.603351  WR_PRE       = 0x1

 7202 23:28:33.606215  WR_PST       = 0x1

 7203 23:28:33.606285  DBI_WR       = 0x0

 7204 23:28:33.609923  DBI_RD       = 0x0

 7205 23:28:33.610009  OTF          = 0x1

 7206 23:28:33.612861  =================================== 

 7207 23:28:33.619577  [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0 

 7208 23:28:33.623432  [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0 

 7209 23:28:33.626559  [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5

 7210 23:28:33.629493  =================================== 

 7211 23:28:33.632818  LPDDR4 DRAM CONFIGURATION

 7212 23:28:33.636208  =================================== 

 7213 23:28:33.639749  EX_ROW_EN[0]    = 0x10

 7214 23:28:33.639830  EX_ROW_EN[1]    = 0x0

 7215 23:28:33.642971  LP4Y_EN      = 0x0

 7216 23:28:33.643051  WORK_FSP     = 0x1

 7217 23:28:33.646513  WL           = 0x5

 7218 23:28:33.646595  RL           = 0x5

 7219 23:28:33.649519  BL           = 0x2

 7220 23:28:33.649657  RPST         = 0x0

 7221 23:28:33.653061  RD_PRE       = 0x0

 7222 23:28:33.653142  WR_PRE       = 0x1

 7223 23:28:33.656577  WR_PST       = 0x1

 7224 23:28:33.656658  DBI_WR       = 0x0

 7225 23:28:33.659898  DBI_RD       = 0x0

 7226 23:28:33.659982  OTF          = 0x1

 7227 23:28:33.662873  =================================== 

 7228 23:28:33.669908  [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit

 7229 23:28:33.669990  ==

 7230 23:28:33.673162  Dram Type= 6, Freq= 0, CH_0, rank 0

 7231 23:28:33.676179  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7232 23:28:33.679417  ==

 7233 23:28:33.679499  [Duty_Offset_Calibration]

 7234 23:28:33.682745  	B0:2	B1:1	CA:1

 7235 23:28:33.682827  

 7236 23:28:33.685720  [DutyScan_Calibration_Flow] k_type=0

 7237 23:28:33.695192  

 7238 23:28:33.695276  ==CLK 0==

 7239 23:28:33.698612  Final CLK duty delay cell = 0

 7240 23:28:33.701457  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7241 23:28:33.705137  [0] MIN Duty = 4876%(X100), DQS PI = 48

 7242 23:28:33.708385  [0] AVG Duty = 5016%(X100)

 7243 23:28:33.708467  

 7244 23:28:33.711738  CH0 CLK Duty spec in!! Max-Min= 280%

 7245 23:28:33.714879  [DutyScan_Calibration_Flow] ====Done====

 7246 23:28:33.714961  

 7247 23:28:33.718010  [DutyScan_Calibration_Flow] k_type=1

 7248 23:28:33.734235  

 7249 23:28:33.734319  ==DQS 0 ==

 7250 23:28:33.737491  Final DQS duty delay cell = -4

 7251 23:28:33.740769  [-4] MAX Duty = 5125%(X100), DQS PI = 26

 7252 23:28:33.744031  [-4] MIN Duty = 4688%(X100), DQS PI = 0

 7253 23:28:33.747298  [-4] AVG Duty = 4906%(X100)

 7254 23:28:33.747379  

 7255 23:28:33.747444  ==DQS 1 ==

 7256 23:28:33.750592  Final DQS duty delay cell = 0

 7257 23:28:33.753910  [0] MAX Duty = 5187%(X100), DQS PI = 20

 7258 23:28:33.757348  [0] MIN Duty = 5031%(X100), DQS PI = 52

 7259 23:28:33.760778  [0] AVG Duty = 5109%(X100)

 7260 23:28:33.760860  

 7261 23:28:33.764537  CH0 DQS 0 Duty spec in!! Max-Min= 437%

 7262 23:28:33.764619  

 7263 23:28:33.767335  CH0 DQS 1 Duty spec in!! Max-Min= 156%

 7264 23:28:33.770694  [DutyScan_Calibration_Flow] ====Done====

 7265 23:28:33.770775  

 7266 23:28:33.773812  [DutyScan_Calibration_Flow] k_type=3

 7267 23:28:33.790802  

 7268 23:28:33.790888  ==DQM 0 ==

 7269 23:28:33.794083  Final DQM duty delay cell = 0

 7270 23:28:33.797226  [0] MAX Duty = 5218%(X100), DQS PI = 34

 7271 23:28:33.800721  [0] MIN Duty = 4907%(X100), DQS PI = 56

 7272 23:28:33.804089  [0] AVG Duty = 5062%(X100)

 7273 23:28:33.804170  

 7274 23:28:33.804235  ==DQM 1 ==

 7275 23:28:33.807350  Final DQM duty delay cell = -4

 7276 23:28:33.810921  [-4] MAX Duty = 4969%(X100), DQS PI = 22

 7277 23:28:33.814162  [-4] MIN Duty = 4813%(X100), DQS PI = 14

 7278 23:28:33.817829  [-4] AVG Duty = 4891%(X100)

 7279 23:28:33.817911  

 7280 23:28:33.820402  CH0 DQM 0 Duty spec in!! Max-Min= 311%

 7281 23:28:33.820473  

 7282 23:28:33.824009  CH0 DQM 1 Duty spec in!! Max-Min= 156%

 7283 23:28:33.827111  [DutyScan_Calibration_Flow] ====Done====

 7284 23:28:33.827192  

 7285 23:28:33.830288  [DutyScan_Calibration_Flow] k_type=2

 7286 23:28:33.848420  

 7287 23:28:33.848503  ==DQ 0 ==

 7288 23:28:33.851655  Final DQ duty delay cell = 0

 7289 23:28:33.855033  [0] MAX Duty = 5062%(X100), DQS PI = 26

 7290 23:28:33.858321  [0] MIN Duty = 4907%(X100), DQS PI = 0

 7291 23:28:33.858403  [0] AVG Duty = 4984%(X100)

 7292 23:28:33.858468  

 7293 23:28:33.861487  ==DQ 1 ==

 7294 23:28:33.865101  Final DQ duty delay cell = 0

 7295 23:28:33.868176  [0] MAX Duty = 5156%(X100), DQS PI = 22

 7296 23:28:33.871635  [0] MIN Duty = 4938%(X100), DQS PI = 34

 7297 23:28:33.871717  [0] AVG Duty = 5047%(X100)

 7298 23:28:33.871781  

 7299 23:28:33.874827  CH0 DQ 0 Duty spec in!! Max-Min= 155%

 7300 23:28:33.878202  

 7301 23:28:33.881595  CH0 DQ 1 Duty spec in!! Max-Min= 218%

 7302 23:28:33.884999  [DutyScan_Calibration_Flow] ====Done====

 7303 23:28:33.885080  ==

 7304 23:28:33.888026  Dram Type= 6, Freq= 0, CH_1, rank 0

 7305 23:28:33.891464  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7306 23:28:33.891545  ==

 7307 23:28:33.895013  [Duty_Offset_Calibration]

 7308 23:28:33.895094  	B0:1	B1:0	CA:0

 7309 23:28:33.895159  

 7310 23:28:33.898292  [DutyScan_Calibration_Flow] k_type=0

 7311 23:28:33.907822  

 7312 23:28:33.907902  ==CLK 0==

 7313 23:28:33.911340  Final CLK duty delay cell = -4

 7314 23:28:33.914622  [-4] MAX Duty = 5000%(X100), DQS PI = 24

 7315 23:28:33.917654  [-4] MIN Duty = 4844%(X100), DQS PI = 50

 7316 23:28:33.921037  [-4] AVG Duty = 4922%(X100)

 7317 23:28:33.921117  

 7318 23:28:33.924416  CH1 CLK Duty spec in!! Max-Min= 156%

 7319 23:28:33.927604  [DutyScan_Calibration_Flow] ====Done====

 7320 23:28:33.927684  

 7321 23:28:33.930835  [DutyScan_Calibration_Flow] k_type=1

 7322 23:28:33.948081  

 7323 23:28:33.948166  ==DQS 0 ==

 7324 23:28:33.951290  Final DQS duty delay cell = 0

 7325 23:28:33.954190  [0] MAX Duty = 5094%(X100), DQS PI = 22

 7326 23:28:33.957888  [0] MIN Duty = 4875%(X100), DQS PI = 0

 7327 23:28:33.960971  [0] AVG Duty = 4984%(X100)

 7328 23:28:33.961052  

 7329 23:28:33.961116  ==DQS 1 ==

 7330 23:28:33.964594  Final DQS duty delay cell = 0

 7331 23:28:33.967549  [0] MAX Duty = 5249%(X100), DQS PI = 18

 7332 23:28:33.970837  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7333 23:28:33.974165  [0] AVG Duty = 5093%(X100)

 7334 23:28:33.974245  

 7335 23:28:33.977524  CH1 DQS 0 Duty spec in!! Max-Min= 219%

 7336 23:28:33.977613  

 7337 23:28:33.981301  CH1 DQS 1 Duty spec in!! Max-Min= 311%

 7338 23:28:33.984168  [DutyScan_Calibration_Flow] ====Done====

 7339 23:28:33.984249  

 7340 23:28:33.987406  [DutyScan_Calibration_Flow] k_type=3

 7341 23:28:34.004730  

 7342 23:28:34.004813  ==DQM 0 ==

 7343 23:28:34.008112  Final DQM duty delay cell = 0

 7344 23:28:34.011382  [0] MAX Duty = 5218%(X100), DQS PI = 18

 7345 23:28:34.014914  [0] MIN Duty = 4969%(X100), DQS PI = 48

 7346 23:28:34.017704  [0] AVG Duty = 5093%(X100)

 7347 23:28:34.017786  

 7348 23:28:34.017850  ==DQM 1 ==

 7349 23:28:34.021156  Final DQM duty delay cell = 0

 7350 23:28:34.024525  [0] MAX Duty = 5093%(X100), DQS PI = 16

 7351 23:28:34.027918  [0] MIN Duty = 4907%(X100), DQS PI = 34

 7352 23:28:34.031176  [0] AVG Duty = 5000%(X100)

 7353 23:28:34.031257  

 7354 23:28:34.034355  CH1 DQM 0 Duty spec in!! Max-Min= 249%

 7355 23:28:34.034436  

 7356 23:28:34.037567  CH1 DQM 1 Duty spec in!! Max-Min= 186%

 7357 23:28:34.041269  [DutyScan_Calibration_Flow] ====Done====

 7358 23:28:34.041349  

 7359 23:28:34.044577  [DutyScan_Calibration_Flow] k_type=2

 7360 23:28:34.061213  

 7361 23:28:34.061297  ==DQ 0 ==

 7362 23:28:34.064251  Final DQ duty delay cell = -4

 7363 23:28:34.067474  [-4] MAX Duty = 5031%(X100), DQS PI = 8

 7364 23:28:34.070738  [-4] MIN Duty = 4875%(X100), DQS PI = 46

 7365 23:28:34.073967  [-4] AVG Duty = 4953%(X100)

 7366 23:28:34.074048  

 7367 23:28:34.074112  ==DQ 1 ==

 7368 23:28:34.077454  Final DQ duty delay cell = 0

 7369 23:28:34.080844  [0] MAX Duty = 5093%(X100), DQS PI = 16

 7370 23:28:34.084065  [0] MIN Duty = 4938%(X100), DQS PI = 8

 7371 23:28:34.084146  [0] AVG Duty = 5015%(X100)

 7372 23:28:34.087240  

 7373 23:28:34.090695  CH1 DQ 0 Duty spec in!! Max-Min= 156%

 7374 23:28:34.090777  

 7375 23:28:34.094096  CH1 DQ 1 Duty spec in!! Max-Min= 155%

 7376 23:28:34.097544  [DutyScan_Calibration_Flow] ====Done====

 7377 23:28:34.100490  nWR fixed to 30

 7378 23:28:34.100571  [ModeRegInit_LP4] CH0 RK0

 7379 23:28:34.103924  [ModeRegInit_LP4] CH0 RK1

 7380 23:28:34.107544  [ModeRegInit_LP4] CH1 RK0

 7381 23:28:34.110646  [ModeRegInit_LP4] CH1 RK1

 7382 23:28:34.110728  match AC timing 5

 7383 23:28:34.114511  dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1

 7384 23:28:34.120690  SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON

 7385 23:28:34.124217  [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14

 7386 23:28:34.127481  [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29

 7387 23:28:34.134232  [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)

 7388 23:28:34.134313  [MiockJmeterHQA]

 7389 23:28:34.134377  

 7390 23:28:34.137452  [DramcMiockJmeter] u1RxGatingPI = 0

 7391 23:28:34.140731  0 : 4252, 4027

 7392 23:28:34.140814  4 : 4253, 4026

 7393 23:28:34.140879  8 : 4252, 4027

 7394 23:28:34.144182  12 : 4363, 4137

 7395 23:28:34.144265  16 : 4253, 4026

 7396 23:28:34.147279  20 : 4252, 4027

 7397 23:28:34.147360  24 : 4252, 4026

 7398 23:28:34.151058  28 : 4252, 4027

 7399 23:28:34.151140  32 : 4255, 4030

 7400 23:28:34.154230  36 : 4363, 4137

 7401 23:28:34.154313  40 : 4363, 4138

 7402 23:28:34.154379  44 : 4365, 4140

 7403 23:28:34.157481  48 : 4255, 4029

 7404 23:28:34.157612  52 : 4252, 4027

 7405 23:28:34.160820  56 : 4253, 4026

 7406 23:28:34.160902  60 : 4255, 4029

 7407 23:28:34.163766  64 : 4361, 4138

 7408 23:28:34.163876  68 : 4250, 4026

 7409 23:28:34.167297  72 : 4249, 4027

 7410 23:28:34.167380  76 : 4250, 4026

 7411 23:28:34.167445  80 : 4250, 4027

 7412 23:28:34.171032  84 : 4252, 4030

 7413 23:28:34.171114  88 : 4363, 51

 7414 23:28:34.174126  92 : 4249, 0

 7415 23:28:34.174208  96 : 4360, 0

 7416 23:28:34.174274  100 : 4250, 0

 7417 23:28:34.177712  104 : 4250, 0

 7418 23:28:34.177795  108 : 4360, 0

 7419 23:28:34.177861  112 : 4363, 0

 7420 23:28:34.180555  116 : 4250, 0

 7421 23:28:34.180638  120 : 4250, 0

 7422 23:28:34.183842  124 : 4249, 0

 7423 23:28:34.183925  128 : 4250, 0

 7424 23:28:34.183989  132 : 4250, 0

 7425 23:28:34.187006  136 : 4250, 0

 7426 23:28:34.187089  140 : 4255, 0

 7427 23:28:34.190365  144 : 4250, 0

 7428 23:28:34.190447  148 : 4249, 0

 7429 23:28:34.190513  152 : 4252, 0

 7430 23:28:34.194118  156 : 4361, 0

 7431 23:28:34.194201  160 : 4360, 0

 7432 23:28:34.197342  164 : 4363, 0

 7433 23:28:34.197425  168 : 4252, 0

 7434 23:28:34.197491  172 : 4361, 0

 7435 23:28:34.200235  176 : 4249, 0

 7436 23:28:34.200317  180 : 4250, 0

 7437 23:28:34.203960  184 : 4250, 0

 7438 23:28:34.204043  188 : 4249, 0

 7439 23:28:34.204108  192 : 4250, 0

 7440 23:28:34.207439  196 : 4250, 0

 7441 23:28:34.207521  200 : 4249, 0

 7442 23:28:34.210436  204 : 4252, 1123

 7443 23:28:34.210520  208 : 4250, 3973

 7444 23:28:34.210598  212 : 4252, 4029

 7445 23:28:34.213890  216 : 4249, 4027

 7446 23:28:34.213966  220 : 4250, 4027

 7447 23:28:34.217002  224 : 4250, 4027

 7448 23:28:34.217073  228 : 4360, 4137

 7449 23:28:34.220248  232 : 4360, 4137

 7450 23:28:34.220320  236 : 4250, 4027

 7451 23:28:34.223357  240 : 4360, 4138

 7452 23:28:34.223438  244 : 4249, 4027

 7453 23:28:34.226979  248 : 4249, 4027

 7454 23:28:34.227054  252 : 4250, 4027

 7455 23:28:34.230511  256 : 4363, 4140

 7456 23:28:34.230584  260 : 4250, 4027

 7457 23:28:34.234042  264 : 4250, 4027

 7458 23:28:34.234130  268 : 4361, 4137

 7459 23:28:34.236844  272 : 4250, 4027

 7460 23:28:34.236912  276 : 4249, 4027

 7461 23:28:34.236981  280 : 4361, 4137

 7462 23:28:34.240428  284 : 4360, 4137

 7463 23:28:34.240500  288 : 4250, 4027

 7464 23:28:34.243602  292 : 4250, 4027

 7465 23:28:34.243681  296 : 4250, 4027

 7466 23:28:34.246810  300 : 4250, 4027

 7467 23:28:34.246881  304 : 4250, 4027

 7468 23:28:34.250213  308 : 4363, 4029

 7469 23:28:34.250283  312 : 4249, 1967

 7470 23:28:34.250357  

 7471 23:28:34.253551  	MIOCK jitter meter	ch=0

 7472 23:28:34.253676  

 7473 23:28:34.256767  1T = (312-88) = 224 dly cells

 7474 23:28:34.260169  Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps

 7475 23:28:34.263392  ==

 7476 23:28:34.266660  Dram Type= 6, Freq= 0, CH_0, rank 0

 7477 23:28:34.270398  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7478 23:28:34.270480  ==

 7479 23:28:34.273158  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7480 23:28:34.279724  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7481 23:28:34.283221  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7482 23:28:34.289875  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7483 23:28:34.298233  [CA 0] Center 42 (12~73) winsize 62

 7484 23:28:34.301414  [CA 1] Center 42 (12~73) winsize 62

 7485 23:28:34.305312  [CA 2] Center 38 (8~68) winsize 61

 7486 23:28:34.308236  [CA 3] Center 37 (8~67) winsize 60

 7487 23:28:34.311905  [CA 4] Center 36 (6~66) winsize 61

 7488 23:28:34.315074  [CA 5] Center 35 (6~64) winsize 59

 7489 23:28:34.315149  

 7490 23:28:34.318136  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7491 23:28:34.318238  

 7492 23:28:34.321192  [CATrainingPosCal] consider 1 rank data

 7493 23:28:34.324915  u2DelayCellTimex100 = 290/100 ps

 7494 23:28:34.331191  CA0 delay=42 (12~73),Diff = 7 PI (23 cell)

 7495 23:28:34.334374  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7496 23:28:34.337840  CA2 delay=38 (8~68),Diff = 3 PI (10 cell)

 7497 23:28:34.341123  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7498 23:28:34.344785  CA4 delay=36 (6~66),Diff = 1 PI (3 cell)

 7499 23:28:34.347873  CA5 delay=35 (6~64),Diff = 0 PI (0 cell)

 7500 23:28:34.347951  

 7501 23:28:34.351223  CA PerBit enable=1, Macro0, CA PI delay=35

 7502 23:28:34.351293  

 7503 23:28:34.354115  [CBTSetCACLKResult] CA Dly = 35

 7504 23:28:34.357498  CS Dly: 9 (0~40)

 7505 23:28:34.360918  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7506 23:28:34.364218  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7507 23:28:34.364321  ==

 7508 23:28:34.367549  Dram Type= 6, Freq= 0, CH_0, rank 1

 7509 23:28:34.374154  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7510 23:28:34.374237  ==

 7511 23:28:34.377291  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 7512 23:28:34.384234  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1

 7513 23:28:34.387553  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1

 7514 23:28:34.394131  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 7515 23:28:34.401331  [CA 0] Center 42 (12~73) winsize 62

 7516 23:28:34.404675  [CA 1] Center 42 (12~73) winsize 62

 7517 23:28:34.407976  [CA 2] Center 37 (8~67) winsize 60

 7518 23:28:34.411649  [CA 3] Center 38 (8~68) winsize 61

 7519 23:28:34.414623  [CA 4] Center 35 (6~65) winsize 60

 7520 23:28:34.418152  [CA 5] Center 35 (5~65) winsize 61

 7521 23:28:34.418234  

 7522 23:28:34.421467  [CmdBusTrainingLP45] Vref(ca) range 0: 30

 7523 23:28:34.421549  

 7524 23:28:34.424748  [CATrainingPosCal] consider 2 rank data

 7525 23:28:34.427842  u2DelayCellTimex100 = 290/100 ps

 7526 23:28:34.431148  CA0 delay=42 (12~73),Diff = 7 PI (23 cell)

 7527 23:28:34.437800  CA1 delay=42 (12~73),Diff = 7 PI (23 cell)

 7528 23:28:34.441284  CA2 delay=37 (8~67),Diff = 2 PI (6 cell)

 7529 23:28:34.444610  CA3 delay=37 (8~67),Diff = 2 PI (6 cell)

 7530 23:28:34.448006  CA4 delay=35 (6~65),Diff = 0 PI (0 cell)

 7531 23:28:34.451363  CA5 delay=35 (6~64),Diff = 0 PI (0 cell)

 7532 23:28:34.451446  

 7533 23:28:34.454673  CA PerBit enable=1, Macro0, CA PI delay=35

 7534 23:28:34.454773  

 7535 23:28:34.457902  [CBTSetCACLKResult] CA Dly = 35

 7536 23:28:34.461254  CS Dly: 10 (0~42)

 7537 23:28:34.464622  [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0

 7538 23:28:34.468030  [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0

 7539 23:28:34.468112  

 7540 23:28:34.471169  ----->DramcWriteLeveling(PI) begin...

 7541 23:28:34.471252  ==

 7542 23:28:34.474495  Dram Type= 6, Freq= 0, CH_0, rank 0

 7543 23:28:34.481298  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7544 23:28:34.481381  ==

 7545 23:28:34.484195  Write leveling (Byte 0): 35 => 35

 7546 23:28:34.484278  Write leveling (Byte 1): 29 => 29

 7547 23:28:34.487787  DramcWriteLeveling(PI) end<-----

 7548 23:28:34.487868  

 7549 23:28:34.487933  ==

 7550 23:28:34.490962  Dram Type= 6, Freq= 0, CH_0, rank 0

 7551 23:28:34.497556  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7552 23:28:34.497678  ==

 7553 23:28:34.501020  [Gating] SW mode calibration

 7554 23:28:34.507380  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7555 23:28:34.511420  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7556 23:28:34.517596   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7557 23:28:34.520758   1  4  4 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)

 7558 23:28:34.524397   1  4  8 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)

 7559 23:28:34.531351   1  4 12 | B1->B0 | 2323 3635 | 0 1 | (0 0) (0 0)

 7560 23:28:34.534182   1  4 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)

 7561 23:28:34.537429   1  4 20 | B1->B0 | 3434 3636 | 0 1 | (0 0) (0 0)

 7562 23:28:34.544196   1  4 24 | B1->B0 | 3434 3737 | 1 0 | (1 1) (1 1)

 7563 23:28:34.547411   1  4 28 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)

 7564 23:28:34.550764   1  5  0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)

 7565 23:28:34.554440   1  5  4 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)

 7566 23:28:34.560539   1  5  8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)

 7567 23:28:34.564291   1  5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)

 7568 23:28:34.567586   1  5 16 | B1->B0 | 3434 2525 | 1 0 | (1 0) (0 0)

 7569 23:28:34.574235   1  5 20 | B1->B0 | 2525 2727 | 0 0 | (1 0) (0 0)

 7570 23:28:34.577788   1  5 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)

 7571 23:28:34.580635   1  5 28 | B1->B0 | 2323 2928 | 0 1 | (0 0) (0 0)

 7572 23:28:34.587372   1  6  0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)

 7573 23:28:34.590690   1  6  4 | B1->B0 | 2323 2726 | 0 1 | (0 0) (1 1)

 7574 23:28:34.593831   1  6  8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)

 7575 23:28:34.600905   1  6 12 | B1->B0 | 2323 4645 | 0 1 | (0 0) (0 0)

 7576 23:28:34.604030   1  6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)

 7577 23:28:34.607604   1  6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7578 23:28:34.613954   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7579 23:28:34.617454   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7580 23:28:34.620640   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7581 23:28:34.627472   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7582 23:28:34.630699   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7583 23:28:34.634032   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7584 23:28:34.640710   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7585 23:28:34.643757   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7586 23:28:34.647363   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 7587 23:28:34.653717   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7588 23:28:34.657130   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7589 23:28:34.660098   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7590 23:28:34.667041   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7591 23:28:34.670853   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7592 23:28:34.673903   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7593 23:28:34.680694   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7594 23:28:34.683801   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7595 23:28:34.686873   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7596 23:28:34.693801   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7597 23:28:34.697104   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 7598 23:28:34.700653   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7599 23:28:34.703849   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)

 7600 23:28:34.710392   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7601 23:28:34.714060  Total UI for P1: 0, mck2ui 16

 7602 23:28:34.717174  best dqsien dly found for B0: ( 1,  9, 10)

 7603 23:28:34.720687   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)

 7604 23:28:34.723425   1  9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7605 23:28:34.727622  Total UI for P1: 0, mck2ui 16

 7606 23:28:34.730326  best dqsien dly found for B1: ( 1,  9, 18)

 7607 23:28:34.733324  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 7608 23:28:34.736725  best DQS1 dly(MCK, UI, PI) = (1, 9, 18)

 7609 23:28:34.740161  

 7610 23:28:34.743596  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 7611 23:28:34.746485  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)

 7612 23:28:34.749703  [Gating] SW calibration Done

 7613 23:28:34.749782  ==

 7614 23:28:34.752977  Dram Type= 6, Freq= 0, CH_0, rank 0

 7615 23:28:34.756707  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7616 23:28:34.756783  ==

 7617 23:28:34.759914  RX Vref Scan: 0

 7618 23:28:34.759986  

 7619 23:28:34.760094  RX Vref 0 -> 0, step: 1

 7620 23:28:34.760153  

 7621 23:28:34.763075  RX Delay 0 -> 252, step: 8

 7622 23:28:34.766429  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 7623 23:28:34.769799  iDelay=200, Bit 1, Center 143 (88 ~ 199) 112

 7624 23:28:34.776590  iDelay=200, Bit 2, Center 131 (80 ~ 183) 104

 7625 23:28:34.779752  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 7626 23:28:34.782880  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 7627 23:28:34.786381  iDelay=200, Bit 5, Center 123 (72 ~ 175) 104

 7628 23:28:34.789519  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 7629 23:28:34.796319  iDelay=200, Bit 7, Center 143 (96 ~ 191) 96

 7630 23:28:34.799622  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 7631 23:28:34.803084  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 7632 23:28:34.806415  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 7633 23:28:34.809844  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 7634 23:28:34.815961  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 7635 23:28:34.819606  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 7636 23:28:34.822894  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 7637 23:28:34.826416  iDelay=200, Bit 15, Center 135 (80 ~ 191) 112

 7638 23:28:34.826489  ==

 7639 23:28:34.829193  Dram Type= 6, Freq= 0, CH_0, rank 0

 7640 23:28:34.835904  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7641 23:28:34.835989  ==

 7642 23:28:34.836054  DQS Delay:

 7643 23:28:34.839317  DQS0 = 0, DQS1 = 0

 7644 23:28:34.839391  DQM Delay:

 7645 23:28:34.842707  DQM0 = 137, DQM1 = 130

 7646 23:28:34.842778  DQ Delay:

 7647 23:28:34.845950  DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =135

 7648 23:28:34.849402  DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143

 7649 23:28:34.852961  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123

 7650 23:28:34.855597  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135

 7651 23:28:34.855671  

 7652 23:28:34.855732  

 7653 23:28:34.855804  ==

 7654 23:28:34.859175  Dram Type= 6, Freq= 0, CH_0, rank 0

 7655 23:28:34.865980  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7656 23:28:34.866056  ==

 7657 23:28:34.866129  

 7658 23:28:34.866191  

 7659 23:28:34.866248  	TX Vref Scan disable

 7660 23:28:34.869474   == TX Byte 0 ==

 7661 23:28:34.872420  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 7662 23:28:34.878972  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7663 23:28:34.879057   == TX Byte 1 ==

 7664 23:28:34.882099  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 7665 23:28:34.889161  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7666 23:28:34.889269  ==

 7667 23:28:34.892089  Dram Type= 6, Freq= 0, CH_0, rank 0

 7668 23:28:34.895469  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7669 23:28:34.895552  ==

 7670 23:28:34.908800  

 7671 23:28:34.911756  TX Vref early break, caculate TX vref

 7672 23:28:34.914853  TX Vref=16, minBit 7, minWin=22, winSum=375

 7673 23:28:34.918077  TX Vref=18, minBit 4, minWin=23, winSum=387

 7674 23:28:34.921551  TX Vref=20, minBit 0, minWin=24, winSum=398

 7675 23:28:34.924950  TX Vref=22, minBit 0, minWin=24, winSum=407

 7676 23:28:34.928922  TX Vref=24, minBit 0, minWin=25, winSum=415

 7677 23:28:34.935089  TX Vref=26, minBit 6, minWin=25, winSum=428

 7678 23:28:34.938554  TX Vref=28, minBit 6, minWin=24, winSum=425

 7679 23:28:34.941541  TX Vref=30, minBit 1, minWin=24, winSum=412

 7680 23:28:34.944918  TX Vref=32, minBit 6, minWin=23, winSum=406

 7681 23:28:34.948027  TX Vref=34, minBit 1, minWin=23, winSum=397

 7682 23:28:34.954528  [TxChooseVref] Worse bit 6, Min win 25, Win sum 428, Final Vref 26

 7683 23:28:34.954605  

 7684 23:28:34.957853  Final TX Range 0 Vref 26

 7685 23:28:34.957925  

 7686 23:28:34.958000  ==

 7687 23:28:34.961978  Dram Type= 6, Freq= 0, CH_0, rank 0

 7688 23:28:34.964669  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7689 23:28:34.964757  ==

 7690 23:28:34.964818  

 7691 23:28:34.964876  

 7692 23:28:34.967881  	TX Vref Scan disable

 7693 23:28:34.974556  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 7694 23:28:34.974629   == TX Byte 0 ==

 7695 23:28:34.978101  u2DelayCellOfst[0]=10 cells (3 PI)

 7696 23:28:34.981668  u2DelayCellOfst[1]=13 cells (4 PI)

 7697 23:28:34.984595  u2DelayCellOfst[2]=10 cells (3 PI)

 7698 23:28:34.987674  u2DelayCellOfst[3]=10 cells (3 PI)

 7699 23:28:34.991254  u2DelayCellOfst[4]=6 cells (2 PI)

 7700 23:28:34.994195  u2DelayCellOfst[5]=0 cells (0 PI)

 7701 23:28:34.997958  u2DelayCellOfst[6]=16 cells (5 PI)

 7702 23:28:35.001141  u2DelayCellOfst[7]=16 cells (5 PI)

 7703 23:28:35.004439  Update DQ  dly =989 (3 ,6, 29)  DQ  OEN =(3 ,3)

 7704 23:28:35.007629  Update DQM dly =991 (3 ,6, 31)  DQM OEN =(3 ,3)

 7705 23:28:35.011075   == TX Byte 1 ==

 7706 23:28:35.014545  u2DelayCellOfst[8]=0 cells (0 PI)

 7707 23:28:35.014627  u2DelayCellOfst[9]=0 cells (0 PI)

 7708 23:28:35.017470  u2DelayCellOfst[10]=10 cells (3 PI)

 7709 23:28:35.020764  u2DelayCellOfst[11]=6 cells (2 PI)

 7710 23:28:35.024488  u2DelayCellOfst[12]=10 cells (3 PI)

 7711 23:28:35.027627  u2DelayCellOfst[13]=13 cells (4 PI)

 7712 23:28:35.030813  u2DelayCellOfst[14]=13 cells (4 PI)

 7713 23:28:35.034465  u2DelayCellOfst[15]=10 cells (3 PI)

 7714 23:28:35.037372  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 7715 23:28:35.044236  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 7716 23:28:35.044312  DramC Write-DBI on

 7717 23:28:35.044375  ==

 7718 23:28:35.047595  Dram Type= 6, Freq= 0, CH_0, rank 0

 7719 23:28:35.054225  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7720 23:28:35.054303  ==

 7721 23:28:35.054367  

 7722 23:28:35.054435  

 7723 23:28:35.054494  	TX Vref Scan disable

 7724 23:28:35.057942   == TX Byte 0 ==

 7725 23:28:35.061030  Update DQM dly =735 (2 ,6, 31)  DQM OEN =(3 ,3)

 7726 23:28:35.064525   == TX Byte 1 ==

 7727 23:28:35.067684  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 7728 23:28:35.071354  DramC Write-DBI off

 7729 23:28:35.071434  

 7730 23:28:35.071497  [DATLAT]

 7731 23:28:35.071555  Freq=1600, CH0 RK0

 7732 23:28:35.071613  

 7733 23:28:35.074529  DATLAT Default: 0xf

 7734 23:28:35.074620  0, 0xFFFF, sum = 0

 7735 23:28:35.077933  1, 0xFFFF, sum = 0

 7736 23:28:35.081489  2, 0xFFFF, sum = 0

 7737 23:28:35.081634  3, 0xFFFF, sum = 0

 7738 23:28:35.084703  4, 0xFFFF, sum = 0

 7739 23:28:35.084791  5, 0xFFFF, sum = 0

 7740 23:28:35.087885  6, 0xFFFF, sum = 0

 7741 23:28:35.087980  7, 0xFFFF, sum = 0

 7742 23:28:35.091338  8, 0xFFFF, sum = 0

 7743 23:28:35.091433  9, 0xFFFF, sum = 0

 7744 23:28:35.094394  10, 0xFFFF, sum = 0

 7745 23:28:35.094510  11, 0xFFFF, sum = 0

 7746 23:28:35.097596  12, 0xFFFF, sum = 0

 7747 23:28:35.097708  13, 0xFFFF, sum = 0

 7748 23:28:35.101252  14, 0x0, sum = 1

 7749 23:28:35.101362  15, 0x0, sum = 2

 7750 23:28:35.104755  16, 0x0, sum = 3

 7751 23:28:35.104876  17, 0x0, sum = 4

 7752 23:28:35.107651  best_step = 15

 7753 23:28:35.107804  

 7754 23:28:35.107943  ==

 7755 23:28:35.111051  Dram Type= 6, Freq= 0, CH_0, rank 0

 7756 23:28:35.114407  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7757 23:28:35.114557  ==

 7758 23:28:35.117704  RX Vref Scan: 1

 7759 23:28:35.117875  

 7760 23:28:35.118010  Set Vref Range= 24 -> 127

 7761 23:28:35.118136  

 7762 23:28:35.121471  RX Vref 24 -> 127, step: 1

 7763 23:28:35.121703  

 7764 23:28:35.124553  RX Delay 19 -> 252, step: 4

 7765 23:28:35.124750  

 7766 23:28:35.127863  Set Vref, RX VrefLevel [Byte0]: 24

 7767 23:28:35.130919                           [Byte1]: 24

 7768 23:28:35.131157  

 7769 23:28:35.134401  Set Vref, RX VrefLevel [Byte0]: 25

 7770 23:28:35.137797                           [Byte1]: 25

 7771 23:28:35.140887  

 7772 23:28:35.141310  Set Vref, RX VrefLevel [Byte0]: 26

 7773 23:28:35.144515                           [Byte1]: 26

 7774 23:28:35.149174  

 7775 23:28:35.149816  Set Vref, RX VrefLevel [Byte0]: 27

 7776 23:28:35.151939                           [Byte1]: 27

 7777 23:28:35.156802  

 7778 23:28:35.157216  Set Vref, RX VrefLevel [Byte0]: 28

 7779 23:28:35.159732                           [Byte1]: 28

 7780 23:28:35.163899  

 7781 23:28:35.164328  Set Vref, RX VrefLevel [Byte0]: 29

 7782 23:28:35.167504                           [Byte1]: 29

 7783 23:28:35.171794  

 7784 23:28:35.172211  Set Vref, RX VrefLevel [Byte0]: 30

 7785 23:28:35.174603                           [Byte1]: 30

 7786 23:28:35.179112  

 7787 23:28:35.179535  Set Vref, RX VrefLevel [Byte0]: 31

 7788 23:28:35.182636                           [Byte1]: 31

 7789 23:28:35.186617  

 7790 23:28:35.187037  Set Vref, RX VrefLevel [Byte0]: 32

 7791 23:28:35.189860                           [Byte1]: 32

 7792 23:28:35.193926  

 7793 23:28:35.194453  Set Vref, RX VrefLevel [Byte0]: 33

 7794 23:28:35.197739                           [Byte1]: 33

 7795 23:28:35.201673  

 7796 23:28:35.204718  Set Vref, RX VrefLevel [Byte0]: 34

 7797 23:28:35.208209                           [Byte1]: 34

 7798 23:28:35.208631  

 7799 23:28:35.211453  Set Vref, RX VrefLevel [Byte0]: 35

 7800 23:28:35.214831                           [Byte1]: 35

 7801 23:28:35.215256  

 7802 23:28:35.218118  Set Vref, RX VrefLevel [Byte0]: 36

 7803 23:28:35.221282                           [Byte1]: 36

 7804 23:28:35.221730  

 7805 23:28:35.224667  Set Vref, RX VrefLevel [Byte0]: 37

 7806 23:28:35.228235                           [Byte1]: 37

 7807 23:28:35.232006  

 7808 23:28:35.232426  Set Vref, RX VrefLevel [Byte0]: 38

 7809 23:28:35.235352                           [Byte1]: 38

 7810 23:28:35.239569  

 7811 23:28:35.239989  Set Vref, RX VrefLevel [Byte0]: 39

 7812 23:28:35.242713                           [Byte1]: 39

 7813 23:28:35.247385  

 7814 23:28:35.247804  Set Vref, RX VrefLevel [Byte0]: 40

 7815 23:28:35.250358                           [Byte1]: 40

 7816 23:28:35.254838  

 7817 23:28:35.255257  Set Vref, RX VrefLevel [Byte0]: 41

 7818 23:28:35.257886                           [Byte1]: 41

 7819 23:28:35.262524  

 7820 23:28:35.262944  Set Vref, RX VrefLevel [Byte0]: 42

 7821 23:28:35.265879                           [Byte1]: 42

 7822 23:28:35.270014  

 7823 23:28:35.270474  Set Vref, RX VrefLevel [Byte0]: 43

 7824 23:28:35.273535                           [Byte1]: 43

 7825 23:28:35.277624  

 7826 23:28:35.278061  Set Vref, RX VrefLevel [Byte0]: 44

 7827 23:28:35.280836                           [Byte1]: 44

 7828 23:28:35.285024  

 7829 23:28:35.285485  Set Vref, RX VrefLevel [Byte0]: 45

 7830 23:28:35.288206                           [Byte1]: 45

 7831 23:28:35.292794  

 7832 23:28:35.293205  Set Vref, RX VrefLevel [Byte0]: 46

 7833 23:28:35.295890                           [Byte1]: 46

 7834 23:28:35.300705  

 7835 23:28:35.303731  Set Vref, RX VrefLevel [Byte0]: 47

 7836 23:28:35.304264                           [Byte1]: 47

 7837 23:28:35.307631  

 7838 23:28:35.308078  Set Vref, RX VrefLevel [Byte0]: 48

 7839 23:28:35.311017                           [Byte1]: 48

 7840 23:28:35.315691  

 7841 23:28:35.316105  Set Vref, RX VrefLevel [Byte0]: 49

 7842 23:28:35.318454                           [Byte1]: 49

 7843 23:28:35.322723  

 7844 23:28:35.323149  Set Vref, RX VrefLevel [Byte0]: 50

 7845 23:28:35.326387                           [Byte1]: 50

 7846 23:28:35.330380  

 7847 23:28:35.330846  Set Vref, RX VrefLevel [Byte0]: 51

 7848 23:28:35.333654                           [Byte1]: 51

 7849 23:28:35.338086  

 7850 23:28:35.338561  Set Vref, RX VrefLevel [Byte0]: 52

 7851 23:28:35.341393                           [Byte1]: 52

 7852 23:28:35.345905  

 7853 23:28:35.346362  Set Vref, RX VrefLevel [Byte0]: 53

 7854 23:28:35.349325                           [Byte1]: 53

 7855 23:28:35.353028  

 7856 23:28:35.353508  Set Vref, RX VrefLevel [Byte0]: 54

 7857 23:28:35.356698                           [Byte1]: 54

 7858 23:28:35.360770  

 7859 23:28:35.361231  Set Vref, RX VrefLevel [Byte0]: 55

 7860 23:28:35.363846                           [Byte1]: 55

 7861 23:28:35.368229  

 7862 23:28:35.368697  Set Vref, RX VrefLevel [Byte0]: 56

 7863 23:28:35.371608                           [Byte1]: 56

 7864 23:28:35.375846  

 7865 23:28:35.376256  Set Vref, RX VrefLevel [Byte0]: 57

 7866 23:28:35.379128                           [Byte1]: 57

 7867 23:28:35.383373  

 7868 23:28:35.383862  Set Vref, RX VrefLevel [Byte0]: 58

 7869 23:28:35.386629                           [Byte1]: 58

 7870 23:28:35.391195  

 7871 23:28:35.391667  Set Vref, RX VrefLevel [Byte0]: 59

 7872 23:28:35.394120                           [Byte1]: 59

 7873 23:28:35.398903  

 7874 23:28:35.399652  Set Vref, RX VrefLevel [Byte0]: 60

 7875 23:28:35.402040                           [Byte1]: 60

 7876 23:28:35.406217  

 7877 23:28:35.406763  Set Vref, RX VrefLevel [Byte0]: 61

 7878 23:28:35.409707                           [Byte1]: 61

 7879 23:28:35.413477  

 7880 23:28:35.413981  Set Vref, RX VrefLevel [Byte0]: 62

 7881 23:28:35.417340                           [Byte1]: 62

 7882 23:28:35.421459  

 7883 23:28:35.421975  Set Vref, RX VrefLevel [Byte0]: 63

 7884 23:28:35.424417                           [Byte1]: 63

 7885 23:28:35.428911  

 7886 23:28:35.429330  Set Vref, RX VrefLevel [Byte0]: 64

 7887 23:28:35.432144                           [Byte1]: 64

 7888 23:28:35.436539  

 7889 23:28:35.436958  Set Vref, RX VrefLevel [Byte0]: 65

 7890 23:28:35.439827                           [Byte1]: 65

 7891 23:28:35.444304  

 7892 23:28:35.444725  Set Vref, RX VrefLevel [Byte0]: 66

 7893 23:28:35.447535                           [Byte1]: 66

 7894 23:28:35.451514  

 7895 23:28:35.452068  Set Vref, RX VrefLevel [Byte0]: 67

 7896 23:28:35.454806                           [Byte1]: 67

 7897 23:28:35.459007  

 7898 23:28:35.459428  Set Vref, RX VrefLevel [Byte0]: 68

 7899 23:28:35.462299                           [Byte1]: 68

 7900 23:28:35.466953  

 7901 23:28:35.467382  Set Vref, RX VrefLevel [Byte0]: 69

 7902 23:28:35.470182                           [Byte1]: 69

 7903 23:28:35.474445  

 7904 23:28:35.474865  Set Vref, RX VrefLevel [Byte0]: 70

 7905 23:28:35.477646                           [Byte1]: 70

 7906 23:28:35.481834  

 7907 23:28:35.482256  Set Vref, RX VrefLevel [Byte0]: 71

 7908 23:28:35.485436                           [Byte1]: 71

 7909 23:28:35.489339  

 7910 23:28:35.489806  Set Vref, RX VrefLevel [Byte0]: 72

 7911 23:28:35.492591                           [Byte1]: 72

 7912 23:28:35.496991  

 7913 23:28:35.497411  Set Vref, RX VrefLevel [Byte0]: 73

 7914 23:28:35.500359                           [Byte1]: 73

 7915 23:28:35.504859  

 7916 23:28:35.505394  Final RX Vref Byte 0 = 54 to rank0

 7917 23:28:35.508320  Final RX Vref Byte 1 = 63 to rank0

 7918 23:28:35.511228  Final RX Vref Byte 0 = 54 to rank1

 7919 23:28:35.514615  Final RX Vref Byte 1 = 63 to rank1==

 7920 23:28:35.518474  Dram Type= 6, Freq= 0, CH_0, rank 0

 7921 23:28:35.524521  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7922 23:28:35.524948  ==

 7923 23:28:35.525284  DQS Delay:

 7924 23:28:35.525630  DQS0 = 0, DQS1 = 0

 7925 23:28:35.527902  DQM Delay:

 7926 23:28:35.528321  DQM0 = 133, DQM1 = 127

 7927 23:28:35.531081  DQ Delay:

 7928 23:28:35.534612  DQ0 =134, DQ1 =136, DQ2 =134, DQ3 =130

 7929 23:28:35.537863  DQ4 =132, DQ5 =124, DQ6 =140, DQ7 =138

 7930 23:28:35.541079  DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120

 7931 23:28:35.544242  DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136

 7932 23:28:35.544481  

 7933 23:28:35.544545  

 7934 23:28:35.544605  

 7935 23:28:35.547440  [DramC_TX_OE_Calibration] TA2

 7936 23:28:35.550857  Original DQ_B0 (3 6) =30, OEN = 27

 7937 23:28:35.553888  Original DQ_B1 (3 6) =30, OEN = 27

 7938 23:28:35.557323  24, 0x0, End_B0=24 End_B1=24

 7939 23:28:35.557406  25, 0x0, End_B0=25 End_B1=25

 7940 23:28:35.560914  26, 0x0, End_B0=26 End_B1=26

 7941 23:28:35.563966  27, 0x0, End_B0=27 End_B1=27

 7942 23:28:35.567248  28, 0x0, End_B0=28 End_B1=28

 7943 23:28:35.570763  29, 0x0, End_B0=29 End_B1=29

 7944 23:28:35.570846  30, 0x0, End_B0=30 End_B1=30

 7945 23:28:35.573698  31, 0x4545, End_B0=30 End_B1=30

 7946 23:28:35.577293  Byte0 end_step=30  best_step=27

 7947 23:28:35.580384  Byte1 end_step=30  best_step=27

 7948 23:28:35.583943  Byte0 TX OE(2T, 0.5T) = (3, 3)

 7949 23:28:35.587037  Byte1 TX OE(2T, 0.5T) = (3, 3)

 7950 23:28:35.587118  

 7951 23:28:35.587183  

 7952 23:28:35.594066  [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps

 7953 23:28:35.596940  CH0 RK0: MR19=303, MR18=2420

 7954 23:28:35.603852  CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16

 7955 23:28:35.603964  

 7956 23:28:35.606833  ----->DramcWriteLeveling(PI) begin...

 7957 23:28:35.606946  ==

 7958 23:28:35.610179  Dram Type= 6, Freq= 0, CH_0, rank 1

 7959 23:28:35.613666  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7960 23:28:35.613802  ==

 7961 23:28:35.617196  Write leveling (Byte 0): 37 => 37

 7962 23:28:35.620242  Write leveling (Byte 1): 27 => 27

 7963 23:28:35.623737  DramcWriteLeveling(PI) end<-----

 7964 23:28:35.623910  

 7965 23:28:35.624048  ==

 7966 23:28:35.626998  Dram Type= 6, Freq= 0, CH_0, rank 1

 7967 23:28:35.630491  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 7968 23:28:35.630694  ==

 7969 23:28:35.634007  [Gating] SW mode calibration

 7970 23:28:35.640153  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 7971 23:28:35.647412  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 7972 23:28:35.650695   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7973 23:28:35.656884   1  4  4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)

 7974 23:28:35.660236   1  4  8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 7975 23:28:35.663907   1  4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)

 7976 23:28:35.670463   1  4 16 | B1->B0 | 2a2a 2f2f | 1 1 | (1 1) (0 0)

 7977 23:28:35.673748   1  4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)

 7978 23:28:35.677416   1  4 24 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)

 7979 23:28:35.680661   1  4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)

 7980 23:28:35.686603   1  5  0 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)

 7981 23:28:35.690183   1  5  4 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)

 7982 23:28:35.693405   1  5  8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (1 1)

 7983 23:28:35.700364   1  5 12 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 1)

 7984 23:28:35.703195   1  5 16 | B1->B0 | 2b2b 2827 | 0 1 | (1 0) (0 0)

 7985 23:28:35.706904   1  5 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)

 7986 23:28:35.713401   1  5 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)

 7987 23:28:35.716902   1  5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 7988 23:28:35.719913   1  6  0 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)

 7989 23:28:35.727165   1  6  4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)

 7990 23:28:35.729883   1  6  8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)

 7991 23:28:35.733205   1  6 12 | B1->B0 | 2626 3938 | 0 1 | (0 0) (0 0)

 7992 23:28:35.739785   1  6 16 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)

 7993 23:28:35.742956   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7994 23:28:35.746700   1  6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7995 23:28:35.752938   1  6 28 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)

 7996 23:28:35.756760   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7997 23:28:35.759358   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 7998 23:28:35.765851   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 7999 23:28:35.769226   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8000 23:28:35.772889   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8001 23:28:35.779561   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8002 23:28:35.782973   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8003 23:28:35.786377   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8004 23:28:35.792769   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8005 23:28:35.796281   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8006 23:28:35.799450   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8007 23:28:35.806056   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8008 23:28:35.809609   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8009 23:28:35.812470   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8010 23:28:35.819460   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8011 23:28:35.822566   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8012 23:28:35.825877   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8013 23:28:35.833117   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8014 23:28:35.835975   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8015 23:28:35.839198   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8016 23:28:35.843475   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8017 23:28:35.849656   1  9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8018 23:28:35.852688  Total UI for P1: 0, mck2ui 16

 8019 23:28:35.855982  best dqsien dly found for B0: ( 1,  9, 14)

 8020 23:28:35.859389  Total UI for P1: 0, mck2ui 16

 8021 23:28:35.862715  best dqsien dly found for B1: ( 1,  9, 14)

 8022 23:28:35.866333  best DQS0 dly(MCK, UI, PI) = (1, 9, 14)

 8023 23:28:35.869649  best DQS1 dly(MCK, UI, PI) = (1, 9, 14)

 8024 23:28:35.870066  

 8025 23:28:35.872694  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8026 23:28:35.875996  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)

 8027 23:28:35.879179  [Gating] SW calibration Done

 8028 23:28:35.879605  ==

 8029 23:28:35.882823  Dram Type= 6, Freq= 0, CH_0, rank 1

 8030 23:28:35.886316  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8031 23:28:35.886750  ==

 8032 23:28:35.889775  RX Vref Scan: 0

 8033 23:28:35.890187  

 8034 23:28:35.892611  RX Vref 0 -> 0, step: 1

 8035 23:28:35.893026  

 8036 23:28:35.893354  RX Delay 0 -> 252, step: 8

 8037 23:28:35.899488  iDelay=200, Bit 0, Center 135 (80 ~ 191) 112

 8038 23:28:35.903044  iDelay=200, Bit 1, Center 139 (88 ~ 191) 104

 8039 23:28:35.905848  iDelay=200, Bit 2, Center 135 (80 ~ 191) 112

 8040 23:28:35.909420  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8041 23:28:35.913119  iDelay=200, Bit 4, Center 139 (88 ~ 191) 104

 8042 23:28:35.915932  iDelay=200, Bit 5, Center 127 (72 ~ 183) 112

 8043 23:28:35.922359  iDelay=200, Bit 6, Center 143 (88 ~ 199) 112

 8044 23:28:35.925846  iDelay=200, Bit 7, Center 143 (88 ~ 199) 112

 8045 23:28:35.929306  iDelay=200, Bit 8, Center 119 (64 ~ 175) 112

 8046 23:28:35.932404  iDelay=200, Bit 9, Center 119 (64 ~ 175) 112

 8047 23:28:35.935980  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8048 23:28:35.942649  iDelay=200, Bit 11, Center 123 (72 ~ 175) 104

 8049 23:28:35.946055  iDelay=200, Bit 12, Center 135 (80 ~ 191) 112

 8050 23:28:35.948979  iDelay=200, Bit 13, Center 139 (88 ~ 191) 104

 8051 23:28:35.952297  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8052 23:28:35.958955  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8053 23:28:35.959479  ==

 8054 23:28:35.962332  Dram Type= 6, Freq= 0, CH_0, rank 1

 8055 23:28:35.965559  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8056 23:28:35.966108  ==

 8057 23:28:35.966448  DQS Delay:

 8058 23:28:35.969053  DQS0 = 0, DQS1 = 0

 8059 23:28:35.969472  DQM Delay:

 8060 23:28:35.972418  DQM0 = 137, DQM1 = 130

 8061 23:28:35.972836  DQ Delay:

 8062 23:28:35.975612  DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135

 8063 23:28:35.979032  DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143

 8064 23:28:35.982356  DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123

 8065 23:28:35.985544  DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139

 8066 23:28:35.986210  

 8067 23:28:35.986598  

 8068 23:28:35.989092  ==

 8069 23:28:35.991955  Dram Type= 6, Freq= 0, CH_0, rank 1

 8070 23:28:35.995559  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8071 23:28:35.996076  ==

 8072 23:28:35.996414  

 8073 23:28:35.996725  

 8074 23:28:35.999097  	TX Vref Scan disable

 8075 23:28:35.999611   == TX Byte 0 ==

 8076 23:28:36.005617  Update DQ  dly =994 (3 ,6, 34)  DQ  OEN =(3 ,3)

 8077 23:28:36.008589  Update DQM dly =994 (3 ,6, 34)  DQM OEN =(3 ,3)

 8078 23:28:36.009006   == TX Byte 1 ==

 8079 23:28:36.015107  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8080 23:28:36.018717  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8081 23:28:36.019231  ==

 8082 23:28:36.021891  Dram Type= 6, Freq= 0, CH_0, rank 1

 8083 23:28:36.025247  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8084 23:28:36.025709  ==

 8085 23:28:36.041108  

 8086 23:28:36.044552  TX Vref early break, caculate TX vref

 8087 23:28:36.048040  TX Vref=16, minBit 1, minWin=23, winSum=386

 8088 23:28:36.051022  TX Vref=18, minBit 1, minWin=23, winSum=396

 8089 23:28:36.054735  TX Vref=20, minBit 1, minWin=24, winSum=408

 8090 23:28:36.058109  TX Vref=22, minBit 0, minWin=25, winSum=411

 8091 23:28:36.061220  TX Vref=24, minBit 1, minWin=24, winSum=417

 8092 23:28:36.067519  TX Vref=26, minBit 1, minWin=25, winSum=424

 8093 23:28:36.071126  TX Vref=28, minBit 3, minWin=25, winSum=424

 8094 23:28:36.074309  TX Vref=30, minBit 4, minWin=24, winSum=414

 8095 23:28:36.077401  TX Vref=32, minBit 1, minWin=25, winSum=411

 8096 23:28:36.081310  TX Vref=34, minBit 0, minWin=24, winSum=403

 8097 23:28:36.084533  TX Vref=36, minBit 0, minWin=24, winSum=395

 8098 23:28:36.090715  [TxChooseVref] Worse bit 1, Min win 25, Win sum 424, Final Vref 26

 8099 23:28:36.091270  

 8100 23:28:36.094322  Final TX Range 0 Vref 26

 8101 23:28:36.094743  

 8102 23:28:36.095072  ==

 8103 23:28:36.097702  Dram Type= 6, Freq= 0, CH_0, rank 1

 8104 23:28:36.101070  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8105 23:28:36.101626  ==

 8106 23:28:36.101974  

 8107 23:28:36.102284  

 8108 23:28:36.104317  	TX Vref Scan disable

 8109 23:28:36.111022  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8110 23:28:36.111505   == TX Byte 0 ==

 8111 23:28:36.114466  u2DelayCellOfst[0]=13 cells (4 PI)

 8112 23:28:36.117303  u2DelayCellOfst[1]=16 cells (5 PI)

 8113 23:28:36.121386  u2DelayCellOfst[2]=13 cells (4 PI)

 8114 23:28:36.124424  u2DelayCellOfst[3]=13 cells (4 PI)

 8115 23:28:36.127373  u2DelayCellOfst[4]=10 cells (3 PI)

 8116 23:28:36.130719  u2DelayCellOfst[5]=0 cells (0 PI)

 8117 23:28:36.133992  u2DelayCellOfst[6]=16 cells (5 PI)

 8118 23:28:36.137683  u2DelayCellOfst[7]=16 cells (5 PI)

 8119 23:28:36.141136  Update DQ  dly =991 (3 ,6, 31)  DQ  OEN =(3 ,3)

 8120 23:28:36.143860  Update DQM dly =993 (3 ,6, 33)  DQM OEN =(3 ,3)

 8121 23:28:36.147819   == TX Byte 1 ==

 8122 23:28:36.151203  u2DelayCellOfst[8]=3 cells (1 PI)

 8123 23:28:36.151623  u2DelayCellOfst[9]=0 cells (0 PI)

 8124 23:28:36.154640  u2DelayCellOfst[10]=10 cells (3 PI)

 8125 23:28:36.157299  u2DelayCellOfst[11]=6 cells (2 PI)

 8126 23:28:36.160572  u2DelayCellOfst[12]=13 cells (4 PI)

 8127 23:28:36.164129  u2DelayCellOfst[13]=13 cells (4 PI)

 8128 23:28:36.167340  u2DelayCellOfst[14]=16 cells (5 PI)

 8129 23:28:36.170526  u2DelayCellOfst[15]=10 cells (3 PI)

 8130 23:28:36.174232  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8131 23:28:36.180531  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8132 23:28:36.180948  DramC Write-DBI on

 8133 23:28:36.181312  ==

 8134 23:28:36.183951  Dram Type= 6, Freq= 0, CH_0, rank 1

 8135 23:28:36.190834  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8136 23:28:36.191341  ==

 8137 23:28:36.191693  

 8138 23:28:36.192000  

 8139 23:28:36.192289  	TX Vref Scan disable

 8140 23:28:36.194861   == TX Byte 0 ==

 8141 23:28:36.197848  Update DQM dly =737 (2 ,6, 33)  DQM OEN =(3 ,3)

 8142 23:28:36.201392   == TX Byte 1 ==

 8143 23:28:36.204649  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8144 23:28:36.207611  DramC Write-DBI off

 8145 23:28:36.207995  

 8146 23:28:36.208314  [DATLAT]

 8147 23:28:36.208617  Freq=1600, CH0 RK1

 8148 23:28:36.208971  

 8149 23:28:36.211213  DATLAT Default: 0xf

 8150 23:28:36.214639  0, 0xFFFF, sum = 0

 8151 23:28:36.215060  1, 0xFFFF, sum = 0

 8152 23:28:36.218202  2, 0xFFFF, sum = 0

 8153 23:28:36.218624  3, 0xFFFF, sum = 0

 8154 23:28:36.221244  4, 0xFFFF, sum = 0

 8155 23:28:36.221817  5, 0xFFFF, sum = 0

 8156 23:28:36.224968  6, 0xFFFF, sum = 0

 8157 23:28:36.225433  7, 0xFFFF, sum = 0

 8158 23:28:36.228014  8, 0xFFFF, sum = 0

 8159 23:28:36.228388  9, 0xFFFF, sum = 0

 8160 23:28:36.230978  10, 0xFFFF, sum = 0

 8161 23:28:36.231433  11, 0xFFFF, sum = 0

 8162 23:28:36.234362  12, 0xFFFF, sum = 0

 8163 23:28:36.234781  13, 0xFFFF, sum = 0

 8164 23:28:36.237771  14, 0x0, sum = 1

 8165 23:28:36.238191  15, 0x0, sum = 2

 8166 23:28:36.241304  16, 0x0, sum = 3

 8167 23:28:36.241878  17, 0x0, sum = 4

 8168 23:28:36.245070  best_step = 15

 8169 23:28:36.245617  

 8170 23:28:36.245983  ==

 8171 23:28:36.247586  Dram Type= 6, Freq= 0, CH_0, rank 1

 8172 23:28:36.251297  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8173 23:28:36.251815  ==

 8174 23:28:36.254834  RX Vref Scan: 0

 8175 23:28:36.255350  

 8176 23:28:36.255682  RX Vref 0 -> 0, step: 1

 8177 23:28:36.255990  

 8178 23:28:36.257634  RX Delay 19 -> 252, step: 4

 8179 23:28:36.260729  iDelay=191, Bit 0, Center 134 (83 ~ 186) 104

 8180 23:28:36.267469  iDelay=191, Bit 1, Center 138 (91 ~ 186) 96

 8181 23:28:36.271074  iDelay=191, Bit 2, Center 130 (79 ~ 182) 104

 8182 23:28:36.274274  iDelay=191, Bit 3, Center 132 (79 ~ 186) 108

 8183 23:28:36.277439  iDelay=191, Bit 4, Center 136 (83 ~ 190) 108

 8184 23:28:36.280718  iDelay=191, Bit 5, Center 124 (71 ~ 178) 108

 8185 23:28:36.287775  iDelay=191, Bit 6, Center 138 (87 ~ 190) 104

 8186 23:28:36.290820  iDelay=191, Bit 7, Center 140 (91 ~ 190) 100

 8187 23:28:36.294192  iDelay=191, Bit 8, Center 118 (67 ~ 170) 104

 8188 23:28:36.297507  iDelay=191, Bit 9, Center 116 (67 ~ 166) 100

 8189 23:28:36.300752  iDelay=191, Bit 10, Center 128 (75 ~ 182) 108

 8190 23:28:36.307660  iDelay=191, Bit 11, Center 118 (67 ~ 170) 104

 8191 23:28:36.311023  iDelay=191, Bit 12, Center 134 (83 ~ 186) 104

 8192 23:28:36.314107  iDelay=191, Bit 13, Center 134 (83 ~ 186) 104

 8193 23:28:36.317538  iDelay=191, Bit 14, Center 134 (83 ~ 186) 104

 8194 23:28:36.323890  iDelay=191, Bit 15, Center 134 (87 ~ 182) 96

 8195 23:28:36.324581  ==

 8196 23:28:36.327543  Dram Type= 6, Freq= 0, CH_0, rank 1

 8197 23:28:36.330589  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8198 23:28:36.331084  ==

 8199 23:28:36.331450  DQS Delay:

 8200 23:28:36.334099  DQS0 = 0, DQS1 = 0

 8201 23:28:36.334553  DQM Delay:

 8202 23:28:36.337156  DQM0 = 134, DQM1 = 127

 8203 23:28:36.337702  DQ Delay:

 8204 23:28:36.340443  DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =132

 8205 23:28:36.344267  DQ4 =136, DQ5 =124, DQ6 =138, DQ7 =140

 8206 23:28:36.347305  DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118

 8207 23:28:36.350439  DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134

 8208 23:28:36.350900  

 8209 23:28:36.351391  

 8210 23:28:36.351913  

 8211 23:28:36.354211  [DramC_TX_OE_Calibration] TA2

 8212 23:28:36.357049  Original DQ_B0 (3 6) =30, OEN = 27

 8213 23:28:36.360467  Original DQ_B1 (3 6) =30, OEN = 27

 8214 23:28:36.363833  24, 0x0, End_B0=24 End_B1=24

 8215 23:28:36.367270  25, 0x0, End_B0=25 End_B1=25

 8216 23:28:36.367737  26, 0x0, End_B0=26 End_B1=26

 8217 23:28:36.370674  27, 0x0, End_B0=27 End_B1=27

 8218 23:28:36.373809  28, 0x0, End_B0=28 End_B1=28

 8219 23:28:36.377111  29, 0x0, End_B0=29 End_B1=29

 8220 23:28:36.380150  30, 0x0, End_B0=30 End_B1=30

 8221 23:28:36.380566  31, 0x5151, End_B0=30 End_B1=30

 8222 23:28:36.383546  Byte0 end_step=30  best_step=27

 8223 23:28:36.387118  Byte1 end_step=30  best_step=27

 8224 23:28:36.390357  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8225 23:28:36.393792  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8226 23:28:36.394206  

 8227 23:28:36.394529  

 8228 23:28:36.400258  [DQSOSCAuto] RK1, (LSB)MR18= 0x1d06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 395 ps

 8229 23:28:36.403852  CH0 RK1: MR19=303, MR18=1D06

 8230 23:28:36.410489  CH0_RK1: MR19=0x303, MR18=0x1D06, DQSOSC=395, MR23=63, INC=23, DEC=15

 8231 23:28:36.413662  [RxdqsGatingPostProcess] freq 1600

 8232 23:28:36.420558  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8233 23:28:36.423373  best DQS0 dly(2T, 0.5T) = (1, 1)

 8234 23:28:36.424018  best DQS1 dly(2T, 0.5T) = (1, 1)

 8235 23:28:36.426579  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8236 23:28:36.429700  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8237 23:28:36.432990  best DQS0 dly(2T, 0.5T) = (1, 1)

 8238 23:28:36.436305  best DQS1 dly(2T, 0.5T) = (1, 1)

 8239 23:28:36.439611  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 8240 23:28:36.443076  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 8241 23:28:36.446943  Pre-setting of DQS Precalculation

 8242 23:28:36.449946  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 8243 23:28:36.450369  ==

 8244 23:28:36.452855  Dram Type= 6, Freq= 0, CH_1, rank 0

 8245 23:28:36.459736  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8246 23:28:36.460156  ==

 8247 23:28:36.463208  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8248 23:28:36.470079  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8249 23:28:36.473000  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8250 23:28:36.480024  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8251 23:28:36.487322  [CA 0] Center 41 (12~71) winsize 60

 8252 23:28:36.490823  [CA 1] Center 41 (12~71) winsize 60

 8253 23:28:36.494138  [CA 2] Center 38 (9~68) winsize 60

 8254 23:28:36.497754  [CA 3] Center 37 (8~66) winsize 59

 8255 23:28:36.500573  [CA 4] Center 37 (8~67) winsize 60

 8256 23:28:36.504148  [CA 5] Center 36 (7~66) winsize 60

 8257 23:28:36.504565  

 8258 23:28:36.507249  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8259 23:28:36.507668  

 8260 23:28:36.510689  [CATrainingPosCal] consider 1 rank data

 8261 23:28:36.514525  u2DelayCellTimex100 = 290/100 ps

 8262 23:28:36.517711  CA0 delay=41 (12~71),Diff = 5 PI (16 cell)

 8263 23:28:36.524363  CA1 delay=41 (12~71),Diff = 5 PI (16 cell)

 8264 23:28:36.527195  CA2 delay=38 (9~68),Diff = 2 PI (6 cell)

 8265 23:28:36.530661  CA3 delay=37 (8~66),Diff = 1 PI (3 cell)

 8266 23:28:36.533983  CA4 delay=37 (8~67),Diff = 1 PI (3 cell)

 8267 23:28:36.537239  CA5 delay=36 (7~66),Diff = 0 PI (0 cell)

 8268 23:28:36.537689  

 8269 23:28:36.541061  CA PerBit enable=1, Macro0, CA PI delay=36

 8270 23:28:36.541482  

 8271 23:28:36.544213  [CBTSetCACLKResult] CA Dly = 36

 8272 23:28:36.547619  CS Dly: 12 (0~43)

 8273 23:28:36.550935  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8274 23:28:36.554090  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8275 23:28:36.554512  ==

 8276 23:28:36.557140  Dram Type= 6, Freq= 0, CH_1, rank 1

 8277 23:28:36.560316  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8278 23:28:36.563757  ==

 8279 23:28:36.567100  pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0

 8280 23:28:36.570317  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1

 8281 23:28:36.577352  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1

 8282 23:28:36.583390  u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32

 8283 23:28:36.591166  [CA 0] Center 42 (12~72) winsize 61

 8284 23:28:36.594253  [CA 1] Center 41 (12~71) winsize 60

 8285 23:28:36.597649  [CA 2] Center 38 (9~68) winsize 60

 8286 23:28:36.601014  [CA 3] Center 38 (8~68) winsize 61

 8287 23:28:36.604432  [CA 4] Center 38 (8~69) winsize 62

 8288 23:28:36.607682  [CA 5] Center 37 (8~67) winsize 60

 8289 23:28:36.608131  

 8290 23:28:36.610805  [CmdBusTrainingLP45] Vref(ca) range 0: 32

 8291 23:28:36.611237  

 8292 23:28:36.614380  [CATrainingPosCal] consider 2 rank data

 8293 23:28:36.617531  u2DelayCellTimex100 = 290/100 ps

 8294 23:28:36.620867  CA0 delay=41 (12~71),Diff = 4 PI (13 cell)

 8295 23:28:36.627331  CA1 delay=41 (12~71),Diff = 4 PI (13 cell)

 8296 23:28:36.630493  CA2 delay=38 (9~68),Diff = 1 PI (3 cell)

 8297 23:28:36.634431  CA3 delay=37 (8~66),Diff = 0 PI (0 cell)

 8298 23:28:36.637280  CA4 delay=37 (8~67),Diff = 0 PI (0 cell)

 8299 23:28:36.640927  CA5 delay=37 (8~66),Diff = 0 PI (0 cell)

 8300 23:28:36.641451  

 8301 23:28:36.644259  CA PerBit enable=1, Macro0, CA PI delay=37

 8302 23:28:36.644673  

 8303 23:28:36.648054  [CBTSetCACLKResult] CA Dly = 37

 8304 23:28:36.650560  CS Dly: 13 (0~45)

 8305 23:28:36.654107  [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0

 8306 23:28:36.657444  [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0

 8307 23:28:36.657956  

 8308 23:28:36.661053  ----->DramcWriteLeveling(PI) begin...

 8309 23:28:36.661655  ==

 8310 23:28:36.664226  Dram Type= 6, Freq= 0, CH_1, rank 0

 8311 23:28:36.670717  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8312 23:28:36.671132  ==

 8313 23:28:36.673620  Write leveling (Byte 0): 28 => 28

 8314 23:28:36.674037  Write leveling (Byte 1): 28 => 28

 8315 23:28:36.676900  DramcWriteLeveling(PI) end<-----

 8316 23:28:36.677311  

 8317 23:28:36.677754  ==

 8318 23:28:36.680488  Dram Type= 6, Freq= 0, CH_1, rank 0

 8319 23:28:36.687013  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8320 23:28:36.687451  ==

 8321 23:28:36.690005  [Gating] SW mode calibration

 8322 23:28:36.697038  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8323 23:28:36.700375  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8324 23:28:36.706739   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8325 23:28:36.709939   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8326 23:28:36.713807   1  4  8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (0 0)

 8327 23:28:36.720318   1  4 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)

 8328 23:28:36.723387   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8329 23:28:36.726919   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8330 23:28:36.733222   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8331 23:28:36.736657   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8332 23:28:36.740359   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8333 23:28:36.746795   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8334 23:28:36.750014   1  5  8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)

 8335 23:28:36.753324   1  5 12 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (1 0)

 8336 23:28:36.760186   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8337 23:28:36.763036   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8338 23:28:36.766715   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8339 23:28:36.769705   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8340 23:28:36.776751   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8341 23:28:36.779984   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8342 23:28:36.783210   1  6  8 | B1->B0 | 2424 3737 | 0 1 | (0 0) (0 0)

 8343 23:28:36.789935   1  6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)

 8344 23:28:36.793324   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8345 23:28:36.796686   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8346 23:28:36.803304   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8347 23:28:36.807068   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8348 23:28:36.809883   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8349 23:28:36.816845   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8350 23:28:36.819796   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)

 8351 23:28:36.823453   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)

 8352 23:28:36.829715   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)

 8353 23:28:36.832962   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8354 23:28:36.836305   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8355 23:28:36.843342   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8356 23:28:36.846827   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8357 23:28:36.849747   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8358 23:28:36.856531   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8359 23:28:36.860005   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8360 23:28:36.863075   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8361 23:28:36.870005   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8362 23:28:36.873573   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8363 23:28:36.876789   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8364 23:28:36.882762   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8365 23:28:36.886029   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8366 23:28:36.889180   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8367 23:28:36.896355   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8368 23:28:36.899337   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8369 23:28:36.903044  Total UI for P1: 0, mck2ui 16

 8370 23:28:36.906518  best dqsien dly found for B0: ( 1,  9, 10)

 8371 23:28:36.909922  Total UI for P1: 0, mck2ui 16

 8372 23:28:36.912959  best dqsien dly found for B1: ( 1,  9, 10)

 8373 23:28:36.916736  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8374 23:28:36.919716  best DQS1 dly(MCK, UI, PI) = (1, 9, 10)

 8375 23:28:36.920250  

 8376 23:28:36.923284  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8377 23:28:36.926254  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8378 23:28:36.929448  [Gating] SW calibration Done

 8379 23:28:36.929957  ==

 8380 23:28:36.933150  Dram Type= 6, Freq= 0, CH_1, rank 0

 8381 23:28:36.936036  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8382 23:28:36.936501  ==

 8383 23:28:36.939546  RX Vref Scan: 0

 8384 23:28:36.940115  

 8385 23:28:36.942741  RX Vref 0 -> 0, step: 1

 8386 23:28:36.943209  

 8387 23:28:36.943575  RX Delay 0 -> 252, step: 8

 8388 23:28:36.949673  iDelay=200, Bit 0, Center 143 (96 ~ 191) 96

 8389 23:28:36.953010  iDelay=200, Bit 1, Center 131 (80 ~ 183) 104

 8390 23:28:36.956036  iDelay=200, Bit 2, Center 123 (72 ~ 175) 104

 8391 23:28:36.959449  iDelay=200, Bit 3, Center 135 (80 ~ 191) 112

 8392 23:28:36.962967  iDelay=200, Bit 4, Center 131 (80 ~ 183) 104

 8393 23:28:36.965849  iDelay=200, Bit 5, Center 147 (96 ~ 199) 104

 8394 23:28:36.972816  iDelay=200, Bit 6, Center 147 (96 ~ 199) 104

 8395 23:28:36.976282  iDelay=200, Bit 7, Center 135 (80 ~ 191) 112

 8396 23:28:36.979270  iDelay=200, Bit 8, Center 119 (72 ~ 167) 96

 8397 23:28:36.982677  iDelay=200, Bit 9, Center 123 (72 ~ 175) 104

 8398 23:28:36.985907  iDelay=200, Bit 10, Center 131 (80 ~ 183) 104

 8399 23:28:36.992342  iDelay=200, Bit 11, Center 127 (80 ~ 175) 96

 8400 23:28:36.995785  iDelay=200, Bit 12, Center 139 (88 ~ 191) 104

 8401 23:28:36.999010  iDelay=200, Bit 13, Center 143 (88 ~ 199) 112

 8402 23:28:37.002376  iDelay=200, Bit 14, Center 139 (88 ~ 191) 104

 8403 23:28:37.009322  iDelay=200, Bit 15, Center 139 (88 ~ 191) 104

 8404 23:28:37.009848  ==

 8405 23:28:37.012498  Dram Type= 6, Freq= 0, CH_1, rank 0

 8406 23:28:37.015806  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8407 23:28:37.016228  ==

 8408 23:28:37.016576  DQS Delay:

 8409 23:28:37.019453  DQS0 = 0, DQS1 = 0

 8410 23:28:37.019870  DQM Delay:

 8411 23:28:37.022427  DQM0 = 136, DQM1 = 132

 8412 23:28:37.022844  DQ Delay:

 8413 23:28:37.026182  DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135

 8414 23:28:37.029297  DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135

 8415 23:28:37.032803  DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127

 8416 23:28:37.035886  DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139

 8417 23:28:37.036303  

 8418 23:28:37.036633  

 8419 23:28:37.036938  ==

 8420 23:28:37.039620  Dram Type= 6, Freq= 0, CH_1, rank 0

 8421 23:28:37.046204  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8422 23:28:37.046678  ==

 8423 23:28:37.047018  

 8424 23:28:37.047330  

 8425 23:28:37.047627  	TX Vref Scan disable

 8426 23:28:37.049340   == TX Byte 0 ==

 8427 23:28:37.052935  Update DQ  dly =983 (3 ,6, 23)  DQ  OEN =(3 ,3)

 8428 23:28:37.059181  Update DQM dly =983 (3 ,6, 23)  DQM OEN =(3 ,3)

 8429 23:28:37.059604   == TX Byte 1 ==

 8430 23:28:37.062619  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8431 23:28:37.069182  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8432 23:28:37.069809  ==

 8433 23:28:37.072755  Dram Type= 6, Freq= 0, CH_1, rank 0

 8434 23:28:37.075907  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8435 23:28:37.076332  ==

 8436 23:28:37.087831  

 8437 23:28:37.091384  TX Vref early break, caculate TX vref

 8438 23:28:37.094434  TX Vref=16, minBit 1, minWin=21, winSum=373

 8439 23:28:37.098000  TX Vref=18, minBit 0, minWin=23, winSum=384

 8440 23:28:37.101283  TX Vref=20, minBit 6, minWin=23, winSum=392

 8441 23:28:37.104379  TX Vref=22, minBit 1, minWin=23, winSum=401

 8442 23:28:37.108140  TX Vref=24, minBit 1, minWin=24, winSum=416

 8443 23:28:37.114766  TX Vref=26, minBit 1, minWin=25, winSum=420

 8444 23:28:37.118070  TX Vref=28, minBit 0, minWin=26, winSum=429

 8445 23:28:37.121308  TX Vref=30, minBit 1, minWin=25, winSum=418

 8446 23:28:37.124538  TX Vref=32, minBit 2, minWin=24, winSum=410

 8447 23:28:37.128083  TX Vref=34, minBit 2, minWin=23, winSum=403

 8448 23:28:37.134929  [TxChooseVref] Worse bit 0, Min win 26, Win sum 429, Final Vref 28

 8449 23:28:37.135349  

 8450 23:28:37.138273  Final TX Range 0 Vref 28

 8451 23:28:37.138691  

 8452 23:28:37.139019  ==

 8453 23:28:37.141684  Dram Type= 6, Freq= 0, CH_1, rank 0

 8454 23:28:37.144408  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8455 23:28:37.144826  ==

 8456 23:28:37.145153  

 8457 23:28:37.145459  

 8458 23:28:37.148201  	TX Vref Scan disable

 8459 23:28:37.154789  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8460 23:28:37.155206   == TX Byte 0 ==

 8461 23:28:37.158113  u2DelayCellOfst[0]=16 cells (5 PI)

 8462 23:28:37.160867  u2DelayCellOfst[1]=10 cells (3 PI)

 8463 23:28:37.164823  u2DelayCellOfst[2]=0 cells (0 PI)

 8464 23:28:37.167600  u2DelayCellOfst[3]=6 cells (2 PI)

 8465 23:28:37.170806  u2DelayCellOfst[4]=10 cells (3 PI)

 8466 23:28:37.175005  u2DelayCellOfst[5]=20 cells (6 PI)

 8467 23:28:37.177644  u2DelayCellOfst[6]=20 cells (6 PI)

 8468 23:28:37.178072  u2DelayCellOfst[7]=6 cells (2 PI)

 8469 23:28:37.184097  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8470 23:28:37.187354  Update DQM dly =984 (3 ,6, 24)  DQM OEN =(3 ,3)

 8471 23:28:37.187776   == TX Byte 1 ==

 8472 23:28:37.191146  u2DelayCellOfst[8]=0 cells (0 PI)

 8473 23:28:37.194091  u2DelayCellOfst[9]=3 cells (1 PI)

 8474 23:28:37.196919  u2DelayCellOfst[10]=10 cells (3 PI)

 8475 23:28:37.200776  u2DelayCellOfst[11]=3 cells (1 PI)

 8476 23:28:37.204048  u2DelayCellOfst[12]=13 cells (4 PI)

 8477 23:28:37.207541  u2DelayCellOfst[13]=16 cells (5 PI)

 8478 23:28:37.210050  u2DelayCellOfst[14]=16 cells (5 PI)

 8479 23:28:37.213436  u2DelayCellOfst[15]=16 cells (5 PI)

 8480 23:28:37.217147  Update DQ  dly =980 (3 ,6, 20)  DQ  OEN =(3 ,3)

 8481 23:28:37.223329  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8482 23:28:37.223412  DramC Write-DBI on

 8483 23:28:37.223478  ==

 8484 23:28:37.226824  Dram Type= 6, Freq= 0, CH_1, rank 0

 8485 23:28:37.230190  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8486 23:28:37.233260  ==

 8487 23:28:37.233366  

 8488 23:28:37.233441  

 8489 23:28:37.233510  	TX Vref Scan disable

 8490 23:28:37.236874   == TX Byte 0 ==

 8491 23:28:37.240349  Update DQM dly =725 (2 ,6, 21)  DQM OEN =(3 ,3)

 8492 23:28:37.243712   == TX Byte 1 ==

 8493 23:28:37.247124  Update DQM dly =724 (2 ,6, 20)  DQM OEN =(3 ,3)

 8494 23:28:37.250347  DramC Write-DBI off

 8495 23:28:37.250556  

 8496 23:28:37.250674  [DATLAT]

 8497 23:28:37.250792  Freq=1600, CH1 RK0

 8498 23:28:37.250948  

 8499 23:28:37.253691  DATLAT Default: 0xf

 8500 23:28:37.253818  0, 0xFFFF, sum = 0

 8501 23:28:37.257009  1, 0xFFFF, sum = 0

 8502 23:28:37.260476  2, 0xFFFF, sum = 0

 8503 23:28:37.260559  3, 0xFFFF, sum = 0

 8504 23:28:37.263281  4, 0xFFFF, sum = 0

 8505 23:28:37.263366  5, 0xFFFF, sum = 0

 8506 23:28:37.266783  6, 0xFFFF, sum = 0

 8507 23:28:37.266869  7, 0xFFFF, sum = 0

 8508 23:28:37.270073  8, 0xFFFF, sum = 0

 8509 23:28:37.270157  9, 0xFFFF, sum = 0

 8510 23:28:37.273723  10, 0xFFFF, sum = 0

 8511 23:28:37.273806  11, 0xFFFF, sum = 0

 8512 23:28:37.276736  12, 0xFFFF, sum = 0

 8513 23:28:37.276820  13, 0xFFFF, sum = 0

 8514 23:28:37.280622  14, 0x0, sum = 1

 8515 23:28:37.281045  15, 0x0, sum = 2

 8516 23:28:37.283732  16, 0x0, sum = 3

 8517 23:28:37.284155  17, 0x0, sum = 4

 8518 23:28:37.287174  best_step = 15

 8519 23:28:37.287729  

 8520 23:28:37.288066  ==

 8521 23:28:37.290288  Dram Type= 6, Freq= 0, CH_1, rank 0

 8522 23:28:37.293528  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8523 23:28:37.294001  ==

 8524 23:28:37.297177  RX Vref Scan: 1

 8525 23:28:37.297698  

 8526 23:28:37.298283  Set Vref Range= 24 -> 127

 8527 23:28:37.298464  

 8528 23:28:37.299598  RX Vref 24 -> 127, step: 1

 8529 23:28:37.299699  

 8530 23:28:37.303407  RX Delay 27 -> 252, step: 4

 8531 23:28:37.303489  

 8532 23:28:37.306438  Set Vref, RX VrefLevel [Byte0]: 24

 8533 23:28:37.309756                           [Byte1]: 24

 8534 23:28:37.309837  

 8535 23:28:37.313042  Set Vref, RX VrefLevel [Byte0]: 25

 8536 23:28:37.316568                           [Byte1]: 25

 8537 23:28:37.316649  

 8538 23:28:37.320173  Set Vref, RX VrefLevel [Byte0]: 26

 8539 23:28:37.323350                           [Byte1]: 26

 8540 23:28:37.326951  

 8541 23:28:37.327032  Set Vref, RX VrefLevel [Byte0]: 27

 8542 23:28:37.330629                           [Byte1]: 27

 8543 23:28:37.334456  

 8544 23:28:37.334537  Set Vref, RX VrefLevel [Byte0]: 28

 8545 23:28:37.337996                           [Byte1]: 28

 8546 23:28:37.341860  

 8547 23:28:37.341940  Set Vref, RX VrefLevel [Byte0]: 29

 8548 23:28:37.345122                           [Byte1]: 29

 8549 23:28:37.349760  

 8550 23:28:37.349840  Set Vref, RX VrefLevel [Byte0]: 30

 8551 23:28:37.352907                           [Byte1]: 30

 8552 23:28:37.357097  

 8553 23:28:37.357177  Set Vref, RX VrefLevel [Byte0]: 31

 8554 23:28:37.360824                           [Byte1]: 31

 8555 23:28:37.364754  

 8556 23:28:37.364834  Set Vref, RX VrefLevel [Byte0]: 32

 8557 23:28:37.367911                           [Byte1]: 32

 8558 23:28:37.372123  

 8559 23:28:37.372227  Set Vref, RX VrefLevel [Byte0]: 33

 8560 23:28:37.375388                           [Byte1]: 33

 8561 23:28:37.379976  

 8562 23:28:37.380057  Set Vref, RX VrefLevel [Byte0]: 34

 8563 23:28:37.383464                           [Byte1]: 34

 8564 23:28:37.387350  

 8565 23:28:37.387430  Set Vref, RX VrefLevel [Byte0]: 35

 8566 23:28:37.390887                           [Byte1]: 35

 8567 23:28:37.394806  

 8568 23:28:37.394890  Set Vref, RX VrefLevel [Byte0]: 36

 8569 23:28:37.397984                           [Byte1]: 36

 8570 23:28:37.402240  

 8571 23:28:37.402322  Set Vref, RX VrefLevel [Byte0]: 37

 8572 23:28:37.405943                           [Byte1]: 37

 8573 23:28:37.409920  

 8574 23:28:37.410000  Set Vref, RX VrefLevel [Byte0]: 38

 8575 23:28:37.413484                           [Byte1]: 38

 8576 23:28:37.417507  

 8577 23:28:37.417632  Set Vref, RX VrefLevel [Byte0]: 39

 8578 23:28:37.420910                           [Byte1]: 39

 8579 23:28:37.424942  

 8580 23:28:37.425073  Set Vref, RX VrefLevel [Byte0]: 40

 8581 23:28:37.428446                           [Byte1]: 40

 8582 23:28:37.432690  

 8583 23:28:37.432771  Set Vref, RX VrefLevel [Byte0]: 41

 8584 23:28:37.435990                           [Byte1]: 41

 8585 23:28:37.440274  

 8586 23:28:37.440388  Set Vref, RX VrefLevel [Byte0]: 42

 8587 23:28:37.443513                           [Byte1]: 42

 8588 23:28:37.447675  

 8589 23:28:37.447755  Set Vref, RX VrefLevel [Byte0]: 43

 8590 23:28:37.450962                           [Byte1]: 43

 8591 23:28:37.454895  

 8592 23:28:37.454977  Set Vref, RX VrefLevel [Byte0]: 44

 8593 23:28:37.458303                           [Byte1]: 44

 8594 23:28:37.462660  

 8595 23:28:37.462742  Set Vref, RX VrefLevel [Byte0]: 45

 8596 23:28:37.465882                           [Byte1]: 45

 8597 23:28:37.470171  

 8598 23:28:37.470254  Set Vref, RX VrefLevel [Byte0]: 46

 8599 23:28:37.473485                           [Byte1]: 46

 8600 23:28:37.477442  

 8601 23:28:37.477524  Set Vref, RX VrefLevel [Byte0]: 47

 8602 23:28:37.481006                           [Byte1]: 47

 8603 23:28:37.485038  

 8604 23:28:37.485130  Set Vref, RX VrefLevel [Byte0]: 48

 8605 23:28:37.488435                           [Byte1]: 48

 8606 23:28:37.492718  

 8607 23:28:37.492799  Set Vref, RX VrefLevel [Byte0]: 49

 8608 23:28:37.495785                           [Byte1]: 49

 8609 23:28:37.500487  

 8610 23:28:37.500568  Set Vref, RX VrefLevel [Byte0]: 50

 8611 23:28:37.503660                           [Byte1]: 50

 8612 23:28:37.507880  

 8613 23:28:37.507961  Set Vref, RX VrefLevel [Byte0]: 51

 8614 23:28:37.511180                           [Byte1]: 51

 8615 23:28:37.515487  

 8616 23:28:37.515568  Set Vref, RX VrefLevel [Byte0]: 52

 8617 23:28:37.518752                           [Byte1]: 52

 8618 23:28:37.522888  

 8619 23:28:37.522969  Set Vref, RX VrefLevel [Byte0]: 53

 8620 23:28:37.526095                           [Byte1]: 53

 8621 23:28:37.530385  

 8622 23:28:37.530465  Set Vref, RX VrefLevel [Byte0]: 54

 8623 23:28:37.533758                           [Byte1]: 54

 8624 23:28:37.538080  

 8625 23:28:37.538196  Set Vref, RX VrefLevel [Byte0]: 55

 8626 23:28:37.541503                           [Byte1]: 55

 8627 23:28:37.545621  

 8628 23:28:37.545701  Set Vref, RX VrefLevel [Byte0]: 56

 8629 23:28:37.548487                           [Byte1]: 56

 8630 23:28:37.553174  

 8631 23:28:37.553254  Set Vref, RX VrefLevel [Byte0]: 57

 8632 23:28:37.556178                           [Byte1]: 57

 8633 23:28:37.560386  

 8634 23:28:37.560466  Set Vref, RX VrefLevel [Byte0]: 58

 8635 23:28:37.563965                           [Byte1]: 58

 8636 23:28:37.568388  

 8637 23:28:37.568470  Set Vref, RX VrefLevel [Byte0]: 59

 8638 23:28:37.571650                           [Byte1]: 59

 8639 23:28:37.575494  

 8640 23:28:37.575574  Set Vref, RX VrefLevel [Byte0]: 60

 8641 23:28:37.578905                           [Byte1]: 60

 8642 23:28:37.583122  

 8643 23:28:37.583207  Set Vref, RX VrefLevel [Byte0]: 61

 8644 23:28:37.586335                           [Byte1]: 61

 8645 23:28:37.590746  

 8646 23:28:37.590826  Set Vref, RX VrefLevel [Byte0]: 62

 8647 23:28:37.593806                           [Byte1]: 62

 8648 23:28:37.598135  

 8649 23:28:37.598215  Set Vref, RX VrefLevel [Byte0]: 63

 8650 23:28:37.601407                           [Byte1]: 63

 8651 23:28:37.605557  

 8652 23:28:37.605679  Set Vref, RX VrefLevel [Byte0]: 64

 8653 23:28:37.609117                           [Byte1]: 64

 8654 23:28:37.612987  

 8655 23:28:37.613068  Set Vref, RX VrefLevel [Byte0]: 65

 8656 23:28:37.616427                           [Byte1]: 65

 8657 23:28:37.620655  

 8658 23:28:37.620735  Set Vref, RX VrefLevel [Byte0]: 66

 8659 23:28:37.623930                           [Byte1]: 66

 8660 23:28:37.628423  

 8661 23:28:37.628503  Set Vref, RX VrefLevel [Byte0]: 67

 8662 23:28:37.631748                           [Byte1]: 67

 8663 23:28:37.636106  

 8664 23:28:37.636186  Set Vref, RX VrefLevel [Byte0]: 68

 8665 23:28:37.639200                           [Byte1]: 68

 8666 23:28:37.643517  

 8667 23:28:37.643598  Set Vref, RX VrefLevel [Byte0]: 69

 8668 23:28:37.647024                           [Byte1]: 69

 8669 23:28:37.650891  

 8670 23:28:37.650971  Set Vref, RX VrefLevel [Byte0]: 70

 8671 23:28:37.654031                           [Byte1]: 70

 8672 23:28:37.658596  

 8673 23:28:37.658696  Set Vref, RX VrefLevel [Byte0]: 71

 8674 23:28:37.661899                           [Byte1]: 71

 8675 23:28:37.665778  

 8676 23:28:37.665859  Set Vref, RX VrefLevel [Byte0]: 72

 8677 23:28:37.669458                           [Byte1]: 72

 8678 23:28:37.673703  

 8679 23:28:37.673783  Set Vref, RX VrefLevel [Byte0]: 73

 8680 23:28:37.676927                           [Byte1]: 73

 8681 23:28:37.680947  

 8682 23:28:37.681027  Final RX Vref Byte 0 = 57 to rank0

 8683 23:28:37.684524  Final RX Vref Byte 1 = 57 to rank0

 8684 23:28:37.687739  Final RX Vref Byte 0 = 57 to rank1

 8685 23:28:37.691127  Final RX Vref Byte 1 = 57 to rank1==

 8686 23:28:37.694749  Dram Type= 6, Freq= 0, CH_1, rank 0

 8687 23:28:37.701220  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8688 23:28:37.701301  ==

 8689 23:28:37.701366  DQS Delay:

 8690 23:28:37.701425  DQS0 = 0, DQS1 = 0

 8691 23:28:37.704341  DQM Delay:

 8692 23:28:37.704422  DQM0 = 134, DQM1 = 131

 8693 23:28:37.707351  DQ Delay:

 8694 23:28:37.711122  DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130

 8695 23:28:37.713928  DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132

 8696 23:28:37.717280  DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124

 8697 23:28:37.720606  DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140

 8698 23:28:37.720688  

 8699 23:28:37.720751  

 8700 23:28:37.720810  

 8701 23:28:37.723926  [DramC_TX_OE_Calibration] TA2

 8702 23:28:37.727396  Original DQ_B0 (3 6) =30, OEN = 27

 8703 23:28:37.730678  Original DQ_B1 (3 6) =30, OEN = 27

 8704 23:28:37.733845  24, 0x0, End_B0=24 End_B1=24

 8705 23:28:37.733927  25, 0x0, End_B0=25 End_B1=25

 8706 23:28:37.737309  26, 0x0, End_B0=26 End_B1=26

 8707 23:28:37.740588  27, 0x0, End_B0=27 End_B1=27

 8708 23:28:37.743732  28, 0x0, End_B0=28 End_B1=28

 8709 23:28:37.747605  29, 0x0, End_B0=29 End_B1=29

 8710 23:28:37.747687  30, 0x0, End_B0=30 End_B1=30

 8711 23:28:37.750469  31, 0x4141, End_B0=30 End_B1=30

 8712 23:28:37.753840  Byte0 end_step=30  best_step=27

 8713 23:28:37.757380  Byte1 end_step=30  best_step=27

 8714 23:28:37.760923  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8715 23:28:37.764092  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8716 23:28:37.764174  

 8717 23:28:37.764237  

 8718 23:28:37.770662  [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps

 8719 23:28:37.773812  CH1 RK0: MR19=303, MR18=1422

 8720 23:28:37.780494  CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16

 8721 23:28:37.780576  

 8722 23:28:37.783940  ----->DramcWriteLeveling(PI) begin...

 8723 23:28:37.784022  ==

 8724 23:28:37.787506  Dram Type= 6, Freq= 0, CH_1, rank 1

 8725 23:28:37.790743  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8726 23:28:37.790863  ==

 8727 23:28:37.793964  Write leveling (Byte 0): 24 => 24

 8728 23:28:37.797236  Write leveling (Byte 1): 28 => 28

 8729 23:28:37.800996  DramcWriteLeveling(PI) end<-----

 8730 23:28:37.801077  

 8731 23:28:37.801140  ==

 8732 23:28:37.803734  Dram Type= 6, Freq= 0, CH_1, rank 1

 8733 23:28:37.807236  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8734 23:28:37.807317  ==

 8735 23:28:37.810822  [Gating] SW mode calibration

 8736 23:28:37.817560  [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0

 8737 23:28:37.823787  RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)

 8738 23:28:37.827599   1  4  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8739 23:28:37.830443   1  4  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8740 23:28:37.837338   1  4  8 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)

 8741 23:28:37.840328   1  4 12 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)

 8742 23:28:37.843949   1  4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8743 23:28:37.850562   1  4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8744 23:28:37.853857   1  4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8745 23:28:37.857259   1  4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8746 23:28:37.863453   1  5  0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8747 23:28:37.866868   1  5  4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)

 8748 23:28:37.870035   1  5  8 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)

 8749 23:28:37.877178   1  5 12 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)

 8750 23:28:37.880309   1  5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)

 8751 23:28:37.883529   1  5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8752 23:28:37.890183   1  5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8753 23:28:37.893564   1  5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8754 23:28:37.897026   1  6  0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8755 23:28:37.903298   1  6  4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)

 8756 23:28:37.906927   1  6  8 | B1->B0 | 4242 2323 | 0 0 | (0 0) (0 0)

 8757 23:28:37.910560   1  6 12 | B1->B0 | 4646 3939 | 0 1 | (0 0) (0 0)

 8758 23:28:37.916962   1  6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8759 23:28:37.920098   1  6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8760 23:28:37.923534   1  6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8761 23:28:37.930118   1  6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8762 23:28:37.933462   1  7  0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8763 23:28:37.936966   1  7  4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8764 23:28:37.943512   1  7  8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)

 8765 23:28:37.947016   1  7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)

 8766 23:28:37.949824   1  7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8767 23:28:37.953079   1  7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8768 23:28:37.959856   1  7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8769 23:28:37.963222   1  7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8770 23:28:37.966433   1  8  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8771 23:28:37.973046   1  8  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8772 23:28:37.976703   1  8  8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8773 23:28:37.980029   1  8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8774 23:28:37.986303   1  8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8775 23:28:37.989624   1  8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8776 23:28:37.993354   1  8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8777 23:28:37.999811   1  8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8778 23:28:38.002968   1  9  0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8779 23:28:38.006267   1  9  4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)

 8780 23:28:38.013035   1  9  8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)

 8781 23:28:38.016495   1  9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)

 8782 23:28:38.019527  Total UI for P1: 0, mck2ui 16

 8783 23:28:38.022699  best dqsien dly found for B1: ( 1,  9,  8)

 8784 23:28:38.026319   1  9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)

 8785 23:28:38.029449  Total UI for P1: 0, mck2ui 16

 8786 23:28:38.033196  best dqsien dly found for B0: ( 1,  9, 10)

 8787 23:28:38.036205  best DQS0 dly(MCK, UI, PI) = (1, 9, 10)

 8788 23:28:38.039889  best DQS1 dly(MCK, UI, PI) = (1, 9, 8)

 8789 23:28:38.039970  

 8790 23:28:38.046911  best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)

 8791 23:28:38.049986  best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)

 8792 23:28:38.050067  [Gating] SW calibration Done

 8793 23:28:38.052826  ==

 8794 23:28:38.056082  Dram Type= 6, Freq= 0, CH_1, rank 1

 8795 23:28:38.059553  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8796 23:28:38.059634  ==

 8797 23:28:38.059699  RX Vref Scan: 0

 8798 23:28:38.059758  

 8799 23:28:38.062790  RX Vref 0 -> 0, step: 1

 8800 23:28:38.062870  

 8801 23:28:38.066051  RX Delay 0 -> 252, step: 8

 8802 23:28:38.069487  iDelay=208, Bit 0, Center 139 (88 ~ 191) 104

 8803 23:28:38.072948  iDelay=208, Bit 1, Center 135 (80 ~ 191) 112

 8804 23:28:38.076028  iDelay=208, Bit 2, Center 119 (64 ~ 175) 112

 8805 23:28:38.082845  iDelay=208, Bit 3, Center 131 (80 ~ 183) 104

 8806 23:28:38.086293  iDelay=208, Bit 4, Center 131 (80 ~ 183) 104

 8807 23:28:38.089768  iDelay=208, Bit 5, Center 151 (96 ~ 207) 112

 8808 23:28:38.092568  iDelay=208, Bit 6, Center 143 (88 ~ 199) 112

 8809 23:28:38.095924  iDelay=208, Bit 7, Center 135 (80 ~ 191) 112

 8810 23:28:38.102560  iDelay=208, Bit 8, Center 119 (64 ~ 175) 112

 8811 23:28:38.106106  iDelay=208, Bit 9, Center 119 (64 ~ 175) 112

 8812 23:28:38.109381  iDelay=208, Bit 10, Center 135 (80 ~ 191) 112

 8813 23:28:38.112632  iDelay=208, Bit 11, Center 127 (72 ~ 183) 112

 8814 23:28:38.118889  iDelay=208, Bit 12, Center 143 (88 ~ 199) 112

 8815 23:28:38.122447  iDelay=208, Bit 13, Center 143 (88 ~ 199) 112

 8816 23:28:38.125750  iDelay=208, Bit 14, Center 139 (88 ~ 191) 104

 8817 23:28:38.128953  iDelay=208, Bit 15, Center 143 (88 ~ 199) 112

 8818 23:28:38.129034  ==

 8819 23:28:38.132377  Dram Type= 6, Freq= 0, CH_1, rank 1

 8820 23:28:38.138766  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8821 23:28:38.138874  ==

 8822 23:28:38.138967  DQS Delay:

 8823 23:28:38.139056  DQS0 = 0, DQS1 = 0

 8824 23:28:38.142230  DQM Delay:

 8825 23:28:38.142311  DQM0 = 135, DQM1 = 133

 8826 23:28:38.145857  DQ Delay:

 8827 23:28:38.148598  DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131

 8828 23:28:38.151977  DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135

 8829 23:28:38.155919  DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127

 8830 23:28:38.158914  DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143

 8831 23:28:38.158994  

 8832 23:28:38.159058  

 8833 23:28:38.159118  ==

 8834 23:28:38.161916  Dram Type= 6, Freq= 0, CH_1, rank 1

 8835 23:28:38.165554  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8836 23:28:38.168779  ==

 8837 23:28:38.168861  

 8838 23:28:38.168925  

 8839 23:28:38.168984  	TX Vref Scan disable

 8840 23:28:38.171964   == TX Byte 0 ==

 8841 23:28:38.175775  Update DQ  dly =981 (3 ,6, 21)  DQ  OEN =(3 ,3)

 8842 23:28:38.179382  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8843 23:28:38.181856   == TX Byte 1 ==

 8844 23:28:38.185170  Update DQ  dly =982 (3 ,6, 22)  DQ  OEN =(3 ,3)

 8845 23:28:38.188800  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8846 23:28:38.188880  ==

 8847 23:28:38.192264  Dram Type= 6, Freq= 0, CH_1, rank 1

 8848 23:28:38.198633  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8849 23:28:38.198715  ==

 8850 23:28:38.211537  

 8851 23:28:38.214802  TX Vref early break, caculate TX vref

 8852 23:28:38.218140  TX Vref=16, minBit 0, minWin=22, winSum=381

 8853 23:28:38.221709  TX Vref=18, minBit 0, minWin=22, winSum=386

 8854 23:28:38.225012  TX Vref=20, minBit 0, minWin=24, winSum=401

 8855 23:28:38.228022  TX Vref=22, minBit 0, minWin=24, winSum=407

 8856 23:28:38.231834  TX Vref=24, minBit 0, minWin=25, winSum=414

 8857 23:28:38.238508  TX Vref=26, minBit 0, minWin=25, winSum=421

 8858 23:28:38.241936  TX Vref=28, minBit 0, minWin=25, winSum=424

 8859 23:28:38.245020  TX Vref=30, minBit 0, minWin=24, winSum=419

 8860 23:28:38.248280  TX Vref=32, minBit 6, minWin=23, winSum=410

 8861 23:28:38.251522  TX Vref=34, minBit 0, minWin=24, winSum=404

 8862 23:28:38.254702  TX Vref=36, minBit 0, minWin=23, winSum=394

 8863 23:28:38.261396  [TxChooseVref] Worse bit 0, Min win 25, Win sum 424, Final Vref 28

 8864 23:28:38.261479  

 8865 23:28:38.264562  Final TX Range 0 Vref 28

 8866 23:28:38.264642  

 8867 23:28:38.264705  ==

 8868 23:28:38.268069  Dram Type= 6, Freq= 0, CH_1, rank 1

 8869 23:28:38.271558  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8870 23:28:38.271639  ==

 8871 23:28:38.271749  

 8872 23:28:38.271809  

 8873 23:28:38.274719  	TX Vref Scan disable

 8874 23:28:38.281517  [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps

 8875 23:28:38.281662   == TX Byte 0 ==

 8876 23:28:38.284480  u2DelayCellOfst[0]=20 cells (6 PI)

 8877 23:28:38.287880  u2DelayCellOfst[1]=16 cells (5 PI)

 8878 23:28:38.291464  u2DelayCellOfst[2]=0 cells (0 PI)

 8879 23:28:38.294884  u2DelayCellOfst[3]=6 cells (2 PI)

 8880 23:28:38.298167  u2DelayCellOfst[4]=6 cells (2 PI)

 8881 23:28:38.301588  u2DelayCellOfst[5]=20 cells (6 PI)

 8882 23:28:38.304709  u2DelayCellOfst[6]=20 cells (6 PI)

 8883 23:28:38.308269  u2DelayCellOfst[7]=6 cells (2 PI)

 8884 23:28:38.311134  Update DQ  dly =978 (3 ,6, 18)  DQ  OEN =(3 ,3)

 8885 23:28:38.315095  Update DQM dly =981 (3 ,6, 21)  DQM OEN =(3 ,3)

 8886 23:28:38.317928   == TX Byte 1 ==

 8887 23:28:38.321077  u2DelayCellOfst[8]=0 cells (0 PI)

 8888 23:28:38.321184  u2DelayCellOfst[9]=6 cells (2 PI)

 8889 23:28:38.324639  u2DelayCellOfst[10]=13 cells (4 PI)

 8890 23:28:38.328385  u2DelayCellOfst[11]=6 cells (2 PI)

 8891 23:28:38.331356  u2DelayCellOfst[12]=16 cells (5 PI)

 8892 23:28:38.334477  u2DelayCellOfst[13]=16 cells (5 PI)

 8893 23:28:38.337709  u2DelayCellOfst[14]=20 cells (6 PI)

 8894 23:28:38.341213  u2DelayCellOfst[15]=20 cells (6 PI)

 8895 23:28:38.344500  Update DQ  dly =979 (3 ,6, 19)  DQ  OEN =(3 ,3)

 8896 23:28:38.351127  Update DQM dly =982 (3 ,6, 22)  DQM OEN =(3 ,3)

 8897 23:28:38.351208  DramC Write-DBI on

 8898 23:28:38.351271  ==

 8899 23:28:38.354482  Dram Type= 6, Freq= 0, CH_1, rank 1

 8900 23:28:38.361456  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8901 23:28:38.361539  ==

 8902 23:28:38.361631  

 8903 23:28:38.361702  

 8904 23:28:38.361763  	TX Vref Scan disable

 8905 23:28:38.364873   == TX Byte 0 ==

 8906 23:28:38.368238  Update DQM dly =722 (2 ,6, 18)  DQM OEN =(3 ,3)

 8907 23:28:38.371131   == TX Byte 1 ==

 8908 23:28:38.374811  Update DQM dly =723 (2 ,6, 19)  DQM OEN =(3 ,3)

 8909 23:28:38.377835  DramC Write-DBI off

 8910 23:28:38.377915  

 8911 23:28:38.377979  [DATLAT]

 8912 23:28:38.378039  Freq=1600, CH1 RK1

 8913 23:28:38.378097  

 8914 23:28:38.381356  DATLAT Default: 0xf

 8915 23:28:38.384809  0, 0xFFFF, sum = 0

 8916 23:28:38.384892  1, 0xFFFF, sum = 0

 8917 23:28:38.387996  2, 0xFFFF, sum = 0

 8918 23:28:38.388079  3, 0xFFFF, sum = 0

 8919 23:28:38.391108  4, 0xFFFF, sum = 0

 8920 23:28:38.391191  5, 0xFFFF, sum = 0

 8921 23:28:38.394815  6, 0xFFFF, sum = 0

 8922 23:28:38.394897  7, 0xFFFF, sum = 0

 8923 23:28:38.397920  8, 0xFFFF, sum = 0

 8924 23:28:38.398003  9, 0xFFFF, sum = 0

 8925 23:28:38.401316  10, 0xFFFF, sum = 0

 8926 23:28:38.401398  11, 0xFFFF, sum = 0

 8927 23:28:38.404489  12, 0xFFFF, sum = 0

 8928 23:28:38.404597  13, 0xFFFF, sum = 0

 8929 23:28:38.407723  14, 0x0, sum = 1

 8930 23:28:38.407804  15, 0x0, sum = 2

 8931 23:28:38.411192  16, 0x0, sum = 3

 8932 23:28:38.411274  17, 0x0, sum = 4

 8933 23:28:38.414679  best_step = 15

 8934 23:28:38.414759  

 8935 23:28:38.414824  ==

 8936 23:28:38.417985  Dram Type= 6, Freq= 0, CH_1, rank 1

 8937 23:28:38.421233  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8938 23:28:38.421315  ==

 8939 23:28:38.424294  RX Vref Scan: 0

 8940 23:28:38.424375  

 8941 23:28:38.424439  RX Vref 0 -> 0, step: 1

 8942 23:28:38.424498  

 8943 23:28:38.427794  RX Delay 19 -> 252, step: 4

 8944 23:28:38.431166  iDelay=195, Bit 0, Center 138 (91 ~ 186) 96

 8945 23:28:38.437732  iDelay=195, Bit 1, Center 128 (79 ~ 178) 100

 8946 23:28:38.440904  iDelay=195, Bit 2, Center 122 (71 ~ 174) 104

 8947 23:28:38.444862  iDelay=195, Bit 3, Center 130 (83 ~ 178) 96

 8948 23:28:38.447633  iDelay=195, Bit 4, Center 130 (83 ~ 178) 96

 8949 23:28:38.451420  iDelay=195, Bit 5, Center 146 (99 ~ 194) 96

 8950 23:28:38.457717  iDelay=195, Bit 6, Center 144 (95 ~ 194) 100

 8951 23:28:38.461239  iDelay=195, Bit 7, Center 134 (83 ~ 186) 104

 8952 23:28:38.464778  iDelay=195, Bit 8, Center 118 (67 ~ 170) 104

 8953 23:28:38.467773  iDelay=195, Bit 9, Center 118 (67 ~ 170) 104

 8954 23:28:38.470987  iDelay=195, Bit 10, Center 132 (83 ~ 182) 100

 8955 23:28:38.477756  iDelay=195, Bit 11, Center 124 (71 ~ 178) 108

 8956 23:28:38.480942  iDelay=195, Bit 12, Center 140 (87 ~ 194) 108

 8957 23:28:38.484214  iDelay=195, Bit 13, Center 138 (87 ~ 190) 104

 8958 23:28:38.487552  iDelay=195, Bit 14, Center 136 (87 ~ 186) 100

 8959 23:28:38.490852  iDelay=195, Bit 15, Center 140 (91 ~ 190) 100

 8960 23:28:38.494214  ==

 8961 23:28:38.494295  Dram Type= 6, Freq= 0, CH_1, rank 1

 8962 23:28:38.500657  fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1

 8963 23:28:38.500741  ==

 8964 23:28:38.500829  DQS Delay:

 8965 23:28:38.504389  DQS0 = 0, DQS1 = 0

 8966 23:28:38.504471  DQM Delay:

 8967 23:28:38.507848  DQM0 = 134, DQM1 = 130

 8968 23:28:38.507930  DQ Delay:

 8969 23:28:38.510960  DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130

 8970 23:28:38.514131  DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134

 8971 23:28:38.517705  DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124

 8972 23:28:38.520793  DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140

 8973 23:28:38.520875  

 8974 23:28:38.520938  

 8975 23:28:38.521000  

 8976 23:28:38.523964  [DramC_TX_OE_Calibration] TA2

 8977 23:28:38.527230  Original DQ_B0 (3 6) =30, OEN = 27

 8978 23:28:38.530635  Original DQ_B1 (3 6) =30, OEN = 27

 8979 23:28:38.534135  24, 0x0, End_B0=24 End_B1=24

 8980 23:28:38.537370  25, 0x0, End_B0=25 End_B1=25

 8981 23:28:38.537452  26, 0x0, End_B0=26 End_B1=26

 8982 23:28:38.540938  27, 0x0, End_B0=27 End_B1=27

 8983 23:28:38.544052  28, 0x0, End_B0=28 End_B1=28

 8984 23:28:38.547171  29, 0x0, End_B0=29 End_B1=29

 8985 23:28:38.550408  30, 0x0, End_B0=30 End_B1=30

 8986 23:28:38.550491  31, 0x4141, End_B0=30 End_B1=30

 8987 23:28:38.553759  Byte0 end_step=30  best_step=27

 8988 23:28:38.557103  Byte1 end_step=30  best_step=27

 8989 23:28:38.560528  Byte0 TX OE(2T, 0.5T) = (3, 3)

 8990 23:28:38.563838  Byte1 TX OE(2T, 0.5T) = (3, 3)

 8991 23:28:38.563919  

 8992 23:28:38.563982  

 8993 23:28:38.570165  [DQSOSCAuto] RK1, (LSB)MR18= 0x2207, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps

 8994 23:28:38.573542  CH1 RK1: MR19=303, MR18=2207

 8995 23:28:38.580391  CH1_RK1: MR19=0x303, MR18=0x2207, DQSOSC=392, MR23=63, INC=24, DEC=16

 8996 23:28:38.583772  [RxdqsGatingPostProcess] freq 1600

 8997 23:28:38.590289  ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3

 8998 23:28:38.590382  best DQS0 dly(2T, 0.5T) = (1, 1)

 8999 23:28:38.593623  best DQS1 dly(2T, 0.5T) = (1, 1)

 9000 23:28:38.596811  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9001 23:28:38.600101  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9002 23:28:38.603334  best DQS0 dly(2T, 0.5T) = (1, 1)

 9003 23:28:38.606666  best DQS1 dly(2T, 0.5T) = (1, 1)

 9004 23:28:38.610140  best DQS0 P1 dly(2T, 0.5T) = (1, 5)

 9005 23:28:38.613310  best DQS1 P1 dly(2T, 0.5T) = (1, 5)

 9006 23:28:38.616745  Pre-setting of DQS Precalculation

 9007 23:28:38.619841  [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15

 9008 23:28:38.629962  sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0

 9009 23:28:38.636699  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9010 23:28:38.636781  

 9011 23:28:38.636845  

 9012 23:28:38.639931  [Calibration Summary] 3200 Mbps

 9013 23:28:38.640013  CH 0, Rank 0

 9014 23:28:38.643520  SW Impedance     : PASS

 9015 23:28:38.643602  DUTY Scan        : NO K

 9016 23:28:38.646823  ZQ Calibration   : PASS

 9017 23:28:38.649919  Jitter Meter     : NO K

 9018 23:28:38.650001  CBT Training     : PASS

 9019 23:28:38.653444  Write leveling   : PASS

 9020 23:28:38.656786  RX DQS gating    : PASS

 9021 23:28:38.656869  RX DQ/DQS(RDDQC) : PASS

 9022 23:28:38.659888  TX DQ/DQS        : PASS

 9023 23:28:38.663384  RX DATLAT        : PASS

 9024 23:28:38.663466  RX DQ/DQS(Engine): PASS

 9025 23:28:38.666645  TX OE            : PASS

 9026 23:28:38.666727  All Pass.

 9027 23:28:38.666792  

 9028 23:28:38.666851  CH 0, Rank 1

 9029 23:28:38.669901  SW Impedance     : PASS

 9030 23:28:38.673450  DUTY Scan        : NO K

 9031 23:28:38.673558  ZQ Calibration   : PASS

 9032 23:28:38.677061  Jitter Meter     : NO K

 9033 23:28:38.680163  CBT Training     : PASS

 9034 23:28:38.680245  Write leveling   : PASS

 9035 23:28:38.683596  RX DQS gating    : PASS

 9036 23:28:38.687104  RX DQ/DQS(RDDQC) : PASS

 9037 23:28:38.687186  TX DQ/DQS        : PASS

 9038 23:28:38.689898  RX DATLAT        : PASS

 9039 23:28:38.693213  RX DQ/DQS(Engine): PASS

 9040 23:28:38.693295  TX OE            : PASS

 9041 23:28:38.696796  All Pass.

 9042 23:28:38.696933  

 9043 23:28:38.697001  CH 1, Rank 0

 9044 23:28:38.700043  SW Impedance     : PASS

 9045 23:28:38.700125  DUTY Scan        : NO K

 9046 23:28:38.703348  ZQ Calibration   : PASS

 9047 23:28:38.706405  Jitter Meter     : NO K

 9048 23:28:38.706486  CBT Training     : PASS

 9049 23:28:38.709974  Write leveling   : PASS

 9050 23:28:38.710055  RX DQS gating    : PASS

 9051 23:28:38.712991  RX DQ/DQS(RDDQC) : PASS

 9052 23:28:38.716288  TX DQ/DQS        : PASS

 9053 23:28:38.716371  RX DATLAT        : PASS

 9054 23:28:38.720014  RX DQ/DQS(Engine): PASS

 9055 23:28:38.723210  TX OE            : PASS

 9056 23:28:38.723292  All Pass.

 9057 23:28:38.723357  

 9058 23:28:38.723417  CH 1, Rank 1

 9059 23:28:38.726252  SW Impedance     : PASS

 9060 23:28:38.729811  DUTY Scan        : NO K

 9061 23:28:38.729892  ZQ Calibration   : PASS

 9062 23:28:38.732951  Jitter Meter     : NO K

 9063 23:28:38.736238  CBT Training     : PASS

 9064 23:28:38.736319  Write leveling   : PASS

 9065 23:28:38.739854  RX DQS gating    : PASS

 9066 23:28:38.743218  RX DQ/DQS(RDDQC) : PASS

 9067 23:28:38.743300  TX DQ/DQS        : PASS

 9068 23:28:38.746396  RX DATLAT        : PASS

 9069 23:28:38.749638  RX DQ/DQS(Engine): PASS

 9070 23:28:38.749720  TX OE            : PASS

 9071 23:28:38.753124  All Pass.

 9072 23:28:38.753205  

 9073 23:28:38.753270  DramC Write-DBI on

 9074 23:28:38.756366  	PER_BANK_REFRESH: Hybrid Mode

 9075 23:28:38.756448  TX_TRACKING: ON

 9076 23:28:38.766191  [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0

 9077 23:28:38.772923  sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1

 9078 23:28:38.783342  calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464

 9079 23:28:38.786292  [FAST_K] Save calibration result to emmc

 9080 23:28:38.789953  sync common calibartion params.

 9081 23:28:38.790077  sync cbt_mode0:1, 1:1

 9082 23:28:38.793049  dram_init: ddr_geometry: 2

 9083 23:28:38.796320  dram_init: ddr_geometry: 2

 9084 23:28:38.796401  dram_init: ddr_geometry: 2

 9085 23:28:38.799514  0:dram_rank_size:100000000

 9086 23:28:38.802548  1:dram_rank_size:100000000

 9087 23:28:38.809254  sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000

 9088 23:28:38.809363  DFS_SHUFFLE_HW_MODE: ON

 9089 23:28:38.813076  dramc_set_vcore_voltage set vcore to 725000

 9090 23:28:38.816165  Read voltage for 1600, 0

 9091 23:28:38.816247  Vio18 = 0

 9092 23:28:38.819628  Vcore = 725000

 9093 23:28:38.819710  Vdram = 0

 9094 23:28:38.819775  Vddq = 0

 9095 23:28:38.822298  Vmddr = 0

 9096 23:28:38.822380  switch to 3200 Mbps bootup

 9097 23:28:38.826022  [DramcRunTimeConfig]

 9098 23:28:38.826105  PHYPLL

 9099 23:28:38.828953  DPM_CONTROL_AFTERK: ON

 9100 23:28:38.829034  PER_BANK_REFRESH: ON

 9101 23:28:38.832238  REFRESH_OVERHEAD_REDUCTION: ON

 9102 23:28:38.835594  CMD_PICG_NEW_MODE: OFF

 9103 23:28:38.835676  XRTWTW_NEW_MODE: ON

 9104 23:28:38.838900  XRTRTR_NEW_MODE: ON

 9105 23:28:38.838982  TX_TRACKING: ON

 9106 23:28:38.842497  RDSEL_TRACKING: OFF

 9107 23:28:38.845955  DQS Precalculation for DVFS: ON

 9108 23:28:38.846037  RX_TRACKING: OFF

 9109 23:28:38.849130  HW_GATING DBG: ON

 9110 23:28:38.849211  ZQCS_ENABLE_LP4: ON

 9111 23:28:38.852460  RX_PICG_NEW_MODE: ON

 9112 23:28:38.852541  TX_PICG_NEW_MODE: ON

 9113 23:28:38.855568  ENABLE_RX_DCM_DPHY: ON

 9114 23:28:38.858697  LOWPOWER_GOLDEN_SETTINGS(DCM): ON

 9115 23:28:38.861973  DUMMY_READ_FOR_TRACKING: OFF

 9116 23:28:38.862054  !!! SPM_CONTROL_AFTERK: OFF

 9117 23:28:38.865541  !!! SPM could not control APHY

 9118 23:28:38.868758  IMPEDANCE_TRACKING: ON

 9119 23:28:38.868840  TEMP_SENSOR: ON

 9120 23:28:38.872299  HW_SAVE_FOR_SR: OFF

 9121 23:28:38.875481  CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF

 9122 23:28:38.878631  PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF

 9123 23:28:38.882326  Read ODT Tracking: ON

 9124 23:28:38.882408  Refresh Rate DeBounce: ON

 9125 23:28:38.885573  DFS_NO_QUEUE_FLUSH: ON

 9126 23:28:38.888469  DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF

 9127 23:28:38.892185  ENABLE_DFS_RUNTIME_MRW: OFF

 9128 23:28:38.892268  DDR_RESERVE_NEW_MODE: ON

 9129 23:28:38.895582  MR_CBT_SWITCH_FREQ: ON

 9130 23:28:38.898794  =========================

 9131 23:28:38.916384  [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)

 9132 23:28:38.919509  dram_init: ddr_geometry: 2

 9133 23:28:38.937474  [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)

 9134 23:28:38.940791  dram_init: dram init end (result: 0)

 9135 23:28:38.947331  DRAM-K: Full calibration passed in 24460 msecs

 9136 23:28:38.950753  MRC: failed to locate region type 0.

 9137 23:28:38.950835  DRAM rank0 size:0x100000000,

 9138 23:28:38.954181  DRAM rank1 size=0x100000000

 9139 23:28:38.963920  Mapping address range [0x40000000:0x240000000) as     cacheable | read-write | non-secure | normal

 9140 23:28:38.970834  Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal

 9141 23:28:38.977771  Backing address range [0x40000000:0x80000000) with new page table @0x00112000

 9142 23:28:38.984034  Backing address range [0x40000000:0x40200000) with new page table @0x00113000

 9143 23:28:38.987609  DRAM rank0 size:0x100000000,

 9144 23:28:38.990399  DRAM rank1 size=0x100000000

 9145 23:28:38.990481  CBMEM:

 9146 23:28:38.993953  IMD: root @ 0xfffff000 254 entries.

 9147 23:28:38.997664  IMD: root @ 0xffffec00 62 entries.

 9148 23:28:39.000501  FMAP: area RO_VPD found @ 3f8000 (32768 bytes)

 9149 23:28:39.004179  WARNING: RO_VPD is uninitialized or empty.

 9150 23:28:39.011087  FMAP: area RW_VPD found @ 577000 (16384 bytes)

 9151 23:28:39.017764  CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80

 9152 23:28:39.030622  read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps

 9153 23:28:39.041718  BS: romstage times (exec / console): total (unknown) / 23993 ms

 9154 23:28:39.041802  

 9155 23:28:39.041866  

 9156 23:28:39.051694  coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...

 9157 23:28:39.054949  ARM64: Exception handlers installed.

 9158 23:28:39.058307  ARM64: Testing exception

 9159 23:28:39.061868  ARM64: Done test exception

 9160 23:28:39.061950  Enumerating buses...

 9161 23:28:39.065236  Show all devs... Before device enumeration.

 9162 23:28:39.068522  Root Device: enabled 1

 9163 23:28:39.071585  CPU_CLUSTER: 0: enabled 1

 9164 23:28:39.071667  CPU: 00: enabled 1

 9165 23:28:39.074686  Compare with tree...

 9166 23:28:39.074768  Root Device: enabled 1

 9167 23:28:39.078047   CPU_CLUSTER: 0: enabled 1

 9168 23:28:39.081770    CPU: 00: enabled 1

 9169 23:28:39.081877  Root Device scanning...

 9170 23:28:39.085190  scan_static_bus for Root Device

 9171 23:28:39.088022  CPU_CLUSTER: 0 enabled

 9172 23:28:39.091278  scan_static_bus for Root Device done

 9173 23:28:39.094873  scan_bus: bus Root Device finished in 8 msecs

 9174 23:28:39.094955  done

 9175 23:28:39.101358  BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms

 9176 23:28:39.104531  FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)

 9177 23:28:39.111252  SF: Detected 00 0000 with sector size 0x1000, total 0x800000

 9178 23:28:39.114801  BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms

 9179 23:28:39.118103  Allocating resources...

 9180 23:28:39.121430  Reading resources...

 9181 23:28:39.124918  Root Device read_resources bus 0 link: 0

 9182 23:28:39.124999  DRAM rank0 size:0x100000000,

 9183 23:28:39.128394  DRAM rank1 size=0x100000000

 9184 23:28:39.131627  CPU_CLUSTER: 0 read_resources bus 0 link: 0

 9185 23:28:39.134798  CPU: 00 missing read_resources

 9186 23:28:39.137999  CPU_CLUSTER: 0 read_resources bus 0 link: 0 done

 9187 23:28:39.144811  Root Device read_resources bus 0 link: 0 done

 9188 23:28:39.144920  Done reading resources.

 9189 23:28:39.151259  Show resources in subtree (Root Device)...After reading.

 9190 23:28:39.154243   Root Device child on link 0 CPU_CLUSTER: 0

 9191 23:28:39.158038    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9192 23:28:39.167594    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9193 23:28:39.167677     CPU: 00

 9194 23:28:39.170955  Root Device assign_resources, bus 0 link: 0

 9195 23:28:39.174399  CPU_CLUSTER: 0 missing set_resources

 9196 23:28:39.181080  Root Device assign_resources, bus 0 link: 0 done

 9197 23:28:39.181163  Done setting resources.

 9198 23:28:39.187900  Show resources in subtree (Root Device)...After assigning values.

 9199 23:28:39.191187   Root Device child on link 0 CPU_CLUSTER: 0

 9200 23:28:39.194072    CPU_CLUSTER: 0 child on link 0 CPU: 00

 9201 23:28:39.204117    CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0

 9202 23:28:39.204200     CPU: 00

 9203 23:28:39.207229  Done allocating resources.

 9204 23:28:39.210669  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms

 9205 23:28:39.214440  Enabling resources...

 9206 23:28:39.214521  done.

 9207 23:28:39.220527  BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms

 9208 23:28:39.220609  Initializing devices...

 9209 23:28:39.224246  Root Device init

 9210 23:28:39.224327  init hardware done!

 9211 23:28:39.227651  0x00000018: ctrlr->caps

 9212 23:28:39.231107  52.000 MHz: ctrlr->f_max

 9213 23:28:39.231191  0.400 MHz: ctrlr->f_min

 9214 23:28:39.234023  0x40ff8080: ctrlr->voltages

 9215 23:28:39.234106  sclk: 390625

 9216 23:28:39.237282  Bus Width = 1

 9217 23:28:39.237362  sclk: 390625

 9218 23:28:39.240900  Bus Width = 1

 9219 23:28:39.240981  Early init status = 3

 9220 23:28:39.247407  out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00 

 9221 23:28:39.250728  in-header: 03 fc 00 00 01 00 00 00 

 9222 23:28:39.250836  in-data: 00 

 9223 23:28:39.257263  out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01 

 9224 23:28:39.261166  in-header: 03 fd 00 00 00 00 00 00 

 9225 23:28:39.264603  in-data: 

 9226 23:28:39.268012  out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00 

 9227 23:28:39.271903  in-header: 03 fc 00 00 01 00 00 00 

 9228 23:28:39.275049  in-data: 00 

 9229 23:28:39.278634  out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01 

 9230 23:28:39.284205  in-header: 03 fd 00 00 00 00 00 00 

 9231 23:28:39.287435  in-data: 

 9232 23:28:39.290891  [SSUSB] Setting up USB HOST controller...

 9233 23:28:39.294047  [SSUSB] u3phy_ports_enable u2p:1, u3p:1

 9234 23:28:39.297536  [SSUSB] phy power-on done.

 9235 23:28:39.300791  FMAP: area COREBOOT found @ 21000 (4014080 bytes)

 9236 23:28:39.307603  CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c

 9237 23:28:39.310711  mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)

 9238 23:28:39.317405  CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c

 9239 23:28:39.324189  read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps

 9240 23:28:39.330538  mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)

 9241 23:28:39.337239  CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204

 9242 23:28:39.344028  read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps

 9243 23:28:39.347480  SPM: binary array size = 0x9dc

 9244 23:28:39.350858  SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)

 9245 23:28:39.357153  spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18

 9246 23:28:39.363652  mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)

 9247 23:28:39.367253  SPM: spm_init done in 34 msecs, spm pc = 0x3f4

 9248 23:28:39.373471  configure_display: Starting display init

 9249 23:28:39.407273  anx7625_power_on_init: Init interface.

 9250 23:28:39.410734  anx7625_disable_pd_protocol: Disabled PD feature.

 9251 23:28:39.414208  anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.

 9252 23:28:39.441951  anx7625_start_dp_work: Secure OCM version=00

 9253 23:28:39.445309  anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91

 9254 23:28:39.460052  sp_tx_get_edid_block: EDID Block = 1

 9255 23:28:39.562849  Extracted contents:

 9256 23:28:39.566016  header:          00 ff ff ff ff ff ff 00

 9257 23:28:39.569319  serial number:   26 cf 7d 05 00 00 00 00 00 1e

 9258 23:28:39.572641  version:         01 04

 9259 23:28:39.575994  basic params:    95 1f 11 78 0a

 9260 23:28:39.579163  chroma info:     76 90 94 55 54 90 27 21 50 54

 9261 23:28:39.582523  established:     00 00 00

 9262 23:28:39.589045  standard:        01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01

 9263 23:28:39.592482  descriptor 1:    38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19

 9264 23:28:39.598974  descriptor 2:    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

 9265 23:28:39.605333  descriptor 3:    00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20

 9266 23:28:39.612205  descriptor 4:    00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a

 9267 23:28:39.615689  extensions:      00

 9268 23:28:39.615771  checksum:        fb

 9269 23:28:39.615836  

 9270 23:28:39.618996  Manufacturer: IVO Model 57d Serial Number 0

 9271 23:28:39.622083  Made week 0 of 2020

 9272 23:28:39.622165  EDID version: 1.4

 9273 23:28:39.625746  Digital display

 9274 23:28:39.628647  6 bits per primary color channel

 9275 23:28:39.628730  DisplayPort interface

 9276 23:28:39.631932  Maximum image size: 31 cm x 17 cm

 9277 23:28:39.635347  Gamma: 220%

 9278 23:28:39.635428  Check DPMS levels

 9279 23:28:39.638893  Supported color formats: RGB 4:4:4, YCrCb 4:2:2

 9280 23:28:39.645519  First detailed timing is preferred timing

 9281 23:28:39.645657  Established timings supported:

 9282 23:28:39.648645  Standard timings supported:

 9283 23:28:39.651987  Detailed timings

 9284 23:28:39.655201  Hex of detail: 383680a07038204018303c0035ae10000019

 9285 23:28:39.658381  Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm

 9286 23:28:39.665162                 0780 0798 07c8 0820 hborder 0

 9287 23:28:39.668482                 0438 043b 0447 0458 vborder 0

 9288 23:28:39.671788                 -hsync -vsync

 9289 23:28:39.671871  Did detailed timing

 9290 23:28:39.678722  Hex of detail: 000000000000000000000000000000000000

 9291 23:28:39.678805  Manufacturer-specified data, tag 0

 9292 23:28:39.685226  Hex of detail: 000000fe00496e666f566973696f6e0a2020

 9293 23:28:39.688481  ASCII string: InfoVision

 9294 23:28:39.691824  Hex of detail: 000000fe00523134304e574635205248200a

 9295 23:28:39.695374  ASCII string: R140NWF5 RH 

 9296 23:28:39.695475  Checksum

 9297 23:28:39.698632  Checksum: 0xfb (valid)

 9298 23:28:39.701872  configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz

 9299 23:28:39.705351  DSI data_rate: 832800000 bps

 9300 23:28:39.711700  anx7625_parse_edid: detected IVO panel, use k value 0x3b

 9301 23:28:39.715114  anx7625_parse_edid: pixelclock(138800).

 9302 23:28:39.718627   hactive(1920), hsync(48), hfp(24), hbp(88)

 9303 23:28:39.722007   vactive(1080), vsync(12), vfp(3), vbp(17)

 9304 23:28:39.725359  anx7625_dsi_config: config dsi.

 9305 23:28:39.731872  anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).

 9306 23:28:39.745018  anx7625_dsi_config: success to config DSI

 9307 23:28:39.748151  anx7625_dp_start: MIPI phy setup OK.

 9308 23:28:39.751680  mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4

 9309 23:28:39.755061  mtk_ddp_mode_set invalid vrefresh 60

 9310 23:28:39.757856  main_disp_path_setup

 9311 23:28:39.758373  ovl_layer_smi_id_en

 9312 23:28:39.761663  ovl_layer_smi_id_en

 9313 23:28:39.762031  ccorr_config

 9314 23:28:39.762340  aal_config

 9315 23:28:39.764498  gamma_config

 9316 23:28:39.764908  postmask_config

 9317 23:28:39.767984  dither_config

 9318 23:28:39.771448  framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32

 9319 23:28:39.778185                     x_res x y_res: 1920 x 1080, size: 8294400 at 0x0

 9320 23:28:39.781162  Root Device init finished in 554 msecs

 9321 23:28:39.785387  CPU_CLUSTER: 0 init

 9322 23:28:39.792092  Mapping address range [0x00200000:0x00300000) as     cacheable | read-write |     secure | device

 9323 23:28:39.794794  INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff

 9324 23:28:39.798186  APU_MBOX 0x190000b0 = 0x10001

 9325 23:28:39.801891  APU_MBOX 0x190001b0 = 0x10001

 9326 23:28:39.804562  APU_MBOX 0x190005b0 = 0x10001

 9327 23:28:39.807993  APU_MBOX 0x190006b0 = 0x10001

 9328 23:28:39.811407  CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c

 9329 23:28:39.824017  read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps

 9330 23:28:39.836129  mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)

 9331 23:28:39.842827  CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0

 9332 23:28:39.854623  read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps

 9333 23:28:39.863642  mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)

 9334 23:28:39.866982  CPU_CLUSTER: 0 init finished in 81 msecs

 9335 23:28:39.870488  Devices initialized

 9336 23:28:39.874040  Show all devs... After init.

 9337 23:28:39.874463  Root Device: enabled 1

 9338 23:28:39.876878  CPU_CLUSTER: 0: enabled 1

 9339 23:28:39.880284  CPU: 00: enabled 1

 9340 23:28:39.883381  BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms

 9341 23:28:39.886752  FMAP: area RW_ELOG found @ 57f000 (4096 bytes)

 9342 23:28:39.889994  ELOG: NV offset 0x57f000 size 0x1000

 9343 23:28:39.896661  read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps

 9344 23:28:39.903783  ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024

 9345 23:28:39.906725  ELOG: Event(17) added with size 13 at 2023-12-03 23:26:26 UTC

 9346 23:28:39.912962  out: cmd=0x121: 03 db 21 01 00 00 00 00 

 9347 23:28:39.916792  in-header: 03 d9 00 00 2c 00 00 00 

 9348 23:28:39.926302  in-data: 86 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

 9349 23:28:39.932936  ELOG: Event(A1) added with size 10 at 2023-12-03 23:26:26 UTC

 9350 23:28:39.939676  elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b

 9351 23:28:39.946362  ELOG: Event(A0) added with size 9 at 2023-12-03 23:26:26 UTC

 9352 23:28:39.949737  elog_add_boot_reason: Logged dev mode boot

 9353 23:28:39.956617  BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms

 9354 23:28:39.957037  Finalize devices...

 9355 23:28:39.959730  Devices finalized

 9356 23:28:39.962882  BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms

 9357 23:28:39.966442  Writing coreboot table at 0xffe64000

 9358 23:28:39.969710   0. 000000000010a000-0000000000113fff: RAMSTAGE

 9359 23:28:39.973023   1. 0000000040000000-00000000400fffff: RAM

 9360 23:28:39.979421   2. 0000000040100000-000000004032afff: RAMSTAGE

 9361 23:28:39.982895   3. 000000004032b000-00000000545fffff: RAM

 9362 23:28:39.986140   4. 0000000054600000-000000005465ffff: BL31

 9363 23:28:39.989454   5. 0000000054660000-00000000ffe63fff: RAM

 9364 23:28:39.995695   6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES

 9365 23:28:39.999254   7. 0000000100000000-000000023fffffff: RAM

 9366 23:28:40.002886  Passing 5 GPIOs to payload:

 9367 23:28:40.005856              NAME |       PORT | POLARITY |     VALUE

 9368 23:28:40.009408          EC in RW | 0x000000aa |      low | undefined

 9369 23:28:40.016158      EC interrupt | 0x00000005 |      low | undefined

 9370 23:28:40.019248     TPM interrupt | 0x000000ab |     high | undefined

 9371 23:28:40.026058    SD card detect | 0x00000011 |     high | undefined

 9372 23:28:40.029237    speaker enable | 0x00000093 |     high | undefined

 9373 23:28:40.032702  out: cmd=0x6: 03 f7 06 00 00 00 00 00 

 9374 23:28:40.035894  in-header: 03 f9 00 00 02 00 00 00 

 9375 23:28:40.039305  in-data: 02 00 

 9376 23:28:40.039722  ADC[4]: Raw value=904726 ID=7

 9377 23:28:40.042742  ADC[3]: Raw value=213441 ID=1

 9378 23:28:40.045938  RAM Code: 0x71

 9379 23:28:40.049346  ADC[6]: Raw value=75701 ID=0

 9380 23:28:40.049872  ADC[5]: Raw value=212703 ID=1

 9381 23:28:40.052525  SKU Code: 0x1

 9382 23:28:40.055796  Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c

 9383 23:28:40.059486  coreboot table: 964 bytes.

 9384 23:28:40.062252  IMD ROOT    0. 0xfffff000 0x00001000

 9385 23:28:40.065566  IMD SMALL   1. 0xffffe000 0x00001000

 9386 23:28:40.068918  RO MCACHE   2. 0xffffc000 0x00001104

 9387 23:28:40.072369  CONSOLE     3. 0xfff7c000 0x00080000

 9388 23:28:40.075736  FMAP        4. 0xfff7b000 0x00000452

 9389 23:28:40.078649  TIME STAMP  5. 0xfff7a000 0x00000910

 9390 23:28:40.082300  VBOOT WORK  6. 0xfff66000 0x00014000

 9391 23:28:40.085202  RAMOOPS     7. 0xffe66000 0x00100000

 9392 23:28:40.089355  COREBOOT    8. 0xffe64000 0x00002000

 9393 23:28:40.092403  IMD small region:

 9394 23:28:40.095245    IMD ROOT    0. 0xffffec00 0x00000400

 9395 23:28:40.098561    VPD         1. 0xffffeb80 0x0000006c

 9396 23:28:40.101933    MMC STATUS  2. 0xffffeb60 0x00000004

 9397 23:28:40.105513  BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms

 9398 23:28:40.108485  Probing TPM:  done!

 9399 23:28:40.112242  Connected to device vid:did:rid of 1ae0:0028:00

 9400 23:28:40.122720  Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c

 9401 23:28:40.126100  Initialized TPM device CR50 revision 0

 9402 23:28:40.129852  Checking cr50 for pending updates

 9403 23:28:40.133666  Reading cr50 TPM mode

 9404 23:28:40.142373  BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms

 9405 23:28:40.148960  CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098

 9406 23:28:40.188753  read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps

 9407 23:28:40.192451  Checking segment from ROM address 0x40100000

 9408 23:28:40.195887  Checking segment from ROM address 0x4010001c

 9409 23:28:40.202708  Loading segment from ROM address 0x40100000

 9410 23:28:40.203131    code (compression=0)

 9411 23:28:40.208745    New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178

 9412 23:28:40.218890  Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178

 9413 23:28:40.219315  it's not compressed!

 9414 23:28:40.225507  [ 0x80000000, 8004f178, 0x821a7280) <- 40100038

 9415 23:28:40.228864  Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108

 9416 23:28:40.249282  Loading segment from ROM address 0x4010001c

 9417 23:28:40.249746    Entry Point 0x80000000

 9418 23:28:40.252849  Loaded segments

 9419 23:28:40.256125  BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms

 9420 23:28:40.262540  Jumping to boot code at 0x80000000(0xffe64000)

 9421 23:28:40.269161  CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes

 9422 23:28:40.275802  CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290

 9423 23:28:40.283892  read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps

 9424 23:28:40.286761  Checking segment from ROM address 0x40100000

 9425 23:28:40.290254  Checking segment from ROM address 0x4010001c

 9426 23:28:40.297180  Loading segment from ROM address 0x40100000

 9427 23:28:40.297792    code (compression=1)

 9428 23:28:40.303882    New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470

 9429 23:28:40.313390  Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470

 9430 23:28:40.313860  using LZMA

 9431 23:28:40.322202  [ 0x54600000, 54614abc, 0x5462e000) <- 40100038

 9432 23:28:40.329166  Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544

 9433 23:28:40.332146  Loading segment from ROM address 0x4010001c

 9434 23:28:40.332557    Entry Point 0x54601000

 9435 23:28:40.335525  Loaded segments

 9436 23:28:40.338992  NOTICE:  MT8192 bl31_setup

 9437 23:28:40.345786  NOTICE:  BL31: v2.4(debug):v2.4-448-gce3ebc861

 9438 23:28:40.349534  NOTICE:  BL31: Built : Sat Sep 11 09:59:37 UTC 2021

 9439 23:28:40.352862  WARNING: region 0:

 9440 23:28:40.355701  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9441 23:28:40.356127  WARNING: region 1:

 9442 23:28:40.362275  WARNING: 	sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d

 9443 23:28:40.365784  WARNING: region 2:

 9444 23:28:40.368906  WARNING: 	sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d

 9445 23:28:40.372495  WARNING: region 3:

 9446 23:28:40.375954  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9447 23:28:40.379292  WARNING: region 4:

 9448 23:28:40.385957  WARNING: 	sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d

 9449 23:28:40.386383  WARNING: region 5:

 9450 23:28:40.389016  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9451 23:28:40.392415  WARNING: region 6:

 9452 23:28:40.396125  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9453 23:28:40.398825  WARNING: region 7:

 9454 23:28:40.402275  WARNING: 	sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0

 9455 23:28:40.408948  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000

 9456 23:28:40.412274  INFO:    [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0

 9457 23:28:40.415584  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff

 9458 23:28:40.422310  INFO:    [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff

 9459 23:28:40.425860  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff

 9460 23:28:40.428923  INFO:    [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00

 9461 23:28:40.435640  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff

 9462 23:28:40.439177  INFO:    [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff

 9463 23:28:40.445691  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff

 9464 23:28:40.449028  INFO:    [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff

 9465 23:28:40.452542  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff

 9466 23:28:40.459086  INFO:    [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff

 9467 23:28:40.462934  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff

 9468 23:28:40.465922  INFO:    [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff

 9469 23:28:40.472314  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff

 9470 23:28:40.475878  INFO:    [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff

 9471 23:28:40.479096  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff

 9472 23:28:40.485723  INFO:    [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff

 9473 23:28:40.489025  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff

 9474 23:28:40.495681  INFO:    [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff

 9475 23:28:40.499182  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff

 9476 23:28:40.502463  INFO:    [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff

 9477 23:28:40.509219  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff

 9478 23:28:40.512321  INFO:    [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff

 9479 23:28:40.518874  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff

 9480 23:28:40.522600  INFO:    [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff

 9481 23:28:40.525837  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff

 9482 23:28:40.532045  INFO:    [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff

 9483 23:28:40.535914  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff

 9484 23:28:40.539287  INFO:    [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff

 9485 23:28:40.545556  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff

 9486 23:28:40.549038  INFO:    [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff

 9487 23:28:40.555780  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0

 9488 23:28:40.558797  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0

 9489 23:28:40.562282  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0

 9490 23:28:40.566165  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0

 9491 23:28:40.568853  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0

 9492 23:28:40.576072  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0

 9493 23:28:40.579352  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0

 9494 23:28:40.582536  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0

 9495 23:28:40.585653  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0

 9496 23:28:40.592836  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0

 9497 23:28:40.595722  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0

 9498 23:28:40.598952  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0

 9499 23:28:40.602729  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0

 9500 23:28:40.609312  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0

 9501 23:28:40.612929  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0

 9502 23:28:40.615675  INFO:    [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0

 9503 23:28:40.622457  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff

 9504 23:28:40.625750  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff

 9505 23:28:40.632431  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff

 9506 23:28:40.635769  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff

 9507 23:28:40.639106  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff

 9508 23:28:40.646002  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff

 9509 23:28:40.649465  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff

 9510 23:28:40.655588  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff

 9511 23:28:40.659161  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff

 9512 23:28:40.662378  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff

 9513 23:28:40.669221  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff

 9514 23:28:40.672362  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff

 9515 23:28:40.679239  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff

 9516 23:28:40.682631  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff

 9517 23:28:40.689323  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff

 9518 23:28:40.692421  INFO:    [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff

 9519 23:28:40.699484  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff

 9520 23:28:40.702614  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff

 9521 23:28:40.706124  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff

 9522 23:28:40.712544  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff

 9523 23:28:40.715924  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff

 9524 23:28:40.722720  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff

 9525 23:28:40.726233  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff

 9526 23:28:40.732901  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff

 9527 23:28:40.736068  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff

 9528 23:28:40.739171  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff

 9529 23:28:40.746361  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff

 9530 23:28:40.749393  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff

 9531 23:28:40.755384  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff

 9532 23:28:40.758719  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff

 9533 23:28:40.765543  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff

 9534 23:28:40.769070  INFO:    [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff

 9535 23:28:40.772489  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff

 9536 23:28:40.779004  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff

 9537 23:28:40.782262  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff

 9538 23:28:40.788992  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff

 9539 23:28:40.792359  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff

 9540 23:28:40.799208  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff

 9541 23:28:40.802631  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff

 9542 23:28:40.805375  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff

 9543 23:28:40.812469  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff

 9544 23:28:40.815912  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff

 9545 23:28:40.822452  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff

 9546 23:28:40.825398  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff

 9547 23:28:40.832153  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff

 9548 23:28:40.835593  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff

 9549 23:28:40.839371  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff

 9550 23:28:40.845452  INFO:    [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff

 9551 23:28:40.848725  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0

 9552 23:28:40.852177  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0

 9553 23:28:40.858729  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0

 9554 23:28:40.861964  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0

 9555 23:28:40.865235  INFO:    [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0

 9556 23:28:40.872056  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff

 9557 23:28:40.875772  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff

 9558 23:28:40.878823  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff

 9559 23:28:40.885502  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff

 9560 23:28:40.888831  INFO:    [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff

 9561 23:28:40.895598  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff

 9562 23:28:40.899361  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff

 9563 23:28:40.902107  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff

 9564 23:28:40.908982  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff

 9565 23:28:40.912284  INFO:    [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff

 9566 23:28:40.915418  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff

 9567 23:28:40.922198  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff

 9568 23:28:40.925344  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff

 9569 23:28:40.932122  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff

 9570 23:28:40.935775  INFO:    [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff

 9571 23:28:40.938944  INFO:    [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18

 9572 23:28:40.945542  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000

 9573 23:28:40.948607  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004

 9574 23:28:40.952131  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0

 9575 23:28:40.955420  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0

 9576 23:28:40.962336  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0

 9577 23:28:40.965688  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0

 9578 23:28:40.969166  INFO:    [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000

 9579 23:28:40.975530  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff

 9580 23:28:40.978910  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff

 9581 23:28:40.982566  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff

 9582 23:28:40.989213  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff

 9583 23:28:40.992538  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff

 9584 23:28:40.999194  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff

 9585 23:28:41.002470  INFO:    [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff

 9586 23:28:41.005469  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc

 9587 23:28:41.012432  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff

 9588 23:28:41.016137  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf

 9589 23:28:41.019238  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff

 9590 23:28:41.025587  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc

 9591 23:28:41.029025  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff

 9592 23:28:41.035511  INFO:    [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff

 9593 23:28:41.039294  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff

 9594 23:28:41.042776  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff

 9595 23:28:41.049091  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff

 9596 23:28:41.052845  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff

 9597 23:28:41.055904  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff

 9598 23:28:41.062689  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff

 9599 23:28:41.066079  INFO:    [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff

 9600 23:28:41.072770  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff

 9601 23:28:41.075819  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff

 9602 23:28:41.079304  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff

 9603 23:28:41.085872  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff

 9604 23:28:41.089547  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff

 9605 23:28:41.092604  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff

 9606 23:28:41.099528  INFO:    [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff

 9607 23:28:41.102829  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff

 9608 23:28:41.109395  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff

 9609 23:28:41.112927  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff

 9610 23:28:41.116168  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff

 9611 23:28:41.123097  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff

 9612 23:28:41.126435  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff

 9613 23:28:41.129369  INFO:    [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff

 9614 23:28:41.135776  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff

 9615 23:28:41.139264  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff

 9616 23:28:41.145901  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff

 9617 23:28:41.149250  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff

 9618 23:28:41.152796  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff

 9619 23:28:41.159567  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff

 9620 23:28:41.162550  INFO:    [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff

 9621 23:28:41.169154  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff

 9622 23:28:41.172862  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff

 9623 23:28:41.176179  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff

 9624 23:28:41.182554  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff

 9625 23:28:41.186385  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff

 9626 23:28:41.192800  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff

 9627 23:28:41.196305  INFO:    [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff

 9628 23:28:41.199167  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff

 9629 23:28:41.205782  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff

 9630 23:28:41.209407  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff

 9631 23:28:41.212402  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff

 9632 23:28:41.219856  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff

 9633 23:28:41.222436  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff

 9634 23:28:41.229052  INFO:    [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff

 9635 23:28:41.232608  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff

 9636 23:28:41.235667  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff

 9637 23:28:41.242366  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff

 9638 23:28:41.245741  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff

 9639 23:28:41.252160  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff

 9640 23:28:41.255517  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff

 9641 23:28:41.258987  INFO:    [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff

 9642 23:28:41.265265  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff

 9643 23:28:41.268932  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff

 9644 23:28:41.275476  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff

 9645 23:28:41.278948  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff

 9646 23:28:41.285695  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff

 9647 23:28:41.289102  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff

 9648 23:28:41.292764  INFO:    [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff

 9649 23:28:41.298918  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff

 9650 23:28:41.302195  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff

 9651 23:28:41.308837  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff

 9652 23:28:41.312273  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff

 9653 23:28:41.315482  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff

 9654 23:28:41.322239  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff

 9655 23:28:41.325472  INFO:    [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff

 9656 23:28:41.331767  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff

 9657 23:28:41.335325  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff

 9658 23:28:41.341872  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff

 9659 23:28:41.345326  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff

 9660 23:28:41.348639  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff

 9661 23:28:41.355736  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff

 9662 23:28:41.358865  INFO:    [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff

 9663 23:28:41.365074  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff

 9664 23:28:41.368490  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff

 9665 23:28:41.372040  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff

 9666 23:28:41.378805  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff

 9667 23:28:41.381775  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff

 9668 23:28:41.388635  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff

 9669 23:28:41.392068  INFO:    [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff

 9670 23:28:41.394973  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff

 9671 23:28:41.401988  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff

 9672 23:28:41.405154  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff

 9673 23:28:41.411486  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff

 9674 23:28:41.415431  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff

 9675 23:28:41.421707  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff

 9676 23:28:41.424792  INFO:    [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff

 9677 23:28:41.428262  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff

 9678 23:28:41.435111  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff

 9679 23:28:41.438178  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff

 9680 23:28:41.445256  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff

 9681 23:28:41.447778  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff

 9682 23:28:41.454747  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff

 9683 23:28:41.457846  INFO:    [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff

 9684 23:28:41.461091  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0

 9685 23:28:41.464252  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0

 9686 23:28:41.471087  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0

 9687 23:28:41.474288  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0

 9688 23:28:41.477610  INFO:    [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0

 9689 23:28:41.481008  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff

 9690 23:28:41.487822  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff

 9691 23:28:41.490878  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff

 9692 23:28:41.497794  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff

 9693 23:28:41.501291  INFO:    [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf

 9694 23:28:41.504597  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff

 9695 23:28:41.511251  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff

 9696 23:28:41.514397  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff

 9697 23:28:41.517797  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff

 9698 23:28:41.523954  INFO:    [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf

 9699 23:28:41.527265  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff

 9700 23:28:41.534064  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff

 9701 23:28:41.537530  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff

 9702 23:28:41.541040  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff

 9703 23:28:41.547158  INFO:    [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf

 9704 23:28:41.550496  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff

 9705 23:28:41.554020  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff

 9706 23:28:41.561173  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff

 9707 23:28:41.563775  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff

 9708 23:28:41.567205  INFO:    [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf

 9709 23:28:41.573667  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff

 9710 23:28:41.577315  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff

 9711 23:28:41.583769  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff

 9712 23:28:41.587251  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff

 9713 23:28:41.590577  INFO:    [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf

 9714 23:28:41.597405  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff

 9715 23:28:41.600198  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff

 9716 23:28:41.603779  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff

 9717 23:28:41.610561  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff

 9718 23:28:41.614096  INFO:    [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf

 9719 23:28:41.617242  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff

 9720 23:28:41.623766  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff

 9721 23:28:41.627148  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff

 9722 23:28:41.633513  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff

 9723 23:28:41.636873  INFO:    [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf

 9724 23:28:41.640295  INFO:    [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0

 9725 23:28:41.643398  INFO:    [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3

 9726 23:28:41.650473  INFO:    [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3

 9727 23:28:41.653724  INFO:    [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3

 9728 23:28:41.656702  INFO:    [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0

 9729 23:28:41.659908  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400

 9730 23:28:41.666709  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0

 9731 23:28:41.670002  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0

 9732 23:28:41.673272  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0

 9733 23:28:41.676613  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0

 9734 23:28:41.683896  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0

 9735 23:28:41.687001  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000

 9736 23:28:41.690450  INFO:    [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0

 9737 23:28:41.696576  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff

 9738 23:28:41.700068  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff

 9739 23:28:41.703485  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff

 9740 23:28:41.709965  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff

 9741 23:28:41.713522  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff

 9742 23:28:41.720140  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff

 9743 23:28:41.723355  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff

 9744 23:28:41.726556  INFO:    [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f

 9745 23:28:41.732903  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3

 9746 23:28:41.736320  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff

 9747 23:28:41.743059  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff

 9748 23:28:41.746316  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff

 9749 23:28:41.753049  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff

 9750 23:28:41.756002  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff

 9751 23:28:41.759872  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff

 9752 23:28:41.766408  INFO:    [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f

 9753 23:28:41.769776  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff

 9754 23:28:41.775973  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff

 9755 23:28:41.779360  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff

 9756 23:28:41.782903  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff

 9757 23:28:41.789161  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff

 9758 23:28:41.792740  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff

 9759 23:28:41.799416  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff

 9760 23:28:41.802694  INFO:    [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f

 9761 23:28:41.806221  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff

 9762 23:28:41.812749  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff

 9763 23:28:41.816153  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff

 9764 23:28:41.822910  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff

 9765 23:28:41.825743  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff

 9766 23:28:41.832860  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff

 9767 23:28:41.835734  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff

 9768 23:28:41.839550  INFO:    [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f

 9769 23:28:41.845725  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff

 9770 23:28:41.849290  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff

 9771 23:28:41.855835  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff

 9772 23:28:41.859437  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff

 9773 23:28:41.862329  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff

 9774 23:28:41.869443  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff

 9775 23:28:41.872446  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff

 9776 23:28:41.875931  INFO:    [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f

 9777 23:28:41.882785  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff

 9778 23:28:41.886078  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff

 9779 23:28:41.892717  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff

 9780 23:28:41.895910  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff

 9781 23:28:41.902403  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff

 9782 23:28:41.905983  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff

 9783 23:28:41.909818  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff

 9784 23:28:41.916020  INFO:    [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f

 9785 23:28:41.918839  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff

 9786 23:28:41.925735  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff

 9787 23:28:41.929038  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff

 9788 23:28:41.932579  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff

 9789 23:28:41.939239  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff

 9790 23:28:41.942524  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff

 9791 23:28:41.949369  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff

 9792 23:28:41.952241  INFO:    [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f

 9793 23:28:41.955884  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff

 9794 23:28:41.962105  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff

 9795 23:28:41.965718  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff

 9796 23:28:41.972533  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff

 9797 23:28:41.975434  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff

 9798 23:28:41.982072  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff

 9799 23:28:41.985499  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff

 9800 23:28:41.988782  INFO:    [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f

 9801 23:28:41.995326  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff

 9802 23:28:41.998829  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff

 9803 23:28:42.005282  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff

 9804 23:28:42.008428  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff

 9805 23:28:42.011793  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff

 9806 23:28:42.018232  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff

 9807 23:28:42.021886  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff

 9808 23:28:42.028317  INFO:    [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f

 9809 23:28:42.031752  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff

 9810 23:28:42.035098  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff

 9811 23:28:42.041470  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff

 9812 23:28:42.045106  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff

 9813 23:28:42.051858  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff

 9814 23:28:42.055526  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff

 9815 23:28:42.061643  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff

 9816 23:28:42.064904  INFO:    [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f

 9817 23:28:42.071452  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff

 9818 23:28:42.075076  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff

 9819 23:28:42.078022  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff

 9820 23:28:42.084756  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff

 9821 23:28:42.088188  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff

 9822 23:28:42.094728  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff

 9823 23:28:42.098333  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff

 9824 23:28:42.104602  INFO:    [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f

 9825 23:28:42.108181  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff

 9826 23:28:42.111657  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff

 9827 23:28:42.118023  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff

 9828 23:28:42.121331  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff

 9829 23:28:42.128274  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff

 9830 23:28:42.131240  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff

 9831 23:28:42.138552  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff

 9832 23:28:42.141812  INFO:    [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f

 9833 23:28:42.145069  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff

 9834 23:28:42.151302  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff

 9835 23:28:42.154787  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff

 9836 23:28:42.161545  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff

 9837 23:28:42.165327  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff

 9838 23:28:42.171531  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff

 9839 23:28:42.174542  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff

 9840 23:28:42.178102  INFO:    [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f

 9841 23:28:42.184742  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff

 9842 23:28:42.188205  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff

 9843 23:28:42.195147  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff

 9844 23:28:42.198084  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff

 9845 23:28:42.204408  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff

 9846 23:28:42.208126  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff

 9847 23:28:42.214607  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff

 9848 23:28:42.217961  INFO:    [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f

 9849 23:28:42.221334  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff

 9850 23:28:42.227803  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff

 9851 23:28:42.231024  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff

 9852 23:28:42.237789  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff

 9853 23:28:42.241153  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff

 9854 23:28:42.248030  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff

 9855 23:28:42.251480  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff

 9856 23:28:42.254825  INFO:    [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f

 9857 23:28:42.261213  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0

 9858 23:28:42.264608  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000

 9859 23:28:42.271279  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff

 9860 23:28:42.274512  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff

 9861 23:28:42.280824  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3

 9862 23:28:42.284321  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff

 9863 23:28:42.290848  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff

 9864 23:28:42.294249  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff

 9865 23:28:42.297756  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff

 9866 23:28:42.304413  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff

 9867 23:28:42.307787  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff

 9868 23:28:42.314719  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff

 9869 23:28:42.317461  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff

 9870 23:28:42.324227  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff

 9871 23:28:42.327547  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff

 9872 23:28:42.334214  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff

 9873 23:28:42.337527  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff

 9874 23:28:42.344212  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff

 9875 23:28:42.347243  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff

 9876 23:28:42.354238  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff

 9877 23:28:42.357631  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff

 9878 23:28:42.364242  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff

 9879 23:28:42.367671  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff

 9880 23:28:42.374032  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff

 9881 23:28:42.377281  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff

 9882 23:28:42.384179  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff

 9883 23:28:42.387311  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff

 9884 23:28:42.394290  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff

 9885 23:28:42.397415  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff

 9886 23:28:42.404021  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff

 9887 23:28:42.407288  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff

 9888 23:28:42.413871  INFO:    [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff

 9889 23:28:42.417356  INFO:    [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0

 9890 23:28:42.420537  INFO:    [APUAPC] vio 0

 9891 23:28:42.424122  INFO:    [APUAPC] set_apusys_ao_apc - SUCCESS!

 9892 23:28:42.430602  INFO:    [APUAPC] set_apusys_noc_dapc - SUCCESS!

 9893 23:28:42.430685  INFO:    [APUAPC] D0_APC_0: 0x400510

 9894 23:28:42.434080  INFO:    [APUAPC] D0_APC_1: 0x0

 9895 23:28:42.437215  INFO:    [APUAPC] D0_APC_2: 0x1540

 9896 23:28:42.440533  INFO:    [APUAPC] D0_APC_3: 0x0

 9897 23:28:42.443938  INFO:    [APUAPC] D1_APC_0: 0xffffffff

 9898 23:28:42.447786  INFO:    [APUAPC] D1_APC_1: 0xffffffff

 9899 23:28:42.450886  INFO:    [APUAPC] D1_APC_2: 0x3fffff

 9900 23:28:42.453980  INFO:    [APUAPC] D1_APC_3: 0x0

 9901 23:28:42.457137  INFO:    [APUAPC] D2_APC_0: 0xffffffff

 9902 23:28:42.460551  INFO:    [APUAPC] D2_APC_1: 0xffffffff

 9903 23:28:42.463973  INFO:    [APUAPC] D2_APC_2: 0x3fffff

 9904 23:28:42.467138  INFO:    [APUAPC] D2_APC_3: 0x0

 9905 23:28:42.470308  INFO:    [APUAPC] D3_APC_0: 0xffffffff

 9906 23:28:42.473757  INFO:    [APUAPC] D3_APC_1: 0xffffffff

 9907 23:28:42.477505  INFO:    [APUAPC] D3_APC_2: 0x3fffff

 9908 23:28:42.480601  INFO:    [APUAPC] D3_APC_3: 0x0

 9909 23:28:42.484028  INFO:    [APUAPC] D4_APC_0: 0xffffffff

 9910 23:28:42.487253  INFO:    [APUAPC] D4_APC_1: 0xffffffff

 9911 23:28:42.490730  INFO:    [APUAPC] D4_APC_2: 0x3fffff

 9912 23:28:42.493510  INFO:    [APUAPC] D4_APC_3: 0x0

 9913 23:28:42.496835  INFO:    [APUAPC] D5_APC_0: 0xffffffff

 9914 23:28:42.500370  INFO:    [APUAPC] D5_APC_1: 0xffffffff

 9915 23:28:42.503707  INFO:    [APUAPC] D5_APC_2: 0x3fffff

 9916 23:28:42.506923  INFO:    [APUAPC] D5_APC_3: 0x0

 9917 23:28:42.510343  INFO:    [APUAPC] D6_APC_0: 0xffffffff

 9918 23:28:42.513515  INFO:    [APUAPC] D6_APC_1: 0xffffffff

 9919 23:28:42.516902  INFO:    [APUAPC] D6_APC_2: 0x3fffff

 9920 23:28:42.520235  INFO:    [APUAPC] D6_APC_3: 0x0

 9921 23:28:42.523715  INFO:    [APUAPC] D7_APC_0: 0xffffffff

 9922 23:28:42.526920  INFO:    [APUAPC] D7_APC_1: 0xffffffff

 9923 23:28:42.530486  INFO:    [APUAPC] D7_APC_2: 0x3fffff

 9924 23:28:42.533597  INFO:    [APUAPC] D7_APC_3: 0x0

 9925 23:28:42.537001  INFO:    [APUAPC] D8_APC_0: 0xffffffff

 9926 23:28:42.539851  INFO:    [APUAPC] D8_APC_1: 0xffffffff

 9927 23:28:42.543212  INFO:    [APUAPC] D8_APC_2: 0x3fffff

 9928 23:28:42.546652  INFO:    [APUAPC] D8_APC_3: 0x0

 9929 23:28:42.550085  INFO:    [APUAPC] D9_APC_0: 0xffffffff

 9930 23:28:42.553483  INFO:    [APUAPC] D9_APC_1: 0xffffffff

 9931 23:28:42.557083  INFO:    [APUAPC] D9_APC_2: 0x3fffff

 9932 23:28:42.557165  INFO:    [APUAPC] D9_APC_3: 0x0

 9933 23:28:42.563544  INFO:    [APUAPC] D10_APC_0: 0xffffffff

 9934 23:28:42.566889  INFO:    [APUAPC] D10_APC_1: 0xffffffff

 9935 23:28:42.569804  INFO:    [APUAPC] D10_APC_2: 0x3fffff

 9936 23:28:42.569885  INFO:    [APUAPC] D10_APC_3: 0x0

 9937 23:28:42.576388  INFO:    [APUAPC] D11_APC_0: 0xffffffff

 9938 23:28:42.580050  INFO:    [APUAPC] D11_APC_1: 0xffffffff

 9939 23:28:42.583402  INFO:    [APUAPC] D11_APC_2: 0x3fffff

 9940 23:28:42.583497  INFO:    [APUAPC] D11_APC_3: 0x0

 9941 23:28:42.589722  INFO:    [APUAPC] D12_APC_0: 0xffffffff

 9942 23:28:42.592906  INFO:    [APUAPC] D12_APC_1: 0xffffffff

 9943 23:28:42.596395  INFO:    [APUAPC] D12_APC_2: 0x3fffff

 9944 23:28:42.599573  INFO:    [APUAPC] D12_APC_3: 0x0

 9945 23:28:42.603146  INFO:    [APUAPC] D13_APC_0: 0xffffffff

 9946 23:28:42.606332  INFO:    [APUAPC] D13_APC_1: 0xffffffff

 9947 23:28:42.609778  INFO:    [APUAPC] D13_APC_2: 0x3fffff

 9948 23:28:42.612907  INFO:    [APUAPC] D13_APC_3: 0x0

 9949 23:28:42.616336  INFO:    [APUAPC] D14_APC_0: 0xffffffff

 9950 23:28:42.619378  INFO:    [APUAPC] D14_APC_1: 0xffffffff

 9951 23:28:42.622877  INFO:    [APUAPC] D14_APC_2: 0x3fffff

 9952 23:28:42.626131  INFO:    [APUAPC] D14_APC_3: 0x0

 9953 23:28:42.629228  INFO:    [APUAPC] D15_APC_0: 0xffffffff

 9954 23:28:42.632666  INFO:    [APUAPC] D15_APC_1: 0xffffffff

 9955 23:28:42.635913  INFO:    [APUAPC] D15_APC_2: 0x3fffff

 9956 23:28:42.639516  INFO:    [APUAPC] D15_APC_3: 0x0

 9957 23:28:42.639599  INFO:    [APUAPC] APC_CON: 0x4

 9958 23:28:42.642823  INFO:    [NOCDAPC] D0_APC_0: 0x0

 9959 23:28:42.646169  INFO:    [NOCDAPC] D0_APC_1: 0x0

 9960 23:28:42.649265  INFO:    [NOCDAPC] D1_APC_0: 0x0

 9961 23:28:42.653032  INFO:    [NOCDAPC] D1_APC_1: 0xfff

 9962 23:28:42.656312  INFO:    [NOCDAPC] D2_APC_0: 0x0

 9963 23:28:42.659434  INFO:    [NOCDAPC] D2_APC_1: 0xfff

 9964 23:28:42.662479  INFO:    [NOCDAPC] D3_APC_0: 0x0

 9965 23:28:42.666068  INFO:    [NOCDAPC] D3_APC_1: 0xfff

 9966 23:28:42.669306  INFO:    [NOCDAPC] D4_APC_0: 0x0

 9967 23:28:42.672463  INFO:    [NOCDAPC] D4_APC_1: 0xfff

 9968 23:28:42.672536  INFO:    [NOCDAPC] D5_APC_0: 0x0

 9969 23:28:42.675795  INFO:    [NOCDAPC] D5_APC_1: 0xfff

 9970 23:28:42.679110  INFO:    [NOCDAPC] D6_APC_0: 0x0

 9971 23:28:42.682950  INFO:    [NOCDAPC] D6_APC_1: 0xfff

 9972 23:28:42.685836  INFO:    [NOCDAPC] D7_APC_0: 0x0

 9973 23:28:42.689439  INFO:    [NOCDAPC] D7_APC_1: 0xfff

 9974 23:28:42.692561  INFO:    [NOCDAPC] D8_APC_0: 0x0

 9975 23:28:42.695762  INFO:    [NOCDAPC] D8_APC_1: 0xfff

 9976 23:28:42.699292  INFO:    [NOCDAPC] D9_APC_0: 0x0

 9977 23:28:42.702549  INFO:    [NOCDAPC] D9_APC_1: 0xfff

 9978 23:28:42.705621  INFO:    [NOCDAPC] D10_APC_0: 0x0

 9979 23:28:42.708881  INFO:    [NOCDAPC] D10_APC_1: 0xfff

 9980 23:28:42.708962  INFO:    [NOCDAPC] D11_APC_0: 0x0

 9981 23:28:42.712525  INFO:    [NOCDAPC] D11_APC_1: 0xfff

 9982 23:28:42.715551  INFO:    [NOCDAPC] D12_APC_0: 0x0

 9983 23:28:42.719404  INFO:    [NOCDAPC] D12_APC_1: 0xfff

 9984 23:28:42.722579  INFO:    [NOCDAPC] D13_APC_0: 0x0

 9985 23:28:42.725653  INFO:    [NOCDAPC] D13_APC_1: 0xfff

 9986 23:28:42.729043  INFO:    [NOCDAPC] D14_APC_0: 0x0

 9987 23:28:42.732329  INFO:    [NOCDAPC] D14_APC_1: 0xfff

 9988 23:28:42.735669  INFO:    [NOCDAPC] D15_APC_0: 0x0

 9989 23:28:42.738883  INFO:    [NOCDAPC] D15_APC_1: 0xfff

 9990 23:28:42.742393  INFO:    [NOCDAPC] APC_CON: 0x4

 9991 23:28:42.745834  INFO:    [APUAPC] set_apusys_apc done

 9992 23:28:42.748582  INFO:    [DEVAPC] devapc_init done

 9993 23:28:42.752107  INFO:    GICv3 without legacy support detected.

 9994 23:28:42.755453  INFO:    ARM GICv3 driver initialized in EL3

 9995 23:28:42.758878  INFO:    Maximum SPI INTID supported: 639

 9996 23:28:42.761907  INFO:    BL31: Initializing runtime services

 9997 23:28:42.768728  WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!

 9998 23:28:42.771923  INFO:    SPM: enable CPC mode

 9999 23:28:42.778921  INFO:    mcdi ready for mcusys-off-idle and system suspend

10000 23:28:42.782388  INFO:    BL31: Preparing for EL3 exit to normal world

10001 23:28:42.785904  INFO:    Entry point address = 0x80000000

10002 23:28:42.788772  INFO:    SPSR = 0x8

10003 23:28:42.793214  

10004 23:28:42.793298  

10005 23:28:42.793361  

10006 23:28:42.796456  Starting depthcharge on Spherion...

10007 23:28:42.796536  

10008 23:28:42.796600  Wipe memory regions:

10009 23:28:42.796659  

10010 23:28:42.797327  end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10011 23:28:42.797429  start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10012 23:28:42.797511  Setting prompt string to ['asurada:']
10013 23:28:42.797613  bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10014 23:28:42.799534  	[0x00000040000000, 0x00000054600000)

10015 23:28:42.922154  

10016 23:28:42.922322  	[0x00000054660000, 0x00000080000000)

10017 23:28:43.182884  

10018 23:28:43.183037  	[0x000000821a7280, 0x000000ffe64000)

10019 23:28:43.927346  

10020 23:28:43.927504  	[0x00000100000000, 0x00000240000000)

10021 23:28:45.817526  

10022 23:28:45.820644  Initializing XHCI USB controller at 0x11200000.

10023 23:28:46.858478  

10024 23:28:46.861695  [firmware-asurada-13885.B-collabora] Dec  7 2021 09:38:38

10025 23:28:46.862131  

10026 23:28:46.862467  

10027 23:28:46.862780  

10028 23:28:46.863523  Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 23:28:46.964664  asurada: tftpboot 192.168.201.1 12172428/tftp-deploy-um0a0hli/kernel/image.itb 12172428/tftp-deploy-um0a0hli/kernel/cmdline 

10031 23:28:46.965243  Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10032 23:28:46.965702  bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10033 23:28:46.970427  tftpboot 192.168.201.1 12172428/tftp-deploy-um0a0hli/kernel/image.itp-deploy-um0a0hli/kernel/cmdline 

10034 23:28:46.970863  

10035 23:28:46.971195  Waiting for link

10036 23:28:47.130595  

10037 23:28:47.131116  R8152: Initializing

10038 23:28:47.131459  

10039 23:28:47.134143  Version 9 (ocp_data = 6010)

10040 23:28:47.134580  

10041 23:28:47.136845  R8152: Done initializing

10042 23:28:47.137266  

10043 23:28:47.137638  Adding net device

10044 23:28:49.006777  

10045 23:28:49.007297  done.

10046 23:28:49.007656  

10047 23:28:49.008091  MAC: 00:e0:4c:78:7a:aa

10048 23:28:49.008509  

10049 23:28:49.010031  Sending DHCP discover... done.

10050 23:28:49.010468  

10051 23:28:49.013339  Waiting for reply... done.

10052 23:28:49.013829  

10053 23:28:49.016582  Sending DHCP request... done.

10054 23:28:49.017019  

10055 23:28:49.021843  Waiting for reply... done.

10056 23:28:49.022280  

10057 23:28:49.022722  My ip is 192.168.201.12

10058 23:28:49.023142  

10059 23:28:49.025045  The DHCP server ip is 192.168.201.1

10060 23:28:49.025497  

10061 23:28:49.031410  TFTP server IP predefined by user: 192.168.201.1

10062 23:28:49.031496  

10063 23:28:49.037923  Bootfile predefined by user: 12172428/tftp-deploy-um0a0hli/kernel/image.itb

10064 23:28:49.038004  

10065 23:28:49.041675  Sending tftp read request... done.

10066 23:28:49.042154  

10067 23:28:49.047464  Waiting for the transfer... 

10068 23:28:49.048043  

10069 23:28:49.311416  00000000 ################################################################

10070 23:28:49.311562  

10071 23:28:49.570320  00080000 ################################################################

10072 23:28:49.570491  

10073 23:28:49.816125  00100000 ################################################################

10074 23:28:49.816279  

10075 23:28:50.084403  00180000 ################################################################

10076 23:28:50.084589  

10077 23:28:50.334748  00200000 ################################################################

10078 23:28:50.334901  

10079 23:28:50.587186  00280000 ################################################################

10080 23:28:50.587337  

10081 23:28:50.843823  00300000 ################################################################

10082 23:28:50.843972  

10083 23:28:51.099041  00380000 ################################################################

10084 23:28:51.099193  

10085 23:28:51.351290  00400000 ################################################################

10086 23:28:51.351441  

10087 23:28:51.601713  00480000 ################################################################

10088 23:28:51.601861  

10089 23:28:51.856886  00500000 ################################################################

10090 23:28:51.857043  

10091 23:28:52.125659  00580000 ################################################################

10092 23:28:52.125811  

10093 23:28:52.381747  00600000 ################################################################

10094 23:28:52.381891  

10095 23:28:52.630033  00680000 ################################################################

10096 23:28:52.630185  

10097 23:28:52.895338  00700000 ################################################################

10098 23:28:52.895483  

10099 23:28:53.164280  00780000 ################################################################

10100 23:28:53.164416  

10101 23:28:53.433839  00800000 ################################################################

10102 23:28:53.433986  

10103 23:28:53.707538  00880000 ################################################################

10104 23:28:53.707681  

10105 23:28:53.963735  00900000 ################################################################

10106 23:28:53.963881  

10107 23:28:54.214694  00980000 ################################################################

10108 23:28:54.214842  

10109 23:28:54.474442  00a00000 ################################################################

10110 23:28:54.474588  

10111 23:28:54.760943  00a80000 ################################################################

10112 23:28:54.761091  

10113 23:28:55.041270  00b00000 ################################################################

10114 23:28:55.041438  

10115 23:28:55.304882  00b80000 ################################################################

10116 23:28:55.305029  

10117 23:28:55.581730  00c00000 ################################################################

10118 23:28:55.581870  

10119 23:28:55.856223  00c80000 ################################################################

10120 23:28:55.856379  

10121 23:28:56.099691  00d00000 ################################################################

10122 23:28:56.099889  

10123 23:28:56.346704  00d80000 ################################################################

10124 23:28:56.346848  

10125 23:28:56.587900  00e00000 ################################################################

10126 23:28:56.588054  

10127 23:28:56.830356  00e80000 ################################################################

10128 23:28:56.830518  

10129 23:28:57.071563  00f00000 ################################################################

10130 23:28:57.071720  

10131 23:28:57.312496  00f80000 ################################################################

10132 23:28:57.312645  

10133 23:28:57.554274  01000000 ################################################################

10134 23:28:57.554444  

10135 23:28:57.796387  01080000 ################################################################

10136 23:28:57.796554  

10137 23:28:58.038054  01100000 ################################################################

10138 23:28:58.038226  

10139 23:28:58.279824  01180000 ################################################################

10140 23:28:58.279979  

10141 23:28:58.521353  01200000 ################################################################

10142 23:28:58.521500  

10143 23:28:58.763696  01280000 ################################################################

10144 23:28:58.763851  

10145 23:28:59.005600  01300000 ################################################################

10146 23:28:59.005744  

10147 23:28:59.247965  01380000 ################################################################

10148 23:28:59.248113  

10149 23:28:59.488828  01400000 ################################################################

10150 23:28:59.488979  

10151 23:28:59.730062  01480000 ################################################################

10152 23:28:59.730209  

10153 23:28:59.971814  01500000 ################################################################

10154 23:28:59.971985  

10155 23:29:00.215396  01580000 ################################################################

10156 23:29:00.215552  

10157 23:29:00.458800  01600000 ################################################################

10158 23:29:00.458955  

10159 23:29:00.701486  01680000 ################################################################

10160 23:29:00.701677  

10161 23:29:00.951131  01700000 ################################################################

10162 23:29:00.951276  

10163 23:29:01.201265  01780000 ################################################################

10164 23:29:01.201444  

10165 23:29:01.458253  01800000 ################################################################

10166 23:29:01.458424  

10167 23:29:01.729373  01880000 ################################################################

10168 23:29:01.729509  

10169 23:29:01.989968  01900000 ################################################################

10170 23:29:01.990126  

10171 23:29:02.242717  01980000 ################################################################

10172 23:29:02.242868  

10173 23:29:02.501043  01a00000 ################################################################

10174 23:29:02.501211  

10175 23:29:02.748750  01a80000 ################################################################

10176 23:29:02.748919  

10177 23:29:02.998457  01b00000 ################################################################

10178 23:29:02.998624  

10179 23:29:03.246939  01b80000 ################################################################

10180 23:29:03.247082  

10181 23:29:03.533142  01c00000 ################################################################

10182 23:29:03.533285  

10183 23:29:03.794188  01c80000 ################################################################

10184 23:29:03.794334  

10185 23:29:04.062863  01d00000 ################################################################

10186 23:29:04.063007  

10187 23:29:04.313917  01d80000 ################################################################

10188 23:29:04.314062  

10189 23:29:04.563090  01e00000 ################################################################

10190 23:29:04.563244  

10191 23:29:04.838140  01e80000 ################################################################

10192 23:29:04.838284  

10193 23:29:05.131535  01f00000 ################################################################

10194 23:29:05.131678  

10195 23:29:05.420615  01f80000 ################################################################

10196 23:29:05.420797  

10197 23:29:05.693483  02000000 ################################################################

10198 23:29:05.693670  

10199 23:29:05.935857  02080000 ################################################################

10200 23:29:05.936002  

10201 23:29:06.185227  02100000 ################################################################

10202 23:29:06.185365  

10203 23:29:06.434147  02180000 ################################################################

10204 23:29:06.434315  

10205 23:29:06.685460  02200000 ################################################################

10206 23:29:06.685651  

10207 23:29:06.940258  02280000 ################################################################

10208 23:29:06.940403  

10209 23:29:07.189797  02300000 ################################################################

10210 23:29:07.189948  

10211 23:29:07.439379  02380000 ################################################################

10212 23:29:07.439593  

10213 23:29:07.697914  02400000 ################################################################

10214 23:29:07.698058  

10215 23:29:07.963743  02480000 ################################################################

10216 23:29:07.963932  

10217 23:29:08.205354  02500000 ################################################################

10218 23:29:08.205521  

10219 23:29:08.457720  02580000 ################################################################

10220 23:29:08.457867  

10221 23:29:08.711927  02600000 ################################################################

10222 23:29:08.712072  

10223 23:29:08.963662  02680000 ################################################################

10224 23:29:08.963808  

10225 23:29:09.238183  02700000 ################################################################

10226 23:29:09.238327  

10227 23:29:09.488837  02780000 ################################################################

10228 23:29:09.488994  

10229 23:29:09.732978  02800000 ################################################################

10230 23:29:09.733132  

10231 23:29:09.989391  02880000 ################################################################

10232 23:29:09.989544  

10233 23:29:10.238179  02900000 ################################################################

10234 23:29:10.238334  

10235 23:29:10.485421  02980000 ################################################################

10236 23:29:10.485620  

10237 23:29:10.739515  02a00000 ################################################################

10238 23:29:10.739685  

10239 23:29:10.999076  02a80000 ################################################################

10240 23:29:10.999269  

10241 23:29:11.248068  02b00000 ################################################################

10242 23:29:11.248244  

10243 23:29:11.491785  02b80000 ################################################################

10244 23:29:11.491960  

10245 23:29:11.743747  02c00000 ################################################################

10246 23:29:11.743890  

10247 23:29:12.014687  02c80000 ################################################################

10248 23:29:12.014828  

10249 23:29:12.265986  02d00000 ################################################################

10250 23:29:12.266166  

10251 23:29:12.527351  02d80000 ################################################################

10252 23:29:12.527519  

10253 23:29:12.772995  02e00000 ################################################################

10254 23:29:12.773143  

10255 23:29:13.014616  02e80000 ################################################################

10256 23:29:13.014792  

10257 23:29:13.257554  02f00000 ################################################################

10258 23:29:13.257741  

10259 23:29:13.523849  02f80000 ################################################################

10260 23:29:13.524023  

10261 23:29:13.789903  03000000 ################################################################

10262 23:29:13.790049  

10263 23:29:14.048472  03080000 ################################################################

10264 23:29:14.048617  

10265 23:29:14.320491  03100000 ################################################################

10266 23:29:14.320659  

10267 23:29:14.588706  03180000 ################################################################

10268 23:29:14.588868  

10269 23:29:14.849833  03200000 ################################################################

10270 23:29:14.849978  

10271 23:29:15.112247  03280000 ################################################################

10272 23:29:15.112413  

10273 23:29:15.404012  03300000 ################################################################

10274 23:29:15.404192  

10275 23:29:15.703385  03380000 ################################################################

10276 23:29:15.703560  

10277 23:29:16.011501  03400000 ################################################################

10278 23:29:16.011680  

10279 23:29:16.321811  03480000 ################################################################

10280 23:29:16.321958  

10281 23:29:16.625106  03500000 ################################################################

10282 23:29:16.625274  

10283 23:29:16.918644  03580000 ################################################################

10284 23:29:16.918787  

10285 23:29:17.193517  03600000 ################################################################

10286 23:29:17.193697  

10287 23:29:17.484414  03680000 ################################################################

10288 23:29:17.484557  

10289 23:29:17.775620  03700000 ################################################################

10290 23:29:17.775765  

10291 23:29:18.039656  03780000 ################################################################

10292 23:29:18.039796  

10293 23:29:18.301794  03800000 ################################################################

10294 23:29:18.301940  

10295 23:29:18.579134  03880000 ################################################################

10296 23:29:18.579278  

10297 23:29:18.854565  03900000 ################################################################

10298 23:29:18.854709  

10299 23:29:19.139267  03980000 ################################################################

10300 23:29:19.139412  

10301 23:29:19.412102  03a00000 ################################################################

10302 23:29:19.412246  

10303 23:29:19.681450  03a80000 ################################################################

10304 23:29:19.681663  

10305 23:29:19.966982  03b00000 ################################################################

10306 23:29:19.967152  

10307 23:29:20.253848  03b80000 ################################################################

10308 23:29:20.254021  

10309 23:29:20.547791  03c00000 ################################################################

10310 23:29:20.547958  

10311 23:29:20.815827  03c80000 ################################################################

10312 23:29:20.815999  

10313 23:29:21.085922  03d00000 ################################################################

10314 23:29:21.086094  

10315 23:29:21.356646  03d80000 ################################################################

10316 23:29:21.356790  

10317 23:29:21.641968  03e00000 ################################################################

10318 23:29:21.642130  

10319 23:29:21.909230  03e80000 ################################################################

10320 23:29:21.909402  

10321 23:29:22.194286  03f00000 ################################################################

10322 23:29:22.194460  

10323 23:29:22.464811  03f80000 ################################################################

10324 23:29:22.464974  

10325 23:29:22.694623  04000000 #################################################### done.

10326 23:29:22.694788  

10327 23:29:22.698237  The bootfile was 67529270 bytes long.

10328 23:29:22.698315  

10329 23:29:22.701463  Sending tftp read request... done.

10330 23:29:22.701565  

10331 23:29:22.704475  Waiting for the transfer... 

10332 23:29:22.704563  

10333 23:29:22.704632  00000000 # done.

10334 23:29:22.704699  

10335 23:29:22.714713  Command line loaded dynamically from TFTP file: 12172428/tftp-deploy-um0a0hli/kernel/cmdline

10336 23:29:22.714818  

10337 23:29:22.727906  The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10338 23:29:22.728033  

10339 23:29:22.728130  Loading FIT.

10340 23:29:22.728220  

10341 23:29:22.730867  Image ramdisk-1 has 56430611 bytes.

10342 23:29:22.731011  

10343 23:29:22.734149  Image fdt-1 has 47278 bytes.

10344 23:29:22.734356  

10345 23:29:22.738177  Image kernel-1 has 11049348 bytes.

10346 23:29:22.738338  

10347 23:29:22.747774  Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion

10348 23:29:22.747880  

10349 23:29:22.764222  Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192

10350 23:29:22.764355  

10351 23:29:22.770594  Choosing best match conf-1 for compat google,spherion-rev2.

10352 23:29:22.770691  

10353 23:29:22.778205  Connected to device vid:did:rid of 1ae0:0028:00

10354 23:29:22.786337  

10355 23:29:22.789469  tpm_get_response: command 0x17b, return code 0x0

10356 23:29:22.789661  

10357 23:29:22.792852  ec_init: CrosEC protocol v3 supported (256, 248)

10358 23:29:22.796625  

10359 23:29:22.800475  tpm_cleanup: add release locality here.

10360 23:29:22.800934  

10361 23:29:22.801307  Shutting down all USB controllers.

10362 23:29:22.804095  

10363 23:29:22.804563  Removing current net device

10364 23:29:22.804999  

10365 23:29:22.810687  Exiting depthcharge with code 4 at timestamp: 69295326

10366 23:29:22.811191  

10367 23:29:22.814352  LZMA decompressing kernel-1 to 0x821a6718

10368 23:29:22.814773  

10369 23:29:22.817294  LZMA decompressing kernel-1 to 0x40000000

10370 23:29:24.205424  

10371 23:29:24.205592  jumping to kernel

10372 23:29:24.206181  end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10373 23:29:24.206286  start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10374 23:29:24.206364  Setting prompt string to ['Linux version [0-9]']
10375 23:29:24.206431  Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10376 23:29:24.206512  auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10377 23:29:24.287363  

10378 23:29:24.290572  [    0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]

10379 23:29:24.294539  start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10380 23:29:24.295125  The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10381 23:29:24.295703  Setting prompt string to []
10382 23:29:24.296299  Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10383 23:29:24.296844  Using line separator: #'\n'#
10384 23:29:24.297327  No login prompt set.
10385 23:29:24.297847  Parsing kernel messages
10386 23:29:24.298264  ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10387 23:29:24.298785  [login-action] Waiting for messages, (timeout 00:03:44)
10388 23:29:24.313737  [    0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec  3 22:38:18 UTC 2023

10389 23:29:24.316914  [    0.000000] random: crng init done

10390 23:29:24.323862  [    0.000000] Machine model: Google Spherion (rev0 - 3)

10391 23:29:24.327026  [    0.000000] efi: UEFI not found.

10392 23:29:24.333277  [    0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB

10393 23:29:24.343167  [    0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool

10394 23:29:24.350099  [    0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB

10395 23:29:24.359752  [    0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool

10396 23:29:24.367030  [    0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')

10397 23:29:24.373472  [    0.000000] printk: bootconsole [mtk8250] enabled

10398 23:29:24.380113  [    0.000000] NUMA: No NUMA configuration found

10399 23:29:24.386594  [    0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]

10400 23:29:24.389676  [    0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]

10401 23:29:24.393029  [    0.000000] Zone ranges:

10402 23:29:24.400038  [    0.000000]   DMA      [mem 0x0000000040000000-0x00000000ffffffff]

10403 23:29:24.403350  [    0.000000]   DMA32    empty

10404 23:29:24.409493  [    0.000000]   Normal   [mem 0x0000000100000000-0x000000023fffffff]

10405 23:29:24.413045  [    0.000000] Movable zone start for each node

10406 23:29:24.416151  [    0.000000] Early memory node ranges

10407 23:29:24.422700  [    0.000000]   node   0: [mem 0x0000000040000000-0x000000004fffffff]

10408 23:29:24.429412  [    0.000000]   node   0: [mem 0x0000000050000000-0x00000000528fffff]

10409 23:29:24.436200  [    0.000000]   node   0: [mem 0x0000000052900000-0x00000000545fffff]

10410 23:29:24.442876  [    0.000000]   node   0: [mem 0x0000000054700000-0x00000000ffdfffff]

10411 23:29:24.449520  [    0.000000]   node   0: [mem 0x0000000100000000-0x000000023fffffff]

10412 23:29:24.455855  [    0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]

10413 23:29:24.512233  [    0.000000] On node 0, zone DMA: 256 pages in unavailable ranges

10414 23:29:24.518783  [    0.000000] On node 0, zone Normal: 512 pages in unavailable ranges

10415 23:29:24.525151  [    0.000000] cma: Reserved 32 MiB at 0x00000000fde00000

10416 23:29:24.528217  [    0.000000] psci: probing for conduit method from DT.

10417 23:29:24.535131  [    0.000000] psci: PSCIv1.1 detected in firmware.

10418 23:29:24.538545  [    0.000000] psci: Using standard PSCI v0.2 function IDs

10419 23:29:24.545250  [    0.000000] psci: MIGRATE_INFO_TYPE not supported.

10420 23:29:24.548300  [    0.000000] psci: SMC Calling Convention v1.2

10421 23:29:24.555075  [    0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016

10422 23:29:24.558260  [    0.000000] Detected VIPT I-cache on CPU0

10423 23:29:24.564452  [    0.000000] CPU features: detected: GIC system register CPU interface

10424 23:29:24.571512  [    0.000000] CPU features: detected: Virtualization Host Extensions

10425 23:29:24.578570  [    0.000000] CPU features: kernel page table isolation forced ON by KASLR

10426 23:29:24.584408  [    0.000000] CPU features: detected: Kernel page table isolation (KPTI)

10427 23:29:24.591376  [    0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009

10428 23:29:24.601373  [    0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923

10429 23:29:24.604756  [    0.000000] alternatives: applying boot alternatives

10430 23:29:24.611126  [    0.000000] Fallback order for Node 0: 0 

10431 23:29:24.618303  [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2063616

10432 23:29:24.621438  [    0.000000] Policy zone: Normal

10433 23:29:24.634448  [    0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1

10434 23:29:24.644467  <5>[    0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.

10435 23:29:24.655730  <6>[    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)

10436 23:29:24.665861  <6>[    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)

10437 23:29:24.672544  <6>[    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off

10438 23:29:24.675483  <6>[    0.000000] software IO TLB: area num 8.

10439 23:29:24.731907  <6>[    0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)

10440 23:29:24.881286  <6>[    0.000000] Memory: 7914448K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 438320K reserved, 32768K cma-reserved)

10441 23:29:24.887850  <6>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1

10442 23:29:24.894174  <6>[    0.000000] rcu: Preemptible hierarchical RCU implementation.

10443 23:29:24.897622  <6>[    0.000000] rcu: 	RCU event tracing is enabled.

10444 23:29:24.904227  <6>[    0.000000] rcu: 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.

10445 23:29:24.911332  <6>[    0.000000] 	Trampoline variant of Tasks RCU enabled.

10446 23:29:24.914662  <6>[    0.000000] 	Tracing variant of Tasks RCU enabled.

10447 23:29:24.924581  <6>[    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.

10448 23:29:24.931042  <6>[    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8

10449 23:29:24.934166  <6>[    0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0

10450 23:29:24.942376  <6>[    0.000000] GICv3: GIC: Using split EOI/Deactivate mode

10451 23:29:24.945280  <6>[    0.000000] GICv3: 608 SPIs implemented

10452 23:29:24.952589  <6>[    0.000000] GICv3: 0 Extended SPIs implemented

10453 23:29:24.955485  <6>[    0.000000] Root IRQ handler: gic_handle_irq

10454 23:29:24.962081  <6>[    0.000000] GICv3: GICv3 features: 16 PPIs

10455 23:29:24.968804  <6>[    0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000

10456 23:29:24.978397  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }

10457 23:29:24.991837  <6>[    0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }

10458 23:29:24.997840  <6>[    0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.

10459 23:29:25.008024  <6>[    0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).

10460 23:29:25.020839  <6>[    0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns

10461 23:29:25.027564  <6>[    0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns

10462 23:29:25.034501  <6>[    0.009235] Console: colour dummy device 80x25

10463 23:29:25.044599  <6>[    0.013959] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)

10464 23:29:25.050963  <6>[    0.024401] pid_max: default: 32768 minimum: 301

10465 23:29:25.054423  <6>[    0.029296] LSM: Security Framework initializing

10466 23:29:25.061473  <6>[    0.034233] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10467 23:29:25.071308  <6>[    0.042048] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)

10468 23:29:25.078016  <6>[    0.051455] cblist_init_generic: Setting adjustable number of callback queues.

10469 23:29:25.084287  <6>[    0.058896] cblist_init_generic: Setting shift to 3 and lim to 1.

10470 23:29:25.094066  <6>[    0.065235] cblist_init_generic: Setting adjustable number of callback queues.

10471 23:29:25.100518  <6>[    0.072662] cblist_init_generic: Setting shift to 3 and lim to 1.

10472 23:29:25.104109  <6>[    0.079102] rcu: Hierarchical SRCU implementation.

10473 23:29:25.110494  <6>[    0.079103] rcu: 	Max phase no-delay instances is 1000.

10474 23:29:25.117181  <6>[    0.079128] printk: bootconsole [mtk8250] printing thread started

10475 23:29:25.124117  <6>[    0.097435] EFI services will not be available.

10476 23:29:25.127175  <6>[    0.097632] smp: Bringing up secondary CPUs ...

10477 23:29:25.130167  <6>[    0.097942] Detected VIPT I-cache on CPU1

10478 23:29:25.140380  <6>[    0.098009] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000

10479 23:29:25.147031  <6>[    0.098043] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]

10480 23:29:25.156759  <6>[    0.125884] Detected VIPT I-cache on CPU2

10481 23:29:25.163227  <6>[    0.125932] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000

10482 23:29:25.169462  <6>[    0.125946] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]

10483 23:29:25.176046  <6>[    0.126201] Detected VIPT I-cache on CPU3

10484 23:29:25.182798  <6>[    0.126246] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000

10485 23:29:25.189242  <6>[    0.126261] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]

10486 23:29:25.192690  <6>[    0.126571] CPU features: detected: Spectre-v4

10487 23:29:25.199550  <6>[    0.126576] CPU features: detected: Spectre-BHB

10488 23:29:25.202819  <6>[    0.126581] Detected PIPT I-cache on CPU4

10489 23:29:25.209358  <6>[    0.126637] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000

10490 23:29:25.216144  <6>[    0.126653] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]

10491 23:29:25.222657  <6>[    0.126947] Detected PIPT I-cache on CPU5

10492 23:29:25.229900  <6>[    0.127006] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000

10493 23:29:25.235999  <6>[    0.127022] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]

10494 23:29:25.239408  <6>[    0.127301] Detected PIPT I-cache on CPU6

10495 23:29:25.246248  <6>[    0.127364] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000

10496 23:29:25.252902  <6>[    0.127380] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]

10497 23:29:25.259364  <6>[    0.127674] Detected PIPT I-cache on CPU7

10498 23:29:25.265782  <6>[    0.127736] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000

10499 23:29:25.272426  <6>[    0.127752] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]

10500 23:29:25.276153  <6>[    0.127799] smp: Brought up 1 node, 8 CPUs

10501 23:29:25.282826  <6>[    0.127803] SMP: Total of 8 processors activated.

10502 23:29:25.285475  <6>[    0.127806] CPU features: detected: 32-bit EL0 Support

10503 23:29:25.295766  <6>[    0.127808] CPU features: detected: Data cache clean to the PoU not required for I/D coherence

10504 23:29:25.302467  <6>[    0.127811] CPU features: detected: Common not Private translations

10505 23:29:25.308929  <6>[    0.127812] CPU features: detected: CRC32 instructions

10506 23:29:25.312389  <6>[    0.127815] CPU features: detected: RCpc load-acquire (LDAPR)

10507 23:29:25.318925  <6>[    0.127816] CPU features: detected: LSE atomic instructions

10508 23:29:25.325491  <6>[    0.127818] CPU features: detected: Privileged Access Never

10509 23:29:25.332153  <6>[    0.127819] CPU features: detected: RAS Extension Support

10510 23:29:25.338823  <6>[    0.127822] CPU features: detected: Speculative Store Bypassing Safe (SSBS)

10511 23:29:25.342405  <6>[    0.127893] CPU: All CPU(s) started at EL2

10512 23:29:25.348434  <6>[    0.127894] alternatives: applying system-wide alternatives

10513 23:29:25.351505  <6>[    0.140998] devtmpfs: initialized

10514 23:29:25.361616  <6>[    0.147157] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns

10515 23:29:25.393786  |��ځ��r�������2�ѕၣ�͡����������ɥ�������Bzɑ��郪b�������ѕͱb����ɥkR�<6>[  <  0.368771] printk: console [ttyS0] printing thread started

10516 23:29:25.399946  6<6>[    0.368800] printk: console [ttyS0] enabled

10517 23:29:25.403115  >[    0.148104] pinctrl core: initialized pinctrl subsystem

10518 23:29:25.410157  <6>[    0.368804] printk: bootconsole [mtk8250] disabled

10519 23:29:25.417214  <6>[    0.384528] printk: bootconsole [mtk8250] printing thread stopped

10520 23:29:25.420521  <6>[    0.385932] SuperH (H)SCI(F) driver initialized

10521 23:29:25.426749  <6>[    0.386428] msm_serial: driver initialized

10522 23:29:25.433678  <6>[    0.391088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000

10523 23:29:25.444032  <6>[    0.391117] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000

10524 23:29:25.450315  <6>[    0.391147] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000

10525 23:29:25.461660  <6>[    0.391176] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000

10526 23:29:25.468177  <6>[    0.391198] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000

10527 23:29:25.487256  <6>[    0.391225] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000

10528 23:29:25.491850  <6>[    0.391254] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000

10529 23:29:25.503950  <6>[    0.391376] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000

10530 23:29:25.508857  <6>[    0.391407] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000

10531 23:29:25.509448  <6>[    0.400068] loop: module loaded

10532 23:29:25.514060  <6>[    0.402586] vgpu11_sshub: Bringing 400000uV into 575000-575000uV

10533 23:29:25.518363  <4>[    0.427459] mtk-pmic-keys: Failed to locate of_node [id: -1]

10534 23:29:25.521981  <6>[    0.428386] megasas: 07.719.03.00-rc1

10535 23:29:25.530020  <6>[    0.440581] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2

10536 23:29:25.533568  <6>[    0.441401] spi-nor spi2.0: w25q64jwm (8192 Kbytes)

10537 23:29:25.539971  <6>[    0.452873] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)

10538 23:29:25.553249  <6>[    0.507643] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b

10539 23:29:27.653715  <6>[    2.628070] Freeing initrd memory: 55104K

10540 23:29:27.661758  <6>[    2.634308] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz

10541 23:29:27.668460  <6>[    2.639107] tun: Universal TUN/TAP device driver, 1.6

10542 23:29:27.671984  <6>[    2.639875] thunder_xcv, ver 1.0

10543 23:29:27.675434  <6>[    2.639895] thunder_bgx, ver 1.0

10544 23:29:27.678399  <6>[    2.639909] nicpf, ver 1.0

10545 23:29:27.684771  <6>[    2.640955] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version

10546 23:29:27.691439  <6>[    2.640958] hns3: Copyright (c) 2017 Huawei Corporation.

10547 23:29:27.694933  <6>[    2.640986] hclge is initializing

10548 23:29:27.702133  <6>[    2.641005] e1000: Intel(R) PRO/1000 Network Driver

10549 23:29:27.705477  <6>[    2.641007] e1000: Copyright (c) 1999-2006 Intel Corporation.

10550 23:29:27.712252  <6>[    2.641024] e1000e: Intel(R) PRO/1000 Network Driver

10551 23:29:27.716164  <6>[    2.641026] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.

10552 23:29:27.722874  <6>[    2.641043] igb: Intel(R) Gigabit Ethernet Network Driver

10553 23:29:27.729691  <6>[    2.641045] igb: Copyright (c) 2007-2014 Intel Corporation.

10554 23:29:27.736500  <6>[    2.641061] igbvf: Intel(R) Gigabit Virtual Function Network Driver

10555 23:29:27.740051  <6>[    2.641063] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.

10556 23:29:27.746455  <6>[    2.641368] sky2: driver version 1.30

10557 23:29:27.749928  <6>[    2.642432] VFIO - User Level meta-driver version: 0.3

10558 23:29:27.756174  <6>[    2.645221] usbcore: registered new interface driver usb-storage

10559 23:29:27.763365  <6>[    2.645406] usbcore: registered new device driver onboard-usb-hub

10560 23:29:27.770116  <6>[    2.648186] mt6397-rtc mt6359-rtc: registered as rtc0

10561 23:29:27.776595  <6>[    2.648339] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:27:13 UTC (1701646033)

10562 23:29:27.782776  <6>[    2.648950] i2c_dev: i2c /dev entries driver

10563 23:29:27.789511  <6>[    2.656132] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)

10564 23:29:27.795901  <6>[    2.671121] cpu cpu0: EM: created perf domain

10565 23:29:27.799645  <6>[    2.671440] cpu cpu4: EM: created perf domain

10566 23:29:27.806011  <6>[    2.675413] sdhci: Secure Digital Host Controller Interface driver

10567 23:29:27.809269  <6>[    2.675414] sdhci: Copyright(c) Pierre Ossman

10568 23:29:27.816444  <6>[    2.675764] Synopsys Designware Multimedia Card Interface Driver

10569 23:29:27.822525  <6>[    2.676156] sdhci-pltfm: SDHCI platform and OF driver helper

10570 23:29:27.829178  <6>[    2.680459] ledtrig-cpu: registered to indicate activity on CPUs

10571 23:29:27.832669  <6>[    2.680832] mmc0: CQHCI version 5.10

10572 23:29:27.839025  <6>[    2.681448] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000

10573 23:29:27.845747  <6>[    2.681726] usbcore: registered new interface driver usbhid

10574 23:29:27.849413  <6>[    2.681727] usbhid: USB HID core driver

10575 23:29:27.855638  <6>[    2.681839] spi_master spi0: will run message pump with realtime priority

10576 23:29:27.869279  <6>[    2.710595] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0

10577 23:29:27.882572  <6>[    2.713465] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1

10578 23:29:27.888975  <6>[    2.714465] cros-ec-spi spi0.0: Chrome EC device registered

10579 23:29:27.898693  <6>[    2.732294] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)

10580 23:29:27.902088  <6>[    2.734551] NET: Registered PF_PACKET protocol family

10581 23:29:27.908672  <6>[    2.734646] 9pnet: Installing 9P2000 support

10582 23:29:27.911759  <5>[    2.734685] Key type dns_resolver registered

10583 23:29:27.915257  <6>[    2.734995] registered taskstats version 1

10584 23:29:27.922367  <5>[    2.735011] Loading compiled-in X.509 certificates

10585 23:29:27.932011  <4>[    2.758372] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10586 23:29:27.942328  <4>[    2.758633] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator

10587 23:29:27.948839  <3>[    2.758654] debugfs: File 'uA_load' in directory '/' already present!

10588 23:29:27.955115  <3>[    2.758666] debugfs: File 'min_uV' in directory '/' already present!

10589 23:29:27.961773  <3>[    2.758673] debugfs: File 'max_uV' in directory '/' already present!

10590 23:29:27.968530  <3>[    2.758680] debugfs: File 'constraint_flags' in directory '/' already present!

10591 23:29:27.978513  <3>[    2.762375] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)

10592 23:29:27.985133  <6>[    2.770961] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102

10593 23:29:27.989018  <6>[    2.771593] xhci-mtk 11200000.usb: xHCI Host Controller

10594 23:29:27.998282  <6>[    2.771603] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1

10595 23:29:28.008314  <6>[    2.771789] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010

10596 23:29:28.011695  <6>[    2.771826] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000

10597 23:29:28.017968  <6>[    2.771892] xhci-mtk 11200000.usb: xHCI Host Controller

10598 23:29:28.024546  <6>[    2.771895] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2

10599 23:29:28.034453  <6>[    2.771900] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed

10600 23:29:28.037985  <6>[    2.772155] hub 1-0:1.0: USB hub found

10601 23:29:28.041093  <6>[    2.772166] hub 1-0:1.0: 1 port detected

10602 23:29:28.051011  <6>[    2.772261] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.

10603 23:29:28.054300  <6>[    2.772404] hub 2-0:1.0: USB hub found

10604 23:29:28.057761  <6>[    2.772411] hub 2-0:1.0: 1 port detected

10605 23:29:28.061278  <6>[    2.775208] mtk-msdc 11f70000.mmc: Got CD GPIO

10606 23:29:28.067651  <6>[    2.775249] mmc0: Command Queue Engine enabled

10607 23:29:28.074233  <6>[    2.775262] mmc0: new HS400 Enhanced strobe MMC card at address 0001

10608 23:29:28.077888  <6>[    2.775972] mmcblk0: mmc0:0001 DA4128 116 GiB 

10609 23:29:28.084094  <6>[    2.780295]  mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12

10610 23:29:28.090974  <6>[    2.782143] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB 

10611 23:29:28.094228  <6>[    2.783434] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB 

10612 23:29:28.101078  <6>[    2.784555] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)

10613 23:29:28.110734  <6>[    2.785221] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()

10614 23:29:28.117224  <6>[    2.785230] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()

10615 23:29:28.127157  <4>[    2.785330] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW

10616 23:29:28.133883  <6>[    2.785826] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()

10617 23:29:28.140821  <6>[    2.785828] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()

10618 23:29:28.151117  <6>[    2.785953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()

10619 23:29:28.157008  <6>[    2.785959] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()

10620 23:29:28.167371  <6>[    2.785961] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()

10621 23:29:28.173939  <6>[    2.785965] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39

10622 23:29:28.183607  <6>[    2.787119] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)

10623 23:29:28.190344  <6>[    2.787135] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)

10624 23:29:28.200329  <6>[    2.787138] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)

10625 23:29:28.206672  <6>[    2.787141] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)

10626 23:29:28.216640  <6>[    2.787145] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)

10627 23:29:28.223354  <6>[    2.787149] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)

10628 23:29:28.233549  <6>[    2.787153] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)

10629 23:29:28.239829  <6>[    2.787157] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)

10630 23:29:28.249794  <6>[    2.787160] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)

10631 23:29:28.259832  <6>[    2.787164] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)

10632 23:29:28.266834  <6>[    2.787167] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)

10633 23:29:28.276218  <6>[    2.787171] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)

10634 23:29:28.282987  <6>[    2.787174] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)

10635 23:29:28.293102  <6>[    2.787177] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)

10636 23:29:28.299854  <6>[    2.787181] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)

10637 23:29:28.306000  <6>[    2.787478] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0

10638 23:29:28.312772  <6>[    2.788063] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0

10639 23:29:28.319362  <6>[    2.788295] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0

10640 23:29:28.326260  <6>[    2.788531] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0

10641 23:29:28.332780  <6>[    2.788765] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0

10642 23:29:28.342404  <6>[    2.788916] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)

10643 23:29:28.352196  <6>[    2.788925] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)

10644 23:29:28.358676  <6>[    2.788927] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)

10645 23:29:28.368611  <6>[    2.788930] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)

10646 23:29:28.378834  <6>[    2.788933] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)

10647 23:29:28.388688  <6>[    2.788936] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)

10648 23:29:28.398444  <6>[    2.788938] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)

10649 23:29:28.408490  <6>[    2.788941] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)

10650 23:29:28.415383  <6>[    2.788943] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)

10651 23:29:28.425096  <6>[    2.788947] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing

10652 23:29:28.437894  <6>[    2.788950] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing

10653 23:29:28.444601  <6>[    2.789977] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0

10654 23:29:28.451343  <6>[    3.153520] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk

10655 23:29:28.454363  <6>[    3.180003] hub 2-1:1.0: USB hub found

10656 23:29:28.461253  <6>[    3.180300] hub 2-1:1.0: 3 ports detected

10657 23:29:28.464371  <6>[    3.182021] hub 2-1:1.0: USB hub found

10658 23:29:28.467977  <6>[    3.182321] hub 2-1:1.0: 3 ports detected

10659 23:29:28.474261  <6>[    3.301299] usb 1-1: new high-speed USB device number 2 using xhci-mtk

10660 23:29:28.477917  <6>[    3.453979] hub 1-1:1.0: USB hub found

10661 23:29:28.484497  <6>[    3.454370] hub 1-1:1.0: 4 ports detected

10662 23:29:28.487685  <6>[    3.458321] hub 1-1:1.0: USB hub found

10663 23:29:28.491174  <6>[    3.458729] hub 1-1:1.0: 4 ports detected

10664 23:29:28.561181  <6>[    3.529689] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk

10665 23:29:28.800960  <6>[    3.769470] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk

10666 23:29:28.925877  <6>[    3.897344] hub 1-1.4:1.0: USB hub found

10667 23:29:28.929042  <6>[    3.897786] hub 1-1.4:1.0: 2 ports detected

10668 23:29:28.932447  <6>[    3.901859] hub 1-1.4:1.0: USB hub found

10669 23:29:28.938972  <6>[    3.902210] hub 1-1.4:1.0: 2 ports detected

10670 23:29:29.221006  <6>[    4.189439] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk

10671 23:29:29.405109  <6>[    4.373444] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk

10672 23:29:40.129285  <6>[   15.106264] ALSA device list:

10673 23:29:40.135950  <6>[   15.106286]   No soundcards found.

10674 23:29:40.139121  <6>[   15.110678] Freeing unused kernel memory: 8448K

10675 23:29:40.142646  <6>[   15.110825] Run /init as init process

10676 23:29:40.180901  <6>[   15.153886] NET: Registered PF_INET6 protocol family

10677 23:29:40.183986  <6>[   15.155114] Segment Routing with IPv6

10678 23:29:40.187511  

10679 23:29:40.193775  Welcome to Debian GNU/Linu<6>[   15.155129] In-situ OAM (IOAM) with IPv6

10680 23:29:40.217328  x 11 (bullseye)<30>[   15.166661] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)

10681 23:29:40.217427  [0m!

10682 23:29:40.217494  

10683 23:29:40.223656  <30>[   15.167067] systemd[1]: Detected architecture arm64.

10684 23:29:40.232728  <30>[   15.205159] systemd[1]: Set hostname to <debian-bullseye-arm64>.

10685 23:29:40.363851  <30>[   15.336720] systemd[1]: Queued start job for default target Graphical Interface.

10686 23:29:40.393060  [  OK  ] Created slice syste<30>[   15.366204] systemd[1]: Created slice system-getty.slice.

10687 23:29:40.396387  m-getty.slice.

10688 23:29:40.419711  [  OK  ] Created slice syste<30>[   15.390013] systemd[1]: Created slice system-modprobe.slice.

10689 23:29:40.419803  m-modprobe.slice.

10690 23:29:40.441523  [  OK  ] Created slic<30>[   15.414839] systemd[1]: Created slice system-serial\x2dgetty.slice.

10691 23:29:40.448359  e system-serial\x2dgetty.slice.

10692 23:29:40.468193  [  OK  ] Created slice User <30>[   15.438294] systemd[1]: Created slice User and Session Slice.

10693 23:29:40.468281  and Session Slice.

10694 23:29:40.492510  [  OK  ] Started [0;<30>[   15.462254] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.

10695 23:29:40.496073  1;39mDispatch Password …ts to Console Directory Watch.

10696 23:29:40.520193  [  OK  ] Started Forward Pas<30>[   15.490194] systemd[1]: Started Forward Password Requests to Wall Directory Watch.

10697 23:29:40.523591  sword R…uests to Wall Directory Watch.

10698 23:29:40.551061  [  OK  ] Reached target Loca<30>[   15.517520] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.

10699 23:29:40.561162  l Encrypted Volu<30>[   15.517716] systemd[1]: Reached target Local Encrypted Volumes.

10700 23:29:40.561250  mes.

10701 23:29:40.580833  [  OK  ] Reached target Path<30>[   15.553933] systemd[1]: Reached target Paths.

10702 23:29:40.580921  s.

10703 23:29:40.603489  [  OK  ] Reached target Remo<30>[   15.573431] systemd[1]: Reached target Remote File Systems.

10704 23:29:40.603581  te File Systems.

10705 23:29:40.620503  [  OK  ] Reached target Slic<30>[   15.593436] systemd[1]: Reached target Slices.

10706 23:29:40.620591  es.

10707 23:29:40.639990  [  OK  ] Reached target Swap<30>[   15.613441] systemd[1]: Reached target Swap.

10708 23:29:40.640076  .

10709 23:29:40.664062  [  OK  ] Listening on initct<30>[   15.633926] systemd[1]: Listening on initctl Compatibility Named Pipe.

10710 23:29:40.667407  l Compatibility Named Pipe.

10711 23:29:40.673867  [  OK  [<30>[   15.649036] systemd[1]: Listening on Journal Audit Socket.

10712 23:29:40.680374  0m] Listening on Journal Audit Socket.

10713 23:29:40.697463  [  OK  ] Listening on<30>[   15.670613] systemd[1]: Listening on Journal Socket (/dev/log).

10714 23:29:40.701073   Journal Socket (/dev/log).

10715 23:29:40.721745  [  OK  ] Listening on<30>[   15.694702] systemd[1]: Listening on Journal Socket.

10716 23:29:40.725099   Journal Socket.

10717 23:29:40.740747  [  OK  ] Listening on udev C<30>[   15.713987] systemd[1]: Listening on udev Control Socket.

10718 23:29:40.743687  ontrol Socket.

10719 23:29:40.765737  [  OK  ] Listening on<30>[   15.738454] systemd[1]: Listening on udev Kernel Socket.

10720 23:29:40.768494   udev Kernel Socket.

10721 23:29:40.832053           Mounting Huge Pages File Syste<30>[   15.801639] systemd[1]: Mounting Huge Pages File System...

10722 23:29:40.832172  m...

10723 23:29:40.851090           Mountin<30>[   15.824298] systemd[1]: Mounting POSIX Message Queue File System...

10724 23:29:40.854246  g POSIX Message Queue File System...

10725 23:29:40.872578  <30>[   15.849026] systemd[1]: Mounting Kernel Debug File System...

10726 23:29:40.879434           Mounting Kernel Debug File System...

10727 23:29:40.900213  <30>[   15.869694] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.

10728 23:29:40.909970  <30>[   15.873965] systemd[1]: Starting Create list of static device nodes for the current kernel...

10729 23:29:40.916381           Starting Create list of st…odes for the current kernel...

10730 23:29:40.943738           Starting Load Kernel Module co<30>[   15.913854] systemd[1]: Starting Load Kernel Module configfs...

10731 23:29:40.943830  nfigfs...

10732 23:29:40.967567           Starting Load Kernel Module dr<30>[   15.937527] systemd[1]: Starting Load Kernel Module drm...

10733 23:29:40.967655  m...

10734 23:29:40.987709  <30>[   15.957558] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.

10735 23:29:41.016876           Starting Journal Service..<30>[   15.989826] systemd[1]: Starting Journal Service...

10736 23:29:41.016971  .

10737 23:29:41.039463           Startin<30>[   16.012461] systemd[1]: Starting Load Kernel Modules...

10738 23:29:41.042823  g Load Kernel Modules...

10739 23:29:41.065542           Starting Remou<30>[   16.038302] systemd[1]: Starting Remount Root and Kernel File Systems...

10740 23:29:41.072274  nt Root and Kernel File Systems...

10741 23:29:41.088339  <30>[   16.065100] systemd[1]: Starting Coldplug All udev Devices...

10742 23:29:41.095278           Starting Coldplug All udev Devices...

10743 23:29:41.117407  [  OK  ] Started [0;<30>[   16.090507] systemd[1]: Started Journal Service.

10744 23:29:41.120302  1;39mJournal Service.

10745 23:29:41.134570  [  OK  ] Mounted Huge Pages File System.

10746 23:29:41.150339  [  OK  ] Mounted POSIX Message Queue File System.

10747 23:29:41.166833  [  OK  ] Mounted Kernel Debug File System.

10748 23:29:41.185485  [  OK  ] Finished Create list of st… nodes for the current kernel.

10749 23:29:41.206984  [  OK  ] Finished Load Kernel Module configfs.

10750 23:29:41.227018  [  OK  ] Finished Load Kernel Module drm.

10751 23:29:41.246116  [  OK  ] Finished Load Kernel Modules.

10752 23:29:41.266964  [FAILED] Failed to start Remount Root and Kernel File Systems.

10753 23:29:41.281132  See 'systemctl status systemd-remount-fs.service' for details.

10754 23:29:41.320721           Mounting Kernel Configuration File System...

10755 23:29:41.341546           Starting Flush Journal to Persistent Storage...

10756 23:29:41.355755  <46>[   16.328254] systemd-journald[194]: Received client request to flush runtime journal.

10757 23:29:41.365652           Starting Load/Save Random Seed...

10758 23:29:41.385538           Starting Apply Kernel Variables...

10759 23:29:41.406316           Starting Create System Users...

10760 23:29:41.430392  [  OK  ] Finished Coldplug All udev Devices.

10761 23:29:41.449491  [  OK  ] Mounted Kernel Configuration File System.

10762 23:29:41.473714  [  OK  ] Finished Flush Journal to Persistent Storage.

10763 23:29:41.490361  [  OK  ] Finished Load/Save Random Seed.

10764 23:29:41.506485  [  OK  ] Finished Apply Kernel Variables.

10765 23:29:41.522271  [  OK  ] Finished Create System Users.

10766 23:29:41.561455           Starting Create Static Device Nodes in /dev...

10767 23:29:41.583111  [  OK  ] Finished Create Static Device Nodes in /dev.

10768 23:29:41.597105  [  OK  ] Reached target Local File Systems (Pre).

10769 23:29:41.616606  [  OK  ] Reached target Local File Systems.

10770 23:29:41.673458           Starting Create Volatile Files and Directories...

10771 23:29:41.701376           Starting Rule-based Manage…for Device Events and Files...

10772 23:29:41.723408  [  OK  ] Started Rule-based Manager for Device Events and Files.

10773 23:29:41.748688  [  OK  ] Finished Create Volatile Files and Directories.

10774 23:29:41.786549           Starting Network Time Synchronization...

10775 23:29:41.806576           Starting Update UTMP about System Boot/Shutdown...

10776 23:29:41.849020  [  OK  ] Finished Update UTMP about System Boot/Shutdown.

10777 23:29:41.868595  [  OK  ] Started Network Time Synchronization.

10778 23:29:41.901780  [  OK  ] Created slice system-systemd\x2dbacklight.slice.

10779 23:29:41.915432  <6>[   16.888798] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:

10780 23:29:41.925499  <6>[   16.888828] mtk-pcie-gen3 11230000.pcie:      MEM 0x0012000000..0x00127fffff -> 0x0012000000

10781 23:29:41.935855  <6>[   16.888834] mtk-pcie-gen3 11230000.pcie:       IO 0x0012800000..0x0012ffffff -> 0x0012800000

10782 23:29:41.942284  [  OK  ] Reached target System Time Set.

10783 23:29:41.948854  <6>[   16.923736] usbcore: registered new interface driver r8152

10784 23:29:41.955459  <4>[   16.925734] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator

10785 23:29:41.962173  <4>[   16.925885] elants_i2c 4-0010: supply vccio not found, using dummy regulator

10786 23:29:41.968936  [  OK  ] Reached target System Time Synchronized.

10787 23:29:42.024088  <3>[   16.996726] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10788 23:29:42.033729  <3>[   16.996776] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10789 23:29:42.040012  <3>[   16.996786] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10790 23:29:42.046687           Startin<6>[   16.997057] mc: Linux media interface: v0.10

10791 23:29:42.056756  g Load/<3>[   17.011899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10792 23:29:42.066530  Save Screen …o<3>[   17.011922] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10793 23:29:42.076421  f leds:white:kbd<3>[   17.011925] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10794 23:29:42.083475  _backlight..<3>[   17.011930] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10795 23:29:42.083559  .

10796 23:29:42.092822  <3>[   17.011933] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10797 23:29:42.099750  <3>[   17.013335] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0

10798 23:29:42.109666  <3>[   17.013504] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10799 23:29:42.115750  <3>[   17.013515] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10800 23:29:42.129867  [  OK  ] Finished [0<3>[   17.013526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10801 23:29:42.136314  <3>[   17.013634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10802 23:29:42.146328  ;1;39mLoad/Save <3>[   17.013642] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10803 23:29:42.153062  <3>[   17.013649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10804 23:29:42.163065  Screen …s of l<3>[   17.013657] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10805 23:29:42.170073  <3>[   17.013664] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10806 23:29:42.180277  <3>[   17.013702] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1

10807 23:29:42.187277  <6>[   17.020752] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00

10808 23:29:42.193852  <6>[   17.020796] pci_bus 0000:00: root bus resource [bus 00-ff]

10809 23:29:42.200561  <6>[   17.020806] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]

10810 23:29:42.210811  <6>[   17.020811] pci_bus 0000:00: root bus resource [io  0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])

10811 23:29:42.216974  <6>[   17.020892] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400

10812 23:29:42.223942  <6>[   17.020928] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]

10813 23:29:42.227180  <6>[   17.021049] pci 0000:00:00.0: supports D1 D2

10814 23:29:42.233897  <6>[   17.021052] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10815 23:29:42.240419  <6>[   17.024222] videodev: Linux video capture interface: v2.00

10816 23:29:42.247167  <6>[   17.041200] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring

10817 23:29:42.257240  eds:white:kbd_ba<6>[   17.047372] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk

10818 23:29:42.263961  <6>[   17.048269] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000

10819 23:29:42.270705  <6>[   17.048300] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]

10820 23:29:42.277557  <6>[   17.048320] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]

10821 23:29:42.287069  <6>[   17.048334] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]

10822 23:29:42.290399  <6>[   17.048449] pci 0000:01:00.0: supports D1 D2

10823 23:29:42.297642  <6>[   17.048451] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold

10824 23:29:42.307011  <6>[   17.052362] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2

10825 23:29:42.307096  cklight.

10826 23:29:42.314311  <6>[   17.052463] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered

10827 23:29:42.323777  <6>[   17.069746] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003

10828 23:29:42.334089  <6>[   17.073755] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3

10829 23:29:42.341359  <6>[   17.075501] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01

10830 23:29:42.352069  [  OK  ] Found device<6>[   17.075659] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]

10831 23:29:42.361904   /dev/t<6>[   17.075675] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]

10832 23:29:42.361992  tyS0.

10833 23:29:42.369571  <6>[   17.075745] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]

10834 23:29:42.379738  <6>[   17.075766] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]

10835 23:29:42.386620  <6>[   17.075794] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]

10836 23:29:42.393580  <6>[   17.075811] pci 0000:00:00.0: PCI bridge to [bus 01]

10837 23:29:42.400166  <6>[   17.075827] pci 0000:00:00.0:   bridge window [mem 0x12000000-0x121fffff 64bit pref]

10838 23:29:42.407525  <4>[   17.075959] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2

10839 23:29:42.418125  <4>[   17.075969] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)

10840 23:29:42.424715  <6>[   17.078885] pcieport 0000:00:00.0: enabling device (0000 -> 0002)

10841 23:29:42.428032  <6>[   17.099802] usbcore: registered new interface driver cdc_ether

10842 23:29:42.438377  <4>[   17.104022] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.

10843 23:29:42.441602  <4>[   17.104022] Fallback method does not support PEC.

10844 23:29:42.451569  <6>[   17.104453] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000

10845 23:29:42.455492  <6>[   17.114078] remoteproc remoteproc0: scp is available

10846 23:29:42.459600  <6>[   17.114414] remoteproc remoteproc0: powering up scp

10847 23:29:42.469258  <6>[   17.114432] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164

10848 23:29:42.476326  <6>[   17.114489] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0

10849 23:29:42.479684  [  OK  [<6>[   17.137346] r8152 2-1.3:1.0 eth0: v1.12.13

10850 23:29:42.489684  0m] Reached targ<3>[   17.149463] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10851 23:29:42.496959  et Blue<6>[   17.154201] Bluetooth: Core ver 2.22

10852 23:29:42.497084  tooth.

10853 23:29:42.503830  <6>[   17.154640] NET: Registered PF_BLUETOOTH protocol family

10854 23:29:42.507361  <6>[   17.154649] Bluetooth: HCI device and connection manager initialized

10855 23:29:42.514219  <6>[   17.154670] Bluetooth: HCI socket layer initialized

10856 23:29:42.521164  [  OK  [<6>[   17.154675] Bluetooth: L2CAP socket layer initialized

10857 23:29:42.528224  0m] Reached targ<6>[   17.154691] Bluetooth: SCO socket layer initialized

10858 23:29:42.535020  <6>[   17.156773] usbcore: registered new interface driver r8153_ecm

10859 23:29:42.541526  <6>[   17.162248] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)

10860 23:29:42.548053  <3>[   17.178164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10861 23:29:42.557865  et Syst<6>[   17.183178] pcieport 0000:00:00.0: PME: Signaling with IRQ 281

10862 23:29:42.567946  <6>[   17.192104] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4

10863 23:29:42.574643  <6>[   17.194908] pcieport 0000:00:00.0: AER: enabled with IRQ 281

10864 23:29:42.580945  <6>[   17.207477] usbcore: registered new interface driver uvcvideo

10865 23:29:42.587663  <6>[   17.231953] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0

10866 23:29:42.594498  <6>[   17.240510] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e

10867 23:29:42.604502  <6>[   17.240511] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd

10868 23:29:42.607566  <6>[   17.240551] remoteproc remoteproc0: remote processor scp is now up

10869 23:29:42.617701  <3>[   17.248024] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10870 23:29:42.627813  <4>[   17.272731] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2

10871 23:29:42.633811  <3>[   17.272820] Bluetooth: hci0: Failed to load firmware file (-2)

10872 23:29:42.640730  <3>[   17.272827] Bluetooth: hci0: Failed to set up firmware (-2)

10873 23:29:42.650932  <4>[   17.272837] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.

10874 23:29:42.657343  <6>[   17.275782] usbcore: registered new interface driver btusb

10875 23:29:42.664094  <6>[   17.284863] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0

10876 23:29:42.670291  <6>[   17.298516] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected

10877 23:29:42.680584  <6>[   17.300223] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered

10878 23:29:42.687504  <3>[   17.323689] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10879 23:29:42.697351  <3>[   17.326286] power_supply sbs-5-000b: driver failed to report `capacity' property: -6

10880 23:29:42.703909  <3>[   17.333312] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10881 23:29:42.713807  <3>[   17.352393] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10882 23:29:42.723734  <3>[   17.374768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10883 23:29:42.730321  <3>[   17.395211] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10884 23:29:42.740141  <3>[   17.418945] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5

10885 23:29:42.747105  <5>[   17.507522] cfg80211: Loading compiled-in X.509 certificates for regulatory database

10886 23:29:42.753389  <5>[   17.520512] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'

10887 23:29:42.763208  <4>[   17.520582] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2

10888 23:29:42.769887  <6>[   17.520588] cfg80211: failed to load regulatory.db

10889 23:29:42.776632  <6>[   17.627219] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000

10890 23:29:42.783401  <6>[   17.627321] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)

10891 23:29:42.786777  <6>[   17.645363] mt7921e 0000:01:00.0: ASIC revision: 79610010

10892 23:29:42.799831  <4>[   17.745413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10893 23:29:42.799917  em Initialization.

10894 23:29:42.820043  [  OK  ] Started Discard unused blocks once a week.

10895 23:29:42.839895  [  OK  ] Started Daily Cleanup of Temporary Directories.

10896 23:29:42.856605  [  OK  ] Reached target Timers.

10897 23:29:42.887342  [  OK  ] Listening on D-Bus <4>[   17.855885] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10898 23:29:42.890560  System Message Bus Socket.

10899 23:29:42.904425  [  OK  ] Reached target Sockets.

10900 23:29:42.920613  [  OK  ] Reached target Basic System.

10901 23:29:42.940403  [  OK  ] Listening on Load/Save RF …itch Status /dev/rfkill Watch.

10902 23:29:42.983143  <4>[   17.951209] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10903 23:29:42.990145  [  OK  ] Started D-Bus System Message Bus.

10904 23:29:43.065391           Starting User Login Management...

10905 23:29:43.091374  <4>[   18.060111] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10906 23:29:43.098029           Starting Permit User Sessions...

10907 23:29:43.114736  [  OK  ] Finished Permit User Sessions.

10908 23:29:43.140001  [  OK  ] Started Getty on tty1.

10909 23:29:43.199257  <4>[   18.167842] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10910 23:29:43.206783  [  OK  ] Started Serial Getty on ttyS0.

10911 23:29:43.225199  [  OK  ] Reached target Login Prompts.

10912 23:29:43.245628           Starting Load/Save RF Kill Switch Status...

10913 23:29:43.261572  [  OK  ] Started Load/Save RF Kill Switch Status.

10914 23:29:43.281542  [  OK  ] Started User Login Management.

10915 23:29:43.292154  [  OK  ] Reached target Multi-User System.

10916 23:29:43.309046  <4>[   18.276440] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10917 23:29:43.315566  [  OK  ] Reached target Graphical Interface.

10918 23:29:43.362839           Starting Update UTMP about System Runlevel Changes...

10919 23:29:43.403928  [  OK  ] Finished Update UTMP about System Runlevel Changes.

10920 23:29:43.413766  <4>[   18.384056] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10921 23:29:43.443230  

10922 23:29:43.443321  

10923 23:29:43.446809  Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0

10924 23:29:43.446891  

10925 23:29:43.450035  debian-bullseye-arm64 login: root (automatic login)

10926 23:29:43.450117  

10927 23:29:43.450182  

10928 23:29:43.480959  Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec  3 22:38:18 UTC 2023 aarch64

10929 23:29:43.481065  

10930 23:29:43.487784  The programs included with the Debian GNU/Linux system are free software;

10931 23:29:43.494892  the exact distribution terms for each program are described in the

10932 23:29:43.497487  individual files in /usr/share/doc/*/copyright.

10933 23:29:43.497621  

10934 23:29:43.504160  Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent

10935 23:29:43.507739  permitted by applicable law.

10936 23:29:43.508133  Matched prompt #10: / #
10938 23:29:43.508340  Setting prompt string to ['/ #']
10939 23:29:43.508459  end: 2.2.5.1 login-action (duration 00:00:19) [common]
10941 23:29:43.508651  end: 2.2.5 auto-login-action (duration 00:00:19) [common]
10942 23:29:43.508738  start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10943 23:29:43.508807  Setting prompt string to ['/ #']
10944 23:29:43.508867  Forcing a shell prompt, looking for ['/ #']
10946 23:29:43.559085  / # 

10947 23:29:43.559209  expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10948 23:29:43.559288  Waiting using forced prompt support (timeout 00:02:30)
10949 23:29:43.559393  <4>[   18.491682] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10950 23:29:43.563950  

10951 23:29:43.564224  end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10952 23:29:43.564316  start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10953 23:29:43.564482  end: 2.2.7 export-device-env (duration 00:00:00) [common]
10954 23:29:43.564620  end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10955 23:29:43.564707  end: 2 depthcharge-action (duration 00:01:36) [common]
10956 23:29:43.564796  start: 3 lava-test-retry (timeout 00:08:01) [common]
10957 23:29:43.564884  start: 3.1 lava-test-shell (timeout 00:08:01) [common]
10958 23:29:43.564958  Using namespace: common
10960 23:29:43.665292  / # #

10961 23:29:43.665433  lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10962 23:29:43.665549  #<4>[   18.599851] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10963 23:29:43.670693  

10964 23:29:43.670959  Using /lava-12172428
10966 23:29:43.771297  / # export SHELL=/bin/sh

10967 23:29:43.771482  export SHELL=/bin/sh<4>[   18.707500] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2

10968 23:29:43.776428  

10970 23:29:43.876955  / # . /lava-12172428/environment

10971 23:29:43.877132  . /lava-12172428/environment<3>[   18.813487] mt7921e 0000:01:00.0: hardware init failed

10972 23:29:43.881880  

10974 23:29:43.982440  / # /lava-12172428/bin/lava-test-runner /lava-12172428/0

10975 23:29:43.982578  Test shell timeout: 10s (minimum of the action and connection timeout)
10976 23:29:43.988028  /lava-12172428/bin/lava-test-runner /lava-12172428/0

10977 23:29:44.010729  + export TESTRUN_ID=0_igt-kms-mediatek

10978 23:29:44.020832  + cd /lava-12172428/0/tests/0_igt-kms-me<8>[   18.990017] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 12172428_1.5.2.3.1>

10979 23:29:44.020927  diatek

10980 23:29:44.021029  + cat uuid

10981 23:29:44.021267  Received signal: <STARTRUN> 0_igt-kms-mediatek 12172428_1.5.2.3.1
10982 23:29:44.021339  Starting test lava.0_igt-kms-mediatek (12172428_1.5.2.3.1)
10983 23:29:44.021469  Skipping test definition patterns.
10984 23:29:44.024332  + UUID=12172428_1.5.2.3.1

10985 23:29:44.024415  + set +x

10986 23:29:44.034280  + IGT_FORCE_DRIVER=mediatek /usr/bin/ig<8>[   19.006201] <LAVA_SIGNAL_TESTSET START core_auth>

10987 23:29:44.034536  Received signal: <TESTSET> START core_auth
10988 23:29:44.034614  Starting test_set core_auth
10989 23:29:44.053403  t-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic kms_flip_event_leak kms_prop_blob kms_setmode kms_<14>[   19.027746] [IGT] core_auth: executing

10990 23:29:44.053493  vblank

10991 23:29:44.060086  IGT-Vers<14>[   19.028006] [IGT] core_auth: starting subtest getclient-simple

10992 23:29:44.067023  ion: 1.27.1-g621<14>[   19.028176] [IGT] core_auth: finished subtest getclient-simple, SUCCESS

10993 23:29:44.073375  c2d3 (aarch64) (<14>[   19.028286] [IGT] core_auth: exiting, ret=0

10994 23:29:44.083291  Linux: 6.1.64-ci<8>[   19.034157] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>

10995 23:29:44.083375  p10-rt5 aarch64)

10996 23:29:44.083612  Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
10998 23:29:44.086858  Starting subtest: getclient-simple

10999 23:29:44.093270  Opened dev<14>[   19.065561] [IGT] core_auth: executing

11000 23:29:44.099792  ice: /dev/dri/ca<14>[   19.065811] [IGT] core_auth: starting subtest getclient-master-drop

11001 23:29:44.099875  rd0

11002 23:29:44.110020  Subtest<14>[   19.065986] [IGT] core_auth: finished subtest getclient-master-drop, SUCCESS

11003 23:29:44.113499  <14>[   19.066057] [IGT] core_auth: exiting, ret=0

11004 23:29:44.123257  <8>[   19.071371] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>

11005 23:29:44.123516  Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11007 23:29:44.126503  <14>[   19.096341] [IGT] core_auth: executing

11008 23:29:44.133206   getclient-simpl<14>[   19.108544] [IGT] core_auth: starting subtest basic-auth

11009 23:29:44.139860  e: SUCCESS (0.00<14>[   19.108674] [IGT] core_auth: finished subtest basic-auth, SUCCESS

11010 23:29:44.143199  0s)

11011 23:29:44.146673  IGT-Ver<14>[   19.108713] [IGT] core_auth: exiting, ret=0

11012 23:29:44.153340  <8>[   19.114316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>

11013 23:29:44.153599  Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11015 23:29:44.159601  sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11016 23:29:44.163078  Starting subt<14>[   19.140689] [IGT] core_auth: executing

11017 23:29:44.173249  est: getclient-m<14>[   19.141091] [IGT] core_auth: starting subtest many-magics

11018 23:29:44.173332  aster-drop

11019 23:29:44.176287  Opened device: /dev/dri/card0

11020 23:29:44.183000  S<14>[   19.156073] [IGT] core_auth: finished subtest many-magics, SUCCESS

11021 23:29:44.189361  ubtest getclient<14>[   19.156136] [IGT] core_auth: exiting, ret=0

11022 23:29:44.196287  <8>[   19.161298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>

11023 23:29:44.196544  Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11025 23:29:44.199421  <8>[   19.164073] <LAVA_SIGNAL_TESTSET STOP>

11026 23:29:44.199739  Received signal: <TESTSET> STOP
11027 23:29:44.199812  Closing test_set core_auth
11028 23:29:44.202990  -master-drop: SUCCESS (0.000s)

11029 23:29:44.209879  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11030 23:29:44.212830  Opened device: /dev/dri/card0

11031 23:29:44.212912  Starting subtest: basic-auth

11032 23:29:44.219305  Subtest basic-auth: SUCCESS (0.000s)

11033 23:29:44.229112  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64<14>[   19.202506] [IGT] core_getclient: executing

11034 23:29:44.232379  <14>[   19.202788] [IGT] core_getclient: exiting, ret=0

11035 23:29:44.239147  <8>[   19.210775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>

11036 23:29:44.239402  Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11038 23:29:44.242806  )

11039 23:29:44.242887  Opened device: /dev/dri/card0

11040 23:29:44.245933  Starting subtest: many-magics

11041 23:29:44.249287  Reopening device failed after 1020 opens

11042 23:29:44.256090  Subtest many-magics: SUCCESS (0.015s)

11043 23:29:44.259033  IGT-Version: 1.27.1-g6<14>[   19.236386] [IGT] core_getstats: executing

11044 23:29:44.265911  <14>[   19.236664] [IGT] core_getstats: exiting, ret=0

11045 23:29:44.272824  <8>[   19.242237] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>

11046 23:29:44.273078  Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11048 23:29:44.276082  21c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11049 23:29:44.279110  Opened device: /dev/dri/card0

11050 23:29:44.282206  SUCCESS (0.000s)

11051 23:29:44.289114  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11052 23:29:44.289196  Opened device: /dev/dri/card0

11053 23:29:44.292664  SUCCESS (0.000s)

11054 23:29:44.302764  IGT-Version: 1.2<14>[   19.280030] [IGT] core_getversion: executing

11055 23:29:44.309555  <14>[   19.280318] [IGT] core_getversion: exiting, ret=0

11056 23:29:44.316141  7.1-g621c2d3 (aa<8>[   19.285508] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>

11057 23:29:44.316401  Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11059 23:29:44.323306  rch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11060 23:29:44.323388  Opened device: /dev/dri/card0

11061 23:29:44.326096  SUCCESS (0.000s)

11062 23:29:44.359884  IGT-Version: 1.2<14>[   19.336619] [IGT] core_setmaster_vs_auth: executing

11063 23:29:44.366280  <14>[   19.337069] [IGT] core_setmaster_vs_auth: exiting, ret=0

11064 23:29:44.373072  Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11066 23:29:44.376421  <8>[   19.342487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>

11067 23:29:44.379355  7.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11068 23:29:44.382689  Opened device: /dev/dri/card0

11069 23:29:44.382771  SUCCESS (0.000s)

11070 23:29:44.392210  <8>[   19.367759] <LAVA_SIGNAL_TESTSET START drm_read>

11071 23:29:44.392463  Received signal: <TESTSET> START drm_read
11072 23:29:44.392536  Starting test_set drm_read
11073 23:29:44.403972  IGT-Version: 1.2<14>[   19.380766] [IGT] drm_read: executing

11074 23:29:44.406802  <14>[   19.381242] [IGT] drm_read: exiting, ret=77

11075 23:29:44.413649  7.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11076 23:29:44.423695  Opened device: /dev/dr<8>[   19.396468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>

11077 23:29:44.423783  i/card0

11078 23:29:44.424021  Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11080 23:29:44.427123  No KMS driver or no outputs, pipes: 8, outputs: 0

11081 23:29:44.433825  <14>[   19.408810] [IGT] drm_read: executing

11082 23:29:44.437271  Subtest invalid-buffer: SKIP (0.000s)

11083 23:29:44.440571  IGT-V<14>[   19.409320] [IGT] drm_read: exiting, ret=77

11084 23:29:44.447393  <8>[   19.420022] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>

11085 23:29:44.447647  Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11087 23:29:44.457213  ersion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64<14>[   19.432315] [IGT] drm_read: executing

11088 23:29:44.459918  <14>[   19.432694] [IGT] drm_read: exiting, ret=77

11089 23:29:44.466576  <8>[   19.437198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>

11090 23:29:44.466831  Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11092 23:29:44.470486  -cip10-rt5 aarch64)

11093 23:29:44.473261  Opened device: /dev/dri/card0

11094 23:29:44.476728  No KMS driver or no outputs, pipes: 8, outputs: 0

11095 23:29:44.479850  Subtest fault-buffer: SKIP (0.000s)

11096 23:29:44.490430  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[   19.464124] [IGT] drm_read: executing

11097 23:29:44.493118  <14>[   19.464702] [IGT] drm_read: exiting, ret=77

11098 23:29:44.499910  <8>[   19.469896] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>

11099 23:29:44.500169  Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11101 23:29:44.503378  x: 6.1.64-cip10-rt5 aarch64)

11102 23:29:44.510156  Opened device: /de<14>[   19.482356] [IGT] drm_read: executing

11103 23:29:44.513049  <14>[   19.482749] [IGT] drm_read: exiting, ret=77

11104 23:29:44.519740  <8>[   19.488523] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>

11105 23:29:44.520011  Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11107 23:29:44.522949  v/dri/card0

11108 23:29:44.529497  No KMS driver or no outputs, pipes:<14>[   19.502628] [IGT] drm_read: executing

11109 23:29:44.533344  <14>[   19.503028] [IGT] drm_read: exiting, ret=77

11110 23:29:44.539609  <8>[   19.509744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>

11111 23:29:44.539864  Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11113 23:29:44.543226   8, outputs: 0

11114 23:29:44.545995  Subtest empty-block: SKIP (0.000s)

11115 23:29:44.552645  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11116 23:29:44.555912  Opened device: /dev/dri/card0

11117 23:29:44.559368  No KMS driv<14>[   19.536027] [IGT] drm_read: executing

11118 23:29:44.566213  <14>[   19.536620] [IGT] drm_read: exiting, ret=77

11119 23:29:44.572558  <8>[   19.542006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>

11120 23:29:44.572813  Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11122 23:29:44.575750  <8>[   19.543462] <LAVA_SIGNAL_TESTSET STOP>

11123 23:29:44.576002  Received signal: <TESTSET> STOP
11124 23:29:44.576071  Closing test_set drm_read
11125 23:29:44.579218  er or no outputs, pipes: 8, outputs: 0

11126 23:29:44.582634  Subtest empty-nonblock: SKIP (0.000s)

11127 23:29:44.592712  IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<8>[   19.565606] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>

11128 23:29:44.592967  Received signal: <TESTSET> START kms_addfb_basic
11129 23:29:44.593040  Starting test_set kms_addfb_basic
11130 23:29:44.595751  inux: 6.1.64-cip10-rt5 aarch64)

11131 23:29:44.598807  Opened device: /dev/dri/card0

11132 23:29:44.605484  No KMS driver or<14>[   19.577742] [IGT] kms_addfb_basic: executing

11133 23:29:44.612114  <14>[   19.582168] [IGT] kms_addfb_basic: starting subtest unused-handle

11134 23:29:44.615889   no outputs, pipes: 8, outputs: 0

11135 23:29:44.622278  Subtest s<14>[   19.593287] [IGT] kms_addfb_basic: finished subtest unused-handle, SUCCESS

11136 23:29:44.629269  hort-buffer-bloc<14>[   19.604849] [IGT] kms_addfb_basic: exiting, ret=0

11137 23:29:44.636016  <8>[   19.610615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>

11138 23:29:44.636273  Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11140 23:29:44.639204  k: SKIP (0.000s)

11141 23:29:44.645589  IGT-Version: 1.27.1-g621c2<14>[   19.621055] [IGT] kms_addfb_basic: executing

11142 23:29:44.649111  d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11143 23:29:44.652527  Opened device: /dev/dri/card0

11144 23:29:44.659178  N<14>[   19.631118] [IGT] kms_addfb_basic: starting subtest unused-pitches

11145 23:29:44.665526  <14>[   19.631197] [IGT] kms_addfb_basic: finished subtest unused-pitches, SUCCESS

11146 23:29:44.672281  o KMS driver or no outputs, pipe<14>[   19.647891] [IGT] kms_addfb_basic: exiting, ret=0

11147 23:29:44.682129  s: 8, outputs: 0<8>[   19.652510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>

11148 23:29:44.682211  

11149 23:29:44.682448  Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11151 23:29:44.685525  Subtest short-buffer-nonblock: SKIP (0.000s)

11152 23:29:44.691985  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11153 23:29:44.695395  Opened device: /dev/dri/card0

11154 23:29:44.701757  <14>[   19.675344] [IGT] kms_addfb_basic: executing

11155 23:29:44.708785  <14>[   19.679965] [IGT] kms_addfb_basic: starting subtest unused-offsets

11156 23:29:44.708868  

11157 23:29:44.718472  No KMS driver or no outputs, pipes: 8, outputs:<14>[   19.689491] [IGT] kms_addfb_basic: finished subtest unused-offsets, SUCCESS

11158 23:29:44.718559   0

11159 23:29:44.724939  Subtest <14>[   19.700957] [IGT] kms_addfb_basic: exiting, ret=0

11160 23:29:44.731582  <8>[   19.706691] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>

11161 23:29:44.731840  Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11163 23:29:44.735614  short-buffer-wakeup: SKIP (0.000s)

11164 23:29:44.745012  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-ci<14>[   19.717761] [IGT] kms_addfb_basic: executing

11165 23:29:44.751582  <14>[   19.722186] [IGT] kms_addfb_basic: starting subtest unused-modifier

11166 23:29:44.754773  p10-rt5 aarch64)

11167 23:29:44.754855  Opened device: /dev/dri/card0

11168 23:29:44.764648  <14>[   19.733975] [IGT] kms_addfb_basic: finished subtest unused-modifier, SUCCESS

11169 23:29:44.764730  

11170 23:29:44.764794  Starting subtest: unused-handle

11171 23:29:44.771438  Subtest un<14>[   19.745740] [IGT] kms_addfb_basic: exiting, ret=0

11172 23:29:44.778527  Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11174 23:29:44.781265  <8>[   19.751491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>

11175 23:29:44.781347  used-handle: SUCCESS (0.000s)

11176 23:29:44.788204  Test requirem<14>[   19.762723] [IGT] kms_addfb_basic: executing

11177 23:29:44.794716  <14>[   19.767165] [IGT] kms_addfb_basic: starting subtest clobberred-modifier

11178 23:29:44.808003  ent not met in function igt_require_i915, file .<14>[   19.777948] [IGT] kms_addfb_basic: finished subtest clobberred-modifier, SKIP

11179 23:29:44.808089  ./lib/drmtest.c:720:

11180 23:29:44.817711  Test requirement: is_i915_<14>[   19.789819] [IGT] kms_addfb_basic: exiting, ret=77

11181 23:29:44.824385  <8>[   19.795415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>

11182 23:29:44.824469  device(fd)

11183 23:29:44.824707  Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11185 23:29:44.834281  Test requirement not met in function<14>[   19.806613] [IGT] kms_addfb_basic: executing

11186 23:29:44.840599  <14>[   19.811005] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete

11187 23:29:44.850408   igt_require_i915, file ../lib/d<14>[   19.823140] [IGT] kms_addfb_basic: finished subtest invalid-smem-bo-on-discrete, SKIP

11188 23:29:44.854278  rmtest.c:720:

11189 23:29:44.860229  Test requirement: is_i915_device(<14>[   19.834295] [IGT] kms_addfb_basic: exiting, ret=77

11190 23:29:44.870252  <8>[   19.839758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>

11191 23:29:44.870337  fd)

11192 23:29:44.870574  Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11194 23:29:44.876911  No KMS driver or no outputs<14>[   19.851754] [IGT] kms_addfb_basic: executing

11195 23:29:44.883446  <14>[   19.856017] [IGT] kms_addfb_basic: starting subtest legacy-format

11196 23:29:44.887148  , pipes: 8, outputs: 0

11197 23:29:44.899904  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)<14>[   19.871058] [IGT] kms_addfb_basic: finished subtest legacy-format, SUCCESS

11198 23:29:44.899989  

11199 23:29:44.903357  Opened device: /dev/dri/card0

11200 23:29:44.909942  Starting subtest: unused-pitche<14>[   19.881456] [IGT] kms_addfb_basic: exiting, ret=0

11201 23:29:44.916410  <8>[   19.886741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>

11202 23:29:44.916494  s

11203 23:29:44.916732  Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11205 23:29:44.923520  Subtest unused-pitches: S<14>[   19.899036] [IGT] kms_addfb_basic: executing

11206 23:29:44.929637  <14>[   19.905353] [IGT] kms_addfb_basic: starting subtest no-handle

11207 23:29:44.939865  UCCESS (0.000s)<14>[   19.912565] [IGT] kms_addfb_basic: finished subtest no-handle, SUCCESS

11208 23:29:44.939948  [0m

11209 23:29:44.946219  Test requir<14>[   19.921034] [IGT] kms_addfb_basic: exiting, ret=0

11210 23:29:44.953025  <8>[   19.926647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>

11211 23:29:44.953280  Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11213 23:29:44.959718  ement not met in function igt_require_i915, file<14>[   19.936917] [IGT] kms_addfb_basic: executing

11214 23:29:44.962929   ../lib/drmtest.c:720:

11215 23:29:44.969338  Test req<14>[   19.943441] [IGT] kms_addfb_basic: starting subtest basic

11216 23:29:44.976495  <14>[   19.943533] [IGT] kms_addfb_basic: finished subtest basic, SUCCESS

11217 23:29:44.979261  uirement: is_i915_device(fd)

11218 23:29:44.985932  Test requirement n<14>[   19.958211] [IGT] kms_addfb_basic: exiting, ret=0

11219 23:29:44.992337  <8>[   19.963613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>

11220 23:29:44.992593  Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11222 23:29:44.999099  ot met in function igt_require_i915, file ../lib<14>[   19.974112] [IGT] kms_addfb_basic: executing

11223 23:29:45.005911  <14>[   19.980452] [IGT] kms_addfb_basic: starting subtest bad-pitch-0

11224 23:29:45.008988  /drmtest.c:720:

11225 23:29:45.015551  <14>[   19.988796] [IGT] kms_addfb_basic: finished subtest bad-pitch-0, SUCCESS

11226 23:29:45.015635  

11227 23:29:45.019299  Test requirement: is_i915_device(fd)

11228 23:29:45.022394  No KMS driver or no outputs, pipes: 8, outputs: 0

11229 23:29:45.028726  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11230 23:29:45.032346  Opened device: /dev/dri/card0

11231 23:29:45.037889  Starting subtest: unused-offsets

11232 23:29:45.039013  Subtest unused-offsets: SUCCESS (0.000s)

11233 23:29:45.045843  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11234 23:29:45.049365  Test requirement: is_i915_device(fd)

11235 23:29:45.055748  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11236 23:29:45.058770  Test requirement: is_i915_device(fd)

11237 23:29:45.065520  No KMS driver or no outputs, pipes: 8, outputs: 0

11238 23:29:45.072612  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11239 23:29:45.072695  Opened device: /dev/dri/card0

11240 23:29:45.075367  Starting subtest: unused-modifier

11241 23:29:45.082228  Subtest unused-modifier: SUCCESS (0.000s)

11242 23:29:45.088624  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11243 23:29:45.092051  Test requirement: is_i915_device(fd)

11244 23:29:45.098803  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11245 23:29:45.102381  Test requirement: is_i915_device(fd)

11246 23:29:45.105277  No KMS driver or no outputs, pipes: 8, outputs: 0

11247 23:29:45.111957  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11248 23:29:45.115325  Opened device: /dev/dri/card0

11249 23:29:45.118531  Starting subtest: clobberred-modifier

11250 23:29:45.125412  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11251 23:29:45.128551  Test requirement: is_i915_device(fd)

11252 23:29:45.135328  Subtest clobberred-modifier: SKIP (0.007s)

11253 23:29:45.142092  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11254 23:29:45.145448  Test requirement: is_i915_device(fd)

11255 23:29:45.151609  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11256 23:29:45.154851  Test requirement: is_i915_device(fd)

11257 23:29:45.158232  No KMS driver or no outputs, pipes: 8, outputs: 0

11258 23:29:45.165110  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11259 23:29:45.168345  Opened device: /dev/dri/card0

11260 23:29:45.171790  Starting subtest: invalid-smem-bo-on-discrete

11261 23:29:45.181262  Test requirement not met in function igt_require_intel, file ../lib/drmtest.c:715:

11262 23:29:45.184750  Test requirement: is_intel_device(fd)

11263 23:29:45.188355  Subtest invalid-smem-bo-on-discrete: SKIP (0.000s)

11264 23:29:45.195148  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11265 23:29:45.197920  Test requirement: is_i915_device(fd)

11266 23:29:45.207726  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11267 23:29:45.211128  Test requirement: is_i915_device(fd)

11268 23:29:45.214484  No KMS driver or no outputs, pipes: 8, outputs: 0

11269 23:29:45.221112  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11270 23:29:45.224282  Opened device: /dev/dri/card0

11271 23:29:45.227733  Starting subtest: legacy-format

11272 23:29:45.230899  Successfully fuzzed 10000 {bpp, depth} variations

11273 23:29:45.234056  Subtest legacy-format: SUCCESS (0.005s)

11274 23:29:45.240763  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11275 23:29:45.243987  Test requirement: is_i915_device(fd)

11276 23:29:45.250759  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11277 23:29:45.254415  Test requirement: is_i915_device(fd)

11278 23:29:45.260715  No KMS driver or no outputs, pipes: 8, outputs: 0

11279 23:29:45.267240  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11280 23:29:45.270891  Opened device: /dev/dri/card0

11281 23:29:45.270972  Starting subtest: no-handle

11282 23:29:45.274170  Subtest no-handle: SUCCESS (0.000s)

11283 23:29:45.284177  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11284 23:29:45.287259  Test requirement: is_i915_device(fd)

11285 23:29:45.294255  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11286 23:29:45.297565  Test requirement: is_i915_device(fd)

11287 23:29:45.300466  No KMS driver or no outputs, pipes: 8, outputs: 0

11288 23:29:45.307163  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11289 23:29:45.310703  Opened device: /dev/dri/card0

11290 23:29:45.313905  Starting subtest: basic

11291 23:29:45.317546  Subtest basic: SUCCESS (0.000s)

11292 23:29:45.323895  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11293 23:29:45.327045  Test requirement: is_i915_device(fd)

11294 23:29:45.333677  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11295 23:29:45.337079  Test requirement: is_i915_device(fd)

11296 23:29:45.340255  No KMS driver or no outputs, pipes: 8, outputs: 0

11297 23:29:45.347127  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11298 23:29:45.350397  Opened device: /dev/dri/card0

11299 23:29:45.356799  Starting subtest: bad-<14>[   20.330825] [IGT] kms_addfb_basic: exiting, ret=0

11300 23:29:45.363352  <8>[   20.336230] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>

11301 23:29:45.363442  pitch-0

11302 23:29:45.363693  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11304 23:29:45.370233  Subtest bad-pitch-0<14>[   20.346744] [IGT] kms_addfb_basic: executing

11305 23:29:45.377061  <14>[   20.353299] [IGT] kms_addfb_basic: starting subtest bad-pitch-32

11306 23:29:45.386774  : SUCCESS (0.000<14>[   20.360464] [IGT] kms_addfb_basic: finished subtest bad-pitch-32, SUCCESS

11307 23:29:45.386857  s)

11308 23:29:45.396880  Test requirement not met in function igt_require_i915, f<14>[   20.369344] [IGT] kms_addfb_basic: exiting, ret=0

11309 23:29:45.403190  <8>[   20.374764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>

11310 23:29:45.403449  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11312 23:29:45.407008  ile ../lib/drmtest.c:720:

11313 23:29:45.413092  Test <14>[   20.386969] [IGT] kms_addfb_basic: executing

11314 23:29:45.416543  <14>[   20.393589] [IGT] kms_addfb_basic: starting subtest bad-pitch-63

11315 23:29:45.426638  requirement: is_<14>[   20.400454] [IGT] kms_addfb_basic: finished subtest bad-pitch-63, SUCCESS

11316 23:29:45.429612  i915_device(fd)

11317 23:29:45.436401  Test requirement not met in function igt_requir<14>[   20.409431] [IGT] kms_addfb_basic: exiting, ret=0

11318 23:29:45.443100  <8>[   20.415512] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>

11319 23:29:45.443356  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11321 23:29:45.452986  e_i915, file ../lib/drmtest.c:72<14>[   20.426790] [IGT] kms_addfb_basic: executing

11322 23:29:45.459729  <14>[   20.433378] [IGT] kms_addfb_basic: starting subtest bad-pitch-128

11323 23:29:45.459812  0:

11324 23:29:45.466140  Test require<14>[   20.440567] [IGT] kms_addfb_basic: finished subtest bad-pitch-128, SUCCESS

11325 23:29:45.469465  ment: is_i915_device(fd)

11326 23:29:45.476387  No KMS driver or no outputs, pipes: 8,<14>[   20.449430] [IGT] kms_addfb_basic: exiting, ret=0

11327 23:29:45.483018  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11329 23:29:45.486026  <8>[   20.454748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>

11330 23:29:45.486109   outputs: 0

11331 23:29:45.492919  IGT-Version: 1.27.1<14>[   20.467025] [IGT] kms_addfb_basic: executing

11332 23:29:45.499728  <14>[   20.473492] [IGT] kms_addfb_basic: starting subtest bad-pitch-256

11333 23:29:45.505879  -g621c2d3 (aarch<14>[   20.480874] [IGT] kms_addfb_basic: finished subtest bad-pitch-256, SUCCESS

11334 23:29:45.509103  64) (Linux: 6.1.64-cip10-rt5 aarch64)

11335 23:29:45.515826  Opened de<14>[   20.489721] [IGT] kms_addfb_basic: exiting, ret=0

11336 23:29:45.522420  <8>[   20.494939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>

11337 23:29:45.522677  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11339 23:29:45.526020  vice: /dev/dri/card0

11340 23:29:45.532481  Starting subtest: bad-pitc<14>[   20.505933] [IGT] kms_addfb_basic: executing

11341 23:29:45.539200  <14>[   20.512283] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024

11342 23:29:45.539283  h-32

11343 23:29:45.548980  Subtest bad-pitch-32: SUCCESS (0.000s)<14>[   20.521289] [IGT] kms_addfb_basic: finished subtest bad-pitch-1024, SUCCESS

11344 23:29:45.552343  

11345 23:29:45.555427  Test requi<14>[   20.533018] [IGT] kms_addfb_basic: exiting, ret=0

11346 23:29:45.565328  <8>[   20.538434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>

11347 23:29:45.565634  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11349 23:29:45.572230  rement not met in function igt_require_i915, fil<14>[   20.548706] [IGT] kms_addfb_basic: executing

11350 23:29:45.578515  <14>[   20.555314] [IGT] kms_addfb_basic: starting subtest bad-pitch-999

11351 23:29:45.582466  e ../lib/drmtest.c:720:

11352 23:29:45.591569  Test requirement: is_i9<14>[   20.561847] [IGT] kms_addfb_basic: finished subtest bad-pitch-999, SUCCESS

11353 23:29:45.591654  15_device(fd)

11354 23:29:45.601809  Test requirement not met in function igt_require_<14>[   20.573477] [IGT] kms_addfb_basic: exiting, ret=0

11355 23:29:45.608580  i915, file ../li<8>[   20.579459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>

11356 23:29:45.608839  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11358 23:29:45.611837  b/drmtest.c:720:

11359 23:29:45.615250  Test requirement: is_i915_device(fd)

11360 23:29:45.618584  No KMS driver or no outputs, pipes: 8, outputs: 0

11361 23:29:45.628557  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64<14>[   20.601931] [IGT] kms_addfb_basic: executing

11362 23:29:45.634893  <14>[   20.609031] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536

11363 23:29:45.638287  -cip10-rt5 aarch64)

11364 23:29:45.648465  Opened device: /dev/dri/car<14>[   20.617586] [IGT] kms_addfb_basic: finished subtest bad-pitch-65536, SUCCESS

11365 23:29:45.648551  d0

11366 23:29:45.648616  Starting subtest: bad-pitch-63

11367 23:29:45.658183  Subtest bad-pitch-63: SU<14>[   20.629318] [IGT] kms_addfb_basic: exiting, ret=0

11368 23:29:45.664715  CCESS (0.000s)[<8>[   20.635484] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>

11369 23:29:45.664799  0m

11370 23:29:45.665039  Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11372 23:29:45.674788  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11373 23:29:45.678121  Test requirement: is_i915_device(fd)

11374 23:29:45.684357  Test requirement not met in functio<14>[   20.660007] [IGT] kms_addfb_basic: executing

11375 23:29:45.687656  n igt_require_i915, file ../lib/drmtest.c:720:

11376 23:29:45.697562  Test requirement: is_i915_device<14>[   20.669199] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any

11377 23:29:45.707687  <14>[   20.669324] [IGT] kms_addfb_basic: finished subtest invalid-get-prop-any, SUCCESS

11378 23:29:45.707772  (fd)

11379 23:29:45.714206  No KMS dri<14>[   20.688765] [IGT] kms_addfb_basic: exiting, ret=0

11380 23:29:45.721363  <8>[   20.694836] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>

11381 23:29:45.721633  Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11383 23:29:45.727453  ver or no outputs, pipes: 8, out<14>[   20.705088] [IGT] kms_addfb_basic: executing

11384 23:29:45.727536  puts: 0

11385 23:29:45.734301  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11386 23:29:45.737737  Opened device: /dev/dri/card0

11387 23:29:45.744441  Starting subte<14>[   20.718167] [IGT] kms_addfb_basic: starting subtest invalid-get-prop

11388 23:29:45.753980  <14>[   20.718257] [IGT] kms_addfb_basic: finished subtest invalid-get-prop, SUCCESS

11389 23:29:45.754063  st: bad-pitch-128

11390 23:29:45.760920  Subtest b<14>[   20.735677] [IGT] kms_addfb_basic: exiting, ret=0

11391 23:29:45.767227  <8>[   20.741056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>

11392 23:29:45.767483  Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11394 23:29:45.777345  ad-pitch-128: SUCCESS (0.000s)[<14>[   20.751824] [IGT] kms_addfb_basic: executing

11395 23:29:45.777430  0m

11396 23:29:45.786999  Test requirement not met in function igt_req<14>[   20.760077] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any

11397 23:29:45.793723  <14>[   20.760149] [IGT] kms_addfb_basic: finished subtest invalid-set-prop-any, SUCCESS

11398 23:29:45.797075  uire_i915, file ../lib/drmtest.c:720:

11399 23:29:45.803390  Test requ<14>[   20.777532] [IGT] kms_addfb_basic: exiting, ret=0

11400 23:29:45.810019  <8>[   20.782729] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>

11401 23:29:45.810263  Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11403 23:29:45.813737  irement: is_i915_device(fd)

11404 23:29:45.819963  Test requirement no<14>[   20.794316] [IGT] kms_addfb_basic: executing

11405 23:29:45.826831  <14>[   20.802528] [IGT] kms_addfb_basic: starting subtest invalid-set-prop

11406 23:29:45.840452  t met in function igt_require_i915, file ../lib/<14>[   20.809814] [IGT] kms_addfb_basic: finished subtest invalid-set-prop, SUCCESS

11407 23:29:45.840533  drmtest.c:720:

11408 23:29:45.849958  Test requirement: is_i915_device<14>[   20.821735] [IGT] kms_addfb_basic: exiting, ret=0

11409 23:29:45.856555  <8>[   20.826924] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>

11410 23:29:45.856676  (fd)

11411 23:29:45.856915  Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11413 23:29:45.863501  No KMS driver or no outputs, pipes: 8, out<14>[   20.838201] [IGT] kms_addfb_basic: executing

11414 23:29:45.866826  puts: 0

11415 23:29:45.873449  IGT-Version: 1.27.1-g62<14>[   20.848393] [IGT] kms_addfb_basic: starting subtest master-rmfb

11416 23:29:45.880309  <14>[   20.848541] [IGT] kms_addfb_basic: finished subtest master-rmfb, SUCCESS

11417 23:29:45.886921  1c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11418 23:29:45.887006  Opened device: /dev/dri/card0

11419 23:29:45.889822  Starting subtest: bad-pitch-256

11420 23:29:45.896514  Subtest bad-pitch-256: SUCCESS (0.000s)

11421 23:29:45.903104  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11422 23:29:45.906480  Test requirement: is_i915_device(fd)

11423 23:29:45.913324  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11424 23:29:45.916724  Test requirement: is_i915_device(fd)

11425 23:29:45.919537  No KMS driver or no outputs, pipes: 8, outputs: 0

11426 23:29:45.926807  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11427 23:29:45.929737  Opened device: /dev/dri/card0

11428 23:29:45.933210  Starting subtest: bad-pitch-1024

11429 23:29:45.936294  Subtest bad-pitch-1024: SUCCESS (0.000s)

11430 23:29:45.942909  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11431 23:29:45.946346  Test requirement: is_i915_device(fd)

11432 23:29:45.952762  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11433 23:29:45.956788  Test requirement: is_i915_device(fd)

11434 23:29:45.963027  No KMS driver or no outputs, pipes: 8, outputs: 0

11435 23:29:45.969879  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11436 23:29:45.972827  Opened device: /dev/dri/card0

11437 23:29:45.972910  Starting subtest: bad-pitch-999

11438 23:29:45.979670  Subtest bad-pitch-999: SUCCESS (0.000s)

11439 23:29:45.986064  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11440 23:29:45.989741  Test requirement: is_i915_device(fd)

11441 23:29:45.996262  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11442 23:29:45.999299  Test requirement: is_i915_device(fd)

11443 23:29:46.002566  No KMS driver or no outputs, pipes: 8, outputs: 0

11444 23:29:46.009192  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11445 23:29:46.013106  Opened device: /dev/dri/card0

11446 23:29:46.016692  Starting subtest: bad-pitch-65536

11447 23:29:46.019613  Subtest bad-pitch-65536: SUCCESS (0.000s)

11448 23:29:46.029531  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11449 23:29:46.032510  Test requirement: is_i915_device(fd)

11450 23:29:46.039600  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11451 23:29:46.042538  Test requirement: is_i915_device(fd)

11452 23:29:46.046096  No KMS driver or no outputs, pipes: 8, outputs: 0

11453 23:29:46.052949  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11454 23:29:46.055701  Opened device: /dev/dri/card0

11455 23:29:46.058931  Starting subtest: invalid-get-prop-any

11456 23:29:46.062514  Subtest invalid-get-prop-any: SUCCESS (0.000s)

11457 23:29:46.069307  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11458 23:29:46.072367  Test requirement: is_i915_device(fd)

11459 23:29:46.082382  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11460 23:29:46.085794  Test requirement: is_i915_device(fd)

11461 23:29:46.089146  No KMS driver or no outputs, pipes: 8, outputs: 0

11462 23:29:46.095968  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11463 23:29:46.098634  Opened device: /dev/dri/card0

11464 23:29:46.101949  Starting subtest: invalid-get-prop

11465 23:29:46.105300  Subtest invalid-get-prop: SUCCESS (0.000s)

11466 23:29:46.112249  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11467 23:29:46.115245  Test requirement: is_i915_device(fd)

11468 23:29:46.121852  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11469 23:29:46.125435  Test requirement: is_i915_device(fd)

11470 23:29:46.131839  No KMS driver or no outputs, pipes: 8, outputs: 0

11471 23:29:46.138710  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11472 23:29:46.141699  Opened device: /dev/dri/card0

11473 23:29:46.145134  Starting subtest: invalid-set-prop-any

11474 23:29:46.148079  Subtest invalid-set-prop-any: SUCCESS (0.000s)

11475 23:29:46.155013  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11476 23:29:46.158005  Test requirement: is_i915_device(fd)

11477 23:29:46.164799  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11478 23:29:46.168181  Test requirement: is_i915_device(fd)

11479 23:29:46.174685  No KMS driver or no outputs, pipes: 8, outputs: 0

11480 23:29:46.181254  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11481 23:29:46.185018  Opened device: /dev/dri/card0

11482 23:29:46.185102  Starting subtest: invalid-set-prop

11483 23:29:46.191607  Subtest invalid-set-prop: SUCCESS (0.000s)

11484 23:29:46.198218  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11485 23:29:46.201100  Test requirement: is_i915_device(fd)

11486 23:29:46.207716  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11487 23:29:46.211227  Test requirement: is_i915_device(fd)

11488 23:29:46.221035  No KMS driver or no outputs, pipes: 8, outpu<14>[   21.195599] [IGT] kms_addfb_basic: exiting, ret=0

11489 23:29:46.227722  <8>[   21.200727] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>

11490 23:29:46.227808  ts: 0

11491 23:29:46.228055  Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11493 23:29:46.234175  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11494 23:29:46.237833  Opened device: /dev/dri/card0

11495 23:29:46.240805  Starting subtest: master-rmfb

11496 23:29:46.243803  Subtest master-rmfb: SUCCESS (0.000s)

11497 23:29:46.247160  Te<14>[   21.223063] [IGT] kms_addfb_basic: executing

11498 23:29:46.257754  st requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11499 23:29:46.264358  <14>[   21.236032] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag

11500 23:29:46.271163  <14>[   21.236167] [IGT] kms_addfb_basic: finished subtest addfb25-modifier-no-flag, SUCCESS

11501 23:29:46.277108  <14>[   21.236365] [IGT] kms_addfb_basic: exiting, ret=0

11502 23:29:46.277192  

11503 23:29:46.287209  Test requirement: is_i915_devic<8>[   21.243370] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>

11504 23:29:46.287495  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11506 23:29:46.290295  <14>[   21.258868] [IGT] kms_addfb_basic: executing

11507 23:29:46.300544  <14>[   21.271059] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier

11508 23:29:46.300629  e(fd)

11509 23:29:46.306852  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11510 23:29:46.313790  Test r<14>[   21.286509] [IGT] kms_addfb_basic: finished subtest addfb25-bad-modifier, FAIL

11511 23:29:46.320520  <14>[   21.286749] [IGT] kms_addfb_basic: exiting, ret=98

11512 23:29:46.326832  <8>[   21.292164] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>

11513 23:29:46.327090  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11515 23:29:46.330341  equirement: is_i915_device(fd)

11516 23:29:46.336773  No KMS driver or<14>[   21.310281] [IGT] kms_addfb_basic: executing

11517 23:29:46.340107   no outputs, pipes: 8, outputs: 0

11518 23:29:46.350397  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<14>[   21.323147] [IGT] kms_addfb_basic: exiting, ret=77

11519 23:29:46.357023  <8>[   21.328606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>

11520 23:29:46.357280  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11522 23:29:46.360399  : 6.1.64-cip10-rt5 aarch64)

11523 23:29:46.363829  Ope<14>[   21.340558] [IGT] kms_addfb_basic: executing

11524 23:29:46.366900  ned device: /dev/dri/card0

11525 23:29:46.369896  Starting subtest: addfb25-modifier-no-flag

11526 23:29:46.379999  Subtest addfb25-modifier-no-flag: SUCCESS (0.000s)[<14>[   21.353190] [IGT] kms_addfb_basic: exiting, ret=77

11527 23:29:46.390141  <8>[   21.358782] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>

11528 23:29:46.390225  0m

11529 23:29:46.390465  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11531 23:29:46.396579  Test requirement not met in <14>[   21.371369] [IGT] kms_addfb_basic: executing

11532 23:29:46.400049  function igt_require_i915, file ../lib/drmtest.c:720:

11533 23:29:46.410129  Test requirement: is_i915<14>[   21.383983] [IGT] kms_addfb_basic: exiting, ret=77

11534 23:29:46.416895  <8>[   21.389506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>

11535 23:29:46.417152  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11537 23:29:46.420193  _device(fd)

11538 23:29:46.426496  Test requirement not met in function igt_require_i9<14>[   21.401939] [IGT] kms_addfb_basic: executing

11539 23:29:46.430102  15, file ../lib/drmtest.c:720:

11540 23:29:46.433229  Test requirement: is_i915_device(fd)

11541 23:29:46.439818  No KMS driver or no output<14>[   21.414576] [IGT] kms_addfb_basic: exiting, ret=77

11542 23:29:46.449485  <8>[   21.419879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>

11543 23:29:46.449615  s, pipes: 8, outputs: 0

11544 23:29:46.449871  Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11546 23:29:46.456153  IGT-Ver<14>[   21.431662] [IGT] kms_addfb_basic: executing

11547 23:29:46.462836  sion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11548 23:29:46.466657  Opened device: /dev/dri/card0

11549 23:29:46.469573  Starting subtest: addfb25-bad-modifier

11550 23:29:46.479671  (kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:

11551 23:29:46.496124  (kms_addfb_basic:438) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1

11552 23:29:46.499462  (kms_addfb_basic:438) CRITICAL: error: 0 != -1

11553 23:29:46.502888  Stack trace:

11554 23:29:46.505747    #0 ../lib/igt_core.c:1971 __igt_fail_assert()

11555 23:29:46.509103    #1 [<unknown>+0xc56847e0]

11556 23:29:46.512342    #2 [<unknown>+0xc5686278]

11557 23:29:46.512462    #3 [<unknown>+0xc568167c]

11558 23:29:46.515671    #4 [__libc_start_main+0xe8]

11559 23:29:46.519061    #5 [<unknown>+0xc56816b4]

11560 23:29:46.522492    #6 [<unknown>+0xc56816b4]

11561 23:29:46.526111  Subtest addfb25-bad-modifier failed.

11562 23:29:46.526193  **** DEBUG ****

11563 23:29:46.536120  (kms_addfb_basic:438) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)

11564 23:29:46.545531  (kms_addfb_basic:438) CRITICAL: Test assertion failure function addfb25_tests, file ../tests/kms_addfb_basic.c:662:

11565 23:29:46.562206  (kms_addfb_basic:438) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1

11566 23:29:46.566184  (kms_addfb_basic:438) CRITICAL: error: 0 != -1

11567 23:29:46.572653  (kms_addfb_basic:438) igt_core-INFO: Stack trace:

11568 23:29:46.578724  (kms_addfb_basic:438) igt_core-INFO:   #0 ../lib/igt_core.c:1971 __igt_fail_assert()

11569 23:29:46.585783  (kms_addfb_basic:438) igt_core-INFO:   #1 [<unknown>+0xc56847e0]

11570 23:29:46.589305  (kms_addfb_basic:438) igt_core-INFO:   #2 [<unknown>+0xc5686278]

11571 23:29:46.595387  (kms_addfb_basic:438) igt_core-INFO:   #3 [<unknown>+0xc568167c]

11572 23:29:46.602239  (kms_addfb_basic:438) igt_core-INFO:   #4 [__libc_start_main+0xe8]

11573 23:29:46.608763  (kms_addfb_basic:438) igt_core-INFO:   #5 [<unknown>+0xc56816b4]

11574 23:29:46.611811  (kms_addfb_basic:438) igt_core-INFO:   #6 [<unknown>+0xc56816b4]

11575 23:29:46.615203  ****  END  ****

11576 23:29:46.618997  Subtest addfb25-bad-modifier: FAIL (0.005s)

11577 23:29:46.625544  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11578 23:29:46.628883  Test requirement: is_i915_device(fd)

11579 23:29:46.635478  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11580 23:29:46.638778  Test requirement: is_i915_device(fd)

11581 23:29:46.645426  No KMS driver or no outputs, pipes: 8, outputs: 0

11582 23:29:46.652191  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11583 23:29:46.652270  Opened device: /dev/dri/card0

11584 23:29:46.661949  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11585 23:29:46.664994  Test requirement: is_i915_device(fd)

11586 23:29:46.668382  Subtest addfb25-x-tiled-mismatch-legacy: SKIP (0.000s)

11587 23:29:46.675175  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11588 23:29:46.678383  Test requirement: is_i915_device(fd)

11589 23:29:46.685057  No KMS driver or no outputs, pipes: 8, outputs: 0

11590 23:29:46.691945  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11591 23:29:46.695269  Opened device: /dev/dri/card0

11592 23:29:46.701814  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11593 23:29:46.705023  Test requirement: is_i915_device(fd)

11594 23:29:46.708113  Subtest addfb25-x-tiled-legacy: SKIP (0.000s)

11595 23:29:46.715170  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11596 23:29:46.718131  Test requirement: is_i915_device(fd)

11597 23:29:46.724565  No KMS driver or no outputs, pipes: 8, outputs: 0

11598 23:29:46.731214  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11599 23:29:46.731298  Opened device: /dev/dri/card0

11600 23:29:46.741267  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11601 23:29:46.744896  Test requirement: is_i915_device(fd)

11602 23:29:46.747852  Subtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)

11603 23:29:46.754571  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11604 23:29:46.757887  Test requirement: is_i915_device(fd)

11605 23:29:46.764606  No KMS driver or no outputs, pipes: 8, outputs: 0

11606 23:29:46.771076  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11607 23:29:46.775160  Opened device: /dev/dri/card0

11608 23:29:46.781426  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11609 23:29:46.784721  Test requirement: is_i915_device(fd)

11610 23:29:46.791646  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11611 23:29:46.794479  Test requirement: is_i915_device(fd)

11612 23:29:46.797964  Subtest basic-x-tiled-legacy: SKIP (0.000s)

11613 23:29:46.804447  No KMS driver or no outputs, pipes: 8, outputs: 0

11614 23:29:46.807717  IGT<14>[   21.781718] [IGT] kms_addfb_basic: exiting, ret=77

11615 23:29:46.817941  <8>[   21.787768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>

11616 23:29:46.818208  Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11618 23:29:46.824690  -Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11619 23:29:46.827736  Opened de<14>[   21.801456] [IGT] kms_addfb_basic: executing

11620 23:29:46.831261  vice: /dev/dri/card0

11621 23:29:46.840725  Test requirement not met in function igt_require_i915, fil<14>[   21.813989] [IGT] kms_addfb_basic: exiting, ret=77

11622 23:29:46.847296  <8>[   21.819948] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>

11623 23:29:46.847553  Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11625 23:29:46.850693  e ../lib/drmtest.c:720:

11626 23:29:46.854293  Test requirement: is_i915_device(fd)

11627 23:29:46.860719  Test requirement <14>[   21.834576] [IGT] kms_addfb_basic: executing

11628 23:29:46.864653  not met in function igt_require_i915, file ../lib/drmtest.c:720:

11629 23:29:46.874455  Test requirement: is_i915_devi<14>[   21.847233] [IGT] kms_addfb_basic: exiting, ret=77

11630 23:29:46.880724  <8>[   21.852655] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>

11631 23:29:46.880807  ce(fd)

11632 23:29:46.881044  Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11634 23:29:46.887718  Subtest framebuffer-<14>[   21.864909] [IGT] kms_addfb_basic: executing

11635 23:29:46.890849  vs-set-tiling: SKIP (0.000s)

11636 23:29:46.897373  No KMS driver or no outputs, pipes: 8, outputs: 0

11637 23:29:46.903882  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Lin<14>[   21.877844] [IGT] kms_addfb_basic: exiting, ret=77

11638 23:29:46.910595  <8>[   21.883497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>

11639 23:29:46.910851  Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11641 23:29:46.913999  ux: 6.1.64-cip10-rt5 aarch64)

11642 23:29:46.920949  Opened device: /d<14>[   21.895675] [IGT] kms_addfb_basic: executing

11643 23:29:46.921033  ev/dri/card0

11644 23:29:46.933738  Test requirement not met in function igt_require_i915, file ../lib<14>[   21.908298] [IGT] kms_addfb_basic: exiting, ret=77

11645 23:29:46.937250  Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11647 23:29:46.940678  <8>[   21.913748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>

11648 23:29:46.940762  /drmtest.c:720:

11649 23:29:46.947455  Test requirement: is_i915_devic<14>[   21.925035] [IGT] kms_addfb_basic: executing

11650 23:29:46.947539  e(fd)

11651 23:29:46.957322  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11652 23:29:46.960633  Test requirement: is_i915_device(fd)

11653 23:29:46.967093  Subtest tile-pitch-mismatch: SKIP (0.000s)[<14>[   21.942661] [IGT] kms_addfb_basic: exiting, ret=77

11654 23:29:46.973694  <8>[   21.947953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>

11655 23:29:46.973950  Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11657 23:29:46.977190  0m

11658 23:29:46.983706  No KMS driver or no outputs, pipes: 8, outpu<14>[   21.958428] [IGT] kms_addfb_basic: executing

11659 23:29:46.983790  ts: 0

11660 23:29:46.990014  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11661 23:29:46.997336  Opened device: <14>[   21.971018] [IGT] kms_addfb_basic: exiting, ret=77

11662 23:29:47.003682  <8>[   21.977960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>

11663 23:29:47.003939  Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11665 23:29:47.006895  /dev/dri/card0

11666 23:29:47.016744  Test requirement not met in function igt_require_i915, file ../l<14>[   21.990013] [IGT] kms_addfb_basic: executing

11667 23:29:47.016829  ib/drmtest.c:720:

11668 23:29:47.020014  Test requirement: is_i915_device(fd)

11669 23:29:47.026736  Test requirement not me<14>[   22.002932] [IGT] kms_addfb_basic: exiting, ret=77

11670 23:29:47.033340  <8>[   22.008483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>

11671 23:29:47.033631  Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11673 23:29:47.043673  t in function igt_require_i915, file ../lib/drmt<14>[   22.019830] [IGT] kms_addfb_basic: executing

11674 23:29:47.043757  est.c:720:

11675 23:29:47.046493  Test requirement: is_i915_device(fd)

11676 23:29:47.056632  Subtest basic-y-tiled-legacy: SKIP (0.000s<14>[   22.032442] [IGT] kms_addfb_basic: exiting, ret=77

11677 23:29:47.066739  <8>[   22.038854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>

11678 23:29:47.066818  )

11679 23:29:47.067057  Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11681 23:29:47.070121  No KMS driver or no outputs, pipes: 8, outputs: 0

11682 23:29:47.076485  IGT-Ve<14>[   22.051316] [IGT] kms_addfb_basic: executing

11683 23:29:47.082940  rsion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11684 23:29:47.089806  Opened device: /dev/dri/card<14>[   22.064034] [IGT] kms_addfb_basic: exiting, ret=77

11685 23:29:47.089891  0

11686 23:29:47.099898  Test requirem<8>[   22.070755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>

11687 23:29:47.100158  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11689 23:29:47.102953  ent not met in function igt_require_i915, file ../lib/drmtest.c:720:

11690 23:29:47.106706  Test requirement: is_i915_device(fd)

11691 23:29:47.116540  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11692 23:29:47.119648  T<14>[   22.094186] [IGT] kms_addfb_basic: executing

11693 23:29:47.123545  est requirement: is_i915_device(fd)

11694 23:29:47.126378  No KMS driver or no outputs, pipes: 8, outputs: 0

11695 23:29:47.132914  Subt<14>[   22.107983] [IGT] kms_addfb_basic: exiting, ret=77

11696 23:29:47.139426  <8>[   22.115138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>

11697 23:29:47.139684  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11699 23:29:47.142872  est size-max: SKIP (0.000s)

11700 23:29:47.149771  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11701 23:29:47.153238  Opened device: /dev/dri/card0

11702 23:29:47.163023  Test requirement not met in function igt_require_i915, file ../lib/drm<14>[   22.140614] [IGT] kms_addfb_basic: executing

11703 23:29:47.166460  test.c:720:

11704 23:29:47.169482  Test requirement: is_i915_device(fd)

11705 23:29:47.176253  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11706 23:29:47.182514  Test requi<14>[   22.154070] [IGT] kms_addfb_basic: exiting, ret=77

11707 23:29:47.189136  <8>[   22.160768] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>

11708 23:29:47.189395  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11710 23:29:47.192810  rement: is_i915_device(fd)

11711 23:29:47.199584  No KMS driver or no outputs, pipes: <14>[   22.173780] [IGT] kms_addfb_basic: executing

11712 23:29:47.202757  8, outputs: 0

11713 23:29:47.205865  Subtest too-wide: SKIP (0.000s)

11714 23:29:47.212933  IGT-Version: 1.27.1-g621<14>[   22.186332] [IGT] kms_addfb_basic: exiting, ret=77

11715 23:29:47.219597  <8>[   22.191803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>

11716 23:29:47.219855  Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11718 23:29:47.222943  <8>[   22.193007] <LAVA_SIGNAL_TESTSET STOP>

11719 23:29:47.223198  Received signal: <TESTSET> STOP
11720 23:29:47.223321  Closing test_set kms_addfb_basic
11721 23:29:47.232484  c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)<8>[   22.207891] <LAVA_SIGNAL_TESTSET START kms_atomic>

11722 23:29:47.232569  

11723 23:29:47.232805  Received signal: <TESTSET> START kms_atomic
11724 23:29:47.232872  Starting test_set kms_atomic
11725 23:29:47.236157  Opened device: /dev/dri/card0

11726 23:29:47.242702  Test requirement not met in function igt_requir<14>[   22.220437] [IGT] kms_atomic: executing

11727 23:29:47.249383  e_i915, file ../<14>[   22.220865] [IGT] kms_atomic: exiting, ret=77

11728 23:29:47.259350  <8>[   22.225950] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>

11729 23:29:47.259435  lib/drmtest.c:720:

11730 23:29:47.259673  Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11732 23:29:47.262292  Test requirement: is_i915_device(fd)

11733 23:29:47.272464  Test requirement not met in function igt_require_i915,<14>[   22.248382] [IGT] kms_atomic: executing

11734 23:29:47.276065  <14>[   22.248911] [IGT] kms_atomic: exiting, ret=77

11735 23:29:47.282689  <8>[   22.254533] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>

11736 23:29:47.282945  Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11738 23:29:47.285948   file ../lib/drmtest.c:720:

11739 23:29:47.292651  Test requirement: i<14>[   22.266662] [IGT] kms_atomic: executing

11740 23:29:47.295461  <14>[   22.267058] [IGT] kms_atomic: exiting, ret=77

11741 23:29:47.305489  <8>[   22.271489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>

11742 23:29:47.305757  Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11744 23:29:47.308936  s_i915_device(fd)

11745 23:29:47.312506  No KMS driver or no outputs, pipes: 8, outputs: 0

11746 23:29:47.315444  Subtest too-high: SKIP (0.000s)

11747 23:29:47.325524  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<14>[   22.297393] [IGT] kms_atomic: executing

11748 23:29:47.328563  <14>[   22.298024] [IGT] kms_atomic: exiting, ret=77

11749 23:29:47.335378  <8>[   22.303412] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>

11750 23:29:47.335635  Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11752 23:29:47.338477  1.64-cip10-rt5 aarch64)

11753 23:29:47.342326  Opened <14>[   22.318965] [IGT] kms_atomic: executing

11754 23:29:47.345560  device: /dev/dri/card0

11755 23:29:47.352383  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11756 23:29:47.355535  Test requirement: is_i915_device(fd)

11757 23:29:47.362293  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11758 23:29:47.365039  Test requirement: is_i915_device(fd)

11759 23:29:47.371848  No KMS driver or no outputs, pipes: 8, outputs: 0

11760 23:29:47.375089  Subtest bo-too-small: SKIP (0.000s)

11761 23:29:47.381755  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11762 23:29:47.384877  Opened device: /dev/dri/card0

11763 23:29:47.391548  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11764 23:29:47.394937  Test requirement: is_i915_device(fd)

11765 23:29:47.401744  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11766 23:29:47.404767  Test requirement: is_i915_device(fd)

11767 23:29:47.408507  No KMS driver or no outputs, pipes: 8, outputs: 0

11768 23:29:47.411656  Subtest small-bo: SKIP (0.000s)

11769 23:29:47.418234  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11770 23:29:47.421239  Opened device: /dev/dri/card0

11771 23:29:47.428062  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11772 23:29:47.431583  Test requirement: is_i915_device(fd)

11773 23:29:47.441455  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11774 23:29:47.444790  Test requirement: is_i915_device(fd)

11775 23:29:47.448095  No KMS driver or no outputs, pipes: 8, outputs: 0

11776 23:29:47.451020  Subtest bo-too-small-due-to-tiling: SKIP (0.000s)

11777 23:29:47.457703  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11778 23:29:47.461441  Opened device: /dev/dri/card0

11779 23:29:47.468102  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11780 23:29:47.471651  Test requirement: is_i915_device(fd)

11781 23:29:47.481376  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11782 23:29:47.484497  Test requirement: is_i915_device(fd)

11783 23:29:47.488223  No KMS driver or no outputs, pipes: 8, outputs: 0

11784 23:29:47.491572  Subtest addfb25-y-tiled-legacy: SKIP (0.000s)

11785 23:29:47.497701  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11786 23:29:47.501021  Opened device: /dev/dri/card0

11787 23:29:47.507923  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11788 23:29:47.511153  Test requirement: is_i915_device(fd)

11789 23:29:47.517998  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11790 23:29:47.520902  Test requirement: is_i915_device(fd)

11791 23:29:47.527948  No KMS driver or no outputs, pipes: 8, outputs: 0

11792 23:29:47.530740  Subtest addfb25-yf-tiled-legacy: SKIP (0.000s)

11793 23:29:47.537762  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11794 23:29:47.540963  Opened device: /dev/dri/card0

11795 23:29:47.547432  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11796 23:29:47.550859  Test requirement: is_i915_device(fd)

11797 23:29:47.557361  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11798 23:29:47.560742  Test requirement: is_i915_device(fd)

11799 23:29:47.567607  No KMS driver or no outputs, pipes: 8, outputs: 0

11800 23:29:47.570787  Subtest addfb25-y-tiled-small-legacy: SKIP (0.000s)

11801 23:29:47.577181  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11802 23:29:47.580763  Opened device: /dev/dri/card0

11803 23:29:47.586992  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11804 23:29:47.590576  Test requirement: is_i915_device(fd)

11805 23:29:47.596981  Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:720:

11806 23:29:47.600372  Test requirement: is_i915_device(fd)

11807 23:29:47.607171  No KMS driver or no outputs, pipes: 8, outputs: 0

11808 23:29:47.610545  Subtest addfb25-4-tiled: SKIP (0.000s)

11809 23:29:47.616934  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11810 23:29:47.620578  Opened device: /dev/dri/card0

11811 23:29:47.623693  No KMS driver or no outputs, pipes: 8, outputs: 0

11812 23:29:47.626716  Subtest plane-overlay-legacy: SKIP (0.000s)

11813 23:29:47.634077  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11814 23:29:47.637076  Opened device: /dev/dri/card0

11815 23:29:47.643198  No KMS driver or no outputs, pipes: 8, outputs: 0

11816 23:29:47.646569  Subtest plane-primary-legacy: SKIP (0.000s)

11817 23:29:47.653334  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11818 23:29:47.656739  Opened device: /dev/dri/card0

11819 23:29:47.660369  No KMS driver or no outputs, pipes: 8, outputs: 0

11820 23:29:47.666477  Subtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)

11821 23:29:47.673244  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11822 23:29:47.676264  Opened device: /dev/dri/card0

11823 23:29:47.679569  No KMS d<14>[   22.657017] [IGT] kms_atomic: exiting, ret=77

11824 23:29:47.683238  river or no outputs, pipes: 8, outputs: 0

11825 23:29:47.693151  Subtest plane-immutable-zpos: SKI<8>[   22.667994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>

11826 23:29:47.693415  Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11828 23:29:47.696388  P (0.000s)

11829 23:29:47.702685  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6<14>[   22.680500] [IGT] kms_atomic: executing

11830 23:29:47.709421  <14>[   22.680942] [IGT] kms_atomic: exiting, ret=77

11831 23:29:47.716271  <8>[   22.687259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>

11832 23:29:47.716524  Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11834 23:29:47.719383  .1.64-cip10-rt5 aarch64)

11835 23:29:47.723058  Opened<14>[   22.699665] [IGT] kms_atomic: executing

11836 23:29:47.729038   device: /dev/dr<14>[   22.700091] [IGT] kms_atomic: exiting, ret=77

11837 23:29:47.735753  <8>[   22.704704] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>

11838 23:29:47.735833  i/card0

11839 23:29:47.736067  Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11841 23:29:47.742590  No KMS driver or no outputs, pipes: 8, outputs: 0

11842 23:29:47.745846  Subtest test-only: SKIP (0.000s)

11843 23:29:47.752188  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11844 23:29:47.755832  <14>[   22.730906] [IGT] kms_atomic: executing

11845 23:29:47.762065  <14>[   22.731469] [IGT] kms_atomic: exiting, ret=77

11846 23:29:47.768616  <8>[   22.737242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>

11847 23:29:47.768861  Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11849 23:29:47.772046  Opened device: /dev/dri/card0

11850 23:29:47.775773  N<14>[   22.751710] [IGT] kms_atomic: executing

11851 23:29:47.782012  o KMS driver or <14>[   22.752125] [IGT] kms_atomic: exiting, ret=77

11852 23:29:47.792361  no outputs, pipe<8>[   22.756531] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>

11853 23:29:47.792485  s: 8, outputs: 0

11854 23:29:47.792726  Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11856 23:29:47.799069  Subtest plane-cursor-legacy: SKIP (0.000s)

11857 23:29:47.802095  IGT-Version: 1.27.1-g621c2<14>[   22.779492] [IGT] kms_atomic: executing

11858 23:29:47.808719  <14>[   22.780036] [IGT] kms_atomic: exiting, ret=77

11859 23:29:47.815248  <8>[   22.785588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>

11860 23:29:47.815505  Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11862 23:29:47.822130  d3 (aarch64) (Linux: 6.1.64-cip1<14>[   22.799043] [IGT] kms_atomic: executing

11863 23:29:47.825159  0-rt5 aarch64)

11864 23:29:47.828537  <14>[   22.799475] [IGT] kms_atomic: exiting, ret=77

11865 23:29:47.838114  <8>[   22.806967] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>

11866 23:29:47.838199  Opened device: /dev/dri/card0

11867 23:29:47.838439  Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11869 23:29:47.845031  No KMS driver or no outputs, pipes: 8, outputs: 0

11870 23:29:47.848356  Subtest plane-invalid-params: SKIP (0.000s)

11871 23:29:47.854689  IGT-Version: 1.27.1-g621c<14>[   22.832217] [IGT] kms_atomic: executing

11872 23:29:47.861491  <14>[   22.832820] [IGT] kms_atomic: exiting, ret=77

11873 23:29:47.868080  <8>[   22.838169] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>

11874 23:29:47.868337  Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11876 23:29:47.871719  <8>[   22.839625] <LAVA_SIGNAL_TESTSET STOP>

11877 23:29:47.871972  Received signal: <TESTSET> STOP
11878 23:29:47.872041  Closing test_set kms_atomic
11879 23:29:47.878064  <8>[   22.853672] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>

11880 23:29:47.878319  Received signal: <TESTSET> START kms_flip_event_leak
11881 23:29:47.878391  Starting test_set kms_flip_event_leak
11882 23:29:47.881429  2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

11883 23:29:47.888326  Opened device: <14>[   22.864944] [IGT] kms_flip_event_leak: executing

11884 23:29:47.888409  /dev/dri/card0

11885 23:29:47.897874  No KMS driver or no outputs, pip<14>[   22.870841] [IGT] kms_flip_event_leak: exiting, ret=77

11886 23:29:47.904721  <8>[   22.876966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>

11887 23:29:47.904979  Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11889 23:29:47.908021  <8>[   22.878405] <LAVA_SIGNAL_TESTSET STOP>

11890 23:29:47.908274  Received signal: <TESTSET> STOP
11891 23:29:47.908343  Closing test_set kms_flip_event_leak
11892 23:29:47.911170  es: 8, outputs: 0

11893 23:29:47.914592  Received signal: <TESTSET> START kms_prop_blob
11894 23:29:47.914699  Starting test_set kms_prop_blob
11895 23:29:47.917894  Subtest p<8>[   22.892577] <LAVA_SIGNAL_TESTSET START kms_prop_blob>

11896 23:29:47.920894  lane-invalid-params-fence: SKIP (0.000s)

11897 23:29:47.927815  IGT-Version: 1.27.1-g621c2d3 (aarc<14>[   22.904151] [IGT] kms_prop_blob: executing

11898 23:29:47.934241  <14>[   22.904444] [IGT] kms_prop_blob: starting subtest basic

11899 23:29:47.941105  <14>[   22.904500] [IGT] kms_prop_blob: finished subtest basic, SUCCESS

11900 23:29:47.944059  <14>[   22.904551] [IGT] kms_prop_blob: exiting, ret=0

11901 23:29:47.950557  <8>[   22.909903] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>

11902 23:29:47.950814  Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11904 23:29:47.953795  <14>[   22.927183] [IGT] kms_prop_blob: executing

11905 23:29:47.957454  h64) (Linux: 6.1.64-cip10-rt5 aarch64)

11906 23:29:47.967334  Opened d<14>[   22.938127] [IGT] kms_prop_blob: starting subtest blob-prop-core

11907 23:29:47.973889  <14>[   22.938182] [IGT] kms_prop_blob: finished subtest blob-prop-core, SUCCESS

11908 23:29:47.977375  <14>[   22.938230] [IGT] kms_prop_blob: exiting, ret=0

11909 23:29:47.984041  <8>[   22.944275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>

11910 23:29:47.984297  Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11912 23:29:47.987551  evice: /dev/dri/card0

11913 23:29:47.993738  No KMS dr<14>[   22.967663] [IGT] kms_prop_blob: executing

11914 23:29:48.000310  <14>[   22.967932] [IGT] kms_prop_blob: starting subtest blob-prop-validate

11915 23:29:48.007034  <14>[   22.968037] [IGT] kms_prop_blob: finished subtest blob-prop-validate, SUCCESS

11916 23:29:48.010540  <14>[   22.968083] [IGT] kms_prop_blob: exiting, ret=0

11917 23:29:48.020369  <8>[   22.974068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>

11918 23:29:48.020625  Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
11920 23:29:48.023241  iver or no outputs, pipes: 8, outputs: 0

11921 23:29:48.026579  Su<14>[   23.001449] [IGT] kms_prop_blob: executing

11922 23:29:48.033396  <14>[   23.001727] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime

11923 23:29:48.043016  <14>[   23.001806] [IGT] kms_prop_blob: finished subtest blob-prop-lifetime, SUCCESS

11924 23:29:48.046368  <14>[   23.001840] [IGT] kms_prop_blob: exiting, ret=0

11925 23:29:48.053198  <8>[   23.007629] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>

11926 23:29:48.053454  Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
11928 23:29:48.059837  <14>[   23.024297] [IGT] kms_prop_blob: executing

11929 23:29:48.063160  btest crtc-invalid-params: SKIP (0.000s)

11930 23:29:48.069605  IGT-Version: 1.27.<14>[   23.041280] [IGT] kms_prop_blob: starting subtest blob-multiple

11931 23:29:48.076195  <14>[   23.041411] [IGT] kms_prop_blob: finished subtest blob-multiple, SUCCESS

11932 23:29:48.083360  <14>[   23.041444] [IGT] kms_prop_blob: exiting, ret=0

11933 23:29:48.089473  <8>[   23.047289] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>

11934 23:29:48.089762  Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
11936 23:29:48.092784  <14>[   23.059998] [IGT] kms_prop_blob: executing

11937 23:29:48.102729  1-g621c2d3 (aarc<14>[   23.076544] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any

11938 23:29:48.109861  <14>[   23.076595] [IGT] kms_prop_blob: finished subtest invalid-get-prop-any, SUCCESS

11939 23:29:48.116051  <14>[   23.076633] [IGT] kms_prop_blob: exiting, ret=0

11940 23:29:48.122787  <8>[   23.085315] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>

11941 23:29:48.123044  Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11943 23:29:48.129525  h64) (Linux: 6.1<14>[   23.104846] [IGT] kms_prop_blob: executing

11944 23:29:48.136278  <14>[   23.105133] [IGT] kms_prop_blob: starting subtest invalid-get-prop

11945 23:29:48.136362  .64-cip10-rt5 aarch64)

11946 23:29:48.139104  Opened device: /dev/dri/card0

11947 23:29:48.146085  No KMS dr<14>[   23.105238] [IGT] kms_prop_blob: finished subtest invalid-get-prop, SUCCESS

11948 23:29:48.152852  <14>[   23.105306] [IGT] kms_prop_blob: exiting, ret=0

11949 23:29:48.159214  <8>[   23.123442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>

11950 23:29:48.159472  Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11952 23:29:48.162475  <14>[   23.134997] [IGT] kms_prop_blob: executing

11953 23:29:48.169134  iver or no outputs, pipes: 8, outputs: 0

11954 23:29:48.175905  Su<14>[   23.146930] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any

11955 23:29:48.182214  <14>[   23.146978] [IGT] kms_prop_blob: finished subtest invalid-set-prop-any, SUCCESS

11956 23:29:48.189336  <14>[   23.147014] [IGT] kms_prop_blob: exiting, ret=0

11957 23:29:48.195463  <8>[   23.153106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>

11958 23:29:48.195711  Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11960 23:29:48.205384  btest crtc-invalid-params-fence: SKIP (0.000s)[<14>[   23.178050] [IGT] kms_prop_blob: executing

11961 23:29:48.211984  <14>[   23.178432] [IGT] kms_prop_blob: starting subtest invalid-set-prop

11962 23:29:48.218759  <14>[   23.178507] [IGT] kms_prop_blob: finished subtest invalid-set-prop, SUCCESS

11963 23:29:48.222172  <14>[   23.178575] [IGT] kms_prop_blob: exiting, ret=0

11964 23:29:48.228871  <8>[   23.184367] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>

11965 23:29:48.229126  Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11967 23:29:48.235452  <8>[   23.186244] <LAVA_SIGNAL_TESTSET STOP>

11968 23:29:48.235702  Received signal: <TESTSET> STOP
11969 23:29:48.235771  Closing test_set kms_prop_blob
11970 23:29:48.238926  <8>[   23.211917] <LAVA_SIGNAL_TESTSET START kms_setmode>

11971 23:29:48.239007  0m

11972 23:29:48.239247  Received signal: <TESTSET> START kms_setmode
11973 23:29:48.239313  Starting test_set kms_setmode
11974 23:29:48.249006  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[   23.222163] [IGT] kms_setmode: executing

11975 23:29:48.255735  x: 6.1.64-cip10-<14>[   23.222485] [IGT] kms_setmode: starting subtest basic

11976 23:29:48.261931  <14>[   23.222537] [IGT] kms_setmode: finished subtest basic, SKIP

11977 23:29:48.265403  <14>[   23.222579] [IGT] kms_setmode: exiting, ret=77

11978 23:29:48.271759  <8>[   23.230985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>

11979 23:29:48.271841  rt5 aarch64)

11980 23:29:48.272076  Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11982 23:29:48.275152  Opened device: /dev/dri/card0

11983 23:29:48.278124  No <14>[   23.254055] [IGT] kms_setmode: executing

11984 23:29:48.288255  <14>[   23.254377] [IGT] kms_setmode: starting subtest basic-clone-single-crtc

11985 23:29:48.294775  <14>[   23.254425] [IGT] kms_setmode: finished subtest basic-clone-single-crtc, SKIP

11986 23:29:48.298172  <14>[   23.254472] [IGT] kms_setmode: exiting, ret=77

11987 23:29:48.307832  <8>[   23.261007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>

11988 23:29:48.308088  Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
11990 23:29:48.311551  KMS driver or no outputs, pipes: 8, outputs: 0

11991 23:29:48.314668  <14>[   23.289678] [IGT] kms_setmode: executing

11992 23:29:48.321157  <14>[   23.290000] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc

11993 23:29:48.331586  <14>[   23.290050] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc, SKIP

11994 23:29:48.334912  <14>[   23.290089] [IGT] kms_setmode: exiting, ret=77

11995 23:29:48.344554  <8>[   23.294998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>

11996 23:29:48.344896  Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
11998 23:29:48.348178  <14>[   23.312924] [IGT] kms_setmode: executing

11999 23:29:48.358149  Subtest atomic-invalid-params: SKIP (0.000s)<14>[   23.330258] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc

12000 23:29:48.361437  

12001 23:29:48.368308  IGT-Versio<14>[   23.330307] [IGT] kms_setmode: finished subtest invalid-clone-exclusive-crtc, SKIP

12002 23:29:48.374759  <14>[   23.330351] [IGT] kms_setmode: exiting, ret=77

12003 23:29:48.381031  <8>[   23.335465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>

12004 23:29:48.381739  Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12006 23:29:48.387800  n: 1.27.1-g621c2<14>[   23.364243] [IGT] kms_setmode: executing

12007 23:29:48.394400  <14>[   23.364569] [IGT] kms_setmode: starting subtest clone-exclusive-crtc

12008 23:29:48.401070  <14>[   23.364614] [IGT] kms_setmode: finished subtest clone-exclusive-crtc, SKIP

12009 23:29:48.407482  <14>[   23.364649] [IGT] kms_setmode: exiting, ret=77

12010 23:29:48.414632  <8>[   23.369448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>

12011 23:29:48.415322  Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12013 23:29:48.417378  <14>[   23.383700] [IGT] kms_setmode: executing

12014 23:29:48.427516  d3 (aarch64) (Li<14>[   23.400589] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing

12015 23:29:48.437398  <14>[   23.400631] [IGT] kms_setmode: finished subtest invalid-clone-single-crtc-stealing, SKIP

12016 23:29:48.440767  <14>[   23.400667] [IGT] kms_setmode: exiting, ret=77

12017 23:29:48.450443  <8>[   23.406056] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>

12018 23:29:48.451134  Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12020 23:29:48.453808  <8>[   23.407824] <LAVA_SIGNAL_TESTSET STOP>

12021 23:29:48.454491  Received signal: <TESTSET> STOP
12022 23:29:48.454851  Closing test_set kms_setmode
12023 23:29:48.457148  <8>[   23.433133] <LAVA_SIGNAL_TESTSET START kms_vblank>

12024 23:29:48.457978  Received signal: <TESTSET> START kms_vblank
12025 23:29:48.458349  Starting test_set kms_vblank
12026 23:29:48.460294  nux: 6.1.64-cip10-rt5 aarch64)

12027 23:29:48.463754  Opened device: /dev/dri/card0

12028 23:29:48.467209  N<14>[   23.443479] [IGT] kms_vblank: executing

12029 23:29:48.474119  <14>[   23.443958] [IGT] kms_vblank: exiting, ret=77

12030 23:29:48.480709  <8>[   23.450125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>

12031 23:29:48.481411  Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12033 23:29:48.487085  o KMS driver or no outputs, pipes: 8, outputs: 0<14>[   23.461894] [IGT] kms_vblank: executing

12034 23:29:48.487514  

12035 23:29:48.493322  Subtest at<14>[   23.462344] [IGT] kms_vblank: exiting, ret=77

12036 23:29:48.499987  <8>[   23.468224] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>

12037 23:29:48.500672  Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12039 23:29:48.503399  omic_plane_damage: SKIP (0.000s)

12040 23:29:48.510441  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12041 23:29:48.516802  Opened device: /<14>[   23.493023] [IGT] kms_vblank: executing

12042 23:29:48.517226  dev/dri/card0

12043 23:29:48.523172  No KMS driver or no outputs, pipe<14>[   23.498572] [IGT] kms_vblank: exiting, ret=77

12044 23:29:48.532996  s: 8, outputs: 0<8>[   23.503142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>

12045 23:29:48.533537  

12046 23:29:48.534407  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12048 23:29:48.536584  Subtest basic: SKIP (0.000s)

12049 23:29:48.546290  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)<14>[   23.523931] [IGT] kms_vblank: executing

12050 23:29:48.552917  <14>[   23.524682] [IGT] kms_vblank: exiting, ret=77

12051 23:29:48.560016  <8>[   23.529716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>

12052 23:29:48.560909  

12053 23:29:48.561956  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12055 23:29:48.563614  Opened device: /dev/dri/card0

12056 23:29:48.566336  Starting subtest: basic

12057 23:29:48.569753  Subtest basic: SUCCESS (0.000s)

12058 23:29:48.576671  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux<14>[   23.550545] [IGT] kms_vblank: executing

12059 23:29:48.579877  <14>[   23.551362] [IGT] kms_vblank: exiting, ret=77

12060 23:29:48.589542  <8>[   23.556417] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>

12061 23:29:48.590300  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12063 23:29:48.592984  : 6.1.64-cip10-rt5 aarch64)

12064 23:29:48.596207  Ope<14>[   23.571327] [IGT] kms_vblank: executing

12065 23:29:48.599821  ned device: /dev/dri/card0

12066 23:29:48.602953  Starting subtest: blob-prop-core

12067 23:29:48.606158  Subtest blob-prop-core: SUCCESS (0.000s)

12068 23:29:48.612910  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12069 23:29:48.616084  Opened device: /dev/dri/card0

12070 23:29:48.619593  Starting subtest: blob-prop-validate

12071 23:29:48.622919  Subtest blob-prop-validate: SUCCESS (0.000s)

12072 23:29:48.629548  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12073 23:29:48.632963  Opened device: /dev/dri/card0

12074 23:29:48.636108  Starting subtest: blob-prop-lifetime

12075 23:29:48.639055  Subtest blob-prop-lifetime: SUCCESS (0.000s)

12076 23:29:48.645627  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12077 23:29:48.649131  Opened device: /dev/dri/card0

12078 23:29:48.652747  Starting subtest: blob-multiple

12079 23:29:48.655889  Subtest blob-multiple: SUCCESS (0.000s)

12080 23:29:48.662166  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12081 23:29:48.665639  Opened device: /dev/dri/card0

12082 23:29:48.668889  Starting subtest: invalid-get-prop-any

12083 23:29:48.672667  Subtest invalid-get-prop-any: SUCCESS (0.000s)

12084 23:29:48.678871  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12085 23:29:48.681970  Opened device: /dev/dri/card0

12086 23:29:48.685327  Starting subtest: invalid-get-prop

12087 23:29:48.688565  Subtest invalid-get-prop: SUCCESS (0.000s)

12088 23:29:48.695310  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12089 23:29:48.699023  Opened device: /dev/dri/card0

12090 23:29:48.701898  Starting subtest: invalid-set-prop-any

12091 23:29:48.709027  Subtest invalid-set-prop-any: SUCCESS (0.000s)

12092 23:29:48.714973  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12093 23:29:48.718631  Opened device: /dev/dri/card0

12094 23:29:48.719271  Starting subtest: invalid-set-prop

12095 23:29:48.725462  Subtest invalid-set-prop: SUCCESS (0.000s)

12096 23:29:48.731998  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12097 23:29:48.735318  Opened device: /dev/dri/card0

12098 23:29:48.735897  Starting subtest: basic

12099 23:29:48.738446  No dynamic tests executed.

12100 23:29:48.741826  Subtest basic: SKIP (0.000s)

12101 23:29:48.748564  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12102 23:29:48.752185  Opened device: /dev/dri/card0

12103 23:29:48.755190  Starting subtest: basic-clone-single-crtc

12104 23:29:48.758860  No dynamic tests executed.

12105 23:29:48.761758  Subtest basic-clone-single-crtc: SKIP (0.000s)

12106 23:29:48.768027  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12107 23:29:48.771343  Opened device: /dev/dri/card0

12108 23:29:48.775261  Starting subtest: invalid-clone-single-crtc

12109 23:29:48.778090  No dynamic tests executed.

12110 23:29:48.781743  Subtest invalid-clone-single-crtc: SKIP (0.000s)

12111 23:29:48.788536  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12112 23:29:48.791617  Opened device: /dev/dri/card0

12113 23:29:48.795089  Starting subtest: invalid-clone-exclusive-crtc

12114 23:29:48.798304  No dynamic tests executed.

12115 23:29:48.804672  Subtest invalid-clone-exclusive-crtc: SKIP (0.000s)

12116 23:29:48.808687  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12117 23:29:48.811551  Opened device: /dev/dri/card0

12118 23:29:48.814873  Starting subtest: clone-exclusive-crtc

12119 23:29:48.817640  No dynamic tests executed.

12120 23:29:48.821512  Subtest clone-exclusive-crtc: SKIP (0.000s)

12121 23:29:48.828456  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12122 23:29:48.831650  Opened device: /dev/dri/card0

12123 23:29:48.838008  Starting subtest: invalid-clone-single-crtc-stealing

12124 23:29:48.838435  No dynamic tests executed.

12125 23:29:48.844736  Subtest invalid-clone-single-crtc-stealing: SKIP (0.000s)

12126 23:29:48.851025  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12127 23:29:48.854353  Opened device: /dev/dri/card0

12128 23:29:48.857885  No KMS driver or no outputs, pipes: 8, outputs: 0

12129 23:29:48.861265  Subtest invalid: SKIP (0.000s)

12130 23:29:48.867806  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12131 23:29:48.871112  Opened device: /dev/dri/card0

12132 23:29:48.874449  No KMS driver or no outputs, pipes: 8, outputs: 0

12133 23:29:48.878176  Subtest crtc-id: SKIP (0.000s)

12134 23:29:48.884136  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12135 23:29:48.887809  Opened device: /dev/dri/card0

12136 23:29:48.891163  No KMS driver or no outputs, pipes: 8, outputs: 0

12137 23:29:48.897563  Subtest pipe-A-accuracy-idle: SKIP (0.000s)

12138 23:29:48.904289  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12139 23:29:48.907347  Opened device: /dev/dri/card0

12140 23:29:48.911028  No KMS driver or no outputs, pipes: 8, outputs: 0

12141 23:29:48.914415  Subtest pipe-A-query-idle: SKIP (0.000s)

12142 23:29:48.920456  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12143 23:29:48.924202  Opened device: /dev/dri/card0

12144 23:29:48.927300  No KMS driver or no outputs, pipes: 8, outputs: 0

12145 23:29:48.937133  Subtest pipe-A-query-idle-hang: SKIP (<14>[   23.909374] [IGT] kms_vblank: exiting, ret=77

12146 23:29:48.943822  <8>[   23.914914] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>

12147 23:29:48.944573  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12149 23:29:48.947144  0.000s)

12150 23:29:48.950496  IGT-Version: 1.27.1<14>[   23.926786] [IGT] kms_vblank: executing

12151 23:29:48.957251  -g621c2d3 (aarch<14>[   23.927264] [IGT] kms_vblank: exiting, ret=77

12152 23:29:48.967030  <8>[   23.931405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>

12153 23:29:48.967721  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12155 23:29:48.970579  64) (Linux: 6.1.64-cip10-rt5 aarch64)

12156 23:29:48.971012  Opened device: /dev/dri/card0

12157 23:29:48.980075  No KMS driver or no outputs, pipes: 8, out<14>[   23.953864] [IGT] kms_vblank: executing

12158 23:29:48.983373  <14>[   23.954710] [IGT] kms_vblank: exiting, ret=77

12159 23:29:48.990044  <8>[   23.960418] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>

12160 23:29:48.990731  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12162 23:29:48.993232  puts: 0

12163 23:29:49.000004  Subtest pipe-A-query-forked: SKIP (<14>[   23.973868] [IGT] kms_vblank: executing

12164 23:29:49.003550  <14>[   23.974396] [IGT] kms_vblank: exiting, ret=77

12165 23:29:49.013315  <8>[   23.978765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>

12166 23:29:49.013791  0.000s)

12167 23:29:49.014402  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12169 23:29:49.020097  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12170 23:29:49.023375  Opened device: /dev/dri/card0

12171 23:29:49.026869  No KMS dri<14>[   24.004861] [IGT] kms_vblank: executing

12172 23:29:49.029957  ver or no outputs, pipes: 8, outputs: 0

12173 23:29:49.036783  Sub<14>[   24.010519] [IGT] kms_vblank: exiting, ret=77

12174 23:29:49.043441  <8>[   24.015723] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>

12175 23:29:49.044289  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12177 23:29:49.049629  test pipe-A-query-forked-hang: SKIP (0.000s)

12178 23:29:49.056468  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12179 23:29:49.059648  Open<14>[   24.035268] [IGT] kms_vblank: executing

12180 23:29:49.066727  <14>[   24.036156] [IGT] kms_vblank: exiting, ret=77

12181 23:29:49.072817  <8>[   24.041925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>

12182 23:29:49.073484  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12184 23:29:49.076088  ed device: /dev/dri/card0

12185 23:29:49.079283  No KM<14>[   24.055495] [IGT] kms_vblank: executing

12186 23:29:49.085911  S driver or no o<14>[   24.055996] [IGT] kms_vblank: exiting, ret=77

12187 23:29:49.092588  <8>[   24.060751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>

12188 23:29:49.093013  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12190 23:29:49.095596  utputs, pipes: 8, outputs: 0

12191 23:29:49.099030  Subtest pipe-A-query-busy: SKIP (0.000s)

12192 23:29:49.105340  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   24.084423] [IGT] kms_vblank: executing

12193 23:29:49.112272  rch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12194 23:29:49.115407  Opened<14>[   24.085377] [IGT] kms_vblank: exiting, ret=77

12195 23:29:49.122019  <8>[   24.094690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>

12196 23:29:49.122393  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12198 23:29:49.125442   device: /dev/dri/card0

12199 23:29:49.132092  No KMS driver or no out<14>[   24.107513] [IGT] kms_vblank: executing

12200 23:29:49.135537  <14>[   24.108066] [IGT] kms_vblank: exiting, ret=77

12201 23:29:49.145113  <8>[   24.113651] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>

12202 23:29:49.145365  puts, pipes: 8, outputs: 0

12203 23:29:49.145692  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12205 23:29:49.151915  <14>[   24.127021] [IGT] kms_vblank: executing

12206 23:29:49.155117  <14>[   24.127588] [IGT] kms_vblank: exiting, ret=77

12207 23:29:49.165028  <8>[   24.131833] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>

12208 23:29:49.165398  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12210 23:29:49.171698  Subtest pipe-A-query-busy-hang: SKIP (0.000s)[0<14>[   24.146650] [IGT] kms_vblank: executing

12211 23:29:49.178541  <14>[   24.147176] [IGT] kms_vblank: exiting, ret=77

12212 23:29:49.185585  <8>[   24.153460] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>

12213 23:29:49.185701  m

12214 23:29:49.185981  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12216 23:29:49.191884  IGT-Version: 1.27.1-g621c2d3 <14>[   24.167068] [IGT] kms_vblank: executing

12217 23:29:49.195450  <14>[   24.167592] [IGT] kms_vblank: exiting, ret=77

12218 23:29:49.205007  <8>[   24.172947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>

12219 23:29:49.205359  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12221 23:29:49.208267  (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12222 23:29:49.211974  Opened device: /dev/dri/card0

12223 23:29:49.215379  No KMS driver or no outputs, pipes: 8, outputs: 0

12224 23:29:49.218453  <14>[   24.195378] [IGT] kms_vblank: executing

12225 23:29:49.225307  [1mSubtest pipe-<14>[   24.196198] [IGT] kms_vblank: exiting, ret=77

12226 23:29:49.232353  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12228 23:29:49.235413  <8>[   24.201101] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>

12229 23:29:49.238433  A-query-forked-busy: SKIP (0.000s)

12230 23:29:49.244795  IGT-Version: 1.27.1-g621c2d3 (aarch64) (<14>[   24.219674] [IGT] kms_vblank: executing

12231 23:29:49.248148  <14>[   24.220517] [IGT] kms_vblank: exiting, ret=77

12232 23:29:49.258224  <8>[   24.226092] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>

12233 23:29:49.258913  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12235 23:29:49.264801  Linux: 6.1.64-ci<14>[   24.239990] [IGT] kms_vblank: executing

12236 23:29:49.268540  <14>[   24.240467] [IGT] kms_vblank: exiting, ret=77

12237 23:29:49.275306  <8>[   24.246422] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>

12238 23:29:49.276130  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12240 23:29:49.278006  p10-rt5 aarch64)

12241 23:29:49.281518  Opened device: /dev/dri/card0

12242 23:29:49.284926  <14>[   24.258576] [IGT] kms_vblank: executing

12243 23:29:49.288806  <14>[   24.259067] [IGT] kms_vblank: exiting, ret=77

12244 23:29:49.298124  <8>[   24.264391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>

12245 23:29:49.298698  

12246 23:29:49.299345  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12248 23:29:49.304446  No KMS driver o<14>[   24.280387] [IGT] kms_vblank: executing

12249 23:29:49.307993  <14>[   24.280822] [IGT] kms_vblank: exiting, ret=77

12250 23:29:49.317666  <8>[   24.286860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>

12251 23:29:49.318349  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12253 23:29:49.324367  r no outputs, pipes: 8, outputs:<14>[   24.299331] [IGT] kms_vblank: executing

12254 23:29:49.324790   0

12255 23:29:49.331233  Subtest <14>[   24.299802] [IGT] kms_vblank: exiting, ret=77

12256 23:29:49.337314  <8>[   24.303824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>

12257 23:29:49.338029  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12259 23:29:49.344117  pipe-A-query-forked-busy-hang: SKIP (0.000s)

12260 23:29:49.350792  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[   24.326081] [IGT] kms_vblank: executing

12261 23:29:49.357299  <14>[   24.326925] [IGT] kms_vblank: exiting, ret=77

12262 23:29:49.363932  <8>[   24.332491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>

12263 23:29:49.364472  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12265 23:29:49.367056   6.1.64-cip10-rt5 aarch64)

12266 23:29:49.370353  Open<14>[   24.347109] [IGT] kms_vblank: executing

12267 23:29:49.377015  <14>[   24.347590] [IGT] kms_vblank: exiting, ret=77

12268 23:29:49.383472  <8>[   24.353548] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>

12269 23:29:49.384079  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12271 23:29:49.387303  ed device: /dev/dri/card0

12272 23:29:49.391048  No KMS driver or no outputs, pipes: 8, outputs: 0

12273 23:29:49.396787  Subtest pipe-A-wait-idle: SKIP (0.000s)

12274 23:29:49.403546  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<14>[   24.377630] [IGT] kms_vblank: executing

12275 23:29:49.410158  <14>[   24.378501] [IGT] kms_vblank: exiting, ret=77

12276 23:29:49.417138  <8>[   24.383579] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>

12277 23:29:49.418024  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12279 23:29:49.420395  1.64-cip10-rt5 aarch64)

12280 23:29:49.423710  Opened device: /dev/dri/card0

12281 23:29:49.426919  No KMS d<14>[   24.402481] [IGT] kms_vblank: executing

12282 23:29:49.434015  <14>[   24.403343] [IGT] kms_vblank: exiting, ret=77

12283 23:29:49.440350  <8>[   24.408445] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>

12284 23:29:49.441229  Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12286 23:29:49.450251  river or no outputs, pipes: 8, o<14>[   24.423838] [IGT] kms_vblank: executing

12287 23:29:49.453233  <14>[   24.424307] [IGT] kms_vblank: exiting, ret=77

12288 23:29:49.460678  <8>[   24.430759] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>

12289 23:29:49.461413  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12291 23:29:49.463603  utputs: 0

12292 23:29:49.466856  Subtest pipe-A-wait-idle-hang: SKIP (0.000s)

12293 23:29:49.473559  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12294 23:29:49.476983  Opened device: /dev/dri/card0

12295 23:29:49.480566  No KMS<14>[   24.453372] [IGT] kms_vblank: executing

12296 23:29:49.486398  <14>[   24.454208] [IGT] kms_vblank: exiting, ret=77

12297 23:29:49.493022  <8>[   24.458925] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>

12298 23:29:49.493763  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12300 23:29:49.496592   driver or no outputs, pipes: 8, outputs: 0

12301 23:29:49.502772  Subtest pipe-A-wait-forked: SKI<14>[   24.479626] [IGT] kms_vblank: executing

12302 23:29:49.509957  <14>[   24.480436] [IGT] kms_vblank: exiting, ret=77

12303 23:29:49.515990  <8>[   24.485099] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>

12304 23:29:49.516416  P (0.000s)

12305 23:29:49.517007  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12307 23:29:49.526000  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   24.498525] [IGT] kms_vblank: executing

12308 23:29:49.529875  <14>[   24.499000] [IGT] kms_vblank: exiting, ret=77

12309 23:29:49.536088  <8>[   24.504006] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>

12310 23:29:49.536907  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12312 23:29:49.542448  rch64) (Linux: 6.1.64-cip10-rt5 <14>[   24.519235] [IGT] kms_vblank: executing

12313 23:29:49.549350  <14>[   24.519714] [IGT] kms_vblank: exiting, ret=77

12314 23:29:49.555790  <8>[   24.526340] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>

12315 23:29:49.556744  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12317 23:29:49.559280  aarch64)

12318 23:29:49.562431  Opened device: /dev/dr<14>[   24.538948] [IGT] kms_vblank: executing

12319 23:29:49.565474  i/card0

12320 23:29:49.568823  No KMS <14>[   24.539393] [IGT] kms_vblank: exiting, ret=77

12321 23:29:49.576013  <8>[   24.545448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>

12322 23:29:49.576778  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12324 23:29:49.585756  driver or no outputs, pipes: 8, <14>[   24.559409] [IGT] kms_vblank: executing

12325 23:29:49.586322  outputs: 0

12326 23:29:49.589017  Subtest pipe-A-wait-forked-hang: SKIP (0.000s)

12327 23:29:49.595620  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12328 23:29:49.598517  Opened device: /dev/dri/card0

12329 23:29:49.602346  No KMS driver or no outputs, pipes: 8, outputs: 0

12330 23:29:49.608474  Subtest pipe-A-wait-busy: SKIP (0.000s)

12331 23:29:49.615428  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12332 23:29:49.616006  Opened device: /dev/dri/card0

12333 23:29:49.621922  No KMS driver or no outputs, pipes: 8, outputs: 0

12334 23:29:49.625134  Subtest pipe-A-wait-busy-hang: SKIP (0.000s)

12335 23:29:49.632079  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12336 23:29:49.635383  Opened device: /dev/dri/card0

12337 23:29:49.638809  No KMS driver or no outputs, pipes: 8, outputs: 0

12338 23:29:49.645154  Subtest pipe-A-wait-forked-busy: SKIP (0.000s)

12339 23:29:49.652537  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12340 23:29:49.655454  Opened device: /dev/dri/card0

12341 23:29:49.658558  No KMS driver or no outputs, pipes: 8, outputs: 0

12342 23:29:49.661860  Subtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)

12343 23:29:49.668445  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12344 23:29:49.671766  Opened device: /dev/dri/card0

12345 23:29:49.678362  No KMS driver or no outputs, pipes: 8, outputs: 0

12346 23:29:49.681765  Subtest pipe-A-ts-continuation-idle: SKIP (0.000s)

12347 23:29:49.689062  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12348 23:29:49.691734  Opened device: /dev/dri/card0

12349 23:29:49.695171  No KMS driver or no outputs, pipes: 8, outputs: 0

12350 23:29:49.701530  Subtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)

12351 23:29:49.707884  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12352 23:29:49.711572  Opened device: /dev/dri/card0

12353 23:29:49.714554  No KMS driver or no outputs, pipes: 8, outputs: 0

12354 23:29:49.721148  Subtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)

12355 23:29:49.727935  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12356 23:29:49.728371  Opened device: /dev/dri/card0

12357 23:29:49.734648  No KMS driver or no outputs, pipes: 8, outputs: 0

12358 23:29:49.740992  Subtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)

12359 23:29:49.747681  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12360 23:29:49.748098  Opened device: /dev/dri/card0

12361 23:29:49.754429  No KMS driver or no outputs, pipes: 8, outputs: 0

12362 23:29:49.757944  Subtest pipe-A-ts-continuation-suspend: SKIP (0.000s)

12363 23:29:49.764655  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12364 23:29:49.768082  Opened device: /dev/dri/card0

12365 23:29:49.771124  No KMS driver or no outputs, pipes: 8, outputs: 0

12366 23:29:49.777492  Subtest pipe-A-ts-continuation-modeset: SKIP (0.000s)

12367 23:29:49.784077  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12368 23:29:49.787162  Opened device: /dev/dri/card0

12369 23:29:49.791184  No KMS driver or no outputs, pipes: 8, outputs: 0

12370 23:29:49.797655  Subtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)

12371 23:29:49.803957  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12372 23:29:49.807580  Opened device: /dev/dri/card0

12373 23:29:49.810850  No KMS driver or no outputs, pipes: 8, outputs: 0

12374 23:29:49.817341  Subtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)

12375 23:29:49.823831  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12376 23:29:49.827313  Opened device: /dev/dri/card0

12377 23:29:49.830602  No KMS driver or no outputs, pipes: 8, outputs: 0

12378 23:29:49.833952  Subtest pipe-B-accuracy-idle: SKIP (0.000s)

12379 23:29:49.840073  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12380 23:29:49.843424  Opened device: /dev/dri/card0

12381 23:29:49.846868  No KMS driver or no outputs, pipes: 8, outputs: 0

12382 23:29:49.853700  Subtest pipe-B-query-idle: SKIP (0.000s)

12383 23:29:49.860492  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12384 23:29:49.860908  Opened device: /dev/dri/card0

12385 23:29:49.867146  No KMS driver or no outputs, pipes: 8, outputs: 0

12386 23:29:49.870298  Subtest pipe-B-query-idle-hang: SKIP (0.000s)

12387 23:29:49.876762  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12388 23:29:49.880089  Opened device: /dev/dri/card0

12389 23:29:49.883618  No KMS driver or no outputs, pipes: 8, outputs: 0

12390 23:29:49.890041  Subtest pipe-B-query-forked: SKIP (0.000s)

12391 23:29:49.896869  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12392 23:29:49.897329  Opened device: /dev/dri/card0

12393 23:29:49.903260  No KMS driver or no outputs, pipes: 8, outputs: 0

12394 23:29:49.906493  Subtest pipe-B-query-forked-hang: SKIP (0.000s)

12395 23:29:49.913079  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12396 23:29:49.916658  Opened device: /dev/dri/card0

12397 23:29:49.926138  No KMS driver or no outputs, pipes: 8, out<14>[   24.897521] [IGT] kms_vblank: exiting, ret=77

12398 23:29:49.926657  puts: 0

12399 23:29:49.932655  Sub<8>[   24.902326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>

12400 23:29:49.933506  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12402 23:29:49.939858  test pipe-B-quer<14>[   24.916508] [IGT] kms_vblank: executing

12403 23:29:49.946616  y-busy: SKIP (0.<14>[   24.916973] [IGT] kms_vblank: exiting, ret=77

12404 23:29:49.947154  000s)

12405 23:29:49.956393  IGT-V<8>[   24.921038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>

12406 23:29:49.957293  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12408 23:29:49.962911  ersion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12409 23:29:49.963450  Opened device: /dev/dri/card0

12410 23:29:49.972849  No KMS driver or no outputs, pipes: 8, outpu<14>[   24.945292] [IGT] kms_vblank: executing

12411 23:29:49.976483  <14>[   24.946308] [IGT] kms_vblank: exiting, ret=77

12412 23:29:49.985835  <8>[   24.951828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>

12413 23:29:49.986378  ts: 0

12414 23:29:49.987005  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12416 23:29:49.992768  Subtest pipe-B-query-<14>[   24.967402] [IGT] kms_vblank: executing

12417 23:29:49.995664  <14>[   24.967914] [IGT] kms_vblank: exiting, ret=77

12418 23:29:50.002356  <8>[   24.972360] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>

12419 23:29:50.003205  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12421 23:29:50.005644  busy-hang: SKIP (0.000s)

12422 23:29:50.012558  IGT-Version: 1.27.<14>[   24.986422] [IGT] kms_vblank: executing

12423 23:29:50.016141  <14>[   24.986968] [IGT] kms_vblank: exiting, ret=77

12424 23:29:50.025806  <8>[   24.992942] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>

12425 23:29:50.026547  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12427 23:29:50.028930  1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12428 23:29:50.032466  Opened device: /dev/dri/card0

12429 23:29:50.039124  No KMS driver or no outputs, pipes: 8, ou<14>[   25.015579] [IGT] kms_vblank: executing

12430 23:29:50.045329  <14>[   25.016369] [IGT] kms_vblank: exiting, ret=77

12431 23:29:50.052222  <8>[   25.021524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>

12432 23:29:50.052806  tputs: 0

12433 23:29:50.053457  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12435 23:29:50.062164  Subtest pipe-B-query-forked-busy: <14>[   25.034770] [IGT] kms_vblank: executing

12436 23:29:50.065532  <14>[   25.035281] [IGT] kms_vblank: exiting, ret=77

12437 23:29:50.071985  <8>[   25.042513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>

12438 23:29:50.072680  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12440 23:29:50.075766  SKIP (0.000s)

12441 23:29:50.082481  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12442 23:29:50.085868  Opened device: /dev/dri/card0

12443 23:29:50.091914  No KMS driver or no outputs, pipes: <14>[   25.065534] [IGT] kms_vblank: executing

12444 23:29:50.095543  <14>[   25.066336] [IGT] kms_vblank: exiting, ret=77

12445 23:29:50.102285  <8>[   25.071139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>

12446 23:29:50.103076  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12448 23:29:50.105608  8, outputs: 0

12449 23:29:50.112538  Subtest pipe-B-query-forked-b<14>[   25.085928] [IGT] kms_vblank: executing

12450 23:29:50.115161  <14>[   25.086439] [IGT] kms_vblank: exiting, ret=77

12451 23:29:50.125227  <8>[   25.092905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>

12452 23:29:50.126062  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12454 23:29:50.128735  usy-hang: SKIP (0.000s)

12455 23:29:50.132044  IGT<14>[   25.106758] [IGT] kms_vblank: executing

12456 23:29:50.138988  -Version: 1.27.1<14>[   25.107226] [IGT] kms_vblank: exiting, ret=77

12457 23:29:50.145147  <8>[   25.114222] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>

12458 23:29:50.145959  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12460 23:29:50.151912  -g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12461 23:29:50.152457  Opened device: /dev/dri/card0

12462 23:29:50.158432  No KMS driver or no output<14>[   25.136693] [IGT] kms_vblank: executing

12463 23:29:50.161540  s, pipes: 8, outputs: 0

12464 23:29:50.168089  Subtest pipe-B-wait<14>[   25.141889] [IGT] kms_vblank: exiting, ret=77

12465 23:29:50.178170  -idle: SKIP (0.0<8>[   25.146528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>

12466 23:29:50.178695  00s)

12467 23:29:50.179382  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12469 23:29:50.184405  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12470 23:29:50.191492  Opened device: /dev/dri/card<14>[   25.168671] [IGT] kms_vblank: executing

12471 23:29:50.192035  0

12472 23:29:50.201412  No KMS driver or no outputs, pipes: 8, output<14>[   25.174519] [IGT] kms_vblank: exiting, ret=77

12473 23:29:50.207609  <8>[   25.178846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>

12474 23:29:50.208385  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12476 23:29:50.211257  s: 0

12477 23:29:50.214670  Subtest pipe-B-wait-id<14>[   25.191351] [IGT] kms_vblank: executing

12478 23:29:50.221397  le-hang: SKIP (0<14>[   25.191860] [IGT] kms_vblank: exiting, ret=77

12479 23:29:50.231224  <8>[   25.198683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>

12480 23:29:50.231803  .000s)

12481 23:29:50.232457  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12483 23:29:50.237680  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12484 23:29:50.241071  Opened device: /dev/dri/card0

12485 23:29:50.247766  No KMS driver or no outputs<14>[   25.221519] [IGT] kms_vblank: executing

12486 23:29:50.250597  <14>[   25.222358] [IGT] kms_vblank: exiting, ret=77

12487 23:29:50.260874  <8>[   25.227354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>

12488 23:29:50.261561  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12490 23:29:50.263838  , pipes: 8, outputs: 0

12491 23:29:50.267594  Subt<14>[   25.243163] [IGT] kms_vblank: executing

12492 23:29:50.274145  est pipe-B-wait-<14>[   25.243679] [IGT] kms_vblank: exiting, ret=77

12493 23:29:50.284110  <8>[   25.250372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>

12494 23:29:50.284710  forked: SKIP (0.000s)

12495 23:29:50.285325  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12497 23:29:50.293687  IGT-Version: 1.27.1-g621c2d3 (aarch64<14>[   25.265243] [IGT] kms_vblank: executing

12498 23:29:50.297144  <14>[   25.266087] [IGT] kms_vblank: exiting, ret=77

12499 23:29:50.307388  <8>[   25.270429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>

12500 23:29:50.308174  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12502 23:29:50.310668  ) (Linux: 6.1.64<14>[   25.288197] [IGT] kms_vblank: executing

12503 23:29:50.317107  -cip10-rt5 aarch<14>[   25.288710] [IGT] kms_vblank: exiting, ret=77

12504 23:29:50.326902  <8>[   25.295070] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>

12505 23:29:50.327460  64)

12506 23:29:50.328075  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12508 23:29:50.330610  Opened devi<14>[   25.308424] [IGT] kms_vblank: executing

12509 23:29:50.336953  ce: /dev/dri/car<14>[   25.308911] [IGT] kms_vblank: exiting, ret=77

12510 23:29:50.347495  <8>[   25.312960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>

12511 23:29:50.348074  d0

12512 23:29:50.348735  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12514 23:29:50.350320  No KMS driver or no outputs, pipes: 8, outputs: 0

12515 23:29:50.356640  Subtest pipe-B-wait-forked-hang: SKIP (0.000s)

12516 23:29:50.360128  I<14>[   25.337135] [IGT] kms_vblank: executing

12517 23:29:50.366825  GT-Version: 1.27.1-g621c2d3 (aar<14>[   25.343554] [IGT] kms_vblank: exiting, ret=77

12518 23:29:50.376788  <8>[   25.347765] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>

12519 23:29:50.377620  Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12521 23:29:50.383504  ch64) (Linux: 6.1.64-cip10-rt5 a<14>[   25.359333] [IGT] kms_vblank: executing

12522 23:29:50.389775  <14>[   25.359809] [IGT] kms_vblank: exiting, ret=77

12523 23:29:50.390248  arch64)

12524 23:29:50.396457  Opened <8>[   25.363915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>

12525 23:29:50.397329  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12527 23:29:50.399781  device: /dev/dri/card0

12528 23:29:50.403460  No KMS driver or no outputs, pipes: 8, outputs: 0

12529 23:29:50.409511  Subtest pipe-B-wait-busy: SKIP (0.000s)

12530 23:29:50.416406  IGT-Version: 1.27.1-g621c2d3 (aarch6<14>[   25.391194] [IGT] kms_vblank: executing

12531 23:29:50.419847  <14>[   25.391974] [IGT] kms_vblank: exiting, ret=77

12532 23:29:50.426259  <8>[   25.396707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>

12533 23:29:50.427000  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12535 23:29:50.429773  4) (Linux: 6.1.64-cip10-rt5 aarch64)

12536 23:29:50.436472  Opened dev<14>[   25.410237] [IGT] kms_vblank: executing

12537 23:29:50.439720  <14>[   25.410703] [IGT] kms_vblank: exiting, ret=77

12538 23:29:50.449322  <8>[   25.416017] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>

12539 23:29:50.449913  ice: /dev/dri/card0

12540 23:29:50.450555  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12542 23:29:50.456143  No KMS driv<14>[   25.431170] [IGT] kms_vblank: executing

12543 23:29:50.459425  <14>[   25.431655] [IGT] kms_vblank: exiting, ret=77

12544 23:29:50.469197  <8>[   25.438314] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>

12545 23:29:50.469996  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12547 23:29:50.472883  er or no outputs, pipes: 8, outputs: 0

12548 23:29:50.476369  Subt<14>[   25.450459] [IGT] kms_vblank: executing

12549 23:29:50.482660  <14>[   25.450901] [IGT] kms_vblank: exiting, ret=77

12550 23:29:50.489474  <8>[   25.457962] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>

12551 23:29:50.490384  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12553 23:29:50.495989  est pipe-B-wait-busy-hang: SKIP <14>[   25.471553] [IGT] kms_vblank: executing

12554 23:29:50.502286  <14>[   25.472012] [IGT] kms_vblank: exiting, ret=77

12555 23:29:50.509218  <8>[   25.476042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>

12556 23:29:50.509836  (0.000s)

12557 23:29:50.510614  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12559 23:29:50.515819  IGT-Version: 1.27.1-g621c2d3 (aarc<14>[   25.490647] [IGT] kms_vblank: executing

12560 23:29:50.522331  <14>[   25.491121] [IGT] kms_vblank: exiting, ret=77

12561 23:29:50.529114  <8>[   25.497510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>

12562 23:29:50.529904  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12564 23:29:50.535356  h64) (Linux: 6.1.64-cip10-rt5 aa<14>[   25.511569] [IGT] kms_vblank: executing

12565 23:29:50.542020  <14>[   25.512024] [IGT] kms_vblank: exiting, ret=77

12566 23:29:50.548977  <8>[   25.516122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>

12567 23:29:50.549643  rch64)

12568 23:29:50.550482  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12570 23:29:50.555629  Opened device: /dev/dri/<14>[   25.531286] [IGT] kms_vblank: executing

12571 23:29:50.556231  card0

12572 23:29:50.561837  No KMS dr<14>[   25.531764] [IGT] kms_vblank: exiting, ret=77

12573 23:29:50.569356  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12575 23:29:50.572486  <8>[   25.535899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>

12576 23:29:50.575708  iver or no outputs, pipes: 8, outputs: 0

12577 23:29:50.578658  Subtest pipe-B-wait-forked-busy: SKIP (0.000s)

12578 23:29:50.585635  IGT-Version: 1<14>[   25.558413] [IGT] kms_vblank: executing

12579 23:29:50.588613  .27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12580 23:29:50.592054  Opened device: /dev/dri/card0

12581 23:29:50.595230  No KMS driver or no outputs, pipes: 8, outputs: 0

12582 23:29:50.602526  Subtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)

12583 23:29:50.608662  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12584 23:29:50.611705  Opened device: /dev/dri/card0

12585 23:29:50.614898  No KMS driver or no outputs, pipes: 8, outputs: 0

12586 23:29:50.622179  Subtest pipe-B-ts-continuation-idle: SKIP (0.000s)

12587 23:29:50.628469  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12588 23:29:50.628941  Opened device: /dev/dri/card0

12589 23:29:50.635038  No KMS driver or no outputs, pipes: 8, outputs: 0

12590 23:29:50.638455  Subtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)

12591 23:29:50.645173  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12592 23:29:50.648494  Opened device: /dev/dri/card0

12593 23:29:50.654976  No KMS driver or no outputs, pipes: 8, outputs: 0

12594 23:29:50.658366  Subtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)

12595 23:29:50.665103  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12596 23:29:50.668215  Opened device: /dev/dri/card0

12597 23:29:50.671664  No KMS driver or no outputs, pipes: 8, outputs: 0

12598 23:29:50.678801  Subtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)

12599 23:29:50.684940  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12600 23:29:50.687999  Opened device: /dev/dri/card0

12601 23:29:50.691565  No KMS driver or no outputs, pipes: 8, outputs: 0

12602 23:29:50.698423  Subtest pipe-B-ts-continuation-suspend: SKIP (0.000s)

12603 23:29:50.704660  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12604 23:29:50.708148  Opened device: /dev/dri/card0

12605 23:29:50.711323  No KMS driver or no outputs, pipes: 8, outputs: 0

12606 23:29:50.717754  Subtest pipe-B-ts-continuation-modeset: SKIP (0.000s)

12607 23:29:50.721142  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12608 23:29:50.724207  Opened device: /dev/dri/card0

12609 23:29:50.731074  No KMS driver or no outputs, pipes: 8, outputs: 0

12610 23:29:50.734986  Subtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)

12611 23:29:50.740934  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12612 23:29:50.744722  Opened device: /dev/dri/card0

12613 23:29:50.747533  No KMS driver or no outputs, pipes: 8, outputs: 0

12614 23:29:50.754108  Subtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)

12615 23:29:50.761244  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12616 23:29:50.764770  Opened device: /dev/dri/card0

12617 23:29:50.767969  No KMS driver or no outputs, pipes: 8, outputs: 0

12618 23:29:50.774370  Subtest pipe-C-accuracy-idle: SKIP (0.000s)

12619 23:29:50.781310  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12620 23:29:50.781978  Opened device: /dev/dri/card0

12621 23:29:50.787343  No KMS driver or no outputs, pipes: 8, outputs: 0

12622 23:29:50.791006  Subtest pipe-C-query-idle: SKIP (0.000s)

12623 23:29:50.797756  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12624 23:29:50.800902  Opened device: /dev/dri/card0

12625 23:29:50.804583  No KMS driver or no outputs, pipes: 8, outputs: 0

12626 23:29:50.810979  Subtest pipe-C-query-idle-hang: SKIP (0.000s)

12627 23:29:50.817438  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12628 23:29:50.817976  Opened device: /dev/dri/card0

12629 23:29:50.823946  No KMS driver or no outputs, pipes: 8, outputs: 0

12630 23:29:50.827897  Subtest pipe-C-query-forked: SKIP (0.000s)

12631 23:29:50.834281  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12632 23:29:50.837193  Opened device: /dev/dri/card0

12633 23:29:50.840544  No KMS driver or no outputs, pipes: 8, outputs: 0

12634 23:29:50.847013  Subtest pipe-C-query-forked-hang: SKIP (0.000s)

12635 23:29:50.853536  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12636 23:29:50.854031  Opened device: /dev/dri/card0

12637 23:29:50.860684  No KMS driver or no outputs, pipes: 8, outputs: 0

12638 23:29:50.863905  Subtest pipe-C-query-busy: SKIP (0.000s)

12639 23:29:50.870167  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12640 23:29:50.873605  Opened device: /dev/dri/card0

12641 23:29:50.876785  No KMS driver or no outputs, pipes: 8, outputs: 0

12642 23:29:50.883141  Subtest pipe-C-query-busy-hang: SKIP (0.000s)

12643 23:29:50.890463  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12644 23:29:50.890893  Opened device: /dev/dri/card0

12645 23:29:50.896362  No KMS driver or no outputs, pipes: 8, outputs: 0

12646 23:29:50.900124  Subtest pipe-C-query-forked-busy: SKIP (0.000s)

12647 23:29:50.906350  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12648 23:29:50.909928  Opened device: /dev/dri/card0

12649 23:29:50.913174  No KMS driver or no outputs, pipes: 8, outputs: 0

12650 23:29:50.919910  Subtest pipe-C-que<14>[   25.896214] [IGT] kms_vblank: exiting, ret=77

12651 23:29:50.926552  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12653 23:29:50.929514  <8>[   25.900952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>

12654 23:29:50.936144  ry-forked-busy-hang: SKIP (0.000<14>[   25.910919] [IGT] kms_vblank: executing

12655 23:29:50.939620  <14>[   25.911462] [IGT] kms_vblank: exiting, ret=77

12656 23:29:50.946239  <8>[   25.916103] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>

12657 23:29:50.946937  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12659 23:29:50.949709  s)

12660 23:29:50.955834  IGT-Version: 1.27.1-g621c2d3 (aarch64) (<14>[   25.930110] [IGT] kms_vblank: executing

12661 23:29:50.959438  <14>[   25.930584] [IGT] kms_vblank: exiting, ret=77

12662 23:29:50.969327  <8>[   25.934867] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>

12663 23:29:50.970069  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12665 23:29:50.972697  Linux: 6.1.64-cip10-rt5 aarch64)

12666 23:29:50.976246  Opened device:<14>[   25.950696] [IGT] kms_vblank: executing

12667 23:29:50.982892  <14>[   25.951211] [IGT] kms_vblank: exiting, ret=77

12668 23:29:50.989282  <8>[   25.955661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>

12669 23:29:50.989722   /dev/dri/card0

12670 23:29:50.990339  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12672 23:29:50.996045  No KMS driver o<14>[   25.971732] [IGT] kms_vblank: executing

12673 23:29:50.999377  <14>[   25.972243] [IGT] kms_vblank: exiting, ret=77

12674 23:29:51.009187  <8>[   25.978860] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>

12675 23:29:51.009886  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12677 23:29:51.012609  r no outputs, pipes: 8, outputs: 0

12678 23:29:51.016267  Subtest pipe-C-wait-idle: SKIP (0.000s)

12679 23:29:51.022785  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12680 23:29:51.029419  Opened device: /d<14>[   26.001826] [IGT] kms_vblank: executing

12681 23:29:51.029915  ev/dri/card0

12682 23:29:51.032467  No<14>[   26.002645] [IGT] kms_vblank: exiting, ret=77

12683 23:29:51.042226  <8>[   26.007686] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>

12684 23:29:51.042857  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12686 23:29:51.046071   KMS driver or no outputs, pipes: 8, outputs: 0

12687 23:29:51.052134  Subtest pip<14>[   26.028631] [IGT] kms_vblank: executing

12688 23:29:51.055506  e-C-wait-idle-hang: SKIP (0.000s)

12689 23:29:51.058893  IGT-Versi<14>[   26.033939] [IGT] kms_vblank: exiting, ret=77

12690 23:29:51.069016  on: 1.27.1-g621c<8>[   26.039018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>

12691 23:29:51.069695  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12693 23:29:51.072324  2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12694 23:29:51.075643  Opened device: /dev/dri/card0

12695 23:29:51.082241  No KMS driver or no outputs, pip<14>[   26.058207] [IGT] kms_vblank: executing

12696 23:29:51.088708  <14>[   26.059068] [IGT] kms_vblank: exiting, ret=77

12697 23:29:51.095409  <8>[   26.064539] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>

12698 23:29:51.096066  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12700 23:29:51.098715  es: 8, outputs: 0

12701 23:29:51.102229  Subtest p<14>[   26.078906] [IGT] kms_vblank: executing

12702 23:29:51.108899  ipe-C-wait-forke<14>[   26.079437] [IGT] kms_vblank: exiting, ret=77

12703 23:29:51.118624  d: SKIP (0.000s)<8>[   26.083959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>

12704 23:29:51.119174  

12705 23:29:51.119791  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12707 23:29:51.125451  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12708 23:29:51.131950  Opened device: /<14>[   26.107018] [IGT] kms_vblank: executing

12709 23:29:51.135303  <14>[   26.107946] [IGT] kms_vblank: exiting, ret=77

12710 23:29:51.145100  <8>[   26.113109] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>

12711 23:29:51.145532  dev/dri/card0

12712 23:29:51.146173  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12714 23:29:51.151893  No KMS driver or <14>[   26.127559] [IGT] kms_vblank: executing

12715 23:29:51.158328  no outputs, pipe<14>[   26.128110] [IGT] kms_vblank: exiting, ret=77

12716 23:29:51.164889  <8>[   26.132778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>

12717 23:29:51.165566  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12719 23:29:51.168395  s: 8, outputs: 0

12720 23:29:51.171542  Subtest pipe-C-wait-forked-hang: SKIP (0.000s)

12721 23:29:51.184818  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch6<14>[   26.157602] [IGT] kms_vblank: executing

12722 23:29:51.188032  <14>[   26.158488] [IGT] kms_vblank: exiting, ret=77

12723 23:29:51.198071  <8>[   26.163558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>

12724 23:29:51.198501  4)

12725 23:29:51.199099  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12727 23:29:51.204622  Opened device: /dev/dri/card<14>[   26.179585] [IGT] kms_vblank: executing

12728 23:29:51.205053  0

12729 23:29:51.211371  No KMS driver<14>[   26.180054] [IGT] kms_vblank: exiting, ret=77

12730 23:29:51.217486  <8>[   26.187387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>

12731 23:29:51.218179  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12733 23:29:51.221070   or no outputs, pipes: 8, outputs: 0

12734 23:29:51.227512  Subtest pipe-C-wait-bu<14>[   26.201220] [IGT] kms_vblank: executing

12735 23:29:51.234532  sy: SKIP (0.000s<14>[   26.201857] [IGT] kms_vblank: exiting, ret=77

12736 23:29:51.243980  <8>[   26.206316] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>

12737 23:29:51.244382  )

12738 23:29:51.244961  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12740 23:29:51.250600  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12741 23:29:51.253893  Opened device: <14>[   26.229809] [IGT] kms_vblank: executing

12742 23:29:51.257304  /dev/dri/card0

12743 23:29:51.261012  <14>[   26.230694] [IGT] kms_vblank: exiting, ret=77

12744 23:29:51.270911  <8>[   26.235898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>

12745 23:29:51.271735  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12747 23:29:51.273731  No KMS driver or no outputs, pipes: 8, outputs: 0

12748 23:29:51.281278  Subtest p<14>[   26.255113] [IGT] kms_vblank: executing

12749 23:29:51.284046  <14>[   26.255950] [IGT] kms_vblank: exiting, ret=77

12750 23:29:51.293954  <8>[   26.261122] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>

12751 23:29:51.294788  Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12753 23:29:51.300156  ipe-C-wait-busy-<14>[   26.276447] [IGT] kms_vblank: executing

12754 23:29:51.306367  hang: SKIP (0.00<14>[   26.276909] [IGT] kms_vblank: exiting, ret=77

12755 23:29:51.313434  <8>[   26.283026] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>

12756 23:29:51.313517  0s)

12757 23:29:51.313797  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12759 23:29:51.320137  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12760 23:29:51.323358  Opened device: /dev/dri/card0

12761 23:29:51.330087  No KMS driver or no outputs, pipes: 8, outputs<14>[   26.305353] [IGT] kms_vblank: executing

12762 23:29:51.336969  <14>[   26.306262] [IGT] kms_vblank: exiting, ret=77

12763 23:29:51.343113  <8>[   26.311104] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>

12764 23:29:51.343196  : 0

12765 23:29:51.343432  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12767 23:29:51.349551  Subtest pipe-C-wait-forked-busy: SKIP (<14>[   26.325982] [IGT] kms_vblank: executing

12768 23:29:51.356159  <14>[   26.326460] [IGT] kms_vblank: exiting, ret=77

12769 23:29:51.363226  <8>[   26.331907] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>

12770 23:29:51.363475  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12772 23:29:51.366475  0.000s)

12773 23:29:51.369719  IGT-Version: 1.27.1<14>[   26.346919] [IGT] kms_vblank: executing

12774 23:29:51.376069  -g621c2d3 (aarch<14>[   26.347368] [IGT] kms_vblank: exiting, ret=77

12775 23:29:51.382796  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12777 23:29:51.386189  <8>[   26.351551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>

12778 23:29:51.389514  64) (Linux: 6.1.64-cip10-rt5 aarch64)

12779 23:29:51.389655  Opened device: /dev/dri/card0

12780 23:29:51.396252  No KMS driver or no outputs, pipes: 8, outputs: 0

12781 23:29:51.399479  Subtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)

12782 23:29:51.405769  IGT-Version: 1.27.1-g621c2<14>[   26.381601] [IGT] kms_vblank: executing

12783 23:29:51.412494  d3 (aarch64) (Li<14>[   26.382399] [IGT] kms_vblank: exiting, ret=77

12784 23:29:51.418972  <8>[   26.387082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>

12785 23:29:51.419233  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12787 23:29:51.422686  nux: 6.1.64-cip10-rt5 aarch64)

12788 23:29:51.429324  <14>[   26.403894] [IGT] kms_vblank: executing

12789 23:29:51.432896  <14>[   26.404370] [IGT] kms_vblank: exiting, ret=77

12790 23:29:51.439087  <8>[   26.408547] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>

12791 23:29:51.439341  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12793 23:29:51.442290  Opened device: /dev/dri/card0

12794 23:29:51.445635  No KMS driver or no outputs, pipes: 8, outputs: 0

12795 23:29:51.455708  Subtest pipe-C-ts-continuation-idle: SKIP <14>[   26.431130] [IGT] kms_vblank: executing

12796 23:29:51.459105  <14>[   26.432006] [IGT] kms_vblank: exiting, ret=77

12797 23:29:51.468746  <8>[   26.436966] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>

12798 23:29:51.468829  (0.000s)

12799 23:29:51.469065  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12801 23:29:51.479252  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aa<14>[   26.456472] [IGT] kms_vblank: executing

12802 23:29:51.479334  rch64)

12803 23:29:51.482229  Opened device: /dev/dri/card0

12804 23:29:51.488862  No KMS dr<14>[   26.457426] [IGT] kms_vblank: exiting, ret=77

12805 23:29:51.495376  <8>[   26.466588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>

12806 23:29:51.495629  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12808 23:29:51.498654  iver or no outputs, pipes: 8, outputs: 0

12809 23:29:51.505203  Subtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)

12810 23:29:51.512221  IGT-Version: 1.27.1-g<14>[   26.488383] [IGT] kms_vblank: executing

12811 23:29:51.515522  <14>[   26.489416] [IGT] kms_vblank: exiting, ret=77

12812 23:29:51.521781  621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12813 23:29:51.531995  Opened device: /dev/dri/car<8>[   26.503152] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>

12814 23:29:51.532104  d0

12815 23:29:51.532375  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12817 23:29:51.535354  No KMS driver or no outputs, pipes: 8, outputs: 0

12818 23:29:51.541564  Subtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)

12819 23:29:51.548755  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12820 23:29:51.551572  Opened device: /dev/dri/card0

12821 23:29:51.554843  <14>[   26.530577] [IGT] kms_vblank: executing

12822 23:29:51.558351  <14>[   26.531394] [IGT] kms_vblank: exiting, ret=77

12823 23:29:51.565445  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12825 23:29:51.568468  <8>[   26.536526] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>

12826 23:29:51.574941  No KMS driver or no outputs, pipes: 8, outputs: <14>[   26.550032] [IGT] kms_vblank: executing

12827 23:29:51.578283  <14>[   26.550517] [IGT] kms_vblank: exiting, ret=77

12828 23:29:51.588235  <8>[   26.557080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>

12829 23:29:51.588311  0

12830 23:29:51.588545  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12832 23:29:51.594790  Subtest pipe-C-ts-continu<14>[   26.570876] [IGT] kms_vblank: executing

12833 23:29:51.598267  <14>[   26.571349] [IGT] kms_vblank: exiting, ret=77

12834 23:29:51.608238  <8>[   26.575834] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>

12835 23:29:51.608493  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12837 23:29:51.611492  ation-dpms-suspend: SKIP (0.000s)

12838 23:29:51.617983  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12839 23:29:51.618085  Opened device: /dev/dri/card0

12840 23:29:51.624804  <14>[   26.600741] [IGT] kms_vblank: executing

12841 23:29:51.631244  No KMS driver or no outputs, pip<14>[   26.607114] [IGT] kms_vblank: exiting, ret=77

12842 23:29:51.638127  <8>[   26.611945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>

12843 23:29:51.638382  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12845 23:29:51.641560  es: 8, outputs: 0

12846 23:29:51.648324  Subtest pipe-C-ts-continu<14>[   26.623171] [IGT] kms_vblank: executing

12847 23:29:51.651534  <14>[   26.623668] [IGT] kms_vblank: exiting, ret=77

12848 23:29:51.657911  <8>[   26.627978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>

12849 23:29:51.658158  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12851 23:29:51.668103  ation-suspend: SKIP (0.000s)<14>[   26.642684] [IGT] kms_vblank: executing

12852 23:29:51.668214  

12853 23:29:51.671265  IGT-Version: 1<14>[   26.643194] [IGT] kms_vblank: exiting, ret=77

12854 23:29:51.681466  <8>[   26.647401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>

12855 23:29:51.681759  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12857 23:29:51.684906  .27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12858 23:29:51.688150  Opened device: /dev/dri/card0

12859 23:29:51.694577  No KMS driver or no outputs, pipes: 8<14>[   26.670109] [IGT] kms_vblank: executing

12860 23:29:51.701090  <14>[   26.670976] [IGT] kms_vblank: exiting, ret=77

12861 23:29:51.707768  <8>[   26.675930] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>

12862 23:29:51.708044  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12864 23:29:51.711198  , outputs: 0

12865 23:29:51.714457  Subtest pipe-C<14>[   26.691447] [IGT] kms_vblank: executing

12866 23:29:51.721312  <14>[   26.691921] [IGT] kms_vblank: exiting, ret=77

12867 23:29:51.728134  <8>[   26.698604] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>

12868 23:29:51.728413  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12870 23:29:51.731386  -ts-continuation-modeset: SKIP (0.000s)

12871 23:29:51.737939  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12872 23:29:51.741271  Opened device: /dev/dri/card0

12873 23:29:51.747696  No KMS driver or no output<14>[   26.722550] [IGT] kms_vblank: executing

12874 23:29:51.751512  s, pipes: 8, outputs: 0

12875 23:29:51.757981  Subtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)

12876 23:29:51.761264  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12877 23:29:51.764422  Opened device: /dev/dri/card0

12878 23:29:51.771513  No KMS driver or no outputs, pipes: 8, outputs: 0

12879 23:29:51.774404  Subtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)

12880 23:29:51.780956  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12881 23:29:51.784285  Opened device: /dev/dri/card0

12882 23:29:51.790698  No KMS driver or no outputs, pipes: 8, outputs: 0

12883 23:29:51.794527  Subtest pipe-D-accuracy-idle: SKIP (0.000s)

12884 23:29:51.801126  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12885 23:29:51.803864  Opened device: /dev/dri/card0

12886 23:29:51.807168  No KMS driver or no outputs, pipes: 8, outputs: 0

12887 23:29:51.810455  Subtest pipe-D-query-idle: SKIP (0.000s)

12888 23:29:51.817406  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12889 23:29:51.820696  Opened device: /dev/dri/card0

12890 23:29:51.824262  No KMS driver or no outputs, pipes: 8, outputs: 0

12891 23:29:51.830697  Subtest pipe-D-query-idle-hang: SKIP (0.000s)

12892 23:29:51.837067  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12893 23:29:51.840421  Opened device: /dev/dri/card0

12894 23:29:51.843921  No KMS driver or no outputs, pipes: 8, outputs: 0

12895 23:29:51.847433  Subtest pipe-D-query-forked: SKIP (0.000s)

12896 23:29:51.853887  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12897 23:29:51.857329  Opened device: /dev/dri/card0

12898 23:29:51.860513  No KMS driver or no outputs, pipes: 8, outputs: 0

12899 23:29:51.867409  Subtest pipe-D-query-forked-hang: SKIP (0.000s)

12900 23:29:51.873778  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12901 23:29:51.877238  Opened device: /dev/dri/card0

12902 23:29:51.880662  No KMS driver or no outputs, pipes: 8, outputs: 0

12903 23:29:51.883825  Subtest pipe-D-query-busy: SKIP (0.000s)

12904 23:29:51.890301  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12905 23:29:51.893750  Opened device: /dev/dri/card0

12906 23:29:51.897352  No KMS driver or no outputs, pipes: 8, outputs: 0

12907 23:29:51.904057  Subtest pipe-D-query-busy-hang: SKIP (0.000s)

12908 23:29:51.910092  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12909 23:29:51.913817  Opened device: /dev/dri/card0

12910 23:29:51.917440  No KMS driver or no outputs, pipes: 8, outputs: 0

12911 23:29:51.920384  Subtest pipe-D-query-forked-busy: SKIP (0.000s)

12912 23:29:51.926888  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12913 23:29:51.930155  Opened device: /dev/dri/card0

12914 23:29:51.933416  No KMS driver or no outputs, pipes: 8, outputs: 0

12915 23:29:51.940508  Subtest pipe-D-query-forked-busy-hang: SKIP (0.000s)

12916 23:29:51.946458  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12917 23:29:51.949880  Opened device: /dev/dri/card0

12918 23:29:51.953679  No KMS driver or no outputs, pipes: 8, outputs: 0

12919 23:29:51.956525  Subtest pipe-D-wait-idle: SKIP (0.000s)

12920 23:29:51.963369  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12921 23:29:51.966924  Opened device: /dev/dri/card0

12922 23:29:51.973066  No KMS driver or no outputs, pipes: 8, outputs: 0

12923 23:29:51.976365  Subtest pipe-D-wait-idle-hang: SKIP (0.000s)

12924 23:29:51.983390  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12925 23:29:51.986842  Opened device: /dev/dri/card0

12926 23:29:51.989970  No KMS driver or no outputs, pipes: 8, outputs: 0

12927 23:29:51.993436  Subtest pipe-D-wait-forked: SKIP (0.000s)

12928 23:29:52.000055  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12929 23:29:52.002919  Opened device: /dev/dri/card0

12930 23:29:52.006593  No KMS driver or no outputs, pipes: 8, outputs: 0

12931 23:29:52.012864  Subtest pipe-D-wait-forked-hang: SKIP (0.000s)

12932 23:29:52.019972  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12933 23:29:52.023079  Opened device: /dev/dri/card0

12934 23:29:52.026114  No KMS driver or no outputs, pipes: 8, outputs: 0

12935 23:29:52.029538  Subtest pipe-D-wait-busy: SKIP (0.000s)

12936 23:29:52.036191  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12937 23:29:52.039160  Opened device: /dev/dri/card0

12938 23:29:52.042918  No KMS driver or no outputs, pipes: 8, outputs: 0

12939 23:29:52.049906  Subtest pipe-D-wait-busy-hang: SKIP (0.000s)

12940 23:29:52.056006  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12941 23:29:52.059086  Opened device: /dev/dri/card0

12942 23:29:52.062809  No KMS driver or no outputs, pipes: 8, outputs: 0

12943 23:29:52.065832  Subtest pipe-D-wait-forked-busy: SKIP (0.000s)

12944 23:29:52.072674  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12945 23:29:52.075838  Opened device: /dev/dri/card0

12946 23:29:52.082968  No KMS driver or no outputs, pi<14>[   27.060642] [IGT] kms_vblank: exiting, ret=77

12947 23:29:52.092415  <8>[   27.065802] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>

12948 23:29:52.092978  pes: 8, outputs: 0

12949 23:29:52.093683  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12951 23:29:52.099494  Subtest pipe-D-wait-fork<14>[   27.076108] [IGT] kms_vblank: executing

12952 23:29:52.105665  <14>[   27.076589] [IGT] kms_vblank: exiting, ret=77

12953 23:29:52.112561  <8>[   27.080792] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>

12954 23:29:52.113419  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
12956 23:29:52.115649  ed-busy-hang: SKIP (0.000s)

12957 23:29:52.122527  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12958 23:29:52.125714  Opened device: /dev/dri/card0

12959 23:29:52.133061  No KMS driver or no ou<14>[   27.108134] [IGT] kms_vblank: executing

12960 23:29:52.136012  <14>[   27.108949] [IGT] kms_vblank: exiting, ret=77

12961 23:29:52.145413  <8>[   27.114097] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>

12962 23:29:52.146197  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
12964 23:29:52.148837  tputs, pipes: 8, outputs: 0

12965 23:29:52.151954  [1<14>[   27.127738] [IGT] kms_vblank: executing

12966 23:29:52.155129  <14>[   27.128293] [IGT] kms_vblank: exiting, ret=77

12967 23:29:52.165330  <8>[   27.132605] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>

12968 23:29:52.166069  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
12970 23:29:52.171934  mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)

12971 23:29:52.178708  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-c<14>[   27.155673] [IGT] kms_vblank: executing

12972 23:29:52.185697  <14>[   27.156553] [IGT] kms_vblank: exiting, ret=77

12973 23:29:52.192578  <8>[   27.161787] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>

12974 23:29:52.193428  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
12976 23:29:52.195197  ip10-rt5 aarch64)

12977 23:29:52.198671  Opened device: /dev/dri/card0

12978 23:29:52.202340  No KMS driver or no outputs, pipes: 8, outputs: 0

12979 23:29:52.209064  Subtest pipe-D-ts-conti<14>[   27.182165] [IGT] kms_vblank: executing

12980 23:29:52.211918  <14>[   27.182963] [IGT] kms_vblank: exiting, ret=77

12981 23:29:52.222141  <8>[   27.187878] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>

12982 23:29:52.223005  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
12984 23:29:52.228369  nuation-idle-han<14>[   27.204124] [IGT] kms_vblank: executing

12985 23:29:52.231823  <14>[   27.204665] [IGT] kms_vblank: exiting, ret=77

12986 23:29:52.241723  <8>[   27.208920] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>

12987 23:29:52.242317  g: SKIP (0.000s)

12988 23:29:52.242977  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
12990 23:29:52.248536  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

12991 23:29:52.251908  Opened device: /dev/dri/card0

12992 23:29:52.255193  N<14>[   27.232222] [IGT] kms_vblank: executing

12993 23:29:52.261677  <14>[   27.233104] [IGT] kms_vblank: exiting, ret=77

12994 23:29:52.264977  o KMS driver or no outputs, pipes: 8, outputs: 0

12995 23:29:52.278427  Subtest pipe-D-ts-continua<8>[   27.247885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>

12996 23:29:52.279278  Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
12998 23:29:52.281015  tion-dpms-rpm: SKIP (0.000s)

12999 23:29:52.284665  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13000 23:29:52.288042  Opened device: /dev/dri/card0

13001 23:29:52.294396  No KMS driver or no outputs, pipes: 8, outputs: 0

13002 23:29:52.300932  Subtest pipe-D-ts-continuation<14>[   27.274061] [IGT] kms_vblank: executing

13003 23:29:52.304429  <14>[   27.274900] [IGT] kms_vblank: exiting, ret=77

13004 23:29:52.311541  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13006 23:29:52.314195  <8>[   27.280094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>

13007 23:29:52.321010  -dpms-suspend: SKIP (0.000s)<14>[   27.295354] [IGT] kms_vblank: executing

13008 23:29:52.324745  <14>[   27.295898] [IGT] kms_vblank: exiting, ret=77

13009 23:29:52.330780  <8>[   27.300279] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>

13010 23:29:52.331255  

13011 23:29:52.331912  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13013 23:29:52.340942  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux:<14>[   27.314457] [IGT] kms_vblank: executing

13014 23:29:52.344361  <14>[   27.314996] [IGT] kms_vblank: exiting, ret=77

13015 23:29:52.353689  <8>[   27.319390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>

13016 23:29:52.354280   6.1.64-cip10-rt5 aarch64)

13017 23:29:52.354936  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13019 23:29:52.357404  Opened device: /dev/dri/card0

13020 23:29:52.363563  No KMS driver or no outputs, pipes: 8, outputs: 0

13021 23:29:52.367045  Subtest pipe-D<14>[   27.342445] [IGT] kms_vblank: executing

13022 23:29:52.373798  <14>[   27.343326] [IGT] kms_vblank: exiting, ret=77

13023 23:29:52.380798  <8>[   27.348606] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>

13024 23:29:52.381694  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13026 23:29:52.383673  -ts-continuation-suspend: SKIP (0.000s)

13027 23:29:52.390530  IGT-Version: 1.27.1-g621c2d3 (aarch<14>[   27.367975] [IGT] kms_vblank: executing

13028 23:29:52.396835  <14>[   27.368848] [IGT] kms_vblank: exiting, ret=77

13029 23:29:52.403786  <8>[   27.373991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>

13030 23:29:52.404638  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13032 23:29:52.410389  64) (Linux: 6.1.64-cip10-rt5 aar<14>[   27.386829] [IGT] kms_vblank: executing

13033 23:29:52.413517  ch64)

13034 23:29:52.416541  Opened de<14>[   27.387334] [IGT] kms_vblank: exiting, ret=77

13035 23:29:52.423589  <8>[   27.394248] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>

13036 23:29:52.424331  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13038 23:29:52.426481  vice: /dev/dri/card0

13039 23:29:52.430060  No KMS dri<14>[   27.407326] [IGT] kms_vblank: executing

13040 23:29:52.436620  <14>[   27.407805] [IGT] kms_vblank: exiting, ret=77

13041 23:29:52.443278  <8>[   27.412221] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>

13042 23:29:52.444120  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13044 23:29:52.446367  ver or no outputs, pipes: 8, outputs: 0

13045 23:29:52.453234  Subtest pipe-D-ts-continuation-modeset: SKIP (0.000s)

13046 23:29:52.463265  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)<14>[   27.437318] [IGT] kms_vblank: executing

13047 23:29:52.469951  <14>[   27.438178] [IGT] kms_vblank: exiting, ret=77

13048 23:29:52.476542  <8>[   27.443081] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>

13049 23:29:52.477117  

13050 23:29:52.477777  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13052 23:29:52.479917  Opened device: /dev/dri/card0

13053 23:29:52.483225  <14>[   27.459055] [IGT] kms_vblank: executing

13054 23:29:52.490127  <14>[   27.459525] [IGT] kms_vblank: exiting, ret=77

13055 23:29:52.496393  <8>[   27.463652] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>

13056 23:29:52.496971  

13057 23:29:52.497676  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13059 23:29:52.500353  No KMS driver or no outputs, pipes: 8, outputs: 0

13060 23:29:52.506589  Subtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)

13061 23:29:52.513220  IGT-Vers<14>[   27.487024] [IGT] kms_vblank: executing

13062 23:29:52.516645  <14>[   27.487892] [IGT] kms_vblank: exiting, ret=77

13063 23:29:52.523091  <8>[   27.492804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>

13064 23:29:52.523965  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13066 23:29:52.532877  ion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-ci<14>[   27.506529] [IGT] kms_vblank: executing

13067 23:29:52.535760  <14>[   27.507006] [IGT] kms_vblank: exiting, ret=77

13068 23:29:52.545848  <8>[   27.511106] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>

13069 23:29:52.546411  p10-rt5 aarch64)

13070 23:29:52.547057  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13072 23:29:52.552646  Opened device:<14>[   27.527375] [IGT] kms_vblank: executing

13073 23:29:52.555999  <14>[   27.527851] [IGT] kms_vblank: exiting, ret=77

13074 23:29:52.562115  <8>[   27.534208] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>

13075 23:29:52.562862  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13077 23:29:52.565550   /dev/dri/card0

13078 23:29:52.572340  No KMS driver or no outputs, pi<14>[   27.546574] [IGT] kms_vblank: executing

13079 23:29:52.575585  <14>[   27.547013] [IGT] kms_vblank: exiting, ret=77

13080 23:29:52.585715  <8>[   27.553822] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>

13081 23:29:52.586288  pes: 8, outputs: 0

13082 23:29:52.586943  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13084 23:29:52.592331  Subtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)

13085 23:29:52.599373  IGT-Version: 1.27.1-g621c2d3 (aarch64) (L<14>[   27.576005] [IGT] kms_vblank: executing

13086 23:29:52.605792  <14>[   27.576861] [IGT] kms_vblank: exiting, ret=77

13087 23:29:52.612469  <8>[   27.581947] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>

13088 23:29:52.613336  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13090 23:29:52.615502  inux: 6.1.64-cip10-rt5 aarch64)

13091 23:29:52.619056  Opened device: /dev/dri/card0

13092 23:29:52.621746  No KMS driver or no outputs, pipes: 8, outputs: 0

13093 23:29:52.628883  Subtest p<14>[   27.602020] [IGT] kms_vblank: executing

13094 23:29:52.631955  <14>[   27.602796] [IGT] kms_vblank: exiting, ret=77

13095 23:29:52.638411  <8>[   27.607736] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>

13096 23:29:52.639156  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13098 23:29:52.645294  ipe-E-accuracy-idle: SKIP (0.000s)

13099 23:29:52.648447  IGT-Vers<14>[   27.622707] [IGT] kms_vblank: executing

13100 23:29:52.652485  <14>[   27.623186] [IGT] kms_vblank: exiting, ret=77

13101 23:29:52.661556  <8>[   27.627255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>

13102 23:29:52.662595  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13104 23:29:52.668504  ion: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13105 23:29:52.669083  Opened device: /dev/dri/card0

13106 23:29:52.675582  No KMS driver o<14>[   27.650401] [IGT] kms_vblank: executing

13107 23:29:52.678124  <14>[   27.651268] [IGT] kms_vblank: exiting, ret=77

13108 23:29:52.688325  <8>[   27.656298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>

13109 23:29:52.689196  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13111 23:29:52.691710  r no outputs, pipes: 8, outputs: 0

13112 23:29:52.698289  Subtest pipe-E-query-idle: SKIP (0.000s)<14>[   27.675962] [IGT] kms_vblank: executing

13113 23:29:52.704541  <14>[   27.676851] [IGT] kms_vblank: exiting, ret=77

13114 23:29:52.711962  <8>[   27.681872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>

13115 23:29:52.712534  

13116 23:29:52.713182  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13118 23:29:52.718045  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13119 23:29:52.721434  Opened device: /dev/dri/card0

13120 23:29:52.727867  No KMS driver or <14>[   27.702025] [IGT] kms_vblank: executing

13121 23:29:52.730992  <14>[   27.702827] [IGT] kms_vblank: exiting, ret=77

13122 23:29:52.741194  <8>[   27.707730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>

13123 23:29:52.742216  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13125 23:29:52.744581  no outputs, pipes: 8, outputs: 0

13126 23:29:52.751404  Subtest pipe-E-query-idle-hang: SKIP (0.00<14>[   27.728103] [IGT] kms_vblank: executing

13127 23:29:52.757779  <14>[   27.728916] [IGT] kms_vblank: exiting, ret=77

13128 23:29:52.764546  <8>[   27.734091] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>

13129 23:29:52.765389  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13131 23:29:52.768296  0s)

13132 23:29:52.771013  IGT-Ver<14>[   27.748006] [IGT] kms_vblank: executing

13133 23:29:52.778067  sion: 1.27.1-g62<14>[   27.748475] [IGT] kms_vblank: exiting, ret=77

13134 23:29:52.785009  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13136 23:29:52.787604  <8>[   27.754601] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>

13137 23:29:52.790949  1c2d3 (aarch64) <14>[   27.768659] [IGT] kms_vblank: executing

13138 23:29:52.797979  <14>[   27.769160] [IGT] kms_vblank: exiting, ret=77

13139 23:29:52.804105  <8>[   27.778057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>

13140 23:29:52.804948  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13142 23:29:52.810744  (Linux: 6.1.64-cip10-rt5 aarch64<14>[   27.788299] [IGT] kms_vblank: executing

13143 23:29:52.811348  )

13144 23:29:52.814375  Opened device: /dev/dri/card0

13145 23:29:52.820698  No KMS driver or no outputs, pipes: 8, outputs: 0

13146 23:29:52.824144  Subtest pipe-E-query-forked: SKIP (0.000s)

13147 23:29:52.830546  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13148 23:29:52.834052  Opened device: /dev/dri/card0

13149 23:29:52.837333  No KMS driver or no outputs, pipes: 8, outputs: 0

13150 23:29:52.840654  Subtest pipe-E-query-forked-hang: SKIP (0.000s)

13151 23:29:52.847872  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13152 23:29:52.850599  Opened device: /dev/dri/card0

13153 23:29:52.857559  No KMS driver or no outputs, pipes: 8, outputs: 0

13154 23:29:52.860879  Subtest pipe-E-query-busy: SKIP (0.000s)

13155 23:29:52.867403  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13156 23:29:52.870721  Opened device: /dev/dri/card0

13157 23:29:52.874414  No KMS driver or no outputs, pipes: 8, outputs: 0

13158 23:29:52.877255  Subtest pipe-E-query-busy-hang: SKIP (0.000s)

13159 23:29:52.884085  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13160 23:29:52.887581  Opened device: /dev/dri/card0

13161 23:29:52.890790  No KMS driver or no outputs, pipes: 8, outputs: 0

13162 23:29:52.897311  Subtest pipe-E-query-forked-busy: SKIP (0.000s)

13163 23:29:52.903949  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13164 23:29:52.907432  Opened device: /dev/dri/card0

13165 23:29:52.910254  No KMS driver or no outputs, pipes: 8, outputs: 0

13166 23:29:52.917574  Subtest pipe-E-query-forked-busy-hang: SKIP (0.000s)

13167 23:29:52.923803  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13168 23:29:52.924377  Opened device: /dev/dri/card0

13169 23:29:52.930532  No KMS driver or no outputs, pipes: 8, outputs: 0

13170 23:29:52.933763  Subtest pipe-E-wait-idle: SKIP (0.000s)

13171 23:29:52.940368  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13172 23:29:52.943535  Opened device: /dev/dri/card0

13173 23:29:52.946754  No KMS driver or no outputs, pipes: 8, outputs: 0

13174 23:29:52.953385  Subtest pipe-E-wait-idle-hang: SKIP (0.000s)

13175 23:29:52.956718  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13176 23:29:52.960273  Opened device: /dev/dri/card0

13177 23:29:52.966843  No KMS driver or no outputs, pipes: 8, outputs: 0

13178 23:29:52.970150  Subtest pipe-E-wait-forked: SKIP (0.000s)

13179 23:29:52.976860  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13180 23:29:52.980553  Opened device: /dev/dri/card0

13181 23:29:52.983383  No KMS driver or no outputs, pipes: 8, outputs: 0

13182 23:29:52.990287  Subtest pipe-E-wait-forked-hang: SKIP (0.000s)

13183 23:29:52.993491  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13184 23:29:52.996970  Opened device: /dev/dri/card0

13185 23:29:53.003063  No KMS driver or no outputs, pipes: 8, outputs: 0

13186 23:29:53.006462  Subtest pipe-E-wait-busy: SKIP (0.000s)

13187 23:29:53.013129  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13188 23:29:53.016427  Opened device: /dev/dri/card0

13189 23:29:53.019755  No KMS driver or no outputs, pipes: 8, outputs: 0

13190 23:29:53.023296  Subtest pipe-E-wait-busy-hang: SKIP (0.000s)

13191 23:29:53.030156  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13192 23:29:53.033348  Opened device: /dev/dri/card0

13193 23:29:53.036684  No KMS driver or no outputs, pipes: 8, outputs: 0

13194 23:29:53.043537  Subtest pipe-E-wait-forked-busy: SKIP (0.000s)

13195 23:29:53.049739  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13196 23:29:53.053087  Opened device: /dev/dri/card0

13197 23:29:53.056218  No KMS driver or no outputs, pipes: 8, outputs: 0

13198 23:29:53.063561  Subtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)

13199 23:29:53.069362  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13200 23:29:53.070027  Opened device: /dev/dri/card0

13201 23:29:53.076136  No KMS driver or no outputs, pipes: 8, outputs: 0

13202 23:29:53.079167  Subtest pipe-E-ts-continuation-idle: SKIP (0.000s)

13203 23:29:53.086170  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13204 23:29:53.089389  Opened device: /dev/dri/card0

13205 23:29:53.092500  No KMS driver or no outputs, pipes: 8, outputs: 0

13206 23:29:53.099891  Subtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)

13207 23:29:53.105803  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13208 23:29:53.109632  Opened device: /dev/dri/card0

13209 23:29:53.112871  No KMS driver or no outputs, pipes: 8, outputs: 0

13210 23:29:53.119082  Subtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)

13211 23:29:53.125713  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13212 23:29:53.128854  Opened device: /dev/dri/card0

13213 23:29:53.132095  No KMS driver or no outputs, pipes: 8, outputs: 0

13214 23:29:53.138777  Subtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)

13215 23:29:53.145505  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13216 23:29:53.146007  Opened device: /dev/dri/card0

13217 23:29:53.152573  No KMS dri<14>[   28.125817] [IGT] kms_vblank: exiting, ret=77

13218 23:29:53.162429  <8>[   28.130435] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>

13219 23:29:53.163329  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13221 23:29:53.169183  ver or no outputs, pipes: 8, out<14>[   28.143953] [IGT] kms_vblank: executing

13222 23:29:53.172522  <14>[   28.144420] [IGT] kms_vblank: exiting, ret=77

13223 23:29:53.182063  <8>[   28.150828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>

13224 23:29:53.182628  puts: 0

13225 23:29:53.183281  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13227 23:29:53.189128  Sub<14>[   28.164634] [IGT] kms_vblank: executing

13228 23:29:53.192344  <14>[   28.165110] [IGT] kms_vblank: exiting, ret=77

13229 23:29:53.202170  <8>[   28.169527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>

13230 23:29:53.203109  Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13232 23:29:53.208835  test pipe-E-ts-continuation-susp<14>[   28.183850] [IGT] kms_vblank: executing

13233 23:29:53.212056  <14>[   28.184363] [IGT] kms_vblank: exiting, ret=77

13234 23:29:53.222346  <8>[   28.188670] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>

13235 23:29:53.222904  end: SKIP (0.000s)

13236 23:29:53.223554  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13238 23:29:53.228842  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13239 23:29:53.231833  Opened device: /dev/dri/card0

13240 23:29:53.235086  <14>[   28.211179] [IGT] kms_vblank: executing

13241 23:29:53.241484  <14>[   28.212060] [IGT] kms_vblank: exiting, ret=77

13242 23:29:53.248503  <8>[   28.217428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>

13243 23:29:53.249060  

13244 23:29:53.249979  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13246 23:29:53.255391  No KMS driver or no outputs, pipes: 8, outputs:<14>[   28.230668] [IGT] kms_vblank: executing

13247 23:29:53.261764  <14>[   28.231175] [IGT] kms_vblank: exiting, ret=77

13248 23:29:53.268333  <8>[   28.235625] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>

13249 23:29:53.268896   0

13250 23:29:53.269539  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13252 23:29:53.274642  Subtest pipe-E-ts-continuation-modeset: SKIP (0.000s)

13253 23:29:53.284487  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-r<14>[   28.258448] [IGT] kms_vblank: executing

13254 23:29:53.288583  <14>[   28.259328] [IGT] kms_vblank: exiting, ret=77

13255 23:29:53.294960  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13257 23:29:53.297907  <8>[   28.264600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>

13258 23:29:53.298327  t5 aarch64)

13259 23:29:53.304461  Opened device: /dev<14>[   28.279222] [IGT] kms_vblank: executing

13260 23:29:53.308216  <14>[   28.279688] [IGT] kms_vblank: exiting, ret=77

13261 23:29:53.314215  <8>[   28.286915] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>

13262 23:29:53.314857  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13264 23:29:53.317836  /dri/card0

13265 23:29:53.324089  No KMS driver or no <14>[   28.298926] [IGT] kms_vblank: executing

13266 23:29:53.327633  outputs, pipes: <14>[   28.299360] [IGT] kms_vblank: exiting, ret=77

13267 23:29:53.337559  <8>[   28.303631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>

13268 23:29:53.338177  8, outputs: 0

13269 23:29:53.338760  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13271 23:29:53.344367  Subtest pipe-<14>[   28.319445] [IGT] kms_vblank: executing

13272 23:29:53.347371  <14>[   28.319911] [IGT] kms_vblank: exiting, ret=77

13273 23:29:53.357883  <8>[   28.324065] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>

13274 23:29:53.358765  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13276 23:29:53.360900  E-ts-continuation-modeset-hang: SKIP (0.000s)

13277 23:29:53.367664  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13278 23:29:53.371420  Ope<14>[   28.346898] [IGT] kms_vblank: executing

13279 23:29:53.377471  <14>[   28.347775] [IGT] kms_vblank: exiting, ret=77

13280 23:29:53.384806  <8>[   28.352939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>

13281 23:29:53.385685  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13283 23:29:53.388101  ned device: /dev/dri/card0

13284 23:29:53.390970  No K<14>[   28.367003] [IGT] kms_vblank: executing

13285 23:29:53.397547  <14>[   28.367481] [IGT] kms_vblank: exiting, ret=77

13286 23:29:53.404201  <8>[   28.371577] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>

13287 23:29:53.405073  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13289 23:29:53.407928  MS driver or no outputs, pipes: 8, outputs: 0

13290 23:29:53.414211  Subtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)

13291 23:29:53.421133  IGT-Version: 1<14>[   28.394668] [IGT] kms_vblank: executing

13292 23:29:53.424411  <14>[   28.395518] [IGT] kms_vblank: exiting, ret=77

13293 23:29:53.431266  <8>[   28.400550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>

13294 23:29:53.432092  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13296 23:29:53.440704  .27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt<14>[   28.414496] [IGT] kms_vblank: executing

13297 23:29:53.444184  <14>[   28.414983] [IGT] kms_vblank: exiting, ret=77

13298 23:29:53.454081  <8>[   28.419241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>

13299 23:29:53.454540  5 aarch64)

13300 23:29:53.455175  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13302 23:29:53.457042  Opened device: /dev/dri/card0

13303 23:29:53.460924  No KMS driver or no outputs, pipes: 8, outputs: 0

13304 23:29:53.467035  Subtest pipe-F-accuracy-idle: <14>[   28.441969] [IGT] kms_vblank: executing

13305 23:29:53.473931  <14>[   28.442835] [IGT] kms_vblank: exiting, ret=77

13306 23:29:53.480845  <8>[   28.447842] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>

13307 23:29:53.481412  SKIP (0.000s)

13308 23:29:53.482112  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13310 23:29:53.490620  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-r<14>[   28.467786] [IGT] kms_vblank: executing

13311 23:29:53.496907  <14>[   28.468642] [IGT] kms_vblank: exiting, ret=77

13312 23:29:53.503787  <8>[   28.474226] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>

13313 23:29:53.504354  t5 aarch64)

13314 23:29:53.505006  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13316 23:29:53.507481  Opened device: /dev/dri/card0

13317 23:29:53.513465  No KMS driver or no outputs, pipes: 8, outputs: 0

13318 23:29:53.520308  Subtest pipe-F-query-idle: SK<14>[   28.494375] [IGT] kms_vblank: executing

13319 23:29:53.523473  <14>[   28.495132] [IGT] kms_vblank: exiting, ret=77

13320 23:29:53.530368  <8>[   28.499838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>

13321 23:29:53.531099  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13323 23:29:53.533485  IP (0.000s)

13324 23:29:53.540058  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13325 23:29:53.543347  Opene<14>[   28.520070] [IGT] kms_vblank: executing

13326 23:29:53.547449  <14>[   28.520896] [IGT] kms_vblank: exiting, ret=77

13327 23:29:53.556995  <8>[   28.525905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>

13328 23:29:53.557727  d device: /dev/dri/card0

13329 23:29:53.558566  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13331 23:29:53.563319  No KMS driver or no outputs, pipes: 8, outputs: 0

13332 23:29:53.570110  Subtest pipe-F-query-idle-hang: SKIP (0.000s)[<14>[   28.547009] [IGT] kms_vblank: executing

13333 23:29:53.576679  <14>[   28.547857] [IGT] kms_vblank: exiting, ret=77

13334 23:29:53.583700  <8>[   28.552685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>

13335 23:29:53.584282  0m

13336 23:29:53.584937  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13338 23:29:53.593372  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linu<14>[   28.566836] [IGT] kms_vblank: executing

13339 23:29:53.596859  <14>[   28.567325] [IGT] kms_vblank: exiting, ret=77

13340 23:29:53.606641  <8>[   28.571524] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>

13341 23:29:53.607459  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13343 23:29:53.610149  x: 6.1.64-cip10-<14>[   28.588291] [IGT] kms_vblank: executing

13344 23:29:53.616656  <14>[   28.588752] [IGT] kms_vblank: exiting, ret=77

13345 23:29:53.623272  <8>[   28.595456] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>

13346 23:29:53.624344  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13348 23:29:53.627015  rt5 aarch64)

13349 23:29:53.627470  Opened device: /dev/dri/card0

13350 23:29:53.632836  No <14>[   28.606853] [IGT] kms_vblank: executing

13351 23:29:53.636710  <14>[   28.607313] [IGT] kms_vblank: exiting, ret=77

13352 23:29:53.646436  <8>[   28.611549] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>

13353 23:29:53.647277  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13355 23:29:53.649434  KMS driver or no outputs, pipes: 8, outputs: 0

13356 23:29:53.656618  Subtest pipe-F-query-forked: SKIP (0.000s)

13357 23:29:53.663245  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-<14>[   28.638041] [IGT] kms_vblank: executing

13358 23:29:53.669737  <14>[   28.638873] [IGT] kms_vblank: exiting, ret=77

13359 23:29:53.676368  <8>[   28.643824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>

13360 23:29:53.677215  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13362 23:29:53.679806  rt5 aarch64)

13363 23:29:53.682902  Op<14>[   28.660054] [IGT] kms_vblank: executing

13364 23:29:53.686231  <14>[   28.660539] [IGT] kms_vblank: exiting, ret=77

13365 23:29:53.696108  <8>[   28.666955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>

13366 23:29:53.696962  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13368 23:29:53.699700  ened device: /dev/dri/card0

13369 23:29:53.702704  No <14>[   28.679352] [IGT] kms_vblank: executing

13370 23:29:53.709235  <14>[   28.679829] [IGT] kms_vblank: exiting, ret=77

13371 23:29:53.716176  <8>[   28.683884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>

13372 23:29:53.717027  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13374 23:29:53.722774  KMS driver or no outputs, pipes: 8, outputs: 0

13375 23:29:53.726132  Subtest pipe-F-query-forked-hang: SKIP (0.000s)

13376 23:29:53.735968  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64<14>[   28.708246] [IGT] kms_vblank: executing

13377 23:29:53.742800  <14>[   28.709115] [IGT] kms_vblank: exiting, ret=77

13378 23:29:53.749397  <8>[   28.714194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>

13379 23:29:53.750210  )

13380 23:29:53.750874  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13382 23:29:53.756053  Opened device<14>[   28.732252] [IGT] kms_vblank: executing

13383 23:29:53.759096  <14>[   28.732731] [IGT] kms_vblank: exiting, ret=77

13384 23:29:53.769649  <8>[   28.736847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>

13385 23:29:53.770215  : /dev/dri/card0

13386 23:29:53.770858  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13388 23:29:53.776119  No KMS driver or no outputs, pipes: 8, outputs: 0

13389 23:29:53.779446  Subtest pipe-F-query-busy: SKIP (0.000s)

13390 23:29:53.786289  IGT-Versi<14>[   28.759164] [IGT] kms_vblank: executing

13391 23:29:53.789119  <14>[   28.760030] [IGT] kms_vblank: exiting, ret=77

13392 23:29:53.798777  <8>[   28.764803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>

13393 23:29:53.799619  Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13395 23:29:53.802077  on: 1.27.1-g621c<14>[   28.780393] [IGT] kms_vblank: executing

13396 23:29:53.808866  2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13397 23:29:53.809437  Opened device: /dev/dri/card0

13398 23:29:53.815433  No KMS driver or no outputs, pipes: 8, outputs: 0

13399 23:29:53.818999  Subtest pipe-F-query-busy-hang: SKIP (0.000s)

13400 23:29:53.825205  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13401 23:29:53.828795  Opened device: /dev/dri/card0

13402 23:29:53.831879  No KMS driver or no outputs, pipes: 8, outputs: 0

13403 23:29:53.839001  Subtest pipe-F-query-forked-busy: SKIP (0.000s)

13404 23:29:53.845352  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13405 23:29:53.848411  Opened device: /dev/dri/card0

13406 23:29:53.851967  No KMS driver or no outputs, pipes: 8, outputs: 0

13407 23:29:53.855417  Subtest pipe-F-query-forked-busy-hang: SKIP (0.000s)

13408 23:29:53.862153  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13409 23:29:53.865134  Opened device: /dev/dri/card0

13410 23:29:53.871805  No KMS driver or no outputs, pipes: 8, outputs: 0

13411 23:29:53.875398  Subtest pipe-F-wait-idle: SKIP (0.000s)

13412 23:29:53.881650  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13413 23:29:53.884719  Opened device: /dev/dri/card0

13414 23:29:53.888205  No KMS driver or no outputs, pipes: 8, outputs: 0

13415 23:29:53.891494  Subtest pipe-F-wait-idle-hang: SKIP (0.000s)

13416 23:29:53.898445  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13417 23:29:53.901847  Opened device: /dev/dri/card0

13418 23:29:53.904629  No KMS driver or no outputs, pipes: 8, outputs: 0

13419 23:29:53.911309  Subtest pipe-F-wait-forked: SKIP (0.000s)

13420 23:29:53.918495  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13421 23:29:53.921830  Opened device: /dev/dri/card0

13422 23:29:53.925271  No KMS driver or no outputs, pipes: 8, outputs: 0

13423 23:29:53.928269  Subtest pipe-F-wait-forked-hang: SKIP (0.000s)

13424 23:29:53.935202  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13425 23:29:53.938310  Opened device: /dev/dri/card0

13426 23:29:53.941787  No KMS driver or no outputs, pipes: 8, outputs: 0

13427 23:29:53.948173  Subtest pipe-F-wait-busy: SKIP (0.000s)

13428 23:29:53.954787  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13429 23:29:53.955269  Opened device: /dev/dri/card0

13430 23:29:53.961511  No KMS driver or no outputs, pipes: 8, outputs: 0

13431 23:29:53.964775  Subtest pipe-F-wait-busy-hang: SKIP (0.000s)

13432 23:29:53.971386  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13433 23:29:53.974513  Opened device: /dev/dri/card0

13434 23:29:53.977883  No KMS driver or no outputs, pipes: 8, outputs: 0

13435 23:29:53.984556  Subtest pipe-F-wait-forked-busy: SKIP (0.000s)

13436 23:29:53.991217  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13437 23:29:53.994182  Opened device: /dev/dri/card0

13438 23:29:53.997966  No KMS driver or no outputs, pipes: 8, outputs: 0

13439 23:29:54.001793  Subtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)

13440 23:29:54.007437  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13441 23:29:54.011154  Opened device: /dev/dri/card0

13442 23:29:54.017806  No KMS driver or no outputs, pipes: 8, outputs: 0

13443 23:29:54.020914  Subtest pipe-F-ts-continuation-idle: SKIP (0.000s)

13444 23:29:54.027538  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13445 23:29:54.030641  Opened device: /dev/dri/card0

13446 23:29:54.034261  No KMS driver or no outputs, pipes: 8, outputs: 0

13447 23:29:54.040922  Subtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)

13448 23:29:54.047210  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13449 23:29:54.050871  Opened device: /dev/dri/card0

13450 23:29:54.053840  No KMS driver or no outputs, pipes: 8, outputs: 0

13451 23:29:54.061064  Subtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)

13452 23:29:54.067083  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13453 23:29:54.067634  Opened device: /dev/dri/card0

13454 23:29:54.074018  No KMS driver or no outputs, pipes: 8, outputs: 0

13455 23:29:54.080699  Subtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)

13456 23:29:54.087406  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13457 23:29:54.088067  Opened device: /dev/dri/card0

13458 23:29:54.093855  No KMS driver or no outputs, pipes: 8, outputs: 0

13459 23:29:54.097256  Subtest pipe-F-ts-continuation-suspend: SKIP (0.000s)

13460 23:29:54.103420  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13461 23:29:54.107019  Opened device: /dev/dri/card0

13462 23:29:54.110347  No KMS driver or no outputs, pipes: 8, outputs: 0

13463 23:29:54.116622  Subtest pipe-F-ts-continuation-modeset: SKIP (0.000s)

13464 23:29:54.123541  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13465 23:29:54.126655  Opened device: /dev/dri/card0

13466 23:29:54.129824  No KMS driver or no outputs, pipes: 8, outputs: 0

13467 23:29:54.136681  Subtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)

13468 23:29:54.143329  IGT-Version: 1.27.1-g621c2d3 (aarc<14>[   29.118667] [IGT] kms_vblank: exiting, ret=77

13469 23:29:54.152938  <8>[   29.123839] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>

13470 23:29:54.153855  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13472 23:29:54.156535  h64) (Linux: 6.1.64-cip10-rt5 aarch64)

13473 23:29:54.159728  Opened d<14>[   29.134552] [IGT] kms_vblank: executing

13474 23:29:54.166427  <14>[   29.135024] [IGT] kms_vblank: exiting, ret=77

13475 23:29:54.173440  <8>[   29.138946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>

13476 23:29:54.174074  evice: /dev/dri/card0

13477 23:29:54.174729  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13479 23:29:54.179912  No KMS driver or no outputs, pipes: 8, outputs: 0

13480 23:29:54.186612  Subtest pipe-F-ts-continuation-modeset-rpm: SKIP (<14>[   29.164448] [IGT] kms_vblank: executing

13481 23:29:54.189802  0.000s)

13482 23:29:54.196240  IGT-Version: 1.27.1-g621c2d3 (aarch<14>[   29.170466] [IGT] kms_vblank: exiting, ret=77

13483 23:29:54.206196  64) (Linux: 6.1.<8>[   29.176563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>

13484 23:29:54.207177  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13486 23:29:54.212489  64-cip10-rt5 aar<14>[   29.188950] [IGT] kms_vblank: executing

13487 23:29:54.213051  ch64)

13488 23:29:54.216155  Opened device: /dev/dri/card0

13489 23:29:54.219327  No KMS dri<14>[   29.194378] [IGT] kms_vblank: exiting, ret=77

13490 23:29:54.226116  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13492 23:29:54.229520  <8>[   29.199602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>

13493 23:29:54.232757  ver or no outputs, pipes: 8, outputs: 0

13494 23:29:54.236055  Sub<14>[   29.211463] [IGT] kms_vblank: executing

13495 23:29:54.239715  <14>[   29.212032] [IGT] kms_vblank: exiting, ret=77

13496 23:29:54.249420  <8>[   29.218926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>

13497 23:29:54.250205  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13499 23:29:54.256103  test pipe-G-accuracy-idle: SKIP <14>[   29.231745] [IGT] kms_vblank: executing

13500 23:29:54.259766  <14>[   29.232286] [IGT] kms_vblank: exiting, ret=77

13501 23:29:54.269288  <8>[   29.238681] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>

13502 23:29:54.269915  (0.000s)

13503 23:29:54.270570  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13505 23:29:54.276584  IGT-Version: 1.27.<14>[   29.250865] [IGT] kms_vblank: executing

13506 23:29:54.279689  <14>[   29.251399] [IGT] kms_vblank: exiting, ret=77

13507 23:29:54.286191  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13509 23:29:54.289231  <8>[   29.256446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>

13510 23:29:54.295763  1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aa<14>[   29.270420] [IGT] kms_vblank: executing

13511 23:29:54.299366  <14>[   29.270974] [IGT] kms_vblank: exiting, ret=77

13512 23:29:54.309154  <8>[   29.276339] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>

13513 23:29:54.309767  rch64)

13514 23:29:54.310425  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13516 23:29:54.315388  Opened device: /dev/dri/<14>[   29.291545] [IGT] kms_vblank: executing

13517 23:29:54.319018  <14>[   29.292051] [IGT] kms_vblank: exiting, ret=77

13518 23:29:54.328942  <8>[   29.298135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>

13519 23:29:54.329492  card0

13520 23:29:54.330286  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13522 23:29:54.335776  No KMS driver or no outputs, pipes: 8, outputs: 0

13523 23:29:54.339133  Subtest pipe-G-query-idle: SKIP (0.000s)

13524 23:29:54.345056  IGT-Version: 1.27.1-<14>[   29.320482] [IGT] kms_vblank: executing

13525 23:29:54.351694  g621c2d3 (aarch64) (Linux: 6.1.6<14>[   29.327030] [IGT] kms_vblank: exiting, ret=77

13526 23:29:54.358293  <8>[   29.332088] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>

13527 23:29:54.359138  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13529 23:29:54.361707  4-cip10-rt5 aarch64)

13530 23:29:54.368349  Opened device: /dev/dri/ca<14>[   29.342565] [IGT] kms_vblank: executing

13531 23:29:54.371882  <14>[   29.343042] [IGT] kms_vblank: exiting, ret=77

13532 23:29:54.378403  <8>[   29.348818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>

13533 23:29:54.379267  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13535 23:29:54.381963  rd0

13536 23:29:54.388061  No KMS driver or no outputs, pipes: 8, outp<14>[   29.362679] [IGT] kms_vblank: executing

13537 23:29:54.391820  <14>[   29.363124] [IGT] kms_vblank: exiting, ret=77

13538 23:29:54.401665  <8>[   29.368664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>

13539 23:29:54.402231  uts: 0

13540 23:29:54.402886  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13542 23:29:54.408330  Subtest pipe-G-query<14>[   29.383288] [IGT] kms_vblank: executing

13543 23:29:54.411356  <14>[   29.383750] [IGT] kms_vblank: exiting, ret=77

13544 23:29:54.421279  <8>[   29.389546] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>

13545 23:29:54.421754  -idle-hang: SKIP (0.000s)

13546 23:29:54.422357  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13548 23:29:54.428193  I<14>[   29.402929] [IGT] kms_vblank: executing

13549 23:29:54.431194  <14>[   29.403390] [IGT] kms_vblank: exiting, ret=77

13550 23:29:54.437912  <8>[   29.409089] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>

13551 23:29:54.438597  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13553 23:29:54.447948  GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.<14>[   29.421954] [IGT] kms_vblank: executing

13554 23:29:54.451409  <14>[   29.422427] [IGT] kms_vblank: exiting, ret=77

13555 23:29:54.461168  <8>[   29.427391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>

13556 23:29:54.461805  1.64-cip10-rt5 aarch64)

13557 23:29:54.462475  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13559 23:29:54.464389  Opened device: /dev/dri/card0

13560 23:29:54.467895  No KMS driver or no outputs, pipes: 8, outputs: 0

13561 23:29:54.474142  Subtest pipe-G-qu<14>[   29.449734] [IGT] kms_vblank: executing

13562 23:29:54.481347  <14>[   29.450521] [IGT] kms_vblank: exiting, ret=77

13563 23:29:54.487825  <8>[   29.455618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>

13564 23:29:54.488704  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13566 23:29:54.490948  ery-forked: SKIP (0.000s)

13567 23:29:54.497700  IGT-Version: 1.27<14>[   29.470749] [IGT] kms_vblank: executing

13568 23:29:54.501193  <14>[   29.471228] [IGT] kms_vblank: exiting, ret=77

13569 23:29:54.507779  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13571 23:29:54.511201  <8>[   29.475341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>

13572 23:29:54.514182  .1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13573 23:29:54.517361  Opened device: /dev/dri/card0

13574 23:29:54.524160  No KMS driver or no outp<14>[   29.497915] [IGT] kms_vblank: executing

13575 23:29:54.527766  <14>[   29.498799] [IGT] kms_vblank: exiting, ret=77

13576 23:29:54.537403  <8>[   29.504133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>

13577 23:29:54.537918  uts, pipes: 8, outputs: 0

13578 23:29:54.538578  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13580 23:29:54.544549  S<14>[   29.519085] [IGT] kms_vblank: executing

13581 23:29:54.547258  <14>[   29.519567] [IGT] kms_vblank: exiting, ret=77

13582 23:29:54.557990  <8>[   29.525307] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>

13583 23:29:54.558844  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13585 23:29:54.563948  ubtest pipe-G-query-forked-hang:<14>[   29.539504] [IGT] kms_vblank: executing

13586 23:29:54.567366  <14>[   29.539980] [IGT] kms_vblank: exiting, ret=77

13587 23:29:54.577774  <8>[   29.543945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>

13588 23:29:54.578355   SKIP (0.000s)

13589 23:29:54.579008  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13591 23:29:54.583865  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13592 23:29:54.590655  Opened device: /de<14>[   29.568465] [IGT] kms_vblank: executing

13593 23:29:54.596851  <14>[   29.569420] [IGT] kms_vblank: exiting, ret=77

13594 23:29:54.597448  v/dri/card0

13595 23:29:54.599902  No KMS driver or no outputs, pipes: 8, outputs: 0

13596 23:29:54.613347  Subtest pipe-G-query-busy: S<8>[   29.582888] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>

13597 23:29:54.613614  KIP (0.000s)

13598 23:29:54.614022  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13600 23:29:54.619906  IGT-Version: 1<14>[   29.595814] [IGT] kms_vblank: executing

13601 23:29:54.623050  <14>[   29.596301] [IGT] kms_vblank: exiting, ret=77

13602 23:29:54.633267  <8>[   29.600362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>

13603 23:29:54.633728  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13605 23:29:54.639788  .27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13606 23:29:54.640029  Opened device: /dev/dri/card0

13607 23:29:54.646204  No KMS driver or no outputs, pipes: 8, outputs: 0

13608 23:29:54.649524  Subtest pipe-G<14>[   29.625489] [IGT] kms_vblank: executing

13609 23:29:54.656533  <14>[   29.626316] [IGT] kms_vblank: exiting, ret=77

13610 23:29:54.663131  <8>[   29.631778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>

13611 23:29:54.663722  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13613 23:29:54.669698  -query-busy-hang: SKIP (0.000s)<14>[   29.647333] [IGT] kms_vblank: executing

13614 23:29:54.676658  <14>[   29.647819] [IGT] kms_vblank: exiting, ret=77

13615 23:29:54.686758  <8>[   29.653790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>

13616 23:29:54.687388  [0m

13617 23:29:54.688043  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13619 23:29:54.693436  IGT-Version: 1.27.1-g621c2d<14>[   29.668004] [IGT] kms_vblank: executing

13620 23:29:54.696447  <14>[   29.668473] [IGT] kms_vblank: exiting, ret=77

13621 23:29:54.706461  <8>[   29.674372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>

13622 23:29:54.707317  Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13624 23:29:54.709949  3 (aarch64) (Lin<14>[   29.688577] [IGT] kms_vblank: executing

13625 23:29:54.716485  <14>[   29.689059] [IGT] kms_vblank: exiting, ret=77

13626 23:29:54.723229  <8>[   29.694272] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>

13627 23:29:54.724109  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13629 23:29:54.726093  ux: 6.1.64-cip10-rt5 aarch64)

13630 23:29:54.733455  Opened device: /d<14>[   29.706551] [IGT] kms_vblank: executing

13631 23:29:54.734073  ev/dri/card0

13632 23:29:54.736209  No KMS driver or no outputs, pipes: 8, outputs: 0

13633 23:29:54.743197  Subtest pipe-G-query-forked-busy: SKIP (0.000s)

13634 23:29:54.749752  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13635 23:29:54.752872  Opened device: /dev/dri/card0

13636 23:29:54.755787  No KMS driver or no outputs, pipes: 8, outputs: 0

13637 23:29:54.762726  Subtest pipe-G-query-forked-busy-hang: SKIP (0.000s)

13638 23:29:54.769397  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13639 23:29:54.770029  Opened device: /dev/dri/card0

13640 23:29:54.775828  No KMS driver or no outputs, pipes: 8, outputs: 0

13641 23:29:54.779364  Subtest pipe-G-wait-idle: SKIP (0.000s)

13642 23:29:54.786342  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13643 23:29:54.789079  Opened device: /dev/dri/card0

13644 23:29:54.792358  No KMS driver or no outputs, pipes: 8, outputs: 0

13645 23:29:54.799007  Subtest pipe-G-wait-idle-hang: SKIP (0.000s)

13646 23:29:54.805642  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13647 23:29:54.806232  Opened device: /dev/dri/card0

13648 23:29:54.812449  No KMS driver or no outputs, pipes: 8, outputs: 0

13649 23:29:54.815451  Subtest pipe-G-wait-forked: SKIP (0.000s)

13650 23:29:54.821987  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13651 23:29:54.825630  Opened device: /dev/dri/card0

13652 23:29:54.829078  No KMS driver or no outputs, pipes: 8, outputs: 0

13653 23:29:54.835243  Subtest pipe-G-wait-forked-hang: SKIP (0.000s)

13654 23:29:54.842089  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13655 23:29:54.842662  Opened device: /dev/dri/card0

13656 23:29:54.848377  No KMS driver or no outputs, pipes: 8, outputs: 0

13657 23:29:54.852279  Subtest pipe-G-wait-busy: SKIP (0.000s)

13658 23:29:54.858473  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13659 23:29:54.861955  Opened device: /dev/dri/card0

13660 23:29:54.865095  No KMS driver or no outputs, pipes: 8, outputs: 0

13661 23:29:54.869004  Subtest pipe-G-wait-busy-hang: SKIP (0.000s)

13662 23:29:54.875552  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13663 23:29:54.878592  Opened device: /dev/dri/card0

13664 23:29:54.882361  No KMS driver or no outputs, pipes: 8, outputs: 0

13665 23:29:54.889197  Subtest pipe-G-wait-forked-busy: SKIP (0.000s)

13666 23:29:54.895423  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13667 23:29:54.898993  Opened device: /dev/dri/card0

13668 23:29:54.902182  No KMS driver or no outputs, pipes: 8, outputs: 0

13669 23:29:54.908189  Subtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)

13670 23:29:54.914816  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13671 23:29:54.915327  Opened device: /dev/dri/card0

13672 23:29:54.921228  No KMS driver or no outputs, pipes: 8, outputs: 0

13673 23:29:54.924661  Subtest pipe-G-ts-continuation-idle: SKIP (0.000s)

13674 23:29:54.931319  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13675 23:29:54.934637  Opened device: /dev/dri/card0

13676 23:29:54.941013  No KMS driver or no outputs, pipes: 8, outputs: 0

13677 23:29:54.944570  Subtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)

13678 23:29:54.951492  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13679 23:29:54.954328  Opened device: /dev/dri/card0

13680 23:29:54.957545  No KMS driver or no outputs, pipes: 8, outputs: 0

13681 23:29:54.964292  Subtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)

13682 23:29:54.970756  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13683 23:29:54.974450  Opened device: /dev/dri/card0

13684 23:29:54.977994  No KMS driver or no outputs, pipes: 8, outputs: 0

13685 23:29:54.984516  Subtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)

13686 23:29:54.990916  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13687 23:29:54.994232  Opened device: /dev/dri/card0

13688 23:29:54.997686  No KMS driver or no outputs, pipes: 8, outputs: 0

13689 23:29:55.004150  Subtest pipe-G-ts-continuation-suspend: SKIP (0.000s)

13690 23:29:55.010580  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13691 23:29:55.011140  Opened device: /dev/dri/card0

13692 23:29:55.017172  No KMS driver or no outputs, pipes: 8, outputs: 0

13693 23:29:55.020808  Subtest pipe-G-ts-continuation-modeset: SKIP (0.000s)

13694 23:29:55.027030  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13695 23:29:55.030400  Opened device: /dev/dri/card0

13696 23:29:55.036695  No KMS driver or no outputs, pipes: 8, outputs: 0

13697 23:29:55.040394  Subtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)

13698 23:29:55.047052  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13699 23:29:55.049960  Opened device: /dev/dri/card0

13700 23:29:55.053926  No KMS driver or no outputs, pipes: 8, outputs: 0

13701 23:29:55.060476  Subtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)

13702 23:29:55.066990  IGT-Version: 1.27.1-g621<14>[   30.044728] [IGT] kms_vblank: exiting, ret=77

13703 23:29:55.073333  <8>[   30.049913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>

13704 23:29:55.074239  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13706 23:29:55.083358  c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)<14>[   30.060843] [IGT] kms_vblank: executing

13707 23:29:55.083834  

13708 23:29:55.086388  Opened device: /dev/dri/card0

13709 23:29:55.093334  No KMS driver o<14>[   30.065979] [IGT] kms_vblank: exiting, ret=77

13710 23:29:55.099801  <8>[   30.072688] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>

13711 23:29:55.100659  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13713 23:29:55.103343  r no outputs, pipes: 8, outputs: 0

13714 23:29:55.110072  Subtest pipe-H-accuracy-idle: SKIP (0.00<14>[   30.086299] [IGT] kms_vblank: executing

13715 23:29:55.116106  <14>[   30.086785] [IGT] kms_vblank: exiting, ret=77

13716 23:29:55.122981  <8>[   30.092812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>

13717 23:29:55.123546  0s)

13718 23:29:55.124208  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13720 23:29:55.133133  IGT-Version: 1.27.1-g621c2d3 (aarch64) <14>[   30.106211] [IGT] kms_vblank: executing

13721 23:29:55.136199  <14>[   30.106769] [IGT] kms_vblank: exiting, ret=77

13722 23:29:55.143274  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13724 23:29:55.146136  <8>[   30.111129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>

13725 23:29:55.152473  (Linux: 6.1.64-cip10-rt5 aarch64<14>[   30.127333] [IGT] kms_vblank: executing

13726 23:29:55.155958  <14>[   30.127870] [IGT] kms_vblank: exiting, ret=77

13727 23:29:55.162288  <8>[   30.133303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>

13728 23:29:55.162900  )

13729 23:29:55.163550  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13731 23:29:55.165509  Opened device: /dev/dri/card0

13732 23:29:55.172487  No KMS driver <14>[   30.146423] [IGT] kms_vblank: executing

13733 23:29:55.175750  <14>[   30.146985] [IGT] kms_vblank: exiting, ret=77

13734 23:29:55.186409  <8>[   30.152898] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>

13735 23:29:55.187258  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13737 23:29:55.192643  or no outputs, pipes: 8, outputs<14>[   30.167371] [IGT] kms_vblank: executing

13738 23:29:55.195985  <14>[   30.167911] [IGT] kms_vblank: exiting, ret=77

13739 23:29:55.206137  <8>[   30.174173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>

13740 23:29:55.206706  : 0

13741 23:29:55.207373  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13743 23:29:55.212508  Subtest pipe-H-query-id<14>[   30.187095] [IGT] kms_vblank: executing

13744 23:29:55.215582  <14>[   30.187612] [IGT] kms_vblank: exiting, ret=77

13745 23:29:55.225760  <8>[   30.194306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>

13746 23:29:55.226327  le: SKIP (0.000s)

13747 23:29:55.226980  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13749 23:29:55.232189  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13750 23:29:55.235303  Opened device: /dev/dri/card0

13751 23:29:55.245887  No KMS driver or no outputs, pipes: 8, outputs: <14>[   30.219294] [IGT] kms_vblank: executing

13752 23:29:55.249067  <14>[   30.220140] [IGT] kms_vblank: exiting, ret=77

13753 23:29:55.255719  <8>[   30.226031] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>

13754 23:29:55.256283  0

13755 23:29:55.256945  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13757 23:29:55.261761  Subtest pipe-H-query-idle-hang: SKIP (0.000s)

13758 23:29:55.268224  IGT-Version: 1.27.1-g6<14>[   30.244898] [IGT] kms_vblank: executing

13759 23:29:55.274892  21c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch6<14>[   30.250635] [IGT] kms_vblank: exiting, ret=77

13760 23:29:55.285150  <8>[   30.255513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>

13761 23:29:55.285807  4)

13762 23:29:55.286275  Opened device: /dev/dri/card0

13763 23:29:55.287089  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13765 23:29:55.292106  No KMS driver or no outputs, pipes: 8, outputs: 0

13766 23:29:55.298348  Subtest pipe-H-query-forked: SKIP (0.0<14>[   30.276090] [IGT] kms_vblank: executing

13767 23:29:55.305220  <14>[   30.276890] [IGT] kms_vblank: exiting, ret=77

13768 23:29:55.311816  <8>[   30.281905] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>

13769 23:29:55.312382  00s)

13770 23:29:55.313041  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13772 23:29:55.318490  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13773 23:29:55.322079  Opened device: /dev/dri/card0

13774 23:29:55.328488  No KMS driver or no outputs, <14>[   30.303150] [IGT] kms_vblank: executing

13775 23:29:55.331931  <14>[   30.304013] [IGT] kms_vblank: exiting, ret=77

13776 23:29:55.342013  <8>[   30.309111] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>

13777 23:29:55.342583  pipes: 8, outputs: 0

13778 23:29:55.343234  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13780 23:29:55.348641  Subtest pipe-H-query-forked-hang: SKIP (0.000s)

13781 23:29:55.351935  I<14>[   30.328033] [IGT] kms_vblank: executing

13782 23:29:55.355344  <14>[   30.328885] [IGT] kms_vblank: exiting, ret=77

13783 23:29:55.365442  <8>[   30.334467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>

13784 23:29:55.366368  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13786 23:29:55.371338  GT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13787 23:29:55.371821  Opened device: /dev/dri/card0

13788 23:29:55.378059  No KMS driver or no outputs, pipes: 8, outputs: 0

13789 23:29:55.384385  Subtest pipe-H-qu<14>[   30.360717] [IGT] kms_vblank: executing

13790 23:29:55.384930  ery-busy: SKIP (0.000s)

13791 23:29:55.391408  IGT-Version: 1.27.1<14>[   30.366041] [IGT] kms_vblank: exiting, ret=77

13792 23:29:55.401143  <8>[   30.370983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>

13793 23:29:55.402210  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13795 23:29:55.404503  -g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13796 23:29:55.408373  Opened device: /dev/dri/card0

13797 23:29:55.411013  No KMS driver or no outputs, pipes: 8, outputs: 0

13798 23:29:55.417892  Subtest pipe-H-query-busy-hang: SKIP (0.000s)

13799 23:29:55.424359  IGT-Version: 1.27.1-g621c2d3 (aa<14>[   30.399434] [IGT] kms_vblank: executing

13800 23:29:55.427585  <14>[   30.400263] [IGT] kms_vblank: exiting, ret=77

13801 23:29:55.434482  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13803 23:29:55.437408  <8>[   30.405580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>

13804 23:29:55.441252  rch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13805 23:29:55.441868  Opened device: /dev/dri/card0

13806 23:29:55.447651  No KMS driver or no outputs, pipes: 8, outputs: 0

13807 23:29:55.450812  <14>[   30.426682] [IGT] kms_vblank: executing

13808 23:29:55.457421  <14>[   30.427533] [IGT] kms_vblank: exiting, ret=77

13809 23:29:55.464152  <8>[   30.433227] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>

13810 23:29:55.464997  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13812 23:29:55.470792  Subtest pipe-H-query-forked-busy<14>[   30.447350] [IGT] kms_vblank: executing

13813 23:29:55.477501  <14>[   30.447892] [IGT] kms_vblank: exiting, ret=77

13814 23:29:55.484048  <8>[   30.452216] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>

13815 23:29:55.484930  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13817 23:29:55.486929  : SKIP (0.000s)

13818 23:29:55.494111  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13819 23:29:55.494670  Opened device: /dev/dri/card0

13820 23:29:55.500593  No KMS driver or no outputs, pipes: 8, outputs: 0

13821 23:29:55.503978  <14>[   30.478223] [IGT] kms_vblank: executing

13822 23:29:55.507892  <14>[   30.479075] [IGT] kms_vblank: exiting, ret=77

13823 23:29:55.517233  <8>[   30.484671] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>

13824 23:29:55.518038  

13825 23:29:55.518875  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13827 23:29:55.523859  Subtest pip<14>[   30.500187] [IGT] kms_vblank: executing

13828 23:29:55.527524  <14>[   30.500721] [IGT] kms_vblank: exiting, ret=77

13829 23:29:55.536842  <8>[   30.507068] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>

13830 23:29:55.537757  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13832 23:29:55.543918  e-H-query-forked-busy-hang: SKIP<14>[   30.519126] [IGT] kms_vblank: executing

13833 23:29:55.546815  <14>[   30.519670] [IGT] kms_vblank: exiting, ret=77

13834 23:29:55.557033  <8>[   30.526179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>

13835 23:29:55.557667   (0.000s)

13836 23:29:55.558450  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13838 23:29:55.563653  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13839 23:29:55.566481  Opened device: /dev/dri/card0

13840 23:29:55.576804  No KMS driver or no outputs, pipes: 8, o<14>[   30.552014] [IGT] kms_vblank: executing

13841 23:29:55.579589  <14>[   30.552892] [IGT] kms_vblank: exiting, ret=77

13842 23:29:55.586665  <8>[   30.558353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>

13843 23:29:55.587721  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13845 23:29:55.589953  utputs: 0

13846 23:29:55.597005  Subtest pipe-H-wa<14>[   30.571117] [IGT] kms_vblank: executing

13847 23:29:55.600404  <14>[   30.571655] [IGT] kms_vblank: exiting, ret=77

13848 23:29:55.607409  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13850 23:29:55.609796  <8>[   30.576444] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>

13851 23:29:55.610272  it-idle: SKIP (0.000s)

13852 23:29:55.616449  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13853 23:29:55.623022  Opened device: /dev/dri/ca<14>[   30.600637] [IGT] kms_vblank: executing

13854 23:29:55.623585  rd0

13855 23:29:55.629780  No KMS driver or no outputs<14>[   30.606673] [IGT] kms_vblank: exiting, ret=77

13856 23:29:55.639988  <8>[   30.611790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>

13857 23:29:55.640735  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13859 23:29:55.643313  , pipes: 8, outputs: 0

13860 23:29:55.646016  Subt<14>[   30.623214] [IGT] kms_vblank: executing

13861 23:29:55.652847  est pipe-H-wait-<14>[   30.623739] [IGT] kms_vblank: exiting, ret=77

13862 23:29:55.663133  <8>[   30.628241] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>

13863 23:29:55.664008  Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13865 23:29:55.666469  <8>[   30.630423] <LAVA_SIGNAL_TESTSET STOP>

13866 23:29:55.667210  Received signal: <TESTSET> STOP
13867 23:29:55.667615  Closing test_set kms_vblank
13868 23:29:55.669794  idle-hang: SKIP (0.000s)

13869 23:29:55.679751  IGT-Version: 1.27.1-g621c2d3 (aarc<8>[   30.649261] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 12172428_1.5.2.3.1>

13870 23:29:55.680645  Received signal: <ENDRUN> 0_igt-kms-mediatek 12172428_1.5.2.3.1
13871 23:29:55.681105  Ending use of test pattern.
13872 23:29:55.681461  Ending test lava.0_igt-kms-mediatek (12172428_1.5.2.3.1), duration 11.66
13874 23:29:55.683272  h64) (Linux: 6.1.64-cip10-rt5 aarch64)

13875 23:29:55.686302  Opened device: /dev/dri/card0

13876 23:29:55.689557  No KMS driver or no outputs, pipes: 8, outputs: 0

13877 23:29:55.693194  Subtest pipe-H-wait-forked: SKIP (0.000s)

13878 23:29:55.699586  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13879 23:29:55.702645  Opened device: /dev/dri/card0

13880 23:29:55.706332  No KMS driver or no outputs, pipes: 8, outputs: 0

13881 23:29:55.712990  Subtest pipe-H-wait-forked-hang: SKIP (0.000s)

13882 23:29:55.719185  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13883 23:29:55.722626  Opened device: /dev/dri/card0

13884 23:29:55.726028  No KMS driver or no outputs, pipes: 8, outputs: 0

13885 23:29:55.729809  Subtest pipe-H-wait-busy: SKIP (0.000s)

13886 23:29:55.736042  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13887 23:29:55.739172  Opened device: /dev/dri/card0

13888 23:29:55.742450  No KMS driver or no outputs, pipes: 8, outputs: 0

13889 23:29:55.749413  Subtest pipe-H-wait-busy-hang: SKIP (0.000s)

13890 23:29:55.755796  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13891 23:29:55.756377  Opened device: /dev/dri/card0

13892 23:29:55.762931  No KMS driver or no outputs, pipes: 8, outputs: 0

13893 23:29:55.765733  Subtest pipe-H-wait-forked-busy: SKIP (0.000s)

13894 23:29:55.772736  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13895 23:29:55.775558  Opened device: /dev/dri/card0

13896 23:29:55.779315  No KMS driver or no outputs, pipes: 8, outputs: 0

13897 23:29:55.786061  Subtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)

13898 23:29:55.792337  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13899 23:29:55.795681  Opened device: /dev/dri/card0

13900 23:29:55.798901  No KMS driver or no outputs, pipes: 8, outputs: 0

13901 23:29:55.805343  Subtest pipe-H-ts-continuation-idle: SKIP (0.000s)

13902 23:29:55.811968  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13903 23:29:55.812519  Opened device: /dev/dri/card0

13904 23:29:55.818457  No KMS driver or no outputs, pipes: 8, outputs: 0

13905 23:29:55.822250  Subtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)

13906 23:29:55.828646  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13907 23:29:55.831937  Opened device: /dev/dri/card0

13908 23:29:55.834787  No KMS driver or no outputs, pipes: 8, outputs: 0

13909 23:29:55.841794  Subtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)

13910 23:29:55.848572  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13911 23:29:55.851625  Opened device: /dev/dri/card0

13912 23:29:55.854886  No KMS driver or no outputs, pipes: 8, outputs: 0

13913 23:29:55.861751  Subtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)

13914 23:29:55.868670  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13915 23:29:55.871743  Opened device: /dev/dri/card0

13916 23:29:55.875121  No KMS driver or no outputs, pipes: 8, outputs: 0

13917 23:29:55.881367  Subtest pipe-H-ts-continuation-suspend: SKIP (0.000s)

13918 23:29:55.888509  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13919 23:29:55.891306  Opened device: /dev/dri/card0

13920 23:29:55.895291  No KMS driver or no outputs, pipes: 8, outputs: 0

13921 23:29:55.901486  Subtest pipe-H-ts-continuation-modeset: SKIP (0.000s)

13922 23:29:55.904643  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13923 23:29:55.908526  Opened device: /dev/dri/card0

13924 23:29:55.914595  No KMS driver or no outputs, pipes: 8, outputs: 0

13925 23:29:55.918212  Subtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)

13926 23:29:55.924629  IGT-Version: 1.27.1-g621c2d3 (aarch64) (Linux: 6.1.64-cip10-rt5 aarch64)

13927 23:29:55.928039  Opened device: /dev/dri/card0

13928 23:29:55.934122  No KMS driver or no outputs, pipes: 8, outputs: 0

13929 23:29:55.937899  Subtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)

13930 23:29:55.941204  + set +x

13931 23:29:55.941809  <LAVA_TEST_RUNNER EXIT>

13932 23:29:55.942491  ok: lava_test_shell seems to have completed
13933 23:29:55.967053  addfb25-4-tiled:
  result: skip
  set: kms_addfb_basic
addfb25-bad-modifier:
  result: fail
  set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
  result: skip
  set: kms_addfb_basic
addfb25-modifier-no-flag:
  result: pass
  set: kms_addfb_basic
addfb25-x-tiled-legacy:
  result: skip
  set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
  result: skip
  set: kms_addfb_basic
addfb25-y-tiled-legacy:
  result: skip
  set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
  result: skip
  set: kms_addfb_basic
addfb25-yf-tiled-legacy:
  result: skip
  set: kms_addfb_basic
atomic-invalid-params:
  result: skip
  set: kms_atomic
atomic_plane_damage:
  result: skip
  set: kms_atomic
bad-pitch-0:
  result: pass
  set: kms_addfb_basic
bad-pitch-1024:
  result: pass
  set: kms_addfb_basic
bad-pitch-128:
  result: pass
  set: kms_addfb_basic
bad-pitch-256:
  result: pass
  set: kms_addfb_basic
bad-pitch-32:
  result: pass
  set: kms_addfb_basic
bad-pitch-63:
  result: pass
  set: kms_addfb_basic
bad-pitch-65536:
  result: pass
  set: kms_addfb_basic
bad-pitch-999:
  result: pass
  set: kms_addfb_basic
basic:
  result: skip
  set: kms_setmode
basic-auth:
  result: pass
  set: core_auth
basic-clone-single-crtc:
  result: skip
  set: kms_setmode
basic-x-tiled-legacy:
  result: skip
  set: kms_addfb_basic
basic-y-tiled-legacy:
  result: skip
  set: kms_addfb_basic
blob-multiple:
  result: pass
  set: kms_prop_blob
blob-prop-core:
  result: pass
  set: kms_prop_blob
blob-prop-lifetime:
  result: pass
  set: kms_prop_blob
blob-prop-validate:
  result: pass
  set: kms_prop_blob
bo-too-small:
  result: skip
  set: kms_addfb_basic
bo-too-small-due-to-tiling:
  result: skip
  set: kms_addfb_basic
clobberred-modifier:
  result: skip
  set: kms_addfb_basic
clone-exclusive-crtc:
  result: skip
  set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
  result: skip
  set: kms_vblank
crtc-invalid-params:
  result: skip
  set: kms_atomic
crtc-invalid-params-fence:
  result: skip
  set: kms_atomic
empty-block:
  result: skip
  set: drm_read
empty-nonblock:
  result: skip
  set: drm_read
fault-buffer:
  result: skip
  set: drm_read
framebuffer-vs-set-tiling:
  result: skip
  set: kms_addfb_basic
getclient-master-drop:
  result: pass
  set: core_auth
getclient-simple:
  result: pass
  set: core_auth
invalid:
  result: skip
  set: kms_vblank
invalid-buffer:
  result: skip
  set: drm_read
invalid-clone-exclusive-crtc:
  result: skip
  set: kms_setmode
invalid-clone-single-crtc:
  result: skip
  set: kms_setmode
invalid-clone-single-crtc-stealing:
  result: skip
  set: kms_setmode
invalid-get-prop:
  result: pass
  set: kms_prop_blob
invalid-get-prop-any:
  result: pass
  set: kms_prop_blob
invalid-set-prop:
  result: pass
  set: kms_prop_blob
invalid-set-prop-any:
  result: pass
  set: kms_prop_blob
invalid-smem-bo-on-discrete:
  result: skip
  set: kms_addfb_basic
legacy-format:
  result: pass
  set: kms_addfb_basic
many-magics:
  result: pass
  set: core_auth
master-rmfb:
  result: pass
  set: kms_addfb_basic
no-handle:
  result: pass
  set: kms_addfb_basic
pipe-A-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-A-query-busy:
  result: skip
  set: kms_vblank
pipe-A-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-A-query-forked:
  result: skip
  set: kms_vblank
pipe-A-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-A-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-A-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-A-query-idle:
  result: skip
  set: kms_vblank
pipe-A-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-A-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-A-wait-busy:
  result: skip
  set: kms_vblank
pipe-A-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-A-wait-forked:
  result: skip
  set: kms_vblank
pipe-A-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-A-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-A-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-A-wait-idle:
  result: skip
  set: kms_vblank
pipe-A-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-B-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-B-query-busy:
  result: skip
  set: kms_vblank
pipe-B-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-B-query-forked:
  result: skip
  set: kms_vblank
pipe-B-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-B-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-B-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-B-query-idle:
  result: skip
  set: kms_vblank
pipe-B-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-B-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-B-wait-busy:
  result: skip
  set: kms_vblank
pipe-B-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-B-wait-forked:
  result: skip
  set: kms_vblank
pipe-B-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-B-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-B-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-B-wait-idle:
  result: skip
  set: kms_vblank
pipe-B-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-C-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-C-query-busy:
  result: skip
  set: kms_vblank
pipe-C-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-C-query-forked:
  result: skip
  set: kms_vblank
pipe-C-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-C-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-C-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-C-query-idle:
  result: skip
  set: kms_vblank
pipe-C-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-C-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-C-wait-busy:
  result: skip
  set: kms_vblank
pipe-C-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-C-wait-forked:
  result: skip
  set: kms_vblank
pipe-C-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-C-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-C-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-C-wait-idle:
  result: skip
  set: kms_vblank
pipe-C-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-D-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-D-query-busy:
  result: skip
  set: kms_vblank
pipe-D-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-D-query-forked:
  result: skip
  set: kms_vblank
pipe-D-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-D-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-D-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-D-query-idle:
  result: skip
  set: kms_vblank
pipe-D-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-D-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-D-wait-busy:
  result: skip
  set: kms_vblank
pipe-D-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-D-wait-forked:
  result: skip
  set: kms_vblank
pipe-D-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-D-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-D-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-D-wait-idle:
  result: skip
  set: kms_vblank
pipe-D-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-E-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-E-query-busy:
  result: skip
  set: kms_vblank
pipe-E-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-E-query-forked:
  result: skip
  set: kms_vblank
pipe-E-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-E-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-E-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-E-query-idle:
  result: skip
  set: kms_vblank
pipe-E-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-E-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-E-wait-busy:
  result: skip
  set: kms_vblank
pipe-E-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-E-wait-forked:
  result: skip
  set: kms_vblank
pipe-E-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-E-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-E-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-E-wait-idle:
  result: skip
  set: kms_vblank
pipe-E-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-F-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-F-query-busy:
  result: skip
  set: kms_vblank
pipe-F-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-F-query-forked:
  result: skip
  set: kms_vblank
pipe-F-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-F-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-F-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-F-query-idle:
  result: skip
  set: kms_vblank
pipe-F-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-F-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-F-wait-busy:
  result: skip
  set: kms_vblank
pipe-F-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-F-wait-forked:
  result: skip
  set: kms_vblank
pipe-F-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-F-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-F-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-F-wait-idle:
  result: skip
  set: kms_vblank
pipe-F-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-G-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-G-query-busy:
  result: skip
  set: kms_vblank
pipe-G-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-G-query-forked:
  result: skip
  set: kms_vblank
pipe-G-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-G-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-G-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-G-query-idle:
  result: skip
  set: kms_vblank
pipe-G-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-G-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-G-wait-busy:
  result: skip
  set: kms_vblank
pipe-G-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-G-wait-forked:
  result: skip
  set: kms_vblank
pipe-G-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-G-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-G-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-G-wait-idle:
  result: skip
  set: kms_vblank
pipe-G-wait-idle-hang:
  result: skip
  set: kms_vblank
pipe-H-accuracy-idle:
  result: skip
  set: kms_vblank
pipe-H-query-busy:
  result: skip
  set: kms_vblank
pipe-H-query-busy-hang:
  result: skip
  set: kms_vblank
pipe-H-query-forked:
  result: skip
  set: kms_vblank
pipe-H-query-forked-busy:
  result: skip
  set: kms_vblank
pipe-H-query-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-H-query-forked-hang:
  result: skip
  set: kms_vblank
pipe-H-query-idle:
  result: skip
  set: kms_vblank
pipe-H-query-idle-hang:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-idle:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-idle-hang:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-modeset:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
  result: skip
  set: kms_vblank
pipe-H-ts-continuation-suspend:
  result: skip
  set: kms_vblank
pipe-H-wait-busy:
  result: skip
  set: kms_vblank
pipe-H-wait-busy-hang:
  result: skip
  set: kms_vblank
pipe-H-wait-forked:
  result: skip
  set: kms_vblank
pipe-H-wait-forked-busy:
  result: skip
  set: kms_vblank
pipe-H-wait-forked-busy-hang:
  result: skip
  set: kms_vblank
pipe-H-wait-forked-hang:
  result: skip
  set: kms_vblank
pipe-H-wait-idle:
  result: skip
  set: kms_vblank
pipe-H-wait-idle-hang:
  result: skip
  set: kms_vblank
plane-cursor-legacy:
  result: skip
  set: kms_atomic
plane-immutable-zpos:
  result: skip
  set: kms_atomic
plane-invalid-params:
  result: skip
  set: kms_atomic
plane-invalid-params-fence:
  result: skip
  set: kms_atomic
plane-overlay-legacy:
  result: skip
  set: kms_atomic
plane-primary-legacy:
  result: skip
  set: kms_atomic
plane-primary-overlay-mutable-zpos:
  result: skip
  set: kms_atomic
short-buffer-block:
  result: skip
  set: drm_read
short-buffer-nonblock:
  result: skip
  set: drm_read
short-buffer-wakeup:
  result: skip
  set: drm_read
size-max:
  result: skip
  set: kms_addfb_basic
small-bo:
  result: skip
  set: kms_addfb_basic
test-only:
  result: skip
  set: kms_atomic
tile-pitch-mismatch:
  result: skip
  set: kms_addfb_basic
too-high:
  result: skip
  set: kms_addfb_basic
too-wide:
  result: skip
  set: kms_addfb_basic
unused-handle:
  result: pass
  set: kms_addfb_basic
unused-modifier:
  result: pass
  set: kms_addfb_basic
unused-offsets:
  result: pass
  set: kms_addfb_basic
unused-pitches:
  result: pass
  set: kms_addfb_basic

13934 23:29:55.967974  end: 3.1 lava-test-shell (duration 00:00:12) [common]
13935 23:29:55.968341  end: 3 lava-test-retry (duration 00:00:12) [common]
13936 23:29:55.968689  start: 4 finalize (timeout 00:07:49) [common]
13937 23:29:55.969061  start: 4.1 power-off (timeout 00:00:30) [common]
13938 23:29:55.969842  Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
13939 23:29:56.075070  >> Command sent successfully.

13940 23:29:56.087253  Returned 0 in 0 seconds
13941 23:29:56.188623  end: 4.1 power-off (duration 00:00:00) [common]
13943 23:29:56.190312  start: 4.2 read-feedback (timeout 00:07:49) [common]
13944 23:29:56.191659  Listened to connection for namespace 'common' for up to 1s
13945 23:29:57.192253  Finalising connection for namespace 'common'
13946 23:29:57.192932  Disconnecting from shell: Finalise
13947 23:29:57.193334  / # 
13948 23:29:57.294390  end: 4.2 read-feedback (duration 00:00:01) [common]
13949 23:29:57.295139  end: 4 finalize (duration 00:00:01) [common]
13950 23:29:57.295765  Cleaning after the job
13951 23:29:57.296303  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/ramdisk
13952 23:29:57.330228  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/kernel
13953 23:29:57.346631  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/dtb
13954 23:29:57.346930  Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172428/tftp-deploy-um0a0hli/modules
13955 23:29:57.356676  Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172428
13956 23:29:57.474427  Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172428
13957 23:29:57.474614  Job finished correctly