Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 36
- Errors: 0
1 23:24:43.695518 lava-dispatcher, installed at version: 2023.10
2 23:24:43.695741 start: 0 validate
3 23:24:43.695870 Start time: 2023-12-03 23:24:43.695861+00:00 (UTC)
4 23:24:43.695984 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:24:43.696114 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:24:43.979154 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:24:43.979893 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:24:44.249424 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:24:44.250286 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:24:44.511629 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:24:44.512384 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:24:44.783105 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:24:44.783867 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:24:45.056108 validate duration: 1.36
16 23:24:45.056773 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:24:45.057054 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:24:45.057304 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:24:45.057667 Not decompressing ramdisk as can be used compressed.
20 23:24:45.057909 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:24:45.058099 saving as /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/ramdisk/initrd.cpio.gz
22 23:24:45.058299 total size: 4665395 (4 MB)
23 23:24:45.061058 progress 0 % (0 MB)
24 23:24:45.065376 progress 5 % (0 MB)
25 23:24:45.069027 progress 10 % (0 MB)
26 23:24:45.072622 progress 15 % (0 MB)
27 23:24:45.076270 progress 20 % (0 MB)
28 23:24:45.079901 progress 25 % (1 MB)
29 23:24:45.082995 progress 30 % (1 MB)
30 23:24:45.085928 progress 35 % (1 MB)
31 23:24:45.088288 progress 40 % (1 MB)
32 23:24:45.090946 progress 45 % (2 MB)
33 23:24:45.092979 progress 50 % (2 MB)
34 23:24:45.095028 progress 55 % (2 MB)
35 23:24:45.096929 progress 60 % (2 MB)
36 23:24:45.098686 progress 65 % (2 MB)
37 23:24:45.100431 progress 70 % (3 MB)
38 23:24:45.102070 progress 75 % (3 MB)
39 23:24:45.103617 progress 80 % (3 MB)
40 23:24:45.105381 progress 85 % (3 MB)
41 23:24:45.106862 progress 90 % (4 MB)
42 23:24:45.108278 progress 95 % (4 MB)
43 23:24:45.109706 progress 100 % (4 MB)
44 23:24:45.109880 4 MB downloaded in 0.05 s (86.25 MB/s)
45 23:24:45.110057 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:24:45.110326 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:24:45.110423 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:24:45.110515 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:24:45.110655 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:24:45.110735 saving as /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/kernel/Image
52 23:24:45.110803 total size: 49172992 (46 MB)
53 23:24:45.110870 No compression specified
54 23:24:45.111966 progress 0 % (0 MB)
55 23:24:45.125079 progress 5 % (2 MB)
56 23:24:45.137828 progress 10 % (4 MB)
57 23:24:45.150758 progress 15 % (7 MB)
58 23:24:45.163709 progress 20 % (9 MB)
59 23:24:45.176551 progress 25 % (11 MB)
60 23:24:45.189349 progress 30 % (14 MB)
61 23:24:45.201983 progress 35 % (16 MB)
62 23:24:45.214604 progress 40 % (18 MB)
63 23:24:45.227284 progress 45 % (21 MB)
64 23:24:45.240021 progress 50 % (23 MB)
65 23:24:45.252811 progress 55 % (25 MB)
66 23:24:45.265758 progress 60 % (28 MB)
67 23:24:45.278590 progress 65 % (30 MB)
68 23:24:45.291451 progress 70 % (32 MB)
69 23:24:45.304016 progress 75 % (35 MB)
70 23:24:45.316367 progress 80 % (37 MB)
71 23:24:45.328849 progress 85 % (39 MB)
72 23:24:45.341454 progress 90 % (42 MB)
73 23:24:45.354109 progress 95 % (44 MB)
74 23:24:45.366555 progress 100 % (46 MB)
75 23:24:45.366766 46 MB downloaded in 0.26 s (183.21 MB/s)
76 23:24:45.366925 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:24:45.367161 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:24:45.367248 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:24:45.367329 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:24:45.367462 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:24:45.367527 saving as /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/dtb/mt8192-asurada-spherion-r0.dtb
83 23:24:45.367586 total size: 47278 (0 MB)
84 23:24:45.367644 No compression specified
85 23:24:45.368751 progress 69 % (0 MB)
86 23:24:45.369028 progress 100 % (0 MB)
87 23:24:45.369182 0 MB downloaded in 0.00 s (28.29 MB/s)
88 23:24:45.369299 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:24:45.369516 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:24:45.369646 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:24:45.369753 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:24:45.369860 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:24:45.369924 saving as /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/nfsrootfs/full.rootfs.tar
95 23:24:45.369981 total size: 200813988 (191 MB)
96 23:24:45.370039 Using unxz to decompress xz
97 23:24:45.374216 progress 0 % (0 MB)
98 23:24:45.897384 progress 5 % (9 MB)
99 23:24:46.408601 progress 10 % (19 MB)
100 23:24:46.987740 progress 15 % (28 MB)
101 23:24:47.360398 progress 20 % (38 MB)
102 23:24:47.680444 progress 25 % (47 MB)
103 23:24:48.267337 progress 30 % (57 MB)
104 23:24:48.812807 progress 35 % (67 MB)
105 23:24:49.402618 progress 40 % (76 MB)
106 23:24:49.955844 progress 45 % (86 MB)
107 23:24:50.533636 progress 50 % (95 MB)
108 23:24:51.155531 progress 55 % (105 MB)
109 23:24:51.814764 progress 60 % (114 MB)
110 23:24:51.930968 progress 65 % (124 MB)
111 23:24:52.068931 progress 70 % (134 MB)
112 23:24:52.164340 progress 75 % (143 MB)
113 23:24:52.235462 progress 80 % (153 MB)
114 23:24:52.303784 progress 85 % (162 MB)
115 23:24:52.404098 progress 90 % (172 MB)
116 23:24:52.679875 progress 95 % (181 MB)
117 23:24:53.248199 progress 100 % (191 MB)
118 23:24:53.253494 191 MB downloaded in 7.88 s (24.29 MB/s)
119 23:24:53.253817 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:24:53.254174 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:24:53.254336 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:24:53.254468 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:24:53.254664 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:24:53.254764 saving as /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/modules/modules.tar
126 23:24:53.254858 total size: 8614132 (8 MB)
127 23:24:53.254957 Using unxz to decompress xz
128 23:24:53.259508 progress 0 % (0 MB)
129 23:24:53.280671 progress 5 % (0 MB)
130 23:24:53.304359 progress 10 % (0 MB)
131 23:24:53.327527 progress 15 % (1 MB)
132 23:24:53.350420 progress 20 % (1 MB)
133 23:24:53.374458 progress 25 % (2 MB)
134 23:24:53.399928 progress 30 % (2 MB)
135 23:24:53.425705 progress 35 % (2 MB)
136 23:24:53.448374 progress 40 % (3 MB)
137 23:24:53.472160 progress 45 % (3 MB)
138 23:24:53.497363 progress 50 % (4 MB)
139 23:24:53.521327 progress 55 % (4 MB)
140 23:24:53.546530 progress 60 % (4 MB)
141 23:24:53.573130 progress 65 % (5 MB)
142 23:24:53.600652 progress 70 % (5 MB)
143 23:24:53.624017 progress 75 % (6 MB)
144 23:24:53.650960 progress 80 % (6 MB)
145 23:24:53.676657 progress 85 % (7 MB)
146 23:24:53.701538 progress 90 % (7 MB)
147 23:24:53.730867 progress 95 % (7 MB)
148 23:24:53.758728 progress 100 % (8 MB)
149 23:24:53.765111 8 MB downloaded in 0.51 s (16.10 MB/s)
150 23:24:53.765380 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:24:53.765678 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:24:53.765771 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:24:53.765868 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:24:57.259062 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6
156 23:24:57.259362 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 23:24:57.259501 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:24:57.259665 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf
159 23:24:57.259794 makedir: /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin
160 23:24:57.259892 makedir: /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/tests
161 23:24:57.259988 makedir: /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/results
162 23:24:57.260085 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-add-keys
163 23:24:57.260226 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-add-sources
164 23:24:57.260353 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-background-process-start
165 23:24:57.260477 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-background-process-stop
166 23:24:57.260608 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-common-functions
167 23:24:57.260732 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-echo-ipv4
168 23:24:57.260853 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-install-packages
169 23:24:57.260974 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-installed-packages
170 23:24:57.261094 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-os-build
171 23:24:57.261219 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-probe-channel
172 23:24:57.261383 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-probe-ip
173 23:24:57.261504 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-target-ip
174 23:24:57.261666 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-target-mac
175 23:24:57.261800 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-target-storage
176 23:24:57.261922 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-case
177 23:24:57.262046 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-event
178 23:24:57.262165 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-feedback
179 23:24:57.262286 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-raise
180 23:24:57.262404 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-reference
181 23:24:57.262525 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-runner
182 23:24:57.262644 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-set
183 23:24:57.262766 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-test-shell
184 23:24:57.262887 Updating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-add-keys (debian)
185 23:24:57.263035 Updating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-add-sources (debian)
186 23:24:57.263172 Updating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-install-packages (debian)
187 23:24:57.263356 Updating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-installed-packages (debian)
188 23:24:57.263489 Updating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/bin/lava-os-build (debian)
189 23:24:57.263605 Creating /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/environment
190 23:24:57.263697 LAVA metadata
191 23:24:57.263765 - LAVA_JOB_ID=12172424
192 23:24:57.263824 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:24:57.263928 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:24:57.263993 skipped lava-vland-overlay
195 23:24:57.264062 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:24:57.264136 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:24:57.264194 skipped lava-multinode-overlay
198 23:24:57.264262 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:24:57.264334 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:24:57.264403 Loading test definitions
201 23:24:57.264486 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:24:57.264552 Using /lava-12172424 at stage 0
203 23:24:57.264824 uuid=12172424_1.6.2.3.1 testdef=None
204 23:24:57.264908 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:24:57.264988 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:24:57.265482 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:24:57.265758 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:24:57.266299 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:24:57.266519 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:24:57.267037 runner path: /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/0/tests/0_timesync-off test_uuid 12172424_1.6.2.3.1
213 23:24:57.267186 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:24:57.267532 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:24:57.267657 Using /lava-12172424 at stage 0
217 23:24:57.267755 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:24:57.267830 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/0/tests/1_kselftest-dt'
219 23:25:01.249122 Running '/usr/bin/git checkout kernelci.org
220 23:25:01.396230 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/0/tests/1_kselftest-dt/automated/linux/kselftest/kselftest.yaml
221 23:25:01.396982 uuid=12172424_1.6.2.3.5 testdef=None
222 23:25:01.397135 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 23:25:01.397389 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 23:25:01.398326 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:25:01.398559 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 23:25:01.399527 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:25:01.399759 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 23:25:01.400692 runner path: /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/0/tests/1_kselftest-dt test_uuid 12172424_1.6.2.3.5
232 23:25:01.400784 BOARD='mt8192-asurada-spherion-r0'
233 23:25:01.400848 BRANCH='cip-gitlab'
234 23:25:01.400906 SKIPFILE='/dev/null'
235 23:25:01.400963 SKIP_INSTALL='True'
236 23:25:01.401018 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:25:01.401074 TST_CASENAME=''
238 23:25:01.401128 TST_CMDFILES='dt'
239 23:25:01.401267 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:25:01.401471 Creating lava-test-runner.conf files
242 23:25:01.401538 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172424/lava-overlay-4i4182wf/lava-12172424/0 for stage 0
243 23:25:01.401712 - 0_timesync-off
244 23:25:01.401784 - 1_kselftest-dt
245 23:25:01.401881 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 23:25:01.401970 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 23:25:08.833141 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:25:08.833304 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 23:25:08.833397 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:25:08.833497 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 23:25:08.833625 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 23:25:08.953384 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:25:08.953832 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 23:25:08.953961 extracting modules file /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6
255 23:25:09.175928 extracting modules file /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172424/extract-overlay-ramdisk-5am80o8t/ramdisk
256 23:25:09.403560 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:25:09.403730 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 23:25:09.403827 [common] Applying overlay to NFS
259 23:25:09.403899 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172424/compress-overlay-o8_jundi/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6
260 23:25:10.319218 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:25:10.319388 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 23:25:10.319482 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:25:10.319565 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 23:25:10.319645 Building ramdisk /var/lib/lava/dispatcher/tmp/12172424/extract-overlay-ramdisk-5am80o8t/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172424/extract-overlay-ramdisk-5am80o8t/ramdisk
265 23:25:10.654613 >> 119416 blocks
266 23:25:12.611275 rename /var/lib/lava/dispatcher/tmp/12172424/extract-overlay-ramdisk-5am80o8t/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/ramdisk/ramdisk.cpio.gz
267 23:25:12.611922 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:25:12.612051 start: 1.6.8 prepare-kernel (timeout 00:09:32) [common]
269 23:25:12.612155 start: 1.6.8.1 prepare-fit (timeout 00:09:32) [common]
270 23:25:12.612257 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/kernel/Image'
271 23:25:24.425375 Returned 0 in 11 seconds
272 23:25:24.526414 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/kernel/image.itb
273 23:25:24.902252 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:25:24.902626 output: Created: Sun Dec 3 23:25:24 2023
275 23:25:24.902704 output: Image 0 (kernel-1)
276 23:25:24.902770 output: Description:
277 23:25:24.902830 output: Created: Sun Dec 3 23:25:24 2023
278 23:25:24.902891 output: Type: Kernel Image
279 23:25:24.902948 output: Compression: lzma compressed
280 23:25:24.903005 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
281 23:25:24.903060 output: Architecture: AArch64
282 23:25:24.903113 output: OS: Linux
283 23:25:24.903166 output: Load Address: 0x00000000
284 23:25:24.903220 output: Entry Point: 0x00000000
285 23:25:24.903276 output: Hash algo: crc32
286 23:25:24.903330 output: Hash value: c85ea8f0
287 23:25:24.903383 output: Image 1 (fdt-1)
288 23:25:24.903434 output: Description: mt8192-asurada-spherion-r0
289 23:25:24.903486 output: Created: Sun Dec 3 23:25:24 2023
290 23:25:24.903537 output: Type: Flat Device Tree
291 23:25:24.903588 output: Compression: uncompressed
292 23:25:24.903639 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:25:24.903690 output: Architecture: AArch64
294 23:25:24.903741 output: Hash algo: crc32
295 23:25:24.903791 output: Hash value: cc4352de
296 23:25:24.903842 output: Image 2 (ramdisk-1)
297 23:25:24.903892 output: Description: unavailable
298 23:25:24.903942 output: Created: Sun Dec 3 23:25:24 2023
299 23:25:24.903993 output: Type: RAMDisk Image
300 23:25:24.904043 output: Compression: Unknown Compression
301 23:25:24.904094 output: Data Size: 17795424 Bytes = 17378.34 KiB = 16.97 MiB
302 23:25:24.904145 output: Architecture: AArch64
303 23:25:24.904196 output: OS: Linux
304 23:25:24.904246 output: Load Address: unavailable
305 23:25:24.904297 output: Entry Point: unavailable
306 23:25:24.904347 output: Hash algo: crc32
307 23:25:24.904397 output: Hash value: d03516f3
308 23:25:24.904447 output: Default Configuration: 'conf-1'
309 23:25:24.904497 output: Configuration 0 (conf-1)
310 23:25:24.904548 output: Description: mt8192-asurada-spherion-r0
311 23:25:24.904599 output: Kernel: kernel-1
312 23:25:24.904649 output: Init Ramdisk: ramdisk-1
313 23:25:24.904700 output: FDT: fdt-1
314 23:25:24.904788 output: Loadables: kernel-1
315 23:25:24.904839 output:
316 23:25:24.905043 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:25:24.905155 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:25:24.905260 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 23:25:24.905353 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 23:25:24.905433 No LXC device requested
321 23:25:24.905508 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:25:24.905621 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 23:25:24.905724 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:25:24.905791 Checking files for TFTP limit of 4294967296 bytes.
325 23:25:24.906295 end: 1 tftp-deploy (duration 00:00:40) [common]
326 23:25:24.906399 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:25:24.906489 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:25:24.906609 substitutions:
329 23:25:24.906676 - {DTB}: 12172424/tftp-deploy-1ans5gei/dtb/mt8192-asurada-spherion-r0.dtb
330 23:25:24.906776 - {INITRD}: 12172424/tftp-deploy-1ans5gei/ramdisk/ramdisk.cpio.gz
331 23:25:24.906834 - {KERNEL}: 12172424/tftp-deploy-1ans5gei/kernel/Image
332 23:25:24.906890 - {LAVA_MAC}: None
333 23:25:24.906944 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6
334 23:25:24.907017 - {NFS_SERVER_IP}: 192.168.201.1
335 23:25:24.907075 - {PRESEED_CONFIG}: None
336 23:25:24.907131 - {PRESEED_LOCAL}: None
337 23:25:24.907184 - {RAMDISK}: 12172424/tftp-deploy-1ans5gei/ramdisk/ramdisk.cpio.gz
338 23:25:24.907238 - {ROOT_PART}: None
339 23:25:24.907303 - {ROOT}: None
340 23:25:24.907363 - {SERVER_IP}: 192.168.201.1
341 23:25:24.907416 - {TEE}: None
342 23:25:24.907469 Parsed boot commands:
343 23:25:24.907521 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:25:24.907703 Parsed boot commands: tftpboot 192.168.201.1 12172424/tftp-deploy-1ans5gei/kernel/image.itb 12172424/tftp-deploy-1ans5gei/kernel/cmdline
345 23:25:24.907790 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:25:24.907871 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:25:24.907961 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:25:24.908049 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:25:24.908119 Not connected, no need to disconnect.
350 23:25:24.908190 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:25:24.908267 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:25:24.908332 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:25:24.912513 Setting prompt string to ['lava-test: # ']
354 23:25:24.912894 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:25:24.913003 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:25:24.913104 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:25:24.913237 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:25:24.913474 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:25:30.054660 >> Command sent successfully.
360 23:25:30.057374 Returned 0 in 5 seconds
361 23:25:30.157762 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:25:30.158096 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:25:30.158198 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:25:30.158292 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:25:30.158360 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:25:30.158426 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:25:30.158697 [Enter `^Ec?' for help]
369 23:25:30.331125
370 23:25:30.331406
371 23:25:30.331545 F0: 102B 0000
372 23:25:30.331641
373 23:25:30.331726 F3: 1001 0000 [0200]
374 23:25:30.334598
375 23:25:30.334718 F3: 1001 0000
376 23:25:30.334811
377 23:25:30.334897 F7: 102D 0000
378 23:25:30.334980
379 23:25:30.338281 F1: 0000 0000
380 23:25:30.338978
381 23:25:30.339591 V0: 0000 0000 [0001]
382 23:25:30.340176
383 23:25:30.341684 00: 0007 8000
384 23:25:30.342368
385 23:25:30.342975 01: 0000 0000
386 23:25:30.343589
387 23:25:30.344884 BP: 0C00 0209 [0000]
388 23:25:30.345307
389 23:25:30.345679 G0: 1182 0000
390 23:25:30.346010
391 23:25:30.348565 EC: 0000 0021 [4000]
392 23:25:30.349064
393 23:25:30.349443 S7: 0000 0000 [0000]
394 23:25:30.349921
395 23:25:30.352218 CC: 0000 0000 [0001]
396 23:25:30.352817
397 23:25:30.353158 T0: 0000 0040 [010F]
398 23:25:30.353466
399 23:25:30.353853 Jump to BL
400 23:25:30.354146
401 23:25:30.378765
402 23:25:30.378975
403 23:25:30.379192
404 23:25:30.385610 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:25:30.389135 ARM64: Exception handlers installed.
406 23:25:30.392616 ARM64: Testing exception
407 23:25:30.396132 ARM64: Done test exception
408 23:25:30.402560 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:25:30.413353 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:25:30.420041 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:25:30.430174 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:25:30.436747 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:25:30.443659 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:25:30.455162 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:25:30.462463 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:25:30.481416 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:25:30.484560 WDT: Last reset was cold boot
418 23:25:30.487846 SPI1(PAD0) initialized at 2873684 Hz
419 23:25:30.491216 SPI5(PAD0) initialized at 992727 Hz
420 23:25:30.494387 VBOOT: Loading verstage.
421 23:25:30.501617 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:25:30.505426 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:25:30.508287 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:25:30.511930 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:25:30.519441 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:25:30.525361 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:25:30.536820 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
428 23:25:30.537334
429 23:25:30.537715
430 23:25:30.547566 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:25:30.550909 ARM64: Exception handlers installed.
432 23:25:30.551425 ARM64: Testing exception
433 23:25:30.554213 ARM64: Done test exception
434 23:25:30.558449 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:25:30.564516 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:25:30.578141 Probing TPM: . done!
437 23:25:30.578702 TPM ready after 0 ms
438 23:25:30.584807 Connected to device vid:did:rid of 1ae0:0028:00
439 23:25:30.592447 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:25:30.650889 Initialized TPM device CR50 revision 0
441 23:25:30.663416 tlcl_send_startup: Startup return code is 0
442 23:25:30.663976 TPM: setup succeeded
443 23:25:30.674630 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:25:30.683699 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:25:30.695412 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:25:30.706028 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:25:30.710025 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:25:30.712666 in-header: 03 07 00 00 08 00 00 00
449 23:25:30.716989 in-data: aa e4 47 04 13 02 00 00
450 23:25:30.720404 Chrome EC: UHEPI supported
451 23:25:30.724003 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:25:30.728366 in-header: 03 95 00 00 08 00 00 00
453 23:25:30.732027 in-data: 18 20 20 08 00 00 00 00
454 23:25:30.732649 Phase 1
455 23:25:30.735937 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:25:30.743444 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:25:30.751362 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:25:30.751844 Recovery requested (1009000e)
459 23:25:30.761129 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:25:30.771747 tlcl_extend: response is 0
461 23:25:30.778136 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:25:30.781709 tlcl_extend: response is 0
463 23:25:30.788595 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:25:30.809005 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 23:25:30.815090 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:25:30.815645
467 23:25:30.816011
468 23:25:30.825298 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:25:30.828945 ARM64: Exception handlers installed.
470 23:25:30.831734 ARM64: Testing exception
471 23:25:30.832296 ARM64: Done test exception
472 23:25:30.854362 pmic_efuse_setting: Set efuses in 11 msecs
473 23:25:30.857281 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:25:30.864294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:25:30.867806 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:25:30.871332 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:25:30.878950 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:25:30.882593 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:25:30.886679 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:25:30.894384 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:25:30.898006 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:25:30.901552 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:25:30.904954 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:25:30.912729 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:25:30.916642 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:25:30.920277 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:25:30.928219 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:25:30.931917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:25:30.938806 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:25:30.942752 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:25:30.950146 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:25:30.953893 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:25:30.961400 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:25:30.964575 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:25:30.972496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:25:30.975929 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:25:30.982978 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:25:30.986934 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:25:30.994067 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:25:30.998009 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:25:31.004837 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:25:31.008992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:25:31.012259 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:25:31.016291 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:25:31.023774 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:25:31.027401 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:25:31.034893 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:25:31.038403 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:25:31.042401 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:25:31.049883 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:25:31.053219 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:25:31.056727 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:25:31.060785 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:25:31.068062 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:25:31.071920 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:25:31.075403 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:25:31.078878 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:25:31.082940 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:25:31.087095 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:25:31.090564 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:25:31.097771 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:25:31.101163 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:25:31.105223 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:25:31.109028 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:25:31.116575 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:25:31.123554 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:25:31.130879 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:25:31.138141 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:25:31.145566 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:25:31.149354 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:25:31.156952 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:25:31.160796 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:25:31.168831 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x1b
534 23:25:31.171614 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:25:31.175493 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:25:31.182507 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:25:31.191312 [RTC]rtc_get_frequency_meter,154: input=15, output=758
538 23:25:31.200886 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 23:25:31.210181 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 23:25:31.220056 [RTC]rtc_get_frequency_meter,154: input=17, output=805
541 23:25:31.229961 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 23:25:31.239306 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 23:25:31.248788 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 23:25:31.252973 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:25:31.256659 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:25:31.260755 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:25:31.267974 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:25:31.271749 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:25:31.275759 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:25:31.279474 ADC[4]: Raw value=906203 ID=7
551 23:25:31.279941 ADC[3]: Raw value=213810 ID=1
552 23:25:31.283513 RAM Code: 0x71
553 23:25:31.287106 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:25:31.290948 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:25:31.298224 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:25:31.305385 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:25:31.309555 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:25:31.313344 in-header: 03 07 00 00 08 00 00 00
559 23:25:31.316674 in-data: aa e4 47 04 13 02 00 00
560 23:25:31.320720 Chrome EC: UHEPI supported
561 23:25:31.323646 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:25:31.327883 in-header: 03 95 00 00 08 00 00 00
563 23:25:31.331620 in-data: 18 20 20 08 00 00 00 00
564 23:25:31.335379 MRC: failed to locate region type 0.
565 23:25:31.343165 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:25:31.346464 DRAM-K: Running full calibration
567 23:25:31.349744 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:25:31.353618 header.status = 0x0
569 23:25:31.357167 header.version = 0x6 (expected: 0x6)
570 23:25:31.361013 header.size = 0xd00 (expected: 0xd00)
571 23:25:31.361435 header.flags = 0x0
572 23:25:31.368243 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:25:31.386920 read SPI 0x72590 0x1c583: 12496 us, 9290 KB/s, 74.320 Mbps
574 23:25:31.394023 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:25:31.394497 dram_init: ddr_geometry: 2
576 23:25:31.397338 [EMI] MDL number = 2
577 23:25:31.397823 [EMI] Get MDL freq = 0
578 23:25:31.400945 dram_init: ddr_type: 0
579 23:25:31.404814 is_discrete_lpddr4: 1
580 23:25:31.405345 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:25:31.405717
582 23:25:31.409284
583 23:25:31.409854 [Bian_co] ETT version 0.0.0.1
584 23:25:31.412423 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:25:31.412848
586 23:25:31.420073 dramc_set_vcore_voltage set vcore to 650000
587 23:25:31.420569 Read voltage for 800, 4
588 23:25:31.421024 Vio18 = 0
589 23:25:31.422989 Vcore = 650000
590 23:25:31.423453 Vdram = 0
591 23:25:31.423783 Vddq = 0
592 23:25:31.427076 Vmddr = 0
593 23:25:31.427517 dram_init: config_dvfs: 1
594 23:25:31.434251 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:25:31.437867 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:25:31.441857 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:25:31.445876 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:25:31.449257 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:25:31.453357 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:25:31.456293 MEM_TYPE=3, freq_sel=18
601 23:25:31.460174 sv_algorithm_assistance_LP4_1600
602 23:25:31.463619 ============ PULL DRAM RESETB DOWN ============
603 23:25:31.467040 ========== PULL DRAM RESETB DOWN end =========
604 23:25:31.469940 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:25:31.474028 ===================================
606 23:25:31.477255 LPDDR4 DRAM CONFIGURATION
607 23:25:31.480951 ===================================
608 23:25:31.481525 EX_ROW_EN[0] = 0x0
609 23:25:31.484641 EX_ROW_EN[1] = 0x0
610 23:25:31.485181 LP4Y_EN = 0x0
611 23:25:31.488473 WORK_FSP = 0x0
612 23:25:31.489186 WL = 0x2
613 23:25:31.492083 RL = 0x2
614 23:25:31.492502 BL = 0x2
615 23:25:31.495781 RPST = 0x0
616 23:25:31.496318 RD_PRE = 0x0
617 23:25:31.498972 WR_PRE = 0x1
618 23:25:31.499402 WR_PST = 0x0
619 23:25:31.502537 DBI_WR = 0x0
620 23:25:31.503073 DBI_RD = 0x0
621 23:25:31.506308 OTF = 0x1
622 23:25:31.509292 ===================================
623 23:25:31.512583 ===================================
624 23:25:31.513161 ANA top config
625 23:25:31.515711 ===================================
626 23:25:31.519260 DLL_ASYNC_EN = 0
627 23:25:31.522567 ALL_SLAVE_EN = 1
628 23:25:31.523133 NEW_RANK_MODE = 1
629 23:25:31.525652 DLL_IDLE_MODE = 1
630 23:25:31.529901 LP45_APHY_COMB_EN = 1
631 23:25:31.532913 TX_ODT_DIS = 1
632 23:25:31.533480 NEW_8X_MODE = 1
633 23:25:31.536591 ===================================
634 23:25:31.540443 ===================================
635 23:25:31.543489 data_rate = 1600
636 23:25:31.546491 CKR = 1
637 23:25:31.549790 DQ_P2S_RATIO = 8
638 23:25:31.553232 ===================================
639 23:25:31.556542 CA_P2S_RATIO = 8
640 23:25:31.557005 DQ_CA_OPEN = 0
641 23:25:31.560225 DQ_SEMI_OPEN = 0
642 23:25:31.563641 CA_SEMI_OPEN = 0
643 23:25:31.566505 CA_FULL_RATE = 0
644 23:25:31.569960 DQ_CKDIV4_EN = 1
645 23:25:31.573512 CA_CKDIV4_EN = 1
646 23:25:31.574170 CA_PREDIV_EN = 0
647 23:25:31.576634 PH8_DLY = 0
648 23:25:31.579929 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:25:31.583405 DQ_AAMCK_DIV = 4
650 23:25:31.586829 CA_AAMCK_DIV = 4
651 23:25:31.590021 CA_ADMCK_DIV = 4
652 23:25:31.590443 DQ_TRACK_CA_EN = 0
653 23:25:31.593534 CA_PICK = 800
654 23:25:31.597004 CA_MCKIO = 800
655 23:25:31.600519 MCKIO_SEMI = 0
656 23:25:31.604149 PLL_FREQ = 3068
657 23:25:31.604706 DQ_UI_PI_RATIO = 32
658 23:25:31.608319 CA_UI_PI_RATIO = 0
659 23:25:31.611592 ===================================
660 23:25:31.615526 ===================================
661 23:25:31.619220 memory_type:LPDDR4
662 23:25:31.619739 GP_NUM : 10
663 23:25:31.623388 SRAM_EN : 1
664 23:25:31.623905 MD32_EN : 0
665 23:25:31.626438 ===================================
666 23:25:31.630538 [ANA_INIT] >>>>>>>>>>>>>>
667 23:25:31.631123 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:25:31.634681 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:25:31.637513 ===================================
670 23:25:31.641325 data_rate = 1600,PCW = 0X7600
671 23:25:31.644614 ===================================
672 23:25:31.647785 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:25:31.654232 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:25:31.657958 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:25:31.664851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:25:31.667939 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:25:31.671455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:25:31.674565 [ANA_INIT] flow start
679 23:25:31.675201 [ANA_INIT] PLL >>>>>>>>
680 23:25:31.677506 [ANA_INIT] PLL <<<<<<<<
681 23:25:31.680900 [ANA_INIT] MIDPI >>>>>>>>
682 23:25:31.681364 [ANA_INIT] MIDPI <<<<<<<<
683 23:25:31.683985 [ANA_INIT] DLL >>>>>>>>
684 23:25:31.687372 [ANA_INIT] flow end
685 23:25:31.690645 ============ LP4 DIFF to SE enter ============
686 23:25:31.694274 ============ LP4 DIFF to SE exit ============
687 23:25:31.697565 [ANA_INIT] <<<<<<<<<<<<<
688 23:25:31.701016 [Flow] Enable top DCM control >>>>>
689 23:25:31.704410 [Flow] Enable top DCM control <<<<<
690 23:25:31.707681 Enable DLL master slave shuffle
691 23:25:31.711091 ==============================================================
692 23:25:31.714515 Gating Mode config
693 23:25:31.717778 ==============================================================
694 23:25:31.721083 Config description:
695 23:25:31.731229 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:25:31.737971 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:25:31.741012 SELPH_MODE 0: By rank 1: By Phase
698 23:25:31.748147 ==============================================================
699 23:25:31.750877 GAT_TRACK_EN = 1
700 23:25:31.754600 RX_GATING_MODE = 2
701 23:25:31.757713 RX_GATING_TRACK_MODE = 2
702 23:25:31.761292 SELPH_MODE = 1
703 23:25:31.761811 PICG_EARLY_EN = 1
704 23:25:31.765091 VALID_LAT_VALUE = 1
705 23:25:31.771361 ==============================================================
706 23:25:31.774938 Enter into Gating configuration >>>>
707 23:25:31.777875 Exit from Gating configuration <<<<
708 23:25:31.781502 Enter into DVFS_PRE_config >>>>>
709 23:25:31.791445 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:25:31.794263 Exit from DVFS_PRE_config <<<<<
711 23:25:31.797852 Enter into PICG configuration >>>>
712 23:25:31.801243 Exit from PICG configuration <<<<
713 23:25:31.804530 [RX_INPUT] configuration >>>>>
714 23:25:31.807718 [RX_INPUT] configuration <<<<<
715 23:25:31.810913 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:25:31.817728 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:25:31.824328 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:25:31.831835 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:25:31.837735 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:25:31.841090 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:25:31.847934 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:25:31.850893 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:25:31.854510 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:25:31.857415 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:25:31.864488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:25:31.867639 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:25:31.871012 ===================================
728 23:25:31.874233 LPDDR4 DRAM CONFIGURATION
729 23:25:31.877987 ===================================
730 23:25:31.878510 EX_ROW_EN[0] = 0x0
731 23:25:31.881347 EX_ROW_EN[1] = 0x0
732 23:25:31.881909 LP4Y_EN = 0x0
733 23:25:31.884592 WORK_FSP = 0x0
734 23:25:31.885115 WL = 0x2
735 23:25:31.887919 RL = 0x2
736 23:25:31.888342 BL = 0x2
737 23:25:31.890759 RPST = 0x0
738 23:25:31.891183 RD_PRE = 0x0
739 23:25:31.894150 WR_PRE = 0x1
740 23:25:31.894574 WR_PST = 0x0
741 23:25:31.898106 DBI_WR = 0x0
742 23:25:31.898629 DBI_RD = 0x0
743 23:25:31.901167 OTF = 0x1
744 23:25:31.904544 ===================================
745 23:25:31.908000 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:25:31.911073 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:25:31.917543 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:25:31.920769 ===================================
749 23:25:31.921192 LPDDR4 DRAM CONFIGURATION
750 23:25:31.924532 ===================================
751 23:25:31.927887 EX_ROW_EN[0] = 0x10
752 23:25:31.931127 EX_ROW_EN[1] = 0x0
753 23:25:31.931651 LP4Y_EN = 0x0
754 23:25:31.934176 WORK_FSP = 0x0
755 23:25:31.934600 WL = 0x2
756 23:25:31.937784 RL = 0x2
757 23:25:31.938309 BL = 0x2
758 23:25:31.940542 RPST = 0x0
759 23:25:31.940965 RD_PRE = 0x0
760 23:25:31.944169 WR_PRE = 0x1
761 23:25:31.944689 WR_PST = 0x0
762 23:25:31.947394 DBI_WR = 0x0
763 23:25:31.947816 DBI_RD = 0x0
764 23:25:31.950558 OTF = 0x1
765 23:25:31.954104 ===================================
766 23:25:31.961414 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:25:31.964127 nWR fixed to 40
768 23:25:31.967434 [ModeRegInit_LP4] CH0 RK0
769 23:25:31.967857 [ModeRegInit_LP4] CH0 RK1
770 23:25:31.970709 [ModeRegInit_LP4] CH1 RK0
771 23:25:31.974163 [ModeRegInit_LP4] CH1 RK1
772 23:25:31.974588 match AC timing 13
773 23:25:31.980283 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:25:31.984174 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:25:31.987354 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:25:31.994079 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:25:31.997460 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:25:31.998043 [EMI DOE] emi_dcm 0
779 23:25:32.004227 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:25:32.004750 ==
781 23:25:32.007697 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:25:32.010349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:25:32.010778 ==
784 23:25:32.017393 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:25:32.020774 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:25:32.031211 [CA 0] Center 36 (6~67) winsize 62
787 23:25:32.034954 [CA 1] Center 36 (6~67) winsize 62
788 23:25:32.038284 [CA 2] Center 34 (4~65) winsize 62
789 23:25:32.040881 [CA 3] Center 34 (4~64) winsize 61
790 23:25:32.044965 [CA 4] Center 33 (2~64) winsize 63
791 23:25:32.047620 [CA 5] Center 32 (2~62) winsize 61
792 23:25:32.048093
793 23:25:32.051277 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:25:32.051746
795 23:25:32.054413 [CATrainingPosCal] consider 1 rank data
796 23:25:32.057692 u2DelayCellTimex100 = 270/100 ps
797 23:25:32.061779 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:25:32.064273 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:25:32.070702 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 23:25:32.074034 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 23:25:32.077393 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
802 23:25:32.080643 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 23:25:32.081067
804 23:25:32.084297 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:25:32.084820
806 23:25:32.087703 [CBTSetCACLKResult] CA Dly = 32
807 23:25:32.088230 CS Dly: 4 (0~35)
808 23:25:32.090632 ==
809 23:25:32.094140 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:25:32.097774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:25:32.098201 ==
812 23:25:32.101263 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:25:32.108170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:25:32.117800 [CA 0] Center 36 (6~67) winsize 62
815 23:25:32.121092 [CA 1] Center 36 (6~67) winsize 62
816 23:25:32.124366 [CA 2] Center 34 (4~65) winsize 62
817 23:25:32.127466 [CA 3] Center 34 (3~65) winsize 63
818 23:25:32.130784 [CA 4] Center 33 (2~64) winsize 63
819 23:25:32.134551 [CA 5] Center 32 (2~63) winsize 62
820 23:25:32.135114
821 23:25:32.137083 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:25:32.137551
823 23:25:32.140400 [CATrainingPosCal] consider 2 rank data
824 23:25:32.144315 u2DelayCellTimex100 = 270/100 ps
825 23:25:32.147544 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:25:32.151307 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:25:32.157775 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:25:32.160704 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 23:25:32.164174 CA4 delay=33 (2~64),Diff = 1 PI (7 cell)
830 23:25:32.167354 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 23:25:32.167827
832 23:25:32.170905 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:25:32.171478
834 23:25:32.174547 [CBTSetCACLKResult] CA Dly = 32
835 23:25:32.175109 CS Dly: 5 (0~37)
836 23:25:32.175482
837 23:25:32.178482 ----->DramcWriteLeveling(PI) begin...
838 23:25:32.179077 ==
839 23:25:32.182136 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:25:32.185904 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:25:32.186491 ==
842 23:25:32.189110 Write leveling (Byte 0): 34 => 34
843 23:25:32.193045 Write leveling (Byte 1): 33 => 33
844 23:25:32.196259 DramcWriteLeveling(PI) end<-----
845 23:25:32.196685
846 23:25:32.197054 ==
847 23:25:32.199789 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:25:32.202928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:25:32.203415 ==
850 23:25:32.207032 [Gating] SW mode calibration
851 23:25:32.213513 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:25:32.220885 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:25:32.223927 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:25:32.227469 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:25:32.233621 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 23:25:32.237470 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 23:25:32.240446 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:25:32.243966 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:25:32.250885 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:25:32.253837 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:25:32.257761 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:25:32.264146 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:25:32.267470 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:25:32.270858 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:25:32.277737 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:25:32.280606 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:25:32.284334 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:25:32.291170 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:25:32.294871 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:25:32.297628 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:25:32.304567 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 23:25:32.307462 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:25:32.310981 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:25:32.314352 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:25:32.320952 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:25:32.324245 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:25:32.327600 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:25:32.334070 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:25:32.337563 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
880 23:25:32.340968 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
881 23:25:32.347481 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:25:32.350755 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:25:32.354254 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:25:32.360856 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:25:32.364026 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:25:32.367513 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 23:25:32.374471 0 10 8 | B1->B0 | 2f2f 2525 | 0 0 | (0 0) (0 0)
888 23:25:32.377440 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
889 23:25:32.381300 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:25:32.384488 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:25:32.391519 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:25:32.394421 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:25:32.397672 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:25:32.404491 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
895 23:25:32.407585 0 11 8 | B1->B0 | 2b2b 3f3f | 0 1 | (0 0) (0 0)
896 23:25:32.410957 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
897 23:25:32.417375 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:25:32.421396 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:25:32.424684 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:25:32.431108 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:25:32.434872 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:25:32.438357 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:25:32.444801 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:25:32.447932 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:25:32.451725 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:25:32.454337 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:25:32.461430 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:25:32.464772 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:25:32.467700 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:25:32.474357 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:25:32.477766 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:25:32.481085 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:25:32.487866 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:25:32.491794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:25:32.494593 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:25:32.501254 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:25:32.504544 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:25:32.508130 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:25:32.515043 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 23:25:32.518103 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 23:25:32.521470 Total UI for P1: 0, mck2ui 16
922 23:25:32.524800 best dqsien dly found for B0: ( 0, 14, 6)
923 23:25:32.527695 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 23:25:32.532004 Total UI for P1: 0, mck2ui 16
925 23:25:32.535500 best dqsien dly found for B1: ( 0, 14, 10)
926 23:25:32.539035 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
927 23:25:32.542648 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 23:25:32.543214
929 23:25:32.545517 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
930 23:25:32.548624 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 23:25:32.552184 [Gating] SW calibration Done
932 23:25:32.552746 ==
933 23:25:32.555467 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:25:32.558581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:25:32.561817 ==
936 23:25:32.562287 RX Vref Scan: 0
937 23:25:32.562652
938 23:25:32.565191 RX Vref 0 -> 0, step: 1
939 23:25:32.565684
940 23:25:32.569255 RX Delay -130 -> 252, step: 16
941 23:25:32.572378 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
942 23:25:32.575406 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
943 23:25:32.578495 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 23:25:32.581900 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 23:25:32.588541 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
946 23:25:32.592466 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 23:25:32.595325 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
948 23:25:32.599090 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
949 23:25:32.602367 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
950 23:25:32.605601 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
951 23:25:32.612099 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
952 23:25:32.615313 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
953 23:25:32.618987 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
954 23:25:32.622109 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
955 23:25:32.629126 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
956 23:25:32.632269 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
957 23:25:32.632833 ==
958 23:25:32.635542 Dram Type= 6, Freq= 0, CH_0, rank 0
959 23:25:32.639170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 23:25:32.639732 ==
961 23:25:32.640113 DQS Delay:
962 23:25:32.642200 DQS0 = 0, DQS1 = 0
963 23:25:32.642666 DQM Delay:
964 23:25:32.646172 DQM0 = 90, DQM1 = 86
965 23:25:32.646734 DQ Delay:
966 23:25:32.648916 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 23:25:32.652356 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =101
968 23:25:32.655811 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
969 23:25:32.659247 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
970 23:25:32.659809
971 23:25:32.660173
972 23:25:32.660505 ==
973 23:25:32.662166 Dram Type= 6, Freq= 0, CH_0, rank 0
974 23:25:32.665392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 23:25:32.665887 ==
976 23:25:32.669233
977 23:25:32.669747
978 23:25:32.670115 TX Vref Scan disable
979 23:25:32.672577 == TX Byte 0 ==
980 23:25:32.675852 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
981 23:25:32.679393 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
982 23:25:32.682269 == TX Byte 1 ==
983 23:25:32.686126 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
984 23:25:32.689228 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
985 23:25:32.689863 ==
986 23:25:32.692596 Dram Type= 6, Freq= 0, CH_0, rank 0
987 23:25:32.699071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 23:25:32.699546 ==
989 23:25:32.711178 TX Vref=22, minBit 8, minWin=27, winSum=447
990 23:25:32.714761 TX Vref=24, minBit 10, minWin=27, winSum=452
991 23:25:32.718030 TX Vref=26, minBit 5, minWin=27, winSum=451
992 23:25:32.721041 TX Vref=28, minBit 5, minWin=28, winSum=456
993 23:25:32.724374 TX Vref=30, minBit 12, minWin=27, winSum=454
994 23:25:32.730744 TX Vref=32, minBit 10, minWin=27, winSum=451
995 23:25:32.734221 [TxChooseVref] Worse bit 5, Min win 28, Win sum 456, Final Vref 28
996 23:25:32.734802
997 23:25:32.737527 Final TX Range 1 Vref 28
998 23:25:32.738138
999 23:25:32.738527 ==
1000 23:25:32.740983 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 23:25:32.744395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 23:25:32.747717 ==
1003 23:25:32.748282
1004 23:25:32.748650
1005 23:25:32.749061 TX Vref Scan disable
1006 23:25:32.751076 == TX Byte 0 ==
1007 23:25:32.754667 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1008 23:25:32.757769 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1009 23:25:32.761486 == TX Byte 1 ==
1010 23:25:32.764561 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1011 23:25:32.767383 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1012 23:25:32.771439
1013 23:25:32.772020 [DATLAT]
1014 23:25:32.772411 Freq=800, CH0 RK0
1015 23:25:32.772755
1016 23:25:32.774382 DATLAT Default: 0xa
1017 23:25:32.774850 0, 0xFFFF, sum = 0
1018 23:25:32.777993 1, 0xFFFF, sum = 0
1019 23:25:32.778592 2, 0xFFFF, sum = 0
1020 23:25:32.781117 3, 0xFFFF, sum = 0
1021 23:25:32.781721 4, 0xFFFF, sum = 0
1022 23:25:32.784898 5, 0xFFFF, sum = 0
1023 23:25:32.787925 6, 0xFFFF, sum = 0
1024 23:25:32.788497 7, 0xFFFF, sum = 0
1025 23:25:32.790974 8, 0xFFFF, sum = 0
1026 23:25:32.791441 9, 0x0, sum = 1
1027 23:25:32.791808 10, 0x0, sum = 2
1028 23:25:32.794454 11, 0x0, sum = 3
1029 23:25:32.794917 12, 0x0, sum = 4
1030 23:25:32.798032 best_step = 10
1031 23:25:32.798492
1032 23:25:32.798850 ==
1033 23:25:32.801499 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 23:25:32.804486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 23:25:32.804952 ==
1036 23:25:32.807841 RX Vref Scan: 1
1037 23:25:32.808432
1038 23:25:32.808803 Set Vref Range= 32 -> 127
1039 23:25:32.809138
1040 23:25:32.811192 RX Vref 32 -> 127, step: 1
1041 23:25:32.811744
1042 23:25:32.814408 RX Delay -79 -> 252, step: 8
1043 23:25:32.814869
1044 23:25:32.817870 Set Vref, RX VrefLevel [Byte0]: 32
1045 23:25:32.821333 [Byte1]: 32
1046 23:25:32.821938
1047 23:25:32.824961 Set Vref, RX VrefLevel [Byte0]: 33
1048 23:25:32.827963 [Byte1]: 33
1049 23:25:32.831193
1050 23:25:32.831724 Set Vref, RX VrefLevel [Byte0]: 34
1051 23:25:32.834569 [Byte1]: 34
1052 23:25:32.838850
1053 23:25:32.839399 Set Vref, RX VrefLevel [Byte0]: 35
1054 23:25:32.842407 [Byte1]: 35
1055 23:25:32.846498
1056 23:25:32.846956 Set Vref, RX VrefLevel [Byte0]: 36
1057 23:25:32.849978 [Byte1]: 36
1058 23:25:32.854698
1059 23:25:32.855154 Set Vref, RX VrefLevel [Byte0]: 37
1060 23:25:32.857620 [Byte1]: 37
1061 23:25:32.861730
1062 23:25:32.862145 Set Vref, RX VrefLevel [Byte0]: 38
1063 23:25:32.865248 [Byte1]: 38
1064 23:25:32.869341
1065 23:25:32.869813 Set Vref, RX VrefLevel [Byte0]: 39
1066 23:25:32.873152 [Byte1]: 39
1067 23:25:32.877050
1068 23:25:32.877641 Set Vref, RX VrefLevel [Byte0]: 40
1069 23:25:32.880241 [Byte1]: 40
1070 23:25:32.884069
1071 23:25:32.884565 Set Vref, RX VrefLevel [Byte0]: 41
1072 23:25:32.887448 [Byte1]: 41
1073 23:25:32.891384
1074 23:25:32.891798 Set Vref, RX VrefLevel [Byte0]: 42
1075 23:25:32.895336 [Byte1]: 42
1076 23:25:32.899285
1077 23:25:32.899699 Set Vref, RX VrefLevel [Byte0]: 43
1078 23:25:32.902241 [Byte1]: 43
1079 23:25:32.906939
1080 23:25:32.907450 Set Vref, RX VrefLevel [Byte0]: 44
1081 23:25:32.910162 [Byte1]: 44
1082 23:25:32.914979
1083 23:25:32.915485 Set Vref, RX VrefLevel [Byte0]: 45
1084 23:25:32.917783 [Byte1]: 45
1085 23:25:32.922182
1086 23:25:32.922691 Set Vref, RX VrefLevel [Byte0]: 46
1087 23:25:32.925187 [Byte1]: 46
1088 23:25:32.929394
1089 23:25:32.930014 Set Vref, RX VrefLevel [Byte0]: 47
1090 23:25:32.933209 [Byte1]: 47
1091 23:25:32.937167
1092 23:25:32.937765 Set Vref, RX VrefLevel [Byte0]: 48
1093 23:25:32.940209 [Byte1]: 48
1094 23:25:32.944915
1095 23:25:32.945461 Set Vref, RX VrefLevel [Byte0]: 49
1096 23:25:32.948221 [Byte1]: 49
1097 23:25:32.952342
1098 23:25:32.952857 Set Vref, RX VrefLevel [Byte0]: 50
1099 23:25:32.955451 [Byte1]: 50
1100 23:25:32.959533
1101 23:25:32.960113 Set Vref, RX VrefLevel [Byte0]: 51
1102 23:25:32.962673 [Byte1]: 51
1103 23:25:32.967119
1104 23:25:32.967577 Set Vref, RX VrefLevel [Byte0]: 52
1105 23:25:32.970277 [Byte1]: 52
1106 23:25:32.974914
1107 23:25:32.975472 Set Vref, RX VrefLevel [Byte0]: 53
1108 23:25:32.977711 [Byte1]: 53
1109 23:25:32.982152
1110 23:25:32.982710 Set Vref, RX VrefLevel [Byte0]: 54
1111 23:25:32.985431 [Byte1]: 54
1112 23:25:32.989496
1113 23:25:32.990007 Set Vref, RX VrefLevel [Byte0]: 55
1114 23:25:32.992729 [Byte1]: 55
1115 23:25:32.997254
1116 23:25:32.997853 Set Vref, RX VrefLevel [Byte0]: 56
1117 23:25:33.000323 [Byte1]: 56
1118 23:25:33.004991
1119 23:25:33.005406 Set Vref, RX VrefLevel [Byte0]: 57
1120 23:25:33.008301 [Byte1]: 57
1121 23:25:33.012546
1122 23:25:33.013082 Set Vref, RX VrefLevel [Byte0]: 58
1123 23:25:33.015567 [Byte1]: 58
1124 23:25:33.019559
1125 23:25:33.019973 Set Vref, RX VrefLevel [Byte0]: 59
1126 23:25:33.023472 [Byte1]: 59
1127 23:25:33.027326
1128 23:25:33.027752 Set Vref, RX VrefLevel [Byte0]: 60
1129 23:25:33.031139 [Byte1]: 60
1130 23:25:33.035197
1131 23:25:33.035710 Set Vref, RX VrefLevel [Byte0]: 61
1132 23:25:33.038565 [Byte1]: 61
1133 23:25:33.042647
1134 23:25:33.043178 Set Vref, RX VrefLevel [Byte0]: 62
1135 23:25:33.045759 [Byte1]: 62
1136 23:25:33.050206
1137 23:25:33.050722 Set Vref, RX VrefLevel [Byte0]: 63
1138 23:25:33.053668 [Byte1]: 63
1139 23:25:33.058048
1140 23:25:33.058564 Set Vref, RX VrefLevel [Byte0]: 64
1141 23:25:33.060930 [Byte1]: 64
1142 23:25:33.065345
1143 23:25:33.065808 Set Vref, RX VrefLevel [Byte0]: 65
1144 23:25:33.068688 [Byte1]: 65
1145 23:25:33.073134
1146 23:25:33.073697 Set Vref, RX VrefLevel [Byte0]: 66
1147 23:25:33.076387 [Byte1]: 66
1148 23:25:33.080386
1149 23:25:33.080804 Set Vref, RX VrefLevel [Byte0]: 67
1150 23:25:33.083772 [Byte1]: 67
1151 23:25:33.088400
1152 23:25:33.088919 Set Vref, RX VrefLevel [Byte0]: 68
1153 23:25:33.091318 [Byte1]: 68
1154 23:25:33.095823
1155 23:25:33.096340 Set Vref, RX VrefLevel [Byte0]: 69
1156 23:25:33.098729 [Byte1]: 69
1157 23:25:33.103601
1158 23:25:33.104204 Set Vref, RX VrefLevel [Byte0]: 70
1159 23:25:33.106251 [Byte1]: 70
1160 23:25:33.110672
1161 23:25:33.111189 Set Vref, RX VrefLevel [Byte0]: 71
1162 23:25:33.113705 [Byte1]: 71
1163 23:25:33.118424
1164 23:25:33.119006 Set Vref, RX VrefLevel [Byte0]: 72
1165 23:25:33.121333 [Byte1]: 72
1166 23:25:33.125668
1167 23:25:33.126084 Set Vref, RX VrefLevel [Byte0]: 73
1168 23:25:33.128749 [Byte1]: 73
1169 23:25:33.133249
1170 23:25:33.133694 Set Vref, RX VrefLevel [Byte0]: 74
1171 23:25:33.136657 [Byte1]: 74
1172 23:25:33.141360
1173 23:25:33.141928 Set Vref, RX VrefLevel [Byte0]: 75
1174 23:25:33.143992 [Byte1]: 75
1175 23:25:33.148546
1176 23:25:33.149062 Set Vref, RX VrefLevel [Byte0]: 76
1177 23:25:33.151649 [Byte1]: 76
1178 23:25:33.156141
1179 23:25:33.156655 Set Vref, RX VrefLevel [Byte0]: 77
1180 23:25:33.159206 [Byte1]: 77
1181 23:25:33.163002
1182 23:25:33.163414 Set Vref, RX VrefLevel [Byte0]: 78
1183 23:25:33.166395 [Byte1]: 78
1184 23:25:33.171536
1185 23:25:33.172052 Final RX Vref Byte 0 = 59 to rank0
1186 23:25:33.174157 Final RX Vref Byte 1 = 61 to rank0
1187 23:25:33.177697 Final RX Vref Byte 0 = 59 to rank1
1188 23:25:33.180831 Final RX Vref Byte 1 = 61 to rank1==
1189 23:25:33.184309 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 23:25:33.187918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 23:25:33.191538 ==
1192 23:25:33.192057 DQS Delay:
1193 23:25:33.192384 DQS0 = 0, DQS1 = 0
1194 23:25:33.194588 DQM Delay:
1195 23:25:33.195020 DQM0 = 92, DQM1 = 85
1196 23:25:33.197822 DQ Delay:
1197 23:25:33.200894 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1198 23:25:33.201420 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =100
1199 23:25:33.204288 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1200 23:25:33.207783 DQ12 =92, DQ13 =96, DQ14 =92, DQ15 =92
1201 23:25:33.211234
1202 23:25:33.211744
1203 23:25:33.217905 [DQSOSCAuto] RK0, (LSB)MR18= 0x4c43, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 390 ps
1204 23:25:33.221310 CH0 RK0: MR19=606, MR18=4C43
1205 23:25:33.227703 CH0_RK0: MR19=0x606, MR18=0x4C43, DQSOSC=390, MR23=63, INC=97, DEC=64
1206 23:25:33.228223
1207 23:25:33.230991 ----->DramcWriteLeveling(PI) begin...
1208 23:25:33.231417 ==
1209 23:25:33.234059 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 23:25:33.237275 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 23:25:33.237725 ==
1212 23:25:33.241297 Write leveling (Byte 0): 34 => 34
1213 23:25:33.244509 Write leveling (Byte 1): 33 => 33
1214 23:25:33.247965 DramcWriteLeveling(PI) end<-----
1215 23:25:33.248481
1216 23:25:33.248811 ==
1217 23:25:33.250930 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 23:25:33.295199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 23:25:33.295790 ==
1220 23:25:33.296163 [Gating] SW mode calibration
1221 23:25:33.296870 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 23:25:33.297234 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 23:25:33.297563 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 23:25:33.298013 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 23:25:33.298345 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1226 23:25:33.298733 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:25:33.299058 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:25:33.299370 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:25:33.339543 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:25:33.340133 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:25:33.340504 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:25:33.341223 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:25:33.341628 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:25:33.342074 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:25:33.342406 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:25:33.342720 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:25:33.343028 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:25:33.343336 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:25:33.383433 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:25:33.384386 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1241 23:25:33.384778 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1242 23:25:33.385184 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:25:33.385661 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:25:33.386003 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:25:33.386392 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:25:33.386713 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:25:33.387019 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:25:33.387325 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1249 23:25:33.397112 0 9 8 | B1->B0 | 2929 2929 | 1 0 | (0 0) (0 0)
1250 23:25:33.397724 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:25:33.400092 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:25:33.403064 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:25:33.406957 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:25:33.410239 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 23:25:33.416891 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 23:25:33.419692 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1257 23:25:33.424269 0 10 8 | B1->B0 | 2424 2727 | 0 0 | (1 0) (0 0)
1258 23:25:33.427377 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:25:33.431491 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:25:33.438477 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:25:33.441758 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:25:33.445162 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 23:25:33.448932 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 23:25:33.455759 0 11 4 | B1->B0 | 2525 2626 | 0 0 | (1 1) (0 0)
1265 23:25:33.459520 0 11 8 | B1->B0 | 3d3d 3636 | 0 0 | (0 0) (0 0)
1266 23:25:33.462989 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:25:33.466201 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:25:33.473107 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:25:33.476771 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:25:33.479632 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:25:33.486256 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 23:25:33.489656 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 23:25:33.492824 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 23:25:33.499042 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:25:33.502779 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:25:33.506144 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:25:33.512710 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:25:33.516064 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:25:33.519586 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:25:33.526287 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:25:33.529939 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:25:33.532832 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:25:33.536801 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:25:33.543154 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:25:33.546173 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:25:33.549850 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:25:33.556704 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:25:33.559875 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:25:33.563145 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1290 23:25:33.566507 Total UI for P1: 0, mck2ui 16
1291 23:25:33.569681 best dqsien dly found for B1: ( 0, 14, 6)
1292 23:25:33.576757 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1293 23:25:33.577316 Total UI for P1: 0, mck2ui 16
1294 23:25:33.582975 best dqsien dly found for B0: ( 0, 14, 8)
1295 23:25:33.586697 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1296 23:25:33.590216 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1297 23:25:33.590776
1298 23:25:33.592938 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 23:25:33.596338 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1300 23:25:33.599942 [Gating] SW calibration Done
1301 23:25:33.600635 ==
1302 23:25:33.602816 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 23:25:33.606209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 23:25:33.606676 ==
1305 23:25:33.609726 RX Vref Scan: 0
1306 23:25:33.610186
1307 23:25:33.610540 RX Vref 0 -> 0, step: 1
1308 23:25:33.610876
1309 23:25:33.613703 RX Delay -130 -> 252, step: 16
1310 23:25:33.616511 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1311 23:25:33.623683 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1312 23:25:33.626818 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1313 23:25:33.630058 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1314 23:25:33.633638 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1315 23:25:33.636494 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1316 23:25:33.640243 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1317 23:25:33.646883 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1318 23:25:33.650435 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1319 23:25:33.653519 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1320 23:25:33.656580 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1321 23:25:33.663557 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1322 23:25:33.666402 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1323 23:25:33.670147 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1324 23:25:33.673203 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1325 23:25:33.676441 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1326 23:25:33.676903 ==
1327 23:25:33.680037 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:25:33.686848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:25:33.687402 ==
1330 23:25:33.687770 DQS Delay:
1331 23:25:33.689665 DQS0 = 0, DQS1 = 0
1332 23:25:33.690165 DQM Delay:
1333 23:25:33.690529 DQM0 = 92, DQM1 = 83
1334 23:25:33.693238 DQ Delay:
1335 23:25:33.696858 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =85
1336 23:25:33.700058 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1337 23:25:33.704018 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1338 23:25:33.707074 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
1339 23:25:33.707536
1340 23:25:33.707894
1341 23:25:33.708224 ==
1342 23:25:33.710122 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:25:33.713667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 23:25:33.714228 ==
1345 23:25:33.714588
1346 23:25:33.714919
1347 23:25:33.716652 TX Vref Scan disable
1348 23:25:33.717110 == TX Byte 0 ==
1349 23:25:33.723768 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1350 23:25:33.727249 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1351 23:25:33.727807 == TX Byte 1 ==
1352 23:25:33.733516 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1353 23:25:33.737184 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1354 23:25:33.737689 ==
1355 23:25:33.740611 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 23:25:33.743774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 23:25:33.744239 ==
1358 23:25:33.758157 TX Vref=22, minBit 10, minWin=27, winSum=450
1359 23:25:33.760818 TX Vref=24, minBit 8, minWin=27, winSum=449
1360 23:25:33.763919 TX Vref=26, minBit 1, minWin=28, winSum=454
1361 23:25:33.767464 TX Vref=28, minBit 11, minWin=27, winSum=453
1362 23:25:33.770944 TX Vref=30, minBit 10, minWin=27, winSum=453
1363 23:25:33.777168 TX Vref=32, minBit 10, minWin=27, winSum=452
1364 23:25:33.780475 [TxChooseVref] Worse bit 1, Min win 28, Win sum 454, Final Vref 26
1365 23:25:33.780930
1366 23:25:33.783799 Final TX Range 1 Vref 26
1367 23:25:33.784209
1368 23:25:33.784529 ==
1369 23:25:33.787340 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 23:25:33.790530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 23:25:33.793985 ==
1372 23:25:33.794278
1373 23:25:33.794505
1374 23:25:33.794715 TX Vref Scan disable
1375 23:25:33.797691 == TX Byte 0 ==
1376 23:25:33.801056 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1377 23:25:33.804478 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1378 23:25:33.808001 == TX Byte 1 ==
1379 23:25:33.811230 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1380 23:25:33.814022 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1381 23:25:33.817747
1382 23:25:33.818157 [DATLAT]
1383 23:25:33.818476 Freq=800, CH0 RK1
1384 23:25:33.818779
1385 23:25:33.820904 DATLAT Default: 0xa
1386 23:25:33.821316 0, 0xFFFF, sum = 0
1387 23:25:33.824421 1, 0xFFFF, sum = 0
1388 23:25:33.824840 2, 0xFFFF, sum = 0
1389 23:25:33.827310 3, 0xFFFF, sum = 0
1390 23:25:33.827728 4, 0xFFFF, sum = 0
1391 23:25:33.831168 5, 0xFFFF, sum = 0
1392 23:25:33.834467 6, 0xFFFF, sum = 0
1393 23:25:33.834883 7, 0xFFFF, sum = 0
1394 23:25:33.837393 8, 0xFFFF, sum = 0
1395 23:25:33.837861 9, 0x0, sum = 1
1396 23:25:33.838193 10, 0x0, sum = 2
1397 23:25:33.841487 11, 0x0, sum = 3
1398 23:25:33.841959 12, 0x0, sum = 4
1399 23:25:33.844291 best_step = 10
1400 23:25:33.844802
1401 23:25:33.845124 ==
1402 23:25:33.847749 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 23:25:33.851035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:25:33.851572 ==
1405 23:25:33.854676 RX Vref Scan: 0
1406 23:25:33.855088
1407 23:25:33.855556 RX Vref 0 -> 0, step: 1
1408 23:25:33.855977
1409 23:25:33.857671 RX Delay -95 -> 252, step: 8
1410 23:25:33.864842 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1411 23:25:33.867987 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1412 23:25:33.871132 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 23:25:33.874297 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1414 23:25:33.877933 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1415 23:25:33.884773 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1416 23:25:33.888052 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 23:25:33.891510 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 23:25:33.894465 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1419 23:25:33.897705 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1420 23:25:33.904685 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1421 23:25:33.908173 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1422 23:25:33.911329 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
1423 23:25:33.914224 iDelay=209, Bit 13, Center 84 (-23 ~ 192) 216
1424 23:25:33.918010 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 23:25:33.924521 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1426 23:25:33.925035 ==
1427 23:25:33.928014 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 23:25:33.931011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 23:25:33.931429 ==
1430 23:25:33.931755 DQS Delay:
1431 23:25:33.934743 DQS0 = 0, DQS1 = 0
1432 23:25:33.935246 DQM Delay:
1433 23:25:33.937847 DQM0 = 92, DQM1 = 83
1434 23:25:33.938300 DQ Delay:
1435 23:25:33.941264 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1436 23:25:33.944848 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1437 23:25:33.947808 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1438 23:25:33.951292 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1439 23:25:33.951810
1440 23:25:33.952137
1441 23:25:33.957557 [DQSOSCAuto] RK1, (LSB)MR18= 0x3f11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1442 23:25:33.961738 CH0 RK1: MR19=606, MR18=3F11
1443 23:25:33.968176 CH0_RK1: MR19=0x606, MR18=0x3F11, DQSOSC=393, MR23=63, INC=95, DEC=63
1444 23:25:33.971292 [RxdqsGatingPostProcess] freq 800
1445 23:25:33.977979 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 23:25:33.981239 Pre-setting of DQS Precalculation
1447 23:25:33.984537 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 23:25:33.985054 ==
1449 23:25:33.988136 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 23:25:33.991667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 23:25:33.992184 ==
1452 23:25:33.998121 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 23:25:34.004607 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 23:25:34.013099 [CA 0] Center 36 (6~67) winsize 62
1455 23:25:34.016348 [CA 1] Center 36 (6~67) winsize 62
1456 23:25:34.019507 [CA 2] Center 35 (5~66) winsize 62
1457 23:25:34.022530 [CA 3] Center 35 (5~65) winsize 61
1458 23:25:34.026411 [CA 4] Center 34 (4~65) winsize 62
1459 23:25:34.029326 [CA 5] Center 34 (4~65) winsize 62
1460 23:25:34.029834
1461 23:25:34.032646 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 23:25:34.033100
1463 23:25:34.036082 [CATrainingPosCal] consider 1 rank data
1464 23:25:34.039151 u2DelayCellTimex100 = 270/100 ps
1465 23:25:34.042581 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 23:25:34.045932 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 23:25:34.052666 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1468 23:25:34.056242 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1469 23:25:34.059450 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 23:25:34.063108 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 23:25:34.063744
1472 23:25:34.066313 CA PerBit enable=1, Macro0, CA PI delay=34
1473 23:25:34.066773
1474 23:25:34.069076 [CBTSetCACLKResult] CA Dly = 34
1475 23:25:34.069533 CS Dly: 5 (0~36)
1476 23:25:34.069928 ==
1477 23:25:34.072656 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 23:25:34.079998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 23:25:34.080555 ==
1480 23:25:34.083031 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 23:25:34.090074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 23:25:34.099044 [CA 0] Center 36 (6~67) winsize 62
1483 23:25:34.102905 [CA 1] Center 37 (6~68) winsize 63
1484 23:25:34.106790 [CA 2] Center 35 (4~66) winsize 63
1485 23:25:34.110618 [CA 3] Center 34 (4~65) winsize 62
1486 23:25:34.114554 [CA 4] Center 35 (5~66) winsize 62
1487 23:25:34.115062 [CA 5] Center 34 (4~65) winsize 62
1488 23:25:34.115392
1489 23:25:34.118770 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 23:25:34.119278
1491 23:25:34.122125 [CATrainingPosCal] consider 2 rank data
1492 23:25:34.125336 u2DelayCellTimex100 = 270/100 ps
1493 23:25:34.129314 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 23:25:34.132216 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 23:25:34.139362 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1496 23:25:34.142198 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1497 23:25:34.145781 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1498 23:25:34.149031 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1499 23:25:34.149619
1500 23:25:34.152175 CA PerBit enable=1, Macro0, CA PI delay=34
1501 23:25:34.152729
1502 23:25:34.155202 [CBTSetCACLKResult] CA Dly = 34
1503 23:25:34.155659 CS Dly: 6 (0~38)
1504 23:25:34.156023
1505 23:25:34.159077 ----->DramcWriteLeveling(PI) begin...
1506 23:25:34.162310 ==
1507 23:25:34.165782 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 23:25:34.168651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 23:25:34.169210 ==
1510 23:25:34.172140 Write leveling (Byte 0): 29 => 29
1511 23:25:34.175708 Write leveling (Byte 1): 29 => 29
1512 23:25:34.178375 DramcWriteLeveling(PI) end<-----
1513 23:25:34.178833
1514 23:25:34.179191 ==
1515 23:25:34.181710 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 23:25:34.185203 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 23:25:34.185810 ==
1518 23:25:34.188693 [Gating] SW mode calibration
1519 23:25:34.195573 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 23:25:34.198578 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 23:25:34.205465 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 23:25:34.208911 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1523 23:25:34.212723 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1524 23:25:34.219218 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:25:34.221893 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:25:34.225499 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:25:34.232349 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:25:34.235525 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:25:34.238722 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:25:34.245627 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:25:34.249434 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:25:34.252231 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:25:34.258577 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:25:34.261955 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:25:34.265779 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:25:34.272007 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:25:34.275595 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 23:25:34.278619 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1539 23:25:34.285352 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:25:34.288957 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:25:34.292776 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:25:34.295413 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:25:34.301994 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:25:34.305329 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:25:34.308665 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:25:34.315554 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1547 23:25:34.319223 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1548 23:25:34.322123 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:25:34.329321 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:25:34.331960 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:25:34.335358 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 23:25:34.342090 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 23:25:34.345674 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1554 23:25:34.349149 0 10 4 | B1->B0 | 3030 2b2b | 1 1 | (1 0) (1 0)
1555 23:25:34.355475 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1556 23:25:34.359235 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:25:34.361988 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:25:34.368757 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:25:34.371966 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:25:34.375242 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 23:25:34.382622 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 23:25:34.385687 0 11 4 | B1->B0 | 2727 3939 | 0 1 | (0 0) (0 0)
1563 23:25:34.388871 0 11 8 | B1->B0 | 4141 4646 | 1 0 | (0 0) (0 0)
1564 23:25:34.395018 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:25:34.398927 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:25:34.402169 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:25:34.408580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:25:34.412134 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 23:25:34.415370 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1570 23:25:34.418954 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 23:25:34.425477 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 23:25:34.428903 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:25:34.431601 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:25:34.438463 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:25:34.442140 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:25:34.445229 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:25:34.452376 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:25:34.455143 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:25:34.458817 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:25:34.465339 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:25:34.469027 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:25:34.471605 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:25:34.479018 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:25:34.482215 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:25:34.485707 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:25:34.492221 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1587 23:25:34.492815 Total UI for P1: 0, mck2ui 16
1588 23:25:34.495812 best dqsien dly found for B1: ( 0, 14, 2)
1589 23:25:34.502134 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1590 23:25:34.505456 Total UI for P1: 0, mck2ui 16
1591 23:25:34.508645 best dqsien dly found for B0: ( 0, 14, 4)
1592 23:25:34.512135 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1593 23:25:34.515222 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1594 23:25:34.515686
1595 23:25:34.518947 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1596 23:25:34.522061 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1597 23:25:34.525152 [Gating] SW calibration Done
1598 23:25:34.525645 ==
1599 23:25:34.528724 Dram Type= 6, Freq= 0, CH_1, rank 0
1600 23:25:34.532181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1601 23:25:34.532657 ==
1602 23:25:34.535691 RX Vref Scan: 0
1603 23:25:34.536113
1604 23:25:34.536443 RX Vref 0 -> 0, step: 1
1605 23:25:34.536803
1606 23:25:34.538554 RX Delay -130 -> 252, step: 16
1607 23:25:34.545332 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1608 23:25:34.548628 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1609 23:25:34.552444 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1610 23:25:34.555687 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1611 23:25:34.558833 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1612 23:25:34.562198 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1613 23:25:34.569127 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1614 23:25:34.572383 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1615 23:25:34.575244 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1616 23:25:34.578703 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1617 23:25:34.582584 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1618 23:25:34.588868 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1619 23:25:34.592643 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1620 23:25:34.595776 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1621 23:25:34.598842 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1622 23:25:34.602103 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1623 23:25:34.605465 ==
1624 23:25:34.608893 Dram Type= 6, Freq= 0, CH_1, rank 0
1625 23:25:34.612366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1626 23:25:34.612886 ==
1627 23:25:34.613217 DQS Delay:
1628 23:25:34.615322 DQS0 = 0, DQS1 = 0
1629 23:25:34.615742 DQM Delay:
1630 23:25:34.619079 DQM0 = 93, DQM1 = 87
1631 23:25:34.619500 DQ Delay:
1632 23:25:34.622205 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1633 23:25:34.625924 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1634 23:25:34.629173 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1635 23:25:34.632187 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1636 23:25:34.632610
1637 23:25:34.632934
1638 23:25:34.633326 ==
1639 23:25:34.635902 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 23:25:34.638985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 23:25:34.639436 ==
1642 23:25:34.639767
1643 23:25:34.640067
1644 23:25:34.641973 TX Vref Scan disable
1645 23:25:34.645562 == TX Byte 0 ==
1646 23:25:34.648969 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1647 23:25:34.652301 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1648 23:25:34.655309 == TX Byte 1 ==
1649 23:25:34.658557 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1650 23:25:34.662200 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1651 23:25:34.662719 ==
1652 23:25:34.665880 Dram Type= 6, Freq= 0, CH_1, rank 0
1653 23:25:34.669663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1654 23:25:34.670187 ==
1655 23:25:34.683512 TX Vref=22, minBit 0, minWin=27, winSum=439
1656 23:25:34.686592 TX Vref=24, minBit 3, minWin=26, winSum=441
1657 23:25:34.690384 TX Vref=26, minBit 1, minWin=27, winSum=444
1658 23:25:34.693621 TX Vref=28, minBit 1, minWin=27, winSum=449
1659 23:25:34.696806 TX Vref=30, minBit 0, minWin=27, winSum=449
1660 23:25:34.700752 TX Vref=32, minBit 2, minWin=26, winSum=447
1661 23:25:34.706565 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
1662 23:25:34.707103
1663 23:25:34.709943 Final TX Range 1 Vref 28
1664 23:25:34.710361
1665 23:25:34.710687 ==
1666 23:25:34.713744 Dram Type= 6, Freq= 0, CH_1, rank 0
1667 23:25:34.716952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1668 23:25:34.717472 ==
1669 23:25:34.717860
1670 23:25:34.718171
1671 23:25:34.720011 TX Vref Scan disable
1672 23:25:34.723364 == TX Byte 0 ==
1673 23:25:34.727167 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1674 23:25:34.729901 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1675 23:25:34.733506 == TX Byte 1 ==
1676 23:25:34.737110 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1677 23:25:34.740115 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1678 23:25:34.740529
1679 23:25:34.743523 [DATLAT]
1680 23:25:34.744042 Freq=800, CH1 RK0
1681 23:25:34.744372
1682 23:25:34.746759 DATLAT Default: 0xa
1683 23:25:34.747182 0, 0xFFFF, sum = 0
1684 23:25:34.750270 1, 0xFFFF, sum = 0
1685 23:25:34.750693 2, 0xFFFF, sum = 0
1686 23:25:34.753176 3, 0xFFFF, sum = 0
1687 23:25:34.753642 4, 0xFFFF, sum = 0
1688 23:25:34.756565 5, 0xFFFF, sum = 0
1689 23:25:34.756988 6, 0xFFFF, sum = 0
1690 23:25:34.760127 7, 0xFFFF, sum = 0
1691 23:25:34.760649 8, 0xFFFF, sum = 0
1692 23:25:34.763610 9, 0x0, sum = 1
1693 23:25:34.764129 10, 0x0, sum = 2
1694 23:25:34.767223 11, 0x0, sum = 3
1695 23:25:34.767744 12, 0x0, sum = 4
1696 23:25:34.769681 best_step = 10
1697 23:25:34.770098
1698 23:25:34.770422 ==
1699 23:25:34.773381 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 23:25:34.776760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 23:25:34.777180 ==
1702 23:25:34.780174 RX Vref Scan: 1
1703 23:25:34.780679
1704 23:25:34.781008 Set Vref Range= 32 -> 127
1705 23:25:34.781313
1706 23:25:34.783585 RX Vref 32 -> 127, step: 1
1707 23:25:34.784101
1708 23:25:34.787210 RX Delay -79 -> 252, step: 8
1709 23:25:34.787723
1710 23:25:34.790568 Set Vref, RX VrefLevel [Byte0]: 32
1711 23:25:34.793746 [Byte1]: 32
1712 23:25:34.794294
1713 23:25:34.796770 Set Vref, RX VrefLevel [Byte0]: 33
1714 23:25:34.800536 [Byte1]: 33
1715 23:25:34.801053
1716 23:25:34.803826 Set Vref, RX VrefLevel [Byte0]: 34
1717 23:25:34.807227 [Byte1]: 34
1718 23:25:34.811294
1719 23:25:34.811804 Set Vref, RX VrefLevel [Byte0]: 35
1720 23:25:34.817542 [Byte1]: 35
1721 23:25:34.818100
1722 23:25:34.821113 Set Vref, RX VrefLevel [Byte0]: 36
1723 23:25:34.824386 [Byte1]: 36
1724 23:25:34.824902
1725 23:25:34.827424 Set Vref, RX VrefLevel [Byte0]: 37
1726 23:25:34.830605 [Byte1]: 37
1727 23:25:34.831030
1728 23:25:34.834352 Set Vref, RX VrefLevel [Byte0]: 38
1729 23:25:34.837786 [Byte1]: 38
1730 23:25:34.841291
1731 23:25:34.841847 Set Vref, RX VrefLevel [Byte0]: 39
1732 23:25:34.844694 [Byte1]: 39
1733 23:25:34.849336
1734 23:25:34.849910 Set Vref, RX VrefLevel [Byte0]: 40
1735 23:25:34.852009 [Byte1]: 40
1736 23:25:34.856612
1737 23:25:34.857027 Set Vref, RX VrefLevel [Byte0]: 41
1738 23:25:34.859417 [Byte1]: 41
1739 23:25:34.863877
1740 23:25:34.864390 Set Vref, RX VrefLevel [Byte0]: 42
1741 23:25:34.867259 [Byte1]: 42
1742 23:25:34.871536
1743 23:25:34.872051 Set Vref, RX VrefLevel [Byte0]: 43
1744 23:25:34.874755 [Byte1]: 43
1745 23:25:34.878892
1746 23:25:34.879465 Set Vref, RX VrefLevel [Byte0]: 44
1747 23:25:34.881980 [Byte1]: 44
1748 23:25:34.886869
1749 23:25:34.887387 Set Vref, RX VrefLevel [Byte0]: 45
1750 23:25:34.889899 [Byte1]: 45
1751 23:25:34.894220
1752 23:25:34.894778 Set Vref, RX VrefLevel [Byte0]: 46
1753 23:25:34.897463 [Byte1]: 46
1754 23:25:34.901516
1755 23:25:34.901964 Set Vref, RX VrefLevel [Byte0]: 47
1756 23:25:34.904832 [Byte1]: 47
1757 23:25:34.909321
1758 23:25:34.909889 Set Vref, RX VrefLevel [Byte0]: 48
1759 23:25:34.912583 [Byte1]: 48
1760 23:25:34.916691
1761 23:25:34.917205 Set Vref, RX VrefLevel [Byte0]: 49
1762 23:25:34.920276 [Byte1]: 49
1763 23:25:34.924279
1764 23:25:34.924797 Set Vref, RX VrefLevel [Byte0]: 50
1765 23:25:34.927691 [Byte1]: 50
1766 23:25:34.931983
1767 23:25:34.932499 Set Vref, RX VrefLevel [Byte0]: 51
1768 23:25:34.935018 [Byte1]: 51
1769 23:25:34.939248
1770 23:25:34.939807 Set Vref, RX VrefLevel [Byte0]: 52
1771 23:25:34.942560 [Byte1]: 52
1772 23:25:34.947006
1773 23:25:34.947521 Set Vref, RX VrefLevel [Byte0]: 53
1774 23:25:34.950213 [Byte1]: 53
1775 23:25:34.954158
1776 23:25:34.954571 Set Vref, RX VrefLevel [Byte0]: 54
1777 23:25:34.957758 [Byte1]: 54
1778 23:25:34.962115
1779 23:25:34.962628 Set Vref, RX VrefLevel [Byte0]: 55
1780 23:25:34.965362 [Byte1]: 55
1781 23:25:34.969978
1782 23:25:34.970508 Set Vref, RX VrefLevel [Byte0]: 56
1783 23:25:34.972686 [Byte1]: 56
1784 23:25:34.976881
1785 23:25:34.977323 Set Vref, RX VrefLevel [Byte0]: 57
1786 23:25:34.980318 [Byte1]: 57
1787 23:25:34.984421
1788 23:25:34.984938 Set Vref, RX VrefLevel [Byte0]: 58
1789 23:25:34.987857 [Byte1]: 58
1790 23:25:34.992466
1791 23:25:34.993145 Set Vref, RX VrefLevel [Byte0]: 59
1792 23:25:34.995197 [Byte1]: 59
1793 23:25:34.999376
1794 23:25:34.999791 Set Vref, RX VrefLevel [Byte0]: 60
1795 23:25:35.002656 [Byte1]: 60
1796 23:25:35.007446
1797 23:25:35.007977 Set Vref, RX VrefLevel [Byte0]: 61
1798 23:25:35.010430 [Byte1]: 61
1799 23:25:35.014883
1800 23:25:35.015398 Set Vref, RX VrefLevel [Byte0]: 62
1801 23:25:35.017816 [Byte1]: 62
1802 23:25:35.022328
1803 23:25:35.022866 Set Vref, RX VrefLevel [Byte0]: 63
1804 23:25:35.025727 [Byte1]: 63
1805 23:25:35.030395
1806 23:25:35.030912 Set Vref, RX VrefLevel [Byte0]: 64
1807 23:25:35.033076 [Byte1]: 64
1808 23:25:35.037343
1809 23:25:35.037923 Set Vref, RX VrefLevel [Byte0]: 65
1810 23:25:35.040569 [Byte1]: 65
1811 23:25:35.045095
1812 23:25:35.045652 Set Vref, RX VrefLevel [Byte0]: 66
1813 23:25:35.048599 [Byte1]: 66
1814 23:25:35.052701
1815 23:25:35.053218 Set Vref, RX VrefLevel [Byte0]: 67
1816 23:25:35.055694 [Byte1]: 67
1817 23:25:35.060293
1818 23:25:35.060809 Set Vref, RX VrefLevel [Byte0]: 68
1819 23:25:35.063931 [Byte1]: 68
1820 23:25:35.067692
1821 23:25:35.068205 Set Vref, RX VrefLevel [Byte0]: 69
1822 23:25:35.071209 [Byte1]: 69
1823 23:25:35.075147
1824 23:25:35.075668 Set Vref, RX VrefLevel [Byte0]: 70
1825 23:25:35.078503 [Byte1]: 70
1826 23:25:35.082727
1827 23:25:35.083244 Set Vref, RX VrefLevel [Byte0]: 71
1828 23:25:35.086124 [Byte1]: 71
1829 23:25:35.090192
1830 23:25:35.090646 Set Vref, RX VrefLevel [Byte0]: 72
1831 23:25:35.093546 [Byte1]: 72
1832 23:25:35.097378
1833 23:25:35.097896 Final RX Vref Byte 0 = 56 to rank0
1834 23:25:35.101250 Final RX Vref Byte 1 = 55 to rank0
1835 23:25:35.104320 Final RX Vref Byte 0 = 56 to rank1
1836 23:25:35.107996 Final RX Vref Byte 1 = 55 to rank1==
1837 23:25:35.111190 Dram Type= 6, Freq= 0, CH_1, rank 0
1838 23:25:35.117903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1839 23:25:35.118460 ==
1840 23:25:35.118828 DQS Delay:
1841 23:25:35.119257 DQS0 = 0, DQS1 = 0
1842 23:25:35.121006 DQM Delay:
1843 23:25:35.121466 DQM0 = 95, DQM1 = 90
1844 23:25:35.124721 DQ Delay:
1845 23:25:35.127837 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1846 23:25:35.131303 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1847 23:25:35.134149 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1848 23:25:35.137891 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1849 23:25:35.138445
1850 23:25:35.138804
1851 23:25:35.144125 [DQSOSCAuto] RK0, (LSB)MR18= 0x2946, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
1852 23:25:35.147560 CH1 RK0: MR19=606, MR18=2946
1853 23:25:35.154316 CH1_RK0: MR19=0x606, MR18=0x2946, DQSOSC=392, MR23=63, INC=96, DEC=64
1854 23:25:35.154779
1855 23:25:35.157706 ----->DramcWriteLeveling(PI) begin...
1856 23:25:35.158294 ==
1857 23:25:35.161124 Dram Type= 6, Freq= 0, CH_1, rank 1
1858 23:25:35.164856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1859 23:25:35.165424 ==
1860 23:25:35.167704 Write leveling (Byte 0): 24 => 24
1861 23:25:35.171226 Write leveling (Byte 1): 30 => 30
1862 23:25:35.174591 DramcWriteLeveling(PI) end<-----
1863 23:25:35.175155
1864 23:25:35.175524 ==
1865 23:25:35.177866 Dram Type= 6, Freq= 0, CH_1, rank 1
1866 23:25:35.181156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1867 23:25:35.181771 ==
1868 23:25:35.184412 [Gating] SW mode calibration
1869 23:25:35.190901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1870 23:25:35.197646 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1871 23:25:35.201109 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1872 23:25:35.203766 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1873 23:25:35.210942 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 23:25:35.214115 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 23:25:35.217440 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 23:25:35.224289 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 23:25:35.227941 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 23:25:35.231156 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 23:25:35.237777 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 23:25:35.241521 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:25:35.244889 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:25:35.251316 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:25:35.254431 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:25:35.257624 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:25:35.264798 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:25:35.268165 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:25:35.271029 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1888 23:25:35.274589 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1889 23:25:35.281150 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:25:35.284473 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:25:35.288297 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:25:35.294344 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:25:35.298058 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:25:35.300848 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:25:35.308256 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 23:25:35.310781 0 9 4 | B1->B0 | 2525 2323 | 1 1 | (1 1) (1 1)
1897 23:25:35.314507 0 9 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
1898 23:25:35.320772 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1899 23:25:35.323992 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1900 23:25:35.327964 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1901 23:25:35.334273 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1902 23:25:35.338151 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1903 23:25:35.341509 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
1904 23:25:35.347820 0 10 4 | B1->B0 | 2b2b 3030 | 0 1 | (1 0) (1 0)
1905 23:25:35.351199 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1906 23:25:35.354518 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1907 23:25:35.361521 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1908 23:25:35.364337 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 23:25:35.368019 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 23:25:35.370826 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 23:25:35.377544 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 23:25:35.380931 0 11 4 | B1->B0 | 4242 2c2c | 0 0 | (0 0) (0 0)
1913 23:25:35.384742 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 23:25:35.391302 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1915 23:25:35.394581 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1916 23:25:35.397632 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1917 23:25:35.404112 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1918 23:25:35.408154 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1919 23:25:35.411060 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1920 23:25:35.417751 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1921 23:25:35.421177 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1922 23:25:35.423975 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 23:25:35.430849 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 23:25:35.434110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 23:25:35.437851 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 23:25:35.444630 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 23:25:35.447984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 23:25:35.450970 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 23:25:35.457564 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:25:35.461442 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:25:35.464604 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:25:35.467888 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:25:35.474583 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:25:35.477708 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:25:35.480920 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:25:35.488189 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1937 23:25:35.490906 Total UI for P1: 0, mck2ui 16
1938 23:25:35.494549 best dqsien dly found for B1: ( 0, 14, 2)
1939 23:25:35.498030 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1940 23:25:35.501061 Total UI for P1: 0, mck2ui 16
1941 23:25:35.504228 best dqsien dly found for B0: ( 0, 14, 4)
1942 23:25:35.507634 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1943 23:25:35.510897 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1944 23:25:35.511633
1945 23:25:35.514311 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1946 23:25:35.518006 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1947 23:25:35.521165 [Gating] SW calibration Done
1948 23:25:35.521919 ==
1949 23:25:35.524445 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 23:25:35.527871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 23:25:35.528376 ==
1952 23:25:35.530924 RX Vref Scan: 0
1953 23:25:35.531293
1954 23:25:35.534556 RX Vref 0 -> 0, step: 1
1955 23:25:35.534836
1956 23:25:35.537178 RX Delay -130 -> 252, step: 16
1957 23:25:35.540758 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1958 23:25:35.543687 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1959 23:25:35.547215 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1960 23:25:35.550576 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1961 23:25:35.554059 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1962 23:25:35.560240 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1963 23:25:35.563998 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1964 23:25:35.567285 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1965 23:25:35.570683 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1966 23:25:35.574095 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1967 23:25:35.580508 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1968 23:25:35.583537 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1969 23:25:35.586944 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1970 23:25:35.590306 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1971 23:25:35.597162 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1972 23:25:35.600982 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1973 23:25:35.601114 ==
1974 23:25:35.603804 Dram Type= 6, Freq= 0, CH_1, rank 1
1975 23:25:35.607493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1976 23:25:35.607640 ==
1977 23:25:35.607755 DQS Delay:
1978 23:25:35.610876 DQS0 = 0, DQS1 = 0
1979 23:25:35.611127 DQM Delay:
1980 23:25:35.613951 DQM0 = 93, DQM1 = 92
1981 23:25:35.614127 DQ Delay:
1982 23:25:35.617256 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1983 23:25:35.620548 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =93
1984 23:25:35.623627 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =85
1985 23:25:35.627905 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1986 23:25:35.628264
1987 23:25:35.628487
1988 23:25:35.628684 ==
1989 23:25:35.630806 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 23:25:35.637351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 23:25:35.637965 ==
1992 23:25:35.638332
1993 23:25:35.638660
1994 23:25:35.638975 TX Vref Scan disable
1995 23:25:35.640830 == TX Byte 0 ==
1996 23:25:35.644664 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1997 23:25:35.651465 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1998 23:25:35.652027 == TX Byte 1 ==
1999 23:25:35.654937 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2000 23:25:35.657775 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2001 23:25:35.661552 ==
2002 23:25:35.664778 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 23:25:35.668494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 23:25:35.669051 ==
2005 23:25:35.680856 TX Vref=22, minBit 3, minWin=26, winSum=441
2006 23:25:35.684104 TX Vref=24, minBit 5, minWin=26, winSum=444
2007 23:25:35.687857 TX Vref=26, minBit 0, minWin=27, winSum=446
2008 23:25:35.690996 TX Vref=28, minBit 0, minWin=27, winSum=451
2009 23:25:35.694093 TX Vref=30, minBit 5, minWin=26, winSum=448
2010 23:25:35.697662 TX Vref=32, minBit 5, minWin=26, winSum=447
2011 23:25:35.704045 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 28
2012 23:25:35.704505
2013 23:25:35.707831 Final TX Range 1 Vref 28
2014 23:25:35.708384
2015 23:25:35.708741 ==
2016 23:25:35.711103 Dram Type= 6, Freq= 0, CH_1, rank 1
2017 23:25:35.713944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2018 23:25:35.714403 ==
2019 23:25:35.714759
2020 23:25:35.717670
2021 23:25:35.718221 TX Vref Scan disable
2022 23:25:35.721404 == TX Byte 0 ==
2023 23:25:35.724155 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
2024 23:25:35.728009 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
2025 23:25:35.731304 == TX Byte 1 ==
2026 23:25:35.734296 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2027 23:25:35.738267 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2028 23:25:35.740944
2029 23:25:35.741396 [DATLAT]
2030 23:25:35.741829 Freq=800, CH1 RK1
2031 23:25:35.742224
2032 23:25:35.744100 DATLAT Default: 0xa
2033 23:25:35.744673 0, 0xFFFF, sum = 0
2034 23:25:35.747502 1, 0xFFFF, sum = 0
2035 23:25:35.748073 2, 0xFFFF, sum = 0
2036 23:25:35.750802 3, 0xFFFF, sum = 0
2037 23:25:35.751265 4, 0xFFFF, sum = 0
2038 23:25:35.754359 5, 0xFFFF, sum = 0
2039 23:25:35.754963 6, 0xFFFF, sum = 0
2040 23:25:35.757316 7, 0xFFFF, sum = 0
2041 23:25:35.761017 8, 0xFFFF, sum = 0
2042 23:25:35.761793 9, 0x0, sum = 1
2043 23:25:35.762182 10, 0x0, sum = 2
2044 23:25:35.764456 11, 0x0, sum = 3
2045 23:25:35.765016 12, 0x0, sum = 4
2046 23:25:35.767419 best_step = 10
2047 23:25:35.767971
2048 23:25:35.768326 ==
2049 23:25:35.770873 Dram Type= 6, Freq= 0, CH_1, rank 1
2050 23:25:35.774643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2051 23:25:35.775197 ==
2052 23:25:35.777846 RX Vref Scan: 0
2053 23:25:35.778394
2054 23:25:35.778754 RX Vref 0 -> 0, step: 1
2055 23:25:35.779086
2056 23:25:35.780624 RX Delay -79 -> 252, step: 8
2057 23:25:35.787590 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2058 23:25:35.791175 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2059 23:25:35.794367 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2060 23:25:35.797772 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2061 23:25:35.800839 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2062 23:25:35.804650 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2063 23:25:35.811273 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2064 23:25:35.814387 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2065 23:25:35.817670 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2066 23:25:35.820987 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2067 23:25:35.824510 iDelay=209, Bit 10, Center 96 (-7 ~ 200) 208
2068 23:25:35.831711 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2069 23:25:35.834671 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2070 23:25:35.837935 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2071 23:25:35.841179 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2072 23:25:35.844267 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2073 23:25:35.844819 ==
2074 23:25:35.847680 Dram Type= 6, Freq= 0, CH_1, rank 1
2075 23:25:35.854759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2076 23:25:35.855307 ==
2077 23:25:35.855668 DQS Delay:
2078 23:25:35.857569 DQS0 = 0, DQS1 = 0
2079 23:25:35.858058 DQM Delay:
2080 23:25:35.858413 DQM0 = 97, DQM1 = 91
2081 23:25:35.860729 DQ Delay:
2082 23:25:35.864868 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2083 23:25:35.868070 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2084 23:25:35.870691 DQ8 =80, DQ9 =80, DQ10 =96, DQ11 =88
2085 23:25:35.874378 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2086 23:25:35.874930
2087 23:25:35.875285
2088 23:25:35.880744 [DQSOSCAuto] RK1, (LSB)MR18= 0x430d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 393 ps
2089 23:25:35.884749 CH1 RK1: MR19=606, MR18=430D
2090 23:25:35.891127 CH1_RK1: MR19=0x606, MR18=0x430D, DQSOSC=393, MR23=63, INC=95, DEC=63
2091 23:25:35.894082 [RxdqsGatingPostProcess] freq 800
2092 23:25:35.897747 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2093 23:25:35.900724 Pre-setting of DQS Precalculation
2094 23:25:35.907927 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2095 23:25:35.914466 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2096 23:25:35.921350 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2097 23:25:35.921972
2098 23:25:35.922332
2099 23:25:35.924479 [Calibration Summary] 1600 Mbps
2100 23:25:35.924935 CH 0, Rank 0
2101 23:25:35.927733 SW Impedance : PASS
2102 23:25:35.931248 DUTY Scan : NO K
2103 23:25:35.931804 ZQ Calibration : PASS
2104 23:25:35.934238 Jitter Meter : NO K
2105 23:25:35.938173 CBT Training : PASS
2106 23:25:35.938730 Write leveling : PASS
2107 23:25:35.941109 RX DQS gating : PASS
2108 23:25:35.944836 RX DQ/DQS(RDDQC) : PASS
2109 23:25:35.945389 TX DQ/DQS : PASS
2110 23:25:35.947982 RX DATLAT : PASS
2111 23:25:35.951259 RX DQ/DQS(Engine): PASS
2112 23:25:35.951812 TX OE : NO K
2113 23:25:35.952173 All Pass.
2114 23:25:35.954419
2115 23:25:35.954875 CH 0, Rank 1
2116 23:25:35.957662 SW Impedance : PASS
2117 23:25:35.958116 DUTY Scan : NO K
2118 23:25:35.961035 ZQ Calibration : PASS
2119 23:25:35.961489 Jitter Meter : NO K
2120 23:25:35.964785 CBT Training : PASS
2121 23:25:35.967701 Write leveling : PASS
2122 23:25:35.968160 RX DQS gating : PASS
2123 23:25:35.971566 RX DQ/DQS(RDDQC) : PASS
2124 23:25:35.974328 TX DQ/DQS : PASS
2125 23:25:35.974888 RX DATLAT : PASS
2126 23:25:35.977573 RX DQ/DQS(Engine): PASS
2127 23:25:35.980727 TX OE : NO K
2128 23:25:35.981187 All Pass.
2129 23:25:35.981542
2130 23:25:35.981942 CH 1, Rank 0
2131 23:25:35.984556 SW Impedance : PASS
2132 23:25:35.987538 DUTY Scan : NO K
2133 23:25:35.987997 ZQ Calibration : PASS
2134 23:25:35.990836 Jitter Meter : NO K
2135 23:25:35.994205 CBT Training : PASS
2136 23:25:35.994685 Write leveling : PASS
2137 23:25:35.997815 RX DQS gating : PASS
2138 23:25:36.001230 RX DQ/DQS(RDDQC) : PASS
2139 23:25:36.001843 TX DQ/DQS : PASS
2140 23:25:36.004517 RX DATLAT : PASS
2141 23:25:36.005098 RX DQ/DQS(Engine): PASS
2142 23:25:36.008496 TX OE : NO K
2143 23:25:36.009065 All Pass.
2144 23:25:36.009660
2145 23:25:36.011176 CH 1, Rank 1
2146 23:25:36.011655 SW Impedance : PASS
2147 23:25:36.014486 DUTY Scan : NO K
2148 23:25:36.017705 ZQ Calibration : PASS
2149 23:25:36.018188 Jitter Meter : NO K
2150 23:25:36.021176 CBT Training : PASS
2151 23:25:36.024237 Write leveling : PASS
2152 23:25:36.024684 RX DQS gating : PASS
2153 23:25:36.027454 RX DQ/DQS(RDDQC) : PASS
2154 23:25:36.031054 TX DQ/DQS : PASS
2155 23:25:36.031583 RX DATLAT : PASS
2156 23:25:36.034979 RX DQ/DQS(Engine): PASS
2157 23:25:36.037875 TX OE : NO K
2158 23:25:36.038312 All Pass.
2159 23:25:36.038750
2160 23:25:36.039162 DramC Write-DBI off
2161 23:25:36.040968 PER_BANK_REFRESH: Hybrid Mode
2162 23:25:36.044389 TX_TRACKING: ON
2163 23:25:36.047787 [GetDramInforAfterCalByMRR] Vendor 6.
2164 23:25:36.051101 [GetDramInforAfterCalByMRR] Revision 606.
2165 23:25:36.054782 [GetDramInforAfterCalByMRR] Revision 2 0.
2166 23:25:36.055311 MR0 0x3b3b
2167 23:25:36.057648 MR8 0x5151
2168 23:25:36.060783 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2169 23:25:36.061219
2170 23:25:36.061765 MR0 0x3b3b
2171 23:25:36.062189 MR8 0x5151
2172 23:25:36.065020 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2173 23:25:36.065544
2174 23:25:36.074205 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2175 23:25:36.078045 [FAST_K] Save calibration result to emmc
2176 23:25:36.080773 [FAST_K] Save calibration result to emmc
2177 23:25:36.084581 dram_init: config_dvfs: 1
2178 23:25:36.087596 dramc_set_vcore_voltage set vcore to 662500
2179 23:25:36.091313 Read voltage for 1200, 2
2180 23:25:36.091840 Vio18 = 0
2181 23:25:36.092284 Vcore = 662500
2182 23:25:36.094346 Vdram = 0
2183 23:25:36.094780 Vddq = 0
2184 23:25:36.095272 Vmddr = 0
2185 23:25:36.100891 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2186 23:25:36.104306 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2187 23:25:36.107802 MEM_TYPE=3, freq_sel=15
2188 23:25:36.110904 sv_algorithm_assistance_LP4_1600
2189 23:25:36.114277 ============ PULL DRAM RESETB DOWN ============
2190 23:25:36.120947 ========== PULL DRAM RESETB DOWN end =========
2191 23:25:36.124395 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2192 23:25:36.127636 ===================================
2193 23:25:36.131451 LPDDR4 DRAM CONFIGURATION
2194 23:25:36.134802 ===================================
2195 23:25:36.135321 EX_ROW_EN[0] = 0x0
2196 23:25:36.138254 EX_ROW_EN[1] = 0x0
2197 23:25:36.138774 LP4Y_EN = 0x0
2198 23:25:36.141181 WORK_FSP = 0x0
2199 23:25:36.141760 WL = 0x4
2200 23:25:36.144974 RL = 0x4
2201 23:25:36.145486 BL = 0x2
2202 23:25:36.147915 RPST = 0x0
2203 23:25:36.148429 RD_PRE = 0x0
2204 23:25:36.151033 WR_PRE = 0x1
2205 23:25:36.151550 WR_PST = 0x0
2206 23:25:36.154722 DBI_WR = 0x0
2207 23:25:36.155236 DBI_RD = 0x0
2208 23:25:36.157875 OTF = 0x1
2209 23:25:36.161703 ===================================
2210 23:25:36.164599 ===================================
2211 23:25:36.165114 ANA top config
2212 23:25:36.167922 ===================================
2213 23:25:36.171332 DLL_ASYNC_EN = 0
2214 23:25:36.174345 ALL_SLAVE_EN = 0
2215 23:25:36.177839 NEW_RANK_MODE = 1
2216 23:25:36.178357 DLL_IDLE_MODE = 1
2217 23:25:36.181059 LP45_APHY_COMB_EN = 1
2218 23:25:36.184355 TX_ODT_DIS = 1
2219 23:25:36.187761 NEW_8X_MODE = 1
2220 23:25:36.191523 ===================================
2221 23:25:36.194844 ===================================
2222 23:25:36.197742 data_rate = 2400
2223 23:25:36.198201 CKR = 1
2224 23:25:36.200878 DQ_P2S_RATIO = 8
2225 23:25:36.204438 ===================================
2226 23:25:36.207799 CA_P2S_RATIO = 8
2227 23:25:36.211158 DQ_CA_OPEN = 0
2228 23:25:36.214913 DQ_SEMI_OPEN = 0
2229 23:25:36.217698 CA_SEMI_OPEN = 0
2230 23:25:36.218180 CA_FULL_RATE = 0
2231 23:25:36.221530 DQ_CKDIV4_EN = 0
2232 23:25:36.224505 CA_CKDIV4_EN = 0
2233 23:25:36.227624 CA_PREDIV_EN = 0
2234 23:25:36.231344 PH8_DLY = 17
2235 23:25:36.231961 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2236 23:25:36.235056 DQ_AAMCK_DIV = 4
2237 23:25:36.238538 CA_AAMCK_DIV = 4
2238 23:25:36.241207 CA_ADMCK_DIV = 4
2239 23:25:36.244821 DQ_TRACK_CA_EN = 0
2240 23:25:36.248246 CA_PICK = 1200
2241 23:25:36.251467 CA_MCKIO = 1200
2242 23:25:36.252025 MCKIO_SEMI = 0
2243 23:25:36.255276 PLL_FREQ = 2366
2244 23:25:36.258002 DQ_UI_PI_RATIO = 32
2245 23:25:36.261720 CA_UI_PI_RATIO = 0
2246 23:25:36.264680 ===================================
2247 23:25:36.268234 ===================================
2248 23:25:36.271894 memory_type:LPDDR4
2249 23:25:36.272445 GP_NUM : 10
2250 23:25:36.274471 SRAM_EN : 1
2251 23:25:36.278085 MD32_EN : 0
2252 23:25:36.281476 ===================================
2253 23:25:36.281967 [ANA_INIT] >>>>>>>>>>>>>>
2254 23:25:36.284778 <<<<<< [CONFIGURE PHASE]: ANA_TX
2255 23:25:36.288337 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2256 23:25:36.291785 ===================================
2257 23:25:36.294932 data_rate = 2400,PCW = 0X5b00
2258 23:25:36.297970 ===================================
2259 23:25:36.301124 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2260 23:25:36.308047 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2261 23:25:36.311678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2262 23:25:36.318577 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2263 23:25:36.321322 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2264 23:25:36.324951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2265 23:25:36.325611 [ANA_INIT] flow start
2266 23:25:36.328134 [ANA_INIT] PLL >>>>>>>>
2267 23:25:36.331535 [ANA_INIT] PLL <<<<<<<<
2268 23:25:36.332086 [ANA_INIT] MIDPI >>>>>>>>
2269 23:25:36.335035 [ANA_INIT] MIDPI <<<<<<<<
2270 23:25:36.337882 [ANA_INIT] DLL >>>>>>>>
2271 23:25:36.338429 [ANA_INIT] DLL <<<<<<<<
2272 23:25:36.341430 [ANA_INIT] flow end
2273 23:25:36.344937 ============ LP4 DIFF to SE enter ============
2274 23:25:36.348336 ============ LP4 DIFF to SE exit ============
2275 23:25:36.351627 [ANA_INIT] <<<<<<<<<<<<<
2276 23:25:36.354640 [Flow] Enable top DCM control >>>>>
2277 23:25:36.358572 [Flow] Enable top DCM control <<<<<
2278 23:25:36.361741 Enable DLL master slave shuffle
2279 23:25:36.368677 ==============================================================
2280 23:25:36.369231 Gating Mode config
2281 23:25:36.375227 ==============================================================
2282 23:25:36.375787 Config description:
2283 23:25:36.384982 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2284 23:25:36.391752 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2285 23:25:36.398496 SELPH_MODE 0: By rank 1: By Phase
2286 23:25:36.401254 ==============================================================
2287 23:25:36.404553 GAT_TRACK_EN = 1
2288 23:25:36.408525 RX_GATING_MODE = 2
2289 23:25:36.411461 RX_GATING_TRACK_MODE = 2
2290 23:25:36.415427 SELPH_MODE = 1
2291 23:25:36.418336 PICG_EARLY_EN = 1
2292 23:25:36.421645 VALID_LAT_VALUE = 1
2293 23:25:36.424858 ==============================================================
2294 23:25:36.431895 Enter into Gating configuration >>>>
2295 23:25:36.435209 Exit from Gating configuration <<<<
2296 23:25:36.435763 Enter into DVFS_PRE_config >>>>>
2297 23:25:36.448590 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2298 23:25:36.451617 Exit from DVFS_PRE_config <<<<<
2299 23:25:36.454912 Enter into PICG configuration >>>>
2300 23:25:36.457940 Exit from PICG configuration <<<<
2301 23:25:36.458438 [RX_INPUT] configuration >>>>>
2302 23:25:36.461328 [RX_INPUT] configuration <<<<<
2303 23:25:36.468274 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2304 23:25:36.471820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2305 23:25:36.478576 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2306 23:25:36.484774 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2307 23:25:36.491508 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2308 23:25:36.498084 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2309 23:25:36.501280 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2310 23:25:36.504919 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2311 23:25:36.508602 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2312 23:25:36.514606 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2313 23:25:36.518285 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2314 23:25:36.521917 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2315 23:25:36.524978 ===================================
2316 23:25:36.528132 LPDDR4 DRAM CONFIGURATION
2317 23:25:36.531680 ===================================
2318 23:25:36.534988 EX_ROW_EN[0] = 0x0
2319 23:25:36.535563 EX_ROW_EN[1] = 0x0
2320 23:25:36.537904 LP4Y_EN = 0x0
2321 23:25:36.538364 WORK_FSP = 0x0
2322 23:25:36.541352 WL = 0x4
2323 23:25:36.542214 RL = 0x4
2324 23:25:36.545300 BL = 0x2
2325 23:25:36.545913 RPST = 0x0
2326 23:25:36.548206 RD_PRE = 0x0
2327 23:25:36.548761 WR_PRE = 0x1
2328 23:25:36.552019 WR_PST = 0x0
2329 23:25:36.552572 DBI_WR = 0x0
2330 23:25:36.554554 DBI_RD = 0x0
2331 23:25:36.555013 OTF = 0x1
2332 23:25:36.557866 ===================================
2333 23:25:36.561216 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2334 23:25:36.568198 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2335 23:25:36.571824 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2336 23:25:36.575202 ===================================
2337 23:25:36.577896 LPDDR4 DRAM CONFIGURATION
2338 23:25:36.581530 ===================================
2339 23:25:36.582086 EX_ROW_EN[0] = 0x10
2340 23:25:36.584658 EX_ROW_EN[1] = 0x0
2341 23:25:36.588537 LP4Y_EN = 0x0
2342 23:25:36.588990 WORK_FSP = 0x0
2343 23:25:36.591559 WL = 0x4
2344 23:25:36.592090 RL = 0x4
2345 23:25:36.594861 BL = 0x2
2346 23:25:36.595316 RPST = 0x0
2347 23:25:36.598111 RD_PRE = 0x0
2348 23:25:36.598553 WR_PRE = 0x1
2349 23:25:36.601291 WR_PST = 0x0
2350 23:25:36.601911 DBI_WR = 0x0
2351 23:25:36.605346 DBI_RD = 0x0
2352 23:25:36.606073 OTF = 0x1
2353 23:25:36.608260 ===================================
2354 23:25:36.615293 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2355 23:25:36.615722 ==
2356 23:25:36.618467 Dram Type= 6, Freq= 0, CH_0, rank 0
2357 23:25:36.621438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2358 23:25:36.621904 ==
2359 23:25:36.624730 [Duty_Offset_Calibration]
2360 23:25:36.628061 B0:2 B1:1 CA:1
2361 23:25:36.628467
2362 23:25:36.631192 [DutyScan_Calibration_Flow] k_type=0
2363 23:25:36.639185
2364 23:25:36.639588 ==CLK 0==
2365 23:25:36.642860 Final CLK duty delay cell = 0
2366 23:25:36.646246 [0] MAX Duty = 5187%(X100), DQS PI = 24
2367 23:25:36.649519 [0] MIN Duty = 4875%(X100), DQS PI = 0
2368 23:25:36.650079 [0] AVG Duty = 5031%(X100)
2369 23:25:36.650401
2370 23:25:36.652687 CH0 CLK Duty spec in!! Max-Min= 312%
2371 23:25:36.659562 [DutyScan_Calibration_Flow] ====Done====
2372 23:25:36.659971
2373 23:25:36.663146 [DutyScan_Calibration_Flow] k_type=1
2374 23:25:36.678071
2375 23:25:36.678579 ==DQS 0 ==
2376 23:25:36.681176 Final DQS duty delay cell = -4
2377 23:25:36.684438 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2378 23:25:36.688632 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2379 23:25:36.691576 [-4] AVG Duty = 4937%(X100)
2380 23:25:36.691994
2381 23:25:36.692325 ==DQS 1 ==
2382 23:25:36.694622 Final DQS duty delay cell = 0
2383 23:25:36.697891 [0] MAX Duty = 5187%(X100), DQS PI = 0
2384 23:25:36.701872 [0] MIN Duty = 5000%(X100), DQS PI = 36
2385 23:25:36.704802 [0] AVG Duty = 5093%(X100)
2386 23:25:36.705450
2387 23:25:36.708405 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2388 23:25:36.708816
2389 23:25:36.711737 CH0 DQS 1 Duty spec in!! Max-Min= 187%
2390 23:25:36.714534 [DutyScan_Calibration_Flow] ====Done====
2391 23:25:36.714991
2392 23:25:36.718333 [DutyScan_Calibration_Flow] k_type=3
2393 23:25:36.735144
2394 23:25:36.735688 ==DQM 0 ==
2395 23:25:36.738335 Final DQM duty delay cell = 0
2396 23:25:36.741410 [0] MAX Duty = 5156%(X100), DQS PI = 30
2397 23:25:36.744797 [0] MIN Duty = 4906%(X100), DQS PI = 50
2398 23:25:36.745364 [0] AVG Duty = 5031%(X100)
2399 23:25:36.748216
2400 23:25:36.748758 ==DQM 1 ==
2401 23:25:36.751688 Final DQM duty delay cell = 0
2402 23:25:36.755011 [0] MAX Duty = 5156%(X100), DQS PI = 60
2403 23:25:36.758079 [0] MIN Duty = 5031%(X100), DQS PI = 34
2404 23:25:36.758550 [0] AVG Duty = 5093%(X100)
2405 23:25:36.761735
2406 23:25:36.765376 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2407 23:25:36.765971
2408 23:25:36.768463 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2409 23:25:36.771779 [DutyScan_Calibration_Flow] ====Done====
2410 23:25:36.772326
2411 23:25:36.774770 [DutyScan_Calibration_Flow] k_type=2
2412 23:25:36.791366
2413 23:25:36.791905 ==DQ 0 ==
2414 23:25:36.794841 Final DQ duty delay cell = 0
2415 23:25:36.798176 [0] MAX Duty = 5031%(X100), DQS PI = 26
2416 23:25:36.801748 [0] MIN Duty = 4875%(X100), DQS PI = 62
2417 23:25:36.802321 [0] AVG Duty = 4953%(X100)
2418 23:25:36.802677
2419 23:25:36.804793 ==DQ 1 ==
2420 23:25:36.808305 Final DQ duty delay cell = 0
2421 23:25:36.811572 [0] MAX Duty = 5093%(X100), DQS PI = 24
2422 23:25:36.814689 [0] MIN Duty = 4938%(X100), DQS PI = 36
2423 23:25:36.815147 [0] AVG Duty = 5015%(X100)
2424 23:25:36.815504
2425 23:25:36.817882 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2426 23:25:36.821530
2427 23:25:36.824955 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2428 23:25:36.828575 [DutyScan_Calibration_Flow] ====Done====
2429 23:25:36.829132 ==
2430 23:25:36.832056 Dram Type= 6, Freq= 0, CH_1, rank 0
2431 23:25:36.834654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2432 23:25:36.835114 ==
2433 23:25:36.838718 [Duty_Offset_Calibration]
2434 23:25:36.839268 B0:1 B1:0 CA:0
2435 23:25:36.839627
2436 23:25:36.841864 [DutyScan_Calibration_Flow] k_type=0
2437 23:25:36.850966
2438 23:25:36.851513 ==CLK 0==
2439 23:25:36.854221 Final CLK duty delay cell = -4
2440 23:25:36.857295 [-4] MAX Duty = 5000%(X100), DQS PI = 18
2441 23:25:36.860345 [-4] MIN Duty = 4907%(X100), DQS PI = 48
2442 23:25:36.864433 [-4] AVG Duty = 4953%(X100)
2443 23:25:36.864984
2444 23:25:36.867464 CH1 CLK Duty spec in!! Max-Min= 93%
2445 23:25:36.870937 [DutyScan_Calibration_Flow] ====Done====
2446 23:25:36.871491
2447 23:25:36.874406 [DutyScan_Calibration_Flow] k_type=1
2448 23:25:36.890413
2449 23:25:36.890971 ==DQS 0 ==
2450 23:25:36.893622 Final DQS duty delay cell = 0
2451 23:25:36.897042 [0] MAX Duty = 5062%(X100), DQS PI = 14
2452 23:25:36.900189 [0] MIN Duty = 4875%(X100), DQS PI = 0
2453 23:25:36.900743 [0] AVG Duty = 4968%(X100)
2454 23:25:36.903902
2455 23:25:36.904462 ==DQS 1 ==
2456 23:25:36.907320 Final DQS duty delay cell = 0
2457 23:25:36.910331 [0] MAX Duty = 5187%(X100), DQS PI = 20
2458 23:25:36.913889 [0] MIN Duty = 4969%(X100), DQS PI = 8
2459 23:25:36.914444 [0] AVG Duty = 5078%(X100)
2460 23:25:36.914800
2461 23:25:36.920286 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2462 23:25:36.920887
2463 23:25:36.923965 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2464 23:25:36.927527 [DutyScan_Calibration_Flow] ====Done====
2465 23:25:36.928007
2466 23:25:36.930043 [DutyScan_Calibration_Flow] k_type=3
2467 23:25:36.947124
2468 23:25:36.947678 ==DQM 0 ==
2469 23:25:36.950117 Final DQM duty delay cell = 0
2470 23:25:36.953746 [0] MAX Duty = 5156%(X100), DQS PI = 6
2471 23:25:36.957157 [0] MIN Duty = 5031%(X100), DQS PI = 0
2472 23:25:36.957765 [0] AVG Duty = 5093%(X100)
2473 23:25:36.958136
2474 23:25:36.960311 ==DQM 1 ==
2475 23:25:36.963636 Final DQM duty delay cell = 0
2476 23:25:36.966925 [0] MAX Duty = 5031%(X100), DQS PI = 16
2477 23:25:36.970198 [0] MIN Duty = 4907%(X100), DQS PI = 36
2478 23:25:36.970658 [0] AVG Duty = 4969%(X100)
2479 23:25:36.971016
2480 23:25:36.973685 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2481 23:25:36.977228
2482 23:25:36.980142 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2483 23:25:36.983735 [DutyScan_Calibration_Flow] ====Done====
2484 23:25:36.984286
2485 23:25:36.987058 [DutyScan_Calibration_Flow] k_type=2
2486 23:25:37.002619
2487 23:25:37.003170 ==DQ 0 ==
2488 23:25:37.006239 Final DQ duty delay cell = -4
2489 23:25:37.009333 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2490 23:25:37.013127 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2491 23:25:37.015851 [-4] AVG Duty = 5000%(X100)
2492 23:25:37.016312
2493 23:25:37.016666 ==DQ 1 ==
2494 23:25:37.019123 Final DQ duty delay cell = 0
2495 23:25:37.022972 [0] MAX Duty = 5125%(X100), DQS PI = 20
2496 23:25:37.026082 [0] MIN Duty = 4969%(X100), DQS PI = 12
2497 23:25:37.026568 [0] AVG Duty = 5047%(X100)
2498 23:25:37.029145
2499 23:25:37.032657 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2500 23:25:37.033208
2501 23:25:37.035626 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2502 23:25:37.039021 [DutyScan_Calibration_Flow] ====Done====
2503 23:25:37.042647 nWR fixed to 30
2504 23:25:37.043103 [ModeRegInit_LP4] CH0 RK0
2505 23:25:37.046127 [ModeRegInit_LP4] CH0 RK1
2506 23:25:37.049098 [ModeRegInit_LP4] CH1 RK0
2507 23:25:37.049552 [ModeRegInit_LP4] CH1 RK1
2508 23:25:37.052922 match AC timing 7
2509 23:25:37.056199 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2510 23:25:37.059204 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2511 23:25:37.066159 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2512 23:25:37.069368 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2513 23:25:37.076310 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2514 23:25:37.076892 ==
2515 23:25:37.079466 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 23:25:37.082771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 23:25:37.083330 ==
2518 23:25:37.089256 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2519 23:25:37.093004 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2520 23:25:37.102591 [CA 0] Center 39 (8~70) winsize 63
2521 23:25:37.106585 [CA 1] Center 39 (8~70) winsize 63
2522 23:25:37.109467 [CA 2] Center 35 (5~66) winsize 62
2523 23:25:37.112673 [CA 3] Center 34 (4~65) winsize 62
2524 23:25:37.116261 [CA 4] Center 33 (3~64) winsize 62
2525 23:25:37.119533 [CA 5] Center 32 (3~62) winsize 60
2526 23:25:37.120089
2527 23:25:37.122802 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2528 23:25:37.123357
2529 23:25:37.125938 [CATrainingPosCal] consider 1 rank data
2530 23:25:37.129492 u2DelayCellTimex100 = 270/100 ps
2531 23:25:37.132860 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2532 23:25:37.135969 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2533 23:25:37.142647 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2534 23:25:37.145967 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2535 23:25:37.149678 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2536 23:25:37.153143 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2537 23:25:37.153743
2538 23:25:37.156784 CA PerBit enable=1, Macro0, CA PI delay=32
2539 23:25:37.157238
2540 23:25:37.159596 [CBTSetCACLKResult] CA Dly = 32
2541 23:25:37.160055 CS Dly: 6 (0~37)
2542 23:25:37.160409 ==
2543 23:25:37.162844 Dram Type= 6, Freq= 0, CH_0, rank 1
2544 23:25:37.169687 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2545 23:25:37.170248 ==
2546 23:25:37.172520 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2547 23:25:37.179101 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2548 23:25:37.188407 [CA 0] Center 38 (8~69) winsize 62
2549 23:25:37.191899 [CA 1] Center 38 (8~69) winsize 62
2550 23:25:37.195448 [CA 2] Center 35 (4~66) winsize 63
2551 23:25:37.198374 [CA 3] Center 34 (4~65) winsize 62
2552 23:25:37.202055 [CA 4] Center 33 (3~64) winsize 62
2553 23:25:37.205160 [CA 5] Center 32 (3~62) winsize 60
2554 23:25:37.205642
2555 23:25:37.208541 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2556 23:25:37.208997
2557 23:25:37.211797 [CATrainingPosCal] consider 2 rank data
2558 23:25:37.215166 u2DelayCellTimex100 = 270/100 ps
2559 23:25:37.218512 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2560 23:25:37.222144 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2561 23:25:37.228590 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2562 23:25:37.232412 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2563 23:25:37.235130 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2564 23:25:37.238641 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2565 23:25:37.239200
2566 23:25:37.242083 CA PerBit enable=1, Macro0, CA PI delay=32
2567 23:25:37.242678
2568 23:25:37.244977 [CBTSetCACLKResult] CA Dly = 32
2569 23:25:37.245432 CS Dly: 6 (0~38)
2570 23:25:37.245833
2571 23:25:37.248770 ----->DramcWriteLeveling(PI) begin...
2572 23:25:37.252109 ==
2573 23:25:37.252659 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 23:25:37.258357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 23:25:37.258904 ==
2576 23:25:37.261642 Write leveling (Byte 0): 32 => 32
2577 23:25:37.265166 Write leveling (Byte 1): 30 => 30
2578 23:25:37.265760 DramcWriteLeveling(PI) end<-----
2579 23:25:37.268721
2580 23:25:37.269272 ==
2581 23:25:37.271716 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 23:25:37.275201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 23:25:37.275759 ==
2584 23:25:37.278547 [Gating] SW mode calibration
2585 23:25:37.285383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2586 23:25:37.288586 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2587 23:25:37.295650 0 15 0 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
2588 23:25:37.298954 0 15 4 | B1->B0 | 3333 3434 | 1 1 | (0 0) (1 1)
2589 23:25:37.301795 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2590 23:25:37.308390 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2591 23:25:37.312523 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2592 23:25:37.315369 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2593 23:25:37.322452 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2594 23:25:37.325701 0 15 28 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
2595 23:25:37.328823 1 0 0 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
2596 23:25:37.335761 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2597 23:25:37.339217 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2598 23:25:37.342589 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2599 23:25:37.345480 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2600 23:25:37.352141 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2601 23:25:37.355232 1 0 24 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
2602 23:25:37.358982 1 0 28 | B1->B0 | 2626 4545 | 0 0 | (0 0) (0 0)
2603 23:25:37.365246 1 1 0 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
2604 23:25:37.369369 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2605 23:25:37.372666 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 23:25:37.379330 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2607 23:25:37.382256 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2608 23:25:37.386259 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2609 23:25:37.392055 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2610 23:25:37.395599 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2611 23:25:37.399161 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2612 23:25:37.405714 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 23:25:37.408743 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 23:25:37.412560 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 23:25:37.419213 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 23:25:37.422432 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 23:25:37.425869 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 23:25:37.429457 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 23:25:37.435802 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:25:37.439538 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:25:37.442369 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:25:37.449457 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:25:37.452542 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:25:37.456113 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:25:37.462683 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:25:37.465650 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2627 23:25:37.468891 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2628 23:25:37.472291 Total UI for P1: 0, mck2ui 16
2629 23:25:37.476334 best dqsien dly found for B0: ( 1, 3, 28)
2630 23:25:37.482313 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2631 23:25:37.482866 Total UI for P1: 0, mck2ui 16
2632 23:25:37.486007 best dqsien dly found for B1: ( 1, 4, 0)
2633 23:25:37.492444 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2634 23:25:37.495722 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2635 23:25:37.496219
2636 23:25:37.499551 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2637 23:25:37.502707 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2638 23:25:37.505830 [Gating] SW calibration Done
2639 23:25:37.506285 ==
2640 23:25:37.509239 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 23:25:37.512454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 23:25:37.513015 ==
2643 23:25:37.513371 RX Vref Scan: 0
2644 23:25:37.515653
2645 23:25:37.516229 RX Vref 0 -> 0, step: 1
2646 23:25:37.516707
2647 23:25:37.519192 RX Delay -40 -> 252, step: 8
2648 23:25:37.523002 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2649 23:25:37.526206 iDelay=200, Bit 1, Center 127 (56 ~ 199) 144
2650 23:25:37.532610 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2651 23:25:37.535979 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2652 23:25:37.539376 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2653 23:25:37.542871 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2654 23:25:37.545995 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2655 23:25:37.552689 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2656 23:25:37.555969 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2657 23:25:37.559093 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2658 23:25:37.562126 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2659 23:25:37.566131 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2660 23:25:37.573007 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2661 23:25:37.576052 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2662 23:25:37.579392 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2663 23:25:37.582303 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2664 23:25:37.582761 ==
2665 23:25:37.586235 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 23:25:37.592357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 23:25:37.592816 ==
2668 23:25:37.593172 DQS Delay:
2669 23:25:37.593500 DQS0 = 0, DQS1 = 0
2670 23:25:37.595564 DQM Delay:
2671 23:25:37.596019 DQM0 = 122, DQM1 = 113
2672 23:25:37.599104 DQ Delay:
2673 23:25:37.602263 DQ0 =119, DQ1 =127, DQ2 =119, DQ3 =119
2674 23:25:37.605688 DQ4 =123, DQ5 =115, DQ6 =127, DQ7 =127
2675 23:25:37.609301 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2676 23:25:37.612802 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2677 23:25:37.613367
2678 23:25:37.613785
2679 23:25:37.614357 ==
2680 23:25:37.615726 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 23:25:37.619344 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 23:25:37.619805 ==
2683 23:25:37.620161
2684 23:25:37.622742
2685 23:25:37.623201 TX Vref Scan disable
2686 23:25:37.625983 == TX Byte 0 ==
2687 23:25:37.629489 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2688 23:25:37.632385 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2689 23:25:37.635836 == TX Byte 1 ==
2690 23:25:37.639250 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2691 23:25:37.642377 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2692 23:25:37.642947 ==
2693 23:25:37.645748 Dram Type= 6, Freq= 0, CH_0, rank 0
2694 23:25:37.652804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2695 23:25:37.653322 ==
2696 23:25:37.662918 TX Vref=22, minBit 14, minWin=24, winSum=407
2697 23:25:37.666397 TX Vref=24, minBit 0, minWin=25, winSum=412
2698 23:25:37.669616 TX Vref=26, minBit 12, minWin=25, winSum=418
2699 23:25:37.673085 TX Vref=28, minBit 10, minWin=25, winSum=425
2700 23:25:37.676601 TX Vref=30, minBit 12, minWin=25, winSum=425
2701 23:25:37.682711 TX Vref=32, minBit 0, minWin=26, winSum=421
2702 23:25:37.686452 [TxChooseVref] Worse bit 0, Min win 26, Win sum 421, Final Vref 32
2703 23:25:37.686936
2704 23:25:37.689647 Final TX Range 1 Vref 32
2705 23:25:37.690108
2706 23:25:37.690461 ==
2707 23:25:37.693120 Dram Type= 6, Freq= 0, CH_0, rank 0
2708 23:25:37.696290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2709 23:25:37.700177 ==
2710 23:25:37.700736
2711 23:25:37.701092
2712 23:25:37.701421 TX Vref Scan disable
2713 23:25:37.702843 == TX Byte 0 ==
2714 23:25:37.706827 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2715 23:25:37.709629 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2716 23:25:37.713250 == TX Byte 1 ==
2717 23:25:37.716526 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2718 23:25:37.719770 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2719 23:25:37.723286
2720 23:25:37.723841 [DATLAT]
2721 23:25:37.724198 Freq=1200, CH0 RK0
2722 23:25:37.724528
2723 23:25:37.726429 DATLAT Default: 0xd
2724 23:25:37.726882 0, 0xFFFF, sum = 0
2725 23:25:37.729844 1, 0xFFFF, sum = 0
2726 23:25:37.730305 2, 0xFFFF, sum = 0
2727 23:25:37.733630 3, 0xFFFF, sum = 0
2728 23:25:37.734201 4, 0xFFFF, sum = 0
2729 23:25:37.736624 5, 0xFFFF, sum = 0
2730 23:25:37.739551 6, 0xFFFF, sum = 0
2731 23:25:37.740016 7, 0xFFFF, sum = 0
2732 23:25:37.742974 8, 0xFFFF, sum = 0
2733 23:25:37.743438 9, 0xFFFF, sum = 0
2734 23:25:37.746425 10, 0xFFFF, sum = 0
2735 23:25:37.746890 11, 0xFFFF, sum = 0
2736 23:25:37.750034 12, 0x0, sum = 1
2737 23:25:37.750595 13, 0x0, sum = 2
2738 23:25:37.753235 14, 0x0, sum = 3
2739 23:25:37.753836 15, 0x0, sum = 4
2740 23:25:37.754203 best_step = 13
2741 23:25:37.754534
2742 23:25:37.756591 ==
2743 23:25:37.760319 Dram Type= 6, Freq= 0, CH_0, rank 0
2744 23:25:37.763202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2745 23:25:37.763764 ==
2746 23:25:37.764124 RX Vref Scan: 1
2747 23:25:37.764455
2748 23:25:37.766336 Set Vref Range= 32 -> 127
2749 23:25:37.766793
2750 23:25:37.770302 RX Vref 32 -> 127, step: 1
2751 23:25:37.770859
2752 23:25:37.773318 RX Delay -13 -> 252, step: 4
2753 23:25:37.773902
2754 23:25:37.776802 Set Vref, RX VrefLevel [Byte0]: 32
2755 23:25:37.780004 [Byte1]: 32
2756 23:25:37.780561
2757 23:25:37.782715 Set Vref, RX VrefLevel [Byte0]: 33
2758 23:25:37.786563 [Byte1]: 33
2759 23:25:37.787114
2760 23:25:37.789691 Set Vref, RX VrefLevel [Byte0]: 34
2761 23:25:37.792906 [Byte1]: 34
2762 23:25:37.796954
2763 23:25:37.797411 Set Vref, RX VrefLevel [Byte0]: 35
2764 23:25:37.800929 [Byte1]: 35
2765 23:25:37.805077
2766 23:25:37.805559 Set Vref, RX VrefLevel [Byte0]: 36
2767 23:25:37.808282 [Byte1]: 36
2768 23:25:37.813488
2769 23:25:37.813996 Set Vref, RX VrefLevel [Byte0]: 37
2770 23:25:37.816630 [Byte1]: 37
2771 23:25:37.820964
2772 23:25:37.821511 Set Vref, RX VrefLevel [Byte0]: 38
2773 23:25:37.824214 [Byte1]: 38
2774 23:25:37.828820
2775 23:25:37.829275 Set Vref, RX VrefLevel [Byte0]: 39
2776 23:25:37.832158 [Byte1]: 39
2777 23:25:37.836782
2778 23:25:37.837326 Set Vref, RX VrefLevel [Byte0]: 40
2779 23:25:37.840300 [Byte1]: 40
2780 23:25:37.845199
2781 23:25:37.845797 Set Vref, RX VrefLevel [Byte0]: 41
2782 23:25:37.847666 [Byte1]: 41
2783 23:25:37.852693
2784 23:25:37.853238 Set Vref, RX VrefLevel [Byte0]: 42
2785 23:25:37.855835 [Byte1]: 42
2786 23:25:37.860570
2787 23:25:37.861214 Set Vref, RX VrefLevel [Byte0]: 43
2788 23:25:37.863794 [Byte1]: 43
2789 23:25:37.868508
2790 23:25:37.869053 Set Vref, RX VrefLevel [Byte0]: 44
2791 23:25:37.871488 [Byte1]: 44
2792 23:25:37.876455
2793 23:25:37.876998 Set Vref, RX VrefLevel [Byte0]: 45
2794 23:25:37.879677 [Byte1]: 45
2795 23:25:37.884062
2796 23:25:37.884606 Set Vref, RX VrefLevel [Byte0]: 46
2797 23:25:37.887789 [Byte1]: 46
2798 23:25:37.892066
2799 23:25:37.892648 Set Vref, RX VrefLevel [Byte0]: 47
2800 23:25:37.895571 [Byte1]: 47
2801 23:25:37.900217
2802 23:25:37.900763 Set Vref, RX VrefLevel [Byte0]: 48
2803 23:25:37.903029 [Byte1]: 48
2804 23:25:37.907699
2805 23:25:37.908247 Set Vref, RX VrefLevel [Byte0]: 49
2806 23:25:37.911019 [Byte1]: 49
2807 23:25:37.915990
2808 23:25:37.916540 Set Vref, RX VrefLevel [Byte0]: 50
2809 23:25:37.919039 [Byte1]: 50
2810 23:25:37.924036
2811 23:25:37.924583 Set Vref, RX VrefLevel [Byte0]: 51
2812 23:25:37.926775 [Byte1]: 51
2813 23:25:37.931363
2814 23:25:37.931817 Set Vref, RX VrefLevel [Byte0]: 52
2815 23:25:37.934789 [Byte1]: 52
2816 23:25:37.939257
2817 23:25:37.939803 Set Vref, RX VrefLevel [Byte0]: 53
2818 23:25:37.945749 [Byte1]: 53
2819 23:25:37.946299
2820 23:25:37.948823 Set Vref, RX VrefLevel [Byte0]: 54
2821 23:25:37.952671 [Byte1]: 54
2822 23:25:37.953222
2823 23:25:37.955634 Set Vref, RX VrefLevel [Byte0]: 55
2824 23:25:37.958628 [Byte1]: 55
2825 23:25:37.963013
2826 23:25:37.963468 Set Vref, RX VrefLevel [Byte0]: 56
2827 23:25:37.966452 [Byte1]: 56
2828 23:25:37.971506
2829 23:25:37.972057 Set Vref, RX VrefLevel [Byte0]: 57
2830 23:25:37.974368 [Byte1]: 57
2831 23:25:37.979101
2832 23:25:37.979651 Set Vref, RX VrefLevel [Byte0]: 58
2833 23:25:37.982147 [Byte1]: 58
2834 23:25:37.987585
2835 23:25:37.988136 Set Vref, RX VrefLevel [Byte0]: 59
2836 23:25:37.990409 [Byte1]: 59
2837 23:25:37.994612
2838 23:25:37.995065 Set Vref, RX VrefLevel [Byte0]: 60
2839 23:25:37.998386 [Byte1]: 60
2840 23:25:38.002400
2841 23:25:38.002953 Set Vref, RX VrefLevel [Byte0]: 61
2842 23:25:38.005814 [Byte1]: 61
2843 23:25:38.010540
2844 23:25:38.011089 Set Vref, RX VrefLevel [Byte0]: 62
2845 23:25:38.013525 [Byte1]: 62
2846 23:25:38.018809
2847 23:25:38.019358 Set Vref, RX VrefLevel [Byte0]: 63
2848 23:25:38.021703 [Byte1]: 63
2849 23:25:38.026396
2850 23:25:38.026951 Set Vref, RX VrefLevel [Byte0]: 64
2851 23:25:38.029128 [Byte1]: 64
2852 23:25:38.033736
2853 23:25:38.034193 Set Vref, RX VrefLevel [Byte0]: 65
2854 23:25:38.037674 [Byte1]: 65
2855 23:25:38.041923
2856 23:25:38.042469 Set Vref, RX VrefLevel [Byte0]: 66
2857 23:25:38.045164 [Byte1]: 66
2858 23:25:38.049953
2859 23:25:38.050502 Set Vref, RX VrefLevel [Byte0]: 67
2860 23:25:38.052850 [Byte1]: 67
2861 23:25:38.057889
2862 23:25:38.058515 Set Vref, RX VrefLevel [Byte0]: 68
2863 23:25:38.060918 [Byte1]: 68
2864 23:25:38.065276
2865 23:25:38.065757 Set Vref, RX VrefLevel [Byte0]: 69
2866 23:25:38.068905 [Byte1]: 69
2867 23:25:38.073521
2868 23:25:38.074120 Final RX Vref Byte 0 = 56 to rank0
2869 23:25:38.076670 Final RX Vref Byte 1 = 55 to rank0
2870 23:25:38.080814 Final RX Vref Byte 0 = 56 to rank1
2871 23:25:38.083548 Final RX Vref Byte 1 = 55 to rank1==
2872 23:25:38.087036 Dram Type= 6, Freq= 0, CH_0, rank 0
2873 23:25:38.090537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2874 23:25:38.094091 ==
2875 23:25:38.094552 DQS Delay:
2876 23:25:38.094912 DQS0 = 0, DQS1 = 0
2877 23:25:38.097172 DQM Delay:
2878 23:25:38.097789 DQM0 = 120, DQM1 = 113
2879 23:25:38.100694 DQ Delay:
2880 23:25:38.103962 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2881 23:25:38.107024 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2882 23:25:38.110592 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2883 23:25:38.113520 DQ12 =120, DQ13 =116, DQ14 =126, DQ15 =122
2884 23:25:38.114102
2885 23:25:38.114459
2886 23:25:38.120824 [DQSOSCAuto] RK0, (LSB)MR18= 0x150e, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2887 23:25:38.124150 CH0 RK0: MR19=404, MR18=150E
2888 23:25:38.130162 CH0_RK0: MR19=0x404, MR18=0x150E, DQSOSC=401, MR23=63, INC=40, DEC=27
2889 23:25:38.130622
2890 23:25:38.133455 ----->DramcWriteLeveling(PI) begin...
2891 23:25:38.133953 ==
2892 23:25:38.137107 Dram Type= 6, Freq= 0, CH_0, rank 1
2893 23:25:38.140350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 23:25:38.140910 ==
2895 23:25:38.143977 Write leveling (Byte 0): 38 => 38
2896 23:25:38.146869 Write leveling (Byte 1): 30 => 30
2897 23:25:38.150046 DramcWriteLeveling(PI) end<-----
2898 23:25:38.150503
2899 23:25:38.150854 ==
2900 23:25:38.153737 Dram Type= 6, Freq= 0, CH_0, rank 1
2901 23:25:38.160309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2902 23:25:38.160862 ==
2903 23:25:38.161221 [Gating] SW mode calibration
2904 23:25:38.170870 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2905 23:25:38.173986 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2906 23:25:38.177227 0 15 0 | B1->B0 | 3333 2f2f | 0 0 | (0 0) (1 1)
2907 23:25:38.183801 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2908 23:25:38.187770 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2909 23:25:38.191011 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2910 23:25:38.197236 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2911 23:25:38.201062 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2912 23:25:38.203582 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2913 23:25:38.210356 0 15 28 | B1->B0 | 3131 3232 | 0 0 | (0 1) (0 1)
2914 23:25:38.213959 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2915 23:25:38.217487 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2916 23:25:38.223927 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2917 23:25:38.227507 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2918 23:25:38.231047 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2919 23:25:38.233998 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2920 23:25:38.240730 1 0 24 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
2921 23:25:38.244417 1 0 28 | B1->B0 | 3c3c 3e3e | 0 1 | (0 0) (0 0)
2922 23:25:38.247275 1 1 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
2923 23:25:38.254154 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2924 23:25:38.257535 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2925 23:25:38.260757 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2926 23:25:38.267262 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2927 23:25:38.270797 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2928 23:25:38.274397 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 23:25:38.280625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2930 23:25:38.283974 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 23:25:38.287359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 23:25:38.293723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 23:25:38.297360 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 23:25:38.300255 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 23:25:38.307162 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 23:25:38.310737 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 23:25:38.313931 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 23:25:38.320593 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 23:25:38.323820 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2940 23:25:38.327109 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:25:38.333979 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:25:38.337264 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:25:38.340600 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:25:38.344317 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:25:38.350816 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2946 23:25:38.353951 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 23:25:38.357708 Total UI for P1: 0, mck2ui 16
2948 23:25:38.360322 best dqsien dly found for B0: ( 1, 3, 28)
2949 23:25:38.363857 Total UI for P1: 0, mck2ui 16
2950 23:25:38.367697 best dqsien dly found for B1: ( 1, 3, 28)
2951 23:25:38.370500 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2952 23:25:38.373758 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2953 23:25:38.374313
2954 23:25:38.377311 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2955 23:25:38.381084 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2956 23:25:38.383679 [Gating] SW calibration Done
2957 23:25:38.384176 ==
2958 23:25:38.387284 Dram Type= 6, Freq= 0, CH_0, rank 1
2959 23:25:38.390856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2960 23:25:38.393550 ==
2961 23:25:38.394057 RX Vref Scan: 0
2962 23:25:38.394413
2963 23:25:38.396919 RX Vref 0 -> 0, step: 1
2964 23:25:38.397372
2965 23:25:38.400247 RX Delay -40 -> 252, step: 8
2966 23:25:38.403688 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2967 23:25:38.407684 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2968 23:25:38.410228 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2969 23:25:38.413704 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2970 23:25:38.420916 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2971 23:25:38.424408 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2972 23:25:38.427494 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2973 23:25:38.430250 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2974 23:25:38.434068 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
2975 23:25:38.437449 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
2976 23:25:38.443993 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2977 23:25:38.447173 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2978 23:25:38.450486 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2979 23:25:38.454308 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2980 23:25:38.460473 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2981 23:25:38.463798 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2982 23:25:38.464255 ==
2983 23:25:38.467831 Dram Type= 6, Freq= 0, CH_0, rank 1
2984 23:25:38.470959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2985 23:25:38.471517 ==
2986 23:25:38.471879 DQS Delay:
2987 23:25:38.474247 DQS0 = 0, DQS1 = 0
2988 23:25:38.474801 DQM Delay:
2989 23:25:38.477659 DQM0 = 122, DQM1 = 113
2990 23:25:38.478215 DQ Delay:
2991 23:25:38.481020 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2992 23:25:38.484237 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2993 23:25:38.487645 DQ8 =103, DQ9 =99, DQ10 =115, DQ11 =107
2994 23:25:38.491001 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2995 23:25:38.491558
2996 23:25:38.494565
2997 23:25:38.495118 ==
2998 23:25:38.497463 Dram Type= 6, Freq= 0, CH_0, rank 1
2999 23:25:38.500739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3000 23:25:38.501197 ==
3001 23:25:38.501550
3002 23:25:38.501934
3003 23:25:38.504051 TX Vref Scan disable
3004 23:25:38.504505 == TX Byte 0 ==
3005 23:25:38.507975 Update DQ dly =857 (3 ,2, 25) DQ OEN =(2 ,7)
3006 23:25:38.514218 Update DQM dly =857 (3 ,2, 25) DQM OEN =(2 ,7)
3007 23:25:38.514678 == TX Byte 1 ==
3008 23:25:38.517642 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3009 23:25:38.524829 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3010 23:25:38.525461 ==
3011 23:25:38.527588 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 23:25:38.530764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 23:25:38.531222 ==
3014 23:25:38.543294 TX Vref=22, minBit 12, minWin=24, winSum=415
3015 23:25:38.546617 TX Vref=24, minBit 13, minWin=25, winSum=422
3016 23:25:38.550111 TX Vref=26, minBit 12, minWin=25, winSum=422
3017 23:25:38.553748 TX Vref=28, minBit 15, minWin=25, winSum=427
3018 23:25:38.556833 TX Vref=30, minBit 15, minWin=25, winSum=427
3019 23:25:38.563538 TX Vref=32, minBit 8, minWin=26, winSum=428
3020 23:25:38.566919 [TxChooseVref] Worse bit 8, Min win 26, Win sum 428, Final Vref 32
3021 23:25:38.567472
3022 23:25:38.570459 Final TX Range 1 Vref 32
3023 23:25:38.570919
3024 23:25:38.571271 ==
3025 23:25:38.573875 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 23:25:38.577171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 23:25:38.580262 ==
3028 23:25:38.580816
3029 23:25:38.581172
3030 23:25:38.581497 TX Vref Scan disable
3031 23:25:38.583762 == TX Byte 0 ==
3032 23:25:38.587460 Update DQ dly =857 (3 ,2, 25) DQ OEN =(2 ,7)
3033 23:25:38.594425 Update DQM dly =857 (3 ,2, 25) DQM OEN =(2 ,7)
3034 23:25:38.595004 == TX Byte 1 ==
3035 23:25:38.597105 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3036 23:25:38.601606 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3037 23:25:38.604180
3038 23:25:38.604631 [DATLAT]
3039 23:25:38.605061 Freq=1200, CH0 RK1
3040 23:25:38.605403
3041 23:25:38.607823 DATLAT Default: 0xd
3042 23:25:38.608371 0, 0xFFFF, sum = 0
3043 23:25:38.610679 1, 0xFFFF, sum = 0
3044 23:25:38.611145 2, 0xFFFF, sum = 0
3045 23:25:38.613878 3, 0xFFFF, sum = 0
3046 23:25:38.614436 4, 0xFFFF, sum = 0
3047 23:25:38.617413 5, 0xFFFF, sum = 0
3048 23:25:38.617910 6, 0xFFFF, sum = 0
3049 23:25:38.620972 7, 0xFFFF, sum = 0
3050 23:25:38.624301 8, 0xFFFF, sum = 0
3051 23:25:38.624859 9, 0xFFFF, sum = 0
3052 23:25:38.627715 10, 0xFFFF, sum = 0
3053 23:25:38.628274 11, 0xFFFF, sum = 0
3054 23:25:38.630429 12, 0x0, sum = 1
3055 23:25:38.630892 13, 0x0, sum = 2
3056 23:25:38.633811 14, 0x0, sum = 3
3057 23:25:38.634370 15, 0x0, sum = 4
3058 23:25:38.634734 best_step = 13
3059 23:25:38.635066
3060 23:25:38.637499 ==
3061 23:25:38.640446 Dram Type= 6, Freq= 0, CH_0, rank 1
3062 23:25:38.643884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3063 23:25:38.644443 ==
3064 23:25:38.644804 RX Vref Scan: 0
3065 23:25:38.645137
3066 23:25:38.647218 RX Vref 0 -> 0, step: 1
3067 23:25:38.647810
3068 23:25:38.650386 RX Delay -13 -> 252, step: 4
3069 23:25:38.653688 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3070 23:25:38.657153 iDelay=195, Bit 1, Center 120 (55 ~ 186) 132
3071 23:25:38.664263 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3072 23:25:38.667252 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3073 23:25:38.670511 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3074 23:25:38.673937 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3075 23:25:38.677290 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3076 23:25:38.684033 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3077 23:25:38.687582 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3078 23:25:38.691285 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3079 23:25:38.694360 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3080 23:25:38.697607 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3081 23:25:38.704227 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3082 23:25:38.707570 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3083 23:25:38.710480 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3084 23:25:38.714129 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3085 23:25:38.714635 ==
3086 23:25:38.717380 Dram Type= 6, Freq= 0, CH_0, rank 1
3087 23:25:38.724396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3088 23:25:38.724912 ==
3089 23:25:38.725240 DQS Delay:
3090 23:25:38.725537 DQS0 = 0, DQS1 = 0
3091 23:25:38.727692 DQM Delay:
3092 23:25:38.728105 DQM0 = 120, DQM1 = 111
3093 23:25:38.730914 DQ Delay:
3094 23:25:38.734403 DQ0 =118, DQ1 =120, DQ2 =118, DQ3 =118
3095 23:25:38.737866 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3096 23:25:38.741232 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3097 23:25:38.744717 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =118
3098 23:25:38.745233
3099 23:25:38.745556
3100 23:25:38.750609 [DQSOSCAuto] RK1, (LSB)MR18= 0xbec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 405 ps
3101 23:25:38.754530 CH0 RK1: MR19=403, MR18=BEC
3102 23:25:38.761261 CH0_RK1: MR19=0x403, MR18=0xBEC, DQSOSC=405, MR23=63, INC=39, DEC=26
3103 23:25:38.764562 [RxdqsGatingPostProcess] freq 1200
3104 23:25:38.771359 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3105 23:25:38.774182 best DQS0 dly(2T, 0.5T) = (0, 11)
3106 23:25:38.774691 best DQS1 dly(2T, 0.5T) = (0, 12)
3107 23:25:38.777771 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3108 23:25:38.781255 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3109 23:25:38.784351 best DQS0 dly(2T, 0.5T) = (0, 11)
3110 23:25:38.787813 best DQS1 dly(2T, 0.5T) = (0, 11)
3111 23:25:38.791639 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3112 23:25:38.794424 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3113 23:25:38.797328 Pre-setting of DQS Precalculation
3114 23:25:38.804538 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3115 23:25:38.805053 ==
3116 23:25:38.808180 Dram Type= 6, Freq= 0, CH_1, rank 0
3117 23:25:38.811076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3118 23:25:38.811495 ==
3119 23:25:38.814446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3120 23:25:38.820618 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3121 23:25:38.830544 [CA 0] Center 37 (7~68) winsize 62
3122 23:25:38.833236 [CA 1] Center 37 (7~68) winsize 62
3123 23:25:38.836725 [CA 2] Center 35 (5~65) winsize 61
3124 23:25:38.839956 [CA 3] Center 34 (4~64) winsize 61
3125 23:25:38.843804 [CA 4] Center 34 (4~64) winsize 61
3126 23:25:38.846915 [CA 5] Center 33 (3~63) winsize 61
3127 23:25:38.847430
3128 23:25:38.850531 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3129 23:25:38.851046
3130 23:25:38.853378 [CATrainingPosCal] consider 1 rank data
3131 23:25:38.857010 u2DelayCellTimex100 = 270/100 ps
3132 23:25:38.860659 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3133 23:25:38.863222 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3134 23:25:38.870245 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3135 23:25:38.874015 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3136 23:25:38.876928 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3137 23:25:38.880319 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3138 23:25:38.880832
3139 23:25:38.883344 CA PerBit enable=1, Macro0, CA PI delay=33
3140 23:25:38.883761
3141 23:25:38.886606 [CBTSetCACLKResult] CA Dly = 33
3142 23:25:38.887016 CS Dly: 7 (0~38)
3143 23:25:38.887335 ==
3144 23:25:38.890263 Dram Type= 6, Freq= 0, CH_1, rank 1
3145 23:25:38.897130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3146 23:25:38.897700 ==
3147 23:25:38.900492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3148 23:25:38.906932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3149 23:25:38.915960 [CA 0] Center 37 (7~68) winsize 62
3150 23:25:38.919412 [CA 1] Center 37 (7~68) winsize 62
3151 23:25:38.922541 [CA 2] Center 35 (5~65) winsize 61
3152 23:25:38.926188 [CA 3] Center 34 (4~65) winsize 62
3153 23:25:38.929511 [CA 4] Center 34 (4~65) winsize 62
3154 23:25:38.932961 [CA 5] Center 34 (4~64) winsize 61
3155 23:25:38.933474
3156 23:25:38.935847 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3157 23:25:38.936259
3158 23:25:38.939147 [CATrainingPosCal] consider 2 rank data
3159 23:25:38.942328 u2DelayCellTimex100 = 270/100 ps
3160 23:25:38.946035 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3161 23:25:38.949139 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3162 23:25:38.956342 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3163 23:25:38.959587 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3164 23:25:38.962495 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3165 23:25:38.966508 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3166 23:25:38.967025
3167 23:25:38.969420 CA PerBit enable=1, Macro0, CA PI delay=33
3168 23:25:38.969983
3169 23:25:38.972582 [CBTSetCACLKResult] CA Dly = 33
3170 23:25:38.973100 CS Dly: 8 (0~41)
3171 23:25:38.973425
3172 23:25:38.975991 ----->DramcWriteLeveling(PI) begin...
3173 23:25:38.976510 ==
3174 23:25:38.979174 Dram Type= 6, Freq= 0, CH_1, rank 0
3175 23:25:38.986196 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3176 23:25:38.986695 ==
3177 23:25:38.989101 Write leveling (Byte 0): 26 => 26
3178 23:25:38.992738 Write leveling (Byte 1): 29 => 29
3179 23:25:38.993195 DramcWriteLeveling(PI) end<-----
3180 23:25:38.996108
3181 23:25:38.996562 ==
3182 23:25:38.999242 Dram Type= 6, Freq= 0, CH_1, rank 0
3183 23:25:39.002888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3184 23:25:39.003448 ==
3185 23:25:39.006022 [Gating] SW mode calibration
3186 23:25:39.013121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3187 23:25:39.016078 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3188 23:25:39.022730 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 23:25:39.025813 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3190 23:25:39.029476 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3191 23:25:39.036569 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3192 23:25:39.039400 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3193 23:25:39.042736 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3194 23:25:39.049728 0 15 24 | B1->B0 | 3131 2d2d | 0 1 | (0 0) (1 0)
3195 23:25:39.052678 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3196 23:25:39.056314 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 23:25:39.062462 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3198 23:25:39.065611 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3199 23:25:39.069673 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3200 23:25:39.076347 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3201 23:25:39.079618 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3202 23:25:39.082717 1 0 24 | B1->B0 | 3232 4040 | 0 0 | (0 0) (0 0)
3203 23:25:39.085999 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 23:25:39.093378 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 23:25:39.096199 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3206 23:25:39.099269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3207 23:25:39.106105 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3208 23:25:39.109362 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3209 23:25:39.112981 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3210 23:25:39.119365 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3211 23:25:39.123079 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3212 23:25:39.126034 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 23:25:39.132587 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 23:25:39.136229 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 23:25:39.139602 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 23:25:39.146514 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 23:25:39.150105 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 23:25:39.152865 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 23:25:39.159544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 23:25:39.162895 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3221 23:25:39.166522 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3222 23:25:39.172656 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:25:39.175986 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:25:39.179918 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:25:39.182518 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3226 23:25:39.189843 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3227 23:25:39.192984 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3228 23:25:39.196267 Total UI for P1: 0, mck2ui 16
3229 23:25:39.199263 best dqsien dly found for B1: ( 1, 3, 24)
3230 23:25:39.202496 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 23:25:39.205948 Total UI for P1: 0, mck2ui 16
3232 23:25:39.209655 best dqsien dly found for B0: ( 1, 3, 24)
3233 23:25:39.213115 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3234 23:25:39.216789 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3235 23:25:39.217343
3236 23:25:39.223258 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3237 23:25:39.226121 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3238 23:25:39.229723 [Gating] SW calibration Done
3239 23:25:39.230275 ==
3240 23:25:39.233475 Dram Type= 6, Freq= 0, CH_1, rank 0
3241 23:25:39.236132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3242 23:25:39.236593 ==
3243 23:25:39.236947 RX Vref Scan: 0
3244 23:25:39.237274
3245 23:25:39.239912 RX Vref 0 -> 0, step: 1
3246 23:25:39.240471
3247 23:25:39.243321 RX Delay -40 -> 252, step: 8
3248 23:25:39.246514 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3249 23:25:39.249780 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3250 23:25:39.253189 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3251 23:25:39.259951 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3252 23:25:39.262828 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3253 23:25:39.266015 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3254 23:25:39.270056 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3255 23:25:39.273135 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3256 23:25:39.279731 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3257 23:25:39.282573 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3258 23:25:39.286492 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3259 23:25:39.289842 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3260 23:25:39.296141 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3261 23:25:39.299035 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3262 23:25:39.302568 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3263 23:25:39.306080 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3264 23:25:39.306679 ==
3265 23:25:39.309693 Dram Type= 6, Freq= 0, CH_1, rank 0
3266 23:25:39.312996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3267 23:25:39.316434 ==
3268 23:25:39.317029 DQS Delay:
3269 23:25:39.317510 DQS0 = 0, DQS1 = 0
3270 23:25:39.319773 DQM Delay:
3271 23:25:39.320361 DQM0 = 119, DQM1 = 116
3272 23:25:39.323055 DQ Delay:
3273 23:25:39.326616 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3274 23:25:39.329549 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3275 23:25:39.332611 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3276 23:25:39.336182 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3277 23:25:39.336756
3278 23:25:39.337238
3279 23:25:39.337811 ==
3280 23:25:39.339939 Dram Type= 6, Freq= 0, CH_1, rank 0
3281 23:25:39.343260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3282 23:25:39.343833 ==
3283 23:25:39.344314
3284 23:25:39.344758
3285 23:25:39.345896 TX Vref Scan disable
3286 23:25:39.350061 == TX Byte 0 ==
3287 23:25:39.352990 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3288 23:25:39.355697 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3289 23:25:39.359728 == TX Byte 1 ==
3290 23:25:39.362644 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3291 23:25:39.365971 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3292 23:25:39.366446 ==
3293 23:25:39.369652 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 23:25:39.376576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 23:25:39.377191 ==
3296 23:25:39.386351 TX Vref=22, minBit 1, minWin=25, winSum=413
3297 23:25:39.389997 TX Vref=24, minBit 9, minWin=24, winSum=418
3298 23:25:39.393120 TX Vref=26, minBit 1, minWin=26, winSum=427
3299 23:25:39.396546 TX Vref=28, minBit 2, minWin=26, winSum=430
3300 23:25:39.399450 TX Vref=30, minBit 2, minWin=26, winSum=432
3301 23:25:39.402922 TX Vref=32, minBit 10, minWin=25, winSum=432
3302 23:25:39.409747 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 30
3303 23:25:39.410452
3304 23:25:39.413060 Final TX Range 1 Vref 30
3305 23:25:39.413517
3306 23:25:39.413913 ==
3307 23:25:39.416417 Dram Type= 6, Freq= 0, CH_1, rank 0
3308 23:25:39.420161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3309 23:25:39.420745 ==
3310 23:25:39.422905
3311 23:25:39.423448
3312 23:25:39.423805 TX Vref Scan disable
3313 23:25:39.426186 == TX Byte 0 ==
3314 23:25:39.429660 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3315 23:25:39.432781 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3316 23:25:39.436193 == TX Byte 1 ==
3317 23:25:39.439615 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3318 23:25:39.442949 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3319 23:25:39.443434
3320 23:25:39.446457 [DATLAT]
3321 23:25:39.446909 Freq=1200, CH1 RK0
3322 23:25:39.447262
3323 23:25:39.450071 DATLAT Default: 0xd
3324 23:25:39.450662 0, 0xFFFF, sum = 0
3325 23:25:39.453282 1, 0xFFFF, sum = 0
3326 23:25:39.453886 2, 0xFFFF, sum = 0
3327 23:25:39.456205 3, 0xFFFF, sum = 0
3328 23:25:39.456666 4, 0xFFFF, sum = 0
3329 23:25:39.459900 5, 0xFFFF, sum = 0
3330 23:25:39.460461 6, 0xFFFF, sum = 0
3331 23:25:39.462854 7, 0xFFFF, sum = 0
3332 23:25:39.466123 8, 0xFFFF, sum = 0
3333 23:25:39.466588 9, 0xFFFF, sum = 0
3334 23:25:39.469685 10, 0xFFFF, sum = 0
3335 23:25:39.470249 11, 0xFFFF, sum = 0
3336 23:25:39.473138 12, 0x0, sum = 1
3337 23:25:39.473629 13, 0x0, sum = 2
3338 23:25:39.476214 14, 0x0, sum = 3
3339 23:25:39.476628 15, 0x0, sum = 4
3340 23:25:39.476951 best_step = 13
3341 23:25:39.477247
3342 23:25:39.479568 ==
3343 23:25:39.483119 Dram Type= 6, Freq= 0, CH_1, rank 0
3344 23:25:39.486564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3345 23:25:39.487118 ==
3346 23:25:39.487449 RX Vref Scan: 1
3347 23:25:39.487748
3348 23:25:39.489679 Set Vref Range= 32 -> 127
3349 23:25:39.490091
3350 23:25:39.492662 RX Vref 32 -> 127, step: 1
3351 23:25:39.493070
3352 23:25:39.496175 RX Delay -5 -> 252, step: 4
3353 23:25:39.496687
3354 23:25:39.499561 Set Vref, RX VrefLevel [Byte0]: 32
3355 23:25:39.502646 [Byte1]: 32
3356 23:25:39.503061
3357 23:25:39.506239 Set Vref, RX VrefLevel [Byte0]: 33
3358 23:25:39.509604 [Byte1]: 33
3359 23:25:39.510027
3360 23:25:39.512512 Set Vref, RX VrefLevel [Byte0]: 34
3361 23:25:39.516078 [Byte1]: 34
3362 23:25:39.520062
3363 23:25:39.520472 Set Vref, RX VrefLevel [Byte0]: 35
3364 23:25:39.526698 [Byte1]: 35
3365 23:25:39.527110
3366 23:25:39.530093 Set Vref, RX VrefLevel [Byte0]: 36
3367 23:25:39.533130 [Byte1]: 36
3368 23:25:39.533539
3369 23:25:39.536717 Set Vref, RX VrefLevel [Byte0]: 37
3370 23:25:39.539977 [Byte1]: 37
3371 23:25:39.543817
3372 23:25:39.544319 Set Vref, RX VrefLevel [Byte0]: 38
3373 23:25:39.547297 [Byte1]: 38
3374 23:25:39.551886
3375 23:25:39.552414 Set Vref, RX VrefLevel [Byte0]: 39
3376 23:25:39.554622 [Byte1]: 39
3377 23:25:39.559285
3378 23:25:39.559786 Set Vref, RX VrefLevel [Byte0]: 40
3379 23:25:39.562491 [Byte1]: 40
3380 23:25:39.567651
3381 23:25:39.568157 Set Vref, RX VrefLevel [Byte0]: 41
3382 23:25:39.570676 [Byte1]: 41
3383 23:25:39.575838
3384 23:25:39.576344 Set Vref, RX VrefLevel [Byte0]: 42
3385 23:25:39.578810 [Byte1]: 42
3386 23:25:39.582955
3387 23:25:39.583364 Set Vref, RX VrefLevel [Byte0]: 43
3388 23:25:39.586511 [Byte1]: 43
3389 23:25:39.590914
3390 23:25:39.591412 Set Vref, RX VrefLevel [Byte0]: 44
3391 23:25:39.594265 [Byte1]: 44
3392 23:25:39.598415
3393 23:25:39.598822 Set Vref, RX VrefLevel [Byte0]: 45
3394 23:25:39.602144 [Byte1]: 45
3395 23:25:39.606688
3396 23:25:39.607212 Set Vref, RX VrefLevel [Byte0]: 46
3397 23:25:39.609689 [Byte1]: 46
3398 23:25:39.614372
3399 23:25:39.614874 Set Vref, RX VrefLevel [Byte0]: 47
3400 23:25:39.617848 [Byte1]: 47
3401 23:25:39.621979
3402 23:25:39.622532 Set Vref, RX VrefLevel [Byte0]: 48
3403 23:25:39.625618 [Byte1]: 48
3404 23:25:39.630443
3405 23:25:39.630947 Set Vref, RX VrefLevel [Byte0]: 49
3406 23:25:39.633252 [Byte1]: 49
3407 23:25:39.638080
3408 23:25:39.638579 Set Vref, RX VrefLevel [Byte0]: 50
3409 23:25:39.641204 [Byte1]: 50
3410 23:25:39.645893
3411 23:25:39.646411 Set Vref, RX VrefLevel [Byte0]: 51
3412 23:25:39.648882 [Byte1]: 51
3413 23:25:39.653936
3414 23:25:39.654491 Set Vref, RX VrefLevel [Byte0]: 52
3415 23:25:39.657088 [Byte1]: 52
3416 23:25:39.661469
3417 23:25:39.662026 Set Vref, RX VrefLevel [Byte0]: 53
3418 23:25:39.665011 [Byte1]: 53
3419 23:25:39.669404
3420 23:25:39.669962 Set Vref, RX VrefLevel [Byte0]: 54
3421 23:25:39.672689 [Byte1]: 54
3422 23:25:39.677746
3423 23:25:39.678430 Set Vref, RX VrefLevel [Byte0]: 55
3424 23:25:39.680283 [Byte1]: 55
3425 23:25:39.685224
3426 23:25:39.685683 Set Vref, RX VrefLevel [Byte0]: 56
3427 23:25:39.688423 [Byte1]: 56
3428 23:25:39.693104
3429 23:25:39.693672 Set Vref, RX VrefLevel [Byte0]: 57
3430 23:25:39.696390 [Byte1]: 57
3431 23:25:39.700726
3432 23:25:39.701135 Set Vref, RX VrefLevel [Byte0]: 58
3433 23:25:39.704280 [Byte1]: 58
3434 23:25:39.708402
3435 23:25:39.708834 Set Vref, RX VrefLevel [Byte0]: 59
3436 23:25:39.712318 [Byte1]: 59
3437 23:25:39.716892
3438 23:25:39.717455 Set Vref, RX VrefLevel [Byte0]: 60
3439 23:25:39.719535 [Byte1]: 60
3440 23:25:39.724536
3441 23:25:39.725044 Set Vref, RX VrefLevel [Byte0]: 61
3442 23:25:39.727460 [Byte1]: 61
3443 23:25:39.732100
3444 23:25:39.732654 Set Vref, RX VrefLevel [Byte0]: 62
3445 23:25:39.735372 [Byte1]: 62
3446 23:25:39.739882
3447 23:25:39.740448 Set Vref, RX VrefLevel [Byte0]: 63
3448 23:25:39.743077 [Byte1]: 63
3449 23:25:39.747928
3450 23:25:39.748411 Set Vref, RX VrefLevel [Byte0]: 64
3451 23:25:39.750916 [Byte1]: 64
3452 23:25:39.755871
3453 23:25:39.756406 Set Vref, RX VrefLevel [Byte0]: 65
3454 23:25:39.759198 [Byte1]: 65
3455 23:25:39.763646
3456 23:25:39.764158 Set Vref, RX VrefLevel [Byte0]: 66
3457 23:25:39.767171 [Byte1]: 66
3458 23:25:39.771362
3459 23:25:39.771861 Set Vref, RX VrefLevel [Byte0]: 67
3460 23:25:39.774543 [Byte1]: 67
3461 23:25:39.779012
3462 23:25:39.779538 Set Vref, RX VrefLevel [Byte0]: 68
3463 23:25:39.782434 [Byte1]: 68
3464 23:25:39.786952
3465 23:25:39.787409 Set Vref, RX VrefLevel [Byte0]: 69
3466 23:25:39.790746 [Byte1]: 69
3467 23:25:39.794996
3468 23:25:39.795536 Final RX Vref Byte 0 = 54 to rank0
3469 23:25:39.798531 Final RX Vref Byte 1 = 54 to rank0
3470 23:25:39.801680 Final RX Vref Byte 0 = 54 to rank1
3471 23:25:39.805286 Final RX Vref Byte 1 = 54 to rank1==
3472 23:25:39.807971 Dram Type= 6, Freq= 0, CH_1, rank 0
3473 23:25:39.814782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3474 23:25:39.815353 ==
3475 23:25:39.815714 DQS Delay:
3476 23:25:39.816043 DQS0 = 0, DQS1 = 0
3477 23:25:39.818084 DQM Delay:
3478 23:25:39.818538 DQM0 = 120, DQM1 = 117
3479 23:25:39.821852 DQ Delay:
3480 23:25:39.824858 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3481 23:25:39.828311 DQ4 =120, DQ5 =128, DQ6 =130, DQ7 =120
3482 23:25:39.831935 DQ8 =104, DQ9 =108, DQ10 =118, DQ11 =112
3483 23:25:39.835193 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3484 23:25:39.835745
3485 23:25:39.836102
3486 23:25:39.841770 [DQSOSCAuto] RK0, (LSB)MR18= 0x13, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 410 ps
3487 23:25:39.845003 CH1 RK0: MR19=404, MR18=13
3488 23:25:39.851951 CH1_RK0: MR19=0x404, MR18=0x13, DQSOSC=402, MR23=63, INC=40, DEC=27
3489 23:25:39.852508
3490 23:25:39.855232 ----->DramcWriteLeveling(PI) begin...
3491 23:25:39.855792 ==
3492 23:25:39.858343 Dram Type= 6, Freq= 0, CH_1, rank 1
3493 23:25:39.862072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3494 23:25:39.862630 ==
3495 23:25:39.864770 Write leveling (Byte 0): 26 => 26
3496 23:25:39.868658 Write leveling (Byte 1): 27 => 27
3497 23:25:39.872281 DramcWriteLeveling(PI) end<-----
3498 23:25:39.872832
3499 23:25:39.873188 ==
3500 23:25:39.875337 Dram Type= 6, Freq= 0, CH_1, rank 1
3501 23:25:39.878374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3502 23:25:39.881638 ==
3503 23:25:39.882098 [Gating] SW mode calibration
3504 23:25:39.888081 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3505 23:25:39.894935 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3506 23:25:39.898199 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3507 23:25:39.905234 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3508 23:25:39.908316 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 23:25:39.912276 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 23:25:39.918695 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 23:25:39.921881 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3512 23:25:39.925208 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (1 0) (0 1)
3513 23:25:39.928324 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3514 23:25:39.935902 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3515 23:25:39.938327 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 23:25:39.942092 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 23:25:39.948370 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 23:25:39.951505 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 23:25:39.955229 1 0 20 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3520 23:25:39.961722 1 0 24 | B1->B0 | 4444 2f2f | 0 0 | (0 0) (1 1)
3521 23:25:39.964820 1 0 28 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
3522 23:25:39.969308 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 23:25:39.975289 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 23:25:39.978807 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 23:25:39.981802 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 23:25:39.988432 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 23:25:39.991293 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3528 23:25:39.994961 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3529 23:25:40.001229 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3530 23:25:40.004343 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3531 23:25:40.007782 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 23:25:40.014651 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 23:25:40.018317 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 23:25:40.021349 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 23:25:40.027731 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 23:25:40.031561 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 23:25:40.034916 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 23:25:40.041341 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 23:25:40.044726 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 23:25:40.047918 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 23:25:40.054595 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:25:40.057659 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:25:40.061136 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:25:40.067702 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3545 23:25:40.071000 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3546 23:25:40.074024 Total UI for P1: 0, mck2ui 16
3547 23:25:40.077885 best dqsien dly found for B1: ( 1, 3, 24)
3548 23:25:40.081041 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3549 23:25:40.084535 Total UI for P1: 0, mck2ui 16
3550 23:25:40.088156 best dqsien dly found for B0: ( 1, 3, 28)
3551 23:25:40.091156 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3552 23:25:40.094302 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3553 23:25:40.094723
3554 23:25:40.098080 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3555 23:25:40.103946 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3556 23:25:40.104538 [Gating] SW calibration Done
3557 23:25:40.105020 ==
3558 23:25:40.107629 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 23:25:40.114114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 23:25:40.114539 ==
3561 23:25:40.114868 RX Vref Scan: 0
3562 23:25:40.115171
3563 23:25:40.118095 RX Vref 0 -> 0, step: 1
3564 23:25:40.118558
3565 23:25:40.120787 RX Delay -40 -> 252, step: 8
3566 23:25:40.124709 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3567 23:25:40.127826 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3568 23:25:40.130580 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3569 23:25:40.137301 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3570 23:25:40.140974 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3571 23:25:40.143929 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3572 23:25:40.147355 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3573 23:25:40.150710 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3574 23:25:40.157809 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3575 23:25:40.160740 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3576 23:25:40.164307 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3577 23:25:40.167159 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3578 23:25:40.170457 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3579 23:25:40.177045 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3580 23:25:40.180700 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3581 23:25:40.184122 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3582 23:25:40.184697 ==
3583 23:25:40.187412 Dram Type= 6, Freq= 0, CH_1, rank 1
3584 23:25:40.190657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3585 23:25:40.191237 ==
3586 23:25:40.194050 DQS Delay:
3587 23:25:40.194614 DQS0 = 0, DQS1 = 0
3588 23:25:40.197051 DQM Delay:
3589 23:25:40.197660 DQM0 = 121, DQM1 = 117
3590 23:25:40.201208 DQ Delay:
3591 23:25:40.204102 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3592 23:25:40.207418 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3593 23:25:40.210366 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3594 23:25:40.213671 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3595 23:25:40.214196
3596 23:25:40.214563
3597 23:25:40.214899 ==
3598 23:25:40.217027 Dram Type= 6, Freq= 0, CH_1, rank 1
3599 23:25:40.220593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3600 23:25:40.221060 ==
3601 23:25:40.221423
3602 23:25:40.221822
3603 23:25:40.223648 TX Vref Scan disable
3604 23:25:40.227462 == TX Byte 0 ==
3605 23:25:40.230158 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3606 23:25:40.233656 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3607 23:25:40.237408 == TX Byte 1 ==
3608 23:25:40.239835 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3609 23:25:40.243774 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3610 23:25:40.244342 ==
3611 23:25:40.247054 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 23:25:40.253496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 23:25:40.254129 ==
3614 23:25:40.263976 TX Vref=22, minBit 10, minWin=25, winSum=419
3615 23:25:40.267122 TX Vref=24, minBit 2, minWin=26, winSum=425
3616 23:25:40.270895 TX Vref=26, minBit 2, minWin=26, winSum=428
3617 23:25:40.273679 TX Vref=28, minBit 9, minWin=26, winSum=433
3618 23:25:40.277540 TX Vref=30, minBit 9, minWin=26, winSum=435
3619 23:25:40.283766 TX Vref=32, minBit 9, minWin=26, winSum=434
3620 23:25:40.287456 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3621 23:25:40.288017
3622 23:25:40.290571 Final TX Range 1 Vref 30
3623 23:25:40.291029
3624 23:25:40.291386 ==
3625 23:25:40.293678 Dram Type= 6, Freq= 0, CH_1, rank 1
3626 23:25:40.297092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3627 23:25:40.297705 ==
3628 23:25:40.300900
3629 23:25:40.301466
3630 23:25:40.301892 TX Vref Scan disable
3631 23:25:40.303576 == TX Byte 0 ==
3632 23:25:40.306847 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3633 23:25:40.310293 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3634 23:25:40.313564 == TX Byte 1 ==
3635 23:25:40.317367 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3636 23:25:40.320806 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3637 23:25:40.323263
3638 23:25:40.323721 [DATLAT]
3639 23:25:40.324081 Freq=1200, CH1 RK1
3640 23:25:40.324521
3641 23:25:40.326817 DATLAT Default: 0xd
3642 23:25:40.327276 0, 0xFFFF, sum = 0
3643 23:25:40.330025 1, 0xFFFF, sum = 0
3644 23:25:40.330494 2, 0xFFFF, sum = 0
3645 23:25:40.333220 3, 0xFFFF, sum = 0
3646 23:25:40.336793 4, 0xFFFF, sum = 0
3647 23:25:40.337350 5, 0xFFFF, sum = 0
3648 23:25:40.340704 6, 0xFFFF, sum = 0
3649 23:25:40.341260 7, 0xFFFF, sum = 0
3650 23:25:40.343523 8, 0xFFFF, sum = 0
3651 23:25:40.344081 9, 0xFFFF, sum = 0
3652 23:25:40.346927 10, 0xFFFF, sum = 0
3653 23:25:40.347488 11, 0xFFFF, sum = 0
3654 23:25:40.350406 12, 0x0, sum = 1
3655 23:25:40.350966 13, 0x0, sum = 2
3656 23:25:40.353499 14, 0x0, sum = 3
3657 23:25:40.354129 15, 0x0, sum = 4
3658 23:25:40.354513 best_step = 13
3659 23:25:40.356883
3660 23:25:40.357433 ==
3661 23:25:40.360590 Dram Type= 6, Freq= 0, CH_1, rank 1
3662 23:25:40.363773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3663 23:25:40.364329 ==
3664 23:25:40.364687 RX Vref Scan: 0
3665 23:25:40.365018
3666 23:25:40.366705 RX Vref 0 -> 0, step: 1
3667 23:25:40.367162
3668 23:25:40.370227 RX Delay -5 -> 252, step: 4
3669 23:25:40.373896 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3670 23:25:40.380179 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3671 23:25:40.383157 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3672 23:25:40.387105 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3673 23:25:40.389679 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3674 23:25:40.393152 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3675 23:25:40.399971 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3676 23:25:40.403374 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3677 23:25:40.406467 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3678 23:25:40.410555 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3679 23:25:40.413177 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3680 23:25:40.420167 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3681 23:25:40.423163 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3682 23:25:40.426845 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3683 23:25:40.430184 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3684 23:25:40.433359 iDelay=195, Bit 15, Center 126 (67 ~ 186) 120
3685 23:25:40.436007 ==
3686 23:25:40.439843 Dram Type= 6, Freq= 0, CH_1, rank 1
3687 23:25:40.443064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3688 23:25:40.443610 ==
3689 23:25:40.443968 DQS Delay:
3690 23:25:40.446919 DQS0 = 0, DQS1 = 0
3691 23:25:40.447467 DQM Delay:
3692 23:25:40.449704 DQM0 = 120, DQM1 = 117
3693 23:25:40.450159 DQ Delay:
3694 23:25:40.453429 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3695 23:25:40.456459 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3696 23:25:40.459660 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3697 23:25:40.463316 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =126
3698 23:25:40.463862
3699 23:25:40.464218
3700 23:25:40.472949 [DQSOSCAuto] RK1, (LSB)MR18= 0xfeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3701 23:25:40.473504 CH1 RK1: MR19=403, MR18=FEB
3702 23:25:40.479865 CH1_RK1: MR19=0x403, MR18=0xFEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3703 23:25:40.483156 [RxdqsGatingPostProcess] freq 1200
3704 23:25:40.489647 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3705 23:25:40.493654 best DQS0 dly(2T, 0.5T) = (0, 11)
3706 23:25:40.496491 best DQS1 dly(2T, 0.5T) = (0, 11)
3707 23:25:40.499939 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3708 23:25:40.503621 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3709 23:25:40.506222 best DQS0 dly(2T, 0.5T) = (0, 11)
3710 23:25:40.506682 best DQS1 dly(2T, 0.5T) = (0, 11)
3711 23:25:40.509847 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3712 23:25:40.512910 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3713 23:25:40.515968 Pre-setting of DQS Precalculation
3714 23:25:40.522667 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3715 23:25:40.529692 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3716 23:25:40.536400 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3717 23:25:40.536963
3718 23:25:40.537319
3719 23:25:40.539707 [Calibration Summary] 2400 Mbps
3720 23:25:40.542864 CH 0, Rank 0
3721 23:25:40.543421 SW Impedance : PASS
3722 23:25:40.545873 DUTY Scan : NO K
3723 23:25:40.549409 ZQ Calibration : PASS
3724 23:25:40.550034 Jitter Meter : NO K
3725 23:25:40.552857 CBT Training : PASS
3726 23:25:40.553418 Write leveling : PASS
3727 23:25:40.555997 RX DQS gating : PASS
3728 23:25:40.559499 RX DQ/DQS(RDDQC) : PASS
3729 23:25:40.560057 TX DQ/DQS : PASS
3730 23:25:40.562895 RX DATLAT : PASS
3731 23:25:40.566236 RX DQ/DQS(Engine): PASS
3732 23:25:40.566781 TX OE : NO K
3733 23:25:40.569489 All Pass.
3734 23:25:40.570008
3735 23:25:40.570369 CH 0, Rank 1
3736 23:25:40.573142 SW Impedance : PASS
3737 23:25:40.573754 DUTY Scan : NO K
3738 23:25:40.576100 ZQ Calibration : PASS
3739 23:25:40.579355 Jitter Meter : NO K
3740 23:25:40.579911 CBT Training : PASS
3741 23:25:40.583165 Write leveling : PASS
3742 23:25:40.586176 RX DQS gating : PASS
3743 23:25:40.586727 RX DQ/DQS(RDDQC) : PASS
3744 23:25:40.589024 TX DQ/DQS : PASS
3745 23:25:40.592484 RX DATLAT : PASS
3746 23:25:40.593056 RX DQ/DQS(Engine): PASS
3747 23:25:40.595889 TX OE : NO K
3748 23:25:40.596460 All Pass.
3749 23:25:40.596943
3750 23:25:40.599475 CH 1, Rank 0
3751 23:25:40.600046 SW Impedance : PASS
3752 23:25:40.602439 DUTY Scan : NO K
3753 23:25:40.605731 ZQ Calibration : PASS
3754 23:25:40.606210 Jitter Meter : NO K
3755 23:25:40.609283 CBT Training : PASS
3756 23:25:40.609808 Write leveling : PASS
3757 23:25:40.612275 RX DQS gating : PASS
3758 23:25:40.615557 RX DQ/DQS(RDDQC) : PASS
3759 23:25:40.616073 TX DQ/DQS : PASS
3760 23:25:40.618882 RX DATLAT : PASS
3761 23:25:40.622465 RX DQ/DQS(Engine): PASS
3762 23:25:40.623030 TX OE : NO K
3763 23:25:40.625313 All Pass.
3764 23:25:40.625812
3765 23:25:40.626170 CH 1, Rank 1
3766 23:25:40.628713 SW Impedance : PASS
3767 23:25:40.629174 DUTY Scan : NO K
3768 23:25:40.632490 ZQ Calibration : PASS
3769 23:25:40.635439 Jitter Meter : NO K
3770 23:25:40.636110 CBT Training : PASS
3771 23:25:40.638426 Write leveling : PASS
3772 23:25:40.641780 RX DQS gating : PASS
3773 23:25:40.642444 RX DQ/DQS(RDDQC) : PASS
3774 23:25:40.645540 TX DQ/DQS : PASS
3775 23:25:40.648836 RX DATLAT : PASS
3776 23:25:40.649153 RX DQ/DQS(Engine): PASS
3777 23:25:40.652007 TX OE : NO K
3778 23:25:40.652230 All Pass.
3779 23:25:40.652404
3780 23:25:40.655131 DramC Write-DBI off
3781 23:25:40.658320 PER_BANK_REFRESH: Hybrid Mode
3782 23:25:40.658497 TX_TRACKING: ON
3783 23:25:40.667928 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3784 23:25:40.671628 [FAST_K] Save calibration result to emmc
3785 23:25:40.674383 dramc_set_vcore_voltage set vcore to 650000
3786 23:25:40.677816 Read voltage for 600, 5
3787 23:25:40.677918 Vio18 = 0
3788 23:25:40.677997 Vcore = 650000
3789 23:25:40.681297 Vdram = 0
3790 23:25:40.681387 Vddq = 0
3791 23:25:40.681457 Vmddr = 0
3792 23:25:40.687966 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3793 23:25:40.691629 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3794 23:25:40.694793 MEM_TYPE=3, freq_sel=19
3795 23:25:40.697753 sv_algorithm_assistance_LP4_1600
3796 23:25:40.701041 ============ PULL DRAM RESETB DOWN ============
3797 23:25:40.704725 ========== PULL DRAM RESETB DOWN end =========
3798 23:25:40.710945 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3799 23:25:40.715150 ===================================
3800 23:25:40.715569 LPDDR4 DRAM CONFIGURATION
3801 23:25:40.718044 ===================================
3802 23:25:40.721236 EX_ROW_EN[0] = 0x0
3803 23:25:40.724802 EX_ROW_EN[1] = 0x0
3804 23:25:40.725216 LP4Y_EN = 0x0
3805 23:25:40.728357 WORK_FSP = 0x0
3806 23:25:40.728880 WL = 0x2
3807 23:25:40.731540 RL = 0x2
3808 23:25:40.732157 BL = 0x2
3809 23:25:40.734723 RPST = 0x0
3810 23:25:40.735135 RD_PRE = 0x0
3811 23:25:40.738182 WR_PRE = 0x1
3812 23:25:40.738600 WR_PST = 0x0
3813 23:25:40.741813 DBI_WR = 0x0
3814 23:25:40.742225 DBI_RD = 0x0
3815 23:25:40.744714 OTF = 0x1
3816 23:25:40.748146 ===================================
3817 23:25:40.751257 ===================================
3818 23:25:40.751552 ANA top config
3819 23:25:40.754648 ===================================
3820 23:25:40.757911 DLL_ASYNC_EN = 0
3821 23:25:40.760899 ALL_SLAVE_EN = 1
3822 23:25:40.764679 NEW_RANK_MODE = 1
3823 23:25:40.764828 DLL_IDLE_MODE = 1
3824 23:25:40.767694 LP45_APHY_COMB_EN = 1
3825 23:25:40.771363 TX_ODT_DIS = 1
3826 23:25:40.774278 NEW_8X_MODE = 1
3827 23:25:40.777604 ===================================
3828 23:25:40.781042 ===================================
3829 23:25:40.784645 data_rate = 1200
3830 23:25:40.784964 CKR = 1
3831 23:25:40.788108 DQ_P2S_RATIO = 8
3832 23:25:40.791045 ===================================
3833 23:25:40.794694 CA_P2S_RATIO = 8
3834 23:25:40.797625 DQ_CA_OPEN = 0
3835 23:25:40.801047 DQ_SEMI_OPEN = 0
3836 23:25:40.804260 CA_SEMI_OPEN = 0
3837 23:25:40.804514 CA_FULL_RATE = 0
3838 23:25:40.807693 DQ_CKDIV4_EN = 1
3839 23:25:40.811671 CA_CKDIV4_EN = 1
3840 23:25:40.814680 CA_PREDIV_EN = 0
3841 23:25:40.817990 PH8_DLY = 0
3842 23:25:40.818153 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3843 23:25:40.821342 DQ_AAMCK_DIV = 4
3844 23:25:40.824598 CA_AAMCK_DIV = 4
3845 23:25:40.828280 CA_ADMCK_DIV = 4
3846 23:25:40.831062 DQ_TRACK_CA_EN = 0
3847 23:25:40.834542 CA_PICK = 600
3848 23:25:40.837679 CA_MCKIO = 600
3849 23:25:40.837880 MCKIO_SEMI = 0
3850 23:25:40.840639 PLL_FREQ = 2288
3851 23:25:40.844136 DQ_UI_PI_RATIO = 32
3852 23:25:40.847608 CA_UI_PI_RATIO = 0
3853 23:25:40.851096 ===================================
3854 23:25:40.854089 ===================================
3855 23:25:40.857687 memory_type:LPDDR4
3856 23:25:40.857997 GP_NUM : 10
3857 23:25:40.860986 SRAM_EN : 1
3858 23:25:40.864762 MD32_EN : 0
3859 23:25:40.867864 ===================================
3860 23:25:40.868220 [ANA_INIT] >>>>>>>>>>>>>>
3861 23:25:40.871108 <<<<<< [CONFIGURE PHASE]: ANA_TX
3862 23:25:40.874274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3863 23:25:40.877744 ===================================
3864 23:25:40.881345 data_rate = 1200,PCW = 0X5800
3865 23:25:40.884882 ===================================
3866 23:25:40.888117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3867 23:25:40.894392 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3868 23:25:40.897552 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 23:25:40.904081 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3870 23:25:40.907412 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3871 23:25:40.910583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3872 23:25:40.911069 [ANA_INIT] flow start
3873 23:25:40.914170 [ANA_INIT] PLL >>>>>>>>
3874 23:25:40.917382 [ANA_INIT] PLL <<<<<<<<
3875 23:25:40.921123 [ANA_INIT] MIDPI >>>>>>>>
3876 23:25:40.921744 [ANA_INIT] MIDPI <<<<<<<<
3877 23:25:40.924254 [ANA_INIT] DLL >>>>>>>>
3878 23:25:40.924836 [ANA_INIT] flow end
3879 23:25:40.931159 ============ LP4 DIFF to SE enter ============
3880 23:25:40.934334 ============ LP4 DIFF to SE exit ============
3881 23:25:40.937398 [ANA_INIT] <<<<<<<<<<<<<
3882 23:25:40.941218 [Flow] Enable top DCM control >>>>>
3883 23:25:40.944358 [Flow] Enable top DCM control <<<<<
3884 23:25:40.947621 Enable DLL master slave shuffle
3885 23:25:40.950882 ==============================================================
3886 23:25:40.954097 Gating Mode config
3887 23:25:40.957258 ==============================================================
3888 23:25:40.961147 Config description:
3889 23:25:40.970684 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3890 23:25:40.977279 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3891 23:25:40.980812 SELPH_MODE 0: By rank 1: By Phase
3892 23:25:40.987604 ==============================================================
3893 23:25:40.990876 GAT_TRACK_EN = 1
3894 23:25:40.993948 RX_GATING_MODE = 2
3895 23:25:40.997362 RX_GATING_TRACK_MODE = 2
3896 23:25:41.001348 SELPH_MODE = 1
3897 23:25:41.003894 PICG_EARLY_EN = 1
3898 23:25:41.004461 VALID_LAT_VALUE = 1
3899 23:25:41.010225 ==============================================================
3900 23:25:41.013817 Enter into Gating configuration >>>>
3901 23:25:41.017099 Exit from Gating configuration <<<<
3902 23:25:41.020882 Enter into DVFS_PRE_config >>>>>
3903 23:25:41.030485 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3904 23:25:41.034314 Exit from DVFS_PRE_config <<<<<
3905 23:25:41.037405 Enter into PICG configuration >>>>
3906 23:25:41.040783 Exit from PICG configuration <<<<
3907 23:25:41.043688 [RX_INPUT] configuration >>>>>
3908 23:25:41.046876 [RX_INPUT] configuration <<<<<
3909 23:25:41.050888 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3910 23:25:41.056795 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3911 23:25:41.063728 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3912 23:25:41.069982 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3913 23:25:41.076888 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3914 23:25:41.083748 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3915 23:25:41.087070 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3916 23:25:41.090605 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3917 23:25:41.093415 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3918 23:25:41.097137 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3919 23:25:41.104057 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3920 23:25:41.107113 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3921 23:25:41.110765 ===================================
3922 23:25:41.113867 LPDDR4 DRAM CONFIGURATION
3923 23:25:41.116851 ===================================
3924 23:25:41.117345 EX_ROW_EN[0] = 0x0
3925 23:25:41.120487 EX_ROW_EN[1] = 0x0
3926 23:25:41.121055 LP4Y_EN = 0x0
3927 23:25:41.123707 WORK_FSP = 0x0
3928 23:25:41.124279 WL = 0x2
3929 23:25:41.126924 RL = 0x2
3930 23:25:41.127398 BL = 0x2
3931 23:25:41.129941 RPST = 0x0
3932 23:25:41.130635 RD_PRE = 0x0
3933 23:25:41.133177 WR_PRE = 0x1
3934 23:25:41.136686 WR_PST = 0x0
3935 23:25:41.137258 DBI_WR = 0x0
3936 23:25:41.140524 DBI_RD = 0x0
3937 23:25:41.141088 OTF = 0x1
3938 23:25:41.143785 ===================================
3939 23:25:41.146336 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3940 23:25:41.153971 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3941 23:25:41.156629 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3942 23:25:41.160112 ===================================
3943 23:25:41.163627 LPDDR4 DRAM CONFIGURATION
3944 23:25:41.166661 ===================================
3945 23:25:41.167158 EX_ROW_EN[0] = 0x10
3946 23:25:41.169979 EX_ROW_EN[1] = 0x0
3947 23:25:41.170434 LP4Y_EN = 0x0
3948 23:25:41.173435 WORK_FSP = 0x0
3949 23:25:41.174048 WL = 0x2
3950 23:25:41.176714 RL = 0x2
3951 23:25:41.177320 BL = 0x2
3952 23:25:41.180155 RPST = 0x0
3953 23:25:41.180702 RD_PRE = 0x0
3954 23:25:41.183590 WR_PRE = 0x1
3955 23:25:41.184154 WR_PST = 0x0
3956 23:25:41.186512 DBI_WR = 0x0
3957 23:25:41.186966 DBI_RD = 0x0
3958 23:25:41.189982 OTF = 0x1
3959 23:25:41.194090 ===================================
3960 23:25:41.199881 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3961 23:25:41.203517 nWR fixed to 30
3962 23:25:41.206492 [ModeRegInit_LP4] CH0 RK0
3963 23:25:41.207038 [ModeRegInit_LP4] CH0 RK1
3964 23:25:41.209876 [ModeRegInit_LP4] CH1 RK0
3965 23:25:41.213047 [ModeRegInit_LP4] CH1 RK1
3966 23:25:41.213502 match AC timing 17
3967 23:25:41.219818 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3968 23:25:41.223347 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3969 23:25:41.226331 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3970 23:25:41.233140 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3971 23:25:41.236361 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3972 23:25:41.236817 ==
3973 23:25:41.239826 Dram Type= 6, Freq= 0, CH_0, rank 0
3974 23:25:41.242813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3975 23:25:41.243273 ==
3976 23:25:41.250290 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3977 23:25:41.256320 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3978 23:25:41.260220 [CA 0] Center 36 (5~67) winsize 63
3979 23:25:41.263728 [CA 1] Center 36 (5~67) winsize 63
3980 23:25:41.266455 [CA 2] Center 33 (3~64) winsize 62
3981 23:25:41.269515 [CA 3] Center 33 (2~64) winsize 63
3982 23:25:41.273117 [CA 4] Center 33 (2~64) winsize 63
3983 23:25:41.276400 [CA 5] Center 32 (2~63) winsize 62
3984 23:25:41.276952
3985 23:25:41.279206 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3986 23:25:41.279663
3987 23:25:41.283144 [CATrainingPosCal] consider 1 rank data
3988 23:25:41.286147 u2DelayCellTimex100 = 270/100 ps
3989 23:25:41.289390 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
3990 23:25:41.292922 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
3991 23:25:41.296267 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3992 23:25:41.299632 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3993 23:25:41.302555 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3994 23:25:41.309266 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3995 23:25:41.309936
3996 23:25:41.312784 CA PerBit enable=1, Macro0, CA PI delay=32
3997 23:25:41.313344
3998 23:25:41.315938 [CBTSetCACLKResult] CA Dly = 32
3999 23:25:41.316577 CS Dly: 4 (0~35)
4000 23:25:41.316938 ==
4001 23:25:41.319605 Dram Type= 6, Freq= 0, CH_0, rank 1
4002 23:25:41.322662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4003 23:25:41.326048 ==
4004 23:25:41.329420 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4005 23:25:41.335531 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4006 23:25:41.339131 [CA 0] Center 36 (5~67) winsize 63
4007 23:25:41.342415 [CA 1] Center 36 (5~67) winsize 63
4008 23:25:41.346160 [CA 2] Center 34 (3~65) winsize 63
4009 23:25:41.349682 [CA 3] Center 34 (3~65) winsize 63
4010 23:25:41.352158 [CA 4] Center 33 (2~64) winsize 63
4011 23:25:41.355927 [CA 5] Center 32 (2~63) winsize 62
4012 23:25:41.356384
4013 23:25:41.359354 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4014 23:25:41.359910
4015 23:25:41.362177 [CATrainingPosCal] consider 2 rank data
4016 23:25:41.365448 u2DelayCellTimex100 = 270/100 ps
4017 23:25:41.368830 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
4018 23:25:41.372109 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4019 23:25:41.376222 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4020 23:25:41.382418 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4021 23:25:41.386071 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4022 23:25:41.388802 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4023 23:25:41.389357
4024 23:25:41.392383 CA PerBit enable=1, Macro0, CA PI delay=32
4025 23:25:41.392837
4026 23:25:41.395830 [CBTSetCACLKResult] CA Dly = 32
4027 23:25:41.396384 CS Dly: 4 (0~36)
4028 23:25:41.396749
4029 23:25:41.398438 ----->DramcWriteLeveling(PI) begin...
4030 23:25:41.398905 ==
4031 23:25:41.402558 Dram Type= 6, Freq= 0, CH_0, rank 0
4032 23:25:41.408764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4033 23:25:41.409335 ==
4034 23:25:41.412403 Write leveling (Byte 0): 33 => 33
4035 23:25:41.415909 Write leveling (Byte 1): 32 => 32
4036 23:25:41.416463 DramcWriteLeveling(PI) end<-----
4037 23:25:41.418717
4038 23:25:41.419166 ==
4039 23:25:41.422149 Dram Type= 6, Freq= 0, CH_0, rank 0
4040 23:25:41.425533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4041 23:25:41.426161 ==
4042 23:25:41.428401 [Gating] SW mode calibration
4043 23:25:41.435573 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4044 23:25:41.438985 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4045 23:25:41.445380 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4046 23:25:41.448712 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 23:25:41.452234 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4048 23:25:41.458691 0 9 12 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
4049 23:25:41.462071 0 9 16 | B1->B0 | 2e2e 2323 | 1 0 | (1 1) (0 0)
4050 23:25:41.465761 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 23:25:41.471897 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 23:25:41.475292 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 23:25:41.479111 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 23:25:41.485444 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 23:25:41.488530 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 23:25:41.492595 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4057 23:25:41.499264 0 10 16 | B1->B0 | 3636 4646 | 0 0 | (1 1) (0 0)
4058 23:25:41.502274 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 23:25:41.505748 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 23:25:41.508937 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 23:25:41.515089 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 23:25:41.518924 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 23:25:41.522615 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 23:25:41.528506 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4065 23:25:41.531651 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4066 23:25:41.535537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 23:25:41.541981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 23:25:41.545690 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 23:25:41.548947 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 23:25:41.555335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 23:25:41.558600 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 23:25:41.561895 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 23:25:41.568701 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 23:25:41.571928 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 23:25:41.575071 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 23:25:41.582136 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:25:41.585089 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:25:41.588288 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:25:41.595210 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:25:41.598361 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4081 23:25:41.601647 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4082 23:25:41.604828 Total UI for P1: 0, mck2ui 16
4083 23:25:41.608451 best dqsien dly found for B0: ( 0, 13, 12)
4084 23:25:41.614985 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4085 23:25:41.615445 Total UI for P1: 0, mck2ui 16
4086 23:25:41.621349 best dqsien dly found for B1: ( 0, 13, 18)
4087 23:25:41.624680 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4088 23:25:41.628180 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4089 23:25:41.628691
4090 23:25:41.631848 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4091 23:25:41.635183 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4092 23:25:41.638085 [Gating] SW calibration Done
4093 23:25:41.638495 ==
4094 23:25:41.641734 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 23:25:41.644836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 23:25:41.645347 ==
4097 23:25:41.648246 RX Vref Scan: 0
4098 23:25:41.648655
4099 23:25:41.648974 RX Vref 0 -> 0, step: 1
4100 23:25:41.649271
4101 23:25:41.651474 RX Delay -230 -> 252, step: 16
4102 23:25:41.654876 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4103 23:25:41.661546 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4104 23:25:41.665081 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4105 23:25:41.667985 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4106 23:25:41.671571 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4107 23:25:41.678254 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4108 23:25:41.681639 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4109 23:25:41.684598 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4110 23:25:41.688485 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4111 23:25:41.691368 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4112 23:25:41.697910 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4113 23:25:41.701429 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4114 23:25:41.704794 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4115 23:25:41.707776 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4116 23:25:41.714399 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4117 23:25:41.717514 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4118 23:25:41.717966 ==
4119 23:25:41.721524 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 23:25:41.724383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 23:25:41.724898 ==
4122 23:25:41.727753 DQS Delay:
4123 23:25:41.728283 DQS0 = 0, DQS1 = 0
4124 23:25:41.728612 DQM Delay:
4125 23:25:41.731276 DQM0 = 49, DQM1 = 46
4126 23:25:41.731788 DQ Delay:
4127 23:25:41.734417 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4128 23:25:41.737608 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4129 23:25:41.740881 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4130 23:25:41.744577 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4131 23:25:41.745089
4132 23:25:41.745412
4133 23:25:41.747399 ==
4134 23:25:41.747980 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 23:25:41.754195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 23:25:41.754696 ==
4137 23:25:41.755195
4138 23:25:41.755566
4139 23:25:41.757863 TX Vref Scan disable
4140 23:25:41.758291 == TX Byte 0 ==
4141 23:25:41.760578 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4142 23:25:41.766995 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4143 23:25:41.767412 == TX Byte 1 ==
4144 23:25:41.773481 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4145 23:25:41.776797 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4146 23:25:41.777218 ==
4147 23:25:41.780466 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 23:25:41.783696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 23:25:41.784119 ==
4150 23:25:41.784444
4151 23:25:41.784742
4152 23:25:41.786846 TX Vref Scan disable
4153 23:25:41.789987 == TX Byte 0 ==
4154 23:25:41.793985 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4155 23:25:41.796984 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4156 23:25:41.800223 == TX Byte 1 ==
4157 23:25:41.803430 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4158 23:25:41.806678 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4159 23:25:41.807091
4160 23:25:41.810215 [DATLAT]
4161 23:25:41.810625 Freq=600, CH0 RK0
4162 23:25:41.811018
4163 23:25:41.813210 DATLAT Default: 0x9
4164 23:25:41.813653 0, 0xFFFF, sum = 0
4165 23:25:41.816725 1, 0xFFFF, sum = 0
4166 23:25:41.817142 2, 0xFFFF, sum = 0
4167 23:25:41.819981 3, 0xFFFF, sum = 0
4168 23:25:41.820403 4, 0xFFFF, sum = 0
4169 23:25:41.823241 5, 0xFFFF, sum = 0
4170 23:25:41.823794 6, 0xFFFF, sum = 0
4171 23:25:41.826687 7, 0xFFFF, sum = 0
4172 23:25:41.827104 8, 0x0, sum = 1
4173 23:25:41.830019 9, 0x0, sum = 2
4174 23:25:41.830435 10, 0x0, sum = 3
4175 23:25:41.833507 11, 0x0, sum = 4
4176 23:25:41.833972 best_step = 9
4177 23:25:41.834299
4178 23:25:41.834598 ==
4179 23:25:41.836308 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 23:25:41.842861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 23:25:41.843274 ==
4182 23:25:41.843595 RX Vref Scan: 1
4183 23:25:41.843893
4184 23:25:41.846322 RX Vref 0 -> 0, step: 1
4185 23:25:41.846735
4186 23:25:41.850314 RX Delay -163 -> 252, step: 8
4187 23:25:41.850726
4188 23:25:41.852913 Set Vref, RX VrefLevel [Byte0]: 56
4189 23:25:41.856269 [Byte1]: 55
4190 23:25:41.856683
4191 23:25:41.860058 Final RX Vref Byte 0 = 56 to rank0
4192 23:25:41.863617 Final RX Vref Byte 1 = 55 to rank0
4193 23:25:41.866920 Final RX Vref Byte 0 = 56 to rank1
4194 23:25:41.869645 Final RX Vref Byte 1 = 55 to rank1==
4195 23:25:41.873099 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 23:25:41.876739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 23:25:41.877251 ==
4198 23:25:41.879698 DQS Delay:
4199 23:25:41.880212 DQS0 = 0, DQS1 = 0
4200 23:25:41.880538 DQM Delay:
4201 23:25:41.883133 DQM0 = 52, DQM1 = 47
4202 23:25:41.883655 DQ Delay:
4203 23:25:41.886204 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4204 23:25:41.889469 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4205 23:25:41.893075 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =40
4206 23:25:41.895895 DQ12 =56, DQ13 =52, DQ14 =56, DQ15 =52
4207 23:25:41.896307
4208 23:25:41.896628
4209 23:25:41.905881 [DQSOSCAuto] RK0, (LSB)MR18= 0x7265, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4210 23:25:41.909489 CH0 RK0: MR19=808, MR18=7265
4211 23:25:41.912704 CH0_RK0: MR19=0x808, MR18=0x7265, DQSOSC=388, MR23=63, INC=174, DEC=116
4212 23:25:41.913124
4213 23:25:41.916190 ----->DramcWriteLeveling(PI) begin...
4214 23:25:41.919358 ==
4215 23:25:41.922641 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 23:25:41.925996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 23:25:41.926514 ==
4218 23:25:41.929765 Write leveling (Byte 0): 35 => 35
4219 23:25:41.932680 Write leveling (Byte 1): 31 => 31
4220 23:25:41.935886 DramcWriteLeveling(PI) end<-----
4221 23:25:41.936363
4222 23:25:41.936801 ==
4223 23:25:41.939604 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 23:25:41.942417 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 23:25:41.942900 ==
4226 23:25:41.945701 [Gating] SW mode calibration
4227 23:25:41.952810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 23:25:41.955871 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 23:25:41.963246 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 23:25:41.966081 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 23:25:41.969132 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 23:25:41.976285 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4233 23:25:41.979531 0 9 16 | B1->B0 | 2727 2828 | 0 0 | (0 0) (0 0)
4234 23:25:41.983236 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 23:25:41.989002 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 23:25:41.992633 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 23:25:41.996070 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 23:25:42.002558 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 23:25:42.005557 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 23:25:42.008913 0 10 12 | B1->B0 | 2929 2929 | 0 0 | (0 0) (0 0)
4241 23:25:42.015727 0 10 16 | B1->B0 | 4141 4242 | 0 0 | (0 0) (0 0)
4242 23:25:42.019072 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 23:25:42.022210 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 23:25:42.029158 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 23:25:42.032467 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 23:25:42.035356 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 23:25:42.042302 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 23:25:42.046021 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 23:25:42.048978 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 23:25:42.055580 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 23:25:42.059251 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 23:25:42.062176 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 23:25:42.068734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 23:25:42.072396 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 23:25:42.076030 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 23:25:42.081922 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 23:25:42.085409 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 23:25:42.089276 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 23:25:42.095445 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:25:42.098593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:25:42.102561 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:25:42.108758 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:25:42.111761 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:25:42.115295 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4265 23:25:42.118331 Total UI for P1: 0, mck2ui 16
4266 23:25:42.121750 best dqsien dly found for B0: ( 0, 13, 10)
4267 23:25:42.125319 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4268 23:25:42.132004 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4269 23:25:42.135461 Total UI for P1: 0, mck2ui 16
4270 23:25:42.138769 best dqsien dly found for B1: ( 0, 13, 14)
4271 23:25:42.141896 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4272 23:25:42.145034 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4273 23:25:42.145519
4274 23:25:42.148765 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4275 23:25:42.152234 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4276 23:25:42.154789 [Gating] SW calibration Done
4277 23:25:42.155242 ==
4278 23:25:42.158436 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 23:25:42.161673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 23:25:42.162239 ==
4281 23:25:42.165626 RX Vref Scan: 0
4282 23:25:42.166188
4283 23:25:42.168619 RX Vref 0 -> 0, step: 1
4284 23:25:42.169169
4285 23:25:42.169542 RX Delay -230 -> 252, step: 16
4286 23:25:42.175027 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4287 23:25:42.178349 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4288 23:25:42.181779 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4289 23:25:42.185187 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4290 23:25:42.191480 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4291 23:25:42.194614 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4292 23:25:42.198361 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4293 23:25:42.201716 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4294 23:25:42.204898 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4295 23:25:42.211700 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4296 23:25:42.215151 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4297 23:25:42.218561 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4298 23:25:42.221374 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4299 23:25:42.228153 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4300 23:25:42.231196 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4301 23:25:42.234249 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4302 23:25:42.234705 ==
4303 23:25:42.237651 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 23:25:42.244711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 23:25:42.245268 ==
4306 23:25:42.245687 DQS Delay:
4307 23:25:42.246087 DQS0 = 0, DQS1 = 0
4308 23:25:42.248527 DQM Delay:
4309 23:25:42.249081 DQM0 = 51, DQM1 = 43
4310 23:25:42.251274 DQ Delay:
4311 23:25:42.254118 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4312 23:25:42.257670 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =65
4313 23:25:42.258196 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4314 23:25:42.260963 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4315 23:25:42.264402
4316 23:25:42.264837
4317 23:25:42.265156 ==
4318 23:25:42.267453 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 23:25:42.270852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 23:25:42.271265 ==
4321 23:25:42.271583
4322 23:25:42.271878
4323 23:25:42.274374 TX Vref Scan disable
4324 23:25:42.274887 == TX Byte 0 ==
4325 23:25:42.281144 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4326 23:25:42.284756 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4327 23:25:42.285272 == TX Byte 1 ==
4328 23:25:42.291011 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4329 23:25:42.294026 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4330 23:25:42.294439 ==
4331 23:25:42.297758 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 23:25:42.301227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 23:25:42.301800 ==
4334 23:25:42.302135
4335 23:25:42.304530
4336 23:25:42.305068 TX Vref Scan disable
4337 23:25:42.307498 == TX Byte 0 ==
4338 23:25:42.310601 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4339 23:25:42.317844 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4340 23:25:42.318355 == TX Byte 1 ==
4341 23:25:42.320881 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4342 23:25:42.327554 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4343 23:25:42.328067
4344 23:25:42.328389 [DATLAT]
4345 23:25:42.328684 Freq=600, CH0 RK1
4346 23:25:42.328974
4347 23:25:42.331080 DATLAT Default: 0x9
4348 23:25:42.331489 0, 0xFFFF, sum = 0
4349 23:25:42.334600 1, 0xFFFF, sum = 0
4350 23:25:42.335121 2, 0xFFFF, sum = 0
4351 23:25:42.337155 3, 0xFFFF, sum = 0
4352 23:25:42.337824 4, 0xFFFF, sum = 0
4353 23:25:42.341061 5, 0xFFFF, sum = 0
4354 23:25:42.344501 6, 0xFFFF, sum = 0
4355 23:25:42.345102 7, 0xFFFF, sum = 0
4356 23:25:42.345443 8, 0x0, sum = 1
4357 23:25:42.347506 9, 0x0, sum = 2
4358 23:25:42.348036 10, 0x0, sum = 3
4359 23:25:42.350757 11, 0x0, sum = 4
4360 23:25:42.351182 best_step = 9
4361 23:25:42.351509
4362 23:25:42.351809 ==
4363 23:25:42.353929 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 23:25:42.360662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 23:25:42.361075 ==
4366 23:25:42.361399 RX Vref Scan: 0
4367 23:25:42.361750
4368 23:25:42.363817 RX Vref 0 -> 0, step: 1
4369 23:25:42.364225
4370 23:25:42.367306 RX Delay -163 -> 252, step: 8
4371 23:25:42.370554 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4372 23:25:42.373870 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4373 23:25:42.380943 iDelay=197, Bit 2, Center 52 (-91 ~ 196) 288
4374 23:25:42.384366 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4375 23:25:42.387499 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4376 23:25:42.390350 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4377 23:25:42.394111 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4378 23:25:42.400516 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4379 23:25:42.403930 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4380 23:25:42.407561 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4381 23:25:42.410645 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4382 23:25:42.417171 iDelay=197, Bit 11, Center 40 (-99 ~ 180) 280
4383 23:25:42.420542 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4384 23:25:42.424165 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4385 23:25:42.427572 iDelay=197, Bit 14, Center 56 (-83 ~ 196) 280
4386 23:25:42.431115 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4387 23:25:42.431621 ==
4388 23:25:42.433965 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 23:25:42.441065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 23:25:42.441569 ==
4391 23:25:42.441956 DQS Delay:
4392 23:25:42.444354 DQS0 = 0, DQS1 = 0
4393 23:25:42.444855 DQM Delay:
4394 23:25:42.445175 DQM0 = 52, DQM1 = 46
4395 23:25:42.447724 DQ Delay:
4396 23:25:42.451018 DQ0 =52, DQ1 =52, DQ2 =52, DQ3 =52
4397 23:25:42.453834 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4398 23:25:42.457732 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4399 23:25:42.460585 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4400 23:25:42.461014
4401 23:25:42.461379
4402 23:25:42.467345 [DQSOSCAuto] RK1, (LSB)MR18= 0x6324, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4403 23:25:42.470373 CH0 RK1: MR19=808, MR18=6324
4404 23:25:42.476784 CH0_RK1: MR19=0x808, MR18=0x6324, DQSOSC=391, MR23=63, INC=171, DEC=114
4405 23:25:42.480839 [RxdqsGatingPostProcess] freq 600
4406 23:25:42.483877 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 23:25:42.487424 Pre-setting of DQS Precalculation
4408 23:25:42.493814 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4409 23:25:42.494372 ==
4410 23:25:42.497169 Dram Type= 6, Freq= 0, CH_1, rank 0
4411 23:25:42.500729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4412 23:25:42.501282 ==
4413 23:25:42.506696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4414 23:25:42.513536 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4415 23:25:42.516675 [CA 0] Center 36 (5~67) winsize 63
4416 23:25:42.520550 [CA 1] Center 36 (5~67) winsize 63
4417 23:25:42.523294 [CA 2] Center 35 (4~66) winsize 63
4418 23:25:42.526995 [CA 3] Center 34 (4~65) winsize 62
4419 23:25:42.530090 [CA 4] Center 34 (4~65) winsize 62
4420 23:25:42.533209 [CA 5] Center 33 (3~64) winsize 62
4421 23:25:42.533721
4422 23:25:42.537047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4423 23:25:42.537667
4424 23:25:42.540178 [CATrainingPosCal] consider 1 rank data
4425 23:25:42.543651 u2DelayCellTimex100 = 270/100 ps
4426 23:25:42.546888 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4427 23:25:42.550550 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4428 23:25:42.553504 CA2 delay=35 (4~66),Diff = 2 PI (19 cell)
4429 23:25:42.556951 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 23:25:42.560534 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4431 23:25:42.563827 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4432 23:25:42.564345
4433 23:25:42.570056 CA PerBit enable=1, Macro0, CA PI delay=33
4434 23:25:42.570638
4435 23:25:42.571057 [CBTSetCACLKResult] CA Dly = 33
4436 23:25:42.573533 CS Dly: 6 (0~37)
4437 23:25:42.574011 ==
4438 23:25:42.576330 Dram Type= 6, Freq= 0, CH_1, rank 1
4439 23:25:42.580248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4440 23:25:42.580766 ==
4441 23:25:42.586704 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4442 23:25:42.593758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4443 23:25:42.597314 [CA 0] Center 36 (5~67) winsize 63
4444 23:25:42.600193 [CA 1] Center 36 (5~67) winsize 63
4445 23:25:42.603769 [CA 2] Center 34 (4~65) winsize 62
4446 23:25:42.607025 [CA 3] Center 34 (4~65) winsize 62
4447 23:25:42.610567 [CA 4] Center 34 (4~65) winsize 62
4448 23:25:42.613335 [CA 5] Center 33 (3~64) winsize 62
4449 23:25:42.613807
4450 23:25:42.616437 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4451 23:25:42.616851
4452 23:25:42.619780 [CATrainingPosCal] consider 2 rank data
4453 23:25:42.623415 u2DelayCellTimex100 = 270/100 ps
4454 23:25:42.626451 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4455 23:25:42.629375 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4456 23:25:42.633686 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 23:25:42.636532 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 23:25:42.639515 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4459 23:25:42.646163 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4460 23:25:42.646662
4461 23:25:42.649572 CA PerBit enable=1, Macro0, CA PI delay=33
4462 23:25:42.650127
4463 23:25:42.652775 [CBTSetCACLKResult] CA Dly = 33
4464 23:25:42.653185 CS Dly: 6 (0~38)
4465 23:25:42.653501
4466 23:25:42.656230 ----->DramcWriteLeveling(PI) begin...
4467 23:25:42.656750 ==
4468 23:25:42.659950 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 23:25:42.666571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 23:25:42.667085 ==
4471 23:25:42.669275 Write leveling (Byte 0): 29 => 29
4472 23:25:42.669741 Write leveling (Byte 1): 30 => 30
4473 23:25:42.673338 DramcWriteLeveling(PI) end<-----
4474 23:25:42.673936
4475 23:25:42.674271 ==
4476 23:25:42.676135 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 23:25:42.682964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 23:25:42.683477 ==
4479 23:25:42.686129 [Gating] SW mode calibration
4480 23:25:42.692676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4481 23:25:42.696298 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4482 23:25:42.703125 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 23:25:42.706405 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 23:25:42.709692 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4485 23:25:42.715868 0 9 12 | B1->B0 | 2e2e 2e2e | 1 0 | (1 1) (1 0)
4486 23:25:42.719491 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 23:25:42.722714 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 23:25:42.729542 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 23:25:42.732700 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 23:25:42.735888 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 23:25:42.738846 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 23:25:42.746260 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 23:25:42.749609 0 10 12 | B1->B0 | 3838 3737 | 0 0 | (0 0) (1 1)
4494 23:25:42.752534 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 23:25:42.759414 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 23:25:42.762486 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 23:25:42.765724 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 23:25:42.772822 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 23:25:42.775951 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 23:25:42.779138 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 23:25:42.786524 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4502 23:25:42.789453 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 23:25:42.792482 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 23:25:42.799503 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 23:25:42.802563 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 23:25:42.805686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 23:25:42.812016 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 23:25:42.815202 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 23:25:42.818980 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:25:42.825479 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:25:42.829101 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:25:42.832066 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:25:42.839172 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:25:42.842403 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:25:42.845510 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:25:42.852373 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4517 23:25:42.855751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4518 23:25:42.859114 Total UI for P1: 0, mck2ui 16
4519 23:25:42.862153 best dqsien dly found for B1: ( 0, 13, 8)
4520 23:25:42.865664 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4521 23:25:42.868956 Total UI for P1: 0, mck2ui 16
4522 23:25:42.872153 best dqsien dly found for B0: ( 0, 13, 10)
4523 23:25:42.875560 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4524 23:25:42.879002 best DQS1 dly(MCK, UI, PI) = (0, 13, 8)
4525 23:25:42.879415
4526 23:25:42.882531 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4527 23:25:42.885477 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 8)
4528 23:25:42.889549 [Gating] SW calibration Done
4529 23:25:42.890109 ==
4530 23:25:42.892240 Dram Type= 6, Freq= 0, CH_1, rank 0
4531 23:25:42.899207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4532 23:25:42.899789 ==
4533 23:25:42.900154 RX Vref Scan: 0
4534 23:25:42.900489
4535 23:25:42.901887 RX Vref 0 -> 0, step: 1
4536 23:25:42.902352
4537 23:25:42.905636 RX Delay -230 -> 252, step: 16
4538 23:25:42.909067 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4539 23:25:42.912169 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4540 23:25:42.915034 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4541 23:25:42.922546 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4542 23:25:42.925040 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4543 23:25:42.928632 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4544 23:25:42.931508 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4545 23:25:42.938452 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4546 23:25:42.941834 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4547 23:25:42.945343 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4548 23:25:42.948758 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4549 23:25:42.955495 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4550 23:25:42.958393 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4551 23:25:42.961883 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4552 23:25:42.965006 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4553 23:25:42.968940 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4554 23:25:42.971393 ==
4555 23:25:42.975274 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 23:25:42.978273 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 23:25:42.978752 ==
4558 23:25:42.979111 DQS Delay:
4559 23:25:42.981546 DQS0 = 0, DQS1 = 0
4560 23:25:42.982165 DQM Delay:
4561 23:25:42.984752 DQM0 = 52, DQM1 = 49
4562 23:25:42.985222 DQ Delay:
4563 23:25:42.988669 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4564 23:25:42.991784 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4565 23:25:42.995522 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4566 23:25:42.998241 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4567 23:25:42.998790
4568 23:25:42.999223
4569 23:25:42.999561 ==
4570 23:25:43.001895 Dram Type= 6, Freq= 0, CH_1, rank 0
4571 23:25:43.005160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4572 23:25:43.005747 ==
4573 23:25:43.006112
4574 23:25:43.006438
4575 23:25:43.008023 TX Vref Scan disable
4576 23:25:43.011886 == TX Byte 0 ==
4577 23:25:43.015071 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4578 23:25:43.017940 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4579 23:25:43.021450 == TX Byte 1 ==
4580 23:25:43.024794 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4581 23:25:43.028171 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4582 23:25:43.028725 ==
4583 23:25:43.031481 Dram Type= 6, Freq= 0, CH_1, rank 0
4584 23:25:43.038067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4585 23:25:43.038606 ==
4586 23:25:43.039109
4587 23:25:43.039450
4588 23:25:43.039767 TX Vref Scan disable
4589 23:25:43.042021 == TX Byte 0 ==
4590 23:25:43.045685 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4591 23:25:43.052614 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4592 23:25:43.053172 == TX Byte 1 ==
4593 23:25:43.055799 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4594 23:25:43.062165 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4595 23:25:43.062729
4596 23:25:43.063086 [DATLAT]
4597 23:25:43.063414 Freq=600, CH1 RK0
4598 23:25:43.063730
4599 23:25:43.065270 DATLAT Default: 0x9
4600 23:25:43.065778 0, 0xFFFF, sum = 0
4601 23:25:43.068420 1, 0xFFFF, sum = 0
4602 23:25:43.071578 2, 0xFFFF, sum = 0
4603 23:25:43.072046 3, 0xFFFF, sum = 0
4604 23:25:43.075047 4, 0xFFFF, sum = 0
4605 23:25:43.075639 5, 0xFFFF, sum = 0
4606 23:25:43.078581 6, 0xFFFF, sum = 0
4607 23:25:43.079135 7, 0xFFFF, sum = 0
4608 23:25:43.081550 8, 0x0, sum = 1
4609 23:25:43.082059 9, 0x0, sum = 2
4610 23:25:43.082505 10, 0x0, sum = 3
4611 23:25:43.084977 11, 0x0, sum = 4
4612 23:25:43.085537 best_step = 9
4613 23:25:43.086016
4614 23:25:43.086355 ==
4615 23:25:43.088605 Dram Type= 6, Freq= 0, CH_1, rank 0
4616 23:25:43.095765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 23:25:43.096329 ==
4618 23:25:43.096690 RX Vref Scan: 1
4619 23:25:43.097022
4620 23:25:43.098455 RX Vref 0 -> 0, step: 1
4621 23:25:43.098912
4622 23:25:43.101698 RX Delay -147 -> 252, step: 8
4623 23:25:43.102158
4624 23:25:43.105036 Set Vref, RX VrefLevel [Byte0]: 54
4625 23:25:43.108540 [Byte1]: 54
4626 23:25:43.109088
4627 23:25:43.111827 Final RX Vref Byte 0 = 54 to rank0
4628 23:25:43.114815 Final RX Vref Byte 1 = 54 to rank0
4629 23:25:43.118528 Final RX Vref Byte 0 = 54 to rank1
4630 23:25:43.121827 Final RX Vref Byte 1 = 54 to rank1==
4631 23:25:43.125024 Dram Type= 6, Freq= 0, CH_1, rank 0
4632 23:25:43.128229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4633 23:25:43.128778 ==
4634 23:25:43.131439 DQS Delay:
4635 23:25:43.131994 DQS0 = 0, DQS1 = 0
4636 23:25:43.134733 DQM Delay:
4637 23:25:43.135279 DQM0 = 48, DQM1 = 45
4638 23:25:43.135636 DQ Delay:
4639 23:25:43.137934 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =48
4640 23:25:43.141965 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4641 23:25:43.144999 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4642 23:25:43.148265 DQ12 =52, DQ13 =52, DQ14 =56, DQ15 =52
4643 23:25:43.148812
4644 23:25:43.149164
4645 23:25:43.158044 [DQSOSCAuto] RK0, (LSB)MR18= 0x4368, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
4646 23:25:43.161705 CH1 RK0: MR19=808, MR18=4368
4647 23:25:43.164774 CH1_RK0: MR19=0x808, MR18=0x4368, DQSOSC=390, MR23=63, INC=172, DEC=114
4648 23:25:43.168137
4649 23:25:43.171450 ----->DramcWriteLeveling(PI) begin...
4650 23:25:43.171916 ==
4651 23:25:43.174956 Dram Type= 6, Freq= 0, CH_1, rank 1
4652 23:25:43.177906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4653 23:25:43.178365 ==
4654 23:25:43.181449 Write leveling (Byte 0): 30 => 30
4655 23:25:43.184625 Write leveling (Byte 1): 30 => 30
4656 23:25:43.187768 DramcWriteLeveling(PI) end<-----
4657 23:25:43.188227
4658 23:25:43.188583 ==
4659 23:25:43.191825 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 23:25:43.195092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 23:25:43.195664 ==
4662 23:25:43.198360 [Gating] SW mode calibration
4663 23:25:43.204746 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4664 23:25:43.211218 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4665 23:25:43.214327 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 23:25:43.217745 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 23:25:43.224969 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4668 23:25:43.227623 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (0 0) (0 0)
4669 23:25:43.230667 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 23:25:43.237813 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 23:25:43.241285 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 23:25:43.244640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 23:25:43.251541 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 23:25:43.254261 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4675 23:25:43.257519 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4676 23:25:43.264266 0 10 12 | B1->B0 | 3737 3636 | 0 0 | (1 1) (0 0)
4677 23:25:43.267859 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 23:25:43.270650 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 23:25:43.277783 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 23:25:43.281162 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 23:25:43.284616 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 23:25:43.287863 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 23:25:43.293977 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4684 23:25:43.297201 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4685 23:25:43.300648 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 23:25:43.307831 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 23:25:43.310869 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 23:25:43.314158 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 23:25:43.320575 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 23:25:43.323919 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 23:25:43.327224 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 23:25:43.333985 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 23:25:43.337221 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:25:43.340392 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:25:43.347536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:25:43.350555 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:25:43.353782 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:25:43.360802 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:25:43.363512 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:25:43.367594 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4701 23:25:43.373668 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4702 23:25:43.374222 Total UI for P1: 0, mck2ui 16
4703 23:25:43.380546 best dqsien dly found for B1: ( 0, 13, 12)
4704 23:25:43.383918 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4705 23:25:43.387071 Total UI for P1: 0, mck2ui 16
4706 23:25:43.390610 best dqsien dly found for B0: ( 0, 13, 14)
4707 23:25:43.394357 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4708 23:25:43.397054 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4709 23:25:43.397710
4710 23:25:43.400705 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4711 23:25:43.403435 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4712 23:25:43.406849 [Gating] SW calibration Done
4713 23:25:43.407437 ==
4714 23:25:43.410208 Dram Type= 6, Freq= 0, CH_1, rank 1
4715 23:25:43.413653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4716 23:25:43.417227 ==
4717 23:25:43.417839 RX Vref Scan: 0
4718 23:25:43.418209
4719 23:25:43.419943 RX Vref 0 -> 0, step: 1
4720 23:25:43.420405
4721 23:25:43.423631 RX Delay -230 -> 252, step: 16
4722 23:25:43.426711 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4723 23:25:43.430332 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4724 23:25:43.433629 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4725 23:25:43.440027 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4726 23:25:43.443040 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4727 23:25:43.446230 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4728 23:25:43.450055 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4729 23:25:43.453344 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4730 23:25:43.459920 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4731 23:25:43.463408 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4732 23:25:43.466373 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4733 23:25:43.470484 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4734 23:25:43.476745 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4735 23:25:43.480102 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4736 23:25:43.482752 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4737 23:25:43.486481 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4738 23:25:43.486892 ==
4739 23:25:43.489456 Dram Type= 6, Freq= 0, CH_1, rank 1
4740 23:25:43.496619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4741 23:25:43.497158 ==
4742 23:25:43.497485 DQS Delay:
4743 23:25:43.499576 DQS0 = 0, DQS1 = 0
4744 23:25:43.499985 DQM Delay:
4745 23:25:43.500474 DQM0 = 50, DQM1 = 47
4746 23:25:43.502837 DQ Delay:
4747 23:25:43.506323 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4748 23:25:43.510008 DQ4 =49, DQ5 =65, DQ6 =57, DQ7 =49
4749 23:25:43.512833 DQ8 =33, DQ9 =41, DQ10 =41, DQ11 =41
4750 23:25:43.516202 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4751 23:25:43.516618
4752 23:25:43.516938
4753 23:25:43.517233 ==
4754 23:25:43.519186 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 23:25:43.523017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 23:25:43.523432 ==
4757 23:25:43.523754
4758 23:25:43.524047
4759 23:25:43.526189 TX Vref Scan disable
4760 23:25:43.529304 == TX Byte 0 ==
4761 23:25:43.533280 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4762 23:25:43.536005 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4763 23:25:43.539593 == TX Byte 1 ==
4764 23:25:43.542758 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4765 23:25:43.545704 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4766 23:25:43.546124 ==
4767 23:25:43.549546 Dram Type= 6, Freq= 0, CH_1, rank 1
4768 23:25:43.552901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4769 23:25:43.553405 ==
4770 23:25:43.556092
4771 23:25:43.556605
4772 23:25:43.556935 TX Vref Scan disable
4773 23:25:43.559582 == TX Byte 0 ==
4774 23:25:43.562854 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4775 23:25:43.569538 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4776 23:25:43.570038 == TX Byte 1 ==
4777 23:25:43.573547 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4778 23:25:43.579636 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4779 23:25:43.580188
4780 23:25:43.580558 [DATLAT]
4781 23:25:43.580914 Freq=600, CH1 RK1
4782 23:25:43.581234
4783 23:25:43.582699 DATLAT Default: 0x9
4784 23:25:43.583152 0, 0xFFFF, sum = 0
4785 23:25:43.586413 1, 0xFFFF, sum = 0
4786 23:25:43.590133 2, 0xFFFF, sum = 0
4787 23:25:43.590693 3, 0xFFFF, sum = 0
4788 23:25:43.592786 4, 0xFFFF, sum = 0
4789 23:25:43.593349 5, 0xFFFF, sum = 0
4790 23:25:43.596282 6, 0xFFFF, sum = 0
4791 23:25:43.596740 7, 0xFFFF, sum = 0
4792 23:25:43.600066 8, 0x0, sum = 1
4793 23:25:43.600658 9, 0x0, sum = 2
4794 23:25:43.601031 10, 0x0, sum = 3
4795 23:25:43.603015 11, 0x0, sum = 4
4796 23:25:43.603481 best_step = 9
4797 23:25:43.603836
4798 23:25:43.604164 ==
4799 23:25:43.606258 Dram Type= 6, Freq= 0, CH_1, rank 1
4800 23:25:43.612982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4801 23:25:43.613536 ==
4802 23:25:43.613964 RX Vref Scan: 0
4803 23:25:43.614300
4804 23:25:43.615865 RX Vref 0 -> 0, step: 1
4805 23:25:43.616320
4806 23:25:43.619228 RX Delay -163 -> 252, step: 8
4807 23:25:43.623238 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4808 23:25:43.629273 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4809 23:25:43.632768 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4810 23:25:43.636495 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4811 23:25:43.639497 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4812 23:25:43.642687 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4813 23:25:43.649747 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4814 23:25:43.652459 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4815 23:25:43.656198 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4816 23:25:43.659345 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4817 23:25:43.662644 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4818 23:25:43.669668 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4819 23:25:43.672385 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4820 23:25:43.675750 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4821 23:25:43.679115 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4822 23:25:43.685924 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4823 23:25:43.686436 ==
4824 23:25:43.689210 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 23:25:43.692332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 23:25:43.692846 ==
4827 23:25:43.693168 DQS Delay:
4828 23:25:43.695574 DQS0 = 0, DQS1 = 0
4829 23:25:43.695983 DQM Delay:
4830 23:25:43.698645 DQM0 = 48, DQM1 = 45
4831 23:25:43.699053 DQ Delay:
4832 23:25:43.701996 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4833 23:25:43.705528 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4834 23:25:43.708801 DQ8 =28, DQ9 =32, DQ10 =48, DQ11 =40
4835 23:25:43.711891 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4836 23:25:43.712303
4837 23:25:43.712623
4838 23:25:43.719299 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4839 23:25:43.722034 CH1 RK1: MR19=808, MR18=6C24
4840 23:25:43.728882 CH1_RK1: MR19=0x808, MR18=0x6C24, DQSOSC=389, MR23=63, INC=173, DEC=115
4841 23:25:43.731813 [RxdqsGatingPostProcess] freq 600
4842 23:25:43.738577 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4843 23:25:43.742181 Pre-setting of DQS Precalculation
4844 23:25:43.745738 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4845 23:25:43.752019 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4846 23:25:43.758464 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4847 23:25:43.758981
4848 23:25:43.759305
4849 23:25:43.762053 [Calibration Summary] 1200 Mbps
4850 23:25:43.765425 CH 0, Rank 0
4851 23:25:43.765987 SW Impedance : PASS
4852 23:25:43.768666 DUTY Scan : NO K
4853 23:25:43.771990 ZQ Calibration : PASS
4854 23:25:43.772500 Jitter Meter : NO K
4855 23:25:43.775564 CBT Training : PASS
4856 23:25:43.778966 Write leveling : PASS
4857 23:25:43.779474 RX DQS gating : PASS
4858 23:25:43.782209 RX DQ/DQS(RDDQC) : PASS
4859 23:25:43.782723 TX DQ/DQS : PASS
4860 23:25:43.785389 RX DATLAT : PASS
4861 23:25:43.788600 RX DQ/DQS(Engine): PASS
4862 23:25:43.789011 TX OE : NO K
4863 23:25:43.792399 All Pass.
4864 23:25:43.792905
4865 23:25:43.793233 CH 0, Rank 1
4866 23:25:43.795482 SW Impedance : PASS
4867 23:25:43.795992 DUTY Scan : NO K
4868 23:25:43.798765 ZQ Calibration : PASS
4869 23:25:43.802011 Jitter Meter : NO K
4870 23:25:43.802566 CBT Training : PASS
4871 23:25:43.805632 Write leveling : PASS
4872 23:25:43.808665 RX DQS gating : PASS
4873 23:25:43.809076 RX DQ/DQS(RDDQC) : PASS
4874 23:25:43.811724 TX DQ/DQS : PASS
4875 23:25:43.815174 RX DATLAT : PASS
4876 23:25:43.815588 RX DQ/DQS(Engine): PASS
4877 23:25:43.818654 TX OE : NO K
4878 23:25:43.819160 All Pass.
4879 23:25:43.819484
4880 23:25:43.822155 CH 1, Rank 0
4881 23:25:43.822667 SW Impedance : PASS
4882 23:25:43.824922 DUTY Scan : NO K
4883 23:25:43.828500 ZQ Calibration : PASS
4884 23:25:43.828912 Jitter Meter : NO K
4885 23:25:43.832260 CBT Training : PASS
4886 23:25:43.832775 Write leveling : PASS
4887 23:25:43.835391 RX DQS gating : PASS
4888 23:25:43.838303 RX DQ/DQS(RDDQC) : PASS
4889 23:25:43.838862 TX DQ/DQS : PASS
4890 23:25:43.841713 RX DATLAT : PASS
4891 23:25:43.844941 RX DQ/DQS(Engine): PASS
4892 23:25:43.845352 TX OE : NO K
4893 23:25:43.848551 All Pass.
4894 23:25:43.848962
4895 23:25:43.849283 CH 1, Rank 1
4896 23:25:43.851705 SW Impedance : PASS
4897 23:25:43.852117 DUTY Scan : NO K
4898 23:25:43.855247 ZQ Calibration : PASS
4899 23:25:43.858475 Jitter Meter : NO K
4900 23:25:43.858986 CBT Training : PASS
4901 23:25:43.861969 Write leveling : PASS
4902 23:25:43.865185 RX DQS gating : PASS
4903 23:25:43.865651 RX DQ/DQS(RDDQC) : PASS
4904 23:25:43.868388 TX DQ/DQS : PASS
4905 23:25:43.868825 RX DATLAT : PASS
4906 23:25:43.871881 RX DQ/DQS(Engine): PASS
4907 23:25:43.875135 TX OE : NO K
4908 23:25:43.875547 All Pass.
4909 23:25:43.875868
4910 23:25:43.878551 DramC Write-DBI off
4911 23:25:43.878963 PER_BANK_REFRESH: Hybrid Mode
4912 23:25:43.881868 TX_TRACKING: ON
4913 23:25:43.891552 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4914 23:25:43.895282 [FAST_K] Save calibration result to emmc
4915 23:25:43.898365 dramc_set_vcore_voltage set vcore to 662500
4916 23:25:43.898870 Read voltage for 933, 3
4917 23:25:43.901479 Vio18 = 0
4918 23:25:43.902171 Vcore = 662500
4919 23:25:43.902508 Vdram = 0
4920 23:25:43.905143 Vddq = 0
4921 23:25:43.905694 Vmddr = 0
4922 23:25:43.908430 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4923 23:25:43.915263 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4924 23:25:43.918550 MEM_TYPE=3, freq_sel=17
4925 23:25:43.921680 sv_algorithm_assistance_LP4_1600
4926 23:25:43.924948 ============ PULL DRAM RESETB DOWN ============
4927 23:25:43.928781 ========== PULL DRAM RESETB DOWN end =========
4928 23:25:43.935129 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4929 23:25:43.938512 ===================================
4930 23:25:43.938929 LPDDR4 DRAM CONFIGURATION
4931 23:25:43.941600 ===================================
4932 23:25:43.945474 EX_ROW_EN[0] = 0x0
4933 23:25:43.946054 EX_ROW_EN[1] = 0x0
4934 23:25:43.948500 LP4Y_EN = 0x0
4935 23:25:43.948991 WORK_FSP = 0x0
4936 23:25:43.951724 WL = 0x3
4937 23:25:43.955313 RL = 0x3
4938 23:25:43.955820 BL = 0x2
4939 23:25:43.958042 RPST = 0x0
4940 23:25:43.958450 RD_PRE = 0x0
4941 23:25:43.961416 WR_PRE = 0x1
4942 23:25:43.961927 WR_PST = 0x0
4943 23:25:43.964790 DBI_WR = 0x0
4944 23:25:43.965288 DBI_RD = 0x0
4945 23:25:43.968281 OTF = 0x1
4946 23:25:43.971366 ===================================
4947 23:25:43.974761 ===================================
4948 23:25:43.975172 ANA top config
4949 23:25:43.978243 ===================================
4950 23:25:43.981830 DLL_ASYNC_EN = 0
4951 23:25:43.984713 ALL_SLAVE_EN = 1
4952 23:25:43.985225 NEW_RANK_MODE = 1
4953 23:25:43.988413 DLL_IDLE_MODE = 1
4954 23:25:43.991746 LP45_APHY_COMB_EN = 1
4955 23:25:43.994734 TX_ODT_DIS = 1
4956 23:25:43.998484 NEW_8X_MODE = 1
4957 23:25:44.001280 ===================================
4958 23:25:44.001734 ===================================
4959 23:25:44.005238 data_rate = 1866
4960 23:25:44.008613 CKR = 1
4961 23:25:44.011905 DQ_P2S_RATIO = 8
4962 23:25:44.014645 ===================================
4963 23:25:44.018112 CA_P2S_RATIO = 8
4964 23:25:44.021776 DQ_CA_OPEN = 0
4965 23:25:44.025026 DQ_SEMI_OPEN = 0
4966 23:25:44.025481 CA_SEMI_OPEN = 0
4967 23:25:44.028655 CA_FULL_RATE = 0
4968 23:25:44.031580 DQ_CKDIV4_EN = 1
4969 23:25:44.034631 CA_CKDIV4_EN = 1
4970 23:25:44.038266 CA_PREDIV_EN = 0
4971 23:25:44.038822 PH8_DLY = 0
4972 23:25:44.041761 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4973 23:25:44.044931 DQ_AAMCK_DIV = 4
4974 23:25:44.047677 CA_AAMCK_DIV = 4
4975 23:25:44.051684 CA_ADMCK_DIV = 4
4976 23:25:44.054390 DQ_TRACK_CA_EN = 0
4977 23:25:44.057953 CA_PICK = 933
4978 23:25:44.058503 CA_MCKIO = 933
4979 23:25:44.061936 MCKIO_SEMI = 0
4980 23:25:44.064508 PLL_FREQ = 3732
4981 23:25:44.068172 DQ_UI_PI_RATIO = 32
4982 23:25:44.070963 CA_UI_PI_RATIO = 0
4983 23:25:44.075221 ===================================
4984 23:25:44.077818 ===================================
4985 23:25:44.081766 memory_type:LPDDR4
4986 23:25:44.082328 GP_NUM : 10
4987 23:25:44.084624 SRAM_EN : 1
4988 23:25:44.085174 MD32_EN : 0
4989 23:25:44.087868 ===================================
4990 23:25:44.091074 [ANA_INIT] >>>>>>>>>>>>>>
4991 23:25:44.094566 <<<<<< [CONFIGURE PHASE]: ANA_TX
4992 23:25:44.098019 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4993 23:25:44.101176 ===================================
4994 23:25:44.104423 data_rate = 1866,PCW = 0X8f00
4995 23:25:44.108018 ===================================
4996 23:25:44.110974 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4997 23:25:44.117273 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4998 23:25:44.120981 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4999 23:25:44.127663 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5000 23:25:44.131473 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5001 23:25:44.134220 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5002 23:25:44.134694 [ANA_INIT] flow start
5003 23:25:44.137484 [ANA_INIT] PLL >>>>>>>>
5004 23:25:44.140722 [ANA_INIT] PLL <<<<<<<<
5005 23:25:44.141172 [ANA_INIT] MIDPI >>>>>>>>
5006 23:25:44.144951 [ANA_INIT] MIDPI <<<<<<<<
5007 23:25:44.147297 [ANA_INIT] DLL >>>>>>>>
5008 23:25:44.147755 [ANA_INIT] flow end
5009 23:25:44.154099 ============ LP4 DIFF to SE enter ============
5010 23:25:44.157510 ============ LP4 DIFF to SE exit ============
5011 23:25:44.160830 [ANA_INIT] <<<<<<<<<<<<<
5012 23:25:44.163957 [Flow] Enable top DCM control >>>>>
5013 23:25:44.167436 [Flow] Enable top DCM control <<<<<
5014 23:25:44.168004 Enable DLL master slave shuffle
5015 23:25:44.174265 ==============================================================
5016 23:25:44.177129 Gating Mode config
5017 23:25:44.180733 ==============================================================
5018 23:25:44.184381 Config description:
5019 23:25:44.194297 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5020 23:25:44.201024 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5021 23:25:44.203891 SELPH_MODE 0: By rank 1: By Phase
5022 23:25:44.210738 ==============================================================
5023 23:25:44.214263 GAT_TRACK_EN = 1
5024 23:25:44.217001 RX_GATING_MODE = 2
5025 23:25:44.220792 RX_GATING_TRACK_MODE = 2
5026 23:25:44.221371 SELPH_MODE = 1
5027 23:25:44.223702 PICG_EARLY_EN = 1
5028 23:25:44.227602 VALID_LAT_VALUE = 1
5029 23:25:44.233848 ==============================================================
5030 23:25:44.237425 Enter into Gating configuration >>>>
5031 23:25:44.240219 Exit from Gating configuration <<<<
5032 23:25:44.244318 Enter into DVFS_PRE_config >>>>>
5033 23:25:44.253637 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5034 23:25:44.257409 Exit from DVFS_PRE_config <<<<<
5035 23:25:44.260248 Enter into PICG configuration >>>>
5036 23:25:44.264048 Exit from PICG configuration <<<<
5037 23:25:44.266971 [RX_INPUT] configuration >>>>>
5038 23:25:44.270360 [RX_INPUT] configuration <<<<<
5039 23:25:44.273498 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5040 23:25:44.280612 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5041 23:25:44.287695 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 23:25:44.293522 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 23:25:44.300347 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5044 23:25:44.304160 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5045 23:25:44.310055 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5046 23:25:44.313555 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5047 23:25:44.316732 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5048 23:25:44.320018 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5049 23:25:44.323044 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5050 23:25:44.330324 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5051 23:25:44.333156 ===================================
5052 23:25:44.336981 LPDDR4 DRAM CONFIGURATION
5053 23:25:44.339959 ===================================
5054 23:25:44.340423 EX_ROW_EN[0] = 0x0
5055 23:25:44.343456 EX_ROW_EN[1] = 0x0
5056 23:25:44.344016 LP4Y_EN = 0x0
5057 23:25:44.346524 WORK_FSP = 0x0
5058 23:25:44.346983 WL = 0x3
5059 23:25:44.349657 RL = 0x3
5060 23:25:44.350116 BL = 0x2
5061 23:25:44.353064 RPST = 0x0
5062 23:25:44.353519 RD_PRE = 0x0
5063 23:25:44.356793 WR_PRE = 0x1
5064 23:25:44.357351 WR_PST = 0x0
5065 23:25:44.360325 DBI_WR = 0x0
5066 23:25:44.360882 DBI_RD = 0x0
5067 23:25:44.363286 OTF = 0x1
5068 23:25:44.366516 ===================================
5069 23:25:44.370253 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5070 23:25:44.373330 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5071 23:25:44.380489 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5072 23:25:44.384062 ===================================
5073 23:25:44.384661 LPDDR4 DRAM CONFIGURATION
5074 23:25:44.386181 ===================================
5075 23:25:44.389826 EX_ROW_EN[0] = 0x10
5076 23:25:44.393153 EX_ROW_EN[1] = 0x0
5077 23:25:44.393637 LP4Y_EN = 0x0
5078 23:25:44.396622 WORK_FSP = 0x0
5079 23:25:44.397252 WL = 0x3
5080 23:25:44.399853 RL = 0x3
5081 23:25:44.400326 BL = 0x2
5082 23:25:44.403157 RPST = 0x0
5083 23:25:44.403714 RD_PRE = 0x0
5084 23:25:44.406518 WR_PRE = 0x1
5085 23:25:44.407101 WR_PST = 0x0
5086 23:25:44.409470 DBI_WR = 0x0
5087 23:25:44.409955 DBI_RD = 0x0
5088 23:25:44.413014 OTF = 0x1
5089 23:25:44.416206 ===================================
5090 23:25:44.422889 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5091 23:25:44.426297 nWR fixed to 30
5092 23:25:44.429356 [ModeRegInit_LP4] CH0 RK0
5093 23:25:44.429857 [ModeRegInit_LP4] CH0 RK1
5094 23:25:44.432583 [ModeRegInit_LP4] CH1 RK0
5095 23:25:44.436311 [ModeRegInit_LP4] CH1 RK1
5096 23:25:44.436829 match AC timing 9
5097 23:25:44.442881 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5098 23:25:44.446299 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5099 23:25:44.449361 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5100 23:25:44.456311 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5101 23:25:44.459310 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5102 23:25:44.459722 ==
5103 23:25:44.462800 Dram Type= 6, Freq= 0, CH_0, rank 0
5104 23:25:44.466550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5105 23:25:44.467109 ==
5106 23:25:44.473316 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5107 23:25:44.479723 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5108 23:25:44.483021 [CA 0] Center 37 (6~68) winsize 63
5109 23:25:44.486321 [CA 1] Center 37 (6~68) winsize 63
5110 23:25:44.489775 [CA 2] Center 34 (4~65) winsize 62
5111 23:25:44.492963 [CA 3] Center 33 (3~64) winsize 62
5112 23:25:44.496117 [CA 4] Center 33 (3~64) winsize 62
5113 23:25:44.499464 [CA 5] Center 32 (2~62) winsize 61
5114 23:25:44.499921
5115 23:25:44.503227 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5116 23:25:44.503779
5117 23:25:44.505979 [CATrainingPosCal] consider 1 rank data
5118 23:25:44.509570 u2DelayCellTimex100 = 270/100 ps
5119 23:25:44.512318 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5120 23:25:44.515634 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5121 23:25:44.520063 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5122 23:25:44.522991 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5123 23:25:44.526113 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5124 23:25:44.528986 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5125 23:25:44.529461
5126 23:25:44.535981 CA PerBit enable=1, Macro0, CA PI delay=32
5127 23:25:44.536516
5128 23:25:44.536871 [CBTSetCACLKResult] CA Dly = 32
5129 23:25:44.539401 CS Dly: 5 (0~36)
5130 23:25:44.539881 ==
5131 23:25:44.542227 Dram Type= 6, Freq= 0, CH_0, rank 1
5132 23:25:44.545889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5133 23:25:44.546446 ==
5134 23:25:44.552882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5135 23:25:44.559041 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5136 23:25:44.562800 [CA 0] Center 37 (6~68) winsize 63
5137 23:25:44.565698 [CA 1] Center 37 (6~68) winsize 63
5138 23:25:44.569394 [CA 2] Center 34 (4~65) winsize 62
5139 23:25:44.572516 [CA 3] Center 34 (4~65) winsize 62
5140 23:25:44.575560 [CA 4] Center 33 (3~63) winsize 61
5141 23:25:44.579373 [CA 5] Center 32 (2~62) winsize 61
5142 23:25:44.579884
5143 23:25:44.582568 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5144 23:25:44.583124
5145 23:25:44.586192 [CATrainingPosCal] consider 2 rank data
5146 23:25:44.588966 u2DelayCellTimex100 = 270/100 ps
5147 23:25:44.592662 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5148 23:25:44.595785 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5149 23:25:44.599014 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5150 23:25:44.602374 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5151 23:25:44.605784 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5152 23:25:44.609184 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5153 23:25:44.611937
5154 23:25:44.615772 CA PerBit enable=1, Macro0, CA PI delay=32
5155 23:25:44.616244
5156 23:25:44.618803 [CBTSetCACLKResult] CA Dly = 32
5157 23:25:44.619258 CS Dly: 5 (0~37)
5158 23:25:44.619610
5159 23:25:44.622209 ----->DramcWriteLeveling(PI) begin...
5160 23:25:44.622781 ==
5161 23:25:44.625813 Dram Type= 6, Freq= 0, CH_0, rank 0
5162 23:25:44.628613 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5163 23:25:44.632630 ==
5164 23:25:44.633183 Write leveling (Byte 0): 31 => 31
5165 23:25:44.635304 Write leveling (Byte 1): 31 => 31
5166 23:25:44.638774 DramcWriteLeveling(PI) end<-----
5167 23:25:44.639254
5168 23:25:44.639608 ==
5169 23:25:44.642140 Dram Type= 6, Freq= 0, CH_0, rank 0
5170 23:25:44.649180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5171 23:25:44.649778 ==
5172 23:25:44.650143 [Gating] SW mode calibration
5173 23:25:44.658910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5174 23:25:44.661851 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5175 23:25:44.668591 0 14 0 | B1->B0 | 2727 3434 | 0 1 | (0 0) (1 1)
5176 23:25:44.672337 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 23:25:44.675400 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 23:25:44.678450 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 23:25:44.685572 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5180 23:25:44.688845 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5181 23:25:44.692307 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5182 23:25:44.698999 0 14 28 | B1->B0 | 3434 2626 | 1 0 | (1 0) (0 0)
5183 23:25:44.702695 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
5184 23:25:44.705653 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 23:25:44.712490 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 23:25:44.715644 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 23:25:44.718821 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5188 23:25:44.725451 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5189 23:25:44.728720 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5190 23:25:44.732654 0 15 28 | B1->B0 | 2424 3f3f | 0 0 | (0 0) (0 0)
5191 23:25:44.738974 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5192 23:25:44.741962 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 23:25:44.745700 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 23:25:44.752031 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 23:25:44.755193 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5196 23:25:44.758754 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5197 23:25:44.764956 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5198 23:25:44.769081 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5199 23:25:44.771665 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5200 23:25:44.778309 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 23:25:44.781713 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 23:25:44.785065 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 23:25:44.792005 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 23:25:44.795174 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 23:25:44.798528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 23:25:44.801639 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 23:25:44.808931 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:25:44.812079 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:25:44.814771 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:25:44.821806 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:25:44.825071 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:25:44.828508 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:25:44.835379 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5214 23:25:44.838882 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5215 23:25:44.841703 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5216 23:25:44.845646 Total UI for P1: 0, mck2ui 16
5217 23:25:44.848360 best dqsien dly found for B0: ( 1, 2, 26)
5218 23:25:44.855461 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5219 23:25:44.856018 Total UI for P1: 0, mck2ui 16
5220 23:25:44.861740 best dqsien dly found for B1: ( 1, 3, 0)
5221 23:25:44.865037 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5222 23:25:44.869098 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5223 23:25:44.869693
5224 23:25:44.872237 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5225 23:25:44.875057 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5226 23:25:44.878424 [Gating] SW calibration Done
5227 23:25:44.878887 ==
5228 23:25:44.881955 Dram Type= 6, Freq= 0, CH_0, rank 0
5229 23:25:44.885170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5230 23:25:44.885775 ==
5231 23:25:44.888132 RX Vref Scan: 0
5232 23:25:44.888683
5233 23:25:44.889045 RX Vref 0 -> 0, step: 1
5234 23:25:44.889379
5235 23:25:44.891794 RX Delay -80 -> 252, step: 8
5236 23:25:44.894926 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5237 23:25:44.901183 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5238 23:25:44.905147 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5239 23:25:44.908317 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5240 23:25:44.911577 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5241 23:25:44.914498 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5242 23:25:44.917836 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5243 23:25:44.924326 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5244 23:25:44.928033 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5245 23:25:44.931038 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5246 23:25:44.934400 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5247 23:25:44.937561 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5248 23:25:44.940713 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5249 23:25:44.947820 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5250 23:25:44.951262 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5251 23:25:44.954703 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5252 23:25:44.955210 ==
5253 23:25:44.958111 Dram Type= 6, Freq= 0, CH_0, rank 0
5254 23:25:44.961854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5255 23:25:44.962373 ==
5256 23:25:44.964160 DQS Delay:
5257 23:25:44.964578 DQS0 = 0, DQS1 = 0
5258 23:25:44.967401 DQM Delay:
5259 23:25:44.967819 DQM0 = 104, DQM1 = 95
5260 23:25:44.968147 DQ Delay:
5261 23:25:44.971597 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5262 23:25:44.974596 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5263 23:25:44.977500 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5264 23:25:44.984317 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5265 23:25:44.984831
5266 23:25:44.985160
5267 23:25:44.985464 ==
5268 23:25:44.987771 Dram Type= 6, Freq= 0, CH_0, rank 0
5269 23:25:44.991320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5270 23:25:44.991833 ==
5271 23:25:44.992161
5272 23:25:44.992462
5273 23:25:44.994389 TX Vref Scan disable
5274 23:25:44.994809 == TX Byte 0 ==
5275 23:25:45.000837 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5276 23:25:45.004847 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5277 23:25:45.005503 == TX Byte 1 ==
5278 23:25:45.010544 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5279 23:25:45.014216 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5280 23:25:45.014812 ==
5281 23:25:45.017688 Dram Type= 6, Freq= 0, CH_0, rank 0
5282 23:25:45.021327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5283 23:25:45.021955 ==
5284 23:25:45.022354
5285 23:25:45.022759
5286 23:25:45.024253 TX Vref Scan disable
5287 23:25:45.027320 == TX Byte 0 ==
5288 23:25:45.031636 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5289 23:25:45.034113 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5290 23:25:45.037610 == TX Byte 1 ==
5291 23:25:45.040596 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5292 23:25:45.044221 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5293 23:25:45.044696
5294 23:25:45.048004 [DATLAT]
5295 23:25:45.048621 Freq=933, CH0 RK0
5296 23:25:45.048999
5297 23:25:45.050838 DATLAT Default: 0xd
5298 23:25:45.051290 0, 0xFFFF, sum = 0
5299 23:25:45.053911 1, 0xFFFF, sum = 0
5300 23:25:45.054373 2, 0xFFFF, sum = 0
5301 23:25:45.057485 3, 0xFFFF, sum = 0
5302 23:25:45.057986 4, 0xFFFF, sum = 0
5303 23:25:45.060951 5, 0xFFFF, sum = 0
5304 23:25:45.061647 6, 0xFFFF, sum = 0
5305 23:25:45.063876 7, 0xFFFF, sum = 0
5306 23:25:45.064337 8, 0xFFFF, sum = 0
5307 23:25:45.066950 9, 0xFFFF, sum = 0
5308 23:25:45.067472 10, 0x0, sum = 1
5309 23:25:45.070220 11, 0x0, sum = 2
5310 23:25:45.070637 12, 0x0, sum = 3
5311 23:25:45.074234 13, 0x0, sum = 4
5312 23:25:45.074655 best_step = 11
5313 23:25:45.074976
5314 23:25:45.075273 ==
5315 23:25:45.077227 Dram Type= 6, Freq= 0, CH_0, rank 0
5316 23:25:45.084258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 23:25:45.084769 ==
5318 23:25:45.085099 RX Vref Scan: 1
5319 23:25:45.085402
5320 23:25:45.087347 RX Vref 0 -> 0, step: 1
5321 23:25:45.087860
5322 23:25:45.090582 RX Delay -45 -> 252, step: 4
5323 23:25:45.091096
5324 23:25:45.094311 Set Vref, RX VrefLevel [Byte0]: 56
5325 23:25:45.097662 [Byte1]: 55
5326 23:25:45.098221
5327 23:25:45.100435 Final RX Vref Byte 0 = 56 to rank0
5328 23:25:45.104332 Final RX Vref Byte 1 = 55 to rank0
5329 23:25:45.107338 Final RX Vref Byte 0 = 56 to rank1
5330 23:25:45.110721 Final RX Vref Byte 1 = 55 to rank1==
5331 23:25:45.114223 Dram Type= 6, Freq= 0, CH_0, rank 0
5332 23:25:45.117070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5333 23:25:45.117672 ==
5334 23:25:45.120358 DQS Delay:
5335 23:25:45.120909 DQS0 = 0, DQS1 = 0
5336 23:25:45.123827 DQM Delay:
5337 23:25:45.124308 DQM0 = 104, DQM1 = 97
5338 23:25:45.124674 DQ Delay:
5339 23:25:45.126624 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5340 23:25:45.130161 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5341 23:25:45.133661 DQ8 =88, DQ9 =90, DQ10 =98, DQ11 =92
5342 23:25:45.139926 DQ12 =102, DQ13 =102, DQ14 =106, DQ15 =104
5343 23:25:45.140383
5344 23:25:45.140735
5345 23:25:45.146768 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5346 23:25:45.149846 CH0 RK0: MR19=505, MR18=2D25
5347 23:25:45.156794 CH0_RK0: MR19=0x505, MR18=0x2D25, DQSOSC=407, MR23=63, INC=65, DEC=43
5348 23:25:45.157363
5349 23:25:45.160123 ----->DramcWriteLeveling(PI) begin...
5350 23:25:45.160678 ==
5351 23:25:45.163007 Dram Type= 6, Freq= 0, CH_0, rank 1
5352 23:25:45.166390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 23:25:45.166962 ==
5354 23:25:45.169712 Write leveling (Byte 0): 34 => 34
5355 23:25:45.173081 Write leveling (Byte 1): 30 => 30
5356 23:25:45.176445 DramcWriteLeveling(PI) end<-----
5357 23:25:45.176899
5358 23:25:45.177306 ==
5359 23:25:45.179552 Dram Type= 6, Freq= 0, CH_0, rank 1
5360 23:25:45.182807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5361 23:25:45.183243 ==
5362 23:25:45.186057 [Gating] SW mode calibration
5363 23:25:45.193306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5364 23:25:45.199419 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5365 23:25:45.203605 0 14 0 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 1)
5366 23:25:45.209860 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 23:25:45.212882 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 23:25:45.216786 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5369 23:25:45.223233 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5370 23:25:45.226406 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5371 23:25:45.229912 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5372 23:25:45.236125 0 14 28 | B1->B0 | 2f2f 2a2a | 1 0 | (1 1) (0 0)
5373 23:25:45.239382 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
5374 23:25:45.242931 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 23:25:45.246189 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 23:25:45.253456 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5377 23:25:45.256654 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5378 23:25:45.259842 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5379 23:25:45.266545 0 15 24 | B1->B0 | 2424 2525 | 0 0 | (0 0) (0 0)
5380 23:25:45.269450 0 15 28 | B1->B0 | 3b3b 3f3f | 1 1 | (0 0) (0 0)
5381 23:25:45.272789 1 0 0 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
5382 23:25:45.279380 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 23:25:45.283121 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 23:25:45.286029 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 23:25:45.292530 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5386 23:25:45.296144 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5387 23:25:45.299225 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5388 23:25:45.306230 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5389 23:25:45.309303 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 23:25:45.312534 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 23:25:45.319046 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 23:25:45.323267 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 23:25:45.325665 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 23:25:45.332630 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 23:25:45.336105 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 23:25:45.339658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:25:45.345525 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:25:45.349082 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:25:45.352886 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:25:45.358958 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:25:45.362188 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:25:45.365259 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 23:25:45.372589 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 23:25:45.375835 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5405 23:25:45.378567 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5406 23:25:45.382200 Total UI for P1: 0, mck2ui 16
5407 23:25:45.386090 best dqsien dly found for B0: ( 1, 2, 28)
5408 23:25:45.392655 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5409 23:25:45.393254 Total UI for P1: 0, mck2ui 16
5410 23:25:45.395276 best dqsien dly found for B1: ( 1, 2, 30)
5411 23:25:45.402119 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5412 23:25:45.405490 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5413 23:25:45.406098
5414 23:25:45.408885 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5415 23:25:45.411901 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5416 23:25:45.415438 [Gating] SW calibration Done
5417 23:25:45.415992 ==
5418 23:25:45.418710 Dram Type= 6, Freq= 0, CH_0, rank 1
5419 23:25:45.421797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5420 23:25:45.422348 ==
5421 23:25:45.425088 RX Vref Scan: 0
5422 23:25:45.425549
5423 23:25:45.425948 RX Vref 0 -> 0, step: 1
5424 23:25:45.426285
5425 23:25:45.428242 RX Delay -80 -> 252, step: 8
5426 23:25:45.431800 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5427 23:25:45.438223 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5428 23:25:45.441671 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5429 23:25:45.445084 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5430 23:25:45.448846 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5431 23:25:45.451878 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5432 23:25:45.455098 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5433 23:25:45.462074 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5434 23:25:45.464979 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5435 23:25:45.469008 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5436 23:25:45.472208 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5437 23:25:45.475460 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5438 23:25:45.478734 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5439 23:25:45.485155 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5440 23:25:45.488380 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5441 23:25:45.491519 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5442 23:25:45.492000 ==
5443 23:25:45.494970 Dram Type= 6, Freq= 0, CH_0, rank 1
5444 23:25:45.498664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5445 23:25:45.499240 ==
5446 23:25:45.501425 DQS Delay:
5447 23:25:45.502046 DQS0 = 0, DQS1 = 0
5448 23:25:45.505090 DQM Delay:
5449 23:25:45.505683 DQM0 = 105, DQM1 = 94
5450 23:25:45.506055 DQ Delay:
5451 23:25:45.508535 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5452 23:25:45.511667 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5453 23:25:45.514932 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =87
5454 23:25:45.521850 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =99
5455 23:25:45.522407
5456 23:25:45.522768
5457 23:25:45.523103 ==
5458 23:25:45.524591 Dram Type= 6, Freq= 0, CH_0, rank 1
5459 23:25:45.528584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5460 23:25:45.529159 ==
5461 23:25:45.529526
5462 23:25:45.529923
5463 23:25:45.531162 TX Vref Scan disable
5464 23:25:45.531624 == TX Byte 0 ==
5465 23:25:45.538283 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5466 23:25:45.541542 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5467 23:25:45.542034 == TX Byte 1 ==
5468 23:25:45.548358 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5469 23:25:45.551677 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5470 23:25:45.552234 ==
5471 23:25:45.554720 Dram Type= 6, Freq= 0, CH_0, rank 1
5472 23:25:45.558120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5473 23:25:45.558587 ==
5474 23:25:45.558947
5475 23:25:45.559279
5476 23:25:45.562224 TX Vref Scan disable
5477 23:25:45.564849 == TX Byte 0 ==
5478 23:25:45.568031 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5479 23:25:45.571204 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5480 23:25:45.575074 == TX Byte 1 ==
5481 23:25:45.578182 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5482 23:25:45.581045 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5483 23:25:45.581632
5484 23:25:45.584474 [DATLAT]
5485 23:25:45.584947 Freq=933, CH0 RK1
5486 23:25:45.585427
5487 23:25:45.588279 DATLAT Default: 0xb
5488 23:25:45.588844 0, 0xFFFF, sum = 0
5489 23:25:45.591310 1, 0xFFFF, sum = 0
5490 23:25:45.591882 2, 0xFFFF, sum = 0
5491 23:25:45.594646 3, 0xFFFF, sum = 0
5492 23:25:45.595221 4, 0xFFFF, sum = 0
5493 23:25:45.597747 5, 0xFFFF, sum = 0
5494 23:25:45.598227 6, 0xFFFF, sum = 0
5495 23:25:45.601116 7, 0xFFFF, sum = 0
5496 23:25:45.604388 8, 0xFFFF, sum = 0
5497 23:25:45.605034 9, 0xFFFF, sum = 0
5498 23:25:45.605657 10, 0x0, sum = 1
5499 23:25:45.607845 11, 0x0, sum = 2
5500 23:25:45.608398 12, 0x0, sum = 3
5501 23:25:45.611103 13, 0x0, sum = 4
5502 23:25:45.611665 best_step = 11
5503 23:25:45.612027
5504 23:25:45.612357 ==
5505 23:25:45.614407 Dram Type= 6, Freq= 0, CH_0, rank 1
5506 23:25:45.621258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5507 23:25:45.621866 ==
5508 23:25:45.622234 RX Vref Scan: 0
5509 23:25:45.622567
5510 23:25:45.624590 RX Vref 0 -> 0, step: 1
5511 23:25:45.625082
5512 23:25:45.628178 RX Delay -53 -> 252, step: 4
5513 23:25:45.630930 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5514 23:25:45.638027 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5515 23:25:45.640816 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5516 23:25:45.644185 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5517 23:25:45.648373 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5518 23:25:45.651380 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5519 23:25:45.654854 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5520 23:25:45.661048 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5521 23:25:45.664400 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5522 23:25:45.667691 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5523 23:25:45.670954 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5524 23:25:45.674593 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5525 23:25:45.677866 iDelay=199, Bit 12, Center 102 (19 ~ 186) 168
5526 23:25:45.684564 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5527 23:25:45.688022 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5528 23:25:45.691358 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5529 23:25:45.691917 ==
5530 23:25:45.694321 Dram Type= 6, Freq= 0, CH_0, rank 1
5531 23:25:45.698043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5532 23:25:45.701367 ==
5533 23:25:45.701944 DQS Delay:
5534 23:25:45.702311 DQS0 = 0, DQS1 = 0
5535 23:25:45.704035 DQM Delay:
5536 23:25:45.704497 DQM0 = 104, DQM1 = 95
5537 23:25:45.707668 DQ Delay:
5538 23:25:45.711022 DQ0 =100, DQ1 =106, DQ2 =102, DQ3 =102
5539 23:25:45.714386 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5540 23:25:45.718024 DQ8 =86, DQ9 =86, DQ10 =94, DQ11 =88
5541 23:25:45.721289 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =102
5542 23:25:45.721874
5543 23:25:45.722239
5544 23:25:45.728192 [DQSOSCAuto] RK1, (LSB)MR18= 0x2700, (MSB)MR19= 0x505, tDQSOscB0 = 422 ps tDQSOscB1 = 409 ps
5545 23:25:45.730848 CH0 RK1: MR19=505, MR18=2700
5546 23:25:45.737465 CH0_RK1: MR19=0x505, MR18=0x2700, DQSOSC=409, MR23=63, INC=64, DEC=43
5547 23:25:45.740768 [RxdqsGatingPostProcess] freq 933
5548 23:25:45.744351 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5549 23:25:45.747902 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 23:25:45.750698 best DQS1 dly(2T, 0.5T) = (0, 11)
5551 23:25:45.754654 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 23:25:45.757540 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5553 23:25:45.760727 best DQS0 dly(2T, 0.5T) = (0, 10)
5554 23:25:45.763832 best DQS1 dly(2T, 0.5T) = (0, 10)
5555 23:25:45.767417 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5556 23:25:45.771170 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5557 23:25:45.773895 Pre-setting of DQS Precalculation
5558 23:25:45.780751 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5559 23:25:45.781345 ==
5560 23:25:45.784042 Dram Type= 6, Freq= 0, CH_1, rank 0
5561 23:25:45.787012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5562 23:25:45.787568 ==
5563 23:25:45.793663 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5564 23:25:45.797048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5565 23:25:45.800985 [CA 0] Center 36 (6~67) winsize 62
5566 23:25:45.804274 [CA 1] Center 36 (6~67) winsize 62
5567 23:25:45.807588 [CA 2] Center 34 (4~65) winsize 62
5568 23:25:45.810762 [CA 3] Center 34 (4~65) winsize 62
5569 23:25:45.814303 [CA 4] Center 34 (4~64) winsize 61
5570 23:25:45.817792 [CA 5] Center 33 (3~64) winsize 62
5571 23:25:45.818349
5572 23:25:45.820977 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5573 23:25:45.821531
5574 23:25:45.824307 [CATrainingPosCal] consider 1 rank data
5575 23:25:45.827741 u2DelayCellTimex100 = 270/100 ps
5576 23:25:45.830764 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5577 23:25:45.837505 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5578 23:25:45.840779 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5579 23:25:45.843773 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5580 23:25:45.847677 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5581 23:25:45.850554 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5582 23:25:45.851028
5583 23:25:45.854155 CA PerBit enable=1, Macro0, CA PI delay=33
5584 23:25:45.854621
5585 23:25:45.857945 [CBTSetCACLKResult] CA Dly = 33
5586 23:25:45.858492 CS Dly: 7 (0~38)
5587 23:25:45.861144 ==
5588 23:25:45.861743 Dram Type= 6, Freq= 0, CH_1, rank 1
5589 23:25:45.867732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 23:25:45.868289 ==
5591 23:25:45.871220 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 23:25:45.877747 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5593 23:25:45.881374 [CA 0] Center 36 (6~67) winsize 62
5594 23:25:45.884601 [CA 1] Center 37 (7~68) winsize 62
5595 23:25:45.887632 [CA 2] Center 35 (5~65) winsize 61
5596 23:25:45.891146 [CA 3] Center 34 (4~65) winsize 62
5597 23:25:45.894630 [CA 4] Center 34 (4~65) winsize 62
5598 23:25:45.897823 [CA 5] Center 33 (3~64) winsize 62
5599 23:25:45.898380
5600 23:25:45.901245 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5601 23:25:45.901845
5602 23:25:45.904269 [CATrainingPosCal] consider 2 rank data
5603 23:25:45.907363 u2DelayCellTimex100 = 270/100 ps
5604 23:25:45.911020 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5605 23:25:45.917800 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5606 23:25:45.921085 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5607 23:25:45.924380 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5608 23:25:45.927880 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5609 23:25:45.931000 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5610 23:25:45.931556
5611 23:25:45.934578 CA PerBit enable=1, Macro0, CA PI delay=33
5612 23:25:45.935312
5613 23:25:45.937056 [CBTSetCACLKResult] CA Dly = 33
5614 23:25:45.937516 CS Dly: 8 (0~40)
5615 23:25:45.940202
5616 23:25:45.943714 ----->DramcWriteLeveling(PI) begin...
5617 23:25:45.944183 ==
5618 23:25:45.947581 Dram Type= 6, Freq= 0, CH_1, rank 0
5619 23:25:45.950638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 23:25:45.951347 ==
5621 23:25:45.953822 Write leveling (Byte 0): 28 => 28
5622 23:25:45.956990 Write leveling (Byte 1): 28 => 28
5623 23:25:45.960236 DramcWriteLeveling(PI) end<-----
5624 23:25:45.960702
5625 23:25:45.961061 ==
5626 23:25:45.963855 Dram Type= 6, Freq= 0, CH_1, rank 0
5627 23:25:45.966842 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5628 23:25:45.967563 ==
5629 23:25:45.970204 [Gating] SW mode calibration
5630 23:25:45.976813 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5631 23:25:45.983136 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5632 23:25:45.986754 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 23:25:45.990350 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5634 23:25:45.997001 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5635 23:25:46.000454 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5636 23:25:46.003633 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5637 23:25:46.009380 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5638 23:25:46.013590 0 14 24 | B1->B0 | 3434 2d2d | 0 1 | (0 1) (1 0)
5639 23:25:46.016804 0 14 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5640 23:25:46.022969 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 23:25:46.026263 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 23:25:46.030059 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5643 23:25:46.036309 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5644 23:25:46.040015 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5645 23:25:46.042902 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5646 23:25:46.049649 0 15 24 | B1->B0 | 2424 3232 | 1 0 | (0 0) (1 1)
5647 23:25:46.052936 0 15 28 | B1->B0 | 3434 4545 | 0 0 | (0 0) (0 0)
5648 23:25:46.056227 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 23:25:46.062894 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 23:25:46.066059 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5651 23:25:46.069209 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5652 23:25:46.076795 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5653 23:25:46.079703 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5654 23:25:46.082842 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5655 23:25:46.086047 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 23:25:46.093094 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 23:25:46.096338 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 23:25:46.099577 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 23:25:46.106571 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 23:25:46.109824 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 23:25:46.113218 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:25:46.120068 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:25:46.123007 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:25:46.126159 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:25:46.133263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:25:46.135892 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:25:46.139614 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:25:46.146003 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:25:46.149369 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 23:25:46.152529 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5671 23:25:46.158909 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5672 23:25:46.162438 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 23:25:46.165688 Total UI for P1: 0, mck2ui 16
5674 23:25:46.169336 best dqsien dly found for B0: ( 1, 2, 26)
5675 23:25:46.172392 Total UI for P1: 0, mck2ui 16
5676 23:25:46.175562 best dqsien dly found for B1: ( 1, 2, 26)
5677 23:25:46.178924 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5678 23:25:46.182169 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5679 23:25:46.182633
5680 23:25:46.186080 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5681 23:25:46.188744 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5682 23:25:46.192119 [Gating] SW calibration Done
5683 23:25:46.192684 ==
5684 23:25:46.195724 Dram Type= 6, Freq= 0, CH_1, rank 0
5685 23:25:46.202138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5686 23:25:46.202694 ==
5687 23:25:46.203055 RX Vref Scan: 0
5688 23:25:46.203386
5689 23:25:46.205102 RX Vref 0 -> 0, step: 1
5690 23:25:46.205562
5691 23:25:46.208966 RX Delay -80 -> 252, step: 8
5692 23:25:46.212377 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5693 23:25:46.215258 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5694 23:25:46.218400 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5695 23:25:46.221893 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5696 23:25:46.228795 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5697 23:25:46.231891 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5698 23:25:46.235592 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5699 23:25:46.238942 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5700 23:25:46.241997 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5701 23:25:46.245178 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5702 23:25:46.251786 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5703 23:25:46.255456 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5704 23:25:46.258225 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5705 23:25:46.261774 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5706 23:25:46.265492 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5707 23:25:46.272338 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5708 23:25:46.272894 ==
5709 23:25:46.275166 Dram Type= 6, Freq= 0, CH_1, rank 0
5710 23:25:46.278285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5711 23:25:46.278770 ==
5712 23:25:46.279134 DQS Delay:
5713 23:25:46.281416 DQS0 = 0, DQS1 = 0
5714 23:25:46.281930 DQM Delay:
5715 23:25:46.285313 DQM0 = 102, DQM1 = 98
5716 23:25:46.285919 DQ Delay:
5717 23:25:46.288757 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
5718 23:25:46.291794 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5719 23:25:46.295117 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5720 23:25:46.298407 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5721 23:25:46.298875
5722 23:25:46.299233
5723 23:25:46.299568 ==
5724 23:25:46.301818 Dram Type= 6, Freq= 0, CH_1, rank 0
5725 23:25:46.304753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5726 23:25:46.308258 ==
5727 23:25:46.308840
5728 23:25:46.309203
5729 23:25:46.309535 TX Vref Scan disable
5730 23:25:46.311547 == TX Byte 0 ==
5731 23:25:46.315002 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5732 23:25:46.318557 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5733 23:25:46.322064 == TX Byte 1 ==
5734 23:25:46.325272 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5735 23:25:46.328071 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5736 23:25:46.331466 ==
5737 23:25:46.331928 Dram Type= 6, Freq= 0, CH_1, rank 0
5738 23:25:46.338108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5739 23:25:46.338653 ==
5740 23:25:46.339013
5741 23:25:46.339345
5742 23:25:46.341497 TX Vref Scan disable
5743 23:25:46.342254 == TX Byte 0 ==
5744 23:25:46.348212 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5745 23:25:46.351619 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5746 23:25:46.352180 == TX Byte 1 ==
5747 23:25:46.358273 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5748 23:25:46.361060 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5749 23:25:46.361524
5750 23:25:46.361937 [DATLAT]
5751 23:25:46.364715 Freq=933, CH1 RK0
5752 23:25:46.365173
5753 23:25:46.365544 DATLAT Default: 0xd
5754 23:25:46.368017 0, 0xFFFF, sum = 0
5755 23:25:46.368486 1, 0xFFFF, sum = 0
5756 23:25:46.371053 2, 0xFFFF, sum = 0
5757 23:25:46.371525 3, 0xFFFF, sum = 0
5758 23:25:46.374468 4, 0xFFFF, sum = 0
5759 23:25:46.374942 5, 0xFFFF, sum = 0
5760 23:25:46.377664 6, 0xFFFF, sum = 0
5761 23:25:46.378137 7, 0xFFFF, sum = 0
5762 23:25:46.381285 8, 0xFFFF, sum = 0
5763 23:25:46.384284 9, 0xFFFF, sum = 0
5764 23:25:46.384709 10, 0x0, sum = 1
5765 23:25:46.385045 11, 0x0, sum = 2
5766 23:25:46.387961 12, 0x0, sum = 3
5767 23:25:46.388481 13, 0x0, sum = 4
5768 23:25:46.390951 best_step = 11
5769 23:25:46.391370
5770 23:25:46.391694 ==
5771 23:25:46.394446 Dram Type= 6, Freq= 0, CH_1, rank 0
5772 23:25:46.397775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5773 23:25:46.398201 ==
5774 23:25:46.401230 RX Vref Scan: 1
5775 23:25:46.401698
5776 23:25:46.402129 RX Vref 0 -> 0, step: 1
5777 23:25:46.402535
5778 23:25:46.404589 RX Delay -45 -> 252, step: 4
5779 23:25:46.405129
5780 23:25:46.408083 Set Vref, RX VrefLevel [Byte0]: 54
5781 23:25:46.410962 [Byte1]: 54
5782 23:25:46.415366
5783 23:25:46.415934 Final RX Vref Byte 0 = 54 to rank0
5784 23:25:46.419168 Final RX Vref Byte 1 = 54 to rank0
5785 23:25:46.421924 Final RX Vref Byte 0 = 54 to rank1
5786 23:25:46.425757 Final RX Vref Byte 1 = 54 to rank1==
5787 23:25:46.428263 Dram Type= 6, Freq= 0, CH_1, rank 0
5788 23:25:46.435109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5789 23:25:46.435683 ==
5790 23:25:46.436046 DQS Delay:
5791 23:25:46.436379 DQS0 = 0, DQS1 = 0
5792 23:25:46.438298 DQM Delay:
5793 23:25:46.438757 DQM0 = 103, DQM1 = 99
5794 23:25:46.442056 DQ Delay:
5795 23:25:46.444934 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5796 23:25:46.448109 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =102
5797 23:25:46.451741 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5798 23:25:46.454856 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =106
5799 23:25:46.455318
5800 23:25:46.455734
5801 23:25:46.462013 [DQSOSCAuto] RK0, (LSB)MR18= 0x132b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
5802 23:25:46.464745 CH1 RK0: MR19=505, MR18=132B
5803 23:25:46.471357 CH1_RK0: MR19=0x505, MR18=0x132B, DQSOSC=408, MR23=63, INC=65, DEC=43
5804 23:25:46.471825
5805 23:25:46.475408 ----->DramcWriteLeveling(PI) begin...
5806 23:25:46.475976 ==
5807 23:25:46.478363 Dram Type= 6, Freq= 0, CH_1, rank 1
5808 23:25:46.481802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 23:25:46.485201 ==
5810 23:25:46.485810 Write leveling (Byte 0): 27 => 27
5811 23:25:46.488559 Write leveling (Byte 1): 28 => 28
5812 23:25:46.491535 DramcWriteLeveling(PI) end<-----
5813 23:25:46.491998
5814 23:25:46.492359 ==
5815 23:25:46.495235 Dram Type= 6, Freq= 0, CH_1, rank 1
5816 23:25:46.501263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5817 23:25:46.501871 ==
5818 23:25:46.502238 [Gating] SW mode calibration
5819 23:25:46.511587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5820 23:25:46.514794 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5821 23:25:46.518271 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 23:25:46.524810 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 23:25:46.528625 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5824 23:25:46.531612 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5825 23:25:46.537820 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5826 23:25:46.541238 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5827 23:25:46.544745 0 14 24 | B1->B0 | 2e2e 3333 | 0 0 | (0 0) (1 0)
5828 23:25:46.551925 0 14 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5829 23:25:46.554278 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 23:25:46.558242 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 23:25:46.564659 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5832 23:25:46.567999 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5833 23:25:46.571037 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5834 23:25:46.577988 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 23:25:46.581249 0 15 24 | B1->B0 | 3333 2929 | 0 0 | (0 0) (0 0)
5836 23:25:46.584695 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (1 1)
5837 23:25:46.591877 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 23:25:46.594608 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 23:25:46.598218 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5840 23:25:46.604469 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5841 23:25:46.607884 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5842 23:25:46.611463 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5843 23:25:46.618155 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5844 23:25:46.620934 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5845 23:25:46.624915 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 23:25:46.631572 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 23:25:46.634556 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 23:25:46.638595 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 23:25:46.641059 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 23:25:46.648207 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:25:46.651388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:25:46.654449 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:25:46.660872 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:25:46.664376 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:25:46.667376 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:25:46.674587 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:25:46.677687 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:25:46.680507 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 23:25:46.687769 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5860 23:25:46.690888 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5861 23:25:46.694161 Total UI for P1: 0, mck2ui 16
5862 23:25:46.697688 best dqsien dly found for B1: ( 1, 2, 26)
5863 23:25:46.700356 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5864 23:25:46.703959 Total UI for P1: 0, mck2ui 16
5865 23:25:46.707361 best dqsien dly found for B0: ( 1, 2, 26)
5866 23:25:46.710564 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5867 23:25:46.713714 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5868 23:25:46.716980
5869 23:25:46.720544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5870 23:25:46.723945 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5871 23:25:46.726944 [Gating] SW calibration Done
5872 23:25:46.727409 ==
5873 23:25:46.730159 Dram Type= 6, Freq= 0, CH_1, rank 1
5874 23:25:46.733749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 23:25:46.734305 ==
5876 23:25:46.734670 RX Vref Scan: 0
5877 23:25:46.737464
5878 23:25:46.738053 RX Vref 0 -> 0, step: 1
5879 23:25:46.738422
5880 23:25:46.740284 RX Delay -80 -> 252, step: 8
5881 23:25:46.744181 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5882 23:25:46.746891 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5883 23:25:46.753852 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5884 23:25:46.757382 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5885 23:25:46.760661 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5886 23:25:46.763405 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5887 23:25:46.766943 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5888 23:25:46.774011 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5889 23:25:46.777006 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5890 23:25:46.780273 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5891 23:25:46.783421 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5892 23:25:46.787213 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5893 23:25:46.790536 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5894 23:25:46.797463 iDelay=208, Bit 13, Center 111 (24 ~ 199) 176
5895 23:25:46.800281 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5896 23:25:46.804036 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5897 23:25:46.804589 ==
5898 23:25:46.807116 Dram Type= 6, Freq= 0, CH_1, rank 1
5899 23:25:46.810291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5900 23:25:46.810847 ==
5901 23:25:46.813775 DQS Delay:
5902 23:25:46.814323 DQS0 = 0, DQS1 = 0
5903 23:25:46.817037 DQM Delay:
5904 23:25:46.817622 DQM0 = 105, DQM1 = 99
5905 23:25:46.820084 DQ Delay:
5906 23:25:46.823413 DQ0 =107, DQ1 =103, DQ2 =91, DQ3 =103
5907 23:25:46.826362 DQ4 =99, DQ5 =119, DQ6 =115, DQ7 =103
5908 23:25:46.829641 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5909 23:25:46.833174 DQ12 =107, DQ13 =111, DQ14 =103, DQ15 =107
5910 23:25:46.833690
5911 23:25:46.834083
5912 23:25:46.834420 ==
5913 23:25:46.836445 Dram Type= 6, Freq= 0, CH_1, rank 1
5914 23:25:46.839645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5915 23:25:46.840294 ==
5916 23:25:46.840670
5917 23:25:46.841007
5918 23:25:46.843043 TX Vref Scan disable
5919 23:25:46.846262 == TX Byte 0 ==
5920 23:25:46.849710 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5921 23:25:46.853115 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5922 23:25:46.856613 == TX Byte 1 ==
5923 23:25:46.859892 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5924 23:25:46.862731 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5925 23:25:46.863188 ==
5926 23:25:46.866675 Dram Type= 6, Freq= 0, CH_1, rank 1
5927 23:25:46.869719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5928 23:25:46.870180 ==
5929 23:25:46.872703
5930 23:25:46.873151
5931 23:25:46.873501 TX Vref Scan disable
5932 23:25:46.876368 == TX Byte 0 ==
5933 23:25:46.879640 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5934 23:25:46.882738 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5935 23:25:46.886639 == TX Byte 1 ==
5936 23:25:46.890082 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5937 23:25:46.896455 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5938 23:25:46.897013
5939 23:25:46.897365 [DATLAT]
5940 23:25:46.897751 Freq=933, CH1 RK1
5941 23:25:46.898076
5942 23:25:46.899579 DATLAT Default: 0xb
5943 23:25:46.900027 0, 0xFFFF, sum = 0
5944 23:25:46.903471 1, 0xFFFF, sum = 0
5945 23:25:46.904033 2, 0xFFFF, sum = 0
5946 23:25:46.906189 3, 0xFFFF, sum = 0
5947 23:25:46.906650 4, 0xFFFF, sum = 0
5948 23:25:46.910212 5, 0xFFFF, sum = 0
5949 23:25:46.912618 6, 0xFFFF, sum = 0
5950 23:25:46.913079 7, 0xFFFF, sum = 0
5951 23:25:46.916339 8, 0xFFFF, sum = 0
5952 23:25:46.916898 9, 0xFFFF, sum = 0
5953 23:25:46.919746 10, 0x0, sum = 1
5954 23:25:46.920307 11, 0x0, sum = 2
5955 23:25:46.920670 12, 0x0, sum = 3
5956 23:25:46.922531 13, 0x0, sum = 4
5957 23:25:46.922990 best_step = 11
5958 23:25:46.923339
5959 23:25:46.925801 ==
5960 23:25:46.926257 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 23:25:46.932786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 23:25:46.933250 ==
5963 23:25:46.933643 RX Vref Scan: 0
5964 23:25:46.933986
5965 23:25:46.936375 RX Vref 0 -> 0, step: 1
5966 23:25:46.936946
5967 23:25:46.939216 RX Delay -45 -> 252, step: 4
5968 23:25:46.942855 iDelay=203, Bit 0, Center 110 (27 ~ 194) 168
5969 23:25:46.949562 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5970 23:25:46.952826 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5971 23:25:46.956590 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5972 23:25:46.959302 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5973 23:25:46.963070 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5974 23:25:46.969349 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5975 23:25:46.972436 iDelay=203, Bit 7, Center 102 (19 ~ 186) 168
5976 23:25:46.976259 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5977 23:25:46.979140 iDelay=203, Bit 9, Center 90 (3 ~ 178) 176
5978 23:25:46.982654 iDelay=203, Bit 10, Center 102 (19 ~ 186) 168
5979 23:25:46.985767 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5980 23:25:46.992706 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5981 23:25:46.995780 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5982 23:25:46.999187 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5983 23:25:47.002378 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5984 23:25:47.002852 ==
5985 23:25:47.005572 Dram Type= 6, Freq= 0, CH_1, rank 1
5986 23:25:47.012670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5987 23:25:47.013250 ==
5988 23:25:47.013794 DQS Delay:
5989 23:25:47.015697 DQS0 = 0, DQS1 = 0
5990 23:25:47.016252 DQM Delay:
5991 23:25:47.016710 DQM0 = 104, DQM1 = 100
5992 23:25:47.019519 DQ Delay:
5993 23:25:47.021976 DQ0 =110, DQ1 =100, DQ2 =94, DQ3 =100
5994 23:25:47.025516 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =102
5995 23:25:47.028897 DQ8 =90, DQ9 =90, DQ10 =102, DQ11 =92
5996 23:25:47.032297 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5997 23:25:47.032396
5998 23:25:47.032484
5999 23:25:47.039120 [DQSOSCAuto] RK1, (LSB)MR18= 0x2bff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 408 ps
6000 23:25:47.042449 CH1 RK1: MR19=504, MR18=2BFF
6001 23:25:47.049101 CH1_RK1: MR19=0x504, MR18=0x2BFF, DQSOSC=408, MR23=63, INC=65, DEC=43
6002 23:25:47.052031 [RxdqsGatingPostProcess] freq 933
6003 23:25:47.058970 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6004 23:25:47.061978 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 23:25:47.062168 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 23:25:47.065572 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 23:25:47.069410 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 23:25:47.072393 best DQS0 dly(2T, 0.5T) = (0, 10)
6009 23:25:47.075453 best DQS1 dly(2T, 0.5T) = (0, 10)
6010 23:25:47.078850 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6011 23:25:47.082189 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6012 23:25:47.085668 Pre-setting of DQS Precalculation
6013 23:25:47.092292 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6014 23:25:47.099204 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6015 23:25:47.106039 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6016 23:25:47.106620
6017 23:25:47.106984
6018 23:25:47.109290 [Calibration Summary] 1866 Mbps
6019 23:25:47.109874 CH 0, Rank 0
6020 23:25:47.112910 SW Impedance : PASS
6021 23:25:47.116265 DUTY Scan : NO K
6022 23:25:47.116815 ZQ Calibration : PASS
6023 23:25:47.119308 Jitter Meter : NO K
6024 23:25:47.119858 CBT Training : PASS
6025 23:25:47.122821 Write leveling : PASS
6026 23:25:47.125976 RX DQS gating : PASS
6027 23:25:47.126526 RX DQ/DQS(RDDQC) : PASS
6028 23:25:47.129181 TX DQ/DQS : PASS
6029 23:25:47.132833 RX DATLAT : PASS
6030 23:25:47.133397 RX DQ/DQS(Engine): PASS
6031 23:25:47.136140 TX OE : NO K
6032 23:25:47.136697 All Pass.
6033 23:25:47.137059
6034 23:25:47.139366 CH 0, Rank 1
6035 23:25:47.139946 SW Impedance : PASS
6036 23:25:47.143002 DUTY Scan : NO K
6037 23:25:47.146144 ZQ Calibration : PASS
6038 23:25:47.146783 Jitter Meter : NO K
6039 23:25:47.149398 CBT Training : PASS
6040 23:25:47.152612 Write leveling : PASS
6041 23:25:47.153073 RX DQS gating : PASS
6042 23:25:47.155958 RX DQ/DQS(RDDQC) : PASS
6043 23:25:47.159460 TX DQ/DQS : PASS
6044 23:25:47.160013 RX DATLAT : PASS
6045 23:25:47.162731 RX DQ/DQS(Engine): PASS
6046 23:25:47.163194 TX OE : NO K
6047 23:25:47.165919 All Pass.
6048 23:25:47.166452
6049 23:25:47.166815 CH 1, Rank 0
6050 23:25:47.169041 SW Impedance : PASS
6051 23:25:47.169634 DUTY Scan : NO K
6052 23:25:47.172677 ZQ Calibration : PASS
6053 23:25:47.176178 Jitter Meter : NO K
6054 23:25:47.176728 CBT Training : PASS
6055 23:25:47.179036 Write leveling : PASS
6056 23:25:47.182766 RX DQS gating : PASS
6057 23:25:47.183232 RX DQ/DQS(RDDQC) : PASS
6058 23:25:47.186037 TX DQ/DQS : PASS
6059 23:25:47.189513 RX DATLAT : PASS
6060 23:25:47.190119 RX DQ/DQS(Engine): PASS
6061 23:25:47.192551 TX OE : NO K
6062 23:25:47.193101 All Pass.
6063 23:25:47.193460
6064 23:25:47.196449 CH 1, Rank 1
6065 23:25:47.196999 SW Impedance : PASS
6066 23:25:47.199429 DUTY Scan : NO K
6067 23:25:47.202596 ZQ Calibration : PASS
6068 23:25:47.203147 Jitter Meter : NO K
6069 23:25:47.205883 CBT Training : PASS
6070 23:25:47.209170 Write leveling : PASS
6071 23:25:47.209764 RX DQS gating : PASS
6072 23:25:47.212465 RX DQ/DQS(RDDQC) : PASS
6073 23:25:47.213020 TX DQ/DQS : PASS
6074 23:25:47.215826 RX DATLAT : PASS
6075 23:25:47.219048 RX DQ/DQS(Engine): PASS
6076 23:25:47.219507 TX OE : NO K
6077 23:25:47.222331 All Pass.
6078 23:25:47.222836
6079 23:25:47.223204 DramC Write-DBI off
6080 23:25:47.225756 PER_BANK_REFRESH: Hybrid Mode
6081 23:25:47.228715 TX_TRACKING: ON
6082 23:25:47.235736 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6083 23:25:47.238924 [FAST_K] Save calibration result to emmc
6084 23:25:47.245390 dramc_set_vcore_voltage set vcore to 650000
6085 23:25:47.246011 Read voltage for 400, 6
6086 23:25:47.246404 Vio18 = 0
6087 23:25:47.249041 Vcore = 650000
6088 23:25:47.249497 Vdram = 0
6089 23:25:47.249944 Vddq = 0
6090 23:25:47.252068 Vmddr = 0
6091 23:25:47.255536 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6092 23:25:47.262130 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6093 23:25:47.262685 MEM_TYPE=3, freq_sel=20
6094 23:25:47.265691 sv_algorithm_assistance_LP4_800
6095 23:25:47.271821 ============ PULL DRAM RESETB DOWN ============
6096 23:25:47.275147 ========== PULL DRAM RESETB DOWN end =========
6097 23:25:47.278541 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6098 23:25:47.282084 ===================================
6099 23:25:47.285379 LPDDR4 DRAM CONFIGURATION
6100 23:25:47.288714 ===================================
6101 23:25:47.292508 EX_ROW_EN[0] = 0x0
6102 23:25:47.293059 EX_ROW_EN[1] = 0x0
6103 23:25:47.295568 LP4Y_EN = 0x0
6104 23:25:47.296123 WORK_FSP = 0x0
6105 23:25:47.298812 WL = 0x2
6106 23:25:47.299272 RL = 0x2
6107 23:25:47.302347 BL = 0x2
6108 23:25:47.302911 RPST = 0x0
6109 23:25:47.305026 RD_PRE = 0x0
6110 23:25:47.305486 WR_PRE = 0x1
6111 23:25:47.308480 WR_PST = 0x0
6112 23:25:47.308941 DBI_WR = 0x0
6113 23:25:47.311781 DBI_RD = 0x0
6114 23:25:47.312333 OTF = 0x1
6115 23:25:47.315243 ===================================
6116 23:25:47.318701 ===================================
6117 23:25:47.321739 ANA top config
6118 23:25:47.324710 ===================================
6119 23:25:47.328675 DLL_ASYNC_EN = 0
6120 23:25:47.329224 ALL_SLAVE_EN = 1
6121 23:25:47.331844 NEW_RANK_MODE = 1
6122 23:25:47.335115 DLL_IDLE_MODE = 1
6123 23:25:47.338507 LP45_APHY_COMB_EN = 1
6124 23:25:47.339229 TX_ODT_DIS = 1
6125 23:25:47.341915 NEW_8X_MODE = 1
6126 23:25:47.345285 ===================================
6127 23:25:47.348219 ===================================
6128 23:25:47.351457 data_rate = 800
6129 23:25:47.354780 CKR = 1
6130 23:25:47.358099 DQ_P2S_RATIO = 4
6131 23:25:47.361433 ===================================
6132 23:25:47.365130 CA_P2S_RATIO = 4
6133 23:25:47.365753 DQ_CA_OPEN = 0
6134 23:25:47.367804 DQ_SEMI_OPEN = 1
6135 23:25:47.371348 CA_SEMI_OPEN = 1
6136 23:25:47.374815 CA_FULL_RATE = 0
6137 23:25:47.377816 DQ_CKDIV4_EN = 0
6138 23:25:47.381027 CA_CKDIV4_EN = 1
6139 23:25:47.381491 CA_PREDIV_EN = 0
6140 23:25:47.384421 PH8_DLY = 0
6141 23:25:47.387718 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6142 23:25:47.391558 DQ_AAMCK_DIV = 0
6143 23:25:47.394805 CA_AAMCK_DIV = 0
6144 23:25:47.397959 CA_ADMCK_DIV = 4
6145 23:25:47.398519 DQ_TRACK_CA_EN = 0
6146 23:25:47.401700 CA_PICK = 800
6147 23:25:47.404743 CA_MCKIO = 400
6148 23:25:47.407818 MCKIO_SEMI = 400
6149 23:25:47.411322 PLL_FREQ = 3016
6150 23:25:47.414244 DQ_UI_PI_RATIO = 32
6151 23:25:47.417760 CA_UI_PI_RATIO = 32
6152 23:25:47.421466 ===================================
6153 23:25:47.423999 ===================================
6154 23:25:47.424458 memory_type:LPDDR4
6155 23:25:47.428244 GP_NUM : 10
6156 23:25:47.431125 SRAM_EN : 1
6157 23:25:47.431587 MD32_EN : 0
6158 23:25:47.434108 ===================================
6159 23:25:47.437989 [ANA_INIT] >>>>>>>>>>>>>>
6160 23:25:47.440955 <<<<<< [CONFIGURE PHASE]: ANA_TX
6161 23:25:47.444204 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6162 23:25:47.447867 ===================================
6163 23:25:47.451242 data_rate = 800,PCW = 0X7400
6164 23:25:47.454210 ===================================
6165 23:25:47.457397 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6166 23:25:47.461055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6167 23:25:47.474603 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6168 23:25:47.477643 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6169 23:25:47.480916 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6170 23:25:47.483987 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6171 23:25:47.488246 [ANA_INIT] flow start
6172 23:25:47.490829 [ANA_INIT] PLL >>>>>>>>
6173 23:25:47.491382 [ANA_INIT] PLL <<<<<<<<
6174 23:25:47.493987 [ANA_INIT] MIDPI >>>>>>>>
6175 23:25:47.497874 [ANA_INIT] MIDPI <<<<<<<<
6176 23:25:47.498632 [ANA_INIT] DLL >>>>>>>>
6177 23:25:47.501402 [ANA_INIT] flow end
6178 23:25:47.504802 ============ LP4 DIFF to SE enter ============
6179 23:25:47.507268 ============ LP4 DIFF to SE exit ============
6180 23:25:47.510740 [ANA_INIT] <<<<<<<<<<<<<
6181 23:25:47.514426 [Flow] Enable top DCM control >>>>>
6182 23:25:47.517638 [Flow] Enable top DCM control <<<<<
6183 23:25:47.520978 Enable DLL master slave shuffle
6184 23:25:47.528091 ==============================================================
6185 23:25:47.528646 Gating Mode config
6186 23:25:47.534452 ==============================================================
6187 23:25:47.535007 Config description:
6188 23:25:47.543792 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6189 23:25:47.550231 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6190 23:25:47.557561 SELPH_MODE 0: By rank 1: By Phase
6191 23:25:47.560355 ==============================================================
6192 23:25:47.563872 GAT_TRACK_EN = 0
6193 23:25:47.567031 RX_GATING_MODE = 2
6194 23:25:47.570547 RX_GATING_TRACK_MODE = 2
6195 23:25:47.573774 SELPH_MODE = 1
6196 23:25:47.576965 PICG_EARLY_EN = 1
6197 23:25:47.580450 VALID_LAT_VALUE = 1
6198 23:25:47.586957 ==============================================================
6199 23:25:47.590528 Enter into Gating configuration >>>>
6200 23:25:47.593713 Exit from Gating configuration <<<<
6201 23:25:47.594282 Enter into DVFS_PRE_config >>>>>
6202 23:25:47.606887 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6203 23:25:47.610367 Exit from DVFS_PRE_config <<<<<
6204 23:25:47.613773 Enter into PICG configuration >>>>
6205 23:25:47.617009 Exit from PICG configuration <<<<
6206 23:25:47.617468 [RX_INPUT] configuration >>>>>
6207 23:25:47.620142 [RX_INPUT] configuration <<<<<
6208 23:25:47.626789 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6209 23:25:47.630510 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6210 23:25:47.637178 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6211 23:25:47.643434 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6212 23:25:47.650015 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6213 23:25:47.656711 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6214 23:25:47.660367 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6215 23:25:47.663312 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6216 23:25:47.669814 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6217 23:25:47.673235 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6218 23:25:47.676690 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6219 23:25:47.683407 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6220 23:25:47.686594 ===================================
6221 23:25:47.687125 LPDDR4 DRAM CONFIGURATION
6222 23:25:47.689780 ===================================
6223 23:25:47.692953 EX_ROW_EN[0] = 0x0
6224 23:25:47.693502 EX_ROW_EN[1] = 0x0
6225 23:25:47.696354 LP4Y_EN = 0x0
6226 23:25:47.696901 WORK_FSP = 0x0
6227 23:25:47.699699 WL = 0x2
6228 23:25:47.702828 RL = 0x2
6229 23:25:47.703377 BL = 0x2
6230 23:25:47.705964 RPST = 0x0
6231 23:25:47.706428 RD_PRE = 0x0
6232 23:25:47.710116 WR_PRE = 0x1
6233 23:25:47.710694 WR_PST = 0x0
6234 23:25:47.712708 DBI_WR = 0x0
6235 23:25:47.713258 DBI_RD = 0x0
6236 23:25:47.716046 OTF = 0x1
6237 23:25:47.719536 ===================================
6238 23:25:47.722961 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6239 23:25:47.725687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6240 23:25:47.732643 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6241 23:25:47.736056 ===================================
6242 23:25:47.736605 LPDDR4 DRAM CONFIGURATION
6243 23:25:47.739653 ===================================
6244 23:25:47.742345 EX_ROW_EN[0] = 0x10
6245 23:25:47.743062 EX_ROW_EN[1] = 0x0
6246 23:25:47.746220 LP4Y_EN = 0x0
6247 23:25:47.746682 WORK_FSP = 0x0
6248 23:25:47.749090 WL = 0x2
6249 23:25:47.753174 RL = 0x2
6250 23:25:47.753780 BL = 0x2
6251 23:25:47.756323 RPST = 0x0
6252 23:25:47.756876 RD_PRE = 0x0
6253 23:25:47.759693 WR_PRE = 0x1
6254 23:25:47.760246 WR_PST = 0x0
6255 23:25:47.762471 DBI_WR = 0x0
6256 23:25:47.762932 DBI_RD = 0x0
6257 23:25:47.766275 OTF = 0x1
6258 23:25:47.769101 ===================================
6259 23:25:47.772426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6260 23:25:47.778214 nWR fixed to 30
6261 23:25:47.781377 [ModeRegInit_LP4] CH0 RK0
6262 23:25:47.781999 [ModeRegInit_LP4] CH0 RK1
6263 23:25:47.784363 [ModeRegInit_LP4] CH1 RK0
6264 23:25:47.787812 [ModeRegInit_LP4] CH1 RK1
6265 23:25:47.788368 match AC timing 19
6266 23:25:47.794797 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6267 23:25:47.797795 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6268 23:25:47.801303 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6269 23:25:47.808486 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6270 23:25:47.811134 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6271 23:25:47.811692 ==
6272 23:25:47.815122 Dram Type= 6, Freq= 0, CH_0, rank 0
6273 23:25:47.817682 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6274 23:25:47.818148 ==
6275 23:25:47.824193 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6276 23:25:47.831099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6277 23:25:47.834377 [CA 0] Center 36 (8~64) winsize 57
6278 23:25:47.837749 [CA 1] Center 36 (8~64) winsize 57
6279 23:25:47.841490 [CA 2] Center 36 (8~64) winsize 57
6280 23:25:47.842084 [CA 3] Center 36 (8~64) winsize 57
6281 23:25:47.844730 [CA 4] Center 36 (8~64) winsize 57
6282 23:25:47.847538 [CA 5] Center 36 (8~64) winsize 57
6283 23:25:47.848017
6284 23:25:47.854447 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6285 23:25:47.854988
6286 23:25:47.857661 [CATrainingPosCal] consider 1 rank data
6287 23:25:47.861046 u2DelayCellTimex100 = 270/100 ps
6288 23:25:47.864195 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 23:25:47.867281 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 23:25:47.871043 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6291 23:25:47.874413 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6292 23:25:47.877781 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6293 23:25:47.880735 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:25:47.881245
6295 23:25:47.884339 CA PerBit enable=1, Macro0, CA PI delay=36
6296 23:25:47.884798
6297 23:25:47.887660 [CBTSetCACLKResult] CA Dly = 36
6298 23:25:47.891305 CS Dly: 1 (0~32)
6299 23:25:47.891858 ==
6300 23:25:47.894442 Dram Type= 6, Freq= 0, CH_0, rank 1
6301 23:25:47.897660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6302 23:25:47.898212 ==
6303 23:25:47.904153 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6304 23:25:47.907293 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6305 23:25:47.910782 [CA 0] Center 36 (8~64) winsize 57
6306 23:25:47.914071 [CA 1] Center 36 (8~64) winsize 57
6307 23:25:47.917753 [CA 2] Center 36 (8~64) winsize 57
6308 23:25:47.920834 [CA 3] Center 36 (8~64) winsize 57
6309 23:25:47.923976 [CA 4] Center 36 (8~64) winsize 57
6310 23:25:47.928099 [CA 5] Center 36 (8~64) winsize 57
6311 23:25:47.928651
6312 23:25:47.930916 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6313 23:25:47.931385
6314 23:25:47.933867 [CATrainingPosCal] consider 2 rank data
6315 23:25:47.937661 u2DelayCellTimex100 = 270/100 ps
6316 23:25:47.940843 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 23:25:47.943845 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 23:25:47.950635 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6319 23:25:47.953884 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6320 23:25:47.957257 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6321 23:25:47.960401 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 23:25:47.960951
6323 23:25:47.963725 CA PerBit enable=1, Macro0, CA PI delay=36
6324 23:25:47.964184
6325 23:25:47.967124 [CBTSetCACLKResult] CA Dly = 36
6326 23:25:47.967683 CS Dly: 1 (0~32)
6327 23:25:47.968127
6328 23:25:47.970254 ----->DramcWriteLeveling(PI) begin...
6329 23:25:47.973508 ==
6330 23:25:47.977572 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 23:25:47.980570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 23:25:47.981037 ==
6333 23:25:47.983446 Write leveling (Byte 0): 40 => 8
6334 23:25:47.987118 Write leveling (Byte 1): 40 => 8
6335 23:25:47.990852 DramcWriteLeveling(PI) end<-----
6336 23:25:47.991405
6337 23:25:47.991763 ==
6338 23:25:47.993622 Dram Type= 6, Freq= 0, CH_0, rank 0
6339 23:25:47.996883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6340 23:25:47.997343 ==
6341 23:25:48.000253 [Gating] SW mode calibration
6342 23:25:48.006925 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6343 23:25:48.010316 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6344 23:25:48.017431 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6345 23:25:48.020694 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6346 23:25:48.023970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6347 23:25:48.030581 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6348 23:25:48.033726 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6349 23:25:48.036910 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6350 23:25:48.043505 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6351 23:25:48.046834 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6352 23:25:48.049822 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 23:25:48.053207 Total UI for P1: 0, mck2ui 16
6354 23:25:48.057208 best dqsien dly found for B0: ( 0, 14, 24)
6355 23:25:48.059699 Total UI for P1: 0, mck2ui 16
6356 23:25:48.063496 best dqsien dly found for B1: ( 0, 14, 24)
6357 23:25:48.066305 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6358 23:25:48.069656 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6359 23:25:48.070276
6360 23:25:48.076646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6361 23:25:48.079655 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6362 23:25:48.083285 [Gating] SW calibration Done
6363 23:25:48.083692 ==
6364 23:25:48.087071 Dram Type= 6, Freq= 0, CH_0, rank 0
6365 23:25:48.089671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6366 23:25:48.090086 ==
6367 23:25:48.090407 RX Vref Scan: 0
6368 23:25:48.090707
6369 23:25:48.093424 RX Vref 0 -> 0, step: 1
6370 23:25:48.093875
6371 23:25:48.096272 RX Delay -410 -> 252, step: 16
6372 23:25:48.100444 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6373 23:25:48.106576 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6374 23:25:48.109680 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6375 23:25:48.113198 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6376 23:25:48.116742 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6377 23:25:48.122994 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6378 23:25:48.126385 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6379 23:25:48.129700 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6380 23:25:48.133274 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6381 23:25:48.139726 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6382 23:25:48.142848 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6383 23:25:48.146367 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6384 23:25:48.150039 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6385 23:25:48.156100 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6386 23:25:48.160104 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6387 23:25:48.162917 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6388 23:25:48.163521 ==
6389 23:25:48.165933 Dram Type= 6, Freq= 0, CH_0, rank 0
6390 23:25:48.172849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6391 23:25:48.173386 ==
6392 23:25:48.173811 DQS Delay:
6393 23:25:48.174150 DQS0 = 27, DQS1 = 35
6394 23:25:48.176482 DQM Delay:
6395 23:25:48.176939 DQM0 = 12, DQM1 = 12
6396 23:25:48.179543 DQ Delay:
6397 23:25:48.182477 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6398 23:25:48.182932 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6399 23:25:48.185704 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6400 23:25:48.189253 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6401 23:25:48.189756
6402 23:25:48.190115
6403 23:25:48.193056 ==
6404 23:25:48.196087 Dram Type= 6, Freq= 0, CH_0, rank 0
6405 23:25:48.199245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6406 23:25:48.199798 ==
6407 23:25:48.200150
6408 23:25:48.200471
6409 23:25:48.202317 TX Vref Scan disable
6410 23:25:48.202819 == TX Byte 0 ==
6411 23:25:48.206204 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6412 23:25:48.212520 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6413 23:25:48.213099 == TX Byte 1 ==
6414 23:25:48.215779 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6415 23:25:48.222905 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6416 23:25:48.223471 ==
6417 23:25:48.225475 Dram Type= 6, Freq= 0, CH_0, rank 0
6418 23:25:48.229041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 23:25:48.229643 ==
6420 23:25:48.230010
6421 23:25:48.230336
6422 23:25:48.232594 TX Vref Scan disable
6423 23:25:48.233050 == TX Byte 0 ==
6424 23:25:48.235875 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6425 23:25:48.242584 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6426 23:25:48.243138 == TX Byte 1 ==
6427 23:25:48.245952 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6428 23:25:48.252710 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6429 23:25:48.253256
6430 23:25:48.253724 [DATLAT]
6431 23:25:48.254275 Freq=400, CH0 RK0
6432 23:25:48.254620
6433 23:25:48.255505 DATLAT Default: 0xf
6434 23:25:48.255961 0, 0xFFFF, sum = 0
6435 23:25:48.259297 1, 0xFFFF, sum = 0
6436 23:25:48.259854 2, 0xFFFF, sum = 0
6437 23:25:48.262331 3, 0xFFFF, sum = 0
6438 23:25:48.266007 4, 0xFFFF, sum = 0
6439 23:25:48.266565 5, 0xFFFF, sum = 0
6440 23:25:48.269334 6, 0xFFFF, sum = 0
6441 23:25:48.270150 7, 0xFFFF, sum = 0
6442 23:25:48.272236 8, 0xFFFF, sum = 0
6443 23:25:48.272790 9, 0xFFFF, sum = 0
6444 23:25:48.275353 10, 0xFFFF, sum = 0
6445 23:25:48.275841 11, 0xFFFF, sum = 0
6446 23:25:48.279501 12, 0xFFFF, sum = 0
6447 23:25:48.280056 13, 0x0, sum = 1
6448 23:25:48.282141 14, 0x0, sum = 2
6449 23:25:48.282606 15, 0x0, sum = 3
6450 23:25:48.285288 16, 0x0, sum = 4
6451 23:25:48.285787 best_step = 14
6452 23:25:48.286149
6453 23:25:48.286476 ==
6454 23:25:48.289101 Dram Type= 6, Freq= 0, CH_0, rank 0
6455 23:25:48.292412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6456 23:25:48.295619 ==
6457 23:25:48.296168 RX Vref Scan: 1
6458 23:25:48.296527
6459 23:25:48.298527 RX Vref 0 -> 0, step: 1
6460 23:25:48.298985
6461 23:25:48.302018 RX Delay -311 -> 252, step: 8
6462 23:25:48.302564
6463 23:25:48.305545 Set Vref, RX VrefLevel [Byte0]: 56
6464 23:25:48.309271 [Byte1]: 55
6465 23:25:48.309949
6466 23:25:48.311923 Final RX Vref Byte 0 = 56 to rank0
6467 23:25:48.315198 Final RX Vref Byte 1 = 55 to rank0
6468 23:25:48.318497 Final RX Vref Byte 0 = 56 to rank1
6469 23:25:48.322079 Final RX Vref Byte 1 = 55 to rank1==
6470 23:25:48.325196 Dram Type= 6, Freq= 0, CH_0, rank 0
6471 23:25:48.328634 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 23:25:48.329186 ==
6473 23:25:48.331796 DQS Delay:
6474 23:25:48.332253 DQS0 = 28, DQS1 = 36
6475 23:25:48.335327 DQM Delay:
6476 23:25:48.335814 DQM0 = 11, DQM1 = 14
6477 23:25:48.336196 DQ Delay:
6478 23:25:48.338239 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6479 23:25:48.341909 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6480 23:25:48.345070 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6481 23:25:48.348243 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6482 23:25:48.348704
6483 23:25:48.349109
6484 23:25:48.358664 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b4, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6485 23:25:48.361810 CH0 RK0: MR19=C0C, MR18=C8B4
6486 23:25:48.365011 CH0_RK0: MR19=0xC0C, MR18=0xC8B4, DQSOSC=385, MR23=63, INC=398, DEC=265
6487 23:25:48.368644 ==
6488 23:25:48.369223 Dram Type= 6, Freq= 0, CH_0, rank 1
6489 23:25:48.374958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6490 23:25:48.375524 ==
6491 23:25:48.377898 [Gating] SW mode calibration
6492 23:25:48.384822 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6493 23:25:48.388085 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6494 23:25:48.395065 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6495 23:25:48.398014 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6496 23:25:48.401479 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6497 23:25:48.408025 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6498 23:25:48.411520 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6499 23:25:48.414520 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6500 23:25:48.420820 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6501 23:25:48.424806 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6502 23:25:48.428182 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 23:25:48.430823 Total UI for P1: 0, mck2ui 16
6504 23:25:48.434257 best dqsien dly found for B0: ( 0, 14, 24)
6505 23:25:48.437893 Total UI for P1: 0, mck2ui 16
6506 23:25:48.441190 best dqsien dly found for B1: ( 0, 14, 24)
6507 23:25:48.444712 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6508 23:25:48.447713 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6509 23:25:48.448181
6510 23:25:48.454270 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6511 23:25:48.457474 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6512 23:25:48.457966 [Gating] SW calibration Done
6513 23:25:48.460999 ==
6514 23:25:48.464106 Dram Type= 6, Freq= 0, CH_0, rank 1
6515 23:25:48.467701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6516 23:25:48.468259 ==
6517 23:25:48.468612 RX Vref Scan: 0
6518 23:25:48.468939
6519 23:25:48.470791 RX Vref 0 -> 0, step: 1
6520 23:25:48.471346
6521 23:25:48.474103 RX Delay -410 -> 252, step: 16
6522 23:25:48.477511 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6523 23:25:48.480999 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6524 23:25:48.487717 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6525 23:25:48.491076 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6526 23:25:48.494547 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6527 23:25:48.497477 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6528 23:25:48.504618 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6529 23:25:48.508062 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6530 23:25:48.511016 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6531 23:25:48.514166 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6532 23:25:48.521001 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6533 23:25:48.524890 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6534 23:25:48.527680 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6535 23:25:48.530571 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6536 23:25:48.537984 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6537 23:25:48.541307 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6538 23:25:48.541906 ==
6539 23:25:48.544079 Dram Type= 6, Freq= 0, CH_0, rank 1
6540 23:25:48.547193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6541 23:25:48.547666 ==
6542 23:25:48.550871 DQS Delay:
6543 23:25:48.551353 DQS0 = 27, DQS1 = 35
6544 23:25:48.554009 DQM Delay:
6545 23:25:48.554560 DQM0 = 12, DQM1 = 10
6546 23:25:48.554918 DQ Delay:
6547 23:25:48.557011 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6548 23:25:48.560325 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6549 23:25:48.564149 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6550 23:25:48.567367 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6551 23:25:48.567927
6552 23:25:48.568282
6553 23:25:48.568607 ==
6554 23:25:48.570484 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 23:25:48.576971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 23:25:48.577430 ==
6557 23:25:48.577841
6558 23:25:48.578172
6559 23:25:48.578485 TX Vref Scan disable
6560 23:25:48.580605 == TX Byte 0 ==
6561 23:25:48.583791 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6562 23:25:48.587422 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6563 23:25:48.590585 == TX Byte 1 ==
6564 23:25:48.594396 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6565 23:25:48.597286 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6566 23:25:48.597778 ==
6567 23:25:48.600743 Dram Type= 6, Freq= 0, CH_0, rank 1
6568 23:25:48.607830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6569 23:25:48.608390 ==
6570 23:25:48.608798
6571 23:25:48.609139
6572 23:25:48.609452 TX Vref Scan disable
6573 23:25:48.610251 == TX Byte 0 ==
6574 23:25:48.614073 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6575 23:25:48.617635 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6576 23:25:48.620487 == TX Byte 1 ==
6577 23:25:48.624743 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6578 23:25:48.627203 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6579 23:25:48.627659
6580 23:25:48.630090 [DATLAT]
6581 23:25:48.630544 Freq=400, CH0 RK1
6582 23:25:48.630898
6583 23:25:48.634121 DATLAT Default: 0xe
6584 23:25:48.634575 0, 0xFFFF, sum = 0
6585 23:25:48.637256 1, 0xFFFF, sum = 0
6586 23:25:48.637757 2, 0xFFFF, sum = 0
6587 23:25:48.640626 3, 0xFFFF, sum = 0
6588 23:25:48.641086 4, 0xFFFF, sum = 0
6589 23:25:48.644398 5, 0xFFFF, sum = 0
6590 23:25:48.644958 6, 0xFFFF, sum = 0
6591 23:25:48.647444 7, 0xFFFF, sum = 0
6592 23:25:48.647906 8, 0xFFFF, sum = 0
6593 23:25:48.650548 9, 0xFFFF, sum = 0
6594 23:25:48.651012 10, 0xFFFF, sum = 0
6595 23:25:48.654316 11, 0xFFFF, sum = 0
6596 23:25:48.654877 12, 0xFFFF, sum = 0
6597 23:25:48.657032 13, 0x0, sum = 1
6598 23:25:48.657490 14, 0x0, sum = 2
6599 23:25:48.660574 15, 0x0, sum = 3
6600 23:25:48.661130 16, 0x0, sum = 4
6601 23:25:48.663976 best_step = 14
6602 23:25:48.664485
6603 23:25:48.664838 ==
6604 23:25:48.667205 Dram Type= 6, Freq= 0, CH_0, rank 1
6605 23:25:48.670594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6606 23:25:48.671155 ==
6607 23:25:48.674154 RX Vref Scan: 0
6608 23:25:48.674610
6609 23:25:48.674964 RX Vref 0 -> 0, step: 1
6610 23:25:48.675290
6611 23:25:48.677244 RX Delay -311 -> 252, step: 8
6612 23:25:48.684720 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6613 23:25:48.688569 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6614 23:25:48.691730 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6615 23:25:48.694992 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6616 23:25:48.701929 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6617 23:25:48.704912 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6618 23:25:48.708385 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6619 23:25:48.711599 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6620 23:25:48.718405 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6621 23:25:48.722056 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6622 23:25:48.725252 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6623 23:25:48.728272 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6624 23:25:48.734976 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6625 23:25:48.738525 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6626 23:25:48.742109 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6627 23:25:48.744749 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6628 23:25:48.748433 ==
6629 23:25:48.751314 Dram Type= 6, Freq= 0, CH_0, rank 1
6630 23:25:48.755853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6631 23:25:48.756408 ==
6632 23:25:48.756768 DQS Delay:
6633 23:25:48.758497 DQS0 = 24, DQS1 = 32
6634 23:25:48.758956 DQM Delay:
6635 23:25:48.761658 DQM0 = 8, DQM1 = 10
6636 23:25:48.762118 DQ Delay:
6637 23:25:48.765302 DQ0 =8, DQ1 =8, DQ2 =4, DQ3 =8
6638 23:25:48.768245 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6639 23:25:48.771818 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6640 23:25:48.774994 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6641 23:25:48.775449
6642 23:25:48.775803
6643 23:25:48.782233 [DQSOSCAuto] RK1, (LSB)MR18= 0xb354, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 387 ps
6644 23:25:48.785681 CH0 RK1: MR19=C0C, MR18=B354
6645 23:25:48.791569 CH0_RK1: MR19=0xC0C, MR18=0xB354, DQSOSC=387, MR23=63, INC=394, DEC=262
6646 23:25:48.795215 [RxdqsGatingPostProcess] freq 400
6647 23:25:48.798241 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6648 23:25:48.801641 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 23:25:48.805444 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 23:25:48.808445 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 23:25:48.811304 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 23:25:48.814928 best DQS0 dly(2T, 0.5T) = (0, 10)
6653 23:25:48.818820 best DQS1 dly(2T, 0.5T) = (0, 10)
6654 23:25:48.822036 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6655 23:25:48.825027 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6656 23:25:48.828284 Pre-setting of DQS Precalculation
6657 23:25:48.831123 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6658 23:25:48.831579 ==
6659 23:25:48.834499 Dram Type= 6, Freq= 0, CH_1, rank 0
6660 23:25:48.841376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6661 23:25:48.841981 ==
6662 23:25:48.844499 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6663 23:25:48.851394 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6664 23:25:48.854309 [CA 0] Center 36 (8~64) winsize 57
6665 23:25:48.857968 [CA 1] Center 36 (8~64) winsize 57
6666 23:25:48.861537 [CA 2] Center 36 (8~64) winsize 57
6667 23:25:48.864350 [CA 3] Center 36 (8~64) winsize 57
6668 23:25:48.868234 [CA 4] Center 36 (8~64) winsize 57
6669 23:25:48.870970 [CA 5] Center 36 (8~64) winsize 57
6670 23:25:48.871425
6671 23:25:48.874464 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6672 23:25:48.874919
6673 23:25:48.877720 [CATrainingPosCal] consider 1 rank data
6674 23:25:48.881393 u2DelayCellTimex100 = 270/100 ps
6675 23:25:48.884383 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 23:25:48.887784 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 23:25:48.891688 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6678 23:25:48.894827 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6679 23:25:48.897671 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6680 23:25:48.901667 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:25:48.904857
6682 23:25:48.908141 CA PerBit enable=1, Macro0, CA PI delay=36
6683 23:25:48.908694
6684 23:25:48.911058 [CBTSetCACLKResult] CA Dly = 36
6685 23:25:48.911550 CS Dly: 1 (0~32)
6686 23:25:48.911968 ==
6687 23:25:48.914392 Dram Type= 6, Freq= 0, CH_1, rank 1
6688 23:25:48.917738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6689 23:25:48.918295 ==
6690 23:25:48.924585 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6691 23:25:48.931147 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6692 23:25:48.934784 [CA 0] Center 36 (8~64) winsize 57
6693 23:25:48.937868 [CA 1] Center 36 (8~64) winsize 57
6694 23:25:48.941176 [CA 2] Center 36 (8~64) winsize 57
6695 23:25:48.944455 [CA 3] Center 36 (8~64) winsize 57
6696 23:25:48.947534 [CA 4] Center 36 (8~64) winsize 57
6697 23:25:48.947993 [CA 5] Center 36 (8~64) winsize 57
6698 23:25:48.948350
6699 23:25:48.954338 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6700 23:25:48.954794
6701 23:25:48.957570 [CATrainingPosCal] consider 2 rank data
6702 23:25:48.960729 u2DelayCellTimex100 = 270/100 ps
6703 23:25:48.964342 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 23:25:48.967743 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 23:25:48.970535 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6706 23:25:48.974219 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6707 23:25:48.977412 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6708 23:25:48.981398 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 23:25:48.982030
6710 23:25:48.984472 CA PerBit enable=1, Macro0, CA PI delay=36
6711 23:25:48.984925
6712 23:25:48.987415 [CBTSetCACLKResult] CA Dly = 36
6713 23:25:48.991170 CS Dly: 1 (0~32)
6714 23:25:48.991720
6715 23:25:48.994733 ----->DramcWriteLeveling(PI) begin...
6716 23:25:48.995299 ==
6717 23:25:48.997286 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 23:25:49.001070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 23:25:49.001698 ==
6720 23:25:49.004203 Write leveling (Byte 0): 40 => 8
6721 23:25:49.007349 Write leveling (Byte 1): 40 => 8
6722 23:25:49.010902 DramcWriteLeveling(PI) end<-----
6723 23:25:49.011477
6724 23:25:49.011933 ==
6725 23:25:49.013913 Dram Type= 6, Freq= 0, CH_1, rank 0
6726 23:25:49.017539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6727 23:25:49.018143 ==
6728 23:25:49.021170 [Gating] SW mode calibration
6729 23:25:49.027292 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6730 23:25:49.033753 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6731 23:25:49.037293 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6732 23:25:49.043654 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6733 23:25:49.047032 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6734 23:25:49.050382 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6735 23:25:49.056822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6736 23:25:49.060314 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6737 23:25:49.063759 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6738 23:25:49.067028 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6739 23:25:49.073378 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 23:25:49.077164 Total UI for P1: 0, mck2ui 16
6741 23:25:49.080229 best dqsien dly found for B0: ( 0, 14, 24)
6742 23:25:49.083344 Total UI for P1: 0, mck2ui 16
6743 23:25:49.086612 best dqsien dly found for B1: ( 0, 14, 24)
6744 23:25:49.090037 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6745 23:25:49.093398 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6746 23:25:49.094198
6747 23:25:49.096569 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6748 23:25:49.099847 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6749 23:25:49.103161 [Gating] SW calibration Done
6750 23:25:49.103746 ==
6751 23:25:49.106633 Dram Type= 6, Freq= 0, CH_1, rank 0
6752 23:25:49.109903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6753 23:25:49.110326 ==
6754 23:25:49.113454 RX Vref Scan: 0
6755 23:25:49.113916
6756 23:25:49.116745 RX Vref 0 -> 0, step: 1
6757 23:25:49.117163
6758 23:25:49.117487 RX Delay -410 -> 252, step: 16
6759 23:25:49.123793 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6760 23:25:49.126701 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6761 23:25:49.130406 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6762 23:25:49.133440 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6763 23:25:49.140509 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6764 23:25:49.143629 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6765 23:25:49.146627 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6766 23:25:49.149927 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6767 23:25:49.156995 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6768 23:25:49.160098 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6769 23:25:49.163473 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6770 23:25:49.167011 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6771 23:25:49.173466 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6772 23:25:49.176423 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6773 23:25:49.179926 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6774 23:25:49.186655 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6775 23:25:49.187233 ==
6776 23:25:49.189864 Dram Type= 6, Freq= 0, CH_1, rank 0
6777 23:25:49.193277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6778 23:25:49.193888 ==
6779 23:25:49.194254 DQS Delay:
6780 23:25:49.196551 DQS0 = 35, DQS1 = 35
6781 23:25:49.197097 DQM Delay:
6782 23:25:49.199737 DQM0 = 18, DQM1 = 13
6783 23:25:49.200474 DQ Delay:
6784 23:25:49.202855 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =16
6785 23:25:49.205993 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6786 23:25:49.209898 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6787 23:25:49.212935 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6788 23:25:49.213390
6789 23:25:49.213806
6790 23:25:49.214143 ==
6791 23:25:49.216238 Dram Type= 6, Freq= 0, CH_1, rank 0
6792 23:25:49.219423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6793 23:25:49.219886 ==
6794 23:25:49.220243
6795 23:25:49.220571
6796 23:25:49.223026 TX Vref Scan disable
6797 23:25:49.226282 == TX Byte 0 ==
6798 23:25:49.229633 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6799 23:25:49.233190 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6800 23:25:49.233782 == TX Byte 1 ==
6801 23:25:49.240253 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6802 23:25:49.243141 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6803 23:25:49.243695 ==
6804 23:25:49.246502 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 23:25:49.249701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 23:25:49.250275 ==
6807 23:25:49.250687
6808 23:25:49.251041
6809 23:25:49.252896 TX Vref Scan disable
6810 23:25:49.256725 == TX Byte 0 ==
6811 23:25:49.259436 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6812 23:25:49.262861 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6813 23:25:49.266145 == TX Byte 1 ==
6814 23:25:49.269836 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6815 23:25:49.273367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6816 23:25:49.273978
6817 23:25:49.274338 [DATLAT]
6818 23:25:49.275884 Freq=400, CH1 RK0
6819 23:25:49.276337
6820 23:25:49.276691 DATLAT Default: 0xf
6821 23:25:49.279959 0, 0xFFFF, sum = 0
6822 23:25:49.280518 1, 0xFFFF, sum = 0
6823 23:25:49.282763 2, 0xFFFF, sum = 0
6824 23:25:49.283327 3, 0xFFFF, sum = 0
6825 23:25:49.285935 4, 0xFFFF, sum = 0
6826 23:25:49.289815 5, 0xFFFF, sum = 0
6827 23:25:49.290277 6, 0xFFFF, sum = 0
6828 23:25:49.292516 7, 0xFFFF, sum = 0
6829 23:25:49.292976 8, 0xFFFF, sum = 0
6830 23:25:49.296309 9, 0xFFFF, sum = 0
6831 23:25:49.296875 10, 0xFFFF, sum = 0
6832 23:25:49.299580 11, 0xFFFF, sum = 0
6833 23:25:49.300137 12, 0xFFFF, sum = 0
6834 23:25:49.302400 13, 0x0, sum = 1
6835 23:25:49.302926 14, 0x0, sum = 2
6836 23:25:49.305981 15, 0x0, sum = 3
6837 23:25:49.306536 16, 0x0, sum = 4
6838 23:25:49.309133 best_step = 14
6839 23:25:49.309605
6840 23:25:49.309963 ==
6841 23:25:49.312769 Dram Type= 6, Freq= 0, CH_1, rank 0
6842 23:25:49.316159 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6843 23:25:49.316620 ==
6844 23:25:49.316977 RX Vref Scan: 1
6845 23:25:49.317308
6846 23:25:49.319036 RX Vref 0 -> 0, step: 1
6847 23:25:49.319488
6848 23:25:49.322599 RX Delay -311 -> 252, step: 8
6849 23:25:49.323150
6850 23:25:49.326128 Set Vref, RX VrefLevel [Byte0]: 54
6851 23:25:49.329272 [Byte1]: 54
6852 23:25:49.332873
6853 23:25:49.333325 Final RX Vref Byte 0 = 54 to rank0
6854 23:25:49.335933 Final RX Vref Byte 1 = 54 to rank0
6855 23:25:49.339306 Final RX Vref Byte 0 = 54 to rank1
6856 23:25:49.342638 Final RX Vref Byte 1 = 54 to rank1==
6857 23:25:49.346238 Dram Type= 6, Freq= 0, CH_1, rank 0
6858 23:25:49.352500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 23:25:49.353001 ==
6860 23:25:49.353330 DQS Delay:
6861 23:25:49.356247 DQS0 = 32, DQS1 = 32
6862 23:25:49.356681 DQM Delay:
6863 23:25:49.357006 DQM0 = 13, DQM1 = 9
6864 23:25:49.359105 DQ Delay:
6865 23:25:49.363024 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6866 23:25:49.366237 DQ4 =12, DQ5 =24, DQ6 =20, DQ7 =12
6867 23:25:49.366698 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6868 23:25:49.369177 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6869 23:25:49.369703
6870 23:25:49.372709
6871 23:25:49.379587 [DQSOSCAuto] RK0, (LSB)MR18= 0x8ec7, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6872 23:25:49.382899 CH1 RK0: MR19=C0C, MR18=8EC7
6873 23:25:49.389411 CH1_RK0: MR19=0xC0C, MR18=0x8EC7, DQSOSC=385, MR23=63, INC=398, DEC=265
6874 23:25:49.389920 ==
6875 23:25:49.393403 Dram Type= 6, Freq= 0, CH_1, rank 1
6876 23:25:49.396394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6877 23:25:49.396861 ==
6878 23:25:49.399732 [Gating] SW mode calibration
6879 23:25:49.406217 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6880 23:25:49.409661 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6881 23:25:49.416544 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6882 23:25:49.419917 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6883 23:25:49.423423 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6884 23:25:49.429514 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6885 23:25:49.432796 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6886 23:25:49.436436 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6887 23:25:49.442672 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6888 23:25:49.446143 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6889 23:25:49.449070 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 23:25:49.452448 Total UI for P1: 0, mck2ui 16
6891 23:25:49.455609 best dqsien dly found for B0: ( 0, 14, 24)
6892 23:25:49.459511 Total UI for P1: 0, mck2ui 16
6893 23:25:49.462384 best dqsien dly found for B1: ( 0, 14, 24)
6894 23:25:49.465720 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6895 23:25:49.472781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6896 23:25:49.473338
6897 23:25:49.475838 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6898 23:25:49.479277 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6899 23:25:49.482321 [Gating] SW calibration Done
6900 23:25:49.482785 ==
6901 23:25:49.485760 Dram Type= 6, Freq= 0, CH_1, rank 1
6902 23:25:49.489134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6903 23:25:49.489639 ==
6904 23:25:49.492137 RX Vref Scan: 0
6905 23:25:49.492598
6906 23:25:49.492954 RX Vref 0 -> 0, step: 1
6907 23:25:49.493344
6908 23:25:49.495335 RX Delay -410 -> 252, step: 16
6909 23:25:49.499370 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6910 23:25:49.505689 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6911 23:25:49.509228 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6912 23:25:49.512409 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6913 23:25:49.515809 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6914 23:25:49.522012 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6915 23:25:49.525536 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6916 23:25:49.528879 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6917 23:25:49.532507 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6918 23:25:49.538831 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6919 23:25:49.542550 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6920 23:25:49.545857 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6921 23:25:49.548461 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6922 23:25:49.555301 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6923 23:25:49.558984 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6924 23:25:49.561710 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6925 23:25:49.562177 ==
6926 23:25:49.565512 Dram Type= 6, Freq= 0, CH_1, rank 1
6927 23:25:49.571925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6928 23:25:49.572476 ==
6929 23:25:49.572837 DQS Delay:
6930 23:25:49.575481 DQS0 = 35, DQS1 = 35
6931 23:25:49.576044 DQM Delay:
6932 23:25:49.576412 DQM0 = 18, DQM1 = 14
6933 23:25:49.578357 DQ Delay:
6934 23:25:49.581507 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6935 23:25:49.584709 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6936 23:25:49.585172 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6937 23:25:49.591897 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6938 23:25:49.592435
6939 23:25:49.592790
6940 23:25:49.593119 ==
6941 23:25:49.595051 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 23:25:49.598326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 23:25:49.598785 ==
6944 23:25:49.599136
6945 23:25:49.599464
6946 23:25:49.601900 TX Vref Scan disable
6947 23:25:49.602356 == TX Byte 0 ==
6948 23:25:49.604957 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6949 23:25:49.611729 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6950 23:25:49.612269 == TX Byte 1 ==
6951 23:25:49.615058 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6952 23:25:49.621722 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6953 23:25:49.622278 ==
6954 23:25:49.625268 Dram Type= 6, Freq= 0, CH_1, rank 1
6955 23:25:49.628479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6956 23:25:49.628937 ==
6957 23:25:49.629346
6958 23:25:49.629727
6959 23:25:49.631756 TX Vref Scan disable
6960 23:25:49.632308 == TX Byte 0 ==
6961 23:25:49.634648 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6962 23:25:49.641680 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6963 23:25:49.642233 == TX Byte 1 ==
6964 23:25:49.645172 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6965 23:25:49.651758 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6966 23:25:49.652328
6967 23:25:49.652700 [DATLAT]
6968 23:25:49.653034 Freq=400, CH1 RK1
6969 23:25:49.654920
6970 23:25:49.655427 DATLAT Default: 0xe
6971 23:25:49.658037 0, 0xFFFF, sum = 0
6972 23:25:49.658502 1, 0xFFFF, sum = 0
6973 23:25:49.661487 2, 0xFFFF, sum = 0
6974 23:25:49.662102 3, 0xFFFF, sum = 0
6975 23:25:49.665296 4, 0xFFFF, sum = 0
6976 23:25:49.665911 5, 0xFFFF, sum = 0
6977 23:25:49.668332 6, 0xFFFF, sum = 0
6978 23:25:49.668888 7, 0xFFFF, sum = 0
6979 23:25:49.671316 8, 0xFFFF, sum = 0
6980 23:25:49.671777 9, 0xFFFF, sum = 0
6981 23:25:49.674886 10, 0xFFFF, sum = 0
6982 23:25:49.675390 11, 0xFFFF, sum = 0
6983 23:25:49.678144 12, 0xFFFF, sum = 0
6984 23:25:49.678710 13, 0x0, sum = 1
6985 23:25:49.681465 14, 0x0, sum = 2
6986 23:25:49.681982 15, 0x0, sum = 3
6987 23:25:49.684429 16, 0x0, sum = 4
6988 23:25:49.684894 best_step = 14
6989 23:25:49.685247
6990 23:25:49.685630 ==
6991 23:25:49.687787 Dram Type= 6, Freq= 0, CH_1, rank 1
6992 23:25:49.694861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6993 23:25:49.695418 ==
6994 23:25:49.695820 RX Vref Scan: 0
6995 23:25:49.696152
6996 23:25:49.697819 RX Vref 0 -> 0, step: 1
6997 23:25:49.698272
6998 23:25:49.701286 RX Delay -311 -> 252, step: 8
6999 23:25:49.707609 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7000 23:25:49.711223 iDelay=217, Bit 1, Center -24 (-247 ~ 200) 448
7001 23:25:49.714530 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7002 23:25:49.717609 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
7003 23:25:49.724973 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7004 23:25:49.728044 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7005 23:25:49.731333 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7006 23:25:49.734147 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
7007 23:25:49.738416 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7008 23:25:49.744787 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7009 23:25:49.748086 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
7010 23:25:49.751089 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7011 23:25:49.758170 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7012 23:25:49.761038 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7013 23:25:49.764879 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7014 23:25:49.767846 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7015 23:25:49.768398 ==
7016 23:25:49.771379 Dram Type= 6, Freq= 0, CH_1, rank 1
7017 23:25:49.777775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7018 23:25:49.778375 ==
7019 23:25:49.778945 DQS Delay:
7020 23:25:49.780879 DQS0 = 28, DQS1 = 32
7021 23:25:49.781342 DQM Delay:
7022 23:25:49.784323 DQM0 = 11, DQM1 = 11
7023 23:25:49.784874 DQ Delay:
7024 23:25:49.787187 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
7025 23:25:49.790774 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =12
7026 23:25:49.794394 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7027 23:25:49.797951 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7028 23:25:49.798503
7029 23:25:49.798855
7030 23:25:49.804612 [DQSOSCAuto] RK1, (LSB)MR18= 0xc152, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7031 23:25:49.807445 CH1 RK1: MR19=C0C, MR18=C152
7032 23:25:49.814140 CH1_RK1: MR19=0xC0C, MR18=0xC152, DQSOSC=385, MR23=63, INC=398, DEC=265
7033 23:25:49.817693 [RxdqsGatingPostProcess] freq 400
7034 23:25:49.820702 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7035 23:25:49.823826 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 23:25:49.827170 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 23:25:49.830780 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 23:25:49.833725 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 23:25:49.837230 best DQS0 dly(2T, 0.5T) = (0, 10)
7040 23:25:49.840531 best DQS1 dly(2T, 0.5T) = (0, 10)
7041 23:25:49.843650 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7042 23:25:49.847552 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7043 23:25:49.850309 Pre-setting of DQS Precalculation
7044 23:25:49.853551 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7045 23:25:49.863508 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7046 23:25:49.870622 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7047 23:25:49.871182
7048 23:25:49.871536
7049 23:25:49.874015 [Calibration Summary] 800 Mbps
7050 23:25:49.874568 CH 0, Rank 0
7051 23:25:49.877626 SW Impedance : PASS
7052 23:25:49.878179 DUTY Scan : NO K
7053 23:25:49.880322 ZQ Calibration : PASS
7054 23:25:49.883843 Jitter Meter : NO K
7055 23:25:49.884395 CBT Training : PASS
7056 23:25:49.887194 Write leveling : PASS
7057 23:25:49.887650 RX DQS gating : PASS
7058 23:25:49.890242 RX DQ/DQS(RDDQC) : PASS
7059 23:25:49.893816 TX DQ/DQS : PASS
7060 23:25:49.894375 RX DATLAT : PASS
7061 23:25:49.897264 RX DQ/DQS(Engine): PASS
7062 23:25:49.900583 TX OE : NO K
7063 23:25:49.901147 All Pass.
7064 23:25:49.901510
7065 23:25:49.901903 CH 0, Rank 1
7066 23:25:49.903991 SW Impedance : PASS
7067 23:25:49.906996 DUTY Scan : NO K
7068 23:25:49.907564 ZQ Calibration : PASS
7069 23:25:49.910742 Jitter Meter : NO K
7070 23:25:49.913701 CBT Training : PASS
7071 23:25:49.914238 Write leveling : NO K
7072 23:25:49.917060 RX DQS gating : PASS
7073 23:25:49.920665 RX DQ/DQS(RDDQC) : PASS
7074 23:25:49.921234 TX DQ/DQS : PASS
7075 23:25:49.923464 RX DATLAT : PASS
7076 23:25:49.926909 RX DQ/DQS(Engine): PASS
7077 23:25:49.927469 TX OE : NO K
7078 23:25:49.930377 All Pass.
7079 23:25:49.930840
7080 23:25:49.931200 CH 1, Rank 0
7081 23:25:49.933731 SW Impedance : PASS
7082 23:25:49.934302 DUTY Scan : NO K
7083 23:25:49.936817 ZQ Calibration : PASS
7084 23:25:49.940210 Jitter Meter : NO K
7085 23:25:49.940673 CBT Training : PASS
7086 23:25:49.943469 Write leveling : PASS
7087 23:25:49.946949 RX DQS gating : PASS
7088 23:25:49.947518 RX DQ/DQS(RDDQC) : PASS
7089 23:25:49.950136 TX DQ/DQS : PASS
7090 23:25:49.950722 RX DATLAT : PASS
7091 23:25:49.953322 RX DQ/DQS(Engine): PASS
7092 23:25:49.956772 TX OE : NO K
7093 23:25:49.957346 All Pass.
7094 23:25:49.957763
7095 23:25:49.958102 CH 1, Rank 1
7096 23:25:49.959865 SW Impedance : PASS
7097 23:25:49.963134 DUTY Scan : NO K
7098 23:25:49.963839 ZQ Calibration : PASS
7099 23:25:49.966752 Jitter Meter : NO K
7100 23:25:49.969785 CBT Training : PASS
7101 23:25:49.970364 Write leveling : NO K
7102 23:25:49.973313 RX DQS gating : PASS
7103 23:25:49.977300 RX DQ/DQS(RDDQC) : PASS
7104 23:25:49.977917 TX DQ/DQS : PASS
7105 23:25:49.979996 RX DATLAT : PASS
7106 23:25:49.983765 RX DQ/DQS(Engine): PASS
7107 23:25:49.984315 TX OE : NO K
7108 23:25:49.984679 All Pass.
7109 23:25:49.986570
7110 23:25:49.987036 DramC Write-DBI off
7111 23:25:49.990326 PER_BANK_REFRESH: Hybrid Mode
7112 23:25:49.990781 TX_TRACKING: ON
7113 23:25:50.000254 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7114 23:25:50.003988 [FAST_K] Save calibration result to emmc
7115 23:25:50.006747 dramc_set_vcore_voltage set vcore to 725000
7116 23:25:50.010590 Read voltage for 1600, 0
7117 23:25:50.011141 Vio18 = 0
7118 23:25:50.013338 Vcore = 725000
7119 23:25:50.013920 Vdram = 0
7120 23:25:50.014335 Vddq = 0
7121 23:25:50.014670 Vmddr = 0
7122 23:25:50.020704 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7123 23:25:50.027037 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7124 23:25:50.027616 MEM_TYPE=3, freq_sel=13
7125 23:25:50.030646 sv_algorithm_assistance_LP4_3733
7126 23:25:50.033665 ============ PULL DRAM RESETB DOWN ============
7127 23:25:50.040339 ========== PULL DRAM RESETB DOWN end =========
7128 23:25:50.043823 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7129 23:25:50.047805 ===================================
7130 23:25:50.050017 LPDDR4 DRAM CONFIGURATION
7131 23:25:50.053639 ===================================
7132 23:25:50.054097 EX_ROW_EN[0] = 0x0
7133 23:25:50.056794 EX_ROW_EN[1] = 0x0
7134 23:25:50.057248 LP4Y_EN = 0x0
7135 23:25:50.060267 WORK_FSP = 0x1
7136 23:25:50.060827 WL = 0x5
7137 23:25:50.063410 RL = 0x5
7138 23:25:50.064011 BL = 0x2
7139 23:25:50.066373 RPST = 0x0
7140 23:25:50.070594 RD_PRE = 0x0
7141 23:25:50.071143 WR_PRE = 0x1
7142 23:25:50.073365 WR_PST = 0x1
7143 23:25:50.074025 DBI_WR = 0x0
7144 23:25:50.076568 DBI_RD = 0x0
7145 23:25:50.077040 OTF = 0x1
7146 23:25:50.080077 ===================================
7147 23:25:50.083969 ===================================
7148 23:25:50.084426 ANA top config
7149 23:25:50.086732 ===================================
7150 23:25:50.089854 DLL_ASYNC_EN = 0
7151 23:25:50.093346 ALL_SLAVE_EN = 0
7152 23:25:50.096809 NEW_RANK_MODE = 1
7153 23:25:50.100127 DLL_IDLE_MODE = 1
7154 23:25:50.100845 LP45_APHY_COMB_EN = 1
7155 23:25:50.103294 TX_ODT_DIS = 0
7156 23:25:50.106721 NEW_8X_MODE = 1
7157 23:25:50.110074 ===================================
7158 23:25:50.113462 ===================================
7159 23:25:50.116999 data_rate = 3200
7160 23:25:50.119900 CKR = 1
7161 23:25:50.120360 DQ_P2S_RATIO = 8
7162 23:25:50.123086 ===================================
7163 23:25:50.126341 CA_P2S_RATIO = 8
7164 23:25:50.130326 DQ_CA_OPEN = 0
7165 23:25:50.133237 DQ_SEMI_OPEN = 0
7166 23:25:50.136279 CA_SEMI_OPEN = 0
7167 23:25:50.139471 CA_FULL_RATE = 0
7168 23:25:50.140121 DQ_CKDIV4_EN = 0
7169 23:25:50.142833 CA_CKDIV4_EN = 0
7170 23:25:50.146208 CA_PREDIV_EN = 0
7171 23:25:50.149524 PH8_DLY = 12
7172 23:25:50.153454 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7173 23:25:50.156550 DQ_AAMCK_DIV = 4
7174 23:25:50.157084 CA_AAMCK_DIV = 4
7175 23:25:50.159813 CA_ADMCK_DIV = 4
7176 23:25:50.162984 DQ_TRACK_CA_EN = 0
7177 23:25:50.166511 CA_PICK = 1600
7178 23:25:50.169863 CA_MCKIO = 1600
7179 23:25:50.173264 MCKIO_SEMI = 0
7180 23:25:50.176711 PLL_FREQ = 3068
7181 23:25:50.177221 DQ_UI_PI_RATIO = 32
7182 23:25:50.179810 CA_UI_PI_RATIO = 0
7183 23:25:50.182938 ===================================
7184 23:25:50.186114 ===================================
7185 23:25:50.189960 memory_type:LPDDR4
7186 23:25:50.193023 GP_NUM : 10
7187 23:25:50.193544 SRAM_EN : 1
7188 23:25:50.196735 MD32_EN : 0
7189 23:25:50.199743 ===================================
7190 23:25:50.203010 [ANA_INIT] >>>>>>>>>>>>>>
7191 23:25:50.203574 <<<<<< [CONFIGURE PHASE]: ANA_TX
7192 23:25:50.206478 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7193 23:25:50.209700 ===================================
7194 23:25:50.212927 data_rate = 3200,PCW = 0X7600
7195 23:25:50.216573 ===================================
7196 23:25:50.219986 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7197 23:25:50.226546 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7198 23:25:50.233029 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7199 23:25:50.236398 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7200 23:25:50.239654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7201 23:25:50.243452 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7202 23:25:50.246529 [ANA_INIT] flow start
7203 23:25:50.247100 [ANA_INIT] PLL >>>>>>>>
7204 23:25:50.249761 [ANA_INIT] PLL <<<<<<<<
7205 23:25:50.252811 [ANA_INIT] MIDPI >>>>>>>>
7206 23:25:50.253270 [ANA_INIT] MIDPI <<<<<<<<
7207 23:25:50.256820 [ANA_INIT] DLL >>>>>>>>
7208 23:25:50.259889 [ANA_INIT] DLL <<<<<<<<
7209 23:25:50.260557 [ANA_INIT] flow end
7210 23:25:50.266616 ============ LP4 DIFF to SE enter ============
7211 23:25:50.269815 ============ LP4 DIFF to SE exit ============
7212 23:25:50.273250 [ANA_INIT] <<<<<<<<<<<<<
7213 23:25:50.276184 [Flow] Enable top DCM control >>>>>
7214 23:25:50.276737 [Flow] Enable top DCM control <<<<<
7215 23:25:50.279442 Enable DLL master slave shuffle
7216 23:25:50.286358 ==============================================================
7217 23:25:50.289487 Gating Mode config
7218 23:25:50.292684 ==============================================================
7219 23:25:50.296255 Config description:
7220 23:25:50.306005 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7221 23:25:50.313323 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7222 23:25:50.315854 SELPH_MODE 0: By rank 1: By Phase
7223 23:25:50.322677 ==============================================================
7224 23:25:50.326063 GAT_TRACK_EN = 1
7225 23:25:50.329334 RX_GATING_MODE = 2
7226 23:25:50.332610 RX_GATING_TRACK_MODE = 2
7227 23:25:50.335700 SELPH_MODE = 1
7228 23:25:50.336252 PICG_EARLY_EN = 1
7229 23:25:50.339604 VALID_LAT_VALUE = 1
7230 23:25:50.345734 ==============================================================
7231 23:25:50.349083 Enter into Gating configuration >>>>
7232 23:25:50.352193 Exit from Gating configuration <<<<
7233 23:25:50.355848 Enter into DVFS_PRE_config >>>>>
7234 23:25:50.365833 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7235 23:25:50.369028 Exit from DVFS_PRE_config <<<<<
7236 23:25:50.372008 Enter into PICG configuration >>>>
7237 23:25:50.375668 Exit from PICG configuration <<<<
7238 23:25:50.378825 [RX_INPUT] configuration >>>>>
7239 23:25:50.382267 [RX_INPUT] configuration <<<<<
7240 23:25:50.385770 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7241 23:25:50.392203 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7242 23:25:50.398842 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7243 23:25:50.405663 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7244 23:25:50.411923 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7245 23:25:50.418532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7246 23:25:50.422327 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7247 23:25:50.425396 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7248 23:25:50.428252 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7249 23:25:50.432107 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7250 23:25:50.438290 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7251 23:25:50.442002 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7252 23:25:50.445425 ===================================
7253 23:25:50.448867 LPDDR4 DRAM CONFIGURATION
7254 23:25:50.451648 ===================================
7255 23:25:50.452114 EX_ROW_EN[0] = 0x0
7256 23:25:50.454805 EX_ROW_EN[1] = 0x0
7257 23:25:50.455266 LP4Y_EN = 0x0
7258 23:25:50.458330 WORK_FSP = 0x1
7259 23:25:50.458887 WL = 0x5
7260 23:25:50.461368 RL = 0x5
7261 23:25:50.465417 BL = 0x2
7262 23:25:50.466037 RPST = 0x0
7263 23:25:50.468080 RD_PRE = 0x0
7264 23:25:50.468622 WR_PRE = 0x1
7265 23:25:50.471820 WR_PST = 0x1
7266 23:25:50.472374 DBI_WR = 0x0
7267 23:25:50.474782 DBI_RD = 0x0
7268 23:25:50.475261 OTF = 0x1
7269 23:25:50.478443 ===================================
7270 23:25:50.481352 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7271 23:25:50.488530 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7272 23:25:50.491337 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7273 23:25:50.494993 ===================================
7274 23:25:50.498280 LPDDR4 DRAM CONFIGURATION
7275 23:25:50.501820 ===================================
7276 23:25:50.502373 EX_ROW_EN[0] = 0x10
7277 23:25:50.505136 EX_ROW_EN[1] = 0x0
7278 23:25:50.505731 LP4Y_EN = 0x0
7279 23:25:50.508272 WORK_FSP = 0x1
7280 23:25:50.508825 WL = 0x5
7281 23:25:50.511448 RL = 0x5
7282 23:25:50.512004 BL = 0x2
7283 23:25:50.514588 RPST = 0x0
7284 23:25:50.515045 RD_PRE = 0x0
7285 23:25:50.518359 WR_PRE = 0x1
7286 23:25:50.521605 WR_PST = 0x1
7287 23:25:50.522163 DBI_WR = 0x0
7288 23:25:50.524694 DBI_RD = 0x0
7289 23:25:50.525244 OTF = 0x1
7290 23:25:50.527875 ===================================
7291 23:25:50.535091 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7292 23:25:50.535643 ==
7293 23:25:50.538305 Dram Type= 6, Freq= 0, CH_0, rank 0
7294 23:25:50.541662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 23:25:50.542240 ==
7296 23:25:50.544904 [Duty_Offset_Calibration]
7297 23:25:50.545550 B0:2 B1:1 CA:1
7298 23:25:50.547783
7299 23:25:50.551487 [DutyScan_Calibration_Flow] k_type=0
7300 23:25:50.559331
7301 23:25:50.559884 ==CLK 0==
7302 23:25:50.562341 Final CLK duty delay cell = 0
7303 23:25:50.566410 [0] MAX Duty = 5156%(X100), DQS PI = 22
7304 23:25:50.569388 [0] MIN Duty = 4907%(X100), DQS PI = 0
7305 23:25:50.569990 [0] AVG Duty = 5031%(X100)
7306 23:25:50.572806
7307 23:25:50.576144 CH0 CLK Duty spec in!! Max-Min= 249%
7308 23:25:50.578973 [DutyScan_Calibration_Flow] ====Done====
7309 23:25:50.579433
7310 23:25:50.582162 [DutyScan_Calibration_Flow] k_type=1
7311 23:25:50.598218
7312 23:25:50.598766 ==DQS 0 ==
7313 23:25:50.602002 Final DQS duty delay cell = -4
7314 23:25:50.605073 [-4] MAX Duty = 5156%(X100), DQS PI = 24
7315 23:25:50.608539 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7316 23:25:50.612418 [-4] AVG Duty = 4906%(X100)
7317 23:25:50.613015
7318 23:25:50.613503 ==DQS 1 ==
7319 23:25:50.614979 Final DQS duty delay cell = 0
7320 23:25:50.618505 [0] MAX Duty = 5218%(X100), DQS PI = 22
7321 23:25:50.622305 [0] MIN Duty = 5062%(X100), DQS PI = 32
7322 23:25:50.625264 [0] AVG Duty = 5140%(X100)
7323 23:25:50.625853
7324 23:25:50.628296 CH0 DQS 0 Duty spec in!! Max-Min= 499%
7325 23:25:50.628862
7326 23:25:50.632056 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7327 23:25:50.635037 [DutyScan_Calibration_Flow] ====Done====
7328 23:25:50.635588
7329 23:25:50.638416 [DutyScan_Calibration_Flow] k_type=3
7330 23:25:50.655282
7331 23:25:50.655823 ==DQM 0 ==
7332 23:25:50.658578 Final DQM duty delay cell = 0
7333 23:25:50.661765 [0] MAX Duty = 5218%(X100), DQS PI = 34
7334 23:25:50.665052 [0] MIN Duty = 4907%(X100), DQS PI = 56
7335 23:25:50.668345 [0] AVG Duty = 5062%(X100)
7336 23:25:50.668900
7337 23:25:50.669281 ==DQM 1 ==
7338 23:25:50.671933 Final DQM duty delay cell = -4
7339 23:25:50.674623 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7340 23:25:50.678204 [-4] MIN Duty = 4844%(X100), DQS PI = 12
7341 23:25:50.682049 [-4] AVG Duty = 4922%(X100)
7342 23:25:50.682617
7343 23:25:50.685611 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7344 23:25:50.686216
7345 23:25:50.688063 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7346 23:25:50.691928 [DutyScan_Calibration_Flow] ====Done====
7347 23:25:50.692509
7348 23:25:50.695465 [DutyScan_Calibration_Flow] k_type=2
7349 23:25:50.712925
7350 23:25:50.713490 ==DQ 0 ==
7351 23:25:50.716130 Final DQ duty delay cell = 0
7352 23:25:50.719266 [0] MAX Duty = 5062%(X100), DQS PI = 24
7353 23:25:50.722873 [0] MIN Duty = 4907%(X100), DQS PI = 0
7354 23:25:50.723348 [0] AVG Duty = 4984%(X100)
7355 23:25:50.723826
7356 23:25:50.725983 ==DQ 1 ==
7357 23:25:50.729110 Final DQ duty delay cell = 0
7358 23:25:50.732320 [0] MAX Duty = 5093%(X100), DQS PI = 6
7359 23:25:50.736030 [0] MIN Duty = 4907%(X100), DQS PI = 34
7360 23:25:50.736630 [0] AVG Duty = 5000%(X100)
7361 23:25:50.737136
7362 23:25:50.739584 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7363 23:25:50.740130
7364 23:25:50.745548 CH0 DQ 1 Duty spec in!! Max-Min= 186%
7365 23:25:50.748912 [DutyScan_Calibration_Flow] ====Done====
7366 23:25:50.749456 ==
7367 23:25:50.752260 Dram Type= 6, Freq= 0, CH_1, rank 0
7368 23:25:50.755346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7369 23:25:50.755728 ==
7370 23:25:50.758905 [Duty_Offset_Calibration]
7371 23:25:50.759139 B0:1 B1:0 CA:0
7372 23:25:50.759319
7373 23:25:50.762012 [DutyScan_Calibration_Flow] k_type=0
7374 23:25:50.771956
7375 23:25:50.772224 ==CLK 0==
7376 23:25:50.774840 Final CLK duty delay cell = -4
7377 23:25:50.778443 [-4] MAX Duty = 4969%(X100), DQS PI = 20
7378 23:25:50.781702 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7379 23:25:50.784803 [-4] AVG Duty = 4906%(X100)
7380 23:25:50.785256
7381 23:25:50.788680 CH1 CLK Duty spec in!! Max-Min= 125%
7382 23:25:50.792051 [DutyScan_Calibration_Flow] ====Done====
7383 23:25:50.792503
7384 23:25:50.795201 [DutyScan_Calibration_Flow] k_type=1
7385 23:25:50.812235
7386 23:25:50.812781 ==DQS 0 ==
7387 23:25:50.815731 Final DQS duty delay cell = 0
7388 23:25:50.818338 [0] MAX Duty = 5094%(X100), DQS PI = 14
7389 23:25:50.822166 [0] MIN Duty = 4844%(X100), DQS PI = 48
7390 23:25:50.825121 [0] AVG Duty = 4969%(X100)
7391 23:25:50.825705
7392 23:25:50.826065 ==DQS 1 ==
7393 23:25:50.828419 Final DQS duty delay cell = 0
7394 23:25:50.832493 [0] MAX Duty = 5249%(X100), DQS PI = 16
7395 23:25:50.835816 [0] MIN Duty = 4969%(X100), DQS PI = 6
7396 23:25:50.838283 [0] AVG Duty = 5109%(X100)
7397 23:25:50.838774
7398 23:25:50.841827 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7399 23:25:50.842282
7400 23:25:50.845242 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7401 23:25:50.848758 [DutyScan_Calibration_Flow] ====Done====
7402 23:25:50.849313
7403 23:25:50.851816 [DutyScan_Calibration_Flow] k_type=3
7404 23:25:50.869055
7405 23:25:50.869679 ==DQM 0 ==
7406 23:25:50.872442 Final DQM duty delay cell = 0
7407 23:25:50.875332 [0] MAX Duty = 5218%(X100), DQS PI = 18
7408 23:25:50.878864 [0] MIN Duty = 4969%(X100), DQS PI = 48
7409 23:25:50.882160 [0] AVG Duty = 5093%(X100)
7410 23:25:50.882723
7411 23:25:50.883087 ==DQM 1 ==
7412 23:25:50.885626 Final DQM duty delay cell = 0
7413 23:25:50.888794 [0] MAX Duty = 5093%(X100), DQS PI = 40
7414 23:25:50.892157 [0] MIN Duty = 4907%(X100), DQS PI = 34
7415 23:25:50.895684 [0] AVG Duty = 5000%(X100)
7416 23:25:50.896239
7417 23:25:50.898712 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7418 23:25:50.899266
7419 23:25:50.901752 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7420 23:25:50.905391 [DutyScan_Calibration_Flow] ====Done====
7421 23:25:50.905999
7422 23:25:50.908621 [DutyScan_Calibration_Flow] k_type=2
7423 23:25:50.925140
7424 23:25:50.925745 ==DQ 0 ==
7425 23:25:50.928730 Final DQ duty delay cell = -4
7426 23:25:50.931387 [-4] MAX Duty = 5031%(X100), DQS PI = 10
7427 23:25:50.935634 [-4] MIN Duty = 4875%(X100), DQS PI = 44
7428 23:25:50.938156 [-4] AVG Duty = 4953%(X100)
7429 23:25:50.938610
7430 23:25:50.938966 ==DQ 1 ==
7431 23:25:50.941613 Final DQ duty delay cell = 0
7432 23:25:50.945246 [0] MAX Duty = 5156%(X100), DQS PI = 18
7433 23:25:50.948423 [0] MIN Duty = 4938%(X100), DQS PI = 8
7434 23:25:50.951668 [0] AVG Duty = 5047%(X100)
7435 23:25:50.952129
7436 23:25:50.954638 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7437 23:25:50.955111
7438 23:25:50.958177 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7439 23:25:50.961679 [DutyScan_Calibration_Flow] ====Done====
7440 23:25:50.964969 nWR fixed to 30
7441 23:25:50.965470 [ModeRegInit_LP4] CH0 RK0
7442 23:25:50.968163 [ModeRegInit_LP4] CH0 RK1
7443 23:25:50.971227 [ModeRegInit_LP4] CH1 RK0
7444 23:25:50.974611 [ModeRegInit_LP4] CH1 RK1
7445 23:25:50.975066 match AC timing 5
7446 23:25:50.981436 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7447 23:25:50.984581 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7448 23:25:50.987931 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7449 23:25:50.995051 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7450 23:25:50.998661 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7451 23:25:50.999217 [MiockJmeterHQA]
7452 23:25:50.999574
7453 23:25:51.001479 [DramcMiockJmeter] u1RxGatingPI = 0
7454 23:25:51.005316 0 : 4253, 4027
7455 23:25:51.005935 4 : 4252, 4027
7456 23:25:51.008325 8 : 4252, 4027
7457 23:25:51.008787 12 : 4255, 4029
7458 23:25:51.009151 16 : 4257, 4029
7459 23:25:51.011359 20 : 4363, 4137
7460 23:25:51.011824 24 : 4363, 4138
7461 23:25:51.014400 28 : 4253, 4026
7462 23:25:51.014860 32 : 4252, 4027
7463 23:25:51.017756 36 : 4252, 4027
7464 23:25:51.018222 40 : 4253, 4026
7465 23:25:51.021453 44 : 4254, 4029
7466 23:25:51.022111 48 : 4363, 4137
7467 23:25:51.022482 52 : 4253, 4027
7468 23:25:51.024468 56 : 4253, 4026
7469 23:25:51.025027 60 : 4252, 4027
7470 23:25:51.028298 64 : 4252, 4029
7471 23:25:51.028858 68 : 4250, 4026
7472 23:25:51.031006 72 : 4363, 4140
7473 23:25:51.031533 76 : 4360, 4137
7474 23:25:51.034563 80 : 4250, 4026
7475 23:25:51.035126 84 : 4250, 4027
7476 23:25:51.035490 88 : 4249, 30
7477 23:25:51.037657 92 : 4252, 0
7478 23:25:51.038120 96 : 4252, 0
7479 23:25:51.038486 100 : 4252, 0
7480 23:25:51.041564 104 : 4250, 0
7481 23:25:51.042072 108 : 4252, 0
7482 23:25:51.044774 112 : 4252, 0
7483 23:25:51.045335 116 : 4250, 0
7484 23:25:51.045772 120 : 4252, 0
7485 23:25:51.048062 124 : 4363, 0
7486 23:25:51.048617 128 : 4253, 0
7487 23:25:51.051038 132 : 4360, 0
7488 23:25:51.051623 136 : 4255, 0
7489 23:25:51.052024 140 : 4252, 0
7490 23:25:51.054472 144 : 4250, 0
7491 23:25:51.054936 148 : 4253, 0
7492 23:25:51.057723 152 : 4252, 0
7493 23:25:51.058491 156 : 4250, 0
7494 23:25:51.058881 160 : 4252, 0
7495 23:25:51.060845 164 : 4252, 0
7496 23:25:51.061414 168 : 4250, 0
7497 23:25:51.061859 172 : 4252, 0
7498 23:25:51.064215 176 : 4363, 0
7499 23:25:51.064678 180 : 4361, 0
7500 23:25:51.068126 184 : 4363, 0
7501 23:25:51.068684 188 : 4250, 0
7502 23:25:51.069053 192 : 4250, 0
7503 23:25:51.071385 196 : 4249, 0
7504 23:25:51.072007 200 : 4249, 0
7505 23:25:51.074234 204 : 4250, 1044
7506 23:25:51.074699 208 : 4250, 4002
7507 23:25:51.077659 212 : 4361, 4138
7508 23:25:51.078180 216 : 4249, 4027
7509 23:25:51.080487 220 : 4250, 4026
7510 23:25:51.080948 224 : 4252, 4027
7511 23:25:51.081313 228 : 4252, 4029
7512 23:25:51.084358 232 : 4250, 4027
7513 23:25:51.084839 236 : 4250, 4026
7514 23:25:51.087971 240 : 4361, 4137
7515 23:25:51.088455 244 : 4250, 4026
7516 23:25:51.090671 248 : 4250, 4027
7517 23:25:51.091155 252 : 4360, 4137
7518 23:25:51.094198 256 : 4250, 4027
7519 23:25:51.094765 260 : 4250, 4027
7520 23:25:51.097724 264 : 4363, 4140
7521 23:25:51.098290 268 : 4250, 4027
7522 23:25:51.100802 272 : 4250, 4026
7523 23:25:51.101380 276 : 4250, 4027
7524 23:25:51.104319 280 : 4252, 4029
7525 23:25:51.104916 284 : 4250, 4027
7526 23:25:51.105407 288 : 4250, 4026
7527 23:25:51.107303 292 : 4361, 4137
7528 23:25:51.107781 296 : 4250, 4027
7529 23:25:51.110879 300 : 4250, 4027
7530 23:25:51.111456 304 : 4360, 4137
7531 23:25:51.114242 308 : 4250, 3999
7532 23:25:51.114813 312 : 4250, 1911
7533 23:25:51.115303
7534 23:25:51.117562 MIOCK jitter meter ch=0
7535 23:25:51.118223
7536 23:25:51.120905 1T = (312-88) = 224 dly cells
7537 23:25:51.127545 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7538 23:25:51.128100 ==
7539 23:25:51.130487 Dram Type= 6, Freq= 0, CH_0, rank 0
7540 23:25:51.133640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7541 23:25:51.134105 ==
7542 23:25:51.140452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7543 23:25:51.143873 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7544 23:25:51.147349 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7545 23:25:51.153793 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7546 23:25:51.162678 [CA 0] Center 42 (12~73) winsize 62
7547 23:25:51.166693 [CA 1] Center 42 (12~73) winsize 62
7548 23:25:51.168772 [CA 2] Center 38 (8~68) winsize 61
7549 23:25:51.171994 [CA 3] Center 37 (8~67) winsize 60
7550 23:25:51.175236 [CA 4] Center 36 (6~66) winsize 61
7551 23:25:51.178600 [CA 5] Center 35 (6~64) winsize 59
7552 23:25:51.178680
7553 23:25:51.181730 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7554 23:25:51.181803
7555 23:25:51.185452 [CATrainingPosCal] consider 1 rank data
7556 23:25:51.188565 u2DelayCellTimex100 = 290/100 ps
7557 23:25:51.191926 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7558 23:25:51.198840 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7559 23:25:51.202064 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7560 23:25:51.205121 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7561 23:25:51.208248 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7562 23:25:51.212074 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7563 23:25:51.212288
7564 23:25:51.215201 CA PerBit enable=1, Macro0, CA PI delay=35
7565 23:25:51.215435
7566 23:25:51.218443 [CBTSetCACLKResult] CA Dly = 35
7567 23:25:51.221647 CS Dly: 9 (0~40)
7568 23:25:51.225342 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7569 23:25:51.228425 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7570 23:25:51.228851 ==
7571 23:25:51.232084 Dram Type= 6, Freq= 0, CH_0, rank 1
7572 23:25:51.235104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 23:25:51.238361 ==
7574 23:25:51.241983 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 23:25:51.245248 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 23:25:51.252125 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 23:25:51.258616 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 23:25:51.265866 [CA 0] Center 42 (12~73) winsize 62
7579 23:25:51.269439 [CA 1] Center 42 (12~73) winsize 62
7580 23:25:51.272809 [CA 2] Center 38 (8~68) winsize 61
7581 23:25:51.276525 [CA 3] Center 38 (8~68) winsize 61
7582 23:25:51.279526 [CA 4] Center 35 (6~65) winsize 60
7583 23:25:51.282374 [CA 5] Center 35 (5~65) winsize 61
7584 23:25:51.282930
7585 23:25:51.285830 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7586 23:25:51.286380
7587 23:25:51.289447 [CATrainingPosCal] consider 2 rank data
7588 23:25:51.292775 u2DelayCellTimex100 = 290/100 ps
7589 23:25:51.295780 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7590 23:25:51.302605 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7591 23:25:51.306013 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7592 23:25:51.309303 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7593 23:25:51.312357 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7594 23:25:51.315568 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7595 23:25:51.316127
7596 23:25:51.319262 CA PerBit enable=1, Macro0, CA PI delay=35
7597 23:25:51.319819
7598 23:25:51.322072 [CBTSetCACLKResult] CA Dly = 35
7599 23:25:51.325719 CS Dly: 9 (0~41)
7600 23:25:51.328899 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 23:25:51.331822 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 23:25:51.332279
7603 23:25:51.335512 ----->DramcWriteLeveling(PI) begin...
7604 23:25:51.336072 ==
7605 23:25:51.338554 Dram Type= 6, Freq= 0, CH_0, rank 0
7606 23:25:51.345163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7607 23:25:51.345814 ==
7608 23:25:51.348664 Write leveling (Byte 0): 36 => 36
7609 23:25:51.349218 Write leveling (Byte 1): 27 => 27
7610 23:25:51.351946 DramcWriteLeveling(PI) end<-----
7611 23:25:51.352428
7612 23:25:51.352787 ==
7613 23:25:51.355484 Dram Type= 6, Freq= 0, CH_0, rank 0
7614 23:25:51.361928 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7615 23:25:51.362465 ==
7616 23:25:51.365095 [Gating] SW mode calibration
7617 23:25:51.371888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7618 23:25:51.375300 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7619 23:25:51.381797 1 4 0 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
7620 23:25:51.385488 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7621 23:25:51.388253 1 4 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7622 23:25:51.395562 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7623 23:25:51.398363 1 4 16 | B1->B0 | 2323 3938 | 0 1 | (0 0) (1 1)
7624 23:25:51.401794 1 4 20 | B1->B0 | 3333 3636 | 1 1 | (1 1) (0 0)
7625 23:25:51.408768 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7626 23:25:51.411975 1 4 28 | B1->B0 | 3434 3939 | 1 1 | (1 1) (1 1)
7627 23:25:51.414998 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7628 23:25:51.422018 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7629 23:25:51.425070 1 5 8 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7630 23:25:51.428655 1 5 12 | B1->B0 | 3434 2928 | 1 1 | (1 1) (1 0)
7631 23:25:51.431610 1 5 16 | B1->B0 | 3232 2928 | 1 1 | (1 0) (0 0)
7632 23:25:51.438331 1 5 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7633 23:25:51.441851 1 5 24 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
7634 23:25:51.444734 1 5 28 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
7635 23:25:51.452401 1 6 0 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
7636 23:25:51.455199 1 6 4 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7637 23:25:51.458414 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
7638 23:25:51.465089 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7639 23:25:51.468487 1 6 16 | B1->B0 | 2525 4645 | 0 1 | (0 0) (0 0)
7640 23:25:51.471451 1 6 20 | B1->B0 | 4545 4646 | 0 1 | (0 0) (1 1)
7641 23:25:51.478291 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 23:25:51.481399 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7643 23:25:51.484676 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7644 23:25:51.491441 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7645 23:25:51.494666 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7646 23:25:51.498751 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7647 23:25:51.505143 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7648 23:25:51.508066 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7649 23:25:51.511970 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 23:25:51.518275 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 23:25:51.521994 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 23:25:51.524815 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 23:25:51.531403 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 23:25:51.534905 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 23:25:51.538314 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:25:51.545034 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 23:25:51.548669 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 23:25:51.551683 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 23:25:51.558350 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 23:25:51.561432 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 23:25:51.564407 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7662 23:25:51.571000 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7663 23:25:51.574926 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7664 23:25:51.577969 Total UI for P1: 0, mck2ui 16
7665 23:25:51.581317 best dqsien dly found for B0: ( 1, 9, 10)
7666 23:25:51.584231 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7667 23:25:51.588156 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7668 23:25:51.590743 Total UI for P1: 0, mck2ui 16
7669 23:25:51.594729 best dqsien dly found for B1: ( 1, 9, 18)
7670 23:25:51.597989 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7671 23:25:51.604255 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7672 23:25:51.604811
7673 23:25:51.608038 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7674 23:25:51.611060 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7675 23:25:51.614413 [Gating] SW calibration Done
7676 23:25:51.614965 ==
7677 23:25:51.617706 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 23:25:51.620979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 23:25:51.621538 ==
7680 23:25:51.624480 RX Vref Scan: 0
7681 23:25:51.625025
7682 23:25:51.625384 RX Vref 0 -> 0, step: 1
7683 23:25:51.625787
7684 23:25:51.627318 RX Delay 0 -> 252, step: 8
7685 23:25:51.631352 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7686 23:25:51.634061 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7687 23:25:51.640716 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7688 23:25:51.644492 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7689 23:25:51.648092 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7690 23:25:51.650890 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7691 23:25:51.654519 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7692 23:25:51.660786 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7693 23:25:51.664299 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7694 23:25:51.667322 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7695 23:25:51.670385 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7696 23:25:51.674022 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7697 23:25:51.680467 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7698 23:25:51.684389 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7699 23:25:51.687467 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7700 23:25:51.690522 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7701 23:25:51.691015 ==
7702 23:25:51.693692 Dram Type= 6, Freq= 0, CH_0, rank 0
7703 23:25:51.700930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7704 23:25:51.701478 ==
7705 23:25:51.701947 DQS Delay:
7706 23:25:51.702287 DQS0 = 0, DQS1 = 0
7707 23:25:51.703796 DQM Delay:
7708 23:25:51.704245 DQM0 = 137, DQM1 = 130
7709 23:25:51.707699 DQ Delay:
7710 23:25:51.710481 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7711 23:25:51.714085 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7712 23:25:51.717091 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7713 23:25:51.720353 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7714 23:25:51.720808
7715 23:25:51.721165
7716 23:25:51.721490 ==
7717 23:25:51.724120 Dram Type= 6, Freq= 0, CH_0, rank 0
7718 23:25:51.727428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7719 23:25:51.730119 ==
7720 23:25:51.730582
7721 23:25:51.730936
7722 23:25:51.731264 TX Vref Scan disable
7723 23:25:51.733882 == TX Byte 0 ==
7724 23:25:51.737428 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7725 23:25:51.740539 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7726 23:25:51.743697 == TX Byte 1 ==
7727 23:25:51.746830 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7728 23:25:51.750207 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7729 23:25:51.753516 ==
7730 23:25:51.754167 Dram Type= 6, Freq= 0, CH_0, rank 0
7731 23:25:51.760102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7732 23:25:51.760688 ==
7733 23:25:51.773138
7734 23:25:51.776569 TX Vref early break, caculate TX vref
7735 23:25:51.779899 TX Vref=16, minBit 1, minWin=22, winSum=379
7736 23:25:51.783217 TX Vref=18, minBit 0, minWin=22, winSum=387
7737 23:25:51.786249 TX Vref=20, minBit 1, minWin=23, winSum=393
7738 23:25:51.790045 TX Vref=22, minBit 0, minWin=24, winSum=408
7739 23:25:51.792772 TX Vref=24, minBit 0, minWin=25, winSum=415
7740 23:25:51.800012 TX Vref=26, minBit 0, minWin=25, winSum=426
7741 23:25:51.802995 TX Vref=28, minBit 2, minWin=24, winSum=423
7742 23:25:51.806494 TX Vref=30, minBit 1, minWin=25, winSum=413
7743 23:25:51.810068 TX Vref=32, minBit 6, minWin=23, winSum=405
7744 23:25:51.812823 TX Vref=34, minBit 1, minWin=23, winSum=393
7745 23:25:51.819528 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
7746 23:25:51.819987
7747 23:25:51.822893 Final TX Range 0 Vref 26
7748 23:25:51.823448
7749 23:25:51.823808 ==
7750 23:25:51.826558 Dram Type= 6, Freq= 0, CH_0, rank 0
7751 23:25:51.829891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7752 23:25:51.830450 ==
7753 23:25:51.830809
7754 23:25:51.831138
7755 23:25:51.833043 TX Vref Scan disable
7756 23:25:51.839699 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7757 23:25:51.840256 == TX Byte 0 ==
7758 23:25:51.842664 u2DelayCellOfst[0]=10 cells (3 PI)
7759 23:25:51.846594 u2DelayCellOfst[1]=13 cells (4 PI)
7760 23:25:51.849792 u2DelayCellOfst[2]=10 cells (3 PI)
7761 23:25:51.852959 u2DelayCellOfst[3]=10 cells (3 PI)
7762 23:25:51.856219 u2DelayCellOfst[4]=6 cells (2 PI)
7763 23:25:51.860044 u2DelayCellOfst[5]=0 cells (0 PI)
7764 23:25:51.862598 u2DelayCellOfst[6]=16 cells (5 PI)
7765 23:25:51.866140 u2DelayCellOfst[7]=16 cells (5 PI)
7766 23:25:51.869071 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7767 23:25:51.873052 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7768 23:25:51.875925 == TX Byte 1 ==
7769 23:25:51.876472 u2DelayCellOfst[8]=0 cells (0 PI)
7770 23:25:51.879125 u2DelayCellOfst[9]=3 cells (1 PI)
7771 23:25:51.882919 u2DelayCellOfst[10]=10 cells (3 PI)
7772 23:25:51.885898 u2DelayCellOfst[11]=6 cells (2 PI)
7773 23:25:51.889175 u2DelayCellOfst[12]=13 cells (4 PI)
7774 23:25:51.892717 u2DelayCellOfst[13]=13 cells (4 PI)
7775 23:25:51.896221 u2DelayCellOfst[14]=13 cells (4 PI)
7776 23:25:51.899782 u2DelayCellOfst[15]=10 cells (3 PI)
7777 23:25:51.902872 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7778 23:25:51.909287 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
7779 23:25:51.909915 DramC Write-DBI on
7780 23:25:51.910283 ==
7781 23:25:51.912670 Dram Type= 6, Freq= 0, CH_0, rank 0
7782 23:25:51.916053 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7783 23:25:51.919139 ==
7784 23:25:51.919641
7785 23:25:51.920002
7786 23:25:51.920335 TX Vref Scan disable
7787 23:25:51.923464 == TX Byte 0 ==
7788 23:25:51.925987 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7789 23:25:51.929638 == TX Byte 1 ==
7790 23:25:51.932979 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7791 23:25:51.936580 DramC Write-DBI off
7792 23:25:51.937135
7793 23:25:51.937496 [DATLAT]
7794 23:25:51.937909 Freq=1600, CH0 RK0
7795 23:25:51.938241
7796 23:25:51.939240 DATLAT Default: 0xf
7797 23:25:51.939695 0, 0xFFFF, sum = 0
7798 23:25:51.943038 1, 0xFFFF, sum = 0
7799 23:25:51.943598 2, 0xFFFF, sum = 0
7800 23:25:51.946301 3, 0xFFFF, sum = 0
7801 23:25:51.949545 4, 0xFFFF, sum = 0
7802 23:25:51.950162 5, 0xFFFF, sum = 0
7803 23:25:51.952549 6, 0xFFFF, sum = 0
7804 23:25:51.953110 7, 0xFFFF, sum = 0
7805 23:25:51.955792 8, 0xFFFF, sum = 0
7806 23:25:51.956238 9, 0xFFFF, sum = 0
7807 23:25:51.959630 10, 0xFFFF, sum = 0
7808 23:25:51.960193 11, 0xFFFF, sum = 0
7809 23:25:51.962682 12, 0xFFFF, sum = 0
7810 23:25:51.963145 13, 0xFFFF, sum = 0
7811 23:25:51.966408 14, 0x0, sum = 1
7812 23:25:51.966968 15, 0x0, sum = 2
7813 23:25:51.968998 16, 0x0, sum = 3
7814 23:25:51.969554 17, 0x0, sum = 4
7815 23:25:51.972450 best_step = 15
7816 23:25:51.972904
7817 23:25:51.973283 ==
7818 23:25:51.975797 Dram Type= 6, Freq= 0, CH_0, rank 0
7819 23:25:51.979687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7820 23:25:51.980150 ==
7821 23:25:51.982566 RX Vref Scan: 1
7822 23:25:51.983021
7823 23:25:51.983459 Set Vref Range= 24 -> 127
7824 23:25:51.983808
7825 23:25:51.985851 RX Vref 24 -> 127, step: 1
7826 23:25:51.986310
7827 23:25:51.988983 RX Delay 19 -> 252, step: 4
7828 23:25:51.989506
7829 23:25:51.992347 Set Vref, RX VrefLevel [Byte0]: 24
7830 23:25:51.996152 [Byte1]: 24
7831 23:25:51.996668
7832 23:25:51.999277 Set Vref, RX VrefLevel [Byte0]: 25
7833 23:25:52.002544 [Byte1]: 25
7834 23:25:52.003058
7835 23:25:52.005708 Set Vref, RX VrefLevel [Byte0]: 26
7836 23:25:52.009376 [Byte1]: 26
7837 23:25:52.013165
7838 23:25:52.013771 Set Vref, RX VrefLevel [Byte0]: 27
7839 23:25:52.016244 [Byte1]: 27
7840 23:25:52.020862
7841 23:25:52.021392 Set Vref, RX VrefLevel [Byte0]: 28
7842 23:25:52.024212 [Byte1]: 28
7843 23:25:52.028358
7844 23:25:52.028873 Set Vref, RX VrefLevel [Byte0]: 29
7845 23:25:52.031339 [Byte1]: 29
7846 23:25:52.036047
7847 23:25:52.036583 Set Vref, RX VrefLevel [Byte0]: 30
7848 23:25:52.039261 [Byte1]: 30
7849 23:25:52.043366
7850 23:25:52.043880 Set Vref, RX VrefLevel [Byte0]: 31
7851 23:25:52.047050 [Byte1]: 31
7852 23:25:52.051325
7853 23:25:52.051843 Set Vref, RX VrefLevel [Byte0]: 32
7854 23:25:52.054298 [Byte1]: 32
7855 23:25:52.059276
7856 23:25:52.059787 Set Vref, RX VrefLevel [Byte0]: 33
7857 23:25:52.061973 [Byte1]: 33
7858 23:25:52.066457
7859 23:25:52.066987 Set Vref, RX VrefLevel [Byte0]: 34
7860 23:25:52.069147 [Byte1]: 34
7861 23:25:52.073850
7862 23:25:52.074360 Set Vref, RX VrefLevel [Byte0]: 35
7863 23:25:52.077503 [Byte1]: 35
7864 23:25:52.081278
7865 23:25:52.081872 Set Vref, RX VrefLevel [Byte0]: 36
7866 23:25:52.084228 [Byte1]: 36
7867 23:25:52.088766
7868 23:25:52.089271 Set Vref, RX VrefLevel [Byte0]: 37
7869 23:25:52.091891 [Byte1]: 37
7870 23:25:52.096374
7871 23:25:52.096923 Set Vref, RX VrefLevel [Byte0]: 38
7872 23:25:52.099726 [Byte1]: 38
7873 23:25:52.104677
7874 23:25:52.105187 Set Vref, RX VrefLevel [Byte0]: 39
7875 23:25:52.107463 [Byte1]: 39
7876 23:25:52.111558
7877 23:25:52.112068 Set Vref, RX VrefLevel [Byte0]: 40
7878 23:25:52.115215 [Byte1]: 40
7879 23:25:52.118936
7880 23:25:52.119351 Set Vref, RX VrefLevel [Byte0]: 41
7881 23:25:52.122496 [Byte1]: 41
7882 23:25:52.127190
7883 23:25:52.127699 Set Vref, RX VrefLevel [Byte0]: 42
7884 23:25:52.129918 [Byte1]: 42
7885 23:25:52.135097
7886 23:25:52.135615 Set Vref, RX VrefLevel [Byte0]: 43
7887 23:25:52.137607 [Byte1]: 43
7888 23:25:52.141748
7889 23:25:52.142257 Set Vref, RX VrefLevel [Byte0]: 44
7890 23:25:52.145893 [Byte1]: 44
7891 23:25:52.149463
7892 23:25:52.150044 Set Vref, RX VrefLevel [Byte0]: 45
7893 23:25:52.152645 [Byte1]: 45
7894 23:25:52.156793
7895 23:25:52.157207 Set Vref, RX VrefLevel [Byte0]: 46
7896 23:25:52.160047 [Byte1]: 46
7897 23:25:52.164668
7898 23:25:52.165179 Set Vref, RX VrefLevel [Byte0]: 47
7899 23:25:52.168214 [Byte1]: 47
7900 23:25:52.172517
7901 23:25:52.173028 Set Vref, RX VrefLevel [Byte0]: 48
7902 23:25:52.175582 [Byte1]: 48
7903 23:25:52.179648
7904 23:25:52.180069 Set Vref, RX VrefLevel [Byte0]: 49
7905 23:25:52.182804 [Byte1]: 49
7906 23:25:52.187694
7907 23:25:52.188204 Set Vref, RX VrefLevel [Byte0]: 50
7908 23:25:52.190216 [Byte1]: 50
7909 23:25:52.194892
7910 23:25:52.195335 Set Vref, RX VrefLevel [Byte0]: 51
7911 23:25:52.198059 [Byte1]: 51
7912 23:25:52.202157
7913 23:25:52.202689 Set Vref, RX VrefLevel [Byte0]: 52
7914 23:25:52.205812 [Byte1]: 52
7915 23:25:52.209993
7916 23:25:52.210518 Set Vref, RX VrefLevel [Byte0]: 53
7917 23:25:52.212844 [Byte1]: 53
7918 23:25:52.217305
7919 23:25:52.217883 Set Vref, RX VrefLevel [Byte0]: 54
7920 23:25:52.220559 [Byte1]: 54
7921 23:25:52.224981
7922 23:25:52.225390 Set Vref, RX VrefLevel [Byte0]: 55
7923 23:25:52.228476 [Byte1]: 55
7924 23:25:52.232663
7925 23:25:52.233284 Set Vref, RX VrefLevel [Byte0]: 56
7926 23:25:52.236216 [Byte1]: 56
7927 23:25:52.240936
7928 23:25:52.241449 Set Vref, RX VrefLevel [Byte0]: 57
7929 23:25:52.243557 [Byte1]: 57
7930 23:25:52.247752
7931 23:25:52.248258 Set Vref, RX VrefLevel [Byte0]: 58
7932 23:25:52.251558 [Byte1]: 58
7933 23:25:52.255284
7934 23:25:52.255920 Set Vref, RX VrefLevel [Byte0]: 59
7935 23:25:52.258746 [Byte1]: 59
7936 23:25:52.263129
7937 23:25:52.263676 Set Vref, RX VrefLevel [Byte0]: 60
7938 23:25:52.266467 [Byte1]: 60
7939 23:25:52.270961
7940 23:25:52.271469 Set Vref, RX VrefLevel [Byte0]: 61
7941 23:25:52.273828 [Byte1]: 61
7942 23:25:52.277797
7943 23:25:52.278253 Set Vref, RX VrefLevel [Byte0]: 62
7944 23:25:52.281365 [Byte1]: 62
7945 23:25:52.285868
7946 23:25:52.286474 Set Vref, RX VrefLevel [Byte0]: 63
7947 23:25:52.289130 [Byte1]: 63
7948 23:25:52.293242
7949 23:25:52.293696 Set Vref, RX VrefLevel [Byte0]: 64
7950 23:25:52.296993 [Byte1]: 64
7951 23:25:52.300926
7952 23:25:52.301436 Set Vref, RX VrefLevel [Byte0]: 65
7953 23:25:52.304347 [Byte1]: 65
7954 23:25:52.308778
7955 23:25:52.309283 Set Vref, RX VrefLevel [Byte0]: 66
7956 23:25:52.311733 [Byte1]: 66
7957 23:25:52.316471
7958 23:25:52.316987 Set Vref, RX VrefLevel [Byte0]: 67
7959 23:25:52.319525 [Byte1]: 67
7960 23:25:52.323772
7961 23:25:52.324281 Set Vref, RX VrefLevel [Byte0]: 68
7962 23:25:52.326904 [Byte1]: 68
7963 23:25:52.331554
7964 23:25:52.332067 Set Vref, RX VrefLevel [Byte0]: 69
7965 23:25:52.334055 [Byte1]: 69
7966 23:25:52.339168
7967 23:25:52.339690 Set Vref, RX VrefLevel [Byte0]: 70
7968 23:25:52.342145 [Byte1]: 70
7969 23:25:52.346551
7970 23:25:52.347149 Set Vref, RX VrefLevel [Byte0]: 71
7971 23:25:52.350258 [Byte1]: 71
7972 23:25:52.354402
7973 23:25:52.354911 Set Vref, RX VrefLevel [Byte0]: 72
7974 23:25:52.357469 [Byte1]: 72
7975 23:25:52.361410
7976 23:25:52.361966 Set Vref, RX VrefLevel [Byte0]: 73
7977 23:25:52.364862 [Byte1]: 73
7978 23:25:52.368902
7979 23:25:52.369314 Set Vref, RX VrefLevel [Byte0]: 74
7980 23:25:52.372225 [Byte1]: 74
7981 23:25:52.376575
7982 23:25:52.377118 Set Vref, RX VrefLevel [Byte0]: 75
7983 23:25:52.379872 [Byte1]: 75
7984 23:25:52.383949
7985 23:25:52.384475 Set Vref, RX VrefLevel [Byte0]: 76
7986 23:25:52.387331 [Byte1]: 76
7987 23:25:52.391777
7988 23:25:52.392197 Final RX Vref Byte 0 = 59 to rank0
7989 23:25:52.395004 Final RX Vref Byte 1 = 62 to rank0
7990 23:25:52.398196 Final RX Vref Byte 0 = 59 to rank1
7991 23:25:52.401415 Final RX Vref Byte 1 = 62 to rank1==
7992 23:25:52.405108 Dram Type= 6, Freq= 0, CH_0, rank 0
7993 23:25:52.412170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7994 23:25:52.412688 ==
7995 23:25:52.413018 DQS Delay:
7996 23:25:52.413318 DQS0 = 0, DQS1 = 0
7997 23:25:52.414997 DQM Delay:
7998 23:25:52.415508 DQM0 = 134, DQM1 = 127
7999 23:25:52.417944 DQ Delay:
8000 23:25:52.421163 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
8001 23:25:52.425353 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8002 23:25:52.428312 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
8003 23:25:52.431557 DQ12 =132, DQ13 =134, DQ14 =138, DQ15 =134
8004 23:25:52.432073
8005 23:25:52.432396
8006 23:25:52.432692
8007 23:25:52.434451 [DramC_TX_OE_Calibration] TA2
8008 23:25:52.438423 Original DQ_B0 (3 6) =30, OEN = 27
8009 23:25:52.441599 Original DQ_B1 (3 6) =30, OEN = 27
8010 23:25:52.445208 24, 0x0, End_B0=24 End_B1=24
8011 23:25:52.445838 25, 0x0, End_B0=25 End_B1=25
8012 23:25:52.448506 26, 0x0, End_B0=26 End_B1=26
8013 23:25:52.451616 27, 0x0, End_B0=27 End_B1=27
8014 23:25:52.455302 28, 0x0, End_B0=28 End_B1=28
8015 23:25:52.456079 29, 0x0, End_B0=29 End_B1=29
8016 23:25:52.458067 30, 0x0, End_B0=30 End_B1=30
8017 23:25:52.461676 31, 0x4545, End_B0=30 End_B1=30
8018 23:25:52.464603 Byte0 end_step=30 best_step=27
8019 23:25:52.468380 Byte1 end_step=30 best_step=27
8020 23:25:52.471774 Byte0 TX OE(2T, 0.5T) = (3, 3)
8021 23:25:52.474895 Byte1 TX OE(2T, 0.5T) = (3, 3)
8022 23:25:52.475445
8023 23:25:52.475806
8024 23:25:52.481126 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8025 23:25:52.484485 CH0 RK0: MR19=303, MR18=2521
8026 23:25:52.491229 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8027 23:25:52.491816
8028 23:25:52.494718 ----->DramcWriteLeveling(PI) begin...
8029 23:25:52.495182 ==
8030 23:25:52.497862 Dram Type= 6, Freq= 0, CH_0, rank 1
8031 23:25:52.501227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 23:25:52.501957 ==
8033 23:25:52.504479 Write leveling (Byte 0): 36 => 36
8034 23:25:52.507779 Write leveling (Byte 1): 27 => 27
8035 23:25:52.511232 DramcWriteLeveling(PI) end<-----
8036 23:25:52.511713
8037 23:25:52.512068 ==
8038 23:25:52.514265 Dram Type= 6, Freq= 0, CH_0, rank 1
8039 23:25:52.517899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8040 23:25:52.518463 ==
8041 23:25:52.521211 [Gating] SW mode calibration
8042 23:25:52.527950 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8043 23:25:52.534418 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8044 23:25:52.538079 1 4 0 | B1->B0 | 2323 2222 | 0 1 | (0 0) (0 0)
8045 23:25:52.541398 1 4 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8046 23:25:52.547798 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8047 23:25:52.551404 1 4 12 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8048 23:25:52.554920 1 4 16 | B1->B0 | 3030 3838 | 0 0 | (0 0) (0 0)
8049 23:25:52.561110 1 4 20 | B1->B0 | 3434 3a39 | 1 1 | (1 1) (1 1)
8050 23:25:52.564653 1 4 24 | B1->B0 | 3434 3838 | 1 1 | (1 1) (1 1)
8051 23:25:52.567581 1 4 28 | B1->B0 | 3434 3737 | 1 1 | (1 1) (1 1)
8052 23:25:52.574042 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8053 23:25:52.577320 1 5 4 | B1->B0 | 3434 3938 | 1 1 | (1 1) (0 0)
8054 23:25:52.581264 1 5 8 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
8055 23:25:52.587392 1 5 12 | B1->B0 | 3434 3736 | 1 1 | (1 1) (0 0)
8056 23:25:52.590767 1 5 16 | B1->B0 | 3131 2c2b | 1 1 | (1 0) (1 0)
8057 23:25:52.594225 1 5 20 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (0 0)
8058 23:25:52.600507 1 5 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
8059 23:25:52.604696 1 5 28 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
8060 23:25:52.607232 1 6 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8061 23:25:52.613757 1 6 4 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8062 23:25:52.617235 1 6 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8063 23:25:52.620381 1 6 12 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8064 23:25:52.627209 1 6 16 | B1->B0 | 3737 4645 | 0 1 | (0 0) (0 0)
8065 23:25:52.630732 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8066 23:25:52.633690 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8067 23:25:52.640742 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8068 23:25:52.643976 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8069 23:25:52.647059 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8070 23:25:52.653815 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8071 23:25:52.656739 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8072 23:25:52.660834 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 23:25:52.667307 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 23:25:52.670422 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 23:25:52.673971 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8076 23:25:52.677255 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8077 23:25:52.683988 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8078 23:25:52.686962 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8079 23:25:52.690949 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8080 23:25:52.697503 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8081 23:25:52.700736 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8082 23:25:52.704426 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8083 23:25:52.710617 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 23:25:52.714040 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 23:25:52.717697 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 23:25:52.723618 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8087 23:25:52.727287 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8088 23:25:52.730124 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8089 23:25:52.733560 Total UI for P1: 0, mck2ui 16
8090 23:25:52.737554 best dqsien dly found for B0: ( 1, 9, 10)
8091 23:25:52.740711 Total UI for P1: 0, mck2ui 16
8092 23:25:52.744031 best dqsien dly found for B1: ( 1, 9, 12)
8093 23:25:52.746993 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8094 23:25:52.751232 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8095 23:25:52.751792
8096 23:25:52.757323 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8097 23:25:52.760680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8098 23:25:52.763464 [Gating] SW calibration Done
8099 23:25:52.763919 ==
8100 23:25:52.767114 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 23:25:52.770444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 23:25:52.771044 ==
8103 23:25:52.771406 RX Vref Scan: 0
8104 23:25:52.771742
8105 23:25:52.773624 RX Vref 0 -> 0, step: 1
8106 23:25:52.774199
8107 23:25:52.777266 RX Delay 0 -> 252, step: 8
8108 23:25:52.780444 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8109 23:25:52.783562 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8110 23:25:52.787042 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8111 23:25:52.793558 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8112 23:25:52.796930 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8113 23:25:52.800953 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8114 23:25:52.803436 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8115 23:25:52.807287 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8116 23:25:52.813730 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8117 23:25:52.816974 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8118 23:25:52.820375 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8119 23:25:52.823908 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8120 23:25:52.826701 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8121 23:25:52.833511 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8122 23:25:52.836776 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8123 23:25:52.840694 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8124 23:25:52.841242 ==
8125 23:25:52.843467 Dram Type= 6, Freq= 0, CH_0, rank 1
8126 23:25:52.847205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8127 23:25:52.850038 ==
8128 23:25:52.850598 DQS Delay:
8129 23:25:52.850960 DQS0 = 0, DQS1 = 0
8130 23:25:52.853260 DQM Delay:
8131 23:25:52.853852 DQM0 = 137, DQM1 = 128
8132 23:25:52.856657 DQ Delay:
8133 23:25:52.860102 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8134 23:25:52.863793 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8135 23:25:52.866952 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8136 23:25:52.870518 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8137 23:25:52.871072
8138 23:25:52.871429
8139 23:25:52.871757 ==
8140 23:25:52.873282 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 23:25:52.876522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 23:25:52.876981 ==
8143 23:25:52.877336
8144 23:25:52.879977
8145 23:25:52.880530 TX Vref Scan disable
8146 23:25:52.883289 == TX Byte 0 ==
8147 23:25:52.886292 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8148 23:25:52.889786 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8149 23:25:52.893145 == TX Byte 1 ==
8150 23:25:52.896685 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8151 23:25:52.900540 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8152 23:25:52.901093 ==
8153 23:25:52.902965 Dram Type= 6, Freq= 0, CH_0, rank 1
8154 23:25:52.909690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8155 23:25:52.910226 ==
8156 23:25:52.923799
8157 23:25:52.927631 TX Vref early break, caculate TX vref
8158 23:25:52.930605 TX Vref=16, minBit 1, minWin=23, winSum=386
8159 23:25:52.933641 TX Vref=18, minBit 1, minWin=23, winSum=398
8160 23:25:52.937234 TX Vref=20, minBit 1, minWin=23, winSum=404
8161 23:25:52.940732 TX Vref=22, minBit 0, minWin=24, winSum=411
8162 23:25:52.943882 TX Vref=24, minBit 0, minWin=25, winSum=419
8163 23:25:52.950740 TX Vref=26, minBit 1, minWin=25, winSum=428
8164 23:25:52.953725 TX Vref=28, minBit 2, minWin=25, winSum=425
8165 23:25:52.957060 TX Vref=30, minBit 0, minWin=25, winSum=418
8166 23:25:52.960143 TX Vref=32, minBit 1, minWin=24, winSum=408
8167 23:25:52.963618 TX Vref=34, minBit 1, minWin=24, winSum=407
8168 23:25:52.967234 TX Vref=36, minBit 0, minWin=24, winSum=395
8169 23:25:52.974035 [TxChooseVref] Worse bit 1, Min win 25, Win sum 428, Final Vref 26
8170 23:25:52.974613
8171 23:25:52.976784 Final TX Range 0 Vref 26
8172 23:25:52.977240
8173 23:25:52.977637 ==
8174 23:25:52.980431 Dram Type= 6, Freq= 0, CH_0, rank 1
8175 23:25:52.983910 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8176 23:25:52.984475 ==
8177 23:25:52.984839
8178 23:25:52.985167
8179 23:25:52.987335 TX Vref Scan disable
8180 23:25:52.993499 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8181 23:25:52.994027 == TX Byte 0 ==
8182 23:25:52.996767 u2DelayCellOfst[0]=10 cells (3 PI)
8183 23:25:53.000332 u2DelayCellOfst[1]=13 cells (4 PI)
8184 23:25:53.003406 u2DelayCellOfst[2]=10 cells (3 PI)
8185 23:25:53.006926 u2DelayCellOfst[3]=6 cells (2 PI)
8186 23:25:53.010135 u2DelayCellOfst[4]=6 cells (2 PI)
8187 23:25:53.013857 u2DelayCellOfst[5]=0 cells (0 PI)
8188 23:25:53.016776 u2DelayCellOfst[6]=13 cells (4 PI)
8189 23:25:53.020510 u2DelayCellOfst[7]=13 cells (4 PI)
8190 23:25:53.023778 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8191 23:25:53.026278 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8192 23:25:53.029744 == TX Byte 1 ==
8193 23:25:53.033458 u2DelayCellOfst[8]=0 cells (0 PI)
8194 23:25:53.036389 u2DelayCellOfst[9]=0 cells (0 PI)
8195 23:25:53.036847 u2DelayCellOfst[10]=3 cells (1 PI)
8196 23:25:53.039834 u2DelayCellOfst[11]=0 cells (0 PI)
8197 23:25:53.042926 u2DelayCellOfst[12]=10 cells (3 PI)
8198 23:25:53.046314 u2DelayCellOfst[13]=10 cells (3 PI)
8199 23:25:53.049844 u2DelayCellOfst[14]=10 cells (3 PI)
8200 23:25:53.053109 u2DelayCellOfst[15]=10 cells (3 PI)
8201 23:25:53.059374 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8202 23:25:53.062708 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8203 23:25:53.063165 DramC Write-DBI on
8204 23:25:53.063582 ==
8205 23:25:53.066142 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 23:25:53.073099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 23:25:53.073687 ==
8208 23:25:53.074057
8209 23:25:53.074385
8210 23:25:53.074699 TX Vref Scan disable
8211 23:25:53.077268 == TX Byte 0 ==
8212 23:25:53.080735 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8213 23:25:53.083750 == TX Byte 1 ==
8214 23:25:53.087425 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8215 23:25:53.090252 DramC Write-DBI off
8216 23:25:53.090710
8217 23:25:53.091066 [DATLAT]
8218 23:25:53.091393 Freq=1600, CH0 RK1
8219 23:25:53.091782
8220 23:25:53.093893 DATLAT Default: 0xf
8221 23:25:53.094351 0, 0xFFFF, sum = 0
8222 23:25:53.096987 1, 0xFFFF, sum = 0
8223 23:25:53.097450 2, 0xFFFF, sum = 0
8224 23:25:53.100451 3, 0xFFFF, sum = 0
8225 23:25:53.103885 4, 0xFFFF, sum = 0
8226 23:25:53.104446 5, 0xFFFF, sum = 0
8227 23:25:53.107542 6, 0xFFFF, sum = 0
8228 23:25:53.108109 7, 0xFFFF, sum = 0
8229 23:25:53.110683 8, 0xFFFF, sum = 0
8230 23:25:53.111151 9, 0xFFFF, sum = 0
8231 23:25:53.113489 10, 0xFFFF, sum = 0
8232 23:25:53.114019 11, 0xFFFF, sum = 0
8233 23:25:53.117985 12, 0xFFFF, sum = 0
8234 23:25:53.118626 13, 0xFFFF, sum = 0
8235 23:25:53.120477 14, 0x0, sum = 1
8236 23:25:53.120942 15, 0x0, sum = 2
8237 23:25:53.124093 16, 0x0, sum = 3
8238 23:25:53.124655 17, 0x0, sum = 4
8239 23:25:53.127810 best_step = 15
8240 23:25:53.128362
8241 23:25:53.128724 ==
8242 23:25:53.130357 Dram Type= 6, Freq= 0, CH_0, rank 1
8243 23:25:53.133617 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8244 23:25:53.134178 ==
8245 23:25:53.134544 RX Vref Scan: 0
8246 23:25:53.137089
8247 23:25:53.137687 RX Vref 0 -> 0, step: 1
8248 23:25:53.138115
8249 23:25:53.140628 RX Delay 19 -> 252, step: 4
8250 23:25:53.143372 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8251 23:25:53.150440 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8252 23:25:53.153744 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8253 23:25:53.156872 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8254 23:25:53.160262 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8255 23:25:53.163314 iDelay=191, Bit 5, Center 128 (75 ~ 182) 108
8256 23:25:53.170294 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8257 23:25:53.174277 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8258 23:25:53.176562 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8259 23:25:53.180354 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8260 23:25:53.183362 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8261 23:25:53.190242 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8262 23:25:53.193171 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8263 23:25:53.196688 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8264 23:25:53.200015 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8265 23:25:53.203378 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8266 23:25:53.206832 ==
8267 23:25:53.209826 Dram Type= 6, Freq= 0, CH_0, rank 1
8268 23:25:53.213528 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8269 23:25:53.214190 ==
8270 23:25:53.214569 DQS Delay:
8271 23:25:53.216599 DQS0 = 0, DQS1 = 0
8272 23:25:53.217194 DQM Delay:
8273 23:25:53.220325 DQM0 = 135, DQM1 = 127
8274 23:25:53.220880 DQ Delay:
8275 23:25:53.223288 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8276 23:25:53.226186 DQ4 =136, DQ5 =128, DQ6 =140, DQ7 =140
8277 23:25:53.229381 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8278 23:25:53.232954 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
8279 23:25:53.233521
8280 23:25:53.234039
8281 23:25:53.234777
8282 23:25:53.236285 [DramC_TX_OE_Calibration] TA2
8283 23:25:53.239869 Original DQ_B0 (3 6) =30, OEN = 27
8284 23:25:53.243452 Original DQ_B1 (3 6) =30, OEN = 27
8285 23:25:53.246604 24, 0x0, End_B0=24 End_B1=24
8286 23:25:53.249687 25, 0x0, End_B0=25 End_B1=25
8287 23:25:53.250212 26, 0x0, End_B0=26 End_B1=26
8288 23:25:53.253113 27, 0x0, End_B0=27 End_B1=27
8289 23:25:53.256161 28, 0x0, End_B0=28 End_B1=28
8290 23:25:53.259712 29, 0x0, End_B0=29 End_B1=29
8291 23:25:53.260406 30, 0x0, End_B0=30 End_B1=30
8292 23:25:53.263448 31, 0x4141, End_B0=30 End_B1=30
8293 23:25:53.266982 Byte0 end_step=30 best_step=27
8294 23:25:53.270084 Byte1 end_step=30 best_step=27
8295 23:25:53.272982 Byte0 TX OE(2T, 0.5T) = (3, 3)
8296 23:25:53.276349 Byte1 TX OE(2T, 0.5T) = (3, 3)
8297 23:25:53.276801
8298 23:25:53.277223
8299 23:25:53.282747 [DQSOSCAuto] RK1, (LSB)MR18= 0x220a, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 392 ps
8300 23:25:53.286191 CH0 RK1: MR19=303, MR18=220A
8301 23:25:53.292755 CH0_RK1: MR19=0x303, MR18=0x220A, DQSOSC=392, MR23=63, INC=24, DEC=16
8302 23:25:53.296543 [RxdqsGatingPostProcess] freq 1600
8303 23:25:53.303135 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8304 23:25:53.303780 best DQS0 dly(2T, 0.5T) = (1, 1)
8305 23:25:53.306369 best DQS1 dly(2T, 0.5T) = (1, 1)
8306 23:25:53.309817 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8307 23:25:53.313076 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8308 23:25:53.316769 best DQS0 dly(2T, 0.5T) = (1, 1)
8309 23:25:53.319671 best DQS1 dly(2T, 0.5T) = (1, 1)
8310 23:25:53.322908 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8311 23:25:53.326076 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8312 23:25:53.329655 Pre-setting of DQS Precalculation
8313 23:25:53.333166 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8314 23:25:53.333723 ==
8315 23:25:53.336700 Dram Type= 6, Freq= 0, CH_1, rank 0
8316 23:25:53.343544 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8317 23:25:53.344067 ==
8318 23:25:53.345984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8319 23:25:53.349346 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8320 23:25:53.356473 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8321 23:25:53.362308 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8322 23:25:53.370310 [CA 0] Center 41 (12~71) winsize 60
8323 23:25:53.373830 [CA 1] Center 41 (12~71) winsize 60
8324 23:25:53.376983 [CA 2] Center 38 (9~68) winsize 60
8325 23:25:53.380326 [CA 3] Center 37 (8~66) winsize 59
8326 23:25:53.383364 [CA 4] Center 38 (9~68) winsize 60
8327 23:25:53.386767 [CA 5] Center 36 (7~66) winsize 60
8328 23:25:53.387320
8329 23:25:53.389920 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8330 23:25:53.390381
8331 23:25:53.393215 [CATrainingPosCal] consider 1 rank data
8332 23:25:53.396296 u2DelayCellTimex100 = 290/100 ps
8333 23:25:53.399897 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8334 23:25:53.406497 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8335 23:25:53.410131 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8336 23:25:53.413137 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8337 23:25:53.416796 CA4 delay=38 (9~68),Diff = 2 PI (6 cell)
8338 23:25:53.419702 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8339 23:25:53.420166
8340 23:25:53.423400 CA PerBit enable=1, Macro0, CA PI delay=36
8341 23:25:53.423864
8342 23:25:53.426353 [CBTSetCACLKResult] CA Dly = 36
8343 23:25:53.430079 CS Dly: 10 (0~41)
8344 23:25:53.433627 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8345 23:25:53.436379 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8346 23:25:53.436838 ==
8347 23:25:53.440147 Dram Type= 6, Freq= 0, CH_1, rank 1
8348 23:25:53.443082 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 23:25:53.446663 ==
8350 23:25:53.450134 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8351 23:25:53.453421 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8352 23:25:53.459589 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8353 23:25:53.462877 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8354 23:25:53.473483 [CA 0] Center 42 (12~72) winsize 61
8355 23:25:53.476966 [CA 1] Center 42 (12~72) winsize 61
8356 23:25:53.479761 [CA 2] Center 38 (9~68) winsize 60
8357 23:25:53.483232 [CA 3] Center 38 (8~68) winsize 61
8358 23:25:53.486930 [CA 4] Center 38 (8~69) winsize 62
8359 23:25:53.489433 [CA 5] Center 37 (7~67) winsize 61
8360 23:25:53.490098
8361 23:25:53.492840 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8362 23:25:53.493407
8363 23:25:53.496219 [CATrainingPosCal] consider 2 rank data
8364 23:25:53.499522 u2DelayCellTimex100 = 290/100 ps
8365 23:25:53.502868 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8366 23:25:53.509469 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8367 23:25:53.513224 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8368 23:25:53.516450 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8369 23:25:53.520043 CA4 delay=38 (9~68),Diff = 2 PI (6 cell)
8370 23:25:53.522690 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8371 23:25:53.522959
8372 23:25:53.526351 CA PerBit enable=1, Macro0, CA PI delay=36
8373 23:25:53.526870
8374 23:25:53.529696 [CBTSetCACLKResult] CA Dly = 36
8375 23:25:53.532941 CS Dly: 12 (0~45)
8376 23:25:53.536491 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8377 23:25:53.539978 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8378 23:25:53.540304
8379 23:25:53.543782 ----->DramcWriteLeveling(PI) begin...
8380 23:25:53.544120 ==
8381 23:25:53.546564 Dram Type= 6, Freq= 0, CH_1, rank 0
8382 23:25:53.549318 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8383 23:25:53.552957 ==
8384 23:25:53.553334 Write leveling (Byte 0): 25 => 25
8385 23:25:53.556067 Write leveling (Byte 1): 28 => 28
8386 23:25:53.560090 DramcWriteLeveling(PI) end<-----
8387 23:25:53.560322
8388 23:25:53.560510 ==
8389 23:25:53.562624 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 23:25:53.569380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 23:25:53.569738 ==
8392 23:25:53.569938 [Gating] SW mode calibration
8393 23:25:53.579339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8394 23:25:53.582675 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8395 23:25:53.589338 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 23:25:53.592553 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 23:25:53.596630 1 4 8 | B1->B0 | 2322 2c2c | 1 1 | (0 0) (0 0)
8398 23:25:53.602792 1 4 12 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
8399 23:25:53.606346 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8400 23:25:53.609528 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8401 23:25:53.616114 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8402 23:25:53.619136 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8403 23:25:53.622652 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8404 23:25:53.629552 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8405 23:25:53.632431 1 5 8 | B1->B0 | 3333 3232 | 1 1 | (1 1) (1 0)
8406 23:25:53.635490 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (1 0)
8407 23:25:53.642984 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 23:25:53.645976 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8409 23:25:53.649057 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8410 23:25:53.652502 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8411 23:25:53.658983 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8412 23:25:53.662515 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8413 23:25:53.669128 1 6 8 | B1->B0 | 2727 403f | 0 1 | (0 0) (0 0)
8414 23:25:53.672084 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8415 23:25:53.675655 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8416 23:25:53.681969 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8417 23:25:53.685758 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8418 23:25:53.688767 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8419 23:25:53.695146 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8420 23:25:53.698104 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8421 23:25:53.701538 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8422 23:25:53.704926 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8423 23:25:53.711549 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 23:25:53.715197 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 23:25:53.718465 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 23:25:53.725255 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 23:25:53.728457 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8428 23:25:53.731794 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8429 23:25:53.738324 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8430 23:25:53.741761 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8431 23:25:53.744900 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8432 23:25:53.751606 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8433 23:25:53.755463 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8434 23:25:53.758587 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8435 23:25:53.765343 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 23:25:53.768355 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 23:25:53.771326 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8438 23:25:53.778121 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8439 23:25:53.781369 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8440 23:25:53.784311 Total UI for P1: 0, mck2ui 16
8441 23:25:53.788307 best dqsien dly found for B0: ( 1, 9, 10)
8442 23:25:53.791135 Total UI for P1: 0, mck2ui 16
8443 23:25:53.794253 best dqsien dly found for B1: ( 1, 9, 10)
8444 23:25:53.798292 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8445 23:25:53.800935 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8446 23:25:53.801494
8447 23:25:53.804452 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8448 23:25:53.808491 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8449 23:25:53.811169 [Gating] SW calibration Done
8450 23:25:53.811723 ==
8451 23:25:53.814417 Dram Type= 6, Freq= 0, CH_1, rank 0
8452 23:25:53.821120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8453 23:25:53.821722 ==
8454 23:25:53.822089 RX Vref Scan: 0
8455 23:25:53.822423
8456 23:25:53.824190 RX Vref 0 -> 0, step: 1
8457 23:25:53.824651
8458 23:25:53.827783 RX Delay 0 -> 252, step: 8
8459 23:25:53.831143 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8460 23:25:53.834550 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8461 23:25:53.837777 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8462 23:25:53.840792 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8463 23:25:53.847611 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8464 23:25:53.850877 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8465 23:25:53.854585 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8466 23:25:53.857631 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8467 23:25:53.860936 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8468 23:25:53.867567 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8469 23:25:53.871092 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8470 23:25:53.874186 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8471 23:25:53.877611 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8472 23:25:53.880854 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8473 23:25:53.887937 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8474 23:25:53.890642 iDelay=200, Bit 15, Center 147 (96 ~ 199) 104
8475 23:25:53.891121 ==
8476 23:25:53.894600 Dram Type= 6, Freq= 0, CH_1, rank 0
8477 23:25:53.898031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8478 23:25:53.898592 ==
8479 23:25:53.898956 DQS Delay:
8480 23:25:53.901110 DQS0 = 0, DQS1 = 0
8481 23:25:53.901725 DQM Delay:
8482 23:25:53.905120 DQM0 = 136, DQM1 = 134
8483 23:25:53.905719 DQ Delay:
8484 23:25:53.908003 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8485 23:25:53.911185 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8486 23:25:53.915049 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8487 23:25:53.917844 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =147
8488 23:25:53.921231
8489 23:25:53.921823
8490 23:25:53.922184 ==
8491 23:25:53.924344 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 23:25:53.928052 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 23:25:53.928612 ==
8494 23:25:53.928975
8495 23:25:53.929307
8496 23:25:53.931163 TX Vref Scan disable
8497 23:25:53.931718 == TX Byte 0 ==
8498 23:25:53.937463 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8499 23:25:53.941398 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8500 23:25:53.942006 == TX Byte 1 ==
8501 23:25:53.947840 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8502 23:25:53.950945 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8503 23:25:53.951407 ==
8504 23:25:53.954387 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 23:25:53.958099 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 23:25:53.958565 ==
8507 23:25:53.971168
8508 23:25:53.974439 TX Vref early break, caculate TX vref
8509 23:25:53.978210 TX Vref=16, minBit 9, minWin=22, winSum=380
8510 23:25:53.980594 TX Vref=18, minBit 1, minWin=23, winSum=390
8511 23:25:53.983958 TX Vref=20, minBit 0, minWin=24, winSum=397
8512 23:25:53.987832 TX Vref=22, minBit 0, minWin=25, winSum=407
8513 23:25:53.990794 TX Vref=24, minBit 0, minWin=25, winSum=421
8514 23:25:53.997623 TX Vref=26, minBit 0, minWin=26, winSum=426
8515 23:25:54.001341 TX Vref=28, minBit 6, minWin=25, winSum=428
8516 23:25:54.004081 TX Vref=30, minBit 0, minWin=25, winSum=421
8517 23:25:54.007861 TX Vref=32, minBit 6, minWin=24, winSum=410
8518 23:25:54.011115 TX Vref=34, minBit 0, minWin=24, winSum=403
8519 23:25:54.017949 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 26
8520 23:25:54.018503
8521 23:25:54.020756 Final TX Range 0 Vref 26
8522 23:25:54.021307
8523 23:25:54.021709 ==
8524 23:25:54.023974 Dram Type= 6, Freq= 0, CH_1, rank 0
8525 23:25:54.027272 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8526 23:25:54.027828 ==
8527 23:25:54.028193
8528 23:25:54.028521
8529 23:25:54.031091 TX Vref Scan disable
8530 23:25:54.037494 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8531 23:25:54.038096 == TX Byte 0 ==
8532 23:25:54.040368 u2DelayCellOfst[0]=16 cells (5 PI)
8533 23:25:54.044095 u2DelayCellOfst[1]=10 cells (3 PI)
8534 23:25:54.046984 u2DelayCellOfst[2]=0 cells (0 PI)
8535 23:25:54.050694 u2DelayCellOfst[3]=3 cells (1 PI)
8536 23:25:54.054291 u2DelayCellOfst[4]=6 cells (2 PI)
8537 23:25:54.057672 u2DelayCellOfst[5]=16 cells (5 PI)
8538 23:25:54.060508 u2DelayCellOfst[6]=16 cells (5 PI)
8539 23:25:54.061020 u2DelayCellOfst[7]=6 cells (2 PI)
8540 23:25:54.067693 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8541 23:25:54.070572 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8542 23:25:54.071127 == TX Byte 1 ==
8543 23:25:54.073948 u2DelayCellOfst[8]=0 cells (0 PI)
8544 23:25:54.077526 u2DelayCellOfst[9]=3 cells (1 PI)
8545 23:25:54.080715 u2DelayCellOfst[10]=13 cells (4 PI)
8546 23:25:54.083592 u2DelayCellOfst[11]=6 cells (2 PI)
8547 23:25:54.086834 u2DelayCellOfst[12]=16 cells (5 PI)
8548 23:25:54.090256 u2DelayCellOfst[13]=13 cells (4 PI)
8549 23:25:54.093850 u2DelayCellOfst[14]=16 cells (5 PI)
8550 23:25:54.096723 u2DelayCellOfst[15]=16 cells (5 PI)
8551 23:25:54.100520 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8552 23:25:54.106948 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8553 23:25:54.107507 DramC Write-DBI on
8554 23:25:54.107865 ==
8555 23:25:54.109990 Dram Type= 6, Freq= 0, CH_1, rank 0
8556 23:25:54.113418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8557 23:25:54.116758 ==
8558 23:25:54.117229
8559 23:25:54.117630
8560 23:25:54.117981 TX Vref Scan disable
8561 23:25:54.119978 == TX Byte 0 ==
8562 23:25:54.123811 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8563 23:25:54.126910 == TX Byte 1 ==
8564 23:25:54.130333 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8565 23:25:54.134049 DramC Write-DBI off
8566 23:25:54.134558
8567 23:25:54.134884 [DATLAT]
8568 23:25:54.135181 Freq=1600, CH1 RK0
8569 23:25:54.135470
8570 23:25:54.136712 DATLAT Default: 0xf
8571 23:25:54.137128 0, 0xFFFF, sum = 0
8572 23:25:54.140207 1, 0xFFFF, sum = 0
8573 23:25:54.140630 2, 0xFFFF, sum = 0
8574 23:25:54.143628 3, 0xFFFF, sum = 0
8575 23:25:54.146738 4, 0xFFFF, sum = 0
8576 23:25:54.147161 5, 0xFFFF, sum = 0
8577 23:25:54.150537 6, 0xFFFF, sum = 0
8578 23:25:54.151058 7, 0xFFFF, sum = 0
8579 23:25:54.153483 8, 0xFFFF, sum = 0
8580 23:25:54.154021 9, 0xFFFF, sum = 0
8581 23:25:54.156468 10, 0xFFFF, sum = 0
8582 23:25:54.156890 11, 0xFFFF, sum = 0
8583 23:25:54.160001 12, 0xFFFF, sum = 0
8584 23:25:54.160487 13, 0xFFFF, sum = 0
8585 23:25:54.163305 14, 0x0, sum = 1
8586 23:25:54.163730 15, 0x0, sum = 2
8587 23:25:54.166846 16, 0x0, sum = 3
8588 23:25:54.167364 17, 0x0, sum = 4
8589 23:25:54.170585 best_step = 15
8590 23:25:54.171095
8591 23:25:54.171421 ==
8592 23:25:54.173374 Dram Type= 6, Freq= 0, CH_1, rank 0
8593 23:25:54.176902 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8594 23:25:54.177441 ==
8595 23:25:54.177831 RX Vref Scan: 1
8596 23:25:54.179972
8597 23:25:54.180479 Set Vref Range= 24 -> 127
8598 23:25:54.180804
8599 23:25:54.183222 RX Vref 24 -> 127, step: 1
8600 23:25:54.183637
8601 23:25:54.186604 RX Delay 27 -> 252, step: 4
8602 23:25:54.187019
8603 23:25:54.190101 Set Vref, RX VrefLevel [Byte0]: 24
8604 23:25:54.193159 [Byte1]: 24
8605 23:25:54.193616
8606 23:25:54.196581 Set Vref, RX VrefLevel [Byte0]: 25
8607 23:25:54.200017 [Byte1]: 25
8608 23:25:54.200531
8609 23:25:54.203223 Set Vref, RX VrefLevel [Byte0]: 26
8610 23:25:54.206395 [Byte1]: 26
8611 23:25:54.210386
8612 23:25:54.210974 Set Vref, RX VrefLevel [Byte0]: 27
8613 23:25:54.213647 [Byte1]: 27
8614 23:25:54.217754
8615 23:25:54.218266 Set Vref, RX VrefLevel [Byte0]: 28
8616 23:25:54.221320 [Byte1]: 28
8617 23:25:54.225460
8618 23:25:54.226046 Set Vref, RX VrefLevel [Byte0]: 29
8619 23:25:54.229393 [Byte1]: 29
8620 23:25:54.233043
8621 23:25:54.233642 Set Vref, RX VrefLevel [Byte0]: 30
8622 23:25:54.236325 [Byte1]: 30
8623 23:25:54.240489
8624 23:25:54.241072 Set Vref, RX VrefLevel [Byte0]: 31
8625 23:25:54.243875 [Byte1]: 31
8626 23:25:54.248254
8627 23:25:54.248713 Set Vref, RX VrefLevel [Byte0]: 32
8628 23:25:54.251554 [Byte1]: 32
8629 23:25:54.255468
8630 23:25:54.255977 Set Vref, RX VrefLevel [Byte0]: 33
8631 23:25:54.258512 [Byte1]: 33
8632 23:25:54.263013
8633 23:25:54.263471 Set Vref, RX VrefLevel [Byte0]: 34
8634 23:25:54.266567 [Byte1]: 34
8635 23:25:54.270253
8636 23:25:54.270993 Set Vref, RX VrefLevel [Byte0]: 35
8637 23:25:54.273440 [Byte1]: 35
8638 23:25:54.278242
8639 23:25:54.278657 Set Vref, RX VrefLevel [Byte0]: 36
8640 23:25:54.281188 [Byte1]: 36
8641 23:25:54.285604
8642 23:25:54.286223 Set Vref, RX VrefLevel [Byte0]: 37
8643 23:25:54.288874 [Byte1]: 37
8644 23:25:54.293039
8645 23:25:54.293756 Set Vref, RX VrefLevel [Byte0]: 38
8646 23:25:54.296247 [Byte1]: 38
8647 23:25:54.300575
8648 23:25:54.301119 Set Vref, RX VrefLevel [Byte0]: 39
8649 23:25:54.303663 [Byte1]: 39
8650 23:25:54.308886
8651 23:25:54.309400 Set Vref, RX VrefLevel [Byte0]: 40
8652 23:25:54.311729 [Byte1]: 40
8653 23:25:54.316221
8654 23:25:54.316731 Set Vref, RX VrefLevel [Byte0]: 41
8655 23:25:54.319118 [Byte1]: 41
8656 23:25:54.323641
8657 23:25:54.324152 Set Vref, RX VrefLevel [Byte0]: 42
8658 23:25:54.326368 [Byte1]: 42
8659 23:25:54.330663
8660 23:25:54.331178 Set Vref, RX VrefLevel [Byte0]: 43
8661 23:25:54.334150 [Byte1]: 43
8662 23:25:54.338164
8663 23:25:54.338671 Set Vref, RX VrefLevel [Byte0]: 44
8664 23:25:54.341694 [Byte1]: 44
8665 23:25:54.345546
8666 23:25:54.346006 Set Vref, RX VrefLevel [Byte0]: 45
8667 23:25:54.349004 [Byte1]: 45
8668 23:25:54.353017
8669 23:25:54.353452 Set Vref, RX VrefLevel [Byte0]: 46
8670 23:25:54.357019 [Byte1]: 46
8671 23:25:54.360637
8672 23:25:54.361056 Set Vref, RX VrefLevel [Byte0]: 47
8673 23:25:54.364434 [Byte1]: 47
8674 23:25:54.368286
8675 23:25:54.368702 Set Vref, RX VrefLevel [Byte0]: 48
8676 23:25:54.371966 [Byte1]: 48
8677 23:25:54.376281
8678 23:25:54.376837 Set Vref, RX VrefLevel [Byte0]: 49
8679 23:25:54.379071 [Byte1]: 49
8680 23:25:54.383258
8681 23:25:54.383711 Set Vref, RX VrefLevel [Byte0]: 50
8682 23:25:54.386568 [Byte1]: 50
8683 23:25:54.391271
8684 23:25:54.391946 Set Vref, RX VrefLevel [Byte0]: 51
8685 23:25:54.394313 [Byte1]: 51
8686 23:25:54.398740
8687 23:25:54.399156 Set Vref, RX VrefLevel [Byte0]: 52
8688 23:25:54.401961 [Byte1]: 52
8689 23:25:54.406623
8690 23:25:54.407038 Set Vref, RX VrefLevel [Byte0]: 53
8691 23:25:54.409677 [Byte1]: 53
8692 23:25:54.413947
8693 23:25:54.414453 Set Vref, RX VrefLevel [Byte0]: 54
8694 23:25:54.417442 [Byte1]: 54
8695 23:25:54.421625
8696 23:25:54.422144 Set Vref, RX VrefLevel [Byte0]: 55
8697 23:25:54.424414 [Byte1]: 55
8698 23:25:54.428747
8699 23:25:54.429269 Set Vref, RX VrefLevel [Byte0]: 56
8700 23:25:54.432243 [Byte1]: 56
8701 23:25:54.436312
8702 23:25:54.436867 Set Vref, RX VrefLevel [Byte0]: 57
8703 23:25:54.439393 [Byte1]: 57
8704 23:25:54.444050
8705 23:25:54.444562 Set Vref, RX VrefLevel [Byte0]: 58
8706 23:25:54.447215 [Byte1]: 58
8707 23:25:54.451757
8708 23:25:54.452174 Set Vref, RX VrefLevel [Byte0]: 59
8709 23:25:54.454888 [Byte1]: 59
8710 23:25:54.459066
8711 23:25:54.459622 Set Vref, RX VrefLevel [Byte0]: 60
8712 23:25:54.461945 [Byte1]: 60
8713 23:25:54.466552
8714 23:25:54.467064 Set Vref, RX VrefLevel [Byte0]: 61
8715 23:25:54.470136 [Byte1]: 61
8716 23:25:54.474211
8717 23:25:54.474762 Set Vref, RX VrefLevel [Byte0]: 62
8718 23:25:54.477101 [Byte1]: 62
8719 23:25:54.481367
8720 23:25:54.481879 Set Vref, RX VrefLevel [Byte0]: 63
8721 23:25:54.484681 [Byte1]: 63
8722 23:25:54.488983
8723 23:25:54.489446 Set Vref, RX VrefLevel [Byte0]: 64
8724 23:25:54.492119 [Byte1]: 64
8725 23:25:54.496285
8726 23:25:54.496698 Set Vref, RX VrefLevel [Byte0]: 65
8727 23:25:54.499861 [Byte1]: 65
8728 23:25:54.504162
8729 23:25:54.504788 Set Vref, RX VrefLevel [Byte0]: 66
8730 23:25:54.507172 [Byte1]: 66
8731 23:25:54.512034
8732 23:25:54.512545 Set Vref, RX VrefLevel [Byte0]: 67
8733 23:25:54.515443 [Byte1]: 67
8734 23:25:54.519171
8735 23:25:54.519683 Set Vref, RX VrefLevel [Byte0]: 68
8736 23:25:54.522866 [Byte1]: 68
8737 23:25:54.526742
8738 23:25:54.527200 Set Vref, RX VrefLevel [Byte0]: 69
8739 23:25:54.530237 [Byte1]: 69
8740 23:25:54.534506
8741 23:25:54.535054 Set Vref, RX VrefLevel [Byte0]: 70
8742 23:25:54.537451 [Byte1]: 70
8743 23:25:54.541736
8744 23:25:54.542288 Set Vref, RX VrefLevel [Byte0]: 71
8745 23:25:54.545119 [Byte1]: 71
8746 23:25:54.549731
8747 23:25:54.550284 Set Vref, RX VrefLevel [Byte0]: 72
8748 23:25:54.552374 [Byte1]: 72
8749 23:25:54.557387
8750 23:25:54.558029 Set Vref, RX VrefLevel [Byte0]: 73
8751 23:25:54.559769 [Byte1]: 73
8752 23:25:54.564116
8753 23:25:54.564622 Set Vref, RX VrefLevel [Byte0]: 74
8754 23:25:54.567546 [Byte1]: 74
8755 23:25:54.572057
8756 23:25:54.572617 Final RX Vref Byte 0 = 58 to rank0
8757 23:25:54.575220 Final RX Vref Byte 1 = 58 to rank0
8758 23:25:54.578656 Final RX Vref Byte 0 = 58 to rank1
8759 23:25:54.581834 Final RX Vref Byte 1 = 58 to rank1==
8760 23:25:54.585296 Dram Type= 6, Freq= 0, CH_1, rank 0
8761 23:25:54.591773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8762 23:25:54.592333 ==
8763 23:25:54.592847 DQS Delay:
8764 23:25:54.593290 DQS0 = 0, DQS1 = 0
8765 23:25:54.595288 DQM Delay:
8766 23:25:54.595756 DQM0 = 134, DQM1 = 131
8767 23:25:54.598142 DQ Delay:
8768 23:25:54.601503 DQ0 =140, DQ1 =130, DQ2 =124, DQ3 =130
8769 23:25:54.604999 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8770 23:25:54.608276 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =122
8771 23:25:54.611887 DQ12 =140, DQ13 =140, DQ14 =138, DQ15 =140
8772 23:25:54.612416
8773 23:25:54.612853
8774 23:25:54.613270
8775 23:25:54.615393 [DramC_TX_OE_Calibration] TA2
8776 23:25:54.618159 Original DQ_B0 (3 6) =30, OEN = 27
8777 23:25:54.621734 Original DQ_B1 (3 6) =30, OEN = 27
8778 23:25:54.625017 24, 0x0, End_B0=24 End_B1=24
8779 23:25:54.625450 25, 0x0, End_B0=25 End_B1=25
8780 23:25:54.628239 26, 0x0, End_B0=26 End_B1=26
8781 23:25:54.631586 27, 0x0, End_B0=27 End_B1=27
8782 23:25:54.634878 28, 0x0, End_B0=28 End_B1=28
8783 23:25:54.635311 29, 0x0, End_B0=29 End_B1=29
8784 23:25:54.638136 30, 0x0, End_B0=30 End_B1=30
8785 23:25:54.641773 31, 0x4141, End_B0=30 End_B1=30
8786 23:25:54.645322 Byte0 end_step=30 best_step=27
8787 23:25:54.648490 Byte1 end_step=30 best_step=27
8788 23:25:54.651999 Byte0 TX OE(2T, 0.5T) = (3, 3)
8789 23:25:54.652430 Byte1 TX OE(2T, 0.5T) = (3, 3)
8790 23:25:54.655191
8791 23:25:54.655719
8792 23:25:54.661462 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8793 23:25:54.665340 CH1 RK0: MR19=303, MR18=1422
8794 23:25:54.671447 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8795 23:25:54.671973
8796 23:25:54.675021 ----->DramcWriteLeveling(PI) begin...
8797 23:25:54.675555 ==
8798 23:25:54.678325 Dram Type= 6, Freq= 0, CH_1, rank 1
8799 23:25:54.681974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8800 23:25:54.682508 ==
8801 23:25:54.685026 Write leveling (Byte 0): 25 => 25
8802 23:25:54.688532 Write leveling (Byte 1): 28 => 28
8803 23:25:54.691804 DramcWriteLeveling(PI) end<-----
8804 23:25:54.692330
8805 23:25:54.692771 ==
8806 23:25:54.694959 Dram Type= 6, Freq= 0, CH_1, rank 1
8807 23:25:54.698780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8808 23:25:54.699312 ==
8809 23:25:54.701814 [Gating] SW mode calibration
8810 23:25:54.708092 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8811 23:25:54.715154 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8812 23:25:54.718513 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 23:25:54.721471 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8814 23:25:54.727996 1 4 8 | B1->B0 | 2e2e 2323 | 1 1 | (1 1) (1 1)
8815 23:25:54.731842 1 4 12 | B1->B0 | 3434 2f2e | 1 1 | (1 1) (0 0)
8816 23:25:54.734775 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 23:25:54.741664 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 23:25:54.745050 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 23:25:54.747665 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 23:25:54.755097 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8821 23:25:54.758164 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8822 23:25:54.761008 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (0 1) (1 0)
8823 23:25:54.768135 1 5 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 1)
8824 23:25:54.771062 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 23:25:54.774725 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 23:25:54.781457 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 23:25:54.784388 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 23:25:54.787441 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 23:25:54.794040 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8830 23:25:54.797208 1 6 8 | B1->B0 | 3636 2323 | 0 0 | (0 0) (0 0)
8831 23:25:54.800702 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (1 1)
8832 23:25:54.807712 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 23:25:54.811096 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 23:25:54.814203 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 23:25:54.821003 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 23:25:54.824303 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 23:25:54.827563 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8838 23:25:54.834078 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8839 23:25:54.837396 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8840 23:25:54.841285 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8841 23:25:54.844285 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 23:25:54.851026 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 23:25:54.853793 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 23:25:54.857492 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 23:25:54.864348 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 23:25:54.867048 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 23:25:54.870855 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 23:25:54.877228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 23:25:54.881038 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 23:25:54.884325 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 23:25:54.890340 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 23:25:54.893914 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8853 23:25:54.897502 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8854 23:25:54.904038 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8855 23:25:54.907284 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8856 23:25:54.910803 Total UI for P1: 0, mck2ui 16
8857 23:25:54.914186 best dqsien dly found for B1: ( 1, 9, 8)
8858 23:25:54.917118 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 23:25:54.920469 Total UI for P1: 0, mck2ui 16
8860 23:25:54.924216 best dqsien dly found for B0: ( 1, 9, 12)
8861 23:25:54.926960 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8862 23:25:54.930562 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8863 23:25:54.931116
8864 23:25:54.936848 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8865 23:25:54.940226 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8866 23:25:54.943500 [Gating] SW calibration Done
8867 23:25:54.944077 ==
8868 23:25:54.946792 Dram Type= 6, Freq= 0, CH_1, rank 1
8869 23:25:54.950425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8870 23:25:54.951056 ==
8871 23:25:54.951420 RX Vref Scan: 0
8872 23:25:54.951751
8873 23:25:54.953860 RX Vref 0 -> 0, step: 1
8874 23:25:54.954421
8875 23:25:54.957155 RX Delay 0 -> 252, step: 8
8876 23:25:54.960619 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8877 23:25:54.963526 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8878 23:25:54.970246 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8879 23:25:54.973217 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8880 23:25:54.976294 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8881 23:25:54.980125 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8882 23:25:54.983088 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8883 23:25:54.989908 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8884 23:25:54.992934 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8885 23:25:54.996409 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8886 23:25:55.000198 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8887 23:25:55.003066 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8888 23:25:55.009918 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8889 23:25:55.013333 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8890 23:25:55.016123 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8891 23:25:55.019793 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8892 23:25:55.020347 ==
8893 23:25:55.023027 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 23:25:55.029439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 23:25:55.029898 ==
8896 23:25:55.030229 DQS Delay:
8897 23:25:55.030532 DQS0 = 0, DQS1 = 0
8898 23:25:55.033108 DQM Delay:
8899 23:25:55.033711 DQM0 = 135, DQM1 = 133
8900 23:25:55.036902 DQ Delay:
8901 23:25:55.039827 DQ0 =139, DQ1 =135, DQ2 =119, DQ3 =131
8902 23:25:55.043405 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8903 23:25:55.046595 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8904 23:25:55.049554 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8905 23:25:55.050168
8906 23:25:55.050636
8907 23:25:55.051074 ==
8908 23:25:55.052937 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 23:25:55.056414 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 23:25:55.059770 ==
8911 23:25:55.060399
8912 23:25:55.060763
8913 23:25:55.061097 TX Vref Scan disable
8914 23:25:55.062574 == TX Byte 0 ==
8915 23:25:55.066324 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8916 23:25:55.069763 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8917 23:25:55.073263 == TX Byte 1 ==
8918 23:25:55.076164 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8919 23:25:55.080049 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8920 23:25:55.080755 ==
8921 23:25:55.082579 Dram Type= 6, Freq= 0, CH_1, rank 1
8922 23:25:55.089628 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8923 23:25:55.090188 ==
8924 23:25:55.102848
8925 23:25:55.105372 TX Vref early break, caculate TX vref
8926 23:25:55.108712 TX Vref=16, minBit 0, minWin=23, winSum=385
8927 23:25:55.111986 TX Vref=18, minBit 0, minWin=23, winSum=391
8928 23:25:55.115530 TX Vref=20, minBit 1, minWin=24, winSum=401
8929 23:25:55.118432 TX Vref=22, minBit 6, minWin=24, winSum=409
8930 23:25:55.122101 TX Vref=24, minBit 0, minWin=25, winSum=422
8931 23:25:55.128434 TX Vref=26, minBit 0, minWin=26, winSum=427
8932 23:25:55.132173 TX Vref=28, minBit 0, minWin=25, winSum=426
8933 23:25:55.135307 TX Vref=30, minBit 0, minWin=25, winSum=425
8934 23:25:55.138522 TX Vref=32, minBit 0, minWin=25, winSum=412
8935 23:25:55.141717 TX Vref=34, minBit 0, minWin=24, winSum=405
8936 23:25:55.145165 TX Vref=36, minBit 0, minWin=23, winSum=397
8937 23:25:55.151853 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 26
8938 23:25:55.152392
8939 23:25:55.155131 Final TX Range 0 Vref 26
8940 23:25:55.155591
8941 23:25:55.155947 ==
8942 23:25:55.158695 Dram Type= 6, Freq= 0, CH_1, rank 1
8943 23:25:55.162228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8944 23:25:55.162865 ==
8945 23:25:55.163235
8946 23:25:55.164906
8947 23:25:55.165362 TX Vref Scan disable
8948 23:25:55.172052 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8949 23:25:55.172639 == TX Byte 0 ==
8950 23:25:55.175128 u2DelayCellOfst[0]=16 cells (5 PI)
8951 23:25:55.178502 u2DelayCellOfst[1]=10 cells (3 PI)
8952 23:25:55.182263 u2DelayCellOfst[2]=0 cells (0 PI)
8953 23:25:55.185271 u2DelayCellOfst[3]=6 cells (2 PI)
8954 23:25:55.188549 u2DelayCellOfst[4]=6 cells (2 PI)
8955 23:25:55.191704 u2DelayCellOfst[5]=16 cells (5 PI)
8956 23:25:55.194999 u2DelayCellOfst[6]=16 cells (5 PI)
8957 23:25:55.198144 u2DelayCellOfst[7]=6 cells (2 PI)
8958 23:25:55.202025 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8959 23:25:55.205315 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8960 23:25:55.208597 == TX Byte 1 ==
8961 23:25:55.211941 u2DelayCellOfst[8]=0 cells (0 PI)
8962 23:25:55.212406 u2DelayCellOfst[9]=3 cells (1 PI)
8963 23:25:55.215476 u2DelayCellOfst[10]=10 cells (3 PI)
8964 23:25:55.218221 u2DelayCellOfst[11]=3 cells (1 PI)
8965 23:25:55.222029 u2DelayCellOfst[12]=13 cells (4 PI)
8966 23:25:55.225434 u2DelayCellOfst[13]=13 cells (4 PI)
8967 23:25:55.228148 u2DelayCellOfst[14]=16 cells (5 PI)
8968 23:25:55.231706 u2DelayCellOfst[15]=16 cells (5 PI)
8969 23:25:55.235282 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8970 23:25:55.241401 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8971 23:25:55.241906 DramC Write-DBI on
8972 23:25:55.242271 ==
8973 23:25:55.245113 Dram Type= 6, Freq= 0, CH_1, rank 1
8974 23:25:55.251235 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8975 23:25:55.251791 ==
8976 23:25:55.252158
8977 23:25:55.252493
8978 23:25:55.252808 TX Vref Scan disable
8979 23:25:55.255365 == TX Byte 0 ==
8980 23:25:55.258709 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8981 23:25:55.262083 == TX Byte 1 ==
8982 23:25:55.265400 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8983 23:25:55.268966 DramC Write-DBI off
8984 23:25:55.269516
8985 23:25:55.269942 [DATLAT]
8986 23:25:55.270279 Freq=1600, CH1 RK1
8987 23:25:55.270600
8988 23:25:55.272503 DATLAT Default: 0xf
8989 23:25:55.273058 0, 0xFFFF, sum = 0
8990 23:25:55.275385 1, 0xFFFF, sum = 0
8991 23:25:55.275948 2, 0xFFFF, sum = 0
8992 23:25:55.278933 3, 0xFFFF, sum = 0
8993 23:25:55.282127 4, 0xFFFF, sum = 0
8994 23:25:55.282688 5, 0xFFFF, sum = 0
8995 23:25:55.285734 6, 0xFFFF, sum = 0
8996 23:25:55.286307 7, 0xFFFF, sum = 0
8997 23:25:55.288577 8, 0xFFFF, sum = 0
8998 23:25:55.289043 9, 0xFFFF, sum = 0
8999 23:25:55.292054 10, 0xFFFF, sum = 0
9000 23:25:55.292522 11, 0xFFFF, sum = 0
9001 23:25:55.295204 12, 0xFFFF, sum = 0
9002 23:25:55.295672 13, 0xFFFF, sum = 0
9003 23:25:55.298871 14, 0x0, sum = 1
9004 23:25:55.299338 15, 0x0, sum = 2
9005 23:25:55.301749 16, 0x0, sum = 3
9006 23:25:55.302215 17, 0x0, sum = 4
9007 23:25:55.304760 best_step = 15
9008 23:25:55.305215
9009 23:25:55.305568 ==
9010 23:25:55.308476 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 23:25:55.311919 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 23:25:55.312339 ==
9013 23:25:55.314659 RX Vref Scan: 0
9014 23:25:55.315076
9015 23:25:55.315402 RX Vref 0 -> 0, step: 1
9016 23:25:55.315706
9017 23:25:55.318474 RX Delay 19 -> 252, step: 4
9018 23:25:55.321630 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9019 23:25:55.328343 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
9020 23:25:55.331417 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9021 23:25:55.334862 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9022 23:25:55.338336 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9023 23:25:55.341541 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9024 23:25:55.345254 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9025 23:25:55.351384 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9026 23:25:55.354768 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9027 23:25:55.358654 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9028 23:25:55.361717 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9029 23:25:55.368061 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9030 23:25:55.371481 iDelay=195, Bit 12, Center 142 (91 ~ 194) 104
9031 23:25:55.374892 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9032 23:25:55.378224 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9033 23:25:55.381909 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9034 23:25:55.382421 ==
9035 23:25:55.384933 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 23:25:55.391389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 23:25:55.391813 ==
9038 23:25:55.392140 DQS Delay:
9039 23:25:55.394418 DQS0 = 0, DQS1 = 0
9040 23:25:55.394835 DQM Delay:
9041 23:25:55.398288 DQM0 = 134, DQM1 = 131
9042 23:25:55.398706 DQ Delay:
9043 23:25:55.401017 DQ0 =138, DQ1 =130, DQ2 =122, DQ3 =130
9044 23:25:55.404621 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9045 23:25:55.407909 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9046 23:25:55.411571 DQ12 =142, DQ13 =138, DQ14 =136, DQ15 =140
9047 23:25:55.411999
9048 23:25:55.412322
9049 23:25:55.412620
9050 23:25:55.414496 [DramC_TX_OE_Calibration] TA2
9051 23:25:55.417880 Original DQ_B0 (3 6) =30, OEN = 27
9052 23:25:55.421262 Original DQ_B1 (3 6) =30, OEN = 27
9053 23:25:55.424666 24, 0x0, End_B0=24 End_B1=24
9054 23:25:55.427704 25, 0x0, End_B0=25 End_B1=25
9055 23:25:55.428214 26, 0x0, End_B0=26 End_B1=26
9056 23:25:55.431592 27, 0x0, End_B0=27 End_B1=27
9057 23:25:55.434689 28, 0x0, End_B0=28 End_B1=28
9058 23:25:55.438032 29, 0x0, End_B0=29 End_B1=29
9059 23:25:55.440901 30, 0x0, End_B0=30 End_B1=30
9060 23:25:55.441376 31, 0x4141, End_B0=30 End_B1=30
9061 23:25:55.444508 Byte0 end_step=30 best_step=27
9062 23:25:55.447940 Byte1 end_step=30 best_step=27
9063 23:25:55.451080 Byte0 TX OE(2T, 0.5T) = (3, 3)
9064 23:25:55.454744 Byte1 TX OE(2T, 0.5T) = (3, 3)
9065 23:25:55.455305
9066 23:25:55.455661
9067 23:25:55.461170 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9068 23:25:55.463889 CH1 RK1: MR19=303, MR18=2309
9069 23:25:55.470890 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9070 23:25:55.474228 [RxdqsGatingPostProcess] freq 1600
9071 23:25:55.480855 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9072 23:25:55.481411 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 23:25:55.484190 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 23:25:55.487354 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 23:25:55.490592 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 23:25:55.494104 best DQS0 dly(2T, 0.5T) = (1, 1)
9077 23:25:55.497632 best DQS1 dly(2T, 0.5T) = (1, 1)
9078 23:25:55.500589 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9079 23:25:55.504227 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9080 23:25:55.507099 Pre-setting of DQS Precalculation
9081 23:25:55.510484 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9082 23:25:55.520723 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9083 23:25:55.527274 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9084 23:25:55.527814
9085 23:25:55.528174
9086 23:25:55.530420 [Calibration Summary] 3200 Mbps
9087 23:25:55.530883 CH 0, Rank 0
9088 23:25:55.533676 SW Impedance : PASS
9089 23:25:55.534233 DUTY Scan : NO K
9090 23:25:55.537265 ZQ Calibration : PASS
9091 23:25:55.541116 Jitter Meter : NO K
9092 23:25:55.541716 CBT Training : PASS
9093 23:25:55.543840 Write leveling : PASS
9094 23:25:55.547594 RX DQS gating : PASS
9095 23:25:55.548149 RX DQ/DQS(RDDQC) : PASS
9096 23:25:55.550476 TX DQ/DQS : PASS
9097 23:25:55.553832 RX DATLAT : PASS
9098 23:25:55.554383 RX DQ/DQS(Engine): PASS
9099 23:25:55.557344 TX OE : PASS
9100 23:25:55.557938 All Pass.
9101 23:25:55.558301
9102 23:25:55.559999 CH 0, Rank 1
9103 23:25:55.560460 SW Impedance : PASS
9104 23:25:55.563477 DUTY Scan : NO K
9105 23:25:55.563941 ZQ Calibration : PASS
9106 23:25:55.567496 Jitter Meter : NO K
9107 23:25:55.570403 CBT Training : PASS
9108 23:25:55.570965 Write leveling : PASS
9109 23:25:55.573857 RX DQS gating : PASS
9110 23:25:55.577313 RX DQ/DQS(RDDQC) : PASS
9111 23:25:55.577921 TX DQ/DQS : PASS
9112 23:25:55.580415 RX DATLAT : PASS
9113 23:25:55.583754 RX DQ/DQS(Engine): PASS
9114 23:25:55.584316 TX OE : PASS
9115 23:25:55.587717 All Pass.
9116 23:25:55.588288
9117 23:25:55.588650 CH 1, Rank 0
9118 23:25:55.590203 SW Impedance : PASS
9119 23:25:55.590662 DUTY Scan : NO K
9120 23:25:55.593748 ZQ Calibration : PASS
9121 23:25:55.596891 Jitter Meter : NO K
9122 23:25:55.597364 CBT Training : PASS
9123 23:25:55.600514 Write leveling : PASS
9124 23:25:55.603450 RX DQS gating : PASS
9125 23:25:55.604008 RX DQ/DQS(RDDQC) : PASS
9126 23:25:55.607405 TX DQ/DQS : PASS
9127 23:25:55.610071 RX DATLAT : PASS
9128 23:25:55.610530 RX DQ/DQS(Engine): PASS
9129 23:25:55.613067 TX OE : PASS
9130 23:25:55.613526 All Pass.
9131 23:25:55.613944
9132 23:25:55.616739 CH 1, Rank 1
9133 23:25:55.617201 SW Impedance : PASS
9134 23:25:55.620285 DUTY Scan : NO K
9135 23:25:55.620746 ZQ Calibration : PASS
9136 23:25:55.623654 Jitter Meter : NO K
9137 23:25:55.626614 CBT Training : PASS
9138 23:25:55.627031 Write leveling : PASS
9139 23:25:55.630224 RX DQS gating : PASS
9140 23:25:55.633358 RX DQ/DQS(RDDQC) : PASS
9141 23:25:55.633923 TX DQ/DQS : PASS
9142 23:25:55.636622 RX DATLAT : PASS
9143 23:25:55.639970 RX DQ/DQS(Engine): PASS
9144 23:25:55.640393 TX OE : PASS
9145 23:25:55.643532 All Pass.
9146 23:25:55.644038
9147 23:25:55.644367 DramC Write-DBI on
9148 23:25:55.647105 PER_BANK_REFRESH: Hybrid Mode
9149 23:25:55.647637 TX_TRACKING: ON
9150 23:25:55.656833 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9151 23:25:55.663552 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9152 23:25:55.673393 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9153 23:25:55.676988 [FAST_K] Save calibration result to emmc
9154 23:25:55.680265 sync common calibartion params.
9155 23:25:55.680819 sync cbt_mode0:1, 1:1
9156 23:25:55.683428 dram_init: ddr_geometry: 2
9157 23:25:55.686794 dram_init: ddr_geometry: 2
9158 23:25:55.687347 dram_init: ddr_geometry: 2
9159 23:25:55.689832 0:dram_rank_size:100000000
9160 23:25:55.693377 1:dram_rank_size:100000000
9161 23:25:55.696782 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9162 23:25:55.699787 DFS_SHUFFLE_HW_MODE: ON
9163 23:25:55.703600 dramc_set_vcore_voltage set vcore to 725000
9164 23:25:55.706931 Read voltage for 1600, 0
9165 23:25:55.707484 Vio18 = 0
9166 23:25:55.709869 Vcore = 725000
9167 23:25:55.710421 Vdram = 0
9168 23:25:55.710801 Vddq = 0
9169 23:25:55.713721 Vmddr = 0
9170 23:25:55.714283 switch to 3200 Mbps bootup
9171 23:25:55.716731 [DramcRunTimeConfig]
9172 23:25:55.717334 PHYPLL
9173 23:25:55.719649 DPM_CONTROL_AFTERK: ON
9174 23:25:55.720104 PER_BANK_REFRESH: ON
9175 23:25:55.723653 REFRESH_OVERHEAD_REDUCTION: ON
9176 23:25:55.726667 CMD_PICG_NEW_MODE: OFF
9177 23:25:55.727346 XRTWTW_NEW_MODE: ON
9178 23:25:55.729783 XRTRTR_NEW_MODE: ON
9179 23:25:55.730377 TX_TRACKING: ON
9180 23:25:55.733466 RDSEL_TRACKING: OFF
9181 23:25:55.736777 DQS Precalculation for DVFS: ON
9182 23:25:55.737326 RX_TRACKING: OFF
9183 23:25:55.739882 HW_GATING DBG: ON
9184 23:25:55.740355 ZQCS_ENABLE_LP4: ON
9185 23:25:55.743035 RX_PICG_NEW_MODE: ON
9186 23:25:55.743569 TX_PICG_NEW_MODE: ON
9187 23:25:55.746383 ENABLE_RX_DCM_DPHY: ON
9188 23:25:55.750058 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9189 23:25:55.752940 DUMMY_READ_FOR_TRACKING: OFF
9190 23:25:55.753396 !!! SPM_CONTROL_AFTERK: OFF
9191 23:25:55.756354 !!! SPM could not control APHY
9192 23:25:55.759665 IMPEDANCE_TRACKING: ON
9193 23:25:55.760123 TEMP_SENSOR: ON
9194 23:25:55.763164 HW_SAVE_FOR_SR: OFF
9195 23:25:55.766794 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9196 23:25:55.770061 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9197 23:25:55.770621 Read ODT Tracking: ON
9198 23:25:55.773184 Refresh Rate DeBounce: ON
9199 23:25:55.776648 DFS_NO_QUEUE_FLUSH: ON
9200 23:25:55.779973 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9201 23:25:55.780538 ENABLE_DFS_RUNTIME_MRW: OFF
9202 23:25:55.783317 DDR_RESERVE_NEW_MODE: ON
9203 23:25:55.786636 MR_CBT_SWITCH_FREQ: ON
9204 23:25:55.787194 =========================
9205 23:25:55.807015 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9206 23:25:55.809863 dram_init: ddr_geometry: 2
9207 23:25:55.828348 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9208 23:25:55.831498 dram_init: dram init end (result: 0)
9209 23:25:55.838170 DRAM-K: Full calibration passed in 24481 msecs
9210 23:25:55.842006 MRC: failed to locate region type 0.
9211 23:25:55.842467 DRAM rank0 size:0x100000000,
9212 23:25:55.845023 DRAM rank1 size=0x100000000
9213 23:25:55.855101 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9214 23:25:55.861968 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9215 23:25:55.868423 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9216 23:25:55.875221 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9217 23:25:55.878596 DRAM rank0 size:0x100000000,
9218 23:25:55.881807 DRAM rank1 size=0x100000000
9219 23:25:55.882359 CBMEM:
9220 23:25:55.885345 IMD: root @ 0xfffff000 254 entries.
9221 23:25:55.888577 IMD: root @ 0xffffec00 62 entries.
9222 23:25:55.891628 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9223 23:25:55.894561 WARNING: RO_VPD is uninitialized or empty.
9224 23:25:55.901744 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9225 23:25:55.908055 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9226 23:25:55.920912 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9227 23:25:55.932498 BS: romstage times (exec / console): total (unknown) / 24010 ms
9228 23:25:55.933060
9229 23:25:55.933420
9230 23:25:55.942019 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9231 23:25:55.946121 ARM64: Exception handlers installed.
9232 23:25:55.949431 ARM64: Testing exception
9233 23:25:55.951964 ARM64: Done test exception
9234 23:25:55.952425 Enumerating buses...
9235 23:25:55.955927 Show all devs... Before device enumeration.
9236 23:25:55.958616 Root Device: enabled 1
9237 23:25:55.961915 CPU_CLUSTER: 0: enabled 1
9238 23:25:55.962374 CPU: 00: enabled 1
9239 23:25:55.965892 Compare with tree...
9240 23:25:55.966349 Root Device: enabled 1
9241 23:25:55.969335 CPU_CLUSTER: 0: enabled 1
9242 23:25:55.972387 CPU: 00: enabled 1
9243 23:25:55.972958 Root Device scanning...
9244 23:25:55.975418 scan_static_bus for Root Device
9245 23:25:55.978896 CPU_CLUSTER: 0 enabled
9246 23:25:55.982466 scan_static_bus for Root Device done
9247 23:25:55.985459 scan_bus: bus Root Device finished in 8 msecs
9248 23:25:55.986065 done
9249 23:25:55.991926 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9250 23:25:55.995192 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9251 23:25:56.002073 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9252 23:25:56.005236 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9253 23:25:56.008732 Allocating resources...
9254 23:25:56.012579 Reading resources...
9255 23:25:56.015469 Root Device read_resources bus 0 link: 0
9256 23:25:56.015932 DRAM rank0 size:0x100000000,
9257 23:25:56.018877 DRAM rank1 size=0x100000000
9258 23:25:56.021678 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9259 23:25:56.025438 CPU: 00 missing read_resources
9260 23:25:56.028661 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9261 23:25:56.035478 Root Device read_resources bus 0 link: 0 done
9262 23:25:56.036039 Done reading resources.
9263 23:25:56.041508 Show resources in subtree (Root Device)...After reading.
9264 23:25:56.045655 Root Device child on link 0 CPU_CLUSTER: 0
9265 23:25:56.048800 CPU_CLUSTER: 0 child on link 0 CPU: 00
9266 23:25:56.058183 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9267 23:25:56.058737 CPU: 00
9268 23:25:56.062007 Root Device assign_resources, bus 0 link: 0
9269 23:25:56.064960 CPU_CLUSTER: 0 missing set_resources
9270 23:25:56.068474 Root Device assign_resources, bus 0 link: 0 done
9271 23:25:56.072232 Done setting resources.
9272 23:25:56.078538 Show resources in subtree (Root Device)...After assigning values.
9273 23:25:56.082078 Root Device child on link 0 CPU_CLUSTER: 0
9274 23:25:56.084961 CPU_CLUSTER: 0 child on link 0 CPU: 00
9275 23:25:56.095312 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9276 23:25:56.095858 CPU: 00
9277 23:25:56.098087 Done allocating resources.
9278 23:25:56.101650 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9279 23:25:56.105035 Enabling resources...
9280 23:25:56.105630 done.
9281 23:25:56.112151 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9282 23:25:56.112705 Initializing devices...
9283 23:25:56.114850 Root Device init
9284 23:25:56.115311 init hardware done!
9285 23:25:56.118309 0x00000018: ctrlr->caps
9286 23:25:56.121693 52.000 MHz: ctrlr->f_max
9287 23:25:56.122254 0.400 MHz: ctrlr->f_min
9288 23:25:56.125212 0x40ff8080: ctrlr->voltages
9289 23:25:56.125822 sclk: 390625
9290 23:25:56.128677 Bus Width = 1
9291 23:25:56.129132 sclk: 390625
9292 23:25:56.129489 Bus Width = 1
9293 23:25:56.132097 Early init status = 3
9294 23:25:56.138147 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9295 23:25:56.141721 in-header: 03 fc 00 00 01 00 00 00
9296 23:25:56.142277 in-data: 00
9297 23:25:56.148929 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9298 23:25:56.152962 in-header: 03 fd 00 00 00 00 00 00
9299 23:25:56.156874 in-data:
9300 23:25:56.159809 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9301 23:25:56.164072 in-header: 03 fc 00 00 01 00 00 00
9302 23:25:56.167530 in-data: 00
9303 23:25:56.170724 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9304 23:25:56.176103 in-header: 03 fd 00 00 00 00 00 00
9305 23:25:56.179487 in-data:
9306 23:25:56.182793 [SSUSB] Setting up USB HOST controller...
9307 23:25:56.186159 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9308 23:25:56.189149 [SSUSB] phy power-on done.
9309 23:25:56.192562 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9310 23:25:56.199039 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9311 23:25:56.202565 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9312 23:25:56.209199 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9313 23:25:56.215741 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9314 23:25:56.222464 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9315 23:25:56.229021 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9316 23:25:56.235673 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9317 23:25:56.239046 SPM: binary array size = 0x9dc
9318 23:25:56.242628 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9319 23:25:56.249097 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9320 23:25:56.255533 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9321 23:25:56.259210 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9322 23:25:56.265187 configure_display: Starting display init
9323 23:25:56.299426 anx7625_power_on_init: Init interface.
9324 23:25:56.302507 anx7625_disable_pd_protocol: Disabled PD feature.
9325 23:25:56.306001 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9326 23:25:56.334034 anx7625_start_dp_work: Secure OCM version=00
9327 23:25:56.337610 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9328 23:25:56.351782 sp_tx_get_edid_block: EDID Block = 1
9329 23:25:56.454172 Extracted contents:
9330 23:25:56.457511 header: 00 ff ff ff ff ff ff 00
9331 23:25:56.461008 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9332 23:25:56.464293 version: 01 04
9333 23:25:56.467271 basic params: 95 1f 11 78 0a
9334 23:25:56.471013 chroma info: 76 90 94 55 54 90 27 21 50 54
9335 23:25:56.474062 established: 00 00 00
9336 23:25:56.481443 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9337 23:25:56.484749 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9338 23:25:56.490620 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9339 23:25:56.497343 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9340 23:25:56.504329 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9341 23:25:56.507039 extensions: 00
9342 23:25:56.507499 checksum: fb
9343 23:25:56.507859
9344 23:25:56.510469 Manufacturer: IVO Model 57d Serial Number 0
9345 23:25:56.514228 Made week 0 of 2020
9346 23:25:56.516770 EDID version: 1.4
9347 23:25:56.517226 Digital display
9348 23:25:56.520461 6 bits per primary color channel
9349 23:25:56.521022 DisplayPort interface
9350 23:25:56.523755 Maximum image size: 31 cm x 17 cm
9351 23:25:56.527450 Gamma: 220%
9352 23:25:56.528003 Check DPMS levels
9353 23:25:56.533626 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9354 23:25:56.537249 First detailed timing is preferred timing
9355 23:25:56.537854 Established timings supported:
9356 23:25:56.540087 Standard timings supported:
9357 23:25:56.542997 Detailed timings
9358 23:25:56.546878 Hex of detail: 383680a07038204018303c0035ae10000019
9359 23:25:56.552968 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9360 23:25:56.556543 0780 0798 07c8 0820 hborder 0
9361 23:25:56.559542 0438 043b 0447 0458 vborder 0
9362 23:25:56.562937 -hsync -vsync
9363 23:25:56.563369 Did detailed timing
9364 23:25:56.570043 Hex of detail: 000000000000000000000000000000000000
9365 23:25:56.573009 Manufacturer-specified data, tag 0
9366 23:25:56.576395 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9367 23:25:56.580092 ASCII string: InfoVision
9368 23:25:56.583126 Hex of detail: 000000fe00523134304e574635205248200a
9369 23:25:56.586575 ASCII string: R140NWF5 RH
9370 23:25:56.586989 Checksum
9371 23:25:56.589647 Checksum: 0xfb (valid)
9372 23:25:56.592900 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9373 23:25:56.596144 DSI data_rate: 832800000 bps
9374 23:25:56.603008 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9375 23:25:56.605971 anx7625_parse_edid: pixelclock(138800).
9376 23:25:56.609764 hactive(1920), hsync(48), hfp(24), hbp(88)
9377 23:25:56.613378 vactive(1080), vsync(12), vfp(3), vbp(17)
9378 23:25:56.616658 anx7625_dsi_config: config dsi.
9379 23:25:56.622971 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9380 23:25:56.637053 anx7625_dsi_config: success to config DSI
9381 23:25:56.639661 anx7625_dp_start: MIPI phy setup OK.
9382 23:25:56.642862 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9383 23:25:56.646543 mtk_ddp_mode_set invalid vrefresh 60
9384 23:25:56.649997 main_disp_path_setup
9385 23:25:56.650593 ovl_layer_smi_id_en
9386 23:25:56.652985 ovl_layer_smi_id_en
9387 23:25:56.653532 ccorr_config
9388 23:25:56.653942 aal_config
9389 23:25:56.656565 gamma_config
9390 23:25:56.657245 postmask_config
9391 23:25:56.659607 dither_config
9392 23:25:56.662823 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9393 23:25:56.669368 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9394 23:25:56.673046 Root Device init finished in 555 msecs
9395 23:25:56.676437 CPU_CLUSTER: 0 init
9396 23:25:56.682801 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9397 23:25:56.686392 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9398 23:25:56.689194 APU_MBOX 0x190000b0 = 0x10001
9399 23:25:56.693188 APU_MBOX 0x190001b0 = 0x10001
9400 23:25:56.695980 APU_MBOX 0x190005b0 = 0x10001
9401 23:25:56.699344 APU_MBOX 0x190006b0 = 0x10001
9402 23:25:56.703191 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9403 23:25:56.715746 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9404 23:25:56.728045 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9405 23:25:56.734474 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9406 23:25:56.746189 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9407 23:25:56.755120 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9408 23:25:56.758368 CPU_CLUSTER: 0 init finished in 81 msecs
9409 23:25:56.761872 Devices initialized
9410 23:25:56.765285 Show all devs... After init.
9411 23:25:56.766106 Root Device: enabled 1
9412 23:25:56.768592 CPU_CLUSTER: 0: enabled 1
9413 23:25:56.772168 CPU: 00: enabled 1
9414 23:25:56.774875 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9415 23:25:56.778465 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9416 23:25:56.781740 ELOG: NV offset 0x57f000 size 0x1000
9417 23:25:56.788020 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9418 23:25:56.795118 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9419 23:25:56.798155 ELOG: Event(17) added with size 13 at 2023-12-03 23:23:42 UTC
9420 23:25:56.804741 out: cmd=0x121: 03 db 21 01 00 00 00 00
9421 23:25:56.808260 in-header: 03 c0 00 00 2c 00 00 00
9422 23:25:56.818059 in-data: 9f 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9423 23:25:56.825069 ELOG: Event(A1) added with size 10 at 2023-12-03 23:23:42 UTC
9424 23:25:56.831474 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9425 23:25:56.838200 ELOG: Event(A0) added with size 9 at 2023-12-03 23:23:42 UTC
9426 23:25:56.841361 elog_add_boot_reason: Logged dev mode boot
9427 23:25:56.847651 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9428 23:25:56.848210 Finalize devices...
9429 23:25:56.851354 Devices finalized
9430 23:25:56.854384 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9431 23:25:56.857529 Writing coreboot table at 0xffe64000
9432 23:25:56.861186 0. 000000000010a000-0000000000113fff: RAMSTAGE
9433 23:25:56.864780 1. 0000000040000000-00000000400fffff: RAM
9434 23:25:56.871588 2. 0000000040100000-000000004032afff: RAMSTAGE
9435 23:25:56.874304 3. 000000004032b000-00000000545fffff: RAM
9436 23:25:56.877768 4. 0000000054600000-000000005465ffff: BL31
9437 23:25:56.881159 5. 0000000054660000-00000000ffe63fff: RAM
9438 23:25:56.887650 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9439 23:25:56.890764 7. 0000000100000000-000000023fffffff: RAM
9440 23:25:56.894157 Passing 5 GPIOs to payload:
9441 23:25:56.897424 NAME | PORT | POLARITY | VALUE
9442 23:25:56.904182 EC in RW | 0x000000aa | low | undefined
9443 23:25:56.907480 EC interrupt | 0x00000005 | low | undefined
9444 23:25:56.910869 TPM interrupt | 0x000000ab | high | undefined
9445 23:25:56.917677 SD card detect | 0x00000011 | high | undefined
9446 23:25:56.920609 speaker enable | 0x00000093 | high | undefined
9447 23:25:56.924184 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9448 23:25:56.927194 in-header: 03 f9 00 00 02 00 00 00
9449 23:25:56.930848 in-data: 02 00
9450 23:25:56.934254 ADC[4]: Raw value=904357 ID=7
9451 23:25:56.934713 ADC[3]: Raw value=213441 ID=1
9452 23:25:56.937433 RAM Code: 0x71
9453 23:25:56.940760 ADC[6]: Raw value=75701 ID=0
9454 23:25:56.941310 ADC[5]: Raw value=213072 ID=1
9455 23:25:56.944028 SKU Code: 0x1
9456 23:25:56.947759 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9457 23:25:56.950756 coreboot table: 964 bytes.
9458 23:25:56.953980 IMD ROOT 0. 0xfffff000 0x00001000
9459 23:25:56.957528 IMD SMALL 1. 0xffffe000 0x00001000
9460 23:25:56.960334 RO MCACHE 2. 0xffffc000 0x00001104
9461 23:25:56.963963 CONSOLE 3. 0xfff7c000 0x00080000
9462 23:25:56.967237 FMAP 4. 0xfff7b000 0x00000452
9463 23:25:56.970554 TIME STAMP 5. 0xfff7a000 0x00000910
9464 23:25:56.974010 VBOOT WORK 6. 0xfff66000 0x00014000
9465 23:25:56.977008 RAMOOPS 7. 0xffe66000 0x00100000
9466 23:25:56.980433 COREBOOT 8. 0xffe64000 0x00002000
9467 23:25:56.984014 IMD small region:
9468 23:25:56.987182 IMD ROOT 0. 0xffffec00 0x00000400
9469 23:25:56.990573 VPD 1. 0xffffeb80 0x0000006c
9470 23:25:56.994117 MMC STATUS 2. 0xffffeb60 0x00000004
9471 23:25:56.997259 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9472 23:25:57.000062 Probing TPM: done!
9473 23:25:57.004197 Connected to device vid:did:rid of 1ae0:0028:00
9474 23:25:57.014834 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9475 23:25:57.017487 Initialized TPM device CR50 revision 0
9476 23:25:57.021268 Checking cr50 for pending updates
9477 23:25:57.025432 Reading cr50 TPM mode
9478 23:25:57.033810 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9479 23:25:57.040075 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9480 23:25:57.080732 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9481 23:25:57.083938 Checking segment from ROM address 0x40100000
9482 23:25:57.086998 Checking segment from ROM address 0x4010001c
9483 23:25:57.093894 Loading segment from ROM address 0x40100000
9484 23:25:57.094450 code (compression=0)
9485 23:25:57.103952 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9486 23:25:57.110322 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9487 23:25:57.110878 it's not compressed!
9488 23:25:57.117184 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9489 23:25:57.120383 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9490 23:25:57.140901 Loading segment from ROM address 0x4010001c
9491 23:25:57.141464 Entry Point 0x80000000
9492 23:25:57.144200 Loaded segments
9493 23:25:57.148268 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9494 23:25:57.154617 Jumping to boot code at 0x80000000(0xffe64000)
9495 23:25:57.160666 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9496 23:25:57.167783 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9497 23:25:57.175380 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9498 23:25:57.178509 Checking segment from ROM address 0x40100000
9499 23:25:57.182067 Checking segment from ROM address 0x4010001c
9500 23:25:57.188979 Loading segment from ROM address 0x40100000
9501 23:25:57.189541 code (compression=1)
9502 23:25:57.195273 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9503 23:25:57.205361 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9504 23:25:57.205971 using LZMA
9505 23:25:57.213677 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9506 23:25:57.220574 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9507 23:25:57.223601 Loading segment from ROM address 0x4010001c
9508 23:25:57.224064 Entry Point 0x54601000
9509 23:25:57.227483 Loaded segments
9510 23:25:57.230180 NOTICE: MT8192 bl31_setup
9511 23:25:57.236912 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9512 23:25:57.240803 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9513 23:25:57.243842 WARNING: region 0:
9514 23:25:57.247070 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9515 23:25:57.247628 WARNING: region 1:
9516 23:25:57.254183 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9517 23:25:57.257185 WARNING: region 2:
9518 23:25:57.260501 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9519 23:25:57.264045 WARNING: region 3:
9520 23:25:57.267172 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 23:25:57.270446 WARNING: region 4:
9522 23:25:57.277527 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9523 23:25:57.278291 WARNING: region 5:
9524 23:25:57.280699 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 23:25:57.284415 WARNING: region 6:
9526 23:25:57.287501 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 23:25:57.288256 WARNING: region 7:
9528 23:25:57.293842 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9529 23:25:57.300865 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9530 23:25:57.304085 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9531 23:25:57.307359 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9532 23:25:57.313942 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9533 23:25:57.317479 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9534 23:25:57.320887 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9535 23:25:57.327255 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9536 23:25:57.331116 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9537 23:25:57.337513 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9538 23:25:57.340946 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9539 23:25:57.343689 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9540 23:25:57.351280 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9541 23:25:57.354073 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9542 23:25:57.357749 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9543 23:25:57.364012 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9544 23:25:57.367361 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9545 23:25:57.370761 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9546 23:25:57.377530 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9547 23:25:57.380987 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9548 23:25:57.387259 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9549 23:25:57.390657 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9550 23:25:57.394058 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9551 23:25:57.400273 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9552 23:25:57.403934 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9553 23:25:57.410954 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9554 23:25:57.414178 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9555 23:25:57.417468 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9556 23:25:57.424302 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9557 23:25:57.427584 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9558 23:25:57.431121 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9559 23:25:57.438074 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9560 23:25:57.441154 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9561 23:25:57.444582 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9562 23:25:57.451598 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9563 23:25:57.454403 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9564 23:25:57.457989 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9565 23:25:57.461423 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9566 23:25:57.467654 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9567 23:25:57.471297 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9568 23:25:57.475013 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9569 23:25:57.478260 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9570 23:25:57.484828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9571 23:25:57.488050 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9572 23:25:57.491073 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9573 23:25:57.494204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9574 23:25:57.501659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9575 23:25:57.504497 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9576 23:25:57.507921 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9577 23:25:57.514879 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9578 23:25:57.517982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9579 23:25:57.521469 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9580 23:25:57.527963 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9581 23:25:57.531667 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9582 23:25:57.538162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9583 23:25:57.541877 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9584 23:25:57.544778 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9585 23:25:57.552178 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9586 23:25:57.554694 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9587 23:25:57.561554 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9588 23:25:57.565100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9589 23:25:57.571328 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9590 23:25:57.574564 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9591 23:25:57.581759 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9592 23:25:57.584922 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9593 23:25:57.588143 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9594 23:25:57.594581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9595 23:25:57.598245 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9596 23:25:57.604519 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9597 23:25:57.607967 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9598 23:25:57.611609 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9599 23:25:57.618268 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9600 23:25:57.621769 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9601 23:25:57.628139 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9602 23:25:57.631973 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9603 23:25:57.638256 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9604 23:25:57.641673 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9605 23:25:57.644732 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9606 23:25:57.651666 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9607 23:25:57.655767 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9608 23:25:57.661705 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9609 23:25:57.665017 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9610 23:25:57.671825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9611 23:25:57.675004 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9612 23:25:57.678274 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9613 23:25:57.685067 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9614 23:25:57.688465 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9615 23:25:57.695815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9616 23:25:57.698707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9617 23:25:57.705206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9618 23:25:57.708510 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9619 23:25:57.711680 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9620 23:25:57.718687 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9621 23:25:57.722489 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9622 23:25:57.728542 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9623 23:25:57.732006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9624 23:25:57.738740 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9625 23:25:57.741671 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9626 23:25:57.745264 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9627 23:25:57.748803 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9628 23:25:57.755252 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9629 23:25:57.758557 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9630 23:25:57.762121 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9631 23:25:57.768294 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9632 23:25:57.771994 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9633 23:25:57.778697 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9634 23:25:57.782346 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9635 23:25:57.785468 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9636 23:25:57.791742 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9637 23:25:57.795835 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9638 23:25:57.798318 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9639 23:25:57.804996 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9640 23:25:57.808425 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9641 23:25:57.815377 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9642 23:25:57.818630 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9643 23:25:57.821675 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9644 23:25:57.829020 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9645 23:25:57.832184 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9646 23:25:57.835705 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9647 23:25:57.842188 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9648 23:25:57.845311 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9649 23:25:57.848883 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9650 23:25:57.852101 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9651 23:25:57.859052 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9652 23:25:57.862166 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9653 23:25:57.865849 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9654 23:25:57.872034 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9655 23:25:57.875236 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9656 23:25:57.878704 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9657 23:25:57.885272 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9658 23:25:57.888624 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9659 23:25:57.895019 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9660 23:25:57.898497 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9661 23:25:57.901965 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9662 23:25:57.908697 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9663 23:25:57.912104 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9664 23:25:57.915567 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9665 23:25:57.922144 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9666 23:25:57.925474 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9667 23:25:57.932342 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9668 23:25:57.935624 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9669 23:25:57.938897 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9670 23:25:57.945408 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9671 23:25:57.949054 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9672 23:25:57.955199 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9673 23:25:57.958943 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9674 23:25:57.962199 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9675 23:25:57.968552 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9676 23:25:57.971724 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9677 23:25:57.975989 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9678 23:25:57.982358 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9679 23:25:57.985762 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9680 23:25:57.992504 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9681 23:25:57.995689 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9682 23:25:57.998980 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9683 23:25:58.005657 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9684 23:25:58.008667 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9685 23:25:58.015623 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9686 23:25:58.018449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9687 23:25:58.021969 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9688 23:25:58.028718 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9689 23:25:58.031851 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9690 23:25:58.035087 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9691 23:25:58.042241 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9692 23:25:58.045439 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9693 23:25:58.051793 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9694 23:25:58.055154 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9695 23:25:58.059045 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9696 23:25:58.065262 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9697 23:25:58.068372 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9698 23:25:58.075143 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9699 23:25:58.078502 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9700 23:25:58.082197 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9701 23:25:58.088979 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9702 23:25:58.092162 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9703 23:25:58.098357 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9704 23:25:58.101731 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9705 23:25:58.105014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9706 23:25:58.111935 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9707 23:25:58.115670 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9708 23:25:58.118304 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9709 23:25:58.125126 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9710 23:25:58.128269 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9711 23:25:58.134824 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9712 23:25:58.138151 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9713 23:25:58.141628 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9714 23:25:58.148418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9715 23:25:58.151999 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9716 23:25:58.158288 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9717 23:25:58.161723 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9718 23:25:58.164749 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9719 23:25:58.171352 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9720 23:25:58.175168 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9721 23:25:58.181507 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9722 23:25:58.184772 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9723 23:25:58.191285 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9724 23:25:58.194293 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9725 23:25:58.198163 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9726 23:25:58.204611 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9727 23:25:58.207621 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9728 23:25:58.214546 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9729 23:25:58.217913 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9730 23:25:58.221790 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9731 23:25:58.227913 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9732 23:25:58.231012 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9733 23:25:58.237923 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9734 23:25:58.241182 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9735 23:25:58.247693 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9736 23:25:58.250897 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9737 23:25:58.253961 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9738 23:25:58.261213 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9739 23:25:58.263821 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9740 23:25:58.270970 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9741 23:25:58.274209 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9742 23:25:58.280995 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9743 23:25:58.284958 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9744 23:25:58.287449 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9745 23:25:58.294008 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9746 23:25:58.297168 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9747 23:25:58.304485 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9748 23:25:58.307745 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9749 23:25:58.311223 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9750 23:25:58.317571 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9751 23:25:58.321239 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9752 23:25:58.327444 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9753 23:25:58.331137 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9754 23:25:58.334166 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9755 23:25:58.340852 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9756 23:25:58.343978 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9757 23:25:58.350583 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9758 23:25:58.353962 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9759 23:25:58.357646 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9760 23:25:58.360255 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9761 23:25:58.367351 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9762 23:25:58.370438 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9763 23:25:58.374008 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9764 23:25:58.380925 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9765 23:25:58.384391 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9766 23:25:58.388200 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9767 23:25:58.393998 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9768 23:25:58.397026 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9769 23:25:58.400938 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9770 23:25:58.406971 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9771 23:25:58.410172 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9772 23:25:58.416817 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9773 23:25:58.420065 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9774 23:25:58.422924 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9775 23:25:58.430156 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9776 23:25:58.433410 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9777 23:25:58.436210 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9778 23:25:58.443527 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9779 23:25:58.446297 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9780 23:25:58.453366 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9781 23:25:58.456469 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9782 23:25:58.459681 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9783 23:25:58.466220 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9784 23:25:58.469718 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9785 23:25:58.473141 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9786 23:25:58.480070 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9787 23:25:58.482887 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9788 23:25:58.486413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9789 23:25:58.492980 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9790 23:25:58.495738 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9791 23:25:58.502698 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9792 23:25:58.505678 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9793 23:25:58.509281 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9794 23:25:58.515637 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9795 23:25:58.519421 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9796 23:25:58.525924 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9797 23:25:58.529105 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9798 23:25:58.532253 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9799 23:25:58.536017 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9800 23:25:58.542521 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9801 23:25:58.545875 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9802 23:25:58.549308 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9803 23:25:58.552245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9804 23:25:58.556153 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9805 23:25:58.562137 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9806 23:25:58.565571 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9807 23:25:58.568787 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9808 23:25:58.575330 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9809 23:25:58.578580 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9810 23:25:58.581765 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9811 23:25:58.588512 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9812 23:25:58.591859 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9813 23:25:58.598069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9814 23:25:58.601476 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9815 23:25:58.604958 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9816 23:25:58.611560 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9817 23:25:58.614878 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9818 23:25:58.617930 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9819 23:25:58.624686 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9820 23:25:58.628372 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9821 23:25:58.634976 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9822 23:25:58.638011 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9823 23:25:58.644581 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9824 23:25:58.648386 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9825 23:25:58.654592 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9826 23:25:58.658223 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9827 23:25:58.661394 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9828 23:25:58.668076 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9829 23:25:58.671577 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9830 23:25:58.674905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9831 23:25:58.681736 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9832 23:25:58.685214 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9833 23:25:58.691210 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9834 23:25:58.694919 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9835 23:25:58.698151 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9836 23:25:58.704460 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9837 23:25:58.708521 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9838 23:25:58.714789 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9839 23:25:58.718140 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9840 23:25:58.724910 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9841 23:25:58.728627 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9842 23:25:58.730992 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9843 23:25:58.737961 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9844 23:25:58.741279 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9845 23:25:58.747509 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9846 23:25:58.751406 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9847 23:25:58.754490 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9848 23:25:58.760833 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9849 23:25:58.764457 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9850 23:25:58.771279 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9851 23:25:58.774476 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9852 23:25:58.777338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9853 23:25:58.784440 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9854 23:25:58.787492 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9855 23:25:58.793913 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9856 23:25:58.797565 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9857 23:25:58.804086 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9858 23:25:58.807406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9859 23:25:58.810918 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9860 23:25:58.817410 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9861 23:25:58.820822 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9862 23:25:58.823967 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9863 23:25:58.830822 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9864 23:25:58.834110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9865 23:25:58.840649 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9866 23:25:58.843901 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9867 23:25:58.847133 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9868 23:25:58.854225 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9869 23:25:58.857231 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9870 23:25:58.864127 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9871 23:25:58.867157 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9872 23:25:58.874434 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9873 23:25:58.877846 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9874 23:25:58.880958 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9875 23:25:58.887191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9876 23:25:58.890398 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9877 23:25:58.897646 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9878 23:25:58.901081 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9879 23:25:58.903441 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9880 23:25:58.910307 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9881 23:25:58.913617 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9882 23:25:58.920343 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9883 23:25:58.923638 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9884 23:25:58.930159 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9885 23:25:58.933760 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9886 23:25:58.936724 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9887 23:25:58.944173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9888 23:25:58.946896 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9889 23:25:58.953831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9890 23:25:58.957045 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9891 23:25:58.960903 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9892 23:25:58.966982 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9893 23:25:58.970349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9894 23:25:58.976867 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9895 23:25:58.980809 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9896 23:25:58.986924 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9897 23:25:58.989786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9898 23:25:58.996668 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9899 23:25:58.999594 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9900 23:25:59.003460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9901 23:25:59.009758 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9902 23:25:59.013230 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9903 23:25:59.020307 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9904 23:25:59.023333 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9905 23:25:59.030148 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9906 23:25:59.033292 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9907 23:25:59.036515 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9908 23:25:59.043516 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9909 23:25:59.046441 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9910 23:25:59.053006 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9911 23:25:59.056445 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9912 23:25:59.063338 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9913 23:25:59.066470 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9914 23:25:59.069919 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9915 23:25:59.076442 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9916 23:25:59.079482 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9917 23:25:59.086434 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9918 23:25:59.089915 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9919 23:25:59.096241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9920 23:25:59.099463 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9921 23:25:59.106156 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9922 23:25:59.109394 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9923 23:25:59.112807 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9924 23:25:59.119552 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9925 23:25:59.122399 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9926 23:25:59.129496 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9927 23:25:59.132391 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9928 23:25:59.139300 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9929 23:25:59.142932 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9930 23:25:59.146135 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9931 23:25:59.152688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9932 23:25:59.156125 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9933 23:25:59.162215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9934 23:25:59.165683 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9935 23:25:59.172019 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9936 23:25:59.175628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9937 23:25:59.182573 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9938 23:25:59.185717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9939 23:25:59.192511 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9940 23:25:59.195970 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9941 23:25:59.202214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9942 23:25:59.205109 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9943 23:25:59.212050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9944 23:25:59.215526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9945 23:25:59.221977 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9946 23:25:59.225680 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9947 23:25:59.228946 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9948 23:25:59.235460 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9949 23:25:59.238874 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9950 23:25:59.245708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9951 23:25:59.248545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9952 23:25:59.255336 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9953 23:25:59.258714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9954 23:25:59.265265 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9955 23:25:59.268786 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9956 23:25:59.275605 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9957 23:25:59.278950 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9958 23:25:59.285195 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9959 23:25:59.288653 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9960 23:25:59.295119 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9961 23:25:59.298832 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9962 23:25:59.305233 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9963 23:25:59.308706 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9964 23:25:59.312079 INFO: [APUAPC] vio 0
9965 23:25:59.315089 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9966 23:25:59.322251 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9967 23:25:59.325310 INFO: [APUAPC] D0_APC_0: 0x400510
9968 23:25:59.328394 INFO: [APUAPC] D0_APC_1: 0x0
9969 23:25:59.328947 INFO: [APUAPC] D0_APC_2: 0x1540
9970 23:25:59.332555 INFO: [APUAPC] D0_APC_3: 0x0
9971 23:25:59.335034 INFO: [APUAPC] D1_APC_0: 0xffffffff
9972 23:25:59.338071 INFO: [APUAPC] D1_APC_1: 0xffffffff
9973 23:25:59.341960 INFO: [APUAPC] D1_APC_2: 0x3fffff
9974 23:25:59.345128 INFO: [APUAPC] D1_APC_3: 0x0
9975 23:25:59.348096 INFO: [APUAPC] D2_APC_0: 0xffffffff
9976 23:25:59.352073 INFO: [APUAPC] D2_APC_1: 0xffffffff
9977 23:25:59.355311 INFO: [APUAPC] D2_APC_2: 0x3fffff
9978 23:25:59.358549 INFO: [APUAPC] D2_APC_3: 0x0
9979 23:25:59.361839 INFO: [APUAPC] D3_APC_0: 0xffffffff
9980 23:25:59.365395 INFO: [APUAPC] D3_APC_1: 0xffffffff
9981 23:25:59.368832 INFO: [APUAPC] D3_APC_2: 0x3fffff
9982 23:25:59.371896 INFO: [APUAPC] D3_APC_3: 0x0
9983 23:25:59.375147 INFO: [APUAPC] D4_APC_0: 0xffffffff
9984 23:25:59.378544 INFO: [APUAPC] D4_APC_1: 0xffffffff
9985 23:25:59.381712 INFO: [APUAPC] D4_APC_2: 0x3fffff
9986 23:25:59.384590 INFO: [APUAPC] D4_APC_3: 0x0
9987 23:25:59.388159 INFO: [APUAPC] D5_APC_0: 0xffffffff
9988 23:25:59.391541 INFO: [APUAPC] D5_APC_1: 0xffffffff
9989 23:25:59.394848 INFO: [APUAPC] D5_APC_2: 0x3fffff
9990 23:25:59.398112 INFO: [APUAPC] D5_APC_3: 0x0
9991 23:25:59.401491 INFO: [APUAPC] D6_APC_0: 0xffffffff
9992 23:25:59.404604 INFO: [APUAPC] D6_APC_1: 0xffffffff
9993 23:25:59.408122 INFO: [APUAPC] D6_APC_2: 0x3fffff
9994 23:25:59.411407 INFO: [APUAPC] D6_APC_3: 0x0
9995 23:25:59.414721 INFO: [APUAPC] D7_APC_0: 0xffffffff
9996 23:25:59.418516 INFO: [APUAPC] D7_APC_1: 0xffffffff
9997 23:25:59.421339 INFO: [APUAPC] D7_APC_2: 0x3fffff
9998 23:25:59.424588 INFO: [APUAPC] D7_APC_3: 0x0
9999 23:25:59.428011 INFO: [APUAPC] D8_APC_0: 0xffffffff
10000 23:25:59.431416 INFO: [APUAPC] D8_APC_1: 0xffffffff
10001 23:25:59.435078 INFO: [APUAPC] D8_APC_2: 0x3fffff
10002 23:25:59.437749 INFO: [APUAPC] D8_APC_3: 0x0
10003 23:25:59.440759 INFO: [APUAPC] D9_APC_0: 0xffffffff
10004 23:25:59.444560 INFO: [APUAPC] D9_APC_1: 0xffffffff
10005 23:25:59.447705 INFO: [APUAPC] D9_APC_2: 0x3fffff
10006 23:25:59.450990 INFO: [APUAPC] D9_APC_3: 0x0
10007 23:25:59.454293 INFO: [APUAPC] D10_APC_0: 0xffffffff
10008 23:25:59.457649 INFO: [APUAPC] D10_APC_1: 0xffffffff
10009 23:25:59.461509 INFO: [APUAPC] D10_APC_2: 0x3fffff
10010 23:25:59.464200 INFO: [APUAPC] D10_APC_3: 0x0
10011 23:25:59.467796 INFO: [APUAPC] D11_APC_0: 0xffffffff
10012 23:25:59.470721 INFO: [APUAPC] D11_APC_1: 0xffffffff
10013 23:25:59.474037 INFO: [APUAPC] D11_APC_2: 0x3fffff
10014 23:25:59.477493 INFO: [APUAPC] D11_APC_3: 0x0
10015 23:25:59.480936 INFO: [APUAPC] D12_APC_0: 0xffffffff
10016 23:25:59.483899 INFO: [APUAPC] D12_APC_1: 0xffffffff
10017 23:25:59.487296 INFO: [APUAPC] D12_APC_2: 0x3fffff
10018 23:25:59.490888 INFO: [APUAPC] D12_APC_3: 0x0
10019 23:25:59.494164 INFO: [APUAPC] D13_APC_0: 0xffffffff
10020 23:25:59.498104 INFO: [APUAPC] D13_APC_1: 0xffffffff
10021 23:25:59.501160 INFO: [APUAPC] D13_APC_2: 0x3fffff
10022 23:25:59.504213 INFO: [APUAPC] D13_APC_3: 0x0
10023 23:25:59.507530 INFO: [APUAPC] D14_APC_0: 0xffffffff
10024 23:25:59.510865 INFO: [APUAPC] D14_APC_1: 0xffffffff
10025 23:25:59.513708 INFO: [APUAPC] D14_APC_2: 0x3fffff
10026 23:25:59.517712 INFO: [APUAPC] D14_APC_3: 0x0
10027 23:25:59.521106 INFO: [APUAPC] D15_APC_0: 0xffffffff
10028 23:25:59.524523 INFO: [APUAPC] D15_APC_1: 0xffffffff
10029 23:25:59.527360 INFO: [APUAPC] D15_APC_2: 0x3fffff
10030 23:25:59.530554 INFO: [APUAPC] D15_APC_3: 0x0
10031 23:25:59.534134 INFO: [APUAPC] APC_CON: 0x4
10032 23:25:59.537305 INFO: [NOCDAPC] D0_APC_0: 0x0
10033 23:25:59.537927 INFO: [NOCDAPC] D0_APC_1: 0x0
10034 23:25:59.540478 INFO: [NOCDAPC] D1_APC_0: 0x0
10035 23:25:59.543943 INFO: [NOCDAPC] D1_APC_1: 0xfff
10036 23:25:59.547315 INFO: [NOCDAPC] D2_APC_0: 0x0
10037 23:25:59.551070 INFO: [NOCDAPC] D2_APC_1: 0xfff
10038 23:25:59.554192 INFO: [NOCDAPC] D3_APC_0: 0x0
10039 23:25:59.557037 INFO: [NOCDAPC] D3_APC_1: 0xfff
10040 23:25:59.560414 INFO: [NOCDAPC] D4_APC_0: 0x0
10041 23:25:59.564156 INFO: [NOCDAPC] D4_APC_1: 0xfff
10042 23:25:59.567347 INFO: [NOCDAPC] D5_APC_0: 0x0
10043 23:25:59.567813 INFO: [NOCDAPC] D5_APC_1: 0xfff
10044 23:25:59.570840 INFO: [NOCDAPC] D6_APC_0: 0x0
10045 23:25:59.574086 INFO: [NOCDAPC] D6_APC_1: 0xfff
10046 23:25:59.577394 INFO: [NOCDAPC] D7_APC_0: 0x0
10047 23:25:59.580534 INFO: [NOCDAPC] D7_APC_1: 0xfff
10048 23:25:59.584106 INFO: [NOCDAPC] D8_APC_0: 0x0
10049 23:25:59.587270 INFO: [NOCDAPC] D8_APC_1: 0xfff
10050 23:25:59.590481 INFO: [NOCDAPC] D9_APC_0: 0x0
10051 23:25:59.593654 INFO: [NOCDAPC] D9_APC_1: 0xfff
10052 23:25:59.597255 INFO: [NOCDAPC] D10_APC_0: 0x0
10053 23:25:59.600751 INFO: [NOCDAPC] D10_APC_1: 0xfff
10054 23:25:59.603585 INFO: [NOCDAPC] D11_APC_0: 0x0
10055 23:25:59.606649 INFO: [NOCDAPC] D11_APC_1: 0xfff
10056 23:25:59.607112 INFO: [NOCDAPC] D12_APC_0: 0x0
10057 23:25:59.610532 INFO: [NOCDAPC] D12_APC_1: 0xfff
10058 23:25:59.613548 INFO: [NOCDAPC] D13_APC_0: 0x0
10059 23:25:59.616929 INFO: [NOCDAPC] D13_APC_1: 0xfff
10060 23:25:59.620234 INFO: [NOCDAPC] D14_APC_0: 0x0
10061 23:25:59.624096 INFO: [NOCDAPC] D14_APC_1: 0xfff
10062 23:25:59.627064 INFO: [NOCDAPC] D15_APC_0: 0x0
10063 23:25:59.629990 INFO: [NOCDAPC] D15_APC_1: 0xfff
10064 23:25:59.633875 INFO: [NOCDAPC] APC_CON: 0x4
10065 23:25:59.636711 INFO: [APUAPC] set_apusys_apc done
10066 23:25:59.640524 INFO: [DEVAPC] devapc_init done
10067 23:25:59.643555 INFO: GICv3 without legacy support detected.
10068 23:25:59.646900 INFO: ARM GICv3 driver initialized in EL3
10069 23:25:59.650212 INFO: Maximum SPI INTID supported: 639
10070 23:25:59.656941 INFO: BL31: Initializing runtime services
10071 23:25:59.660098 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10072 23:25:59.663244 INFO: SPM: enable CPC mode
10073 23:25:59.670016 INFO: mcdi ready for mcusys-off-idle and system suspend
10074 23:25:59.673688 INFO: BL31: Preparing for EL3 exit to normal world
10075 23:25:59.676867 INFO: Entry point address = 0x80000000
10076 23:25:59.679824 INFO: SPSR = 0x8
10077 23:25:59.685041
10078 23:25:59.685656
10079 23:25:59.686031
10080 23:25:59.688804 Starting depthcharge on Spherion...
10081 23:25:59.689368
10082 23:25:59.689775 Wipe memory regions:
10083 23:25:59.690118
10084 23:25:59.692857 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10085 23:25:59.693388 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10086 23:25:59.693861 Setting prompt string to ['asurada:']
10087 23:25:59.694304 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10088 23:25:59.695025 [0x00000040000000, 0x00000054600000)
10089 23:25:59.814234
10090 23:25:59.814795 [0x00000054660000, 0x00000080000000)
10091 23:26:00.074860
10092 23:26:00.075427 [0x000000821a7280, 0x000000ffe64000)
10093 23:26:00.819178
10094 23:26:00.819749 [0x00000100000000, 0x00000240000000)
10095 23:26:02.708770
10096 23:26:02.712103 Initializing XHCI USB controller at 0x11200000.
10097 23:26:03.750581
10098 23:26:03.753173 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10099 23:26:03.753678
10100 23:26:03.754051
10101 23:26:03.754388
10102 23:26:03.755193 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 23:26:03.856570 asurada: tftpboot 192.168.201.1 12172424/tftp-deploy-1ans5gei/kernel/image.itb 12172424/tftp-deploy-1ans5gei/kernel/cmdline
10105 23:26:03.857226 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10106 23:26:03.857758 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10107 23:26:03.861885 tftpboot 192.168.201.1 12172424/tftp-deploy-1ans5gei/kernel/image.ittp-deploy-1ans5gei/kernel/cmdline
10108 23:26:03.862357
10109 23:26:03.862715 Waiting for link
10110 23:26:04.022462
10111 23:26:04.023015 R8152: Initializing
10112 23:26:04.023510
10113 23:26:04.025747 Version 9 (ocp_data = 6010)
10114 23:26:04.026211
10115 23:26:04.029526 R8152: Done initializing
10116 23:26:04.030128
10117 23:26:04.030495 Adding net device
10118 23:26:05.971839
10119 23:26:05.972434 done.
10120 23:26:05.972922
10121 23:26:05.973517 MAC: 00:e0:4c:78:7a:aa
10122 23:26:05.973969
10123 23:26:05.974644 Sending DHCP discover... done.
10124 23:26:05.975015
10125 23:26:05.978424 Waiting for reply... done.
10126 23:26:05.978972
10127 23:26:05.981651 Sending DHCP request... done.
10128 23:26:05.982206
10129 23:26:05.982572 Waiting for reply... done.
10130 23:26:05.982912
10131 23:26:05.984550 My ip is 192.168.201.12
10132 23:26:05.985010
10133 23:26:05.988339 The DHCP server ip is 192.168.201.1
10134 23:26:05.988807
10135 23:26:05.991573 TFTP server IP predefined by user: 192.168.201.1
10136 23:26:05.992134
10137 23:26:05.998153 Bootfile predefined by user: 12172424/tftp-deploy-1ans5gei/kernel/image.itb
10138 23:26:05.998779
10139 23:26:06.001351 Sending tftp read request... done.
10140 23:26:06.001937
10141 23:26:06.010519 Waiting for the transfer...
10142 23:26:06.011069
10143 23:26:06.287947 00000000 ################################################################
10144 23:26:06.288107
10145 23:26:06.581521 00080000 ################################################################
10146 23:26:06.581701
10147 23:26:06.853248 00100000 ################################################################
10148 23:26:06.853420
10149 23:26:07.143389 00180000 ################################################################
10150 23:26:07.143528
10151 23:26:07.432274 00200000 ################################################################
10152 23:26:07.432411
10153 23:26:07.720192 00280000 ################################################################
10154 23:26:07.720327
10155 23:26:07.993031 00300000 ################################################################
10156 23:26:07.993192
10157 23:26:08.267835 00380000 ################################################################
10158 23:26:08.267970
10159 23:26:08.559819 00400000 ################################################################
10160 23:26:08.559955
10161 23:26:08.816855 00480000 ################################################################
10162 23:26:08.816989
10163 23:26:09.070561 00500000 ################################################################
10164 23:26:09.070696
10165 23:26:09.324537 00580000 ################################################################
10166 23:26:09.324703
10167 23:26:09.589643 00600000 ################################################################
10168 23:26:09.589777
10169 23:26:09.843547 00680000 ################################################################
10170 23:26:09.843706
10171 23:26:10.093718 00700000 ################################################################
10172 23:26:10.093873
10173 23:26:10.377959 00780000 ################################################################
10174 23:26:10.378118
10175 23:26:10.660153 00800000 ################################################################
10176 23:26:10.660316
10177 23:26:10.928204 00880000 ################################################################
10178 23:26:10.928340
10179 23:26:11.203304 00900000 ################################################################
10180 23:26:11.203466
10181 23:26:11.494349 00980000 ################################################################
10182 23:26:11.494510
10183 23:26:11.791857 00a00000 ################################################################
10184 23:26:11.792015
10185 23:26:12.083061 00a80000 ################################################################
10186 23:26:12.083234
10187 23:26:12.380032 00b00000 ################################################################
10188 23:26:12.380242
10189 23:26:12.671815 00b80000 ################################################################
10190 23:26:12.671955
10191 23:26:12.952933 00c00000 ################################################################
10192 23:26:12.953096
10193 23:26:13.238517 00c80000 ################################################################
10194 23:26:13.238683
10195 23:26:13.535570 00d00000 ################################################################
10196 23:26:13.535732
10197 23:26:13.832225 00d80000 ################################################################
10198 23:26:13.832387
10199 23:26:14.115689 00e00000 ################################################################
10200 23:26:14.115830
10201 23:26:14.412189 00e80000 ################################################################
10202 23:26:14.412354
10203 23:26:14.704527 00f00000 ################################################################
10204 23:26:14.704682
10205 23:26:14.976474 00f80000 ################################################################
10206 23:26:14.976635
10207 23:26:15.238658 01000000 ################################################################
10208 23:26:15.238796
10209 23:26:15.534510 01080000 ################################################################
10210 23:26:15.534672
10211 23:26:15.832185 01100000 ################################################################
10212 23:26:15.832338
10213 23:26:16.109347 01180000 ################################################################
10214 23:26:16.109487
10215 23:26:16.405457 01200000 ################################################################
10216 23:26:16.405630
10217 23:26:16.703118 01280000 ################################################################
10218 23:26:16.703254
10219 23:26:16.999639 01300000 ################################################################
10220 23:26:16.999779
10221 23:26:17.290817 01380000 ################################################################
10222 23:26:17.290960
10223 23:26:17.588142 01400000 ################################################################
10224 23:26:17.588281
10225 23:26:17.881791 01480000 ################################################################
10226 23:26:17.881927
10227 23:26:18.164061 01500000 ################################################################
10228 23:26:18.164200
10229 23:26:18.432533 01580000 ################################################################
10230 23:26:18.432676
10231 23:26:18.685807 01600000 ################################################################
10232 23:26:18.685938
10233 23:26:18.937217 01680000 ################################################################
10234 23:26:18.937349
10235 23:26:19.204091 01700000 ################################################################
10236 23:26:19.204227
10237 23:26:19.493711 01780000 ################################################################
10238 23:26:19.493849
10239 23:26:19.790573 01800000 ################################################################
10240 23:26:19.790704
10241 23:26:20.088297 01880000 ################################################################
10242 23:26:20.088444
10243 23:26:20.392852 01900000 ################################################################
10244 23:26:20.393000
10245 23:26:20.676858 01980000 ################################################################
10246 23:26:20.676996
10247 23:26:20.931320 01a00000 ################################################################
10248 23:26:20.931451
10249 23:26:21.192979 01a80000 ################################################################
10250 23:26:21.193119
10251 23:26:21.458878 01b00000 ################################################################
10252 23:26:21.459021
10253 23:26:21.492617 01b80000 ######## done.
10254 23:26:21.493048
10255 23:26:21.495732 The bootfile was 28894082 bytes long.
10256 23:26:21.496188
10257 23:26:21.498794 Sending tftp read request... done.
10258 23:26:21.499190
10259 23:26:21.502897 Waiting for the transfer...
10260 23:26:21.503371
10261 23:26:21.503703 00000000 # done.
10262 23:26:21.504021
10263 23:26:21.509704 Command line loaded dynamically from TFTP file: 12172424/tftp-deploy-1ans5gei/kernel/cmdline
10264 23:26:21.510125
10265 23:26:21.533025 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10266 23:26:21.533551
10267 23:26:21.533944 Loading FIT.
10268 23:26:21.534252
10269 23:26:21.536088 Image ramdisk-1 has 17795424 bytes.
10270 23:26:21.536502
10271 23:26:21.539749 Image fdt-1 has 47278 bytes.
10272 23:26:21.540164
10273 23:26:21.542719 Image kernel-1 has 11049348 bytes.
10274 23:26:21.543133
10275 23:26:21.552780 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10276 23:26:21.553281
10277 23:26:21.569631 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10278 23:26:21.570226
10279 23:26:21.576208 Choosing best match conf-1 for compat google,spherion-rev2.
10280 23:26:21.576744
10281 23:26:21.584046 Connected to device vid:did:rid of 1ae0:0028:00
10282 23:26:21.592052
10283 23:26:21.595414 tpm_get_response: command 0x17b, return code 0x0
10284 23:26:21.595951
10285 23:26:21.598046 ec_init: CrosEC protocol v3 supported (256, 248)
10286 23:26:21.602784
10287 23:26:21.605974 tpm_cleanup: add release locality here.
10288 23:26:21.606529
10289 23:26:21.606945 Shutting down all USB controllers.
10290 23:26:21.609918
10291 23:26:21.610331 Removing current net device
10292 23:26:21.610657
10293 23:26:21.616793 Exiting depthcharge with code 4 at timestamp: 51233469
10294 23:26:21.617307
10295 23:26:21.619911 LZMA decompressing kernel-1 to 0x821a6718
10296 23:26:21.620426
10297 23:26:21.622792 LZMA decompressing kernel-1 to 0x40000000
10298 23:26:23.011286
10299 23:26:23.011843 jumping to kernel
10300 23:26:23.013545 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
10301 23:26:23.014127 start: 2.2.5 auto-login-action (timeout 00:04:02) [common]
10302 23:26:23.014538 Setting prompt string to ['Linux version [0-9]']
10303 23:26:23.014909 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10304 23:26:23.015278 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10305 23:26:23.093130
10306 23:26:23.096145 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10307 23:26:23.100510 start: 2.2.5.1 login-action (timeout 00:04:02) [common]
10308 23:26:23.101093 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10309 23:26:23.101484 Setting prompt string to []
10310 23:26:23.101945 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10311 23:26:23.102340 Using line separator: #'\n'#
10312 23:26:23.102666 No login prompt set.
10313 23:26:23.103006 Parsing kernel messages
10314 23:26:23.103311 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10315 23:26:23.103856 [login-action] Waiting for messages, (timeout 00:04:02)
10316 23:26:23.120005 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10317 23:26:23.122646 [ 0.000000] random: crng init done
10318 23:26:23.129724 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10319 23:26:23.133116 [ 0.000000] efi: UEFI not found.
10320 23:26:23.139822 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10321 23:26:23.146204 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10322 23:26:23.156600 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10323 23:26:23.165886 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10324 23:26:23.171942 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10325 23:26:23.178595 [ 0.000000] printk: bootconsole [mtk8250] enabled
10326 23:26:23.185498 [ 0.000000] NUMA: No NUMA configuration found
10327 23:26:23.191752 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 23:26:23.195214 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10329 23:26:23.199162 [ 0.000000] Zone ranges:
10330 23:26:23.205737 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 23:26:23.208865 [ 0.000000] DMA32 empty
10332 23:26:23.215885 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 23:26:23.218992 [ 0.000000] Movable zone start for each node
10334 23:26:23.222734 [ 0.000000] Early memory node ranges
10335 23:26:23.228929 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 23:26:23.235608 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 23:26:23.242145 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 23:26:23.249385 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 23:26:23.255709 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 23:26:23.261738 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 23:26:23.318159 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 23:26:23.324491 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 23:26:23.331281 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 23:26:23.334439 [ 0.000000] psci: probing for conduit method from DT.
10345 23:26:23.340788 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 23:26:23.344130 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 23:26:23.350671 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 23:26:23.353821 [ 0.000000] psci: SMC Calling Convention v1.2
10349 23:26:23.361296 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10350 23:26:23.364076 [ 0.000000] Detected VIPT I-cache on CPU0
10351 23:26:23.370830 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 23:26:23.377640 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 23:26:23.384600 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 23:26:23.390795 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 23:26:23.397248 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 23:26:23.404050 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 23:26:23.410304 [ 0.000000] alternatives: applying boot alternatives
10358 23:26:23.413490 [ 0.000000] Fallback order for Node 0: 0
10359 23:26:23.423738 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 23:26:23.424284 [ 0.000000] Policy zone: Normal
10361 23:26:23.447501 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10362 23:26:23.457759 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 23:26:23.470510 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 23:26:23.480460 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 23:26:23.487399 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 23:26:23.490224 <6>[ 0.000000] software IO TLB: area num 8.
10367 23:26:23.546763 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 23:26:23.695539 <6>[ 0.000000] Memory: 7952180K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400588K reserved, 32768K cma-reserved)
10369 23:26:23.702402 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 23:26:23.709200 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 23:26:23.712470 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10372 23:26:23.719449 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 23:26:23.726013 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 23:26:23.728916 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10375 23:26:23.739433 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 23:26:23.745498 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 23:26:23.749219 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 23:26:23.757191 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 23:26:23.760380 <6>[ 0.000000] GICv3: 608 SPIs implemented
10380 23:26:23.767012 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10381 23:26:23.770305 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10382 23:26:23.773676 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 23:26:23.780332 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 23:26:23.793906 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 23:26:23.807198 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 23:26:23.813566 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 23:26:23.822611 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 23:26:23.835422 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 23:26:23.842225 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 23:26:23.849199 <6>[ 0.009217] Console: colour dummy device 80x25
10391 23:26:23.858515 <6>[ 0.013941] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 23:26:23.865457 <6>[ 0.024384] pid_max: default: 32768 minimum: 301
10393 23:26:23.868479 <6>[ 0.029285] LSM: Security Framework initializing
10394 23:26:23.875252 <6>[ 0.034221] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 23:26:23.885098 <6>[ 0.042085] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 23:26:23.891801 <6>[ 0.051487] cblist_init_generic: Setting adjustable number of callback queues.
10397 23:26:23.898554 <6>[ 0.058928] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 23:26:23.908502 <6>[ 0.065266] cblist_init_generic: Setting adjustable number of callback queues.
10399 23:26:23.915243 <6>[ 0.072693] cblist_init_generic: Setting shift to 3 and lim to 1.
10400 23:26:23.919069 <6>[ 0.079134] rcu: Hierarchical SRCU implementation.
10401 23:26:23.925073 <6>[ 0.079136] rcu: Max phase no-delay instances is 1000.
10402 23:26:23.931776 <6>[ 0.079161] printk: bootconsole [mtk8250] printing thread started
10403 23:26:23.938445 <6>[ 0.097528] EFI services will not be available.
10404 23:26:23.941668 <6>[ 0.097728] smp: Bringing up secondary CPUs ...
10405 23:26:23.944682 <6>[ 0.098040] Detected VIPT I-cache on CPU1
10406 23:26:23.954643 <6>[ 0.098109] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10407 23:26:23.961263 <6>[ 0.098141] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10408 23:26:23.970616 <6>[ 0.126011] Detected VIPT I-cache on CPU2
10409 23:26:23.980234 <6>[ 0.126062] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10410 23:26:23.987084 <6>[ 0.126079] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10411 23:26:23.989940 <6>[ 0.126334] Detected VIPT I-cache on CPU3
10412 23:26:23.996718 <6>[ 0.126380] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10413 23:26:24.003345 <6>[ 0.126394] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10414 23:26:24.006848 <6>[ 0.126689] CPU features: detected: Spectre-v4
10415 23:26:24.013112 <6>[ 0.126694] CPU features: detected: Spectre-BHB
10416 23:26:24.016450 <6>[ 0.126699] Detected PIPT I-cache on CPU4
10417 23:26:24.023932 <6>[ 0.126748] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10418 23:26:24.030285 <6>[ 0.126763] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10419 23:26:24.037005 <6>[ 0.127041] Detected PIPT I-cache on CPU5
10420 23:26:24.043343 <6>[ 0.127101] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10421 23:26:24.049761 <6>[ 0.127120] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10422 23:26:24.053690 <6>[ 0.127393] Detected PIPT I-cache on CPU6
10423 23:26:24.060359 <6>[ 0.127456] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10424 23:26:24.066501 <6>[ 0.127472] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10425 23:26:24.073225 <6>[ 0.127762] Detected PIPT I-cache on CPU7
10426 23:26:24.080491 <6>[ 0.127825] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10427 23:26:24.086790 <6>[ 0.127842] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10428 23:26:24.089679 <6>[ 0.127888] smp: Brought up 1 node, 8 CPUs
10429 23:26:24.096533 <6>[ 0.127892] SMP: Total of 8 processors activated.
10430 23:26:24.100282 <6>[ 0.127895] CPU features: detected: 32-bit EL0 Support
10431 23:26:24.109655 <6>[ 0.127897] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10432 23:26:24.116024 <6>[ 0.127900] CPU features: detected: Common not Private translations
10433 23:26:24.122954 <6>[ 0.127901] CPU features: detected: CRC32 instructions
10434 23:26:24.125911 <6>[ 0.127904] CPU features: detected: RCpc load-acquire (LDAPR)
10435 23:26:24.132703 <6>[ 0.127906] CPU features: detected: LSE atomic instructions
10436 23:26:24.139638 <6>[ 0.127908] CPU features: detected: Privileged Access Never
10437 23:26:24.146029 <6>[ 0.127909] CPU features: detected: RAS Extension Support
10438 23:26:24.152690 <6>[ 0.127912] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10439 23:26:24.156115 <6>[ 0.127979] CPU: All CPU(s) started at EL2
10440 23:26:24.163122 <6>[ 0.127980] alternatives: applying system-wide alternatives
10441 23:26:24.166193 <6>[ 0.141027] devtmpfs: initialized
10442 23:26:24.176241 <6>[ 0.147368] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10443 23:26:24.203974 �)���ѕɕ���}%9Q��ɽѽ����2�����5S�<6>[ 0.<364579] printk: console [ttyS0] printing thread started
10444 23:26:24.210606 6<6>[ 0.364607] printk: console [ttyS0] enabled
10445 23:26:24.216988 >[ 0.224653] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10446 23:26:24.225188 <6>[ 0.364611] printk: bootconsole [mtk8250] disabled
10447 23:26:24.231061 <6>[ 0.382698] printk: bootconsole [mtk8250] printing thread stopped
10448 23:26:24.235060 <6>[ 0.383980] SuperH (H)SCI(F) driver initialized
10449 23:26:24.241678 <6>[ 0.384455] msm_serial: driver initialized
10450 23:26:24.247789 <6>[ 0.389048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10451 23:26:24.257800 <6>[ 0.389077] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10452 23:26:24.264385 <6>[ 0.389106] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10453 23:26:24.284532 <6>[ 0.389135] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10454 23:26:24.292470 <6>[ 0.389156] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10455 23:26:24.293136 <6>[ 0.389184] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10456 23:26:24.309368 <6>[ 0.389211] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10457 23:26:24.316519 <6>[ 0.389333] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10458 23:26:24.324174 <6>[ 0.389363] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10459 23:26:24.324744 <6>[ 0.400426] loop: module loaded
10460 23:26:24.333516 <6>[ 0.403082] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10461 23:26:24.336644 <4>[ 0.419674] mtk-pmic-keys: Failed to locate of_node [id: -1]
10462 23:26:24.337206 <6>[ 0.420605] megasas: 07.719.03.00-rc1
10463 23:26:24.343048 <6>[ 0.432734] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10464 23:26:24.350206 <6>[ 0.432864] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10465 23:26:24.356650 <6>[ 0.444569] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10466 23:26:24.366592 <6>[ 0.496969] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10467 23:26:24.804863 <6>[ 0.962215] Freeing initrd memory: 17372K
10468 23:26:24.811635 <6>[ 0.968341] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10469 23:26:24.814426 <6>[ 0.973123] tun: Universal TUN/TAP device driver, 1.6
10470 23:26:24.818327 <6>[ 0.973890] thunder_xcv, ver 1.0
10471 23:26:24.822001 <6>[ 0.973912] thunder_bgx, ver 1.0
10472 23:26:24.825033 <6>[ 0.973926] nicpf, ver 1.0
10473 23:26:24.831449 <6>[ 0.974982] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10474 23:26:24.838236 <6>[ 0.974985] hns3: Copyright (c) 2017 Huawei Corporation.
10475 23:26:24.841790 <6>[ 0.975010] hclge is initializing
10476 23:26:24.848216 <6>[ 0.975025] e1000: Intel(R) PRO/1000 Network Driver
10477 23:26:24.851665 <6>[ 0.975027] e1000: Copyright (c) 1999-2006 Intel Corporation.
10478 23:26:24.859174 <6>[ 0.975044] e1000e: Intel(R) PRO/1000 Network Driver
10479 23:26:24.865753 <6>[ 0.975046] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10480 23:26:24.869749 <6>[ 0.975063] igb: Intel(R) Gigabit Ethernet Network Driver
10481 23:26:24.876201 <6>[ 0.975065] igb: Copyright (c) 2007-2014 Intel Corporation.
10482 23:26:24.883486 <6>[ 0.975081] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10483 23:26:24.890208 <6>[ 0.975083] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10484 23:26:24.893124 <6>[ 0.975371] sky2: driver version 1.30
10485 23:26:24.896532 <6>[ 0.976454] VFIO - User Level meta-driver version: 0.3
10486 23:26:24.902911 <6>[ 0.979267] usbcore: registered new interface driver usb-storage
10487 23:26:24.909825 <6>[ 0.979452] usbcore: registered new device driver onboard-usb-hub
10488 23:26:24.916384 <6>[ 0.982204] mt6397-rtc mt6359-rtc: registered as rtc0
10489 23:26:24.926473 <6>[ 0.982357] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:24:10 UTC (1701645850)
10490 23:26:24.929931 <6>[ 0.982969] i2c_dev: i2c /dev entries driver
10491 23:26:24.936446 <6>[ 0.990159] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10492 23:26:24.943105 <6>[ 1.005140] cpu cpu0: EM: created perf domain
10493 23:26:24.946389 <6>[ 1.005471] cpu cpu4: EM: created perf domain
10494 23:26:24.953319 <6>[ 1.007859] sdhci: Secure Digital Host Controller Interface driver
10495 23:26:24.956263 <6>[ 1.007860] sdhci: Copyright(c) Pierre Ossman
10496 23:26:24.963457 <6>[ 1.008217] Synopsys Designware Multimedia Card Interface Driver
10497 23:26:24.970156 <6>[ 1.008605] sdhci-pltfm: SDHCI platform and OF driver helper
10498 23:26:24.976708 <6>[ 1.012824] ledtrig-cpu: registered to indicate activity on CPUs
10499 23:26:24.979779 <6>[ 1.013514] mmc0: CQHCI version 5.10
10500 23:26:24.986669 <6>[ 1.013583] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10501 23:26:24.993139 <6>[ 1.013855] usbcore: registered new interface driver usbhid
10502 23:26:24.996557 <6>[ 1.013856] usbhid: USB HID core driver
10503 23:26:25.003277 <6>[ 1.013966] spi_master spi0: will run message pump with realtime priority
10504 23:26:25.016143 <6>[ 1.043235] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10505 23:26:25.029971 <6>[ 1.045695] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10506 23:26:25.036130 <6>[ 1.047370] cros-ec-spi spi0.0: Chrome EC device registered
10507 23:26:25.043220 <6>[ 1.063278] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10508 23:26:25.049392 <6>[ 1.064252] NET: Registered PF_PACKET protocol family
10509 23:26:25.053518 <6>[ 1.064324] 9pnet: Installing 9P2000 support
10510 23:26:25.059489 <5>[ 1.064360] Key type dns_resolver registered
10511 23:26:25.062956 <6>[ 1.064762] registered taskstats version 1
10512 23:26:25.069400 <5>[ 1.064776] Loading compiled-in X.509 certificates
10513 23:26:25.079267 <4>[ 1.082640] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 23:26:25.088944 <4>[ 1.082860] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 23:26:25.095635 <3>[ 1.082879] debugfs: File 'uA_load' in directory '/' already present!
10516 23:26:25.102329 <3>[ 1.082890] debugfs: File 'min_uV' in directory '/' already present!
10517 23:26:25.109528 <3>[ 1.082896] debugfs: File 'max_uV' in directory '/' already present!
10518 23:26:25.115679 <3>[ 1.082902] debugfs: File 'constraint_flags' in directory '/' already present!
10519 23:26:25.126009 <3>[ 1.085991] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10520 23:26:25.132476 <6>[ 1.095859] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10521 23:26:25.136002 <6>[ 1.096485] xhci-mtk 11200000.usb: xHCI Host Controller
10522 23:26:25.145707 <6>[ 1.096502] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10523 23:26:25.155626 <6>[ 1.096720] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10524 23:26:25.159142 <6>[ 1.096767] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10525 23:26:25.165629 <6>[ 1.096870] xhci-mtk 11200000.usb: xHCI Host Controller
10526 23:26:25.172221 <6>[ 1.096878] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10527 23:26:25.178795 <6>[ 1.096885] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10528 23:26:25.185368 <6>[ 1.097393] hub 1-0:1.0: USB hub found
10529 23:26:25.188837 <6>[ 1.097430] hub 1-0:1.0: 1 port detected
10530 23:26:25.195553 <6>[ 1.097718] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10531 23:26:25.202051 <6>[ 1.098337] hub 2-0:1.0: USB hub found
10532 23:26:25.205657 <6>[ 1.098361] hub 2-0:1.0: 1 port detected
10533 23:26:25.208735 <6>[ 1.101848] mtk-msdc 11f70000.mmc: Got CD GPIO
10534 23:26:25.215389 <6>[ 1.112308] mmc0: Command Queue Engine enabled
10535 23:26:25.222218 <6>[ 1.112322] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10536 23:26:25.225165 <6>[ 1.112853] mmcblk0: mmc0:0001 DA4128 116 GiB
10537 23:26:25.232196 <6>[ 1.116274] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10538 23:26:25.238298 <6>[ 1.116587] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10539 23:26:25.248521 <6>[ 1.116593] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10540 23:26:25.255137 <4>[ 1.116753] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10541 23:26:25.261739 <6>[ 1.117248] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10542 23:26:25.268929 <6>[ 1.117404] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10543 23:26:25.278919 <6>[ 1.117410] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10544 23:26:25.285782 <6>[ 1.117551] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10545 23:26:25.292221 <6>[ 1.117562] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10546 23:26:25.302570 <6>[ 1.117566] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10547 23:26:25.308841 <6>[ 1.117572] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10548 23:26:25.315491 <6>[ 1.118021] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10549 23:26:25.322548 <6>[ 1.118751] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10550 23:26:25.328934 <6>[ 1.119741] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10551 23:26:25.338772 <6>[ 1.119760] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10552 23:26:25.345918 <6>[ 1.119766] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10553 23:26:25.355592 <6>[ 1.119773] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10554 23:26:25.362522 <6>[ 1.119779] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10555 23:26:25.372162 <6>[ 1.119785] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10556 23:26:25.379107 <6>[ 1.119792] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10557 23:26:25.388924 <6>[ 1.119798] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10558 23:26:25.398672 <6>[ 1.119804] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10559 23:26:25.405619 <6>[ 1.119810] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10560 23:26:25.414997 <6>[ 1.119816] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10561 23:26:25.421568 <6>[ 1.119823] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10562 23:26:25.431642 <6>[ 1.119829] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10563 23:26:25.438323 <6>[ 1.119835] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10564 23:26:25.448233 <6>[ 1.119842] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10565 23:26:25.454864 <6>[ 1.120416] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10566 23:26:25.462149 <6>[ 1.121283] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10567 23:26:25.468263 <6>[ 1.121955] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10568 23:26:25.475696 <6>[ 1.122611] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10569 23:26:25.481351 <6>[ 1.123239] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10570 23:26:25.488306 <6>[ 1.123459] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10571 23:26:25.497976 <6>[ 1.123472] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10572 23:26:25.508177 <6>[ 1.123478] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10573 23:26:25.517828 <6>[ 1.123483] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10574 23:26:25.528145 <6>[ 1.123489] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10575 23:26:25.534408 <6>[ 1.123494] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10576 23:26:25.544874 <6>[ 1.123499] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10577 23:26:25.554318 <6>[ 1.123504] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10578 23:26:25.564420 <6>[ 1.123509] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10579 23:26:25.574357 <6>[ 1.123515] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10580 23:26:25.583725 <6>[ 1.123520] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10581 23:26:25.590556 <6>[ 1.124179] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10582 23:26:25.597538 <6>[ 1.133845] Trying to probe devices needed for running init ...
10583 23:26:25.604381 <6>[ 1.489628] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10584 23:26:25.610349 <6>[ 1.519814] hub 2-1:1.0: USB hub found
10585 23:26:25.613870 <6>[ 1.520121] hub 2-1:1.0: 3 ports detected
10586 23:26:25.617251 <6>[ 1.522500] hub 2-1:1.0: USB hub found
10587 23:26:25.620264 <6>[ 1.522847] hub 2-1:1.0: 3 ports detected
10588 23:26:25.627474 <6>[ 1.641393] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10589 23:26:25.636611 <6>[ 1.794476] hub 1-1:1.0: USB hub found
10590 23:26:25.639961 <6>[ 1.794860] hub 1-1:1.0: 4 ports detected
10591 23:26:25.643366 <6>[ 1.798593] hub 1-1:1.0: USB hub found
10592 23:26:25.646249 <6>[ 1.798923] hub 1-1:1.0: 4 ports detected
10593 23:26:25.720023 <6>[ 1.873722] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10594 23:26:25.956148 <6>[ 2.109710] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10595 23:26:26.077084 <6>[ 2.236875] hub 1-1.4:1.0: USB hub found
10596 23:26:26.080551 <6>[ 2.237190] hub 1-1.4:1.0: 2 ports detected
10597 23:26:26.083825 <6>[ 2.240196] hub 1-1.4:1.0: USB hub found
10598 23:26:26.089660 <6>[ 2.240501] hub 1-1.4:1.0: 2 ports detected
10599 23:26:26.375946 <6>[ 2.529601] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10600 23:26:26.560671 <6>[ 2.713602] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10601 23:26:37.248575 <6>[ 13.410640] ALSA device list:
10602 23:26:37.254972 <6>[ 13.410663] No soundcards found.
10603 23:26:37.258262 <6>[ 13.415077] Freeing unused kernel memory: 8448K
10604 23:26:37.261416 <6>[ 13.415224] Run /init as init process
10605 23:26:37.264836 Loading, please wait...
10606 23:26:37.286448 Starting version 247.3-7+deb11u2
10607 23:26:37.466382 <6>[ 13.619708] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10608 23:26:37.469311 <6>[ 13.624033] remoteproc remoteproc0: scp is available
10609 23:26:37.475621 <6>[ 13.624223] remoteproc remoteproc0: powering up scp
10610 23:26:37.482623 <6>[ 13.624236] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10611 23:26:37.489361 <6>[ 13.624296] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10612 23:26:37.531101 <6>[ 13.687966] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10613 23:26:37.537227 <6>[ 13.688034] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10614 23:26:37.547211 <6>[ 13.688047] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10615 23:26:37.559795 <6>[ 13.718576] mc: Linux media interface: v0.10
10616 23:26:37.566499 <3>[ 13.718765] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10617 23:26:37.575837 <3>[ 13.718790] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10618 23:26:37.582846 <3>[ 13.718797] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 23:26:37.592848 <3>[ 13.722050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10620 23:26:37.599339 <3>[ 13.722099] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10621 23:26:37.606802 <3>[ 13.722107] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 23:26:37.616446 <3>[ 13.722116] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 23:26:37.623236 <3>[ 13.722121] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 23:26:37.629071 <4>[ 13.722642] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10625 23:26:37.639456 <6>[ 13.723638] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10626 23:26:37.646951 <3>[ 13.731910] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 23:26:37.653764 <4>[ 13.732163] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10628 23:26:37.663565 <3>[ 13.734324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10629 23:26:37.669968 <3>[ 13.734345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10630 23:26:37.676612 <3>[ 13.734355] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10631 23:26:37.683212 <6>[ 13.736006] videodev: Linux video capture interface: v2.00
10632 23:26:37.693415 <3>[ 13.741421] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10633 23:26:37.699757 <3>[ 13.741456] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 23:26:37.706169 <3>[ 13.741464] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 23:26:37.716341 <3>[ 13.741474] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 23:26:37.723222 <3>[ 13.741482] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 23:26:37.732854 <3>[ 13.747218] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 23:26:37.740005 <4>[ 13.748198] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10639 23:26:37.745898 <4>[ 13.748198] Fallback method does not support PEC.
10640 23:26:37.756325 <6>[ 13.751198] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10641 23:26:37.762757 <6>[ 13.751208] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10642 23:26:37.768978 <6>[ 13.751212] remoteproc remoteproc0: remote processor scp is now up
10643 23:26:37.775887 <3>[ 13.782587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10644 23:26:37.782771 <6>[ 13.783897] usbcore: registered new interface driver r8152
10645 23:26:37.789536 <6>[ 13.792418] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10646 23:26:37.799352 <6>[ 13.797064] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10647 23:26:37.806017 <6>[ 13.806825] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10648 23:26:37.812524 <6>[ 13.806860] pci_bus 0000:00: root bus resource [bus 00-ff]
10649 23:26:37.819179 <6>[ 13.806889] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10650 23:26:37.828724 <6>[ 13.806896] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10651 23:26:37.836003 <6>[ 13.806986] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10652 23:26:37.842246 <6>[ 13.807023] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10653 23:26:37.845914 <6>[ 13.807134] pci 0000:00:00.0: supports D1 D2
10654 23:26:37.852564 <6>[ 13.807138] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10655 23:26:37.861952 <6>[ 13.809203] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10656 23:26:37.868666 <6>[ 13.809907] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10657 23:26:37.875317 <6>[ 13.809959] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10658 23:26:37.882166 <6>[ 13.809983] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10659 23:26:37.891705 <6>[ 13.810008] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10660 23:26:37.895214 <6>[ 13.810236] pci 0000:01:00.0: supports D1 D2
10661 23:26:37.901823 <6>[ 13.810242] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10662 23:26:37.911972 <3>[ 13.817214] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10663 23:26:37.918359 <6>[ 13.825406] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10664 23:26:37.924968 <6>[ 13.825449] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10665 23:26:37.934891 <6>[ 13.825456] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10666 23:26:37.941598 <6>[ 13.825468] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10667 23:26:37.948339 <6>[ 13.825484] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10668 23:26:37.958567 <6>[ 13.825516] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10669 23:26:37.961390 <6>[ 13.825541] pci 0000:00:00.0: PCI bridge to [bus 01]
10670 23:26:37.971548 <6>[ 13.825550] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10671 23:26:37.977877 <6>[ 13.825746] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10672 23:26:37.984491 <6>[ 13.826892] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10673 23:26:37.987839 <6>[ 13.827230] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10674 23:26:37.998143 <6>[ 13.840233] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10675 23:26:38.004475 <6>[ 13.861852] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10676 23:26:38.014126 <6>[ 13.870605] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10677 23:26:38.024275 <6>[ 13.871010] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10678 23:26:38.034168 <4>[ 13.885953] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10679 23:26:38.040817 <4>[ 13.885970] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10680 23:26:38.047452 <6>[ 13.900685] usbcore: registered new interface driver cdc_ether
10681 23:26:38.050520 <6>[ 13.901453] r8152 2-1.3:1.0 eth0: v1.12.13
10682 23:26:38.060687 <5>[ 13.904376] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10683 23:26:38.067390 <5>[ 13.919294] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10684 23:26:38.076930 <4>[ 13.919389] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10685 23:26:38.080437 <6>[ 13.919398] cfg80211: failed to load regulatory.db
10686 23:26:38.083938 <6>[ 13.922277] Bluetooth: Core ver 2.22
10687 23:26:38.090552 <6>[ 13.922435] usbcore: registered new interface driver r8153_ecm
10688 23:26:38.096594 <6>[ 13.922457] NET: Registered PF_BLUETOOTH protocol family
10689 23:26:38.103217 <6>[ 13.922467] Bluetooth: HCI device and connection manager initialized
10690 23:26:38.106758 <6>[ 13.922533] Bluetooth: HCI socket layer initialized
10691 23:26:38.113680 <6>[ 13.922556] Bluetooth: L2CAP socket layer initialized
10692 23:26:38.120346 <6>[ 13.922597] Bluetooth: SCO socket layer initialized
10693 23:26:38.123579 <6>[ 13.931690] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10694 23:26:38.130169 <6>[ 13.936592] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10695 23:26:38.142986 <6>[ 13.937624] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10696 23:26:38.150044 <6>[ 13.937716] usbcore: registered new interface driver uvcvideo
10697 23:26:38.156811 <6>[ 13.966828] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10698 23:26:38.163629 <6>[ 13.973293] usbcore: registered new interface driver btusb
10699 23:26:38.173283 <4>[ 13.974530] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10700 23:26:38.179627 <3>[ 13.974539] Bluetooth: hci0: Failed to load firmware file (-2)
10701 23:26:38.186335 <3>[ 13.974541] Bluetooth: hci0: Failed to set up firmware (-2)
10702 23:26:38.196316 <4>[ 13.974544] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10703 23:26:38.203043 <6>[ 14.270249] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10704 23:26:38.208990 <6>[ 14.270358] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10705 23:26:38.212322 <6>[ 14.289556] mt7921e 0000:01:00.0: ASIC revision: 79610010
10706 23:26:38.230069 <4>[ 14.384950] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10707 23:26:38.232923 Begin: Loading essential drivers ... done.
10708 23:26:38.239890 Begin: Running /scripts/init-premount ... done.
10709 23:26:38.246210 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10710 23:26:38.252920 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10711 23:26:38.260011 Device /sys/class/net/enx00e04c787aaa found
10712 23:26:38.260618 done.
10713 23:26:38.302711 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10714 23:26:38.338129 <4>[ 14.491562] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10715 23:26:38.441979 <4>[ 14.594706] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10716 23:26:38.546167 <4>[ 14.698427] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10717 23:26:38.649951 <4>[ 14.802413] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10718 23:26:38.754304 <4>[ 14.906277] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10719 23:26:38.858506 <4>[ 15.010270] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10720 23:26:38.961992 <4>[ 15.114163] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10721 23:26:39.066248 <4>[ 15.218191] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10722 23:26:39.170471 <4>[ 15.322451] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10723 23:26:39.263143 <3>[ 15.424195] mt7921e 0000:01:00.0: hardware init failed
10724 23:26:39.320168 IP-Config: no response after 2 secs - giving up
10725 23:26:39.370673 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10726 23:26:39.422926 <6>[ 15.582440] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10727 23:26:40.474272 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10728 23:26:40.481233 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10729 23:26:40.487555 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10730 23:26:40.494422 host : mt8192-asurada-spherion-r0-cbg-0
10731 23:26:40.501133 domain : lava-rack
10732 23:26:40.506901 rootserver: 192.168.201.1 rootpath:
10733 23:26:40.507407 filename :
10734 23:26:40.633033 done.
10735 23:26:40.639596 Begin: Running /scripts/nfs-bottom ... done.
10736 23:26:40.658157 Begin: Running /scripts/init-bottom ... done.
10737 23:26:41.878655 <6>[ 18.038266] NET: Registered PF_INET6 protocol family
10738 23:26:41.882025 <6>[ 18.040078] Segment Routing with IPv6
10739 23:26:41.888510 <6>[ 18.040105] In-situ OAM (IOAM) with IPv6
10740 23:26:42.002575 <30>[ 18.145186] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10741 23:26:42.005770 <30>[ 18.146296] systemd[1]: Detected architecture arm64.
10742 23:26:42.006191
10743 23:26:42.012427 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10744 23:26:42.012863
10745 23:26:42.035082 <30>[ 18.196009] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10746 23:26:42.933892 <30>[ 19.092236] systemd[1]: Queued start job for default target Graphical Interface.
10747 23:26:42.977142 [[0;32m OK [<30>[ 19.135969] systemd[1]: Created slice system-getty.slice.
10748 23:26:42.980497 0m] Created slice [0;1;39msystem-getty.slice[0m.
10749 23:26:43.000327 [[0;32m OK [0m] Created slic<30>[ 19.159002] systemd[1]: Created slice system-modprobe.slice.
10750 23:26:43.002952 e [0;1;39msystem-modprobe.slice[0m.
10751 23:26:43.024011 [[0;32m OK [0m] Created slic<30>[ 19.182824] systemd[1]: Created slice system-serial\x2dgetty.slice.
10752 23:26:43.030067 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10753 23:26:43.048705 [[0;32m OK [0m] Created slic<30>[ 19.207480] systemd[1]: Created slice User and Session Slice.
10754 23:26:43.051663 e [0;1;39mUser and Session Slice[0m.
10755 23:26:43.074561 [[0;32m OK [0m] Started [0;1;39mDispatch Pa<30>[ 19.230320] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10756 23:26:43.077621 ssword …ts to Console Directory Watch[0m.
10757 23:26:43.102270 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.257813] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10758 23:26:43.105084 sword R…uests to Wall Directory Watch[0m.
10759 23:26:43.129647 [[0;32m OK [0m] Reached target [0;1;39mLoca<30>[ 19.281720] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10760 23:26:43.139384 l Encrypted Volu<30>[ 19.281945] systemd[1]: Reached target Local Encrypted Volumes.
10761 23:26:43.139931 mes[0m.
10762 23:26:43.159466 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.318133] systemd[1]: Reached target Paths.
10763 23:26:43.160027 s[0m.
10764 23:26:43.181679 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.337585] systemd[1]: Reached target Remote File Systems.
10765 23:26:43.182245 te File Systems[0m.
10766 23:26:43.203679 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.361996] systemd[1]: Reached target Slices.
10767 23:26:43.204307 es[0m.
10768 23:26:43.222586 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.381623] systemd[1]: Reached target Swap.
10769 23:26:43.223155 [0m.
10770 23:26:43.246582 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.402114] systemd[1]: Listening on initctl Compatibility Named Pipe.
10771 23:26:43.250029 l Compatibility Named Pipe[0m.
10772 23:26:43.259519 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.418317] systemd[1]: Listening on Journal Audit Socket.
10773 23:26:43.262848 l Audit Socket[0m.
10774 23:26:43.283968 [[0;32m OK [0m] Listening on<30>[ 19.443216] systemd[1]: Listening on Journal Socket (/dev/log).
10775 23:26:43.287428 [0;1;39mJournal Socket (/dev/log)[0m.
10776 23:26:43.307615 [[0;32m OK [0m] Listening on<30>[ 19.466928] systemd[1]: Listening on Journal Socket.
10777 23:26:43.310987 [0;1;39mJournal Socket[0m.
10778 23:26:43.328529 [[0;32m OK [0m] Listening on<30>[ 19.487629] systemd[1]: Listening on Network Service Netlink Socket.
10779 23:26:43.334996 [0;1;39mNetwork Service Netlink Socket[0m.
10780 23:26:43.353705 [[0;32m OK [<30>[ 19.512897] systemd[1]: Listening on udev Control Socket.
10781 23:26:43.357185 0m] Listening on [0;1;39mudev Control Socket[0m.
10782 23:26:43.375632 [[0;32m OK [0m] Listening on<30>[ 19.534714] systemd[1]: Listening on udev Kernel Socket.
10783 23:26:43.378790 [0;1;39mudev Kernel Socket[0m.
10784 23:26:43.434150 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.590050] systemd[1]: Mounting Huge Pages File System...
10785 23:26:43.434786 m[0m...
10786 23:26:43.452533 Mounting [0;1;39mPOSIX<30>[ 19.611763] systemd[1]: Mounting POSIX Message Queue File System...
10787 23:26:43.455502 Message Queue File System[0m...
10788 23:26:43.482125 Mounting [0;1;39mKernel Debug File Sys<30>[ 19.637822] systemd[1]: Mounting Kernel Debug File System...
10789 23:26:43.482551 tem[0m...
10790 23:26:43.506088 <30>[ 19.662150] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10791 23:26:43.515668 <30>[ 19.673726] systemd[1]: Starting Create list of static device nodes for the current kernel...
10792 23:26:43.522306 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10793 23:26:43.554214 Starting [0;1;39mLoad Kernel Module co<30>[ 19.710040] systemd[1]: Starting Load Kernel Module configfs...
10794 23:26:43.554810 nfigfs[0m...
10795 23:26:43.578338 Starting [0;1;39mLoad Kernel Module dr<30>[ 19.734310] systemd[1]: Starting Load Kernel Module drm...
10796 23:26:43.578819 m[0m...
10797 23:26:43.599107 Starting [0;1;39mLoad <30>[ 19.758605] systemd[1]: Starting Load Kernel Module fuse...
10798 23:26:43.602565 Kernel Module fuse[0m...
10799 23:26:43.637337 <30>[ 19.797017] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10800 23:26:43.643778 <6>[ 19.797030] fuse: init (API version 7.37)
10801 23:26:43.690798 Starting [0;1;39mJourn<30>[ 19.850437] systemd[1]: Starting Journal Service...
10802 23:26:43.690945 al Service[0m...
10803 23:26:43.719657 Starting [0;1;39mLoad <30>[ 19.879168] systemd[1]: Starting Load Kernel Modules...
10804 23:26:43.722979 Kernel Modules[0m...
10805 23:26:43.747809 Starting [0;1;39mRemou<30>[ 19.907540] systemd[1]: Starting Remount Root and Kernel File Systems...
10806 23:26:43.754639 nt Root and Kernel File Systems[0m...
10807 23:26:43.780633 Startin<30>[ 19.939911] systemd[1]: Starting Coldplug All udev Devices...
10808 23:26:43.783716 g [0;1;39mColdplug All udev Devices[0m...
10809 23:26:43.817874 [[0;32m OK [<30>[ 19.980087] systemd[1]: Mounted Huge Pages File System.
10810 23:26:43.830977 0m] Mounted [0;<3>[ 19.985764] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10811 23:26:43.831148 1;39mHuge Pages File System[0m.
10812 23:26:43.855150 [[0;32m OK [0m] Mounted [0;<30>[ 20.014670] systemd[1]: Mounted POSIX Message Queue File System.
10813 23:26:43.864994 1;39mPOSIX Messa<3>[ 20.018972] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10814 23:26:43.868264 ge Queue File System[0m.
10815 23:26:43.891023 [[0;32m OK [0m] Mounted [0;1;39mKernel Debu<30>[ 20.050076] systemd[1]: Mounted Kernel Debug File System.
10816 23:26:43.893896 g File System[0m.
10817 23:26:43.905227 <3>[ 20.064467] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10818 23:26:43.917454 <30>[ 20.077101] systemd[1]: Finished Create list of static device nodes for the current kernel.
10819 23:26:43.928072 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10820 23:26:43.938016 <3>[ 20.096639] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10821 23:26:43.946287 <30>[ 20.108137] systemd[1]: modprobe@configfs.service: Succeeded.
10822 23:26:43.953306 <30>[ 20.109459] systemd[1]: Finished Load Kernel Module configfs.
10823 23:26:43.963430 <3>[ 20.120911] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10824 23:26:43.969963 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10825 23:26:43.985852 [[0;32m OK [<30>[ 20.147149] systemd[1]: modprobe@drm.service: Succeeded.
10826 23:26:43.995518 0m] Finished [0<30>[ 20.148392] systemd[1]: Finished Load Kernel Module drm.
10827 23:26:44.002617 <3>[ 20.151442] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 23:26:44.005252 ;1;39mLoad Kernel Module drm[0m.
10829 23:26:44.021370 <3>[ 20.180603] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10830 23:26:44.032616 [[0;32m OK [0m] Finished [0<30>[ 20.191230] systemd[1]: modprobe@fuse.service: Succeeded.
10831 23:26:44.038974 ;1;39mLoad Kerne<30>[ 20.191886] systemd[1]: Finished Load Kernel Module fuse.
10832 23:26:44.048970 l Module fuse[0<3>[ 20.207378] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10833 23:26:44.049109 m.
10834 23:26:44.069220 <3>[ 20.228101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 23:26:44.080494 [[0;32m OK [<30>[ 20.240251] systemd[1]: Finished Load Kernel Modules.
10836 23:26:44.083697 0m] Finished [0;1;39mLoad Kernel Modules[0m.
10837 23:26:44.097625 <3>[ 20.257278] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10838 23:26:44.108671 [[0;32m OK [<30>[ 20.268003] systemd[1]: Finished Remount Root and Kernel File Systems.
10839 23:26:44.115367 0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10840 23:26:44.171003 [[0;32m OK [0m] Started [0;<30>[ 20.330948] systemd[1]: Started Journal Service.
10841 23:26:44.174313 1;39mJournal Service[0m.
10842 23:26:44.194902 Mounting [0;1;39mFUSE Control File System[0m...
10843 23:26:44.214521 Mounting [0;1;39mKernel Configuration File System[0m...
10844 23:26:44.237511 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10845 23:26:44.258663 Starting [0;1;39mLoad/Save Random Seed[0m...
10846 23:26:44.281476 <46>[ 20.439352] systemd-journald[305]: Received client request to flush runtime journal.
10847 23:26:44.287761 Starting [0;1;39mApply Kernel Variables[0m...
10848 23:26:44.308732 Starting [0;1;39mCreate System Users[0m...
10849 23:26:44.326737 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10850 23:26:44.343091 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10851 23:26:44.361190 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10852 23:26:44.384025 <4>[ 20.535578] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10853 23:26:44.394220 <3>[ 20.535592] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10854 23:26:44.400303 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10855 23:26:44.414235 See 'systemctl status systemd-udev-trigger.service' for details.
10856 23:26:45.046401 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10857 23:26:45.708653 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10858 23:26:45.742162 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10859 23:26:45.791257 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10860 23:26:45.860917 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10861 23:26:45.868071 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10862 23:26:45.886268 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10863 23:26:45.943023 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10864 23:26:45.966509 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10865 23:26:46.133884 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10866 23:26:46.192494 Starting [0;1;39mNetwork Service[0m...
10867 23:26:46.211619 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10868 23:26:46.241170 Starting [0;1;39mNetwork Time Synchronization[0m...
10869 23:26:46.258312 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10870 23:26:46.326191 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10871 23:26:46.521762 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10872 23:26:46.543893 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10873 23:26:46.602442 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10874 23:26:46.816067 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10875 23:26:46.833364 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10876 23:26:46.895389 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10877 23:26:46.924887 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10878 23:26:46.938851 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10879 23:26:46.958654 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10880 23:26:46.975042 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10881 23:26:47.010477 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10882 23:26:47.029724 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10883 23:26:47.042087 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10884 23:26:47.057956 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10885 23:26:47.080574 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10886 23:26:47.103958 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10887 23:26:47.124395 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10888 23:26:47.143638 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10889 23:26:47.157886 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10890 23:26:47.207713 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10891 23:26:47.222385 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10892 23:26:47.238329 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10893 23:26:47.290429 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10894 23:26:47.379053 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10895 23:26:47.481673 Starting [0;1;39mUser Login Management[0m...
10896 23:26:47.520416 Starting [0;1;39mNetwork Name Resolution[0m...
10897 23:26:47.647051 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10898 23:26:47.707349 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10899 23:26:48.298757 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10900 23:26:48.319701 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10901 23:26:48.341886 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10902 23:26:48.396015 Starting [0;1;39mPermit User Sessions[0m...
10903 23:26:48.426847 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10904 23:26:48.479583 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10905 23:26:48.527728 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10906 23:26:48.543554 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10907 23:26:48.558484 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10908 23:26:48.575667 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10909 23:26:48.630430 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10910 23:26:48.694619 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10911 23:26:48.756289
10912 23:26:48.756476
10913 23:26:48.759724 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10914 23:26:48.759816
10915 23:26:48.762599 debian-bullseye-arm64 login: root (automatic login)
10916 23:26:48.762688
10917 23:26:48.762754
10918 23:26:49.080518 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10919 23:26:49.080668
10920 23:26:49.086897 The programs included with the Debian GNU/Linux system are free software;
10921 23:26:49.093597 the exact distribution terms for each program are described in the
10922 23:26:49.096850 individual files in /usr/share/doc/*/copyright.
10923 23:26:49.096976
10924 23:26:49.103987 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10925 23:26:49.107402 permitted by applicable law.
10926 23:26:50.057515 Matched prompt #10: / #
10928 23:26:50.057834 Setting prompt string to ['/ #']
10929 23:26:50.057926 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10931 23:26:50.058114 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10932 23:26:50.058201 start: 2.2.6 expect-shell-connection (timeout 00:03:35) [common]
10933 23:26:50.058269 Setting prompt string to ['/ #']
10934 23:26:50.058328 Forcing a shell prompt, looking for ['/ #']
10936 23:26:50.108525 / #
10937 23:26:50.108702 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10938 23:26:50.108801 Waiting using forced prompt support (timeout 00:02:30)
10939 23:26:50.114374
10940 23:26:50.114699 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10941 23:26:50.114799 start: 2.2.7 export-device-env (timeout 00:03:35) [common]
10943 23:26:50.215146 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6'
10944 23:26:50.220661 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172424/extract-nfsrootfs-19ngpsl6'
10946 23:26:50.321240 / # export NFS_SERVER_IP='192.168.201.1'
10947 23:26:50.326812 export NFS_SERVER_IP='192.168.201.1'
10948 23:26:50.327099 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10949 23:26:50.327195 end: 2.2 depthcharge-retry (duration 00:01:25) [common]
10950 23:26:50.327286 end: 2 depthcharge-action (duration 00:01:25) [common]
10951 23:26:50.327376 start: 3 lava-test-retry (timeout 00:07:55) [common]
10952 23:26:50.327461 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
10953 23:26:50.327535 Using namespace: common
10955 23:26:50.427852 / # #
10956 23:26:50.428029 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10957 23:26:50.433224 #
10958 23:26:50.433490 Using /lava-12172424
10960 23:26:50.533860 / # export SHELL=/bin/bash
10961 23:26:50.540049 export SHELL=/bin/bash
10963 23:26:50.640585 / # . /lava-12172424/environment
10964 23:26:50.646795 . /lava-12172424/environment
10966 23:26:50.752046 / # /lava-12172424/bin/lava-test-runner /lava-12172424/0
10967 23:26:50.752198 Test shell timeout: 10s (minimum of the action and connection timeout)
10968 23:26:50.756986 /lava-12172424/bin/lava-test-runner /lava-12172424/0
10969 23:26:51.006195 + export TESTRUN_ID=0_timesync-off
10970 23:26:51.009462 + TESTRUN_ID=0_timesync-off
10971 23:26:51.013047 + cd /lava-12172424/0/tests/0_timesync-off
10972 23:26:51.016088 ++ cat uuid
10973 23:26:51.016171 + UUID=12172424_1.6.2.3.1
10974 23:26:51.020222 + set +x
10975 23:26:51.022817 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12172424_1.6.2.3.1>
10976 23:26:51.023079 Received signal: <STARTRUN> 0_timesync-off 12172424_1.6.2.3.1
10977 23:26:51.023155 Starting test lava.0_timesync-off (12172424_1.6.2.3.1)
10978 23:26:51.023240 Skipping test definition patterns.
10979 23:26:51.026045 + systemctl stop systemd-timesyncd
10980 23:26:51.123268 + set +x
10981 23:26:51.126489 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12172424_1.6.2.3.1>
10982 23:26:51.126788 Received signal: <ENDRUN> 0_timesync-off 12172424_1.6.2.3.1
10983 23:26:51.126897 Ending use of test pattern.
10984 23:26:51.126974 Ending test lava.0_timesync-off (12172424_1.6.2.3.1), duration 0.10
10986 23:26:51.177262 + export TESTRUN_ID=1_kselftest-dt
10987 23:26:51.180623 + TESTRUN_ID=1_kselftest-dt
10988 23:26:51.183825 + cd /lava-12172424/0/tests/1_kselftest-dt
10989 23:26:51.187182 ++ cat uuid
10990 23:26:51.187263 + UUID=12172424_1.6.2.3.5
10991 23:26:51.190435 + set +x
10992 23:26:51.194086 <LAVA_SIGNAL_STARTRUN 1_kselftest-dt 12172424_1.6.2.3.5>
10993 23:26:51.194342 Received signal: <STARTRUN> 1_kselftest-dt 12172424_1.6.2.3.5
10994 23:26:51.194411 Starting test lava.1_kselftest-dt (12172424_1.6.2.3.5)
10995 23:26:51.194491 Skipping test definition patterns.
10996 23:26:51.197044 + cd ./automated/linux/kselftest/
10997 23:26:51.223638 + ./kselftest.sh -c dt -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
10998 23:26:51.249554 INFO: install_deps skipped
10999 23:26:51.354263 --2023-12-03 23:24:37-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11000 23:26:51.363049 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11001 23:26:51.495370 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11002 23:26:51.628169 HTTP request sent, awaiting response... 200 OK
11003 23:26:51.631754 Length: 2966880 (2.8M) [application/octet-stream]
11004 23:26:51.635299 Saving to: 'kselftest.tar.xz'
11005 23:26:51.635386
11006 23:26:51.635450
11007 23:26:51.893947 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11008 23:26:52.158740 kselftest.tar.xz 1%[ ] 49.22K 186KB/s
11009 23:26:52.474193 kselftest.tar.xz 7%[> ] 214.67K 406KB/s
11010 23:26:52.751299 kselftest.tar.xz 28%[====> ] 831.20K 984KB/s
11011 23:26:52.873457 kselftest.tar.xz 69%[============> ] 1.96M 1.75MB/s
11012 23:26:52.880062 kselftest.tar.xz 100%[===================>] 2.83M 2.27MB/s in 1.2s
11013 23:26:52.880149
11014 23:26:53.137740 2023-12-03 23:24:39 (2.27 MB/s) - 'kselftest.tar.xz' saved [2966880/2966880]
11015 23:26:53.137886
11016 23:26:58.669046 skiplist:
11017 23:26:58.672831 ========================================
11018 23:26:58.675934 ========================================
11019 23:26:58.738826 ============== Tests to run ===============
11020 23:26:58.742038 ===========End Tests to run ===============
11021 23:26:58.745453 shardfile-dt fail
11022 23:26:58.768074 ./kselftest.sh: 131: cannot open /lava-12172424/0/tests/1_kselftest-dt/automated/linux/kselftest/output/kselftest.txt: No such file
11023 23:26:58.771156 + ../../utils/send-to-lava.sh ./output/result.txt
11024 23:26:58.834201 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-dt RESULT=fail>
11025 23:26:58.834368 + set +x
11026 23:26:58.834648 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-dt RESULT=fail
11028 23:26:58.841113 <LAVA_SIGNAL_ENDRUN 1_kselftest-dt 12172424_1.6.2.3.5>
11029 23:26:58.841397 Received signal: <ENDRUN> 1_kselftest-dt 12172424_1.6.2.3.5
11030 23:26:58.841496 Ending use of test pattern.
11031 23:26:58.841590 Ending test lava.1_kselftest-dt (12172424_1.6.2.3.5), duration 7.65
11033 23:26:58.841845 ok: lava_test_shell seems to have completed
11034 23:26:58.841934 shardfile-dt: fail
11035 23:26:58.842018 end: 3.1 lava-test-shell (duration 00:00:09) [common]
11036 23:26:58.842097 end: 3 lava-test-retry (duration 00:00:09) [common]
11037 23:26:58.842182 start: 4 finalize (timeout 00:07:46) [common]
11038 23:26:58.842271 start: 4.1 power-off (timeout 00:00:30) [common]
11039 23:26:58.842422 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11040 23:26:58.918346 >> Command sent successfully.
11041 23:26:58.920839 Returned 0 in 0 seconds
11042 23:26:59.021220 end: 4.1 power-off (duration 00:00:00) [common]
11044 23:26:59.021734 start: 4.2 read-feedback (timeout 00:07:46) [common]
11046 23:26:59.022344 Listened to connection for namespace 'common' for up to 1s
11047 23:27:00.022987 Finalising connection for namespace 'common'
11048 23:27:00.023169 Disconnecting from shell: Finalise
11049 23:27:00.023252 / #
11050 23:27:00.123611 end: 4.2 read-feedback (duration 00:00:01) [common]
11051 23:27:00.123797 end: 4 finalize (duration 00:00:01) [common]
11052 23:27:00.123912 Cleaning after the job
11053 23:27:00.124009 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/ramdisk
11054 23:27:00.126894 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/kernel
11055 23:27:00.139503 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/dtb
11056 23:27:00.139722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/nfsrootfs
11057 23:27:00.231814 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172424/tftp-deploy-1ans5gei/modules
11058 23:27:00.239526 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172424
11059 23:27:00.879265 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172424
11060 23:27:00.879451 Job finished correctly