Boot log: mt8192-asurada-spherion-r0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
- Kernel Errors: 34
- Errors: 0
1 23:41:44.298150 lava-dispatcher, installed at version: 2023.10
2 23:41:44.298373 start: 0 validate
3 23:41:44.298513 Start time: 2023-12-03 23:41:44.298506+00:00 (UTC)
4 23:41:44.298638 Using caching service: 'http://localhost/cache/?uri=%s'
5 23:41:44.298773 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Finitrd.cpio.gz exists
6 23:41:44.581450 Using caching service: 'http://localhost/cache/?uri=%s'
7 23:41:44.582228 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 23:41:44.852431 Using caching service: 'http://localhost/cache/?uri=%s'
9 23:41:44.853272 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 23:41:45.115167 Using caching service: 'http://localhost/cache/?uri=%s'
11 23:41:45.115955 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230623.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 23:41:45.389896 Using caching service: 'http://localhost/cache/?uri=%s'
13 23:41:45.390694 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip-gitlab%2Fci-pavel-linux-test%2Fv6.1.64-cip10-rt5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 23:41:45.657494 validate duration: 1.36
16 23:41:45.657798 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 23:41:45.657898 start: 1.1 download-retry (timeout 00:10:00) [common]
18 23:41:45.657986 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 23:41:45.658118 Not decompressing ramdisk as can be used compressed.
20 23:41:45.658207 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/initrd.cpio.gz
21 23:41:45.658273 saving as /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/ramdisk/initrd.cpio.gz
22 23:41:45.658340 total size: 4665395 (4 MB)
23 23:41:45.659386 progress 0 % (0 MB)
24 23:41:45.660811 progress 5 % (0 MB)
25 23:41:45.662114 progress 10 % (0 MB)
26 23:41:45.663341 progress 15 % (0 MB)
27 23:41:45.664565 progress 20 % (0 MB)
28 23:41:45.665833 progress 25 % (1 MB)
29 23:41:45.667095 progress 30 % (1 MB)
30 23:41:45.668303 progress 35 % (1 MB)
31 23:41:45.669509 progress 40 % (1 MB)
32 23:41:45.670915 progress 45 % (2 MB)
33 23:41:45.672118 progress 50 % (2 MB)
34 23:41:45.673323 progress 55 % (2 MB)
35 23:41:45.674566 progress 60 % (2 MB)
36 23:41:45.675765 progress 65 % (2 MB)
37 23:41:45.676967 progress 70 % (3 MB)
38 23:41:45.678216 progress 75 % (3 MB)
39 23:41:45.679421 progress 80 % (3 MB)
40 23:41:45.680785 progress 85 % (3 MB)
41 23:41:45.682036 progress 90 % (4 MB)
42 23:41:45.683240 progress 95 % (4 MB)
43 23:41:45.684463 progress 100 % (4 MB)
44 23:41:45.684615 4 MB downloaded in 0.03 s (169.33 MB/s)
45 23:41:45.684752 end: 1.1.1 http-download (duration 00:00:00) [common]
47 23:41:45.684987 end: 1.1 download-retry (duration 00:00:00) [common]
48 23:41:45.685073 start: 1.2 download-retry (timeout 00:10:00) [common]
49 23:41:45.685155 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 23:41:45.685278 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 23:41:45.685353 saving as /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/kernel/Image
52 23:41:45.685414 total size: 49172992 (46 MB)
53 23:41:45.685476 No compression specified
54 23:41:45.686550 progress 0 % (0 MB)
55 23:41:45.699268 progress 5 % (2 MB)
56 23:41:45.712268 progress 10 % (4 MB)
57 23:41:45.725136 progress 15 % (7 MB)
58 23:41:45.737992 progress 20 % (9 MB)
59 23:41:45.750898 progress 25 % (11 MB)
60 23:41:45.763724 progress 30 % (14 MB)
61 23:41:45.776418 progress 35 % (16 MB)
62 23:41:45.789098 progress 40 % (18 MB)
63 23:41:45.801777 progress 45 % (21 MB)
64 23:41:45.814639 progress 50 % (23 MB)
65 23:41:45.827551 progress 55 % (25 MB)
66 23:41:45.840518 progress 60 % (28 MB)
67 23:41:45.853553 progress 65 % (30 MB)
68 23:41:45.866251 progress 70 % (32 MB)
69 23:41:45.878909 progress 75 % (35 MB)
70 23:41:45.891597 progress 80 % (37 MB)
71 23:41:45.904268 progress 85 % (39 MB)
72 23:41:45.917052 progress 90 % (42 MB)
73 23:41:45.929699 progress 95 % (44 MB)
74 23:41:45.942283 progress 100 % (46 MB)
75 23:41:45.942493 46 MB downloaded in 0.26 s (182.42 MB/s)
76 23:41:45.942646 end: 1.2.1 http-download (duration 00:00:00) [common]
78 23:41:45.942877 end: 1.2 download-retry (duration 00:00:00) [common]
79 23:41:45.942969 start: 1.3 download-retry (timeout 00:10:00) [common]
80 23:41:45.943056 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 23:41:45.943196 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 23:41:45.943266 saving as /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/dtb/mt8192-asurada-spherion-r0.dtb
83 23:41:45.943330 total size: 47278 (0 MB)
84 23:41:45.943392 No compression specified
85 23:41:45.944532 progress 69 % (0 MB)
86 23:41:45.944808 progress 100 % (0 MB)
87 23:41:45.944966 0 MB downloaded in 0.00 s (27.59 MB/s)
88 23:41:45.945090 end: 1.3.1 http-download (duration 00:00:00) [common]
90 23:41:45.945318 end: 1.3 download-retry (duration 00:00:00) [common]
91 23:41:45.945407 start: 1.4 download-retry (timeout 00:10:00) [common]
92 23:41:45.945491 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 23:41:45.945651 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230623.0/arm64/full.rootfs.tar.xz
94 23:41:45.945721 saving as /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/nfsrootfs/full.rootfs.tar
95 23:41:45.945783 total size: 200813988 (191 MB)
96 23:41:45.945846 Using unxz to decompress xz
97 23:41:45.950094 progress 0 % (0 MB)
98 23:41:46.475830 progress 5 % (9 MB)
99 23:41:46.983986 progress 10 % (19 MB)
100 23:41:47.566233 progress 15 % (28 MB)
101 23:41:47.936409 progress 20 % (38 MB)
102 23:41:48.258629 progress 25 % (47 MB)
103 23:41:48.843195 progress 30 % (57 MB)
104 23:41:49.392107 progress 35 % (67 MB)
105 23:41:49.977468 progress 40 % (76 MB)
106 23:41:50.532179 progress 45 % (86 MB)
107 23:41:51.109151 progress 50 % (95 MB)
108 23:41:51.733482 progress 55 % (105 MB)
109 23:41:52.391329 progress 60 % (114 MB)
110 23:41:52.507921 progress 65 % (124 MB)
111 23:41:52.646274 progress 70 % (134 MB)
112 23:41:52.741705 progress 75 % (143 MB)
113 23:41:52.811741 progress 80 % (153 MB)
114 23:41:52.879630 progress 85 % (162 MB)
115 23:41:52.979425 progress 90 % (172 MB)
116 23:41:53.254408 progress 95 % (181 MB)
117 23:41:53.824131 progress 100 % (191 MB)
118 23:41:53.829389 191 MB downloaded in 7.88 s (24.29 MB/s)
119 23:41:53.829698 end: 1.4.1 http-download (duration 00:00:08) [common]
121 23:41:53.829962 end: 1.4 download-retry (duration 00:00:08) [common]
122 23:41:53.830052 start: 1.5 download-retry (timeout 00:09:52) [common]
123 23:41:53.830138 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 23:41:53.830296 downloading http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 23:41:53.830367 saving as /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/modules/modules.tar
126 23:41:53.830430 total size: 8614132 (8 MB)
127 23:41:53.830495 Using unxz to decompress xz
128 23:41:53.834755 progress 0 % (0 MB)
129 23:41:53.855603 progress 5 % (0 MB)
130 23:41:53.879319 progress 10 % (0 MB)
131 23:41:53.902578 progress 15 % (1 MB)
132 23:41:53.925630 progress 20 % (1 MB)
133 23:41:53.949408 progress 25 % (2 MB)
134 23:41:53.974624 progress 30 % (2 MB)
135 23:41:54.000373 progress 35 % (2 MB)
136 23:41:54.023496 progress 40 % (3 MB)
137 23:41:54.047697 progress 45 % (3 MB)
138 23:41:54.082966 progress 50 % (4 MB)
139 23:41:54.117452 progress 55 % (4 MB)
140 23:41:54.142136 progress 60 % (4 MB)
141 23:41:54.167354 progress 65 % (5 MB)
142 23:41:54.193727 progress 70 % (5 MB)
143 23:41:54.216676 progress 75 % (6 MB)
144 23:41:54.243752 progress 80 % (6 MB)
145 23:41:54.271395 progress 85 % (7 MB)
146 23:41:54.295997 progress 90 % (7 MB)
147 23:41:54.325238 progress 95 % (7 MB)
148 23:41:54.352869 progress 100 % (8 MB)
149 23:41:54.359128 8 MB downloaded in 0.53 s (15.54 MB/s)
150 23:41:54.359377 end: 1.5.1 http-download (duration 00:00:01) [common]
152 23:41:54.359640 end: 1.5 download-retry (duration 00:00:01) [common]
153 23:41:54.359736 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 23:41:54.359834 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 23:41:57.872437 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq
156 23:41:57.872642 end: 1.6.1 extract-nfsrootfs (duration 00:00:04) [common]
157 23:41:57.872747 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 23:41:57.872917 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0
159 23:41:57.873053 makedir: /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin
160 23:41:57.873157 makedir: /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/tests
161 23:41:57.873258 makedir: /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/results
162 23:41:57.873361 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-add-keys
163 23:41:57.873513 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-add-sources
164 23:41:57.873765 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-background-process-start
165 23:41:57.873900 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-background-process-stop
166 23:41:57.874030 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-common-functions
167 23:41:57.874158 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-echo-ipv4
168 23:41:57.874287 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-install-packages
169 23:41:57.874413 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-installed-packages
170 23:41:57.874539 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-os-build
171 23:41:57.874667 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-probe-channel
172 23:41:57.874792 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-probe-ip
173 23:41:57.874919 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-target-ip
174 23:41:57.875045 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-target-mac
175 23:41:57.875174 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-target-storage
176 23:41:57.875304 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-case
177 23:41:57.875433 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-event
178 23:41:57.875559 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-feedback
179 23:41:57.875686 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-raise
180 23:41:57.875814 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-reference
181 23:41:57.875942 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-runner
182 23:41:57.876070 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-set
183 23:41:57.876198 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-test-shell
184 23:41:57.876326 Updating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-add-keys (debian)
185 23:41:57.876483 Updating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-add-sources (debian)
186 23:41:57.876628 Updating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-install-packages (debian)
187 23:41:57.876771 Updating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-installed-packages (debian)
188 23:41:57.876913 Updating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/bin/lava-os-build (debian)
189 23:41:57.877037 Creating /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/environment
190 23:41:57.877135 LAVA metadata
191 23:41:57.877208 - LAVA_JOB_ID=12172464
192 23:41:57.877272 - LAVA_DISPATCHER_IP=192.168.201.1
193 23:41:57.877375 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 23:41:57.877442 skipped lava-vland-overlay
195 23:41:57.877517 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 23:41:57.877605 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 23:41:57.877667 skipped lava-multinode-overlay
198 23:41:57.877741 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 23:41:57.877819 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 23:41:57.877898 Loading test definitions
201 23:41:57.877991 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 23:41:57.878065 Using /lava-12172464 at stage 0
203 23:41:57.878349 uuid=12172464_1.6.2.3.1 testdef=None
204 23:41:57.878437 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 23:41:57.878522 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 23:41:57.878983 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 23:41:57.879201 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 23:41:57.879756 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 23:41:57.879985 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 23:41:57.880547 runner path: /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/0/tests/0_timesync-off test_uuid 12172464_1.6.2.3.1
213 23:41:57.880705 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 23:41:57.880932 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 23:41:57.881005 Using /lava-12172464 at stage 0
217 23:41:57.881103 Fetching tests from https://github.com/kernelci/test-definitions.git
218 23:41:57.881182 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/0/tests/1_kselftest-tpm2'
219 23:42:03.468659 Running '/usr/bin/git checkout kernelci.org
220 23:42:03.617260 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 23:42:03.618024 uuid=12172464_1.6.2.3.5 testdef=None
222 23:42:03.618179 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 23:42:03.618430 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 23:42:03.619199 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 23:42:03.619434 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 23:42:03.620420 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 23:42:03.620656 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 23:42:03.621606 runner path: /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/0/tests/1_kselftest-tpm2 test_uuid 12172464_1.6.2.3.5
232 23:42:03.621701 BOARD='mt8192-asurada-spherion-r0'
233 23:42:03.621767 BRANCH='cip-gitlab'
234 23:42:03.621830 SKIPFILE='/dev/null'
235 23:42:03.621890 SKIP_INSTALL='True'
236 23:42:03.621948 TESTPROG_URL='http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 23:42:03.622007 TST_CASENAME=''
238 23:42:03.622064 TST_CMDFILES='tpm2'
239 23:42:03.622208 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 23:42:03.622414 Creating lava-test-runner.conf files
242 23:42:03.622480 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12172464/lava-overlay-77tg5be0/lava-12172464/0 for stage 0
243 23:42:03.622575 - 0_timesync-off
244 23:42:03.622648 - 1_kselftest-tpm2
245 23:42:03.622745 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 23:42:03.622836 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 23:42:11.101961 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 23:42:11.102126 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:35) [common]
249 23:42:11.102222 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 23:42:11.102323 end: 1.6.2 lava-overlay (duration 00:00:13) [common]
251 23:42:11.102412 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:35) [common]
252 23:42:11.222136 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 23:42:11.222536 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 23:42:11.222661 extracting modules file /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq
255 23:42:11.446384 extracting modules file /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12172464/extract-overlay-ramdisk-ns8adsr4/ramdisk
256 23:42:11.676369 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 23:42:11.676547 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 23:42:11.676693 [common] Applying overlay to NFS
259 23:42:11.676779 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12172464/compress-overlay-fmhojn06/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq
260 23:42:12.596455 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 23:42:12.596656 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 23:42:12.596759 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 23:42:12.596850 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 23:42:12.596932 Building ramdisk /var/lib/lava/dispatcher/tmp/12172464/extract-overlay-ramdisk-ns8adsr4/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12172464/extract-overlay-ramdisk-ns8adsr4/ramdisk
265 23:42:12.939094 >> 119416 blocks
266 23:42:14.885790 rename /var/lib/lava/dispatcher/tmp/12172464/extract-overlay-ramdisk-ns8adsr4/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/ramdisk/ramdisk.cpio.gz
267 23:42:14.886254 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 23:42:14.886386 start: 1.6.8 prepare-kernel (timeout 00:09:31) [common]
269 23:42:14.886488 start: 1.6.8.1 prepare-fit (timeout 00:09:31) [common]
270 23:42:14.886593 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/kernel/Image'
271 23:42:26.707983 Returned 0 in 11 seconds
272 23:42:26.809008 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/kernel/image.itb
273 23:42:27.175505 output: FIT description: Kernel Image image with one or more FDT blobs
274 23:42:27.175897 output: Created: Sun Dec 3 23:42:27 2023
275 23:42:27.175978 output: Image 0 (kernel-1)
276 23:42:27.176048 output: Description:
277 23:42:27.176114 output: Created: Sun Dec 3 23:42:27 2023
278 23:42:27.176179 output: Type: Kernel Image
279 23:42:27.176242 output: Compression: lzma compressed
280 23:42:27.176302 output: Data Size: 11049348 Bytes = 10790.38 KiB = 10.54 MiB
281 23:42:27.176363 output: Architecture: AArch64
282 23:42:27.176424 output: OS: Linux
283 23:42:27.176479 output: Load Address: 0x00000000
284 23:42:27.176538 output: Entry Point: 0x00000000
285 23:42:27.176596 output: Hash algo: crc32
286 23:42:27.176654 output: Hash value: c85ea8f0
287 23:42:27.176713 output: Image 1 (fdt-1)
288 23:42:27.176767 output: Description: mt8192-asurada-spherion-r0
289 23:42:27.176820 output: Created: Sun Dec 3 23:42:27 2023
290 23:42:27.176875 output: Type: Flat Device Tree
291 23:42:27.176930 output: Compression: uncompressed
292 23:42:27.176984 output: Data Size: 47278 Bytes = 46.17 KiB = 0.05 MiB
293 23:42:27.177038 output: Architecture: AArch64
294 23:42:27.177092 output: Hash algo: crc32
295 23:42:27.177145 output: Hash value: cc4352de
296 23:42:27.177199 output: Image 2 (ramdisk-1)
297 23:42:27.177251 output: Description: unavailable
298 23:42:27.177305 output: Created: Sun Dec 3 23:42:27 2023
299 23:42:27.177359 output: Type: RAMDisk Image
300 23:42:27.177412 output: Compression: Unknown Compression
301 23:42:27.177466 output: Data Size: 17795402 Bytes = 17378.32 KiB = 16.97 MiB
302 23:42:27.177521 output: Architecture: AArch64
303 23:42:27.177579 output: OS: Linux
304 23:42:27.177676 output: Load Address: unavailable
305 23:42:27.177730 output: Entry Point: unavailable
306 23:42:27.177783 output: Hash algo: crc32
307 23:42:27.177836 output: Hash value: 85430062
308 23:42:27.177890 output: Default Configuration: 'conf-1'
309 23:42:27.177943 output: Configuration 0 (conf-1)
310 23:42:27.177996 output: Description: mt8192-asurada-spherion-r0
311 23:42:27.178049 output: Kernel: kernel-1
312 23:42:27.178103 output: Init Ramdisk: ramdisk-1
313 23:42:27.178156 output: FDT: fdt-1
314 23:42:27.178209 output: Loadables: kernel-1
315 23:42:27.178262 output:
316 23:42:27.178468 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 23:42:27.178571 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 23:42:27.178672 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 23:42:27.178764 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 23:42:27.178845 No LXC device requested
321 23:42:27.178926 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 23:42:27.179009 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 23:42:27.179087 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 23:42:27.179156 Checking files for TFTP limit of 4294967296 bytes.
325 23:42:27.179670 end: 1 tftp-deploy (duration 00:00:42) [common]
326 23:42:27.179773 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 23:42:27.179871 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 23:42:27.180017 substitutions:
329 23:42:27.180090 - {DTB}: 12172464/tftp-deploy-kxi0e2kd/dtb/mt8192-asurada-spherion-r0.dtb
330 23:42:27.180157 - {INITRD}: 12172464/tftp-deploy-kxi0e2kd/ramdisk/ramdisk.cpio.gz
331 23:42:27.180218 - {KERNEL}: 12172464/tftp-deploy-kxi0e2kd/kernel/Image
332 23:42:27.180277 - {LAVA_MAC}: None
333 23:42:27.180335 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq
334 23:42:27.180392 - {NFS_SERVER_IP}: 192.168.201.1
335 23:42:27.180448 - {PRESEED_CONFIG}: None
336 23:42:27.180504 - {PRESEED_LOCAL}: None
337 23:42:27.180560 - {RAMDISK}: 12172464/tftp-deploy-kxi0e2kd/ramdisk/ramdisk.cpio.gz
338 23:42:27.180615 - {ROOT_PART}: None
339 23:42:27.180670 - {ROOT}: None
340 23:42:27.180726 - {SERVER_IP}: 192.168.201.1
341 23:42:27.180780 - {TEE}: None
342 23:42:27.180835 Parsed boot commands:
343 23:42:27.180889 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 23:42:27.181082 Parsed boot commands: tftpboot 192.168.201.1 12172464/tftp-deploy-kxi0e2kd/kernel/image.itb 12172464/tftp-deploy-kxi0e2kd/kernel/cmdline
345 23:42:27.181170 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 23:42:27.181256 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 23:42:27.181350 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 23:42:27.181433 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 23:42:27.181503 Not connected, no need to disconnect.
350 23:42:27.181584 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 23:42:27.181713 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 23:42:27.181784 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh mt8192-asurada-spherion-r0-cbg-0'
353 23:42:27.185851 Setting prompt string to ['lava-test: # ']
354 23:42:27.186229 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 23:42:27.186344 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 23:42:27.186449 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 23:42:27.186539 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 23:42:27.186738 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 23:42:32.334897 >> Command sent successfully.
360 23:42:32.345861 Returned 0 in 5 seconds
361 23:42:32.447087 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 23:42:32.448479 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 23:42:32.448988 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 23:42:32.449441 Setting prompt string to 'Starting depthcharge on Spherion...'
366 23:42:32.449856 Changing prompt to 'Starting depthcharge on Spherion...'
367 23:42:32.450364 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 23:42:32.451655 [Enter `^Ec?' for help]
369 23:42:32.614178
370 23:42:32.614764
371 23:42:32.615161 F0: 102B 0000
372 23:42:32.615548
373 23:42:32.615882 F3: 1001 0000 [0200]
374 23:42:32.616759
375 23:42:32.617223 F3: 1001 0000
376 23:42:32.617645
377 23:42:32.618014 F7: 102D 0000
378 23:42:32.618356
379 23:42:32.620197 F1: 0000 0000
380 23:42:32.620668
381 23:42:32.621042 V0: 0000 0000 [0001]
382 23:42:32.621408
383 23:42:32.623638 00: 0007 8000
384 23:42:32.624128
385 23:42:32.624513 01: 0000 0000
386 23:42:32.624863
387 23:42:32.627278 BP: 0C00 0209 [0000]
388 23:42:32.627809
389 23:42:32.628152 G0: 1182 0000
390 23:42:32.628468
391 23:42:32.630649 EC: 0000 0021 [4000]
392 23:42:32.631089
393 23:42:32.631439 S7: 0000 0000 [0000]
394 23:42:32.631762
395 23:42:32.633957 CC: 0000 0000 [0001]
396 23:42:32.634394
397 23:42:32.634739 T0: 0000 0040 [010F]
398 23:42:32.635064
399 23:42:32.637480 Jump to BL
400 23:42:32.637945
401 23:42:32.661222
402 23:42:32.661789
403 23:42:32.662140
404 23:42:32.668249 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 23:42:32.671613 ARM64: Exception handlers installed.
406 23:42:32.675577 ARM64: Testing exception
407 23:42:32.678720 ARM64: Done test exception
408 23:42:32.685485 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 23:42:32.695605 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 23:42:32.702159 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 23:42:32.712408 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 23:42:32.719246 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 23:42:32.725571 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 23:42:32.738787 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 23:42:32.745401 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 23:42:32.763919 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 23:42:32.767244 WDT: Last reset was cold boot
418 23:42:32.770338 SPI1(PAD0) initialized at 2873684 Hz
419 23:42:32.773663 SPI5(PAD0) initialized at 992727 Hz
420 23:42:32.777474 VBOOT: Loading verstage.
421 23:42:32.783479 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 23:42:32.788529 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 23:42:32.791835 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 23:42:32.794961 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 23:42:32.801757 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 23:42:32.808253 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 23:42:32.818928 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 23:42:32.819486
429 23:42:32.819836
430 23:42:32.829493 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 23:42:32.832694 ARM64: Exception handlers installed.
432 23:42:32.833230 ARM64: Testing exception
433 23:42:32.836475 ARM64: Done test exception
434 23:42:32.840091 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 23:42:32.846091 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 23:42:32.859772 Probing TPM: . done!
437 23:42:32.860360 TPM ready after 0 ms
438 23:42:32.866662 Connected to device vid:did:rid of 1ae0:0028:00
439 23:42:32.873301 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
440 23:42:32.933246 Initialized TPM device CR50 revision 0
441 23:42:32.943947 tlcl_send_startup: Startup return code is 0
442 23:42:32.944418 TPM: setup succeeded
443 23:42:32.955659 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 23:42:32.964731 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 23:42:32.976857 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 23:42:32.987055 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 23:42:32.990634 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 23:42:32.994523 in-header: 03 07 00 00 08 00 00 00
449 23:42:32.998337 in-data: aa e4 47 04 13 02 00 00
450 23:42:33.001870 Chrome EC: UHEPI supported
451 23:42:33.008908 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 23:42:33.012738 in-header: 03 95 00 00 08 00 00 00
453 23:42:33.013322 in-data: 18 20 20 08 00 00 00 00
454 23:42:33.016403 Phase 1
455 23:42:33.020533 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 23:42:33.024087 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 23:42:33.031368 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 23:42:33.035175 Recovery requested (1009000e)
459 23:42:33.044484 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 23:42:33.047776 tlcl_extend: response is 0
461 23:42:33.059702 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 23:42:33.063200 tlcl_extend: response is 0
463 23:42:33.070617 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 23:42:33.089698 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 23:42:33.096443 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 23:42:33.097024
467 23:42:33.097401
468 23:42:33.106446 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 23:42:33.110463 ARM64: Exception handlers installed.
470 23:42:33.113680 ARM64: Testing exception
471 23:42:33.114255 ARM64: Done test exception
472 23:42:33.135119 pmic_efuse_setting: Set efuses in 11 msecs
473 23:42:33.139109 pmwrap_interface_init: Select PMIF_VLD_RDY
474 23:42:33.145362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 23:42:33.148707 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 23:42:33.156236 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 23:42:33.160395 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 23:42:33.163930 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 23:42:33.166916 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 23:42:33.174857 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 23:42:33.178156 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 23:42:33.181846 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 23:42:33.189361 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 23:42:33.192889 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 23:42:33.197382 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 23:42:33.200373 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 23:42:33.207890 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 23:42:33.215446 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 23:42:33.218961 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 23:42:33.226899 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 23:42:33.230483 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 23:42:33.234425 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 23:42:33.241832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 23:42:33.245426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 23:42:33.253079 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 23:42:33.260296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 23:42:33.264075 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 23:42:33.267931 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 23:42:33.274810 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 23:42:33.278161 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 23:42:33.285887 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 23:42:33.289687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 23:42:33.293229 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 23:42:33.300983 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 23:42:33.304492 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 23:42:33.308099 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 23:42:33.315488 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 23:42:33.319000 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 23:42:33.323224 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 23:42:33.330314 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 23:42:33.334267 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 23:42:33.337761 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 23:42:33.341286 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 23:42:33.348999 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 23:42:33.352680 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 23:42:33.356705 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 23:42:33.360021 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 23:42:33.363836 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 23:42:33.371223 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 23:42:33.374958 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 23:42:33.378828 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 23:42:33.382529 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 23:42:33.386219 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 23:42:33.389862 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 23:42:33.397486 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 23:42:33.408319 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 23:42:33.412032 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 23:42:33.419185 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 23:42:33.426741 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 23:42:33.434112 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 23:42:33.438249 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 23:42:33.440924 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 23:42:33.448394 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 23:42:33.452040 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 23:42:33.459806 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 23:42:33.463321 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 23:42:33.473222 [RTC]rtc_get_frequency_meter,154: input=15, output=758
538 23:42:33.482364 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 23:42:33.491890 [RTC]rtc_get_frequency_meter,154: input=19, output=851
540 23:42:33.501494 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 23:42:33.510625 [RTC]rtc_get_frequency_meter,154: input=16, output=782
542 23:42:33.520572 [RTC]rtc_get_frequency_meter,154: input=16, output=780
543 23:42:33.530729 [RTC]rtc_get_frequency_meter,154: input=17, output=805
544 23:42:33.533969 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 23:42:33.537627 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 23:42:33.541566 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 23:42:33.549017 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 23:42:33.553016 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 23:42:33.556950 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 23:42:33.560328 ADC[4]: Raw value=906203 ID=7
551 23:42:33.560770 ADC[3]: Raw value=213810 ID=1
552 23:42:33.564778 RAM Code: 0x71
553 23:42:33.568408 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 23:42:33.572207 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 23:42:33.579236 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 23:42:33.587008 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 23:42:33.590091 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 23:42:33.594727 in-header: 03 07 00 00 08 00 00 00
559 23:42:33.598365 in-data: aa e4 47 04 13 02 00 00
560 23:42:33.601912 Chrome EC: UHEPI supported
561 23:42:33.609863 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 23:42:33.613104 in-header: 03 95 00 00 08 00 00 00
563 23:42:33.613716 in-data: 18 20 20 08 00 00 00 00
564 23:42:33.617054 MRC: failed to locate region type 0.
565 23:42:33.624435 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 23:42:33.629059 DRAM-K: Running full calibration
567 23:42:33.635234 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 23:42:33.635697 header.status = 0x0
569 23:42:33.638957 header.version = 0x6 (expected: 0x6)
570 23:42:33.642736 header.size = 0xd00 (expected: 0xd00)
571 23:42:33.643177 header.flags = 0x0
572 23:42:33.650128 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 23:42:33.667909 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 23:42:33.675672 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 23:42:33.679278 dram_init: ddr_geometry: 2
576 23:42:33.679720 [EMI] MDL number = 2
577 23:42:33.683415 [EMI] Get MDL freq = 0
578 23:42:33.683864 dram_init: ddr_type: 0
579 23:42:33.686210 is_discrete_lpddr4: 1
580 23:42:33.690627 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 23:42:33.691068
582 23:42:33.691585
583 23:42:33.692037 [Bian_co] ETT version 0.0.0.1
584 23:42:33.698095 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 23:42:33.698630
586 23:42:33.701616 dramc_set_vcore_voltage set vcore to 650000
587 23:42:33.702110 Read voltage for 800, 4
588 23:42:33.705608 Vio18 = 0
589 23:42:33.706054 Vcore = 650000
590 23:42:33.706495 Vdram = 0
591 23:42:33.707015 Vddq = 0
592 23:42:33.709093 Vmddr = 0
593 23:42:33.709535 dram_init: config_dvfs: 1
594 23:42:33.716058 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 23:42:33.719523 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 23:42:33.723466 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 23:42:33.726894 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 23:42:33.730530 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 23:42:33.734029 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 23:42:33.737684 MEM_TYPE=3, freq_sel=18
601 23:42:33.741096 sv_algorithm_assistance_LP4_1600
602 23:42:33.745177 ============ PULL DRAM RESETB DOWN ============
603 23:42:33.748285 ========== PULL DRAM RESETB DOWN end =========
604 23:42:33.754825 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 23:42:33.758110 ===================================
606 23:42:33.758553 LPDDR4 DRAM CONFIGURATION
607 23:42:33.761624 ===================================
608 23:42:33.765717 EX_ROW_EN[0] = 0x0
609 23:42:33.768958 EX_ROW_EN[1] = 0x0
610 23:42:33.769428 LP4Y_EN = 0x0
611 23:42:33.769909 WORK_FSP = 0x0
612 23:42:33.772603 WL = 0x2
613 23:42:33.773040 RL = 0x2
614 23:42:33.776237 BL = 0x2
615 23:42:33.776778 RPST = 0x0
616 23:42:33.779871 RD_PRE = 0x0
617 23:42:33.780419 WR_PRE = 0x1
618 23:42:33.783398 WR_PST = 0x0
619 23:42:33.783961 DBI_WR = 0x0
620 23:42:33.786519 DBI_RD = 0x0
621 23:42:33.786960 OTF = 0x1
622 23:42:33.790075 ===================================
623 23:42:33.793265 ===================================
624 23:42:33.796981 ANA top config
625 23:42:33.800181 ===================================
626 23:42:33.800727 DLL_ASYNC_EN = 0
627 23:42:33.803408 ALL_SLAVE_EN = 1
628 23:42:33.806838 NEW_RANK_MODE = 1
629 23:42:33.810232 DLL_IDLE_MODE = 1
630 23:42:33.810831 LP45_APHY_COMB_EN = 1
631 23:42:33.813508 TX_ODT_DIS = 1
632 23:42:33.817331 NEW_8X_MODE = 1
633 23:42:33.820799 ===================================
634 23:42:33.824138 ===================================
635 23:42:33.828038 data_rate = 1600
636 23:42:33.828588 CKR = 1
637 23:42:33.830850 DQ_P2S_RATIO = 8
638 23:42:33.834122 ===================================
639 23:42:33.837190 CA_P2S_RATIO = 8
640 23:42:33.840520 DQ_CA_OPEN = 0
641 23:42:33.844754 DQ_SEMI_OPEN = 0
642 23:42:33.847887 CA_SEMI_OPEN = 0
643 23:42:33.848434 CA_FULL_RATE = 0
644 23:42:33.850675 DQ_CKDIV4_EN = 1
645 23:42:33.854150 CA_CKDIV4_EN = 1
646 23:42:33.857945 CA_PREDIV_EN = 0
647 23:42:33.861196 PH8_DLY = 0
648 23:42:33.864201 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 23:42:33.864751 DQ_AAMCK_DIV = 4
650 23:42:33.867858 CA_AAMCK_DIV = 4
651 23:42:33.871129 CA_ADMCK_DIV = 4
652 23:42:33.874156 DQ_TRACK_CA_EN = 0
653 23:42:33.877500 CA_PICK = 800
654 23:42:33.881000 CA_MCKIO = 800
655 23:42:33.881658 MCKIO_SEMI = 0
656 23:42:33.884759 PLL_FREQ = 3068
657 23:42:33.888897 DQ_UI_PI_RATIO = 32
658 23:42:33.892582 CA_UI_PI_RATIO = 0
659 23:42:33.893022 ===================================
660 23:42:33.896683 ===================================
661 23:42:33.900361 memory_type:LPDDR4
662 23:42:33.904290 GP_NUM : 10
663 23:42:33.904850 SRAM_EN : 1
664 23:42:33.907799 MD32_EN : 0
665 23:42:33.908244 ===================================
666 23:42:33.911546 [ANA_INIT] >>>>>>>>>>>>>>
667 23:42:33.915461 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 23:42:33.918914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 23:42:33.922261 ===================================
670 23:42:33.925420 data_rate = 1600,PCW = 0X7600
671 23:42:33.928975 ===================================
672 23:42:33.932326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 23:42:33.935826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 23:42:33.942758 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 23:42:33.945741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 23:42:33.949234 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 23:42:33.952565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 23:42:33.956035 [ANA_INIT] flow start
679 23:42:33.959154 [ANA_INIT] PLL >>>>>>>>
680 23:42:33.959637 [ANA_INIT] PLL <<<<<<<<
681 23:42:33.962706 [ANA_INIT] MIDPI >>>>>>>>
682 23:42:33.966565 [ANA_INIT] MIDPI <<<<<<<<
683 23:42:33.967104 [ANA_INIT] DLL >>>>>>>>
684 23:42:33.969724 [ANA_INIT] flow end
685 23:42:33.972853 ============ LP4 DIFF to SE enter ============
686 23:42:33.976334 ============ LP4 DIFF to SE exit ============
687 23:42:33.979495 [ANA_INIT] <<<<<<<<<<<<<
688 23:42:33.982864 [Flow] Enable top DCM control >>>>>
689 23:42:33.986212 [Flow] Enable top DCM control <<<<<
690 23:42:33.989318 Enable DLL master slave shuffle
691 23:42:33.995860 ==============================================================
692 23:42:33.996451 Gating Mode config
693 23:42:34.002545 ==============================================================
694 23:42:34.003135 Config description:
695 23:42:34.012387 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 23:42:34.019532 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 23:42:34.025961 SELPH_MODE 0: By rank 1: By Phase
698 23:42:34.029753 ==============================================================
699 23:42:34.032899 GAT_TRACK_EN = 1
700 23:42:34.035956 RX_GATING_MODE = 2
701 23:42:34.038969 RX_GATING_TRACK_MODE = 2
702 23:42:34.042463 SELPH_MODE = 1
703 23:42:34.045708 PICG_EARLY_EN = 1
704 23:42:34.049031 VALID_LAT_VALUE = 1
705 23:42:34.052291 ==============================================================
706 23:42:34.056179 Enter into Gating configuration >>>>
707 23:42:34.058902 Exit from Gating configuration <<<<
708 23:42:34.062315 Enter into DVFS_PRE_config >>>>>
709 23:42:34.076089 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 23:42:34.079724 Exit from DVFS_PRE_config <<<<<
711 23:42:34.080258 Enter into PICG configuration >>>>
712 23:42:34.082565 Exit from PICG configuration <<<<
713 23:42:34.086290 [RX_INPUT] configuration >>>>>
714 23:42:34.089464 [RX_INPUT] configuration <<<<<
715 23:42:34.096337 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 23:42:34.099448 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 23:42:34.106689 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 23:42:34.112679 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 23:42:34.119540 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 23:42:34.125817 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 23:42:34.129480 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 23:42:34.132995 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 23:42:34.135999 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 23:42:34.142697 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 23:42:34.146032 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 23:42:34.149511 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 23:42:34.152614 ===================================
728 23:42:34.155874 LPDDR4 DRAM CONFIGURATION
729 23:42:34.159006 ===================================
730 23:42:34.159689 EX_ROW_EN[0] = 0x0
731 23:42:34.162608 EX_ROW_EN[1] = 0x0
732 23:42:34.165875 LP4Y_EN = 0x0
733 23:42:34.166345 WORK_FSP = 0x0
734 23:42:34.169103 WL = 0x2
735 23:42:34.169562 RL = 0x2
736 23:42:34.173024 BL = 0x2
737 23:42:34.173383 RPST = 0x0
738 23:42:34.175620 RD_PRE = 0x0
739 23:42:34.175910 WR_PRE = 0x1
740 23:42:34.179407 WR_PST = 0x0
741 23:42:34.179696 DBI_WR = 0x0
742 23:42:34.182785 DBI_RD = 0x0
743 23:42:34.183042 OTF = 0x1
744 23:42:34.185806 ===================================
745 23:42:34.189010 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 23:42:34.195876 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 23:42:34.199538 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 23:42:34.202863 ===================================
749 23:42:34.206109 LPDDR4 DRAM CONFIGURATION
750 23:42:34.209080 ===================================
751 23:42:34.209245 EX_ROW_EN[0] = 0x10
752 23:42:34.212815 EX_ROW_EN[1] = 0x0
753 23:42:34.212979 LP4Y_EN = 0x0
754 23:42:34.216153 WORK_FSP = 0x0
755 23:42:34.216293 WL = 0x2
756 23:42:34.219636 RL = 0x2
757 23:42:34.219776 BL = 0x2
758 23:42:34.222777 RPST = 0x0
759 23:42:34.223004 RD_PRE = 0x0
760 23:42:34.225696 WR_PRE = 0x1
761 23:42:34.225841 WR_PST = 0x0
762 23:42:34.229640 DBI_WR = 0x0
763 23:42:34.229853 DBI_RD = 0x0
764 23:42:34.232991 OTF = 0x1
765 23:42:34.235923 ===================================
766 23:42:34.242619 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 23:42:34.246158 nWR fixed to 40
768 23:42:34.249489 [ModeRegInit_LP4] CH0 RK0
769 23:42:34.249738 [ModeRegInit_LP4] CH0 RK1
770 23:42:34.253037 [ModeRegInit_LP4] CH1 RK0
771 23:42:34.256603 [ModeRegInit_LP4] CH1 RK1
772 23:42:34.256844 match AC timing 13
773 23:42:34.262644 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 23:42:34.265959 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 23:42:34.269466 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 23:42:34.276397 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 23:42:34.279728 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 23:42:34.280290 [EMI DOE] emi_dcm 0
779 23:42:34.286315 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 23:42:34.286892 ==
781 23:42:34.289497 Dram Type= 6, Freq= 0, CH_0, rank 0
782 23:42:34.292809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 23:42:34.293307 ==
784 23:42:34.299715 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 23:42:34.306136 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 23:42:34.313748 [CA 0] Center 36 (6~67) winsize 62
787 23:42:34.316977 [CA 1] Center 36 (6~67) winsize 62
788 23:42:34.320302 [CA 2] Center 34 (4~65) winsize 62
789 23:42:34.323925 [CA 3] Center 34 (4~64) winsize 61
790 23:42:34.326617 [CA 4] Center 33 (3~64) winsize 62
791 23:42:34.330562 [CA 5] Center 32 (3~62) winsize 60
792 23:42:34.331135
793 23:42:34.333547 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 23:42:34.334055
795 23:42:34.337055 [CATrainingPosCal] consider 1 rank data
796 23:42:34.340418 u2DelayCellTimex100 = 270/100 ps
797 23:42:34.344185 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 23:42:34.346835 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 23:42:34.353968 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 23:42:34.357258 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 23:42:34.360860 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
802 23:42:34.363943 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
803 23:42:34.364485
804 23:42:34.367281 CA PerBit enable=1, Macro0, CA PI delay=32
805 23:42:34.367858
806 23:42:34.370505 [CBTSetCACLKResult] CA Dly = 32
807 23:42:34.370984 CS Dly: 4 (0~35)
808 23:42:34.371367 ==
809 23:42:34.373602 Dram Type= 6, Freq= 0, CH_0, rank 1
810 23:42:34.380747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 23:42:34.381283 ==
812 23:42:34.383693 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 23:42:34.390664 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 23:42:34.400466 [CA 0] Center 36 (6~67) winsize 62
815 23:42:34.403631 [CA 1] Center 36 (6~67) winsize 62
816 23:42:34.407066 [CA 2] Center 34 (4~65) winsize 62
817 23:42:34.410381 [CA 3] Center 34 (4~65) winsize 62
818 23:42:34.413506 [CA 4] Center 33 (3~64) winsize 62
819 23:42:34.416796 [CA 5] Center 32 (2~63) winsize 62
820 23:42:34.417377
821 23:42:34.420158 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 23:42:34.420749
823 23:42:34.423825 [CATrainingPosCal] consider 2 rank data
824 23:42:34.426441 u2DelayCellTimex100 = 270/100 ps
825 23:42:34.429985 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 23:42:34.433634 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 23:42:34.440399 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 23:42:34.443589 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 23:42:34.446505 CA4 delay=33 (3~64),Diff = 1 PI (7 cell)
830 23:42:34.450120 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
831 23:42:34.450593
832 23:42:34.454290 CA PerBit enable=1, Macro0, CA PI delay=32
833 23:42:34.454867
834 23:42:34.457117 [CBTSetCACLKResult] CA Dly = 32
835 23:42:34.457744 CS Dly: 5 (0~37)
836 23:42:34.458137
837 23:42:34.460203 ----->DramcWriteLeveling(PI) begin...
838 23:42:34.460699 ==
839 23:42:34.463950 Dram Type= 6, Freq= 0, CH_0, rank 0
840 23:42:34.467989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 23:42:34.471077 ==
842 23:42:34.471560 Write leveling (Byte 0): 33 => 33
843 23:42:34.475284 Write leveling (Byte 1): 30 => 30
844 23:42:34.478377 DramcWriteLeveling(PI) end<-----
845 23:42:34.478807
846 23:42:34.479183 ==
847 23:42:34.481705 Dram Type= 6, Freq= 0, CH_0, rank 0
848 23:42:34.485052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 23:42:34.485669 ==
850 23:42:34.488693 [Gating] SW mode calibration
851 23:42:34.496363 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 23:42:34.502964 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 23:42:34.506554 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 23:42:34.509333 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 23:42:34.516106 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 23:42:34.519535 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 23:42:34.522955 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 23:42:34.526307 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 23:42:34.533882 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 23:42:34.536682 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 23:42:34.539641 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 23:42:34.546352 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 23:42:34.549628 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 23:42:34.553140 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 23:42:34.559829 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 23:42:34.563033 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 23:42:34.566629 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 23:42:34.573339 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 23:42:34.576771 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 23:42:34.580022 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 23:42:34.586570 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
872 23:42:34.589734 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 23:42:34.593248 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 23:42:34.596598 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 23:42:34.603918 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 23:42:34.606821 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 23:42:34.609926 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 23:42:34.616867 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 23:42:34.619841 0 9 8 | B1->B0 | 2322 2e2e | 1 0 | (0 0) (0 0)
880 23:42:34.623490 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
881 23:42:34.629877 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 23:42:34.633424 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 23:42:34.636867 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 23:42:34.642952 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 23:42:34.646384 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 23:42:34.650105 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
887 23:42:34.656696 0 10 8 | B1->B0 | 2e2e 2525 | 1 0 | (1 1) (0 0)
888 23:42:34.660129 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
889 23:42:34.663693 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 23:42:34.670156 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 23:42:34.673494 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 23:42:34.677315 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 23:42:34.680228 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 23:42:34.686768 0 11 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
895 23:42:34.690320 0 11 8 | B1->B0 | 2a2a 4141 | 0 0 | (0 0) (1 1)
896 23:42:34.693064 0 11 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
897 23:42:34.700107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 23:42:34.703718 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 23:42:34.707032 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 23:42:34.713467 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 23:42:34.716800 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 23:42:34.720610 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 23:42:34.727266 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
904 23:42:34.730180 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 23:42:34.733646 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 23:42:34.740915 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 23:42:34.743739 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 23:42:34.747052 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 23:42:34.750750 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 23:42:34.757139 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 23:42:34.760435 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 23:42:34.764194 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 23:42:34.770638 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 23:42:34.774422 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 23:42:34.777689 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 23:42:34.783841 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 23:42:34.787970 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 23:42:34.791267 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 23:42:34.797324 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
920 23:42:34.797864 Total UI for P1: 0, mck2ui 16
921 23:42:34.804529 best dqsien dly found for B0: ( 0, 14, 4)
922 23:42:34.807512 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
923 23:42:34.810451 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 23:42:34.814320 Total UI for P1: 0, mck2ui 16
925 23:42:34.818020 best dqsien dly found for B1: ( 0, 14, 12)
926 23:42:34.821692 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
927 23:42:34.824719 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
928 23:42:34.825198
929 23:42:34.828037 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
930 23:42:34.831639 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
931 23:42:34.834766 [Gating] SW calibration Done
932 23:42:34.835245 ==
933 23:42:34.838225 Dram Type= 6, Freq= 0, CH_0, rank 0
934 23:42:34.841146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 23:42:34.841812 ==
936 23:42:34.844460 RX Vref Scan: 0
937 23:42:34.844935
938 23:42:34.847728 RX Vref 0 -> 0, step: 1
939 23:42:34.848206
940 23:42:34.851152 RX Delay -130 -> 252, step: 16
941 23:42:34.854902 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
942 23:42:34.857995 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
943 23:42:34.861354 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
944 23:42:34.864987 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
945 23:42:34.868720 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
946 23:42:34.874887 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
947 23:42:34.878312 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
948 23:42:34.882055 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
949 23:42:34.884659 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
950 23:42:34.888126 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
951 23:42:34.894619 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
952 23:42:34.898155 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
953 23:42:34.901943 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
954 23:42:34.904784 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
955 23:42:34.911964 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
956 23:42:34.915315 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
957 23:42:34.915896 ==
958 23:42:34.918461 Dram Type= 6, Freq= 0, CH_0, rank 0
959 23:42:34.921436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 23:42:34.922071 ==
961 23:42:34.922454 DQS Delay:
962 23:42:34.925417 DQS0 = 0, DQS1 = 0
963 23:42:34.926046 DQM Delay:
964 23:42:34.927808 DQM0 = 89, DQM1 = 82
965 23:42:34.928279 DQ Delay:
966 23:42:34.931653 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
967 23:42:34.934917 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
968 23:42:34.938072 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
969 23:42:34.942236 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =85
970 23:42:34.942810
971 23:42:34.943189
972 23:42:34.943541 ==
973 23:42:34.944983 Dram Type= 6, Freq= 0, CH_0, rank 0
974 23:42:34.948303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 23:42:34.951765 ==
976 23:42:34.952343
977 23:42:34.952730
978 23:42:34.953079 TX Vref Scan disable
979 23:42:34.954780 == TX Byte 0 ==
980 23:42:34.958062 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
981 23:42:34.961460 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
982 23:42:34.964795 == TX Byte 1 ==
983 23:42:34.968392 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 23:42:34.971525 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 23:42:34.972115 ==
986 23:42:34.974728 Dram Type= 6, Freq= 0, CH_0, rank 0
987 23:42:34.981343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 23:42:34.981971 ==
989 23:42:34.993819 TX Vref=22, minBit 8, minWin=27, winSum=447
990 23:42:34.997192 TX Vref=24, minBit 8, minWin=27, winSum=450
991 23:42:35.000452 TX Vref=26, minBit 8, minWin=27, winSum=454
992 23:42:35.003540 TX Vref=28, minBit 0, minWin=28, winSum=456
993 23:42:35.007128 TX Vref=30, minBit 0, minWin=28, winSum=458
994 23:42:35.010350 TX Vref=32, minBit 0, minWin=28, winSum=452
995 23:42:35.017497 [TxChooseVref] Worse bit 0, Min win 28, Win sum 458, Final Vref 30
996 23:42:35.018162
997 23:42:35.020851 Final TX Range 1 Vref 30
998 23:42:35.021425
999 23:42:35.021867 ==
1000 23:42:35.024302 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 23:42:35.027355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 23:42:35.027842 ==
1003 23:42:35.028220
1004 23:42:35.028571
1005 23:42:35.030623 TX Vref Scan disable
1006 23:42:35.033949 == TX Byte 0 ==
1007 23:42:35.037316 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 23:42:35.040703 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 23:42:35.043803 == TX Byte 1 ==
1010 23:42:35.047366 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1011 23:42:35.050230 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1012 23:42:35.050710
1013 23:42:35.053803 [DATLAT]
1014 23:42:35.054367 Freq=800, CH0 RK0
1015 23:42:35.054754
1016 23:42:35.057290 DATLAT Default: 0xa
1017 23:42:35.057918 0, 0xFFFF, sum = 0
1018 23:42:35.060829 1, 0xFFFF, sum = 0
1019 23:42:35.061422 2, 0xFFFF, sum = 0
1020 23:42:35.063571 3, 0xFFFF, sum = 0
1021 23:42:35.064150 4, 0xFFFF, sum = 0
1022 23:42:35.067179 5, 0xFFFF, sum = 0
1023 23:42:35.067760 6, 0xFFFF, sum = 0
1024 23:42:35.070170 7, 0xFFFF, sum = 0
1025 23:42:35.070683 8, 0xFFFF, sum = 0
1026 23:42:35.073766 9, 0x0, sum = 1
1027 23:42:35.074242 10, 0x0, sum = 2
1028 23:42:35.077119 11, 0x0, sum = 3
1029 23:42:35.077764 12, 0x0, sum = 4
1030 23:42:35.080451 best_step = 10
1031 23:42:35.080964
1032 23:42:35.081342 ==
1033 23:42:35.083520 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 23:42:35.086576 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 23:42:35.087042 ==
1036 23:42:35.090272 RX Vref Scan: 1
1037 23:42:35.090743
1038 23:42:35.091132 Set Vref Range= 32 -> 127
1039 23:42:35.091448
1040 23:42:35.093338 RX Vref 32 -> 127, step: 1
1041 23:42:35.093823
1042 23:42:35.096937 RX Delay -95 -> 252, step: 8
1043 23:42:35.097359
1044 23:42:35.100189 Set Vref, RX VrefLevel [Byte0]: 32
1045 23:42:35.103714 [Byte1]: 32
1046 23:42:35.104140
1047 23:42:35.107047 Set Vref, RX VrefLevel [Byte0]: 33
1048 23:42:35.110547 [Byte1]: 33
1049 23:42:35.114128
1050 23:42:35.114651 Set Vref, RX VrefLevel [Byte0]: 34
1051 23:42:35.117397 [Byte1]: 34
1052 23:42:35.121715
1053 23:42:35.122230 Set Vref, RX VrefLevel [Byte0]: 35
1054 23:42:35.124770 [Byte1]: 35
1055 23:42:35.129241
1056 23:42:35.129709 Set Vref, RX VrefLevel [Byte0]: 36
1057 23:42:35.132996 [Byte1]: 36
1058 23:42:35.136743
1059 23:42:35.137265 Set Vref, RX VrefLevel [Byte0]: 37
1060 23:42:35.139986 [Byte1]: 37
1061 23:42:35.144341
1062 23:42:35.144912 Set Vref, RX VrefLevel [Byte0]: 38
1063 23:42:35.148093 [Byte1]: 38
1064 23:42:35.152452
1065 23:42:35.153004 Set Vref, RX VrefLevel [Byte0]: 39
1066 23:42:35.155511 [Byte1]: 39
1067 23:42:35.159849
1068 23:42:35.160408 Set Vref, RX VrefLevel [Byte0]: 40
1069 23:42:35.163104 [Byte1]: 40
1070 23:42:35.167386
1071 23:42:35.167944 Set Vref, RX VrefLevel [Byte0]: 41
1072 23:42:35.170232 [Byte1]: 41
1073 23:42:35.174898
1074 23:42:35.175454 Set Vref, RX VrefLevel [Byte0]: 42
1075 23:42:35.178114 [Byte1]: 42
1076 23:42:35.182626
1077 23:42:35.183188 Set Vref, RX VrefLevel [Byte0]: 43
1078 23:42:35.185427 [Byte1]: 43
1079 23:42:35.190033
1080 23:42:35.190592 Set Vref, RX VrefLevel [Byte0]: 44
1081 23:42:35.193207 [Byte1]: 44
1082 23:42:35.197768
1083 23:42:35.198325 Set Vref, RX VrefLevel [Byte0]: 45
1084 23:42:35.200965 [Byte1]: 45
1085 23:42:35.205616
1086 23:42:35.206178 Set Vref, RX VrefLevel [Byte0]: 46
1087 23:42:35.208698 [Byte1]: 46
1088 23:42:35.212637
1089 23:42:35.213201 Set Vref, RX VrefLevel [Byte0]: 47
1090 23:42:35.216542 [Byte1]: 47
1091 23:42:35.220667
1092 23:42:35.221219 Set Vref, RX VrefLevel [Byte0]: 48
1093 23:42:35.223517 [Byte1]: 48
1094 23:42:35.227580
1095 23:42:35.228088 Set Vref, RX VrefLevel [Byte0]: 49
1096 23:42:35.231419 [Byte1]: 49
1097 23:42:35.235609
1098 23:42:35.236076 Set Vref, RX VrefLevel [Byte0]: 50
1099 23:42:35.238723 [Byte1]: 50
1100 23:42:35.243337
1101 23:42:35.243907 Set Vref, RX VrefLevel [Byte0]: 51
1102 23:42:35.246205 [Byte1]: 51
1103 23:42:35.250530
1104 23:42:35.251005 Set Vref, RX VrefLevel [Byte0]: 52
1105 23:42:35.253717 [Byte1]: 52
1106 23:42:35.258499
1107 23:42:35.259050 Set Vref, RX VrefLevel [Byte0]: 53
1108 23:42:35.261193 [Byte1]: 53
1109 23:42:35.265855
1110 23:42:35.266432 Set Vref, RX VrefLevel [Byte0]: 54
1111 23:42:35.269109 [Byte1]: 54
1112 23:42:35.273106
1113 23:42:35.273572 Set Vref, RX VrefLevel [Byte0]: 55
1114 23:42:35.276681 [Byte1]: 55
1115 23:42:35.281019
1116 23:42:35.281489 Set Vref, RX VrefLevel [Byte0]: 56
1117 23:42:35.284080 [Byte1]: 56
1118 23:42:35.288880
1119 23:42:35.289442 Set Vref, RX VrefLevel [Byte0]: 57
1120 23:42:35.292100 [Byte1]: 57
1121 23:42:35.296224
1122 23:42:35.296793 Set Vref, RX VrefLevel [Byte0]: 58
1123 23:42:35.299292 [Byte1]: 58
1124 23:42:35.304061
1125 23:42:35.304618 Set Vref, RX VrefLevel [Byte0]: 59
1126 23:42:35.306953 [Byte1]: 59
1127 23:42:35.311549
1128 23:42:35.312111 Set Vref, RX VrefLevel [Byte0]: 60
1129 23:42:35.314501 [Byte1]: 60
1130 23:42:35.318972
1131 23:42:35.319536 Set Vref, RX VrefLevel [Byte0]: 61
1132 23:42:35.322422 [Byte1]: 61
1133 23:42:35.326721
1134 23:42:35.327282 Set Vref, RX VrefLevel [Byte0]: 62
1135 23:42:35.330102 [Byte1]: 62
1136 23:42:35.334315
1137 23:42:35.334875 Set Vref, RX VrefLevel [Byte0]: 63
1138 23:42:35.337493 [Byte1]: 63
1139 23:42:35.341809
1140 23:42:35.342362 Set Vref, RX VrefLevel [Byte0]: 64
1141 23:42:35.345402 [Byte1]: 64
1142 23:42:35.349811
1143 23:42:35.350281 Set Vref, RX VrefLevel [Byte0]: 65
1144 23:42:35.353202 [Byte1]: 65
1145 23:42:35.357187
1146 23:42:35.357810 Set Vref, RX VrefLevel [Byte0]: 66
1147 23:42:35.360845 [Byte1]: 66
1148 23:42:35.365158
1149 23:42:35.365768 Set Vref, RX VrefLevel [Byte0]: 67
1150 23:42:35.367839 [Byte1]: 67
1151 23:42:35.372420
1152 23:42:35.372991 Set Vref, RX VrefLevel [Byte0]: 68
1153 23:42:35.375827 [Byte1]: 68
1154 23:42:35.379935
1155 23:42:35.380402 Set Vref, RX VrefLevel [Byte0]: 69
1156 23:42:35.383151 [Byte1]: 69
1157 23:42:35.387838
1158 23:42:35.388402 Set Vref, RX VrefLevel [Byte0]: 70
1159 23:42:35.390484 [Byte1]: 70
1160 23:42:35.394792
1161 23:42:35.395258 Set Vref, RX VrefLevel [Byte0]: 71
1162 23:42:35.398453 [Byte1]: 71
1163 23:42:35.402674
1164 23:42:35.403137 Set Vref, RX VrefLevel [Byte0]: 72
1165 23:42:35.405674 [Byte1]: 72
1166 23:42:35.410114
1167 23:42:35.410531 Set Vref, RX VrefLevel [Byte0]: 73
1168 23:42:35.413808 [Byte1]: 73
1169 23:42:35.417795
1170 23:42:35.418313 Set Vref, RX VrefLevel [Byte0]: 74
1171 23:42:35.421176 [Byte1]: 74
1172 23:42:35.425875
1173 23:42:35.426481 Set Vref, RX VrefLevel [Byte0]: 75
1174 23:42:35.429243 [Byte1]: 75
1175 23:42:35.432844
1176 23:42:35.433402 Set Vref, RX VrefLevel [Byte0]: 76
1177 23:42:35.436774 [Byte1]: 76
1178 23:42:35.440860
1179 23:42:35.441416 Set Vref, RX VrefLevel [Byte0]: 77
1180 23:42:35.444282 [Byte1]: 77
1181 23:42:35.448575
1182 23:42:35.449039 Set Vref, RX VrefLevel [Byte0]: 78
1183 23:42:35.451606 [Byte1]: 78
1184 23:42:35.455759
1185 23:42:35.456320 Final RX Vref Byte 0 = 58 to rank0
1186 23:42:35.458974 Final RX Vref Byte 1 = 60 to rank0
1187 23:42:35.462229 Final RX Vref Byte 0 = 58 to rank1
1188 23:42:35.465765 Final RX Vref Byte 1 = 60 to rank1==
1189 23:42:35.469108 Dram Type= 6, Freq= 0, CH_0, rank 0
1190 23:42:35.476399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1191 23:42:35.476980 ==
1192 23:42:35.477358 DQS Delay:
1193 23:42:35.477751 DQS0 = 0, DQS1 = 0
1194 23:42:35.479105 DQM Delay:
1195 23:42:35.479612 DQM0 = 92, DQM1 = 85
1196 23:42:35.482324 DQ Delay:
1197 23:42:35.486185 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1198 23:42:35.489158 DQ4 =96, DQ5 =80, DQ6 =100, DQ7 =100
1199 23:42:35.492583 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1200 23:42:35.496103 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1201 23:42:35.496681
1202 23:42:35.497103
1203 23:42:35.502741 [DQSOSCAuto] RK0, (LSB)MR18= 0x463c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 392 ps
1204 23:42:35.506270 CH0 RK0: MR19=606, MR18=463C
1205 23:42:35.512246 CH0_RK0: MR19=0x606, MR18=0x463C, DQSOSC=392, MR23=63, INC=96, DEC=64
1206 23:42:35.512721
1207 23:42:35.515566 ----->DramcWriteLeveling(PI) begin...
1208 23:42:35.516023 ==
1209 23:42:35.518881 Dram Type= 6, Freq= 0, CH_0, rank 1
1210 23:42:35.522175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1211 23:42:35.522659 ==
1212 23:42:35.525842 Write leveling (Byte 0): 35 => 35
1213 23:42:35.528965 Write leveling (Byte 1): 30 => 30
1214 23:42:35.532279 DramcWriteLeveling(PI) end<-----
1215 23:42:35.532738
1216 23:42:35.533081 ==
1217 23:42:35.575458 Dram Type= 6, Freq= 0, CH_0, rank 1
1218 23:42:35.576140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1219 23:42:35.576737 ==
1220 23:42:35.577104 [Gating] SW mode calibration
1221 23:42:35.577447 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1222 23:42:35.577827 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1223 23:42:35.578565 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1224 23:42:35.578945 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1225 23:42:35.579409 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1226 23:42:35.579747 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 23:42:35.580275 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 23:42:35.582817 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 23:42:35.586331 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 23:42:35.589463 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 23:42:35.596132 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 23:42:35.599272 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 23:42:35.603305 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 23:42:35.606387 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 23:42:35.612919 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 23:42:35.616264 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 23:42:35.619562 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 23:42:35.626202 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 23:42:35.629382 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 23:42:35.633184 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1241 23:42:35.639692 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1242 23:42:35.642789 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 23:42:35.645988 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 23:42:35.653530 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 23:42:35.656595 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 23:42:35.659763 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 23:42:35.666249 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 23:42:35.669949 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 23:42:35.673161 0 9 8 | B1->B0 | 3131 2a2a | 1 1 | (1 1) (1 1)
1250 23:42:35.679644 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 23:42:35.683097 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 23:42:35.686166 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 23:42:35.689527 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 23:42:35.696167 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1255 23:42:35.699304 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1256 23:42:35.702835 0 10 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1257 23:42:35.707388 0 10 8 | B1->B0 | 2828 2b2b | 0 1 | (0 0) (1 1)
1258 23:42:35.714680 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 23:42:35.718253 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 23:42:35.721943 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 23:42:35.725154 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 23:42:35.733154 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 23:42:35.735727 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 23:42:35.739459 0 11 4 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
1265 23:42:35.742519 0 11 8 | B1->B0 | 3d3d 3b3b | 0 1 | (0 0) (0 0)
1266 23:42:35.749321 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 23:42:35.752803 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 23:42:35.755948 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 23:42:35.763431 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 23:42:35.766321 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 23:42:35.769201 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1272 23:42:35.776577 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1273 23:42:35.779526 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1274 23:42:35.782383 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 23:42:35.789342 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 23:42:35.792423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 23:42:35.796026 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 23:42:35.803380 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 23:42:35.805988 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 23:42:35.809361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 23:42:35.815810 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 23:42:35.819222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 23:42:35.822514 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 23:42:35.825862 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 23:42:35.832464 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 23:42:35.836331 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 23:42:35.839473 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 23:42:35.846043 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 23:42:35.849630 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1290 23:42:35.852832 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1291 23:42:35.855828 Total UI for P1: 0, mck2ui 16
1292 23:42:35.859854 best dqsien dly found for B0: ( 0, 14, 8)
1293 23:42:35.862489 Total UI for P1: 0, mck2ui 16
1294 23:42:35.866473 best dqsien dly found for B1: ( 0, 14, 8)
1295 23:42:35.869612 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1296 23:42:35.872950 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1297 23:42:35.873414
1298 23:42:35.876019 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1299 23:42:35.883015 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1300 23:42:35.883598 [Gating] SW calibration Done
1301 23:42:35.883979 ==
1302 23:42:35.886445 Dram Type= 6, Freq= 0, CH_0, rank 1
1303 23:42:35.892847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1304 23:42:35.893426 ==
1305 23:42:35.893866 RX Vref Scan: 0
1306 23:42:35.894219
1307 23:42:35.896043 RX Vref 0 -> 0, step: 1
1308 23:42:35.896510
1309 23:42:35.899486 RX Delay -130 -> 252, step: 16
1310 23:42:35.903013 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1311 23:42:35.906185 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1312 23:42:35.909538 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1313 23:42:35.915974 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1314 23:42:35.919924 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1315 23:42:35.922916 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1316 23:42:35.926420 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1317 23:42:35.929713 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1318 23:42:35.936739 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1319 23:42:35.939693 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1320 23:42:35.942542 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
1321 23:42:35.946090 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1322 23:42:35.949358 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1323 23:42:35.956484 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1324 23:42:35.959474 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1325 23:42:35.963171 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1326 23:42:35.963671 ==
1327 23:42:35.966134 Dram Type= 6, Freq= 0, CH_0, rank 1
1328 23:42:35.969529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1329 23:42:35.970161 ==
1330 23:42:35.972790 DQS Delay:
1331 23:42:35.973362 DQS0 = 0, DQS1 = 0
1332 23:42:35.976226 DQM Delay:
1333 23:42:35.976796 DQM0 = 91, DQM1 = 83
1334 23:42:35.977168 DQ Delay:
1335 23:42:35.979561 DQ0 =93, DQ1 =93, DQ2 =85, DQ3 =85
1336 23:42:35.982790 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1337 23:42:35.986668 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
1338 23:42:35.990085 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =93
1339 23:42:35.990656
1340 23:42:35.991032
1341 23:42:35.991380 ==
1342 23:42:35.992600 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 23:42:36.000059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 23:42:36.000671 ==
1345 23:42:36.001067
1346 23:42:36.001421
1347 23:42:36.001794 TX Vref Scan disable
1348 23:42:36.002874 == TX Byte 0 ==
1349 23:42:36.006828 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1350 23:42:36.013684 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1351 23:42:36.014369 == TX Byte 1 ==
1352 23:42:36.016878 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1353 23:42:36.023827 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1354 23:42:36.024403 ==
1355 23:42:36.026924 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 23:42:36.029798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 23:42:36.030272 ==
1358 23:42:36.043369 TX Vref=22, minBit 8, minWin=27, winSum=447
1359 23:42:36.046385 TX Vref=24, minBit 1, minWin=28, winSum=451
1360 23:42:36.049746 TX Vref=26, minBit 12, minWin=27, winSum=453
1361 23:42:36.052739 TX Vref=28, minBit 4, minWin=28, winSum=460
1362 23:42:36.055975 TX Vref=30, minBit 7, minWin=28, winSum=461
1363 23:42:36.059796 TX Vref=32, minBit 2, minWin=28, winSum=453
1364 23:42:36.066136 [TxChooseVref] Worse bit 7, Min win 28, Win sum 461, Final Vref 30
1365 23:42:36.066561
1366 23:42:36.069490 Final TX Range 1 Vref 30
1367 23:42:36.069970
1368 23:42:36.070253 ==
1369 23:42:36.072523 Dram Type= 6, Freq= 0, CH_0, rank 1
1370 23:42:36.076239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1371 23:42:36.076643 ==
1372 23:42:36.076892
1373 23:42:36.079496
1374 23:42:36.079891 TX Vref Scan disable
1375 23:42:36.083220 == TX Byte 0 ==
1376 23:42:36.086141 Update DQ dly =586 (2 ,2, 10) DQ OEN =(1 ,7)
1377 23:42:36.089920 Update DQM dly =586 (2 ,2, 10) DQM OEN =(1 ,7)
1378 23:42:36.092867 == TX Byte 1 ==
1379 23:42:36.096651 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1380 23:42:36.099848 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1381 23:42:36.102660
1382 23:42:36.102937 [DATLAT]
1383 23:42:36.103171 Freq=800, CH0 RK1
1384 23:42:36.103392
1385 23:42:36.106576 DATLAT Default: 0xa
1386 23:42:36.106876 0, 0xFFFF, sum = 0
1387 23:42:36.109867 1, 0xFFFF, sum = 0
1388 23:42:36.110339 2, 0xFFFF, sum = 0
1389 23:42:36.113760 3, 0xFFFF, sum = 0
1390 23:42:36.114274 4, 0xFFFF, sum = 0
1391 23:42:36.116690 5, 0xFFFF, sum = 0
1392 23:42:36.119820 6, 0xFFFF, sum = 0
1393 23:42:36.120214 7, 0xFFFF, sum = 0
1394 23:42:36.123032 8, 0xFFFF, sum = 0
1395 23:42:36.123425 9, 0x0, sum = 1
1396 23:42:36.123744 10, 0x0, sum = 2
1397 23:42:36.126776 11, 0x0, sum = 3
1398 23:42:36.127276 12, 0x0, sum = 4
1399 23:42:36.130037 best_step = 10
1400 23:42:36.130421
1401 23:42:36.130727 ==
1402 23:42:36.133459 Dram Type= 6, Freq= 0, CH_0, rank 1
1403 23:42:36.136141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1404 23:42:36.136651 ==
1405 23:42:36.139886 RX Vref Scan: 0
1406 23:42:36.140389
1407 23:42:36.140702 RX Vref 0 -> 0, step: 1
1408 23:42:36.140991
1409 23:42:36.143041 RX Delay -79 -> 252, step: 8
1410 23:42:36.150137 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1411 23:42:36.153124 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1412 23:42:36.156458 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1413 23:42:36.159640 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1414 23:42:36.162866 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1415 23:42:36.169971 iDelay=209, Bit 5, Center 88 (-23 ~ 200) 224
1416 23:42:36.173147 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1417 23:42:36.176302 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1418 23:42:36.179413 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
1419 23:42:36.183201 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1420 23:42:36.190331 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1421 23:42:36.192967 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1422 23:42:36.196505 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
1423 23:42:36.199496 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1424 23:42:36.202869 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1425 23:42:36.209645 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1426 23:42:36.210222 ==
1427 23:42:36.212859 Dram Type= 6, Freq= 0, CH_0, rank 1
1428 23:42:36.216828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1429 23:42:36.217390 ==
1430 23:42:36.217820 DQS Delay:
1431 23:42:36.219378 DQS0 = 0, DQS1 = 0
1432 23:42:36.219882 DQM Delay:
1433 23:42:36.222904 DQM0 = 93, DQM1 = 83
1434 23:42:36.223481 DQ Delay:
1435 23:42:36.226686 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1436 23:42:36.229616 DQ4 =92, DQ5 =88, DQ6 =100, DQ7 =100
1437 23:42:36.233222 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
1438 23:42:36.236386 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
1439 23:42:36.236945
1440 23:42:36.237327
1441 23:42:36.246226 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c0d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
1442 23:42:36.246816 CH0 RK1: MR19=606, MR18=3C0D
1443 23:42:36.253094 CH0_RK1: MR19=0x606, MR18=0x3C0D, DQSOSC=394, MR23=63, INC=95, DEC=63
1444 23:42:36.256461 [RxdqsGatingPostProcess] freq 800
1445 23:42:36.262801 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1446 23:42:36.266693 Pre-setting of DQS Precalculation
1447 23:42:36.269871 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1448 23:42:36.270432 ==
1449 23:42:36.273241 Dram Type= 6, Freq= 0, CH_1, rank 0
1450 23:42:36.276447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1451 23:42:36.277013 ==
1452 23:42:36.283245 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1453 23:42:36.289164 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1454 23:42:36.297832 [CA 0] Center 36 (6~67) winsize 62
1455 23:42:36.301686 [CA 1] Center 36 (6~67) winsize 62
1456 23:42:36.304974 [CA 2] Center 35 (4~66) winsize 63
1457 23:42:36.308456 [CA 3] Center 34 (4~65) winsize 62
1458 23:42:36.311739 [CA 4] Center 34 (4~65) winsize 62
1459 23:42:36.314763 [CA 5] Center 34 (4~65) winsize 62
1460 23:42:36.315323
1461 23:42:36.318368 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1462 23:42:36.318926
1463 23:42:36.321275 [CATrainingPosCal] consider 1 rank data
1464 23:42:36.324851 u2DelayCellTimex100 = 270/100 ps
1465 23:42:36.328242 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1466 23:42:36.331300 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1467 23:42:36.338119 CA2 delay=35 (4~66),Diff = 1 PI (7 cell)
1468 23:42:36.341637 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1469 23:42:36.344982 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1470 23:42:36.348473 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1471 23:42:36.349041
1472 23:42:36.351502 CA PerBit enable=1, Macro0, CA PI delay=34
1473 23:42:36.351967
1474 23:42:36.354921 [CBTSetCACLKResult] CA Dly = 34
1475 23:42:36.355378 CS Dly: 5 (0~36)
1476 23:42:36.355743 ==
1477 23:42:36.358022 Dram Type= 6, Freq= 0, CH_1, rank 1
1478 23:42:36.364861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1479 23:42:36.365438 ==
1480 23:42:36.369027 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1481 23:42:36.375514 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1482 23:42:36.384390 [CA 0] Center 36 (6~67) winsize 62
1483 23:42:36.388203 [CA 1] Center 37 (6~68) winsize 63
1484 23:42:36.392221 [CA 2] Center 35 (5~66) winsize 62
1485 23:42:36.395973 [CA 3] Center 34 (4~65) winsize 62
1486 23:42:36.399274 [CA 4] Center 35 (5~66) winsize 62
1487 23:42:36.402960 [CA 5] Center 34 (4~65) winsize 62
1488 23:42:36.403430
1489 23:42:36.406184 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1490 23:42:36.406653
1491 23:42:36.409639 [CATrainingPosCal] consider 2 rank data
1492 23:42:36.413068 u2DelayCellTimex100 = 270/100 ps
1493 23:42:36.416571 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1494 23:42:36.419805 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1495 23:42:36.423034 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1496 23:42:36.426747 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 23:42:36.429782 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1498 23:42:36.433105 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1499 23:42:36.433712
1500 23:42:36.436355 CA PerBit enable=1, Macro0, CA PI delay=34
1501 23:42:36.436912
1502 23:42:36.439698 [CBTSetCACLKResult] CA Dly = 34
1503 23:42:36.443148 CS Dly: 6 (0~39)
1504 23:42:36.443798
1505 23:42:36.446678 ----->DramcWriteLeveling(PI) begin...
1506 23:42:36.447243 ==
1507 23:42:36.449924 Dram Type= 6, Freq= 0, CH_1, rank 0
1508 23:42:36.453355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1509 23:42:36.453919 ==
1510 23:42:36.456173 Write leveling (Byte 0): 29 => 29
1511 23:42:36.460162 Write leveling (Byte 1): 29 => 29
1512 23:42:36.463500 DramcWriteLeveling(PI) end<-----
1513 23:42:36.463972
1514 23:42:36.464397 ==
1515 23:42:36.466327 Dram Type= 6, Freq= 0, CH_1, rank 0
1516 23:42:36.469688 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1517 23:42:36.470165 ==
1518 23:42:36.473664 [Gating] SW mode calibration
1519 23:42:36.479736 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1520 23:42:36.486965 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1521 23:42:36.490235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1522 23:42:36.493273 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1523 23:42:36.499635 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 23:42:36.503153 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 23:42:36.506686 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 23:42:36.513345 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 23:42:36.516535 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 23:42:36.519762 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 23:42:36.526345 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 23:42:36.529697 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 23:42:36.533315 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 23:42:36.540005 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 23:42:36.542868 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 23:42:36.546391 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 23:42:36.549857 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 23:42:36.556508 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 23:42:36.559796 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 23:42:36.562982 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1539 23:42:36.569914 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 23:42:36.573424 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 23:42:36.576842 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 23:42:36.583572 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 23:42:36.587133 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 23:42:36.589965 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 23:42:36.596965 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 23:42:36.600454 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1547 23:42:36.603349 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1548 23:42:36.610221 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 23:42:36.613819 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 23:42:36.617287 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 23:42:36.623873 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 23:42:36.626523 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 23:42:36.630016 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1554 23:42:36.633532 0 10 4 | B1->B0 | 3131 2d2d | 1 1 | (1 0) (1 0)
1555 23:42:36.640043 0 10 8 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
1556 23:42:36.643088 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 23:42:36.647082 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 23:42:36.653165 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 23:42:36.656682 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 23:42:36.659950 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 23:42:36.666989 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 23:42:36.669864 0 11 4 | B1->B0 | 2727 3636 | 0 0 | (0 0) (1 1)
1563 23:42:36.673295 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1564 23:42:36.679982 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 23:42:36.683620 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 23:42:36.686698 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 23:42:36.693833 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 23:42:36.696959 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 23:42:36.700394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1570 23:42:36.707123 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1571 23:42:36.710590 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1572 23:42:36.713641 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 23:42:36.720029 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 23:42:36.723470 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 23:42:36.726883 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 23:42:36.730158 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 23:42:36.736993 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 23:42:36.740368 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 23:42:36.743749 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 23:42:36.750362 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 23:42:36.753246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 23:42:36.756917 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 23:42:36.764163 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 23:42:36.766882 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 23:42:36.770145 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 23:42:36.776939 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1587 23:42:36.780005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1588 23:42:36.783528 Total UI for P1: 0, mck2ui 16
1589 23:42:36.786747 best dqsien dly found for B0: ( 0, 14, 6)
1590 23:42:36.790152 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1591 23:42:36.793858 Total UI for P1: 0, mck2ui 16
1592 23:42:36.797267 best dqsien dly found for B1: ( 0, 14, 6)
1593 23:42:36.800192 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1594 23:42:36.803295 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1595 23:42:36.803890
1596 23:42:36.807265 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1597 23:42:36.810839 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1598 23:42:36.814338 [Gating] SW calibration Done
1599 23:42:36.814907 ==
1600 23:42:36.817138 Dram Type= 6, Freq= 0, CH_1, rank 0
1601 23:42:36.824076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1602 23:42:36.824643 ==
1603 23:42:36.825019 RX Vref Scan: 0
1604 23:42:36.825369
1605 23:42:36.826918 RX Vref 0 -> 0, step: 1
1606 23:42:36.827379
1607 23:42:36.830777 RX Delay -130 -> 252, step: 16
1608 23:42:36.833817 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1609 23:42:36.837513 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1610 23:42:36.840555 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1611 23:42:36.843477 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1612 23:42:36.850654 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1613 23:42:36.853961 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1614 23:42:36.857514 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1615 23:42:36.860732 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1616 23:42:36.863516 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1617 23:42:36.870726 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1618 23:42:36.873657 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1619 23:42:36.877152 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1620 23:42:36.880272 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1621 23:42:36.884035 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1622 23:42:36.889953 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1623 23:42:36.893536 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1624 23:42:36.894160 ==
1625 23:42:36.897119 Dram Type= 6, Freq= 0, CH_1, rank 0
1626 23:42:36.900055 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1627 23:42:36.900531 ==
1628 23:42:36.903529 DQS Delay:
1629 23:42:36.903995 DQS0 = 0, DQS1 = 0
1630 23:42:36.904369 DQM Delay:
1631 23:42:36.906822 DQM0 = 92, DQM1 = 86
1632 23:42:36.907288 DQ Delay:
1633 23:42:36.910300 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1634 23:42:36.913658 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1635 23:42:36.917227 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1636 23:42:36.920523 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1637 23:42:36.921220
1638 23:42:36.921655
1639 23:42:36.922020 ==
1640 23:42:36.923945 Dram Type= 6, Freq= 0, CH_1, rank 0
1641 23:42:36.930593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1642 23:42:36.931200 ==
1643 23:42:36.931592
1644 23:42:36.931939
1645 23:42:36.932268 TX Vref Scan disable
1646 23:42:36.933658 == TX Byte 0 ==
1647 23:42:36.937224 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1648 23:42:36.943781 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1649 23:42:36.944371 == TX Byte 1 ==
1650 23:42:36.947818 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1651 23:42:36.951057 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1652 23:42:36.951648 ==
1653 23:42:36.954007 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 23:42:36.960924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 23:42:36.961484 ==
1656 23:42:36.973167 TX Vref=22, minBit 1, minWin=26, winSum=437
1657 23:42:36.976443 TX Vref=24, minBit 3, minWin=26, winSum=443
1658 23:42:36.979828 TX Vref=26, minBit 3, minWin=26, winSum=445
1659 23:42:36.983029 TX Vref=28, minBit 1, minWin=27, winSum=449
1660 23:42:36.986479 TX Vref=30, minBit 1, minWin=27, winSum=452
1661 23:42:36.989556 TX Vref=32, minBit 1, minWin=27, winSum=451
1662 23:42:36.996187 [TxChooseVref] Worse bit 1, Min win 27, Win sum 452, Final Vref 30
1663 23:42:36.996764
1664 23:42:36.999192 Final TX Range 1 Vref 30
1665 23:42:36.999664
1666 23:42:37.000038 ==
1667 23:42:37.002847 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 23:42:37.006608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 23:42:37.007187 ==
1670 23:42:37.007566
1671 23:42:37.009644
1672 23:42:37.010117 TX Vref Scan disable
1673 23:42:37.013334 == TX Byte 0 ==
1674 23:42:37.016524 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1675 23:42:37.019777 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1676 23:42:37.023080 == TX Byte 1 ==
1677 23:42:37.026162 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1678 23:42:37.029550 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1679 23:42:37.030189
1680 23:42:37.032965 [DATLAT]
1681 23:42:37.033431 Freq=800, CH1 RK0
1682 23:42:37.033870
1683 23:42:37.036547 DATLAT Default: 0xa
1684 23:42:37.037118 0, 0xFFFF, sum = 0
1685 23:42:37.039668 1, 0xFFFF, sum = 0
1686 23:42:37.040141 2, 0xFFFF, sum = 0
1687 23:42:37.043021 3, 0xFFFF, sum = 0
1688 23:42:37.043497 4, 0xFFFF, sum = 0
1689 23:42:37.046604 5, 0xFFFF, sum = 0
1690 23:42:37.047167 6, 0xFFFF, sum = 0
1691 23:42:37.050326 7, 0xFFFF, sum = 0
1692 23:42:37.050911 8, 0xFFFF, sum = 0
1693 23:42:37.052817 9, 0x0, sum = 1
1694 23:42:37.053288 10, 0x0, sum = 2
1695 23:42:37.056789 11, 0x0, sum = 3
1696 23:42:37.057368 12, 0x0, sum = 4
1697 23:42:37.059603 best_step = 10
1698 23:42:37.060071
1699 23:42:37.060443 ==
1700 23:42:37.063445 Dram Type= 6, Freq= 0, CH_1, rank 0
1701 23:42:37.066200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1702 23:42:37.066678 ==
1703 23:42:37.069829 RX Vref Scan: 1
1704 23:42:37.070403
1705 23:42:37.070778 Set Vref Range= 32 -> 127
1706 23:42:37.071125
1707 23:42:37.073009 RX Vref 32 -> 127, step: 1
1708 23:42:37.073477
1709 23:42:37.076432 RX Delay -79 -> 252, step: 8
1710 23:42:37.076999
1711 23:42:37.079945 Set Vref, RX VrefLevel [Byte0]: 32
1712 23:42:37.082877 [Byte1]: 32
1713 23:42:37.083347
1714 23:42:37.086994 Set Vref, RX VrefLevel [Byte0]: 33
1715 23:42:37.089646 [Byte1]: 33
1716 23:42:37.090195
1717 23:42:37.093405 Set Vref, RX VrefLevel [Byte0]: 34
1718 23:42:37.096648 [Byte1]: 34
1719 23:42:37.100130
1720 23:42:37.100601 Set Vref, RX VrefLevel [Byte0]: 35
1721 23:42:37.104046 [Byte1]: 35
1722 23:42:37.107753
1723 23:42:37.108222 Set Vref, RX VrefLevel [Byte0]: 36
1724 23:42:37.111984 [Byte1]: 36
1725 23:42:37.115652
1726 23:42:37.116121 Set Vref, RX VrefLevel [Byte0]: 37
1727 23:42:37.119092 [Byte1]: 37
1728 23:42:37.123610
1729 23:42:37.124181 Set Vref, RX VrefLevel [Byte0]: 38
1730 23:42:37.126590 [Byte1]: 38
1731 23:42:37.130893
1732 23:42:37.131535 Set Vref, RX VrefLevel [Byte0]: 39
1733 23:42:37.134356 [Byte1]: 39
1734 23:42:37.138709
1735 23:42:37.139275 Set Vref, RX VrefLevel [Byte0]: 40
1736 23:42:37.141753 [Byte1]: 40
1737 23:42:37.146198
1738 23:42:37.146752 Set Vref, RX VrefLevel [Byte0]: 41
1739 23:42:37.149018 [Byte1]: 41
1740 23:42:37.153419
1741 23:42:37.154051 Set Vref, RX VrefLevel [Byte0]: 42
1742 23:42:37.156441 [Byte1]: 42
1743 23:42:37.161194
1744 23:42:37.161788 Set Vref, RX VrefLevel [Byte0]: 43
1745 23:42:37.164494 [Byte1]: 43
1746 23:42:37.168577
1747 23:42:37.169133 Set Vref, RX VrefLevel [Byte0]: 44
1748 23:42:37.171869 [Byte1]: 44
1749 23:42:37.176095
1750 23:42:37.176650 Set Vref, RX VrefLevel [Byte0]: 45
1751 23:42:37.179674 [Byte1]: 45
1752 23:42:37.183349
1753 23:42:37.183816 Set Vref, RX VrefLevel [Byte0]: 46
1754 23:42:37.186892 [Byte1]: 46
1755 23:42:37.190718
1756 23:42:37.191185 Set Vref, RX VrefLevel [Byte0]: 47
1757 23:42:37.194160 [Byte1]: 47
1758 23:42:37.198578
1759 23:42:37.199123 Set Vref, RX VrefLevel [Byte0]: 48
1760 23:42:37.201659 [Byte1]: 48
1761 23:42:37.206277
1762 23:42:37.206846 Set Vref, RX VrefLevel [Byte0]: 49
1763 23:42:37.209716 [Byte1]: 49
1764 23:42:37.213875
1765 23:42:37.214476 Set Vref, RX VrefLevel [Byte0]: 50
1766 23:42:37.217047 [Byte1]: 50
1767 23:42:37.221310
1768 23:42:37.221821 Set Vref, RX VrefLevel [Byte0]: 51
1769 23:42:37.224607 [Byte1]: 51
1770 23:42:37.229217
1771 23:42:37.229834 Set Vref, RX VrefLevel [Byte0]: 52
1772 23:42:37.232296 [Byte1]: 52
1773 23:42:37.236577
1774 23:42:37.237147 Set Vref, RX VrefLevel [Byte0]: 53
1775 23:42:37.239261 [Byte1]: 53
1776 23:42:37.243938
1777 23:42:37.244506 Set Vref, RX VrefLevel [Byte0]: 54
1778 23:42:37.247261 [Byte1]: 54
1779 23:42:37.251840
1780 23:42:37.252417 Set Vref, RX VrefLevel [Byte0]: 55
1781 23:42:37.254399 [Byte1]: 55
1782 23:42:37.259128
1783 23:42:37.259705 Set Vref, RX VrefLevel [Byte0]: 56
1784 23:42:37.262221 [Byte1]: 56
1785 23:42:37.266431
1786 23:42:37.266998 Set Vref, RX VrefLevel [Byte0]: 57
1787 23:42:37.269883 [Byte1]: 57
1788 23:42:37.274217
1789 23:42:37.274789 Set Vref, RX VrefLevel [Byte0]: 58
1790 23:42:37.277549 [Byte1]: 58
1791 23:42:37.281842
1792 23:42:37.282511 Set Vref, RX VrefLevel [Byte0]: 59
1793 23:42:37.285186 [Byte1]: 59
1794 23:42:37.289280
1795 23:42:37.289777 Set Vref, RX VrefLevel [Byte0]: 60
1796 23:42:37.292539 [Byte1]: 60
1797 23:42:37.297169
1798 23:42:37.297770 Set Vref, RX VrefLevel [Byte0]: 61
1799 23:42:37.300070 [Byte1]: 61
1800 23:42:37.304232
1801 23:42:37.304693 Set Vref, RX VrefLevel [Byte0]: 62
1802 23:42:37.307716 [Byte1]: 62
1803 23:42:37.312061
1804 23:42:37.312760 Set Vref, RX VrefLevel [Byte0]: 63
1805 23:42:37.314888 [Byte1]: 63
1806 23:42:37.319618
1807 23:42:37.320198 Set Vref, RX VrefLevel [Byte0]: 64
1808 23:42:37.322389 [Byte1]: 64
1809 23:42:37.327319
1810 23:42:37.327884 Set Vref, RX VrefLevel [Byte0]: 65
1811 23:42:37.330348 [Byte1]: 65
1812 23:42:37.334264
1813 23:42:37.334729 Set Vref, RX VrefLevel [Byte0]: 66
1814 23:42:37.337764 [Byte1]: 66
1815 23:42:37.341725
1816 23:42:37.342186 Set Vref, RX VrefLevel [Byte0]: 67
1817 23:42:37.345514 [Byte1]: 67
1818 23:42:37.349395
1819 23:42:37.350009 Set Vref, RX VrefLevel [Byte0]: 68
1820 23:42:37.352993 [Byte1]: 68
1821 23:42:37.357530
1822 23:42:37.358126 Set Vref, RX VrefLevel [Byte0]: 69
1823 23:42:37.360688 [Byte1]: 69
1824 23:42:37.365002
1825 23:42:37.365629 Set Vref, RX VrefLevel [Byte0]: 70
1826 23:42:37.367882 [Byte1]: 70
1827 23:42:37.372272
1828 23:42:37.372830 Set Vref, RX VrefLevel [Byte0]: 71
1829 23:42:37.375361 [Byte1]: 71
1830 23:42:37.379422
1831 23:42:37.379917 Set Vref, RX VrefLevel [Byte0]: 72
1832 23:42:37.382828 [Byte1]: 72
1833 23:42:37.387277
1834 23:42:37.390589 Set Vref, RX VrefLevel [Byte0]: 73
1835 23:42:37.391062 [Byte1]: 73
1836 23:42:37.394840
1837 23:42:37.395417 Set Vref, RX VrefLevel [Byte0]: 74
1838 23:42:37.398077 [Byte1]: 74
1839 23:42:37.402393
1840 23:42:37.403064 Final RX Vref Byte 0 = 55 to rank0
1841 23:42:37.405795 Final RX Vref Byte 1 = 59 to rank0
1842 23:42:37.408991 Final RX Vref Byte 0 = 55 to rank1
1843 23:42:37.412923 Final RX Vref Byte 1 = 59 to rank1==
1844 23:42:37.415545 Dram Type= 6, Freq= 0, CH_1, rank 0
1845 23:42:37.422155 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 23:42:37.422704 ==
1847 23:42:37.423076 DQS Delay:
1848 23:42:37.423420 DQS0 = 0, DQS1 = 0
1849 23:42:37.426173 DQM Delay:
1850 23:42:37.426731 DQM0 = 94, DQM1 = 90
1851 23:42:37.429276 DQ Delay:
1852 23:42:37.432549 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1853 23:42:37.433013 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1854 23:42:37.435965 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
1855 23:42:37.442547 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =96
1856 23:42:37.443122
1857 23:42:37.443492
1858 23:42:37.449068 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4b, (MSB)MR19= 0x606, tDQSOscB0 = 391 ps tDQSOscB1 = 397 ps
1859 23:42:37.452417 CH1 RK0: MR19=606, MR18=2F4B
1860 23:42:37.459390 CH1_RK0: MR19=0x606, MR18=0x2F4B, DQSOSC=391, MR23=63, INC=96, DEC=64
1861 23:42:37.459956
1862 23:42:37.462452 ----->DramcWriteLeveling(PI) begin...
1863 23:42:37.462919 ==
1864 23:42:37.466017 Dram Type= 6, Freq= 0, CH_1, rank 1
1865 23:42:37.469702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1866 23:42:37.470170 ==
1867 23:42:37.472484 Write leveling (Byte 0): 25 => 25
1868 23:42:37.476387 Write leveling (Byte 1): 29 => 29
1869 23:42:37.479647 DramcWriteLeveling(PI) end<-----
1870 23:42:37.480206
1871 23:42:37.480575 ==
1872 23:42:37.482490 Dram Type= 6, Freq= 0, CH_1, rank 1
1873 23:42:37.486110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1874 23:42:37.486575 ==
1875 23:42:37.489733 [Gating] SW mode calibration
1876 23:42:37.495901 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1877 23:42:37.502353 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1878 23:42:37.505691 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1879 23:42:37.509148 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1880 23:42:37.515788 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 23:42:37.519161 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 23:42:37.522486 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 23:42:37.529420 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 23:42:37.532459 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 23:42:37.536235 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 23:42:37.542829 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 23:42:37.545991 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 23:42:37.549514 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 23:42:37.552681 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 23:42:37.559559 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 23:42:37.562616 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 23:42:37.566161 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 23:42:37.572743 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 23:42:37.575752 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 23:42:37.579704 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1896 23:42:37.586180 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 23:42:37.589090 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 23:42:37.592545 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 23:42:37.599218 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 23:42:37.603107 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 23:42:37.606280 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 23:42:37.612937 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 23:42:37.615817 0 9 4 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
1904 23:42:37.619640 0 9 8 | B1->B0 | 3434 3030 | 1 1 | (1 1) (0 0)
1905 23:42:37.622653 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 23:42:37.629675 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 23:42:37.632681 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 23:42:37.636557 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1909 23:42:37.642901 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1910 23:42:37.646075 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
1911 23:42:37.649377 0 10 4 | B1->B0 | 2929 3333 | 0 0 | (0 0) (1 0)
1912 23:42:37.656236 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1913 23:42:37.659261 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 23:42:37.662619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 23:42:37.669706 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 23:42:37.673106 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 23:42:37.676614 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 23:42:37.683270 0 11 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1919 23:42:37.686457 0 11 4 | B1->B0 | 3a3a 2d2d | 0 0 | (0 0) (0 0)
1920 23:42:37.689674 0 11 8 | B1->B0 | 4646 4141 | 0 0 | (0 0) (1 1)
1921 23:42:37.696039 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 23:42:37.699304 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 23:42:37.703297 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 23:42:37.709835 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 23:42:37.712927 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1926 23:42:37.717004 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1927 23:42:37.719899 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1928 23:42:37.726511 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1929 23:42:37.730004 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 23:42:37.732670 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 23:42:37.739581 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 23:42:37.743307 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 23:42:37.746224 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 23:42:37.753117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 23:42:37.756920 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 23:42:37.759695 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 23:42:37.766096 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 23:42:37.769804 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 23:42:37.773100 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 23:42:37.779579 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 23:42:37.782733 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 23:42:37.786526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1943 23:42:37.793158 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1944 23:42:37.795938 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1945 23:42:37.799086 Total UI for P1: 0, mck2ui 16
1946 23:42:37.802673 best dqsien dly found for B0: ( 0, 14, 4)
1947 23:42:37.805974 Total UI for P1: 0, mck2ui 16
1948 23:42:37.809599 best dqsien dly found for B1: ( 0, 14, 2)
1949 23:42:37.813512 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1950 23:42:37.816592 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1951 23:42:37.817155
1952 23:42:37.819719 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1953 23:42:37.822890 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1954 23:42:37.826291 [Gating] SW calibration Done
1955 23:42:37.826855 ==
1956 23:42:37.829565 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 23:42:37.832692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 23:42:37.833350 ==
1959 23:42:37.836460 RX Vref Scan: 0
1960 23:42:37.837027
1961 23:42:37.839677 RX Vref 0 -> 0, step: 1
1962 23:42:37.840245
1963 23:42:37.840618 RX Delay -130 -> 252, step: 16
1964 23:42:37.845854 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1965 23:42:37.850057 iDelay=222, Bit 1, Center 93 (-2 ~ 189) 192
1966 23:42:37.852890 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1967 23:42:37.855882 iDelay=222, Bit 3, Center 93 (-2 ~ 189) 192
1968 23:42:37.859631 iDelay=222, Bit 4, Center 93 (-2 ~ 189) 192
1969 23:42:37.863264 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1970 23:42:37.869350 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1971 23:42:37.873275 iDelay=222, Bit 7, Center 101 (-2 ~ 205) 208
1972 23:42:37.876288 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1973 23:42:37.879602 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1974 23:42:37.883112 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1975 23:42:37.889754 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1976 23:42:37.893001 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1977 23:42:37.896181 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1978 23:42:37.899909 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1979 23:42:37.906389 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1980 23:42:37.906854 ==
1981 23:42:37.909341 Dram Type= 6, Freq= 0, CH_1, rank 1
1982 23:42:37.912813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1983 23:42:37.913379 ==
1984 23:42:37.913804 DQS Delay:
1985 23:42:37.915879 DQS0 = 0, DQS1 = 0
1986 23:42:37.916397 DQM Delay:
1987 23:42:37.919274 DQM0 = 96, DQM1 = 90
1988 23:42:37.919836 DQ Delay:
1989 23:42:37.922340 DQ0 =101, DQ1 =93, DQ2 =77, DQ3 =93
1990 23:42:37.926213 DQ4 =93, DQ5 =109, DQ6 =101, DQ7 =101
1991 23:42:37.929698 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1992 23:42:37.932493 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1993 23:42:37.932954
1994 23:42:37.933440
1995 23:42:37.933834 ==
1996 23:42:37.936083 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 23:42:37.939360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 23:42:37.942868 ==
1999 23:42:37.943431
2000 23:42:37.943799
2001 23:42:37.944140 TX Vref Scan disable
2002 23:42:37.945866 == TX Byte 0 ==
2003 23:42:37.949477 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
2004 23:42:37.952705 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
2005 23:42:37.956061 == TX Byte 1 ==
2006 23:42:37.959167 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2007 23:42:37.962887 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2008 23:42:37.965698 ==
2009 23:42:37.966161 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 23:42:37.972510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 23:42:37.973068 ==
2012 23:42:37.984914 TX Vref=22, minBit 5, minWin=26, winSum=442
2013 23:42:37.988412 TX Vref=24, minBit 5, minWin=26, winSum=444
2014 23:42:37.991477 TX Vref=26, minBit 0, minWin=27, winSum=447
2015 23:42:37.995107 TX Vref=28, minBit 0, minWin=27, winSum=451
2016 23:42:37.999487 TX Vref=30, minBit 5, minWin=26, winSum=449
2017 23:42:38.001614 TX Vref=32, minBit 0, minWin=27, winSum=448
2018 23:42:38.008906 [TxChooseVref] Worse bit 0, Min win 27, Win sum 451, Final Vref 28
2019 23:42:38.009471
2020 23:42:38.011918 Final TX Range 1 Vref 28
2021 23:42:38.012479
2022 23:42:38.012846 ==
2023 23:42:38.015650 Dram Type= 6, Freq= 0, CH_1, rank 1
2024 23:42:38.018466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2025 23:42:38.018929 ==
2026 23:42:38.019297
2027 23:42:38.019636
2028 23:42:38.022020 TX Vref Scan disable
2029 23:42:38.025693 == TX Byte 0 ==
2030 23:42:38.028817 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
2031 23:42:38.031827 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
2032 23:42:38.034856 == TX Byte 1 ==
2033 23:42:38.038344 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2034 23:42:38.041945 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2035 23:42:38.042508
2036 23:42:38.045460 [DATLAT]
2037 23:42:38.046061 Freq=800, CH1 RK1
2038 23:42:38.046436
2039 23:42:38.048480 DATLAT Default: 0xa
2040 23:42:38.049034 0, 0xFFFF, sum = 0
2041 23:42:38.051605 1, 0xFFFF, sum = 0
2042 23:42:38.052077 2, 0xFFFF, sum = 0
2043 23:42:38.054785 3, 0xFFFF, sum = 0
2044 23:42:38.055254 4, 0xFFFF, sum = 0
2045 23:42:38.058516 5, 0xFFFF, sum = 0
2046 23:42:38.059082 6, 0xFFFF, sum = 0
2047 23:42:38.061553 7, 0xFFFF, sum = 0
2048 23:42:38.062047 8, 0xFFFF, sum = 0
2049 23:42:38.064993 9, 0x0, sum = 1
2050 23:42:38.065525 10, 0x0, sum = 2
2051 23:42:38.068242 11, 0x0, sum = 3
2052 23:42:38.068712 12, 0x0, sum = 4
2053 23:42:38.071729 best_step = 10
2054 23:42:38.072188
2055 23:42:38.072554 ==
2056 23:42:38.075654 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 23:42:38.078466 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 23:42:38.078932 ==
2059 23:42:38.081836 RX Vref Scan: 0
2060 23:42:38.082294
2061 23:42:38.082665 RX Vref 0 -> 0, step: 1
2062 23:42:38.083012
2063 23:42:38.085438 RX Delay -79 -> 252, step: 8
2064 23:42:38.089032 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2065 23:42:38.095987 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2066 23:42:38.098810 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2067 23:42:38.102268 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2068 23:42:38.105934 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2069 23:42:38.109181 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2070 23:42:38.112249 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2071 23:42:38.119418 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2072 23:42:38.122438 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2073 23:42:38.125871 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2074 23:42:38.129443 iDelay=209, Bit 10, Center 88 (-15 ~ 192) 208
2075 23:42:38.132432 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2076 23:42:38.139155 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2077 23:42:38.142299 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2078 23:42:38.146217 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2079 23:42:38.148862 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2080 23:42:38.149420 ==
2081 23:42:38.152509 Dram Type= 6, Freq= 0, CH_1, rank 1
2082 23:42:38.155706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2083 23:42:38.159366 ==
2084 23:42:38.159924 DQS Delay:
2085 23:42:38.160292 DQS0 = 0, DQS1 = 0
2086 23:42:38.162499 DQM Delay:
2087 23:42:38.162959 DQM0 = 97, DQM1 = 90
2088 23:42:38.165638 DQ Delay:
2089 23:42:38.168977 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2090 23:42:38.172704 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2091 23:42:38.175666 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =88
2092 23:42:38.179069 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2093 23:42:38.179629
2094 23:42:38.180000
2095 23:42:38.185950 [DQSOSCAuto] RK1, (LSB)MR18= 0x4610, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
2096 23:42:38.189353 CH1 RK1: MR19=606, MR18=4610
2097 23:42:38.196237 CH1_RK1: MR19=0x606, MR18=0x4610, DQSOSC=392, MR23=63, INC=96, DEC=64
2098 23:42:38.199220 [RxdqsGatingPostProcess] freq 800
2099 23:42:38.202472 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2100 23:42:38.205441 Pre-setting of DQS Precalculation
2101 23:42:38.213055 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2102 23:42:38.218984 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2103 23:42:38.225642 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2104 23:42:38.226194
2105 23:42:38.226564
2106 23:42:38.229482 [Calibration Summary] 1600 Mbps
2107 23:42:38.230101 CH 0, Rank 0
2108 23:42:38.232355 SW Impedance : PASS
2109 23:42:38.236100 DUTY Scan : NO K
2110 23:42:38.236662 ZQ Calibration : PASS
2111 23:42:38.239270 Jitter Meter : NO K
2112 23:42:38.242140 CBT Training : PASS
2113 23:42:38.242602 Write leveling : PASS
2114 23:42:38.246272 RX DQS gating : PASS
2115 23:42:38.246832 RX DQ/DQS(RDDQC) : PASS
2116 23:42:38.249323 TX DQ/DQS : PASS
2117 23:42:38.252535 RX DATLAT : PASS
2118 23:42:38.253098 RX DQ/DQS(Engine): PASS
2119 23:42:38.255514 TX OE : NO K
2120 23:42:38.255977 All Pass.
2121 23:42:38.256343
2122 23:42:38.259127 CH 0, Rank 1
2123 23:42:38.259689 SW Impedance : PASS
2124 23:42:38.262103 DUTY Scan : NO K
2125 23:42:38.265902 ZQ Calibration : PASS
2126 23:42:38.266471 Jitter Meter : NO K
2127 23:42:38.268986 CBT Training : PASS
2128 23:42:38.272096 Write leveling : PASS
2129 23:42:38.272563 RX DQS gating : PASS
2130 23:42:38.275977 RX DQ/DQS(RDDQC) : PASS
2131 23:42:38.279142 TX DQ/DQS : PASS
2132 23:42:38.279614 RX DATLAT : PASS
2133 23:42:38.281983 RX DQ/DQS(Engine): PASS
2134 23:42:38.286034 TX OE : NO K
2135 23:42:38.286601 All Pass.
2136 23:42:38.286970
2137 23:42:38.287311 CH 1, Rank 0
2138 23:42:38.288840 SW Impedance : PASS
2139 23:42:38.292299 DUTY Scan : NO K
2140 23:42:38.292762 ZQ Calibration : PASS
2141 23:42:38.295704 Jitter Meter : NO K
2142 23:42:38.296262 CBT Training : PASS
2143 23:42:38.299262 Write leveling : PASS
2144 23:42:38.302401 RX DQS gating : PASS
2145 23:42:38.302969 RX DQ/DQS(RDDQC) : PASS
2146 23:42:38.305471 TX DQ/DQS : PASS
2147 23:42:38.308989 RX DATLAT : PASS
2148 23:42:38.309549 RX DQ/DQS(Engine): PASS
2149 23:42:38.312480 TX OE : NO K
2150 23:42:38.313042 All Pass.
2151 23:42:38.313413
2152 23:42:38.315826 CH 1, Rank 1
2153 23:42:38.316281 SW Impedance : PASS
2154 23:42:38.319198 DUTY Scan : NO K
2155 23:42:38.322302 ZQ Calibration : PASS
2156 23:42:38.322924 Jitter Meter : NO K
2157 23:42:38.325716 CBT Training : PASS
2158 23:42:38.326283 Write leveling : PASS
2159 23:42:38.329394 RX DQS gating : PASS
2160 23:42:38.332656 RX DQ/DQS(RDDQC) : PASS
2161 23:42:38.333202 TX DQ/DQS : PASS
2162 23:42:38.336249 RX DATLAT : PASS
2163 23:42:38.339122 RX DQ/DQS(Engine): PASS
2164 23:42:38.339684 TX OE : NO K
2165 23:42:38.342394 All Pass.
2166 23:42:38.342853
2167 23:42:38.343222 DramC Write-DBI off
2168 23:42:38.346621 PER_BANK_REFRESH: Hybrid Mode
2169 23:42:38.349639 TX_TRACKING: ON
2170 23:42:38.352694 [GetDramInforAfterCalByMRR] Vendor 6.
2171 23:42:38.355813 [GetDramInforAfterCalByMRR] Revision 606.
2172 23:42:38.358926 [GetDramInforAfterCalByMRR] Revision 2 0.
2173 23:42:38.359387 MR0 0x3b3b
2174 23:42:38.359755 MR8 0x5151
2175 23:42:38.362606 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2176 23:42:38.365887
2177 23:42:38.366452 MR0 0x3b3b
2178 23:42:38.366824 MR8 0x5151
2179 23:42:38.368946 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2180 23:42:38.369410
2181 23:42:38.379339 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2182 23:42:38.382164 [FAST_K] Save calibration result to emmc
2183 23:42:38.386010 [FAST_K] Save calibration result to emmc
2184 23:42:38.389862 dram_init: config_dvfs: 1
2185 23:42:38.393074 dramc_set_vcore_voltage set vcore to 662500
2186 23:42:38.395962 Read voltage for 1200, 2
2187 23:42:38.396529 Vio18 = 0
2188 23:42:38.396903 Vcore = 662500
2189 23:42:38.398940 Vdram = 0
2190 23:42:38.399404 Vddq = 0
2191 23:42:38.399882 Vmddr = 0
2192 23:42:38.405824 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2193 23:42:38.409507 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2194 23:42:38.413127 MEM_TYPE=3, freq_sel=15
2195 23:42:38.416053 sv_algorithm_assistance_LP4_1600
2196 23:42:38.419192 ============ PULL DRAM RESETB DOWN ============
2197 23:42:38.422655 ========== PULL DRAM RESETB DOWN end =========
2198 23:42:38.429483 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2199 23:42:38.432412 ===================================
2200 23:42:38.432882 LPDDR4 DRAM CONFIGURATION
2201 23:42:38.435802 ===================================
2202 23:42:38.439163 EX_ROW_EN[0] = 0x0
2203 23:42:38.442806 EX_ROW_EN[1] = 0x0
2204 23:42:38.443356 LP4Y_EN = 0x0
2205 23:42:38.445990 WORK_FSP = 0x0
2206 23:42:38.446453 WL = 0x4
2207 23:42:38.449452 RL = 0x4
2208 23:42:38.450158 BL = 0x2
2209 23:42:38.453195 RPST = 0x0
2210 23:42:38.453818 RD_PRE = 0x0
2211 23:42:38.456130 WR_PRE = 0x1
2212 23:42:38.456594 WR_PST = 0x0
2213 23:42:38.459935 DBI_WR = 0x0
2214 23:42:38.460502 DBI_RD = 0x0
2215 23:42:38.462928 OTF = 0x1
2216 23:42:38.466142 ===================================
2217 23:42:38.469609 ===================================
2218 23:42:38.470084 ANA top config
2219 23:42:38.472752 ===================================
2220 23:42:38.476071 DLL_ASYNC_EN = 0
2221 23:42:38.479808 ALL_SLAVE_EN = 0
2222 23:42:38.480380 NEW_RANK_MODE = 1
2223 23:42:38.482994 DLL_IDLE_MODE = 1
2224 23:42:38.485885 LP45_APHY_COMB_EN = 1
2225 23:42:38.490082 TX_ODT_DIS = 1
2226 23:42:38.492661 NEW_8X_MODE = 1
2227 23:42:38.493133 ===================================
2228 23:42:38.495884 ===================================
2229 23:42:38.500109 data_rate = 2400
2230 23:42:38.502471 CKR = 1
2231 23:42:38.506154 DQ_P2S_RATIO = 8
2232 23:42:38.509267 ===================================
2233 23:42:38.512921 CA_P2S_RATIO = 8
2234 23:42:38.516671 DQ_CA_OPEN = 0
2235 23:42:38.517139 DQ_SEMI_OPEN = 0
2236 23:42:38.519943 CA_SEMI_OPEN = 0
2237 23:42:38.522824 CA_FULL_RATE = 0
2238 23:42:38.525797 DQ_CKDIV4_EN = 0
2239 23:42:38.529684 CA_CKDIV4_EN = 0
2240 23:42:38.532450 CA_PREDIV_EN = 0
2241 23:42:38.535888 PH8_DLY = 17
2242 23:42:38.536391 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2243 23:42:38.539367 DQ_AAMCK_DIV = 4
2244 23:42:38.543304 CA_AAMCK_DIV = 4
2245 23:42:38.546235 CA_ADMCK_DIV = 4
2246 23:42:38.549772 DQ_TRACK_CA_EN = 0
2247 23:42:38.550343 CA_PICK = 1200
2248 23:42:38.552947 CA_MCKIO = 1200
2249 23:42:38.556092 MCKIO_SEMI = 0
2250 23:42:38.560215 PLL_FREQ = 2366
2251 23:42:38.562759 DQ_UI_PI_RATIO = 32
2252 23:42:38.566934 CA_UI_PI_RATIO = 0
2253 23:42:38.569896 ===================================
2254 23:42:38.573154 ===================================
2255 23:42:38.573779 memory_type:LPDDR4
2256 23:42:38.576759 GP_NUM : 10
2257 23:42:38.580155 SRAM_EN : 1
2258 23:42:38.580724 MD32_EN : 0
2259 23:42:38.583352 ===================================
2260 23:42:38.586290 [ANA_INIT] >>>>>>>>>>>>>>
2261 23:42:38.590061 <<<<<< [CONFIGURE PHASE]: ANA_TX
2262 23:42:38.592967 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2263 23:42:38.596937 ===================================
2264 23:42:38.600057 data_rate = 2400,PCW = 0X5b00
2265 23:42:38.602894 ===================================
2266 23:42:38.606803 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2267 23:42:38.609957 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2268 23:42:38.616349 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2269 23:42:38.619665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2270 23:42:38.622937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2271 23:42:38.626086 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2272 23:42:38.630119 [ANA_INIT] flow start
2273 23:42:38.633007 [ANA_INIT] PLL >>>>>>>>
2274 23:42:38.633426 [ANA_INIT] PLL <<<<<<<<
2275 23:42:38.636361 [ANA_INIT] MIDPI >>>>>>>>
2276 23:42:38.639657 [ANA_INIT] MIDPI <<<<<<<<
2277 23:42:38.640178 [ANA_INIT] DLL >>>>>>>>
2278 23:42:38.643152 [ANA_INIT] DLL <<<<<<<<
2279 23:42:38.646391 [ANA_INIT] flow end
2280 23:42:38.650090 ============ LP4 DIFF to SE enter ============
2281 23:42:38.653148 ============ LP4 DIFF to SE exit ============
2282 23:42:38.656605 [ANA_INIT] <<<<<<<<<<<<<
2283 23:42:38.659835 [Flow] Enable top DCM control >>>>>
2284 23:42:38.663014 [Flow] Enable top DCM control <<<<<
2285 23:42:38.666390 Enable DLL master slave shuffle
2286 23:42:38.669465 ==============================================================
2287 23:42:38.672926 Gating Mode config
2288 23:42:38.679725 ==============================================================
2289 23:42:38.680305 Config description:
2290 23:42:38.689508 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2291 23:42:38.696681 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2292 23:42:38.699786 SELPH_MODE 0: By rank 1: By Phase
2293 23:42:38.706983 ==============================================================
2294 23:42:38.710070 GAT_TRACK_EN = 1
2295 23:42:38.713175 RX_GATING_MODE = 2
2296 23:42:38.717091 RX_GATING_TRACK_MODE = 2
2297 23:42:38.720162 SELPH_MODE = 1
2298 23:42:38.723394 PICG_EARLY_EN = 1
2299 23:42:38.726855 VALID_LAT_VALUE = 1
2300 23:42:38.730313 ==============================================================
2301 23:42:38.733013 Enter into Gating configuration >>>>
2302 23:42:38.736894 Exit from Gating configuration <<<<
2303 23:42:38.740321 Enter into DVFS_PRE_config >>>>>
2304 23:42:38.750160 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2305 23:42:38.753350 Exit from DVFS_PRE_config <<<<<
2306 23:42:38.756987 Enter into PICG configuration >>>>
2307 23:42:38.760586 Exit from PICG configuration <<<<
2308 23:42:38.763179 [RX_INPUT] configuration >>>>>
2309 23:42:38.767008 [RX_INPUT] configuration <<<<<
2310 23:42:38.773370 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2311 23:42:38.776931 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2312 23:42:38.783488 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 23:42:38.790158 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 23:42:38.797035 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2315 23:42:38.803382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2316 23:42:38.806707 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2317 23:42:38.810116 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2318 23:42:38.813417 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2319 23:42:38.816971 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2320 23:42:38.823756 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2321 23:42:38.826649 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 23:42:38.830406 ===================================
2323 23:42:38.833671 LPDDR4 DRAM CONFIGURATION
2324 23:42:38.836804 ===================================
2325 23:42:38.837374 EX_ROW_EN[0] = 0x0
2326 23:42:38.840626 EX_ROW_EN[1] = 0x0
2327 23:42:38.841291 LP4Y_EN = 0x0
2328 23:42:38.843389 WORK_FSP = 0x0
2329 23:42:38.843851 WL = 0x4
2330 23:42:38.846741 RL = 0x4
2331 23:42:38.847308 BL = 0x2
2332 23:42:38.850227 RPST = 0x0
2333 23:42:38.850801 RD_PRE = 0x0
2334 23:42:38.853424 WR_PRE = 0x1
2335 23:42:38.853922 WR_PST = 0x0
2336 23:42:38.856703 DBI_WR = 0x0
2337 23:42:38.859927 DBI_RD = 0x0
2338 23:42:38.860391 OTF = 0x1
2339 23:42:38.863817 ===================================
2340 23:42:38.866603 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2341 23:42:38.870598 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2342 23:42:38.877245 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2343 23:42:38.880104 ===================================
2344 23:42:38.880676 LPDDR4 DRAM CONFIGURATION
2345 23:42:38.883137 ===================================
2346 23:42:38.887086 EX_ROW_EN[0] = 0x10
2347 23:42:38.889965 EX_ROW_EN[1] = 0x0
2348 23:42:38.890429 LP4Y_EN = 0x0
2349 23:42:38.893417 WORK_FSP = 0x0
2350 23:42:38.894017 WL = 0x4
2351 23:42:38.896767 RL = 0x4
2352 23:42:38.897334 BL = 0x2
2353 23:42:38.900635 RPST = 0x0
2354 23:42:38.901196 RD_PRE = 0x0
2355 23:42:38.903487 WR_PRE = 0x1
2356 23:42:38.903952 WR_PST = 0x0
2357 23:42:38.907104 DBI_WR = 0x0
2358 23:42:38.907567 DBI_RD = 0x0
2359 23:42:38.909893 OTF = 0x1
2360 23:42:38.913092 ===================================
2361 23:42:38.919784 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2362 23:42:38.920223 ==
2363 23:42:38.923366 Dram Type= 6, Freq= 0, CH_0, rank 0
2364 23:42:38.926495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 23:42:38.926917 ==
2366 23:42:38.929753 [Duty_Offset_Calibration]
2367 23:42:38.930168 B0:2 B1:1 CA:1
2368 23:42:38.930502
2369 23:42:38.934473 [DutyScan_Calibration_Flow] k_type=0
2370 23:42:38.943913
2371 23:42:38.944428 ==CLK 0==
2372 23:42:38.946927 Final CLK duty delay cell = 0
2373 23:42:38.950301 [0] MAX Duty = 5156%(X100), DQS PI = 22
2374 23:42:38.953720 [0] MIN Duty = 4875%(X100), DQS PI = 0
2375 23:42:38.954142 [0] AVG Duty = 5015%(X100)
2376 23:42:38.957528
2377 23:42:38.958113 CH0 CLK Duty spec in!! Max-Min= 281%
2378 23:42:38.963676 [DutyScan_Calibration_Flow] ====Done====
2379 23:42:38.964202
2380 23:42:38.966949 [DutyScan_Calibration_Flow] k_type=1
2381 23:42:38.981555
2382 23:42:38.982147 ==DQS 0 ==
2383 23:42:38.985137 Final DQS duty delay cell = -4
2384 23:42:38.987959 [-4] MAX Duty = 5156%(X100), DQS PI = 24
2385 23:42:38.991129 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2386 23:42:38.994905 [-4] AVG Duty = 4969%(X100)
2387 23:42:38.995366
2388 23:42:38.995731 ==DQS 1 ==
2389 23:42:38.998021 Final DQS duty delay cell = -4
2390 23:42:39.001519 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2391 23:42:39.004935 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2392 23:42:39.008320 [-4] AVG Duty = 4906%(X100)
2393 23:42:39.008894
2394 23:42:39.011414 CH0 DQS 0 Duty spec in!! Max-Min= 374%
2395 23:42:39.011876
2396 23:42:39.015408 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2397 23:42:39.019005 [DutyScan_Calibration_Flow] ====Done====
2398 23:42:39.019574
2399 23:42:39.022399 [DutyScan_Calibration_Flow] k_type=3
2400 23:42:39.039065
2401 23:42:39.039628 ==DQM 0 ==
2402 23:42:39.042236 Final DQM duty delay cell = 0
2403 23:42:39.045849 [0] MAX Duty = 5156%(X100), DQS PI = 30
2404 23:42:39.048664 [0] MIN Duty = 4906%(X100), DQS PI = 52
2405 23:42:39.051991 [0] AVG Duty = 5031%(X100)
2406 23:42:39.052561
2407 23:42:39.052936 ==DQM 1 ==
2408 23:42:39.055286 Final DQM duty delay cell = 0
2409 23:42:39.059029 [0] MAX Duty = 5093%(X100), DQS PI = 0
2410 23:42:39.061855 [0] MIN Duty = 5031%(X100), DQS PI = 18
2411 23:42:39.062421 [0] AVG Duty = 5062%(X100)
2412 23:42:39.065380
2413 23:42:39.068409 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2414 23:42:39.068875
2415 23:42:39.072881 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2416 23:42:39.075550 [DutyScan_Calibration_Flow] ====Done====
2417 23:42:39.076114
2418 23:42:39.078984 [DutyScan_Calibration_Flow] k_type=2
2419 23:42:39.095185
2420 23:42:39.095743 ==DQ 0 ==
2421 23:42:39.098524 Final DQ duty delay cell = 0
2422 23:42:39.101715 [0] MAX Duty = 5062%(X100), DQS PI = 32
2423 23:42:39.104929 [0] MIN Duty = 4875%(X100), DQS PI = 0
2424 23:42:39.105386 [0] AVG Duty = 4968%(X100)
2425 23:42:39.105808
2426 23:42:39.107999 ==DQ 1 ==
2427 23:42:39.111757 Final DQ duty delay cell = 0
2428 23:42:39.115147 [0] MAX Duty = 5093%(X100), DQS PI = 24
2429 23:42:39.118603 [0] MIN Duty = 4938%(X100), DQS PI = 36
2430 23:42:39.119172 [0] AVG Duty = 5015%(X100)
2431 23:42:39.119539
2432 23:42:39.121733 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2433 23:42:39.122193
2434 23:42:39.125743 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2435 23:42:39.132030 [DutyScan_Calibration_Flow] ====Done====
2436 23:42:39.132593 ==
2437 23:42:39.135436 Dram Type= 6, Freq= 0, CH_1, rank 0
2438 23:42:39.138594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2439 23:42:39.139161 ==
2440 23:42:39.142056 [Duty_Offset_Calibration]
2441 23:42:39.142628 B0:1 B1:0 CA:0
2442 23:42:39.142998
2443 23:42:39.145336 [DutyScan_Calibration_Flow] k_type=0
2444 23:42:39.154371
2445 23:42:39.154942 ==CLK 0==
2446 23:42:39.157572 Final CLK duty delay cell = -4
2447 23:42:39.161080 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2448 23:42:39.164947 [-4] MIN Duty = 4875%(X100), DQS PI = 50
2449 23:42:39.167835 [-4] AVG Duty = 4953%(X100)
2450 23:42:39.168543
2451 23:42:39.171100 CH1 CLK Duty spec in!! Max-Min= 156%
2452 23:42:39.174550 [DutyScan_Calibration_Flow] ====Done====
2453 23:42:39.175013
2454 23:42:39.177617 [DutyScan_Calibration_Flow] k_type=1
2455 23:42:39.193781
2456 23:42:39.194322 ==DQS 0 ==
2457 23:42:39.197305 Final DQS duty delay cell = 0
2458 23:42:39.200513 [0] MAX Duty = 5094%(X100), DQS PI = 26
2459 23:42:39.203865 [0] MIN Duty = 4875%(X100), DQS PI = 0
2460 23:42:39.204520 [0] AVG Duty = 4984%(X100)
2461 23:42:39.207247
2462 23:42:39.207708 ==DQS 1 ==
2463 23:42:39.211114 Final DQS duty delay cell = 0
2464 23:42:39.213796 [0] MAX Duty = 5156%(X100), DQS PI = 18
2465 23:42:39.217452 [0] MIN Duty = 4969%(X100), DQS PI = 10
2466 23:42:39.218074 [0] AVG Duty = 5062%(X100)
2467 23:42:39.220652
2468 23:42:39.224196 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2469 23:42:39.224961
2470 23:42:39.227812 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2471 23:42:39.231261 [DutyScan_Calibration_Flow] ====Done====
2472 23:42:39.231831
2473 23:42:39.234521 [DutyScan_Calibration_Flow] k_type=3
2474 23:42:39.250566
2475 23:42:39.251127 ==DQM 0 ==
2476 23:42:39.254122 Final DQM duty delay cell = 0
2477 23:42:39.257856 [0] MAX Duty = 5156%(X100), DQS PI = 6
2478 23:42:39.260807 [0] MIN Duty = 5031%(X100), DQS PI = 0
2479 23:42:39.261372 [0] AVG Duty = 5093%(X100)
2480 23:42:39.261809
2481 23:42:39.264545 ==DQM 1 ==
2482 23:42:39.267473 Final DQM duty delay cell = 0
2483 23:42:39.270806 [0] MAX Duty = 5031%(X100), DQS PI = 16
2484 23:42:39.273952 [0] MIN Duty = 4907%(X100), DQS PI = 34
2485 23:42:39.274514 [0] AVG Duty = 4969%(X100)
2486 23:42:39.274885
2487 23:42:39.277931 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2488 23:42:39.280814
2489 23:42:39.284736 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2490 23:42:39.287334 [DutyScan_Calibration_Flow] ====Done====
2491 23:42:39.287795
2492 23:42:39.290822 [DutyScan_Calibration_Flow] k_type=2
2493 23:42:39.306630
2494 23:42:39.307232 ==DQ 0 ==
2495 23:42:39.309276 Final DQ duty delay cell = -4
2496 23:42:39.312912 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2497 23:42:39.316109 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2498 23:42:39.320197 [-4] AVG Duty = 5000%(X100)
2499 23:42:39.320912
2500 23:42:39.321501 ==DQ 1 ==
2501 23:42:39.322860 Final DQ duty delay cell = 0
2502 23:42:39.326297 [0] MAX Duty = 5125%(X100), DQS PI = 20
2503 23:42:39.330412 [0] MIN Duty = 4969%(X100), DQS PI = 12
2504 23:42:39.330876 [0] AVG Duty = 5047%(X100)
2505 23:42:39.331242
2506 23:42:39.333388 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2507 23:42:39.336532
2508 23:42:39.340230 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2509 23:42:39.342947 [DutyScan_Calibration_Flow] ====Done====
2510 23:42:39.346632 nWR fixed to 30
2511 23:42:39.347400 [ModeRegInit_LP4] CH0 RK0
2512 23:42:39.349813 [ModeRegInit_LP4] CH0 RK1
2513 23:42:39.353246 [ModeRegInit_LP4] CH1 RK0
2514 23:42:39.353746 [ModeRegInit_LP4] CH1 RK1
2515 23:42:39.356307 match AC timing 7
2516 23:42:39.359550 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2517 23:42:39.363271 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2518 23:42:39.369973 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2519 23:42:39.373200 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2520 23:42:39.379890 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2521 23:42:39.380420 ==
2522 23:42:39.383068 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 23:42:39.386590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 23:42:39.387014 ==
2525 23:42:39.392762 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2526 23:42:39.396558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2527 23:42:39.407012 [CA 0] Center 39 (8~70) winsize 63
2528 23:42:39.409992 [CA 1] Center 39 (8~70) winsize 63
2529 23:42:39.413661 [CA 2] Center 35 (5~66) winsize 62
2530 23:42:39.416615 [CA 3] Center 34 (4~65) winsize 62
2531 23:42:39.420059 [CA 4] Center 33 (3~64) winsize 62
2532 23:42:39.423148 [CA 5] Center 32 (3~62) winsize 60
2533 23:42:39.423724
2534 23:42:39.427172 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2535 23:42:39.427738
2536 23:42:39.430412 [CATrainingPosCal] consider 1 rank data
2537 23:42:39.433722 u2DelayCellTimex100 = 270/100 ps
2538 23:42:39.436348 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2539 23:42:39.440196 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2540 23:42:39.443413 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2541 23:42:39.450174 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2542 23:42:39.453164 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2543 23:42:39.456895 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2544 23:42:39.457398
2545 23:42:39.459990 CA PerBit enable=1, Macro0, CA PI delay=32
2546 23:42:39.460447
2547 23:42:39.463871 [CBTSetCACLKResult] CA Dly = 32
2548 23:42:39.464393 CS Dly: 6 (0~37)
2549 23:42:39.464727 ==
2550 23:42:39.466518 Dram Type= 6, Freq= 0, CH_0, rank 1
2551 23:42:39.473535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2552 23:42:39.474156 ==
2553 23:42:39.476511 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2554 23:42:39.483488 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2555 23:42:39.492338 [CA 0] Center 38 (8~69) winsize 62
2556 23:42:39.495344 [CA 1] Center 38 (8~69) winsize 62
2557 23:42:39.499016 [CA 2] Center 35 (4~66) winsize 63
2558 23:42:39.502623 [CA 3] Center 34 (4~65) winsize 62
2559 23:42:39.505685 [CA 4] Center 33 (3~64) winsize 62
2560 23:42:39.508646 [CA 5] Center 32 (3~62) winsize 60
2561 23:42:39.509113
2562 23:42:39.511962 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2563 23:42:39.512390
2564 23:42:39.515843 [CATrainingPosCal] consider 2 rank data
2565 23:42:39.519071 u2DelayCellTimex100 = 270/100 ps
2566 23:42:39.522038 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2567 23:42:39.525643 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2568 23:42:39.532594 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2569 23:42:39.535408 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2570 23:42:39.538976 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2571 23:42:39.542259 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2572 23:42:39.542685
2573 23:42:39.545375 CA PerBit enable=1, Macro0, CA PI delay=32
2574 23:42:39.545930
2575 23:42:39.549182 [CBTSetCACLKResult] CA Dly = 32
2576 23:42:39.549781 CS Dly: 6 (0~38)
2577 23:42:39.550130
2578 23:42:39.552262 ----->DramcWriteLeveling(PI) begin...
2579 23:42:39.555519 ==
2580 23:42:39.556055 Dram Type= 6, Freq= 0, CH_0, rank 0
2581 23:42:39.562537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2582 23:42:39.563072 ==
2583 23:42:39.565979 Write leveling (Byte 0): 32 => 32
2584 23:42:39.568554 Write leveling (Byte 1): 29 => 29
2585 23:42:39.572303 DramcWriteLeveling(PI) end<-----
2586 23:42:39.572730
2587 23:42:39.573065 ==
2588 23:42:39.575435 Dram Type= 6, Freq= 0, CH_0, rank 0
2589 23:42:39.579040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2590 23:42:39.579576 ==
2591 23:42:39.582090 [Gating] SW mode calibration
2592 23:42:39.588800 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2593 23:42:39.592077 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2594 23:42:39.598640 0 15 0 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)
2595 23:42:39.602017 0 15 4 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
2596 23:42:39.605541 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 23:42:39.612136 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 23:42:39.616098 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 23:42:39.618715 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2600 23:42:39.625081 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2601 23:42:39.628892 0 15 28 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
2602 23:42:39.632082 1 0 0 | B1->B0 | 2626 2323 | 1 0 | (1 0) (0 0)
2603 23:42:39.638832 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 23:42:39.641783 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 23:42:39.645552 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 23:42:39.652066 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 23:42:39.655513 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2608 23:42:39.658663 1 0 24 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
2609 23:42:39.665047 1 0 28 | B1->B0 | 2424 4444 | 1 0 | (0 0) (0 0)
2610 23:42:39.668343 1 1 0 | B1->B0 | 3a3a 4646 | 0 0 | (1 1) (0 0)
2611 23:42:39.671970 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 23:42:39.679074 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 23:42:39.681858 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 23:42:39.685379 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 23:42:39.688993 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2616 23:42:39.695305 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2617 23:42:39.698953 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2618 23:42:39.702086 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2619 23:42:39.708612 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 23:42:39.712388 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 23:42:39.715261 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 23:42:39.722223 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 23:42:39.725469 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 23:42:39.728758 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 23:42:39.735647 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 23:42:39.738722 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 23:42:39.742080 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 23:42:39.748819 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 23:42:39.752321 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 23:42:39.755497 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 23:42:39.762123 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 23:42:39.765606 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2633 23:42:39.769046 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2634 23:42:39.775846 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2635 23:42:39.776387 Total UI for P1: 0, mck2ui 16
2636 23:42:39.778838 best dqsien dly found for B0: ( 1, 3, 26)
2637 23:42:39.782512 Total UI for P1: 0, mck2ui 16
2638 23:42:39.785838 best dqsien dly found for B1: ( 1, 3, 30)
2639 23:42:39.789133 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2640 23:42:39.795183 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2641 23:42:39.795693
2642 23:42:39.798986 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2643 23:42:39.802594 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2644 23:42:39.805853 [Gating] SW calibration Done
2645 23:42:39.806430 ==
2646 23:42:39.809033 Dram Type= 6, Freq= 0, CH_0, rank 0
2647 23:42:39.812137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2648 23:42:39.812716 ==
2649 23:42:39.813090 RX Vref Scan: 0
2650 23:42:39.813435
2651 23:42:39.815276 RX Vref 0 -> 0, step: 1
2652 23:42:39.815930
2653 23:42:39.819212 RX Delay -40 -> 252, step: 8
2654 23:42:39.822320 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2655 23:42:39.826036 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2656 23:42:39.832584 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2657 23:42:39.835548 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2658 23:42:39.839231 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2659 23:42:39.842513 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2660 23:42:39.845679 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2661 23:42:39.852215 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2662 23:42:39.855868 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2663 23:42:39.859166 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2664 23:42:39.862762 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2665 23:42:39.865726 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2666 23:42:39.869399 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2667 23:42:39.875400 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2668 23:42:39.878941 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2669 23:42:39.882094 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2670 23:42:39.882584 ==
2671 23:42:39.885732 Dram Type= 6, Freq= 0, CH_0, rank 0
2672 23:42:39.888834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2673 23:42:39.892265 ==
2674 23:42:39.892723 DQS Delay:
2675 23:42:39.893071 DQS0 = 0, DQS1 = 0
2676 23:42:39.895472 DQM Delay:
2677 23:42:39.895932 DQM0 = 121, DQM1 = 113
2678 23:42:39.899164 DQ Delay:
2679 23:42:39.902287 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2680 23:42:39.905773 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2681 23:42:39.908917 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2682 23:42:39.912445 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2683 23:42:39.913019
2684 23:42:39.913393
2685 23:42:39.913806 ==
2686 23:42:39.915726 Dram Type= 6, Freq= 0, CH_0, rank 0
2687 23:42:39.919204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2688 23:42:39.919781 ==
2689 23:42:39.920245
2690 23:42:39.920611
2691 23:42:39.922141 TX Vref Scan disable
2692 23:42:39.925487 == TX Byte 0 ==
2693 23:42:39.929259 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2694 23:42:39.932238 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2695 23:42:39.936189 == TX Byte 1 ==
2696 23:42:39.939025 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2697 23:42:39.942319 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2698 23:42:39.942893 ==
2699 23:42:39.945732 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 23:42:39.952285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 23:42:39.952846 ==
2702 23:42:39.962529 TX Vref=22, minBit 0, minWin=25, winSum=409
2703 23:42:39.966271 TX Vref=24, minBit 1, minWin=25, winSum=417
2704 23:42:39.969300 TX Vref=26, minBit 1, minWin=25, winSum=421
2705 23:42:39.972781 TX Vref=28, minBit 0, minWin=26, winSum=425
2706 23:42:39.976005 TX Vref=30, minBit 0, minWin=26, winSum=424
2707 23:42:39.983178 TX Vref=32, minBit 14, minWin=25, winSum=425
2708 23:42:39.985691 [TxChooseVref] Worse bit 0, Min win 26, Win sum 425, Final Vref 28
2709 23:42:39.986222
2710 23:42:39.989128 Final TX Range 1 Vref 28
2711 23:42:39.989629
2712 23:42:39.990008 ==
2713 23:42:39.992242 Dram Type= 6, Freq= 0, CH_0, rank 0
2714 23:42:39.995477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2715 23:42:39.995939 ==
2716 23:42:39.999282
2717 23:42:39.999852
2718 23:42:40.000292 TX Vref Scan disable
2719 23:42:40.002392 == TX Byte 0 ==
2720 23:42:40.005967 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2721 23:42:40.008961 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2722 23:42:40.012622 == TX Byte 1 ==
2723 23:42:40.016245 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2724 23:42:40.019413 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2725 23:42:40.022576
2726 23:42:40.023127 [DATLAT]
2727 23:42:40.023507 Freq=1200, CH0 RK0
2728 23:42:40.023854
2729 23:42:40.025780 DATLAT Default: 0xd
2730 23:42:40.026251 0, 0xFFFF, sum = 0
2731 23:42:40.028928 1, 0xFFFF, sum = 0
2732 23:42:40.029547 2, 0xFFFF, sum = 0
2733 23:42:40.032681 3, 0xFFFF, sum = 0
2734 23:42:40.033405 4, 0xFFFF, sum = 0
2735 23:42:40.036082 5, 0xFFFF, sum = 0
2736 23:42:40.038879 6, 0xFFFF, sum = 0
2737 23:42:40.039314 7, 0xFFFF, sum = 0
2738 23:42:40.042188 8, 0xFFFF, sum = 0
2739 23:42:40.042622 9, 0xFFFF, sum = 0
2740 23:42:40.045482 10, 0xFFFF, sum = 0
2741 23:42:40.045963 11, 0xFFFF, sum = 0
2742 23:42:40.048864 12, 0x0, sum = 1
2743 23:42:40.049297 13, 0x0, sum = 2
2744 23:42:40.052497 14, 0x0, sum = 3
2745 23:42:40.053063 15, 0x0, sum = 4
2746 23:42:40.053421 best_step = 13
2747 23:42:40.053808
2748 23:42:40.055696 ==
2749 23:42:40.059447 Dram Type= 6, Freq= 0, CH_0, rank 0
2750 23:42:40.062520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2751 23:42:40.063056 ==
2752 23:42:40.063397 RX Vref Scan: 1
2753 23:42:40.063712
2754 23:42:40.065744 Set Vref Range= 32 -> 127
2755 23:42:40.066274
2756 23:42:40.069405 RX Vref 32 -> 127, step: 1
2757 23:42:40.069988
2758 23:42:40.072519 RX Delay -13 -> 252, step: 4
2759 23:42:40.072942
2760 23:42:40.075394 Set Vref, RX VrefLevel [Byte0]: 32
2761 23:42:40.079579 [Byte1]: 32
2762 23:42:40.080118
2763 23:42:40.082423 Set Vref, RX VrefLevel [Byte0]: 33
2764 23:42:40.085643 [Byte1]: 33
2765 23:42:40.086066
2766 23:42:40.088964 Set Vref, RX VrefLevel [Byte0]: 34
2767 23:42:40.092804 [Byte1]: 34
2768 23:42:40.096793
2769 23:42:40.097252 Set Vref, RX VrefLevel [Byte0]: 35
2770 23:42:40.100360 [Byte1]: 35
2771 23:42:40.105104
2772 23:42:40.105713 Set Vref, RX VrefLevel [Byte0]: 36
2773 23:42:40.108105 [Byte1]: 36
2774 23:42:40.112711
2775 23:42:40.113298 Set Vref, RX VrefLevel [Byte0]: 37
2776 23:42:40.116009 [Byte1]: 37
2777 23:42:40.120670
2778 23:42:40.121236 Set Vref, RX VrefLevel [Byte0]: 38
2779 23:42:40.124502 [Byte1]: 38
2780 23:42:40.128431
2781 23:42:40.128999 Set Vref, RX VrefLevel [Byte0]: 39
2782 23:42:40.132056 [Byte1]: 39
2783 23:42:40.136446
2784 23:42:40.137086 Set Vref, RX VrefLevel [Byte0]: 40
2785 23:42:40.139562 [Byte1]: 40
2786 23:42:40.144430
2787 23:42:40.145005 Set Vref, RX VrefLevel [Byte0]: 41
2788 23:42:40.147635 [Byte1]: 41
2789 23:42:40.152066
2790 23:42:40.152657 Set Vref, RX VrefLevel [Byte0]: 42
2791 23:42:40.154994 [Byte1]: 42
2792 23:42:40.160161
2793 23:42:40.160735 Set Vref, RX VrefLevel [Byte0]: 43
2794 23:42:40.163344 [Byte1]: 43
2795 23:42:40.168248
2796 23:42:40.168884 Set Vref, RX VrefLevel [Byte0]: 44
2797 23:42:40.171428 [Byte1]: 44
2798 23:42:40.175785
2799 23:42:40.176355 Set Vref, RX VrefLevel [Byte0]: 45
2800 23:42:40.178576 [Byte1]: 45
2801 23:42:40.183581
2802 23:42:40.184164 Set Vref, RX VrefLevel [Byte0]: 46
2803 23:42:40.190369 [Byte1]: 46
2804 23:42:40.190955
2805 23:42:40.193673 Set Vref, RX VrefLevel [Byte0]: 47
2806 23:42:40.196629 [Byte1]: 47
2807 23:42:40.197096
2808 23:42:40.200307 Set Vref, RX VrefLevel [Byte0]: 48
2809 23:42:40.203232 [Byte1]: 48
2810 23:42:40.207350
2811 23:42:40.207819 Set Vref, RX VrefLevel [Byte0]: 49
2812 23:42:40.210611 [Byte1]: 49
2813 23:42:40.215203
2814 23:42:40.215771 Set Vref, RX VrefLevel [Byte0]: 50
2815 23:42:40.218591 [Byte1]: 50
2816 23:42:40.223298
2817 23:42:40.223853 Set Vref, RX VrefLevel [Byte0]: 51
2818 23:42:40.226512 [Byte1]: 51
2819 23:42:40.230696
2820 23:42:40.231256 Set Vref, RX VrefLevel [Byte0]: 52
2821 23:42:40.234617 [Byte1]: 52
2822 23:42:40.238434
2823 23:42:40.238897 Set Vref, RX VrefLevel [Byte0]: 53
2824 23:42:40.242087 [Byte1]: 53
2825 23:42:40.246583
2826 23:42:40.247146 Set Vref, RX VrefLevel [Byte0]: 54
2827 23:42:40.249751 [Byte1]: 54
2828 23:42:40.254710
2829 23:42:40.255274 Set Vref, RX VrefLevel [Byte0]: 55
2830 23:42:40.258265 [Byte1]: 55
2831 23:42:40.262309
2832 23:42:40.262814 Set Vref, RX VrefLevel [Byte0]: 56
2833 23:42:40.265817 [Byte1]: 56
2834 23:42:40.270376
2835 23:42:40.270942 Set Vref, RX VrefLevel [Byte0]: 57
2836 23:42:40.273797 [Byte1]: 57
2837 23:42:40.278233
2838 23:42:40.278723 Set Vref, RX VrefLevel [Byte0]: 58
2839 23:42:40.281676 [Byte1]: 58
2840 23:42:40.286006
2841 23:42:40.286579 Set Vref, RX VrefLevel [Byte0]: 59
2842 23:42:40.289009 [Byte1]: 59
2843 23:42:40.293766
2844 23:42:40.294226 Set Vref, RX VrefLevel [Byte0]: 60
2845 23:42:40.296822 [Byte1]: 60
2846 23:42:40.302291
2847 23:42:40.302813 Set Vref, RX VrefLevel [Byte0]: 61
2848 23:42:40.305478 [Byte1]: 61
2849 23:42:40.310191
2850 23:42:40.310711 Set Vref, RX VrefLevel [Byte0]: 62
2851 23:42:40.313101 [Byte1]: 62
2852 23:42:40.317993
2853 23:42:40.318557 Set Vref, RX VrefLevel [Byte0]: 63
2854 23:42:40.321454 [Byte1]: 63
2855 23:42:40.325743
2856 23:42:40.326325 Set Vref, RX VrefLevel [Byte0]: 64
2857 23:42:40.328892 [Byte1]: 64
2858 23:42:40.333720
2859 23:42:40.334286 Set Vref, RX VrefLevel [Byte0]: 65
2860 23:42:40.337080 [Byte1]: 65
2861 23:42:40.341570
2862 23:42:40.342197 Set Vref, RX VrefLevel [Byte0]: 66
2863 23:42:40.344561 [Byte1]: 66
2864 23:42:40.349387
2865 23:42:40.350009 Set Vref, RX VrefLevel [Byte0]: 67
2866 23:42:40.352941 [Byte1]: 67
2867 23:42:40.357213
2868 23:42:40.357853 Set Vref, RX VrefLevel [Byte0]: 68
2869 23:42:40.360804 [Byte1]: 68
2870 23:42:40.365422
2871 23:42:40.366039 Set Vref, RX VrefLevel [Byte0]: 69
2872 23:42:40.368721 [Byte1]: 69
2873 23:42:40.372656
2874 23:42:40.373217 Set Vref, RX VrefLevel [Byte0]: 70
2875 23:42:40.375943 [Byte1]: 70
2876 23:42:40.380856
2877 23:42:40.381466 Final RX Vref Byte 0 = 56 to rank0
2878 23:42:40.383837 Final RX Vref Byte 1 = 48 to rank0
2879 23:42:40.387358 Final RX Vref Byte 0 = 56 to rank1
2880 23:42:40.390440 Final RX Vref Byte 1 = 48 to rank1==
2881 23:42:40.394084 Dram Type= 6, Freq= 0, CH_0, rank 0
2882 23:42:40.400544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2883 23:42:40.401078 ==
2884 23:42:40.401415 DQS Delay:
2885 23:42:40.401809 DQS0 = 0, DQS1 = 0
2886 23:42:40.404079 DQM Delay:
2887 23:42:40.404496 DQM0 = 120, DQM1 = 111
2888 23:42:40.407041 DQ Delay:
2889 23:42:40.410306 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
2890 23:42:40.413647 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2891 23:42:40.417405 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =104
2892 23:42:40.420550 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =122
2893 23:42:40.420977
2894 23:42:40.421308
2895 23:42:40.430613 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2896 23:42:40.431126 CH0 RK0: MR19=404, MR18=160F
2897 23:42:40.437521 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2898 23:42:40.438141
2899 23:42:40.441053 ----->DramcWriteLeveling(PI) begin...
2900 23:42:40.441628 ==
2901 23:42:40.444371 Dram Type= 6, Freq= 0, CH_0, rank 1
2902 23:42:40.447315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2903 23:42:40.450478 ==
2904 23:42:40.451004 Write leveling (Byte 0): 33 => 33
2905 23:42:40.453699 Write leveling (Byte 1): 28 => 28
2906 23:42:40.458056 DramcWriteLeveling(PI) end<-----
2907 23:42:40.458580
2908 23:42:40.458916 ==
2909 23:42:40.460952 Dram Type= 6, Freq= 0, CH_0, rank 1
2910 23:42:40.467503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2911 23:42:40.468067 ==
2912 23:42:40.468415 [Gating] SW mode calibration
2913 23:42:40.477198 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2914 23:42:40.480758 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2915 23:42:40.484447 0 15 0 | B1->B0 | 3232 2e2e | 1 1 | (1 1) (0 0)
2916 23:42:40.490909 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2917 23:42:40.493870 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2918 23:42:40.497141 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2919 23:42:40.504404 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2920 23:42:40.507381 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2921 23:42:40.511163 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2922 23:42:40.517396 0 15 28 | B1->B0 | 2e2e 2d2d | 0 0 | (0 1) (0 1)
2923 23:42:40.521195 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2924 23:42:40.524260 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2925 23:42:40.530442 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2926 23:42:40.534093 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2927 23:42:40.537327 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2928 23:42:40.544484 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2929 23:42:40.547286 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2930 23:42:40.550801 1 0 28 | B1->B0 | 3939 3a3a | 1 0 | (0 0) (0 0)
2931 23:42:40.557512 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2932 23:42:40.561113 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2933 23:42:40.564166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2934 23:42:40.568039 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 23:42:40.574436 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2936 23:42:40.577646 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2937 23:42:40.580739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2938 23:42:40.587604 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2939 23:42:40.591591 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2940 23:42:40.594580 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2941 23:42:40.600801 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2942 23:42:40.604523 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2943 23:42:40.607441 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2944 23:42:40.614556 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2945 23:42:40.618023 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2946 23:42:40.621173 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2947 23:42:40.627803 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2948 23:42:40.630689 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2949 23:42:40.634449 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2950 23:42:40.640669 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 23:42:40.644475 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 23:42:40.647638 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 23:42:40.654220 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2954 23:42:40.657489 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2955 23:42:40.661288 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2956 23:42:40.667906 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2957 23:42:40.668469 Total UI for P1: 0, mck2ui 16
2958 23:42:40.670683 best dqsien dly found for B0: ( 1, 3, 28)
2959 23:42:40.674370 Total UI for P1: 0, mck2ui 16
2960 23:42:40.677418 best dqsien dly found for B1: ( 1, 3, 28)
2961 23:42:40.680957 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2962 23:42:40.683862 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2963 23:42:40.687369
2964 23:42:40.691065 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2965 23:42:40.694204 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2966 23:42:40.697643 [Gating] SW calibration Done
2967 23:42:40.698128 ==
2968 23:42:40.700660 Dram Type= 6, Freq= 0, CH_0, rank 1
2969 23:42:40.704643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2970 23:42:40.705205 ==
2971 23:42:40.705544 RX Vref Scan: 0
2972 23:42:40.705922
2973 23:42:40.708000 RX Vref 0 -> 0, step: 1
2974 23:42:40.708420
2975 23:42:40.710519 RX Delay -40 -> 252, step: 8
2976 23:42:40.713939 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2977 23:42:40.717857 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2978 23:42:40.724327 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2979 23:42:40.727824 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2980 23:42:40.730696 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2981 23:42:40.734448 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2982 23:42:40.737738 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2983 23:42:40.744634 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2984 23:42:40.747623 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2985 23:42:40.751401 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2986 23:42:40.754207 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2987 23:42:40.757807 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2988 23:42:40.764206 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2989 23:42:40.767787 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2990 23:42:40.770666 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2991 23:42:40.774154 iDelay=200, Bit 15, Center 119 (56 ~ 183) 128
2992 23:42:40.774621 ==
2993 23:42:40.777380 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 23:42:40.780991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 23:42:40.784568 ==
2996 23:42:40.785082 DQS Delay:
2997 23:42:40.785413 DQS0 = 0, DQS1 = 0
2998 23:42:40.787655 DQM Delay:
2999 23:42:40.788074 DQM0 = 121, DQM1 = 111
3000 23:42:40.791019 DQ Delay:
3001 23:42:40.794485 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
3002 23:42:40.797648 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
3003 23:42:40.801054 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =103
3004 23:42:40.804597 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =119
3005 23:42:40.805153
3006 23:42:40.805517
3007 23:42:40.805960 ==
3008 23:42:40.807784 Dram Type= 6, Freq= 0, CH_0, rank 1
3009 23:42:40.810743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3010 23:42:40.811292 ==
3011 23:42:40.811671
3012 23:42:40.812015
3013 23:42:40.814945 TX Vref Scan disable
3014 23:42:40.817956 == TX Byte 0 ==
3015 23:42:40.821078 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3016 23:42:40.824740 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3017 23:42:40.828305 == TX Byte 1 ==
3018 23:42:40.830922 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3019 23:42:40.834187 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3020 23:42:40.834649 ==
3021 23:42:40.838367 Dram Type= 6, Freq= 0, CH_0, rank 1
3022 23:42:40.841397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3023 23:42:40.844742 ==
3024 23:42:40.854656 TX Vref=22, minBit 3, minWin=25, winSum=423
3025 23:42:40.858163 TX Vref=24, minBit 1, minWin=26, winSum=429
3026 23:42:40.861711 TX Vref=26, minBit 1, minWin=26, winSum=427
3027 23:42:40.864721 TX Vref=28, minBit 0, minWin=26, winSum=432
3028 23:42:40.868653 TX Vref=30, minBit 3, minWin=26, winSum=433
3029 23:42:40.875163 TX Vref=32, minBit 0, minWin=26, winSum=429
3030 23:42:40.878056 [TxChooseVref] Worse bit 3, Min win 26, Win sum 433, Final Vref 30
3031 23:42:40.878519
3032 23:42:40.881567 Final TX Range 1 Vref 30
3033 23:42:40.882230
3034 23:42:40.882801 ==
3035 23:42:40.884723 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 23:42:40.888077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 23:42:40.888546 ==
3038 23:42:40.891563
3039 23:42:40.892124
3040 23:42:40.892498 TX Vref Scan disable
3041 23:42:40.894596 == TX Byte 0 ==
3042 23:42:40.898170 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3043 23:42:40.901645 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3044 23:42:40.904990 == TX Byte 1 ==
3045 23:42:40.908476 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3046 23:42:40.910980 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3047 23:42:40.914878
3048 23:42:40.915443 [DATLAT]
3049 23:42:40.915813 Freq=1200, CH0 RK1
3050 23:42:40.916158
3051 23:42:40.918055 DATLAT Default: 0xd
3052 23:42:40.918596 0, 0xFFFF, sum = 0
3053 23:42:40.921360 1, 0xFFFF, sum = 0
3054 23:42:40.921882 2, 0xFFFF, sum = 0
3055 23:42:40.924883 3, 0xFFFF, sum = 0
3056 23:42:40.925309 4, 0xFFFF, sum = 0
3057 23:42:40.928182 5, 0xFFFF, sum = 0
3058 23:42:40.928718 6, 0xFFFF, sum = 0
3059 23:42:40.931409 7, 0xFFFF, sum = 0
3060 23:42:40.935072 8, 0xFFFF, sum = 0
3061 23:42:40.935608 9, 0xFFFF, sum = 0
3062 23:42:40.937952 10, 0xFFFF, sum = 0
3063 23:42:40.938377 11, 0xFFFF, sum = 0
3064 23:42:40.941839 12, 0x0, sum = 1
3065 23:42:40.942378 13, 0x0, sum = 2
3066 23:42:40.944916 14, 0x0, sum = 3
3067 23:42:40.945450 15, 0x0, sum = 4
3068 23:42:40.945822 best_step = 13
3069 23:42:40.946136
3070 23:42:40.948662 ==
3071 23:42:40.949201 Dram Type= 6, Freq= 0, CH_0, rank 1
3072 23:42:40.954776 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3073 23:42:40.955289 ==
3074 23:42:40.955625 RX Vref Scan: 0
3075 23:42:40.955936
3076 23:42:40.958559 RX Vref 0 -> 0, step: 1
3077 23:42:40.959090
3078 23:42:40.961840 RX Delay -13 -> 252, step: 4
3079 23:42:40.965042 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3080 23:42:40.968750 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3081 23:42:40.975035 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3082 23:42:40.978363 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3083 23:42:40.982144 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3084 23:42:40.984985 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3085 23:42:40.987899 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3086 23:42:40.995043 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3087 23:42:40.998289 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3088 23:42:41.001807 iDelay=195, Bit 9, Center 96 (31 ~ 162) 132
3089 23:42:41.005049 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3090 23:42:41.008342 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3091 23:42:41.015222 iDelay=195, Bit 12, Center 116 (55 ~ 178) 124
3092 23:42:41.018518 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3093 23:42:41.022069 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3094 23:42:41.024972 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3095 23:42:41.025500 ==
3096 23:42:41.028408 Dram Type= 6, Freq= 0, CH_0, rank 1
3097 23:42:41.034870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3098 23:42:41.035445 ==
3099 23:42:41.035816 DQS Delay:
3100 23:42:41.036156 DQS0 = 0, DQS1 = 0
3101 23:42:41.038582 DQM Delay:
3102 23:42:41.039040 DQM0 = 121, DQM1 = 110
3103 23:42:41.041702 DQ Delay:
3104 23:42:41.044817 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3105 23:42:41.048268 DQ4 =122, DQ5 =116, DQ6 =126, DQ7 =126
3106 23:42:41.051373 DQ8 =100, DQ9 =96, DQ10 =110, DQ11 =102
3107 23:42:41.054741 DQ12 =116, DQ13 =116, DQ14 =122, DQ15 =118
3108 23:42:41.055158
3109 23:42:41.055490
3110 23:42:41.061957 [DQSOSCAuto] RK1, (LSB)MR18= 0xaed, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3111 23:42:41.064848 CH0 RK1: MR19=403, MR18=AED
3112 23:42:41.071672 CH0_RK1: MR19=0x403, MR18=0xAED, DQSOSC=406, MR23=63, INC=39, DEC=26
3113 23:42:41.074747 [RxdqsGatingPostProcess] freq 1200
3114 23:42:41.081504 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3115 23:42:41.085069 best DQS0 dly(2T, 0.5T) = (0, 11)
3116 23:42:41.085641 best DQS1 dly(2T, 0.5T) = (0, 11)
3117 23:42:41.088086 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3118 23:42:41.091313 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3119 23:42:41.094547 best DQS0 dly(2T, 0.5T) = (0, 11)
3120 23:42:41.098060 best DQS1 dly(2T, 0.5T) = (0, 11)
3121 23:42:41.101225 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3122 23:42:41.105188 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3123 23:42:41.108575 Pre-setting of DQS Precalculation
3124 23:42:41.114792 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3125 23:42:41.115317 ==
3126 23:42:41.118105 Dram Type= 6, Freq= 0, CH_1, rank 0
3127 23:42:41.121516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3128 23:42:41.122087 ==
3129 23:42:41.128001 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3130 23:42:41.131379 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3131 23:42:41.141160 [CA 0] Center 37 (7~68) winsize 62
3132 23:42:41.144055 [CA 1] Center 37 (7~68) winsize 62
3133 23:42:41.147782 [CA 2] Center 35 (5~65) winsize 61
3134 23:42:41.151191 [CA 3] Center 34 (4~64) winsize 61
3135 23:42:41.154829 [CA 4] Center 34 (4~64) winsize 61
3136 23:42:41.158037 [CA 5] Center 33 (3~63) winsize 61
3137 23:42:41.158647
3138 23:42:41.161313 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3139 23:42:41.161821
3140 23:42:41.164328 [CATrainingPosCal] consider 1 rank data
3141 23:42:41.167793 u2DelayCellTimex100 = 270/100 ps
3142 23:42:41.171245 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3143 23:42:41.174830 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3144 23:42:41.177698 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3145 23:42:41.184545 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3146 23:42:41.188615 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3147 23:42:41.191044 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3148 23:42:41.191516
3149 23:42:41.195084 CA PerBit enable=1, Macro0, CA PI delay=33
3150 23:42:41.195661
3151 23:42:41.198308 [CBTSetCACLKResult] CA Dly = 33
3152 23:42:41.198777 CS Dly: 7 (0~38)
3153 23:42:41.199148 ==
3154 23:42:41.201359 Dram Type= 6, Freq= 0, CH_1, rank 1
3155 23:42:41.208435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 23:42:41.209018 ==
3157 23:42:41.211164 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3158 23:42:41.218157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3159 23:42:41.226994 [CA 0] Center 37 (7~68) winsize 62
3160 23:42:41.230188 [CA 1] Center 37 (7~68) winsize 62
3161 23:42:41.233855 [CA 2] Center 35 (5~65) winsize 61
3162 23:42:41.237026 [CA 3] Center 34 (4~65) winsize 62
3163 23:42:41.240019 [CA 4] Center 34 (4~64) winsize 61
3164 23:42:41.243445 [CA 5] Center 34 (4~64) winsize 61
3165 23:42:41.243915
3166 23:42:41.246978 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3167 23:42:41.247565
3168 23:42:41.249876 [CATrainingPosCal] consider 2 rank data
3169 23:42:41.253879 u2DelayCellTimex100 = 270/100 ps
3170 23:42:41.257061 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3171 23:42:41.260449 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3172 23:42:41.263548 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3173 23:42:41.270092 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3174 23:42:41.273670 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3175 23:42:41.276674 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3176 23:42:41.277141
3177 23:42:41.279984 CA PerBit enable=1, Macro0, CA PI delay=33
3178 23:42:41.280453
3179 23:42:41.283446 [CBTSetCACLKResult] CA Dly = 33
3180 23:42:41.284028 CS Dly: 8 (0~40)
3181 23:42:41.284401
3182 23:42:41.286743 ----->DramcWriteLeveling(PI) begin...
3183 23:42:41.287276 ==
3184 23:42:41.290121 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 23:42:41.296710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 23:42:41.297239 ==
3187 23:42:41.299829 Write leveling (Byte 0): 26 => 26
3188 23:42:41.303836 Write leveling (Byte 1): 28 => 28
3189 23:42:41.304375 DramcWriteLeveling(PI) end<-----
3190 23:42:41.306432
3191 23:42:41.306854 ==
3192 23:42:41.310157 Dram Type= 6, Freq= 0, CH_1, rank 0
3193 23:42:41.313279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3194 23:42:41.313888 ==
3195 23:42:41.316943 [Gating] SW mode calibration
3196 23:42:41.323713 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3197 23:42:41.326732 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3198 23:42:41.333613 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3199 23:42:41.337514 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3200 23:42:41.340262 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3201 23:42:41.347247 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3202 23:42:41.350137 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3203 23:42:41.353262 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3204 23:42:41.360487 0 15 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 0)
3205 23:42:41.363903 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3206 23:42:41.367213 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3207 23:42:41.373991 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3208 23:42:41.377020 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3209 23:42:41.380649 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3210 23:42:41.386885 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3211 23:42:41.390097 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3212 23:42:41.393705 1 0 24 | B1->B0 | 3535 4444 | 1 0 | (0 0) (0 0)
3213 23:42:41.396647 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3214 23:42:41.403382 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 23:42:41.407372 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3216 23:42:41.410155 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3217 23:42:41.416957 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3218 23:42:41.419843 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3219 23:42:41.423306 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3220 23:42:41.429877 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3221 23:42:41.433382 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3222 23:42:41.437199 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3223 23:42:41.443641 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3224 23:42:41.447063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3225 23:42:41.449779 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3226 23:42:41.456623 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3227 23:42:41.459965 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3228 23:42:41.463965 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3229 23:42:41.470587 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3230 23:42:41.473897 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3231 23:42:41.477089 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3232 23:42:41.484004 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3233 23:42:41.486830 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 23:42:41.490126 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 23:42:41.493770 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 23:42:41.500367 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3237 23:42:41.503876 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3238 23:42:41.507171 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3239 23:42:41.510216 Total UI for P1: 0, mck2ui 16
3240 23:42:41.513848 best dqsien dly found for B0: ( 1, 3, 26)
3241 23:42:41.517100 Total UI for P1: 0, mck2ui 16
3242 23:42:41.520313 best dqsien dly found for B1: ( 1, 3, 26)
3243 23:42:41.524160 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3244 23:42:41.527108 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3245 23:42:41.527571
3246 23:42:41.534018 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3247 23:42:41.537421 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3248 23:42:41.538052 [Gating] SW calibration Done
3249 23:42:41.540428 ==
3250 23:42:41.543834 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 23:42:41.547728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 23:42:41.548292 ==
3253 23:42:41.548660 RX Vref Scan: 0
3254 23:42:41.549110
3255 23:42:41.550387 RX Vref 0 -> 0, step: 1
3256 23:42:41.550867
3257 23:42:41.553882 RX Delay -40 -> 252, step: 8
3258 23:42:41.557183 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3259 23:42:41.560584 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3260 23:42:41.564106 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3261 23:42:41.570456 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3262 23:42:41.574023 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3263 23:42:41.577396 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3264 23:42:41.580433 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3265 23:42:41.584156 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3266 23:42:41.587778 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3267 23:42:41.593940 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3268 23:42:41.597342 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3269 23:42:41.601352 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3270 23:42:41.604248 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3271 23:42:41.610448 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3272 23:42:41.613752 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3273 23:42:41.617676 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3274 23:42:41.618260 ==
3275 23:42:41.620680 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 23:42:41.624402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 23:42:41.624994 ==
3278 23:42:41.628245 DQS Delay:
3279 23:42:41.628819 DQS0 = 0, DQS1 = 0
3280 23:42:41.629194 DQM Delay:
3281 23:42:41.631390 DQM0 = 120, DQM1 = 116
3282 23:42:41.631982 DQ Delay:
3283 23:42:41.634379 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3284 23:42:41.637967 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =123
3285 23:42:41.644398 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3286 23:42:41.648112 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3287 23:42:41.648681
3288 23:42:41.649058
3289 23:42:41.649459 ==
3290 23:42:41.650808 Dram Type= 6, Freq= 0, CH_1, rank 0
3291 23:42:41.654342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3292 23:42:41.654919 ==
3293 23:42:41.655296
3294 23:42:41.655640
3295 23:42:41.657457 TX Vref Scan disable
3296 23:42:41.658083 == TX Byte 0 ==
3297 23:42:41.664226 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3298 23:42:41.668280 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3299 23:42:41.668971 == TX Byte 1 ==
3300 23:42:41.674489 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3301 23:42:41.677951 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3302 23:42:41.678420 ==
3303 23:42:41.681155 Dram Type= 6, Freq= 0, CH_1, rank 0
3304 23:42:41.684817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3305 23:42:41.685391 ==
3306 23:42:41.697344 TX Vref=22, minBit 9, minWin=24, winSum=410
3307 23:42:41.700610 TX Vref=24, minBit 9, minWin=25, winSum=418
3308 23:42:41.703317 TX Vref=26, minBit 1, minWin=26, winSum=426
3309 23:42:41.707466 TX Vref=28, minBit 2, minWin=26, winSum=430
3310 23:42:41.710394 TX Vref=30, minBit 9, minWin=26, winSum=431
3311 23:42:41.713417 TX Vref=32, minBit 9, minWin=26, winSum=431
3312 23:42:41.720209 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 30
3313 23:42:41.720650
3314 23:42:41.723710 Final TX Range 1 Vref 30
3315 23:42:41.724152
3316 23:42:41.724487 ==
3317 23:42:41.727083 Dram Type= 6, Freq= 0, CH_1, rank 0
3318 23:42:41.730350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3319 23:42:41.730919 ==
3320 23:42:41.731269
3321 23:42:41.731584
3322 23:42:41.733654 TX Vref Scan disable
3323 23:42:41.736753 == TX Byte 0 ==
3324 23:42:41.740030 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3325 23:42:41.743569 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3326 23:42:41.746691 == TX Byte 1 ==
3327 23:42:41.750224 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3328 23:42:41.753298 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3329 23:42:41.753763
3330 23:42:41.756609 [DATLAT]
3331 23:42:41.757034 Freq=1200, CH1 RK0
3332 23:42:41.757440
3333 23:42:41.760200 DATLAT Default: 0xd
3334 23:42:41.760693 0, 0xFFFF, sum = 0
3335 23:42:41.763296 1, 0xFFFF, sum = 0
3336 23:42:41.763725 2, 0xFFFF, sum = 0
3337 23:42:41.767115 3, 0xFFFF, sum = 0
3338 23:42:41.767549 4, 0xFFFF, sum = 0
3339 23:42:41.770073 5, 0xFFFF, sum = 0
3340 23:42:41.770503 6, 0xFFFF, sum = 0
3341 23:42:41.773705 7, 0xFFFF, sum = 0
3342 23:42:41.774138 8, 0xFFFF, sum = 0
3343 23:42:41.776831 9, 0xFFFF, sum = 0
3344 23:42:41.780475 10, 0xFFFF, sum = 0
3345 23:42:41.780910 11, 0xFFFF, sum = 0
3346 23:42:41.783729 12, 0x0, sum = 1
3347 23:42:41.784164 13, 0x0, sum = 2
3348 23:42:41.784510 14, 0x0, sum = 3
3349 23:42:41.786675 15, 0x0, sum = 4
3350 23:42:41.787107 best_step = 13
3351 23:42:41.787447
3352 23:42:41.787764 ==
3353 23:42:41.790023 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 23:42:41.796627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 23:42:41.797059 ==
3356 23:42:41.797395 RX Vref Scan: 1
3357 23:42:41.797771
3358 23:42:41.800146 Set Vref Range= 32 -> 127
3359 23:42:41.800570
3360 23:42:41.803234 RX Vref 32 -> 127, step: 1
3361 23:42:41.803657
3362 23:42:41.806677 RX Delay -5 -> 252, step: 4
3363 23:42:41.807120
3364 23:42:41.810138 Set Vref, RX VrefLevel [Byte0]: 32
3365 23:42:41.813132 [Byte1]: 32
3366 23:42:41.813565
3367 23:42:41.817029 Set Vref, RX VrefLevel [Byte0]: 33
3368 23:42:41.820099 [Byte1]: 33
3369 23:42:41.820399
3370 23:42:41.823251 Set Vref, RX VrefLevel [Byte0]: 34
3371 23:42:41.827471 [Byte1]: 34
3372 23:42:41.830358
3373 23:42:41.830752 Set Vref, RX VrefLevel [Byte0]: 35
3374 23:42:41.833447 [Byte1]: 35
3375 23:42:41.838405
3376 23:42:41.838701 Set Vref, RX VrefLevel [Byte0]: 36
3377 23:42:41.841517 [Byte1]: 36
3378 23:42:41.846227
3379 23:42:41.846619 Set Vref, RX VrefLevel [Byte0]: 37
3380 23:42:41.849445 [Byte1]: 37
3381 23:42:41.854582
3382 23:42:41.855110 Set Vref, RX VrefLevel [Byte0]: 38
3383 23:42:41.857695 [Byte1]: 38
3384 23:42:41.861862
3385 23:42:41.862279 Set Vref, RX VrefLevel [Byte0]: 39
3386 23:42:41.865607 [Byte1]: 39
3387 23:42:41.869946
3388 23:42:41.870366 Set Vref, RX VrefLevel [Byte0]: 40
3389 23:42:41.873131 [Byte1]: 40
3390 23:42:41.878011
3391 23:42:41.878534 Set Vref, RX VrefLevel [Byte0]: 41
3392 23:42:41.881314 [Byte1]: 41
3393 23:42:41.885696
3394 23:42:41.886217 Set Vref, RX VrefLevel [Byte0]: 42
3395 23:42:41.889068 [Byte1]: 42
3396 23:42:41.893173
3397 23:42:41.893635 Set Vref, RX VrefLevel [Byte0]: 43
3398 23:42:41.896940 [Byte1]: 43
3399 23:42:41.901716
3400 23:42:41.902248 Set Vref, RX VrefLevel [Byte0]: 44
3401 23:42:41.904631 [Byte1]: 44
3402 23:42:41.909399
3403 23:42:41.909962 Set Vref, RX VrefLevel [Byte0]: 45
3404 23:42:41.912501 [Byte1]: 45
3405 23:42:41.916878
3406 23:42:41.917295 Set Vref, RX VrefLevel [Byte0]: 46
3407 23:42:41.920436 [Byte1]: 46
3408 23:42:41.924871
3409 23:42:41.925474 Set Vref, RX VrefLevel [Byte0]: 47
3410 23:42:41.927830 [Byte1]: 47
3411 23:42:41.932888
3412 23:42:41.933460 Set Vref, RX VrefLevel [Byte0]: 48
3413 23:42:41.936125 [Byte1]: 48
3414 23:42:41.940545
3415 23:42:41.941144 Set Vref, RX VrefLevel [Byte0]: 49
3416 23:42:41.943633 [Byte1]: 49
3417 23:42:41.948509
3418 23:42:41.949027 Set Vref, RX VrefLevel [Byte0]: 50
3419 23:42:41.952072 [Byte1]: 50
3420 23:42:41.956679
3421 23:42:41.957201 Set Vref, RX VrefLevel [Byte0]: 51
3422 23:42:41.959841 [Byte1]: 51
3423 23:42:41.964177
3424 23:42:41.964691 Set Vref, RX VrefLevel [Byte0]: 52
3425 23:42:41.967480 [Byte1]: 52
3426 23:42:41.972122
3427 23:42:41.972648 Set Vref, RX VrefLevel [Byte0]: 53
3428 23:42:41.975438 [Byte1]: 53
3429 23:42:41.979893
3430 23:42:41.980311 Set Vref, RX VrefLevel [Byte0]: 54
3431 23:42:41.982746 [Byte1]: 54
3432 23:42:41.987589
3433 23:42:41.988007 Set Vref, RX VrefLevel [Byte0]: 55
3434 23:42:41.990867 [Byte1]: 55
3435 23:42:41.995412
3436 23:42:41.995830 Set Vref, RX VrefLevel [Byte0]: 56
3437 23:42:41.998847 [Byte1]: 56
3438 23:42:42.003056
3439 23:42:42.003474 Set Vref, RX VrefLevel [Byte0]: 57
3440 23:42:42.006606 [Byte1]: 57
3441 23:42:42.011334
3442 23:42:42.011808 Set Vref, RX VrefLevel [Byte0]: 58
3443 23:42:42.014493 [Byte1]: 58
3444 23:42:42.019394
3445 23:42:42.019915 Set Vref, RX VrefLevel [Byte0]: 59
3446 23:42:42.022522 [Byte1]: 59
3447 23:42:42.027123
3448 23:42:42.027657 Set Vref, RX VrefLevel [Byte0]: 60
3449 23:42:42.030251 [Byte1]: 60
3450 23:42:42.034876
3451 23:42:42.035294 Set Vref, RX VrefLevel [Byte0]: 61
3452 23:42:42.038228 [Byte1]: 61
3453 23:42:42.042730
3454 23:42:42.043254 Set Vref, RX VrefLevel [Byte0]: 62
3455 23:42:42.045945 [Byte1]: 62
3456 23:42:42.050314
3457 23:42:42.050742 Set Vref, RX VrefLevel [Byte0]: 63
3458 23:42:42.053427 [Byte1]: 63
3459 23:42:42.057935
3460 23:42:42.058370 Set Vref, RX VrefLevel [Byte0]: 64
3461 23:42:42.061246 [Byte1]: 64
3462 23:42:42.066422
3463 23:42:42.066852 Set Vref, RX VrefLevel [Byte0]: 65
3464 23:42:42.069385 [Byte1]: 65
3465 23:42:42.074228
3466 23:42:42.074757 Set Vref, RX VrefLevel [Byte0]: 66
3467 23:42:42.077722 [Byte1]: 66
3468 23:42:42.081973
3469 23:42:42.082491 Set Vref, RX VrefLevel [Byte0]: 67
3470 23:42:42.084962 [Byte1]: 67
3471 23:42:42.089783
3472 23:42:42.090303 Set Vref, RX VrefLevel [Byte0]: 68
3473 23:42:42.093657 [Byte1]: 68
3474 23:42:42.097768
3475 23:42:42.098292 Set Vref, RX VrefLevel [Byte0]: 69
3476 23:42:42.101018 [Byte1]: 69
3477 23:42:42.105902
3478 23:42:42.106448 Final RX Vref Byte 0 = 54 to rank0
3479 23:42:42.109424 Final RX Vref Byte 1 = 48 to rank0
3480 23:42:42.111789 Final RX Vref Byte 0 = 54 to rank1
3481 23:42:42.115107 Final RX Vref Byte 1 = 48 to rank1==
3482 23:42:42.119377 Dram Type= 6, Freq= 0, CH_1, rank 0
3483 23:42:42.125723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3484 23:42:42.126257 ==
3485 23:42:42.126600 DQS Delay:
3486 23:42:42.126913 DQS0 = 0, DQS1 = 0
3487 23:42:42.128917 DQM Delay:
3488 23:42:42.129466 DQM0 = 120, DQM1 = 116
3489 23:42:42.132510 DQ Delay:
3490 23:42:42.135785 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3491 23:42:42.138902 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3492 23:42:42.141838 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =108
3493 23:42:42.146146 DQ12 =122, DQ13 =124, DQ14 =124, DQ15 =126
3494 23:42:42.146679
3495 23:42:42.147019
3496 23:42:42.152403 [DQSOSCAuto] RK0, (LSB)MR18= 0x215, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 409 ps
3497 23:42:42.155903 CH1 RK0: MR19=404, MR18=215
3498 23:42:42.161796 CH1_RK0: MR19=0x404, MR18=0x215, DQSOSC=401, MR23=63, INC=40, DEC=27
3499 23:42:42.162309
3500 23:42:42.165657 ----->DramcWriteLeveling(PI) begin...
3501 23:42:42.166093 ==
3502 23:42:42.168799 Dram Type= 6, Freq= 0, CH_1, rank 1
3503 23:42:42.172185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3504 23:42:42.172746 ==
3505 23:42:42.175452 Write leveling (Byte 0): 26 => 26
3506 23:42:42.178819 Write leveling (Byte 1): 29 => 29
3507 23:42:42.182477 DramcWriteLeveling(PI) end<-----
3508 23:42:42.183012
3509 23:42:42.183350 ==
3510 23:42:42.185354 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 23:42:42.192494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 23:42:42.193044 ==
3513 23:42:42.193382 [Gating] SW mode calibration
3514 23:42:42.198924 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3515 23:42:42.206132 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3516 23:42:42.209687 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3517 23:42:42.215822 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3518 23:42:42.219148 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3519 23:42:42.222594 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3520 23:42:42.229133 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3521 23:42:42.232661 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
3522 23:42:42.235587 0 15 24 | B1->B0 | 2727 3232 | 0 1 | (1 0) (1 0)
3523 23:42:42.242060 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3524 23:42:42.245626 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3525 23:42:42.249434 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3526 23:42:42.255823 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3527 23:42:42.259213 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3528 23:42:42.262330 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3529 23:42:42.269403 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3530 23:42:42.272465 1 0 24 | B1->B0 | 4141 2b2b | 0 0 | (0 0) (0 0)
3531 23:42:42.275442 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3532 23:42:42.282152 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3533 23:42:42.285095 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3534 23:42:42.288960 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 23:42:42.291627 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3536 23:42:42.298393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3537 23:42:42.301992 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3538 23:42:42.305383 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3539 23:42:42.312117 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3540 23:42:42.315187 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3541 23:42:42.318882 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 23:42:42.325662 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 23:42:42.328651 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 23:42:42.332164 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3545 23:42:42.338349 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3546 23:42:42.341270 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3547 23:42:42.345028 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 23:42:42.351535 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 23:42:42.354930 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 23:42:42.358029 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 23:42:42.365393 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 23:42:42.368261 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 23:42:42.371418 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3554 23:42:42.378193 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3555 23:42:42.381619 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3556 23:42:42.384725 Total UI for P1: 0, mck2ui 16
3557 23:42:42.388588 best dqsien dly found for B1: ( 1, 3, 22)
3558 23:42:42.391548 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3559 23:42:42.394679 Total UI for P1: 0, mck2ui 16
3560 23:42:42.398296 best dqsien dly found for B0: ( 1, 3, 26)
3561 23:42:42.400866 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3562 23:42:42.404814 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3563 23:42:42.405379
3564 23:42:42.411245 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3565 23:42:42.414827 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3566 23:42:42.417875 [Gating] SW calibration Done
3567 23:42:42.418337 ==
3568 23:42:42.421413 Dram Type= 6, Freq= 0, CH_1, rank 1
3569 23:42:42.424817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3570 23:42:42.425377 ==
3571 23:42:42.425805 RX Vref Scan: 0
3572 23:42:42.426154
3573 23:42:42.428111 RX Vref 0 -> 0, step: 1
3574 23:42:42.428668
3575 23:42:42.431438 RX Delay -40 -> 252, step: 8
3576 23:42:42.434563 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3577 23:42:42.437886 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3578 23:42:42.444776 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3579 23:42:42.447981 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3580 23:42:42.450926 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3581 23:42:42.454003 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3582 23:42:42.458151 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3583 23:42:42.464200 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3584 23:42:42.468114 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
3585 23:42:42.471198 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3586 23:42:42.474623 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3587 23:42:42.477816 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3588 23:42:42.484232 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3589 23:42:42.487053 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3590 23:42:42.490617 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3591 23:42:42.493766 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
3592 23:42:42.494230 ==
3593 23:42:42.497652 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 23:42:42.504221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 23:42:42.504788 ==
3596 23:42:42.505158 DQS Delay:
3597 23:42:42.507733 DQS0 = 0, DQS1 = 0
3598 23:42:42.508203 DQM Delay:
3599 23:42:42.508567 DQM0 = 120, DQM1 = 118
3600 23:42:42.510508 DQ Delay:
3601 23:42:42.514376 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3602 23:42:42.517125 DQ4 =115, DQ5 =131, DQ6 =131, DQ7 =119
3603 23:42:42.520791 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =115
3604 23:42:42.523805 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =127
3605 23:42:42.524268
3606 23:42:42.524631
3607 23:42:42.524967 ==
3608 23:42:42.527384 Dram Type= 6, Freq= 0, CH_1, rank 1
3609 23:42:42.530280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3610 23:42:42.534264 ==
3611 23:42:42.534806
3612 23:42:42.535149
3613 23:42:42.535456 TX Vref Scan disable
3614 23:42:42.537277 == TX Byte 0 ==
3615 23:42:42.540686 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3616 23:42:42.544138 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3617 23:42:42.547657 == TX Byte 1 ==
3618 23:42:42.550479 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3619 23:42:42.554021 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3620 23:42:42.557039 ==
3621 23:42:42.557570 Dram Type= 6, Freq= 0, CH_1, rank 1
3622 23:42:42.564011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3623 23:42:42.564533 ==
3624 23:42:42.574703 TX Vref=22, minBit 9, minWin=25, winSum=422
3625 23:42:42.578138 TX Vref=24, minBit 1, minWin=26, winSum=423
3626 23:42:42.581279 TX Vref=26, minBit 8, minWin=26, winSum=429
3627 23:42:42.585038 TX Vref=28, minBit 9, minWin=26, winSum=437
3628 23:42:42.588206 TX Vref=30, minBit 9, minWin=26, winSum=435
3629 23:42:42.594624 TX Vref=32, minBit 9, minWin=26, winSum=436
3630 23:42:42.597888 [TxChooseVref] Worse bit 9, Min win 26, Win sum 437, Final Vref 28
3631 23:42:42.598479
3632 23:42:42.601080 Final TX Range 1 Vref 28
3633 23:42:42.601643
3634 23:42:42.602194 ==
3635 23:42:42.604321 Dram Type= 6, Freq= 0, CH_1, rank 1
3636 23:42:42.607759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3637 23:42:42.611278 ==
3638 23:42:42.611843
3639 23:42:42.612211
3640 23:42:42.612549 TX Vref Scan disable
3641 23:42:42.614695 == TX Byte 0 ==
3642 23:42:42.617569 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3643 23:42:42.624099 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3644 23:42:42.624645 == TX Byte 1 ==
3645 23:42:42.627382 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3646 23:42:42.634530 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3647 23:42:42.634948
3648 23:42:42.635280 [DATLAT]
3649 23:42:42.635584 Freq=1200, CH1 RK1
3650 23:42:42.635884
3651 23:42:42.637102 DATLAT Default: 0xd
3652 23:42:42.637516 0, 0xFFFF, sum = 0
3653 23:42:42.640900 1, 0xFFFF, sum = 0
3654 23:42:42.644072 2, 0xFFFF, sum = 0
3655 23:42:42.644599 3, 0xFFFF, sum = 0
3656 23:42:42.647690 4, 0xFFFF, sum = 0
3657 23:42:42.648216 5, 0xFFFF, sum = 0
3658 23:42:42.650588 6, 0xFFFF, sum = 0
3659 23:42:42.651050 7, 0xFFFF, sum = 0
3660 23:42:42.654001 8, 0xFFFF, sum = 0
3661 23:42:42.654526 9, 0xFFFF, sum = 0
3662 23:42:42.657349 10, 0xFFFF, sum = 0
3663 23:42:42.657798 11, 0xFFFF, sum = 0
3664 23:42:42.660378 12, 0x0, sum = 1
3665 23:42:42.660796 13, 0x0, sum = 2
3666 23:42:42.663690 14, 0x0, sum = 3
3667 23:42:42.664112 15, 0x0, sum = 4
3668 23:42:42.667468 best_step = 13
3669 23:42:42.667881
3670 23:42:42.668209 ==
3671 23:42:42.670964 Dram Type= 6, Freq= 0, CH_1, rank 1
3672 23:42:42.674186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3673 23:42:42.674718 ==
3674 23:42:42.675099 RX Vref Scan: 0
3675 23:42:42.675419
3676 23:42:42.677439 RX Vref 0 -> 0, step: 1
3677 23:42:42.678016
3678 23:42:42.681013 RX Delay -5 -> 252, step: 4
3679 23:42:42.684266 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3680 23:42:42.690893 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3681 23:42:42.694241 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3682 23:42:42.697370 iDelay=195, Bit 3, Center 114 (55 ~ 174) 120
3683 23:42:42.700704 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3684 23:42:42.703597 iDelay=195, Bit 5, Center 132 (71 ~ 194) 124
3685 23:42:42.710741 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3686 23:42:42.713962 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3687 23:42:42.716956 iDelay=195, Bit 8, Center 104 (43 ~ 166) 124
3688 23:42:42.720726 iDelay=195, Bit 9, Center 106 (47 ~ 166) 120
3689 23:42:42.723986 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3690 23:42:42.730930 iDelay=195, Bit 11, Center 110 (51 ~ 170) 120
3691 23:42:42.733553 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3692 23:42:42.737359 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3693 23:42:42.740582 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3694 23:42:42.747036 iDelay=195, Bit 15, Center 124 (63 ~ 186) 124
3695 23:42:42.747497 ==
3696 23:42:42.750084 Dram Type= 6, Freq= 0, CH_1, rank 1
3697 23:42:42.753638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3698 23:42:42.754060 ==
3699 23:42:42.754390 DQS Delay:
3700 23:42:42.757226 DQS0 = 0, DQS1 = 0
3701 23:42:42.757828 DQM Delay:
3702 23:42:42.760557 DQM0 = 120, DQM1 = 116
3703 23:42:42.761074 DQ Delay:
3704 23:42:42.763697 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =114
3705 23:42:42.766675 DQ4 =116, DQ5 =132, DQ6 =130, DQ7 =120
3706 23:42:42.770417 DQ8 =104, DQ9 =106, DQ10 =116, DQ11 =110
3707 23:42:42.773955 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =124
3708 23:42:42.774484
3709 23:42:42.774825
3710 23:42:42.784078 [DQSOSCAuto] RK1, (LSB)MR18= 0xeeb, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3711 23:42:42.786993 CH1 RK1: MR19=403, MR18=EEB
3712 23:42:42.790388 CH1_RK1: MR19=0x403, MR18=0xEEB, DQSOSC=404, MR23=63, INC=40, DEC=26
3713 23:42:42.793715 [RxdqsGatingPostProcess] freq 1200
3714 23:42:42.800336 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3715 23:42:42.803929 best DQS0 dly(2T, 0.5T) = (0, 11)
3716 23:42:42.807174 best DQS1 dly(2T, 0.5T) = (0, 11)
3717 23:42:42.810695 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3718 23:42:42.813654 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3719 23:42:42.816791 best DQS0 dly(2T, 0.5T) = (0, 11)
3720 23:42:42.820303 best DQS1 dly(2T, 0.5T) = (0, 11)
3721 23:42:42.823510 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3722 23:42:42.826929 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3723 23:42:42.827486 Pre-setting of DQS Precalculation
3724 23:42:42.833379 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3725 23:42:42.840213 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3726 23:42:42.847015 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3727 23:42:42.847480
3728 23:42:42.847839
3729 23:42:42.850147 [Calibration Summary] 2400 Mbps
3730 23:42:42.853476 CH 0, Rank 0
3731 23:42:42.853915 SW Impedance : PASS
3732 23:42:42.856533 DUTY Scan : NO K
3733 23:42:42.860349 ZQ Calibration : PASS
3734 23:42:42.860992 Jitter Meter : NO K
3735 23:42:42.863072 CBT Training : PASS
3736 23:42:42.866536 Write leveling : PASS
3737 23:42:42.866952 RX DQS gating : PASS
3738 23:42:42.870052 RX DQ/DQS(RDDQC) : PASS
3739 23:42:42.873346 TX DQ/DQS : PASS
3740 23:42:42.873964 RX DATLAT : PASS
3741 23:42:42.876674 RX DQ/DQS(Engine): PASS
3742 23:42:42.877137 TX OE : NO K
3743 23:42:42.880103 All Pass.
3744 23:42:42.880639
3745 23:42:42.881026 CH 0, Rank 1
3746 23:42:42.883195 SW Impedance : PASS
3747 23:42:42.883763 DUTY Scan : NO K
3748 23:42:42.886506 ZQ Calibration : PASS
3749 23:42:42.890113 Jitter Meter : NO K
3750 23:42:42.890689 CBT Training : PASS
3751 23:42:42.893288 Write leveling : PASS
3752 23:42:42.896659 RX DQS gating : PASS
3753 23:42:42.897225 RX DQ/DQS(RDDQC) : PASS
3754 23:42:42.900173 TX DQ/DQS : PASS
3755 23:42:42.903144 RX DATLAT : PASS
3756 23:42:42.903894 RX DQ/DQS(Engine): PASS
3757 23:42:42.906533 TX OE : NO K
3758 23:42:42.907001 All Pass.
3759 23:42:42.907369
3760 23:42:42.910002 CH 1, Rank 0
3761 23:42:42.910463 SW Impedance : PASS
3762 23:42:42.913196 DUTY Scan : NO K
3763 23:42:42.916498 ZQ Calibration : PASS
3764 23:42:42.917057 Jitter Meter : NO K
3765 23:42:42.919724 CBT Training : PASS
3766 23:42:42.923192 Write leveling : PASS
3767 23:42:42.923770 RX DQS gating : PASS
3768 23:42:42.926278 RX DQ/DQS(RDDQC) : PASS
3769 23:42:42.926742 TX DQ/DQS : PASS
3770 23:42:42.929715 RX DATLAT : PASS
3771 23:42:42.933033 RX DQ/DQS(Engine): PASS
3772 23:42:42.933627 TX OE : NO K
3773 23:42:42.936339 All Pass.
3774 23:42:42.936827
3775 23:42:42.937194 CH 1, Rank 1
3776 23:42:42.939843 SW Impedance : PASS
3777 23:42:42.940418 DUTY Scan : NO K
3778 23:42:42.942610 ZQ Calibration : PASS
3779 23:42:42.946157 Jitter Meter : NO K
3780 23:42:42.946616 CBT Training : PASS
3781 23:42:42.949744 Write leveling : PASS
3782 23:42:42.952828 RX DQS gating : PASS
3783 23:42:42.953392 RX DQ/DQS(RDDQC) : PASS
3784 23:42:42.956721 TX DQ/DQS : PASS
3785 23:42:42.959443 RX DATLAT : PASS
3786 23:42:42.959905 RX DQ/DQS(Engine): PASS
3787 23:42:42.962686 TX OE : NO K
3788 23:42:42.963148 All Pass.
3789 23:42:42.963513
3790 23:42:42.965773 DramC Write-DBI off
3791 23:42:42.969418 PER_BANK_REFRESH: Hybrid Mode
3792 23:42:42.969912 TX_TRACKING: ON
3793 23:42:42.979633 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3794 23:42:42.982818 [FAST_K] Save calibration result to emmc
3795 23:42:42.986427 dramc_set_vcore_voltage set vcore to 650000
3796 23:42:42.989274 Read voltage for 600, 5
3797 23:42:42.989733 Vio18 = 0
3798 23:42:42.990069 Vcore = 650000
3799 23:42:42.993149 Vdram = 0
3800 23:42:42.993716 Vddq = 0
3801 23:42:42.994058 Vmddr = 0
3802 23:42:42.999789 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3803 23:42:43.002986 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3804 23:42:43.006295 MEM_TYPE=3, freq_sel=19
3805 23:42:43.009338 sv_algorithm_assistance_LP4_1600
3806 23:42:43.013051 ============ PULL DRAM RESETB DOWN ============
3807 23:42:43.015746 ========== PULL DRAM RESETB DOWN end =========
3808 23:42:43.022578 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3809 23:42:43.025955 ===================================
3810 23:42:43.026371 LPDDR4 DRAM CONFIGURATION
3811 23:42:43.028894 ===================================
3812 23:42:43.032398 EX_ROW_EN[0] = 0x0
3813 23:42:43.035704 EX_ROW_EN[1] = 0x0
3814 23:42:43.036120 LP4Y_EN = 0x0
3815 23:42:43.039312 WORK_FSP = 0x0
3816 23:42:43.039723 WL = 0x2
3817 23:42:43.042910 RL = 0x2
3818 23:42:43.043338 BL = 0x2
3819 23:42:43.046293 RPST = 0x0
3820 23:42:43.046816 RD_PRE = 0x0
3821 23:42:43.048950 WR_PRE = 0x1
3822 23:42:43.049761 WR_PST = 0x0
3823 23:42:43.052274 DBI_WR = 0x0
3824 23:42:43.052688 DBI_RD = 0x0
3825 23:42:43.055562 OTF = 0x1
3826 23:42:43.059016 ===================================
3827 23:42:43.062476 ===================================
3828 23:42:43.062899 ANA top config
3829 23:42:43.065392 ===================================
3830 23:42:43.068763 DLL_ASYNC_EN = 0
3831 23:42:43.072369 ALL_SLAVE_EN = 1
3832 23:42:43.075556 NEW_RANK_MODE = 1
3833 23:42:43.075995 DLL_IDLE_MODE = 1
3834 23:42:43.078675 LP45_APHY_COMB_EN = 1
3835 23:42:43.082181 TX_ODT_DIS = 1
3836 23:42:43.085559 NEW_8X_MODE = 1
3837 23:42:43.088544 ===================================
3838 23:42:43.092091 ===================================
3839 23:42:43.095105 data_rate = 1200
3840 23:42:43.095525 CKR = 1
3841 23:42:43.098854 DQ_P2S_RATIO = 8
3842 23:42:43.102188 ===================================
3843 23:42:43.105242 CA_P2S_RATIO = 8
3844 23:42:43.108863 DQ_CA_OPEN = 0
3845 23:42:43.112230 DQ_SEMI_OPEN = 0
3846 23:42:43.115645 CA_SEMI_OPEN = 0
3847 23:42:43.116166 CA_FULL_RATE = 0
3848 23:42:43.118936 DQ_CKDIV4_EN = 1
3849 23:42:43.122207 CA_CKDIV4_EN = 1
3850 23:42:43.125850 CA_PREDIV_EN = 0
3851 23:42:43.129496 PH8_DLY = 0
3852 23:42:43.130036 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3853 23:42:43.132709 DQ_AAMCK_DIV = 4
3854 23:42:43.135252 CA_AAMCK_DIV = 4
3855 23:42:43.138810 CA_ADMCK_DIV = 4
3856 23:42:43.142105 DQ_TRACK_CA_EN = 0
3857 23:42:43.146042 CA_PICK = 600
3858 23:42:43.149557 CA_MCKIO = 600
3859 23:42:43.150114 MCKIO_SEMI = 0
3860 23:42:43.152336 PLL_FREQ = 2288
3861 23:42:43.155587 DQ_UI_PI_RATIO = 32
3862 23:42:43.158918 CA_UI_PI_RATIO = 0
3863 23:42:43.162192 ===================================
3864 23:42:43.165676 ===================================
3865 23:42:43.168693 memory_type:LPDDR4
3866 23:42:43.169107 GP_NUM : 10
3867 23:42:43.172243 SRAM_EN : 1
3868 23:42:43.175514 MD32_EN : 0
3869 23:42:43.178653 ===================================
3870 23:42:43.179070 [ANA_INIT] >>>>>>>>>>>>>>
3871 23:42:43.181848 <<<<<< [CONFIGURE PHASE]: ANA_TX
3872 23:42:43.185731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3873 23:42:43.188710 ===================================
3874 23:42:43.192348 data_rate = 1200,PCW = 0X5800
3875 23:42:43.195457 ===================================
3876 23:42:43.199255 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3877 23:42:43.205625 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3878 23:42:43.208338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3879 23:42:43.214899 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3880 23:42:43.218588 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3881 23:42:43.222314 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3882 23:42:43.222834 [ANA_INIT] flow start
3883 23:42:43.225525 [ANA_INIT] PLL >>>>>>>>
3884 23:42:43.228606 [ANA_INIT] PLL <<<<<<<<
3885 23:42:43.229121 [ANA_INIT] MIDPI >>>>>>>>
3886 23:42:43.232013 [ANA_INIT] MIDPI <<<<<<<<
3887 23:42:43.235462 [ANA_INIT] DLL >>>>>>>>
3888 23:42:43.235878 [ANA_INIT] flow end
3889 23:42:43.242029 ============ LP4 DIFF to SE enter ============
3890 23:42:43.244698 ============ LP4 DIFF to SE exit ============
3891 23:42:43.248203 [ANA_INIT] <<<<<<<<<<<<<
3892 23:42:43.251865 [Flow] Enable top DCM control >>>>>
3893 23:42:43.255208 [Flow] Enable top DCM control <<<<<
3894 23:42:43.258916 Enable DLL master slave shuffle
3895 23:42:43.262302 ==============================================================
3896 23:42:43.265432 Gating Mode config
3897 23:42:43.268433 ==============================================================
3898 23:42:43.271955 Config description:
3899 23:42:43.281730 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3900 23:42:43.288859 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3901 23:42:43.291978 SELPH_MODE 0: By rank 1: By Phase
3902 23:42:43.298134 ==============================================================
3903 23:42:43.301726 GAT_TRACK_EN = 1
3904 23:42:43.305285 RX_GATING_MODE = 2
3905 23:42:43.308149 RX_GATING_TRACK_MODE = 2
3906 23:42:43.311747 SELPH_MODE = 1
3907 23:42:43.312314 PICG_EARLY_EN = 1
3908 23:42:43.315057 VALID_LAT_VALUE = 1
3909 23:42:43.321767 ==============================================================
3910 23:42:43.325059 Enter into Gating configuration >>>>
3911 23:42:43.328105 Exit from Gating configuration <<<<
3912 23:42:43.331635 Enter into DVFS_PRE_config >>>>>
3913 23:42:43.341898 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3914 23:42:43.344383 Exit from DVFS_PRE_config <<<<<
3915 23:42:43.347653 Enter into PICG configuration >>>>
3916 23:42:43.351401 Exit from PICG configuration <<<<
3917 23:42:43.354324 [RX_INPUT] configuration >>>>>
3918 23:42:43.357866 [RX_INPUT] configuration <<<<<
3919 23:42:43.361410 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3920 23:42:43.367939 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3921 23:42:43.374942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3922 23:42:43.381620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3923 23:42:43.388248 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3924 23:42:43.391064 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3925 23:42:43.397658 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3926 23:42:43.401481 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3927 23:42:43.404711 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3928 23:42:43.407927 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3929 23:42:43.414488 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3930 23:42:43.418305 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3931 23:42:43.421883 ===================================
3932 23:42:43.425098 LPDDR4 DRAM CONFIGURATION
3933 23:42:43.428131 ===================================
3934 23:42:43.428684 EX_ROW_EN[0] = 0x0
3935 23:42:43.431557 EX_ROW_EN[1] = 0x0
3936 23:42:43.432162 LP4Y_EN = 0x0
3937 23:42:43.434653 WORK_FSP = 0x0
3938 23:42:43.435111 WL = 0x2
3939 23:42:43.437933 RL = 0x2
3940 23:42:43.438393 BL = 0x2
3941 23:42:43.441397 RPST = 0x0
3942 23:42:43.442031 RD_PRE = 0x0
3943 23:42:43.444497 WR_PRE = 0x1
3944 23:42:43.445026 WR_PST = 0x0
3945 23:42:43.448403 DBI_WR = 0x0
3946 23:42:43.448959 DBI_RD = 0x0
3947 23:42:43.451812 OTF = 0x1
3948 23:42:43.454619 ===================================
3949 23:42:43.458415 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3950 23:42:43.461431 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3951 23:42:43.468005 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3952 23:42:43.471554 ===================================
3953 23:42:43.472143 LPDDR4 DRAM CONFIGURATION
3954 23:42:43.474678 ===================================
3955 23:42:43.477557 EX_ROW_EN[0] = 0x10
3956 23:42:43.480731 EX_ROW_EN[1] = 0x0
3957 23:42:43.481190 LP4Y_EN = 0x0
3958 23:42:43.485013 WORK_FSP = 0x0
3959 23:42:43.485616 WL = 0x2
3960 23:42:43.487936 RL = 0x2
3961 23:42:43.488496 BL = 0x2
3962 23:42:43.491184 RPST = 0x0
3963 23:42:43.491866 RD_PRE = 0x0
3964 23:42:43.494630 WR_PRE = 0x1
3965 23:42:43.495112 WR_PST = 0x0
3966 23:42:43.497624 DBI_WR = 0x0
3967 23:42:43.498087 DBI_RD = 0x0
3968 23:42:43.500712 OTF = 0x1
3969 23:42:43.504614 ===================================
3970 23:42:43.510799 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3971 23:42:43.514158 nWR fixed to 30
3972 23:42:43.517379 [ModeRegInit_LP4] CH0 RK0
3973 23:42:43.517894 [ModeRegInit_LP4] CH0 RK1
3974 23:42:43.521071 [ModeRegInit_LP4] CH1 RK0
3975 23:42:43.524507 [ModeRegInit_LP4] CH1 RK1
3976 23:42:43.525066 match AC timing 17
3977 23:42:43.530809 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3978 23:42:43.533823 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3979 23:42:43.537061 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3980 23:42:43.544375 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3981 23:42:43.547464 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3982 23:42:43.548026 ==
3983 23:42:43.550900 Dram Type= 6, Freq= 0, CH_0, rank 0
3984 23:42:43.554337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3985 23:42:43.554898 ==
3986 23:42:43.561011 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3987 23:42:43.567134 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3988 23:42:43.570858 [CA 0] Center 36 (5~67) winsize 63
3989 23:42:43.573691 [CA 1] Center 36 (5~67) winsize 63
3990 23:42:43.577055 [CA 2] Center 34 (3~65) winsize 63
3991 23:42:43.580729 [CA 3] Center 33 (2~64) winsize 63
3992 23:42:43.583942 [CA 4] Center 33 (2~64) winsize 63
3993 23:42:43.587092 [CA 5] Center 32 (2~63) winsize 62
3994 23:42:43.587648
3995 23:42:43.590493 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3996 23:42:43.591233
3997 23:42:43.593695 [CATrainingPosCal] consider 1 rank data
3998 23:42:43.597556 u2DelayCellTimex100 = 270/100 ps
3999 23:42:43.600235 CA0 delay=36 (5~67),Diff = 4 PI (38 cell)
4000 23:42:43.603829 CA1 delay=36 (5~67),Diff = 4 PI (38 cell)
4001 23:42:43.606679 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4002 23:42:43.610128 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
4003 23:42:43.613666 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4004 23:42:43.620450 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4005 23:42:43.621012
4006 23:42:43.623858 CA PerBit enable=1, Macro0, CA PI delay=32
4007 23:42:43.624422
4008 23:42:43.627080 [CBTSetCACLKResult] CA Dly = 32
4009 23:42:43.627635 CS Dly: 4 (0~35)
4010 23:42:43.628003 ==
4011 23:42:43.630290 Dram Type= 6, Freq= 0, CH_0, rank 1
4012 23:42:43.633323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4013 23:42:43.636791 ==
4014 23:42:43.640160 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4015 23:42:43.647049 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4016 23:42:43.650110 [CA 0] Center 35 (5~66) winsize 62
4017 23:42:43.653519 [CA 1] Center 35 (5~66) winsize 62
4018 23:42:43.657237 [CA 2] Center 34 (3~65) winsize 63
4019 23:42:43.660323 [CA 3] Center 33 (3~64) winsize 62
4020 23:42:43.663884 [CA 4] Center 33 (2~64) winsize 63
4021 23:42:43.666727 [CA 5] Center 32 (1~63) winsize 63
4022 23:42:43.667292
4023 23:42:43.670102 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4024 23:42:43.670561
4025 23:42:43.673661 [CATrainingPosCal] consider 2 rank data
4026 23:42:43.677080 u2DelayCellTimex100 = 270/100 ps
4027 23:42:43.680179 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4028 23:42:43.683293 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4029 23:42:43.686674 CA2 delay=34 (3~65),Diff = 2 PI (19 cell)
4030 23:42:43.692810 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4031 23:42:43.696288 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4032 23:42:43.699706 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4033 23:42:43.700262
4034 23:42:43.703093 CA PerBit enable=1, Macro0, CA PI delay=32
4035 23:42:43.703563
4036 23:42:43.706082 [CBTSetCACLKResult] CA Dly = 32
4037 23:42:43.706656 CS Dly: 4 (0~36)
4038 23:42:43.707091
4039 23:42:43.709454 ----->DramcWriteLeveling(PI) begin...
4040 23:42:43.713140 ==
4041 23:42:43.713762 Dram Type= 6, Freq= 0, CH_0, rank 0
4042 23:42:43.719653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4043 23:42:43.720198 ==
4044 23:42:43.723271 Write leveling (Byte 0): 33 => 33
4045 23:42:43.726562 Write leveling (Byte 1): 31 => 31
4046 23:42:43.729193 DramcWriteLeveling(PI) end<-----
4047 23:42:43.729708
4048 23:42:43.730084 ==
4049 23:42:43.733162 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 23:42:43.736101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 23:42:43.736566 ==
4052 23:42:43.739553 [Gating] SW mode calibration
4053 23:42:43.746283 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4054 23:42:43.749479 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4055 23:42:43.755959 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4056 23:42:43.759672 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4057 23:42:43.762898 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4058 23:42:43.769250 0 9 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
4059 23:42:43.772774 0 9 16 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
4060 23:42:43.776380 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4061 23:42:43.782496 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4062 23:42:43.786177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4063 23:42:43.789311 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4064 23:42:43.796451 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4065 23:42:43.799384 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4066 23:42:43.802761 0 10 12 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
4067 23:42:43.809553 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4068 23:42:43.812013 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 23:42:43.815652 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4070 23:42:43.822244 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4071 23:42:43.825437 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4072 23:42:43.829415 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4073 23:42:43.835763 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4074 23:42:43.838924 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4075 23:42:43.842564 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4076 23:42:43.848865 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 23:42:43.852636 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 23:42:43.855480 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 23:42:43.862039 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 23:42:43.865374 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 23:42:43.868715 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4082 23:42:43.875569 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4083 23:42:43.879136 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 23:42:43.881781 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 23:42:43.888953 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 23:42:43.892113 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 23:42:43.895447 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 23:42:43.901737 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 23:42:43.905978 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 23:42:43.908645 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4091 23:42:43.912184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4092 23:42:43.915505 Total UI for P1: 0, mck2ui 16
4093 23:42:43.918578 best dqsien dly found for B0: ( 0, 13, 12)
4094 23:42:43.921685 Total UI for P1: 0, mck2ui 16
4095 23:42:43.925500 best dqsien dly found for B1: ( 0, 13, 14)
4096 23:42:43.929231 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4097 23:42:43.935335 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4098 23:42:43.935912
4099 23:42:43.938388 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4100 23:42:43.942067 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4101 23:42:43.945548 [Gating] SW calibration Done
4102 23:42:43.946180 ==
4103 23:42:43.948948 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 23:42:43.951877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 23:42:43.952447 ==
4106 23:42:43.952821 RX Vref Scan: 0
4107 23:42:43.955513
4108 23:42:43.956085 RX Vref 0 -> 0, step: 1
4109 23:42:43.956462
4110 23:42:43.958431 RX Delay -230 -> 252, step: 16
4111 23:42:43.961688 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4112 23:42:43.968513 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4113 23:42:43.971733 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4114 23:42:43.975036 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4115 23:42:43.978447 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4116 23:42:43.985305 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4117 23:42:43.988617 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4118 23:42:43.991326 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4119 23:42:43.994699 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4120 23:42:43.997834 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4121 23:42:44.004716 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4122 23:42:44.008215 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4123 23:42:44.011864 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4124 23:42:44.014930 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4125 23:42:44.018127 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4126 23:42:44.025257 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4127 23:42:44.025873 ==
4128 23:42:44.028413 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 23:42:44.031676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 23:42:44.032240 ==
4131 23:42:44.032610 DQS Delay:
4132 23:42:44.034845 DQS0 = 0, DQS1 = 0
4133 23:42:44.035402 DQM Delay:
4134 23:42:44.038751 DQM0 = 51, DQM1 = 45
4135 23:42:44.039311 DQ Delay:
4136 23:42:44.041340 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4137 23:42:44.045241 DQ4 =49, DQ5 =41, DQ6 =65, DQ7 =65
4138 23:42:44.048974 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4139 23:42:44.051440 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4140 23:42:44.051904
4141 23:42:44.052272
4142 23:42:44.052611 ==
4143 23:42:44.054763 Dram Type= 6, Freq= 0, CH_0, rank 0
4144 23:42:44.058676 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 23:42:44.061699 ==
4146 23:42:44.062161
4147 23:42:44.062525
4148 23:42:44.062866 TX Vref Scan disable
4149 23:42:44.065152 == TX Byte 0 ==
4150 23:42:44.068109 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4151 23:42:44.071365 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4152 23:42:44.074711 == TX Byte 1 ==
4153 23:42:44.078352 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4154 23:42:44.082058 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4155 23:42:44.084606 ==
4156 23:42:44.085046 Dram Type= 6, Freq= 0, CH_0, rank 0
4157 23:42:44.092301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 23:42:44.092849 ==
4159 23:42:44.093307
4160 23:42:44.093805
4161 23:42:44.095048 TX Vref Scan disable
4162 23:42:44.095503 == TX Byte 0 ==
4163 23:42:44.101992 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4164 23:42:44.104912 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4165 23:42:44.105359 == TX Byte 1 ==
4166 23:42:44.111707 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4167 23:42:44.114660 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4168 23:42:44.115125
4169 23:42:44.115571 [DATLAT]
4170 23:42:44.118096 Freq=600, CH0 RK0
4171 23:42:44.118521
4172 23:42:44.118862 DATLAT Default: 0x9
4173 23:42:44.121090 0, 0xFFFF, sum = 0
4174 23:42:44.121557 1, 0xFFFF, sum = 0
4175 23:42:44.124700 2, 0xFFFF, sum = 0
4176 23:42:44.125262 3, 0xFFFF, sum = 0
4177 23:42:44.128173 4, 0xFFFF, sum = 0
4178 23:42:44.128623 5, 0xFFFF, sum = 0
4179 23:42:44.131553 6, 0xFFFF, sum = 0
4180 23:42:44.134898 7, 0xFFFF, sum = 0
4181 23:42:44.135448 8, 0x0, sum = 1
4182 23:42:44.135914 9, 0x0, sum = 2
4183 23:42:44.138055 10, 0x0, sum = 3
4184 23:42:44.138502 11, 0x0, sum = 4
4185 23:42:44.141454 best_step = 9
4186 23:42:44.141951
4187 23:42:44.142394 ==
4188 23:42:44.144330 Dram Type= 6, Freq= 0, CH_0, rank 0
4189 23:42:44.148156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4190 23:42:44.148727 ==
4191 23:42:44.151397 RX Vref Scan: 1
4192 23:42:44.151969
4193 23:42:44.152431 RX Vref 0 -> 0, step: 1
4194 23:42:44.152854
4195 23:42:44.154444 RX Delay -163 -> 252, step: 8
4196 23:42:44.154885
4197 23:42:44.157843 Set Vref, RX VrefLevel [Byte0]: 56
4198 23:42:44.161310 [Byte1]: 48
4199 23:42:44.164909
4200 23:42:44.165470 Final RX Vref Byte 0 = 56 to rank0
4201 23:42:44.168828 Final RX Vref Byte 1 = 48 to rank0
4202 23:42:44.171670 Final RX Vref Byte 0 = 56 to rank1
4203 23:42:44.174648 Final RX Vref Byte 1 = 48 to rank1==
4204 23:42:44.178073 Dram Type= 6, Freq= 0, CH_0, rank 0
4205 23:42:44.184680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4206 23:42:44.185108 ==
4207 23:42:44.185444 DQS Delay:
4208 23:42:44.185843 DQS0 = 0, DQS1 = 0
4209 23:42:44.188661 DQM Delay:
4210 23:42:44.189120 DQM0 = 52, DQM1 = 46
4211 23:42:44.191046 DQ Delay:
4212 23:42:44.194356 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =48
4213 23:42:44.197720 DQ4 =52, DQ5 =44, DQ6 =64, DQ7 =60
4214 23:42:44.201672 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4215 23:42:44.204430 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4216 23:42:44.204852
4217 23:42:44.205185
4218 23:42:44.211083 [DQSOSCAuto] RK0, (LSB)MR18= 0x6d60, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4219 23:42:44.214561 CH0 RK0: MR19=808, MR18=6D60
4220 23:42:44.220972 CH0_RK0: MR19=0x808, MR18=0x6D60, DQSOSC=389, MR23=63, INC=173, DEC=115
4221 23:42:44.221562
4222 23:42:44.225176 ----->DramcWriteLeveling(PI) begin...
4223 23:42:44.225749 ==
4224 23:42:44.228109 Dram Type= 6, Freq= 0, CH_0, rank 1
4225 23:42:44.231343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4226 23:42:44.231782 ==
4227 23:42:44.234449 Write leveling (Byte 0): 34 => 34
4228 23:42:44.237913 Write leveling (Byte 1): 33 => 33
4229 23:42:44.241487 DramcWriteLeveling(PI) end<-----
4230 23:42:44.242062
4231 23:42:44.242401 ==
4232 23:42:44.244988 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 23:42:44.248101 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 23:42:44.248620 ==
4235 23:42:44.251609 [Gating] SW mode calibration
4236 23:42:44.258281 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4237 23:42:44.264959 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4238 23:42:44.268426 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4239 23:42:44.271712 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4240 23:42:44.278573 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4241 23:42:44.281383 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 0) (0 1)
4242 23:42:44.284733 0 9 16 | B1->B0 | 2d2d 2727 | 1 0 | (0 0) (0 0)
4243 23:42:44.291317 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4244 23:42:44.295006 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4245 23:42:44.298310 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4246 23:42:44.304422 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4247 23:42:44.307794 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4248 23:42:44.311339 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4249 23:42:44.317573 0 10 12 | B1->B0 | 2929 2525 | 0 0 | (1 1) (0 0)
4250 23:42:44.321303 0 10 16 | B1->B0 | 3d3d 4141 | 0 0 | (0 0) (0 0)
4251 23:42:44.324514 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 23:42:44.331261 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4253 23:42:44.334287 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4254 23:42:44.338350 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4255 23:42:44.344649 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4256 23:42:44.348028 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4257 23:42:44.351485 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4258 23:42:44.357560 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4259 23:42:44.361503 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 23:42:44.364800 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 23:42:44.371050 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 23:42:44.374449 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 23:42:44.377841 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 23:42:44.384366 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4265 23:42:44.387407 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4266 23:42:44.391030 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4267 23:42:44.394427 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4268 23:42:44.400763 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 23:42:44.403980 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 23:42:44.407620 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 23:42:44.413673 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 23:42:44.417278 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 23:42:44.420454 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 23:42:44.427214 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4275 23:42:44.430917 Total UI for P1: 0, mck2ui 16
4276 23:42:44.433722 best dqsien dly found for B0: ( 0, 13, 14)
4277 23:42:44.433854 Total UI for P1: 0, mck2ui 16
4278 23:42:44.440692 best dqsien dly found for B1: ( 0, 13, 14)
4279 23:42:44.443855 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4280 23:42:44.446837 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4281 23:42:44.446970
4282 23:42:44.450240 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4283 23:42:44.453895 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4284 23:42:44.456802 [Gating] SW calibration Done
4285 23:42:44.456936 ==
4286 23:42:44.460203 Dram Type= 6, Freq= 0, CH_0, rank 1
4287 23:42:44.463560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4288 23:42:44.463697 ==
4289 23:42:44.467141 RX Vref Scan: 0
4290 23:42:44.467274
4291 23:42:44.467380 RX Vref 0 -> 0, step: 1
4292 23:42:44.467478
4293 23:42:44.470453 RX Delay -230 -> 252, step: 16
4294 23:42:44.476630 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4295 23:42:44.479869 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4296 23:42:44.483631 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4297 23:42:44.486659 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4298 23:42:44.490059 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4299 23:42:44.496918 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4300 23:42:44.500598 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4301 23:42:44.503361 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4302 23:42:44.506485 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4303 23:42:44.510297 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4304 23:42:44.516913 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4305 23:42:44.520103 iDelay=218, Bit 11, Center 41 (-102 ~ 185) 288
4306 23:42:44.523501 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4307 23:42:44.526994 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4308 23:42:44.533928 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4309 23:42:44.537235 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4310 23:42:44.537700 ==
4311 23:42:44.540489 Dram Type= 6, Freq= 0, CH_0, rank 1
4312 23:42:44.543704 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4313 23:42:44.544133 ==
4314 23:42:44.547105 DQS Delay:
4315 23:42:44.547531 DQS0 = 0, DQS1 = 0
4316 23:42:44.547871 DQM Delay:
4317 23:42:44.550767 DQM0 = 57, DQM1 = 46
4318 23:42:44.551192 DQ Delay:
4319 23:42:44.553730 DQ0 =57, DQ1 =57, DQ2 =49, DQ3 =49
4320 23:42:44.556876 DQ4 =65, DQ5 =49, DQ6 =65, DQ7 =65
4321 23:42:44.559830 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4322 23:42:44.563418 DQ12 =57, DQ13 =49, DQ14 =57, DQ15 =49
4323 23:42:44.563602
4324 23:42:44.563748
4325 23:42:44.563883 ==
4326 23:42:44.566933 Dram Type= 6, Freq= 0, CH_0, rank 1
4327 23:42:44.573433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4328 23:42:44.573641 ==
4329 23:42:44.573768
4330 23:42:44.573883
4331 23:42:44.573993 TX Vref Scan disable
4332 23:42:44.577088 == TX Byte 0 ==
4333 23:42:44.580592 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4334 23:42:44.587159 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4335 23:42:44.587396 == TX Byte 1 ==
4336 23:42:44.590374 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4337 23:42:44.597244 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4338 23:42:44.597534 ==
4339 23:42:44.600346 Dram Type= 6, Freq= 0, CH_0, rank 1
4340 23:42:44.603976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 23:42:44.604273 ==
4342 23:42:44.604477
4343 23:42:44.604664
4344 23:42:44.606974 TX Vref Scan disable
4345 23:42:44.607264 == TX Byte 0 ==
4346 23:42:44.613961 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4347 23:42:44.617330 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4348 23:42:44.620896 == TX Byte 1 ==
4349 23:42:44.623989 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4350 23:42:44.627630 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4351 23:42:44.628148
4352 23:42:44.628511 [DATLAT]
4353 23:42:44.630691 Freq=600, CH0 RK1
4354 23:42:44.631112
4355 23:42:44.631443 DATLAT Default: 0x9
4356 23:42:44.634045 0, 0xFFFF, sum = 0
4357 23:42:44.634570 1, 0xFFFF, sum = 0
4358 23:42:44.637416 2, 0xFFFF, sum = 0
4359 23:42:44.640486 3, 0xFFFF, sum = 0
4360 23:42:44.640911 4, 0xFFFF, sum = 0
4361 23:42:44.643686 5, 0xFFFF, sum = 0
4362 23:42:44.644110 6, 0xFFFF, sum = 0
4363 23:42:44.647023 7, 0xFFFF, sum = 0
4364 23:42:44.647450 8, 0x0, sum = 1
4365 23:42:44.647794 9, 0x0, sum = 2
4366 23:42:44.650034 10, 0x0, sum = 3
4367 23:42:44.650466 11, 0x0, sum = 4
4368 23:42:44.653361 best_step = 9
4369 23:42:44.653817
4370 23:42:44.654154 ==
4371 23:42:44.657085 Dram Type= 6, Freq= 0, CH_0, rank 1
4372 23:42:44.660134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 23:42:44.660559 ==
4374 23:42:44.663426 RX Vref Scan: 0
4375 23:42:44.663845
4376 23:42:44.664178 RX Vref 0 -> 0, step: 1
4377 23:42:44.664491
4378 23:42:44.666781 RX Delay -163 -> 252, step: 8
4379 23:42:44.674288 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4380 23:42:44.677744 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4381 23:42:44.680801 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4382 23:42:44.684266 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4383 23:42:44.687889 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4384 23:42:44.694233 iDelay=205, Bit 5, Center 48 (-91 ~ 188) 280
4385 23:42:44.697338 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4386 23:42:44.701045 iDelay=205, Bit 7, Center 64 (-75 ~ 204) 280
4387 23:42:44.703847 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4388 23:42:44.710616 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4389 23:42:44.714289 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4390 23:42:44.717127 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4391 23:42:44.720788 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4392 23:42:44.724169 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4393 23:42:44.730424 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4394 23:42:44.734288 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4395 23:42:44.734807 ==
4396 23:42:44.737111 Dram Type= 6, Freq= 0, CH_0, rank 1
4397 23:42:44.740415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4398 23:42:44.740834 ==
4399 23:42:44.744409 DQS Delay:
4400 23:42:44.744925 DQS0 = 0, DQS1 = 0
4401 23:42:44.745271 DQM Delay:
4402 23:42:44.747263 DQM0 = 55, DQM1 = 46
4403 23:42:44.747681 DQ Delay:
4404 23:42:44.750827 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4405 23:42:44.754051 DQ4 =56, DQ5 =48, DQ6 =60, DQ7 =64
4406 23:42:44.757489 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4407 23:42:44.761017 DQ12 =48, DQ13 =52, DQ14 =56, DQ15 =52
4408 23:42:44.761543
4409 23:42:44.761939
4410 23:42:44.770942 [DQSOSCAuto] RK1, (LSB)MR18= 0x6022, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4411 23:42:44.771480 CH0 RK1: MR19=808, MR18=6022
4412 23:42:44.777845 CH0_RK1: MR19=0x808, MR18=0x6022, DQSOSC=391, MR23=63, INC=171, DEC=114
4413 23:42:44.780902 [RxdqsGatingPostProcess] freq 600
4414 23:42:44.787448 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4415 23:42:44.791411 Pre-setting of DQS Precalculation
4416 23:42:44.794418 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4417 23:42:44.794986 ==
4418 23:42:44.797291 Dram Type= 6, Freq= 0, CH_1, rank 0
4419 23:42:44.803566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4420 23:42:44.804108 ==
4421 23:42:44.806777 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4422 23:42:44.813750 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4423 23:42:44.816873 [CA 0] Center 35 (5~66) winsize 62
4424 23:42:44.820377 [CA 1] Center 36 (5~67) winsize 63
4425 23:42:44.824096 [CA 2] Center 34 (4~65) winsize 62
4426 23:42:44.827595 [CA 3] Center 34 (4~65) winsize 62
4427 23:42:44.830587 [CA 4] Center 34 (4~65) winsize 62
4428 23:42:44.833755 [CA 5] Center 33 (3~64) winsize 62
4429 23:42:44.834171
4430 23:42:44.836908 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4431 23:42:44.837422
4432 23:42:44.840392 [CATrainingPosCal] consider 1 rank data
4433 23:42:44.843635 u2DelayCellTimex100 = 270/100 ps
4434 23:42:44.846815 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4435 23:42:44.850339 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4436 23:42:44.854017 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4437 23:42:44.860333 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4438 23:42:44.863961 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4439 23:42:44.866872 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4440 23:42:44.867333
4441 23:42:44.870213 CA PerBit enable=1, Macro0, CA PI delay=33
4442 23:42:44.870775
4443 23:42:44.874100 [CBTSetCACLKResult] CA Dly = 33
4444 23:42:44.874659 CS Dly: 6 (0~37)
4445 23:42:44.875025 ==
4446 23:42:44.877549 Dram Type= 6, Freq= 0, CH_1, rank 1
4447 23:42:44.883851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 23:42:44.884422 ==
4449 23:42:44.886684 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4450 23:42:44.894278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4451 23:42:44.897269 [CA 0] Center 36 (5~67) winsize 63
4452 23:42:44.900073 [CA 1] Center 36 (5~67) winsize 63
4453 23:42:44.903567 [CA 2] Center 34 (4~65) winsize 62
4454 23:42:44.906547 [CA 3] Center 34 (4~65) winsize 62
4455 23:42:44.909869 [CA 4] Center 34 (4~65) winsize 62
4456 23:42:44.913659 [CA 5] Center 34 (4~64) winsize 61
4457 23:42:44.914231
4458 23:42:44.916982 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4459 23:42:44.917544
4460 23:42:44.919792 [CATrainingPosCal] consider 2 rank data
4461 23:42:44.923478 u2DelayCellTimex100 = 270/100 ps
4462 23:42:44.927264 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4463 23:42:44.932976 CA1 delay=36 (5~67),Diff = 2 PI (19 cell)
4464 23:42:44.936966 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4465 23:42:44.939826 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4466 23:42:44.943088 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4467 23:42:44.946731 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4468 23:42:44.947264
4469 23:42:44.950055 CA PerBit enable=1, Macro0, CA PI delay=34
4470 23:42:44.950498
4471 23:42:44.953240 [CBTSetCACLKResult] CA Dly = 34
4472 23:42:44.953843 CS Dly: 6 (0~38)
4473 23:42:44.954306
4474 23:42:44.956767 ----->DramcWriteLeveling(PI) begin...
4475 23:42:44.959800 ==
4476 23:42:44.963083 Dram Type= 6, Freq= 0, CH_1, rank 0
4477 23:42:44.966526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4478 23:42:44.966979 ==
4479 23:42:44.969467 Write leveling (Byte 0): 29 => 29
4480 23:42:44.973018 Write leveling (Byte 1): 29 => 29
4481 23:42:44.976211 DramcWriteLeveling(PI) end<-----
4482 23:42:44.976654
4483 23:42:44.977097 ==
4484 23:42:44.979964 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 23:42:44.982955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 23:42:44.983382 ==
4487 23:42:44.986696 [Gating] SW mode calibration
4488 23:42:44.993511 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4489 23:42:44.999943 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4490 23:42:45.003240 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4491 23:42:45.006270 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4492 23:42:45.012766 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4493 23:42:45.016279 0 9 12 | B1->B0 | 3131 2e2e | 1 0 | (1 0) (0 1)
4494 23:42:45.019805 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 23:42:45.026337 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4496 23:42:45.029757 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4497 23:42:45.032887 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4498 23:42:45.036566 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4499 23:42:45.042703 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4500 23:42:45.046199 0 10 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
4501 23:42:45.049314 0 10 12 | B1->B0 | 3434 3e3e | 1 0 | (0 0) (0 0)
4502 23:42:45.055887 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 23:42:45.058956 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 23:42:45.062326 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4505 23:42:45.069300 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4506 23:42:45.072731 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4507 23:42:45.076050 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4508 23:42:45.082702 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4509 23:42:45.085528 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 23:42:45.089045 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 23:42:45.095897 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 23:42:45.099089 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 23:42:45.102136 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 23:42:45.108895 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 23:42:45.112088 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 23:42:45.115916 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 23:42:45.122122 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 23:42:45.125418 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 23:42:45.128927 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 23:42:45.135958 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4521 23:42:45.139385 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 23:42:45.142198 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 23:42:45.148929 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 23:42:45.152487 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 23:42:45.155655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4526 23:42:45.162347 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4527 23:42:45.162910 Total UI for P1: 0, mck2ui 16
4528 23:42:45.168733 best dqsien dly found for B0: ( 0, 13, 12)
4529 23:42:45.169299 Total UI for P1: 0, mck2ui 16
4530 23:42:45.172184 best dqsien dly found for B1: ( 0, 13, 12)
4531 23:42:45.178594 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4532 23:42:45.181829 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4533 23:42:45.182388
4534 23:42:45.185426 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4535 23:42:45.189131 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4536 23:42:45.192042 [Gating] SW calibration Done
4537 23:42:45.192613 ==
4538 23:42:45.195467 Dram Type= 6, Freq= 0, CH_1, rank 0
4539 23:42:45.198628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4540 23:42:45.199206 ==
4541 23:42:45.201701 RX Vref Scan: 0
4542 23:42:45.202166
4543 23:42:45.202535 RX Vref 0 -> 0, step: 1
4544 23:42:45.202882
4545 23:42:45.205696 RX Delay -230 -> 252, step: 16
4546 23:42:45.208918 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4547 23:42:45.215284 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4548 23:42:45.218348 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4549 23:42:45.221819 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4550 23:42:45.225136 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4551 23:42:45.231546 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4552 23:42:45.234856 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4553 23:42:45.238018 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4554 23:42:45.241656 iDelay=218, Bit 8, Center 41 (-102 ~ 185) 288
4555 23:42:45.244830 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4556 23:42:45.251841 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4557 23:42:45.254685 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4558 23:42:45.257889 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4559 23:42:45.261533 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4560 23:42:45.268088 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4561 23:42:45.271871 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4562 23:42:45.272290 ==
4563 23:42:45.275181 Dram Type= 6, Freq= 0, CH_1, rank 0
4564 23:42:45.277985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4565 23:42:45.278409 ==
4566 23:42:45.281667 DQS Delay:
4567 23:42:45.282092 DQS0 = 0, DQS1 = 0
4568 23:42:45.282443 DQM Delay:
4569 23:42:45.284879 DQM0 = 52, DQM1 = 49
4570 23:42:45.285301 DQ Delay:
4571 23:42:45.288348 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4572 23:42:45.291664 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4573 23:42:45.295903 DQ8 =41, DQ9 =41, DQ10 =49, DQ11 =49
4574 23:42:45.298451 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4575 23:42:45.298876
4576 23:42:45.299253
4577 23:42:45.299578 ==
4578 23:42:45.301483 Dram Type= 6, Freq= 0, CH_1, rank 0
4579 23:42:45.308321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 23:42:45.308860 ==
4581 23:42:45.309313
4582 23:42:45.309812
4583 23:42:45.310234 TX Vref Scan disable
4584 23:42:45.312246 == TX Byte 0 ==
4585 23:42:45.315468 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4586 23:42:45.318876 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4587 23:42:45.322113 == TX Byte 1 ==
4588 23:42:45.325108 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4589 23:42:45.332245 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4590 23:42:45.332783 ==
4591 23:42:45.335298 Dram Type= 6, Freq= 0, CH_1, rank 0
4592 23:42:45.338853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4593 23:42:45.339392 ==
4594 23:42:45.339842
4595 23:42:45.340259
4596 23:42:45.341690 TX Vref Scan disable
4597 23:42:45.345261 == TX Byte 0 ==
4598 23:42:45.348575 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4599 23:42:45.352033 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4600 23:42:45.355077 == TX Byte 1 ==
4601 23:42:45.358420 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4602 23:42:45.361831 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4603 23:42:45.362368
4604 23:42:45.362819 [DATLAT]
4605 23:42:45.365111 Freq=600, CH1 RK0
4606 23:42:45.365682
4607 23:42:45.366209 DATLAT Default: 0x9
4608 23:42:45.368810 0, 0xFFFF, sum = 0
4609 23:42:45.369350 1, 0xFFFF, sum = 0
4610 23:42:45.371867 2, 0xFFFF, sum = 0
4611 23:42:45.375127 3, 0xFFFF, sum = 0
4612 23:42:45.375673 4, 0xFFFF, sum = 0
4613 23:42:45.378435 5, 0xFFFF, sum = 0
4614 23:42:45.378971 6, 0xFFFF, sum = 0
4615 23:42:45.381767 7, 0xFFFF, sum = 0
4616 23:42:45.382305 8, 0x0, sum = 1
4617 23:42:45.382763 9, 0x0, sum = 2
4618 23:42:45.385249 10, 0x0, sum = 3
4619 23:42:45.385845 11, 0x0, sum = 4
4620 23:42:45.388389 best_step = 9
4621 23:42:45.388917
4622 23:42:45.389362 ==
4623 23:42:45.391795 Dram Type= 6, Freq= 0, CH_1, rank 0
4624 23:42:45.395574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4625 23:42:45.396126 ==
4626 23:42:45.398425 RX Vref Scan: 1
4627 23:42:45.398856
4628 23:42:45.399298 RX Vref 0 -> 0, step: 1
4629 23:42:45.399715
4630 23:42:45.401368 RX Delay -147 -> 252, step: 8
4631 23:42:45.401850
4632 23:42:45.404702 Set Vref, RX VrefLevel [Byte0]: 54
4633 23:42:45.408012 [Byte1]: 48
4634 23:42:45.412063
4635 23:42:45.412493 Final RX Vref Byte 0 = 54 to rank0
4636 23:42:45.415540 Final RX Vref Byte 1 = 48 to rank0
4637 23:42:45.418591 Final RX Vref Byte 0 = 54 to rank1
4638 23:42:45.421916 Final RX Vref Byte 1 = 48 to rank1==
4639 23:42:45.425978 Dram Type= 6, Freq= 0, CH_1, rank 0
4640 23:42:45.431935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4641 23:42:45.432452 ==
4642 23:42:45.432902 DQS Delay:
4643 23:42:45.433322 DQS0 = 0, DQS1 = 0
4644 23:42:45.435272 DQM Delay:
4645 23:42:45.435814 DQM0 = 48, DQM1 = 45
4646 23:42:45.439051 DQ Delay:
4647 23:42:45.442359 DQ0 =52, DQ1 =40, DQ2 =40, DQ3 =48
4648 23:42:45.445519 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4649 23:42:45.446095 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4650 23:42:45.452343 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =60
4651 23:42:45.452865
4652 23:42:45.453202
4653 23:42:45.459135 [DQSOSCAuto] RK0, (LSB)MR18= 0x4469, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 396 ps
4654 23:42:45.462397 CH1 RK0: MR19=808, MR18=4469
4655 23:42:45.468905 CH1_RK0: MR19=0x808, MR18=0x4469, DQSOSC=390, MR23=63, INC=172, DEC=114
4656 23:42:45.469470
4657 23:42:45.472408 ----->DramcWriteLeveling(PI) begin...
4658 23:42:45.472981 ==
4659 23:42:45.475265 Dram Type= 6, Freq= 0, CH_1, rank 1
4660 23:42:45.478750 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4661 23:42:45.479315 ==
4662 23:42:45.482280 Write leveling (Byte 0): 31 => 31
4663 23:42:45.485458 Write leveling (Byte 1): 30 => 30
4664 23:42:45.488874 DramcWriteLeveling(PI) end<-----
4665 23:42:45.489435
4666 23:42:45.489875 ==
4667 23:42:45.491952 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 23:42:45.495348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 23:42:45.495776 ==
4670 23:42:45.498472 [Gating] SW mode calibration
4671 23:42:45.505091 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4672 23:42:45.511747 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4673 23:42:45.515563 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4674 23:42:45.521740 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4675 23:42:45.525206 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4676 23:42:45.529014 0 9 12 | B1->B0 | 2a2a 2f2f | 1 0 | (1 0) (0 1)
4677 23:42:45.531945 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 23:42:45.538285 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 23:42:45.541663 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 23:42:45.544962 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 23:42:45.551944 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4682 23:42:45.555010 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4683 23:42:45.558219 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4684 23:42:45.564695 0 10 12 | B1->B0 | 3636 3232 | 0 0 | (0 0) (0 0)
4685 23:42:45.568598 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 23:42:45.571245 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 23:42:45.578063 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 23:42:45.581730 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 23:42:45.584569 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 23:42:45.592013 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4691 23:42:45.594451 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4692 23:42:45.597661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4693 23:42:45.604292 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 23:42:45.607829 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 23:42:45.611085 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 23:42:45.617572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 23:42:45.620881 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 23:42:45.624456 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 23:42:45.631388 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 23:42:45.634191 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 23:42:45.637909 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 23:42:45.644652 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 23:42:45.647565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 23:42:45.651470 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 23:42:45.657862 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 23:42:45.661204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 23:42:45.664688 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4708 23:42:45.670992 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4709 23:42:45.674754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 23:42:45.677756 Total UI for P1: 0, mck2ui 16
4711 23:42:45.681145 best dqsien dly found for B0: ( 0, 13, 14)
4712 23:42:45.684858 Total UI for P1: 0, mck2ui 16
4713 23:42:45.687319 best dqsien dly found for B1: ( 0, 13, 10)
4714 23:42:45.690522 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4715 23:42:45.694356 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4716 23:42:45.694916
4717 23:42:45.697494 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4718 23:42:45.700784 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4719 23:42:45.703986 [Gating] SW calibration Done
4720 23:42:45.704455 ==
4721 23:42:45.707385 Dram Type= 6, Freq= 0, CH_1, rank 1
4722 23:42:45.710972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4723 23:42:45.714064 ==
4724 23:42:45.714499 RX Vref Scan: 0
4725 23:42:45.714942
4726 23:42:45.717765 RX Vref 0 -> 0, step: 1
4727 23:42:45.718292
4728 23:42:45.720633 RX Delay -230 -> 252, step: 16
4729 23:42:45.723766 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4730 23:42:45.727229 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4731 23:42:45.730287 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4732 23:42:45.737677 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4733 23:42:45.740388 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4734 23:42:45.744215 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4735 23:42:45.747271 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4736 23:42:45.750188 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4737 23:42:45.757048 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4738 23:42:45.760497 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4739 23:42:45.763887 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4740 23:42:45.766607 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4741 23:42:45.773677 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4742 23:42:45.777081 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4743 23:42:45.780435 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4744 23:42:45.783312 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4745 23:42:45.783779 ==
4746 23:42:45.786930 Dram Type= 6, Freq= 0, CH_1, rank 1
4747 23:42:45.793657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4748 23:42:45.794192 ==
4749 23:42:45.794636 DQS Delay:
4750 23:42:45.796670 DQS0 = 0, DQS1 = 0
4751 23:42:45.797098 DQM Delay:
4752 23:42:45.797532 DQM0 = 49, DQM1 = 47
4753 23:42:45.800425 DQ Delay:
4754 23:42:45.803365 DQ0 =49, DQ1 =49, DQ2 =33, DQ3 =49
4755 23:42:45.806847 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4756 23:42:45.809983 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4757 23:42:45.813349 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4758 23:42:45.813814
4759 23:42:45.814150
4760 23:42:45.814460 ==
4761 23:42:45.816643 Dram Type= 6, Freq= 0, CH_1, rank 1
4762 23:42:45.820120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4763 23:42:45.820645 ==
4764 23:42:45.821072
4765 23:42:45.821396
4766 23:42:45.823065 TX Vref Scan disable
4767 23:42:45.826917 == TX Byte 0 ==
4768 23:42:45.830200 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4769 23:42:45.833175 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4770 23:42:45.836987 == TX Byte 1 ==
4771 23:42:45.840331 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4772 23:42:45.843177 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4773 23:42:45.843642 ==
4774 23:42:45.846842 Dram Type= 6, Freq= 0, CH_1, rank 1
4775 23:42:45.850443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4776 23:42:45.850911 ==
4777 23:42:45.853235
4778 23:42:45.853824
4779 23:42:45.854195 TX Vref Scan disable
4780 23:42:45.857186 == TX Byte 0 ==
4781 23:42:45.860455 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4782 23:42:45.867241 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4783 23:42:45.867806 == TX Byte 1 ==
4784 23:42:45.869901 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4785 23:42:45.876994 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4786 23:42:45.877558
4787 23:42:45.877974 [DATLAT]
4788 23:42:45.878319 Freq=600, CH1 RK1
4789 23:42:45.878649
4790 23:42:45.880427 DATLAT Default: 0x9
4791 23:42:45.881007 0, 0xFFFF, sum = 0
4792 23:42:45.883505 1, 0xFFFF, sum = 0
4793 23:42:45.883978 2, 0xFFFF, sum = 0
4794 23:42:45.887015 3, 0xFFFF, sum = 0
4795 23:42:45.890073 4, 0xFFFF, sum = 0
4796 23:42:45.890616 5, 0xFFFF, sum = 0
4797 23:42:45.893241 6, 0xFFFF, sum = 0
4798 23:42:45.893721 7, 0xFFFF, sum = 0
4799 23:42:45.896440 8, 0x0, sum = 1
4800 23:42:45.896877 9, 0x0, sum = 2
4801 23:42:45.897322 10, 0x0, sum = 3
4802 23:42:45.900048 11, 0x0, sum = 4
4803 23:42:45.900583 best_step = 9
4804 23:42:45.901025
4805 23:42:45.901432 ==
4806 23:42:45.903172 Dram Type= 6, Freq= 0, CH_1, rank 1
4807 23:42:45.909680 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4808 23:42:45.910109 ==
4809 23:42:45.910446 RX Vref Scan: 0
4810 23:42:45.910757
4811 23:42:45.913045 RX Vref 0 -> 0, step: 1
4812 23:42:45.913678
4813 23:42:45.916913 RX Delay -163 -> 252, step: 8
4814 23:42:45.919621 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4815 23:42:45.926249 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4816 23:42:45.930287 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4817 23:42:45.933145 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4818 23:42:45.936494 iDelay=205, Bit 4, Center 48 (-91 ~ 188) 280
4819 23:42:45.940067 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4820 23:42:45.946884 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4821 23:42:45.950028 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4822 23:42:45.952909 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4823 23:42:45.956564 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4824 23:42:45.960016 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4825 23:42:45.966485 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4826 23:42:45.970326 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4827 23:42:45.973273 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4828 23:42:45.975853 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4829 23:42:45.982928 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4830 23:42:45.983515 ==
4831 23:42:45.986106 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 23:42:45.989748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 23:42:45.990322 ==
4834 23:42:45.990693 DQS Delay:
4835 23:42:45.993197 DQS0 = 0, DQS1 = 0
4836 23:42:45.993807 DQM Delay:
4837 23:42:45.996089 DQM0 = 49, DQM1 = 45
4838 23:42:45.996653 DQ Delay:
4839 23:42:45.999548 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4840 23:42:46.002796 DQ4 =48, DQ5 =60, DQ6 =60, DQ7 =48
4841 23:42:46.005837 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4842 23:42:46.009365 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =52
4843 23:42:46.009837
4844 23:42:46.010176
4845 23:42:46.016027 [DQSOSCAuto] RK1, (LSB)MR18= 0x6921, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 390 ps
4846 23:42:46.019300 CH1 RK1: MR19=808, MR18=6921
4847 23:42:46.025616 CH1_RK1: MR19=0x808, MR18=0x6921, DQSOSC=390, MR23=63, INC=172, DEC=114
4848 23:42:46.029283 [RxdqsGatingPostProcess] freq 600
4849 23:42:46.035936 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4850 23:42:46.039298 Pre-setting of DQS Precalculation
4851 23:42:46.042716 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4852 23:42:46.050004 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4853 23:42:46.056039 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4854 23:42:46.056769
4855 23:42:46.057122
4856 23:42:46.059200 [Calibration Summary] 1200 Mbps
4857 23:42:46.062342 CH 0, Rank 0
4858 23:42:46.062754 SW Impedance : PASS
4859 23:42:46.066469 DUTY Scan : NO K
4860 23:42:46.069356 ZQ Calibration : PASS
4861 23:42:46.069942 Jitter Meter : NO K
4862 23:42:46.072951 CBT Training : PASS
4863 23:42:46.076014 Write leveling : PASS
4864 23:42:46.076531 RX DQS gating : PASS
4865 23:42:46.079102 RX DQ/DQS(RDDQC) : PASS
4866 23:42:46.079619 TX DQ/DQS : PASS
4867 23:42:46.082500 RX DATLAT : PASS
4868 23:42:46.085869 RX DQ/DQS(Engine): PASS
4869 23:42:46.086379 TX OE : NO K
4870 23:42:46.089335 All Pass.
4871 23:42:46.089815
4872 23:42:46.090154 CH 0, Rank 1
4873 23:42:46.092886 SW Impedance : PASS
4874 23:42:46.093407 DUTY Scan : NO K
4875 23:42:46.095951 ZQ Calibration : PASS
4876 23:42:46.099283 Jitter Meter : NO K
4877 23:42:46.099804 CBT Training : PASS
4878 23:42:46.102328 Write leveling : PASS
4879 23:42:46.105721 RX DQS gating : PASS
4880 23:42:46.106261 RX DQ/DQS(RDDQC) : PASS
4881 23:42:46.109180 TX DQ/DQS : PASS
4882 23:42:46.112122 RX DATLAT : PASS
4883 23:42:46.112536 RX DQ/DQS(Engine): PASS
4884 23:42:46.116125 TX OE : NO K
4885 23:42:46.116644 All Pass.
4886 23:42:46.116975
4887 23:42:46.119403 CH 1, Rank 0
4888 23:42:46.119920 SW Impedance : PASS
4889 23:42:46.122557 DUTY Scan : NO K
4890 23:42:46.122972 ZQ Calibration : PASS
4891 23:42:46.126216 Jitter Meter : NO K
4892 23:42:46.129392 CBT Training : PASS
4893 23:42:46.129985 Write leveling : PASS
4894 23:42:46.132499 RX DQS gating : PASS
4895 23:42:46.135652 RX DQ/DQS(RDDQC) : PASS
4896 23:42:46.136067 TX DQ/DQS : PASS
4897 23:42:46.139205 RX DATLAT : PASS
4898 23:42:46.142175 RX DQ/DQS(Engine): PASS
4899 23:42:46.142592 TX OE : NO K
4900 23:42:46.145847 All Pass.
4901 23:42:46.146362
4902 23:42:46.146694 CH 1, Rank 1
4903 23:42:46.149093 SW Impedance : PASS
4904 23:42:46.149553 DUTY Scan : NO K
4905 23:42:46.152904 ZQ Calibration : PASS
4906 23:42:46.155766 Jitter Meter : NO K
4907 23:42:46.156282 CBT Training : PASS
4908 23:42:46.159095 Write leveling : PASS
4909 23:42:46.162735 RX DQS gating : PASS
4910 23:42:46.163258 RX DQ/DQS(RDDQC) : PASS
4911 23:42:46.165760 TX DQ/DQS : PASS
4912 23:42:46.166275 RX DATLAT : PASS
4913 23:42:46.169083 RX DQ/DQS(Engine): PASS
4914 23:42:46.172617 TX OE : NO K
4915 23:42:46.173163 All Pass.
4916 23:42:46.173500
4917 23:42:46.176034 DramC Write-DBI off
4918 23:42:46.176554 PER_BANK_REFRESH: Hybrid Mode
4919 23:42:46.179157 TX_TRACKING: ON
4920 23:42:46.189784 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4921 23:42:46.192411 [FAST_K] Save calibration result to emmc
4922 23:42:46.195980 dramc_set_vcore_voltage set vcore to 662500
4923 23:42:46.196497 Read voltage for 933, 3
4924 23:42:46.199510 Vio18 = 0
4925 23:42:46.200024 Vcore = 662500
4926 23:42:46.200354 Vdram = 0
4927 23:42:46.202819 Vddq = 0
4928 23:42:46.203233 Vmddr = 0
4929 23:42:46.205929 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4930 23:42:46.212578 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4931 23:42:46.215543 MEM_TYPE=3, freq_sel=17
4932 23:42:46.219662 sv_algorithm_assistance_LP4_1600
4933 23:42:46.222820 ============ PULL DRAM RESETB DOWN ============
4934 23:42:46.225639 ========== PULL DRAM RESETB DOWN end =========
4935 23:42:46.232797 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4936 23:42:46.235356 ===================================
4937 23:42:46.235777 LPDDR4 DRAM CONFIGURATION
4938 23:42:46.239038 ===================================
4939 23:42:46.242448 EX_ROW_EN[0] = 0x0
4940 23:42:46.243040 EX_ROW_EN[1] = 0x0
4941 23:42:46.246023 LP4Y_EN = 0x0
4942 23:42:46.246547 WORK_FSP = 0x0
4943 23:42:46.248729 WL = 0x3
4944 23:42:46.252236 RL = 0x3
4945 23:42:46.252650 BL = 0x2
4946 23:42:46.255787 RPST = 0x0
4947 23:42:46.256307 RD_PRE = 0x0
4948 23:42:46.258617 WR_PRE = 0x1
4949 23:42:46.259033 WR_PST = 0x0
4950 23:42:46.262253 DBI_WR = 0x0
4951 23:42:46.262668 DBI_RD = 0x0
4952 23:42:46.265486 OTF = 0x1
4953 23:42:46.268941 ===================================
4954 23:42:46.272376 ===================================
4955 23:42:46.272911 ANA top config
4956 23:42:46.275294 ===================================
4957 23:42:46.278594 DLL_ASYNC_EN = 0
4958 23:42:46.282037 ALL_SLAVE_EN = 1
4959 23:42:46.282561 NEW_RANK_MODE = 1
4960 23:42:46.285387 DLL_IDLE_MODE = 1
4961 23:42:46.288769 LP45_APHY_COMB_EN = 1
4962 23:42:46.292754 TX_ODT_DIS = 1
4963 23:42:46.293295 NEW_8X_MODE = 1
4964 23:42:46.295588 ===================================
4965 23:42:46.298705 ===================================
4966 23:42:46.302145 data_rate = 1866
4967 23:42:46.305038 CKR = 1
4968 23:42:46.308521 DQ_P2S_RATIO = 8
4969 23:42:46.312268 ===================================
4970 23:42:46.315320 CA_P2S_RATIO = 8
4971 23:42:46.318437 DQ_CA_OPEN = 0
4972 23:42:46.322015 DQ_SEMI_OPEN = 0
4973 23:42:46.322415 CA_SEMI_OPEN = 0
4974 23:42:46.325143 CA_FULL_RATE = 0
4975 23:42:46.328705 DQ_CKDIV4_EN = 1
4976 23:42:46.332593 CA_CKDIV4_EN = 1
4977 23:42:46.335071 CA_PREDIV_EN = 0
4978 23:42:46.335490 PH8_DLY = 0
4979 23:42:46.338344 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4980 23:42:46.341646 DQ_AAMCK_DIV = 4
4981 23:42:46.345306 CA_AAMCK_DIV = 4
4982 23:42:46.348267 CA_ADMCK_DIV = 4
4983 23:42:46.351735 DQ_TRACK_CA_EN = 0
4984 23:42:46.354767 CA_PICK = 933
4985 23:42:46.355183 CA_MCKIO = 933
4986 23:42:46.358351 MCKIO_SEMI = 0
4987 23:42:46.361883 PLL_FREQ = 3732
4988 23:42:46.365193 DQ_UI_PI_RATIO = 32
4989 23:42:46.368307 CA_UI_PI_RATIO = 0
4990 23:42:46.371872 ===================================
4991 23:42:46.374991 ===================================
4992 23:42:46.378366 memory_type:LPDDR4
4993 23:42:46.378785 GP_NUM : 10
4994 23:42:46.381746 SRAM_EN : 1
4995 23:42:46.382159 MD32_EN : 0
4996 23:42:46.384619 ===================================
4997 23:42:46.387986 [ANA_INIT] >>>>>>>>>>>>>>
4998 23:42:46.391347 <<<<<< [CONFIGURE PHASE]: ANA_TX
4999 23:42:46.395208 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5000 23:42:46.398013 ===================================
5001 23:42:46.401329 data_rate = 1866,PCW = 0X8f00
5002 23:42:46.404619 ===================================
5003 23:42:46.407848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5004 23:42:46.411849 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5005 23:42:46.418226 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5006 23:42:46.421698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5007 23:42:46.428170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5008 23:42:46.432415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5009 23:42:46.432941 [ANA_INIT] flow start
5010 23:42:46.434931 [ANA_INIT] PLL >>>>>>>>
5011 23:42:46.438120 [ANA_INIT] PLL <<<<<<<<
5012 23:42:46.438538 [ANA_INIT] MIDPI >>>>>>>>
5013 23:42:46.441674 [ANA_INIT] MIDPI <<<<<<<<
5014 23:42:46.445528 [ANA_INIT] DLL >>>>>>>>
5015 23:42:46.446099 [ANA_INIT] flow end
5016 23:42:46.451558 ============ LP4 DIFF to SE enter ============
5017 23:42:46.454756 ============ LP4 DIFF to SE exit ============
5018 23:42:46.455174 [ANA_INIT] <<<<<<<<<<<<<
5019 23:42:46.457993 [Flow] Enable top DCM control >>>>>
5020 23:42:46.461898 [Flow] Enable top DCM control <<<<<
5021 23:42:46.464890 Enable DLL master slave shuffle
5022 23:42:46.471351 ==============================================================
5023 23:42:46.474484 Gating Mode config
5024 23:42:46.478270 ==============================================================
5025 23:42:46.481549 Config description:
5026 23:42:46.491457 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5027 23:42:46.497760 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5028 23:42:46.501440 SELPH_MODE 0: By rank 1: By Phase
5029 23:42:46.507897 ==============================================================
5030 23:42:46.511782 GAT_TRACK_EN = 1
5031 23:42:46.514305 RX_GATING_MODE = 2
5032 23:42:46.517720 RX_GATING_TRACK_MODE = 2
5033 23:42:46.518141 SELPH_MODE = 1
5034 23:42:46.521127 PICG_EARLY_EN = 1
5035 23:42:46.524731 VALID_LAT_VALUE = 1
5036 23:42:46.531086 ==============================================================
5037 23:42:46.534255 Enter into Gating configuration >>>>
5038 23:42:46.537563 Exit from Gating configuration <<<<
5039 23:42:46.541247 Enter into DVFS_PRE_config >>>>>
5040 23:42:46.550383 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5041 23:42:46.554529 Exit from DVFS_PRE_config <<<<<
5042 23:42:46.557597 Enter into PICG configuration >>>>
5043 23:42:46.560671 Exit from PICG configuration <<<<
5044 23:42:46.564376 [RX_INPUT] configuration >>>>>
5045 23:42:46.567537 [RX_INPUT] configuration <<<<<
5046 23:42:46.570777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5047 23:42:46.577656 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5048 23:42:46.583923 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5049 23:42:46.591373 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5050 23:42:46.597392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5051 23:42:46.600981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5052 23:42:46.607218 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5053 23:42:46.610417 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5054 23:42:46.613513 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5055 23:42:46.616872 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5056 23:42:46.620724 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5057 23:42:46.627112 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5058 23:42:46.631342 ===================================
5059 23:42:46.634023 LPDDR4 DRAM CONFIGURATION
5060 23:42:46.637265 ===================================
5061 23:42:46.637735 EX_ROW_EN[0] = 0x0
5062 23:42:46.640876 EX_ROW_EN[1] = 0x0
5063 23:42:46.641431 LP4Y_EN = 0x0
5064 23:42:46.643907 WORK_FSP = 0x0
5065 23:42:46.644492 WL = 0x3
5066 23:42:46.647407 RL = 0x3
5067 23:42:46.647970 BL = 0x2
5068 23:42:46.650266 RPST = 0x0
5069 23:42:46.650724 RD_PRE = 0x0
5070 23:42:46.654721 WR_PRE = 0x1
5071 23:42:46.655282 WR_PST = 0x0
5072 23:42:46.657049 DBI_WR = 0x0
5073 23:42:46.657507 DBI_RD = 0x0
5074 23:42:46.661058 OTF = 0x1
5075 23:42:46.663911 ===================================
5076 23:42:46.667468 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5077 23:42:46.670278 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5078 23:42:46.677716 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5079 23:42:46.680622 ===================================
5080 23:42:46.681182 LPDDR4 DRAM CONFIGURATION
5081 23:42:46.684053 ===================================
5082 23:42:46.686860 EX_ROW_EN[0] = 0x10
5083 23:42:46.690099 EX_ROW_EN[1] = 0x0
5084 23:42:46.690559 LP4Y_EN = 0x0
5085 23:42:46.693752 WORK_FSP = 0x0
5086 23:42:46.694212 WL = 0x3
5087 23:42:46.697139 RL = 0x3
5088 23:42:46.697626 BL = 0x2
5089 23:42:46.700399 RPST = 0x0
5090 23:42:46.700921 RD_PRE = 0x0
5091 23:42:46.703403 WR_PRE = 0x1
5092 23:42:46.703821 WR_PST = 0x0
5093 23:42:46.706854 DBI_WR = 0x0
5094 23:42:46.707271 DBI_RD = 0x0
5095 23:42:46.710120 OTF = 0x1
5096 23:42:46.713478 ===================================
5097 23:42:46.720309 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5098 23:42:46.723390 nWR fixed to 30
5099 23:42:46.726874 [ModeRegInit_LP4] CH0 RK0
5100 23:42:46.727286 [ModeRegInit_LP4] CH0 RK1
5101 23:42:46.730179 [ModeRegInit_LP4] CH1 RK0
5102 23:42:46.733661 [ModeRegInit_LP4] CH1 RK1
5103 23:42:46.734183 match AC timing 9
5104 23:42:46.740539 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5105 23:42:46.743576 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5106 23:42:46.746964 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5107 23:42:46.753523 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5108 23:42:46.756835 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5109 23:42:46.757397 ==
5110 23:42:46.760318 Dram Type= 6, Freq= 0, CH_0, rank 0
5111 23:42:46.763345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5112 23:42:46.763911 ==
5113 23:42:46.770095 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5114 23:42:46.776739 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5115 23:42:46.779967 [CA 0] Center 37 (6~68) winsize 63
5116 23:42:46.783163 [CA 1] Center 37 (7~68) winsize 62
5117 23:42:46.786545 [CA 2] Center 34 (4~65) winsize 62
5118 23:42:46.790134 [CA 3] Center 34 (3~65) winsize 63
5119 23:42:46.793458 [CA 4] Center 33 (3~64) winsize 62
5120 23:42:46.796866 [CA 5] Center 32 (2~62) winsize 61
5121 23:42:46.797429
5122 23:42:46.800028 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5123 23:42:46.800602
5124 23:42:46.803247 [CATrainingPosCal] consider 1 rank data
5125 23:42:46.806368 u2DelayCellTimex100 = 270/100 ps
5126 23:42:46.809385 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5127 23:42:46.813179 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5128 23:42:46.816597 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5129 23:42:46.819550 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5130 23:42:46.822572 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5131 23:42:46.826468 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5132 23:42:46.827002
5133 23:42:46.833174 CA PerBit enable=1, Macro0, CA PI delay=32
5134 23:42:46.833792
5135 23:42:46.836401 [CBTSetCACLKResult] CA Dly = 32
5136 23:42:46.836857 CS Dly: 5 (0~36)
5137 23:42:46.837218 ==
5138 23:42:46.840097 Dram Type= 6, Freq= 0, CH_0, rank 1
5139 23:42:46.842880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5140 23:42:46.843346 ==
5141 23:42:46.849459 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5142 23:42:46.856279 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5143 23:42:46.859654 [CA 0] Center 37 (6~68) winsize 63
5144 23:42:46.863181 [CA 1] Center 37 (6~68) winsize 63
5145 23:42:46.866612 [CA 2] Center 34 (4~65) winsize 62
5146 23:42:46.869538 [CA 3] Center 34 (3~65) winsize 63
5147 23:42:46.873202 [CA 4] Center 32 (2~63) winsize 62
5148 23:42:46.876177 [CA 5] Center 32 (2~62) winsize 61
5149 23:42:46.876731
5150 23:42:46.879696 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5151 23:42:46.880260
5152 23:42:46.883082 [CATrainingPosCal] consider 2 rank data
5153 23:42:46.885836 u2DelayCellTimex100 = 270/100 ps
5154 23:42:46.888927 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5155 23:42:46.892486 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5156 23:42:46.896585 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5157 23:42:46.898999 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5158 23:42:46.906346 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5159 23:42:46.908991 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5160 23:42:46.909498
5161 23:42:46.912300 CA PerBit enable=1, Macro0, CA PI delay=32
5162 23:42:46.912862
5163 23:42:46.915462 [CBTSetCACLKResult] CA Dly = 32
5164 23:42:46.915920 CS Dly: 5 (0~37)
5165 23:42:46.916283
5166 23:42:46.919116 ----->DramcWriteLeveling(PI) begin...
5167 23:42:46.919538 ==
5168 23:42:46.922250 Dram Type= 6, Freq= 0, CH_0, rank 0
5169 23:42:46.928831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5170 23:42:46.929337 ==
5171 23:42:46.932326 Write leveling (Byte 0): 31 => 31
5172 23:42:46.935718 Write leveling (Byte 1): 30 => 30
5173 23:42:46.936171 DramcWriteLeveling(PI) end<-----
5174 23:42:46.936504
5175 23:42:46.938675 ==
5176 23:42:46.942077 Dram Type= 6, Freq= 0, CH_0, rank 0
5177 23:42:46.946037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5178 23:42:46.946458 ==
5179 23:42:46.948756 [Gating] SW mode calibration
5180 23:42:46.955732 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5181 23:42:46.958889 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5182 23:42:46.965820 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
5183 23:42:46.968509 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5184 23:42:46.972387 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5185 23:42:46.978735 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5186 23:42:46.982636 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5187 23:42:46.985238 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5188 23:42:46.992030 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5189 23:42:46.995182 0 14 28 | B1->B0 | 3434 2424 | 0 0 | (0 1) (1 1)
5190 23:42:46.998386 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5191 23:42:47.005046 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5192 23:42:47.008210 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5193 23:42:47.011740 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5194 23:42:47.018166 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5195 23:42:47.021483 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5196 23:42:47.025521 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5197 23:42:47.031850 0 15 28 | B1->B0 | 2424 4040 | 0 0 | (0 0) (0 0)
5198 23:42:47.034769 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
5199 23:42:47.038261 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5200 23:42:47.044503 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5201 23:42:47.048269 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 23:42:47.051658 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5203 23:42:47.058124 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5204 23:42:47.061255 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5205 23:42:47.065176 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5206 23:42:47.071520 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5207 23:42:47.074944 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 23:42:47.078493 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 23:42:47.081524 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 23:42:47.088479 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 23:42:47.091867 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5212 23:42:47.095101 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5213 23:42:47.101391 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5214 23:42:47.104455 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5215 23:42:47.108211 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 23:42:47.114729 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 23:42:47.118149 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 23:42:47.121078 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 23:42:47.128388 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 23:42:47.131267 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5221 23:42:47.134585 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5222 23:42:47.141360 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5223 23:42:47.141968 Total UI for P1: 0, mck2ui 16
5224 23:42:47.148071 best dqsien dly found for B0: ( 1, 2, 26)
5225 23:42:47.151253 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5226 23:42:47.154311 Total UI for P1: 0, mck2ui 16
5227 23:42:47.158021 best dqsien dly found for B1: ( 1, 2, 30)
5228 23:42:47.160916 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5229 23:42:47.164274 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5230 23:42:47.164834
5231 23:42:47.167750 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5232 23:42:47.170717 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5233 23:42:47.174540 [Gating] SW calibration Done
5234 23:42:47.175109 ==
5235 23:42:47.177560 Dram Type= 6, Freq= 0, CH_0, rank 0
5236 23:42:47.184424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5237 23:42:47.184986 ==
5238 23:42:47.185355 RX Vref Scan: 0
5239 23:42:47.185734
5240 23:42:47.187445 RX Vref 0 -> 0, step: 1
5241 23:42:47.187904
5242 23:42:47.190756 RX Delay -80 -> 252, step: 8
5243 23:42:47.194106 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5244 23:42:47.197957 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5245 23:42:47.201007 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5246 23:42:47.204291 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5247 23:42:47.210691 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5248 23:42:47.213719 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5249 23:42:47.218043 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5250 23:42:47.220402 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5251 23:42:47.224054 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5252 23:42:47.227377 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5253 23:42:47.234360 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5254 23:42:47.237246 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5255 23:42:47.240963 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5256 23:42:47.244368 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5257 23:42:47.247627 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5258 23:42:47.254036 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5259 23:42:47.254609 ==
5260 23:42:47.257622 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 23:42:47.260810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 23:42:47.261274 ==
5263 23:42:47.261677 DQS Delay:
5264 23:42:47.264080 DQS0 = 0, DQS1 = 0
5265 23:42:47.264656 DQM Delay:
5266 23:42:47.267097 DQM0 = 105, DQM1 = 95
5267 23:42:47.267660 DQ Delay:
5268 23:42:47.270217 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5269 23:42:47.274032 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5270 23:42:47.276744 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5271 23:42:47.280713 DQ12 =103, DQ13 =103, DQ14 =107, DQ15 =103
5272 23:42:47.281274
5273 23:42:47.281683
5274 23:42:47.282024 ==
5275 23:42:47.283587 Dram Type= 6, Freq= 0, CH_0, rank 0
5276 23:42:47.290298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5277 23:42:47.290860 ==
5278 23:42:47.291229
5279 23:42:47.291566
5280 23:42:47.291886 TX Vref Scan disable
5281 23:42:47.294037 == TX Byte 0 ==
5282 23:42:47.297238 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5283 23:42:47.303689 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5284 23:42:47.304232 == TX Byte 1 ==
5285 23:42:47.307088 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5286 23:42:47.314375 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5287 23:42:47.314837 ==
5288 23:42:47.317497 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 23:42:47.320760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 23:42:47.321224 ==
5291 23:42:47.321620
5292 23:42:47.321967
5293 23:42:47.323534 TX Vref Scan disable
5294 23:42:47.324008 == TX Byte 0 ==
5295 23:42:47.330252 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5296 23:42:47.333766 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5297 23:42:47.334327 == TX Byte 1 ==
5298 23:42:47.340334 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5299 23:42:47.343779 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5300 23:42:47.344359
5301 23:42:47.344726 [DATLAT]
5302 23:42:47.346677 Freq=933, CH0 RK0
5303 23:42:47.347138
5304 23:42:47.347502 DATLAT Default: 0xd
5305 23:42:47.350513 0, 0xFFFF, sum = 0
5306 23:42:47.350981 1, 0xFFFF, sum = 0
5307 23:42:47.354096 2, 0xFFFF, sum = 0
5308 23:42:47.354521 3, 0xFFFF, sum = 0
5309 23:42:47.357195 4, 0xFFFF, sum = 0
5310 23:42:47.357764 5, 0xFFFF, sum = 0
5311 23:42:47.360191 6, 0xFFFF, sum = 0
5312 23:42:47.363470 7, 0xFFFF, sum = 0
5313 23:42:47.364034 8, 0xFFFF, sum = 0
5314 23:42:47.367395 9, 0xFFFF, sum = 0
5315 23:42:47.367968 10, 0x0, sum = 1
5316 23:42:47.368341 11, 0x0, sum = 2
5317 23:42:47.370403 12, 0x0, sum = 3
5318 23:42:47.370872 13, 0x0, sum = 4
5319 23:42:47.373748 best_step = 11
5320 23:42:47.374208
5321 23:42:47.374572 ==
5322 23:42:47.377262 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 23:42:47.380504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 23:42:47.381069 ==
5325 23:42:47.383954 RX Vref Scan: 1
5326 23:42:47.384540
5327 23:42:47.384909 RX Vref 0 -> 0, step: 1
5328 23:42:47.385248
5329 23:42:47.386945 RX Delay -53 -> 252, step: 4
5330 23:42:47.387418
5331 23:42:47.390428 Set Vref, RX VrefLevel [Byte0]: 56
5332 23:42:47.393670 [Byte1]: 48
5333 23:42:47.397523
5334 23:42:47.398018 Final RX Vref Byte 0 = 56 to rank0
5335 23:42:47.401043 Final RX Vref Byte 1 = 48 to rank0
5336 23:42:47.404308 Final RX Vref Byte 0 = 56 to rank1
5337 23:42:47.407827 Final RX Vref Byte 1 = 48 to rank1==
5338 23:42:47.411093 Dram Type= 6, Freq= 0, CH_0, rank 0
5339 23:42:47.417979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 23:42:47.418535 ==
5341 23:42:47.418937 DQS Delay:
5342 23:42:47.421017 DQS0 = 0, DQS1 = 0
5343 23:42:47.421757 DQM Delay:
5344 23:42:47.422358 DQM0 = 105, DQM1 = 96
5345 23:42:47.423998 DQ Delay:
5346 23:42:47.427526 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =102
5347 23:42:47.430887 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =112
5348 23:42:47.434314 DQ8 =82, DQ9 =84, DQ10 =96, DQ11 =92
5349 23:42:47.437316 DQ12 =102, DQ13 =102, DQ14 =108, DQ15 =104
5350 23:42:47.438017
5351 23:42:47.438445
5352 23:42:47.444159 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d24, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 407 ps
5353 23:42:47.447421 CH0 RK0: MR19=505, MR18=2D24
5354 23:42:47.454106 CH0_RK0: MR19=0x505, MR18=0x2D24, DQSOSC=407, MR23=63, INC=65, DEC=43
5355 23:42:47.454524
5356 23:42:47.457313 ----->DramcWriteLeveling(PI) begin...
5357 23:42:47.457776 ==
5358 23:42:47.461149 Dram Type= 6, Freq= 0, CH_0, rank 1
5359 23:42:47.463864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5360 23:42:47.464283 ==
5361 23:42:47.467156 Write leveling (Byte 0): 34 => 34
5362 23:42:47.470898 Write leveling (Byte 1): 30 => 30
5363 23:42:47.473829 DramcWriteLeveling(PI) end<-----
5364 23:42:47.474462
5365 23:42:47.474981 ==
5366 23:42:47.476939 Dram Type= 6, Freq= 0, CH_0, rank 1
5367 23:42:47.483854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5368 23:42:47.484530 ==
5369 23:42:47.485018 [Gating] SW mode calibration
5370 23:42:47.494315 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5371 23:42:47.497261 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5372 23:42:47.501301 0 14 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (0 0)
5373 23:42:47.507287 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5374 23:42:47.510328 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5375 23:42:47.513786 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5376 23:42:47.520496 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5377 23:42:47.524288 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5378 23:42:47.527180 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 0)
5379 23:42:47.533967 0 14 28 | B1->B0 | 2929 2525 | 0 0 | (0 0) (0 0)
5380 23:42:47.537148 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
5381 23:42:47.540894 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5382 23:42:47.547365 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5383 23:42:47.551297 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5384 23:42:47.553600 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5385 23:42:47.560617 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5386 23:42:47.563877 0 15 24 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
5387 23:42:47.566958 0 15 28 | B1->B0 | 3f3e 3535 | 1 0 | (0 0) (0 0)
5388 23:42:47.573731 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5389 23:42:47.577321 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5390 23:42:47.579998 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5391 23:42:47.586914 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 23:42:47.590222 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5393 23:42:47.593562 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5394 23:42:47.600333 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5395 23:42:47.603965 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5396 23:42:47.606654 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 23:42:47.613232 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 23:42:47.617251 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 23:42:47.620120 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 23:42:47.626961 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 23:42:47.630055 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5402 23:42:47.632966 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5403 23:42:47.640060 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5404 23:42:47.643326 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5405 23:42:47.646526 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5406 23:42:47.653104 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5407 23:42:47.656911 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5408 23:42:47.660340 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5409 23:42:47.663239 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5410 23:42:47.670326 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 23:42:47.673107 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5412 23:42:47.676856 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5413 23:42:47.680487 Total UI for P1: 0, mck2ui 16
5414 23:42:47.683383 best dqsien dly found for B0: ( 1, 2, 28)
5415 23:42:47.686468 Total UI for P1: 0, mck2ui 16
5416 23:42:47.689894 best dqsien dly found for B1: ( 1, 2, 28)
5417 23:42:47.693106 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5418 23:42:47.696747 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5419 23:42:47.697306
5420 23:42:47.702973 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5421 23:42:47.706437 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5422 23:42:47.709543 [Gating] SW calibration Done
5423 23:42:47.710055 ==
5424 23:42:47.712699 Dram Type= 6, Freq= 0, CH_0, rank 1
5425 23:42:47.716222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5426 23:42:47.716686 ==
5427 23:42:47.717054 RX Vref Scan: 0
5428 23:42:47.717391
5429 23:42:47.719548 RX Vref 0 -> 0, step: 1
5430 23:42:47.720006
5431 23:42:47.723001 RX Delay -80 -> 252, step: 8
5432 23:42:47.726089 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5433 23:42:47.729354 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5434 23:42:47.736321 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5435 23:42:47.739623 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5436 23:42:47.743277 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5437 23:42:47.746422 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5438 23:42:47.749846 iDelay=208, Bit 6, Center 107 (16 ~ 199) 184
5439 23:42:47.752861 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5440 23:42:47.759618 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5441 23:42:47.762817 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5442 23:42:47.765967 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5443 23:42:47.769761 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5444 23:42:47.773338 iDelay=208, Bit 12, Center 95 (8 ~ 183) 176
5445 23:42:47.776250 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5446 23:42:47.782925 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5447 23:42:47.786036 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5448 23:42:47.786601 ==
5449 23:42:47.789554 Dram Type= 6, Freq= 0, CH_0, rank 1
5450 23:42:47.792366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5451 23:42:47.792927 ==
5452 23:42:47.796298 DQS Delay:
5453 23:42:47.796858 DQS0 = 0, DQS1 = 0
5454 23:42:47.797224 DQM Delay:
5455 23:42:47.799415 DQM0 = 105, DQM1 = 94
5456 23:42:47.799972 DQ Delay:
5457 23:42:47.802840 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =99
5458 23:42:47.805806 DQ4 =107, DQ5 =95, DQ6 =107, DQ7 =115
5459 23:42:47.809369 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5460 23:42:47.812370 DQ12 =95, DQ13 =103, DQ14 =103, DQ15 =99
5461 23:42:47.812847
5462 23:42:47.815413
5463 23:42:47.815876 ==
5464 23:42:47.818742 Dram Type= 6, Freq= 0, CH_0, rank 1
5465 23:42:47.822205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5466 23:42:47.822671 ==
5467 23:42:47.823039
5468 23:42:47.823377
5469 23:42:47.825554 TX Vref Scan disable
5470 23:42:47.826056 == TX Byte 0 ==
5471 23:42:47.832713 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5472 23:42:47.835683 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5473 23:42:47.836251 == TX Byte 1 ==
5474 23:42:47.842005 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5475 23:42:47.845363 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5476 23:42:47.845871 ==
5477 23:42:47.848866 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 23:42:47.851919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 23:42:47.852389 ==
5480 23:42:47.852813
5481 23:42:47.853195
5482 23:42:47.855562 TX Vref Scan disable
5483 23:42:47.858633 == TX Byte 0 ==
5484 23:42:47.861830 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5485 23:42:47.865293 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5486 23:42:47.868501 == TX Byte 1 ==
5487 23:42:47.871825 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5488 23:42:47.875295 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5489 23:42:47.875827
5490 23:42:47.878591 [DATLAT]
5491 23:42:47.879138 Freq=933, CH0 RK1
5492 23:42:47.879515
5493 23:42:47.882089 DATLAT Default: 0xb
5494 23:42:47.882554 0, 0xFFFF, sum = 0
5495 23:42:47.885323 1, 0xFFFF, sum = 0
5496 23:42:47.885935 2, 0xFFFF, sum = 0
5497 23:42:47.888908 3, 0xFFFF, sum = 0
5498 23:42:47.889485 4, 0xFFFF, sum = 0
5499 23:42:47.891705 5, 0xFFFF, sum = 0
5500 23:42:47.892176 6, 0xFFFF, sum = 0
5501 23:42:47.895639 7, 0xFFFF, sum = 0
5502 23:42:47.896235 8, 0xFFFF, sum = 0
5503 23:42:47.899030 9, 0xFFFF, sum = 0
5504 23:42:47.899600 10, 0x0, sum = 1
5505 23:42:47.901861 11, 0x0, sum = 2
5506 23:42:47.902442 12, 0x0, sum = 3
5507 23:42:47.905370 13, 0x0, sum = 4
5508 23:42:47.906013 best_step = 11
5509 23:42:47.906391
5510 23:42:47.906733 ==
5511 23:42:47.908669 Dram Type= 6, Freq= 0, CH_0, rank 1
5512 23:42:47.915244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5513 23:42:47.915942 ==
5514 23:42:47.916324 RX Vref Scan: 0
5515 23:42:47.916671
5516 23:42:47.918671 RX Vref 0 -> 0, step: 1
5517 23:42:47.919134
5518 23:42:47.922011 RX Delay -45 -> 252, step: 4
5519 23:42:47.925264 iDelay=199, Bit 0, Center 100 (11 ~ 190) 180
5520 23:42:47.929008 iDelay=199, Bit 1, Center 104 (19 ~ 190) 172
5521 23:42:47.935525 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5522 23:42:47.939022 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5523 23:42:47.941789 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5524 23:42:47.945131 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5525 23:42:47.948523 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5526 23:42:47.955425 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5527 23:42:47.958310 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5528 23:42:47.962079 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5529 23:42:47.965198 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5530 23:42:47.968685 iDelay=199, Bit 11, Center 86 (3 ~ 170) 168
5531 23:42:47.974747 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5532 23:42:47.978086 iDelay=199, Bit 13, Center 100 (19 ~ 182) 164
5533 23:42:47.981472 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5534 23:42:47.984911 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5535 23:42:47.985473 ==
5536 23:42:47.988167 Dram Type= 6, Freq= 0, CH_0, rank 1
5537 23:42:47.995340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5538 23:42:47.995932 ==
5539 23:42:47.996307 DQS Delay:
5540 23:42:47.996654 DQS0 = 0, DQS1 = 0
5541 23:42:47.997953 DQM Delay:
5542 23:42:47.998418 DQM0 = 104, DQM1 = 93
5543 23:42:48.001358 DQ Delay:
5544 23:42:48.004952 DQ0 =100, DQ1 =104, DQ2 =102, DQ3 =102
5545 23:42:48.008098 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5546 23:42:48.011513 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =86
5547 23:42:48.014496 DQ12 =100, DQ13 =100, DQ14 =102, DQ15 =102
5548 23:42:48.014956
5549 23:42:48.015320
5550 23:42:48.021775 [DQSOSCAuto] RK1, (LSB)MR18= 0x2902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5551 23:42:48.024896 CH0 RK1: MR19=505, MR18=2902
5552 23:42:48.031529 CH0_RK1: MR19=0x505, MR18=0x2902, DQSOSC=408, MR23=63, INC=65, DEC=43
5553 23:42:48.035174 [RxdqsGatingPostProcess] freq 933
5554 23:42:48.041758 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5555 23:42:48.042326 best DQS0 dly(2T, 0.5T) = (0, 10)
5556 23:42:48.044840 best DQS1 dly(2T, 0.5T) = (0, 10)
5557 23:42:48.048111 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5558 23:42:48.051662 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5559 23:42:48.054538 best DQS0 dly(2T, 0.5T) = (0, 10)
5560 23:42:48.058271 best DQS1 dly(2T, 0.5T) = (0, 10)
5561 23:42:48.061488 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5562 23:42:48.064445 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5563 23:42:48.067882 Pre-setting of DQS Precalculation
5564 23:42:48.074318 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5565 23:42:48.074783 ==
5566 23:42:48.077470 Dram Type= 6, Freq= 0, CH_1, rank 0
5567 23:42:48.080972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5568 23:42:48.081442 ==
5569 23:42:48.087427 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5570 23:42:48.091131 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5571 23:42:48.095219 [CA 0] Center 36 (6~67) winsize 62
5572 23:42:48.098232 [CA 1] Center 37 (6~68) winsize 63
5573 23:42:48.101630 [CA 2] Center 34 (4~65) winsize 62
5574 23:42:48.104928 [CA 3] Center 34 (4~65) winsize 62
5575 23:42:48.108423 [CA 4] Center 34 (4~64) winsize 61
5576 23:42:48.111564 [CA 5] Center 33 (3~64) winsize 62
5577 23:42:48.112031
5578 23:42:48.114670 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5579 23:42:48.115096
5580 23:42:48.118337 [CATrainingPosCal] consider 1 rank data
5581 23:42:48.121550 u2DelayCellTimex100 = 270/100 ps
5582 23:42:48.124874 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5583 23:42:48.131142 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5584 23:42:48.134405 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5585 23:42:48.138034 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5586 23:42:48.141526 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5587 23:42:48.144952 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5588 23:42:48.145482
5589 23:42:48.148231 CA PerBit enable=1, Macro0, CA PI delay=33
5590 23:42:48.148766
5591 23:42:48.151313 [CBTSetCACLKResult] CA Dly = 33
5592 23:42:48.154276 CS Dly: 7 (0~38)
5593 23:42:48.154696 ==
5594 23:42:48.158211 Dram Type= 6, Freq= 0, CH_1, rank 1
5595 23:42:48.161541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5596 23:42:48.162097 ==
5597 23:42:48.167850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5598 23:42:48.170826 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5599 23:42:48.174753 [CA 0] Center 36 (6~67) winsize 62
5600 23:42:48.178076 [CA 1] Center 37 (7~68) winsize 62
5601 23:42:48.181410 [CA 2] Center 35 (5~65) winsize 61
5602 23:42:48.184722 [CA 3] Center 34 (4~65) winsize 62
5603 23:42:48.188326 [CA 4] Center 34 (4~65) winsize 62
5604 23:42:48.191595 [CA 5] Center 33 (3~64) winsize 62
5605 23:42:48.192067
5606 23:42:48.194773 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5607 23:42:48.195253
5608 23:42:48.198267 [CATrainingPosCal] consider 2 rank data
5609 23:42:48.202223 u2DelayCellTimex100 = 270/100 ps
5610 23:42:48.205055 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5611 23:42:48.208154 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5612 23:42:48.214952 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5613 23:42:48.218087 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5614 23:42:48.221385 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5615 23:42:48.224586 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5616 23:42:48.225062
5617 23:42:48.228899 CA PerBit enable=1, Macro0, CA PI delay=33
5618 23:42:48.229463
5619 23:42:48.231872 [CBTSetCACLKResult] CA Dly = 33
5620 23:42:48.232439 CS Dly: 8 (0~40)
5621 23:42:48.232807
5622 23:42:48.238116 ----->DramcWriteLeveling(PI) begin...
5623 23:42:48.238688 ==
5624 23:42:48.241684 Dram Type= 6, Freq= 0, CH_1, rank 0
5625 23:42:48.244797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5626 23:42:48.245362 ==
5627 23:42:48.248330 Write leveling (Byte 0): 28 => 28
5628 23:42:48.251559 Write leveling (Byte 1): 28 => 28
5629 23:42:48.254701 DramcWriteLeveling(PI) end<-----
5630 23:42:48.255160
5631 23:42:48.255525 ==
5632 23:42:48.258013 Dram Type= 6, Freq= 0, CH_1, rank 0
5633 23:42:48.261925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5634 23:42:48.262452 ==
5635 23:42:48.264857 [Gating] SW mode calibration
5636 23:42:48.271354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5637 23:42:48.278523 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5638 23:42:48.280935 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5639 23:42:48.284671 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5640 23:42:48.291373 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5641 23:42:48.294580 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5642 23:42:48.298098 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5643 23:42:48.304615 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5644 23:42:48.308110 0 14 24 | B1->B0 | 3434 2a2a | 1 0 | (1 0) (0 0)
5645 23:42:48.311437 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
5646 23:42:48.314290 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5647 23:42:48.321034 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5648 23:42:48.324812 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5649 23:42:48.327728 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5650 23:42:48.334924 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5651 23:42:48.337861 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5652 23:42:48.341698 0 15 24 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
5653 23:42:48.347711 0 15 28 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5654 23:42:48.350889 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 23:42:48.354009 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5656 23:42:48.361076 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5657 23:42:48.364569 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5658 23:42:48.367716 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5659 23:42:48.374857 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5660 23:42:48.378247 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5661 23:42:48.381320 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 23:42:48.387812 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 23:42:48.391170 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 23:42:48.394157 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 23:42:48.400959 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 23:42:48.404223 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5667 23:42:48.407315 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5668 23:42:48.414212 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5669 23:42:48.417381 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5670 23:42:48.420887 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5671 23:42:48.427325 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5672 23:42:48.431149 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5673 23:42:48.433940 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5674 23:42:48.437473 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5675 23:42:48.444849 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 23:42:48.447690 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5677 23:42:48.451016 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5678 23:42:48.457518 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 23:42:48.460879 Total UI for P1: 0, mck2ui 16
5680 23:42:48.464042 best dqsien dly found for B0: ( 1, 2, 26)
5681 23:42:48.467016 Total UI for P1: 0, mck2ui 16
5682 23:42:48.470555 best dqsien dly found for B1: ( 1, 2, 26)
5683 23:42:48.473645 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5684 23:42:48.477372 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5685 23:42:48.477982
5686 23:42:48.480356 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5687 23:42:48.484080 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5688 23:42:48.487310 [Gating] SW calibration Done
5689 23:42:48.487862 ==
5690 23:42:48.490254 Dram Type= 6, Freq= 0, CH_1, rank 0
5691 23:42:48.493552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5692 23:42:48.494061 ==
5693 23:42:48.496815 RX Vref Scan: 0
5694 23:42:48.497278
5695 23:42:48.500701 RX Vref 0 -> 0, step: 1
5696 23:42:48.501264
5697 23:42:48.501696 RX Delay -80 -> 252, step: 8
5698 23:42:48.507332 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5699 23:42:48.510687 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5700 23:42:48.513775 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5701 23:42:48.517061 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5702 23:42:48.520282 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5703 23:42:48.523911 iDelay=208, Bit 5, Center 119 (32 ~ 207) 176
5704 23:42:48.530549 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5705 23:42:48.533197 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5706 23:42:48.537282 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5707 23:42:48.540218 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5708 23:42:48.543841 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5709 23:42:48.547043 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5710 23:42:48.553667 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5711 23:42:48.557229 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5712 23:42:48.560707 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5713 23:42:48.563552 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5714 23:42:48.564129 ==
5715 23:42:48.566646 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 23:42:48.573533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 23:42:48.574167 ==
5718 23:42:48.574545 DQS Delay:
5719 23:42:48.576860 DQS0 = 0, DQS1 = 0
5720 23:42:48.577429 DQM Delay:
5721 23:42:48.577916 DQM0 = 103, DQM1 = 98
5722 23:42:48.580047 DQ Delay:
5723 23:42:48.583183 DQ0 =103, DQ1 =99, DQ2 =91, DQ3 =99
5724 23:42:48.586880 DQ4 =99, DQ5 =119, DQ6 =111, DQ7 =103
5725 23:42:48.589806 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5726 23:42:48.593075 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5727 23:42:48.593544
5728 23:42:48.593954
5729 23:42:48.594429 ==
5730 23:42:48.596707 Dram Type= 6, Freq= 0, CH_1, rank 0
5731 23:42:48.600624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5732 23:42:48.601202 ==
5733 23:42:48.601621
5734 23:42:48.601992
5735 23:42:48.603199 TX Vref Scan disable
5736 23:42:48.606245 == TX Byte 0 ==
5737 23:42:48.609844 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5738 23:42:48.613317 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5739 23:42:48.616777 == TX Byte 1 ==
5740 23:42:48.619596 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5741 23:42:48.623858 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5742 23:42:48.624422 ==
5743 23:42:48.626532 Dram Type= 6, Freq= 0, CH_1, rank 0
5744 23:42:48.629799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 23:42:48.633172 ==
5746 23:42:48.633672
5747 23:42:48.634042
5748 23:42:48.634380 TX Vref Scan disable
5749 23:42:48.636926 == TX Byte 0 ==
5750 23:42:48.640068 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5751 23:42:48.646897 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5752 23:42:48.647517 == TX Byte 1 ==
5753 23:42:48.650160 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5754 23:42:48.657076 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5755 23:42:48.657705
5756 23:42:48.658088 [DATLAT]
5757 23:42:48.658556 Freq=933, CH1 RK0
5758 23:42:48.658910
5759 23:42:48.659838 DATLAT Default: 0xd
5760 23:42:48.660304 0, 0xFFFF, sum = 0
5761 23:42:48.663675 1, 0xFFFF, sum = 0
5762 23:42:48.664255 2, 0xFFFF, sum = 0
5763 23:42:48.667029 3, 0xFFFF, sum = 0
5764 23:42:48.669899 4, 0xFFFF, sum = 0
5765 23:42:48.670375 5, 0xFFFF, sum = 0
5766 23:42:48.673747 6, 0xFFFF, sum = 0
5767 23:42:48.674223 7, 0xFFFF, sum = 0
5768 23:42:48.676724 8, 0xFFFF, sum = 0
5769 23:42:48.677421 9, 0xFFFF, sum = 0
5770 23:42:48.679718 10, 0x0, sum = 1
5771 23:42:48.680273 11, 0x0, sum = 2
5772 23:42:48.683393 12, 0x0, sum = 3
5773 23:42:48.684011 13, 0x0, sum = 4
5774 23:42:48.684630 best_step = 11
5775 23:42:48.684983
5776 23:42:48.686727 ==
5777 23:42:48.689571 Dram Type= 6, Freq= 0, CH_1, rank 0
5778 23:42:48.693081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5779 23:42:48.693508 ==
5780 23:42:48.693927 RX Vref Scan: 1
5781 23:42:48.694464
5782 23:42:48.696226 RX Vref 0 -> 0, step: 1
5783 23:42:48.696654
5784 23:42:48.699754 RX Delay -45 -> 252, step: 4
5785 23:42:48.700175
5786 23:42:48.702756 Set Vref, RX VrefLevel [Byte0]: 54
5787 23:42:48.706176 [Byte1]: 48
5788 23:42:48.706616
5789 23:42:48.709337 Final RX Vref Byte 0 = 54 to rank0
5790 23:42:48.713193 Final RX Vref Byte 1 = 48 to rank0
5791 23:42:48.716312 Final RX Vref Byte 0 = 54 to rank1
5792 23:42:48.720161 Final RX Vref Byte 1 = 48 to rank1==
5793 23:42:48.722967 Dram Type= 6, Freq= 0, CH_1, rank 0
5794 23:42:48.726121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5795 23:42:48.730018 ==
5796 23:42:48.730441 DQS Delay:
5797 23:42:48.730777 DQS0 = 0, DQS1 = 0
5798 23:42:48.732650 DQM Delay:
5799 23:42:48.733071 DQM0 = 103, DQM1 = 99
5800 23:42:48.736611 DQ Delay:
5801 23:42:48.739482 DQ0 =106, DQ1 =96, DQ2 =96, DQ3 =102
5802 23:42:48.742942 DQ4 =102, DQ5 =112, DQ6 =112, DQ7 =104
5803 23:42:48.746294 DQ8 =88, DQ9 =92, DQ10 =100, DQ11 =92
5804 23:42:48.749485 DQ12 =104, DQ13 =106, DQ14 =108, DQ15 =108
5805 23:42:48.750090
5806 23:42:48.750436
5807 23:42:48.755835 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5808 23:42:48.759375 CH1 RK0: MR19=505, MR18=1830
5809 23:42:48.765801 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5810 23:42:48.766320
5811 23:42:48.769233 ----->DramcWriteLeveling(PI) begin...
5812 23:42:48.769714 ==
5813 23:42:48.773233 Dram Type= 6, Freq= 0, CH_1, rank 1
5814 23:42:48.776109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 23:42:48.776642 ==
5816 23:42:48.779919 Write leveling (Byte 0): 25 => 25
5817 23:42:48.782936 Write leveling (Byte 1): 26 => 26
5818 23:42:48.786119 DramcWriteLeveling(PI) end<-----
5819 23:42:48.786651
5820 23:42:48.786989 ==
5821 23:42:48.789440 Dram Type= 6, Freq= 0, CH_1, rank 1
5822 23:42:48.792759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5823 23:42:48.796337 ==
5824 23:42:48.796865 [Gating] SW mode calibration
5825 23:42:48.802803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5826 23:42:48.809268 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5827 23:42:48.812496 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5828 23:42:48.819405 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5829 23:42:48.822978 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5830 23:42:48.826453 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5831 23:42:48.833176 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5832 23:42:48.835848 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (0 0) (1 1)
5833 23:42:48.839878 0 14 24 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 0)
5834 23:42:48.846078 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5835 23:42:48.849849 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5836 23:42:48.852750 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5837 23:42:48.859089 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5838 23:42:48.862605 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5839 23:42:48.866115 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5840 23:42:48.872953 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5841 23:42:48.875728 0 15 24 | B1->B0 | 3737 2929 | 0 1 | (0 0) (0 0)
5842 23:42:48.879624 0 15 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
5843 23:42:48.882703 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5844 23:42:48.889036 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5845 23:42:48.892311 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 23:42:48.896106 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5847 23:42:48.902596 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5848 23:42:48.905693 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5849 23:42:48.909193 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5850 23:42:48.915247 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 23:42:48.919354 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 23:42:48.921709 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 23:42:48.928673 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 23:42:48.931963 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 23:42:48.935888 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5856 23:42:48.941718 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5857 23:42:48.945277 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5858 23:42:48.949069 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5859 23:42:48.955105 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5860 23:42:48.958860 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5861 23:42:48.961995 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5862 23:42:48.968594 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5863 23:42:48.972289 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5864 23:42:48.975028 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5865 23:42:48.981927 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5866 23:42:48.984962 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5867 23:42:48.988604 Total UI for P1: 0, mck2ui 16
5868 23:42:48.991891 best dqsien dly found for B0: ( 1, 2, 26)
5869 23:42:48.995295 Total UI for P1: 0, mck2ui 16
5870 23:42:48.998703 best dqsien dly found for B1: ( 1, 2, 22)
5871 23:42:49.001707 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5872 23:42:49.005742 best DQS1 dly(MCK, UI, PI) = (1, 2, 22)
5873 23:42:49.006313
5874 23:42:49.008694 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5875 23:42:49.011811 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 22)
5876 23:42:49.014870 [Gating] SW calibration Done
5877 23:42:49.015339 ==
5878 23:42:49.018238 Dram Type= 6, Freq= 0, CH_1, rank 1
5879 23:42:49.021476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5880 23:42:49.025423 ==
5881 23:42:49.026046 RX Vref Scan: 0
5882 23:42:49.026426
5883 23:42:49.028220 RX Vref 0 -> 0, step: 1
5884 23:42:49.028686
5885 23:42:49.031619 RX Delay -80 -> 252, step: 8
5886 23:42:49.034789 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5887 23:42:49.038793 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5888 23:42:49.041433 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5889 23:42:49.045117 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5890 23:42:49.048326 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5891 23:42:49.055162 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5892 23:42:49.058262 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5893 23:42:49.061478 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5894 23:42:49.064759 iDelay=208, Bit 8, Center 91 (0 ~ 183) 184
5895 23:42:49.067875 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5896 23:42:49.071516 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5897 23:42:49.077837 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5898 23:42:49.081189 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5899 23:42:49.084148 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5900 23:42:49.087915 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5901 23:42:49.091042 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5902 23:42:49.094352 ==
5903 23:42:49.094837 Dram Type= 6, Freq= 0, CH_1, rank 1
5904 23:42:49.101191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5905 23:42:49.101703 ==
5906 23:42:49.102084 DQS Delay:
5907 23:42:49.104642 DQS0 = 0, DQS1 = 0
5908 23:42:49.105221 DQM Delay:
5909 23:42:49.107855 DQM0 = 102, DQM1 = 98
5910 23:42:49.108323 DQ Delay:
5911 23:42:49.110832 DQ0 =107, DQ1 =99, DQ2 =91, DQ3 =99
5912 23:42:49.114774 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5913 23:42:49.117955 DQ8 =91, DQ9 =91, DQ10 =99, DQ11 =91
5914 23:42:49.121203 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5915 23:42:49.121811
5916 23:42:49.122187
5917 23:42:49.122533 ==
5918 23:42:49.124667 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 23:42:49.127969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 23:42:49.128537 ==
5921 23:42:49.128921
5922 23:42:49.131531
5923 23:42:49.132020 TX Vref Scan disable
5924 23:42:49.134583 == TX Byte 0 ==
5925 23:42:49.137766 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5926 23:42:49.140829 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5927 23:42:49.144316 == TX Byte 1 ==
5928 23:42:49.148045 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5929 23:42:49.150643 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5930 23:42:49.151114 ==
5931 23:42:49.154144 Dram Type= 6, Freq= 0, CH_1, rank 1
5932 23:42:49.160440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5933 23:42:49.160994 ==
5934 23:42:49.161365
5935 23:42:49.161756
5936 23:42:49.162092 TX Vref Scan disable
5937 23:42:49.164994 == TX Byte 0 ==
5938 23:42:49.168359 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5939 23:42:49.174906 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5940 23:42:49.175566 == TX Byte 1 ==
5941 23:42:49.178516 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5942 23:42:49.181769 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5943 23:42:49.185124
5944 23:42:49.185742 [DATLAT]
5945 23:42:49.186125 Freq=933, CH1 RK1
5946 23:42:49.186476
5947 23:42:49.188776 DATLAT Default: 0xb
5948 23:42:49.189346 0, 0xFFFF, sum = 0
5949 23:42:49.191980 1, 0xFFFF, sum = 0
5950 23:42:49.192455 2, 0xFFFF, sum = 0
5951 23:42:49.195085 3, 0xFFFF, sum = 0
5952 23:42:49.195559 4, 0xFFFF, sum = 0
5953 23:42:49.198271 5, 0xFFFF, sum = 0
5954 23:42:49.198743 6, 0xFFFF, sum = 0
5955 23:42:49.201826 7, 0xFFFF, sum = 0
5956 23:42:49.204994 8, 0xFFFF, sum = 0
5957 23:42:49.205471 9, 0xFFFF, sum = 0
5958 23:42:49.208088 10, 0x0, sum = 1
5959 23:42:49.208562 11, 0x0, sum = 2
5960 23:42:49.208941 12, 0x0, sum = 3
5961 23:42:49.211582 13, 0x0, sum = 4
5962 23:42:49.212074 best_step = 11
5963 23:42:49.212445
5964 23:42:49.212884 ==
5965 23:42:49.214787 Dram Type= 6, Freq= 0, CH_1, rank 1
5966 23:42:49.221949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5967 23:42:49.222525 ==
5968 23:42:49.223106 RX Vref Scan: 0
5969 23:42:49.223528
5970 23:42:49.224865 RX Vref 0 -> 0, step: 1
5971 23:42:49.225327
5972 23:42:49.228454 RX Delay -45 -> 252, step: 4
5973 23:42:49.231578 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5974 23:42:49.237907 iDelay=203, Bit 1, Center 100 (19 ~ 182) 164
5975 23:42:49.241505 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5976 23:42:49.244901 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5977 23:42:49.247948 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5978 23:42:49.251600 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5979 23:42:49.258199 iDelay=203, Bit 6, Center 114 (31 ~ 198) 168
5980 23:42:49.261422 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5981 23:42:49.264785 iDelay=203, Bit 8, Center 88 (3 ~ 174) 172
5982 23:42:49.268120 iDelay=203, Bit 9, Center 88 (3 ~ 174) 172
5983 23:42:49.271283 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5984 23:42:49.274749 iDelay=203, Bit 11, Center 92 (7 ~ 178) 172
5985 23:42:49.281296 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5986 23:42:49.284620 iDelay=203, Bit 13, Center 104 (23 ~ 186) 164
5987 23:42:49.287994 iDelay=203, Bit 14, Center 106 (27 ~ 186) 160
5988 23:42:49.291256 iDelay=203, Bit 15, Center 110 (27 ~ 194) 168
5989 23:42:49.291819 ==
5990 23:42:49.295089 Dram Type= 6, Freq= 0, CH_1, rank 1
5991 23:42:49.301081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5992 23:42:49.301649 ==
5993 23:42:49.302023 DQS Delay:
5994 23:42:49.305234 DQS0 = 0, DQS1 = 0
5995 23:42:49.305840 DQM Delay:
5996 23:42:49.306218 DQM0 = 104, DQM1 = 99
5997 23:42:49.308226 DQ Delay:
5998 23:42:49.311622 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5999 23:42:49.314058 DQ4 =100, DQ5 =118, DQ6 =114, DQ7 =104
6000 23:42:49.317782 DQ8 =88, DQ9 =88, DQ10 =100, DQ11 =92
6001 23:42:49.321315 DQ12 =110, DQ13 =104, DQ14 =106, DQ15 =110
6002 23:42:49.321932
6003 23:42:49.322306
6004 23:42:49.327615 [DQSOSCAuto] RK1, (LSB)MR18= 0x28fc, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 409 ps
6005 23:42:49.331067 CH1 RK1: MR19=504, MR18=28FC
6006 23:42:49.337508 CH1_RK1: MR19=0x504, MR18=0x28FC, DQSOSC=409, MR23=63, INC=64, DEC=43
6007 23:42:49.341021 [RxdqsGatingPostProcess] freq 933
6008 23:42:49.347642 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6009 23:42:49.350825 best DQS0 dly(2T, 0.5T) = (0, 10)
6010 23:42:49.354102 best DQS1 dly(2T, 0.5T) = (0, 10)
6011 23:42:49.354574 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6012 23:42:49.357371 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6013 23:42:49.360739 best DQS0 dly(2T, 0.5T) = (0, 10)
6014 23:42:49.364373 best DQS1 dly(2T, 0.5T) = (0, 10)
6015 23:42:49.367849 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6016 23:42:49.370900 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6017 23:42:49.374245 Pre-setting of DQS Precalculation
6018 23:42:49.380907 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6019 23:42:49.387523 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6020 23:42:49.393800 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6021 23:42:49.394352
6022 23:42:49.394726
6023 23:42:49.397564 [Calibration Summary] 1866 Mbps
6024 23:42:49.398189 CH 0, Rank 0
6025 23:42:49.400602 SW Impedance : PASS
6026 23:42:49.404391 DUTY Scan : NO K
6027 23:42:49.404957 ZQ Calibration : PASS
6028 23:42:49.407567 Jitter Meter : NO K
6029 23:42:49.410528 CBT Training : PASS
6030 23:42:49.411091 Write leveling : PASS
6031 23:42:49.413790 RX DQS gating : PASS
6032 23:42:49.417369 RX DQ/DQS(RDDQC) : PASS
6033 23:42:49.418003 TX DQ/DQS : PASS
6034 23:42:49.420388 RX DATLAT : PASS
6035 23:42:49.423652 RX DQ/DQS(Engine): PASS
6036 23:42:49.424149 TX OE : NO K
6037 23:42:49.424536 All Pass.
6038 23:42:49.427516
6039 23:42:49.428083 CH 0, Rank 1
6040 23:42:49.430238 SW Impedance : PASS
6041 23:42:49.430706 DUTY Scan : NO K
6042 23:42:49.434054 ZQ Calibration : PASS
6043 23:42:49.434613 Jitter Meter : NO K
6044 23:42:49.437213 CBT Training : PASS
6045 23:42:49.440390 Write leveling : PASS
6046 23:42:49.440958 RX DQS gating : PASS
6047 23:42:49.443824 RX DQ/DQS(RDDQC) : PASS
6048 23:42:49.447178 TX DQ/DQS : PASS
6049 23:42:49.447750 RX DATLAT : PASS
6050 23:42:49.450874 RX DQ/DQS(Engine): PASS
6051 23:42:49.453667 TX OE : NO K
6052 23:42:49.454144 All Pass.
6053 23:42:49.454520
6054 23:42:49.454864 CH 1, Rank 0
6055 23:42:49.457032 SW Impedance : PASS
6056 23:42:49.460085 DUTY Scan : NO K
6057 23:42:49.460627 ZQ Calibration : PASS
6058 23:42:49.463957 Jitter Meter : NO K
6059 23:42:49.467048 CBT Training : PASS
6060 23:42:49.467514 Write leveling : PASS
6061 23:42:49.470616 RX DQS gating : PASS
6062 23:42:49.473353 RX DQ/DQS(RDDQC) : PASS
6063 23:42:49.473882 TX DQ/DQS : PASS
6064 23:42:49.476911 RX DATLAT : PASS
6065 23:42:49.479999 RX DQ/DQS(Engine): PASS
6066 23:42:49.480570 TX OE : NO K
6067 23:42:49.480950 All Pass.
6068 23:42:49.483724
6069 23:42:49.484297 CH 1, Rank 1
6070 23:42:49.486861 SW Impedance : PASS
6071 23:42:49.487328 DUTY Scan : NO K
6072 23:42:49.490139 ZQ Calibration : PASS
6073 23:42:49.493113 Jitter Meter : NO K
6074 23:42:49.493619 CBT Training : PASS
6075 23:42:49.497023 Write leveling : PASS
6076 23:42:49.497490 RX DQS gating : PASS
6077 23:42:49.500357 RX DQ/DQS(RDDQC) : PASS
6078 23:42:49.503498 TX DQ/DQS : PASS
6079 23:42:49.504071 RX DATLAT : PASS
6080 23:42:49.506566 RX DQ/DQS(Engine): PASS
6081 23:42:49.510220 TX OE : NO K
6082 23:42:49.510799 All Pass.
6083 23:42:49.511171
6084 23:42:49.513211 DramC Write-DBI off
6085 23:42:49.513664 PER_BANK_REFRESH: Hybrid Mode
6086 23:42:49.516880 TX_TRACKING: ON
6087 23:42:49.523615 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6088 23:42:49.529726 [FAST_K] Save calibration result to emmc
6089 23:42:49.533326 dramc_set_vcore_voltage set vcore to 650000
6090 23:42:49.533880 Read voltage for 400, 6
6091 23:42:49.536463 Vio18 = 0
6092 23:42:49.536940 Vcore = 650000
6093 23:42:49.537309 Vdram = 0
6094 23:42:49.539720 Vddq = 0
6095 23:42:49.540286 Vmddr = 0
6096 23:42:49.543166 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6097 23:42:49.550146 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6098 23:42:49.553480 MEM_TYPE=3, freq_sel=20
6099 23:42:49.556730 sv_algorithm_assistance_LP4_800
6100 23:42:49.559986 ============ PULL DRAM RESETB DOWN ============
6101 23:42:49.563600 ========== PULL DRAM RESETB DOWN end =========
6102 23:42:49.566625 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6103 23:42:49.570190 ===================================
6104 23:42:49.573629 LPDDR4 DRAM CONFIGURATION
6105 23:42:49.576623 ===================================
6106 23:42:49.579977 EX_ROW_EN[0] = 0x0
6107 23:42:49.580448 EX_ROW_EN[1] = 0x0
6108 23:42:49.583318 LP4Y_EN = 0x0
6109 23:42:49.583885 WORK_FSP = 0x0
6110 23:42:49.586500 WL = 0x2
6111 23:42:49.586966 RL = 0x2
6112 23:42:49.590249 BL = 0x2
6113 23:42:49.590828 RPST = 0x0
6114 23:42:49.593177 RD_PRE = 0x0
6115 23:42:49.593708 WR_PRE = 0x1
6116 23:42:49.596549 WR_PST = 0x0
6117 23:42:49.597122 DBI_WR = 0x0
6118 23:42:49.600181 DBI_RD = 0x0
6119 23:42:49.603029 OTF = 0x1
6120 23:42:49.606794 ===================================
6121 23:42:49.607372 ===================================
6122 23:42:49.609633 ANA top config
6123 23:42:49.612961 ===================================
6124 23:42:49.617064 DLL_ASYNC_EN = 0
6125 23:42:49.617691 ALL_SLAVE_EN = 1
6126 23:42:49.620515 NEW_RANK_MODE = 1
6127 23:42:49.623512 DLL_IDLE_MODE = 1
6128 23:42:49.626431 LP45_APHY_COMB_EN = 1
6129 23:42:49.629766 TX_ODT_DIS = 1
6130 23:42:49.630342 NEW_8X_MODE = 1
6131 23:42:49.633380 ===================================
6132 23:42:49.636334 ===================================
6133 23:42:49.640163 data_rate = 800
6134 23:42:49.643318 CKR = 1
6135 23:42:49.646777 DQ_P2S_RATIO = 4
6136 23:42:49.650117 ===================================
6137 23:42:49.653094 CA_P2S_RATIO = 4
6138 23:42:49.656367 DQ_CA_OPEN = 0
6139 23:42:49.657083 DQ_SEMI_OPEN = 1
6140 23:42:49.659952 CA_SEMI_OPEN = 1
6141 23:42:49.663059 CA_FULL_RATE = 0
6142 23:42:49.666084 DQ_CKDIV4_EN = 0
6143 23:42:49.670349 CA_CKDIV4_EN = 1
6144 23:42:49.672935 CA_PREDIV_EN = 0
6145 23:42:49.673403 PH8_DLY = 0
6146 23:42:49.676071 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6147 23:42:49.679441 DQ_AAMCK_DIV = 0
6148 23:42:49.683226 CA_AAMCK_DIV = 0
6149 23:42:49.685950 CA_ADMCK_DIV = 4
6150 23:42:49.689730 DQ_TRACK_CA_EN = 0
6151 23:42:49.690305 CA_PICK = 800
6152 23:42:49.692856 CA_MCKIO = 400
6153 23:42:49.696300 MCKIO_SEMI = 400
6154 23:42:49.699338 PLL_FREQ = 3016
6155 23:42:49.702685 DQ_UI_PI_RATIO = 32
6156 23:42:49.706107 CA_UI_PI_RATIO = 32
6157 23:42:49.709388 ===================================
6158 23:42:49.712768 ===================================
6159 23:42:49.715960 memory_type:LPDDR4
6160 23:42:49.716429 GP_NUM : 10
6161 23:42:49.719441 SRAM_EN : 1
6162 23:42:49.720006 MD32_EN : 0
6163 23:42:49.722337 ===================================
6164 23:42:49.726403 [ANA_INIT] >>>>>>>>>>>>>>
6165 23:42:49.729390 <<<<<< [CONFIGURE PHASE]: ANA_TX
6166 23:42:49.732373 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6167 23:42:49.735648 ===================================
6168 23:42:49.739183 data_rate = 800,PCW = 0X7400
6169 23:42:49.742388 ===================================
6170 23:42:49.745687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6171 23:42:49.749219 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6172 23:42:49.762002 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6173 23:42:49.766093 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6174 23:42:49.768801 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6175 23:42:49.772470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6176 23:42:49.775614 [ANA_INIT] flow start
6177 23:42:49.779235 [ANA_INIT] PLL >>>>>>>>
6178 23:42:49.779728 [ANA_INIT] PLL <<<<<<<<
6179 23:42:49.782251 [ANA_INIT] MIDPI >>>>>>>>
6180 23:42:49.785510 [ANA_INIT] MIDPI <<<<<<<<
6181 23:42:49.786029 [ANA_INIT] DLL >>>>>>>>
6182 23:42:49.788744 [ANA_INIT] flow end
6183 23:42:49.792277 ============ LP4 DIFF to SE enter ============
6184 23:42:49.798501 ============ LP4 DIFF to SE exit ============
6185 23:42:49.798928 [ANA_INIT] <<<<<<<<<<<<<
6186 23:42:49.802649 [Flow] Enable top DCM control >>>>>
6187 23:42:49.805401 [Flow] Enable top DCM control <<<<<
6188 23:42:49.809256 Enable DLL master slave shuffle
6189 23:42:49.815156 ==============================================================
6190 23:42:49.815633 Gating Mode config
6191 23:42:49.821981 ==============================================================
6192 23:42:49.825552 Config description:
6193 23:42:49.831960 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6194 23:42:49.839073 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6195 23:42:49.845624 SELPH_MODE 0: By rank 1: By Phase
6196 23:42:49.852472 ==============================================================
6197 23:42:49.853049 GAT_TRACK_EN = 0
6198 23:42:49.855318 RX_GATING_MODE = 2
6199 23:42:49.858712 RX_GATING_TRACK_MODE = 2
6200 23:42:49.861686 SELPH_MODE = 1
6201 23:42:49.865327 PICG_EARLY_EN = 1
6202 23:42:49.868648 VALID_LAT_VALUE = 1
6203 23:42:49.875282 ==============================================================
6204 23:42:49.878360 Enter into Gating configuration >>>>
6205 23:42:49.882139 Exit from Gating configuration <<<<
6206 23:42:49.885076 Enter into DVFS_PRE_config >>>>>
6207 23:42:49.894891 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6208 23:42:49.898059 Exit from DVFS_PRE_config <<<<<
6209 23:42:49.901666 Enter into PICG configuration >>>>
6210 23:42:49.904615 Exit from PICG configuration <<<<
6211 23:42:49.907783 [RX_INPUT] configuration >>>>>
6212 23:42:49.911581 [RX_INPUT] configuration <<<<<
6213 23:42:49.914884 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6214 23:42:49.921544 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6215 23:42:49.928620 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6216 23:42:49.931417 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6217 23:42:49.937689 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6218 23:42:49.944623 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6219 23:42:49.948208 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6220 23:42:49.951153 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6221 23:42:49.957631 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6222 23:42:49.961895 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6223 23:42:49.964413 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6224 23:42:49.971112 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6225 23:42:49.974504 ===================================
6226 23:42:49.974975 LPDDR4 DRAM CONFIGURATION
6227 23:42:49.977442 ===================================
6228 23:42:49.980947 EX_ROW_EN[0] = 0x0
6229 23:42:49.984249 EX_ROW_EN[1] = 0x0
6230 23:42:49.984823 LP4Y_EN = 0x0
6231 23:42:49.987802 WORK_FSP = 0x0
6232 23:42:49.988315 WL = 0x2
6233 23:42:49.991060 RL = 0x2
6234 23:42:49.991670 BL = 0x2
6235 23:42:49.994182 RPST = 0x0
6236 23:42:49.994694 RD_PRE = 0x0
6237 23:42:49.997397 WR_PRE = 0x1
6238 23:42:49.997918 WR_PST = 0x0
6239 23:42:50.001025 DBI_WR = 0x0
6240 23:42:50.001443 DBI_RD = 0x0
6241 23:42:50.004125 OTF = 0x1
6242 23:42:50.007628 ===================================
6243 23:42:50.010565 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6244 23:42:50.014091 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6245 23:42:50.020531 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6246 23:42:50.024161 ===================================
6247 23:42:50.024602 LPDDR4 DRAM CONFIGURATION
6248 23:42:50.027241 ===================================
6249 23:42:50.030756 EX_ROW_EN[0] = 0x10
6250 23:42:50.034275 EX_ROW_EN[1] = 0x0
6251 23:42:50.034776 LP4Y_EN = 0x0
6252 23:42:50.037167 WORK_FSP = 0x0
6253 23:42:50.037619 WL = 0x2
6254 23:42:50.040756 RL = 0x2
6255 23:42:50.041181 BL = 0x2
6256 23:42:50.044738 RPST = 0x0
6257 23:42:50.045295 RD_PRE = 0x0
6258 23:42:50.047697 WR_PRE = 0x1
6259 23:42:50.048274 WR_PST = 0x0
6260 23:42:50.050519 DBI_WR = 0x0
6261 23:42:50.050980 DBI_RD = 0x0
6262 23:42:50.054012 OTF = 0x1
6263 23:42:50.057682 ===================================
6264 23:42:50.064052 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6265 23:42:50.067451 nWR fixed to 30
6266 23:42:50.068019 [ModeRegInit_LP4] CH0 RK0
6267 23:42:50.070245 [ModeRegInit_LP4] CH0 RK1
6268 23:42:50.073965 [ModeRegInit_LP4] CH1 RK0
6269 23:42:50.077266 [ModeRegInit_LP4] CH1 RK1
6270 23:42:50.077786 match AC timing 19
6271 23:42:50.081196 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6272 23:42:50.087281 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6273 23:42:50.090470 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6274 23:42:50.093886 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6275 23:42:50.101006 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6276 23:42:50.101568 ==
6277 23:42:50.104068 Dram Type= 6, Freq= 0, CH_0, rank 0
6278 23:42:50.107197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6279 23:42:50.107756 ==
6280 23:42:50.113849 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6281 23:42:50.117066 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6282 23:42:50.120895 [CA 0] Center 36 (8~64) winsize 57
6283 23:42:50.123917 [CA 1] Center 36 (8~64) winsize 57
6284 23:42:50.127588 [CA 2] Center 36 (8~64) winsize 57
6285 23:42:50.130342 [CA 3] Center 36 (8~64) winsize 57
6286 23:42:50.133552 [CA 4] Center 36 (8~64) winsize 57
6287 23:42:50.137638 [CA 5] Center 36 (8~64) winsize 57
6288 23:42:50.138199
6289 23:42:50.140555 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6290 23:42:50.141024
6291 23:42:50.143663 [CATrainingPosCal] consider 1 rank data
6292 23:42:50.147169 u2DelayCellTimex100 = 270/100 ps
6293 23:42:50.150577 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6294 23:42:50.153828 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6295 23:42:50.160877 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6296 23:42:50.163900 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6297 23:42:50.167151 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6298 23:42:50.170298 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 23:42:50.170855
6300 23:42:50.173542 CA PerBit enable=1, Macro0, CA PI delay=36
6301 23:42:50.174135
6302 23:42:50.177064 [CBTSetCACLKResult] CA Dly = 36
6303 23:42:50.177530 CS Dly: 1 (0~32)
6304 23:42:50.177938 ==
6305 23:42:50.180608 Dram Type= 6, Freq= 0, CH_0, rank 1
6306 23:42:50.187021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6307 23:42:50.187595 ==
6308 23:42:50.190184 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6309 23:42:50.197217 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6310 23:42:50.200306 [CA 0] Center 36 (8~64) winsize 57
6311 23:42:50.203789 [CA 1] Center 36 (8~64) winsize 57
6312 23:42:50.207177 [CA 2] Center 36 (8~64) winsize 57
6313 23:42:50.210301 [CA 3] Center 36 (8~64) winsize 57
6314 23:42:50.213649 [CA 4] Center 36 (8~64) winsize 57
6315 23:42:50.216784 [CA 5] Center 36 (8~64) winsize 57
6316 23:42:50.217252
6317 23:42:50.220366 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6318 23:42:50.220928
6319 23:42:50.223486 [CATrainingPosCal] consider 2 rank data
6320 23:42:50.227306 u2DelayCellTimex100 = 270/100 ps
6321 23:42:50.230510 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6322 23:42:50.233744 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6323 23:42:50.237345 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6324 23:42:50.240524 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6325 23:42:50.243659 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6326 23:42:50.246952 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6327 23:42:50.249938
6328 23:42:50.253454 CA PerBit enable=1, Macro0, CA PI delay=36
6329 23:42:50.254111
6330 23:42:50.256511 [CBTSetCACLKResult] CA Dly = 36
6331 23:42:50.256968 CS Dly: 1 (0~32)
6332 23:42:50.257332
6333 23:42:50.260431 ----->DramcWriteLeveling(PI) begin...
6334 23:42:50.261000 ==
6335 23:42:50.263613 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 23:42:50.267178 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 23:42:50.270539 ==
6338 23:42:50.271101 Write leveling (Byte 0): 40 => 8
6339 23:42:50.273368 Write leveling (Byte 1): 40 => 8
6340 23:42:50.276687 DramcWriteLeveling(PI) end<-----
6341 23:42:50.277152
6342 23:42:50.277523 ==
6343 23:42:50.280092 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 23:42:50.286831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 23:42:50.287395 ==
6346 23:42:50.287772 [Gating] SW mode calibration
6347 23:42:50.296640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6348 23:42:50.300293 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6349 23:42:50.303316 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6350 23:42:50.309989 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6351 23:42:50.313391 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6352 23:42:50.316457 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6353 23:42:50.322908 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6354 23:42:50.327056 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6355 23:42:50.329825 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6356 23:42:50.336196 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6357 23:42:50.339765 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6358 23:42:50.342875 Total UI for P1: 0, mck2ui 16
6359 23:42:50.346305 best dqsien dly found for B0: ( 0, 14, 24)
6360 23:42:50.349714 Total UI for P1: 0, mck2ui 16
6361 23:42:50.352705 best dqsien dly found for B1: ( 0, 14, 24)
6362 23:42:50.356367 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6363 23:42:50.359450 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6364 23:42:50.359863
6365 23:42:50.363211 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6366 23:42:50.366206 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6367 23:42:50.369625 [Gating] SW calibration Done
6368 23:42:50.370149 ==
6369 23:42:50.373102 Dram Type= 6, Freq= 0, CH_0, rank 0
6370 23:42:50.379202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6371 23:42:50.379621 ==
6372 23:42:50.379982 RX Vref Scan: 0
6373 23:42:50.380297
6374 23:42:50.382400 RX Vref 0 -> 0, step: 1
6375 23:42:50.382814
6376 23:42:50.386280 RX Delay -410 -> 252, step: 16
6377 23:42:50.389093 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6378 23:42:50.392269 iDelay=230, Bit 1, Center -3 (-234 ~ 229) 464
6379 23:42:50.399481 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6380 23:42:50.402462 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6381 23:42:50.406128 iDelay=230, Bit 4, Center -11 (-234 ~ 213) 448
6382 23:42:50.409753 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6383 23:42:50.412633 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6384 23:42:50.419481 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6385 23:42:50.422510 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6386 23:42:50.425803 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6387 23:42:50.429248 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6388 23:42:50.435768 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6389 23:42:50.439229 iDelay=230, Bit 12, Center -11 (-234 ~ 213) 448
6390 23:42:50.442325 iDelay=230, Bit 13, Center -11 (-234 ~ 213) 448
6391 23:42:50.449226 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6392 23:42:50.452582 iDelay=230, Bit 15, Center -11 (-234 ~ 213) 448
6393 23:42:50.453001 ==
6394 23:42:50.456204 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 23:42:50.458716 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 23:42:50.459179 ==
6397 23:42:50.462404 DQS Delay:
6398 23:42:50.462974 DQS0 = 27, DQS1 = 35
6399 23:42:50.463342 DQM Delay:
6400 23:42:50.465988 DQM0 = 13, DQM1 = 15
6401 23:42:50.466545 DQ Delay:
6402 23:42:50.469035 DQ0 =8, DQ1 =24, DQ2 =8, DQ3 =0
6403 23:42:50.472093 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6404 23:42:50.475364 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6405 23:42:50.478917 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6406 23:42:50.479381
6407 23:42:50.479746
6408 23:42:50.480086 ==
6409 23:42:50.481968 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 23:42:50.485733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 23:42:50.488912 ==
6412 23:42:50.489376
6413 23:42:50.489801
6414 23:42:50.490152 TX Vref Scan disable
6415 23:42:50.492016 == TX Byte 0 ==
6416 23:42:50.495367 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6417 23:42:50.498400 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6418 23:42:50.502088 == TX Byte 1 ==
6419 23:42:50.505799 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6420 23:42:50.508867 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6421 23:42:50.509384 ==
6422 23:42:50.512142 Dram Type= 6, Freq= 0, CH_0, rank 0
6423 23:42:50.518150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6424 23:42:50.518580 ==
6425 23:42:50.518919
6426 23:42:50.519364
6427 23:42:50.519793 TX Vref Scan disable
6428 23:42:50.521694 == TX Byte 0 ==
6429 23:42:50.525104 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6430 23:42:50.528672 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6431 23:42:50.531928 == TX Byte 1 ==
6432 23:42:50.535077 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6433 23:42:50.538712 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6434 23:42:50.539269
6435 23:42:50.541714 [DATLAT]
6436 23:42:50.542136 Freq=400, CH0 RK0
6437 23:42:50.542476
6438 23:42:50.544961 DATLAT Default: 0xf
6439 23:42:50.545481 0, 0xFFFF, sum = 0
6440 23:42:50.548055 1, 0xFFFF, sum = 0
6441 23:42:50.548609 2, 0xFFFF, sum = 0
6442 23:42:50.551892 3, 0xFFFF, sum = 0
6443 23:42:50.552422 4, 0xFFFF, sum = 0
6444 23:42:50.555144 5, 0xFFFF, sum = 0
6445 23:42:50.555623 6, 0xFFFF, sum = 0
6446 23:42:50.557884 7, 0xFFFF, sum = 0
6447 23:42:50.558364 8, 0xFFFF, sum = 0
6448 23:42:50.561345 9, 0xFFFF, sum = 0
6449 23:42:50.561802 10, 0xFFFF, sum = 0
6450 23:42:50.565491 11, 0xFFFF, sum = 0
6451 23:42:50.568429 12, 0xFFFF, sum = 0
6452 23:42:50.568960 13, 0x0, sum = 1
6453 23:42:50.571822 14, 0x0, sum = 2
6454 23:42:50.572356 15, 0x0, sum = 3
6455 23:42:50.572700 16, 0x0, sum = 4
6456 23:42:50.575086 best_step = 14
6457 23:42:50.575608
6458 23:42:50.575949 ==
6459 23:42:50.577974 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 23:42:50.581596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 23:42:50.582132 ==
6462 23:42:50.585108 RX Vref Scan: 1
6463 23:42:50.585662
6464 23:42:50.586005 RX Vref 0 -> 0, step: 1
6465 23:42:50.586323
6466 23:42:50.588119 RX Delay -311 -> 252, step: 8
6467 23:42:50.588543
6468 23:42:50.591866 Set Vref, RX VrefLevel [Byte0]: 56
6469 23:42:50.594549 [Byte1]: 48
6470 23:42:50.600117
6471 23:42:50.600678 Final RX Vref Byte 0 = 56 to rank0
6472 23:42:50.602941 Final RX Vref Byte 1 = 48 to rank0
6473 23:42:50.606544 Final RX Vref Byte 0 = 56 to rank1
6474 23:42:50.610083 Final RX Vref Byte 1 = 48 to rank1==
6475 23:42:50.613176 Dram Type= 6, Freq= 0, CH_0, rank 0
6476 23:42:50.619653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6477 23:42:50.620118 ==
6478 23:42:50.620484 DQS Delay:
6479 23:42:50.623037 DQS0 = 28, DQS1 = 36
6480 23:42:50.623596 DQM Delay:
6481 23:42:50.624011 DQM0 = 11, DQM1 = 12
6482 23:42:50.626312 DQ Delay:
6483 23:42:50.629706 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6484 23:42:50.630290 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6485 23:42:50.632997 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6486 23:42:50.636114 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6487 23:42:50.636574
6488 23:42:50.639160
6489 23:42:50.646287 [DQSOSCAuto] RK0, (LSB)MR18= 0xc5b2, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6490 23:42:50.649734 CH0 RK0: MR19=C0C, MR18=C5B2
6491 23:42:50.656407 CH0_RK0: MR19=0xC0C, MR18=0xC5B2, DQSOSC=385, MR23=63, INC=398, DEC=265
6492 23:42:50.656952 ==
6493 23:42:50.659575 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 23:42:50.662792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 23:42:50.663350 ==
6496 23:42:50.666013 [Gating] SW mode calibration
6497 23:42:50.672914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6498 23:42:50.679601 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6499 23:42:50.682814 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6500 23:42:50.686027 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6501 23:42:50.692970 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6502 23:42:50.695770 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6503 23:42:50.699316 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6504 23:42:50.702579 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6505 23:42:50.709200 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6506 23:42:50.712814 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6507 23:42:50.715853 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6508 23:42:50.718884 Total UI for P1: 0, mck2ui 16
6509 23:42:50.722341 best dqsien dly found for B0: ( 0, 14, 24)
6510 23:42:50.726058 Total UI for P1: 0, mck2ui 16
6511 23:42:50.729497 best dqsien dly found for B1: ( 0, 14, 24)
6512 23:42:50.732229 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6513 23:42:50.736215 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6514 23:42:50.740001
6515 23:42:50.742385 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6516 23:42:50.745419 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6517 23:42:50.749241 [Gating] SW calibration Done
6518 23:42:50.749868 ==
6519 23:42:50.752311 Dram Type= 6, Freq= 0, CH_0, rank 1
6520 23:42:50.755833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6521 23:42:50.756401 ==
6522 23:42:50.756776 RX Vref Scan: 0
6523 23:42:50.759207
6524 23:42:50.759674 RX Vref 0 -> 0, step: 1
6525 23:42:50.760044
6526 23:42:50.762774 RX Delay -410 -> 252, step: 16
6527 23:42:50.766083 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6528 23:42:50.772737 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6529 23:42:50.775957 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6530 23:42:50.778824 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6531 23:42:50.782516 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6532 23:42:50.788764 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6533 23:42:50.792925 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6534 23:42:50.795982 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6535 23:42:50.798574 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6536 23:42:50.805539 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6537 23:42:50.809072 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6538 23:42:50.812079 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6539 23:42:50.815276 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6540 23:42:50.822005 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6541 23:42:50.825187 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6542 23:42:50.828706 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6543 23:42:50.829274 ==
6544 23:42:50.832662 Dram Type= 6, Freq= 0, CH_0, rank 1
6545 23:42:50.835479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6546 23:42:50.838636 ==
6547 23:42:50.839126 DQS Delay:
6548 23:42:50.839502 DQS0 = 27, DQS1 = 35
6549 23:42:50.841961 DQM Delay:
6550 23:42:50.842428 DQM0 = 12, DQM1 = 11
6551 23:42:50.845643 DQ Delay:
6552 23:42:50.846224 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6553 23:42:50.849210 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6554 23:42:50.852243 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6555 23:42:50.855649 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6556 23:42:50.856228
6557 23:42:50.856603
6558 23:42:50.858746 ==
6559 23:42:50.859329 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 23:42:50.865388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 23:42:50.866021 ==
6562 23:42:50.866406
6563 23:42:50.866754
6564 23:42:50.868633 TX Vref Scan disable
6565 23:42:50.869193 == TX Byte 0 ==
6566 23:42:50.872210 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6567 23:42:50.875491 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6568 23:42:50.878589 == TX Byte 1 ==
6569 23:42:50.882213 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6570 23:42:50.885433 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6571 23:42:50.888682 ==
6572 23:42:50.889256 Dram Type= 6, Freq= 0, CH_0, rank 1
6573 23:42:50.895194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6574 23:42:50.895743 ==
6575 23:42:50.896119
6576 23:42:50.896465
6577 23:42:50.898284 TX Vref Scan disable
6578 23:42:50.898754 == TX Byte 0 ==
6579 23:42:50.902128 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6580 23:42:50.908530 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6581 23:42:50.909104 == TX Byte 1 ==
6582 23:42:50.911633 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6583 23:42:50.915301 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6584 23:42:50.918147
6585 23:42:50.918612 [DATLAT]
6586 23:42:50.918983 Freq=400, CH0 RK1
6587 23:42:50.919330
6588 23:42:50.922010 DATLAT Default: 0xe
6589 23:42:50.922581 0, 0xFFFF, sum = 0
6590 23:42:50.925337 1, 0xFFFF, sum = 0
6591 23:42:50.925864 2, 0xFFFF, sum = 0
6592 23:42:50.928469 3, 0xFFFF, sum = 0
6593 23:42:50.929040 4, 0xFFFF, sum = 0
6594 23:42:50.931518 5, 0xFFFF, sum = 0
6595 23:42:50.935239 6, 0xFFFF, sum = 0
6596 23:42:50.935735 7, 0xFFFF, sum = 0
6597 23:42:50.938569 8, 0xFFFF, sum = 0
6598 23:42:50.939035 9, 0xFFFF, sum = 0
6599 23:42:50.942191 10, 0xFFFF, sum = 0
6600 23:42:50.942836 11, 0xFFFF, sum = 0
6601 23:42:50.945097 12, 0xFFFF, sum = 0
6602 23:42:50.945731 13, 0x0, sum = 1
6603 23:42:50.948294 14, 0x0, sum = 2
6604 23:42:50.948763 15, 0x0, sum = 3
6605 23:42:50.952003 16, 0x0, sum = 4
6606 23:42:50.952570 best_step = 14
6607 23:42:50.952940
6608 23:42:50.953279 ==
6609 23:42:50.954956 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 23:42:50.958481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 23:42:50.958948 ==
6612 23:42:50.961468 RX Vref Scan: 0
6613 23:42:50.962062
6614 23:42:50.965396 RX Vref 0 -> 0, step: 1
6615 23:42:50.966004
6616 23:42:50.966371 RX Delay -311 -> 252, step: 8
6617 23:42:50.973749 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6618 23:42:50.976902 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6619 23:42:50.980391 iDelay=217, Bit 2, Center -16 (-239 ~ 208) 448
6620 23:42:50.986543 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6621 23:42:50.990508 iDelay=217, Bit 4, Center -12 (-231 ~ 208) 440
6622 23:42:50.993966 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6623 23:42:50.997458 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6624 23:42:51.000223 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6625 23:42:51.007207 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6626 23:42:51.010398 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6627 23:42:51.013451 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6628 23:42:51.016690 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6629 23:42:51.023423 iDelay=217, Bit 12, Center -16 (-231 ~ 200) 432
6630 23:42:51.026526 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6631 23:42:51.029996 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6632 23:42:51.036643 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6633 23:42:51.037305 ==
6634 23:42:51.040004 Dram Type= 6, Freq= 0, CH_0, rank 1
6635 23:42:51.042981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6636 23:42:51.043605 ==
6637 23:42:51.043988 DQS Delay:
6638 23:42:51.046455 DQS0 = 24, DQS1 = 36
6639 23:42:51.046915 DQM Delay:
6640 23:42:51.049786 DQM0 = 9, DQM1 = 14
6641 23:42:51.050355 DQ Delay:
6642 23:42:51.052765 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6643 23:42:51.056274 DQ4 =12, DQ5 =0, DQ6 =12, DQ7 =16
6644 23:42:51.059404 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6645 23:42:51.062773 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6646 23:42:51.062893
6647 23:42:51.062970
6648 23:42:51.069031 [DQSOSCAuto] RK1, (LSB)MR18= 0xb95a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6649 23:42:51.072439 CH0 RK1: MR19=C0C, MR18=B95A
6650 23:42:51.079320 CH0_RK1: MR19=0xC0C, MR18=0xB95A, DQSOSC=386, MR23=63, INC=396, DEC=264
6651 23:42:51.082765 [RxdqsGatingPostProcess] freq 400
6652 23:42:51.089026 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6653 23:42:51.089239 best DQS0 dly(2T, 0.5T) = (0, 10)
6654 23:42:51.092365 best DQS1 dly(2T, 0.5T) = (0, 10)
6655 23:42:51.095584 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6656 23:42:51.099669 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6657 23:42:51.102458 best DQS0 dly(2T, 0.5T) = (0, 10)
6658 23:42:51.105810 best DQS1 dly(2T, 0.5T) = (0, 10)
6659 23:42:51.109547 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6660 23:42:51.112806 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6661 23:42:51.115892 Pre-setting of DQS Precalculation
6662 23:42:51.122646 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6663 23:42:51.123148 ==
6664 23:42:51.125715 Dram Type= 6, Freq= 0, CH_1, rank 0
6665 23:42:51.129250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6666 23:42:51.129709 ==
6667 23:42:51.135654 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6668 23:42:51.139432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6669 23:42:51.142963 [CA 0] Center 36 (8~64) winsize 57
6670 23:42:51.145983 [CA 1] Center 36 (8~64) winsize 57
6671 23:42:51.149083 [CA 2] Center 36 (8~64) winsize 57
6672 23:42:51.152924 [CA 3] Center 36 (8~64) winsize 57
6673 23:42:51.155726 [CA 4] Center 36 (8~64) winsize 57
6674 23:42:51.159234 [CA 5] Center 36 (8~64) winsize 57
6675 23:42:51.159728
6676 23:42:51.162845 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6677 23:42:51.163506
6678 23:42:51.165918 [CATrainingPosCal] consider 1 rank data
6679 23:42:51.169757 u2DelayCellTimex100 = 270/100 ps
6680 23:42:51.172776 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6681 23:42:51.176025 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6682 23:42:51.179657 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6683 23:42:51.182579 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6684 23:42:51.189349 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6685 23:42:51.192836 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 23:42:51.193356
6687 23:42:51.196115 CA PerBit enable=1, Macro0, CA PI delay=36
6688 23:42:51.196591
6689 23:42:51.199403 [CBTSetCACLKResult] CA Dly = 36
6690 23:42:51.199883 CS Dly: 1 (0~32)
6691 23:42:51.200218 ==
6692 23:42:51.202522 Dram Type= 6, Freq= 0, CH_1, rank 1
6693 23:42:51.209432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6694 23:42:51.210099 ==
6695 23:42:51.212752 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6696 23:42:51.219642 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6697 23:42:51.222579 [CA 0] Center 36 (8~64) winsize 57
6698 23:42:51.225683 [CA 1] Center 36 (8~64) winsize 57
6699 23:42:51.229622 [CA 2] Center 36 (8~64) winsize 57
6700 23:42:51.232586 [CA 3] Center 36 (8~64) winsize 57
6701 23:42:51.236050 [CA 4] Center 36 (8~64) winsize 57
6702 23:42:51.238949 [CA 5] Center 36 (8~64) winsize 57
6703 23:42:51.239621
6704 23:42:51.242497 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6705 23:42:51.242959
6706 23:42:51.245688 [CATrainingPosCal] consider 2 rank data
6707 23:42:51.249247 u2DelayCellTimex100 = 270/100 ps
6708 23:42:51.252988 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6709 23:42:51.255568 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6710 23:42:51.259228 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6711 23:42:51.262135 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6712 23:42:51.266001 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6713 23:42:51.269571 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6714 23:42:51.270181
6715 23:42:51.276053 CA PerBit enable=1, Macro0, CA PI delay=36
6716 23:42:51.276617
6717 23:42:51.276990 [CBTSetCACLKResult] CA Dly = 36
6718 23:42:51.278735 CS Dly: 1 (0~32)
6719 23:42:51.279201
6720 23:42:51.281919 ----->DramcWriteLeveling(PI) begin...
6721 23:42:51.282393 ==
6722 23:42:51.285232 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 23:42:51.289103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 23:42:51.289730 ==
6725 23:42:51.292031 Write leveling (Byte 0): 40 => 8
6726 23:42:51.295743 Write leveling (Byte 1): 40 => 8
6727 23:42:51.298756 DramcWriteLeveling(PI) end<-----
6728 23:42:51.299221
6729 23:42:51.299586 ==
6730 23:42:51.302152 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 23:42:51.305315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 23:42:51.308908 ==
6733 23:42:51.309442 [Gating] SW mode calibration
6734 23:42:51.318624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6735 23:42:51.322144 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6736 23:42:51.325850 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6737 23:42:51.332604 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6738 23:42:51.335510 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6739 23:42:51.338475 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6740 23:42:51.345454 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6741 23:42:51.348492 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6742 23:42:51.351927 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6743 23:42:51.359015 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6744 23:42:51.362043 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6745 23:42:51.365919 Total UI for P1: 0, mck2ui 16
6746 23:42:51.368865 best dqsien dly found for B0: ( 0, 14, 24)
6747 23:42:51.371947 Total UI for P1: 0, mck2ui 16
6748 23:42:51.375330 best dqsien dly found for B1: ( 0, 14, 24)
6749 23:42:51.378485 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6750 23:42:51.381624 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6751 23:42:51.382113
6752 23:42:51.385289 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6753 23:42:51.389040 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6754 23:42:51.391600 [Gating] SW calibration Done
6755 23:42:51.392067 ==
6756 23:42:51.395037 Dram Type= 6, Freq= 0, CH_1, rank 0
6757 23:42:51.398204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6758 23:42:51.402162 ==
6759 23:42:51.402740 RX Vref Scan: 0
6760 23:42:51.403113
6761 23:42:51.405343 RX Vref 0 -> 0, step: 1
6762 23:42:51.405979
6763 23:42:51.408982 RX Delay -410 -> 252, step: 16
6764 23:42:51.412110 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6765 23:42:51.414924 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6766 23:42:51.418483 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6767 23:42:51.424995 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6768 23:42:51.428292 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6769 23:42:51.431739 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6770 23:42:51.434687 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6771 23:42:51.441859 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6772 23:42:51.445241 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6773 23:42:51.448608 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6774 23:42:51.451594 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6775 23:42:51.458328 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6776 23:42:51.461433 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6777 23:42:51.465243 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6778 23:42:51.468375 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6779 23:42:51.474977 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6780 23:42:51.475550 ==
6781 23:42:51.478254 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 23:42:51.481363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 23:42:51.481889 ==
6784 23:42:51.482267 DQS Delay:
6785 23:42:51.484899 DQS0 = 27, DQS1 = 35
6786 23:42:51.485457 DQM Delay:
6787 23:42:51.487645 DQM0 = 10, DQM1 = 13
6788 23:42:51.488114 DQ Delay:
6789 23:42:51.491477 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6790 23:42:51.494506 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6791 23:42:51.497948 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6792 23:42:51.501753 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6793 23:42:51.502317
6794 23:42:51.502689
6795 23:42:51.503034 ==
6796 23:42:51.504876 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 23:42:51.507765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 23:42:51.508295 ==
6799 23:42:51.508669
6800 23:42:51.509014
6801 23:42:51.511907 TX Vref Scan disable
6802 23:42:51.514323 == TX Byte 0 ==
6803 23:42:51.517564 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6804 23:42:51.521418 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6805 23:42:51.524429 == TX Byte 1 ==
6806 23:42:51.527767 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6807 23:42:51.531545 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6808 23:42:51.532105 ==
6809 23:42:51.534552 Dram Type= 6, Freq= 0, CH_1, rank 0
6810 23:42:51.537757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6811 23:42:51.538228 ==
6812 23:42:51.538600
6813 23:42:51.541223
6814 23:42:51.541727 TX Vref Scan disable
6815 23:42:51.544593 == TX Byte 0 ==
6816 23:42:51.548073 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6817 23:42:51.551277 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6818 23:42:51.554718 == TX Byte 1 ==
6819 23:42:51.557904 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6820 23:42:51.560864 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6821 23:42:51.561328
6822 23:42:51.561725 [DATLAT]
6823 23:42:51.564960 Freq=400, CH1 RK0
6824 23:42:51.565522
6825 23:42:51.565943 DATLAT Default: 0xf
6826 23:42:51.567512 0, 0xFFFF, sum = 0
6827 23:42:51.571227 1, 0xFFFF, sum = 0
6828 23:42:51.571801 2, 0xFFFF, sum = 0
6829 23:42:51.574247 3, 0xFFFF, sum = 0
6830 23:42:51.574738 4, 0xFFFF, sum = 0
6831 23:42:51.578030 5, 0xFFFF, sum = 0
6832 23:42:51.578600 6, 0xFFFF, sum = 0
6833 23:42:51.581110 7, 0xFFFF, sum = 0
6834 23:42:51.581762 8, 0xFFFF, sum = 0
6835 23:42:51.584600 9, 0xFFFF, sum = 0
6836 23:42:51.585169 10, 0xFFFF, sum = 0
6837 23:42:51.588061 11, 0xFFFF, sum = 0
6838 23:42:51.588649 12, 0xFFFF, sum = 0
6839 23:42:51.591192 13, 0x0, sum = 1
6840 23:42:51.591668 14, 0x0, sum = 2
6841 23:42:51.594589 15, 0x0, sum = 3
6842 23:42:51.595062 16, 0x0, sum = 4
6843 23:42:51.597476 best_step = 14
6844 23:42:51.598023
6845 23:42:51.598396 ==
6846 23:42:51.600968 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 23:42:51.604970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 23:42:51.605534 ==
6849 23:42:51.606010 RX Vref Scan: 1
6850 23:42:51.608242
6851 23:42:51.608798 RX Vref 0 -> 0, step: 1
6852 23:42:51.609171
6853 23:42:51.611050 RX Delay -311 -> 252, step: 8
6854 23:42:51.611609
6855 23:42:51.614451 Set Vref, RX VrefLevel [Byte0]: 54
6856 23:42:51.617572 [Byte1]: 48
6857 23:42:51.621346
6858 23:42:51.621911 Final RX Vref Byte 0 = 54 to rank0
6859 23:42:51.625003 Final RX Vref Byte 1 = 48 to rank0
6860 23:42:51.628521 Final RX Vref Byte 0 = 54 to rank1
6861 23:42:51.631551 Final RX Vref Byte 1 = 48 to rank1==
6862 23:42:51.634766 Dram Type= 6, Freq= 0, CH_1, rank 0
6863 23:42:51.641415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6864 23:42:51.641925 ==
6865 23:42:51.642290 DQS Delay:
6866 23:42:51.645071 DQS0 = 28, DQS1 = 32
6867 23:42:51.645679 DQM Delay:
6868 23:42:51.646058 DQM0 = 10, DQM1 = 10
6869 23:42:51.647924 DQ Delay:
6870 23:42:51.651158 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6871 23:42:51.654804 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6872 23:42:51.655365 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6873 23:42:51.657789 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6874 23:42:51.661075
6875 23:42:51.661533
6876 23:42:51.668318 [DQSOSCAuto] RK0, (LSB)MR18= 0x87bf, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 392 ps
6877 23:42:51.671765 CH1 RK0: MR19=C0C, MR18=87BF
6878 23:42:51.677969 CH1_RK0: MR19=0xC0C, MR18=0x87BF, DQSOSC=386, MR23=63, INC=396, DEC=264
6879 23:42:51.678537 ==
6880 23:42:51.681310 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 23:42:51.684319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 23:42:51.684785 ==
6883 23:42:51.688183 [Gating] SW mode calibration
6884 23:42:51.694842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6885 23:42:51.697837 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6886 23:42:51.704761 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6887 23:42:51.707968 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6888 23:42:51.711417 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6889 23:42:51.718209 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6890 23:42:51.721421 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6891 23:42:51.724962 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6892 23:42:51.731044 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6893 23:42:51.734625 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6894 23:42:51.738466 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6895 23:42:51.741022 Total UI for P1: 0, mck2ui 16
6896 23:42:51.744691 best dqsien dly found for B0: ( 0, 14, 24)
6897 23:42:51.747846 Total UI for P1: 0, mck2ui 16
6898 23:42:51.751175 best dqsien dly found for B1: ( 0, 14, 24)
6899 23:42:51.754276 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6900 23:42:51.758254 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6901 23:42:51.761297
6902 23:42:51.764888 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6903 23:42:51.767841 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6904 23:42:51.771610 [Gating] SW calibration Done
6905 23:42:51.772173 ==
6906 23:42:51.774596 Dram Type= 6, Freq= 0, CH_1, rank 1
6907 23:42:51.778208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6908 23:42:51.778773 ==
6909 23:42:51.779146 RX Vref Scan: 0
6910 23:42:51.779487
6911 23:42:51.781469 RX Vref 0 -> 0, step: 1
6912 23:42:51.782081
6913 23:42:51.784551 RX Delay -410 -> 252, step: 16
6914 23:42:51.787876 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6915 23:42:51.794146 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6916 23:42:51.798178 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6917 23:42:51.801441 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6918 23:42:51.804398 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6919 23:42:51.808147 iDelay=230, Bit 5, Center 5 (-218 ~ 229) 448
6920 23:42:51.814330 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6921 23:42:51.817567 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6922 23:42:51.821472 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6923 23:42:51.824432 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6924 23:42:51.831354 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6925 23:42:51.833994 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6926 23:42:51.837667 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6927 23:42:51.844238 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6928 23:42:51.847281 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6929 23:42:51.851152 iDelay=230, Bit 15, Center -3 (-234 ~ 229) 464
6930 23:42:51.851619 ==
6931 23:42:51.854322 Dram Type= 6, Freq= 0, CH_1, rank 1
6932 23:42:51.857398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6933 23:42:51.860728 ==
6934 23:42:51.861266 DQS Delay:
6935 23:42:51.861676 DQS0 = 35, DQS1 = 35
6936 23:42:51.864578 DQM Delay:
6937 23:42:51.865040 DQM0 = 20, DQM1 = 14
6938 23:42:51.867426 DQ Delay:
6939 23:42:51.867887 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6940 23:42:51.871119 DQ4 =16, DQ5 =40, DQ6 =32, DQ7 =16
6941 23:42:51.873934 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6942 23:42:51.877396 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =32
6943 23:42:51.877908
6944 23:42:51.878276
6945 23:42:51.880738 ==
6946 23:42:51.883679 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 23:42:51.887446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 23:42:51.888015 ==
6949 23:42:51.888390
6950 23:42:51.888731
6951 23:42:51.890300 TX Vref Scan disable
6952 23:42:51.890764 == TX Byte 0 ==
6953 23:42:51.894024 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6954 23:42:51.900461 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6955 23:42:51.901026 == TX Byte 1 ==
6956 23:42:51.904235 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6957 23:42:51.907473 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6958 23:42:51.910767 ==
6959 23:42:51.913960 Dram Type= 6, Freq= 0, CH_1, rank 1
6960 23:42:51.916910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6961 23:42:51.917380 ==
6962 23:42:51.917805
6963 23:42:51.918154
6964 23:42:51.920617 TX Vref Scan disable
6965 23:42:51.921078 == TX Byte 0 ==
6966 23:42:51.923688 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6967 23:42:51.930265 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6968 23:42:51.930731 == TX Byte 1 ==
6969 23:42:51.933917 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6970 23:42:51.940149 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6971 23:42:51.940692
6972 23:42:51.941061 [DATLAT]
6973 23:42:51.941403 Freq=400, CH1 RK1
6974 23:42:51.941827
6975 23:42:51.943915 DATLAT Default: 0xe
6976 23:42:51.944471 0, 0xFFFF, sum = 0
6977 23:42:51.947331 1, 0xFFFF, sum = 0
6978 23:42:51.947803 2, 0xFFFF, sum = 0
6979 23:42:51.950317 3, 0xFFFF, sum = 0
6980 23:42:51.953877 4, 0xFFFF, sum = 0
6981 23:42:51.954631 5, 0xFFFF, sum = 0
6982 23:42:51.957007 6, 0xFFFF, sum = 0
6983 23:42:51.957615 7, 0xFFFF, sum = 0
6984 23:42:51.960480 8, 0xFFFF, sum = 0
6985 23:42:51.961045 9, 0xFFFF, sum = 0
6986 23:42:51.963642 10, 0xFFFF, sum = 0
6987 23:42:51.964120 11, 0xFFFF, sum = 0
6988 23:42:51.966993 12, 0xFFFF, sum = 0
6989 23:42:51.967461 13, 0x0, sum = 1
6990 23:42:51.970642 14, 0x0, sum = 2
6991 23:42:51.971212 15, 0x0, sum = 3
6992 23:42:51.974005 16, 0x0, sum = 4
6993 23:42:51.974478 best_step = 14
6994 23:42:51.974848
6995 23:42:51.975193 ==
6996 23:42:51.976841 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 23:42:51.980598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 23:42:51.981181 ==
6999 23:42:51.983952 RX Vref Scan: 0
7000 23:42:51.984518
7001 23:42:51.986654 RX Vref 0 -> 0, step: 1
7002 23:42:51.987117
7003 23:42:51.987483 RX Delay -311 -> 252, step: 8
7004 23:42:51.995976 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
7005 23:42:51.999478 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
7006 23:42:52.002529 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
7007 23:42:52.009316 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
7008 23:42:52.012369 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7009 23:42:52.015929 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
7010 23:42:52.018929 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7011 23:42:52.022556 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7012 23:42:52.029229 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
7013 23:42:52.032669 iDelay=217, Bit 9, Center -28 (-247 ~ 192) 440
7014 23:42:52.036141 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7015 23:42:52.038627 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
7016 23:42:52.045431 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7017 23:42:52.048888 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7018 23:42:52.052686 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7019 23:42:52.059196 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7020 23:42:52.059759 ==
7021 23:42:52.061910 Dram Type= 6, Freq= 0, CH_1, rank 1
7022 23:42:52.065402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7023 23:42:52.066021 ==
7024 23:42:52.066395 DQS Delay:
7025 23:42:52.068833 DQS0 = 28, DQS1 = 32
7026 23:42:52.069404 DQM Delay:
7027 23:42:52.072719 DQM0 = 11, DQM1 = 12
7028 23:42:52.073280 DQ Delay:
7029 23:42:52.075427 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7030 23:42:52.078667 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7031 23:42:52.082397 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
7032 23:42:52.085875 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7033 23:42:52.086457
7034 23:42:52.086830
7035 23:42:52.092483 [DQSOSCAuto] RK1, (LSB)MR18= 0xbe50, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 386 ps
7036 23:42:52.095361 CH1 RK1: MR19=C0C, MR18=BE50
7037 23:42:52.102234 CH1_RK1: MR19=0xC0C, MR18=0xBE50, DQSOSC=386, MR23=63, INC=396, DEC=264
7038 23:42:52.105345 [RxdqsGatingPostProcess] freq 400
7039 23:42:52.109037 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7040 23:42:52.112483 best DQS0 dly(2T, 0.5T) = (0, 10)
7041 23:42:52.115356 best DQS1 dly(2T, 0.5T) = (0, 10)
7042 23:42:52.118600 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7043 23:42:52.121921 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7044 23:42:52.125050 best DQS0 dly(2T, 0.5T) = (0, 10)
7045 23:42:52.128322 best DQS1 dly(2T, 0.5T) = (0, 10)
7046 23:42:52.131906 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7047 23:42:52.135661 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7048 23:42:52.138378 Pre-setting of DQS Precalculation
7049 23:42:52.141952 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7050 23:42:52.151851 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7051 23:42:52.158289 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7052 23:42:52.158855
7053 23:42:52.159227
7054 23:42:52.162128 [Calibration Summary] 800 Mbps
7055 23:42:52.162636 CH 0, Rank 0
7056 23:42:52.165201 SW Impedance : PASS
7057 23:42:52.165816 DUTY Scan : NO K
7058 23:42:52.168400 ZQ Calibration : PASS
7059 23:42:52.171946 Jitter Meter : NO K
7060 23:42:52.172508 CBT Training : PASS
7061 23:42:52.175473 Write leveling : PASS
7062 23:42:52.179205 RX DQS gating : PASS
7063 23:42:52.179772 RX DQ/DQS(RDDQC) : PASS
7064 23:42:52.182076 TX DQ/DQS : PASS
7065 23:42:52.185412 RX DATLAT : PASS
7066 23:42:52.186020 RX DQ/DQS(Engine): PASS
7067 23:42:52.188122 TX OE : NO K
7068 23:42:52.188590 All Pass.
7069 23:42:52.188960
7070 23:42:52.192358 CH 0, Rank 1
7071 23:42:52.193007 SW Impedance : PASS
7072 23:42:52.194724 DUTY Scan : NO K
7073 23:42:52.198138 ZQ Calibration : PASS
7074 23:42:52.198603 Jitter Meter : NO K
7075 23:42:52.201499 CBT Training : PASS
7076 23:42:52.202131 Write leveling : NO K
7077 23:42:52.204936 RX DQS gating : PASS
7078 23:42:52.208301 RX DQ/DQS(RDDQC) : PASS
7079 23:42:52.208860 TX DQ/DQS : PASS
7080 23:42:52.211583 RX DATLAT : PASS
7081 23:42:52.214804 RX DQ/DQS(Engine): PASS
7082 23:42:52.215274 TX OE : NO K
7083 23:42:52.218013 All Pass.
7084 23:42:52.218549
7085 23:42:52.218921 CH 1, Rank 0
7086 23:42:52.221329 SW Impedance : PASS
7087 23:42:52.221842 DUTY Scan : NO K
7088 23:42:52.224659 ZQ Calibration : PASS
7089 23:42:52.228489 Jitter Meter : NO K
7090 23:42:52.229059 CBT Training : PASS
7091 23:42:52.231192 Write leveling : PASS
7092 23:42:52.235066 RX DQS gating : PASS
7093 23:42:52.235533 RX DQ/DQS(RDDQC) : PASS
7094 23:42:52.238340 TX DQ/DQS : PASS
7095 23:42:52.241023 RX DATLAT : PASS
7096 23:42:52.241490 RX DQ/DQS(Engine): PASS
7097 23:42:52.244822 TX OE : NO K
7098 23:42:52.245288 All Pass.
7099 23:42:52.245703
7100 23:42:52.247920 CH 1, Rank 1
7101 23:42:52.248388 SW Impedance : PASS
7102 23:42:52.251628 DUTY Scan : NO K
7103 23:42:52.254427 ZQ Calibration : PASS
7104 23:42:52.254895 Jitter Meter : NO K
7105 23:42:52.258116 CBT Training : PASS
7106 23:42:52.258537 Write leveling : NO K
7107 23:42:52.261998 RX DQS gating : PASS
7108 23:42:52.264547 RX DQ/DQS(RDDQC) : PASS
7109 23:42:52.265070 TX DQ/DQS : PASS
7110 23:42:52.268151 RX DATLAT : PASS
7111 23:42:52.271225 RX DQ/DQS(Engine): PASS
7112 23:42:52.271739 TX OE : NO K
7113 23:42:52.275292 All Pass.
7114 23:42:52.275812
7115 23:42:52.276152 DramC Write-DBI off
7116 23:42:52.278187 PER_BANK_REFRESH: Hybrid Mode
7117 23:42:52.278608 TX_TRACKING: ON
7118 23:42:52.288041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7119 23:42:52.291321 [FAST_K] Save calibration result to emmc
7120 23:42:52.294378 dramc_set_vcore_voltage set vcore to 725000
7121 23:42:52.297806 Read voltage for 1600, 0
7122 23:42:52.298231 Vio18 = 0
7123 23:42:52.300883 Vcore = 725000
7124 23:42:52.301324 Vdram = 0
7125 23:42:52.301752 Vddq = 0
7126 23:42:52.304191 Vmddr = 0
7127 23:42:52.308250 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7128 23:42:52.314501 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7129 23:42:52.314935 MEM_TYPE=3, freq_sel=13
7130 23:42:52.317573 sv_algorithm_assistance_LP4_3733
7131 23:42:52.324151 ============ PULL DRAM RESETB DOWN ============
7132 23:42:52.327614 ========== PULL DRAM RESETB DOWN end =========
7133 23:42:52.331146 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7134 23:42:52.334716 ===================================
7135 23:42:52.337510 LPDDR4 DRAM CONFIGURATION
7136 23:42:52.340621 ===================================
7137 23:42:52.341050 EX_ROW_EN[0] = 0x0
7138 23:42:52.344486 EX_ROW_EN[1] = 0x0
7139 23:42:52.347506 LP4Y_EN = 0x0
7140 23:42:52.348201 WORK_FSP = 0x1
7141 23:42:52.350800 WL = 0x5
7142 23:42:52.351272 RL = 0x5
7143 23:42:52.354339 BL = 0x2
7144 23:42:52.354940 RPST = 0x0
7145 23:42:52.357728 RD_PRE = 0x0
7146 23:42:52.358199 WR_PRE = 0x1
7147 23:42:52.360612 WR_PST = 0x1
7148 23:42:52.361121 DBI_WR = 0x0
7149 23:42:52.364105 DBI_RD = 0x0
7150 23:42:52.364533 OTF = 0x1
7151 23:42:52.367506 ===================================
7152 23:42:52.371329 ===================================
7153 23:42:52.373977 ANA top config
7154 23:42:52.377739 ===================================
7155 23:42:52.381041 DLL_ASYNC_EN = 0
7156 23:42:52.381562 ALL_SLAVE_EN = 0
7157 23:42:52.384333 NEW_RANK_MODE = 1
7158 23:42:52.387546 DLL_IDLE_MODE = 1
7159 23:42:52.390789 LP45_APHY_COMB_EN = 1
7160 23:42:52.391310 TX_ODT_DIS = 0
7161 23:42:52.394130 NEW_8X_MODE = 1
7162 23:42:52.397537 ===================================
7163 23:42:52.400791 ===================================
7164 23:42:52.404071 data_rate = 3200
7165 23:42:52.407687 CKR = 1
7166 23:42:52.410943 DQ_P2S_RATIO = 8
7167 23:42:52.414214 ===================================
7168 23:42:52.417533 CA_P2S_RATIO = 8
7169 23:42:52.418004 DQ_CA_OPEN = 0
7170 23:42:52.420443 DQ_SEMI_OPEN = 0
7171 23:42:52.423735 CA_SEMI_OPEN = 0
7172 23:42:52.427279 CA_FULL_RATE = 0
7173 23:42:52.430378 DQ_CKDIV4_EN = 0
7174 23:42:52.430826 CA_CKDIV4_EN = 0
7175 23:42:52.433876 CA_PREDIV_EN = 0
7176 23:42:52.437135 PH8_DLY = 12
7177 23:42:52.440660 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7178 23:42:52.443588 DQ_AAMCK_DIV = 4
7179 23:42:52.447286 CA_AAMCK_DIV = 4
7180 23:42:52.447740 CA_ADMCK_DIV = 4
7181 23:42:52.450671 DQ_TRACK_CA_EN = 0
7182 23:42:52.453916 CA_PICK = 1600
7183 23:42:52.457545 CA_MCKIO = 1600
7184 23:42:52.460424 MCKIO_SEMI = 0
7185 23:42:52.464010 PLL_FREQ = 3068
7186 23:42:52.466953 DQ_UI_PI_RATIO = 32
7187 23:42:52.470229 CA_UI_PI_RATIO = 0
7188 23:42:52.473853 ===================================
7189 23:42:52.477160 ===================================
7190 23:42:52.477731 memory_type:LPDDR4
7191 23:42:52.480645 GP_NUM : 10
7192 23:42:52.483636 SRAM_EN : 1
7193 23:42:52.484061 MD32_EN : 0
7194 23:42:52.487107 ===================================
7195 23:42:52.490384 [ANA_INIT] >>>>>>>>>>>>>>
7196 23:42:52.493723 <<<<<< [CONFIGURE PHASE]: ANA_TX
7197 23:42:52.496848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7198 23:42:52.499987 ===================================
7199 23:42:52.503694 data_rate = 3200,PCW = 0X7600
7200 23:42:52.506818 ===================================
7201 23:42:52.510179 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7202 23:42:52.514078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7203 23:42:52.520110 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7204 23:42:52.523377 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7205 23:42:52.527158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7206 23:42:52.530313 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7207 23:42:52.533547 [ANA_INIT] flow start
7208 23:42:52.537129 [ANA_INIT] PLL >>>>>>>>
7209 23:42:52.537787 [ANA_INIT] PLL <<<<<<<<
7210 23:42:52.540402 [ANA_INIT] MIDPI >>>>>>>>
7211 23:42:52.543294 [ANA_INIT] MIDPI <<<<<<<<
7212 23:42:52.543720 [ANA_INIT] DLL >>>>>>>>
7213 23:42:52.546770 [ANA_INIT] DLL <<<<<<<<
7214 23:42:52.549703 [ANA_INIT] flow end
7215 23:42:52.553452 ============ LP4 DIFF to SE enter ============
7216 23:42:52.556483 ============ LP4 DIFF to SE exit ============
7217 23:42:52.560120 [ANA_INIT] <<<<<<<<<<<<<
7218 23:42:52.563530 [Flow] Enable top DCM control >>>>>
7219 23:42:52.566728 [Flow] Enable top DCM control <<<<<
7220 23:42:52.570207 Enable DLL master slave shuffle
7221 23:42:52.573177 ==============================================================
7222 23:42:52.576780 Gating Mode config
7223 23:42:52.583819 ==============================================================
7224 23:42:52.584392 Config description:
7225 23:42:52.593985 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7226 23:42:52.599733 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7227 23:42:52.603329 SELPH_MODE 0: By rank 1: By Phase
7228 23:42:52.610272 ==============================================================
7229 23:42:52.613926 GAT_TRACK_EN = 1
7230 23:42:52.616681 RX_GATING_MODE = 2
7231 23:42:52.620012 RX_GATING_TRACK_MODE = 2
7232 23:42:52.623321 SELPH_MODE = 1
7233 23:42:52.626581 PICG_EARLY_EN = 1
7234 23:42:52.630028 VALID_LAT_VALUE = 1
7235 23:42:52.633663 ==============================================================
7236 23:42:52.636924 Enter into Gating configuration >>>>
7237 23:42:52.640131 Exit from Gating configuration <<<<
7238 23:42:52.642855 Enter into DVFS_PRE_config >>>>>
7239 23:42:52.656240 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7240 23:42:52.659624 Exit from DVFS_PRE_config <<<<<
7241 23:42:52.660181 Enter into PICG configuration >>>>
7242 23:42:52.662781 Exit from PICG configuration <<<<
7243 23:42:52.666015 [RX_INPUT] configuration >>>>>
7244 23:42:52.669572 [RX_INPUT] configuration <<<<<
7245 23:42:52.676182 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7246 23:42:52.679160 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7247 23:42:52.685726 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7248 23:42:52.692566 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7249 23:42:52.699171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7250 23:42:52.706293 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7251 23:42:52.708836 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7252 23:42:52.712658 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7253 23:42:52.719030 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7254 23:42:52.722395 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7255 23:42:52.726197 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7256 23:42:52.729421 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7257 23:42:52.732757 ===================================
7258 23:42:52.735387 LPDDR4 DRAM CONFIGURATION
7259 23:42:52.739003 ===================================
7260 23:42:52.742155 EX_ROW_EN[0] = 0x0
7261 23:42:52.742715 EX_ROW_EN[1] = 0x0
7262 23:42:52.745463 LP4Y_EN = 0x0
7263 23:42:52.745985 WORK_FSP = 0x1
7264 23:42:52.748958 WL = 0x5
7265 23:42:52.749517 RL = 0x5
7266 23:42:52.752042 BL = 0x2
7267 23:42:52.752621 RPST = 0x0
7268 23:42:52.755265 RD_PRE = 0x0
7269 23:42:52.755823 WR_PRE = 0x1
7270 23:42:52.759282 WR_PST = 0x1
7271 23:42:52.759847 DBI_WR = 0x0
7272 23:42:52.761800 DBI_RD = 0x0
7273 23:42:52.765328 OTF = 0x1
7274 23:42:52.768715 ===================================
7275 23:42:52.772478 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7276 23:42:52.775472 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7277 23:42:52.778449 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7278 23:42:52.782265 ===================================
7279 23:42:52.785272 LPDDR4 DRAM CONFIGURATION
7280 23:42:52.788855 ===================================
7281 23:42:52.791940 EX_ROW_EN[0] = 0x10
7282 23:42:52.792511 EX_ROW_EN[1] = 0x0
7283 23:42:52.794991 LP4Y_EN = 0x0
7284 23:42:52.795466 WORK_FSP = 0x1
7285 23:42:52.798214 WL = 0x5
7286 23:42:52.798680 RL = 0x5
7287 23:42:52.801541 BL = 0x2
7288 23:42:52.802056 RPST = 0x0
7289 23:42:52.806018 RD_PRE = 0x0
7290 23:42:52.806574 WR_PRE = 0x1
7291 23:42:52.808952 WR_PST = 0x1
7292 23:42:52.809511 DBI_WR = 0x0
7293 23:42:52.812376 DBI_RD = 0x0
7294 23:42:52.812947 OTF = 0x1
7295 23:42:52.815475 ===================================
7296 23:42:52.821548 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7297 23:42:52.822253 ==
7298 23:42:52.825638 Dram Type= 6, Freq= 0, CH_0, rank 0
7299 23:42:52.831939 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 23:42:52.832501 ==
7301 23:42:52.832877 [Duty_Offset_Calibration]
7302 23:42:52.835281 B0:2 B1:1 CA:1
7303 23:42:52.835747
7304 23:42:52.838676 [DutyScan_Calibration_Flow] k_type=0
7305 23:42:52.847719
7306 23:42:52.848275 ==CLK 0==
7307 23:42:52.851062 Final CLK duty delay cell = 0
7308 23:42:52.854197 [0] MAX Duty = 5156%(X100), DQS PI = 22
7309 23:42:52.858381 [0] MIN Duty = 4907%(X100), DQS PI = 0
7310 23:42:52.858942 [0] AVG Duty = 5031%(X100)
7311 23:42:52.860887
7312 23:42:52.863883 CH0 CLK Duty spec in!! Max-Min= 249%
7313 23:42:52.867938 [DutyScan_Calibration_Flow] ====Done====
7314 23:42:52.868504
7315 23:42:52.870453 [DutyScan_Calibration_Flow] k_type=1
7316 23:42:52.886877
7317 23:42:52.887436 ==DQS 0 ==
7318 23:42:52.889883 Final DQS duty delay cell = -4
7319 23:42:52.893361 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7320 23:42:52.896660 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7321 23:42:52.900213 [-4] AVG Duty = 4891%(X100)
7322 23:42:52.900681
7323 23:42:52.901053 ==DQS 1 ==
7324 23:42:52.902975 Final DQS duty delay cell = 0
7325 23:42:52.906592 [0] MAX Duty = 5218%(X100), DQS PI = 22
7326 23:42:52.909820 [0] MIN Duty = 5031%(X100), DQS PI = 30
7327 23:42:52.913202 [0] AVG Duty = 5124%(X100)
7328 23:42:52.913689
7329 23:42:52.916379 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7330 23:42:52.916848
7331 23:42:52.920104 CH0 DQS 1 Duty spec in!! Max-Min= 187%
7332 23:42:52.923403 [DutyScan_Calibration_Flow] ====Done====
7333 23:42:52.923881
7334 23:42:52.926400 [DutyScan_Calibration_Flow] k_type=3
7335 23:42:52.943408
7336 23:42:52.943988 ==DQM 0 ==
7337 23:42:52.946565 Final DQM duty delay cell = 0
7338 23:42:52.950135 [0] MAX Duty = 5187%(X100), DQS PI = 26
7339 23:42:52.953264 [0] MIN Duty = 4876%(X100), DQS PI = 60
7340 23:42:52.956962 [0] AVG Duty = 5031%(X100)
7341 23:42:52.957524
7342 23:42:52.957991 ==DQM 1 ==
7343 23:42:52.960173 Final DQM duty delay cell = -4
7344 23:42:52.963090 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7345 23:42:52.966635 [-4] MIN Duty = 4813%(X100), DQS PI = 14
7346 23:42:52.970430 [-4] AVG Duty = 4906%(X100)
7347 23:42:52.970994
7348 23:42:52.973500 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7349 23:42:52.974122
7350 23:42:52.976890 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7351 23:42:52.979727 [DutyScan_Calibration_Flow] ====Done====
7352 23:42:52.980289
7353 23:42:52.983096 [DutyScan_Calibration_Flow] k_type=2
7354 23:42:53.001447
7355 23:42:53.002062 ==DQ 0 ==
7356 23:42:53.004204 Final DQ duty delay cell = 0
7357 23:42:53.007436 [0] MAX Duty = 5062%(X100), DQS PI = 24
7358 23:42:53.011408 [0] MIN Duty = 4907%(X100), DQS PI = 0
7359 23:42:53.011992 [0] AVG Duty = 4984%(X100)
7360 23:42:53.014034
7361 23:42:53.014495 ==DQ 1 ==
7362 23:42:53.017551 Final DQ duty delay cell = 0
7363 23:42:53.020881 [0] MAX Duty = 5125%(X100), DQS PI = 6
7364 23:42:53.023924 [0] MIN Duty = 4907%(X100), DQS PI = 34
7365 23:42:53.024389 [0] AVG Duty = 5016%(X100)
7366 23:42:53.024755
7367 23:42:53.027623 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7368 23:42:53.028088
7369 23:42:53.033967 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7370 23:42:53.037748 [DutyScan_Calibration_Flow] ====Done====
7371 23:42:53.038483 ==
7372 23:42:53.041062 Dram Type= 6, Freq= 0, CH_1, rank 0
7373 23:42:53.044106 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7374 23:42:53.044762 ==
7375 23:42:53.047532 [Duty_Offset_Calibration]
7376 23:42:53.047994 B0:1 B1:0 CA:0
7377 23:42:53.048356
7378 23:42:53.050686 [DutyScan_Calibration_Flow] k_type=0
7379 23:42:53.060089
7380 23:42:53.060782 ==CLK 0==
7381 23:42:53.063407 Final CLK duty delay cell = -4
7382 23:42:53.066585 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7383 23:42:53.070547 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7384 23:42:53.073277 [-4] AVG Duty = 4906%(X100)
7385 23:42:53.073776
7386 23:42:53.076838 CH1 CLK Duty spec in!! Max-Min= 125%
7387 23:42:53.080474 [DutyScan_Calibration_Flow] ====Done====
7388 23:42:53.081039
7389 23:42:53.083711 [DutyScan_Calibration_Flow] k_type=1
7390 23:42:53.100245
7391 23:42:53.100966 ==DQS 0 ==
7392 23:42:53.103792 Final DQS duty delay cell = 0
7393 23:42:53.107281 [0] MAX Duty = 5125%(X100), DQS PI = 24
7394 23:42:53.110509 [0] MIN Duty = 4844%(X100), DQS PI = 48
7395 23:42:53.111067 [0] AVG Duty = 4984%(X100)
7396 23:42:53.113725
7397 23:42:53.114284 ==DQS 1 ==
7398 23:42:53.116956 Final DQS duty delay cell = 0
7399 23:42:53.120539 [0] MAX Duty = 5249%(X100), DQS PI = 16
7400 23:42:53.124281 [0] MIN Duty = 4969%(X100), DQS PI = 6
7401 23:42:53.124831 [0] AVG Duty = 5109%(X100)
7402 23:42:53.126900
7403 23:42:53.129872 CH1 DQS 0 Duty spec in!! Max-Min= 281%
7404 23:42:53.130293
7405 23:42:53.133844 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7406 23:42:53.137203 [DutyScan_Calibration_Flow] ====Done====
7407 23:42:53.137803
7408 23:42:53.140082 [DutyScan_Calibration_Flow] k_type=3
7409 23:42:53.157030
7410 23:42:53.157707 ==DQM 0 ==
7411 23:42:53.160474 Final DQM duty delay cell = 0
7412 23:42:53.163825 [0] MAX Duty = 5218%(X100), DQS PI = 18
7413 23:42:53.167841 [0] MIN Duty = 4969%(X100), DQS PI = 48
7414 23:42:53.170352 [0] AVG Duty = 5093%(X100)
7415 23:42:53.170977
7416 23:42:53.171352 ==DQM 1 ==
7417 23:42:53.173745 Final DQM duty delay cell = 0
7418 23:42:53.177081 [0] MAX Duty = 5093%(X100), DQS PI = 16
7419 23:42:53.180492 [0] MIN Duty = 4907%(X100), DQS PI = 52
7420 23:42:53.183825 [0] AVG Duty = 5000%(X100)
7421 23:42:53.184382
7422 23:42:53.186915 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7423 23:42:53.187428
7424 23:42:53.190341 CH1 DQM 1 Duty spec in!! Max-Min= 186%
7425 23:42:53.193660 [DutyScan_Calibration_Flow] ====Done====
7426 23:42:53.194257
7427 23:42:53.197694 [DutyScan_Calibration_Flow] k_type=2
7428 23:42:53.213370
7429 23:42:53.213976 ==DQ 0 ==
7430 23:42:53.216971 Final DQ duty delay cell = -4
7431 23:42:53.219995 [-4] MAX Duty = 5031%(X100), DQS PI = 8
7432 23:42:53.223206 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7433 23:42:53.226761 [-4] AVG Duty = 4953%(X100)
7434 23:42:53.227259
7435 23:42:53.227624 ==DQ 1 ==
7436 23:42:53.229930 Final DQ duty delay cell = 0
7437 23:42:53.233754 [0] MAX Duty = 5124%(X100), DQS PI = 18
7438 23:42:53.236697 [0] MIN Duty = 4938%(X100), DQS PI = 8
7439 23:42:53.237271 [0] AVG Duty = 5031%(X100)
7440 23:42:53.239674
7441 23:42:53.243271 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7442 23:42:53.243838
7443 23:42:53.246941 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7444 23:42:53.250291 [DutyScan_Calibration_Flow] ====Done====
7445 23:42:53.253356 nWR fixed to 30
7446 23:42:53.253976 [ModeRegInit_LP4] CH0 RK0
7447 23:42:53.256227 [ModeRegInit_LP4] CH0 RK1
7448 23:42:53.259696 [ModeRegInit_LP4] CH1 RK0
7449 23:42:53.262933 [ModeRegInit_LP4] CH1 RK1
7450 23:42:53.263497 match AC timing 5
7451 23:42:53.270177 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7452 23:42:53.273672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7453 23:42:53.276683 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7454 23:42:53.283315 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7455 23:42:53.286082 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7456 23:42:53.286546 [MiockJmeterHQA]
7457 23:42:53.286911
7458 23:42:53.289731 [DramcMiockJmeter] u1RxGatingPI = 0
7459 23:42:53.292869 0 : 4252, 4027
7460 23:42:53.293377 4 : 4363, 4137
7461 23:42:53.295957 8 : 4253, 4027
7462 23:42:53.296426 12 : 4253, 4026
7463 23:42:53.296802 16 : 4365, 4140
7464 23:42:53.300041 20 : 4252, 4027
7465 23:42:53.300611 24 : 4253, 4027
7466 23:42:53.303178 28 : 4252, 4027
7467 23:42:53.303769 32 : 4363, 4137
7468 23:42:53.306221 36 : 4364, 4137
7469 23:42:53.306690 40 : 4252, 4027
7470 23:42:53.309728 44 : 4253, 4027
7471 23:42:53.310311 48 : 4250, 4027
7472 23:42:53.310695 52 : 4250, 4027
7473 23:42:53.312684 56 : 4252, 4029
7474 23:42:53.313155 60 : 4361, 4138
7475 23:42:53.316091 64 : 4250, 4027
7476 23:42:53.316666 68 : 4249, 4027
7477 23:42:53.319673 72 : 4252, 4027
7478 23:42:53.320145 76 : 4252, 4030
7479 23:42:53.320520 80 : 4249, 4027
7480 23:42:53.323036 84 : 4360, 4138
7481 23:42:53.323507 88 : 4361, 92
7482 23:42:53.326348 92 : 4250, 0
7483 23:42:53.326817 96 : 4252, 0
7484 23:42:53.327191 100 : 4363, 0
7485 23:42:53.329843 104 : 4250, 0
7486 23:42:53.330417 108 : 4250, 0
7487 23:42:53.333118 112 : 4249, 0
7488 23:42:53.333737 116 : 4250, 0
7489 23:42:53.334119 120 : 4253, 0
7490 23:42:53.336702 124 : 4250, 0
7491 23:42:53.337281 128 : 4250, 0
7492 23:42:53.339187 132 : 4253, 0
7493 23:42:53.339675 136 : 4250, 0
7494 23:42:53.340052 140 : 4252, 0
7495 23:42:53.343052 144 : 4250, 0
7496 23:42:53.343529 148 : 4252, 0
7497 23:42:53.343909 152 : 4250, 0
7498 23:42:53.346669 156 : 4250, 0
7499 23:42:53.347482 160 : 4253, 0
7500 23:42:53.349527 164 : 4252, 0
7501 23:42:53.350153 168 : 4361, 0
7502 23:42:53.350534 172 : 4250, 0
7503 23:42:53.352555 176 : 4252, 0
7504 23:42:53.353019 180 : 4252, 0
7505 23:42:53.356119 184 : 4250, 0
7506 23:42:53.356623 188 : 4252, 0
7507 23:42:53.357119 192 : 4252, 0
7508 23:42:53.359478 196 : 4250, 0
7509 23:42:53.360060 200 : 4252, 0
7510 23:42:53.362384 204 : 4360, 1169
7511 23:42:53.362874 208 : 4363, 4078
7512 23:42:53.366320 212 : 4248, 4024
7513 23:42:53.366905 216 : 4361, 4137
7514 23:42:53.369319 220 : 4361, 4138
7515 23:42:53.369941 224 : 4250, 4027
7516 23:42:53.370441 228 : 4250, 4027
7517 23:42:53.372754 232 : 4363, 4140
7518 23:42:53.373335 236 : 4250, 4026
7519 23:42:53.376102 240 : 4252, 4029
7520 23:42:53.376684 244 : 4250, 4027
7521 23:42:53.379771 248 : 4253, 4029
7522 23:42:53.380360 252 : 4250, 4026
7523 23:42:53.383114 256 : 4250, 4027
7524 23:42:53.383697 260 : 4363, 4138
7525 23:42:53.385937 264 : 4250, 4027
7526 23:42:53.386422 268 : 4250, 4026
7527 23:42:53.389891 272 : 4361, 4137
7528 23:42:53.390476 276 : 4250, 4027
7529 23:42:53.392657 280 : 4250, 4027
7530 23:42:53.393237 284 : 4363, 4140
7531 23:42:53.393885 288 : 4250, 4026
7532 23:42:53.395983 292 : 4250, 4027
7533 23:42:53.396452 296 : 4250, 4027
7534 23:42:53.399590 300 : 4253, 4029
7535 23:42:53.400156 304 : 4250, 4027
7536 23:42:53.402747 308 : 4250, 3970
7537 23:42:53.403319 312 : 4363, 2287
7538 23:42:53.406072 316 : 4250, 3
7539 23:42:53.406637
7540 23:42:53.407010 MIOCK jitter meter ch=0
7541 23:42:53.407354
7542 23:42:53.409266 1T = (316-88) = 228 dly cells
7543 23:42:53.415982 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 285/100 ps
7544 23:42:53.416541 ==
7545 23:42:53.419128 Dram Type= 6, Freq= 0, CH_0, rank 0
7546 23:42:53.422445 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7547 23:42:53.422914 ==
7548 23:42:53.429257 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7549 23:42:53.432354 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7550 23:42:53.435588 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7551 23:42:53.442175 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7552 23:42:53.452291 [CA 0] Center 43 (13~74) winsize 62
7553 23:42:53.455440 [CA 1] Center 43 (13~74) winsize 62
7554 23:42:53.458742 [CA 2] Center 38 (9~68) winsize 60
7555 23:42:53.462315 [CA 3] Center 38 (8~68) winsize 61
7556 23:42:53.465617 [CA 4] Center 37 (7~67) winsize 61
7557 23:42:53.468954 [CA 5] Center 36 (7~65) winsize 59
7558 23:42:53.469510
7559 23:42:53.471822 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7560 23:42:53.472287
7561 23:42:53.475258 [CATrainingPosCal] consider 1 rank data
7562 23:42:53.478788 u2DelayCellTimex100 = 285/100 ps
7563 23:42:53.482070 CA0 delay=43 (13~74),Diff = 7 PI (23 cell)
7564 23:42:53.488913 CA1 delay=43 (13~74),Diff = 7 PI (23 cell)
7565 23:42:53.491985 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
7566 23:42:53.495314 CA3 delay=38 (8~68),Diff = 2 PI (6 cell)
7567 23:42:53.499091 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
7568 23:42:53.502307 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7569 23:42:53.502770
7570 23:42:53.505396 CA PerBit enable=1, Macro0, CA PI delay=36
7571 23:42:53.505925
7572 23:42:53.508516 [CBTSetCACLKResult] CA Dly = 36
7573 23:42:53.508933 CS Dly: 9 (0~40)
7574 23:42:53.515353 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7575 23:42:53.519418 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7576 23:42:53.519989 ==
7577 23:42:53.523206 Dram Type= 6, Freq= 0, CH_0, rank 1
7578 23:42:53.525487 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7579 23:42:53.526009 ==
7580 23:42:53.532038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7581 23:42:53.535800 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7582 23:42:53.542196 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7583 23:42:53.545682 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7584 23:42:53.555923 [CA 0] Center 42 (12~73) winsize 62
7585 23:42:53.558748 [CA 1] Center 42 (12~73) winsize 62
7586 23:42:53.561774 [CA 2] Center 37 (8~67) winsize 60
7587 23:42:53.565688 [CA 3] Center 37 (8~67) winsize 60
7588 23:42:53.568804 [CA 4] Center 35 (6~65) winsize 60
7589 23:42:53.571728 [CA 5] Center 35 (5~65) winsize 61
7590 23:42:53.572337
7591 23:42:53.575076 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7592 23:42:53.575545
7593 23:42:53.578656 [CATrainingPosCal] consider 2 rank data
7594 23:42:53.582213 u2DelayCellTimex100 = 285/100 ps
7595 23:42:53.585447 CA0 delay=43 (13~73),Diff = 7 PI (23 cell)
7596 23:42:53.591805 CA1 delay=43 (13~73),Diff = 7 PI (23 cell)
7597 23:42:53.594826 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
7598 23:42:53.598603 CA3 delay=37 (8~67),Diff = 1 PI (3 cell)
7599 23:42:53.601797 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7600 23:42:53.604795 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7601 23:42:53.605450
7602 23:42:53.607903 CA PerBit enable=1, Macro0, CA PI delay=36
7603 23:42:53.608529
7604 23:42:53.611121 [CBTSetCACLKResult] CA Dly = 36
7605 23:42:53.614725 CS Dly: 10 (0~42)
7606 23:42:53.618197 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7607 23:42:53.621254 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7608 23:42:53.621815
7609 23:42:53.624703 ----->DramcWriteLeveling(PI) begin...
7610 23:42:53.625147 ==
7611 23:42:53.627785 Dram Type= 6, Freq= 0, CH_0, rank 0
7612 23:42:53.634815 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7613 23:42:53.635355 ==
7614 23:42:53.638092 Write leveling (Byte 0): 38 => 38
7615 23:42:53.640916 Write leveling (Byte 1): 28 => 28
7616 23:42:53.641406 DramcWriteLeveling(PI) end<-----
7617 23:42:53.641892
7618 23:42:53.644413 ==
7619 23:42:53.648182 Dram Type= 6, Freq= 0, CH_0, rank 0
7620 23:42:53.650888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7621 23:42:53.651330 ==
7622 23:42:53.654587 [Gating] SW mode calibration
7623 23:42:53.661051 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7624 23:42:53.663989 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7625 23:42:53.670697 1 4 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7626 23:42:53.674201 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7627 23:42:53.677815 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7628 23:42:53.684768 1 4 12 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
7629 23:42:53.687442 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7630 23:42:53.690999 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7631 23:42:53.697365 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7632 23:42:53.700829 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7633 23:42:53.704716 1 5 0 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7634 23:42:53.711249 1 5 4 | B1->B0 | 3434 3636 | 1 1 | (1 1) (0 0)
7635 23:42:53.714349 1 5 8 | B1->B0 | 3434 3231 | 1 1 | (1 1) (1 1)
7636 23:42:53.717723 1 5 12 | B1->B0 | 3434 2525 | 1 0 | (1 1) (0 0)
7637 23:42:53.724268 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7638 23:42:53.727793 1 5 20 | B1->B0 | 2323 2727 | 0 0 | (1 0) (0 0)
7639 23:42:53.730972 1 5 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7640 23:42:53.737630 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7641 23:42:53.740714 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7642 23:42:53.743971 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7643 23:42:53.747167 1 6 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
7644 23:42:53.754264 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7645 23:42:53.757686 1 6 16 | B1->B0 | 2828 4646 | 0 0 | (0 0) (0 0)
7646 23:42:53.760933 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7647 23:42:53.767411 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7648 23:42:53.770918 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 23:42:53.774097 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7650 23:42:53.780697 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7651 23:42:53.784241 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7652 23:42:53.787426 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7653 23:42:53.794283 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7654 23:42:53.797155 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7655 23:42:53.801093 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 23:42:53.807224 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 23:42:53.811038 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7658 23:42:53.814200 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7659 23:42:53.820800 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7660 23:42:53.823942 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7661 23:42:53.827215 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7662 23:42:53.833929 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7663 23:42:53.837753 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7664 23:42:53.841262 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7665 23:42:53.847380 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7666 23:42:53.850832 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7667 23:42:53.854058 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7668 23:42:53.860489 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7669 23:42:53.863725 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7670 23:42:53.867788 Total UI for P1: 0, mck2ui 16
7671 23:42:53.870886 best dqsien dly found for B0: ( 1, 9, 10)
7672 23:42:53.874240 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7673 23:42:53.877123 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7674 23:42:53.884087 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 23:42:53.887392 Total UI for P1: 0, mck2ui 16
7676 23:42:53.890380 best dqsien dly found for B1: ( 1, 9, 22)
7677 23:42:53.894025 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7678 23:42:53.897212 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7679 23:42:53.897729
7680 23:42:53.900721 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7681 23:42:53.903918 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7682 23:42:53.907285 [Gating] SW calibration Done
7683 23:42:53.907858 ==
7684 23:42:53.910407 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 23:42:53.913754 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 23:42:53.914334 ==
7687 23:42:53.917079 RX Vref Scan: 0
7688 23:42:53.917692
7689 23:42:53.920596 RX Vref 0 -> 0, step: 1
7690 23:42:53.921173
7691 23:42:53.921792 RX Delay 0 -> 252, step: 8
7692 23:42:53.927117 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7693 23:42:53.930160 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7694 23:42:53.933319 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7695 23:42:53.936658 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7696 23:42:53.939894 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7697 23:42:53.946914 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7698 23:42:53.950037 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7699 23:42:53.953287 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7700 23:42:53.957067 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7701 23:42:53.959746 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
7702 23:42:53.966443 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7703 23:42:53.970329 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7704 23:42:53.973550 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7705 23:42:53.976599 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7706 23:42:53.979961 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7707 23:42:53.987165 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7708 23:42:53.987746 ==
7709 23:42:53.990180 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 23:42:53.993619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 23:42:53.994206 ==
7712 23:42:53.994701 DQS Delay:
7713 23:42:53.996909 DQS0 = 0, DQS1 = 0
7714 23:42:53.997385 DQM Delay:
7715 23:42:54.000561 DQM0 = 137, DQM1 = 130
7716 23:42:54.001141 DQ Delay:
7717 23:42:54.003106 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7718 23:42:54.007097 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7719 23:42:54.009833 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
7720 23:42:54.013350 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =135
7721 23:42:54.013980
7722 23:42:54.014479
7723 23:42:54.016583 ==
7724 23:42:54.020456 Dram Type= 6, Freq= 0, CH_0, rank 0
7725 23:42:54.022944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7726 23:42:54.023443 ==
7727 23:42:54.023928
7728 23:42:54.024384
7729 23:42:54.026501 TX Vref Scan disable
7730 23:42:54.026985 == TX Byte 0 ==
7731 23:42:54.033360 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7732 23:42:54.036272 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7733 23:42:54.036840 == TX Byte 1 ==
7734 23:42:54.039542 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7735 23:42:54.046209 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7736 23:42:54.046770 ==
7737 23:42:54.049979 Dram Type= 6, Freq= 0, CH_0, rank 0
7738 23:42:54.052998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7739 23:42:54.053625 ==
7740 23:42:54.067538
7741 23:42:54.070807 TX Vref early break, caculate TX vref
7742 23:42:54.073684 TX Vref=16, minBit 4, minWin=22, winSum=379
7743 23:42:54.076928 TX Vref=18, minBit 0, minWin=22, winSum=382
7744 23:42:54.080641 TX Vref=20, minBit 2, minWin=23, winSum=398
7745 23:42:54.083741 TX Vref=22, minBit 0, minWin=25, winSum=409
7746 23:42:54.087130 TX Vref=24, minBit 0, minWin=25, winSum=416
7747 23:42:54.093263 TX Vref=26, minBit 0, minWin=25, winSum=425
7748 23:42:54.096897 TX Vref=28, minBit 1, minWin=25, winSum=419
7749 23:42:54.100528 TX Vref=30, minBit 4, minWin=24, winSum=413
7750 23:42:54.103447 TX Vref=32, minBit 6, minWin=24, winSum=405
7751 23:42:54.106512 TX Vref=34, minBit 7, minWin=23, winSum=393
7752 23:42:54.113526 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 26
7753 23:42:54.114128
7754 23:42:54.117000 Final TX Range 0 Vref 26
7755 23:42:54.117560
7756 23:42:54.117973 ==
7757 23:42:54.120545 Dram Type= 6, Freq= 0, CH_0, rank 0
7758 23:42:54.123437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7759 23:42:54.123907 ==
7760 23:42:54.124278
7761 23:42:54.124619
7762 23:42:54.127578 TX Vref Scan disable
7763 23:42:54.133746 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
7764 23:42:54.134317 == TX Byte 0 ==
7765 23:42:54.136853 u2DelayCellOfst[0]=10 cells (3 PI)
7766 23:42:54.140451 u2DelayCellOfst[1]=13 cells (4 PI)
7767 23:42:54.143206 u2DelayCellOfst[2]=10 cells (3 PI)
7768 23:42:54.146517 u2DelayCellOfst[3]=6 cells (2 PI)
7769 23:42:54.150147 u2DelayCellOfst[4]=6 cells (2 PI)
7770 23:42:54.153325 u2DelayCellOfst[5]=0 cells (0 PI)
7771 23:42:54.156943 u2DelayCellOfst[6]=17 cells (5 PI)
7772 23:42:54.159892 u2DelayCellOfst[7]=13 cells (4 PI)
7773 23:42:54.163296 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7774 23:42:54.166398 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7775 23:42:54.169898 == TX Byte 1 ==
7776 23:42:54.170478 u2DelayCellOfst[8]=0 cells (0 PI)
7777 23:42:54.173303 u2DelayCellOfst[9]=3 cells (1 PI)
7778 23:42:54.176575 u2DelayCellOfst[10]=6 cells (2 PI)
7779 23:42:54.180381 u2DelayCellOfst[11]=6 cells (2 PI)
7780 23:42:54.183110 u2DelayCellOfst[12]=13 cells (4 PI)
7781 23:42:54.186843 u2DelayCellOfst[13]=13 cells (4 PI)
7782 23:42:54.189973 u2DelayCellOfst[14]=13 cells (4 PI)
7783 23:42:54.193260 u2DelayCellOfst[15]=10 cells (3 PI)
7784 23:42:54.196391 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7785 23:42:54.203116 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7786 23:42:54.203582 DramC Write-DBI on
7787 23:42:54.203951 ==
7788 23:42:54.206377 Dram Type= 6, Freq= 0, CH_0, rank 0
7789 23:42:54.209802 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7790 23:42:54.213391 ==
7791 23:42:54.214021
7792 23:42:54.214395
7793 23:42:54.214742 TX Vref Scan disable
7794 23:42:54.216565 == TX Byte 0 ==
7795 23:42:54.220129 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7796 23:42:54.223427 == TX Byte 1 ==
7797 23:42:54.226905 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7798 23:42:54.227373 DramC Write-DBI off
7799 23:42:54.229697
7800 23:42:54.230165 [DATLAT]
7801 23:42:54.230533 Freq=1600, CH0 RK0
7802 23:42:54.230883
7803 23:42:54.233484 DATLAT Default: 0xf
7804 23:42:54.233992 0, 0xFFFF, sum = 0
7805 23:42:54.237051 1, 0xFFFF, sum = 0
7806 23:42:54.237675 2, 0xFFFF, sum = 0
7807 23:42:54.240171 3, 0xFFFF, sum = 0
7808 23:42:54.243382 4, 0xFFFF, sum = 0
7809 23:42:54.243851 5, 0xFFFF, sum = 0
7810 23:42:54.246650 6, 0xFFFF, sum = 0
7811 23:42:54.247121 7, 0xFFFF, sum = 0
7812 23:42:54.249918 8, 0xFFFF, sum = 0
7813 23:42:54.250390 9, 0xFFFF, sum = 0
7814 23:42:54.253666 10, 0xFFFF, sum = 0
7815 23:42:54.254214 11, 0xFFFF, sum = 0
7816 23:42:54.256958 12, 0xFFFF, sum = 0
7817 23:42:54.257532 13, 0xFFFF, sum = 0
7818 23:42:54.260238 14, 0x0, sum = 1
7819 23:42:54.260812 15, 0x0, sum = 2
7820 23:42:54.263596 16, 0x0, sum = 3
7821 23:42:54.264169 17, 0x0, sum = 4
7822 23:42:54.266491 best_step = 15
7823 23:42:54.266954
7824 23:42:54.267317 ==
7825 23:42:54.270284 Dram Type= 6, Freq= 0, CH_0, rank 0
7826 23:42:54.273150 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7827 23:42:54.273768 ==
7828 23:42:54.274153 RX Vref Scan: 1
7829 23:42:54.276545
7830 23:42:54.277115 Set Vref Range= 24 -> 127
7831 23:42:54.277488
7832 23:42:54.280461 RX Vref 24 -> 127, step: 1
7833 23:42:54.281027
7834 23:42:54.283348 RX Delay 19 -> 252, step: 4
7835 23:42:54.283916
7836 23:42:54.286884 Set Vref, RX VrefLevel [Byte0]: 24
7837 23:42:54.289636 [Byte1]: 24
7838 23:42:54.290132
7839 23:42:54.293350 Set Vref, RX VrefLevel [Byte0]: 25
7840 23:42:54.296298 [Byte1]: 25
7841 23:42:54.296865
7842 23:42:54.300412 Set Vref, RX VrefLevel [Byte0]: 26
7843 23:42:54.303315 [Byte1]: 26
7844 23:42:54.307083
7845 23:42:54.307544 Set Vref, RX VrefLevel [Byte0]: 27
7846 23:42:54.310549 [Byte1]: 27
7847 23:42:54.314978
7848 23:42:54.315541 Set Vref, RX VrefLevel [Byte0]: 28
7849 23:42:54.318065 [Byte1]: 28
7850 23:42:54.322250
7851 23:42:54.322819 Set Vref, RX VrefLevel [Byte0]: 29
7852 23:42:54.325373 [Byte1]: 29
7853 23:42:54.329789
7854 23:42:54.330357 Set Vref, RX VrefLevel [Byte0]: 30
7855 23:42:54.333039 [Byte1]: 30
7856 23:42:54.337068
7857 23:42:54.337688 Set Vref, RX VrefLevel [Byte0]: 31
7858 23:42:54.340391 [Byte1]: 31
7859 23:42:54.345014
7860 23:42:54.345715 Set Vref, RX VrefLevel [Byte0]: 32
7861 23:42:54.347841 [Byte1]: 32
7862 23:42:54.352063
7863 23:42:54.352527 Set Vref, RX VrefLevel [Byte0]: 33
7864 23:42:54.356089 [Byte1]: 33
7865 23:42:54.359853
7866 23:42:54.360457 Set Vref, RX VrefLevel [Byte0]: 34
7867 23:42:54.362830 [Byte1]: 34
7868 23:42:54.367405
7869 23:42:54.367883 Set Vref, RX VrefLevel [Byte0]: 35
7870 23:42:54.371109 [Byte1]: 35
7871 23:42:54.375029
7872 23:42:54.375506 Set Vref, RX VrefLevel [Byte0]: 36
7873 23:42:54.378353 [Byte1]: 36
7874 23:42:54.382484
7875 23:42:54.382967 Set Vref, RX VrefLevel [Byte0]: 37
7876 23:42:54.385667 [Byte1]: 37
7877 23:42:54.390313
7878 23:42:54.390916 Set Vref, RX VrefLevel [Byte0]: 38
7879 23:42:54.393632 [Byte1]: 38
7880 23:42:54.397949
7881 23:42:54.398529 Set Vref, RX VrefLevel [Byte0]: 39
7882 23:42:54.401494 [Byte1]: 39
7883 23:42:54.405350
7884 23:42:54.405981 Set Vref, RX VrefLevel [Byte0]: 40
7885 23:42:54.408908 [Byte1]: 40
7886 23:42:54.412971
7887 23:42:54.413544 Set Vref, RX VrefLevel [Byte0]: 41
7888 23:42:54.416212 [Byte1]: 41
7889 23:42:54.420932
7890 23:42:54.421506 Set Vref, RX VrefLevel [Byte0]: 42
7891 23:42:54.423796 [Byte1]: 42
7892 23:42:54.428760
7893 23:42:54.429332 Set Vref, RX VrefLevel [Byte0]: 43
7894 23:42:54.431334 [Byte1]: 43
7895 23:42:54.435780
7896 23:42:54.436351 Set Vref, RX VrefLevel [Byte0]: 44
7897 23:42:54.439179 [Byte1]: 44
7898 23:42:54.443492
7899 23:42:54.444068 Set Vref, RX VrefLevel [Byte0]: 45
7900 23:42:54.446590 [Byte1]: 45
7901 23:42:54.451089
7902 23:42:54.451672 Set Vref, RX VrefLevel [Byte0]: 46
7903 23:42:54.453942 [Byte1]: 46
7904 23:42:54.458700
7905 23:42:54.459278 Set Vref, RX VrefLevel [Byte0]: 47
7906 23:42:54.461445 [Byte1]: 47
7907 23:42:54.465904
7908 23:42:54.466399 Set Vref, RX VrefLevel [Byte0]: 48
7909 23:42:54.469332 [Byte1]: 48
7910 23:42:54.473507
7911 23:42:54.474130 Set Vref, RX VrefLevel [Byte0]: 49
7912 23:42:54.476609 [Byte1]: 49
7913 23:42:54.481289
7914 23:42:54.481897 Set Vref, RX VrefLevel [Byte0]: 50
7915 23:42:54.484325 [Byte1]: 50
7916 23:42:54.488609
7917 23:42:54.489199 Set Vref, RX VrefLevel [Byte0]: 51
7918 23:42:54.491820 [Byte1]: 51
7919 23:42:54.496121
7920 23:42:54.496687 Set Vref, RX VrefLevel [Byte0]: 52
7921 23:42:54.499323 [Byte1]: 52
7922 23:42:54.503642
7923 23:42:54.504234 Set Vref, RX VrefLevel [Byte0]: 53
7924 23:42:54.507280 [Byte1]: 53
7925 23:42:54.511555
7926 23:42:54.512021 Set Vref, RX VrefLevel [Byte0]: 54
7927 23:42:54.514616 [Byte1]: 54
7928 23:42:54.519637
7929 23:42:54.520209 Set Vref, RX VrefLevel [Byte0]: 55
7930 23:42:54.522033 [Byte1]: 55
7931 23:42:54.526444
7932 23:42:54.526906 Set Vref, RX VrefLevel [Byte0]: 56
7933 23:42:54.529533 [Byte1]: 56
7934 23:42:54.534016
7935 23:42:54.534593 Set Vref, RX VrefLevel [Byte0]: 57
7936 23:42:54.537697 [Byte1]: 57
7937 23:42:54.542070
7938 23:42:54.542643 Set Vref, RX VrefLevel [Byte0]: 58
7939 23:42:54.545056 [Byte1]: 58
7940 23:42:54.549813
7941 23:42:54.550400 Set Vref, RX VrefLevel [Byte0]: 59
7942 23:42:54.552443 [Byte1]: 59
7943 23:42:54.556808
7944 23:42:54.557376 Set Vref, RX VrefLevel [Byte0]: 60
7945 23:42:54.560671 [Byte1]: 60
7946 23:42:54.564734
7947 23:42:54.565302 Set Vref, RX VrefLevel [Byte0]: 61
7948 23:42:54.567662 [Byte1]: 61
7949 23:42:54.572001
7950 23:42:54.572573 Set Vref, RX VrefLevel [Byte0]: 62
7951 23:42:54.575290 [Byte1]: 62
7952 23:42:54.579759
7953 23:42:54.580329 Set Vref, RX VrefLevel [Byte0]: 63
7954 23:42:54.582878 [Byte1]: 63
7955 23:42:54.587556
7956 23:42:54.588119 Set Vref, RX VrefLevel [Byte0]: 64
7957 23:42:54.590197 [Byte1]: 64
7958 23:42:54.594899
7959 23:42:54.595469 Set Vref, RX VrefLevel [Byte0]: 65
7960 23:42:54.598501 [Byte1]: 65
7961 23:42:54.602200
7962 23:42:54.602665 Set Vref, RX VrefLevel [Byte0]: 66
7963 23:42:54.605491 [Byte1]: 66
7964 23:42:54.609973
7965 23:42:54.610545 Set Vref, RX VrefLevel [Byte0]: 67
7966 23:42:54.613711 [Byte1]: 67
7967 23:42:54.617461
7968 23:42:54.618112 Set Vref, RX VrefLevel [Byte0]: 68
7969 23:42:54.621053 [Byte1]: 68
7970 23:42:54.624980
7971 23:42:54.625549 Set Vref, RX VrefLevel [Byte0]: 69
7972 23:42:54.628795 [Byte1]: 69
7973 23:42:54.632540
7974 23:42:54.633125 Set Vref, RX VrefLevel [Byte0]: 70
7975 23:42:54.636280 [Byte1]: 70
7976 23:42:54.640518
7977 23:42:54.641089 Set Vref, RX VrefLevel [Byte0]: 71
7978 23:42:54.643243 [Byte1]: 71
7979 23:42:54.647743
7980 23:42:54.648311 Set Vref, RX VrefLevel [Byte0]: 72
7981 23:42:54.650963 [Byte1]: 72
7982 23:42:54.655270
7983 23:42:54.655916 Set Vref, RX VrefLevel [Byte0]: 73
7984 23:42:54.658883 [Byte1]: 73
7985 23:42:54.662747
7986 23:42:54.663214 Set Vref, RX VrefLevel [Byte0]: 74
7987 23:42:54.666172 [Byte1]: 74
7988 23:42:54.670544
7989 23:42:54.671113 Set Vref, RX VrefLevel [Byte0]: 75
7990 23:42:54.674071 [Byte1]: 75
7991 23:42:54.678208
7992 23:42:54.678779 Set Vref, RX VrefLevel [Byte0]: 76
7993 23:42:54.681745 [Byte1]: 76
7994 23:42:54.685717
7995 23:42:54.686185 Set Vref, RX VrefLevel [Byte0]: 77
7996 23:42:54.689234 [Byte1]: 77
7997 23:42:54.693478
7998 23:42:54.694098 Final RX Vref Byte 0 = 55 to rank0
7999 23:42:54.696613 Final RX Vref Byte 1 = 59 to rank0
8000 23:42:54.699812 Final RX Vref Byte 0 = 55 to rank1
8001 23:42:54.703175 Final RX Vref Byte 1 = 59 to rank1==
8002 23:42:54.706150 Dram Type= 6, Freq= 0, CH_0, rank 0
8003 23:42:54.713240 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 23:42:54.713879 ==
8005 23:42:54.714257 DQS Delay:
8006 23:42:54.714602 DQS0 = 0, DQS1 = 0
8007 23:42:54.716442 DQM Delay:
8008 23:42:54.717007 DQM0 = 134, DQM1 = 127
8009 23:42:54.719866 DQ Delay:
8010 23:42:54.722852 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =130
8011 23:42:54.726147 DQ4 =132, DQ5 =124, DQ6 =142, DQ7 =138
8012 23:42:54.729602 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
8013 23:42:54.732779 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
8014 23:42:54.733244
8015 23:42:54.733656
8016 23:42:54.734012
8017 23:42:54.736129 [DramC_TX_OE_Calibration] TA2
8018 23:42:54.739755 Original DQ_B0 (3 6) =30, OEN = 27
8019 23:42:54.743114 Original DQ_B1 (3 6) =30, OEN = 27
8020 23:42:54.746201 24, 0x0, End_B0=24 End_B1=24
8021 23:42:54.746702 25, 0x0, End_B0=25 End_B1=25
8022 23:42:54.749630 26, 0x0, End_B0=26 End_B1=26
8023 23:42:54.753413 27, 0x0, End_B0=27 End_B1=27
8024 23:42:54.755972 28, 0x0, End_B0=28 End_B1=28
8025 23:42:54.756404 29, 0x0, End_B0=29 End_B1=29
8026 23:42:54.759449 30, 0x0, End_B0=30 End_B1=30
8027 23:42:54.762824 31, 0x4141, End_B0=30 End_B1=30
8028 23:42:54.765987 Byte0 end_step=30 best_step=27
8029 23:42:54.769525 Byte1 end_step=30 best_step=27
8030 23:42:54.772769 Byte0 TX OE(2T, 0.5T) = (3, 3)
8031 23:42:54.773195 Byte1 TX OE(2T, 0.5T) = (3, 3)
8032 23:42:54.776582
8033 23:42:54.777148
8034 23:42:54.783192 [DQSOSCAuto] RK0, (LSB)MR18= 0x2420, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8035 23:42:54.786113 CH0 RK0: MR19=303, MR18=2420
8036 23:42:54.793280 CH0_RK0: MR19=0x303, MR18=0x2420, DQSOSC=391, MR23=63, INC=24, DEC=16
8037 23:42:54.793882
8038 23:42:54.796205 ----->DramcWriteLeveling(PI) begin...
8039 23:42:54.796679 ==
8040 23:42:54.799496 Dram Type= 6, Freq= 0, CH_0, rank 1
8041 23:42:54.802432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8042 23:42:54.802899 ==
8043 23:42:54.805902 Write leveling (Byte 0): 37 => 37
8044 23:42:54.809511 Write leveling (Byte 1): 26 => 26
8045 23:42:54.812701 DramcWriteLeveling(PI) end<-----
8046 23:42:54.813262
8047 23:42:54.813691 ==
8048 23:42:54.816277 Dram Type= 6, Freq= 0, CH_0, rank 1
8049 23:42:54.819143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 23:42:54.819629 ==
8051 23:42:54.822254 [Gating] SW mode calibration
8052 23:42:54.829234 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8053 23:42:54.835636 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8054 23:42:54.839080 1 4 0 | B1->B0 | 2323 2423 | 0 1 | (0 0) (0 0)
8055 23:42:54.842649 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8056 23:42:54.849160 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8057 23:42:54.852485 1 4 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8058 23:42:54.855739 1 4 16 | B1->B0 | 2f2f 3635 | 0 1 | (0 0) (0 0)
8059 23:42:54.862509 1 4 20 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8060 23:42:54.865315 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
8061 23:42:54.868999 1 4 28 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8062 23:42:54.875837 1 5 0 | B1->B0 | 3434 3939 | 1 1 | (1 1) (0 0)
8063 23:42:54.879474 1 5 4 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8064 23:42:54.882213 1 5 8 | B1->B0 | 3434 3636 | 1 0 | (1 1) (0 0)
8065 23:42:54.888769 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 0) (1 0)
8066 23:42:54.891804 1 5 16 | B1->B0 | 2f2f 2a29 | 0 1 | (0 1) (0 0)
8067 23:42:54.895598 1 5 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8068 23:42:54.901936 1 5 24 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8069 23:42:54.905430 1 5 28 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 1)
8070 23:42:54.908722 1 6 0 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
8071 23:42:54.915385 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8072 23:42:54.918549 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8073 23:42:54.922584 1 6 12 | B1->B0 | 2323 3838 | 0 1 | (0 0) (1 1)
8074 23:42:54.928733 1 6 16 | B1->B0 | 3c3c 4645 | 0 1 | (0 0) (0 0)
8075 23:42:54.931760 1 6 20 | B1->B0 | 4646 4545 | 0 1 | (0 0) (0 0)
8076 23:42:54.935154 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8077 23:42:54.941793 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8078 23:42:54.944980 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 23:42:54.948669 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8080 23:42:54.955178 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8081 23:42:54.958545 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8082 23:42:54.961858 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8083 23:42:54.968342 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8084 23:42:54.971814 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8085 23:42:54.974836 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8086 23:42:54.981642 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8087 23:42:54.985013 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8088 23:42:54.988506 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8089 23:42:54.994965 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8090 23:42:54.998000 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8091 23:42:55.001484 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8092 23:42:55.008526 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8093 23:42:55.011547 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8094 23:42:55.014521 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8095 23:42:55.020979 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8096 23:42:55.024352 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8097 23:42:55.028132 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8098 23:42:55.034181 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8099 23:42:55.034648 Total UI for P1: 0, mck2ui 16
8100 23:42:55.037545 best dqsien dly found for B1: ( 1, 9, 12)
8101 23:42:55.044549 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8102 23:42:55.047537 Total UI for P1: 0, mck2ui 16
8103 23:42:55.051080 best dqsien dly found for B0: ( 1, 9, 14)
8104 23:42:55.054379 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8105 23:42:55.057842 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8106 23:42:55.058261
8107 23:42:55.060951 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8108 23:42:55.064634 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8109 23:42:55.067688 [Gating] SW calibration Done
8110 23:42:55.068158 ==
8111 23:42:55.070939 Dram Type= 6, Freq= 0, CH_0, rank 1
8112 23:42:55.074577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8113 23:42:55.077544 ==
8114 23:42:55.078120 RX Vref Scan: 0
8115 23:42:55.078463
8116 23:42:55.081086 RX Vref 0 -> 0, step: 1
8117 23:42:55.081644
8118 23:42:55.081993 RX Delay 0 -> 252, step: 8
8119 23:42:55.087258 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8120 23:42:55.090920 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8121 23:42:55.094173 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8122 23:42:55.097210 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8123 23:42:55.100759 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8124 23:42:55.107469 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8125 23:42:55.110998 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8126 23:42:55.113970 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8127 23:42:55.117379 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8128 23:42:55.120892 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8129 23:42:55.126909 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8130 23:42:55.130612 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8131 23:42:55.133865 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8132 23:42:55.137105 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8133 23:42:55.140728 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8134 23:42:55.147465 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8135 23:42:55.148030 ==
8136 23:42:55.150462 Dram Type= 6, Freq= 0, CH_0, rank 1
8137 23:42:55.153801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8138 23:42:55.154271 ==
8139 23:42:55.154642 DQS Delay:
8140 23:42:55.156934 DQS0 = 0, DQS1 = 0
8141 23:42:55.157399 DQM Delay:
8142 23:42:55.160725 DQM0 = 136, DQM1 = 128
8143 23:42:55.161285 DQ Delay:
8144 23:42:55.163912 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8145 23:42:55.166988 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8146 23:42:55.170411 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8147 23:42:55.173921 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8148 23:42:55.177568
8149 23:42:55.178187
8150 23:42:55.178557 ==
8151 23:42:55.180409 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 23:42:55.183822 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 23:42:55.184386 ==
8154 23:42:55.184756
8155 23:42:55.185095
8156 23:42:55.187004 TX Vref Scan disable
8157 23:42:55.187569 == TX Byte 0 ==
8158 23:42:55.193836 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8159 23:42:55.197405 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8160 23:42:55.198040 == TX Byte 1 ==
8161 23:42:55.203459 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8162 23:42:55.207018 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8163 23:42:55.207584 ==
8164 23:42:55.210211 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 23:42:55.213374 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 23:42:55.213891 ==
8167 23:42:55.230013
8168 23:42:55.233388 TX Vref early break, caculate TX vref
8169 23:42:55.236468 TX Vref=16, minBit 0, minWin=23, winSum=388
8170 23:42:55.239884 TX Vref=18, minBit 1, minWin=23, winSum=394
8171 23:42:55.243249 TX Vref=20, minBit 0, minWin=24, winSum=406
8172 23:42:55.246184 TX Vref=22, minBit 1, minWin=25, winSum=410
8173 23:42:55.249821 TX Vref=24, minBit 1, minWin=25, winSum=422
8174 23:42:55.256712 TX Vref=26, minBit 1, minWin=25, winSum=425
8175 23:42:55.259503 TX Vref=28, minBit 1, minWin=25, winSum=421
8176 23:42:55.262683 TX Vref=30, minBit 0, minWin=25, winSum=415
8177 23:42:55.266265 TX Vref=32, minBit 4, minWin=24, winSum=406
8178 23:42:55.269785 TX Vref=34, minBit 0, minWin=24, winSum=404
8179 23:42:55.273178 TX Vref=36, minBit 8, minWin=23, winSum=392
8180 23:42:55.279514 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 26
8181 23:42:55.280064
8182 23:42:55.283174 Final TX Range 0 Vref 26
8183 23:42:55.283740
8184 23:42:55.284110 ==
8185 23:42:55.286250 Dram Type= 6, Freq= 0, CH_0, rank 1
8186 23:42:55.289932 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8187 23:42:55.290501 ==
8188 23:42:55.290870
8189 23:42:55.291208
8190 23:42:55.293254 TX Vref Scan disable
8191 23:42:55.300084 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8192 23:42:55.300644 == TX Byte 0 ==
8193 23:42:55.303358 u2DelayCellOfst[0]=13 cells (4 PI)
8194 23:42:55.306482 u2DelayCellOfst[1]=17 cells (5 PI)
8195 23:42:55.309798 u2DelayCellOfst[2]=13 cells (4 PI)
8196 23:42:55.313005 u2DelayCellOfst[3]=10 cells (3 PI)
8197 23:42:55.316381 u2DelayCellOfst[4]=10 cells (3 PI)
8198 23:42:55.319583 u2DelayCellOfst[5]=0 cells (0 PI)
8199 23:42:55.323503 u2DelayCellOfst[6]=17 cells (5 PI)
8200 23:42:55.326149 u2DelayCellOfst[7]=17 cells (5 PI)
8201 23:42:55.329731 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8202 23:42:55.333182 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8203 23:42:55.336006 == TX Byte 1 ==
8204 23:42:55.339543 u2DelayCellOfst[8]=0 cells (0 PI)
8205 23:42:55.342675 u2DelayCellOfst[9]=0 cells (0 PI)
8206 23:42:55.343241 u2DelayCellOfst[10]=3 cells (1 PI)
8207 23:42:55.346061 u2DelayCellOfst[11]=0 cells (0 PI)
8208 23:42:55.349025 u2DelayCellOfst[12]=10 cells (3 PI)
8209 23:42:55.352576 u2DelayCellOfst[13]=10 cells (3 PI)
8210 23:42:55.356086 u2DelayCellOfst[14]=10 cells (3 PI)
8211 23:42:55.358995 u2DelayCellOfst[15]=6 cells (2 PI)
8212 23:42:55.362734 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8213 23:42:55.369227 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8214 23:42:55.369820 DramC Write-DBI on
8215 23:42:55.370196 ==
8216 23:42:55.372560 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 23:42:55.379393 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 23:42:55.379947 ==
8219 23:42:55.380317
8220 23:42:55.380657
8221 23:42:55.380984 TX Vref Scan disable
8222 23:42:55.383552 == TX Byte 0 ==
8223 23:42:55.386715 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
8224 23:42:55.389571 == TX Byte 1 ==
8225 23:42:55.392911 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8226 23:42:55.396260 DramC Write-DBI off
8227 23:42:55.396893
8228 23:42:55.397273 [DATLAT]
8229 23:42:55.397664 Freq=1600, CH0 RK1
8230 23:42:55.398010
8231 23:42:55.399734 DATLAT Default: 0xf
8232 23:42:55.400211 0, 0xFFFF, sum = 0
8233 23:42:55.402995 1, 0xFFFF, sum = 0
8234 23:42:55.406173 2, 0xFFFF, sum = 0
8235 23:42:55.406639 3, 0xFFFF, sum = 0
8236 23:42:55.409686 4, 0xFFFF, sum = 0
8237 23:42:55.410159 5, 0xFFFF, sum = 0
8238 23:42:55.412994 6, 0xFFFF, sum = 0
8239 23:42:55.413486 7, 0xFFFF, sum = 0
8240 23:42:55.416698 8, 0xFFFF, sum = 0
8241 23:42:55.417269 9, 0xFFFF, sum = 0
8242 23:42:55.419876 10, 0xFFFF, sum = 0
8243 23:42:55.420453 11, 0xFFFF, sum = 0
8244 23:42:55.422994 12, 0xFFFF, sum = 0
8245 23:42:55.423463 13, 0xFFFF, sum = 0
8246 23:42:55.426235 14, 0x0, sum = 1
8247 23:42:55.426700 15, 0x0, sum = 2
8248 23:42:55.429804 16, 0x0, sum = 3
8249 23:42:55.430269 17, 0x0, sum = 4
8250 23:42:55.432937 best_step = 15
8251 23:42:55.433398
8252 23:42:55.433826 ==
8253 23:42:55.436529 Dram Type= 6, Freq= 0, CH_0, rank 1
8254 23:42:55.439839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 23:42:55.440256 ==
8256 23:42:55.443156 RX Vref Scan: 0
8257 23:42:55.443673
8258 23:42:55.444008 RX Vref 0 -> 0, step: 1
8259 23:42:55.444315
8260 23:42:55.446288 RX Delay 19 -> 252, step: 4
8261 23:42:55.450078 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8262 23:42:55.456456 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8263 23:42:55.460132 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8264 23:42:55.462838 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8265 23:42:55.466496 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8266 23:42:55.469864 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8267 23:42:55.476375 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8268 23:42:55.479650 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8269 23:42:55.483069 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8270 23:42:55.486520 iDelay=191, Bit 9, Center 116 (63 ~ 170) 108
8271 23:42:55.489719 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8272 23:42:55.496778 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8273 23:42:55.499662 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8274 23:42:55.502843 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8275 23:42:55.506071 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8276 23:42:55.509564 iDelay=191, Bit 15, Center 134 (83 ~ 186) 104
8277 23:42:55.512962 ==
8278 23:42:55.516194 Dram Type= 6, Freq= 0, CH_0, rank 1
8279 23:42:55.519201 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8280 23:42:55.519682 ==
8281 23:42:55.520049 DQS Delay:
8282 23:42:55.523100 DQS0 = 0, DQS1 = 0
8283 23:42:55.523671 DQM Delay:
8284 23:42:55.525893 DQM0 = 135, DQM1 = 127
8285 23:42:55.526351 DQ Delay:
8286 23:42:55.529327 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8287 23:42:55.532715 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =142
8288 23:42:55.536706 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8289 23:42:55.540048 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =134
8290 23:42:55.540609
8291 23:42:55.540977
8292 23:42:55.541317
8293 23:42:55.542394 [DramC_TX_OE_Calibration] TA2
8294 23:42:55.546091 Original DQ_B0 (3 6) =30, OEN = 27
8295 23:42:55.549159 Original DQ_B1 (3 6) =30, OEN = 27
8296 23:42:55.552896 24, 0x0, End_B0=24 End_B1=24
8297 23:42:55.556292 25, 0x0, End_B0=25 End_B1=25
8298 23:42:55.556863 26, 0x0, End_B0=26 End_B1=26
8299 23:42:55.559513 27, 0x0, End_B0=27 End_B1=27
8300 23:42:55.562617 28, 0x0, End_B0=28 End_B1=28
8301 23:42:55.565834 29, 0x0, End_B0=29 End_B1=29
8302 23:42:55.566405 30, 0x0, End_B0=30 End_B1=30
8303 23:42:55.569042 31, 0x4141, End_B0=30 End_B1=30
8304 23:42:55.573137 Byte0 end_step=30 best_step=27
8305 23:42:55.575899 Byte1 end_step=30 best_step=27
8306 23:42:55.579440 Byte0 TX OE(2T, 0.5T) = (3, 3)
8307 23:42:55.582786 Byte1 TX OE(2T, 0.5T) = (3, 3)
8308 23:42:55.583349
8309 23:42:55.583715
8310 23:42:55.589317 [DQSOSCAuto] RK1, (LSB)MR18= 0x1e06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8311 23:42:55.592866 CH0 RK1: MR19=303, MR18=1E06
8312 23:42:55.599408 CH0_RK1: MR19=0x303, MR18=0x1E06, DQSOSC=394, MR23=63, INC=23, DEC=15
8313 23:42:55.602663 [RxdqsGatingPostProcess] freq 1600
8314 23:42:55.609174 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8315 23:42:55.609779 best DQS0 dly(2T, 0.5T) = (1, 1)
8316 23:42:55.612196 best DQS1 dly(2T, 0.5T) = (1, 1)
8317 23:42:55.615665 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8318 23:42:55.618831 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8319 23:42:55.622564 best DQS0 dly(2T, 0.5T) = (1, 1)
8320 23:42:55.625971 best DQS1 dly(2T, 0.5T) = (1, 1)
8321 23:42:55.628960 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8322 23:42:55.632478 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8323 23:42:55.635459 Pre-setting of DQS Precalculation
8324 23:42:55.638720 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8325 23:42:55.639186 ==
8326 23:42:55.642222 Dram Type= 6, Freq= 0, CH_1, rank 0
8327 23:42:55.648918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8328 23:42:55.649465 ==
8329 23:42:55.651804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8330 23:42:55.659179 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8331 23:42:55.662169 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8332 23:42:55.668404 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8333 23:42:55.676198 [CA 0] Center 42 (13~72) winsize 60
8334 23:42:55.679293 [CA 1] Center 42 (12~72) winsize 61
8335 23:42:55.682864 [CA 2] Center 39 (10~68) winsize 59
8336 23:42:55.686372 [CA 3] Center 38 (9~67) winsize 59
8337 23:42:55.689525 [CA 4] Center 38 (9~68) winsize 60
8338 23:42:55.692692 [CA 5] Center 37 (8~67) winsize 60
8339 23:42:55.693154
8340 23:42:55.696009 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8341 23:42:55.696566
8342 23:42:55.700110 [CATrainingPosCal] consider 1 rank data
8343 23:42:55.702654 u2DelayCellTimex100 = 285/100 ps
8344 23:42:55.705838 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8345 23:42:55.713162 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8346 23:42:55.716104 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8347 23:42:55.719422 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8348 23:42:55.722340 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8349 23:42:55.725896 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8350 23:42:55.726462
8351 23:42:55.729344 CA PerBit enable=1, Macro0, CA PI delay=37
8352 23:42:55.729961
8353 23:42:55.733231 [CBTSetCACLKResult] CA Dly = 37
8354 23:42:55.736212 CS Dly: 11 (0~42)
8355 23:42:55.738877 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8356 23:42:55.742786 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8357 23:42:55.743346 ==
8358 23:42:55.746030 Dram Type= 6, Freq= 0, CH_1, rank 1
8359 23:42:55.752208 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8360 23:42:55.752671 ==
8361 23:42:55.755543 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8362 23:42:55.758994 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8363 23:42:55.765134 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8364 23:42:55.771608 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8365 23:42:55.780075 [CA 0] Center 42 (12~72) winsize 61
8366 23:42:55.782787 [CA 1] Center 42 (12~72) winsize 61
8367 23:42:55.785956 [CA 2] Center 38 (9~68) winsize 60
8368 23:42:55.789201 [CA 3] Center 38 (8~68) winsize 61
8369 23:42:55.792967 [CA 4] Center 38 (8~69) winsize 62
8370 23:42:55.796110 [CA 5] Center 37 (7~67) winsize 61
8371 23:42:55.796520
8372 23:42:55.799670 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8373 23:42:55.800179
8374 23:42:55.802656 [CATrainingPosCal] consider 2 rank data
8375 23:42:55.805979 u2DelayCellTimex100 = 285/100 ps
8376 23:42:55.809497 CA0 delay=42 (13~72),Diff = 5 PI (17 cell)
8377 23:42:55.815890 CA1 delay=42 (12~72),Diff = 5 PI (17 cell)
8378 23:42:55.819546 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8379 23:42:55.822880 CA3 delay=38 (9~67),Diff = 1 PI (3 cell)
8380 23:42:55.826141 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8381 23:42:55.829245 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8382 23:42:55.829854
8383 23:42:55.832859 CA PerBit enable=1, Macro0, CA PI delay=37
8384 23:42:55.833413
8385 23:42:55.835886 [CBTSetCACLKResult] CA Dly = 37
8386 23:42:55.838873 CS Dly: 12 (0~45)
8387 23:42:55.842238 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8388 23:42:55.845333 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8389 23:42:55.845857
8390 23:42:55.849170 ----->DramcWriteLeveling(PI) begin...
8391 23:42:55.849749 ==
8392 23:42:55.852259 Dram Type= 6, Freq= 0, CH_1, rank 0
8393 23:42:55.859397 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8394 23:42:55.859827 ==
8395 23:42:55.862294 Write leveling (Byte 0): 25 => 25
8396 23:42:55.862709 Write leveling (Byte 1): 28 => 28
8397 23:42:55.865486 DramcWriteLeveling(PI) end<-----
8398 23:42:55.865954
8399 23:42:55.868881 ==
8400 23:42:55.872214 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 23:42:55.875524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 23:42:55.875965 ==
8403 23:42:55.878765 [Gating] SW mode calibration
8404 23:42:55.885669 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8405 23:42:55.889043 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8406 23:42:55.895747 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8407 23:42:55.898900 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8408 23:42:55.902473 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8409 23:42:55.908680 1 4 12 | B1->B0 | 2c2c 3434 | 0 1 | (1 1) (1 1)
8410 23:42:55.912425 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8411 23:42:55.915492 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8412 23:42:55.922218 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8413 23:42:55.925449 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8414 23:42:55.929037 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8415 23:42:55.935258 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8416 23:42:55.938781 1 5 8 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
8417 23:42:55.941905 1 5 12 | B1->B0 | 2a2a 2323 | 1 1 | (1 0) (1 0)
8418 23:42:55.949682 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8419 23:42:55.952091 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8420 23:42:55.955399 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8421 23:42:55.961755 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8422 23:42:55.965324 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8423 23:42:55.968598 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8424 23:42:55.975816 1 6 8 | B1->B0 | 2424 2a2a | 0 0 | (0 0) (0 0)
8425 23:42:55.978887 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8426 23:42:55.981981 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 23:42:55.985825 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8428 23:42:55.992112 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8429 23:42:55.995326 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 23:42:55.998840 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8431 23:42:56.005944 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8432 23:42:56.008721 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8433 23:42:56.011591 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8434 23:42:56.018927 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8435 23:42:56.022262 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8436 23:42:56.025436 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8437 23:42:56.031732 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8438 23:42:56.035122 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8439 23:42:56.038443 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8440 23:42:56.045301 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8441 23:42:56.047811 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8442 23:42:56.051200 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8443 23:42:56.057934 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8444 23:42:56.061793 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8445 23:42:56.064648 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8446 23:42:56.071079 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8447 23:42:56.074531 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8448 23:42:56.078222 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8449 23:42:56.084585 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8450 23:42:56.087608 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8451 23:42:56.091185 Total UI for P1: 0, mck2ui 16
8452 23:42:56.094581 best dqsien dly found for B0: ( 1, 9, 10)
8453 23:42:56.097639 Total UI for P1: 0, mck2ui 16
8454 23:42:56.101241 best dqsien dly found for B1: ( 1, 9, 10)
8455 23:42:56.104725 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8456 23:42:56.108200 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8457 23:42:56.108780
8458 23:42:56.111174 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8459 23:42:56.114685 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8460 23:42:56.117859 [Gating] SW calibration Done
8461 23:42:56.118419 ==
8462 23:42:56.121541 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 23:42:56.124727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 23:42:56.127483 ==
8465 23:42:56.127942 RX Vref Scan: 0
8466 23:42:56.128306
8467 23:42:56.131321 RX Vref 0 -> 0, step: 1
8468 23:42:56.131880
8469 23:42:56.134540 RX Delay 0 -> 252, step: 8
8470 23:42:56.137560 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8471 23:42:56.141042 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8472 23:42:56.144059 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8473 23:42:56.147553 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8474 23:42:56.154420 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8475 23:42:56.157758 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8476 23:42:56.160870 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8477 23:42:56.164372 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8478 23:42:56.167791 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8479 23:42:56.171083 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8480 23:42:56.178068 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8481 23:42:56.181104 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8482 23:42:56.184238 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8483 23:42:56.187507 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8484 23:42:56.194462 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8485 23:42:56.197456 iDelay=200, Bit 15, Center 143 (96 ~ 191) 96
8486 23:42:56.198071 ==
8487 23:42:56.201522 Dram Type= 6, Freq= 0, CH_1, rank 0
8488 23:42:56.203747 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8489 23:42:56.204214 ==
8490 23:42:56.204586 DQS Delay:
8491 23:42:56.207449 DQS0 = 0, DQS1 = 0
8492 23:42:56.208020 DQM Delay:
8493 23:42:56.210509 DQM0 = 136, DQM1 = 133
8494 23:42:56.210973 DQ Delay:
8495 23:42:56.213878 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8496 23:42:56.218032 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8497 23:42:56.220623 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8498 23:42:56.223883 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =143
8499 23:42:56.227324
8500 23:42:56.227786
8501 23:42:56.228156 ==
8502 23:42:56.230831 Dram Type= 6, Freq= 0, CH_1, rank 0
8503 23:42:56.234078 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8504 23:42:56.234546 ==
8505 23:42:56.234914
8506 23:42:56.235257
8507 23:42:56.237489 TX Vref Scan disable
8508 23:42:56.238089 == TX Byte 0 ==
8509 23:42:56.243675 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8510 23:42:56.247464 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8511 23:42:56.248033 == TX Byte 1 ==
8512 23:42:56.253829 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8513 23:42:56.257066 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8514 23:42:56.257688 ==
8515 23:42:56.260490 Dram Type= 6, Freq= 0, CH_1, rank 0
8516 23:42:56.263552 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8517 23:42:56.264024 ==
8518 23:42:56.278492
8519 23:42:56.281693 TX Vref early break, caculate TX vref
8520 23:42:56.285057 TX Vref=16, minBit 0, minWin=22, winSum=376
8521 23:42:56.288706 TX Vref=18, minBit 1, minWin=23, winSum=387
8522 23:42:56.291846 TX Vref=20, minBit 1, minWin=23, winSum=397
8523 23:42:56.295060 TX Vref=22, minBit 6, minWin=24, winSum=405
8524 23:42:56.298590 TX Vref=24, minBit 1, minWin=25, winSum=415
8525 23:42:56.304778 TX Vref=26, minBit 1, minWin=25, winSum=422
8526 23:42:56.309060 TX Vref=28, minBit 0, minWin=26, winSum=426
8527 23:42:56.311842 TX Vref=30, minBit 0, minWin=25, winSum=419
8528 23:42:56.314790 TX Vref=32, minBit 6, minWin=24, winSum=413
8529 23:42:56.318537 TX Vref=34, minBit 6, minWin=24, winSum=407
8530 23:42:56.321742 TX Vref=36, minBit 2, minWin=23, winSum=388
8531 23:42:56.328247 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
8532 23:42:56.328803
8533 23:42:56.331867 Final TX Range 0 Vref 28
8534 23:42:56.332438
8535 23:42:56.332811 ==
8536 23:42:56.335634 Dram Type= 6, Freq= 0, CH_1, rank 0
8537 23:42:56.338275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8538 23:42:56.338847 ==
8539 23:42:56.339220
8540 23:42:56.339562
8541 23:42:56.341485 TX Vref Scan disable
8542 23:42:56.348208 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8543 23:42:56.348878 == TX Byte 0 ==
8544 23:42:56.351597 u2DelayCellOfst[0]=17 cells (5 PI)
8545 23:42:56.354742 u2DelayCellOfst[1]=10 cells (3 PI)
8546 23:42:56.358428 u2DelayCellOfst[2]=0 cells (0 PI)
8547 23:42:56.361919 u2DelayCellOfst[3]=6 cells (2 PI)
8548 23:42:56.365223 u2DelayCellOfst[4]=6 cells (2 PI)
8549 23:42:56.368122 u2DelayCellOfst[5]=20 cells (6 PI)
8550 23:42:56.371902 u2DelayCellOfst[6]=17 cells (5 PI)
8551 23:42:56.374964 u2DelayCellOfst[7]=6 cells (2 PI)
8552 23:42:56.378148 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8553 23:42:56.381423 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8554 23:42:56.384996 == TX Byte 1 ==
8555 23:42:56.385780 u2DelayCellOfst[8]=0 cells (0 PI)
8556 23:42:56.388423 u2DelayCellOfst[9]=0 cells (0 PI)
8557 23:42:56.391725 u2DelayCellOfst[10]=10 cells (3 PI)
8558 23:42:56.394461 u2DelayCellOfst[11]=3 cells (1 PI)
8559 23:42:56.397831 u2DelayCellOfst[12]=13 cells (4 PI)
8560 23:42:56.401674 u2DelayCellOfst[13]=13 cells (4 PI)
8561 23:42:56.405193 u2DelayCellOfst[14]=13 cells (4 PI)
8562 23:42:56.408481 u2DelayCellOfst[15]=13 cells (4 PI)
8563 23:42:56.411555 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8564 23:42:56.418050 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8565 23:42:56.418596 DramC Write-DBI on
8566 23:42:56.418964 ==
8567 23:42:56.421620 Dram Type= 6, Freq= 0, CH_1, rank 0
8568 23:42:56.424826 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8569 23:42:56.427671 ==
8570 23:42:56.428133
8571 23:42:56.428500
8572 23:42:56.428836 TX Vref Scan disable
8573 23:42:56.432039 == TX Byte 0 ==
8574 23:42:56.434644 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8575 23:42:56.438284 == TX Byte 1 ==
8576 23:42:56.441481 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8577 23:42:56.444750 DramC Write-DBI off
8578 23:42:56.445317
8579 23:42:56.445744 [DATLAT]
8580 23:42:56.446094 Freq=1600, CH1 RK0
8581 23:42:56.446429
8582 23:42:56.448149 DATLAT Default: 0xf
8583 23:42:56.448614 0, 0xFFFF, sum = 0
8584 23:42:56.451769 1, 0xFFFF, sum = 0
8585 23:42:56.454371 2, 0xFFFF, sum = 0
8586 23:42:56.454847 3, 0xFFFF, sum = 0
8587 23:42:56.458075 4, 0xFFFF, sum = 0
8588 23:42:56.458658 5, 0xFFFF, sum = 0
8589 23:42:56.461362 6, 0xFFFF, sum = 0
8590 23:42:56.462013 7, 0xFFFF, sum = 0
8591 23:42:56.464572 8, 0xFFFF, sum = 0
8592 23:42:56.465046 9, 0xFFFF, sum = 0
8593 23:42:56.468163 10, 0xFFFF, sum = 0
8594 23:42:56.468817 11, 0xFFFF, sum = 0
8595 23:42:56.471224 12, 0xFFFF, sum = 0
8596 23:42:56.471698 13, 0xFFFF, sum = 0
8597 23:42:56.475199 14, 0x0, sum = 1
8598 23:42:56.475780 15, 0x0, sum = 2
8599 23:42:56.478097 16, 0x0, sum = 3
8600 23:42:56.478575 17, 0x0, sum = 4
8601 23:42:56.481701 best_step = 15
8602 23:42:56.482171
8603 23:42:56.482548 ==
8604 23:42:56.485151 Dram Type= 6, Freq= 0, CH_1, rank 0
8605 23:42:56.487988 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8606 23:42:56.488571 ==
8607 23:42:56.488947 RX Vref Scan: 1
8608 23:42:56.491467
8609 23:42:56.492030 Set Vref Range= 24 -> 127
8610 23:42:56.492410
8611 23:42:56.494662 RX Vref 24 -> 127, step: 1
8612 23:42:56.495130
8613 23:42:56.497962 RX Delay 27 -> 252, step: 4
8614 23:42:56.498430
8615 23:42:56.501487 Set Vref, RX VrefLevel [Byte0]: 24
8616 23:42:56.504501 [Byte1]: 24
8617 23:42:56.505072
8618 23:42:56.507799 Set Vref, RX VrefLevel [Byte0]: 25
8619 23:42:56.510895 [Byte1]: 25
8620 23:42:56.511374
8621 23:42:56.515013 Set Vref, RX VrefLevel [Byte0]: 26
8622 23:42:56.517959 [Byte1]: 26
8623 23:42:56.521638
8624 23:42:56.522191 Set Vref, RX VrefLevel [Byte0]: 27
8625 23:42:56.525260 [Byte1]: 27
8626 23:42:56.529108
8627 23:42:56.529625 Set Vref, RX VrefLevel [Byte0]: 28
8628 23:42:56.532170 [Byte1]: 28
8629 23:42:56.536713
8630 23:42:56.537274 Set Vref, RX VrefLevel [Byte0]: 29
8631 23:42:56.540271 [Byte1]: 29
8632 23:42:56.544864
8633 23:42:56.545420 Set Vref, RX VrefLevel [Byte0]: 30
8634 23:42:56.547885 [Byte1]: 30
8635 23:42:56.551918
8636 23:42:56.552373 Set Vref, RX VrefLevel [Byte0]: 31
8637 23:42:56.555076 [Byte1]: 31
8638 23:42:56.559414
8639 23:42:56.560012 Set Vref, RX VrefLevel [Byte0]: 32
8640 23:42:56.562142 [Byte1]: 32
8641 23:42:56.566798
8642 23:42:56.567381 Set Vref, RX VrefLevel [Byte0]: 33
8643 23:42:56.570512 [Byte1]: 33
8644 23:42:56.574536
8645 23:42:56.575102 Set Vref, RX VrefLevel [Byte0]: 34
8646 23:42:56.577524 [Byte1]: 34
8647 23:42:56.581834
8648 23:42:56.582300 Set Vref, RX VrefLevel [Byte0]: 35
8649 23:42:56.585044 [Byte1]: 35
8650 23:42:56.589375
8651 23:42:56.590008 Set Vref, RX VrefLevel [Byte0]: 36
8652 23:42:56.592466 [Byte1]: 36
8653 23:42:56.596597
8654 23:42:56.597163 Set Vref, RX VrefLevel [Byte0]: 37
8655 23:42:56.599960 [Byte1]: 37
8656 23:42:56.604891
8657 23:42:56.605562 Set Vref, RX VrefLevel [Byte0]: 38
8658 23:42:56.608357 [Byte1]: 38
8659 23:42:56.611689
8660 23:42:56.612150 Set Vref, RX VrefLevel [Byte0]: 39
8661 23:42:56.615200 [Byte1]: 39
8662 23:42:56.619151
8663 23:42:56.619628 Set Vref, RX VrefLevel [Byte0]: 40
8664 23:42:56.623150 [Byte1]: 40
8665 23:42:56.627107
8666 23:42:56.627576 Set Vref, RX VrefLevel [Byte0]: 41
8667 23:42:56.630432 [Byte1]: 41
8668 23:42:56.634464
8669 23:42:56.635033 Set Vref, RX VrefLevel [Byte0]: 42
8670 23:42:56.637984 [Byte1]: 42
8671 23:42:56.642110
8672 23:42:56.642577 Set Vref, RX VrefLevel [Byte0]: 43
8673 23:42:56.646012 [Byte1]: 43
8674 23:42:56.649970
8675 23:42:56.650537 Set Vref, RX VrefLevel [Byte0]: 44
8676 23:42:56.652954 [Byte1]: 44
8677 23:42:56.657068
8678 23:42:56.657695 Set Vref, RX VrefLevel [Byte0]: 45
8679 23:42:56.660630 [Byte1]: 45
8680 23:42:56.665079
8681 23:42:56.665694 Set Vref, RX VrefLevel [Byte0]: 46
8682 23:42:56.668194 [Byte1]: 46
8683 23:42:56.672638
8684 23:42:56.673207 Set Vref, RX VrefLevel [Byte0]: 47
8685 23:42:56.675266 [Byte1]: 47
8686 23:42:56.680041
8687 23:42:56.680615 Set Vref, RX VrefLevel [Byte0]: 48
8688 23:42:56.683310 [Byte1]: 48
8689 23:42:56.687982
8690 23:42:56.688553 Set Vref, RX VrefLevel [Byte0]: 49
8691 23:42:56.690891 [Byte1]: 49
8692 23:42:56.694644
8693 23:42:56.695223 Set Vref, RX VrefLevel [Byte0]: 50
8694 23:42:56.697884 [Byte1]: 50
8695 23:42:56.702154
8696 23:42:56.702616 Set Vref, RX VrefLevel [Byte0]: 51
8697 23:42:56.705755 [Byte1]: 51
8698 23:42:56.710068
8699 23:42:56.710686 Set Vref, RX VrefLevel [Byte0]: 52
8700 23:42:56.713262 [Byte1]: 52
8701 23:42:56.717280
8702 23:42:56.717916 Set Vref, RX VrefLevel [Byte0]: 53
8703 23:42:56.720442 [Byte1]: 53
8704 23:42:56.725640
8705 23:42:56.726211 Set Vref, RX VrefLevel [Byte0]: 54
8706 23:42:56.728020 [Byte1]: 54
8707 23:42:56.732386
8708 23:42:56.732912 Set Vref, RX VrefLevel [Byte0]: 55
8709 23:42:56.736174 [Byte1]: 55
8710 23:42:56.740319
8711 23:42:56.740890 Set Vref, RX VrefLevel [Byte0]: 56
8712 23:42:56.743404 [Byte1]: 56
8713 23:42:56.747588
8714 23:42:56.748082 Set Vref, RX VrefLevel [Byte0]: 57
8715 23:42:56.750917 [Byte1]: 57
8716 23:42:56.755239
8717 23:42:56.755808 Set Vref, RX VrefLevel [Byte0]: 58
8718 23:42:56.758415 [Byte1]: 58
8719 23:42:56.762878
8720 23:42:56.763456 Set Vref, RX VrefLevel [Byte0]: 59
8721 23:42:56.765793 [Byte1]: 59
8722 23:42:56.769916
8723 23:42:56.770391 Set Vref, RX VrefLevel [Byte0]: 60
8724 23:42:56.773748 [Byte1]: 60
8725 23:42:56.777967
8726 23:42:56.778443 Set Vref, RX VrefLevel [Byte0]: 61
8727 23:42:56.781055 [Byte1]: 61
8728 23:42:56.785659
8729 23:42:56.786237 Set Vref, RX VrefLevel [Byte0]: 62
8730 23:42:56.789016 [Byte1]: 62
8731 23:42:56.793171
8732 23:42:56.793790 Set Vref, RX VrefLevel [Byte0]: 63
8733 23:42:56.796433 [Byte1]: 63
8734 23:42:56.800470
8735 23:42:56.801036 Set Vref, RX VrefLevel [Byte0]: 64
8736 23:42:56.803531 [Byte1]: 64
8737 23:42:56.807571
8738 23:42:56.808048 Set Vref, RX VrefLevel [Byte0]: 65
8739 23:42:56.811819 [Byte1]: 65
8740 23:42:56.815746
8741 23:42:56.816321 Set Vref, RX VrefLevel [Byte0]: 66
8742 23:42:56.818407 [Byte1]: 66
8743 23:42:56.823112
8744 23:42:56.823682 Set Vref, RX VrefLevel [Byte0]: 67
8745 23:42:56.826210 [Byte1]: 67
8746 23:42:56.830091
8747 23:42:56.830583 Set Vref, RX VrefLevel [Byte0]: 68
8748 23:42:56.834045 [Byte1]: 68
8749 23:42:56.837692
8750 23:42:56.838171 Set Vref, RX VrefLevel [Byte0]: 69
8751 23:42:56.842027 [Byte1]: 69
8752 23:42:56.845545
8753 23:42:56.846092 Set Vref, RX VrefLevel [Byte0]: 70
8754 23:42:56.849022 [Byte1]: 70
8755 23:42:56.852969
8756 23:42:56.853646 Set Vref, RX VrefLevel [Byte0]: 71
8757 23:42:56.855871 [Byte1]: 71
8758 23:42:56.860524
8759 23:42:56.861088 Set Vref, RX VrefLevel [Byte0]: 72
8760 23:42:56.863593 [Byte1]: 72
8761 23:42:56.867713
8762 23:42:56.868273 Set Vref, RX VrefLevel [Byte0]: 73
8763 23:42:56.871285 [Byte1]: 73
8764 23:42:56.875461
8765 23:42:56.876089 Set Vref, RX VrefLevel [Byte0]: 74
8766 23:42:56.878694 [Byte1]: 74
8767 23:42:56.883639
8768 23:42:56.884209 Set Vref, RX VrefLevel [Byte0]: 75
8769 23:42:56.886995 [Byte1]: 75
8770 23:42:56.890580
8771 23:42:56.891152 Final RX Vref Byte 0 = 58 to rank0
8772 23:42:56.894502 Final RX Vref Byte 1 = 57 to rank0
8773 23:42:56.897677 Final RX Vref Byte 0 = 58 to rank1
8774 23:42:56.900760 Final RX Vref Byte 1 = 57 to rank1==
8775 23:42:56.903781 Dram Type= 6, Freq= 0, CH_1, rank 0
8776 23:42:56.910707 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8777 23:42:56.911250 ==
8778 23:42:56.911632 DQS Delay:
8779 23:42:56.911983 DQS0 = 0, DQS1 = 0
8780 23:42:56.913654 DQM Delay:
8781 23:42:56.914122 DQM0 = 134, DQM1 = 131
8782 23:42:56.917170 DQ Delay:
8783 23:42:56.920493 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8784 23:42:56.923752 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8785 23:42:56.926937 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8786 23:42:56.930093 DQ12 =140, DQ13 =140, DQ14 =140, DQ15 =140
8787 23:42:56.930518
8788 23:42:56.930854
8789 23:42:56.931165
8790 23:42:56.933991 [DramC_TX_OE_Calibration] TA2
8791 23:42:56.937550 Original DQ_B0 (3 6) =30, OEN = 27
8792 23:42:56.940225 Original DQ_B1 (3 6) =30, OEN = 27
8793 23:42:56.943840 24, 0x0, End_B0=24 End_B1=24
8794 23:42:56.944379 25, 0x0, End_B0=25 End_B1=25
8795 23:42:56.947412 26, 0x0, End_B0=26 End_B1=26
8796 23:42:56.950570 27, 0x0, End_B0=27 End_B1=27
8797 23:42:56.953791 28, 0x0, End_B0=28 End_B1=28
8798 23:42:56.954308 29, 0x0, End_B0=29 End_B1=29
8799 23:42:56.957221 30, 0x0, End_B0=30 End_B1=30
8800 23:42:56.960384 31, 0x4141, End_B0=30 End_B1=30
8801 23:42:56.963904 Byte0 end_step=30 best_step=27
8802 23:42:56.967163 Byte1 end_step=30 best_step=27
8803 23:42:56.970553 Byte0 TX OE(2T, 0.5T) = (3, 3)
8804 23:42:56.971023 Byte1 TX OE(2T, 0.5T) = (3, 3)
8805 23:42:56.974120
8806 23:42:56.974586
8807 23:42:56.980634 [DQSOSCAuto] RK0, (LSB)MR18= 0x1724, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8808 23:42:56.984026 CH1 RK0: MR19=303, MR18=1724
8809 23:42:56.990144 CH1_RK0: MR19=0x303, MR18=0x1724, DQSOSC=391, MR23=63, INC=24, DEC=16
8810 23:42:56.990575
8811 23:42:56.994369 ----->DramcWriteLeveling(PI) begin...
8812 23:42:56.994965 ==
8813 23:42:56.997036 Dram Type= 6, Freq= 0, CH_1, rank 1
8814 23:42:57.000336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8815 23:42:57.000931 ==
8816 23:42:57.003357 Write leveling (Byte 0): 27 => 27
8817 23:42:57.007161 Write leveling (Byte 1): 29 => 29
8818 23:42:57.010934 DramcWriteLeveling(PI) end<-----
8819 23:42:57.011512
8820 23:42:57.011888 ==
8821 23:42:57.014006 Dram Type= 6, Freq= 0, CH_1, rank 1
8822 23:42:57.017151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8823 23:42:57.017759 ==
8824 23:42:57.020738 [Gating] SW mode calibration
8825 23:42:57.027162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8826 23:42:57.033945 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8827 23:42:57.036973 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 23:42:57.040608 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 23:42:57.046865 1 4 8 | B1->B0 | 2929 2323 | 1 0 | (1 1) (0 0)
8830 23:42:57.050406 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8831 23:42:57.054003 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8832 23:42:57.060453 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8833 23:42:57.063524 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8834 23:42:57.066862 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8835 23:42:57.073775 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8836 23:42:57.076971 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8837 23:42:57.080176 1 5 8 | B1->B0 | 3232 3434 | 0 1 | (0 1) (1 1)
8838 23:42:57.086870 1 5 12 | B1->B0 | 2323 2e2e | 0 1 | (1 0) (1 0)
8839 23:42:57.090208 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8840 23:42:57.093633 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8841 23:42:57.100153 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8842 23:42:57.103721 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8843 23:42:57.106569 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8844 23:42:57.113217 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8845 23:42:57.116547 1 6 8 | B1->B0 | 3434 2323 | 1 0 | (0 0) (0 0)
8846 23:42:57.120029 1 6 12 | B1->B0 | 4646 3f3f | 0 0 | (0 0) (0 0)
8847 23:42:57.126351 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8848 23:42:57.129752 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8849 23:42:57.133218 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8850 23:42:57.139982 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8851 23:42:57.143115 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8852 23:42:57.146600 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8853 23:42:57.150138 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8854 23:42:57.156291 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8855 23:42:57.159836 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8856 23:42:57.163746 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8857 23:42:57.169786 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8858 23:42:57.172994 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8859 23:42:57.176320 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8860 23:42:57.183091 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8861 23:42:57.186734 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8862 23:42:57.189998 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8863 23:42:57.196459 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8864 23:42:57.199768 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8865 23:42:57.203159 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8866 23:42:57.209614 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 23:42:57.213096 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 23:42:57.216238 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8869 23:42:57.223185 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8870 23:42:57.226251 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8871 23:42:57.229452 Total UI for P1: 0, mck2ui 16
8872 23:42:57.232437 best dqsien dly found for B1: ( 1, 9, 6)
8873 23:42:57.236419 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8874 23:42:57.242627 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8875 23:42:57.243205 Total UI for P1: 0, mck2ui 16
8876 23:42:57.249417 best dqsien dly found for B0: ( 1, 9, 14)
8877 23:42:57.252448 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8878 23:42:57.256197 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8879 23:42:57.256684
8880 23:42:57.259699 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8881 23:42:57.262394 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8882 23:42:57.265927 [Gating] SW calibration Done
8883 23:42:57.266394 ==
8884 23:42:57.269174 Dram Type= 6, Freq= 0, CH_1, rank 1
8885 23:42:57.272504 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8886 23:42:57.273024 ==
8887 23:42:57.276157 RX Vref Scan: 0
8888 23:42:57.276716
8889 23:42:57.277219 RX Vref 0 -> 0, step: 1
8890 23:42:57.277805
8891 23:42:57.279323 RX Delay 0 -> 252, step: 8
8892 23:42:57.282608 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8893 23:42:57.289852 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8894 23:42:57.293148 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8895 23:42:57.296073 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8896 23:42:57.299480 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8897 23:42:57.302714 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8898 23:42:57.309044 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8899 23:42:57.312515 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8900 23:42:57.315767 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8901 23:42:57.318895 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8902 23:42:57.322129 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8903 23:42:57.328821 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8904 23:42:57.332955 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8905 23:42:57.335713 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8906 23:42:57.338789 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8907 23:42:57.342178 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8908 23:42:57.345403 ==
8909 23:42:57.345946 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 23:42:57.352725 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 23:42:57.353301 ==
8912 23:42:57.353731 DQS Delay:
8913 23:42:57.355562 DQS0 = 0, DQS1 = 0
8914 23:42:57.356023 DQM Delay:
8915 23:42:57.358866 DQM0 = 136, DQM1 = 133
8916 23:42:57.359401 DQ Delay:
8917 23:42:57.362298 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8918 23:42:57.365883 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8919 23:42:57.369491 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8920 23:42:57.372178 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8921 23:42:57.372643
8922 23:42:57.373012
8923 23:42:57.373392 ==
8924 23:42:57.375684 Dram Type= 6, Freq= 0, CH_1, rank 1
8925 23:42:57.382249 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8926 23:42:57.382716 ==
8927 23:42:57.383085
8928 23:42:57.383424
8929 23:42:57.383749 TX Vref Scan disable
8930 23:42:57.385222 == TX Byte 0 ==
8931 23:42:57.388901 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8932 23:42:57.396117 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8933 23:42:57.396681 == TX Byte 1 ==
8934 23:42:57.398892 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8935 23:42:57.405398 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8936 23:42:57.405994 ==
8937 23:42:57.409035 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 23:42:57.411949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 23:42:57.412505 ==
8940 23:42:57.424623
8941 23:42:57.427464 TX Vref early break, caculate TX vref
8942 23:42:57.431153 TX Vref=16, minBit 0, minWin=23, winSum=381
8943 23:42:57.434377 TX Vref=18, minBit 0, minWin=23, winSum=394
8944 23:42:57.437955 TX Vref=20, minBit 2, minWin=23, winSum=400
8945 23:42:57.440899 TX Vref=22, minBit 0, minWin=25, winSum=410
8946 23:42:57.444759 TX Vref=24, minBit 0, minWin=25, winSum=412
8947 23:42:57.451161 TX Vref=26, minBit 0, minWin=25, winSum=425
8948 23:42:57.453931 TX Vref=28, minBit 0, minWin=26, winSum=427
8949 23:42:57.457193 TX Vref=30, minBit 1, minWin=25, winSum=419
8950 23:42:57.460858 TX Vref=32, minBit 0, minWin=25, winSum=412
8951 23:42:57.464228 TX Vref=34, minBit 0, minWin=24, winSum=403
8952 23:42:57.470606 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
8953 23:42:57.471169
8954 23:42:57.473690 Final TX Range 0 Vref 28
8955 23:42:57.474159
8956 23:42:57.474528 ==
8957 23:42:57.477688 Dram Type= 6, Freq= 0, CH_1, rank 1
8958 23:42:57.480746 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8959 23:42:57.481310 ==
8960 23:42:57.481749
8961 23:42:57.482108
8962 23:42:57.484329 TX Vref Scan disable
8963 23:42:57.490721 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =285/100 ps
8964 23:42:57.491279 == TX Byte 0 ==
8965 23:42:57.493834 u2DelayCellOfst[0]=17 cells (5 PI)
8966 23:42:57.497615 u2DelayCellOfst[1]=10 cells (3 PI)
8967 23:42:57.500628 u2DelayCellOfst[2]=0 cells (0 PI)
8968 23:42:57.504018 u2DelayCellOfst[3]=6 cells (2 PI)
8969 23:42:57.507355 u2DelayCellOfst[4]=6 cells (2 PI)
8970 23:42:57.510723 u2DelayCellOfst[5]=20 cells (6 PI)
8971 23:42:57.513950 u2DelayCellOfst[6]=20 cells (6 PI)
8972 23:42:57.516881 u2DelayCellOfst[7]=6 cells (2 PI)
8973 23:42:57.520778 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8974 23:42:57.523448 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8975 23:42:57.527202 == TX Byte 1 ==
8976 23:42:57.527801 u2DelayCellOfst[8]=0 cells (0 PI)
8977 23:42:57.530355 u2DelayCellOfst[9]=3 cells (1 PI)
8978 23:42:57.533543 u2DelayCellOfst[10]=10 cells (3 PI)
8979 23:42:57.537307 u2DelayCellOfst[11]=6 cells (2 PI)
8980 23:42:57.540675 u2DelayCellOfst[12]=13 cells (4 PI)
8981 23:42:57.544315 u2DelayCellOfst[13]=17 cells (5 PI)
8982 23:42:57.547182 u2DelayCellOfst[14]=17 cells (5 PI)
8983 23:42:57.550720 u2DelayCellOfst[15]=17 cells (5 PI)
8984 23:42:57.553568 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8985 23:42:57.559734 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8986 23:42:57.560205 DramC Write-DBI on
8987 23:42:57.560581 ==
8988 23:42:57.563341 Dram Type= 6, Freq= 0, CH_1, rank 1
8989 23:42:57.566923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8990 23:42:57.569918 ==
8991 23:42:57.570485
8992 23:42:57.570857
8993 23:42:57.571200 TX Vref Scan disable
8994 23:42:57.573371 == TX Byte 0 ==
8995 23:42:57.577148 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8996 23:42:57.580083 == TX Byte 1 ==
8997 23:42:57.583265 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8998 23:42:57.587367 DramC Write-DBI off
8999 23:42:57.587936
9000 23:42:57.588358 [DATLAT]
9001 23:42:57.588857 Freq=1600, CH1 RK1
9002 23:42:57.589393
9003 23:42:57.590264 DATLAT Default: 0xf
9004 23:42:57.590652 0, 0xFFFF, sum = 0
9005 23:42:57.593789 1, 0xFFFF, sum = 0
9006 23:42:57.596693 2, 0xFFFF, sum = 0
9007 23:42:57.597162 3, 0xFFFF, sum = 0
9008 23:42:57.600330 4, 0xFFFF, sum = 0
9009 23:42:57.600903 5, 0xFFFF, sum = 0
9010 23:42:57.603346 6, 0xFFFF, sum = 0
9011 23:42:57.603913 7, 0xFFFF, sum = 0
9012 23:42:57.606599 8, 0xFFFF, sum = 0
9013 23:42:57.607076 9, 0xFFFF, sum = 0
9014 23:42:57.609757 10, 0xFFFF, sum = 0
9015 23:42:57.610233 11, 0xFFFF, sum = 0
9016 23:42:57.613361 12, 0xFFFF, sum = 0
9017 23:42:57.613998 13, 0xFFFF, sum = 0
9018 23:42:57.616846 14, 0x0, sum = 1
9019 23:42:57.617651 15, 0x0, sum = 2
9020 23:42:57.619918 16, 0x0, sum = 3
9021 23:42:57.620484 17, 0x0, sum = 4
9022 23:42:57.623459 best_step = 15
9023 23:42:57.624033
9024 23:42:57.624409 ==
9025 23:42:57.626698 Dram Type= 6, Freq= 0, CH_1, rank 1
9026 23:42:57.629649 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9027 23:42:57.630125 ==
9028 23:42:57.633377 RX Vref Scan: 0
9029 23:42:57.633940
9030 23:42:57.634315 RX Vref 0 -> 0, step: 1
9031 23:42:57.634662
9032 23:42:57.636351 RX Delay 19 -> 252, step: 4
9033 23:42:57.639752 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9034 23:42:57.646615 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9035 23:42:57.650436 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9036 23:42:57.653281 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9037 23:42:57.656829 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9038 23:42:57.659416 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9039 23:42:57.666896 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9040 23:42:57.669953 iDelay=195, Bit 7, Center 132 (79 ~ 186) 108
9041 23:42:57.672828 iDelay=195, Bit 8, Center 118 (67 ~ 170) 104
9042 23:42:57.676568 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9043 23:42:57.679431 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9044 23:42:57.685947 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9045 23:42:57.689821 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9046 23:42:57.693019 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9047 23:42:57.696425 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9048 23:42:57.699345 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9049 23:42:57.702643 ==
9050 23:42:57.706300 Dram Type= 6, Freq= 0, CH_1, rank 1
9051 23:42:57.709127 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9052 23:42:57.709636 ==
9053 23:42:57.710024 DQS Delay:
9054 23:42:57.712914 DQS0 = 0, DQS1 = 0
9055 23:42:57.713476 DQM Delay:
9056 23:42:57.716108 DQM0 = 133, DQM1 = 130
9057 23:42:57.716579 DQ Delay:
9058 23:42:57.719175 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9059 23:42:57.722350 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =132
9060 23:42:57.726268 DQ8 =118, DQ9 =118, DQ10 =132, DQ11 =124
9061 23:42:57.729410 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9062 23:42:57.730050
9063 23:42:57.730430
9064 23:42:57.730875
9065 23:42:57.732423 [DramC_TX_OE_Calibration] TA2
9066 23:42:57.735643 Original DQ_B0 (3 6) =30, OEN = 27
9067 23:42:57.738942 Original DQ_B1 (3 6) =30, OEN = 27
9068 23:42:57.742498 24, 0x0, End_B0=24 End_B1=24
9069 23:42:57.745923 25, 0x0, End_B0=25 End_B1=25
9070 23:42:57.746488 26, 0x0, End_B0=26 End_B1=26
9071 23:42:57.749529 27, 0x0, End_B0=27 End_B1=27
9072 23:42:57.752611 28, 0x0, End_B0=28 End_B1=28
9073 23:42:57.756254 29, 0x0, End_B0=29 End_B1=29
9074 23:42:57.759069 30, 0x0, End_B0=30 End_B1=30
9075 23:42:57.759574 31, 0x4545, End_B0=30 End_B1=30
9076 23:42:57.762541 Byte0 end_step=30 best_step=27
9077 23:42:57.765801 Byte1 end_step=30 best_step=27
9078 23:42:57.769204 Byte0 TX OE(2T, 0.5T) = (3, 3)
9079 23:42:57.772429 Byte1 TX OE(2T, 0.5T) = (3, 3)
9080 23:42:57.772887
9081 23:42:57.773253
9082 23:42:57.779097 [DQSOSCAuto] RK1, (LSB)MR18= 0x2309, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9083 23:42:57.782276 CH1 RK1: MR19=303, MR18=2309
9084 23:42:57.789242 CH1_RK1: MR19=0x303, MR18=0x2309, DQSOSC=392, MR23=63, INC=24, DEC=16
9085 23:42:57.792322 [RxdqsGatingPostProcess] freq 1600
9086 23:42:57.798752 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9087 23:42:57.799437 best DQS0 dly(2T, 0.5T) = (1, 1)
9088 23:42:57.802569 best DQS1 dly(2T, 0.5T) = (1, 1)
9089 23:42:57.805743 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9090 23:42:57.808871 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9091 23:42:57.812357 best DQS0 dly(2T, 0.5T) = (1, 1)
9092 23:42:57.815870 best DQS1 dly(2T, 0.5T) = (1, 1)
9093 23:42:57.818731 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9094 23:42:57.822272 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9095 23:42:57.825485 Pre-setting of DQS Precalculation
9096 23:42:57.828914 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9097 23:42:57.839238 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9098 23:42:57.845742 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9099 23:42:57.846305
9100 23:42:57.846679
9101 23:42:57.848720 [Calibration Summary] 3200 Mbps
9102 23:42:57.849189 CH 0, Rank 0
9103 23:42:57.851989 SW Impedance : PASS
9104 23:42:57.852462 DUTY Scan : NO K
9105 23:42:57.855140 ZQ Calibration : PASS
9106 23:42:57.858575 Jitter Meter : NO K
9107 23:42:57.859063 CBT Training : PASS
9108 23:42:57.861787 Write leveling : PASS
9109 23:42:57.865531 RX DQS gating : PASS
9110 23:42:57.866032 RX DQ/DQS(RDDQC) : PASS
9111 23:42:57.868636 TX DQ/DQS : PASS
9112 23:42:57.869338 RX DATLAT : PASS
9113 23:42:57.872061 RX DQ/DQS(Engine): PASS
9114 23:42:57.875436 TX OE : PASS
9115 23:42:57.875906 All Pass.
9116 23:42:57.876274
9117 23:42:57.876616 CH 0, Rank 1
9118 23:42:57.878378 SW Impedance : PASS
9119 23:42:57.881531 DUTY Scan : NO K
9120 23:42:57.882046 ZQ Calibration : PASS
9121 23:42:57.885785 Jitter Meter : NO K
9122 23:42:57.888976 CBT Training : PASS
9123 23:42:57.889537 Write leveling : PASS
9124 23:42:57.892203 RX DQS gating : PASS
9125 23:42:57.895471 RX DQ/DQS(RDDQC) : PASS
9126 23:42:57.896031 TX DQ/DQS : PASS
9127 23:42:57.898330 RX DATLAT : PASS
9128 23:42:57.901983 RX DQ/DQS(Engine): PASS
9129 23:42:57.902447 TX OE : PASS
9130 23:42:57.905173 All Pass.
9131 23:42:57.905671
9132 23:42:57.906054 CH 1, Rank 0
9133 23:42:57.908684 SW Impedance : PASS
9134 23:42:57.909174 DUTY Scan : NO K
9135 23:42:57.911917 ZQ Calibration : PASS
9136 23:42:57.915789 Jitter Meter : NO K
9137 23:42:57.916379 CBT Training : PASS
9138 23:42:57.918620 Write leveling : PASS
9139 23:42:57.919137 RX DQS gating : PASS
9140 23:42:57.922127 RX DQ/DQS(RDDQC) : PASS
9141 23:42:57.925101 TX DQ/DQS : PASS
9142 23:42:57.925831 RX DATLAT : PASS
9143 23:42:57.929000 RX DQ/DQS(Engine): PASS
9144 23:42:57.932408 TX OE : PASS
9145 23:42:57.932985 All Pass.
9146 23:42:57.933359
9147 23:42:57.933755 CH 1, Rank 1
9148 23:42:57.935173 SW Impedance : PASS
9149 23:42:57.938489 DUTY Scan : NO K
9150 23:42:57.938963 ZQ Calibration : PASS
9151 23:42:57.941878 Jitter Meter : NO K
9152 23:42:57.945102 CBT Training : PASS
9153 23:42:57.945765 Write leveling : PASS
9154 23:42:57.948751 RX DQS gating : PASS
9155 23:42:57.952002 RX DQ/DQS(RDDQC) : PASS
9156 23:42:57.952469 TX DQ/DQS : PASS
9157 23:42:57.955104 RX DATLAT : PASS
9158 23:42:57.958240 RX DQ/DQS(Engine): PASS
9159 23:42:57.958708 TX OE : PASS
9160 23:42:57.959083 All Pass.
9161 23:42:57.961928
9162 23:42:57.962395 DramC Write-DBI on
9163 23:42:57.965076 PER_BANK_REFRESH: Hybrid Mode
9164 23:42:57.965501 TX_TRACKING: ON
9165 23:42:57.974885 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9166 23:42:57.981697 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9167 23:42:57.991733 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9168 23:42:57.995205 [FAST_K] Save calibration result to emmc
9169 23:42:57.998113 sync common calibartion params.
9170 23:42:57.998578 sync cbt_mode0:1, 1:1
9171 23:42:58.001784 dram_init: ddr_geometry: 2
9172 23:42:58.004867 dram_init: ddr_geometry: 2
9173 23:42:58.005433 dram_init: ddr_geometry: 2
9174 23:42:58.008330 0:dram_rank_size:100000000
9175 23:42:58.012008 1:dram_rank_size:100000000
9176 23:42:58.014555 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9177 23:42:58.018064 DFS_SHUFFLE_HW_MODE: ON
9178 23:42:58.021976 dramc_set_vcore_voltage set vcore to 725000
9179 23:42:58.024942 Read voltage for 1600, 0
9180 23:42:58.025516 Vio18 = 0
9181 23:42:58.028085 Vcore = 725000
9182 23:42:58.028659 Vdram = 0
9183 23:42:58.029030 Vddq = 0
9184 23:42:58.029374 Vmddr = 0
9185 23:42:58.031477 switch to 3200 Mbps bootup
9186 23:42:58.034722 [DramcRunTimeConfig]
9187 23:42:58.035191 PHYPLL
9188 23:42:58.038288 DPM_CONTROL_AFTERK: ON
9189 23:42:58.038756 PER_BANK_REFRESH: ON
9190 23:42:58.041173 REFRESH_OVERHEAD_REDUCTION: ON
9191 23:42:58.044843 CMD_PICG_NEW_MODE: OFF
9192 23:42:58.045309 XRTWTW_NEW_MODE: ON
9193 23:42:58.048020 XRTRTR_NEW_MODE: ON
9194 23:42:58.048669 TX_TRACKING: ON
9195 23:42:58.051205 RDSEL_TRACKING: OFF
9196 23:42:58.054700 DQS Precalculation for DVFS: ON
9197 23:42:58.055168 RX_TRACKING: OFF
9198 23:42:58.058371 HW_GATING DBG: ON
9199 23:42:58.058948 ZQCS_ENABLE_LP4: ON
9200 23:42:58.061853 RX_PICG_NEW_MODE: ON
9201 23:42:58.062322 TX_PICG_NEW_MODE: ON
9202 23:42:58.064620 ENABLE_RX_DCM_DPHY: ON
9203 23:42:58.067783 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9204 23:42:58.071404 DUMMY_READ_FOR_TRACKING: OFF
9205 23:42:58.071978 !!! SPM_CONTROL_AFTERK: OFF
9206 23:42:58.074469 !!! SPM could not control APHY
9207 23:42:58.077860 IMPEDANCE_TRACKING: ON
9208 23:42:58.078431 TEMP_SENSOR: ON
9209 23:42:58.081554 HW_SAVE_FOR_SR: OFF
9210 23:42:58.084680 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9211 23:42:58.088414 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9212 23:42:58.088982 Read ODT Tracking: ON
9213 23:42:58.091560 Refresh Rate DeBounce: ON
9214 23:42:58.094293 DFS_NO_QUEUE_FLUSH: ON
9215 23:42:58.097716 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9216 23:42:58.098291 ENABLE_DFS_RUNTIME_MRW: OFF
9217 23:42:58.101281 DDR_RESERVE_NEW_MODE: ON
9218 23:42:58.104056 MR_CBT_SWITCH_FREQ: ON
9219 23:42:58.104524 =========================
9220 23:42:58.124973 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9221 23:42:58.128217 dram_init: ddr_geometry: 2
9222 23:42:58.146248 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9223 23:42:58.149372 dram_init: dram init end (result: 0)
9224 23:42:58.156174 DRAM-K: Full calibration passed in 24516 msecs
9225 23:42:58.159115 MRC: failed to locate region type 0.
9226 23:42:58.159674 DRAM rank0 size:0x100000000,
9227 23:42:58.162396 DRAM rank1 size=0x100000000
9228 23:42:58.173024 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9229 23:42:58.179315 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9230 23:42:58.186127 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9231 23:42:58.193259 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9232 23:42:58.195986 DRAM rank0 size:0x100000000,
9233 23:42:58.199334 DRAM rank1 size=0x100000000
9234 23:42:58.199902 CBMEM:
9235 23:42:58.202798 IMD: root @ 0xfffff000 254 entries.
9236 23:42:58.206489 IMD: root @ 0xffffec00 62 entries.
9237 23:42:58.209355 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9238 23:42:58.212373 WARNING: RO_VPD is uninitialized or empty.
9239 23:42:58.219079 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9240 23:42:58.226549 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9241 23:42:58.238901 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9242 23:42:58.250661 BS: romstage times (exec / console): total (unknown) / 24037 ms
9243 23:42:58.251235
9244 23:42:58.251609
9245 23:42:58.260197 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9246 23:42:58.263413 ARM64: Exception handlers installed.
9247 23:42:58.267309 ARM64: Testing exception
9248 23:42:58.270224 ARM64: Done test exception
9249 23:42:58.270686 Enumerating buses...
9250 23:42:58.273858 Show all devs... Before device enumeration.
9251 23:42:58.276722 Root Device: enabled 1
9252 23:42:58.280829 CPU_CLUSTER: 0: enabled 1
9253 23:42:58.281482 CPU: 00: enabled 1
9254 23:42:58.283521 Compare with tree...
9255 23:42:58.283984 Root Device: enabled 1
9256 23:42:58.286885 CPU_CLUSTER: 0: enabled 1
9257 23:42:58.290281 CPU: 00: enabled 1
9258 23:42:58.290748 Root Device scanning...
9259 23:42:58.293630 scan_static_bus for Root Device
9260 23:42:58.296858 CPU_CLUSTER: 0 enabled
9261 23:42:58.299818 scan_static_bus for Root Device done
9262 23:42:58.303697 scan_bus: bus Root Device finished in 8 msecs
9263 23:42:58.304271 done
9264 23:42:58.310182 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9265 23:42:58.313551 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9266 23:42:58.319810 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9267 23:42:58.323108 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9268 23:42:58.326571 Allocating resources...
9269 23:42:58.330015 Reading resources...
9270 23:42:58.333222 Root Device read_resources bus 0 link: 0
9271 23:42:58.333741 DRAM rank0 size:0x100000000,
9272 23:42:58.336604 DRAM rank1 size=0x100000000
9273 23:42:58.340553 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9274 23:42:58.343600 CPU: 00 missing read_resources
9275 23:42:58.346353 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9276 23:42:58.353937 Root Device read_resources bus 0 link: 0 done
9277 23:42:58.354505 Done reading resources.
9278 23:42:58.360042 Show resources in subtree (Root Device)...After reading.
9279 23:42:58.363128 Root Device child on link 0 CPU_CLUSTER: 0
9280 23:42:58.367234 CPU_CLUSTER: 0 child on link 0 CPU: 00
9281 23:42:58.376826 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9282 23:42:58.377440 CPU: 00
9283 23:42:58.380564 Root Device assign_resources, bus 0 link: 0
9284 23:42:58.383657 CPU_CLUSTER: 0 missing set_resources
9285 23:42:58.386458 Root Device assign_resources, bus 0 link: 0 done
9286 23:42:58.389972 Done setting resources.
9287 23:42:58.396932 Show resources in subtree (Root Device)...After assigning values.
9288 23:42:58.399780 Root Device child on link 0 CPU_CLUSTER: 0
9289 23:42:58.403062 CPU_CLUSTER: 0 child on link 0 CPU: 00
9290 23:42:58.413363 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9291 23:42:58.413994 CPU: 00
9292 23:42:58.416606 Done allocating resources.
9293 23:42:58.419711 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9294 23:42:58.423173 Enabling resources...
9295 23:42:58.423638 done.
9296 23:42:58.430023 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9297 23:42:58.430603 Initializing devices...
9298 23:42:58.432966 Root Device init
9299 23:42:58.433429 init hardware done!
9300 23:42:58.437213 0x00000018: ctrlr->caps
9301 23:42:58.440350 52.000 MHz: ctrlr->f_max
9302 23:42:58.440919 0.400 MHz: ctrlr->f_min
9303 23:42:58.443180 0x40ff8080: ctrlr->voltages
9304 23:42:58.443751 sclk: 390625
9305 23:42:58.446261 Bus Width = 1
9306 23:42:58.446728 sclk: 390625
9307 23:42:58.447199 Bus Width = 1
9308 23:42:58.450389 Early init status = 3
9309 23:42:58.453042 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9310 23:42:58.458178 in-header: 03 fc 00 00 01 00 00 00
9311 23:42:58.461371 in-data: 00
9312 23:42:58.464549 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9313 23:42:58.469516 in-header: 03 fd 00 00 00 00 00 00
9314 23:42:58.472401 in-data:
9315 23:42:58.476074 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9316 23:42:58.479403 in-header: 03 fc 00 00 01 00 00 00
9317 23:42:58.482489 in-data: 00
9318 23:42:58.485668 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9319 23:42:58.490505 in-header: 03 fd 00 00 00 00 00 00
9320 23:42:58.493838 in-data:
9321 23:42:58.497001 [SSUSB] Setting up USB HOST controller...
9322 23:42:58.500772 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9323 23:42:58.504178 [SSUSB] phy power-on done.
9324 23:42:58.506973 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9325 23:42:58.513511 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9326 23:42:58.516752 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9327 23:42:58.523243 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9328 23:42:58.530242 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9329 23:42:58.537114 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9330 23:42:58.543664 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9331 23:42:58.550306 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9332 23:42:58.553257 SPM: binary array size = 0x9dc
9333 23:42:58.557019 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9334 23:42:58.563393 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9335 23:42:58.570218 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9336 23:42:58.573273 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9337 23:42:58.579907 configure_display: Starting display init
9338 23:42:58.614017 anx7625_power_on_init: Init interface.
9339 23:42:58.616937 anx7625_disable_pd_protocol: Disabled PD feature.
9340 23:42:58.620418 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9341 23:42:58.648001 anx7625_start_dp_work: Secure OCM version=00
9342 23:42:58.651171 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9343 23:42:58.666538 sp_tx_get_edid_block: EDID Block = 1
9344 23:42:58.768555 Extracted contents:
9345 23:42:58.772296 header: 00 ff ff ff ff ff ff 00
9346 23:42:58.775344 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9347 23:42:58.778425 version: 01 04
9348 23:42:58.782181 basic params: 95 1f 11 78 0a
9349 23:42:58.785476 chroma info: 76 90 94 55 54 90 27 21 50 54
9350 23:42:58.788217 established: 00 00 00
9351 23:42:58.795146 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9352 23:42:58.798321 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9353 23:42:58.805222 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9354 23:42:58.811437 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9355 23:42:58.818495 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9356 23:42:58.821423 extensions: 00
9357 23:42:58.822018 checksum: fb
9358 23:42:58.822388
9359 23:42:58.824968 Manufacturer: IVO Model 57d Serial Number 0
9360 23:42:58.828417 Made week 0 of 2020
9361 23:42:58.828876 EDID version: 1.4
9362 23:42:58.831450 Digital display
9363 23:42:58.834629 6 bits per primary color channel
9364 23:42:58.835095 DisplayPort interface
9365 23:42:58.837894 Maximum image size: 31 cm x 17 cm
9366 23:42:58.841153 Gamma: 220%
9367 23:42:58.841635 Check DPMS levels
9368 23:42:58.844842 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9369 23:42:58.851610 First detailed timing is preferred timing
9370 23:42:58.852184 Established timings supported:
9371 23:42:58.854992 Standard timings supported:
9372 23:42:58.858151 Detailed timings
9373 23:42:58.861395 Hex of detail: 383680a07038204018303c0035ae10000019
9374 23:42:58.865242 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9375 23:42:58.871520 0780 0798 07c8 0820 hborder 0
9376 23:42:58.874521 0438 043b 0447 0458 vborder 0
9377 23:42:58.877727 -hsync -vsync
9378 23:42:58.878143 Did detailed timing
9379 23:42:58.884946 Hex of detail: 000000000000000000000000000000000000
9380 23:42:58.885465 Manufacturer-specified data, tag 0
9381 23:42:58.891032 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9382 23:42:58.895057 ASCII string: InfoVision
9383 23:42:58.897559 Hex of detail: 000000fe00523134304e574635205248200a
9384 23:42:58.901121 ASCII string: R140NWF5 RH
9385 23:42:58.901731 Checksum
9386 23:42:58.904394 Checksum: 0xfb (valid)
9387 23:42:58.907930 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9388 23:42:58.910842 DSI data_rate: 832800000 bps
9389 23:42:58.917794 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9390 23:42:58.921281 anx7625_parse_edid: pixelclock(138800).
9391 23:42:58.924827 hactive(1920), hsync(48), hfp(24), hbp(88)
9392 23:42:58.927680 vactive(1080), vsync(12), vfp(3), vbp(17)
9393 23:42:58.930876 anx7625_dsi_config: config dsi.
9394 23:42:58.937740 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9395 23:42:58.951009 anx7625_dsi_config: success to config DSI
9396 23:42:58.954542 anx7625_dp_start: MIPI phy setup OK.
9397 23:42:58.957442 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9398 23:42:58.960787 mtk_ddp_mode_set invalid vrefresh 60
9399 23:42:58.964032 main_disp_path_setup
9400 23:42:58.964585 ovl_layer_smi_id_en
9401 23:42:58.967343 ovl_layer_smi_id_en
9402 23:42:58.967908 ccorr_config
9403 23:42:58.968276 aal_config
9404 23:42:58.970963 gamma_config
9405 23:42:58.971547 postmask_config
9406 23:42:58.974157 dither_config
9407 23:42:58.977379 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9408 23:42:58.984242 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9409 23:42:58.987300 Root Device init finished in 551 msecs
9410 23:42:58.987857 CPU_CLUSTER: 0 init
9411 23:42:58.996983 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9412 23:42:59.000278 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9413 23:42:59.003775 APU_MBOX 0x190000b0 = 0x10001
9414 23:42:59.007495 APU_MBOX 0x190001b0 = 0x10001
9415 23:42:59.010409 APU_MBOX 0x190005b0 = 0x10001
9416 23:42:59.014117 APU_MBOX 0x190006b0 = 0x10001
9417 23:42:59.017526 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9418 23:42:59.029633 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9419 23:42:59.042194 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9420 23:42:59.048755 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9421 23:42:59.060376 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9422 23:42:59.069625 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9423 23:42:59.073468 CPU_CLUSTER: 0 init finished in 81 msecs
9424 23:42:59.076250 Devices initialized
9425 23:42:59.079942 Show all devs... After init.
9426 23:42:59.080691 Root Device: enabled 1
9427 23:42:59.083036 CPU_CLUSTER: 0: enabled 1
9428 23:42:59.086180 CPU: 00: enabled 1
9429 23:42:59.090057 BS: BS_DEV_INIT run times (exec / console): 209 / 447 ms
9430 23:42:59.092990 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9431 23:42:59.096396 ELOG: NV offset 0x57f000 size 0x1000
9432 23:42:59.103109 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9433 23:42:59.109661 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9434 23:42:59.112838 ELOG: Event(17) added with size 13 at 2023-12-03 23:40:45 UTC
9435 23:42:59.116636 out: cmd=0x121: 03 db 21 01 00 00 00 00
9436 23:42:59.120468 in-header: 03 9e 00 00 2c 00 00 00
9437 23:42:59.133313 in-data: c1 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9438 23:42:59.140003 ELOG: Event(A1) added with size 10 at 2023-12-03 23:40:45 UTC
9439 23:42:59.146598 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9440 23:42:59.152825 ELOG: Event(A0) added with size 9 at 2023-12-03 23:40:45 UTC
9441 23:42:59.156070 elog_add_boot_reason: Logged dev mode boot
9442 23:42:59.159406 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9443 23:42:59.163092 Finalize devices...
9444 23:42:59.163667 Devices finalized
9445 23:42:59.169617 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9446 23:42:59.172978 Writing coreboot table at 0xffe64000
9447 23:42:59.176301 0. 000000000010a000-0000000000113fff: RAMSTAGE
9448 23:42:59.179401 1. 0000000040000000-00000000400fffff: RAM
9449 23:42:59.183096 2. 0000000040100000-000000004032afff: RAMSTAGE
9450 23:42:59.189227 3. 000000004032b000-00000000545fffff: RAM
9451 23:42:59.192557 4. 0000000054600000-000000005465ffff: BL31
9452 23:42:59.195865 5. 0000000054660000-00000000ffe63fff: RAM
9453 23:42:59.202602 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9454 23:42:59.206292 7. 0000000100000000-000000023fffffff: RAM
9455 23:42:59.206850 Passing 5 GPIOs to payload:
9456 23:42:59.212827 NAME | PORT | POLARITY | VALUE
9457 23:42:59.216197 EC in RW | 0x000000aa | low | undefined
9458 23:42:59.222588 EC interrupt | 0x00000005 | low | undefined
9459 23:42:59.226057 TPM interrupt | 0x000000ab | high | undefined
9460 23:42:59.232439 SD card detect | 0x00000011 | high | undefined
9461 23:42:59.235335 speaker enable | 0x00000093 | high | undefined
9462 23:42:59.239103 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9463 23:42:59.242253 in-header: 03 f9 00 00 02 00 00 00
9464 23:42:59.245672 in-data: 02 00
9465 23:42:59.246228 ADC[4]: Raw value=904726 ID=7
9466 23:42:59.248728 ADC[3]: Raw value=213441 ID=1
9467 23:42:59.252490 RAM Code: 0x71
9468 23:42:59.253052 ADC[6]: Raw value=75701 ID=0
9469 23:42:59.255468 ADC[5]: Raw value=212703 ID=1
9470 23:42:59.258556 SKU Code: 0x1
9471 23:42:59.261956 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 425c
9472 23:42:59.265673 coreboot table: 964 bytes.
9473 23:42:59.268873 IMD ROOT 0. 0xfffff000 0x00001000
9474 23:42:59.272115 IMD SMALL 1. 0xffffe000 0x00001000
9475 23:42:59.275064 RO MCACHE 2. 0xffffc000 0x00001104
9476 23:42:59.278857 CONSOLE 3. 0xfff7c000 0x00080000
9477 23:42:59.281982 FMAP 4. 0xfff7b000 0x00000452
9478 23:42:59.284905 TIME STAMP 5. 0xfff7a000 0x00000910
9479 23:42:59.288850 VBOOT WORK 6. 0xfff66000 0x00014000
9480 23:42:59.292281 RAMOOPS 7. 0xffe66000 0x00100000
9481 23:42:59.295396 COREBOOT 8. 0xffe64000 0x00002000
9482 23:42:59.295955 IMD small region:
9483 23:42:59.298724 IMD ROOT 0. 0xffffec00 0x00000400
9484 23:42:59.301563 VPD 1. 0xffffeb80 0x0000006c
9485 23:42:59.308882 MMC STATUS 2. 0xffffeb60 0x00000004
9486 23:42:59.311839 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9487 23:42:59.315318 Probing TPM: done!
9488 23:42:59.318682 Connected to device vid:did:rid of 1ae0:0028:00
9489 23:42:59.328197 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593bf581c
9490 23:42:59.331942 Initialized TPM device CR50 revision 0
9491 23:42:59.335107 Checking cr50 for pending updates
9492 23:42:59.339883 Reading cr50 TPM mode
9493 23:42:59.348337 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9494 23:42:59.354444 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9495 23:42:59.394857 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9496 23:42:59.397930 Checking segment from ROM address 0x40100000
9497 23:42:59.401762 Checking segment from ROM address 0x4010001c
9498 23:42:59.408452 Loading segment from ROM address 0x40100000
9499 23:42:59.409013 code (compression=0)
9500 23:42:59.414931 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9501 23:42:59.424848 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9502 23:42:59.425423 it's not compressed!
9503 23:42:59.431842 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9504 23:42:59.434272 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9505 23:42:59.454866 Loading segment from ROM address 0x4010001c
9506 23:42:59.455423 Entry Point 0x80000000
9507 23:42:59.458560 Loaded segments
9508 23:42:59.461244 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9509 23:42:59.468150 Jumping to boot code at 0x80000000(0xffe64000)
9510 23:42:59.474991 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9511 23:42:59.481516 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9512 23:42:59.489037 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9513 23:42:59.492966 Checking segment from ROM address 0x40100000
9514 23:42:59.495830 Checking segment from ROM address 0x4010001c
9515 23:42:59.502657 Loading segment from ROM address 0x40100000
9516 23:42:59.503227 code (compression=1)
9517 23:42:59.509997 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9518 23:42:59.519229 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9519 23:42:59.519807 using LZMA
9520 23:42:59.528625 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9521 23:42:59.534717 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9522 23:42:59.537992 Loading segment from ROM address 0x4010001c
9523 23:42:59.538409 Entry Point 0x54601000
9524 23:42:59.541450 Loaded segments
9525 23:42:59.544255 NOTICE: MT8192 bl31_setup
9526 23:42:59.551597 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9527 23:42:59.554920 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9528 23:42:59.558205 WARNING: region 0:
9529 23:42:59.561516 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9530 23:42:59.562149 WARNING: region 1:
9531 23:42:59.568337 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9532 23:42:59.571441 WARNING: region 2:
9533 23:42:59.574912 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9534 23:42:59.577925 WARNING: region 3:
9535 23:42:59.581684 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9536 23:42:59.584450 WARNING: region 4:
9537 23:42:59.591349 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9538 23:42:59.591923 WARNING: region 5:
9539 23:42:59.594832 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 23:42:59.598174 WARNING: region 6:
9541 23:42:59.601144 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9542 23:42:59.604423 WARNING: region 7:
9543 23:42:59.608257 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9544 23:42:59.614654 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9545 23:42:59.618148 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9546 23:42:59.621537 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9547 23:42:59.627968 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9548 23:42:59.631257 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9549 23:42:59.634341 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9550 23:42:59.641299 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9551 23:42:59.644637 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9552 23:42:59.651177 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9553 23:42:59.654678 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9554 23:42:59.658286 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9555 23:42:59.664561 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9556 23:42:59.668323 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9557 23:42:59.671616 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9558 23:42:59.678686 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9559 23:42:59.681695 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9560 23:42:59.684747 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9561 23:42:59.691578 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9562 23:42:59.694413 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9563 23:42:59.701876 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9564 23:42:59.705126 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9565 23:42:59.708469 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9566 23:42:59.715003 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9567 23:42:59.718055 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9568 23:42:59.724877 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9569 23:42:59.728264 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9570 23:42:59.731279 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9571 23:42:59.738464 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9572 23:42:59.741646 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9573 23:42:59.744835 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9574 23:42:59.751338 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9575 23:42:59.754621 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9576 23:42:59.757908 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9577 23:42:59.765341 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9578 23:42:59.768333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9579 23:42:59.771928 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9580 23:42:59.775494 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9581 23:42:59.781841 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9582 23:42:59.785133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9583 23:42:59.788419 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9584 23:42:59.791691 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9585 23:42:59.798831 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9586 23:42:59.801689 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9587 23:42:59.805480 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9588 23:42:59.808133 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9589 23:42:59.815427 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9590 23:42:59.818726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9591 23:42:59.822539 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9592 23:42:59.828799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9593 23:42:59.832007 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9594 23:42:59.835193 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9595 23:42:59.841986 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9596 23:42:59.845184 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9597 23:42:59.852038 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9598 23:42:59.855358 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9599 23:42:59.862087 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9600 23:42:59.864896 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9601 23:42:59.868496 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9602 23:42:59.875304 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9603 23:42:59.878150 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9604 23:42:59.885268 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9605 23:42:59.888626 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9606 23:42:59.895534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9607 23:42:59.898938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9608 23:42:59.901976 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9609 23:42:59.908749 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9610 23:42:59.911943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9611 23:42:59.919000 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9612 23:42:59.922363 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9613 23:42:59.929106 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9614 23:42:59.931946 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9615 23:42:59.935605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9616 23:42:59.942088 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9617 23:42:59.945854 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9618 23:42:59.952635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9619 23:42:59.955751 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9620 23:42:59.958701 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9621 23:42:59.965981 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9622 23:42:59.968848 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9623 23:42:59.975573 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9624 23:42:59.978539 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9625 23:42:59.985566 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9626 23:42:59.988872 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9627 23:42:59.995213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9628 23:42:59.998650 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9629 23:43:00.001947 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9630 23:43:00.008611 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9631 23:43:00.011707 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9632 23:43:00.018686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9633 23:43:00.021675 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9634 23:43:00.028737 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9635 23:43:00.031817 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9636 23:43:00.035686 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9637 23:43:00.041804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9638 23:43:00.045319 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9639 23:43:00.051820 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9640 23:43:00.055908 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9641 23:43:00.059000 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9642 23:43:00.065637 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9643 23:43:00.068738 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9644 23:43:00.071915 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9645 23:43:00.075523 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9646 23:43:00.081914 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9647 23:43:00.086038 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9648 23:43:00.092795 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9649 23:43:00.095444 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9650 23:43:00.099386 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9651 23:43:00.105693 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9652 23:43:00.109251 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9653 23:43:00.115222 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9654 23:43:00.118868 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9655 23:43:00.122060 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9656 23:43:00.128896 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9657 23:43:00.132249 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9658 23:43:00.138626 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9659 23:43:00.142220 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9660 23:43:00.146051 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9661 23:43:00.148943 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9662 23:43:00.155447 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9663 23:43:00.158776 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9664 23:43:00.162700 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9665 23:43:00.165663 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9666 23:43:00.172190 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9667 23:43:00.176072 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9668 23:43:00.178839 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9669 23:43:00.185686 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9670 23:43:00.188877 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9671 23:43:00.195888 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9672 23:43:00.199706 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9673 23:43:00.202342 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9674 23:43:00.209179 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9675 23:43:00.212578 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9676 23:43:00.215960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9677 23:43:00.222389 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9678 23:43:00.226097 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9679 23:43:00.232580 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9680 23:43:00.235449 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9681 23:43:00.239424 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9682 23:43:00.245480 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9683 23:43:00.248958 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9684 23:43:00.255910 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9685 23:43:00.259273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9686 23:43:00.262614 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9687 23:43:00.269418 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9688 23:43:00.272209 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9689 23:43:00.275784 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9690 23:43:00.282576 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9691 23:43:00.285986 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9692 23:43:00.292454 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9693 23:43:00.295911 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9694 23:43:00.299973 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9695 23:43:00.305817 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9696 23:43:00.309190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9697 23:43:00.316252 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9698 23:43:00.319137 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9699 23:43:00.322493 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9700 23:43:00.329097 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9701 23:43:00.333055 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9702 23:43:00.335932 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9703 23:43:00.342874 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9704 23:43:00.345854 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9705 23:43:00.352415 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9706 23:43:00.356085 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9707 23:43:00.359291 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9708 23:43:00.365950 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9709 23:43:00.368858 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9710 23:43:00.375430 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9711 23:43:00.378821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9712 23:43:00.382668 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9713 23:43:00.388984 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9714 23:43:00.392681 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9715 23:43:00.398995 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9716 23:43:00.402927 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9717 23:43:00.405552 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9718 23:43:00.412172 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9719 23:43:00.415255 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9720 23:43:00.418736 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9721 23:43:00.425528 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9722 23:43:00.429185 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9723 23:43:00.435858 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9724 23:43:00.438910 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9725 23:43:00.441926 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9726 23:43:00.448941 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9727 23:43:00.451796 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9728 23:43:00.459011 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9729 23:43:00.462116 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9730 23:43:00.465394 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9731 23:43:00.472295 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9732 23:43:00.475811 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9733 23:43:00.482290 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9734 23:43:00.485867 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9735 23:43:00.488497 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9736 23:43:00.495082 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9737 23:43:00.498924 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9738 23:43:00.505337 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9739 23:43:00.508995 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9740 23:43:00.512162 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9741 23:43:00.519067 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9742 23:43:00.522044 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9743 23:43:00.528989 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9744 23:43:00.531903 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9745 23:43:00.535096 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9746 23:43:00.542356 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9747 23:43:00.545325 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9748 23:43:00.552133 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9749 23:43:00.555628 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9750 23:43:00.561853 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9751 23:43:00.565088 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9752 23:43:00.568804 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9753 23:43:00.575488 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9754 23:43:00.578584 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9755 23:43:00.585481 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9756 23:43:00.588630 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9757 23:43:00.591862 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9758 23:43:00.598856 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9759 23:43:00.601793 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9760 23:43:00.608692 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9761 23:43:00.611782 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9762 23:43:00.618336 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9763 23:43:00.622224 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9764 23:43:00.625237 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9765 23:43:00.632035 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9766 23:43:00.635282 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9767 23:43:00.641687 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9768 23:43:00.645078 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9769 23:43:00.648194 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9770 23:43:00.654938 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9771 23:43:00.658112 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9772 23:43:00.664753 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9773 23:43:00.667919 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9774 23:43:00.671781 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9775 23:43:00.675219 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9776 23:43:00.681567 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9777 23:43:00.685219 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9778 23:43:00.688569 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9779 23:43:00.694925 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9780 23:43:00.698212 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9781 23:43:00.701754 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9782 23:43:00.708179 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9783 23:43:00.711517 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9784 23:43:00.714732 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9785 23:43:00.721391 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9786 23:43:00.725212 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9787 23:43:00.728223 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9788 23:43:00.734793 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9789 23:43:00.738087 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9790 23:43:00.744474 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9791 23:43:00.748578 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9792 23:43:00.751931 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9793 23:43:00.758066 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9794 23:43:00.761873 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9795 23:43:00.764801 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9796 23:43:00.771013 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9797 23:43:00.774178 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9798 23:43:00.777475 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9799 23:43:00.784737 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9800 23:43:00.787538 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9801 23:43:00.795009 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9802 23:43:00.798101 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9803 23:43:00.801053 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9804 23:43:00.807570 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9805 23:43:00.810899 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9806 23:43:00.814611 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9807 23:43:00.821072 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9808 23:43:00.824529 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9809 23:43:00.830990 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9810 23:43:00.834226 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9811 23:43:00.837704 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9812 23:43:00.844007 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9813 23:43:00.847252 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9814 23:43:00.850900 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9815 23:43:00.854375 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9816 23:43:00.857766 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9817 23:43:00.863941 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9818 23:43:00.867151 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9819 23:43:00.871305 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9820 23:43:00.874135 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9821 23:43:00.880465 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9822 23:43:00.884212 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9823 23:43:00.887338 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9824 23:43:00.894226 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9825 23:43:00.897394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9826 23:43:00.900552 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9827 23:43:00.907119 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9828 23:43:00.910839 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9829 23:43:00.913988 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9830 23:43:00.920885 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9831 23:43:00.923707 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9832 23:43:00.930474 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9833 23:43:00.933701 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9834 23:43:00.936855 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9835 23:43:00.944000 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9836 23:43:00.947017 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9837 23:43:00.953999 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9838 23:43:00.957260 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9839 23:43:00.963478 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9840 23:43:00.967487 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9841 23:43:00.970127 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9842 23:43:00.976957 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9843 23:43:00.980162 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9844 23:43:00.986968 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9845 23:43:00.990244 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9846 23:43:00.993915 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9847 23:43:01.000376 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9848 23:43:01.003438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9849 23:43:01.010178 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9850 23:43:01.013348 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9851 23:43:01.016854 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9852 23:43:01.023434 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9853 23:43:01.027317 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9854 23:43:01.033882 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9855 23:43:01.036898 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9856 23:43:01.043359 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9857 23:43:01.046530 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9858 23:43:01.050254 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9859 23:43:01.056583 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9860 23:43:01.060382 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9861 23:43:01.063561 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9862 23:43:01.070033 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9863 23:43:01.073099 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9864 23:43:01.079600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9865 23:43:01.083273 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9866 23:43:01.087025 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9867 23:43:01.093242 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9868 23:43:01.096767 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9869 23:43:01.103898 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9870 23:43:01.106895 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9871 23:43:01.113371 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9872 23:43:01.116941 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9873 23:43:01.119964 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9874 23:43:01.126745 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9875 23:43:01.129984 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9876 23:43:01.136602 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9877 23:43:01.140124 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9878 23:43:01.143468 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9879 23:43:01.150063 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9880 23:43:01.153175 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9881 23:43:01.159801 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9882 23:43:01.163248 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9883 23:43:01.166326 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9884 23:43:01.172850 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9885 23:43:01.176608 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9886 23:43:01.182912 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9887 23:43:01.186633 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9888 23:43:01.192995 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9889 23:43:01.196659 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9890 23:43:01.199396 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9891 23:43:01.206461 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9892 23:43:01.209496 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9893 23:43:01.216283 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9894 23:43:01.219287 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9895 23:43:01.222647 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9896 23:43:01.229113 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9897 23:43:01.232553 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9898 23:43:01.239143 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9899 23:43:01.242540 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9900 23:43:01.249137 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9901 23:43:01.252922 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9902 23:43:01.255635 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9903 23:43:01.262828 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9904 23:43:01.265725 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9905 23:43:01.272380 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9906 23:43:01.275776 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9907 23:43:01.282918 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9908 23:43:01.285451 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9909 23:43:01.289349 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9910 23:43:01.295689 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9911 23:43:01.298855 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9912 23:43:01.305563 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9913 23:43:01.308607 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9914 23:43:01.315777 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9915 23:43:01.318801 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9916 23:43:01.322053 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9917 23:43:01.328866 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9918 23:43:01.332598 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9919 23:43:01.338380 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9920 23:43:01.342306 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9921 23:43:01.348340 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9922 23:43:01.351996 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9923 23:43:01.358433 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9924 23:43:01.362163 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9925 23:43:01.365146 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9926 23:43:01.371805 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9927 23:43:01.375062 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9928 23:43:01.381927 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9929 23:43:01.384909 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9930 23:43:01.388563 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9931 23:43:01.395535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9932 23:43:01.398348 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9933 23:43:01.405181 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9934 23:43:01.408291 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9935 23:43:01.415444 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9936 23:43:01.418346 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9937 23:43:01.425714 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9938 23:43:01.428032 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9939 23:43:01.432079 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9940 23:43:01.437944 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9941 23:43:01.441532 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9942 23:43:01.447952 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9943 23:43:01.451858 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9944 23:43:01.458247 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9945 23:43:01.461662 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9946 23:43:01.464598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9947 23:43:01.471718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9948 23:43:01.474754 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9949 23:43:01.481707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9950 23:43:01.484662 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9951 23:43:01.491542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9952 23:43:01.494729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9953 23:43:01.501216 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9954 23:43:01.504732 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9955 23:43:01.511421 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9956 23:43:01.514557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9957 23:43:01.521200 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9958 23:43:01.524704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9959 23:43:01.530967 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9960 23:43:01.534321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9961 23:43:01.541410 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9962 23:43:01.544391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9963 23:43:01.547783 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9964 23:43:01.554598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9965 23:43:01.557803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9966 23:43:01.564500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9967 23:43:01.567747 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9968 23:43:01.574313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9969 23:43:01.577750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9970 23:43:01.585002 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9971 23:43:01.587823 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9972 23:43:01.594700 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9973 23:43:01.597689 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9974 23:43:01.604584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9975 23:43:01.607672 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9976 23:43:01.614320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9977 23:43:01.617568 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9978 23:43:01.624253 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9979 23:43:01.624816 INFO: [APUAPC] vio 0
9980 23:43:01.631353 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9981 23:43:01.635094 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9982 23:43:01.638125 INFO: [APUAPC] D0_APC_0: 0x400510
9983 23:43:01.641359 INFO: [APUAPC] D0_APC_1: 0x0
9984 23:43:01.644247 INFO: [APUAPC] D0_APC_2: 0x1540
9985 23:43:01.648029 INFO: [APUAPC] D0_APC_3: 0x0
9986 23:43:01.650690 INFO: [APUAPC] D1_APC_0: 0xffffffff
9987 23:43:01.654668 INFO: [APUAPC] D1_APC_1: 0xffffffff
9988 23:43:01.657871 INFO: [APUAPC] D1_APC_2: 0x3fffff
9989 23:43:01.661221 INFO: [APUAPC] D1_APC_3: 0x0
9990 23:43:01.664263 INFO: [APUAPC] D2_APC_0: 0xffffffff
9991 23:43:01.667685 INFO: [APUAPC] D2_APC_1: 0xffffffff
9992 23:43:01.670933 INFO: [APUAPC] D2_APC_2: 0x3fffff
9993 23:43:01.674302 INFO: [APUAPC] D2_APC_3: 0x0
9994 23:43:01.677752 INFO: [APUAPC] D3_APC_0: 0xffffffff
9995 23:43:01.681206 INFO: [APUAPC] D3_APC_1: 0xffffffff
9996 23:43:01.684000 INFO: [APUAPC] D3_APC_2: 0x3fffff
9997 23:43:01.687501 INFO: [APUAPC] D3_APC_3: 0x0
9998 23:43:01.691373 INFO: [APUAPC] D4_APC_0: 0xffffffff
9999 23:43:01.694068 INFO: [APUAPC] D4_APC_1: 0xffffffff
10000 23:43:01.697504 INFO: [APUAPC] D4_APC_2: 0x3fffff
10001 23:43:01.698131 INFO: [APUAPC] D4_APC_3: 0x0
10002 23:43:01.704188 INFO: [APUAPC] D5_APC_0: 0xffffffff
10003 23:43:01.707684 INFO: [APUAPC] D5_APC_1: 0xffffffff
10004 23:43:01.710654 INFO: [APUAPC] D5_APC_2: 0x3fffff
10005 23:43:01.711139 INFO: [APUAPC] D5_APC_3: 0x0
10006 23:43:01.714039 INFO: [APUAPC] D6_APC_0: 0xffffffff
10007 23:43:01.717221 INFO: [APUAPC] D6_APC_1: 0xffffffff
10008 23:43:01.720610 INFO: [APUAPC] D6_APC_2: 0x3fffff
10009 23:43:01.724262 INFO: [APUAPC] D6_APC_3: 0x0
10010 23:43:01.728072 INFO: [APUAPC] D7_APC_0: 0xffffffff
10011 23:43:01.730315 INFO: [APUAPC] D7_APC_1: 0xffffffff
10012 23:43:01.733946 INFO: [APUAPC] D7_APC_2: 0x3fffff
10013 23:43:01.737321 INFO: [APUAPC] D7_APC_3: 0x0
10014 23:43:01.740366 INFO: [APUAPC] D8_APC_0: 0xffffffff
10015 23:43:01.743921 INFO: [APUAPC] D8_APC_1: 0xffffffff
10016 23:43:01.747304 INFO: [APUAPC] D8_APC_2: 0x3fffff
10017 23:43:01.750616 INFO: [APUAPC] D8_APC_3: 0x0
10018 23:43:01.754051 INFO: [APUAPC] D9_APC_0: 0xffffffff
10019 23:43:01.757335 INFO: [APUAPC] D9_APC_1: 0xffffffff
10020 23:43:01.760711 INFO: [APUAPC] D9_APC_2: 0x3fffff
10021 23:43:01.763921 INFO: [APUAPC] D9_APC_3: 0x0
10022 23:43:01.767068 INFO: [APUAPC] D10_APC_0: 0xffffffff
10023 23:43:01.770494 INFO: [APUAPC] D10_APC_1: 0xffffffff
10024 23:43:01.773996 INFO: [APUAPC] D10_APC_2: 0x3fffff
10025 23:43:01.777235 INFO: [APUAPC] D10_APC_3: 0x0
10026 23:43:01.780126 INFO: [APUAPC] D11_APC_0: 0xffffffff
10027 23:43:01.783902 INFO: [APUAPC] D11_APC_1: 0xffffffff
10028 23:43:01.787332 INFO: [APUAPC] D11_APC_2: 0x3fffff
10029 23:43:01.790406 INFO: [APUAPC] D11_APC_3: 0x0
10030 23:43:01.793811 INFO: [APUAPC] D12_APC_0: 0xffffffff
10031 23:43:01.797472 INFO: [APUAPC] D12_APC_1: 0xffffffff
10032 23:43:01.801153 INFO: [APUAPC] D12_APC_2: 0x3fffff
10033 23:43:01.803560 INFO: [APUAPC] D12_APC_3: 0x0
10034 23:43:01.807601 INFO: [APUAPC] D13_APC_0: 0xffffffff
10035 23:43:01.810140 INFO: [APUAPC] D13_APC_1: 0xffffffff
10036 23:43:01.813880 INFO: [APUAPC] D13_APC_2: 0x3fffff
10037 23:43:01.816722 INFO: [APUAPC] D13_APC_3: 0x0
10038 23:43:01.820239 INFO: [APUAPC] D14_APC_0: 0xffffffff
10039 23:43:01.823637 INFO: [APUAPC] D14_APC_1: 0xffffffff
10040 23:43:01.827235 INFO: [APUAPC] D14_APC_2: 0x3fffff
10041 23:43:01.830289 INFO: [APUAPC] D14_APC_3: 0x0
10042 23:43:01.833727 INFO: [APUAPC] D15_APC_0: 0xffffffff
10043 23:43:01.837507 INFO: [APUAPC] D15_APC_1: 0xffffffff
10044 23:43:01.840442 INFO: [APUAPC] D15_APC_2: 0x3fffff
10045 23:43:01.844054 INFO: [APUAPC] D15_APC_3: 0x0
10046 23:43:01.846557 INFO: [APUAPC] APC_CON: 0x4
10047 23:43:01.850127 INFO: [NOCDAPC] D0_APC_0: 0x0
10048 23:43:01.853763 INFO: [NOCDAPC] D0_APC_1: 0x0
10049 23:43:01.856498 INFO: [NOCDAPC] D1_APC_0: 0x0
10050 23:43:01.860171 INFO: [NOCDAPC] D1_APC_1: 0xfff
10051 23:43:01.863580 INFO: [NOCDAPC] D2_APC_0: 0x0
10052 23:43:01.864044 INFO: [NOCDAPC] D2_APC_1: 0xfff
10053 23:43:01.866753 INFO: [NOCDAPC] D3_APC_0: 0x0
10054 23:43:01.869890 INFO: [NOCDAPC] D3_APC_1: 0xfff
10055 23:43:01.873640 INFO: [NOCDAPC] D4_APC_0: 0x0
10056 23:43:01.876797 INFO: [NOCDAPC] D4_APC_1: 0xfff
10057 23:43:01.880045 INFO: [NOCDAPC] D5_APC_0: 0x0
10058 23:43:01.883661 INFO: [NOCDAPC] D5_APC_1: 0xfff
10059 23:43:01.886794 INFO: [NOCDAPC] D6_APC_0: 0x0
10060 23:43:01.890231 INFO: [NOCDAPC] D6_APC_1: 0xfff
10061 23:43:01.893229 INFO: [NOCDAPC] D7_APC_0: 0x0
10062 23:43:01.897143 INFO: [NOCDAPC] D7_APC_1: 0xfff
10063 23:43:01.897748 INFO: [NOCDAPC] D8_APC_0: 0x0
10064 23:43:01.900040 INFO: [NOCDAPC] D8_APC_1: 0xfff
10065 23:43:01.903310 INFO: [NOCDAPC] D9_APC_0: 0x0
10066 23:43:01.906712 INFO: [NOCDAPC] D9_APC_1: 0xfff
10067 23:43:01.910112 INFO: [NOCDAPC] D10_APC_0: 0x0
10068 23:43:01.913611 INFO: [NOCDAPC] D10_APC_1: 0xfff
10069 23:43:01.916744 INFO: [NOCDAPC] D11_APC_0: 0x0
10070 23:43:01.920127 INFO: [NOCDAPC] D11_APC_1: 0xfff
10071 23:43:01.923727 INFO: [NOCDAPC] D12_APC_0: 0x0
10072 23:43:01.926451 INFO: [NOCDAPC] D12_APC_1: 0xfff
10073 23:43:01.930267 INFO: [NOCDAPC] D13_APC_0: 0x0
10074 23:43:01.933189 INFO: [NOCDAPC] D13_APC_1: 0xfff
10075 23:43:01.933710 INFO: [NOCDAPC] D14_APC_0: 0x0
10076 23:43:01.936648 INFO: [NOCDAPC] D14_APC_1: 0xfff
10077 23:43:01.940170 INFO: [NOCDAPC] D15_APC_0: 0x0
10078 23:43:01.942939 INFO: [NOCDAPC] D15_APC_1: 0xfff
10079 23:43:01.946644 INFO: [NOCDAPC] APC_CON: 0x4
10080 23:43:01.949550 INFO: [APUAPC] set_apusys_apc done
10081 23:43:01.953244 INFO: [DEVAPC] devapc_init done
10082 23:43:01.956236 INFO: GICv3 without legacy support detected.
10083 23:43:01.962775 INFO: ARM GICv3 driver initialized in EL3
10084 23:43:01.966314 INFO: Maximum SPI INTID supported: 639
10085 23:43:01.969843 INFO: BL31: Initializing runtime services
10086 23:43:01.976415 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10087 23:43:01.980077 INFO: SPM: enable CPC mode
10088 23:43:01.982751 INFO: mcdi ready for mcusys-off-idle and system suspend
10089 23:43:01.989421 INFO: BL31: Preparing for EL3 exit to normal world
10090 23:43:01.992846 INFO: Entry point address = 0x80000000
10091 23:43:01.993310 INFO: SPSR = 0x8
10092 23:43:01.999711
10093 23:43:02.000275
10094 23:43:02.000643
10095 23:43:02.002371 Starting depthcharge on Spherion...
10096 23:43:02.002830
10097 23:43:02.003198 Wipe memory regions:
10098 23:43:02.003536
10099 23:43:02.006578 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10100 23:43:02.007181 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10101 23:43:02.007648 Setting prompt string to ['asurada:']
10102 23:43:02.008095 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10103 23:43:02.008826 [0x00000040000000, 0x00000054600000)
10104 23:43:02.128705
10105 23:43:02.129271 [0x00000054660000, 0x00000080000000)
10106 23:43:02.388693
10107 23:43:02.389262 [0x000000821a7280, 0x000000ffe64000)
10108 23:43:03.133557
10109 23:43:03.134335 [0x00000100000000, 0x00000240000000)
10110 23:43:05.023677
10111 23:43:05.027181 Initializing XHCI USB controller at 0x11200000.
10112 23:43:06.064949
10113 23:43:06.068131 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10114 23:43:06.068696
10115 23:43:06.069090
10116 23:43:06.069434
10117 23:43:06.070307 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10119 23:43:06.171627 asurada: tftpboot 192.168.201.1 12172464/tftp-deploy-kxi0e2kd/kernel/image.itb 12172464/tftp-deploy-kxi0e2kd/kernel/cmdline
10120 23:43:06.172281 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10121 23:43:06.172734 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10122 23:43:06.177200 tftpboot 192.168.201.1 12172464/tftp-deploy-kxi0e2kd/kernel/image.itbtp-deploy-kxi0e2kd/kernel/cmdline
10123 23:43:06.177701
10124 23:43:06.178071 Waiting for link
10125 23:43:06.337854
10126 23:43:06.338409 R8152: Initializing
10127 23:43:06.338779
10128 23:43:06.340948 Version 9 (ocp_data = 6010)
10129 23:43:06.341410
10130 23:43:06.344905 R8152: Done initializing
10131 23:43:06.345509
10132 23:43:06.345946 Adding net device
10133 23:43:08.286889
10134 23:43:08.287713 done.
10135 23:43:08.288118
10136 23:43:08.288467 MAC: 00:e0:4c:78:7a:aa
10137 23:43:08.288819
10138 23:43:08.290226 Sending DHCP discover... done.
10139 23:43:08.290845
10140 23:43:08.292663 Waiting for reply... done.
10141 23:43:08.292768
10142 23:43:08.296069 Sending DHCP request... done.
10143 23:43:08.296182
10144 23:43:08.296280 Waiting for reply... done.
10145 23:43:08.296373
10146 23:43:08.299452 My ip is 192.168.201.12
10147 23:43:08.299542
10148 23:43:08.303138 The DHCP server ip is 192.168.201.1
10149 23:43:08.303255
10150 23:43:08.305932 TFTP server IP predefined by user: 192.168.201.1
10151 23:43:08.306013
10152 23:43:08.312730 Bootfile predefined by user: 12172464/tftp-deploy-kxi0e2kd/kernel/image.itb
10153 23:43:08.312812
10154 23:43:08.316136 Sending tftp read request... done.
10155 23:43:08.316222
10156 23:43:08.319368 Waiting for the transfer...
10157 23:43:08.319456
10158 23:43:08.615577 00000000 ################################################################
10159 23:43:08.615724
10160 23:43:08.903678 00080000 ################################################################
10161 23:43:08.903819
10162 23:43:09.198590 00100000 ################################################################
10163 23:43:09.198731
10164 23:43:09.466619 00180000 ################################################################
10165 23:43:09.466761
10166 23:43:09.764266 00200000 ################################################################
10167 23:43:09.764405
10168 23:43:10.062900 00280000 ################################################################
10169 23:43:10.063041
10170 23:43:10.357794 00300000 ################################################################
10171 23:43:10.357938
10172 23:43:10.612375 00380000 ################################################################
10173 23:43:10.612519
10174 23:43:10.868976 00400000 ################################################################
10175 23:43:10.869112
10176 23:43:11.166727 00480000 ################################################################
10177 23:43:11.166865
10178 23:43:11.464658 00500000 ################################################################
10179 23:43:11.465133
10180 23:43:11.786598 00580000 ################################################################
10181 23:43:11.786739
10182 23:43:12.075749 00600000 ################################################################
10183 23:43:12.075916
10184 23:43:12.374779 00680000 ################################################################
10185 23:43:12.374915
10186 23:43:12.651442 00700000 ################################################################
10187 23:43:12.651584
10188 23:43:12.915755 00780000 ################################################################
10189 23:43:12.915898
10190 23:43:13.200063 00800000 ################################################################
10191 23:43:13.200200
10192 23:43:13.484486 00880000 ################################################################
10193 23:43:13.484625
10194 23:43:13.770542 00900000 ################################################################
10195 23:43:13.770682
10196 23:43:14.061557 00980000 ################################################################
10197 23:43:14.061729
10198 23:43:14.357858 00a00000 ################################################################
10199 23:43:14.358039
10200 23:43:14.650325 00a80000 ################################################################
10201 23:43:14.650465
10202 23:43:14.927900 00b00000 ################################################################
10203 23:43:14.928039
10204 23:43:15.189266 00b80000 ################################################################
10205 23:43:15.189430
10206 23:43:15.481081 00c00000 ################################################################
10207 23:43:15.481224
10208 23:43:15.775655 00c80000 ################################################################
10209 23:43:15.775799
10210 23:43:16.077313 00d00000 ################################################################
10211 23:43:16.077453
10212 23:43:16.377450 00d80000 ################################################################
10213 23:43:16.377602
10214 23:43:16.673964 00e00000 ################################################################
10215 23:43:16.674108
10216 23:43:16.972347 00e80000 ################################################################
10217 23:43:16.972492
10218 23:43:17.273627 00f00000 ################################################################
10219 23:43:17.273771
10220 23:43:17.565538 00f80000 ################################################################
10221 23:43:17.565718
10222 23:43:17.835450 01000000 ################################################################
10223 23:43:17.835590
10224 23:43:18.100716 01080000 ################################################################
10225 23:43:18.100855
10226 23:43:18.389658 01100000 ################################################################
10227 23:43:18.389798
10228 23:43:18.680705 01180000 ################################################################
10229 23:43:18.680848
10230 23:43:18.972703 01200000 ################################################################
10231 23:43:18.972847
10232 23:43:19.266388 01280000 ################################################################
10233 23:43:19.266528
10234 23:43:19.549938 01300000 ################################################################
10235 23:43:19.550078
10236 23:43:19.840983 01380000 ################################################################
10237 23:43:19.841125
10238 23:43:20.127621 01400000 ################################################################
10239 23:43:20.127764
10240 23:43:20.415843 01480000 ################################################################
10241 23:43:20.415987
10242 23:43:20.705807 01500000 ################################################################
10243 23:43:20.705954
10244 23:43:20.996753 01580000 ################################################################
10245 23:43:20.996898
10246 23:43:21.286066 01600000 ################################################################
10247 23:43:21.286202
10248 23:43:21.572490 01680000 ################################################################
10249 23:43:21.572628
10250 23:43:21.868661 01700000 ################################################################
10251 23:43:21.868805
10252 23:43:22.164346 01780000 ################################################################
10253 23:43:22.164491
10254 23:43:22.460462 01800000 ################################################################
10255 23:43:22.460603
10256 23:43:22.760868 01880000 ################################################################
10257 23:43:22.761014
10258 23:43:23.059371 01900000 ################################################################
10259 23:43:23.059516
10260 23:43:23.352915 01980000 ################################################################
10261 23:43:23.353055
10262 23:43:23.641616 01a00000 ################################################################
10263 23:43:23.641755
10264 23:43:23.915199 01a80000 ################################################################
10265 23:43:23.915340
10266 23:43:24.215288 01b00000 ################################################################
10267 23:43:24.215433
10268 23:43:24.249309 01b80000 ######## done.
10269 23:43:24.249399
10270 23:43:24.252514 The bootfile was 28894062 bytes long.
10271 23:43:24.252607
10272 23:43:24.256221 Sending tftp read request... done.
10273 23:43:24.256365
10274 23:43:24.259304 Waiting for the transfer...
10275 23:43:24.259483
10276 23:43:24.259605 00000000 # done.
10277 23:43:24.259713
10278 23:43:24.265597 Command line loaded dynamically from TFTP file: 12172464/tftp-deploy-kxi0e2kd/kernel/cmdline
10279 23:43:24.265731
10280 23:43:24.289074 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10281 23:43:24.289343
10282 23:43:24.289551 Loading FIT.
10283 23:43:24.289772
10284 23:43:24.292353 Image ramdisk-1 has 17795402 bytes.
10285 23:43:24.292563
10286 23:43:24.295845 Image fdt-1 has 47278 bytes.
10287 23:43:24.296205
10288 23:43:24.298867 Image kernel-1 has 11049348 bytes.
10289 23:43:24.299121
10290 23:43:24.309024 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10291 23:43:24.309530
10292 23:43:24.326229 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10293 23:43:24.326852
10294 23:43:24.332598 Choosing best match conf-1 for compat google,spherion-rev2.
10295 23:43:24.333166
10296 23:43:24.340370 Connected to device vid:did:rid of 1ae0:0028:00
10297 23:43:24.348735
10298 23:43:24.351961 tpm_get_response: command 0x17b, return code 0x0
10299 23:43:24.352617
10300 23:43:24.354862 ec_init: CrosEC protocol v3 supported (256, 248)
10301 23:43:24.358892
10302 23:43:24.362433 tpm_cleanup: add release locality here.
10303 23:43:24.363020
10304 23:43:24.363491 Shutting down all USB controllers.
10305 23:43:24.365757
10306 23:43:24.366225 Removing current net device
10307 23:43:24.366597
10308 23:43:24.372239 Exiting depthcharge with code 4 at timestamp: 51707617
10309 23:43:24.372707
10310 23:43:24.375443 LZMA decompressing kernel-1 to 0x821a6718
10311 23:43:24.375911
10312 23:43:24.378915 LZMA decompressing kernel-1 to 0x40000000
10313 23:43:25.767939
10314 23:43:25.768688 jumping to kernel
10315 23:43:25.770437 end: 2.2.4 bootloader-commands (duration 00:00:24) [common]
10316 23:43:25.770974 start: 2.2.5 auto-login-action (timeout 00:04:01) [common]
10317 23:43:25.771387 Setting prompt string to ['Linux version [0-9]']
10318 23:43:25.771770 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10319 23:43:25.772152 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10320 23:43:25.849484
10321 23:43:25.853000 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10322 23:43:25.856658 start: 2.2.5.1 login-action (timeout 00:04:01) [common]
10323 23:43:25.857253 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10324 23:43:25.857878 Setting prompt string to []
10325 23:43:25.858433 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10326 23:43:25.858926 Using line separator: #'\n'#
10327 23:43:25.859475 No login prompt set.
10328 23:43:25.859960 Parsing kernel messages
10329 23:43:25.860309 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10330 23:43:25.860905 [login-action] Waiting for messages, (timeout 00:04:01)
10331 23:43:25.876280 [ 0.000000] Linux version 6.1.64-cip10-rt5 (KernelCI@build-j33605-arm64-gcc-10-defconfig-arm64-chromebook-7778h) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023
10332 23:43:25.879763 [ 0.000000] random: crng init done
10333 23:43:25.886289 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10334 23:43:25.889673 [ 0.000000] efi: UEFI not found.
10335 23:43:25.896499 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10336 23:43:25.903308 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10337 23:43:25.912976 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10338 23:43:25.922886 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10339 23:43:25.929254 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10340 23:43:25.936025 [ 0.000000] printk: bootconsole [mtk8250] enabled
10341 23:43:25.942496 [ 0.000000] NUMA: No NUMA configuration found
10342 23:43:25.949412 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10343 23:43:25.952364 [ 0.000000] NUMA: NODE_DATA [mem 0x23efd0a00-0x23efd2fff]
10344 23:43:25.955574 [ 0.000000] Zone ranges:
10345 23:43:25.962273 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10346 23:43:25.965736 [ 0.000000] DMA32 empty
10347 23:43:25.972584 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10348 23:43:25.975708 [ 0.000000] Movable zone start for each node
10349 23:43:25.978641 [ 0.000000] Early memory node ranges
10350 23:43:25.985996 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10351 23:43:25.992898 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10352 23:43:25.998597 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10353 23:43:26.005900 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10354 23:43:26.012433 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10355 23:43:26.018553 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10356 23:43:26.074249 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10357 23:43:26.081232 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10358 23:43:26.087751 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10359 23:43:26.091063 [ 0.000000] psci: probing for conduit method from DT.
10360 23:43:26.097379 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10361 23:43:26.100987 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10362 23:43:26.107663 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10363 23:43:26.110632 [ 0.000000] psci: SMC Calling Convention v1.2
10364 23:43:26.117215 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10365 23:43:26.121303 [ 0.000000] Detected VIPT I-cache on CPU0
10366 23:43:26.127773 [ 0.000000] CPU features: detected: GIC system register CPU interface
10367 23:43:26.134151 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10368 23:43:26.140928 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10369 23:43:26.147858 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10370 23:43:26.154368 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10371 23:43:26.163916 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10372 23:43:26.167605 [ 0.000000] alternatives: applying boot alternatives
10373 23:43:26.173972 [ 0.000000] Fallback order for Node 0: 0
10374 23:43:26.180948 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10375 23:43:26.181558 [ 0.000000] Policy zone: Normal
10376 23:43:26.203828 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10377 23:43:26.217332 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10378 23:43:26.227117 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10379 23:43:26.237260 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10380 23:43:26.243959 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10381 23:43:26.247471 <6>[ 0.000000] software IO TLB: area num 8.
10382 23:43:26.303684 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10383 23:43:26.453212 <6>[ 0.000000] Memory: 7952180K/8385536K available (17984K kernel code, 4116K rwdata, 17316K rodata, 8448K init, 615K bss, 400588K reserved, 32768K cma-reserved)
10384 23:43:26.459639 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10385 23:43:26.466299 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10386 23:43:26.469565 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10387 23:43:26.476278 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10388 23:43:26.482796 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10389 23:43:26.486036 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10390 23:43:26.496214 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10391 23:43:26.502633 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10392 23:43:26.505668 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10393 23:43:26.514229 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10394 23:43:26.517096 <6>[ 0.000000] GICv3: 608 SPIs implemented
10395 23:43:26.524112 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10396 23:43:26.527488 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10397 23:43:26.530346 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10398 23:43:26.540461 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10399 23:43:26.550447 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10400 23:43:26.563345 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10401 23:43:26.570153 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10402 23:43:26.579141 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10403 23:43:26.593159 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10404 23:43:26.599113 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10405 23:43:26.605812 <6>[ 0.009180] Console: colour dummy device 80x25
10406 23:43:26.615804 <6>[ 0.013907] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10407 23:43:26.619264 <6>[ 0.024350] pid_max: default: 32768 minimum: 301
10408 23:43:26.625713 <6>[ 0.029220] LSM: Security Framework initializing
10409 23:43:26.632570 <6>[ 0.034158] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10410 23:43:26.642599 <6>[ 0.042022] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10411 23:43:26.649027 <6>[ 0.051466] cblist_init_generic: Setting adjustable number of callback queues.
10412 23:43:26.656013 <6>[ 0.058909] cblist_init_generic: Setting shift to 3 and lim to 1.
10413 23:43:26.666055 <6>[ 0.065247] cblist_init_generic: Setting adjustable number of callback queues.
10414 23:43:26.672938 <6>[ 0.072674] cblist_init_generic: Setting shift to 3 and lim to 1.
10415 23:43:26.675331 <6>[ 0.079111] rcu: Hierarchical SRCU implementation.
10416 23:43:26.682335 <6>[ 0.079113] rcu: Max phase no-delay instances is 1000.
10417 23:43:26.689267 <6>[ 0.079137] printk: bootconsole [mtk8250] printing thread started
10418 23:43:26.695223 <6>[ 0.097485] EFI services will not be available.
10419 23:43:26.698336 <6>[ 0.097688] smp: Bringing up secondary CPUs ...
10420 23:43:26.701787 <6>[ 0.097990] Detected VIPT I-cache on CPU1
10421 23:43:26.712210 <6>[ 0.098057] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10422 23:43:26.718716 <6>[ 0.098088] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10423 23:43:26.727639 <6>[ 0.125962] Detected VIPT I-cache on CPU2
10424 23:43:26.733947 <6>[ 0.126012] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10425 23:43:26.743977 <6>[ 0.126027] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10426 23:43:26.747774 <6>[ 0.126284] Detected VIPT I-cache on CPU3
10427 23:43:26.754365 <6>[ 0.126332] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10428 23:43:26.760681 <6>[ 0.126347] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10429 23:43:26.763814 <6>[ 0.126657] CPU features: detected: Spectre-v4
10430 23:43:26.770263 <6>[ 0.126663] CPU features: detected: Spectre-BHB
10431 23:43:26.773863 <6>[ 0.126668] Detected PIPT I-cache on CPU4
10432 23:43:26.780370 <6>[ 0.126728] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10433 23:43:26.786743 <6>[ 0.126745] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10434 23:43:26.793982 <6>[ 0.127041] Detected PIPT I-cache on CPU5
10435 23:43:26.800750 <6>[ 0.127102] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10436 23:43:26.807021 <6>[ 0.127119] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10437 23:43:26.810337 <6>[ 0.127395] Detected PIPT I-cache on CPU6
10438 23:43:26.816948 <6>[ 0.127461] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10439 23:43:26.823432 <6>[ 0.127477] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10440 23:43:26.830082 <6>[ 0.127768] Detected PIPT I-cache on CPU7
10441 23:43:26.836965 <6>[ 0.127836] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10442 23:43:26.843278 <6>[ 0.127853] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10443 23:43:26.847057 <6>[ 0.127899] smp: Brought up 1 node, 8 CPUs
10444 23:43:26.853228 <6>[ 0.127904] SMP: Total of 8 processors activated.
10445 23:43:26.856667 <6>[ 0.127907] CPU features: detected: 32-bit EL0 Support
10446 23:43:26.866826 <6>[ 0.127909] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10447 23:43:26.873671 <6>[ 0.127912] CPU features: detected: Common not Private translations
10448 23:43:26.879948 <6>[ 0.127913] CPU features: detected: CRC32 instructions
10449 23:43:26.883187 <6>[ 0.127916] CPU features: detected: RCpc load-acquire (LDAPR)
10450 23:43:26.890528 <6>[ 0.127917] CPU features: detected: LSE atomic instructions
10451 23:43:26.896808 <6>[ 0.127919] CPU features: detected: Privileged Access Never
10452 23:43:26.903109 <6>[ 0.127920] CPU features: detected: RAS Extension Support
10453 23:43:26.909741 <6>[ 0.127923] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10454 23:43:26.913016 <6>[ 0.127991] CPU: All CPU(s) started at EL2
10455 23:43:26.919712 <6>[ 0.127993] alternatives: applying system-wide alternatives
10456 23:43:26.923183 <6>[ 0.141013] devtmpfs: initialized
10457 23:43:26.933043 <6>[ 0.147290] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10458 23:43:26.954646 �9��V�.]Y�YY��F_INET protocol family
10459 23:43:26.961180 <6>[ 0.36446<9] printk: console [ttyS0] printing thread started
10460 23:43:26.970932 6>[ 0.229031] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10461 23:43:26.978268 <6>[ 0.364481] printk: console [ttyS0] enabled
10462 23:43:26.982051 <6>[ 0.364485] printk: bootconsole [mtk8250] disabled
10463 23:43:26.988183 <6>[ 0.378153] printk: bootconsole [mtk8250] printing thread stopped
10464 23:43:26.995227 <6>[ 0.379505] SuperH (H)SCI(F) driver initialized
10465 23:43:26.998380 <6>[ 0.380013] msm_serial: driver initialized
10466 23:43:27.008674 <6>[ 0.384751] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10467 23:43:27.015066 <6>[ 0.384780] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10468 23:43:27.031634 <6>[ 0.384811] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10469 23:43:27.041634 <6>[ 0.384841] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10470 23:43:27.050070 <6>[ 0.384862] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10471 23:43:27.050640 <6>[ 0.384890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10472 23:43:27.067102 <6>[ 0.384919] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10473 23:43:27.068439 <6>[ 0.385058] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10474 23:43:27.077163 <6>[ 0.385088] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10475 23:43:27.080804 <6>[ 0.394861] loop: module loaded
10476 23:43:27.087834 <6>[ 0.397426] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10477 23:43:27.092450 <4>[ 0.414734] mtk-pmic-keys: Failed to locate of_node [id: -1]
10478 23:43:27.095630 <6>[ 0.415824] megasas: 07.719.03.00-rc1
10479 23:43:27.098484 <6>[ 0.425008] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10480 23:43:27.105775 <6>[ 0.433057] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10481 23:43:27.111975 <6>[ 0.444859] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10482 23:43:27.125094 <6>[ 0.498665] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_B:0.6.171/cr50_v3.94_pp.126-3593b
10483 23:43:27.601870 <6>[ 1.004879] Freeing initrd memory: 17372K
10484 23:43:27.610170 <6>[ 1.010852] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10485 23:43:27.616775 <6>[ 1.015757] tun: Universal TUN/TAP device driver, 1.6
10486 23:43:27.620549 <6>[ 1.016553] thunder_xcv, ver 1.0
10487 23:43:27.623628 <6>[ 1.016573] thunder_bgx, ver 1.0
10488 23:43:27.626588 <6>[ 1.016586] nicpf, ver 1.0
10489 23:43:27.633793 <6>[ 1.017686] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10490 23:43:27.640542 <6>[ 1.017689] hns3: Copyright (c) 2017 Huawei Corporation.
10491 23:43:27.643513 <6>[ 1.017716] hclge is initializing
10492 23:43:27.646701 <6>[ 1.017731] e1000: Intel(R) PRO/1000 Network Driver
10493 23:43:27.654179 <6>[ 1.017733] e1000: Copyright (c) 1999-2006 Intel Corporation.
10494 23:43:27.660872 <6>[ 1.017755] e1000e: Intel(R) PRO/1000 Network Driver
10495 23:43:27.664774 <6>[ 1.017757] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10496 23:43:27.672099 <6>[ 1.017772] igb: Intel(R) Gigabit Ethernet Network Driver
10497 23:43:27.678329 <6>[ 1.017775] igb: Copyright (c) 2007-2014 Intel Corporation.
10498 23:43:27.685741 <6>[ 1.017789] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10499 23:43:27.689278 <6>[ 1.017791] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10500 23:43:27.692156 <6>[ 1.018091] sky2: driver version 1.30
10501 23:43:27.698986 <6>[ 1.019205] VFIO - User Level meta-driver version: 0.3
10502 23:43:27.705470 <6>[ 1.022128] usbcore: registered new interface driver usb-storage
10503 23:43:27.712768 <6>[ 1.022311] usbcore: registered new device driver onboard-usb-hub
10504 23:43:27.715912 <6>[ 1.025151] mt6397-rtc mt6359-rtc: registered as rtc0
10505 23:43:27.725902 <6>[ 1.025303] mt6397-rtc mt6359-rtc: setting system clock to 2023-12-03T23:41:13 UTC (1701646873)
10506 23:43:27.732241 <6>[ 1.025949] i2c_dev: i2c /dev entries driver
10507 23:43:27.739292 <6>[ 1.033274] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10508 23:43:27.742664 <6>[ 1.048287] cpu cpu0: EM: created perf domain
10509 23:43:27.749052 <6>[ 1.048610] cpu cpu4: EM: created perf domain
10510 23:43:27.755582 <6>[ 1.051830] sdhci: Secure Digital Host Controller Interface driver
10511 23:43:27.758615 <6>[ 1.051831] sdhci: Copyright(c) Pierre Ossman
10512 23:43:27.766035 <6>[ 1.052188] Synopsys Designware Multimedia Card Interface Driver
10513 23:43:27.772332 <6>[ 1.052563] sdhci-pltfm: SDHCI platform and OF driver helper
10514 23:43:27.778690 <6>[ 1.056851] ledtrig-cpu: registered to indicate activity on CPUs
10515 23:43:27.782235 <6>[ 1.057659] mmc0: CQHCI version 5.10
10516 23:43:27.789066 <6>[ 1.057679] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10517 23:43:27.792137 <6>[ 1.057932] usbcore: registered new interface driver usbhid
10518 23:43:27.799052 <6>[ 1.057933] usbhid: USB HID core driver
10519 23:43:27.805395 <6>[ 1.058010] spi_master spi0: will run message pump with realtime priority
10520 23:43:27.818755 <6>[ 1.089591] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10521 23:43:27.832378 <6>[ 1.092564] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10522 23:43:27.835377 <6>[ 1.093415] cros-ec-spi spi0.0: Chrome EC device registered
10523 23:43:27.845948 <6>[ 1.108088] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10524 23:43:27.852113 <6>[ 1.110482] NET: Registered PF_PACKET protocol family
10525 23:43:27.855253 <6>[ 1.110602] 9pnet: Installing 9P2000 support
10526 23:43:27.858719 <5>[ 1.110637] Key type dns_resolver registered
10527 23:43:27.865029 <6>[ 1.111018] registered taskstats version 1
10528 23:43:27.868258 <5>[ 1.111039] Loading compiled-in X.509 certificates
10529 23:43:27.878463 <4>[ 1.132990] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10530 23:43:27.891476 <4>[ 1.133130] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10531 23:43:27.898181 <3>[ 1.133140] debugfs: File 'uA_load' in directory '/' already present!
10532 23:43:27.904404 <3>[ 1.133148] debugfs: File 'min_uV' in directory '/' already present!
10533 23:43:27.911585 <3>[ 1.133151] debugfs: File 'max_uV' in directory '/' already present!
10534 23:43:27.918228 <3>[ 1.133154] debugfs: File 'constraint_flags' in directory '/' already present!
10535 23:43:27.924985 <3>[ 1.135061] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10536 23:43:27.931773 <6>[ 1.141659] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10537 23:43:27.938343 <6>[ 1.142291] xhci-mtk 11200000.usb: xHCI Host Controller
10538 23:43:27.944970 <6>[ 1.142309] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10539 23:43:27.955054 <6>[ 1.142528] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10540 23:43:27.961546 <6>[ 1.142573] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10541 23:43:27.968566 <6>[ 1.142671] xhci-mtk 11200000.usb: xHCI Host Controller
10542 23:43:27.975103 <6>[ 1.142678] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10543 23:43:27.981456 <6>[ 1.142685] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10544 23:43:27.984604 <6>[ 1.143331] hub 1-0:1.0: USB hub found
10545 23:43:27.991230 <6>[ 1.143359] hub 1-0:1.0: 1 port detected
10546 23:43:27.997711 <6>[ 1.143589] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10547 23:43:28.001326 <6>[ 1.143862] hub 2-0:1.0: USB hub found
10548 23:43:28.004493 <6>[ 1.143882] hub 2-0:1.0: 1 port detected
10549 23:43:28.011145 <6>[ 1.146908] mtk-msdc 11f70000.mmc: Got CD GPIO
10550 23:43:28.014298 <6>[ 1.156367] mmc0: Command Queue Engine enabled
10551 23:43:28.021240 <6>[ 1.156387] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10552 23:43:28.028005 <6>[ 1.157044] mmcblk0: mmc0:0001 DA4128 116 GiB
10553 23:43:28.034953 <6>[ 1.160626] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10554 23:43:28.040962 <6>[ 1.161142] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10555 23:43:28.048011 <6>[ 1.161149] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10556 23:43:28.057745 <4>[ 1.161305] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10557 23:43:28.064693 <6>[ 1.161715] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10558 23:43:28.071052 <6>[ 1.161967] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10559 23:43:28.077527 <6>[ 1.161970] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10560 23:43:28.087787 <6>[ 1.162108] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10561 23:43:28.094508 <6>[ 1.162119] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10562 23:43:28.100834 <6>[ 1.162122] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10563 23:43:28.111005 <6>[ 1.162128] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10564 23:43:28.117266 <6>[ 1.162520] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10565 23:43:28.123893 <6>[ 1.163296] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10566 23:43:28.131158 <6>[ 1.163983] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10567 23:43:28.140804 <6>[ 1.164002] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10568 23:43:28.147656 <6>[ 1.164009] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10569 23:43:28.157063 <6>[ 1.164015] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10570 23:43:28.163761 <6>[ 1.164021] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10571 23:43:28.173570 <6>[ 1.164027] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10572 23:43:28.180242 <6>[ 1.164034] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10573 23:43:28.190177 <6>[ 1.164040] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10574 23:43:28.197682 <6>[ 1.164046] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10575 23:43:28.207074 <6>[ 1.164052] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10576 23:43:28.213980 <6>[ 1.164058] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10577 23:43:28.223276 <6>[ 1.164064] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10578 23:43:28.229799 <6>[ 1.164071] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10579 23:43:28.240075 <6>[ 1.164077] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10580 23:43:28.246642 <6>[ 1.164083] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10581 23:43:28.253342 <6>[ 1.164623] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10582 23:43:28.259859 <6>[ 1.165470] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10583 23:43:28.266415 <6>[ 1.166064] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10584 23:43:28.272922 <6>[ 1.166689] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10585 23:43:28.279666 <6>[ 1.167322] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10586 23:43:28.290014 <6>[ 1.167522] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10587 23:43:28.299244 <6>[ 1.167536] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10588 23:43:28.309269 <6>[ 1.167541] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10589 23:43:28.319869 <6>[ 1.167546] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10590 23:43:28.326302 <6>[ 1.167552] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10591 23:43:28.336316 <6>[ 1.167557] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10592 23:43:28.345765 <6>[ 1.167562] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10593 23:43:28.355962 <6>[ 1.167567] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10594 23:43:28.366358 <6>[ 1.167572] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10595 23:43:28.376123 <6>[ 1.167579] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10596 23:43:28.385563 <6>[ 1.167583] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10597 23:43:28.392002 <6>[ 1.168335] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10598 23:43:28.399235 <6>[ 1.182342] Trying to probe devices needed for running init ...
10599 23:43:28.405677 <6>[ 1.533989] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10600 23:43:28.408955 <6>[ 1.560711] hub 2-1:1.0: USB hub found
10601 23:43:28.415376 <6>[ 1.561066] hub 2-1:1.0: 3 ports detected
10602 23:43:28.419298 <6>[ 1.563827] hub 2-1:1.0: USB hub found
10603 23:43:28.422281 <6>[ 1.564178] hub 2-1:1.0: 3 ports detected
10604 23:43:28.428677 <6>[ 1.685792] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10605 23:43:28.442015 <6>[ 1.842688] hub 1-1:1.0: USB hub found
10606 23:43:28.445898 <6>[ 1.843072] hub 1-1:1.0: 4 ports detected
10607 23:43:28.449360 <6>[ 1.846800] hub 1-1:1.0: USB hub found
10608 23:43:28.452048 <6>[ 1.847157] hub 1-1:1.0: 4 ports detected
10609 23:43:28.525855 <6>[ 1.922122] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10610 23:43:28.761795 <6>[ 2.157962] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10611 23:43:28.886145 <6>[ 2.285791] hub 1-1.4:1.0: USB hub found
10612 23:43:28.889482 <6>[ 2.286247] hub 1-1.4:1.0: 2 ports detected
10613 23:43:28.893016 <6>[ 2.290610] hub 1-1.4:1.0: USB hub found
10614 23:43:28.899848 <6>[ 2.290968] hub 1-1.4:1.0: 2 ports detected
10615 23:43:29.181475 <6>[ 2.577936] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10616 23:43:29.365415 <6>[ 2.761950] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10617 23:43:40.069911 <6>[ 13.474925] ALSA device list:
10618 23:43:40.076049 <6>[ 13.474947] No soundcards found.
10619 23:43:40.080147 <6>[ 13.479402] Freeing unused kernel memory: 8448K
10620 23:43:40.082995 <6>[ 13.479540] Run /init as init process
10621 23:43:40.086246 Loading, please wait...
10622 23:43:40.106467 Starting version 247.3-7+deb11u2
10623 23:43:40.344070 <6>[ 13.743897] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10624 23:43:40.350830 <3>[ 13.753368] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 23:43:40.360565 <3>[ 13.753459] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 23:43:40.367804 <3>[ 13.753478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 23:43:40.377706 <3>[ 13.756285] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 23:43:40.383649 <3>[ 13.756318] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10629 23:43:40.394050 <3>[ 13.756324] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 23:43:40.400509 <3>[ 13.756336] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 23:43:40.410436 <3>[ 13.756345] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 23:43:40.417416 <3>[ 13.756409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10633 23:43:40.423725 <3>[ 13.756481] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10634 23:43:40.434001 <3>[ 13.756486] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10635 23:43:40.440250 <3>[ 13.756490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10636 23:43:40.449973 <3>[ 13.756662] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 23:43:40.456372 <3>[ 13.756666] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10638 23:43:40.466832 <3>[ 13.756670] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10639 23:43:40.473092 <3>[ 13.756674] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10640 23:43:40.480242 <3>[ 13.756677] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 23:43:40.490997 <3>[ 13.756689] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10642 23:43:40.493434 <6>[ 13.756791] remoteproc remoteproc0: scp is available
10643 23:43:40.500684 <6>[ 13.756965] remoteproc remoteproc0: powering up scp
10644 23:43:40.508465 <6>[ 13.756983] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10645 23:43:40.514774 <6>[ 13.757035] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10646 23:43:40.520904 <6>[ 13.829562] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10647 23:43:40.531461 <6>[ 13.829587] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10648 23:43:40.537948 <6>[ 13.829592] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10649 23:43:40.547290 <6>[ 13.844901] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10650 23:43:40.554118 <4>[ 13.859458] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10651 23:43:40.557542 <6>[ 13.860571] mc: Linux media interface: v0.10
10652 23:43:40.567693 <4>[ 13.867123] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10653 23:43:40.573966 <4>[ 13.867599] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10654 23:43:40.580711 <4>[ 13.867599] Fallback method does not support PEC.
10655 23:43:40.587226 <6>[ 13.882655] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10656 23:43:40.593723 <6>[ 13.883703] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10657 23:43:40.600496 <6>[ 13.883733] remoteproc remoteproc0: remote processor scp is now up
10658 23:43:40.607155 <6>[ 13.886731] usbcore: registered new interface driver r8152
10659 23:43:40.613692 <6>[ 13.886770] videodev: Linux video capture interface: v2.00
10660 23:43:40.620889 <3>[ 13.891719] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10661 23:43:40.630382 <6>[ 13.912613] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10662 23:43:40.637391 <6>[ 13.916897] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10663 23:43:40.646860 <3>[ 13.919161] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10664 23:43:40.653533 <6>[ 13.951054] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10665 23:43:40.659887 <6>[ 13.951064] pci_bus 0000:00: root bus resource [bus 00-ff]
10666 23:43:40.667180 <6>[ 13.951069] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10667 23:43:40.676627 <6>[ 13.951071] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10668 23:43:40.683238 <6>[ 13.951097] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10669 23:43:40.689967 <6>[ 13.951110] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10670 23:43:40.696913 <6>[ 13.951180] pci 0000:00:00.0: supports D1 D2
10671 23:43:40.703002 <6>[ 13.951183] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10672 23:43:40.709823 <6>[ 13.952200] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10673 23:43:40.716566 <6>[ 13.952273] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10674 23:43:40.722806 <6>[ 13.952297] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10675 23:43:40.732959 <6>[ 13.952313] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10676 23:43:40.739606 <6>[ 13.952328] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10677 23:43:40.742999 <6>[ 13.952429] pci 0000:01:00.0: supports D1 D2
10678 23:43:40.749212 <6>[ 13.952430] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10679 23:43:40.756165 <6>[ 13.965794] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10680 23:43:40.765913 <6>[ 13.965818] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10681 23:43:40.772831 <6>[ 13.965822] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10682 23:43:40.783076 <6>[ 13.965829] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10683 23:43:40.789323 <6>[ 13.965842] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10684 23:43:40.795897 <6>[ 13.965854] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10685 23:43:40.802270 <6>[ 13.965865] pci 0000:00:00.0: PCI bridge to [bus 01]
10686 23:43:40.809321 <6>[ 13.965870] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10687 23:43:40.815704 <6>[ 13.965974] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10688 23:43:40.822191 <6>[ 13.966462] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10689 23:43:40.832212 <6>[ 13.966566] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10690 23:43:40.838999 <6>[ 13.967108] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10691 23:43:40.848817 <6>[ 13.967184] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10692 23:43:40.855462 <6>[ 13.970027] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10693 23:43:40.865230 <6>[ 13.978287] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10694 23:43:40.871966 <4>[ 13.992797] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10695 23:43:40.882280 <4>[ 13.992811] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10696 23:43:40.888725 <5>[ 13.999094] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10697 23:43:40.894972 <6>[ 14.013277] usbcore: registered new interface driver cdc_ether
10698 23:43:40.901726 <6>[ 14.017754] usbcore: registered new interface driver r8153_ecm
10699 23:43:40.907907 <5>[ 14.018052] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10700 23:43:40.918216 <4>[ 14.018170] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10701 23:43:40.921834 <6>[ 14.018184] cfg80211: failed to load regulatory.db
10702 23:43:40.925091 <6>[ 14.023615] Bluetooth: Core ver 2.22
10703 23:43:40.931772 <6>[ 14.023708] NET: Registered PF_BLUETOOTH protocol family
10704 23:43:40.938283 <6>[ 14.023709] Bluetooth: HCI device and connection manager initialized
10705 23:43:40.944498 <6>[ 14.023785] Bluetooth: HCI socket layer initialized
10706 23:43:40.948773 <6>[ 14.023810] Bluetooth: L2CAP socket layer initialized
10707 23:43:40.954339 <6>[ 14.023839] Bluetooth: SCO socket layer initialized
10708 23:43:40.961471 <6>[ 14.049826] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10709 23:43:40.974824 <6>[ 14.051116] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10710 23:43:40.977978 <6>[ 14.051206] usbcore: registered new interface driver uvcvideo
10711 23:43:40.984742 <6>[ 14.064057] r8152 2-1.3:1.0 eth0: v1.12.13
10712 23:43:40.987891 <6>[ 14.070074] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10713 23:43:40.994580 <6>[ 14.087932] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10714 23:43:41.001668 <6>[ 14.088056] usbcore: registered new interface driver btusb
10715 23:43:41.011183 <4>[ 14.089092] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10716 23:43:41.018100 <3>[ 14.089104] Bluetooth: hci0: Failed to load firmware file (-2)
10717 23:43:41.024462 <3>[ 14.089109] Bluetooth: hci0: Failed to set up firmware (-2)
10718 23:43:41.034473 <4>[ 14.089114] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10719 23:43:41.041029 <6>[ 14.119682] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10720 23:43:41.047444 <6>[ 14.119774] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10721 23:43:41.054576 <6>[ 14.137823] mt7921e 0000:01:00.0: ASIC revision: 79610010
10722 23:43:41.064582 <4>[ 14.232862] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10723 23:43:41.077811 <4>[ 14.339407] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10724 23:43:41.087933 <4>[ 14.447394] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10725 23:43:41.090429 Begin: Loading essential drivers ... done.
10726 23:43:41.097206 Begin: Running /scripts/init-premount ... done.
10727 23:43:41.104476 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10728 23:43:41.110561 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10729 23:43:41.113616 Device /sys/class/net/enx00e04c787aaa found
10730 23:43:41.117812 done.
10731 23:43:41.155819 <4>[ 14.551898] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10732 23:43:41.168969 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10733 23:43:41.259250 <4>[ 14.655401] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10734 23:43:41.363064 <4>[ 14.758827] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10735 23:43:41.467824 <4>[ 14.862802] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10736 23:43:41.571563 <4>[ 14.966899] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10737 23:43:41.675545 <4>[ 15.070842] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 23:43:41.779470 <4>[ 15.174763] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10739 23:43:41.872708 <3>[ 15.276696] mt7921e 0000:01:00.0: hardware init failed
10740 23:43:42.288710 <6>[ 15.692304] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10741 23:43:43.120176 IP-Config: no response after 2 secs - giving up
10742 23:43:43.168288 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10743 23:43:43.171758 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10744 23:43:43.178333 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10745 23:43:43.184645 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10746 23:43:43.191358 host : mt8192-asurada-spherion-r0-cbg-0
10747 23:43:43.197942 domain : lava-rack
10748 23:43:43.201184 rootserver: 192.168.201.1 rootpath:
10749 23:43:43.204097 filename :
10750 23:43:43.291783 done.
10751 23:43:43.298276 Begin: Running /scripts/nfs-bottom ... done.
10752 23:43:43.320790 Begin: Running /scripts/init-bottom ... done.
10753 23:43:44.524271 <6>[ 17.925736] NET: Registered PF_INET6 protocol family
10754 23:43:44.527032 <6>[ 17.927607] Segment Routing with IPv6
10755 23:43:44.534228 <6>[ 17.927634] In-situ OAM (IOAM) with IPv6
10756 23:43:44.644382 <30>[ 18.029372] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10757 23:43:44.647869 <30>[ 18.030425] systemd[1]: Detected architecture arm64.
10758 23:43:44.648489
10759 23:43:44.653963 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10760 23:43:44.654482
10761 23:43:44.671989 <30>[ 18.076307] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10762 23:43:45.547376 <30>[ 18.946196] systemd[1]: Queued start job for default target Graphical Interface.
10763 23:43:45.579092 [[0;32m OK [<30>[ 18.980507] systemd[1]: Created slice system-getty.slice.
10764 23:43:45.582193 0m] Created slice [0;1;39msystem-getty.slice[0m.
10765 23:43:45.601627 [[0;32m OK [0m] Created slic<30>[ 19.003404] systemd[1]: Created slice system-modprobe.slice.
10766 23:43:45.604610 e [0;1;39msystem-modprobe.slice[0m.
10767 23:43:45.625066 [[0;32m OK [0m] Created slic<30>[ 19.027194] systemd[1]: Created slice system-serial\x2dgetty.slice.
10768 23:43:45.632151 e [0;1;39msystem-serial\x2dgetty.slice[0m.
10769 23:43:45.649928 [[0;32m OK [0m] Created slic<30>[ 19.051714] systemd[1]: Created slice User and Session Slice.
10770 23:43:45.653329 e [0;1;39mUser and Session Slice[0m.
10771 23:43:45.676143 [[0;32m OK [0m] Started [0;<30>[ 19.074759] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10772 23:43:45.679565 1;39mDispatch Password …ts to Console Directory Watch[0m.
10773 23:43:45.704225 [[0;32m OK [0m] Started [0;1;39mForward Pas<30>[ 19.102731] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10774 23:43:45.707115 sword R…uests to Wall Directory Watch[0m.
10775 23:43:45.735787 [[0;32m OK [0m] Reached targ<30>[ 19.130493] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10776 23:43:45.742413 <30>[ 19.130763] systemd[1]: Reached target Local Encrypted Volumes.
10777 23:43:45.745476 et [0;1;39mLocal Encrypted Volumes[0m.
10778 23:43:45.765087 [[0;32m OK [0m] Reached target [0;1;39mPath<30>[ 19.166488] systemd[1]: Reached target Paths.
10779 23:43:45.765704 s[0m.
10780 23:43:45.786913 [[0;32m OK [0m] Reached target [0;1;39mRemo<30>[ 19.185924] systemd[1]: Reached target Remote File Systems.
10781 23:43:45.787479 te File Systems[0m.
10782 23:43:45.807801 [[0;32m OK [0m] Reached target [0;1;39mSlic<30>[ 19.209909] systemd[1]: Reached target Slices.
10783 23:43:45.808369 es[0m.
10784 23:43:45.827883 [[0;32m OK [0m] Reached target [0;1;39mSwap<30>[ 19.229943] systemd[1]: Reached target Swap.
10785 23:43:45.828453 [0m.
10786 23:43:45.851793 [[0;32m OK [0m] Listening on [0;1;39minitct<30>[ 19.250443] systemd[1]: Listening on initctl Compatibility Named Pipe.
10787 23:43:45.854954 l Compatibility Named Pipe[0m.
10788 23:43:45.864790 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.266690] systemd[1]: Listening on Journal Audit Socket.
10789 23:43:45.868256 l Audit Socket[0m.
10790 23:43:45.889785 [[0;32m OK [0m] Listening on<30>[ 19.291318] systemd[1]: Listening on Journal Socket (/dev/log).
10791 23:43:45.892679 [0;1;39mJournal Socket (/dev/log)[0m.
10792 23:43:45.912868 [[0;32m OK [0m] Listening on [0;1;39mJourna<30>[ 19.314483] systemd[1]: Listening on Journal Socket.
10793 23:43:45.915776 l Socket[0m.
10794 23:43:45.933550 [[0;32m OK [0m] Listening on<30>[ 19.335633] systemd[1]: Listening on Network Service Netlink Socket.
10795 23:43:45.940336 [0;1;39mNetwork Service Netlink Socket[0m.
10796 23:43:45.960451 [[0;32m OK [0m] Listening on [0;1;39mudev C<30>[ 19.362372] systemd[1]: Listening on udev Control Socket.
10797 23:43:45.964062 ontrol Socket[0m.
10798 23:43:45.984413 [[0;32m OK [0m] Listening on [0;1;39mudev K<30>[ 19.386474] systemd[1]: Listening on udev Kernel Socket.
10799 23:43:45.987827 ernel Socket[0m.
10800 23:43:46.047122 Mounting [0;1;39mHuge Pages File Syste<30>[ 19.446001] systemd[1]: Mounting Huge Pages File System...
10801 23:43:46.047675 m[0m...
10802 23:43:46.071211 Mounting [0;1;39mPOSIX Message Queue F<30>[ 19.469707] systemd[1]: Mounting POSIX Message Queue File System...
10803 23:43:46.071716 ile System[0m...
10804 23:43:46.100595 Mounting [0;1;39mKerne<30>[ 19.502773] systemd[1]: Mounting Kernel Debug File System...
10805 23:43:46.104090 l Debug File System[0m...
10806 23:43:46.127543 <30>[ 19.526560] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10807 23:43:46.136999 <30>[ 19.532325] systemd[1]: Starting Create list of static device nodes for the current kernel...
10808 23:43:46.143712 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10809 23:43:46.209038 Starting [0;1;39mLoad <30>[ 19.610640] systemd[1]: Starting Load Kernel Module configfs...
10810 23:43:46.211594 Kernel Module configfs[0m...
10811 23:43:46.234384 Startin<30>[ 19.636691] systemd[1]: Starting Load Kernel Module drm...
10812 23:43:46.237986 g [0;1;39mLoad Kernel Module drm[0m...
10813 23:43:46.267770 Starting [0;1;39mLoad Kernel Module fu<30>[ 19.666680] systemd[1]: Starting Load Kernel Module fuse...
10814 23:43:46.268440 se[0m...
10815 23:43:46.307733 <30>[ 19.708048] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10816 23:43:46.314297 <6>[ 19.709012] fuse: init (API version 7.37)
10817 23:43:46.352571 Starting [0;1;39mJourn<30>[ 19.754699] systemd[1]: Starting Journal Service...
10818 23:43:46.353147 al Service[0m...
10819 23:43:46.386413 Startin<30>[ 19.788593] systemd[1]: Starting Load Kernel Modules...
10820 23:43:46.389716 g [0;1;39mLoad Kernel Modules[0m...
10821 23:43:46.413929 Startin<30>[ 19.815970] systemd[1]: Starting Remount Root and Kernel File Systems...
10822 23:43:46.420547 g [0;1;39mRemount Root and Kernel File Systems[0m...
10823 23:43:46.440724 Starting [0;1;39mColdp<30>[ 19.842888] systemd[1]: Starting Coldplug All udev Devices...
10824 23:43:46.443700 lug All udev Devices[0m...
10825 23:43:46.469987 [[0;32m OK [0m] Mounted [0;<30>[ 19.871409] systemd[1]: Mounted Huge Pages File System.
10826 23:43:46.473409 1;39mHuge Pages File System[0m.
10827 23:43:46.483582 <3>[ 19.883452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10828 23:43:46.494123 [[0;32m OK [0m] Mounted [0;<30>[ 19.895732] systemd[1]: Mounted POSIX Message Queue File System.
10829 23:43:46.497417 1;39mPOSIX Message Queue File System[0m.
10830 23:43:46.507325 <3>[ 19.906612] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10831 23:43:46.517506 [[0;32m OK [0m] Mounted [0;<30>[ 19.919454] systemd[1]: Mounted Kernel Debug File System.
10832 23:43:46.521059 1;39mKernel Debug File System[0m.
10833 23:43:46.544974 [[0;32m OK [0m] Finished [0<30>[ 19.943161] systemd[1]: Finished Create list of static device nodes for the current kernel.
10834 23:43:46.555040 ;1;39mCreate lis<3>[ 19.949528] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10835 23:43:46.558589 t of st… nodes for the current kernel[0m.
10836 23:43:46.571110 <3>[ 19.971406] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10837 23:43:46.582979 [[0;32m OK [<30>[ 19.983719] systemd[1]: modprobe@configfs.service: Succeeded.
10838 23:43:46.589545 0m] Finished [0<30>[ 19.984379] systemd[1]: Finished Load Kernel Module configfs.
10839 23:43:46.599641 ;1;39mLoad Kernel Module configf<3>[ 20.001324] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10840 23:43:46.600192 s[0m.
10841 23:43:46.619401 <3>[ 20.021533] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10842 23:43:46.626133 <30>[ 20.023844] systemd[1]: modprobe@drm.service: Succeeded.
10843 23:43:46.633926 [[0;32m OK [0m] Finished [0<30>[ 20.025167] systemd[1]: Finished Load Kernel Module drm.
10844 23:43:46.643776 ;1;39mLoad Kerne<3>[ 20.043812] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10845 23:43:46.646995 l Module drm[0m.
10846 23:43:46.667572 [[0;32m OK [<30>[ 20.068057] systemd[1]: modprobe@fuse.service: Succeeded.
10847 23:43:46.674354 0m] Finished [0<30>[ 20.068888] systemd[1]: Finished Load Kernel Module fuse.
10848 23:43:46.684812 ;1;39mLoad Kerne<3>[ 20.073906] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10849 23:43:46.685632 l Module fuse[0m.
10850 23:43:46.695142 <3>[ 20.096575] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10851 23:43:46.706851 [[0;32m OK [0m] Finished [0<30>[ 20.108178] systemd[1]: Finished Load Kernel Modules.
10852 23:43:46.716543 ;1;39mLoad Kerne<3>[ 20.116346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 23:43:46.717110 l Modules[0m.
10854 23:43:46.736990 [[0;32m OK [0m] Finished [0<30>[ 20.139221] systemd[1]: Finished Remount Root and Kernel File Systems.
10855 23:43:46.743860 ;1;39mRemount Root and Kernel File Systems[0m.
10856 23:43:46.760392 [[0;32m OK [0m] Started [0;1;39mJournal Ser<30>[ 20.162704] systemd[1]: Started Journal Service.
10857 23:43:46.763436 vice[0m.
10858 23:43:46.810804 Mounting [0;1;39mFUSE Control File System[0m...
10859 23:43:46.829797 Mounting [0;1;39mKernel Configuration File System[0m...
10860 23:43:46.853028 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10861 23:43:46.871932 Starting [0;1;39mLoad/Save Random Seed[0m...
10862 23:43:46.906559 Starting [0;1;39mApply Kernel Variable<46>[ 20.309082] systemd-journald[305]: Received client request to flush runtime journal.
10863 23:43:46.909913 s[0m...
10864 23:43:46.930728 Starting [0;1;39mCreate System Users[0m...
10865 23:43:46.951843 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10866 23:43:46.969406 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10867 23:43:46.986806 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10868 23:43:47.003274 <4>[ 20.396793] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10869 23:43:47.009673 <3>[ 20.396813] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10870 23:43:47.021671 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10871 23:43:47.037194 See 'systemctl status systemd-udev-trigger.service' for details.
10872 23:43:47.054362 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10873 23:43:48.311992 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10874 23:43:48.325697 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10875 23:43:48.385424 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10876 23:43:48.467857 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10877 23:43:48.481077 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10878 23:43:48.496265 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10879 23:43:48.536974 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10880 23:43:48.563448 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10881 23:43:48.745867 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10882 23:43:48.800951 Starting [0;1;39mNetwork Service[0m...
10883 23:43:48.843339 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10884 23:43:48.874502 Starting [0;1;39mNetwork Time Synchronization[0m...
10885 23:43:48.894258 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10886 23:43:48.958046 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10887 23:43:49.145734 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10888 23:43:49.196596 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10889 23:43:49.217184 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10890 23:43:49.452103 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10891 23:43:49.471103 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10892 23:43:49.508369 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10893 23:43:49.545945 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10894 23:43:49.560374 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10895 23:43:49.576667 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10896 23:43:49.592529 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10897 23:43:49.609008 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10898 23:43:49.627722 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10899 23:43:49.640150 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10900 23:43:49.656292 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10901 23:43:49.680946 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10902 23:43:49.702230 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10903 23:43:49.723272 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10904 23:43:49.743401 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10905 23:43:49.755841 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10906 23:43:49.789736 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10907 23:43:49.803667 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10908 23:43:49.819931 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10909 23:43:49.868858 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10910 23:43:49.948606 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10911 23:43:50.046386 Starting [0;1;39mUser Login Management[0m...
10912 23:43:50.125253 Starting [0;1;39mNetwork Name Resolution[0m...
10913 23:43:50.241199 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10914 23:43:50.288864 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10915 23:43:50.925949 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10916 23:43:50.948719 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10917 23:43:50.966138 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10918 23:43:51.027402 Starting [0;1;39mPermit User Sessions[0m...
10919 23:43:51.093808 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10920 23:43:51.151681 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10921 23:43:51.172140 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10922 23:43:51.191078 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10923 23:43:51.206206 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10924 23:43:51.221802 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10925 23:43:51.273522 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10926 23:43:51.321264 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10927 23:43:51.391424
10928 23:43:51.391736
10929 23:43:51.394731 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10930 23:43:51.395013
10931 23:43:51.397676 debian-bullseye-arm64 login: root (automatic login)
10932 23:43:51.398055
10933 23:43:51.398351
10934 23:43:51.745337 Linux debian-bullseye-arm64 6.1.64-cip10-rt5 #1 SMP PREEMPT Sun Dec 3 22:38:18 UTC 2023 aarch64
10935 23:43:51.746079
10936 23:43:51.752457 The programs included with the Debian GNU/Linux system are free software;
10937 23:43:51.759229 the exact distribution terms for each program are described in the
10938 23:43:51.762532 individual files in /usr/share/doc/*/copyright.
10939 23:43:51.762960
10940 23:43:51.768584 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10941 23:43:51.771930 permitted by applicable law.
10942 23:43:52.680771 Matched prompt #10: / #
10944 23:43:52.681062 Setting prompt string to ['/ #']
10945 23:43:52.681157 end: 2.2.5.1 login-action (duration 00:00:27) [common]
10947 23:43:52.681352 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
10948 23:43:52.681445 start: 2.2.6 expect-shell-connection (timeout 00:03:34) [common]
10949 23:43:52.681515 Setting prompt string to ['/ #']
10950 23:43:52.681581 Forcing a shell prompt, looking for ['/ #']
10952 23:43:52.732050 / #
10953 23:43:52.732404 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10954 23:43:52.732632 Waiting using forced prompt support (timeout 00:02:30)
10955 23:43:52.737989
10956 23:43:52.738614 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10957 23:43:52.738923 start: 2.2.7 export-device-env (timeout 00:03:34) [common]
10959 23:43:52.839879 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq'
10960 23:43:52.846918 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/12172464/extract-nfsrootfs-n4uis_qq'
10962 23:43:52.948715 / # export NFS_SERVER_IP='192.168.201.1'
10963 23:43:52.955915 export NFS_SERVER_IP='192.168.201.1'
10964 23:43:52.956869 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10965 23:43:52.957436 end: 2.2 depthcharge-retry (duration 00:01:26) [common]
10966 23:43:52.957988 end: 2 depthcharge-action (duration 00:01:26) [common]
10967 23:43:52.958492 start: 3 lava-test-retry (timeout 00:07:53) [common]
10968 23:43:52.958973 start: 3.1 lava-test-shell (timeout 00:07:53) [common]
10969 23:43:52.959412 Using namespace: common
10971 23:43:53.060744 / # #
10972 23:43:53.061464 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10973 23:43:53.067431 #
10974 23:43:53.068312 Using /lava-12172464
10976 23:43:53.169665 / # export SHELL=/bin/bash
10977 23:43:53.176108 export SHELL=/bin/bash
10979 23:43:53.278280 / # . /lava-12172464/environment
10980 23:43:53.284905 . /lava-12172464/environment
10982 23:43:53.393030 / # /lava-12172464/bin/lava-test-runner /lava-12172464/0
10983 23:43:53.393710 Test shell timeout: 10s (minimum of the action and connection timeout)
10984 23:43:53.399625 /lava-12172464/bin/lava-test-runner /lava-12172464/0
10985 23:43:53.679034 + export TESTRUN_ID=0_timesync-off
10986 23:43:53.682000 + TESTRUN_ID=0_timesync-off
10987 23:43:53.685922 + cd /lava-12172464/0/tests/0_timesync-off
10988 23:43:53.688598 ++ cat uuid
10989 23:43:53.692191 + UUID=12172464_1.6.2.3.1
10990 23:43:53.692314 + set +x
10991 23:43:53.695667 <LAVA_SIGNAL_STARTRUN 0_timesync-off 12172464_1.6.2.3.1>
10992 23:43:53.696022 Received signal: <STARTRUN> 0_timesync-off 12172464_1.6.2.3.1
10993 23:43:53.696199 Starting test lava.0_timesync-off (12172464_1.6.2.3.1)
10994 23:43:53.696395 Skipping test definition patterns.
10995 23:43:53.698309 + systemctl stop systemd-timesyncd
10996 23:43:53.743268 + set +x
10997 23:43:53.746235 <LAVA_SIGNAL_ENDRUN 0_timesync-off 12172464_1.6.2.3.1>
10998 23:43:53.747041 Received signal: <ENDRUN> 0_timesync-off 12172464_1.6.2.3.1
10999 23:43:53.747590 Ending use of test pattern.
11000 23:43:53.748059 Ending test lava.0_timesync-off (12172464_1.6.2.3.1), duration 0.05
11002 23:43:53.829462 + export TESTRUN_ID=1_kselftest-tpm2
11003 23:43:53.832836 + TESTRUN_ID=1_kselftest-tpm2
11004 23:43:53.839289 + cd /lava-12172464/0/tests/1_kselftest-tpm2
11005 23:43:53.839993 ++ cat uuid
11006 23:43:53.843062 + UUID=12172464_1.6.2.3.5
11007 23:43:53.843777 + set +x
11008 23:43:53.849954 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 12172464_1.6.2.3.5>
11009 23:43:53.850813 Received signal: <STARTRUN> 1_kselftest-tpm2 12172464_1.6.2.3.5
11010 23:43:53.851330 Starting test lava.1_kselftest-tpm2 (12172464_1.6.2.3.5)
11011 23:43:53.851898 Skipping test definition patterns.
11012 23:43:53.853028 + cd ./automated/linux/kselftest/
11013 23:43:53.879456 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip-gitlab -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11014 23:43:53.915207 INFO: install_deps skipped
11015 23:43:54.037162 --2023-12-03 23:41:39-- http://storage.kernelci.org/cip-gitlab/ci-pavel-linux-test/v6.1.64-cip10-rt5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11016 23:43:54.054973 Resolving storage.kernelci.org (storage.kernelci.org)... 20.171.243.82
11017 23:43:54.188692 Connecting to storage.kernelci.org (storage.kernelci.org)|20.171.243.82|:80... connected.
11018 23:43:54.321009 HTTP request sent, awaiting response... 200 OK
11019 23:43:54.324518 Length: 2966880 (2.8M) [application/octet-stream]
11020 23:43:54.327361 Saving to: 'kselftest.tar.xz'
11021 23:43:54.327831
11022 23:43:54.328207
11023 23:43:54.586865 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11024 23:43:54.852888 kselftest.tar.xz 1%[ ] 47.81K 178KB/s
11025 23:43:55.164613 kselftest.tar.xz 7%[> ] 213.25K 396KB/s
11026 23:43:55.389960 kselftest.tar.xz 25%[====> ] 736.46K 862KB/s
11027 23:43:55.576623 kselftest.tar.xz 63%[===========> ] 1.81M 1.67MB/s
11028 23:43:55.583295 kselftest.tar.xz 100%[===================>] 2.83M 2.22MB/s in 1.3s
11029 23:43:55.583413
11030 23:43:55.841243 2023-12-03 23:41:41 (2.22 MB/s) - 'kselftest.tar.xz' saved [2966880/2966880]
11031 23:43:55.841408
11032 23:44:01.435375 skiplist:
11033 23:44:01.438501 ========================================
11034 23:44:01.442103 ========================================
11035 23:44:01.482122 tpm2:test_smoke.sh
11036 23:44:01.485189 tpm2:test_space.sh
11037 23:44:01.499043 ============== Tests to run ===============
11038 23:44:01.499144 tpm2:test_smoke.sh
11039 23:44:01.502282 tpm2:test_space.sh
11040 23:44:01.505597 ===========End Tests to run ===============
11041 23:44:01.505689 shardfile-tpm2 pass
11042 23:44:01.607037 <12>[ 35.012962] kselftest: Running tests in tpm2
11043 23:44:01.610785 TAP version 13
11044 23:44:01.622540 1..2
11045 23:44:01.652839 # selftests: tpm2: test_smoke.sh
11046 23:44:03.150831 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11047 23:44:03.154100 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11048 23:44:03.161122 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11049 23:44:03.164711 # Traceback (most recent call last):
11050 23:44:03.174254 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11051 23:44:03.174806 # if self.tpm:
11052 23:44:03.181009 # AttributeError: 'Client' object has no attribute 'tpm'
11053 23:44:03.185061 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11054 23:44:03.191317 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11055 23:44:03.194425 # Traceback (most recent call last):
11056 23:44:03.204738 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11057 23:44:03.207789 # if self.tpm:
11058 23:44:03.211427 # AttributeError: 'Client' object has no attribute 'tpm'
11059 23:44:03.218133 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11060 23:44:03.221155 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11061 23:44:03.224640 # Traceback (most recent call last):
11062 23:44:03.234777 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11063 23:44:03.240158 # if self.tpm:
11064 23:44:03.241113 # AttributeError: 'Client' object has no attribute 'tpm'
11065 23:44:03.248054 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11066 23:44:03.254903 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11067 23:44:03.257997 # Traceback (most recent call last):
11068 23:44:03.267788 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11069 23:44:03.268264 # if self.tpm:
11070 23:44:03.274458 # AttributeError: 'Client' object has no attribute 'tpm'
11071 23:44:03.277798 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11072 23:44:03.284238 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11073 23:44:03.287599 # Traceback (most recent call last):
11074 23:44:03.297678 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11075 23:44:03.300882 # if self.tpm:
11076 23:44:03.304562 # AttributeError: 'Client' object has no attribute 'tpm'
11077 23:44:03.307617 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11078 23:44:03.314355 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11079 23:44:03.317688 # Traceback (most recent call last):
11080 23:44:03.328042 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11081 23:44:03.331341 # if self.tpm:
11082 23:44:03.334531 # AttributeError: 'Client' object has no attribute 'tpm'
11083 23:44:03.341298 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11084 23:44:03.348173 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11085 23:44:03.351386 # Traceback (most recent call last):
11086 23:44:03.360978 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11087 23:44:03.361533 # if self.tpm:
11088 23:44:03.367669 # AttributeError: 'Client' object has no attribute 'tpm'
11089 23:44:03.370662 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11090 23:44:03.377164 # Exception ignored in: <function Client.__del__ at 0xffff823a2d30>
11091 23:44:03.380684 # Traceback (most recent call last):
11092 23:44:03.390914 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11093 23:44:03.394306 # if self.tpm:
11094 23:44:03.397302 # AttributeError: 'Client' object has no attribute 'tpm'
11095 23:44:03.397846 #
11096 23:44:03.403972 # ======================================================================
11097 23:44:03.410620 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11098 23:44:03.417452 # ----------------------------------------------------------------------
11099 23:44:03.420968 # Traceback (most recent call last):
11100 23:44:03.431066 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11101 23:44:03.434240 # self.root_key = self.client.create_root_key()
11102 23:44:03.444263 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11103 23:44:03.450826 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11104 23:44:03.461059 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11105 23:44:03.464345 # raise ProtocolError(cc, rc)
11106 23:44:03.469139 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11107 23:44:03.469765 #
11108 23:44:03.475737 # ======================================================================
11109 23:44:03.482267 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11110 23:44:03.489341 # ----------------------------------------------------------------------
11111 23:44:03.492307 # Traceback (most recent call last):
11112 23:44:03.502471 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11113 23:44:03.503033 # self.client = tpm2.Client()
11114 23:44:03.513132 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11115 23:44:03.519639 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11116 23:44:03.522582 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11117 23:44:03.525857 #
11118 23:44:03.532700 # ======================================================================
11119 23:44:03.535635 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11120 23:44:03.542382 # ----------------------------------------------------------------------
11121 23:44:03.545946 # Traceback (most recent call last):
11122 23:44:03.555929 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11123 23:44:03.559072 # self.client = tpm2.Client()
11124 23:44:03.569065 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11125 23:44:03.572489 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11126 23:44:03.579241 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11127 23:44:03.579809 #
11128 23:44:03.585626 # ======================================================================
11129 23:44:03.588892 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11130 23:44:03.595678 # ----------------------------------------------------------------------
11131 23:44:03.598803 # Traceback (most recent call last):
11132 23:44:03.608930 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11133 23:44:03.612131 # self.client = tpm2.Client()
11134 23:44:03.622508 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11135 23:44:03.629121 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11136 23:44:03.632481 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11137 23:44:03.633007 #
11138 23:44:03.639094 # ======================================================================
11139 23:44:03.646067 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11140 23:44:03.652172 # ----------------------------------------------------------------------
11141 23:44:03.655542 # Traceback (most recent call last):
11142 23:44:03.665404 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11143 23:44:03.669145 # self.client = tpm2.Client()
11144 23:44:03.678820 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11145 23:44:03.682148 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11146 23:44:03.689317 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11147 23:44:03.689929 #
11148 23:44:03.695662 # ======================================================================
11149 23:44:03.698775 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11150 23:44:03.705885 # ----------------------------------------------------------------------
11151 23:44:03.708816 # Traceback (most recent call last):
11152 23:44:03.718947 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11153 23:44:03.721953 # self.client = tpm2.Client()
11154 23:44:03.732276 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11155 23:44:03.735478 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11156 23:44:03.742236 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11157 23:44:03.742728 #
11158 23:44:03.749148 # ======================================================================
11159 23:44:03.751936 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11160 23:44:03.758816 # ----------------------------------------------------------------------
11161 23:44:03.763079 # Traceback (most recent call last):
11162 23:44:03.774113 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11163 23:44:03.777296 # self.client = tpm2.Client()
11164 23:44:03.788219 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11165 23:44:03.793065 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11166 23:44:03.796632 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11167 23:44:03.797106 #
11168 23:44:03.807982 # ======================================================================
11169 23:44:03.808545 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11170 23:44:03.816179 # ----------------------------------------------------------------------
11171 23:44:03.816746 # Traceback (most recent call last):
11172 23:44:03.826296 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11173 23:44:03.829518 # self.client = tpm2.Client()
11174 23:44:03.839643 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11175 23:44:03.846283 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11176 23:44:03.850204 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11177 23:44:03.850768 #
11178 23:44:03.856231 # ======================================================================
11179 23:44:03.862980 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11180 23:44:03.869438 # ----------------------------------------------------------------------
11181 23:44:03.873351 # Traceback (most recent call last):
11182 23:44:03.883628 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11183 23:44:03.887176 # self.client = tpm2.Client()
11184 23:44:03.896269 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11185 23:44:03.899991 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11186 23:44:03.906721 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11187 23:44:03.907290 #
11188 23:44:03.913169 # ----------------------------------------------------------------------
11189 23:44:03.913777 # Ran 9 tests in 0.052s
11190 23:44:03.916075 #
11191 23:44:03.916631 # FAILED (errors=9)
11192 23:44:03.919474 # test_async (tpm2_tests.AsyncTest) ... ok
11193 23:44:03.926232 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11194 23:44:03.926824 #
11195 23:44:03.932744 # ----------------------------------------------------------------------
11196 23:44:03.936561 # Ran 2 tests in 0.038s
11197 23:44:03.937124 #
11198 23:44:03.937497 # OK
11199 23:44:03.939438 ok 1 selftests: tpm2: test_smoke.sh
11200 23:44:03.943279 # selftests: tpm2: test_space.sh
11201 23:44:03.946285 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11202 23:44:03.949567 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11203 23:44:03.956439 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11204 23:44:03.959599 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11205 23:44:03.960070 #
11206 23:44:03.966030 # ======================================================================
11207 23:44:03.973213 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11208 23:44:03.979509 # ----------------------------------------------------------------------
11209 23:44:03.983165 # Traceback (most recent call last):
11210 23:44:03.992897 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11211 23:44:03.996107 # root1 = space1.create_root_key()
11212 23:44:04.006321 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11213 23:44:04.013345 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11214 23:44:04.023072 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11215 23:44:04.026321 # raise ProtocolError(cc, rc)
11216 23:44:04.033234 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11217 23:44:04.033852 #
11218 23:44:04.039657 # ======================================================================
11219 23:44:04.042744 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11220 23:44:04.049408 # ----------------------------------------------------------------------
11221 23:44:04.053141 # Traceback (most recent call last):
11222 23:44:04.062683 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11223 23:44:04.066379 # space1.create_root_key()
11224 23:44:04.076291 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11225 23:44:04.082759 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11226 23:44:04.093264 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11227 23:44:04.096116 # raise ProtocolError(cc, rc)
11228 23:44:04.099717 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11229 23:44:04.102728 #
11230 23:44:04.106196 # ======================================================================
11231 23:44:04.112768 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11232 23:44:04.119458 # ----------------------------------------------------------------------
11233 23:44:04.122778 # Traceback (most recent call last):
11234 23:44:04.132948 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11235 23:44:04.135997 # root1 = space1.create_root_key()
11236 23:44:04.146431 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11237 23:44:04.152620 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11238 23:44:04.162299 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11239 23:44:04.166354 # raise ProtocolError(cc, rc)
11240 23:44:04.172796 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11241 23:44:04.173361 #
11242 23:44:04.179531 # ======================================================================
11243 23:44:04.182726 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11244 23:44:04.189091 # ----------------------------------------------------------------------
11245 23:44:04.192364 # Traceback (most recent call last):
11246 23:44:04.202175 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11247 23:44:04.205439 # root1 = space1.create_root_key()
11248 23:44:04.219065 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11249 23:44:04.222282 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11250 23:44:04.232078 # File "/lava-12172464/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11251 23:44:04.235518 # raise ProtocolError(cc, rc)
11252 23:44:04.242177 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11253 23:44:04.242602 #
11254 23:44:04.249178 # ----------------------------------------------------------------------
11255 23:44:04.252334 # Ran 4 tests in 0.071s
11256 23:44:04.252750 #
11257 23:44:04.253086 # FAILED (errors=4)
11258 23:44:04.258528 not ok 2 selftests: tpm2: test_space.sh # exit=1
11259 23:44:04.297924 tpm2_test_smoke_sh pass
11260 23:44:04.301113 tpm2_test_space_sh fail
11261 23:44:04.317049 + ../../utils/send-to-lava.sh ./output/result.txt
11262 23:44:04.402809 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=shardfile-tpm2 RESULT=pass>
11263 23:44:04.403685 Received signal: <TESTCASE> TEST_CASE_ID=shardfile-tpm2 RESULT=pass
11265 23:44:04.462470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11266 23:44:04.463157 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11268 23:44:04.522606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11269 23:44:04.523305 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11271 23:44:04.525864 + set +x
11272 23:44:04.529354 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 12172464_1.6.2.3.5>
11273 23:44:04.530203 Received signal: <ENDRUN> 1_kselftest-tpm2 12172464_1.6.2.3.5
11274 23:44:04.530582 Ending use of test pattern.
11275 23:44:04.530899 Ending test lava.1_kselftest-tpm2 (12172464_1.6.2.3.5), duration 10.68
11277 23:44:04.532315 <LAVA_TEST_RUNNER EXIT>
11278 23:44:04.533080 ok: lava_test_shell seems to have completed
11279 23:44:04.533685 shardfile-tpm2: pass
tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11280 23:44:04.534107 end: 3.1 lava-test-shell (duration 00:00:12) [common]
11281 23:44:04.534532 end: 3 lava-test-retry (duration 00:00:12) [common]
11282 23:44:04.534968 start: 4 finalize (timeout 00:07:41) [common]
11283 23:44:04.535410 start: 4.1 power-off (timeout 00:00:30) [common]
11284 23:44:04.536140 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11285 23:44:04.662031 >> Command sent successfully.
11286 23:44:04.674302 Returned 0 in 0 seconds
11287 23:44:04.775696 end: 4.1 power-off (duration 00:00:00) [common]
11289 23:44:04.777293 start: 4.2 read-feedback (timeout 00:07:41) [common]
11290 23:44:04.778708 Listened to connection for namespace 'common' for up to 1s
11291 23:44:05.779251 Finalising connection for namespace 'common'
11292 23:44:05.779906 Disconnecting from shell: Finalise
11293 23:44:05.780383 / #
11294 23:44:05.881439 end: 4.2 read-feedback (duration 00:00:01) [common]
11295 23:44:05.882200 end: 4 finalize (duration 00:00:01) [common]
11296 23:44:05.882808 Cleaning after the job
11297 23:44:05.883329 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/ramdisk
11298 23:44:05.896674 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/kernel
11299 23:44:05.931151 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/dtb
11300 23:44:05.931435 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/nfsrootfs
11301 23:44:06.025696 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12172464/tftp-deploy-kxi0e2kd/modules
11302 23:44:06.033100 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12172464
11303 23:44:06.662664 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12172464
11304 23:44:06.662852 Job finished correctly